From baldrick at free.fr Mon Sep 13 03:55:30 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 13 Sep 2010 10:55:30 +0200 Subject: [llvm-commits] [llvm] r113618 - in /llvm/trunk: bindings/ocaml/llvm/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/Target/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/VMCore/ In-Reply-To: <20100910205501.8F6CC2A6C12C@llvm.org> References: <20100910205501.8F6CC2A6C12C@llvm.org> Message-ID: <4C8DE702.3020709@free.fr> Hi Dale, > Add X86 MMX type to bitcode and Type. > (The Ada bindings probably need it too, but all the > obvious places to change say "do not edit this file".) the Ada binding is auto-generated, and should probably be regenerated. That said, I'm not sure anyone is using it - perhaps it should just be removed? That way, we will soon find out if anyone is using it :) Ciao, Duncan. From ggreif at gmail.com Mon Sep 13 05:06:27 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 13 Sep 2010 03:06:27 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <5292DDBE-195D-4E8E-8462-7650E7C3E649@apple.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> <5292DDBE-195D-4E8E-8462-7650E7C3E649@apple.com> Message-ID: <64a0fc92-110f-47eb-996a-50b494454f79@j2g2000vbo.googlegroups.com> On Sep 12, 2:22?am, Bill Wendling wrote: > On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote: > > > > > Bill, > > > you might be interested in my dabbling attempts > > withhttp://llvm.org/bugs/show_bug.cgi?id=8125 > > The x86 peephole already manages to eliminate > > the test after the 'and', It would be interesting > > to see whether ARM does too. > > Btw., my commit is not really restricted to 'and', > > any operation that sets the zero flag will do. > > > A.t.m. (before your changes) I got: > > LBB0_1: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ %tailrecurse > > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?@ =>This Inner Loop Header: > > Depth=1 > > ? ? ? ?ldr ? ? lr, [r2, #-4] > > ? ? ? ?and ? ? r4, lr, #3 > > ? ? ? ?tst ? ? lr, #3 > > ? ? ? ?beq ? ? LBB0_4 > > I saw your patch go through. As with your other code, I don't understand it fully. :) It's certainly an interesting optimization. But I think that we would still need the peephole optimizer for ARM (and PPC?). X86's instructions either always set the EFLAGS register or not. A lot of ARM instructions may set CSPR, but they don't have to. And it appears that that decision needs to wait until after instruction selection... > The transformation intends to implement this: %a = and %something, i32 3 ; a 2-bit mask switch %a [ case0 -> case1 -> case2 -> case3 -> ] to %a = and %something, i32 3 ; a 2-bit mask %iszero = cmpi %a, i32 0 br %iszero case0 rest rest: switch %a [ case1 -> case2 -> case3 -> ] Basically separating out the zero leg from the switch to a place where the peephole optimizer is more likely to find it. The ARM patch is an experiment to teach the ARM-peephole optimizer to take advantage of the hint that the zero-leg is hoisted out. This does not work yet because of a (suspected by me) bug, where the ARM::ANDri instruction seems to be dead. It definitely should not be dead. I am investigating the issue. But I would welcome help why that ANDri is appearing dead :-) Cheers, Gabor > -bw > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ggreif at gmail.com Mon Sep 13 05:27:21 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 13 Sep 2010 03:27:21 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> Message-ID: <31a29eba-d910-4783-b998-694ace37562d@g10g2000vbc.googlegroups.com> On Sep 12, 2:04?am, Bill Wendling wrote: > On Sep 11, 2010, at 5:43 AM, Gabor Greif wrote: > > > Bill, > > > I tried to extend your approach to TSTri (as an eliminable compare > > instr.) and > > ANDri (as an implicit compare) with this patch: > > That's what I'm attempting to do right now. :-) I want to do a bit more than just replace the TST with an AND that sets CPSR, though that's the first step. I'm introducing a separate callback instruction to handle TST (i.e., comparisons against a non-zero value). > > > gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ > > ARMBaseInstrInfo.cpp > > Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > > =================================================================== > > --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > > (revision 113683) > > +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > > (working copy) > > @@ -1372,6 +1372,10 @@ > > ? ? SrcReg = MI->getOperand(0).getReg(); > > ? ? CmpValue = MI->getOperand(1).getImm(); > > ? ? return true; > > + ?case ARM::TSTri: > > + ? ?SrcReg = MI->getOperand(0).getReg(); > > + ? ?CmpValue = 0; > > I think the TST instruction can take a compare value other than 0. The CMP instructions take 0, right? > I'd say the opposite. The cmp instruction takes an immediate and a register, the tst only takes a register and tests that against 0. > > > > @@ -1421,6 +1425,7 @@ > > ? switch (MI->getOpcode()) { > > ? default: break; > > ? case ARM::ADDri: > > + ?case ARM::ANDri: > > ? case ARM::SUBri: > > ? case ARM::t2ADDri: > > ? case ARM::t2SUBri: > > gabor at google8:~/llvm-build$ > > > BUT, it does not trigger on my example, because of > > something that appears to be a bug: > > > ? ? ? ?%reg16388 = PHI %reg16396, , %reg16392, ; GPR: > > %reg16388,16396,16392 > > ? ? ? ?%reg16389 = PHI %reg16385, , %reg16391, ; GPR: > > %reg16389,16385,16391 > > ? ? ? ?%reg16397 = LDR %reg16387, %reg0, 4100, pred:14, pred: > > %reg0; mem:LD4[%scevgep1] GPR:%reg16397,16387 > > ? ? ? ?%reg16390 = ANDri %reg16397, 3, pred:14, pred:%reg0, opt: > > %reg0; GPR:%reg16390,16397 > > ? ? ? ?TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR; GPR: > > %reg16397 > > ? ? ? ?Bcc , pred:0, pred:%CPSR > > > The TST seems to use the result of the LDR instead of that of the AND! > > Very fishy... > > If you want to use the result of AND instead of TST in the Bcc, you'll need to say that AND implicitly defines CSPR. In the above case, it looks like the AND is basically dead (at least in this code snippet). The TST performs an "and" of the 3 to the result of LDR, which is what the AND instruction does. The only difference here is that TST sets CPSR and the AND doesn't. I thought the point of your patch is to visit all "cmp r, #0" and "tst r" instructions and when they act on a register that is defined by an instruction that has a form to set CPSR, you switch to that form. This allows you to elide the "tst" rsp. "cmp". Did I get it right? I only know PPC (well-ish) where there are the operations that do not update flags, such as add r1, r2, r3 ; r1 = r2+r3, no flags touched and the recording variant add. r1, r2, r3 ; r1 = r2+r3, update CR0 The first pass could create the simple-minded variant without recording flags and with explicit compares, then the peephole would go over this, find the shortcut opportunities and change the opcode to the recording variant, eventually dropping the explicit compare. You would normally refrain from *always* using the recording variant, as there are 7-8 condition registers available (which can be scheduled too) and in many cases you do not want to clobber CR0 without a reason. Sorry for being dense and not recognizing that possibly you are implementing something more clever :-) Cheers, Gabor > > > The bitcode is ok: > > > ?%tmp2 = load i8** %scevgep1 > > ?%0 = ptrtoint i8* %tmp2 to i32 > > ?%and = and i32 %0, 3 > > ?%tst = icmp eq i32 %and, 0 > > ?br i1 %tst, label %sw.bb, label %tailrecurse.switch > > > What do you think? Okay to commit the above? > > Below is what I have in my tree right now. It's just the skeleton of how I'd like to handle this (it does nothing right now). I like it because of how it separates out different optimization potentialities for each type of instruction, but it may be overkill... > > -bw > > Index: include/llvm/Target/TargetInstrInfo.h > =================================================================== > --- include/llvm/Target/TargetInstrInfo.h ? ? ? (revision 113706) > +++ include/llvm/Target/TargetInstrInfo.h ? ? ? (working copy) > @@ -595,6 +595,15 @@ > ? ? ?return false; > ? ?} > > + ?/// OptimizeTestInstr - See if the test instruction can be converted into > + ?/// something more efficient. Update the iterator *only* if a transformation > + ?/// took place. > + ?virtual bool OptimizeTestInstr(MachineInstr * /*CmpInstr*/, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned /*SrcReg*/, int /*CmpValue*/, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock::iterator &MII) const { > + ? ?return false; > + ?} > + > ? ?/// getNumMicroOps - Return the number of u-operations the given machine > ? ?/// instruction will be decoded to on the target cpu. > ? ?virtual unsigned getNumMicroOps(const MachineInstr *MI, > Index: lib/Target/ARM/ARMBaseInstrInfo.cpp > =================================================================== > --- lib/Target/ARM/ARMBaseInstrInfo.cpp (revision 113706) > +++ lib/Target/ARM/ARMBaseInstrInfo.cpp (working copy) > @@ -1377,6 +1377,18 @@ > ? ?return false; > ?} > > +/// OptimizeTestInstr - See if we can convert the TEST instruction into an > +/// equivalent AND instruction, possibly saving an instruction or two if we can > +/// make AND set the flags register. > +bool ARMBaseInstrInfo:: > +OptimizeTestInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, > + ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock::iterator &MII) const { > + ?if (CmpValue == 0) > + ? ?return false; > + > + ?return false; > +} > + > ?/// OptimizeCompareInstr - Convert the instruction supplying the argument to the > ?/// comparison into one that sets the zero bit in the flags register. Update the > ?/// iterator *only* if a transformation took place. > Index: lib/Target/ARM/ARMBaseInstrInfo.h > =================================================================== > --- lib/Target/ARM/ARMBaseInstrInfo.h ? (revision 113706) > +++ lib/Target/ARM/ARMBaseInstrInfo.h ? (working copy) > @@ -350,6 +350,13 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int CmpValue, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock::iterator &MII) const; > > + ?/// OptimizeTestInstr - See if we can convert the TEST instruction into an > + ?/// equivalent AND instruction, possibly saving an instruction or two if we > + ?/// can make AND set the flags register. > + ?virtual bool OptimizeTestInstr(MachineInstr *CmpInstr, unsigned SrcReg, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int CmpValue, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock::iterator &MII) const; > + > ? ?virtual unsigned getNumMicroOps(const MachineInstr *MI, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const InstrItineraryData *ItinData) const; > ?}; > Index: lib/CodeGen/PeepholeOptimizer.cpp > =================================================================== > --- lib/CodeGen/PeepholeOptimizer.cpp ? (revision 113706) > +++ lib/CodeGen/PeepholeOptimizer.cpp ? (working copy) > @@ -249,6 +249,12 @@ > ? ? ?return true; > ? ?} > > + ?// Attempt to optimize the test instruction. > + ?if (TII->OptimizeTestInstr(MI, SrcReg, CmpValue, NextIter)) { > + ? ?++NumEliminated; > + ? ?return true; > + ?} > + > ? ?return false; > ?} > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Sep 13 07:59:28 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 13 Sep 2010 12:59:28 -0000 Subject: [llvm-commits] [dragonegg] r113745 - /dragonegg/trunk/TODO Message-ID: <20100913125928.A3F202A6C12C@llvm.org> Author: baldrick Date: Mon Sep 13 07:59:28 2010 New Revision: 113745 URL: http://llvm.org/viewvc/llvm-project?rev=113745&view=rev Log: Update the dragonegg TODO list. Modified: dragonegg/trunk/TODO Modified: dragonegg/trunk/TODO URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/TODO?rev=113745&r1=113744&r2=113745&view=diff ============================================================================== --- dragonegg/trunk/TODO (original) +++ dragonegg/trunk/TODO Mon Sep 13 07:59:28 2010 @@ -29,13 +29,6 @@ GCC now has per-function optimization levels. Add support for this. -Fortran is currently broken because it has a boolean type with a precision -of 1 bit but size not equal to 8 bits. We convert to i1 which has the wrong -AllocSize. Fix this by distinguishing between the "memory type" used for -passing the value around in memory (which would be i32 for this Fortran type), -and the "register type" used for passing about in register (i1 in this case). -This should tie in nicely with gimple registers versus references. - Unify the code that determines which LLVM linkage type to use. Need to do a bunch of experimenting to work out how the mapping should really be done. @@ -60,7 +53,8 @@ Features -------- -Output proper debug info rather than throwing most of it away. +Output proper debug info rather than throwing most of it away. Provide column +numbers in location info. Many x86 specific builtins are not supported, even though it would be easy to add support for some of them, for example the 256 bit versions of builtins we @@ -78,3 +72,5 @@ using -c, which runs into trouble because gcc insists on running the assembler on compiler output. Another part is looking into the possibility of encoding bitcode in ELF sections like gcc does for gimple when doing LTO. + +Add support for address spaces. From baldrick at free.fr Mon Sep 13 08:32:22 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 13 Sep 2010 13:32:22 -0000 Subject: [llvm-commits] [llvm] r113746 - /llvm/trunk/test/lit.cfg Message-ID: <20100913133222.9BA3E2A6C12C@llvm.org> Author: baldrick Date: Mon Sep 13 08:32:22 2010 New Revision: 113746 URL: http://llvm.org/viewvc/llvm-project?rev=113746&view=rev Log: Spelling fixes in comments. Modified: llvm/trunk/test/lit.cfg Modified: llvm/trunk/test/lit.cfg URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=113746&r1=113745&r2=113746&view=diff ============================================================================== --- llvm/trunk/test/lit.cfg (original) +++ llvm/trunk/test/lit.cfg Mon Sep 13 08:32:22 2010 @@ -45,22 +45,22 @@ config.environment['PATH'])) config.environment['PATH'] = path -# Propogate 'HOME' through the environment. +# Propagate 'HOME' through the environment. if 'HOME' in os.environ: config.environment['HOME'] = os.environ['HOME'] -# Propogate 'INCLUDE' through the environment. +# Propagate 'INCLUDE' through the environment. if 'INCLUDE' in os.environ: config.environment['INCLUDE'] = os.environ['INCLUDE'] -# Propogate 'LIB' through the environment. +# Propagate 'LIB' through the environment. if 'LIB' in os.environ: config.environment['LIB'] = os.environ['LIB'] -# Propogate LLVM_SRC_ROOT into the environment. +# Propagate LLVM_SRC_ROOT into the environment. config.environment['LLVM_SRC_ROOT'] = getattr(config, 'llvm_src_root', '') -# Propogate PYTHON_EXEUTABLE into the environment +# Propagate PYTHON_EXECUTABLE into the environment config.environment['PYTHON_EXECUTABLE'] = getattr(config, 'python_executable', '') From baldrick at free.fr Mon Sep 13 08:45:34 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 13 Sep 2010 13:45:34 -0000 Subject: [llvm-commits] [llvm] r113747 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100913134534.0B33B2A6C12C@llvm.org> Author: baldrick Date: Mon Sep 13 08:45:33 2010 New Revision: 113747 URL: http://llvm.org/viewvc/llvm-project?rev=113747&view=rev Log: Nowadays a release build has assertions off. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113747&r1=113746&r2=113747&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Mon Sep 13 08:45:33 2010 @@ -175,11 +175,11 @@ case $Flavor in Release | Release-64 ) Optimized="yes" - Assertions="yes" + Assertions="no" ;; - Release-Asserts ) + Release+Asserts ) Optimized="yes" - Assertions="no" + Assertions="yes" ;; Debug ) Optimized="no" From geek4civic at gmail.com Mon Sep 13 09:19:54 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 13 Sep 2010 23:19:54 +0900 Subject: [llvm-commits] [PATCH][EXPERIMENTAL] Building LLVMgold.dll Message-ID: Good evening, guys! This patch enables building LTO.dll, libLTO.a and LLVMgold.dll on cygming. I know it is still incomplete, and I would say it is "experimental". Known issue: - dependency between libs would be incomplete. - I don't know how to test functionality. ...Takumi -------------- next part -------------- diff --git a/tools/Makefile b/tools/Makefile index aa07a2b..fb70f22 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -35,12 +35,11 @@ include $(LEVEL)/Makefile.config # These libraries build as dynamic libraries (.dylib /.so), they can only be # built if ENABLE_PIC is set. ifeq ($(ENABLE_PIC),1) - # No support for dynamic libraries on windows targets. - ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW)) # gold only builds if binutils is around. It requires "lto" to build before # it so it is added to DIRS. ifdef BINUTILS_INCDIR - DIRS += lto gold + DIRS += lto + PARALLEL_DIRS += gold else PARALLEL_DIRS += lto endif @@ -54,6 +53,13 @@ ifeq ($(ENABLE_PIC),1) PARALLEL_DIRS += edis endif endif +endif + +# No support for dynamic libraries on windows targets. +ifneq (,$(filter $(TARGET_OS), Cygwin MingW)) + ifneq ($(ENABLE_SHARED),1) + PARALLEL_DIRS := $(filter-out bugpoint-passes edis, \ + $(PARALLEL_DIRS)) endif endif diff --git a/tools/gold/Makefile b/tools/gold/Makefile index 82a4e39..9eb02c1 100644 --- a/tools/gold/Makefile +++ b/tools/gold/Makefile @@ -22,10 +22,28 @@ SHARED_LIBRARY = 1 LOADABLE_MODULE = 1 LINK_COMPONENTS := support system -LIBS += -llto + +ifneq (,$(filter $(HOST_OS), Cygwin MingW)) + ifneq ($(ENABLE_SHARED),1) + LINK_COMPONENTS += $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter + endif +endif # Because off_t is used in the public API, the largefile parts are required for # ABI compatibility. -CXXFLAGS+=-I$(BINUTILS_INCDIR) -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -lLTO +CXXFLAGS+=-I$(BINUTILS_INCDIR) -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 include $(LEVEL)/Makefile.common + +ifneq (,$(filter $(HOST_OS), Cygwin MingW)) + ifeq ($(ENABLE_SHARED),1) + LLVMLibsOptions := -L$(SharedLibDir) -lLTO $(LLVMLibsOptions) + LLVMLibsPaths += $(SharedLibDir)/$(SharedPrefix)LTO$(SHLIBEXT) + else + LLVMLibsOptions := -lLTO $(LLVMLibsOptions) + LLVMLibsPaths += $(LibDir)/libLTO.a + endif +else + LLVMLibsOptions := -L$(SharedLibDir) -lLTO $(LLVMLibsOptions) + LLVMLibsPaths += $(SharedLibDir)/$(SharedPrefix)LTO$(SHLIBEXT) +endif diff --git a/tools/gold/gold-plugin.cpp b/tools/gold/gold-plugin.cpp index 4b58fae..1f40768 100644 --- a/tools/gold/gold-plugin.cpp +++ b/tools/gold/gold-plugin.cpp @@ -29,6 +29,10 @@ #include #include +#ifdef __MINGW32__ +#include +#endif + using namespace llvm; namespace { From ggreif at gmail.com Mon Sep 13 10:06:29 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 13 Sep 2010 08:06:29 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <64a0fc92-110f-47eb-996a-50b494454f79@j2g2000vbo.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> <5292DDBE-195D-4E8E-8462-7650E7C3E649@apple.com> <64a0fc92-110f-47eb-996a-50b494454f79@j2g2000vbo.googlegroups.com> Message-ID: <928e1ec7-f08a-44ab-9379-11557918f50c@f26g2000vbm.googlegroups.com> On Sep 13, 12:06?pm, Gabor Greif wrote: > On Sep 12, 2:22?am, Bill Wendling wrote: > > > > > On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote: > > > > Bill, > [snippery] > > Basically separating out the zero leg from the switch to a place where > the peephole optimizer is more likely to find it. The ARM patch is an > experiment to teach the ARM-peephole optimizer to take advantage of > the hint that the zero-leg is hoisted out. This does not work yet > because of a (suspected by me) bug, where the ARM::ANDri instruction > seems to be dead. It definitely should not be dead. I am investigating > the issue. But I would welcome help why that ANDri is appearing > dead :-) Sorry for following myself up! Mystery solved, here the MC output: ldr r12, [r2, #-4] and lr, r12, #3 tst r12, #3 beq LBB0_4 @ BB#2: @ %tailrecurse.switch @ in Loop: Header=BB0_1 Depth=1 cmp lr, #3 moveq r0, r2 ldmiaeq sp!, {r7, pc} cmp lr, #2 beq LBB0_5 @ BB#3: @ %tailrecurse.switch The "tst r12, #3" can be replaced here with "cmp lr, #0", because it is a mask operation testing against 0. We get this: ldr r12, [r2, #-4] and lr, r12, #3 cmp lr, #0 beq LBB0_4 @ BB#2: @ %tailrecurse.switch Now the peephole can apply: ldr r12, [r2, #-4] andS lr, r12, #3 beq LBB0_4 effectively choosing the recording variant of AND and eliding the CMP (formerly known as TST). Now I can go over your patch and see whether you already implement this peephole transformation. If not, I'll try to improve on it. Cheers, and sorry for the confusion, Gabor > > Cheers, > > ? ?Gabor > > > -bw > From resistor at mac.com Mon Sep 13 11:28:26 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 13 Sep 2010 16:28:26 -0000 Subject: [llvm-commits] [test-suite] r113752 - in /test-suite/trunk/MultiSource/Applications: Makefile OpenSSL/ Message-ID: <20100913162826.E10492A6C12C@llvm.org> Author: resistor Date: Mon Sep 13 11:28:26 2010 New Revision: 113752 URL: http://llvm.org/viewvc/llvm-project?rev=113752&view=rev Log: Remove OpenSSL from the testsuite, due to questions of export control issues. Removed: test-suite/trunk/MultiSource/Applications/OpenSSL/ Modified: test-suite/trunk/MultiSource/Applications/Makefile Modified: test-suite/trunk/MultiSource/Applications/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/Makefile?rev=113752&r1=113751&r2=113752&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Applications/Makefile (original) +++ test-suite/trunk/MultiSource/Applications/Makefile Mon Sep 13 11:28:26 2010 @@ -5,7 +5,7 @@ include $(LEVEL)/Makefile.config PARALLEL_DIRS = Burg aha sgefa siod d spiff treecc SPASS \ - oggenc JM viterbi SIBsim4 ClamAV sqlite3 lemon OpenSSL + oggenc JM viterbi SIBsim4 ClamAV sqlite3 lemon ifndef DISABLE_CXX PARALLEL_DIRS += lambda-0.1.3 hbd hexxagon minisat endif From dalej at apple.com Mon Sep 13 12:20:17 2010 From: dalej at apple.com (Dale Johannesen) Date: Mon, 13 Sep 2010 10:20:17 -0700 Subject: [llvm-commits] [llvm] r113618 - in /llvm/trunk: bindings/ocaml/llvm/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/Target/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/VMCore/ In-Reply-To: <4C8DE702.3020709@free.fr> References: <20100910205501.8F6CC2A6C12C@llvm.org> <4C8DE702.3020709@free.fr> Message-ID: On Sep 13, 2010, at 1:55 AM, Duncan Sands wrote: > Hi Dale, > >> Add X86 MMX type to bitcode and Type. >> (The Ada bindings probably need it too, but all the >> obvious places to change say "do not edit this file".) > > the Ada binding is auto-generated, and should probably be regenerated. > That said, I'm not sure anyone is using it - perhaps it should just be > removed? That way, we will soon find out if anyone is using it :) Fine with me, but I wouldn't know how. AFAIK you are the only person doing anything with Ada... From bob.wilson at apple.com Mon Sep 13 12:37:56 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 13 Sep 2010 17:37:56 -0000 Subject: [llvm-commits] [llvm] r113757 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20100913173756.2341F2A6C12C@llvm.org> Author: bwilson Date: Mon Sep 13 12:37:55 2010 New Revision: 113757 URL: http://llvm.org/viewvc/llvm-project?rev=113757&view=rev Log: Document NEON intrinsic changes for 2.8. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=113757&r1=113756&r2=113757&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Sep 13 12:37:55 2010 @@ -446,11 +446,50 @@
    -
  • - -
- - +
  • + All of the NEON load and store intrinsics (llvm.arm.neon.vld* and + llvm.arm.neon.vst*) take an extra parameter to specify the alignment in bytes + of the memory being accessed. +
    • +
  • + The llvm.arm.neon.vaba intrinsic (vector absolute difference and + accumulate) has been removed. This operation is now represented using + the llvm.arm.neon.vabd intrinsic (vector absolute difference) followed by a + vector add. + +
  • + The llvm.arm.neon.vabdl and llvm.arm.neon.vabal intrinsics (lengthening + vector absolute difference with and without accumlation) have been removed. + They are represented using the llvm.arm.neon.vabd intrinsic (vector absolute + difference) followed by a vector zero-extend operation, and for vabal, + a vector add. +
    • +
  • + The llvm.arm.neon.vmovn intrinsic has been removed. Calls of this intrinsic + are now replaced by vector truncate operations. +
    • +
  • + The llvm.arm.neon.vmovls and llvm.arm.neon.vmovlu intrinsics have been + removed. They are now represented as vector sign-extend (vmovls) and + zero-extend (vmovlu) operations. +
    • +
  • + The llvm.arm.neon.vaddl*, llvm.arm.neon.vaddw*, llvm.arm.neon.vsubl*, and + llvm.arm.neon.vsubw* intrinsics (lengthening vector add and subtract) have + been removed. They are replaced by vector add and vector subtract operations + where one (vaddw, vsubw) or both (vaddl, vsubl) of the operands are either + sign-extended or zero-extended. +
    • +
  • + The llvm.arm.neon.vmulls, llvm.arm.neon.vmullu, llvm.arm.neon.vmlal*, and + llvm.arm.neon.vmlsl* intrinsics (lengthening vector multiply with and without + accumulation and subtraction) have been removed. These operations are now + represented as vector multiplications where the operands are either + sign-extended or zero-extended, followed by a vector add for vmlal or a + vector subtract for vmlsl. Note that the polynomial vector multiply + intrinsic, llvm.arm.neon.vmullp, remains unchanged. +
    • + From bob.wilson at apple.com Mon Sep 13 12:39:35 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 13 Sep 2010 17:39:35 -0000 Subject: [llvm-commits] [llvm] r113758 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20100913173936.066452A6C12C@llvm.org> Author: bwilson Date: Mon Sep 13 12:39:35 2010 New Revision: 113758 URL: http://llvm.org/viewvc/llvm-project?rev=113758&view=rev Log: Fix formatting tags. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=113758&r1=113757&r2=113758&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Sep 13 12:39:35 2010 @@ -456,7 +456,7 @@ accumulate) has been removed. This operation is now represented using the llvm.arm.neon.vabd intrinsic (vector absolute difference) followed by a vector add. - +
  • The llvm.arm.neon.vabdl and llvm.arm.neon.vabal intrinsics (lengthening vector absolute difference with and without accumlation) have been removed. @@ -489,7 +489,8 @@ vector subtract for vmlsl. Note that the polynomial vector multiply intrinsic, llvm.arm.neon.vmullp, remains unchanged.
    • - + + From rafael.espindola at gmail.com Mon Sep 13 12:39:45 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 13 Sep 2010 17:39:45 -0000 Subject: [llvm-commits] [llvm] r113759 - /llvm/trunk/lib/MC/MCELFStreamer.cpp Message-ID: <20100913173945.640412A6C12C@llvm.org> Author: rafael Date: Mon Sep 13 12:39:45 2010 New Revision: 113759 URL: http://llvm.org/viewvc/llvm-project?rev=113759&view=rev Log: Factoring and potential bug fix. The elf "flags" cannot be used as masks. For example, setting STT_OBJECT (1) and STT_FUNC (2), should not produce a STT_SECTION (3). Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=113759&r1=113758&r2=113759&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Sep 13 12:39:45 2010 @@ -147,6 +147,31 @@ Symbol->setVariableValue(AddValueSymbols(Value)); } +static void SetBinding(MCSymbolData &SD, unsigned Binding) { + assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL || + Binding == ELF::STB_WEAK); + uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STB_Shift); + SD.setFlags(OtherFlags | (Binding << ELF_STB_Shift)); +} + +static void SetType(MCSymbolData &SD, unsigned Type) { + assert(Type == ELF::STT_NOTYPE || Type == ELF::STT_OBJECT || + Type == ELF::STT_FUNC || Type == ELF::STT_SECTION || + Type == ELF::STT_FILE || Type == ELF::STT_COMMON || + Type == ELF::STT_TLS); + + uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STT_Shift); + SD.setFlags(OtherFlags | (Type << ELF_STT_Shift)); +} + +static void SetVisibility(MCSymbolData &SD, unsigned Visibility) { + assert(Visibility == ELF::STV_DEFAULT || Visibility == ELF::STV_INTERNAL || + Visibility == ELF::STV_HIDDEN || Visibility == ELF::STV_PROTECTED); + + uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STV_Shift); + SD.setFlags(OtherFlags | (Visibility << ELF_STV_Shift)); +} + void MCELFStreamer::EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) { // Indirect symbols are handled differently, to match how 'as' handles @@ -186,51 +211,49 @@ break; case MCSA_Global: - SD.setFlags(SD.getFlags() | ELF_STB_Global); + SetBinding(SD, ELF::STB_GLOBAL); SD.setExternal(true); break; case MCSA_WeakReference: case MCSA_Weak: - SD.setFlags(SD.getFlags() | ELF_STB_Weak); + SetBinding(SD, ELF::STB_WEAK); break; case MCSA_Local: - // ELF_STB_Local is 0, so zero the ELF_STB area - // SD.getFlags() | ELF_STB_Local is a NOP - SD.setFlags(SD.getFlags() & ~(0xf << ELF_STB_Shift)); + SetBinding(SD, ELF::STB_LOCAL); break; case MCSA_ELF_TypeFunction: - SD.setFlags(SD.getFlags() | ELF_STT_Func); + SetType(SD, ELF::STT_FUNC); break; case MCSA_ELF_TypeObject: - SD.setFlags(SD.getFlags() | ELF_STT_Object); + SetType(SD, ELF::STT_OBJECT); break; case MCSA_ELF_TypeTLS: - SD.setFlags(SD.getFlags() | ELF_STT_Tls); + SetType(SD, ELF::STT_TLS); break; case MCSA_ELF_TypeCommon: - SD.setFlags(SD.getFlags() | ELF_STT_Common); + SetType(SD, ELF::STT_COMMON); break; case MCSA_ELF_TypeNoType: - SD.setFlags(SD.getFlags() | ELF_STT_Notype); + SetType(SD, ELF::STT_NOTYPE); break; case MCSA_Protected: - SD.setFlags(SD.getFlags() | ELF_STV_Protected); + SetVisibility(SD, ELF::STV_PROTECTED); break; case MCSA_Hidden: - SD.setFlags(SD.getFlags() | ELF_STV_Hidden); + SetVisibility(SD, ELF::STV_HIDDEN); break; case MCSA_Internal: - SD.setFlags(SD.getFlags() | ELF_STV_Internal); + SetVisibility(SD, ELF::STV_INTERNAL); break; } } @@ -253,7 +276,7 @@ SD.setSize(MCConstantExpr::Create(Size, getContext())); } - SD.setFlags(SD.getFlags() | ELF_STB_Global); + SetBinding(SD, ELF::STB_GLOBAL); SD.setExternal(true); SD.setCommon(Size, ByteAlignment); From ggreif at gmail.com Mon Sep 13 12:49:10 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 13 Sep 2010 10:49:10 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <928e1ec7-f08a-44ab-9379-11557918f50c@f26g2000vbm.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> <5292DDBE-195D-4E8E-8462-7650E7C3E649@apple.com> <64a0fc92-110f-47eb-996a-50b494454f79@j2g2000vbo.googlegroups.com> <928e1ec7-f08a-44ab-9379-11557918f50c@f26g2000vbm.googlegroups.com> Message-ID: <21271931-8133-4998-8d71-a0705c3822db@g10g2000vbc.googlegroups.com> Okay, here is a patch that successfully eliminates the "tst" and turns "and" into "andS": gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ ARMBaseInstrInfo.cpp Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (revision 113747) +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (working copy) @@ -1372,6 +1372,19 @@ SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; + case ARM::TSTri: { + if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI)) + return false; + const MachineInstr *AND = llvm::prior(MI); + if (AND->getOpcode() != ARM::ANDri) + return false; + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && // FIXME: or == AND + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {// FIXME: subset + SrcReg = AND->getOperand(0).getReg(); + CmpValue = 0; + return true; + } + } } return false; @@ -1421,6 +1434,7 @@ switch (MI->getOpcode()) { default: break; case ARM::ADDri: + case ARM::ANDri: case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: Here we go: LBB0_1: @ %tailrecurse @ =>This Inner Loop Header: Depth=1 ldr r12, [r2, #-4] ands r12, r12, #3 beq LBB0_4 @ BB#2: @ %tailrecurse.switch @ in Loop: Header=BB0_1 Depth=1 cmp r12, #3 moveq r0, r2 bxeq lr What do you think? The two fixmes would allow more cases to be caught. Now my itch is somewhat reduced, turning my attention to your patch. Cheers, Gabor On 13 Sep., 17:06, Gabor Greif wrote: > On Sep 13, 12:06?pm, Gabor Greif wrote:> On Sep 12, 2:22?am, Bill Wendling wrote: > > > > On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote: > > > > > Bill, > > [snippery] > > > > > Basically separating out the zero leg from the switch to a place where > > the peephole optimizer is more likely to find it. The ARM patch is an > > experiment to teach the ARM-peephole optimizer to take advantage of > > the hint that the zero-leg is hoisted out. This does not work yet > > because of a (suspected by me) bug, where the ARM::ANDri instruction > > seems to be dead. It definitely should not be dead. I am investigating > > the issue. But I would welcome help why that ANDri is appearing > > dead :-) > > Sorry for following myself up! > > Mystery solved, here the MC output: > > ? ? ? ? ldr ? ? r12, [r2, #-4] > ? ? ? ? and ? ? lr, r12, #3 > ? ? ? ? tst ? ? r12, #3 > ? ? ? ? beq ? ? LBB0_4 > @ BB#2: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ %tailrecurse.switch > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ ? in Loop: Header=BB0_1 > Depth=1 > ? ? ? ? cmp ? ? lr, #3 > ? ? ? ? moveq ? r0, r2 > ? ? ? ? ldmiaeq sp!, {r7, pc} > ? ? ? ? cmp ? ? lr, #2 > ? ? ? ? beq ? ? LBB0_5 > @ BB#3: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ %tailrecurse.switch > > The "tst ? ? r12, #3" can be replaced here with "cmp lr, #0", because > it is a mask operation testing against 0. We get this: > > ? ? ? ? ldr ? ? r12, [r2, #-4] > ? ? ? ? and ? ? lr, r12, #3 > ? ? ? ? cmp ? ? lr, #0 > ? ? ? ? beq ? ? LBB0_4 > @ BB#2: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ %tailrecurse.switch > > Now the peephole can apply: > ? ? ? ? ldr ? ? r12, [r2, #-4] > ? ? ? ? andS ? ?lr, r12, #3 > ? ? ? ? beq ? ? LBB0_4 > > effectively choosing the recording variant of AND and eliding the CMP > (formerly known as TST). > > Now I can go over your patch and see whether you already implement > this peephole transformation. If not, I'll try to improve on it. > > Cheers, and sorry for the confusion, > > ? ?Gabor > > > > > Cheers, > > > ? ?Gabor > > > > -bw > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bigcheesegs at gmail.com Mon Sep 13 12:52:38 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 13 Sep 2010 17:52:38 -0000 Subject: [llvm-commits] [llvm] r113762 - in /llvm/trunk: CMakeLists.txt utils/llvm-lit/CMakeLists.txt Message-ID: <20100913175238.826152A6C12C@llvm.org> Author: mspencer Date: Mon Sep 13 12:52:38 2010 New Revision: 113762 URL: http://llvm.org/viewvc/llvm-project?rev=113762&view=rev Log: CMake: Add llvm-lit to CMake build. Added: llvm/trunk/utils/llvm-lit/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=113762&r1=113761&r2=113762&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Mon Sep 13 12:52:38 2010 @@ -311,6 +311,7 @@ add_subdirectory(utils/FileCheck) add_subdirectory(utils/count) add_subdirectory(utils/not) +add_subdirectory(utils/llvm-lit) set(LLVM_ENUM_ASM_PRINTERS "") set(LLVM_ENUM_ASM_PARSERS "") Added: llvm/trunk/utils/llvm-lit/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-lit/CMakeLists.txt?rev=113762&view=auto ============================================================================== --- llvm/trunk/utils/llvm-lit/CMakeLists.txt (added) +++ llvm/trunk/utils/llvm-lit/CMakeLists.txt Mon Sep 13 12:52:38 2010 @@ -0,0 +1,12 @@ +configure_file( + llvm-lit.in + ${LLVM_TOOLS_BINARY_DIR}/llvm-lit + ) + +install(FILES + ${LLVM_TOOLS_BINARY_DIR}/llvm-lit + DESTINATION bin + PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE + GROUP_READ GROUP_EXECUTE + WORLD_READ WORLD_EXECUTE + ) From resistor at mac.com Mon Sep 13 12:59:28 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 13 Sep 2010 17:59:28 -0000 Subject: [llvm-commits] [llvm] r113763 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/CodeGen/ARM/fast-isel.ll test/Transforms/InstCombine/cast.ll test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100913175928.3462F2A6C12C@llvm.org> Author: resistor Date: Mon Sep 13 12:59:27 2010 New Revision: 113763 URL: http://llvm.org/viewvc/llvm-project?rev=113763&view=rev Log: Re-apply r113679, which was reverted in r113720, which added a paid of new instcombine transforms to expose greater opportunities for store narrowing in codegen. This patch fixes a potential infinite loop in instcombine caused by one of the introduced transforms being overly aggressive. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/CodeGen/ARM/fast-isel.ll llvm/trunk/test/Transforms/InstCombine/cast.ll llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=113763&r1=113762&r2=113763&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Sep 13 12:59:27 2010 @@ -207,12 +207,26 @@ } break; case Instruction::Or: - if (Op->hasOneUse() && Together != OpRHS) { - // (X | C1) & C2 --> (X | (C1&C2)) & C2 - Value *Or = Builder->CreateOr(X, Together); - Or->takeName(Op); - return BinaryOperator::CreateAnd(Or, AndRHS); + if (Op->hasOneUse()){ + if (Together != OpRHS) { + // (X | C1) & C2 --> (X | (C1&C2)) & C2 + Value *Or = Builder->CreateOr(X, Together); + Or->takeName(Op); + return BinaryOperator::CreateAnd(Or, AndRHS); + } + + ConstantInt *TogetherCI = dyn_cast(Together); + if (TogetherCI && !TogetherCI->isZero()){ + // (X | C1) & C2 --> (X & (C2^(C1&C2))) | C1 + // NOTE: This reduces the number of bits set in the & mask, which + // can expose opportunities for store narrowing. + Together = ConstantExpr::getXor(AndRHS, Together); + Value *And = Builder->CreateAnd(X, Together); + And->takeName(Op); + return BinaryOperator::CreateOr(And, OpRHS); + } } + break; case Instruction::Add: if (Op->hasOneUse()) { @@ -1943,6 +1957,18 @@ } } + // Note: If we've gotten to the point of visiting the outer OR, then the + // inner one couldn't be simplified. If it was a constant, then it won't + // be simplified by a later pass either, so we try swapping the inner/outer + // ORs in the hopes that we'll be able to simplify it this way. + // (X|C) | V --> (X|V) | C + if (Op0->hasOneUse() && !isa(Op1) && + match(Op0, m_Or(m_Value(A), m_ConstantInt(C1)))) { + Value *Inner = Builder->CreateOr(A, Op1); + Inner->takeName(Op0); + return BinaryOperator::CreateOr(Inner, C1); + } + return Changed ? &I : 0; } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=113763&r1=113762&r2=113763&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Mon Sep 13 12:59:27 2010 @@ -15,22 +15,6 @@ ret i32 %add } -define float @fp_ops(float %a, float %b) nounwind { -entry: - %a.addr = alloca float, align 4 - %b.addr = alloca float, align 4 - store float %a, float* %a.addr - store float %b, float* %b.addr - %tmp = load float* %a.addr - %tmp1 = load float* %b.addr - %mul = fmul float %tmp, %tmp1 - %tmp2 = load float* %b.addr - %tmp3 = load float* %a.addr - %mul2 = fmul float %tmp2, %tmp3 - %add = fadd float %mul, %mul2 - ret float %mul -} - define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind { entry: %r = load i32* %p Modified: llvm/trunk/test/Transforms/InstCombine/cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/cast.ll?rev=113763&r1=113762&r2=113763&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/cast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/cast.ll Mon Sep 13 12:59:27 2010 @@ -437,8 +437,8 @@ ret i64 %E ; CHECK: @test47 ; CHECK-NEXT: %B = sext i8 %A to i64 -; CHECK-NEXT: %C = or i64 %B, 42 -; CHECK-NEXT: %E = and i64 %C, 4294967295 +; CHECK-NEXT: %C = and i64 %B, 4294967253 +; CHECK-NEXT: %E = or i64 %C, 42 ; CHECK-NEXT: ret i64 %E } @@ -508,8 +508,8 @@ ret i32 %E ; CHECK: @test52 ; CHECK-NEXT: %B = trunc i64 %A to i32 -; CHECK-NEXT: %C = or i32 %B, 32962 -; CHECK-NEXT: %D = and i32 %C, 40186 +; CHECK-NEXT: %C = and i32 %B, 7224 +; CHECK-NEXT: %D = or i32 %C, 32962 ; CHECK-NEXT: ret i32 %D } @@ -521,8 +521,8 @@ ret i64 %E ; CHECK: @test53 ; CHECK-NEXT: %B = zext i32 %A to i64 -; CHECK-NEXT: %C = or i64 %B, 32962 -; CHECK-NEXT: %D = and i64 %C, 40186 +; CHECK-NEXT: %C = and i64 %B, 7224 +; CHECK-NEXT: %D = or i64 %C, 32962 ; CHECK-NEXT: ret i64 %D } @@ -534,8 +534,8 @@ ret i32 %E ; CHECK: @test54 ; CHECK-NEXT: %B = trunc i64 %A to i32 -; CHECK-NEXT: %C = or i32 %B, -32574 -; CHECK-NEXT: %D = and i32 %C, -25350 +; CHECK-NEXT: %C = and i32 %B, 7224 +; CHECK-NEXT: %D = or i32 %C, -32574 ; CHECK-NEXT: ret i32 %D } @@ -547,8 +547,8 @@ ret i64 %E ; CHECK: @test55 ; CHECK-NEXT: %B = zext i32 %A to i64 -; CHECK-NEXT: %C = or i64 %B, -32574 -; CHECK-NEXT: %D = and i64 %C, -25350 +; CHECK-NEXT: %C = and i64 %B, 7224 +; CHECK-NEXT: %D = or i64 %C, -32574 ; CHECK-NEXT: ret i64 %D } @@ -584,8 +584,8 @@ ; CHECK: @test58 ; CHECK-NEXT: %C = lshr i64 %A, 8 -; CHECK-NEXT: %D = or i64 %C, 128 -; CHECK-NEXT: %E = and i64 %D, 16777215 +; CHECK-NEXT: %D = and i64 %C, 16777087 +; CHECK-NEXT: %E = or i64 %D, 128 ; CHECK-NEXT: ret i64 %E } Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=113763&r1=113762&r2=113763&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Sep 13 12:59:27 2010 @@ -316,8 +316,8 @@ %E = or i32 %D, %C ret i32 %E ; CHECK: @test30 -; CHECK: %B = or i32 %A, 32962 -; CHECK: %E = and i32 %B, -25350 +; CHECK: %D = and i32 %A, -58312 +; CHECK: %E = or i32 %D, 32962 ; CHECK: ret i32 %E } @@ -332,8 +332,8 @@ %F = or i64 %D, %E ret i64 %F ; CHECK: @test31 -; CHECK-NEXT: %bitfield = or i64 %A, 32962 -; CHECK-NEXT: %F = and i64 %bitfield, 4294941946 +; CHECK-NEXT: %E1 = and i64 %A, 4294908984 +; CHECK-NEXT: %F = or i64 %E1, 32962 ; CHECK-NEXT: ret i64 %F } @@ -367,3 +367,12 @@ ; CHECK-NEXT: or i32 %X, %Y ; CHECK-NEXT: ret } + +define i32 @test35(i32 %a, i32 %b) { + %1 = or i32 %a, 1135 + %2 = or i32 %1, %b + ret i32 %2 + ; CHECK: @test35 + ; CHECK-NEXT: or i32 %a, %b + ; CHECK-NEXT: or i32 %1, 1135 +} Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=113763&r1=113762&r2=113763&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Mon Sep 13 12:59:27 2010 @@ -34,7 +34,7 @@ define i32 @test3(i32 %tmp1) { ; CHECK: @test3 ; CHECK-NEXT: and i32 %tmp1, 32 -; CHECK-NEXT: or i32 %tmp, 8 +; CHECK-NEXT: or i32 %ovm, 8 ; CHECK-NEXT: ret i32 %ovm = or i32 %tmp1, 145 %ov31 = and i32 %ovm, 177 From gohman at apple.com Mon Sep 13 13:00:48 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 13 Sep 2010 18:00:48 -0000 Subject: [llvm-commits] [llvm] r113764 - in /llvm/trunk/lib/Bitcode/Reader: BitcodeReader.cpp BitcodeReader.h Message-ID: <20100913180048.421DD2A6C12C@llvm.org> Author: djg Date: Mon Sep 13 13:00:48 2010 New Revision: 113764 URL: http://llvm.org/viewvc/llvm-project?rev=113764&view=rev Log: Add full auto-upgrade support for LLVM 2.7 bitcode metadata. Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=113764&r1=113763&r2=113764&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon Sep 13 13:00:48 2010 @@ -776,7 +776,8 @@ bool IsFunctionLocal = false; // Read a record. Record.clear(); - switch (Stream.ReadRecord(Code, Record)) { + Code = Stream.ReadRecord(Code, Record); + switch (Code) { default: // Default behavior: ignore. break; case bitc::METADATA_NAME: { @@ -790,11 +791,11 @@ Code = Stream.ReadCode(); // METADATA_NAME is always followed by METADATA_NAMED_NODE2. + // Or METADATA_NAMED_NODE in LLVM 2.7. FIXME: Remove this in LLVM 3.0. unsigned NextBitCode = Stream.ReadRecord(Code, Record); - // FIXME: LLVM 3.0: Remove this. - if (NextBitCode == bitc::METADATA_NAMED_NODE) - break; - if (NextBitCode != bitc::METADATA_NAMED_NODE2) + if (NextBitCode == bitc::METADATA_NAMED_NODE) { + LLVM2_7MetadataDetected = true; + } else if (NextBitCode != bitc::METADATA_NAMED_NODE2) assert ( 0 && "Inavlid Named Metadata record"); // Read named metadata elements. @@ -806,20 +807,27 @@ return Error("Malformed metadata record"); NMD->addOperand(MD); } + // Backwards compatibility hack: NamedMDValues used to be Values, + // and they got their own slots in the value numbering. They are no + // longer Values, however we still need to account for them in the + // numbering in order to be able to read old bitcode files. + // FIXME: Remove this in LLVM 3.0. + if (LLVM2_7MetadataDetected) + MDValueList.AssignValue(0, NextMDValueNo++); break; } - case bitc::METADATA_FN_NODE: - // FIXME: Legacy support for the old fn_node, where function-local - // metadata operands were bogus. Remove in LLVM 3.0. - break; - case bitc::METADATA_NODE: - // FIXME: Legacy support for the old node, where function-local - // metadata operands were bogus. Remove in LLVM 3.0. - break; + case bitc::METADATA_FN_NODE: // FIXME: Remove in LLVM 3.0. case bitc::METADATA_FN_NODE2: IsFunctionLocal = true; // fall-through + case bitc::METADATA_NODE: // FIXME: Remove in LLVM 3.0. case bitc::METADATA_NODE2: { + + // Detect 2.7-era metadata. + // FIXME: Remove in LLVM 3.0. + if (Code == bitc::METADATA_FN_NODE || Code == bitc::METADATA_NODE) + LLVM2_7MetadataDetected = true; + if (Record.size() % 2 == 1) return Error("Invalid METADATA_NODE2 record"); @@ -1614,9 +1622,9 @@ switch (Stream.ReadRecord(Code, Record)) { default: // Default behavior: ignore. break; + // FIXME: Remove in LLVM 3.0. case bitc::METADATA_ATTACHMENT: - // LLVM 3.0: Remove this. - break; + LLVM2_7MetadataDetected = true; case bitc::METADATA_ATTACHMENT2: { unsigned RecordLength = Record.size(); if (Record.empty() || (RecordLength - 1) % 2 == 1) @@ -1730,10 +1738,9 @@ I = 0; continue; + // FIXME: Remove this in LLVM 3.0. case bitc::FUNC_CODE_DEBUG_LOC: - // FIXME: Ignore. Remove this in LLVM 3.0. - continue; - + LLVM2_7MetadataDetected = true; case bitc::FUNC_CODE_DEBUG_LOC2: { // DEBUG_LOC: [line, col, scope, ia] I = 0; // Get the last instruction emitted. if (CurBB && !CurBB->empty()) @@ -2196,7 +2203,7 @@ } case bitc::FUNC_CODE_INST_ALLOCA: { // ALLOCA: [instty, opty, op, align] // For backward compatibility, tolerate a lack of an opty, and use i32. - // LLVM 3.0: Remove this. + // Remove this in LLVM 3.0. if (Record.size() < 3 || Record.size() > 4) return Error("Invalid ALLOCA record"); unsigned OpNum = 0; @@ -2249,12 +2256,10 @@ InstructionList.push_back(I); break; } + // FIXME: Remove this in LLVM 3.0. case bitc::FUNC_CODE_INST_CALL: + LLVM2_7MetadataDetected = true; case bitc::FUNC_CODE_INST_CALL2: { - // FIXME: Legacy support for the old call instruction, where function-local - // metadata operands were bogus. Remove in LLVM 3.0. - bool DropMetadata = BitCode == bitc::FUNC_CODE_INST_CALL; - // CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...] if (Record.size() < 3) return Error("Invalid CALL record"); @@ -2278,13 +2283,7 @@ for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) { if (FTy->getParamType(i)->getTypeID()==Type::LabelTyID) Args.push_back(getBasicBlock(Record[OpNum])); - else if (DropMetadata && - FTy->getParamType(i)->getTypeID()==Type::MetadataTyID) { - // LLVM 2.7 compatibility: drop metadata arguments to null. - Value *Ops = 0; - Args.push_back(MDNode::get(Context, &Ops, 1)); - continue; - } else + else Args.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i))); if (Args.back() == 0) return Error("Invalid CALL record"); } @@ -2379,9 +2378,21 @@ BlockAddrFwdRefs.erase(BAFRI); } + // FIXME: Remove this in LLVM 3.0. + unsigned NewMDValueListSize = MDValueList.size(); + // Trim the value list down to the size it was before we parsed this function. ValueList.shrinkTo(ModuleValueListSize); MDValueList.shrinkTo(ModuleMDValueListSize); + + // Backwards compatibility hack: Function-local metadata numbers + // were previously not reset between functions. This is now fixed, + // however we still need to understand the old numbering in order + // to be able to read old bitcode files. + // FIXME: Remove this in LLVM 3.0. + if (LLVM2_7MetadataDetected) + MDValueList.resize(NewMDValueListSize); + std::vector().swap(FunctionBBs); return false; Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h?rev=113764&r1=113763&r2=113764&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.h Mon Sep 13 13:00:48 2010 @@ -173,11 +173,18 @@ /// are resolved lazily when functions are loaded. typedef std::pair BlockAddrRefTy; DenseMap > BlockAddrFwdRefs; + + /// LLVM2_7MetadataDetected - True if metadata produced by LLVM 2.7 or + /// earlier was detected, in which case we behave slightly differently, + /// for compatibility. + /// FIXME: Remove in LLVM 3.0. + bool LLVM2_7MetadataDetected; public: explicit BitcodeReader(MemoryBuffer *buffer, LLVMContext &C) : Context(C), TheModule(0), Buffer(buffer), BufferOwned(false), - ErrorString(0), ValueList(C), MDValueList(C) { + ErrorString(0), ValueList(C), MDValueList(C), + LLVM2_7MetadataDetected(false) { HasReversedFunctionsWithBodies = false; } ~BitcodeReader() { From gohman at apple.com Mon Sep 13 13:02:47 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 13 Sep 2010 18:02:47 -0000 Subject: [llvm-commits] [llvm] r113765 - /llvm/trunk/tools/llvm-diff/llvm-diff.cpp Message-ID: <20100913180247.2D4732A6C12C@llvm.org> Author: djg Date: Mon Sep 13 13:02:47 2010 New Revision: 113765 URL: http://llvm.org/viewvc/llvm-project?rev=113765&view=rev Log: Use ParseIRFile to auto-detect LLVM Assembly automatically. Modified: llvm/trunk/tools/llvm-diff/llvm-diff.cpp Modified: llvm/trunk/tools/llvm-diff/llvm-diff.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/llvm-diff.cpp?rev=113765&r1=113764&r2=113765&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/llvm-diff.cpp (original) +++ llvm/trunk/tools/llvm-diff/llvm-diff.cpp Mon Sep 13 13:02:47 2010 @@ -17,13 +17,12 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/Type.h" -#include "llvm/Assembly/Parser.h" -#include "llvm/Bitcode/ReaderWriter.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/IRReader.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/SourceMgr.h" @@ -34,32 +33,14 @@ using namespace llvm; -/// Reads a module from a file. If the filename ends in .ll, it is -/// interpreted as an assembly file; otherwise, it is interpreted as -/// bitcode. On error, messages are written to stderr and null is -/// returned. +/// Reads a module from a file. On error, messages are written to stderr +/// and null is returned. static Module *ReadModule(LLVMContext &Context, StringRef Name) { - // LLVM assembly path. - if (Name.endswith(".ll")) { - SMDiagnostic Diag; - Module *M = ParseAssemblyFile(Name, Diag, Context); - if (M) return M; - + SMDiagnostic Diag; + Module *M = ParseIRFile(Name, Diag, Context); + if (!M) Diag.Print("llvmdiff", errs()); - return 0; - } - - // Bitcode path. - MemoryBuffer *Buffer = MemoryBuffer::getFile(Name); - - // ParseBitcodeFile takes ownership of the buffer if it succeeds. - std::string Error; - Module *M = ParseBitcodeFile(Buffer, Context, &Error); - if (M) return M; - - errs() << "error parsing " << Name << ": " << Error; - delete Buffer; - return 0; + return M; } namespace { From ggreif at gmail.com Mon Sep 13 13:04:01 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 13 Sep 2010 11:04:01 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> Message-ID: <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> On 12 Sep., 02:04, Bill Wendling wrote: > On Sep 11, 2010, at 5:43 AM, Gabor Greif wrote: > > > Bill, > > > I tried to extend your approach to TSTri (as an eliminable compare > > instr.) and > > ANDri (as an implicit compare) with this patch: > > That's what I'm attempting to do right now. :-) I want to do a bit more than just replace the TST with an AND that sets CPSR, though that's the first step. I'm introducing a separate callback instruction to handle TST (i.e., comparisons against a non-zero value). > > > gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ > > ARMBaseInstrInfo.cpp > > Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > > =================================================================== > > --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > > (revision 113683) > > +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > > (working copy) > > @@ -1372,6 +1372,10 @@ > > ? ? SrcReg = MI->getOperand(0).getReg(); > > ? ? CmpValue = MI->getOperand(1).getImm(); > > ? ? return true; > > + ?case ARM::TSTri: > > + ? ?SrcReg = MI->getOperand(0).getReg(); > > + ? ?CmpValue = 0; > > I think the TST instruction can take a compare value other than 0. The CMP instructions take 0, right? > > TST instructions have 2 operands and the second is a mask. It is a hybrid of "and" and "cmp" against 0. > > > > > @@ -1421,6 +1425,7 @@ > > ? switch (MI->getOpcode()) { > > ? default: break; > > ? case ARM::ADDri: > > + ?case ARM::ANDri: > > ? case ARM::SUBri: > > ? case ARM::t2ADDri: > > ? case ARM::t2SUBri: > > gabor at google8:~/llvm-build$ > > > BUT, it does not trigger on my example, because of > > something that appears to be a bug: > > > ? ? ? ?%reg16388 = PHI %reg16396, , %reg16392, ; GPR: > > %reg16388,16396,16392 > > ? ? ? ?%reg16389 = PHI %reg16385, , %reg16391, ; GPR: > > %reg16389,16385,16391 > > ? ? ? ?%reg16397 = LDR %reg16387, %reg0, 4100, pred:14, pred: > > %reg0; mem:LD4[%scevgep1] GPR:%reg16397,16387 > > ? ? ? ?%reg16390 = ANDri %reg16397, 3, pred:14, pred:%reg0, opt: > > %reg0; GPR:%reg16390,16397 > > ? ? ? ?TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR; GPR: > > %reg16397 > > ? ? ? ?Bcc , pred:0, pred:%CPSR > > > The TST seems to use the result of the LDR instead of that of the AND! > > Very fishy... > > If you want to use the result of AND instead of TST in the Bcc, you'll need to say that AND implicitly defines CSPR. In the above case, it looks like the AND is basically dead (at least in this code snippet). The TST performs an "and" of the 3 to the result of LDR, which is what the AND instruction does. The only difference here is that TST sets CPSR and the AND doesn't. > > > The bitcode is ok: > > > ?%tmp2 = load i8** %scevgep1 > > ?%0 = ptrtoint i8* %tmp2 to i32 > > ?%and = and i32 %0, 3 > > ?%tst = icmp eq i32 %and, 0 > > ?br i1 %tst, label %sw.bb, label %tailrecurse.switch > > > What do you think? Okay to commit the above? > > Below is what I have in my tree right now. It's just the skeleton of how I'd like to handle this (it does nothing right now). I like it because of how it separates out different optimization potentialities for each type of instruction, but it may be overkill... Yes, I think it is a bit of overkill. Logically TST is a compare instruction. In my last patch I successfully handle both with one sweep. If you think my approach is sufficient and works well on your testcases, I gladly check it in. Then I would like to establish something like dyn_cast > queries (with additional intelligence) for checking opcodes and getting operands. Would simplify my code a great amount. Cheers, Gabor > > -bw > > Index: include/llvm/Target/TargetInstrInfo.h > =================================================================== > --- include/llvm/Target/TargetInstrInfo.h ? ? ? (revision 113706) > +++ include/llvm/Target/TargetInstrInfo.h ? ? ? (working copy) > @@ -595,6 +595,15 @@ > ? ? ?return false; > ? ?} > > + ?/// OptimizeTestInstr - See if the test instruction can be converted into > + ?/// something more efficient. Update the iterator *only* if a transformation > + ?/// took place. > + ?virtual bool OptimizeTestInstr(MachineInstr * /*CmpInstr*/, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned /*SrcReg*/, int /*CmpValue*/, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock::iterator &MII) const { > + ? ?return false; > + ?} > + > ? ?/// getNumMicroOps - Return the number of u-operations the given machine > ? ?/// instruction will be decoded to on the target cpu. > ? ?virtual unsigned getNumMicroOps(const MachineInstr *MI, > Index: lib/Target/ARM/ARMBaseInstrInfo.cpp > =================================================================== > --- lib/Target/ARM/ARMBaseInstrInfo.cpp (revision 113706) > +++ lib/Target/ARM/ARMBaseInstrInfo.cpp (working copy) > @@ -1377,6 +1377,18 @@ > ? ?return false; > ?} > > +/// OptimizeTestInstr - See if we can convert the TEST instruction into an > +/// equivalent AND instruction, possibly saving an instruction or two if we can > +/// make AND set the flags register. > +bool ARMBaseInstrInfo:: > +OptimizeTestInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, > + ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock::iterator &MII) const { > + ?if (CmpValue == 0) > + ? ?return false; > + > + ?return false; > +} > + > ?/// OptimizeCompareInstr - Convert the instruction supplying the argument to the > ?/// comparison into one that sets the zero bit in the flags register. Update the > ?/// iterator *only* if a transformation took place. > Index: lib/Target/ARM/ARMBaseInstrInfo.h > =================================================================== > --- lib/Target/ARM/ARMBaseInstrInfo.h ? (revision 113706) > +++ lib/Target/ARM/ARMBaseInstrInfo.h ? (working copy) > @@ -350,6 +350,13 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int CmpValue, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock::iterator &MII) const; > > + ?/// OptimizeTestInstr - See if we can convert the TEST instruction into an > + ?/// equivalent AND instruction, possibly saving an instruction or two if we > + ?/// can make AND set the flags register. > + ?virtual bool OptimizeTestInstr(MachineInstr *CmpInstr, unsigned SrcReg, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int CmpValue, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock::iterator &MII) const; > + > ? ?virtual unsigned getNumMicroOps(const MachineInstr *MI, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const InstrItineraryData *ItinData) const; > ?}; > Index: lib/CodeGen/PeepholeOptimizer.cpp > =================================================================== > --- lib/CodeGen/PeepholeOptimizer.cpp ? (revision 113706) > +++ lib/CodeGen/PeepholeOptimizer.cpp ? (working copy) > @@ -249,6 +249,12 @@ > ? ? ?return true; > ? ?} > > + ?// Attempt to optimize the test instruction. > + ?if (TII->OptimizeTestInstr(MI, SrcReg, CmpValue, NextIter)) { > + ? ?++NumEliminated; > + ? ?return true; > + ?} > + > ? ?return false; > ?} > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From espindola at google.com Mon Sep 13 13:14:51 2010 From: espindola at google.com (Rafael Espindola) Date: Mon, 13 Sep 2010 14:14:51 -0400 Subject: [llvm-commits] [patch] Fix handling of common symbols Message-ID: The attached patch fixes the included testcase. On ELF common symbols have to have the section index SHN_COMMON. It looks like this is not the case on MACHO, but is similar to how absolute symbols are handled. What this patch does is * Create a CommonPseudoSection so that we don't end up marking the symbol as undefined. * Default the symbol to global. This is what gas does on the attached testcase, not sure if it is always so. * Remove some forcing of STB_GLOBAL. * Add code to handle .local Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: common.patch Type: text/x-patch Size: 4626 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100913/56faf5d7/attachment.bin From echristo at apple.com Mon Sep 13 13:25:05 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 13 Sep 2010 18:25:05 -0000 Subject: [llvm-commits] [llvm] r113767 - /llvm/trunk/lib/VMCore/InlineAsm.cpp Message-ID: <20100913182505.594E32A6C12C@llvm.org> Author: echristo Date: Mon Sep 13 13:25:05 2010 New Revision: 113767 URL: http://llvm.org/viewvc/llvm-project?rev=113767&view=rev Log: Silence some constructor ordering warnings. Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=113767&r1=113766&r2=113767&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Mon Sep 13 13:25:05 2010 @@ -56,18 +56,18 @@ ///Default constructor. InlineAsm::ConstraintInfo::ConstraintInfo() : - isMultipleAlternative(false), Type(isInput), isEarlyClobber(false), MatchingInput(-1), isCommutative(false), - isIndirect(false), currentAlternativeIndex(0) { + isIndirect(false), isMultipleAlternative(false), + currentAlternativeIndex(0) { } /// Copy constructor. InlineAsm::ConstraintInfo::ConstraintInfo(const ConstraintInfo &other) : - isMultipleAlternative(other.isMultipleAlternative), Type(other.Type), isEarlyClobber(other.isEarlyClobber), MatchingInput(other.MatchingInput), isCommutative(other.isCommutative), isIndirect(other.isIndirect), Codes(other.Codes), + isMultipleAlternative(other.isMultipleAlternative), multipleAlternatives(other.multipleAlternatives), currentAlternativeIndex(other.currentAlternativeIndex) { } From grosbach at apple.com Mon Sep 13 13:25:43 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 13 Sep 2010 18:25:43 -0000 Subject: [llvm-commits] [llvm] r113768 - in /llvm/trunk/lib/Target/ARM: ARMMCInstLower.cpp ARMMCInstLower.h Message-ID: <20100913182543.2095D2A6C12C@llvm.org> Author: grosbach Date: Mon Sep 13 13:25:42 2010 New Revision: 113768 URL: http://llvm.org/viewvc/llvm-project?rev=113768&view=rev Log: trailing whitespace Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp llvm/trunk/lib/Target/ARM/ARMMCInstLower.h Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=113768&r1=113767&r2=113768&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Mon Sep 13 13:25:42 2010 @@ -34,7 +34,7 @@ MachineModuleInfoMachO &ARMMCInstLower::getMachOMMI() const { assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin"); - return AsmPrinter.MMI->getObjFileInfo(); + return AsmPrinter.MMI->getObjFileInfo(); } #endif @@ -45,7 +45,7 @@ default: assert(0 && "Unknown target flag on GV operand"); case 0: break; } - + return Printer.Mang->getSymbol(MO.getGlobal()); } @@ -56,7 +56,7 @@ default: assert(0 && "Unknown target flag on GV operand"); case 0: break; } - + return Printer.GetExternalSymbolSymbol(MO.getSymbolName()); } @@ -67,13 +67,13 @@ SmallString<256> Name; raw_svector_ostream(Name) << Printer.MAI->getPrivateGlobalPrefix() << "JTI" << Printer.getFunctionNumber() << '_' << MO.getIndex(); - + #if 0 switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); } #endif - + // Create a symbol for the name. return Ctx.GetOrCreateSymbol(Name.str()); } @@ -83,29 +83,29 @@ SmallString<256> Name; raw_svector_ostream(Name) << Printer.MAI->getPrivateGlobalPrefix() << "CPI" << Printer.getFunctionNumber() << '_' << MO.getIndex(); - + #if 0 switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); } #endif - + // Create a symbol for the name. return Ctx.GetOrCreateSymbol(Name.str()); } - + MCOperand ARMMCInstLower:: LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const { // FIXME: We would like an efficient form for this, so we don't have to do a // lot of extra uniquing. const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx); - + #if 0 switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); } #endif - + if (!MO.isJTI() && MO.getOffset()) Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), @@ -116,10 +116,10 @@ void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); - + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - + MCOperand MCOp; switch (MO.getType()) { default: @@ -155,8 +155,8 @@ MO.getBlockAddress())); break; } - + OutMI.addOperand(MCOp); } - + } Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.h?rev=113768&r1=113767&r2=113768&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.h (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.h Mon Sep 13 13:25:42 2010 @@ -24,7 +24,7 @@ class MachineOperand; class Mangler; //class ARMSubtarget; - + /// ARMMCInstLower - This class is used to lower an MachineInstr into an MCInst. class LLVM_LIBRARY_VISIBILITY ARMMCInstLower { MCContext &Ctx; @@ -35,7 +35,7 @@ public: ARMMCInstLower(MCContext &ctx, Mangler &mang, AsmPrinter &printer) : Ctx(ctx), Mang(mang), Printer(printer) {} - + void Lower(const MachineInstr *MI, MCInst &OutMI) const; //MCSymbol *GetPICBaseSymbol() const; @@ -44,7 +44,7 @@ MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const; MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; - + /* private: MachineModuleInfoMachO &getMachOMMI() const; From wendling at apple.com Mon Sep 13 13:28:11 2010 From: wendling at apple.com (Bill Wendling) Date: Mon, 13 Sep 2010 11:28:11 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <31a29eba-d910-4783-b998-694ace37562d@g10g2000vbc.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> <31a29eba-d910-4783-b998-694ace37562d@g10g2000vbc.googlegroups.com> Message-ID: <6028B900-9B66-4A42-9A79-0DE016DDDCB7@apple.com> On Sep 13, 2010, at 3:27 AM, Gabor Greif wrote: >> If you want to use the result of AND instead of TST in the Bcc, you'll need to say that AND implicitly defines CSPR. In the above case, it looks like the AND is basically dead (at least in this code snippet). The TST performs an "and" of the 3 to the result of LDR, which is what the AND instruction does. The only difference here is that TST sets CPSR and the AND doesn't. > > I thought the point of your patch is to visit all "cmp r, #0" and "tst > r" instructions and when they act on a register that is defined by an > instruction that has a form to set CPSR, you switch to that form. This > allows you to elide the "tst" rsp. "cmp". Did I get it right? > Yup. That's the basic idea. There are other more complex optimizations that I'd like to do, but that's one of the easiest changes. -bw From echristo at apple.com Mon Sep 13 13:27:59 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 13 Sep 2010 18:27:59 -0000 Subject: [llvm-commits] [llvm] r113769 - /llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Message-ID: <20100913182759.5B5172A6C12C@llvm.org> Author: echristo Date: Mon Sep 13 13:27:59 2010 New Revision: 113769 URL: http://llvm.org/viewvc/llvm-project?rev=113769&view=rev Log: Remove unused variable. Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=113769&r1=113768&r2=113769&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Sep 13 13:27:59 2010 @@ -736,7 +736,6 @@ bool CodeGenPrepare::OptimizeInlineAsmInst(Instruction *I, CallSite CS, DenseMap &SunkAddrs) { bool MadeChange = false; - InlineAsm *IA = cast(CS.getCalledValue()); std::vector TargetConstraints = TLI->ParseConstraints(CS); for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { From resistor at mac.com Mon Sep 13 13:28:40 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 13 Sep 2010 18:28:40 -0000 Subject: [llvm-commits] [llvm] r113770 - /llvm/trunk/test/Transforms/InstCombine/crash.ll Message-ID: <20100913182840.2D5212A6C12C@llvm.org> Author: resistor Date: Mon Sep 13 13:28:40 2010 New Revision: 113770 URL: http://llvm.org/viewvc/llvm-project?rev=113770&view=rev Log: Add a reduced testcase for the infinite loop fixed in r113763. Modified: llvm/trunk/test/Transforms/InstCombine/crash.ll Modified: llvm/trunk/test/Transforms/InstCombine/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/crash.ll?rev=113770&r1=113769&r2=113770&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/crash.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/crash.ll Mon Sep 13 13:28:40 2010 @@ -252,3 +252,36 @@ %conv6 = zext i1 %cmp5 to i32 ; [#uses=0] ret void } + +%s1 = type { %s2, %s2, [6 x %s2], i32, i32, i32, [1 x i32], [0 x i8] } +%s2 = type { i64 } +define void @test13() nounwind ssp { +entry: + %0 = getelementptr inbounds %s1* null, i64 0, i32 2, i64 0, i32 0 + %1 = bitcast i64* %0 to i32* + %2 = getelementptr inbounds %s1* null, i64 0, i32 2, i64 1, i32 0 + %.pre = load i32* %1, align 8 + %3 = lshr i32 %.pre, 19 + %brmerge = or i1 undef, undef + %4 = and i32 %3, 3 + %5 = add nsw i32 %4, 1 + %6 = shl i32 %5, 19 + %7 = add i32 %6, 1572864 + %8 = and i32 %7, 1572864 + %9 = load i64* %2, align 8 + %trunc156 = trunc i64 %9 to i32 + %10 = and i32 %trunc156, -1537 + %11 = and i32 %10, -6145 + %12 = or i32 %11, 2048 + %13 = and i32 %12, -24577 + %14 = or i32 %13, 16384 + %15 = or i32 %14, 98304 + store i32 %15, i32* undef, align 8 + %16 = and i32 %15, -1572865 + %17 = or i32 %16, %8 + store i32 %17, i32* undef, align 8 + %18 = and i32 %17, -449 + %19 = or i32 %18, 64 + store i32 %19, i32* undef, align 8 + unreachable +} From echristo at apple.com Mon Sep 13 13:30:57 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 13 Sep 2010 18:30:57 -0000 Subject: [llvm-commits] [llvm] r113771 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20100913183057.98B542A6C12C@llvm.org> Author: echristo Date: Mon Sep 13 13:30:57 2010 New Revision: 113771 URL: http://llvm.org/viewvc/llvm-project?rev=113771&view=rev Log: Silence more warnings. Two more unused variables. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=113771&r1=113770&r2=113771&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Sep 13 13:30:57 2010 @@ -2829,8 +2829,6 @@ int TargetLowering::getMultipleConstraintMatchWeight( AsmOperandInfo &info, int maIndex) const { std::vector &rCodes = info.multipleAlternatives[maIndex].Codes; - int matchingInput = info.multipleAlternatives[maIndex].MatchingInput; - TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; int BestWeight = -1; // Loop over the options, keeping track of the most general one. From echristo at apple.com Mon Sep 13 13:44:30 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 13 Sep 2010 11:44:30 -0700 Subject: [llvm-commits] [PATCH][EXPERIMENTAL] Building LLVMgold.dll In-Reply-To: References: Message-ID: On Sep 13, 2010, at 7:19 AM, NAKAMURA Takumi wrote: > Good evening, guys! > > This patch enables building LTO.dll, libLTO.a and LLVMgold.dll on cygming. > I know it is still incomplete, and I would say it is "experimental". > > Known issue: > > - dependency between libs would be incomplete. > - I don't know how to test functionality. Some review: - # No support for dynamic libraries on windows targets. - ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW)) Do we now support building libLTO and gold as static libraries or do dynamic libraries now work? # gold only builds if binutils is around. It requires "lto" to build before # it so it is added to DIRS. ifdef BINUTILS_INCDIR - DIRS += lto gold + DIRS += lto + PARALLEL_DIRS += gold Either the code is wrong or the comment is wrong :) OK, I see how you're getting around the dynamic library thing: LINK_COMPONENTS := support system -LIBS += -llto + +ifneq (,$(filter $(HOST_OS), Cygwin MingW)) + ifneq ($(ENABLE_SHARED),1) + LINK_COMPONENTS += $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter + endif +endif Eeew. Can you give an explanation? There has to be a better way of doing this. Anyhow, I think the patch needs some explanation of what you're trying to do and why. -eric From resistor at mac.com Mon Sep 13 13:47:42 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 13 Sep 2010 18:47:42 -0000 Subject: [llvm-commits] [llvm] r113772 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp Message-ID: <20100913184742.D8CBA2A6C12C@llvm.org> Author: resistor Date: Mon Sep 13 13:47:42 2010 New Revision: 113772 URL: http://llvm.org/viewvc/llvm-project?rev=113772&view=rev Log: Minimize #includes in a top-level header. Modified: llvm/trunk/include/llvm/PassRegistry.h llvm/trunk/lib/VMCore/PassRegistry.cpp Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=113772&r1=113771&r2=113772&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Mon Sep 13 13:47:42 2010 @@ -17,8 +17,7 @@ #ifndef LLVM_PASSREGISTRY_H #define LLVM_PASSREGISTRY_H -#include "llvm/ADT/StringMap.h" -#include "llvm/System/DataTypes.h" +#include "llvm/ADT/StringRef.h" namespace llvm { Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=113772&r1=113771&r2=113772&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Mon Sep 13 13:47:42 2010 @@ -18,6 +18,7 @@ #include "llvm/Support/ManagedStatic.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/StringMap.h" #include using namespace llvm; From wendling at apple.com Mon Sep 13 13:49:30 2010 From: wendling at apple.com (Bill Wendling) Date: Mon, 13 Sep 2010 11:49:30 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> Message-ID: <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> On Sep 13, 2010, at 11:04 AM, Gabor Greif wrote: > On 12 Sep., 02:04, Bill Wendling wrote: >> I think the TST instruction can take a compare value other than 0. The CMP instructions take 0, right? > TST instructions have 2 operands and the second is a mask. It is a > hybrid of "and" and "cmp" against 0. The third operand is a "shift" when using a register-register test (according to my documentation). But we covered that in a previous email. >> Below is what I have in my tree right now. It's just the skeleton of how I'd like to handle this (it does nothing right now). I like it because of how it separates out different optimization potentialities for each type of instruction, but it may be overkill... > > Yes, I think it is a bit of overkill. Logically TST is a compare > instruction. In my last patch I successfully handle both with one > sweep. If you think my approach is sufficient and works well on your > testcases, I gladly check it in. Then I would like to establish > something like > > dyn_cast > > queries (with additional intelligence) for checking opcodes and > getting operands. Would simplify my code a great amount. > Here's your patch from another email. My comments are in-line: gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ ARMBaseInstrInfo.cpp Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (revision 113747) +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (working copy) @@ -1372,6 +1372,19 @@ SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; + case ARM::TSTri: { + if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI)) + return false; + const MachineInstr *AND = llvm::prior(MI); The AND doesn't have to be the immediately prior instruction. I could happen further up in the BB just as long as there isn't an intervening instruction which sets CPSR. + if (AND->getOpcode() != ARM::ANDri) + return false; + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && // FIXME: or == AND + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {// FIXME: subset + SrcReg = AND->getOperand(0).getReg(); + CmpValue = 0; CmpValue might not be 0 here. + return true; + } + } There's no need for this to be as complex here. The logic should be pretty much identical to the CMP cases. In fact, I think it is identical when you have a TST of an immediate. This logic should reside in ARMBaseInstrInfo::OptimizeCompareInstr. Once you do that, the tests of SrcReg & CmpValue become trivial. I need to comment this method better. It's supposed to return the source register and compare values of the comparison instruction. } return false; @@ -1421,6 +1434,7 @@ switch (MI->getOpcode()) { default: break; case ARM::ADDri: + case ARM::ANDri: Also do t2ANDri. case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: To do the optimization you suggest should be almost as easy as simply adding the TST* cases to the switch statements and removing the "if (CmpValue != 0) return false;" from OptimizeCompareInstr. :-) -bw -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100913/af28af54/attachment.html From resistor at mac.com Mon Sep 13 14:47:32 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 13 Sep 2010 19:47:32 -0000 Subject: [llvm-commits] [llvm] r113773 - /llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Message-ID: <20100913194733.448012A6C12C@llvm.org> Author: resistor Date: Mon Sep 13 14:47:32 2010 New Revision: 113773 URL: http://llvm.org/viewvc/llvm-project?rev=113773&view=rev Log: Attempt to fix the Linux build. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=113773&r1=113772&r2=113773&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Sep 13 14:47:32 2010 @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Support/DebugLoc.h" +#include "llvm/System/DataTypes.h" namespace llvm { class BlockAddress; From isanbard at gmail.com Mon Sep 13 15:00:56 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 13 Sep 2010 20:00:56 -0000 Subject: [llvm-commits] [test-suite] r113774 - /test-suite/branches/release_28/MultiSource/Applications/OpenSSL/ Message-ID: <20100913200056.6603C2A6C12C@llvm.org> Author: void Date: Mon Sep 13 15:00:56 2010 New Revision: 113774 URL: http://llvm.org/viewvc/llvm-project?rev=113774&view=rev Log: Update to r113752. Removed: test-suite/branches/release_28/MultiSource/Applications/OpenSSL/ From isanbard at gmail.com Mon Sep 13 15:01:38 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 13 Sep 2010 20:01:38 -0000 Subject: [llvm-commits] [test-suite] r113775 - /test-suite/branches/release_28/MultiSource/Applications/Makefile Message-ID: <20100913200138.B04092A6C12C@llvm.org> Author: void Date: Mon Sep 13 15:01:38 2010 New Revision: 113775 URL: http://llvm.org/viewvc/llvm-project?rev=113775&view=rev Log: Remove OpenSSL. Modified: test-suite/branches/release_28/MultiSource/Applications/Makefile Modified: test-suite/branches/release_28/MultiSource/Applications/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_28/MultiSource/Applications/Makefile?rev=113775&r1=113774&r2=113775&view=diff ============================================================================== --- test-suite/branches/release_28/MultiSource/Applications/Makefile (original) +++ test-suite/branches/release_28/MultiSource/Applications/Makefile Mon Sep 13 15:01:38 2010 @@ -5,7 +5,7 @@ include $(LEVEL)/Makefile.config PARALLEL_DIRS = Burg aha sgefa siod d spiff treecc SPASS \ - oggenc JM viterbi SIBsim4 ClamAV sqlite3 lemon OpenSSL + oggenc JM viterbi SIBsim4 ClamAV sqlite3 lemon ifndef DISABLE_CXX PARALLEL_DIRS += lambda-0.1.3 hbd hexxagon minisat endif From ggreif at gmail.com Mon Sep 13 15:05:48 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 13 Sep 2010 22:05:48 +0200 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> Message-ID: On 9/13/10, Bill Wendling wrote: > On Sep 13, 2010, at 11:04 AM, Gabor Greif wrote: > >> On 12 Sep., 02:04, Bill Wendling wrote: >>> I think the TST instruction can take a compare value other than 0. The >>> CMP instructions take 0, right? >> TST instructions have 2 operands and the second is a mask. It is a >> hybrid of "and" and "cmp" against 0. I should have worded more carefully here. I mean the TSTri opcode. The corresponding MachineInstruction has 2 operands: - the operand register 1 - the mask immediate > > The third operand is a "shift" when using a register-register test > (according to my documentation). But we covered that in a previous email. This would be TSTrs. I have no ambition to peephole optimize those (yet?). > >>> Below is what I have in my tree right now. It's just the skeleton of how >>> I'd like to handle this (it does nothing right now). I like it because of >>> how it separates out different optimization potentialities for each type >>> of instruction, but it may be overkill... >> >> Yes, I think it is a bit of overkill. Logically TST is a compare >> instruction. In my last patch I successfully handle both with one >> sweep. If you think my approach is sufficient and works well on your >> testcases, I gladly check it in. Then I would like to establish >> something like >> >> dyn_cast > >> queries (with additional intelligence) for checking opcodes and >> getting operands. Would simplify my code a great amount. >> > Here's your patch from another email. My comments are in-line: > > gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ > ARMBaseInstrInfo.cpp > Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > =================================================================== > --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > (revision 113747) > +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > (working copy) > @@ -1372,6 +1372,19 @@ > SrcReg = MI->getOperand(0).getReg(); > CmpValue = MI->getOperand(1).getImm(); > return true; > + case ARM::TSTri: { > + if (MI->getParent()->begin() == > MachineBasicBlock::const_iterator(MI)) > + return false; > + const MachineInstr *AND = llvm::prior(MI); > > The AND doesn't have to be the immediately prior instruction. I could happen > further up in the BB just as long as there isn't an intervening instruction > which sets CPSR. Yes, but the instruction selector tends to create sequences like this: rN = ... rM = and rN, #mask ... ; intervening instructions tst rN, #mask Note that both "and" and "tst" consume rN! But if we want to change the form of "and" to "andS" we have to find it. My first guess is to look immediately before the "tst". I may relax that (to, say 5 predecessors), but do not want to risk a quadratic algorithm. > > + if (AND->getOpcode() != ARM::ANDri) > + return false; > + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && // > FIXME: or == AND > + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {// > FIXME: subset > + SrcReg = AND->getOperand(0).getReg(); > + CmpValue = 0; > > CmpValue might not be 0 here. Whatever the mask is, the comparison is always against zero for the TSTri opcode. I hope I am not terribly mistaken with this statement :-) > > + return true; > + } > + } > > There's no need for this to be as complex here. The logic should be pretty > much identical to the CMP cases. In fact, I think it is identical when you > have a TST of an immediate. This logic should reside in I only attempt to cover the TSTri case. I do *not* think it is just as easy as "CMPri", because of the search for a suitable ANDri instruction that feeds from the same input and uses the same (super-) mask. Only in this case the "andS" will be equivalent. > ARMBaseInstrInfo::OptimizeCompareInstr. Once you do that, the tests of > SrcReg & CmpValue become trivial. > > I need to comment this method better. It's supposed to return the source > register and compare values of the comparison instruction. Yes, I think I got this. > > } > > return false; > @@ -1421,6 +1434,7 @@ > switch (MI->getOpcode()) { > default: break; > case ARM::ADDri: > + case ARM::ANDri: > > Also do t2ANDri. Sure, adding it. > > case ARM::SUBri: > case ARM::t2ADDri: > case ARM::t2SUBri: > > To do the optimization you suggest should be almost as easy as simply adding > the TST* cases to the switch statements and removing the "if (CmpValue != 0) > return false;" from OptimizeCompareInstr. :-) Are you talking about TSTrr and TSTrs here? Cheers, Gabor > > -bw > > From benny.kra at googlemail.com Mon Sep 13 15:04:49 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 13 Sep 2010 20:04:49 -0000 Subject: [llvm-commits] [llvm] r113776 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h include/llvm/Target/TargetData.h lib/CodeGen/AsmPrinter/DwarfDebug.h Message-ID: <20100913200449.7795D2A6C12C@llvm.org> Author: d0k Date: Mon Sep 13 15:04:49 2010 New Revision: 113776 URL: http://llvm.org/viewvc/llvm-project?rev=113776&view=rev Log: Fix linux/msvc build, move include. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=113776&r1=113775&r2=113776&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Sep 13 15:04:49 2010 @@ -17,7 +17,6 @@ #define LLVM_CODEGEN_ASMPRINTER_H #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/Support/DebugLoc.h" #include "llvm/System/DataTypes.h" namespace llvm { Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=113776&r1=113775&r2=113776&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Mon Sep 13 15:04:49 2010 @@ -22,6 +22,7 @@ #include "llvm/Pass.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/System/DataTypes.h" namespace llvm { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=113776&r1=113775&r2=113776&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Sep 13 15:04:49 2010 @@ -23,6 +23,7 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/UniqueVector.h" #include "llvm/Support/Allocator.h" +#include "llvm/Support/DebugLoc.h" namespace llvm { From wendling at apple.com Mon Sep 13 15:06:22 2010 From: wendling at apple.com (Bill Wendling) Date: Mon, 13 Sep 2010 13:06:22 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> Message-ID: <5E398B72-D986-4BFA-851E-BB5EEAF8A1A0@apple.com> On Sep 13, 2010, at 11:49 AM, Bill Wendling wrote: > To do the optimization you suggest should be almost as easy as simply adding the TST* cases to the switch statements and removing the "if (CmpValue != 0) return false;" from OptimizeCompareInstr. :-) > Small correction. You will need to make sure that the AND uses the same SrcReg and CmpValue as the TST instruction. :-) -bw From wendling at apple.com Mon Sep 13 15:22:05 2010 From: wendling at apple.com (Bill Wendling) Date: Mon, 13 Sep 2010 13:22:05 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> Message-ID: On Sep 13, 2010, at 1:05 PM, Gabor Greif wrote: >> Here's your patch from another email. My comments are in-line: >> >> gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ >> ARMBaseInstrInfo.cpp >> Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp >> =================================================================== >> --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp >> (revision 113747) >> +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp >> (working copy) >> @@ -1372,6 +1372,19 @@ >> SrcReg = MI->getOperand(0).getReg(); >> CmpValue = MI->getOperand(1).getImm(); >> return true; >> + case ARM::TSTri: { >> + if (MI->getParent()->begin() == >> MachineBasicBlock::const_iterator(MI)) >> + return false; >> + const MachineInstr *AND = llvm::prior(MI); >> >> The AND doesn't have to be the immediately prior instruction. I could happen >> further up in the BB just as long as there isn't an intervening instruction >> which sets CPSR. > > Yes, but the instruction selector tends to create sequences like this: > > rN = ... > rM = and rN, #mask > ... ; intervening instructions > tst rN, #mask > > Note that both "and" and "tst" consume rN! But if we want to change > the form of "and" to "andS" we have to find it. My first guess is to > look immediately before the "tst". I may relax that (to, say 5 > predecessors), but do not want to risk a quadratic algorithm. > The algorithm is only O(n), where n is the number of instructions in the basic block. But limiting it to 5 or so is probably not bad. My guess is that the back-end generates the AND directly before the TST in most cases. >> + if (AND->getOpcode() != ARM::ANDri) >> + return false; >> + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && // >> FIXME: or == AND >> + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {// >> FIXME: subset >> + SrcReg = AND->getOperand(0).getReg(); >> + CmpValue = 0; >> >> CmpValue might not be 0 here. > > Whatever the mask is, the comparison is always against zero for the > TSTri opcode. I hope I am not terribly mistaken with this statement > :-) > The CmpValue here means the mask value in this case. The terminology is messing us up. >> >> + return true; >> + } >> + } >> >> There's no need for this to be as complex here. The logic should be pretty >> much identical to the CMP cases. In fact, I think it is identical when you >> have a TST of an immediate. This logic should reside in > > I only attempt to cover the TSTri case. I do *not* think it is just as > easy as "CMPri", because of the search for a suitable ANDri > instruction that feeds from the same input > and uses the same (super-) mask. Only in this case the "andS" will be > equivalent. > But that logic should still reside in the OptimizeCompareInstr method. It will have to be modified some, but it's not complex. >> case ARM::SUBri: >> case ARM::t2ADDri: >> case ARM::t2SUBri: >> >> To do the optimization you suggest should be almost as easy as simply adding >> the TST* cases to the switch statements and removing the "if (CmpValue != 0) >> return false;" from OptimizeCompareInstr. :-) > > Are you talking about TSTrr and TSTrs here? > TST against the immediate. -bw From dpatel at apple.com Mon Sep 13 15:42:15 2010 From: dpatel at apple.com (Devang Patel) Date: Mon, 13 Sep 2010 20:42:15 -0000 Subject: [llvm-commits] [llvm] r113779 - /llvm/trunk/utils/test_debuginfo.pl Message-ID: <20100913204215.B069B2A6C12D@llvm.org> Author: dpatel Date: Mon Sep 13 15:42:15 2010 New Revision: 113779 URL: http://llvm.org/viewvc/llvm-project?rev=113779&view=rev Log: Add little test script to check debug info. Added: llvm/trunk/utils/test_debuginfo.pl (with props) Added: llvm/trunk/utils/test_debuginfo.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/test_debuginfo.pl?rev=113779&view=auto ============================================================================== --- llvm/trunk/utils/test_debuginfo.pl (added) +++ llvm/trunk/utils/test_debuginfo.pl Mon Sep 13 15:42:15 2010 @@ -0,0 +1,61 @@ +#!/usr/bin/perl +# +# This script tests debugging information generated by a compiler. +# Input arguments +# - Input source program. Usually this source file is decorated using +# special comments to communicate debugger commands. +# - Executable file. This file is generated by the compiler. +# +# This perl script extracts debugger commands from input source program +# comments in a script. A debugger is used to load the executable file +# and run the script generated from source program comments. Finally, +# the debugger output is checked, using FileCheck, to validate +# debugging information. + +use File::Basename; + +my $testcase_file = $ARGV[0]; +my $executable_file = $ARGV[1]; + +my $input_filename = basename $testcase_file; +my $output_dir = dirname $executable_file; + +my $debugger_script_file = "$output_dir/$input_filename.gdb.scirpt"; +my $output_file = "$output_dir/$input_filename.gdb.output"; + +# Extract debugger commands from testcase. They are marked with DEBUGGER: +# at the beginnign of a comment line. +open(INPUT, $testcase_file); +open(OUTPUT, ">$debugger_script_file"); +while() { + my($line) = $_; + $i = index($line, "DEBUGGER:"); + if ( $i >= 0) { + $l = length("DEBUGGER:"); + $s = substr($line, $i + $l); + print OUTPUT "$s"; + } +} +print OUTPUT "\n"; +print OUTPUT "quit\n"; +close(INPUT); +close(OUTPUT); + +# setup debugger and debugger options to run a script. +my $my_debugger = $ENV{'DEBUGGER'}; +if (!$my_debugger) { + $my_debugger = "gdb"; +} +my $debugger_options = "-q -batch -n -x"; + +# run debugger and capture output. +system("$my_debugger $debugger_options $debugger_script_file $executable_file >& $output_file"); + +# validate output. +system("FileCheck", "-input-file", "$output_file", "$testcase_file"); +if ($?>>8 == 1) { + exit 1; +} +else { + exit 0; +} Propchange: llvm/trunk/utils/test_debuginfo.pl ------------------------------------------------------------------------------ svn:executable = * From grosbach at apple.com Mon Sep 13 15:50:24 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 13 Sep 2010 13:50:24 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> <04c88a25-23dd-4806-bc30-429adae9ec29@e20g2000vbn.googlegroups.com> <4E233121-BF0B-4CC4-A87E-E4CCB6F47031@apple.com> Message-ID: <0B843361-DAEF-4734-B594-E60BEA65D880@apple.com> On Sep 13, 2010, at 1:22 PM, Bill Wendling wrote: > On Sep 13, 2010, at 1:05 PM, Gabor Greif wrote: > >>> Here's your patch from another email. My comments are in-line: >>> >>> gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ >>> ARMBaseInstrInfo.cpp >>> Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp >>> =================================================================== >>> --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp >>> (revision 113747) >>> +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp >>> (working copy) >>> @@ -1372,6 +1372,19 @@ >>> SrcReg = MI->getOperand(0).getReg(); >>> CmpValue = MI->getOperand(1).getImm(); >>> return true; >>> + case ARM::TSTri: { >>> + if (MI->getParent()->begin() == >>> MachineBasicBlock::const_iterator(MI)) >>> + return false; >>> + const MachineInstr *AND = llvm::prior(MI); >>> >>> The AND doesn't have to be the immediately prior instruction. I could happen >>> further up in the BB just as long as there isn't an intervening instruction >>> which sets CPSR. >> >> Yes, but the instruction selector tends to create sequences like this: >> >> rN = ... >> rM = and rN, #mask >> ... ; intervening instructions >> tst rN, #mask >> >> Note that both "and" and "tst" consume rN! But if we want to change >> the form of "and" to "andS" we have to find it. My first guess is to >> look immediately before the "tst". I may relax that (to, say 5 >> predecessors), but do not want to risk a quadratic algorithm. >> > The algorithm is only O(n), where n is the number of instructions in the basic block. But limiting it to 5 or so is probably not bad. My guess is that the back-end generates the AND directly before the TST in most cases. Likely. The scheduler may well move it around a bit, though. Previously, I've dealt with this by scanning backwards in the instructions 'til I find the of the input register or the start of the basic block. Having a hard limit on the number of instructions to scan and just punting if it's not found by then sounds reasonable. For example, it's not too unusual to see sequences like the following: cmp r5, #15 vdup.32 q1, r1 vadd.i32 q2, q1, q1 vadd.i32 q1, q0, q1 bls LBB0_8 When there's no other benefit, we'd like to prevent the post-RA scheduler from doing things like that, but there's no logic in there to do so at the moment. It's on my plate to do that at some point. -Jim > >>> + if (AND->getOpcode() != ARM::ANDri) >>> + return false; >>> + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && // >>> FIXME: or == AND >>> + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {// >>> FIXME: subset >>> + SrcReg = AND->getOperand(0).getReg(); >>> + CmpValue = 0; >>> >>> CmpValue might not be 0 here. >> >> Whatever the mask is, the comparison is always against zero for the >> TSTri opcode. I hope I am not terribly mistaken with this statement >> :-) >> > The CmpValue here means the mask value in this case. The terminology is messing us up. > >>> >>> + return true; >>> + } >>> + } >>> >>> There's no need for this to be as complex here. The logic should be pretty >>> much identical to the CMP cases. In fact, I think it is identical when you >>> have a TST of an immediate. This logic should reside in >> >> I only attempt to cover the TSTri case. I do *not* think it is just as >> easy as "CMPri", because of the search for a suitable ANDri >> instruction that feeds from the same input >> and uses the same (super-) mask. Only in this case the "andS" will be >> equivalent. >> > But that logic should still reside in the OptimizeCompareInstr method. It will have to be modified some, but it's not complex. > >>> case ARM::SUBri: >>> case ARM::t2ADDri: >>> case ARM::t2SUBri: >>> >>> To do the optimization you suggest should be almost as easy as simply adding >>> the TST* cases to the switch statements and removing the "if (CmpValue != 0) >>> return false;" from OptimizeCompareInstr. :-) >> >> Are you talking about TSTrr and TSTrs here? >> > TST against the immediate. > > -bw > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Mon Sep 13 16:01:36 2010 From: dalej at apple.com (Dale Johannesen) Date: Mon, 13 Sep 2010 21:01:36 -0000 Subject: [llvm-commits] [llvm] r113783 - /llvm/trunk/test/Assembler/x86mmx.ll Message-ID: <20100913210136.614002A6C12C@llvm.org> Author: johannes Date: Mon Sep 13 16:01:36 2010 New Revision: 113783 URL: http://llvm.org/viewvc/llvm-project?rev=113783&view=rev Log: Basic smoke test for new x86mmx type. Added: llvm/trunk/test/Assembler/x86mmx.ll Added: llvm/trunk/test/Assembler/x86mmx.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/x86mmx.ll?rev=113783&view=auto ============================================================================== --- llvm/trunk/test/Assembler/x86mmx.ll (added) +++ llvm/trunk/test/Assembler/x86mmx.ll Mon Sep 13 16:01:36 2010 @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; Basic smoke test for x86_mmx type. + +; CHECK: define x86_mmx @sh16 +define x86_mmx @sh16(x86_mmx %A) { +; CHECK: ret x86_mmx %A + ret x86_mmx %A +} From grosser at fim.uni-passau.de Mon Sep 13 16:11:38 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 13 Sep 2010 23:11:38 +0200 Subject: [llvm-commits] [llvm] r113779 - /llvm/trunk/utils/test_debuginfo.pl In-Reply-To: <20100913204215.B069B2A6C12D@llvm.org> References: <20100913204215.B069B2A6C12D@llvm.org> Message-ID: <4C8E938A.2090007@fim.uni-passau.de> On 09/13/2010 10:42 PM, Devang Patel wrote: > Author: dpatel > Date: Mon Sep 13 15:42:15 2010 > New Revision: 113779 > > URL: http://llvm.org/viewvc/llvm-project?rev=113779&view=rev > Log: > Add little test script to check debug info. > > Added: > llvm/trunk/utils/test_debuginfo.pl (with props) > > Added: llvm/trunk/utils/test_debuginfo.pl > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/test_debuginfo.pl?rev=113779&view=auto > ============================================================================== > --- llvm/trunk/utils/test_debuginfo.pl (added) > +++ llvm/trunk/utils/test_debuginfo.pl Mon Sep 13 15:42:15 2010 > @@ -0,0 +1,61 @@ > +#!/usr/bin/perl > +# > +# This script tests debugging information generated by a compiler. > +# Input arguments > +# - Input source program. Usually this source file is decorated using > +# special comments to communicate debugger commands. > +# - Executable file. This file is generated by the compiler. > +# > +# This perl script extracts debugger commands from input source program > +# comments in a script. A debugger is used to load the executable file > +# and run the script generated from source program comments. Finally, > +# the debugger output is checked, using FileCheck, to validate > +# debugging information. > + > +use File::Basename; > + > +my $testcase_file = $ARGV[0]; > +my $executable_file = $ARGV[1]; > + > +my $input_filename = basename $testcase_file; > +my $output_dir = dirname $executable_file; > + > +my $debugger_script_file = "$output_dir/$input_filename.gdb.scirpt"; ^^^^^^ You ment "script"? Tobi From dalej at apple.com Mon Sep 13 16:15:43 2010 From: dalej at apple.com (Dale Johannesen) Date: Mon, 13 Sep 2010 21:15:43 -0000 Subject: [llvm-commits] [llvm] r113785 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20100913211544.89D702A6C12C@llvm.org> Author: johannes Date: Mon Sep 13 16:15:43 2010 New Revision: 113785 URL: http://llvm.org/viewvc/llvm-project?rev=113785&view=rev Log: Fix typos. 128-bit PSHUFB takes 128-bit memory op. v8i16 is not an MMX type; put it where it belongs. Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=113785&r1=113784&r2=113785&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Sep 13 16:15:43 2010 @@ -267,6 +267,7 @@ def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; +def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; // 256-bit memop pattern fragments @@ -285,7 +286,6 @@ def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>; def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>; -def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>; def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>; // MOVNT Support Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113785&r1=113784&r2=113785&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Sep 13 16:15:43 2010 @@ -3597,7 +3597,7 @@ int_x86_ssse3_phsub_sw_128>; defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8, int_x86_ssse3_pmadd_ub_sw_128>; - defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, + defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8, int_x86_ssse3_pshuf_b_128>; defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8, int_x86_ssse3_psign_b_128>; From gkistanova at gmail.com Mon Sep 13 16:18:45 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 13 Sep 2010 21:18:45 -0000 Subject: [llvm-commits] [zorg] r113786 - in /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py Message-ID: <20100913211845.3FB442A6C12C@llvm.org> Author: gkistanova Date: Mon Sep 13 16:18:44 2010 New Revision: 113786 URL: http://llvm.org/viewvc/llvm-project?rev=113786&view=rev Log: Added new slave and builder to build llvm-gcc on Windows 7 slave. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=113786&r1=113785&r2=113786&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Sep 13 16:18:44 2010 @@ -468,6 +468,44 @@ 'haltOnFailure' : True },]), 'category' : 'llvm-gcc' }, + {'name' : "llvm-gcc-native-mingw32-win7", + 'slavenames': [ "kistanova3" ], + 'builddir' : "llvm-gcc-native-mingw32", + 'factory' : ScriptedBuilder.getScriptedBuildFactory( + source_code = [SVN(name='svn-llvm', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/', + defaultBranch='trunk', + workdir="llvm.src"), + SVN(name='svn-llvm-gcc', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm-gcc-4.2/', + defaultBranch='trunk', + workdir="llvm-gcc.src"),], + launcher = 'llvm-gcc.src/extras/buildbot-launcher', + build_script = 'llvm-gcc.src/extras/build-native-mingw32', + extra_args = [], + build_steps = [{'name' : 'clean', + 'description' : 'clean', + 'haltOnFailure' : True }, + {'name' : 'copy_tools', + 'description' : 'copy tools', + 'haltOnFailure' : True }, + {'name' : 'configure_llvm', + 'description' : 'configure llvm', + 'haltOnFailure' : True }, + {'name' : 'make_llvm', + 'description' : 'make llvm', + 'haltOnFailure' : True }, + {'name' : 'configure_llvmgcc', + 'description' : 'configure llvm-gcc', + 'haltOnFailure' : True }, + {'name' : 'make_llvmgcc', + 'description' : 'make llvm-gcc', + 'haltOnFailure' : True }, + {'name' : 'install_llvmgcc', + 'description' : 'install llvm-gcc', + 'haltOnFailure' : True },]), + 'category' : 'llvm-gcc' }, + {'name' : "clang-i686-linux-selfhost-rel", 'slavenames' : ["osu8"], 'builddir' : "clang-i686-linux-selfhost-rel", Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=113786&r1=113785&r2=113786&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Mon Sep 13 16:18:44 2010 @@ -45,6 +45,9 @@ # Win XP SP3. create_slave("kistanova2", properties={'jobs' : 1}, max_builds=1), + # Windows 7 Ultimate. + create_slave("kistanova3", properties={'jobs' : 1}, max_builds=1), + # Quad Core x86_64, Solaris / AurorAUX create_slave("evocallaghan", properties={'jobs' : 4}, max_builds=1), From dpatel at apple.com Mon Sep 13 16:23:17 2010 From: dpatel at apple.com (Devang Patel) Date: Mon, 13 Sep 2010 21:23:17 -0000 Subject: [llvm-commits] [llvm] r113787 - /llvm/trunk/utils/test_debuginfo.pl Message-ID: <20100913212317.DDB212A6C12C@llvm.org> Author: dpatel Date: Mon Sep 13 16:23:17 2010 New Revision: 113787 URL: http://llvm.org/viewvc/llvm-project?rev=113787&view=rev Log: Fix typo in temp. script file name. Modified: llvm/trunk/utils/test_debuginfo.pl Modified: llvm/trunk/utils/test_debuginfo.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/test_debuginfo.pl?rev=113787&r1=113786&r2=113787&view=diff ============================================================================== --- llvm/trunk/utils/test_debuginfo.pl (original) +++ llvm/trunk/utils/test_debuginfo.pl Mon Sep 13 16:23:17 2010 @@ -20,7 +20,7 @@ my $input_filename = basename $testcase_file; my $output_dir = dirname $executable_file; -my $debugger_script_file = "$output_dir/$input_filename.gdb.scirpt"; +my $debugger_script_file = "$output_dir/$input_filename.debugger.script"; my $output_file = "$output_dir/$input_filename.gdb.output"; # Extract debugger commands from testcase. They are marked with DEBUGGER: From dpatel at apple.com Mon Sep 13 16:24:30 2010 From: dpatel at apple.com (Devang Patel) Date: Mon, 13 Sep 2010 14:24:30 -0700 Subject: [llvm-commits] [llvm] r113779 - /llvm/trunk/utils/test_debuginfo.pl In-Reply-To: <4C8E938A.2090007@fim.uni-passau.de> References: <20100913204215.B069B2A6C12D@llvm.org> <4C8E938A.2090007@fim.uni-passau.de> Message-ID: <8BC38924-59EB-42A1-B9E3-B52C39AC9031@apple.com> On Sep 13, 2010, at 2:11 PM, Tobias Grosser wrote: > On 09/13/2010 10:42 PM, Devang Patel wrote: >> +my $debugger_script_file = "$output_dir/$input_filename.gdb.scirpt"; > ^^^^^^ > You ment "script"? > yup. fixed. Thanks! - Devang > Tobi From stoklund at 2pi.dk Mon Sep 13 16:29:45 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 13 Sep 2010 21:29:45 -0000 Subject: [llvm-commits] [llvm] r113788 - /llvm/trunk/lib/CodeGen/SplitKit.cpp Message-ID: <20100913212945.4DAAE2A6C12C@llvm.org> Author: stoklund Date: Mon Sep 13 16:29:45 2010 New Revision: 113788 URL: http://llvm.org/viewvc/llvm-project?rev=113788&view=rev Log: Let's just declare that it is impossible to construct a std::pair from a null pointer and work around that. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=113788&r1=113787&r2=113788&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Sep 13 16:29:45 2010 @@ -339,6 +339,13 @@ // LiveIntervalMap //===----------------------------------------------------------------------===// +// Work around the fact that the std::pair constructors are broken for pointer +// pairs in some implementations. makeVV(x, 0) works. +static inline std::pair +makeVV(const VNInfo *a, VNInfo *b) { + return std::make_pair(a, b); +} + // defValue - Introduce a li_ def for ParentVNI that could be later than // ParentVNI->def. VNInfo *LiveIntervalMap::defValue(const VNInfo *ParentVNI, SlotIndex Idx) { @@ -351,19 +358,9 @@ return mapValue(ParentVNI, Idx); // This is a complex def. Mark with a NULL in valueMap. - VNInfo *OldVNI = - valueMap_.insert( - ValueMap::value_type(ParentVNI, static_cast(0))).first->second; - // The static_cast is only needed to work around a bug in an - // old version of the C++0x standard which the following compilers - // implemented and have yet to fix: - // - // Microsoft Visual Studio 2010 Version 10.0.30319.1 RTMRel - // Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 16.00.30319.01 - // - // If/When we move to C++0x, this can be replaced by nullptr. - (void)OldVNI; - assert(OldVNI == 0 && "Simple/Complex values mixed"); + VNInfo *&OldVNI = valueMap_[ParentVNI]; + assert(!OldVNI && "Simple/Complex values mixed"); + OldVNI = 0; // Should we insert a minimal snippet of VNI LiveRange, or can we count on // callers to do that? We need it for lookups of complex values. @@ -380,15 +377,7 @@ // Use insert for lookup, so we can add missing values with a second lookup. std::pair InsP = - valueMap_.insert(ValueMap::value_type(ParentVNI, static_cast(0))); - // The static_cast is only needed to work around a bug in an - // old version of the C++0x standard which the following compilers - // implemented and have yet to fix: - // - // Microsoft Visual Studio 2010 Version 10.0.30319.1 RTMRel - // Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 16.00.30319.01 - // - // If/When we move to C++0x, this can be replaced by nullptr. + valueMap_.insert(makeVV(ParentVNI, 0)); // This was an unknown value. Create a simple mapping. if (InsP.second) From gkistanova at gmail.com Mon Sep 13 16:41:11 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 13 Sep 2010 14:41:11 -0700 Subject: [llvm-commits] New slave requiest Message-ID: Hello Daniel, I would like to add new slave for llvm-gcc Windows 7with the same credentials. I added slave to slaves.py and builder to builders.py recently. Please have a look. Will really appreciate your assistance. Hope add it pretty soon. Thanks Galina. From espindola at google.com Mon Sep 13 16:59:01 2010 From: espindola at google.com (Rafael Espindola) Date: Mon, 13 Sep 2010 17:59:01 -0400 Subject: [llvm-commits] [patch] Fix handling of common symbols In-Reply-To: References: Message-ID: Roman found an issue with the previous patch that is fixed on this one: If there is no explicit .local directive, a .comm should produce a common symbol, even when the symbol is not first mentioned in a directive. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: common.patch Type: text/x-patch Size: 8156 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100913/3d557076/attachment.bin From aggarwa4 at illinois.edu Mon Sep 13 17:37:43 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Mon, 13 Sep 2010 22:37:43 -0000 Subject: [llvm-commits] [poolalloc] r113802 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100913223744.1C91B2A6C12C@llvm.org> Author: aggarwa4 Date: Mon Sep 13 17:37:43 2010 New Revision: 113802 URL: http://llvm.org/viewvc/llvm-project?rev=113802&view=rev Log: Remove call to OptimizePointerNotNull. This function breaks invalid C code behavior. Move to a separate optimization pass, instead of the pool allocation pass. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=113802&r1=113801&r2=113802&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Sep 13 17:37:43 2010 @@ -283,9 +283,13 @@ // code is trying to do (namely, avoid optimizations for performance // overhead measurements?). // + // FIXME: Breaks invalid C code. Remove from poolalloc and move to a separate pass. + + #if 0 if (CurHeuristic->IsRealHeuristic()) MicroOptimizePoolCalls(); - + #endif + delete CurHeuristic; return true; } From bob.wilson at apple.com Mon Sep 13 18:01:35 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 13 Sep 2010 23:01:35 -0000 Subject: [llvm-commits] [llvm] r113812 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp Message-ID: <20100913230135.E943D2A6C12C@llvm.org> Author: bwilson Date: Mon Sep 13 18:01:35 2010 New Revision: 113812 URL: http://llvm.org/viewvc/llvm-project?rev=113812&view=rev Log: Switch all the NEON vld-lane and vst-lane instructions over to the new pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table to record all the NEON load/store information. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113812&r1=113811&r2=113812&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Sep 13 18:01:35 2010 @@ -24,13 +24,6 @@ namespace { class ARMExpandPseudo : public MachineFunctionPass { - // Constants for register spacing in NEON load/store instructions. - enum NEONRegSpacing { - SingleSpc, - EvenDblSpc, - OddDblSpc - }; - public: static char ID; ARMExpandPseudo() : MachineFunctionPass(ID) {} @@ -48,10 +41,9 @@ void TransferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); bool ExpandMBB(MachineBasicBlock &MBB); - void ExpandVLD(MachineBasicBlock::iterator &MBBI, unsigned Opc, - bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs); - void ExpandVST(MachineBasicBlock::iterator &MBBI, unsigned Opc, - bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs); + void ExpandVLD(MachineBasicBlock::iterator &MBBI); + void ExpandVST(MachineBasicBlock::iterator &MBBI); + void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); }; char ARMExpandPseudo::ID = 0; } @@ -73,37 +65,289 @@ } } +namespace { + // Constants for register spacing in NEON load/store instructions. + // For quad-register load-lane and store-lane pseudo instructors, the + // spacing is initially assumed to be EvenDblSpc, and that is changed to + // OddDblSpc depending on the lane number operand. + enum NEONRegSpacing { + SingleSpc, + EvenDblSpc, + OddDblSpc + }; + + // Entries for NEON load/store information table. The table is sorted by + // PseudoOpc for fast binary-search lookups. + struct NEONLdStTableEntry { + unsigned PseudoOpc; + unsigned RealOpc; + bool IsLoad; + bool HasWriteBack; + NEONRegSpacing RegSpacing; + unsigned char NumRegs; // D registers loaded or stored + unsigned char RegElts; // elements per D register; used for lane ops + + // Comparison methods for binary search of the table. + bool operator<(const NEONLdStTableEntry &TE) const { + return PseudoOpc < TE.PseudoOpc; + } + friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { + return TE.PseudoOpc < PseudoOpc; + } + friend bool ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, + const NEONLdStTableEntry &TE) { + return PseudoOpc < TE.PseudoOpc; + } + }; +} + +static const NEONLdStTableEntry NEONLdStTable[] = { +{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, +{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, +{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, +{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 }, + +{ ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 }, +{ ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 }, +{ ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 }, +{ ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 }, +{ ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 }, +{ ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 }, +{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 }, +{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 }, + +{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 }, +{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 }, +{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 }, +{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 }, +{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 }, +{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 }, +{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 }, +{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 }, +{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 }, +{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 }, + +{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 }, +{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 }, +{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 }, +{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 }, +{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 }, +{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 }, + +{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 }, +{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 }, +{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 }, +{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 }, +{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 }, +{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 }, + +{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 }, +{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 }, +{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 }, +{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 }, +{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 }, +{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 }, +{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 }, +{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 }, +{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 }, +{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 }, + +{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 }, +{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 }, +{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 }, +{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 }, +{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 }, +{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 }, + +{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 }, +{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 }, +{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 }, +{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 }, +{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 }, +{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 }, + +{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 }, +{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 }, +{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 }, +{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 }, +{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 }, +{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 }, +{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 }, +{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 }, +{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 }, +{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 }, + +{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 }, +{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 }, +{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 }, +{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 }, +{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 }, +{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 }, + +{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 }, +{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 }, +{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 }, +{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 }, +{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, +{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, + +{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, +{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, +{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, +{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 }, + +{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 }, +{ ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 }, +{ ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 }, +{ ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 }, +{ ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 }, +{ ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 }, +{ ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 }, +{ ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 }, + +{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 }, +{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 }, +{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 }, +{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 }, +{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 }, +{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 }, +{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4}, +{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4}, +{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2}, +{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2}, + +{ ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 }, +{ ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 }, +{ ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 }, +{ ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 }, +{ ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 }, +{ ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 }, + +{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 }, +{ ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 }, +{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 }, +{ ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 }, +{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 }, +{ ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 }, + +{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 }, +{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 }, +{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 }, +{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 }, +{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 }, +{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 }, +{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4}, +{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4}, +{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2}, +{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2}, + +{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 }, +{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 }, +{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 }, +{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 }, +{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 }, +{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 }, + +{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 }, +{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 }, +{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 }, +{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 }, +{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 }, +{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 }, + +{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 }, +{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 }, +{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 }, +{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 }, +{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 }, +{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 }, +{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4}, +{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4}, +{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2}, +{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2}, + +{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 }, +{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 }, +{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 }, +{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 }, +{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 }, +{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 }, + +{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 }, +{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 }, +{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 }, +{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 }, +{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 }, +{ ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 } +}; + +/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON +/// load or store pseudo instruction. +static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { + unsigned NumEntries = array_lengthof(NEONLdStTable); + +#ifndef NDEBUG + // Make sure the table is sorted. + static bool TableChecked = false; + if (!TableChecked) { + for (unsigned i = 0; i != NumEntries-1; ++i) + assert(NEONLdStTable[i] < NEONLdStTable[i+1] && + "NEONLdStTable is not sorted!"); + TableChecked = true; + } +#endif + + const NEONLdStTableEntry *I = + std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); + if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) + return I; + return NULL; +} + +/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, +/// corresponding to the specified register spacing. Not all of the results +/// are necessarily valid, e.g., a Q register only has 2 D subregisters. +static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, + const TargetRegisterInfo *TRI, unsigned &D0, + unsigned &D1, unsigned &D2, unsigned &D3) { + if (RegSpc == SingleSpc) { + D0 = TRI->getSubReg(Reg, ARM::dsub_0); + D1 = TRI->getSubReg(Reg, ARM::dsub_1); + D2 = TRI->getSubReg(Reg, ARM::dsub_2); + D3 = TRI->getSubReg(Reg, ARM::dsub_3); + } else if (RegSpc == EvenDblSpc) { + D0 = TRI->getSubReg(Reg, ARM::dsub_0); + D1 = TRI->getSubReg(Reg, ARM::dsub_2); + D2 = TRI->getSubReg(Reg, ARM::dsub_4); + D3 = TRI->getSubReg(Reg, ARM::dsub_6); + } else { + assert(RegSpc == OddDblSpc && "unknown register spacing"); + D0 = TRI->getSubReg(Reg, ARM::dsub_1); + D1 = TRI->getSubReg(Reg, ARM::dsub_3); + D2 = TRI->getSubReg(Reg, ARM::dsub_5); + D3 = TRI->getSubReg(Reg, ARM::dsub_7); + } +} + /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register /// operands to real VLD instructions with D register operands. -void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI, - unsigned Opc, bool hasWriteBack, - NEONRegSpacing RegSpc, unsigned NumRegs) { +void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { MachineInstr &MI = *MBBI; MachineBasicBlock &MBB = *MI.getParent(); - MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); + const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); + assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); + NEONRegSpacing RegSpc = TableEntry->RegSpacing; + unsigned NumRegs = TableEntry->NumRegs; + + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(TableEntry->RealOpc)); unsigned OpIdx = 0; bool DstIsDead = MI.getOperand(OpIdx).isDead(); unsigned DstReg = MI.getOperand(OpIdx++).getReg(); unsigned D0, D1, D2, D3; - if (RegSpc == SingleSpc) { - D0 = TRI->getSubReg(DstReg, ARM::dsub_0); - D1 = TRI->getSubReg(DstReg, ARM::dsub_1); - D2 = TRI->getSubReg(DstReg, ARM::dsub_2); - D3 = TRI->getSubReg(DstReg, ARM::dsub_3); - } else if (RegSpc == EvenDblSpc) { - D0 = TRI->getSubReg(DstReg, ARM::dsub_0); - D1 = TRI->getSubReg(DstReg, ARM::dsub_2); - D2 = TRI->getSubReg(DstReg, ARM::dsub_4); - D3 = TRI->getSubReg(DstReg, ARM::dsub_6); - } else { - assert(RegSpc == OddDblSpc && "unknown register spacing for VLD"); - D0 = TRI->getSubReg(DstReg, ARM::dsub_1); - D1 = TRI->getSubReg(DstReg, ARM::dsub_3); - D2 = TRI->getSubReg(DstReg, ARM::dsub_5); - D3 = TRI->getSubReg(DstReg, ARM::dsub_7); - } + GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); if (NumRegs > 2) @@ -111,14 +355,14 @@ if (NumRegs > 3) MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); - if (hasWriteBack) + if (TableEntry->HasWriteBack) MIB.addOperand(MI.getOperand(OpIdx++)); // Copy the addrmode6 operands. MIB.addOperand(MI.getOperand(OpIdx++)); MIB.addOperand(MI.getOperand(OpIdx++)); // Copy the am6offset operand. - if (hasWriteBack) + if (TableEntry->HasWriteBack) MIB.addOperand(MI.getOperand(OpIdx++)); MIB = AddDefaultPred(MIB); @@ -138,45 +382,32 @@ /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register /// operands to real VST instructions with D register operands. -void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI, - unsigned Opc, bool hasWriteBack, - NEONRegSpacing RegSpc, unsigned NumRegs) { +void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { MachineInstr &MI = *MBBI; MachineBasicBlock &MBB = *MI.getParent(); - MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); + const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); + assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); + NEONRegSpacing RegSpc = TableEntry->RegSpacing; + unsigned NumRegs = TableEntry->NumRegs; + + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(TableEntry->RealOpc)); unsigned OpIdx = 0; - if (hasWriteBack) + if (TableEntry->HasWriteBack) MIB.addOperand(MI.getOperand(OpIdx++)); // Copy the addrmode6 operands. MIB.addOperand(MI.getOperand(OpIdx++)); MIB.addOperand(MI.getOperand(OpIdx++)); // Copy the am6offset operand. - if (hasWriteBack) + if (TableEntry->HasWriteBack) MIB.addOperand(MI.getOperand(OpIdx++)); bool SrcIsKill = MI.getOperand(OpIdx).isKill(); unsigned SrcReg = MI.getOperand(OpIdx).getReg(); unsigned D0, D1, D2, D3; - if (RegSpc == SingleSpc) { - D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); - D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); - D2 = TRI->getSubReg(SrcReg, ARM::dsub_2); - D3 = TRI->getSubReg(SrcReg, ARM::dsub_3); - } else if (RegSpc == EvenDblSpc) { - D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); - D1 = TRI->getSubReg(SrcReg, ARM::dsub_2); - D2 = TRI->getSubReg(SrcReg, ARM::dsub_4); - D3 = TRI->getSubReg(SrcReg, ARM::dsub_6); - } else { - assert(RegSpc == OddDblSpc && "unknown register spacing for VST"); - D0 = TRI->getSubReg(SrcReg, ARM::dsub_1); - D1 = TRI->getSubReg(SrcReg, ARM::dsub_3); - D2 = TRI->getSubReg(SrcReg, ARM::dsub_5); - D3 = TRI->getSubReg(SrcReg, ARM::dsub_7); - } - + GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); MIB.addReg(D0).addReg(D1); if (NumRegs > 2) MIB.addReg(D2); @@ -190,6 +421,85 @@ MI.eraseFromParent(); } +/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ +/// register operands to real instructions with D register operands. +void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { + MachineInstr &MI = *MBBI; + MachineBasicBlock &MBB = *MI.getParent(); + + const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); + assert(TableEntry && "NEONLdStTable lookup failed"); + NEONRegSpacing RegSpc = TableEntry->RegSpacing; + unsigned NumRegs = TableEntry->NumRegs; + unsigned RegElts = TableEntry->RegElts; + + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(TableEntry->RealOpc)); + unsigned OpIdx = 0; + // The lane operand is always the 3rd from last operand, before the 2 + // predicate operands. + unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); + + // Adjust the lane and spacing as needed for Q registers. + assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); + if (RegSpc == EvenDblSpc && Lane >= RegElts) { + RegSpc = OddDblSpc; + Lane -= RegElts; + } + assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); + + unsigned DstReg, D0, D1, D2, D3; + bool DstIsDead; + if (TableEntry->IsLoad) { + DstIsDead = MI.getOperand(OpIdx).isDead(); + DstReg = MI.getOperand(OpIdx++).getReg(); + GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) + .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); + if (NumRegs > 2) + MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); + if (NumRegs > 3) + MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); + } + + if (TableEntry->HasWriteBack) + MIB.addOperand(MI.getOperand(OpIdx++)); + + // Copy the addrmode6 operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the am6offset operand. + if (TableEntry->HasWriteBack) + MIB.addOperand(MI.getOperand(OpIdx++)); + + // Grab the super-register source. + MachineOperand MO = MI.getOperand(OpIdx++); + if (!TableEntry->IsLoad) + GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); + + // Add the subregs as sources of the new instruction. + unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | + getKillRegState(MO.isKill())); + MIB.addReg(D0, SrcFlags).addReg(D1, SrcFlags); + if (NumRegs > 2) + MIB.addReg(D2, SrcFlags); + if (NumRegs > 3) + MIB.addReg(D3, SrcFlags); + + // Add the lane number operand. + MIB.addImm(Lane); + + MIB = AddDefaultPred(MIB); + // Copy the super-register source to be an implicit source. + MO.setImplicit(true); + MIB.addOperand(MO); + if (TableEntry->IsLoad) + // Add an implicit def for the super-register. + MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); +} + bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { bool Modified = false; @@ -292,204 +602,169 @@ } case ARM::VLD1q8Pseudo: - ExpandVLD(MBBI, ARM::VLD1q8, false, SingleSpc, 2); break; case ARM::VLD1q16Pseudo: - ExpandVLD(MBBI, ARM::VLD1q16, false, SingleSpc, 2); break; case ARM::VLD1q32Pseudo: - ExpandVLD(MBBI, ARM::VLD1q32, false, SingleSpc, 2); break; case ARM::VLD1q64Pseudo: - ExpandVLD(MBBI, ARM::VLD1q64, false, SingleSpc, 2); break; case ARM::VLD1q8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1q8, true, SingleSpc, 2); break; case ARM::VLD1q16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1q16, true, SingleSpc, 2); break; case ARM::VLD1q32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1q32, true, SingleSpc, 2); break; case ARM::VLD1q64Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1q64, true, SingleSpc, 2); break; - case ARM::VLD2d8Pseudo: - ExpandVLD(MBBI, ARM::VLD2d8, false, SingleSpc, 2); break; case ARM::VLD2d16Pseudo: - ExpandVLD(MBBI, ARM::VLD2d16, false, SingleSpc, 2); break; case ARM::VLD2d32Pseudo: - ExpandVLD(MBBI, ARM::VLD2d32, false, SingleSpc, 2); break; case ARM::VLD2q8Pseudo: - ExpandVLD(MBBI, ARM::VLD2q8, false, SingleSpc, 4); break; case ARM::VLD2q16Pseudo: - ExpandVLD(MBBI, ARM::VLD2q16, false, SingleSpc, 4); break; case ARM::VLD2q32Pseudo: - ExpandVLD(MBBI, ARM::VLD2q32, false, SingleSpc, 4); break; case ARM::VLD2d8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD2d8, true, SingleSpc, 2); break; case ARM::VLD2d16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD2d16, true, SingleSpc, 2); break; case ARM::VLD2d32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD2d32, true, SingleSpc, 2); break; case ARM::VLD2q8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD2q8, true, SingleSpc, 4); break; case ARM::VLD2q16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD2q16, true, SingleSpc, 4); break; case ARM::VLD2q32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD2q32, true, SingleSpc, 4); break; - case ARM::VLD3d8Pseudo: - ExpandVLD(MBBI, ARM::VLD3d8, false, SingleSpc, 3); break; case ARM::VLD3d16Pseudo: - ExpandVLD(MBBI, ARM::VLD3d16, false, SingleSpc, 3); break; case ARM::VLD3d32Pseudo: - ExpandVLD(MBBI, ARM::VLD3d32, false, SingleSpc, 3); break; case ARM::VLD1d64TPseudo: - ExpandVLD(MBBI, ARM::VLD1d64T, false, SingleSpc, 3); break; case ARM::VLD3d8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3d8_UPD, true, SingleSpc, 3); break; case ARM::VLD3d16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3d16_UPD, true, SingleSpc, 3); break; case ARM::VLD3d32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3d32_UPD, true, SingleSpc, 3); break; case ARM::VLD1d64TPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1d64T_UPD, true, SingleSpc, 3); break; case ARM::VLD3q8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, EvenDblSpc, 3); break; case ARM::VLD3q16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, EvenDblSpc, 3); break; case ARM::VLD3q32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, EvenDblSpc, 3); break; case ARM::VLD3q8oddPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, OddDblSpc, 3); break; case ARM::VLD3q16oddPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, OddDblSpc, 3); break; case ARM::VLD3q32oddPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, OddDblSpc, 3); break; - case ARM::VLD4d8Pseudo: - ExpandVLD(MBBI, ARM::VLD4d8, false, SingleSpc, 4); break; case ARM::VLD4d16Pseudo: - ExpandVLD(MBBI, ARM::VLD4d16, false, SingleSpc, 4); break; case ARM::VLD4d32Pseudo: - ExpandVLD(MBBI, ARM::VLD4d32, false, SingleSpc, 4); break; case ARM::VLD1d64QPseudo: - ExpandVLD(MBBI, ARM::VLD1d64Q, false, SingleSpc, 4); break; case ARM::VLD4d8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4d8_UPD, true, SingleSpc, 4); break; case ARM::VLD4d16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4d16_UPD, true, SingleSpc, 4); break; case ARM::VLD4d32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4d32_UPD, true, SingleSpc, 4); break; case ARM::VLD1d64QPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1d64Q_UPD, true, SingleSpc, 4); break; case ARM::VLD4q8Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, EvenDblSpc, 4); break; case ARM::VLD4q16Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, EvenDblSpc, 4); break; case ARM::VLD4q32Pseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, EvenDblSpc, 4); break; case ARM::VLD4q8oddPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, OddDblSpc, 4); break; case ARM::VLD4q16oddPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, OddDblSpc, 4); break; case ARM::VLD4q32oddPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, OddDblSpc, 4); break; + ExpandVLD(MBBI); + break; case ARM::VST1q8Pseudo: - ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break; case ARM::VST1q16Pseudo: - ExpandVST(MBBI, ARM::VST1q16, false, SingleSpc, 2); break; case ARM::VST1q32Pseudo: - ExpandVST(MBBI, ARM::VST1q32, false, SingleSpc, 2); break; case ARM::VST1q64Pseudo: - ExpandVST(MBBI, ARM::VST1q64, false, SingleSpc, 2); break; case ARM::VST1q8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST1q8_UPD, true, SingleSpc, 2); break; case ARM::VST1q16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST1q16_UPD, true, SingleSpc, 2); break; case ARM::VST1q32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST1q32_UPD, true, SingleSpc, 2); break; case ARM::VST1q64Pseudo_UPD: - ExpandVST(MBBI, ARM::VST1q64_UPD, true, SingleSpc, 2); break; - case ARM::VST2d8Pseudo: - ExpandVST(MBBI, ARM::VST2d8, false, SingleSpc, 2); break; case ARM::VST2d16Pseudo: - ExpandVST(MBBI, ARM::VST2d16, false, SingleSpc, 2); break; case ARM::VST2d32Pseudo: - ExpandVST(MBBI, ARM::VST2d32, false, SingleSpc, 2); break; case ARM::VST2q8Pseudo: - ExpandVST(MBBI, ARM::VST2q8, false, SingleSpc, 4); break; case ARM::VST2q16Pseudo: - ExpandVST(MBBI, ARM::VST2q16, false, SingleSpc, 4); break; case ARM::VST2q32Pseudo: - ExpandVST(MBBI, ARM::VST2q32, false, SingleSpc, 4); break; case ARM::VST2d8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST2d8_UPD, true, SingleSpc, 2); break; case ARM::VST2d16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST2d16_UPD, true, SingleSpc, 2); break; case ARM::VST2d32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST2d32_UPD, true, SingleSpc, 2); break; case ARM::VST2q8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST2q8_UPD, true, SingleSpc, 4); break; case ARM::VST2q16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST2q16_UPD, true, SingleSpc, 4); break; case ARM::VST2q32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST2q32_UPD, true, SingleSpc, 4); break; - case ARM::VST3d8Pseudo: - ExpandVST(MBBI, ARM::VST3d8, false, SingleSpc, 3); break; case ARM::VST3d16Pseudo: - ExpandVST(MBBI, ARM::VST3d16, false, SingleSpc, 3); break; case ARM::VST3d32Pseudo: - ExpandVST(MBBI, ARM::VST3d32, false, SingleSpc, 3); break; case ARM::VST1d64TPseudo: - ExpandVST(MBBI, ARM::VST1d64T, false, SingleSpc, 3); break; case ARM::VST3d8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST3d8_UPD, true, SingleSpc, 3); break; case ARM::VST3d16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST3d16_UPD, true, SingleSpc, 3); break; case ARM::VST3d32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST3d32_UPD, true, SingleSpc, 3); break; case ARM::VST1d64TPseudo_UPD: - ExpandVST(MBBI, ARM::VST1d64T_UPD, true, SingleSpc, 3); break; case ARM::VST3q8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST3q8_UPD, true, EvenDblSpc, 3); break; case ARM::VST3q16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST3q16_UPD, true, EvenDblSpc, 3); break; case ARM::VST3q32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST3q32_UPD, true, EvenDblSpc, 3); break; case ARM::VST3q8oddPseudo_UPD: - ExpandVST(MBBI, ARM::VST3q8_UPD, true, OddDblSpc, 3); break; case ARM::VST3q16oddPseudo_UPD: - ExpandVST(MBBI, ARM::VST3q16_UPD, true, OddDblSpc, 3); break; case ARM::VST3q32oddPseudo_UPD: - ExpandVST(MBBI, ARM::VST3q32_UPD, true, OddDblSpc, 3); break; - case ARM::VST4d8Pseudo: - ExpandVST(MBBI, ARM::VST4d8, false, SingleSpc, 4); break; case ARM::VST4d16Pseudo: - ExpandVST(MBBI, ARM::VST4d16, false, SingleSpc, 4); break; case ARM::VST4d32Pseudo: - ExpandVST(MBBI, ARM::VST4d32, false, SingleSpc, 4); break; case ARM::VST1d64QPseudo: - ExpandVST(MBBI, ARM::VST1d64Q, false, SingleSpc, 4); break; case ARM::VST4d8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST4d8_UPD, true, SingleSpc, 4); break; case ARM::VST4d16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST4d16_UPD, true, SingleSpc, 4); break; case ARM::VST4d32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST4d32_UPD, true, SingleSpc, 4); break; case ARM::VST1d64QPseudo_UPD: - ExpandVST(MBBI, ARM::VST1d64Q_UPD, true, SingleSpc, 4); break; case ARM::VST4q8Pseudo_UPD: - ExpandVST(MBBI, ARM::VST4q8_UPD, true, EvenDblSpc, 4); break; case ARM::VST4q16Pseudo_UPD: - ExpandVST(MBBI, ARM::VST4q16_UPD, true, EvenDblSpc, 4); break; case ARM::VST4q32Pseudo_UPD: - ExpandVST(MBBI, ARM::VST4q32_UPD, true, EvenDblSpc, 4); break; case ARM::VST4q8oddPseudo_UPD: - ExpandVST(MBBI, ARM::VST4q8_UPD, true, OddDblSpc, 4); break; case ARM::VST4q16oddPseudo_UPD: - ExpandVST(MBBI, ARM::VST4q16_UPD, true, OddDblSpc, 4); break; case ARM::VST4q32oddPseudo_UPD: - ExpandVST(MBBI, ARM::VST4q32_UPD, true, OddDblSpc, 4); break; + ExpandVST(MBBI); + break; + + case ARM::VLD2LNd8Pseudo: + case ARM::VLD2LNd16Pseudo: + case ARM::VLD2LNd32Pseudo: + case ARM::VLD2LNq16Pseudo: + case ARM::VLD2LNq32Pseudo: + case ARM::VLD2LNd8Pseudo_UPD: + case ARM::VLD2LNd16Pseudo_UPD: + case ARM::VLD2LNd32Pseudo_UPD: + case ARM::VLD2LNq16Pseudo_UPD: + case ARM::VLD2LNq32Pseudo_UPD: + case ARM::VLD3LNd8Pseudo: + case ARM::VLD3LNd16Pseudo: + case ARM::VLD3LNd32Pseudo: + case ARM::VLD3LNq16Pseudo: + case ARM::VLD3LNq32Pseudo: + case ARM::VLD3LNd8Pseudo_UPD: + case ARM::VLD3LNd16Pseudo_UPD: + case ARM::VLD3LNd32Pseudo_UPD: + case ARM::VLD3LNq16Pseudo_UPD: + case ARM::VLD3LNq32Pseudo_UPD: + case ARM::VLD4LNd8Pseudo: + case ARM::VLD4LNd16Pseudo: + case ARM::VLD4LNd32Pseudo: + case ARM::VLD4LNq16Pseudo: + case ARM::VLD4LNq32Pseudo: + case ARM::VLD4LNd8Pseudo_UPD: + case ARM::VLD4LNd16Pseudo_UPD: + case ARM::VLD4LNd32Pseudo_UPD: + case ARM::VLD4LNq16Pseudo_UPD: + case ARM::VLD4LNq32Pseudo_UPD: + case ARM::VST2LNd8Pseudo: + case ARM::VST2LNd16Pseudo: + case ARM::VST2LNd32Pseudo: + case ARM::VST2LNq16Pseudo: + case ARM::VST2LNq32Pseudo: + case ARM::VST2LNd8Pseudo_UPD: + case ARM::VST2LNd16Pseudo_UPD: + case ARM::VST2LNd32Pseudo_UPD: + case ARM::VST2LNq16Pseudo_UPD: + case ARM::VST2LNq32Pseudo_UPD: + case ARM::VST3LNd8Pseudo: + case ARM::VST3LNd16Pseudo: + case ARM::VST3LNd32Pseudo: + case ARM::VST3LNq16Pseudo: + case ARM::VST3LNq32Pseudo: + case ARM::VST3LNd8Pseudo_UPD: + case ARM::VST3LNd16Pseudo_UPD: + case ARM::VST3LNd32Pseudo_UPD: + case ARM::VST3LNq16Pseudo_UPD: + case ARM::VST3LNq32Pseudo_UPD: + case ARM::VST4LNd8Pseudo: + case ARM::VST4LNd16Pseudo: + case ARM::VST4LNd32Pseudo: + case ARM::VST4LNq16Pseudo: + case ARM::VST4LNq32Pseudo: + case ARM::VST4LNd8Pseudo_UPD: + case ARM::VST4LNd16Pseudo_UPD: + case ARM::VST4LNd32Pseudo_UPD: + case ARM::VST4LNq16Pseudo_UPD: + case ARM::VST4LNq32Pseudo_UPD: + ExpandLaneOp(MBBI); + break; } if (ModifiedOp) Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=113812&r1=113811&r2=113812&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Sep 13 18:01:35 2010 @@ -151,10 +151,9 @@ /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should /// be 2, 3 or 4. The opcode arrays specify the instructions used for - /// load/store of D registers and even subregs and odd subregs of Q registers. + /// load/store of D registers and Q registers. SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs, - unsigned *DOpcodes, unsigned *QOpcodes0, - unsigned *QOpcodes1); + unsigned *DOpcodes, unsigned *QOpcodes); /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2, /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be @@ -196,10 +195,6 @@ SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); - - // Form sequences of 8 consecutive D registers. - SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3, - SDValue V4, SDValue V5, SDValue V6, SDValue V7); }; } @@ -1015,39 +1010,6 @@ return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); } -/// OctoDRegs - Form 8 consecutive D registers. -/// -SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1, - SDValue V2, SDValue V3, - SDValue V4, SDValue V5, - SDValue V6, SDValue V7) { - DebugLoc dl = V0.getNode()->getDebugLoc(); - SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); - SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); - SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); - SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); - SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32); - SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32); - SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32); - SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32); - const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3, - V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 }; - return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16); -} - -/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type -/// for a 64-bit subregister of the vector. -static EVT GetNEONSubregVT(EVT VT) { - switch (VT.getSimpleVT().SimpleTy) { - default: llvm_unreachable("unhandled NEON type"); - case MVT::v16i8: return MVT::v8i8; - case MVT::v8i16: return MVT::v4i16; - case MVT::v4f32: return MVT::v2f32; - case MVT::v4i32: return MVT::v2i32; - case MVT::v2i64: return MVT::v1i64; - } -} - SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, unsigned *QOpcodes0, unsigned *QOpcodes1) { @@ -1281,8 +1243,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs, unsigned *DOpcodes, - unsigned *QOpcodes0, - unsigned *QOpcodes1) { + unsigned *QOpcodes) { assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range"); DebugLoc dl = N->getDebugLoc(); @@ -1296,16 +1257,6 @@ EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType(); bool is64BitVector = VT.is64BitVector(); - // Quad registers are handled by load/store of subregs. Find the subreg info. - unsigned NumElts = 0; - bool Even = false; - EVT RegVT = VT; - if (!is64BitVector) { - RegVT = GetNEONSubregVT(VT); - NumElts = RegVT.getVectorNumElements(); - Even = Lane < NumElts; - } - unsigned OpcodeIndex; switch (VT.getSimpleVT().SimpleTy) { default: llvm_unreachable("unhandled vld/vst lane type"); @@ -1323,121 +1274,59 @@ SDValue Pred = getAL(CurDAG); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); - SmallVector Ops; + SmallVector Ops; Ops.push_back(MemAddr); Ops.push_back(Align); - unsigned Opc = 0; - if (is64BitVector) { - Opc = DOpcodes[OpcodeIndex]; - SDValue RegSeq; - SDValue V0 = N->getOperand(0+3); - SDValue V1 = N->getOperand(1+3); - if (NumVecs == 2) { - RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); - } else { - SDValue V2 = N->getOperand(2+3); - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : N->getOperand(3+3); - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); - } + unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : + Opc = QOpcodes[OpcodeIndex]); - // Now extract the D registers back out. - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); - if (NumVecs > 2) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq)); - if (NumVecs > 3) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq)); + SDValue SuperReg; + SDValue V0 = N->getOperand(0+3); + SDValue V1 = N->getOperand(1+3); + if (NumVecs == 2) { + if (is64BitVector) + SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); + else + SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); } else { - // Check if this is loading the even or odd subreg of a Q register. - if (Lane < NumElts) { - Opc = QOpcodes0[OpcodeIndex]; - } else { - Lane -= NumElts; - Opc = QOpcodes1[OpcodeIndex]; - } - - SDValue RegSeq; - SDValue V0 = N->getOperand(0+3); - SDValue V1 = N->getOperand(1+3); - if (NumVecs == 2) { - RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); - } else { - SDValue V2 = N->getOperand(2+3); - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : N->getOperand(3+3); - RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); - } - - // Extract the subregs of the input vector. - unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1; - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT, - RegSeq)); + SDValue V2 = N->getOperand(2+3); + SDValue V3 = (NumVecs == 3) + ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) + : N->getOperand(3+3); + if (is64BitVector) + SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); + else + SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); } + Ops.push_back(SuperReg); Ops.push_back(getI32Imm(Lane)); Ops.push_back(Pred); Ops.push_back(Reg0); Ops.push_back(Chain); if (!IsLoad) - return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6); - - std::vector ResTys(NumVecs, RegVT); - ResTys.push_back(MVT::Other); - SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6); + return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7); - // Form a REG_SEQUENCE to force register allocation. - SDValue RegSeq; - if (is64BitVector) { - SDValue V0 = SDValue(VLdLn, 0); - SDValue V1 = SDValue(VLdLn, 1); - if (NumVecs == 2) { - RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); - } else { - SDValue V2 = SDValue(VLdLn, 2); - // If it's a vld3, form a quad D-register but discard the last part. - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : SDValue(VLdLn, 3); - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); - } - } else { - // For 128-bit vectors, take the 64-bit results of the load and insert - // them as subregs into the result. - SDValue V[8]; - for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { - if (Even) { - V[i] = SDValue(VLdLn, Vec); - V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - } else { - V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - V[i+1] = SDValue(VLdLn, Vec); - } - } - if (NumVecs == 3) - V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - - if (NumVecs == 2) - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0); - else - RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], - V[4], V[5], V[6], V[7]), 0); - } + EVT ResTy; + unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; + if (!is64BitVector) + ResTyElts *= 2; + ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts); + + SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, + Ops.data(), 7); + SuperReg = SDValue(VLdLn, 0); + Chain = SDValue(VLdLn, 1); + // Extract the subregisters. assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; for (unsigned Vec = 0; Vec < NumVecs; ++Vec) ReplaceUses(SDValue(N, Vec), - CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq)); - ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs)); + CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); + ReplaceUses(SDValue(N, NumVecs), Chain); return NULL; } @@ -2119,24 +2008,24 @@ } case Intrinsic::arm_neon_vld2lane: { - unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 }; - unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 }; - unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd }; - return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1); + unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo, + ARM::VLD2LNd32Pseudo }; + unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo }; + return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes); } case Intrinsic::arm_neon_vld3lane: { - unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 }; - unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 }; - unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd }; - return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); + unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo, + ARM::VLD3LNd32Pseudo }; + unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo }; + return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes); } case Intrinsic::arm_neon_vld4lane: { - unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 }; - unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 }; - unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd }; - return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); + unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo, + ARM::VLD4LNd32Pseudo }; + unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo }; + return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes); } case Intrinsic::arm_neon_vst1: { @@ -2180,24 +2069,24 @@ } case Intrinsic::arm_neon_vst2lane: { - unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 }; - unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 }; - unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd }; - return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1); + unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo, + ARM::VST2LNd32Pseudo }; + unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo }; + return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes); } case Intrinsic::arm_neon_vst3lane: { - unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 }; - unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 }; - unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd }; - return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1); + unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo, + ARM::VST3LNd32Pseudo }; + unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo }; + return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes); } case Intrinsic::arm_neon_vst4lane: { - unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 }; - unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 }; - unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd }; - return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1); + unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo, + ARM::VST4LNd32Pseudo }; + unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo }; + return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes); } } break; Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113812&r1=113811&r2=113812&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Sep 13 18:01:35 2010 @@ -445,6 +445,33 @@ def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo; def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo; +// Classes for VLD*LN pseudo-instructions with multi-register operands. +// These are expanded to real instructions after register allocation. +class VLDQLNPseudo + : PseudoNLdSt<(outs QPR:$dst), + (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), + itin, "$src = $dst">; +class VLDQLNWBPseudo + : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QPR:$src, + nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; +class VLDQQLNPseudo + : PseudoNLdSt<(outs QQPR:$dst), + (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), + itin, "$src = $dst">; +class VLDQQLNWBPseudo + : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, + nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; +class VLDQQQQLNPseudo + : PseudoNLdSt<(outs QQQQPR:$dst), + (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), + itin, "$src = $dst">; +class VLDQQQQLNWBPseudo + : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, + nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; + // VLD1LN : Vector Load (single element to one lane) // FIXME: Not yet implemented. @@ -459,13 +486,16 @@ def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">; def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">; +def VLD2LNd8Pseudo : VLDQLNPseudo; +def VLD2LNd16Pseudo : VLDQLNPseudo; +def VLD2LNd32Pseudo : VLDQLNPseudo; + // ...with double-spaced registers: def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">; def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">; -// ...alternate versions to be allocated odd register numbers: -def VLD2LNq16odd : VLD2LN<0b0101, {?,?,1,?}, "16">; -def VLD2LNq32odd : VLD2LN<0b1001, {?,1,?,?}, "32">; +def VLD2LNq16Pseudo : VLDQQLNPseudo; +def VLD2LNq32Pseudo : VLDQQLNPseudo; // ...with address register writeback: class VLD2LNWB op11_8, bits<4> op7_4, string Dt> @@ -479,9 +509,16 @@ def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">; def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">; +def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo; +def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo; +def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo; + def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">; def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">; +def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo; +def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo; + // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), @@ -494,13 +531,16 @@ def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">; def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">; +def VLD3LNd8Pseudo : VLDQQLNPseudo; +def VLD3LNd16Pseudo : VLDQQLNPseudo; +def VLD3LNd32Pseudo : VLDQQLNPseudo; + // ...with double-spaced registers: def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">; def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">; -// ...alternate versions to be allocated odd register numbers: -def VLD3LNq16odd : VLD3LN<0b0110, {?,?,1,0}, "16">; -def VLD3LNq32odd : VLD3LN<0b1010, {?,1,0,0}, "32">; +def VLD3LNq16Pseudo : VLDQQQQLNPseudo; +def VLD3LNq32Pseudo : VLDQQQQLNPseudo; // ...with address register writeback: class VLD3LNWB op11_8, bits<4> op7_4, string Dt> @@ -517,9 +557,16 @@ def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">; def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">; +def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo; +def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo; +def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo; + def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">; def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">; +def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo; +def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo; + // VLD4LN : Vector Load (single 4-element structure to one lane) class VLD4LN op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, @@ -533,13 +580,16 @@ def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">; def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">; +def VLD4LNd8Pseudo : VLDQQLNPseudo; +def VLD4LNd16Pseudo : VLDQQLNPseudo; +def VLD4LNd32Pseudo : VLDQQLNPseudo; + // ...with double-spaced registers: def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">; def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">; -// ...alternate versions to be allocated odd register numbers: -def VLD4LNq16odd : VLD4LN<0b0111, {?,?,1,?}, "16">; -def VLD4LNq32odd : VLD4LN<0b1011, {?,1,?,?}, "32">; +def VLD4LNq16Pseudo : VLDQQQQLNPseudo; +def VLD4LNq32Pseudo : VLDQQQQLNPseudo; // ...with address register writeback: class VLD4LNWB op11_8, bits<4> op7_4, string Dt> @@ -556,9 +606,16 @@ def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">; def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">; +def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo; +def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo; +def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo; + def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">; def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">; +def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo; +def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo; + // VLD1DUP : Vector Load (single element to all lanes) // VLD2DUP : Vector Load (single 2-element structure to all lanes) // VLD3DUP : Vector Load (single 3-element structure to all lanes) @@ -846,6 +903,30 @@ def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo; def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo; +// Classes for VST*LN pseudo-instructions with multi-register operands. +// These are expanded to real instructions after register allocation. +class VSTQLNPseudo + : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), + itin, "">; +class VSTQLNWBPseudo + : PseudoNLdSt<(outs GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QPR:$src, + nohash_imm:$lane), itin, "$addr.addr = $wb">; +class VSTQQLNPseudo + : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), + itin, "">; +class VSTQQLNWBPseudo + : PseudoNLdSt<(outs GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, + nohash_imm:$lane), itin, "$addr.addr = $wb">; +class VSTQQQQLNPseudo + : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), + itin, "">; +class VSTQQQQLNWBPseudo + : PseudoNLdSt<(outs GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, + nohash_imm:$lane), itin, "$addr.addr = $wb">; + // VST1LN : Vector Store (single element from one lane) // FIXME: Not yet implemented. @@ -860,13 +941,16 @@ def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">; def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">; +def VST2LNd8Pseudo : VSTQLNPseudo; +def VST2LNd16Pseudo : VSTQLNPseudo; +def VST2LNd32Pseudo : VSTQLNPseudo; + // ...with double-spaced registers: def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">; def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">; -// ...alternate versions to be allocated odd register numbers: -def VST2LNq16odd : VST2LN<0b0101, {?,?,1,?}, "16">; -def VST2LNq32odd : VST2LN<0b1001, {?,1,?,?}, "32">; +def VST2LNq16Pseudo : VSTQQLNPseudo; +def VST2LNq32Pseudo : VSTQQLNPseudo; // ...with address register writeback: class VST2LNWB op11_8, bits<4> op7_4, string Dt> @@ -880,9 +964,16 @@ def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">; def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">; +def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo; +def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo; +def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo; + def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">; def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">; +def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo; +def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo; + // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b00, op11_8, op7_4, (outs), @@ -894,13 +985,16 @@ def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">; def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">; +def VST3LNd8Pseudo : VSTQQLNPseudo; +def VST3LNd16Pseudo : VSTQQLNPseudo; +def VST3LNd32Pseudo : VSTQQLNPseudo; + // ...with double-spaced registers: def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">; def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">; -// ...alternate versions to be allocated odd register numbers: -def VST3LNq16odd : VST3LN<0b0110, {?,?,1,0}, "16">; -def VST3LNq32odd : VST3LN<0b1010, {?,1,0,0}, "32">; +def VST3LNq16Pseudo : VSTQQQQLNPseudo; +def VST3LNq32Pseudo : VSTQQQQLNPseudo; // ...with address register writeback: class VST3LNWB op11_8, bits<4> op7_4, string Dt> @@ -915,9 +1009,16 @@ def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">; def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">; +def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo; +def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo; +def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo; + def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">; def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">; +def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo; +def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo; + // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b00, op11_8, op7_4, (outs), @@ -930,13 +1031,16 @@ def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">; def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">; +def VST4LNd8Pseudo : VSTQQLNPseudo; +def VST4LNd16Pseudo : VSTQQLNPseudo; +def VST4LNd32Pseudo : VSTQQLNPseudo; + // ...with double-spaced registers: def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">; def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">; -// ...alternate versions to be allocated odd register numbers: -def VST4LNq16odd : VST4LN<0b0111, {?,?,1,?}, "16">; -def VST4LNq32odd : VST4LN<0b1011, {?,1,?,?}, "32">; +def VST4LNq16Pseudo : VSTQQQQLNPseudo; +def VST4LNq32Pseudo : VSTQQQQLNPseudo; // ...with address register writeback: class VST4LNWB op11_8, bits<4> op7_4, string Dt> @@ -951,9 +1055,16 @@ def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">; def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">; +def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo; +def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo; +def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo; + def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">; def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">; +def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo; +def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo; + } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=113812&r1=113811&r2=113812&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Mon Sep 13 18:01:35 2010 @@ -51,144 +51,6 @@ default: break; - case ARM::VLD2LNd8: - case ARM::VLD2LNd16: - case ARM::VLD2LNd32: - FirstOpnd = 0; - NumRegs = 2; - return true; - - case ARM::VLD2LNq16: - case ARM::VLD2LNq32: - FirstOpnd = 0; - NumRegs = 2; - Offset = 0; - Stride = 2; - return true; - - case ARM::VLD2LNq16odd: - case ARM::VLD2LNq32odd: - FirstOpnd = 0; - NumRegs = 2; - Offset = 1; - Stride = 2; - return true; - - case ARM::VLD3LNd8: - case ARM::VLD3LNd16: - case ARM::VLD3LNd32: - FirstOpnd = 0; - NumRegs = 3; - return true; - - case ARM::VLD3LNq16: - case ARM::VLD3LNq32: - FirstOpnd = 0; - NumRegs = 3; - Offset = 0; - Stride = 2; - return true; - - case ARM::VLD3LNq16odd: - case ARM::VLD3LNq32odd: - FirstOpnd = 0; - NumRegs = 3; - Offset = 1; - Stride = 2; - return true; - - case ARM::VLD4LNd8: - case ARM::VLD4LNd16: - case ARM::VLD4LNd32: - FirstOpnd = 0; - NumRegs = 4; - return true; - - case ARM::VLD4LNq16: - case ARM::VLD4LNq32: - FirstOpnd = 0; - NumRegs = 4; - Offset = 0; - Stride = 2; - return true; - - case ARM::VLD4LNq16odd: - case ARM::VLD4LNq32odd: - FirstOpnd = 0; - NumRegs = 4; - Offset = 1; - Stride = 2; - return true; - - case ARM::VST2LNd8: - case ARM::VST2LNd16: - case ARM::VST2LNd32: - FirstOpnd = 2; - NumRegs = 2; - return true; - - case ARM::VST2LNq16: - case ARM::VST2LNq32: - FirstOpnd = 2; - NumRegs = 2; - Offset = 0; - Stride = 2; - return true; - - case ARM::VST2LNq16odd: - case ARM::VST2LNq32odd: - FirstOpnd = 2; - NumRegs = 2; - Offset = 1; - Stride = 2; - return true; - - case ARM::VST3LNd8: - case ARM::VST3LNd16: - case ARM::VST3LNd32: - FirstOpnd = 2; - NumRegs = 3; - return true; - - case ARM::VST3LNq16: - case ARM::VST3LNq32: - FirstOpnd = 2; - NumRegs = 3; - Offset = 0; - Stride = 2; - return true; - - case ARM::VST3LNq16odd: - case ARM::VST3LNq32odd: - FirstOpnd = 2; - NumRegs = 3; - Offset = 1; - Stride = 2; - return true; - - case ARM::VST4LNd8: - case ARM::VST4LNd16: - case ARM::VST4LNd32: - FirstOpnd = 2; - NumRegs = 4; - return true; - - case ARM::VST4LNq16: - case ARM::VST4LNq32: - FirstOpnd = 2; - NumRegs = 4; - Offset = 0; - Stride = 2; - return true; - - case ARM::VST4LNq16odd: - case ARM::VST4LNq32odd: - FirstOpnd = 2; - NumRegs = 4; - Offset = 1; - Stride = 2; - return true; - case ARM::VTBL2: FirstOpnd = 1; NumRegs = 2; From stoklund at 2pi.dk Mon Sep 13 18:29:09 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 13 Sep 2010 23:29:09 -0000 Subject: [llvm-commits] [llvm] r113815 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h Message-ID: <20100913232909.76C1F2A6C12C@llvm.org> Author: stoklund Date: Mon Sep 13 18:29:09 2010 New Revision: 113815 URL: http://llvm.org/viewvc/llvm-project?rev=113815&view=rev Log: Allow LiveIntervalMap to be reused by resetting the current live interval. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=113815&r1=113814&r2=113815&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Sep 13 18:29:09 2010 @@ -346,9 +346,15 @@ return std::make_pair(a, b); } +void LiveIntervalMap::reset(LiveInterval *li) { + li_ = li; + valueMap_.clear(); +} + // defValue - Introduce a li_ def for ParentVNI that could be later than // ParentVNI->def. VNInfo *LiveIntervalMap::defValue(const VNInfo *ParentVNI, SlotIndex Idx) { + assert(li_ && "call reset first"); assert(ParentVNI && "Mapping NULL value"); assert(Idx.isValid() && "Invalid SlotIndex"); assert(parentli_.getVNInfoAt(Idx) == ParentVNI && "Bad ParentVNI"); @@ -364,13 +370,14 @@ // Should we insert a minimal snippet of VNI LiveRange, or can we count on // callers to do that? We need it for lookups of complex values. - VNInfo *VNI = li_.getNextValue(Idx, 0, true, lis_.getVNInfoAllocator()); + VNInfo *VNI = li_->getNextValue(Idx, 0, true, lis_.getVNInfoAllocator()); return VNI; } // mapValue - Find the mapped value for ParentVNI at Idx. // Potentially create phi-def values. VNInfo *LiveIntervalMap::mapValue(const VNInfo *ParentVNI, SlotIndex Idx) { + assert(li_ && "call reset first"); assert(ParentVNI && "Mapping NULL value"); assert(Idx.isValid() && "Invalid SlotIndex"); assert(parentli_.getVNInfoAt(Idx) == ParentVNI && "Bad ParentVNI"); @@ -381,8 +388,8 @@ // This was an unknown value. Create a simple mapping. if (InsP.second) - return InsP.first->second = li_.createValueCopy(ParentVNI, - lis_.getVNInfoAllocator()); + return InsP.first->second = li_->createValueCopy(ParentVNI, + lis_.getVNInfoAllocator()); // This was a simple mapped value. if (InsP.first->second) return InsP.first->second; @@ -449,7 +456,7 @@ // We have a collision between the old and new VNI at Succ. That means // neither dominates and we need a new phi-def. - VNI = li_.getNextValue(Start, 0, true, lis_.getVNInfoAllocator()); + VNI = li_->getNextValue(Start, 0, true, lis_.getVNInfoAllocator()); VNI->setIsPHIDef(true); InsP.first->second = VNI; @@ -482,11 +489,11 @@ if (MBB == IdxMBB) { // Don't add full liveness to IdxMBB, stop at Idx. if (Start != Idx) - li_.addRange(LiveRange(Start, Idx, VNI)); + li_->addRange(LiveRange(Start, Idx, VNI)); // The caller had better add some liveness to IdxVNI, or it leaks. IdxVNI = VNI; } else - li_.addRange(LiveRange(Start, lis_.getMBBEndIdx(MBB), VNI)); + li_->addRange(LiveRange(Start, lis_.getMBBEndIdx(MBB), VNI)); } assert(IdxVNI && "Didn't find value for Idx"); @@ -497,8 +504,9 @@ // parentli_ is assumed to be live at Idx. Extend the live range to Idx. // Return the found VNInfo, or NULL. VNInfo *LiveIntervalMap::extendTo(MachineBasicBlock *MBB, SlotIndex Idx) { - LiveInterval::iterator I = std::upper_bound(li_.begin(), li_.end(), Idx); - if (I == li_.begin()) + assert(li_ && "call reset first"); + LiveInterval::iterator I = std::upper_bound(li_->begin(), li_->end(), Idx); + if (I == li_->begin()) return 0; --I; if (I->start < lis_.getMBBStartIdx(MBB)) @@ -512,10 +520,11 @@ // ParentVNI must be live in the [Start;End) interval. void LiveIntervalMap::addSimpleRange(SlotIndex Start, SlotIndex End, const VNInfo *ParentVNI) { + assert(li_ && "call reset first"); VNInfo *VNI = mapValue(ParentVNI, Start); // A simple mappoing is easy. if (VNI->def == ParentVNI->def) { - li_.addRange(LiveRange(Start, End, VNI)); + li_->addRange(LiveRange(Start, End, VNI)); return; } @@ -524,30 +533,31 @@ MachineFunction::iterator MBBE = lis_.getMBBFromIndex(End); if (MBB == MBBE) { - li_.addRange(LiveRange(Start, End, VNI)); + li_->addRange(LiveRange(Start, End, VNI)); return; } // First block. - li_.addRange(LiveRange(Start, lis_.getMBBEndIdx(MBB), VNI)); + li_->addRange(LiveRange(Start, lis_.getMBBEndIdx(MBB), VNI)); // Run sequence of full blocks. for (++MBB; MBB != MBBE; ++MBB) { Start = lis_.getMBBStartIdx(MBB); - li_.addRange(LiveRange(Start, lis_.getMBBEndIdx(MBB), - mapValue(ParentVNI, Start))); + li_->addRange(LiveRange(Start, lis_.getMBBEndIdx(MBB), + mapValue(ParentVNI, Start))); } // Final block. Start = lis_.getMBBStartIdx(MBB); if (Start != End) - li_.addRange(LiveRange(Start, End, mapValue(ParentVNI, Start))); + li_->addRange(LiveRange(Start, End, mapValue(ParentVNI, Start))); } /// addRange - Add live ranges to li_ where [Start;End) intersects parentli_. /// All needed values whose def is not inside [Start;End) must be defined /// beforehand so mapValue will work. void LiveIntervalMap::addRange(SlotIndex Start, SlotIndex End) { + assert(li_ && "call reset first"); LiveInterval::const_iterator B = parentli_.begin(), E = parentli_.end(); LiveInterval::const_iterator I = std::lower_bound(B, E, Start); Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=113815&r1=113814&r2=113815&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Sep 13 18:29:09 2010 @@ -151,7 +151,7 @@ const LiveInterval &parentli_; // The child interval's values are fully contained inside parentli_ values. - LiveInterval &li_; + LiveInterval *li_; typedef DenseMap ValueMap; @@ -172,9 +172,14 @@ public: LiveIntervalMap(LiveIntervals &lis, - const LiveInterval &parentli, - LiveInterval &li) - : lis_(lis), parentli_(parentli), li_(li) {} + const LiveInterval &parentli) + : lis_(lis), parentli_(parentli), li_(0) {} + + /// reset - clear all data structures and start a new live interval. + void reset(LiveInterval *); + + /// getLI - return the current live interval. + LiveInterval *getLI() const { return li_; } /// defValue - define a value in li_ from the parentli_ value VNI and Idx. /// Idx does not have to be ParentVNI->def, but it must be contained within From stoklund at 2pi.dk Mon Sep 13 18:29:11 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 13 Sep 2010 23:29:11 -0000 Subject: [llvm-commits] [llvm] r113816 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h Message-ID: <20100913232911.E86E92A6C12D@llvm.org> Author: stoklund Date: Mon Sep 13 18:29:11 2010 New Revision: 113816 URL: http://llvm.org/viewvc/llvm-project?rev=113816&view=rev Log: Mechanically replace LiveInterval* with LiveIntervalMap for intervals being edited without actually using LiveIntervalMap functionality. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=113816&r1=113815&r2=113816&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Sep 13 18:29:11 2010 @@ -585,7 +585,8 @@ mri_(vrm.getMachineFunction().getRegInfo()), tii_(*vrm.getMachineFunction().getTarget().getInstrInfo()), curli_(sa_.getCurLI()), - dupli_(0), openli_(0), + dupli_(lis_, *curli_), + openli_(lis_, *curli_), intervals_(intervals), firstInterval(intervals_.size()) { @@ -608,18 +609,18 @@ } LiveInterval *SplitEditor::getDupLI() { - if (!dupli_) { + if (!dupli_.getLI()) { // Create an interval for dupli that is a copy of curli. - dupli_ = createInterval(); - dupli_->Copy(*curli_, &mri_, lis_.getVNInfoAllocator()); + dupli_.reset(createInterval()); + dupli_.getLI()->Copy(*curli_, &mri_, lis_.getVNInfoAllocator()); } - return dupli_; + return dupli_.getLI(); } VNInfo *SplitEditor::mapValue(const VNInfo *curliVNI) { VNInfo *&VNI = valueMap_[curliVNI]; if (!VNI) - VNI = openli_->createValueCopy(curliVNI, lis_.getVNInfoAllocator()); + VNI = openli_.getLI()->createValueCopy(curliVNI, lis_.getVNInfoAllocator()); return VNI; } @@ -638,23 +639,23 @@ /// Create a new virtual register and live interval. void SplitEditor::openIntv() { - assert(!openli_ && "Previous LI not closed before openIntv"); - openli_ = createInterval(); - intervals_.push_back(openli_); + assert(!openli_.getLI() && "Previous LI not closed before openIntv"); + openli_.reset(createInterval()); + intervals_.push_back(openli_.getLI()); liveThrough_ = false; } /// enterIntvBefore - Enter openli before the instruction at Idx. If curli is /// not live before Idx, a COPY is not inserted. void SplitEditor::enterIntvBefore(SlotIndex Idx) { - assert(openli_ && "openIntv not called before enterIntvBefore"); + assert(openli_.getLI() && "openIntv not called before enterIntvBefore"); // Copy from curli_ if it is live. if (VNInfo *CurVNI = curli_->getVNInfoAt(Idx.getUseIndex())) { MachineInstr *MI = lis_.getInstructionFromIndex(Idx); assert(MI && "enterIntvBefore called with invalid index"); - VNInfo *VNI = insertCopy(*openli_, *MI->getParent(), MI); - openli_->addRange(LiveRange(VNI->def, Idx.getDefIndex(), VNI)); + VNInfo *VNI = insertCopy(*openli_.getLI(), *MI->getParent(), MI); + openli_.getLI()->addRange(LiveRange(VNI->def, Idx.getDefIndex(), VNI)); // Make sure CurVNI is properly mapped. VNInfo *&mapVNI = valueMap_[CurVNI]; @@ -662,14 +663,15 @@ assert(!mapVNI && "enterIntvBefore called more than once for the same value"); mapVNI = VNI; } - DEBUG(dbgs() << " enterIntvBefore " << Idx << ": " << *openli_ << '\n'); + DEBUG(dbgs() << " enterIntvBefore " << Idx << ": " << *openli_.getLI() + << '\n'); } /// enterIntvAtEnd - Enter openli at the end of MBB. /// PhiMBB is a successor inside openli where a PHI value is created. /// Currently, all entries must share the same PhiMBB. void SplitEditor::enterIntvAtEnd(MachineBasicBlock &A, MachineBasicBlock &B) { - assert(openli_ && "openIntv not called before enterIntvAtEnd"); + assert(openli_.getLI() && "openIntv not called before enterIntvAtEnd"); SlotIndex EndA = lis_.getMBBEndIdx(&A); VNInfo *CurVNIA = curli_->getVNInfoAt(EndA.getPrevIndex()); @@ -680,8 +682,8 @@ } // Add a phi kill value and live range out of A. - VNInfo *VNIA = insertCopy(*openli_, A, A.getFirstTerminator()); - openli_->addRange(LiveRange(VNIA->def, EndA, VNIA)); + VNInfo *VNIA = insertCopy(*openli_.getLI(), A, A.getFirstTerminator()); + openli_.getLI()->addRange(LiveRange(VNIA->def, EndA, VNIA)); // FIXME: If this is the only entry edge, we don't need the extra PHI value. // FIXME: If there are multiple entry blocks (so not a loop), we need proper @@ -697,11 +699,11 @@ return; } - VNInfo *VNIB = openli_->getVNInfoAt(StartB); + VNInfo *VNIB = openli_.getLI()->getVNInfoAt(StartB); if (!VNIB) { // Create a phi value. - VNIB = openli_->getNextValue(SlotIndex(StartB, true), 0, false, - lis_.getVNInfoAllocator()); + VNIB = openli_.getLI()->getNextValue(SlotIndex(StartB, true), 0, false, + lis_.getVNInfoAllocator()); VNIB->setIsPHIDef(true); VNInfo *&mapVNI = valueMap_[CurB->valno]; if (mapVNI) { @@ -714,7 +716,7 @@ } - DEBUG(dbgs() << " enterIntvAtEnd: " << *openli_ << '\n'); + DEBUG(dbgs() << " enterIntvAtEnd: " << *openli_.getLI() << '\n'); } /// useIntv - indicate that all instructions in MBB should use openli. @@ -723,7 +725,7 @@ } void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) { - assert(openli_ && "openIntv not called before useIntv"); + assert(openli_.getLI() && "openIntv not called before useIntv"); // Map the curli values from the interval into openli_ LiveInterval::const_iterator B = curli_->begin(), E = curli_->end(); @@ -733,22 +735,22 @@ --I; // I begins before Start, but overlaps. if (I->end > Start) - openli_->addRange(LiveRange(Start, std::min(End, I->end), - mapValue(I->valno))); + openli_.getLI()->addRange(LiveRange(Start, std::min(End, I->end), + mapValue(I->valno))); ++I; } // The remaining ranges begin after Start. for (;I != E && I->start < End; ++I) - openli_->addRange(LiveRange(I->start, std::min(End, I->end), - mapValue(I->valno))); - DEBUG(dbgs() << " use [" << Start << ';' << End << "): " << *openli_ - << '\n'); + openli_.getLI()->addRange(LiveRange(I->start, std::min(End, I->end), + mapValue(I->valno))); + DEBUG(dbgs() << " use [" << Start << ';' << End << "): " + << *openli_.getLI() << '\n'); } /// leaveIntvAfter - Leave openli after the instruction at Idx. void SplitEditor::leaveIntvAfter(SlotIndex Idx) { - assert(openli_ && "openIntv not called before leaveIntvAfter"); + assert(openli_.getLI() && "openIntv not called before leaveIntvAfter"); const LiveRange *CurLR = curli_->getLiveRangeContaining(Idx.getDefIndex()); if (!CurLR || CurLR->end <= Idx.getBoundaryIndex()) { @@ -757,7 +759,7 @@ } // Was this value of curli live through openli? - if (!openli_->liveAt(CurLR->valno->def)) { + if (!openli_.getLI()->liveAt(CurLR->valno->def)) { DEBUG(dbgs() << " leaveIntvAfter " << Idx << ": using external value\n"); liveThrough_ = true; return; @@ -765,24 +767,25 @@ // We are going to insert a back copy, so we must have a dupli_. LiveRange *DupLR = getDupLI()->getLiveRangeContaining(Idx.getDefIndex()); - assert(DupLR && "dupli not live into black, but curli is?"); + assert(DupLR && "dupli not live into block, but curli is?"); // Insert the COPY instruction. MachineBasicBlock::iterator I = lis_.getInstructionFromIndex(Idx); MachineInstr *MI = BuildMI(*I->getParent(), llvm::next(I), I->getDebugLoc(), - tii_.get(TargetOpcode::COPY), dupli_->reg) - .addReg(openli_->reg); + tii_.get(TargetOpcode::COPY), dupli_.getLI()->reg) + .addReg(openli_.getLI()->reg); SlotIndex CopyIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); - openli_->addRange(LiveRange(Idx.getDefIndex(), CopyIdx, - mapValue(CurLR->valno))); + openli_.getLI()->addRange(LiveRange(Idx.getDefIndex(), CopyIdx, + mapValue(CurLR->valno))); DupLR->valno->def = CopyIdx; - DEBUG(dbgs() << " leaveIntvAfter " << Idx << ": " << *openli_ << '\n'); + DEBUG(dbgs() << " leaveIntvAfter " << Idx << ": " << *openli_.getLI() + << '\n'); } /// leaveIntvAtTop - Leave the interval at the top of MBB. /// Currently, only one value can leave the interval. void SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) { - assert(openli_ && "openIntv not called before leaveIntvAtTop"); + assert(openli_.getLI() && "openIntv not called before leaveIntvAtTop"); SlotIndex Start = lis_.getMBBStartIdx(&MBB); const LiveRange *CurLR = curli_->getLiveRangeContaining(Start); @@ -799,7 +802,7 @@ // If MBB is using a value of curli that was defined outside the openli range, // we don't want to copy it back here. - if (!isPHIDef && !openli_->liveAt(CurLR->valno->def)) { + if (!isPHIDef && !openli_.getLI()->liveAt(CurLR->valno->def)) { DEBUG(dbgs() << " leaveIntvAtTop at " << Start << ": using external value\n"); liveThrough_ = true; @@ -808,24 +811,24 @@ // We are going to insert a back copy, so we must have a dupli_. LiveRange *DupLR = getDupLI()->getLiveRangeContaining(Start); - assert(DupLR && "dupli not live into black, but curli is?"); + assert(DupLR && "dupli not live into block, but curli is?"); // Insert the COPY instruction. MachineInstr *MI = BuildMI(MBB, MBB.begin(), DebugLoc(), - tii_.get(TargetOpcode::COPY), dupli_->reg) - .addReg(openli_->reg); + tii_.get(TargetOpcode::COPY), dupli_.getLI()->reg) + .addReg(openli_.getLI()->reg); SlotIndex Idx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); // Adjust dupli and openli values. if (isPHIDef) { // dupli was already a PHI on entry to MBB. Simply insert an openli PHI, // and shift the dupli def down to the COPY. - VNInfo *VNI = openli_->getNextValue(SlotIndex(Start, true), 0, false, - lis_.getVNInfoAllocator()); + VNInfo *VNI = openli_.getLI()->getNextValue(SlotIndex(Start,true), 0, false, + lis_.getVNInfoAllocator()); VNI->setIsPHIDef(true); - openli_->addRange(LiveRange(VNI->def, Idx, VNI)); + openli_.getLI()->addRange(LiveRange(VNI->def, Idx, VNI)); - dupli_->removeRange(Start, Idx); + dupli_.getLI()->removeRange(Start, Idx); DupLR->valno->def = Idx; DupLR->valno->setIsPHIDef(false); } else { @@ -834,10 +837,10 @@ << DupLR->valno->def << "\n"); // FIXME: We may not need a PHI here if all predecessors have the same // value. - VNInfo *VNI = openli_->getNextValue(SlotIndex(Start, true), 0, false, - lis_.getVNInfoAllocator()); + VNInfo *VNI = openli_.getLI()->getNextValue(SlotIndex(Start,true), 0, false, + lis_.getVNInfoAllocator()); VNI->setIsPHIDef(true); - openli_->addRange(LiveRange(VNI->def, Idx, VNI)); + openli_.getLI()->addRange(LiveRange(VNI->def, Idx, VNI)); // FIXME: What if DupLR->valno is used by multiple exits? SSA Update. @@ -846,16 +849,17 @@ DupLR->valno->setIsPHIDef(false); } - DEBUG(dbgs() << " leaveIntvAtTop at " << Idx << ": " << *openli_ << '\n'); + DEBUG(dbgs() << " leaveIntvAtTop at " << Idx << ": " << *openli_.getLI() + << '\n'); } /// closeIntv - Indicate that we are done editing the currently open /// LiveInterval, and ranges can be trimmed. void SplitEditor::closeIntv() { - assert(openli_ && "openIntv not called before closeIntv"); + assert(openli_.getLI() && "openIntv not called before closeIntv"); DEBUG(dbgs() << " closeIntv cleaning up\n"); - DEBUG(dbgs() << " open " << *openli_ << '\n'); + DEBUG(dbgs() << " open " << *openli_.getLI() << '\n'); if (liveThrough_) { DEBUG(dbgs() << " value live through region, leaving dupli as is.\n"); @@ -863,22 +867,22 @@ // live out with copies inserted, or killed by region. Either way we need to // remove the overlapping region from dupli. getDupLI(); - for (LiveInterval::iterator I = openli_->begin(), E = openli_->end(); - I != E; ++I) { - dupli_->removeRange(I->start, I->end); + for (LiveInterval::iterator I = openli_.getLI()->begin(), + E = openli_.getLI()->end(); I != E; ++I) { + dupli_.getLI()->removeRange(I->start, I->end); } // FIXME: A block branching to the entry block may also branch elsewhere // curli is live. We need both openli and curli to be live in that case. - DEBUG(dbgs() << " dup2 " << *dupli_ << '\n'); + DEBUG(dbgs() << " dup2 " << *dupli_.getLI() << '\n'); } - openli_ = 0; + openli_.reset(0); valueMap_.clear(); } /// rewrite - after all the new live ranges have been created, rewrite /// instructions using curli to use the new intervals. -void SplitEditor::rewrite() { - assert(!openli_ && "Previous LI not closed before rewrite"); +bool SplitEditor::rewrite() { + assert(!openli_.getLI() && "Previous LI not closed before rewrite"); const LiveInterval *curli = sa_.getCurLI(); for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(curli->reg), RE = mri_.reg_end(); RI != RE;) { @@ -893,7 +897,7 @@ } SlotIndex Idx = lis_.getInstructionIndex(MI); Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex(); - LiveInterval *LI = dupli_; + LiveInterval *LI = dupli_.getLI(); for (unsigned i = firstInterval, e = intervals_.size(); i != e; ++i) { LiveInterval *testli = intervals_[i]; if (testli->liveAt(Idx)) { @@ -909,14 +913,14 @@ } // dupli_ goes in last, after rewriting. - if (dupli_) { - if (dupli_->empty()) { + if (dupli_.getLI()) { + if (dupli_.getLI()->empty()) { DEBUG(dbgs() << " dupli became empty?\n"); - lis_.removeInterval(dupli_->reg); - dupli_ = 0; + lis_.removeInterval(dupli_.getLI()->reg); + dupli_.reset(0); } else { - dupli_->RenumberValues(lis_); - intervals_.push_back(dupli_); + dupli_.getLI()->RenumberValues(lis_); + intervals_.push_back(dupli_.getLI()); } } @@ -929,6 +933,7 @@ DEBUG(dbgs() << " new interval " << mri_.getRegClass(li.reg)->getName() << ":" << li << '\n'); } + return dupli_.getLI(); } @@ -969,8 +974,7 @@ // Done. closeIntv(); - rewrite(); - return dupli_; + return rewrite(); } @@ -1015,8 +1019,7 @@ leaveIntvAfter(IP.second); closeIntv(); } - rewrite(); - return dupli_; + return rewrite(); } @@ -1091,6 +1094,5 @@ closeIntv(); } - rewrite(); - return dupli_; + return rewrite(); } Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=113816&r1=113815&r2=113816&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Sep 13 18:29:11 2010 @@ -227,10 +227,10 @@ /// dupli_ - Created as a copy of curli_, ranges are carved out as new /// intervals get added through openIntv / closeIntv. This is used to avoid /// editing curli_. - LiveInterval *dupli_; + LiveIntervalMap dupli_; /// Currently open LiveInterval. - LiveInterval *openli_; + LiveIntervalMap openli_; /// createInterval - Create a new virtual register and LiveInterval with same /// register class and spill slot as curli. @@ -303,7 +303,9 @@ /// rewrite - after all the new live ranges have been created, rewrite /// instructions using curli to use the new intervals. - void rewrite(); + /// Return true if curli has been completely replaced, false if curli is still + /// intact, and needs to be spilled or split further. + bool rewrite(); // ===--- High level methods ---=== From bob.wilson at apple.com Mon Sep 13 18:55:11 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 13 Sep 2010 23:55:11 -0000 Subject: [llvm-commits] [llvm] r113818 - in /llvm/trunk/lib/Target/ARM: ARM.h ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrFormats.td ARMInstrNEON.td ARMTargetMachine.cpp CMakeLists.txt NEONPreAllocPass.cpp Message-ID: <20100913235511.38A552A6C12C@llvm.org> Author: bwilson Date: Mon Sep 13 18:55:10 2010 New Revision: 113818 URL: http://llvm.org/viewvc/llvm-project?rev=113818&view=rev Log: Convert some VTBL and VTBX instructions to use pseudo instructions prior to register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! Removed: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARM.h llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=113818&r1=113817&r2=113818&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Mon Sep 13 18:55:10 2010 @@ -127,7 +127,6 @@ FunctionPass *createARMExpandPseudoPass(); FunctionPass *createARMGlobalMergePass(const TargetLowering* tli); FunctionPass *createARMConstantIslandPass(); -FunctionPass *createNEONPreAllocPass(); FunctionPass *createNEONMoveFixPass(); FunctionPass *createThumb2ITBlockPass(); FunctionPass *createThumb2SizeReductionPass(); Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113818&r1=113817&r2=113818&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Sep 13 18:55:10 2010 @@ -44,6 +44,8 @@ void ExpandVLD(MachineBasicBlock::iterator &MBBI); void ExpandVST(MachineBasicBlock::iterator &MBBI); void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); + void ExpandVTBL(MachineBasicBlock::iterator &MBBI, + unsigned Opc, bool IsExt, unsigned NumRegs); }; char ARMExpandPseudo::ID = 0; } @@ -326,7 +328,7 @@ D1 = TRI->getSubReg(Reg, ARM::dsub_3); D2 = TRI->getSubReg(Reg, ARM::dsub_5); D3 = TRI->getSubReg(Reg, ARM::dsub_7); - } + } } /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register @@ -414,10 +416,10 @@ if (NumRegs > 3) MIB.addReg(D3); MIB = AddDefaultPred(MIB); - TransferImpOps(MI, MIB, MIB); if (SrcIsKill) // Add an implicit kill for the super-reg. (*MIB).addRegisterKilled(SrcReg, TRI, true); + TransferImpOps(MI, MIB, MIB); MI.eraseFromParent(); } @@ -500,6 +502,42 @@ MI.eraseFromParent(); } +/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ +/// register operands to real instructions with D register operands. +void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, + unsigned Opc, bool IsExt, unsigned NumRegs) { + MachineInstr &MI = *MBBI; + MachineBasicBlock &MBB = *MI.getParent(); + + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); + unsigned OpIdx = 0; + + // Transfer the destination register operand. + MIB.addOperand(MI.getOperand(OpIdx++)); + if (IsExt) + MIB.addOperand(MI.getOperand(OpIdx++)); + + bool SrcIsKill = MI.getOperand(OpIdx).isKill(); + unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); + unsigned D0, D1, D2, D3; + GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); + MIB.addReg(D0).addReg(D1); + if (NumRegs > 2) + MIB.addReg(D2); + if (NumRegs > 3) + MIB.addReg(D3); + + // Copy the other source register operand. + MIB.addOperand(MI.getOperand(OpIdx)); + + MIB = AddDefaultPred(MIB); + if (SrcIsKill) + // Add an implicit kill for the super-reg. + (*MIB).addRegisterKilled(SrcReg, TRI, true); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); +} + bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { bool Modified = false; @@ -515,7 +553,7 @@ ModifiedOp = false; break; - case ARM::tLDRpci_pic: + case ARM::tLDRpci_pic: case ARM::t2LDRpci_pic: { unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) ? ARM::tLDRpci : ARM::t2LDRpci; @@ -765,6 +803,19 @@ case ARM::VST4LNq32Pseudo_UPD: ExpandLaneOp(MBBI); break; + + case ARM::VTBL2Pseudo: + ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break; + case ARM::VTBL3Pseudo: + ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break; + case ARM::VTBL4Pseudo: + ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break; + case ARM::VTBX2Pseudo: + ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break; + case ARM::VTBX3Pseudo: + ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break; + case ARM::VTBX4Pseudo: + ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break; } if (ModifiedOp) Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=113818&r1=113817&r2=113818&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Sep 13 18:55:10 2010 @@ -1353,17 +1353,10 @@ RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); } - // Now extract the D registers back out. SmallVector Ops; if (IsExt) Ops.push_back(N->getOperand(1)); - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); - if (NumVecs > 2) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq)); - if (NumVecs > 3) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq)); - + Ops.push_back(RegSeq); Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); Ops.push_back(getAL(CurDAG)); // predicate Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register @@ -2099,18 +2092,18 @@ break; case Intrinsic::arm_neon_vtbl2: - return SelectVTBL(N, false, 2, ARM::VTBL2); + return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo); case Intrinsic::arm_neon_vtbl3: - return SelectVTBL(N, false, 3, ARM::VTBL3); + return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo); case Intrinsic::arm_neon_vtbl4: - return SelectVTBL(N, false, 4, ARM::VTBL4); + return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo); case Intrinsic::arm_neon_vtbx2: - return SelectVTBL(N, true, 2, ARM::VTBX2); + return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo); case Intrinsic::arm_neon_vtbx3: - return SelectVTBL(N, true, 3, ARM::VTBX3); + return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo); case Intrinsic::arm_neon_vtbx4: - return SelectVTBL(N, true, 4, ARM::VTBX4); + return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo); } break; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=113818&r1=113817&r2=113818&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Sep 13 18:55:10 2010 @@ -1541,6 +1541,14 @@ list Predicates = [HasNEON]; } +class PseudoNeonI + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ins pred:$p)); + list Predicates = [HasNEON]; +} + class NDataI pattern> : NeonI; } // hasExtraSrcRegAllocReq = 1 +def VTBL2Pseudo + : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "">; +def VTBL3Pseudo + : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "">; +def VTBL4Pseudo + : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "">; + // VTBX : Vector Table Extension def VTBX1 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst), @@ -3863,6 +3870,16 @@ "$orig = $dst", []>; } // hasExtraSrcRegAllocReq = 1 +def VTBX2Pseudo + : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src), + IIC_VTBX2, "$orig = $dst">; +def VTBX3Pseudo + : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), + IIC_VTBX3, "$orig = $dst">; +def VTBX4Pseudo + : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), + IIC_VTBX4, "$orig = $dst">; + //===----------------------------------------------------------------------===// // NEON instructions for single-precision FP math //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=113818&r1=113817&r2=113818&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Sep 13 18:55:10 2010 @@ -104,9 +104,6 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - if (Subtarget.hasNEON()) - PM.add(createNEONPreAllocPass()); - // FIXME: temporarily disabling load / store optimization pass for Thumb1. if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) PM.add(createARMLoadStoreOptimizationPass(true)); Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=113818&r1=113817&r2=113818&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Sep 13 18:55:10 2010 @@ -37,7 +37,6 @@ ARMTargetMachine.cpp ARMTargetObjectFile.cpp NEONMoveFix.cpp - NEONPreAllocPass.cpp Thumb1InstrInfo.cpp Thumb1RegisterInfo.cpp Thumb2HazardRecognizer.cpp Removed: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=113817&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (removed) @@ -1,268 +0,0 @@ -//===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "neon-prealloc" -#include "ARM.h" -#include "ARMInstrInfo.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -using namespace llvm; - -namespace { - class NEONPreAllocPass : public MachineFunctionPass { - const TargetInstrInfo *TII; - MachineRegisterInfo *MRI; - - public: - static char ID; - NEONPreAllocPass() : MachineFunctionPass(ID) {} - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual const char *getPassName() const { - return "NEON register pre-allocation pass"; - } - - private: - bool FormsRegSequence(MachineInstr *MI, - unsigned FirstOpnd, unsigned NumRegs, - unsigned Offset, unsigned Stride) const; - bool PreAllocNEONRegisters(MachineBasicBlock &MBB); - }; - - char NEONPreAllocPass::ID = 0; -} - -static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs, - unsigned &Offset, unsigned &Stride) { - // Default to unit stride with no offset. - Stride = 1; - Offset = 0; - - switch (Opcode) { - default: - break; - - case ARM::VTBL2: - FirstOpnd = 1; - NumRegs = 2; - return true; - - case ARM::VTBL3: - FirstOpnd = 1; - NumRegs = 3; - return true; - - case ARM::VTBL4: - FirstOpnd = 1; - NumRegs = 4; - return true; - - case ARM::VTBX2: - FirstOpnd = 2; - NumRegs = 2; - return true; - - case ARM::VTBX3: - FirstOpnd = 2; - NumRegs = 3; - return true; - - case ARM::VTBX4: - FirstOpnd = 2; - NumRegs = 4; - return true; - } - - return false; -} - -bool -NEONPreAllocPass::FormsRegSequence(MachineInstr *MI, - unsigned FirstOpnd, unsigned NumRegs, - unsigned Offset, unsigned Stride) const { - MachineOperand &FMO = MI->getOperand(FirstOpnd); - assert(FMO.isReg() && FMO.getSubReg() == 0 && "unexpected operand"); - unsigned VirtReg = FMO.getReg(); - (void)VirtReg; - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "expected a virtual register"); - - unsigned LastSubIdx = 0; - if (FMO.isDef()) { - MachineInstr *RegSeq = 0; - for (unsigned R = 0; R < NumRegs; ++R) { - const MachineOperand &MO = MI->getOperand(FirstOpnd + R); - assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand"); - unsigned VirtReg = MO.getReg(); - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "expected a virtual register"); - // Feeding into a REG_SEQUENCE. - if (!MRI->hasOneNonDBGUse(VirtReg)) - return false; - MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg); - if (!UseMI->isRegSequence()) - return false; - if (RegSeq && RegSeq != UseMI) - return false; - unsigned OpIdx = 1 + (Offset + R * Stride) * 2; - if (UseMI->getOperand(OpIdx).getReg() != VirtReg) - llvm_unreachable("Malformed REG_SEQUENCE instruction!"); - unsigned SubIdx = UseMI->getOperand(OpIdx + 1).getImm(); - if (LastSubIdx) { - if (LastSubIdx != SubIdx-Stride) - return false; - } else { - // Must start from dsub_0 or qsub_0. - if (SubIdx != (ARM::dsub_0+Offset) && - SubIdx != (ARM::qsub_0+Offset)) - return false; - } - RegSeq = UseMI; - LastSubIdx = SubIdx; - } - - // In the case of vld3, etc., make sure the trailing operand of - // REG_SEQUENCE is an undef. - if (NumRegs == 3) { - unsigned OpIdx = 1 + (Offset + 3 * Stride) * 2; - const MachineOperand &MO = RegSeq->getOperand(OpIdx); - unsigned VirtReg = MO.getReg(); - MachineInstr *DefMI = MRI->getVRegDef(VirtReg); - if (!DefMI || !DefMI->isImplicitDef()) - return false; - } - return true; - } - - unsigned LastSrcReg = 0; - SmallVector SubIds; - for (unsigned R = 0; R < NumRegs; ++R) { - const MachineOperand &MO = MI->getOperand(FirstOpnd + R); - assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand"); - unsigned VirtReg = MO.getReg(); - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "expected a virtual register"); - // Extracting from a Q or QQ register. - MachineInstr *DefMI = MRI->getVRegDef(VirtReg); - if (!DefMI || !DefMI->isCopy() || !DefMI->getOperand(1).getSubReg()) - return false; - VirtReg = DefMI->getOperand(1).getReg(); - if (LastSrcReg && LastSrcReg != VirtReg) - return false; - LastSrcReg = VirtReg; - const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); - if (RC != ARM::QPRRegisterClass && - RC != ARM::QQPRRegisterClass && - RC != ARM::QQQQPRRegisterClass) - return false; - unsigned SubIdx = DefMI->getOperand(1).getSubReg(); - if (LastSubIdx) { - if (LastSubIdx != SubIdx-Stride) - return false; - } else { - // Must start from dsub_0 or qsub_0. - if (SubIdx != (ARM::dsub_0+Offset) && - SubIdx != (ARM::qsub_0+Offset)) - return false; - } - SubIds.push_back(SubIdx); - LastSubIdx = SubIdx; - } - - // FIXME: Update the uses of EXTRACT_SUBREG from REG_SEQUENCE is - // currently required for correctness. e.g. - // %reg1041 = REG_SEQUENCE %reg1040, 5, %reg1035, 6 - // %reg1042 = EXTRACT_SUBREG %reg1041, 6 - // %reg1043 = EXTRACT_SUBREG %reg1041, 5 - // VST1q16 %reg1025, 0, %reg1043, %reg1042, - // reg1042 and reg1043 should be replaced with reg1041:6 and reg1041:5 - // respectively. - // We need to change how we model uses of REG_SEQUENCE. - for (unsigned R = 0; R < NumRegs; ++R) { - MachineOperand &MO = MI->getOperand(FirstOpnd + R); - unsigned OldReg = MO.getReg(); - MachineInstr *DefMI = MRI->getVRegDef(OldReg); - assert(DefMI->isCopy()); - MO.setReg(LastSrcReg); - MO.setSubReg(SubIds[R]); - MO.setIsKill(false); - // Delete the EXTRACT_SUBREG if its result is now dead. - if (MRI->use_empty(OldReg)) - DefMI->eraseFromParent(); - } - - return true; -} - -bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) { - bool Modified = false; - - MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); - for (; MBBI != E; ++MBBI) { - MachineInstr *MI = &*MBBI; - unsigned FirstOpnd, NumRegs, Offset, Stride; - if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride)) - continue; - if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride)) - continue; - - MachineBasicBlock::iterator NextI = llvm::next(MBBI); - for (unsigned R = 0; R < NumRegs; ++R) { - MachineOperand &MO = MI->getOperand(FirstOpnd + R); - assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand"); - unsigned VirtReg = MO.getReg(); - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "expected a virtual register"); - - // For now, just assign a fixed set of adjacent registers. - // This leaves plenty of room for future improvements. - static const unsigned NEONDRegs[] = { - ARM::D0, ARM::D1, ARM::D2, ARM::D3, - ARM::D4, ARM::D5, ARM::D6, ARM::D7 - }; - MO.setReg(NEONDRegs[Offset + R * Stride]); - - if (MO.isUse()) { - // Insert a copy from VirtReg. - BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),MO.getReg()) - .addReg(VirtReg, getKillRegState(MO.isKill())); - MO.setIsKill(); - } else if (MO.isDef() && !MO.isDead()) { - // Add a copy to VirtReg. - BuildMI(MBB, NextI, DebugLoc(), TII->get(TargetOpcode::COPY), VirtReg) - .addReg(MO.getReg()); - } - } - } - - return Modified; -} - -bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) { - TII = MF.getTarget().getInstrInfo(); - MRI = &MF.getRegInfo(); - - bool Modified = false; - for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; - ++MFI) { - MachineBasicBlock &MBB = *MFI; - Modified |= PreAllocNEONRegisters(MBB); - } - - return Modified; -} - -/// createNEONPreAllocPass - returns an instance of the NEON register -/// pre-allocation pass. -FunctionPass *llvm::createNEONPreAllocPass() { - return new NEONPreAllocPass(); -} From bigcheesegs at gmail.com Mon Sep 13 18:59:48 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 13 Sep 2010 23:59:48 -0000 Subject: [llvm-commits] [llvm] r113819 - in /llvm/trunk: ./ cmake/modules/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/ModuleMaker/ examples/ParallelJIT/ lib/Analysis/ lib/Analysis/IPA/ lib/Archive/ lib/AsmParser/ lib/Bitcode/Reader/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/CompilerDriver/ lib/Exec... Message-ID: <20100913235949.13B552A6C12C@llvm.org> Author: mspencer Date: Mon Sep 13 18:59:48 2010 New Revision: 113819 URL: http://llvm.org/viewvc/llvm-project?rev=113819&view=rev Log: Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally." This reverts commit r113632 Conflicts: cmake/modules/AddLLVM.cmake Added: llvm/trunk/cmake/modules/LLVMConfig.cmake (with props) llvm/trunk/cmake/modules/LLVMLibDeps.cmake Removed: llvm/trunk/cmake/modules/LLVMConfig.cmake.in Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/cmake/modules/CMakeLists.txt llvm/trunk/examples/BrainF/CMakeLists.txt llvm/trunk/examples/ExceptionDemo/CMakeLists.txt llvm/trunk/examples/Fibonacci/CMakeLists.txt llvm/trunk/examples/HowToUseJIT/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt llvm/trunk/examples/ModuleMaker/CMakeLists.txt llvm/trunk/examples/ParallelJIT/CMakeLists.txt llvm/trunk/lib/Analysis/CMakeLists.txt llvm/trunk/lib/Analysis/IPA/CMakeLists.txt llvm/trunk/lib/Archive/CMakeLists.txt llvm/trunk/lib/AsmParser/CMakeLists.txt llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt llvm/trunk/lib/CompilerDriver/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt llvm/trunk/lib/Linker/CMakeLists.txt llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt llvm/trunk/lib/Transforms/IPO/CMakeLists.txt llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt llvm/trunk/lib/Transforms/Utils/CMakeLists.txt llvm/trunk/tools/CMakeLists.txt llvm/trunk/tools/bugpoint/CMakeLists.txt llvm/trunk/tools/llc/CMakeLists.txt llvm/trunk/tools/lli/CMakeLists.txt llvm/trunk/tools/llvm-ar/CMakeLists.txt llvm/trunk/tools/llvm-as/CMakeLists.txt llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt llvm/trunk/tools/llvm-config/CMakeLists.txt llvm/trunk/tools/llvm-diff/CMakeLists.txt llvm/trunk/tools/llvm-dis/CMakeLists.txt llvm/trunk/tools/llvm-extract/CMakeLists.txt llvm/trunk/tools/llvm-ld/CMakeLists.txt llvm/trunk/tools/llvm-link/CMakeLists.txt llvm/trunk/tools/llvm-mc/CMakeLists.txt llvm/trunk/tools/llvm-nm/CMakeLists.txt llvm/trunk/tools/llvm-prof/CMakeLists.txt llvm/trunk/tools/llvm-ranlib/CMakeLists.txt llvm/trunk/tools/opt/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -272,7 +272,6 @@ # Everything else depends on Support and System: set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} ${LLVM_LIBS} ) -set(LLVM_COMMON_LIBS LLVMSupport LLVMSystem) set(LLVM_TABLEGEN "tblgen" CACHE STRING "Native TableGen executable. Saves building one when cross-compiling.") @@ -373,11 +372,6 @@ add_subdirectory(cmake/modules) -install(EXPORT LLVM - DESTINATION lib${LLVM_LIBDIR_SUFFIX}/cmake/llvm/ - FILE LLVMTargets.cmake - ) - install(DIRECTORY include/ DESTINATION include FILES_MATCHING Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Mon Sep 13 18:59:48 2010 @@ -1,21 +1,5 @@ include(LLVMProcessSources) - -function(get_system_libs return_var) - # Returns in `return_var' a list of system libraries used by LLVM. - if( NOT MSVC ) - if( MINGW ) - set(system_libs ${system_libs} imagehlp psapi) - elseif( CMAKE_HOST_UNIX ) - if( HAVE_LIBDL ) - set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) - endif() - if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD ) - set(system_libs ${system_libs} pthread) - endif() - endif( MINGW ) - endif( NOT MSVC ) - set(${return_var} ${system_libs} PARENT_SCOPE) -endfunction(get_system_libs) +include(LLVMConfig) macro(add_llvm_library name) llvm_process_sources( ALL_FILES ${ARGN} ) @@ -25,11 +9,7 @@ if( LLVM_COMMON_DEPENDS ) add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) - if (LLVM_COMMON_LIBS) - target_link_libraries(${name} ${LLVM_COMMON_LIBS}) - endif() install(TARGETS ${name} - EXPORT LLVM LIBRARY DESTINATION lib${LLVM_LIBDIR_SUFFIX} ARCHIVE DESTINATION lib${LLVM_LIBDIR_SUFFIX}) # The LLVM Target library shall be built before its sublibraries @@ -58,7 +38,6 @@ endif() install(TARGETS ${name} - EXPORT LLVM LIBRARY DESTINATION lib${LLVM_LIBDIR_SUFFIX} ARCHIVE DESTINATION lib${LLVM_LIBDIR_SUFFIX}) endif() @@ -78,12 +57,12 @@ target_link_libraries( ${name} ${lib} ) endforeach(lib) endif( LLVM_USED_LIBS ) + if( LLVM_LINK_COMPONENTS ) + llvm_config(${name} ${LLVM_LINK_COMPONENTS}) + endif( LLVM_LINK_COMPONENTS ) if( LLVM_COMMON_DEPENDS ) add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) - if (LLVM_COMMON_LIBS) - target_link_libraries(${name} ${LLVM_COMMON_LIBS}) - endif() if( NOT MINGW ) get_system_libs(llvm_system_libs) if( llvm_system_libs ) @@ -130,61 +109,3 @@ endif (TABLEGEN_OUTPUT) set(CURRENT_LLVM_TARGET LLVM${target_name} PARENT_SCOPE) endmacro(add_llvm_target) - -macro(llvm_get_target_libraries return_var) - set( link_components ${ARGN} ) - foreach(c ${link_components}) - # add codegen, asmprinter, asmparser, disassembler - list(FIND LLVM_TARGETS_TO_BUILD ${c} idx) - if( NOT idx LESS 0 ) - list(FIND llvm_libs "LLVM${c}CodeGen" idx) - if( NOT idx LESS 0 ) - list(APPEND expanded_components "LLVM${c}CodeGen") - else() - list(FIND llvm_libs "LLVM${c}" idx) - if( NOT idx LESS 0 ) - list(APPEND expanded_components "LLVM${c}") - else() - message(FATAL_ERROR "Target ${c} is not in the set of libraries.") - endif() - endif() - list(FIND llvm_libs "LLVM${c}AsmPrinter" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}AsmPrinter") - endif() - list(FIND llvm_libs "LLVM${c}AsmParser" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}AsmParser") - endif() - list(FIND llvm_libs "LLVM${c}Info" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}Info") - endif() - list(FIND llvm_libs "LLVM${c}Disassembler" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}Disassembler") - endif() - elseif( c STREQUAL "native" ) - list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") - elseif( c STREQUAL "nativecodegen" ) - list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") - elseif( c STREQUAL "backend" ) - # same case as in `native'. - elseif( c STREQUAL "engine" OR c STREQUAL "jit") - # TODO: as we assume we are on X86, this is `jit'. - list(APPEND expanded_components "LLVMJIT") - elseif( c STREQUAL "interpreter" ) - list(APPEND expanded_components "LLVMInterpreter") - elseif( c STREQUAL "all" ) - list(APPEND expanded_components ${llvm_libs}) - else( NOT idx LESS 0 ) - list(APPEND expanded_components LLVM${c}) - endif( NOT idx LESS 0 ) - endforeach(c) - set(${return_var} ${expanded_components}) -endmacro(llvm_get_target_libraries) - -macro(add_llvm_link_components target_name) - llvm_get_target_libraries(target_libs ${ARGN}) - target_link_libraries(${target_name} ${target_libs}) -endmacro() Modified: llvm/trunk/cmake/modules/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/cmake/modules/CMakeLists.txt (original) +++ llvm/trunk/cmake/modules/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,18 +1,12 @@ -set(LLVM_CFLAGS "${CMAKE_C_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}") -set(LLVM_CXXFLAGS "${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}") -set(LLVM_CPPFLAGS "${CMAKE_CPP_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}") -llvm_get_target_libraries(LLVM_JIT_LIBS jit) -llvm_get_target_libraries(LLVM_INTERPRETER_LIBS interpreter) -llvm_get_target_libraries(LLVM_NATIVECODEGEN_LIBS nativecodegen) -get_system_libs(LLVM_SYSTEM_LIBS) +set(llvm_cmake_builddir "${LLVM_BINARY_DIR}/share/llvm/cmake") configure_file( - LLVMConfig.cmake.in - ${LLVM_BINARY_DIR}/cmake/modules/LLVMConfig.cmake - @ONLY - ) + LLVM.cmake + ${llvm_cmake_builddir}/LLVM.cmake + @ONLY) install(FILES - ${LLVM_BINARY_DIR}/cmake/modules/LLVMConfig.cmake - DESTINATION lib${LLVM_LIBDIR_SUFFIX}/cmake/llvm/ - ) + ${llvm_cmake_builddir}/LLVM.cmake + LLVMConfig.cmake + LLVMLibDeps.cmake + DESTINATION share/llvm/cmake) Added: llvm/trunk/cmake/modules/LLVMConfig.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=113819&view=auto ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake (added) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake Mon Sep 13 18:59:48 2010 @@ -0,0 +1,165 @@ +function(get_system_libs return_var) + # Returns in `return_var' a list of system libraries used by LLVM. + if( NOT MSVC ) + if( MINGW ) + set(system_libs ${system_libs} imagehlp psapi) + elseif( CMAKE_HOST_UNIX ) + if( HAVE_LIBDL ) + set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) + endif() + if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD ) + set(system_libs ${system_libs} pthread) + endif() + endif( MINGW ) + endif( NOT MSVC ) + set(${return_var} ${system_libs} PARENT_SCOPE) +endfunction(get_system_libs) + + +function(is_llvm_target_library library return_var) + # Sets variable `return_var' to ON if `library' corresponds to a + # LLVM supported target. To OFF if it doesn't. + set(${return_var} OFF PARENT_SCOPE) + string(TOUPPER "${library}" capitalized_lib) + string(TOUPPER "${LLVM_ALL_TARGETS}" targets) + foreach(t ${targets}) + if( capitalized_lib STREQUAL "LLVM${t}" OR + capitalized_lib STREQUAL "LLVM${t}CODEGEN" OR + capitalized_lib STREQUAL "LLVM${t}ASMPARSER" OR + capitalized_lib STREQUAL "LLVM${t}ASMPRINTER" OR + capitalized_lib STREQUAL "LLVM${t}DISASSEMBLER" OR + capitalized_lib STREQUAL "LLVM${t}INFO" ) + set(${return_var} ON PARENT_SCOPE) + break() + endif() + endforeach() +endfunction(is_llvm_target_library) + + +macro(llvm_config executable) + explicit_llvm_config(${executable} ${ARGN}) +endmacro(llvm_config) + + +function(explicit_llvm_config executable) + set( link_components ${ARGN} ) + + explicit_map_components_to_libraries(LIBRARIES ${link_components}) + target_link_libraries(${executable} ${LIBRARIES}) +endfunction(explicit_llvm_config) + + +# This is a variant intended for the final user: +function(llvm_map_components_to_libraries OUT_VAR) + explicit_map_components_to_libraries(result ${ARGN}) + get_system_libs(sys_result) + set( ${OUT_VAR} ${result} ${sys_result} PARENT_SCOPE ) +endfunction(llvm_map_components_to_libraries) + + +function(explicit_map_components_to_libraries out_libs) + set( link_components ${ARGN} ) + foreach(c ${link_components}) + # add codegen, asmprinter, asmparser, disassembler + list(FIND LLVM_TARGETS_TO_BUILD ${c} idx) + if( NOT idx LESS 0 ) + list(FIND llvm_libs "LLVM${c}CodeGen" idx) + if( NOT idx LESS 0 ) + list(APPEND expanded_components "LLVM${c}CodeGen") + else() + list(FIND llvm_libs "LLVM${c}" idx) + if( NOT idx LESS 0 ) + list(APPEND expanded_components "LLVM${c}") + else() + message(FATAL_ERROR "Target ${c} is not in the set of libraries.") + endif() + endif() + list(FIND llvm_libs "LLVM${c}AsmPrinter" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}AsmPrinter") + endif() + list(FIND llvm_libs "LLVM${c}AsmParser" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}AsmParser") + endif() + list(FIND llvm_libs "LLVM${c}Info" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}Info") + endif() + list(FIND llvm_libs "LLVM${c}Disassembler" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}Disassembler") + endif() + elseif( c STREQUAL "native" ) + list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") + elseif( c STREQUAL "nativecodegen" ) + list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") + elseif( c STREQUAL "backend" ) + # same case as in `native'. + elseif( c STREQUAL "engine" ) + # TODO: as we assume we are on X86, this is `jit'. + list(APPEND expanded_components "LLVMJIT") + elseif( c STREQUAL "all" ) + list(APPEND expanded_components ${llvm_libs}) + else( NOT idx LESS 0 ) + list(APPEND expanded_components LLVM${c}) + endif( NOT idx LESS 0 ) + endforeach(c) + # We must match capitalization. + string(TOUPPER "${llvm_libs}" capitalized_libs) + list(REMOVE_DUPLICATES expanded_components) + list(LENGTH expanded_components lst_size) + set(result "") + while( 0 LESS ${lst_size} ) + list(GET expanded_components 0 c) + string(TOUPPER "${c}" capitalized) + list(FIND capitalized_libs ${capitalized} idx) + set(add_it ON) + if( idx LESS 0 ) + # The library is unkown. Maybe is an ommitted target? + is_llvm_target_library(${c} iltl_result) + if( NOT iltl_result ) + message(FATAL_ERROR "Library ${c} not found in list of llvm libraries.") + endif() + set(add_it OFF) + endif( idx LESS 0 ) + list(GET llvm_libs ${idx} canonical_lib) + list(REMOVE_ITEM result ${canonical_lib}) + foreach(c ${MSVC_LIB_DEPS_${canonical_lib}}) + list(REMOVE_ITEM expanded_components ${c}) + endforeach() + if( add_it ) + list(APPEND result ${canonical_lib}) + list(APPEND expanded_components ${MSVC_LIB_DEPS_${canonical_lib}}) + endif() + list(REMOVE_AT expanded_components 0) + list(LENGTH expanded_components lst_size) + endwhile( 0 LESS ${lst_size} ) + set(${out_libs} ${result} PARENT_SCOPE) +endfunction(explicit_map_components_to_libraries) + + +# The library dependency data is contained in the file +# LLVMLibDeps.cmake on this directory. It is automatically generated +# by tools/llvm-config/CMakeLists.txt when the build comprises all the +# targets and we are on a environment Posix enough to build the +# llvm-config script. This, in practice, just excludes MSVC. + +# When you remove or rename a library from the build, be sure to +# remove its file from lib/ as well, or the GenLibDeps.pl script will +# include it on its analysis! + +# The format generated by GenLibDeps.pl + +# libLLVMARMAsmPrinter.a: libLLVMMC.a libLLVMSupport.a + +# is translated to: + +# set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) + +# It is necessary to remove the `lib' prefix and the `.a' suffix. + +# This 'sed' script should do the trick: +# sed -e s'#\.a##g' -e 's#libLLVM#LLVM#g' -e 's#: # #' -e 's#\(.*\)#set(MSVC_LIB_DEPS_\1)#' ~/llvm/tools/llvm-config/LibDeps.txt + +include(LLVMLibDeps) Propchange: llvm/trunk/cmake/modules/LLVMConfig.cmake ------------------------------------------------------------------------------ svn:executable = * Removed: llvm/trunk/cmake/modules/LLVMConfig.cmake.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake.in?rev=113818&view=auto ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake.in (original) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake.in (removed) @@ -1,11 +0,0 @@ -get_filename_component(SELF_DIR "${CMAKE_CURRENT_LIST_FILE}" PATH) -include(${SELF_DIR}/LLVMTargets.cmake) -get_filename_component(LLVM_INCLUDE_DIRS "${SELF_DIR}/../../../include" ABSOLUTE) -set(LLVM_CPPFLAGS "@LLVM_CPPFLAGS@") -set(LLVM_CFLAGS "@LLVM_CFLAGS@") -set(LLVM_CXXFLAGS "@LLVM_CXXFLAGS@") -set(LLVM_SYSTEM_LIBS "@LLVM_SYSTEM_LIBS@") -set(LLVM_JIT_LIBS "@LLVM_JIT_LIBS@") -set(LLVM_INTERPRETER_LIBS "@LLVM_INTERPRETER_LIBS@") -set(LLVM_NATIVECODEGEN_LIBS "@LLVM_NATIVECODEGEN_LIBS@") -set(LLVM_BUILDMODE "@LLVM_BUILDMODE@") Added: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=113819&view=auto ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (added) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Mon Sep 13 18:59:48 2010 @@ -0,0 +1,71 @@ +set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) +set(MSVC_LIB_DEPS_LLVMAsmPrinter LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMBitReader LLVMCore LLVMSupport) +set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) +set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) +set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMCore LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMCodeGen LLVMCore LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmPrinter LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430AsmPrinter LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPIC16AsmPrinter LLVMPIC16CodeGen LLVMPIC16Info LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsCodeGen LLVMMipsInfo LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPIC16AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPIC16CodeGen LLVMPIC16Info LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMPIC16CodeGen LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMPIC16Info LLVMSelectionDAG LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMPIC16Info LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSparcInfo LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMSystem ) +set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystemZInfo LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZInfo LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMipa) +set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMX86AsmPrinter LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) +set(MSVC_LIB_DEPS_LLVMX86Info LLVMSupport) +set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) Modified: llvm/trunk/examples/BrainF/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/BrainF/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/BrainF/CMakeLists.txt (original) +++ llvm/trunk/examples/BrainF/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,7 +1,6 @@ +set(LLVM_LINK_COMPONENTS jit bitwriter nativecodegen interpreter) + add_llvm_example(BrainF BrainF.cpp BrainFDriver.cpp ) - -add_llvm_link_components(BrainF jit nativecodegen interpreter) -target_link_libraries(BrainF LLVMBitWriter) Modified: llvm/trunk/examples/ExceptionDemo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ExceptionDemo/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/ExceptionDemo/CMakeLists.txt (original) +++ llvm/trunk/examples/ExceptionDemo/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS jit nativecodegen) + add_llvm_example(ExceptionDemo ExceptionDemo.cpp ) - -add_llvm_link_components(ExceptionDemo jit nativecodegen) Modified: llvm/trunk/examples/Fibonacci/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Fibonacci/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/Fibonacci/CMakeLists.txt (original) +++ llvm/trunk/examples/Fibonacci/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen) + add_llvm_example(Fibonacci fibonacci.cpp ) - -add_llvm_link_components(Fibonacci jit interpreter nativecodegen) Modified: llvm/trunk/examples/HowToUseJIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/HowToUseJIT/CMakeLists.txt (original) +++ llvm/trunk/examples/HowToUseJIT/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen) + add_llvm_example(HowToUseJIT HowToUseJIT.cpp ) - -add_llvm_link_components(HowToUseJIT jit interpreter nativecodegen) Modified: llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS core) + add_llvm_example(Kaleidoscope-Ch3 toy.cpp ) - -target_link_libraries(Kaleidoscope-Ch3 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,5 @@ +set(LLVM_LINK_COMPONENTS core jit interpreter native) + add_llvm_example(Kaleidoscope-Ch4 toy.cpp ) - -add_llvm_link_components(Kaleidoscope-Ch4 jit interpreter native) -target_link_libraries(Kaleidoscope-Ch4 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,5 @@ +set(LLVM_LINK_COMPONENTS core jit interpreter native) + add_llvm_example(Kaleidoscope-Ch5 toy.cpp ) - -add_llvm_link_components(Kaleidoscope-Ch5 jit interpreter native) -target_link_libraries(Kaleidoscope-Ch5 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,5 @@ +set(LLVM_LINK_COMPONENTS core jit interpreter native) + add_llvm_example(Kaleidoscope-Ch6 toy.cpp ) - -add_llvm_link_components(Kaleidoscope-Ch6 jit interpreter native) -target_link_libraries(Kaleidoscope-Ch6 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,5 @@ +set(LLVM_LINK_COMPONENTS core jit interpreter native) + add_llvm_example(Kaleidoscope-Ch7 toy.cpp ) - -add_llvm_link_components(Kaleidoscope-Ch7 jit interpreter native) -target_link_libraries(Kaleidoscope-Ch7 LLVMCore) Modified: llvm/trunk/examples/ModuleMaker/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ModuleMaker/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/ModuleMaker/CMakeLists.txt (original) +++ llvm/trunk/examples/ModuleMaker/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS bitwriter) + add_llvm_example(ModuleMaker ModuleMaker.cpp ) - -target_link_libraries(ModuleMaker LLVMBitWriter LLVMCore) Modified: llvm/trunk/examples/ParallelJIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ParallelJIT/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/examples/ParallelJIT/CMakeLists.txt (original) +++ llvm/trunk/examples/ParallelJIT/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,9 +1,9 @@ +set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen) + add_llvm_example(ParallelJIT ParallelJIT.cpp ) -add_llvm_link_components(ParallelJIT jit interpreter nativecodegen) - if(HAVE_LIBPTHREAD) target_link_libraries(ParallelJIT pthread) endif(HAVE_LIBPTHREAD) Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -50,4 +50,4 @@ ValueTracking.cpp ) -target_link_libraries(LLVMAnalysis LLVMCore LLVMTarget) +target_link_libraries (LLVMAnalysis LLVMSupport) Modified: llvm/trunk/lib/Analysis/IPA/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/IPA/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -4,5 +4,3 @@ FindUsedTypes.cpp GlobalsModRef.cpp ) - -target_link_libraries(LLVMipa LLVMAnalysis LLVMCore) Modified: llvm/trunk/lib/Archive/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Archive/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Archive/CMakeLists.txt (original) +++ llvm/trunk/lib/Archive/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -3,5 +3,3 @@ ArchiveReader.cpp ArchiveWriter.cpp ) - -target_link_libraries(LLVMArchive LLVMBitReader LLVMCore) Modified: llvm/trunk/lib/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/AsmParser/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -4,5 +4,3 @@ LLParser.cpp Parser.cpp ) - -target_link_libraries(LLVMAsmParser LLVMCore) Modified: llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt (original) +++ llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -2,5 +2,3 @@ BitReader.cpp BitcodeReader.cpp ) - -target_link_libraries(LLVMBitReader LLVMCore) Modified: llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -8,11 +8,4 @@ OcamlGCPrinter.cpp ) -target_link_libraries (LLVMAsmPrinter - LLVMAnalysis - LLVMCodeGen - LLVMCore - LLVMMC - LLVMMCParser - LLVMTarget - ) +target_link_libraries (LLVMAsmPrinter LLVMMCParser) Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -83,11 +83,4 @@ VirtRegRewriter.cpp ) -target_link_libraries (LLVMCodeGen - LLVMAnalysis - LLVMCore - LLVMMC - LLVMScalarOpts - LLVMTarget - LLVMTransformUtils - ) +target_link_libraries (LLVMCodeGen LLVMCore LLVMScalarOpts) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -22,10 +22,4 @@ TargetSelectionDAGInfo.cpp ) -target_link_libraries(LLVMSelectionDAG - LLVMAnalysis - LLVMCodeGen - LLVMCore - LLVMMC - LLVMTarget - ) +target_link_libraries (LLVMSelectionDAG LLVMAnalysis LLVMAsmPrinter LLVMCodeGen) Modified: llvm/trunk/lib/CompilerDriver/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/CMakeLists.txt (original) +++ llvm/trunk/lib/CompilerDriver/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,3 +1,4 @@ +set(LLVM_LINK_COMPONENTS support system) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvmc Modified: llvm/trunk/lib/ExecutionEngine/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -2,5 +2,3 @@ ExecutionEngine.cpp ExecutionEngineBindings.cpp ) - -target_link_libraries(LLVMExecutionEngine LLVMCore LLVMTarget) Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -3,10 +3,3 @@ ExternalFunctions.cpp Interpreter.cpp ) - -target_link_libraries(LLVMInterpreter - LLVMCodeGen - LLVMCore - LLVMExecutionEngine - LLVMTarget - ) Modified: llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -11,11 +11,3 @@ OProfileJITEventListener.cpp TargetSelect.cpp ) - -target_link_libraries(LLVMJIT - LLVMCodeGen - LLVMCore - LLVMExecutionEngine - LLVMMC - LLVMTarget - ) Modified: llvm/trunk/lib/Linker/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Linker/CMakeLists.txt (original) +++ llvm/trunk/lib/Linker/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -4,10 +4,3 @@ LinkModules.cpp Linker.cpp ) - -target_link_libraries(LLVMLinker - LLVMArchive - LLVMBitReader - LLVMCore - LLVMTransformUtils - ) Modified: llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,8 +1,7 @@ + add_llvm_library(LLVMMCDisassembler EDDisassembler.cpp EDOperand.cpp EDInst.cpp EDToken.cpp ) - -add_llvm_link_components(LLVMMCDisassembler all) Modified: llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -5,9 +5,3 @@ ARMAsmParser.cpp ) -target_link_libraries(LLVMARMAsmParser - LLVMARMInfo - LLVMMC - LLVMMCParser - LLVMTarget - ) Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -3,6 +3,4 @@ add_llvm_library(LLVMARMAsmPrinter ARMInstPrinter.cpp ) - add_dependencies(LLVMARMAsmPrinter ARMCodeGenTable_gen) -target_link_libraries(LLVMARMAsmPrinter LLVMMC) Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -46,13 +46,4 @@ Thumb2SizeReduction.cpp ) -target_link_libraries (LLVMARMCodeGen - LLVMARMInfo - LLVMAnalysis - LLVMAsmPrinter - LLVMCodeGen - LLVMCore - LLVMMC - LLVMSelectionDAG - LLVMTarget - ) +target_link_libraries (LLVMARMCodeGen LLVMARMAsmPrinter LLVMSelectionDAG) Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -13,5 +13,3 @@ TargetRegisterInfo.cpp TargetSubtarget.cpp ) - -target_link_libraries(LLVMTarget LLVMCore LLVMMC) Modified: llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -4,11 +4,4 @@ X86AsmLexer.cpp X86AsmParser.cpp ) - add_dependencies(LLVMX86AsmParser X86CodeGenTable_gen) -target_link_libraries(LLVMX86AsmParser - LLVMMC - LLVMMCParser - LLVMTarget - LLVMX86Info - ) Modified: llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -5,6 +5,4 @@ X86IntelInstPrinter.cpp X86InstComments.cpp ) - add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen) -target_link_libraries(LLVMX86AsmPrinter LLVMMC) Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -29,7 +29,7 @@ X86InstrInfo.cpp X86JITInfo.cpp X86MCAsmInfo.cpp - X86MCCodeEmitter.cpp + X86MCCodeEmitter.cpp X86MCInstLower.cpp X86RegisterInfo.cpp X86SelectionDAGInfo.cpp @@ -49,14 +49,4 @@ endif() add_llvm_target(X86CodeGen ${sources}) -target_link_libraries(LLVMX86CodeGen - LLVMAnalysis - LLVMAsmPrinter - LLVMCodeGen - LLVMCore - LLVMMC - LLVMSelectionDAG - LLVMTarget - LLVMX86AsmPrinter - LLVMX86Info - ) + Modified: llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -11,6 +11,4 @@ PROPERTY COMPILE_FLAGS "/Od" ) endif() - add_dependencies(LLVMX86Disassembler X86CodeGenTable_gen) -target_link_libraries(LLVMX86Disassembler LLVMMC LLVMX86Info) Modified: llvm/trunk/lib/Transforms/IPO/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/IPO/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -24,11 +24,4 @@ StructRetPromotion.cpp ) -target_link_libraries(LLVMipo - LLVMAnalysis - LLVMCore - LLVMScalarOpts - LLVMTarget - LLVMTransformUtils - LLVMipa - ) +target_link_libraries (LLVMipo LLVMScalarOpts LLVMInstCombine) Modified: llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -9,14 +9,9 @@ InstCombineMulDivRem.cpp InstCombinePHI.cpp InstCombineSelect.cpp - InstCombineShifts.cpp + InstCombineShifts.cpp InstCombineSimplifyDemanded.cpp InstCombineVectorOps.cpp ) -target_link_libraries(LLVMInstCombine - LLVMAnalysis - LLVMCore - LLVMTarget - LLVMTransformUtils - ) +target_link_libraries (LLVMInstCombine LLVMTransformUtils) Modified: llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -3,9 +3,3 @@ OptimalEdgeProfiling.cpp ProfilingUtils.cpp ) - -target_link_libraries(LLVMInstrumentation - LLVMAnalysis - LLVMCore - LLVMTransformUtils - ) Modified: llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -32,10 +32,4 @@ TailRecursionElimination.cpp ) -target_link_libraries (LLVMScalarOpts - LLVMAnalysis - LLVMCore - LLVMInstCombine - LLVMTarget - LLVMTransformUtils - ) +target_link_libraries (LLVMScalarOpts LLVMTransformUtils) Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -25,9 +25,4 @@ ValueMapper.cpp ) -target_link_libraries(LLVMTransformUtils - LLVMAnalysis - LLVMCore - LLVMTarget - LLVMipa - ) +target_link_libraries (LLVMTransformUtils LLVMSupport) Modified: llvm/trunk/tools/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/CMakeLists.txt (original) +++ llvm/trunk/tools/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -2,6 +2,15 @@ # large and three small executables. This is done to minimize memory load # in parallel builds. Please retain this ordering. +if( NOT WIN32 OR MSYS OR CYGWIN ) + # It is useful to build llvm-config before the other tools, so we + # have a fresh LibDeps.txt for regenerating the hard-coded library + # dependencies. llvm-config/CMakeLists.txt takes care of this but we + # must keep llvm-config as the first entry on the list of tools to + # be built. + add_subdirectory(llvm-config) +endif() + add_subdirectory(opt) add_subdirectory(llvm-as) add_subdirectory(llvm-dis) @@ -29,4 +38,6 @@ if( EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/clang/CMakeLists.txt ) add_subdirectory( ${CMAKE_CURRENT_SOURCE_DIR}/clang ) -endif() +endif( EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/clang/CMakeLists.txt ) + +set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} PARENT_SCOPE) Modified: llvm/trunk/tools/bugpoint/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/CMakeLists.txt (original) +++ llvm/trunk/tools/bugpoint/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,3 +1,6 @@ +set(LLVM_LINK_COMPONENTS asmparser instrumentation scalaropts ipo + linker bitreader bitwriter) + add_llvm_tool(bugpoint BugDriver.cpp CrashDebugger.cpp @@ -9,13 +12,3 @@ ToolRunner.cpp bugpoint.cpp ) - -target_link_libraries(bugpoint - LLVMAsmParser - LLVMInstrumentation - LLVMScalarOpts - LLVMipo - LLVMLinker - LLVMBitReader - LLVMBitWriter - ) Modified: llvm/trunk/tools/llc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llc/CMakeLists.txt (original) +++ llvm/trunk/tools/llc/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,5 @@ +set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} bitreader asmparser) + add_llvm_tool(llc llc.cpp ) - -add_llvm_link_components(llc all) -target_link_libraries(llc LLVMBitReader LLVMAsmParser) Modified: llvm/trunk/tools/lli/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/lli/CMakeLists.txt (original) +++ llvm/trunk/tools/lli/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,5 @@ +set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen bitreader selectiondag) + add_llvm_tool(lli lli.cpp ) - -add_llvm_link_components(lli jit interpreter nativecodegen) -target_link_libraries(lli LLVMBitReader LLVMSelectionDAG) Modified: llvm/trunk/tools/llvm-ar/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ar/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ar/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-ar/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,9 +1,8 @@ +set(LLVM_LINK_COMPONENTS archive) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-ar llvm-ar.cpp ) -target_link_libraries(llvm-ar LLVMArchive) - # TODO: Support check-local. Modified: llvm/trunk/tools/llvm-as/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-as/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-as/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-as/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,7 +1,6 @@ +set(LLVM_LINK_COMPONENTS asmparser bitwriter) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-as llvm-as.cpp ) - -target_link_libraries(llvm-as LLVMAsmParser LLVMBitWriter) Modified: llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,7 +1,6 @@ +set(LLVM_LINK_COMPONENTS bitreader) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-bcanalyzer llvm-bcanalyzer.cpp ) - -target_link_libraries(llvm-bcanalyzer LLVMBitReader) Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-config/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-config/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -110,6 +110,10 @@ add_dependencies(llvm-config.target ${llvm_lib_targets}) +# Make sure that llvm-config builds before the llvm tools, so we have +# LibDeps.txt and can use it for updating the hard-coded library +# dependencies on cmake/modules/LLVMLibDeps.cmake when the tools' +# build fail due to outdated dependencies: set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} llvm-config.target) install(FILES ${LLVM_CONFIG} @@ -118,4 +122,25 @@ DESTINATION bin) +# Regeneration of library dependencies. + +# See the comments at the end of cmake/modules/LLVMConfig.cmake for +# notes and guidelines. + +set(LLVMLibDeps ${LLVM_MAIN_SRC_DIR}/cmake/modules/LLVMLibDeps.cmake) +set(LLVMLibDeps_TMP ${CMAKE_CURRENT_BINARY_DIR}/LLVMLibDeps.cmake.tmp) + +add_custom_command(OUTPUT ${LLVMLibDeps_TMP} + COMMAND sed -e s'@\\.a@@g' -e s'@\\.so@@g' -e 's at libLLVM@LLVM at g' -e 's@: @ @' -e 's@\\\(.*\\\)@set\(MSVC_LIB_DEPS_\\1\)@' ${FINAL_LIBDEPS} > ${LLVMLibDeps_TMP} + COMMAND ${CMAKE_COMMAND} -E copy_if_different ${LLVMLibDeps_TMP} ${LLVMLibDeps} + DEPENDS ${FINAL_LIBDEPS} + COMMENT "Updating cmake library dependencies file ${LLVMLibDeps}" + ) + +if( LLVM_TARGETS_TO_BUILD STREQUAL LLVM_ALL_TARGETS ) + add_custom_target(llvmlibdeps.target ALL DEPENDS ${LLVMLibDeps_TMP}) + add_dependencies(llvmlibdeps.target llvm-config.target) + set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} llvmlibdeps.target) +endif() + set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} PARENT_SCOPE) Modified: llvm/trunk/tools/llvm-diff/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-diff/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,6 +1,6 @@ +set(LLVM_LINK_COMPONENTS support asmparser bitreader) + add_llvm_tool(llvm-diff llvm-diff.cpp DifferenceEngine.cpp ) - -target_link_libraries(llvm-diff LLVMAsmParser LLVMBitReader) Modified: llvm/trunk/tools/llvm-dis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-dis/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-dis/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,7 +1,6 @@ +set(LLVM_LINK_COMPONENTS bitreader) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-dis llvm-dis.cpp ) - -target_link_libraries(llvm-dis LLVMCore LLVMBitReader) Modified: llvm/trunk/tools/llvm-extract/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-extract/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-extract/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-extract/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,10 +1,5 @@ +set(LLVM_LINK_COMPONENTS asmparser ipo bitreader bitwriter) + add_llvm_tool(llvm-extract llvm-extract.cpp ) - -target_link_libraries(llvm-extract - LLVMAsmParser - LLVMipo - LLVMBitReader - LLVMBitWriter - ) Modified: llvm/trunk/tools/llvm-ld/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ld/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-ld/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,12 +1,6 @@ +set(LLVM_LINK_COMPONENTS ipo scalaropts linker archive bitwriter) + add_llvm_tool(llvm-ld Optimize.cpp llvm-ld.cpp ) - -target_link_libraries(llvm-ld - LLVMipo - LLVMScalarOpts - LLVMLinker - LLVMArchive - LLVMBitWriter - ) Modified: llvm/trunk/tools/llvm-link/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-link/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-link/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-link/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,10 +1,5 @@ +set(LLVM_LINK_COMPONENTS linker bitreader bitwriter asmparser) + add_llvm_tool(llvm-link llvm-link.cpp ) - -target_link_libraries(llvm-link - LLVMLinker - LLVMBitReader - LLVMBitWriter - LLVMAsmParser - ) Modified: llvm/trunk/tools/llvm-mc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-mc/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,7 +1,6 @@ +set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} support MC MCParser MCDisassembler) + add_llvm_tool(llvm-mc llvm-mc.cpp Disassembler.cpp ) - -add_llvm_link_components(llvm-mc all) -target_link_libraries(llvm-mc LLVMMC LLVMMCParser LLVMMCDisassembler) Modified: llvm/trunk/tools/llvm-nm/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-nm/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-nm/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS archive bitreader) + add_llvm_tool(llvm-nm llvm-nm.cpp ) - -target_link_libraries(llvm-nm LLVMArchive LLVMBitReader) Modified: llvm/trunk/tools/llvm-prof/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-prof/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-prof/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-prof/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,5 +1,5 @@ +set(LLVM_LINK_COMPONENTS bitreader analysis) + add_llvm_tool(llvm-prof llvm-prof.cpp ) - -target_link_libraries(llvm-prof LLVMBitReader LLVMAnalysis) Modified: llvm/trunk/tools/llvm-ranlib/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ranlib/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ranlib/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-ranlib/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,7 +1,6 @@ +set(LLVM_LINK_COMPONENTS archive) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-ranlib llvm-ranlib.cpp ) - -target_link_libraries(llvm-ranlib LLVMArchive) Modified: llvm/trunk/tools/opt/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/CMakeLists.txt?rev=113819&r1=113818&r2=113819&view=diff ============================================================================== --- llvm/trunk/tools/opt/CMakeLists.txt (original) +++ llvm/trunk/tools/opt/CMakeLists.txt Mon Sep 13 18:59:48 2010 @@ -1,15 +1,8 @@ +set(LLVM_LINK_COMPONENTS bitreader asmparser bitwriter instrumentation scalaropts ipo) + add_llvm_tool(opt AnalysisWrappers.cpp GraphPrinters.cpp PrintSCC.cpp opt.cpp ) - -target_link_libraries(opt - LLVMBitReader - LLVMAsmParser - LLVMBitWriter - LLVMInstrumentation - LLVMScalarOpts - LLVMipo - ) From sabre at nondot.org Mon Sep 13 19:19:00 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 14 Sep 2010 00:19:00 -0000 Subject: [llvm-commits] [llvm] r113820 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/crash.ll Message-ID: <20100914001900.84F5C2A6C12C@llvm.org> Author: lattner Date: Mon Sep 13 19:19:00 2010 New Revision: 113820 URL: http://llvm.org/viewvc/llvm-project?rev=113820&view=rev Log: fix PR8102, a case where we'd copyValue from a value that we already deleted. Fix this by doing the copyValue's before we delete stuff! The testcase only repros the problem on my system with valgrind. Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/test/Transforms/LICM/crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=113820&r1=113819&r2=113820&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Mon Sep 13 19:19:00 2010 @@ -837,6 +837,17 @@ ReplacedLoads[ALoad] = NewVal; } + // If the preheader load is itself a pointer, we need to tell alias analysis + // about the new pointer we created in the preheader block and about any PHI + // nodes that just got inserted. + if (PreheaderLoad->getType()->isPointerTy()) { + // Copy any value stored to or loaded from a must-alias of the pointer. + CurAST->copyValue(SomeValue, PreheaderLoad); + + for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i) + CurAST->copyValue(SomeValue, NewPHIs[i]); + } + // Now that everything is rewritten, delete the old instructions from the body // of the loop. They should all be dead now. for (unsigned i = 0, e = LoopUses.size(); i != e; ++i) { @@ -867,17 +878,6 @@ User->eraseFromParent(); } - // If the preheader load is itself a pointer, we need to tell alias analysis - // about the new pointer we created in the preheader block and about any PHI - // nodes that just got inserted. - if (PreheaderLoad->getType()->isPointerTy()) { - // Copy any value stored to or loaded from a must-alias of the pointer. - CurAST->copyValue(SomeValue, PreheaderLoad); - - for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i) - CurAST->copyValue(SomeValue, NewPHIs[i]); - } - // fwew, we're done! } Modified: llvm/trunk/test/Transforms/LICM/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/crash.ll?rev=113820&r1=113819&r2=113820&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/crash.ll (original) +++ llvm/trunk/test/Transforms/LICM/crash.ll Mon Sep 13 19:19:00 2010 @@ -39,3 +39,23 @@ store i32 undef, i32* @g_8, align 4 br label %for.body } + +; PR8102 +define void @test3() { +entry: + %__first = alloca { i32* } + br i1 undef, label %for.cond, label %for.end + +for.cond: ; preds = %for.cond, %entry + %tmp1 = getelementptr { i32*}* %__first, i32 0, i32 0 + %tmp2 = load i32** %tmp1, align 4 + %call = tail call i32* @test3helper(i32* %tmp2) + %tmp3 = getelementptr { i32*}* %__first, i32 0, i32 0 + store i32* %call, i32** %tmp3, align 4 + br i1 false, label %for.cond, label %for.end + +for.end: ; preds = %for.cond, %entry + ret void +} + +declare i32* @test3helper(i32*) From stoklund at 2pi.dk Mon Sep 13 19:51:58 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 14 Sep 2010 00:51:58 -0000 Subject: [llvm-commits] [llvm] r113824 - /llvm/trunk/unittests/ADT/APIntTest.cpp Message-ID: <20100914005158.8407D2A6C12C@llvm.org> Author: stoklund Date: Mon Sep 13 19:51:58 2010 New Revision: 113824 URL: http://llvm.org/viewvc/llvm-project?rev=113824&view=rev Log: Attempt to unbreak the FreeBSD buildbot by XFAILing a unit test that seems to be miscompiled by the system gcc-4.2.1 The test remains enabled for the second-stage test. Modified: llvm/trunk/unittests/ADT/APIntTest.cpp Modified: llvm/trunk/unittests/ADT/APIntTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/APIntTest.cpp?rev=113824&r1=113823&r2=113824&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/APIntTest.cpp (original) +++ llvm/trunk/unittests/ADT/APIntTest.cpp Mon Sep 13 19:51:58 2010 @@ -39,6 +39,9 @@ EXPECT_EQ(-1, Minus1.getSExtValue()); } +// XFAIL this test on FreeBSD where the system gcc-4.2.1 seems to miscompile it. +#if defined(__llvm__) || !defined(__FreeBSD__) + TEST(APIntTest, i33_Count) { APInt i33minus2(33, static_cast(-2), true); EXPECT_EQ(0u, i33minus2.countLeadingZeros()); @@ -50,6 +53,8 @@ EXPECT_EQ(((uint64_t)-2)&((1ull<<33) -1), i33minus2.getZExtValue()); } +#endif + TEST(APIntTest, i65_Count) { APInt i65minus(65, 0, true); i65minus.set(64); From echristo at apple.com Mon Sep 13 20:18:15 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 14 Sep 2010 01:18:15 -0000 Subject: [llvm-commits] [llvm] r113827 - /llvm/trunk/include/llvm/Constant.h Message-ID: <20100914011815.7A3422A6C12C@llvm.org> Author: echristo Date: Mon Sep 13 20:18:15 2010 New Revision: 113827 URL: http://llvm.org/viewvc/llvm-project?rev=113827&view=rev Log: Remove apparently unnecessary forward declaration. Modified: llvm/trunk/include/llvm/Constant.h Modified: llvm/trunk/include/llvm/Constant.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constant.h?rev=113827&r1=113826&r2=113827&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constant.h (original) +++ llvm/trunk/include/llvm/Constant.h Mon Sep 13 20:18:15 2010 @@ -20,7 +20,6 @@ class APInt; template class SmallVectorImpl; - class LLVMContext; /// This is an important base class in LLVM. It provides the common facilities /// of all constant values in an LLVM program. A constant is a value that is From gohman at apple.com Mon Sep 13 20:37:57 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 14 Sep 2010 01:37:57 -0000 Subject: [llvm-commits] [llvm] r113828 - /llvm/trunk/lib/VMCore/Metadata.cpp Message-ID: <20100914013757.DF6102A6C12C@llvm.org> Author: djg Date: Mon Sep 13 20:37:57 2010 New Revision: 113828 URL: http://llvm.org/viewvc/llvm-project?rev=113828&view=rev Log: When a function-local value with function-local metadata uses gets RAUWed with a non-function-local value, it may result in the metadata no longer needing to be function-local. Check for this condition, and clear the isFunctionLocal flag, if it's still in the uniquing map, since any node in the uniquing map needs to have an accurate function-local flag. Also, add an assert to help catch problematic cases. Modified: llvm/trunk/lib/VMCore/Metadata.cpp Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=113828&r1=113827&r2=113828&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Mon Sep 13 20:37:57 2010 @@ -354,6 +354,22 @@ // InsertPoint will have been set by the FindNodeOrInsertPos call. pImpl->MDNodeSet.InsertNode(this, InsertPoint); + + // If this MDValue was previously function-local but no longer is, clear + // its function-local flag. + if (isFunctionLocal() && !isFunctionLocalValue(To)) { + bool isStillFunctionLocal = false; + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + Value *V = getOperand(i); + if (!V) continue; + if (isFunctionLocalValue(V)) { + isStillFunctionLocal = true; + break; + } + } + if (!isStillFunctionLocal) + setValueSubclassData(getSubclassDataFromValue() & ~FunctionLocalBit); + } } //===----------------------------------------------------------------------===// @@ -387,6 +403,8 @@ /// addOperand - Add metadata Operand. void NamedMDNode::addOperand(MDNode *M) { + assert(!M->isFunctionLocal() && + "NamedMDNode operands must not be function-local!"); getNMDOps(Operands).push_back(TrackingVH(M)); } From geek4civic at gmail.com Mon Sep 13 22:34:17 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 14 Sep 2010 12:34:17 +0900 Subject: [llvm-commits] [PATCH][EXPERIMENTAL] Building LLVMgold.dll In-Reply-To: References: Message-ID: Eric, Thank you to give comments. I apologize to disclose a patch without any comments. I will post one again when I resolved dependency issue. > - ?# No support for dynamic libraries on windows targets. > - ?ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW)) > > Do we now support building libLTO and gold as static libraries or do dynamic libraries now work? We can build libLTO.a, LTO.dll and LLVMgold.dll(with binutils), both ENABLE_SHARED=1 and 0 with this patch. libLLVMgold.a is not built on ToT. I don't know yet whether DLLs would work or not. > ? ? # gold only builds if binutils is around. ?It requires "lto" to build before > ? ? # it so it is added to DIRS. > ? ? ifdef BINUTILS_INCDIR > - ? ? ?DIRS += lto gold > + ? ? ?DIRS += lto > + ? ? ?PARALLEL_DIRS += gold > > Either the code is wrong or the comment is wrong :) I believe code might be right. Either lto or gold can be added to parallel set. But I know it is not needed with this patch and I will split away it at next. > OK, I see how you're getting around the dynamic library thing: (see below) > Eeew. ?Can you give an explanation? There has to be a better way of doing this. > -LIBS += -llto I didn't know who creates liblto.(a|so|dylib). Is it needed? > +ifneq (,$(filter $(HOST_OS), Cygwin MingW)) > + ?ifneq ($(ENABLE_SHARED),1) > + ? ?LINK_COMPONENTS += $(TARGETS_TO_BUILD) ipo scalaropts linker bitreader bitwriter > + ?endif > +endif On ENABLE_SHARED=0, LLVMgold.dll should be monolithic and independent from LTO.dll. Since llvm-config does not handle dependency of libLTO, I had to add some components from tool/lto/Makefile. "How huge we are!" 15047789 Sep 10 17:57 LLVMgold.dll 15034550 Sep 10 17:57 LTO.dll > Anyhow, I think the patch needs some explanation of what you're trying to do and why. Ok I see. Please review again when next patch comes! thanks...Takumi From bigcheesegs at gmail.com Mon Sep 13 23:27:26 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 14 Sep 2010 04:27:26 -0000 Subject: [llvm-commits] [llvm] r113833 - /llvm/trunk/lib/Target/CBackend/CBackend.cpp Message-ID: <20100914042726.CB0282A6C12C@llvm.org> Author: mspencer Date: Mon Sep 13 23:27:26 2010 New Revision: 113833 URL: http://llvm.org/viewvc/llvm-project?rev=113833&view=rev Log: CBackend: Cleanup whitespace before I do this next commit. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=113833&r1=113832&r2=113833&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Sep 13 23:27:26 2010 @@ -52,7 +52,7 @@ #include using namespace llvm; -extern "C" void LLVMInitializeCBackendTarget() { +extern "C" void LLVMInitializeCBackendTarget() { // Register the target. RegisterTargetMachine X(TheCBackendTarget); } @@ -72,7 +72,7 @@ class CBackendNameAllUsedStructsAndMergeFunctions : public ModulePass { public: static char ID; - CBackendNameAllUsedStructsAndMergeFunctions() + CBackendNameAllUsedStructsAndMergeFunctions() : ModulePass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); @@ -110,7 +110,7 @@ public: static char ID; explicit CWriter(formatted_raw_ostream &o) - : FunctionPass(ID), Out(o), IL(0), Mang(0), LI(0), + : FunctionPass(ID), Out(o), IL(0), Mang(0), LI(0), TheModule(0), TAsm(0), TCtx(0), TD(0), OpaqueCounter(0), NextAnonValueNumber(0) { FPCounter = 0; @@ -183,7 +183,7 @@ Out << ")"; } } - + void writeOperand(Value *Operand, bool Static = false); void writeInstComputationInline(Instruction &I); void writeOperandInternal(Value *Operand, bool Static = false); @@ -224,7 +224,7 @@ return ByValParams.count(A); return isa(V) || isDirectAlloca(V); } - + // isInlinableInst - Attempt to inline instructions into their uses to build // trees as much as possible. To do this, we have to consistently decide // what is acceptable to inline, so that variable declarations don't get @@ -233,7 +233,7 @@ static bool isInlinableInst(const Instruction &I) { // Always inline cmp instructions, even if they are shared by multiple // expressions. GCC generates horrible code if we don't. - if (isa(I)) + if (isa(I)) return true; // Must be an expression, must be used exactly once. If it is dead, we @@ -270,14 +270,14 @@ return 0; return AI; } - + // isInlineAsm - Check if the instruction is a call to an inline asm chunk static bool isInlineAsm(const Instruction& I) { if (const CallInst *CI = dyn_cast(&I)) return isa(CI->getCalledValue()); return false; } - + // Instruction visitation functions friend class InstVisitor; @@ -310,7 +310,7 @@ void visitStoreInst (StoreInst &I); void visitGetElementPtrInst(GetElementPtrInst &I); void visitVAArgInst (VAArgInst &I); - + void visitInsertElementInst(InsertElementInst &I); void visitExtractElementInst(ExtractElementInst &I); void visitShuffleVectorInst(ShuffleVectorInst &SVI); @@ -346,7 +346,7 @@ static std::string CBEMangle(const std::string &S) { std::string Result; - + for (unsigned i = 0, e = S.size(); i != e; ++i) if (isalnum(S[i]) || S[i] == '_') { Result += S[i]; @@ -375,7 +375,7 @@ for (TypeSymbolTable::iterator TI = TST.begin(), TE = TST.end(); TI != TE; ) { TypeSymbolTable::iterator I = TI++; - + // If this isn't a struct or array type, remove it from our set of types // to name. This simplifies emission later. if (!I->second->isStructTy() && !I->second->isOpaqueTy() && @@ -403,8 +403,8 @@ ++RenameCounter; Changed = true; } - - + + // Loop over all external functions and globals. If we have two with // identical names, merge them. // FIXME: This code should disappear when we don't allow values with the same @@ -440,7 +440,7 @@ } } } - + return Changed; } @@ -479,20 +479,20 @@ FunctionInnards << "void"; } FunctionInnards << ')'; - printType(Out, RetTy, + printType(Out, RetTy, /*isSigned=*/PAL.paramHasAttr(0, Attribute::SExt), FunctionInnards.str()); } raw_ostream & CWriter::printSimpleType(raw_ostream &Out, const Type *Ty, bool isSigned, const std::string &NameSoFar) { - assert((Ty->isPrimitiveType() || Ty->isIntegerTy() || Ty->isVectorTy()) && + assert((Ty->isPrimitiveType() || Ty->isIntegerTy() || Ty->isVectorTy()) && "Invalid type for printSimpleType"); switch (Ty->getTypeID()) { case Type::VoidTyID: return Out << "void " << NameSoFar; case Type::IntegerTyID: { unsigned NumBits = cast(Ty)->getBitWidth(); - if (NumBits == 1) + if (NumBits == 1) return Out << "bool " << NameSoFar; else if (NumBits <= 8) return Out << (isSigned?"signed":"unsigned") << " char " << NameSoFar; @@ -502,7 +502,7 @@ return Out << (isSigned?"signed":"unsigned") << " int " << NameSoFar; else if (NumBits <= 64) return Out << (isSigned?"signed":"unsigned") << " long long "<< NameSoFar; - else { + else { assert(NumBits <= 128 && "Bit widths > 128 not implemented yet"); return Out << (isSigned?"llvmInt128":"llvmUInt128") << " " << NameSoFar; } @@ -525,7 +525,7 @@ " __attribute__((vector_size(" + utostr(TD->getTypeAllocSize(VTy)) + " ))) " + NameSoFar); } - + default: #ifndef NDEBUG errs() << "Unknown primitive type: " << *Ty << "\n"; @@ -579,7 +579,7 @@ FunctionInnards << "void"; } FunctionInnards << ')'; - printType(Out, FTy->getReturnType(), + printType(Out, FTy->getReturnType(), /*isSigned=*/PAL.paramHasAttr(0, Attribute::SExt), FunctionInnards.str()); return Out; } @@ -763,7 +763,7 @@ } /// Print out the casting for a cast operation. This does the double casting -/// necessary for conversion to the destination type, if necessary. +/// necessary for conversion to the destination type, if necessary. /// @brief Print a cast void CWriter::printCast(unsigned opc, const Type *SrcTy, const Type *DstTy) { // Print the destination type cast @@ -786,7 +786,7 @@ printSimpleType(Out, DstTy, false); Out << ')'; break; - case Instruction::SExt: + case Instruction::SExt: case Instruction::FPToSI: // For these, make sure we get a signed dest Out << '('; printSimpleType(Out, DstTy, true); @@ -807,7 +807,7 @@ case Instruction::SIToFP: case Instruction::SExt: Out << '('; - printSimpleType(Out, SrcTy, true); + printSimpleType(Out, SrcTy, true); Out << ')'; break; case Instruction::IntToPtr: @@ -899,7 +899,7 @@ case Instruction::AShr: { Out << '('; - bool NeedsClosingParens = printConstExprCast(CE, Static); + bool NeedsClosingParens = printConstExprCast(CE, Static); printConstantWithCast(CE->getOperand(0), CE->getOpcode()); switch (CE->getOpcode()) { case Instruction::Add: @@ -909,10 +909,10 @@ case Instruction::Mul: case Instruction::FMul: Out << " * "; break; case Instruction::URem: - case Instruction::SRem: + case Instruction::SRem: case Instruction::FRem: Out << " % "; break; - case Instruction::UDiv: - case Instruction::SDiv: + case Instruction::UDiv: + case Instruction::SDiv: case Instruction::FDiv: Out << " / "; break; case Instruction::And: Out << " & "; break; case Instruction::Or: Out << " | "; break; @@ -924,7 +924,7 @@ switch (CE->getPredicate()) { case ICmpInst::ICMP_EQ: Out << " == "; break; case ICmpInst::ICMP_NE: Out << " != "; break; - case ICmpInst::ICMP_SLT: + case ICmpInst::ICMP_SLT: case ICmpInst::ICMP_ULT: Out << " < "; break; case ICmpInst::ICMP_SLE: case ICmpInst::ICMP_ULE: Out << " <= "; break; @@ -944,8 +944,8 @@ return; } case Instruction::FCmp: { - Out << '('; - bool NeedsClosingParens = printConstExprCast(CE, Static); + Out << '('; + bool NeedsClosingParens = printConstExprCast(CE, Static); if (CE->getPredicate() == FCmpInst::FCMP_FALSE) Out << "0"; else if (CE->getPredicate() == FCmpInst::FCMP_TRUE) @@ -1010,18 +1010,18 @@ else { Out << "(("; printSimpleType(Out, Ty, false) << ')'; - if (CI->isMinValue(true)) + if (CI->isMinValue(true)) Out << CI->getZExtValue() << 'u'; else Out << CI->getSExtValue(); Out << ')'; } return; - } + } switch (CPV->getType()->getTypeID()) { case Type::FloatTyID: - case Type::DoubleTyID: + case Type::DoubleTyID: case Type::X86_FP80TyID: case Type::PPC_FP128TyID: case Type::FP128TyID: { @@ -1031,8 +1031,8 @@ // Because of FP precision problems we must load from a stack allocated // value that holds the value in hex. Out << "(*(" << (FPC->getType() == Type::getFloatTy(CPV->getContext()) ? - "float" : - FPC->getType() == Type::getDoubleTy(CPV->getContext()) ? + "float" : + FPC->getType() == Type::getDoubleTy(CPV->getContext()) ? "double" : "long double") << "*)&FPConstant" << I->second << ')'; @@ -1051,7 +1051,7 @@ Tmp.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &LosesInfo); V = Tmp.convertToDouble(); } - + if (IsNAN(V)) { // The value is NaN @@ -1215,10 +1215,10 @@ // We need to cast integer arithmetic so that it is always performed // as unsigned, to avoid undefined behavior on overflow. case Instruction::LShr: - case Instruction::URem: + case Instruction::URem: case Instruction::UDiv: NeedsExplicitCast = true; break; case Instruction::AShr: - case Instruction::SRem: + case Instruction::SRem: case Instruction::SDiv: NeedsExplicitCast = true; TypeIsSigned = true; break; case Instruction::SExt: Ty = CE->getType(); @@ -1271,7 +1271,7 @@ switch (Opcode) { default: // for most instructions, it doesn't matter - break; + break; case Instruction::Add: case Instruction::Sub: case Instruction::Mul: @@ -1298,7 +1298,7 @@ Out << ")"; printConstant(CPV, false); Out << ")"; - } else + } else printConstant(CPV, false); } @@ -1316,16 +1316,16 @@ Mang->getNameWithPrefix(Str, GV, false); return CBEMangle(Str.str().str()); } - + std::string Name = Operand->getName(); - + if (Name.empty()) { // Assign unique names to local temporaries. unsigned &No = AnonValueNumbers[Operand]; if (No == 0) No = ++NextAnonValueNumber; Name = "tmp__" + utostr(No); } - + std::string VarName; VarName.reserve(Name.capacity()); @@ -1352,7 +1352,7 @@ // Validate this. const Type *Ty = I.getType(); if (Ty->isIntegerTy() && (Ty!=Type::getInt1Ty(I.getContext()) && - Ty!=Type::getInt8Ty(I.getContext()) && + Ty!=Type::getInt8Ty(I.getContext()) && Ty!=Type::getInt16Ty(I.getContext()) && Ty!=Type::getInt32Ty(I.getContext()) && Ty!=Type::getInt64Ty(I.getContext()))) { @@ -1368,12 +1368,12 @@ if (I.getType() == Type::getInt1Ty(I.getContext()) && !isa(I) && !isa(I)) NeedBoolTrunc = true; - + if (NeedBoolTrunc) Out << "(("; - + visit(I); - + if (NeedBoolTrunc) Out << ")&1)"; } @@ -1408,9 +1408,9 @@ Out << ')'; } -// Some instructions need to have their result value casted back to the -// original types because their operands were casted to the expected type. -// This function takes care of detecting that case and printing the cast +// Some instructions need to have their result value casted back to the +// original types because their operands were casted to the expected type. +// This function takes care of detecting that case and printing the cast // for the Instruction. bool CWriter::writeInstructionCast(const Instruction &I) { const Type *Ty = I.getOperand(0)->getType(); @@ -1421,15 +1421,15 @@ // We need to cast integer arithmetic so that it is always performed // as unsigned, to avoid undefined behavior on overflow. case Instruction::LShr: - case Instruction::URem: - case Instruction::UDiv: + case Instruction::URem: + case Instruction::UDiv: Out << "(("; printSimpleType(Out, Ty, false); Out << ")("; return true; case Instruction::AShr: - case Instruction::SRem: - case Instruction::SDiv: + case Instruction::SRem: + case Instruction::SDiv: Out << "(("; printSimpleType(Out, Ty, true); Out << ")("; @@ -1441,7 +1441,7 @@ // Write the operand with a cast to another type based on the Opcode being used. // This will be used in cases where an instruction has specific type -// requirements (usually signedness) for its operands. +// requirements (usually signedness) for its operands. void CWriter::writeOperandWithCast(Value* Operand, unsigned Opcode) { // Extract the operand's type, we'll need it. @@ -1459,7 +1459,7 @@ switch (Opcode) { default: // for most instructions, it doesn't matter - break; + break; case Instruction::Add: case Instruction::Sub: case Instruction::Mul: @@ -1488,14 +1488,14 @@ Out << ")"; writeOperand(Operand); Out << ")"; - } else + } else writeOperand(Operand); } -// Write the operand with a cast to another type based on the icmp predicate -// being used. +// Write the operand with a cast to another type based on the icmp predicate +// being used. void CWriter::writeOperandWithCast(Value* Operand, const ICmpInst &Cmp) { - // This has to do a cast to ensure the operand has the right signedness. + // This has to do a cast to ensure the operand has the right signedness. // Also, if the operand is a pointer, we make sure to cast to an integer when // doing the comparison both for signedness and so that the C compiler doesn't // optimize things like "p < NULL" to false (p may contain an integer value @@ -1508,7 +1508,7 @@ writeOperand(Operand); return; } - + // Should this be a signed comparison? If so, convert to signed. bool castIsSigned = Cmp.isSigned(); @@ -1516,7 +1516,7 @@ const Type* OpTy = Operand->getType(); if (OpTy->isPointerTy()) OpTy = TD->getIntPtrType(Operand->getContext()); - + Out << "(("; printSimpleType(Out, OpTy, castIsSigned); Out << ")"; @@ -1583,7 +1583,7 @@ Out << "#if defined(__GNUC__)\n" << "#define __HIDDEN__ __attribute__((visibility(\"hidden\")))\n" << "#endif\n\n"; - + // Define NaN and Inf as GCC builtins if using GCC, as 0 otherwise // From the GCC documentation: // @@ -1639,7 +1639,7 @@ << "#define __ATTRIBUTE_DTOR__\n" << "#define LLVM_ASM(X)\n" << "#endif\n\n"; - + Out << "#if __GNUC__ < 4 /* Old GCC's, or compilers not GCC */ \n" << "#define __builtin_stack_save() 0 /* not implemented */\n" << "#define __builtin_stack_restore(X) /* noop */\n" @@ -1662,11 +1662,11 @@ static void FindStaticTors(GlobalVariable *GV, std::set &StaticTors){ ConstantArray *InitList = dyn_cast(GV->getInitializer()); if (!InitList) return; - + for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i) if (ConstantStruct *CS = dyn_cast(InitList->getOperand(i))){ if (CS->getNumOperands() != 2) return; // Not array of 2-element structs. - + if (CS->getOperand(1)->isNullValue()) return; // Found a null terminator, exit printing. Constant *FP = CS->getOperand(1); @@ -1694,12 +1694,12 @@ else if (GV->getName() == "llvm.global_dtors") return GlobalDtors; } - + // Otherwise, if it is other metadata, don't print it. This catches things // like debug information. if (GV->getSection() == "llvm.metadata") return NotPrinted; - + return NotSpecial; } @@ -1730,7 +1730,7 @@ bool CWriter::doInitialization(Module &M) { FunctionPass::doInitialization(M); - + // Initialize TheModule = &M; @@ -1742,11 +1742,11 @@ std::string Triple = TheModule->getTargetTriple(); if (Triple.empty()) Triple = llvm::sys::getHostTriple(); - + std::string E; if (const Target *Match = TargetRegistry::lookupTarget(Triple, E)) TAsm = Match->createAsmInfo(Triple); -#endif +#endif TAsm = new CBEMCAsmInfo(); TCtx = new MCContext(*TAsm); Mang = new Mangler(*TCtx, *TD); @@ -1766,7 +1766,7 @@ break; } } - + // get declaration for alloca Out << "/* Provide Declarations */\n"; Out << "#include \n"; // Varargs support @@ -1823,7 +1823,7 @@ for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { - if (I->hasExternalLinkage() || I->hasExternalWeakLinkage() || + if (I->hasExternalLinkage() || I->hasExternalWeakLinkage() || I->hasCommonLinkage()) Out << "extern "; else if (I->hasDLLImportLinkage()) @@ -1848,7 +1848,7 @@ Out << "double fmod(double, double);\n"; // Support for FP rem Out << "float fmodf(float, float);\n"; Out << "long double fmodl(long double, long double);\n"; - + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { // Don't print declarations for intrinsic functions. if (!I->isIntrinsic() && I->getName() != "setjmp" && @@ -1856,7 +1856,7 @@ if (I->hasExternalWeakLinkage()) Out << "extern "; printFunctionSignature(I, true); - if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) + if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) Out << " __ATTRIBUTE_WEAK__"; if (I->hasExternalWeakLinkage()) Out << " __EXTERNAL_WEAK__"; @@ -1866,10 +1866,10 @@ Out << " __ATTRIBUTE_DTOR__"; if (I->hasHiddenVisibility()) Out << " __HIDDEN__"; - + if (I->hasName() && I->getName()[0] == 1) Out << " LLVM_ASM(\"" << I->getName().substr(1) << "\")"; - + Out << ";\n"; } } @@ -1893,7 +1893,7 @@ if (I->isThreadLocal()) Out << "__thread "; - printType(Out, I->getType()->getElementType(), false, + printType(Out, I->getType()->getElementType(), false, GetValueName(I)); if (I->hasLinkOnceLinkage()) @@ -1913,7 +1913,7 @@ // Output the global variable definitions and contents... if (!M.global_empty()) { Out << "\n\n/* Global Variable Definitions and Initialization */\n"; - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) if (!I->isDeclaration()) { // Ignore special globals, such as debug info. @@ -1931,7 +1931,7 @@ if (I->isThreadLocal()) Out << "__thread "; - printType(Out, I->getType()->getElementType(), false, + printType(Out, I->getType()->getElementType(), false, GetValueName(I)); if (I->hasLinkOnceLinkage()) Out << " __attribute__((common))"; @@ -1942,7 +1942,7 @@ if (I->hasHiddenVisibility()) Out << " __HIDDEN__"; - + // If the initializer is not null, emit the initializer. If it is null, // we try to avoid emitting large amounts of zeros. The problem with // this, however, occurs when the variable has weak linkage. In this @@ -1976,7 +1976,7 @@ if (!M.empty()) Out << "\n\n/* Function Bodies */\n"; - // Emit some helper functions for dealing with FCMP instruction's + // Emit some helper functions for dealing with FCMP instruction's // predicates Out << "static inline int llvm_fcmp_ord(double X, double Y) { "; Out << "return X == X && Y == Y; }\n"; @@ -2031,7 +2031,7 @@ printFloatingPointConstants(CE->getOperand(i)); return; } - + // Otherwise, check for a FP constant that we need to print. const ConstantFP *FPC = dyn_cast(C); if (FPC == 0 || @@ -2042,7 +2042,7 @@ return; FPConstantMap[FPC] = FPCounter; // Number the FP constants - + if (FPC->getType() == Type::getDoubleTy(FPC->getContext())) { double Val = FPC->getValueAPF().convertToDouble(); uint64_t i = FPC->getValueAPF().bitcastToAPInt().getZExtValue(); @@ -2061,7 +2061,7 @@ APInt api = FPC->getValueAPF().bitcastToAPInt(); const uint64_t *p = api.getRawData(); Out << "static const ConstantFP80Ty FPConstant" << FPCounter++ - << " = { 0x" << utohexstr(p[0]) + << " = { 0x" << utohexstr(p[0]) << "ULL, 0x" << utohexstr((uint16_t)p[1]) << ",{0,0,0}" << "}; /* Long double constant */\n"; } else if (FPC->getType() == Type::getPPC_FP128Ty(FPC->getContext()) || @@ -2072,7 +2072,7 @@ << " = { 0x" << utohexstr(p[0]) << ", 0x" << utohexstr(p[1]) << "}; /* Long double constant */\n"; - + } else { llvm_unreachable("Unknown float type!"); } @@ -2144,12 +2144,12 @@ // Don't walk through pointers. if (Ty->isPointerTy() || Ty->isPrimitiveType() || Ty->isIntegerTy()) return; - + // Print all contained types first. for (Type::subtype_iterator I = Ty->subtype_begin(), E = Ty->subtype_end(); I != E; ++I) printContainedStructs(*I, StructPrinted); - + if (Ty->isStructTy() || Ty->isArrayTy()) { // Check to see if we have already printed this struct. if (StructPrinted.insert(Ty).second) { @@ -2164,10 +2164,10 @@ void CWriter::printFunctionSignature(const Function *F, bool Prototype) { /// isStructReturn - Should this function actually return a struct by-value? bool isStructReturn = F->hasStructRetAttr(); - + if (F->hasLocalLinkage()) Out << "static "; if (F->hasDLLImportLinkage()) Out << "__declspec(dllimport) "; - if (F->hasDLLExportLinkage()) Out << "__declspec(dllexport) "; + if (F->hasDLLExportLinkage()) Out << "__declspec(dllexport) "; switch (F->getCallingConv()) { case CallingConv::X86_StdCall: Out << "__attribute__((stdcall)) "; @@ -2181,7 +2181,7 @@ default: break; } - + // Loop over the arguments, printing them... const FunctionType *FT = cast(F->getFunctionType()); const AttrListPtr &PAL = F->getAttributes(); @@ -2197,7 +2197,7 @@ if (!F->arg_empty()) { Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); unsigned Idx = 1; - + // If this is a struct-return function, don't print the hidden // struct-return argument. if (isStructReturn) { @@ -2205,7 +2205,7 @@ ++I; ++Idx; } - + std::string ArgName; for (; I != E; ++I) { if (PrintedArg) FunctionInnards << ", "; @@ -2229,7 +2229,7 @@ // Loop over the arguments, printing them. FunctionType::param_iterator I = FT->param_begin(), E = FT->param_end(); unsigned Idx = 1; - + // If this is a struct-return function, don't print the hidden // struct-return argument. if (isStructReturn) { @@ -2237,7 +2237,7 @@ ++I; ++Idx; } - + for (; I != E; ++I) { if (PrintedArg) FunctionInnards << ", "; const Type *ArgTy = *I; @@ -2266,7 +2266,7 @@ FunctionInnards << "void"; // ret() -> ret(void) in C. } FunctionInnards << ')'; - + // Get the return tpe for the function. const Type *RetTy; if (!isStructReturn) @@ -2275,9 +2275,9 @@ // If this is a struct-return function, print the struct-return type. RetTy = cast(FT->getParamType(0))->getElementType(); } - + // Print out the return type and the signature built above. - printType(Out, RetTy, + printType(Out, RetTy, /*isSigned=*/PAL.paramHasAttr(0, Attribute::SExt), FunctionInnards.str()); } @@ -2297,7 +2297,7 @@ printFunctionSignature(&F, false); Out << " {\n"; - + // If this is a struct return function, handle the result with magic. if (isStructReturn) { const Type *StructTy = @@ -2307,13 +2307,13 @@ Out << "; /* Struct return temporary */\n"; Out << " "; - printType(Out, F.arg_begin()->getType(), false, + printType(Out, F.arg_begin()->getType(), false, GetValueName(F.arg_begin())); Out << " = &StructReturn;\n"; } bool PrintedVar = false; - + // print local variable information for the function for (inst_iterator I = inst_begin(&F), E = inst_end(&F); I != E; ++I) { if (const AllocaInst *AI = isDirectAlloca(&*I)) { @@ -2321,7 +2321,7 @@ printType(Out, AI->getAllocatedType(), false, GetValueName(AI)); Out << "; /* Address-exposed local */\n"; PrintedVar = true; - } else if (I->getType() != Type::getVoidTy(F.getContext()) && + } else if (I->getType() != Type::getVoidTy(F.getContext()) && !isInlinableInst(*I)) { Out << " "; printType(Out, I->getType(), false, GetValueName(&*I)); @@ -2337,7 +2337,7 @@ } // We need a temporary for the BitCast to use so it can pluck a value out // of a union to do the BitCast. This is separate from the need for a - // variable to hold the result of the BitCast. + // variable to hold the result of the BitCast. if (isFPIntBitCast(*I)) { Out << " llvmBitCastUnion " << GetValueName(&*I) << "__BITCAST_TEMPORARY;\n"; @@ -2425,7 +2425,7 @@ Out << " return StructReturn;\n"; return; } - + // Don't output a void return if this is the last basic block in the function if (I.getNumOperands() == 0 && &*--I.getParent()->getParent()->end() == I.getParent() && @@ -2582,7 +2582,7 @@ // We must cast the results of binary operations which might be promoted. bool needsCast = false; if ((I.getType() == Type::getInt8Ty(I.getContext())) || - (I.getType() == Type::getInt16Ty(I.getContext())) + (I.getType() == Type::getInt16Ty(I.getContext())) || (I.getType() == Type::getFloatTy(I.getContext()))) { needsCast = true; Out << "(("; @@ -2634,7 +2634,7 @@ case Instruction::SRem: case Instruction::FRem: Out << " % "; break; case Instruction::UDiv: - case Instruction::SDiv: + case Instruction::SDiv: case Instruction::FDiv: Out << " / "; break; case Instruction::And: Out << " & "; break; case Instruction::Or: Out << " | "; break; @@ -2642,7 +2642,7 @@ case Instruction::Shl : Out << " << "; break; case Instruction::LShr: case Instruction::AShr: Out << " >> "; break; - default: + default: #ifndef NDEBUG errs() << "Invalid operator type!" << I; #endif @@ -2685,7 +2685,7 @@ case ICmpInst::ICMP_SGT: Out << " > "; break; default: #ifndef NDEBUG - errs() << "Invalid icmp predicate!" << I; + errs() << "Invalid icmp predicate!" << I; #endif llvm_unreachable(0); } @@ -2758,7 +2758,7 @@ if (isFPIntBitCast(I)) { Out << '('; // These int<->float and long<->double casts need to be handled specially - Out << GetValueName(&I) << "__BITCAST_TEMPORARY." + Out << GetValueName(&I) << "__BITCAST_TEMPORARY." << getFloatBitCastField(I.getOperand(0)->getType()) << " = "; writeOperand(I.getOperand(0)); Out << ", " << GetValueName(&I) << "__BITCAST_TEMPORARY." @@ -2766,7 +2766,7 @@ Out << ')'; return; } - + Out << '('; printCast(I.getOpcode(), SrcTy, DstTy); @@ -2774,15 +2774,15 @@ if (SrcTy == Type::getInt1Ty(I.getContext()) && I.getOpcode() == Instruction::SExt) Out << "0-"; - + writeOperand(I.getOperand(0)); - - if (DstTy == Type::getInt1Ty(I.getContext()) && + + if (DstTy == Type::getInt1Ty(I.getContext()) && (I.getOpcode() == Instruction::Trunc || I.getOpcode() == Instruction::FPToUI || I.getOpcode() == Instruction::FPToSI || I.getOpcode() == Instruction::PtrToInt)) { - // Make sure we really get a trunc to bool by anding the operand with 1 + // Make sure we really get a trunc to bool by anding the operand with 1 Out << "&1u"; } Out << ')'; @@ -2839,7 +2839,7 @@ #undef GET_GCC_BUILTIN_NAME // If we handle it, don't lower it. if (BuiltinName[0]) break; - + // All other intrinsic calls we must lower. Instruction *Before = 0; if (CI != &BB->front()) @@ -2862,7 +2862,7 @@ break; } - // We may have collected some prototypes to emit in the loop above. + // We may have collected some prototypes to emit in the loop above. // Emit them now, before the function that uses them is emitted. But, // be careful not to emit them twice. std::vector::iterator I = prototypesToGen.begin(); @@ -2902,9 +2902,9 @@ writeOperandDeref(I.getArgOperand(0)); Out << " = "; } - + if (I.isTailCall()) Out << " /*tail*/ "; - + if (!WroteCallee) { // If this is an indirect call to a struct return function, we need to cast // the pointer. Ditto for indirect calls with byval arguments. @@ -2928,7 +2928,7 @@ NeedsCast = true; Callee = RF; } - + if (NeedsCast) { // Ok, just cast the pointer type. Out << "(("; @@ -2961,14 +2961,14 @@ ++AI; ++ArgNo; } - + for (; AI != AE; ++AI, ++ArgNo) { if (PrintedArg) Out << ", "; if (ArgNo < NumDeclaredParams && (*AI)->getType() != FTy->getParamType(ArgNo)) { Out << '('; - printType(Out, FTy->getParamType(ArgNo), + printType(Out, FTy->getParamType(ArgNo), /*isSigned=*/PAL.paramHasAttr(ArgNo+1, Attribute::SExt)); Out << ')'; } @@ -2997,7 +2997,7 @@ #include "llvm/Intrinsics.gen" #undef GET_GCC_BUILTIN_NAME assert(BuiltinName[0] && "Unknown LLVM intrinsic!"); - + Out << BuiltinName; WroteCallee = true; return false; @@ -3007,7 +3007,7 @@ return true; case Intrinsic::vastart: Out << "0; "; - + Out << "va_start(*(va_list*)"; writeOperand(I.getArgOperand(0)); Out << ", "; @@ -3085,7 +3085,7 @@ case Intrinsic::x86_sse2_cmp_pd: Out << '('; printType(Out, I.getType()); - Out << ')'; + Out << ')'; // Multiple GCC builtins multiplex onto this intrinsic. switch (cast(I.getArgOperand(2))->getZExtValue()) { default: llvm_unreachable("Invalid llvm.x86.sse.cmp!"); @@ -3106,7 +3106,7 @@ Out << 's'; else Out << 'd'; - + Out << "("; writeOperand(I.getArgOperand(0)); Out << ", "; @@ -3116,7 +3116,7 @@ case Intrinsic::ppc_altivec_lvsl: Out << '('; printType(Out, I.getType()); - Out << ')'; + Out << ')'; Out << "__builtin_altivec_lvsl(0, (void*)"; writeOperand(I.getArgOperand(0)); Out << ")"; @@ -3136,13 +3136,13 @@ std::string Triple = TheModule->getTargetTriple(); if (Triple.empty()) Triple = llvm::sys::getHostTriple(); - + std::string E; if (const Target *Match = TargetRegistry::lookupTarget(Triple, E)) TargetAsm = Match->createAsmInfo(Triple); else return c.Codes[0]; - + const char *const *table = TargetAsm->getAsmCBE(); // Search the translation table if it exists. @@ -3168,7 +3168,7 @@ if (asmstr[i + 1] == '{') { std::string::size_type a = asmstr.find_first_of(':', i + 1); std::string::size_type b = asmstr.find_first_of('}', i + 1); - std::string n = "%" + + std::string n = "%" + asmstr.substr(a + 1, b - a - 1) + asmstr.substr(i + 2, a - i - 2); asmstr.replace(i, b - i + 1, n); @@ -3178,7 +3178,7 @@ } else if (asmstr[i] == '%')//grr { asmstr.replace(i, 1, "%%"); ++i;} - + return asmstr; } @@ -3187,7 +3187,7 @@ void CWriter::visitInlineAsm(CallInst &CI) { InlineAsm* as = cast(CI.getCalledValue()); std::vector Constraints = as->ParseConstraints(); - + std::vector > ResultVals; if (CI.getType() == Type::getVoidTy(CI.getContext())) ; @@ -3197,27 +3197,27 @@ } else { ResultVals.push_back(std::make_pair(&CI, -1)); } - + // Fix up the asm string for gcc and emit it. Out << "__asm__ volatile (\"" << gccifyAsm(as->getAsmString()) << "\"\n"; Out << " :"; unsigned ValueCount = 0; bool IsFirst = true; - + // Convert over all the output constraints. for (std::vector::iterator I = Constraints.begin(), E = Constraints.end(); I != E; ++I) { - + if (I->Type != InlineAsm::isOutput) { ++ValueCount; continue; // Ignore non-output constraints. } - + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); std::string C = InterpretASMConstraint(*I); if (C.empty()) continue; - + if (!IsFirst) { Out << ", "; IsFirst = false; @@ -3226,7 +3226,7 @@ // Unpack the dest. Value *DestVal; int DestValNo = -1; - + if (ValueCount < ResultVals.size()) { DestVal = ResultVals[ValueCount].first; DestValNo = ResultVals[ValueCount].second; @@ -3235,15 +3235,15 @@ if (I->isEarlyClobber) C = "&"+C; - + Out << "\"=" << C << "\"(" << GetValueName(DestVal); if (DestValNo != -1) Out << ".field" << DestValNo; // Multiple retvals. Out << ")"; ++ValueCount; } - - + + // Convert over all the input constraints. Out << "\n :"; IsFirst = true; @@ -3254,19 +3254,19 @@ ++ValueCount; continue; // Ignore non-input constraints. } - + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); std::string C = InterpretASMConstraint(*I); if (C.empty()) continue; - + if (!IsFirst) { Out << ", "; IsFirst = false; } - + assert(ValueCount >= ResultVals.size() && "Input can't refer to result"); Value *SrcVal = CI.getArgOperand(ValueCount-ResultVals.size()); - + Out << "\"" << C << "\"("; if (!I->isIndirect) writeOperand(SrcVal); @@ -3274,7 +3274,7 @@ writeOperandDeref(SrcVal); Out << ")"; } - + // Convert over the clobber constraints. IsFirst = true; for (std::vector::iterator I = Constraints.begin(), @@ -3285,15 +3285,15 @@ assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); std::string C = InterpretASMConstraint(*I); if (C.empty()) continue; - + if (!IsFirst) { Out << ", "; IsFirst = false; } - + Out << '\"' << C << '"'; } - + Out << ")"; } @@ -3312,13 +3312,13 @@ void CWriter::printGEPExpression(Value *Ptr, gep_type_iterator I, gep_type_iterator E, bool Static) { - + // If there are no indices, just print out the pointer. if (I == E) { writeOperand(Ptr); return; } - + // Find out if the last index is into a vector. If so, we have to print this // specially. Since vectors can't have elements of indexable type, only the // last index could possibly be of a vector element. @@ -3327,9 +3327,9 @@ for (gep_type_iterator TmpI = I; TmpI != E; ++TmpI) LastIndexIsVector = dyn_cast(*TmpI); } - + Out << "("; - + // If the last index is into a vector, we can't print it as &a[i][j] because // we can't index into a vector with j in GCC. Instead, emit this as // (((float*)&a[i])+j) @@ -3338,7 +3338,7 @@ printType(Out, PointerType::getUnqual(LastIndexIsVector->getElementType())); Out << ")("; } - + Out << '&'; // If the first index is 0 (very typical) we can do a number of @@ -3448,7 +3448,7 @@ if (BitMask) { Out << ") & "; printConstant(BitMask, false); - Out << ")"; + Out << ")"; } } @@ -3481,7 +3481,7 @@ void CWriter::visitExtractElementInst(ExtractElementInst &I) { // We know that our operand is not inlined. Out << "(("; - const Type *EltTy = + const Type *EltTy = cast(I.getOperand(0)->getType())->getElementType(); printType(Out, PointerType::getUnqual(EltTy)); Out << ")(&" << GetValueName(I.getOperand(0)) << "))["; From bigcheesegs at gmail.com Mon Sep 13 23:27:39 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 14 Sep 2010 04:27:39 -0000 Subject: [llvm-commits] [llvm] r113834 - in /llvm/trunk: lib/Target/CBackend/CBackend.cpp utils/TableGen/IntrinsicEmitter.cpp Message-ID: <20100914042739.2B7CF2A6C12C@llvm.org> Author: mspencer Date: Mon Sep 13 23:27:38 2010 New Revision: 113834 URL: http://llvm.org/viewvc/llvm-project?rev=113834&view=rev Log: CBackend: Fix MSVC build. This may produce warnings on MSVS, but it's better than failures. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=113834&r1=113833&r2=113834&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Sep 13 23:27:38 2010 @@ -50,6 +50,10 @@ #include "llvm/System/Host.h" #include "llvm/Config/config.h" #include +// Some ms header decided to define setjmp as _setjmp, undo this for this file. +#ifdef _MSC_VER +#undef setjmp +#endif using namespace llvm; extern "C" void LLVMInitializeCBackendTarget() { Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=113834&r1=113833&r2=113834&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Mon Sep 13 23:27:38 2010 @@ -69,15 +69,15 @@ void IntrinsicEmitter::EmitPrefix(raw_ostream &OS) { OS << "// VisualStudio defines setjmp as _setjmp\n" "#if defined(_MSC_VER) && defined(setjmp)\n" - "#define setjmp_undefined_for_visual_studio\n" - "#undef setjmp\n" + "# pragma push_macro(\"setjmp\")\n" + "# undef setjmp\n" "#endif\n\n"; } void IntrinsicEmitter::EmitSuffix(raw_ostream &OS) { - OS << "#if defined(_MSC_VER) && defined(setjmp_undefined_for_visual_studio)\n" + OS << "#if defined(_MSC_VER)\n" "// let's return it to _setjmp state\n" - "#define setjmp _setjmp\n" + "# pragma pop_macro(\"setjmp\")\n" "#endif\n\n"; } From John.Thompson.JTSoftware at gmail.com Mon Sep 13 13:15:37 2010 From: John.Thompson.JTSoftware at gmail.com (John Thompson) Date: Mon, 13 Sep 2010 18:15:37 -0000 Subject: [llvm-commits] [llvm] r113766 - in /llvm/trunk: include/llvm/InlineAsm.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Transforms/Scalar/CodeGenPrepare.cpp lib/Transforms/Utils/AddrModeMatcher.cpp lib/VMCore/InlineAsm.cpp Message-ID: <20100913181537.E40582A6C12C@llvm.org> Author: jtsoftware Date: Mon Sep 13 13:15:37 2010 New Revision: 113766 URL: http://llvm.org/viewvc/llvm-project?rev=113766&view=rev Log: Added skeleton for inline asm multiple alternative constraint support. Modified: llvm/trunk/include/llvm/InlineAsm.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp llvm/trunk/lib/VMCore/InlineAsm.cpp Modified: llvm/trunk/include/llvm/InlineAsm.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InlineAsm.h?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/include/llvm/InlineAsm.h (original) +++ llvm/trunk/include/llvm/InlineAsm.h Mon Sep 13 13:15:37 2010 @@ -87,6 +87,19 @@ isClobber // '~x' }; + struct SubConstraintInfo { + /// MatchingInput - If this is not -1, this is an output constraint where an + /// input constraint is required to match it (e.g. "0"). The value is the + /// constraint number that matches this one (for example, if this is + /// constraint #0 and constraint #4 has the value "0", this will be 4). + signed char MatchingInput; + /// Code - The constraint code, either the register name (in braces) or the + /// constraint letter/number. + std::vector Codes; + /// Default constructor. + SubConstraintInfo() : MatchingInput(-1) {} + }; + struct ConstraintInfo { /// Type - The basic type of the constraint: input/output/clobber /// @@ -120,11 +133,31 @@ /// constraint letter/number. std::vector Codes; + /// isMultipleAlternative - '|': has multiple-alternative constraints. + bool isMultipleAlternative; + + /// multipleAlternatives - If there are multiple alternative constraints, + /// this array will contain them. Otherwise it will be empty. + std::vector multipleAlternatives; + + /// The currently selected alternative constraint index. + unsigned currentAlternativeIndex; + + ///Default constructor. + ConstraintInfo(); + + /// Copy constructor. + ConstraintInfo(const ConstraintInfo &other); + /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the /// fields in this structure. If the constraint string is not understood, /// return true, otherwise return false. bool Parse(StringRef Str, std::vector &ConstraintsSoFar); + + /// selectAlternative - Point this constraint to the alternative constraint + /// indicated by the index. + void selectAlternative(unsigned index); }; /// ParseConstraints - Split up the constraint string into the specific Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Sep 13 13:15:37 2010 @@ -45,6 +45,7 @@ class Function; class FastISel; class FunctionLoweringInfo; + class ImmutableCallSite; class MachineBasicBlock; class MachineFunction; class MachineFrameInfo; @@ -1356,12 +1357,42 @@ /// returns the output operand it matches. unsigned getMatchedOperand() const; + /// Copy constructor for copying from an AsmOperandInfo. + AsmOperandInfo(const AsmOperandInfo &info) + : InlineAsm::ConstraintInfo(info), + ConstraintCode(info.ConstraintCode), + ConstraintType(info.ConstraintType), + CallOperandVal(info.CallOperandVal), + ConstraintVT(info.ConstraintVT) { + } + + /// Copy constructor for copying from a ConstraintInfo. AsmOperandInfo(const InlineAsm::ConstraintInfo &info) : InlineAsm::ConstraintInfo(info), ConstraintType(TargetLowering::C_Unknown), CallOperandVal(0), ConstraintVT(MVT::Other) { } }; + + /// ParseConstraints - Split up the constraint string from the inline + /// assembly value into the specific constraints and their prefixes, + /// and also tie in the associated operand values. + /// If this returns an empty vector, and if the constraint string itself + /// isn't empty, there was an error parsing. + virtual std::vector ParseConstraints( + ImmutableCallSite CS) const; + + /// Examine constraint type and operand type and determine a weight value, + /// where: -1 = invalid match, and 0 = so-so match to 5 = good match. + /// The operand object must already have been set up with the operand type. + virtual int getMultipleConstraintMatchWeight( + AsmOperandInfo &info, int maIndex) const; + + /// Examine constraint string and operand type and determine a weight value, + /// where: -1 = invalid match, and 0 = so-so match to 3 = good match. + /// The operand object must already have been set up with the operand type. + virtual int getSingleConstraintMatchWeight( + AsmOperandInfo &info, const char *constraint) const; /// ComputeConstraintToUse - Determines the constraint code and constraint /// type to use for the specific AsmOperandInfo, setting Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Sep 13 13:15:37 2010 @@ -5008,7 +5008,7 @@ /// contains the set of register corresponding to the operand. RegsForValue AssignedRegs; - explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) + explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { } @@ -5069,7 +5069,7 @@ return TLI.getValueType(OpTy, true); } - + private: /// MarkRegAndAliases - Mark the specified register and all aliases in the /// specified set. @@ -5324,28 +5324,15 @@ std::set OutputRegs, InputRegs; - // Do a prepass over the constraints, canonicalizing them, and building up the - // ConstraintOperands list. - std::vector - ConstraintInfos = IA->ParseConstraints(); - - bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); - - SDValue Chain, Flag; - - // We won't need to flush pending loads if this asm doesn't touch - // memory and is nonvolatile. - if (hasMemory || IA->hasSideEffects()) - Chain = getRoot(); - else - Chain = DAG.getRoot(); - + std::vector TargetConstraints = TLI.ParseConstraints(CS); + bool hasMemory = false; + unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. unsigned ResNo = 0; // ResNo - The result number of the next output. - for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { - ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); + for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { + ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); - + EVT OpVT = MVT::Other; // Compute the value type for each operand. @@ -5393,33 +5380,35 @@ } OpInfo.ConstraintVT = OpVT; + + // Indirect operand accesses access memory. + if (OpInfo.isIndirect) + hasMemory = true; + else { + for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { + TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); + if (CType == TargetLowering::C_Memory) { + hasMemory = true; + break; + } + } + } } + SDValue Chain, Flag; + + // We won't need to flush pending loads if this asm doesn't touch + // memory and is nonvolatile. + if (hasMemory || IA->hasSideEffects()) + Chain = getRoot(); + else + Chain = DAG.getRoot(); + // Second pass over the constraints: compute which constraint option to use // and assign registers to constraints that want a specific physreg. - for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { + for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; - // If this is an output operand with a matching input operand, look up the - // matching input. If their types mismatch, e.g. one is an integer, the - // other is floating point, or their sizes are different, flag it as an - // error. - if (OpInfo.hasMatchingInput()) { - SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; - - if (OpInfo.ConstraintVT != Input.ConstraintVT) { - if ((OpInfo.ConstraintVT.isInteger() != - Input.ConstraintVT.isInteger()) || - (OpInfo.ConstraintVT.getSizeInBits() != - Input.ConstraintVT.getSizeInBits())) { - report_fatal_error("Unsupported asm: input constraint" - " with a matching output constraint of" - " incompatible type!"); - } - Input.ConstraintVT = OpInfo.ConstraintVT; - } - } - // Compute the constraint code and ConstraintType to use. TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); @@ -5427,7 +5416,7 @@ // need to to provide an address for the memory input. if (OpInfo.ConstraintType == TargetLowering::C_Memory && !OpInfo.isIndirect) { - assert(OpInfo.Type == InlineAsm::isInput && + assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && "Can only indirectify direct input operands!"); // Memory operands really want the address of the value. If we don't have @@ -5469,8 +5458,6 @@ GetRegistersForValue(OpInfo, OutputRegs, InputRegs); } - ConstraintInfos.clear(); - // Second pass - Loop over all of the operands, assigning virtual or physregs // to register class operands. for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Sep 13 13:15:37 2010 @@ -2654,6 +2654,156 @@ return atoi(ConstraintCode.c_str()); } + +/// ParseConstraints - Split up the constraint string from the inline +/// assembly value into the specific constraints and their prefixes, +/// and also tie in the associated operand values. +/// If this returns an empty vector, and if the constraint string itself +/// isn't empty, there was an error parsing. +std::vector TargetLowering::ParseConstraints( + ImmutableCallSite CS) const { + /// ConstraintOperands - Information about all of the constraints. + std::vector ConstraintOperands; + const InlineAsm *IA = cast(CS.getCalledValue()); + + // Do a prepass over the constraints, canonicalizing them, and building up the + // ConstraintOperands list. + std::vector + ConstraintInfos = IA->ParseConstraints(); + + unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. + unsigned ResNo = 0; // ResNo - The result number of the next output. + + for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { + ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); + AsmOperandInfo &OpInfo = ConstraintOperands.back(); + + EVT OpVT = MVT::Other; + + // Compute the value type for each operand. + switch (OpInfo.Type) { + case InlineAsm::isOutput: + // Indirect outputs just consume an argument. + if (OpInfo.isIndirect) { + OpInfo.CallOperandVal = const_cast(CS.getArgument(ArgNo++)); + break; + } + + // The return value of the call is this value. As such, there is no + // corresponding argument. + assert(!CS.getType()->isVoidTy() && + "Bad inline asm!"); + if (const StructType *STy = dyn_cast(CS.getType())) { + OpVT = getValueType(STy->getElementType(ResNo)); + } else { + assert(ResNo == 0 && "Asm only has one result!"); + OpVT = getValueType(CS.getType()); + } + ++ResNo; + break; + case InlineAsm::isInput: + OpInfo.CallOperandVal = const_cast(CS.getArgument(ArgNo++)); + break; + case InlineAsm::isClobber: + // Nothing to do. + break; + } + } + + // If we have multiple alternative constraints, select the best alternative. + if (ConstraintInfos.size()) { + unsigned maCount = ConstraintInfos[0].multipleAlternatives.size(); + if (maCount) { + unsigned bestMAIndex = 0; + int bestWeight = -1; + // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. + int weight = -1; + unsigned maIndex; + // Compute the sums of the weights for each alternative, keeping track + // of the best (highest weight) one so far. + for (maIndex = 0; maIndex < maCount; ++maIndex) { + int weightSum = 0; + for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); + cIndex != eIndex; ++cIndex) { + AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; + if (OpInfo.Type == InlineAsm::isClobber) + continue; + assert((OpInfo.multipleAlternatives.size() == maCount) + && "Constraint has inconsistent multiple alternative count."); + + // If this is an output operand with a matching input operand, look up the + // matching input. If their types mismatch, e.g. one is an integer, the + // other is floating point, or their sizes are different, flag it as an + // maCantMatch. + if (OpInfo.hasMatchingInput()) { + AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; + + if (OpInfo.ConstraintVT != Input.ConstraintVT) { + if ((OpInfo.ConstraintVT.isInteger() != + Input.ConstraintVT.isInteger()) || + (OpInfo.ConstraintVT.getSizeInBits() != + Input.ConstraintVT.getSizeInBits())) { + weightSum = -1; // Can't match. + break; + } + Input.ConstraintVT = OpInfo.ConstraintVT; + } + } + + weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); + if (weight == -1) { + weightSum = -1; + break; + } + weightSum += weight; + } + // Update best. + if (weightSum > bestWeight) { + bestWeight = weightSum; + bestMAIndex = maIndex; + } + } + + // Now select chosen alternative in each constraint. + for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); + cIndex != eIndex; ++cIndex) { + AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; + if (cInfo.Type == InlineAsm::isClobber) + continue; + cInfo.selectAlternative(bestMAIndex); + } + } + } + + // Check and hook up tied operands, choose constraint code to use. + for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); + cIndex != eIndex; ++cIndex) { + AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; + + // If this is an output operand with a matching input operand, look up the + // matching input. If their types mismatch, e.g. one is an integer, the + // other is floating point, or their sizes are different, flag it as an + // error. + if (OpInfo.hasMatchingInput()) { + AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; + + if (OpInfo.ConstraintVT != Input.ConstraintVT) { + if ((OpInfo.ConstraintVT.isInteger() != + Input.ConstraintVT.isInteger()) || + (OpInfo.ConstraintVT.getSizeInBits() != + Input.ConstraintVT.getSizeInBits())) { + report_fatal_error("Unsupported asm: input constraint" + " with a matching output constraint of" + " incompatible type!"); + } + Input.ConstraintVT = OpInfo.ConstraintVT; + } + } + } + + return ConstraintOperands; +} + /// getConstraintGenerality - Return an integer indicating how general CT /// is. @@ -2672,6 +2822,76 @@ } } +/// Examine constraint type and operand type and determine a weight value, +/// where: -1 = invalid match, and 0 = so-so match to 3 = good match. +/// This object must already have been set up with the operand type +/// and the current alternative constraint selected. +int TargetLowering::getMultipleConstraintMatchWeight( + AsmOperandInfo &info, int maIndex) const { + std::vector &rCodes = info.multipleAlternatives[maIndex].Codes; + int matchingInput = info.multipleAlternatives[maIndex].MatchingInput; + TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; + int BestWeight = -1; + + // Loop over the options, keeping track of the most general one. + for (unsigned i = 0, e = rCodes.size(); i != e; ++i) { + int weight = getSingleConstraintMatchWeight(info, rCodes[i].c_str()); + if (weight > BestWeight) + BestWeight = weight; + } + + return BestWeight; +} + +/// Examine constraint type and operand type and determine a weight value, +/// where: -1 = invalid match, and 0 = so-so match to 3 = good match. +/// This object must already have been set up with the operand type +/// and the current alternative constraint selected. +int TargetLowering::getSingleConstraintMatchWeight( + AsmOperandInfo &info, const char *constraint) const { + int weight = -1; + Value *CallOperandVal = info.CallOperandVal; + // If we don't have a value, we can't do a match, + // but allow it at the lowest weight. + if (CallOperandVal == NULL) + return 0; + // Look at the constraint type. + switch (*constraint) { + case 'i': // immediate integer. + case 'n': // immediate integer with a known value. + weight = 0; + if (info.CallOperandVal) { + if (isa(info.CallOperandVal)) + weight = 3; + else + weight = -1; + } + break; + case 's': // non-explicit intregal immediate. + weight = 0; + if (info.CallOperandVal) { + if (isa(info.CallOperandVal)) + weight = 3; + else + weight = -1; + } + break; + case 'm': // memory operand. + case 'o': // offsettable memory operand + case 'V': // non-offsettable memory operand + weight = 2; + break; + case 'g': // general register, memory operand or immediate integer. + case 'X': // any operand. + weight = 1; + break; + default: + weight = 0; + break; + } + return weight; +} + /// ChooseConstraint - If there are multiple different constraints that we /// could pick for this operand (e.g. "imr") try to pick the 'best' one. /// This is somewhat tricky: constraints fall into four classes: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 13 13:15:37 2010 @@ -11193,6 +11193,34 @@ return TargetLowering::getConstraintType(Constraint); } +/// Examine constraint type and operand type and determine a weight value, +/// where: -1 = invalid match, and 0 = so-so match to 3 = good match. +/// This object must already have been set up with the operand type +/// and the current alternative constraint selected. +int X86TargetLowering::getSingleConstraintMatchWeight( + AsmOperandInfo &info, const char *constraint) const { + int weight = -1; + Value *CallOperandVal = info.CallOperandVal; + // If we don't have a value, we can't do a match, + // but allow it at the lowest weight. + if (CallOperandVal == NULL) + return 0; + // Look at the constraint type. + switch (*constraint) { + default: + return TargetLowering::getSingleConstraintMatchWeight(info, constraint); + break; + case 'I': + if (ConstantInt *C = dyn_cast(info.CallOperandVal)) { + if (C->getZExtValue() <= 31) + weight = 3; + } + break; + // etc. + } + return weight; +} + /// LowerXConstraint - try to replace an X constraint, which matches anything, /// with another that has more specific requirements based on the type of the /// corresponding operand. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Sep 13 13:15:37 2010 @@ -531,6 +531,12 @@ virtual bool ExpandInlineAsm(CallInst *CI) const; ConstraintType getConstraintType(const std::string &Constraint) const; + + /// Examine constraint string and operand type and determine a weight value, + /// where: -1 = invalid match, and 0 = so-so match to 3 = good match. + /// The operand object must already have been set up with the operand type. + virtual int getSingleConstraintMatchWeight( + AsmOperandInfo &info, const char *constraint) const; std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Mon Sep 13 13:15:37 2010 @@ -738,33 +738,10 @@ bool MadeChange = false; InlineAsm *IA = cast(CS.getCalledValue()); - // Do a prepass over the constraints, canonicalizing them, and building up the - // ConstraintOperands list. - std::vector - ConstraintInfos = IA->ParseConstraints(); - - /// ConstraintOperands - Information about all of the constraints. - std::vector ConstraintOperands; - unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. - for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { - ConstraintOperands. - push_back(TargetLowering::AsmOperandInfo(ConstraintInfos[i])); - TargetLowering::AsmOperandInfo &OpInfo = ConstraintOperands.back(); - - // Compute the value type for each operand. - switch (OpInfo.Type) { - case InlineAsm::isOutput: - if (OpInfo.isIndirect) - OpInfo.CallOperandVal = CS.getArgument(ArgNo++); - break; - case InlineAsm::isInput: - OpInfo.CallOperandVal = CS.getArgument(ArgNo++); - break; - case InlineAsm::isClobber: - // Nothing to do. - break; - } - + std::vector TargetConstraints = TLI->ParseConstraints(CS); + for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { + TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; + // Compute the constraint code and ConstraintType to use. TLI->ComputeConstraintToUse(OpInfo, SDValue()); Modified: llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp Mon Sep 13 13:15:37 2010 @@ -21,6 +21,7 @@ #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/PatternMatch.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Support/CallSite.h" using namespace llvm; using namespace llvm::PatternMatch; @@ -379,27 +380,10 @@ /// return false. static bool IsOperandAMemoryOperand(CallInst *CI, InlineAsm *IA, Value *OpVal, const TargetLowering &TLI) { - std::vector - Constraints = IA->ParseConstraints(); - - unsigned ArgNo = 0; // The argument of the CallInst. - for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { - TargetLowering::AsmOperandInfo OpInfo(Constraints[i]); - - // Compute the value type for each operand. - switch (OpInfo.Type) { - case InlineAsm::isOutput: - if (OpInfo.isIndirect) - OpInfo.CallOperandVal = CI->getArgOperand(ArgNo++); - break; - case InlineAsm::isInput: - OpInfo.CallOperandVal = CI->getArgOperand(ArgNo++); - break; - case InlineAsm::isClobber: - // Nothing to do. - break; - } - + std::vector TargetConstraints = TLI.ParseConstraints(ImmutableCallSite(CI)); + for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { + TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; + // Compute the constraint code and ConstraintType to use. TLI.ComputeConstraintToUse(OpInfo, SDValue()); Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=113766&r1=113765&r2=113766&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Mon Sep 13 13:15:37 2010 @@ -53,6 +53,24 @@ const FunctionType *InlineAsm::getFunctionType() const { return cast(getType()->getElementType()); } + +///Default constructor. +InlineAsm::ConstraintInfo::ConstraintInfo() : + isMultipleAlternative(false), + Type(isInput), isEarlyClobber(false), + MatchingInput(-1), isCommutative(false), + isIndirect(false), currentAlternativeIndex(0) { +} + +/// Copy constructor. +InlineAsm::ConstraintInfo::ConstraintInfo(const ConstraintInfo &other) : + isMultipleAlternative(other.isMultipleAlternative), + Type(other.Type), isEarlyClobber(other.isEarlyClobber), + MatchingInput(other.MatchingInput), isCommutative(other.isCommutative), + isIndirect(other.isIndirect), Codes(other.Codes), + multipleAlternatives(other.multipleAlternatives), + currentAlternativeIndex(other.currentAlternativeIndex) { +} /// Parse - Analyze the specified string (e.g. "==&{eax}") and fill in the /// fields in this structure. If the constraint string is not understood, @@ -60,13 +78,22 @@ bool InlineAsm::ConstraintInfo::Parse(StringRef Str, std::vector &ConstraintsSoFar) { StringRef::iterator I = Str.begin(), E = Str.end(); + unsigned multipleAlternativeCount = Str.count('|') + 1; + unsigned multipleAlternativeIndex = 0; + std::vector *pCodes = &Codes; // Initialize + isMultipleAlternative = (multipleAlternativeCount > 1 ? true : false); + if (isMultipleAlternative) { + multipleAlternatives.resize(multipleAlternativeCount); + pCodes = &multipleAlternatives[0].Codes; + } Type = isInput; isEarlyClobber = false; MatchingInput = -1; isCommutative = false; isIndirect = false; + currentAlternativeIndex = 0; // Parse prefixes. if (*I == '~') { @@ -120,15 +147,15 @@ // Find the end of the register name. StringRef::iterator ConstraintEnd = std::find(I+1, E, '}'); if (ConstraintEnd == E) return true; // "{foo" - Codes.push_back(std::string(I, ConstraintEnd+1)); + pCodes->push_back(std::string(I, ConstraintEnd+1)); I = ConstraintEnd+1; } else if (isdigit(*I)) { // Matching Constraint // Maximal munch numbers. StringRef::iterator NumStart = I; while (I != E && isdigit(*I)) ++I; - Codes.push_back(std::string(NumStart, I)); - unsigned N = atoi(Codes.back().c_str()); + pCodes->push_back(std::string(NumStart, I)); + unsigned N = atoi(pCodes->back().c_str()); // Check that this is a valid matching constraint! if (N >= ConstraintsSoFar.size() || ConstraintsSoFar[N].Type != isOutput|| Type != isInput) @@ -136,14 +163,26 @@ // If Operand N already has a matching input, reject this. An output // can't be constrained to the same value as multiple inputs. - if (ConstraintsSoFar[N].hasMatchingInput()) - return true; - - // Note that operand #n has a matching input. - ConstraintsSoFar[N].MatchingInput = ConstraintsSoFar.size(); + if (isMultipleAlternative) { + InlineAsm::SubConstraintInfo &scInfo = + ConstraintsSoFar[N].multipleAlternatives[multipleAlternativeIndex]; + if (scInfo.MatchingInput != -1) + return true; + // Note that operand #n has a matching input. + scInfo.MatchingInput = ConstraintsSoFar.size(); + } else { + if (ConstraintsSoFar[N].hasMatchingInput()) + return true; + // Note that operand #n has a matching input. + ConstraintsSoFar[N].MatchingInput = ConstraintsSoFar.size(); + } + } else if (*I == '|') { + multipleAlternativeIndex++; + pCodes = &multipleAlternatives[multipleAlternativeIndex].Codes; + ++I; } else { // Single letter constraint. - Codes.push_back(std::string(I, I+1)); + pCodes->push_back(std::string(I, I+1)); ++I; } } @@ -151,6 +190,18 @@ return false; } +/// selectAlternative - Point this constraint to the alternative constraint +/// indicated by the index. +void InlineAsm::ConstraintInfo::selectAlternative(unsigned index) { + if (index < multipleAlternatives.size()) { + currentAlternativeIndex = index; + InlineAsm::SubConstraintInfo &scInfo = + multipleAlternatives[currentAlternativeIndex]; + MatchingInput = scInfo.MatchingInput; + Codes = scInfo.Codes; + } +} + std::vector InlineAsm::ParseConstraints(StringRef Constraints) { std::vector Result; @@ -183,7 +234,6 @@ return Result; } - /// Verify - Verify that the specified constraint string is reasonable for the /// specified function type, and otherwise validate the constraint string. bool InlineAsm::Verify(const FunctionType *Ty, StringRef ConstStr) { From rdivacky at freebsd.org Tue Sep 14 02:28:30 2010 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 14 Sep 2010 09:28:30 +0200 Subject: [llvm-commits] [patch] Fix handling of common symbols In-Reply-To: References: Message-ID: <20100914072830.GA18152@freebsd.org> On Mon, Sep 13, 2010 at 05:59:01PM -0400, Rafael Espindola wrote: > Roman found an issue with the previous patch that is fixed on this > one: If there is no explicit .local directive, a .comm should produce > a common symbol, even when the symbol is not first mentioned in a > directive. this one is a little better but still broken :( Rafael, try to compile "gnu screen" (version 4.0.3?), it compiles now but hungs when running. with vanilla SVN llvm it links/runs just fine... From echristo at apple.com Tue Sep 14 03:31:26 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 14 Sep 2010 08:31:26 -0000 Subject: [llvm-commits] [llvm] r113837 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <20100914083126.287212A6C12C@llvm.org> Author: echristo Date: Tue Sep 14 03:31:25 2010 New Revision: 113837 URL: http://llvm.org/viewvc/llvm-project?rev=113837&view=rev Log: Fix QOpcode assignment to Opc. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=113837&r1=113836&r2=113837&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Sep 14 03:31:25 2010 @@ -1278,8 +1278,8 @@ Ops.push_back(MemAddr); Ops.push_back(Align); - unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : - Opc = QOpcodes[OpcodeIndex]); + unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : + QOpcodes[OpcodeIndex]); SDValue SuperReg; SDValue V0 = N->getOperand(0+3); From ggreif at gmail.com Tue Sep 14 03:50:43 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 08:50:43 -0000 Subject: [llvm-commits] [llvm] r113838 - /llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Message-ID: <20100914085043.5E6D42A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 03:50:43 2010 New Revision: 113838 URL: http://llvm.org/viewvc/llvm-project?rev=113838&view=rev Log: test for and-tst peephole optimization documents the status-quo with its opportunities Added: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Added: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=113838&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (added) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Tue Sep 14 03:50:43 2010 @@ -0,0 +1,58 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck -check-prefix=T2 %s + +%struct.Foo = type { i8* } + +define %struct.Foo* @_ZN3Foo7collectEj(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { +entry: + %scevgep = getelementptr %struct.Foo* %this, i32 1 + br label %tailrecurse + +tailrecurse: ; preds = %sw.bb, %entry + %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ] + %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ] + %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] + %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8** + %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1 + %tmp2 = load i8** %scevgep5 + %0 = ptrtoint i8* %tmp2 to i32 + +; CHECK: and lr, r12, #3 +; CHECK-NEXT: tst r12, #3 +; CHECK-NEXT: beq LBB0_4 + +; T2: movs r5, #3 +; T2-NEXT: mov r6, r4 +; T2-NEXT: ands r6, r5 +; T2-NEXT: tst r4, r5 +; T2-NEXT: beq LBB0_5 + + %and = and i32 %0, 3 + %tst = icmp eq i32 %and, 0 + br i1 %tst, label %sw.bb, label %tailrecurse.switch + +tailrecurse.switch: ; preds = %tailrecurse + switch i32 %and, label %sw.epilog [ + i32 1, label %sw.bb + i32 3, label %sw.bb6 + i32 2, label %sw.bb8 + ] + +sw.bb: ; preds = %tailrecurse.switch, %tailrecurse + %shl = shl i32 %acc.tr, 1 + %or = or i32 %and, %shl + %lsr.iv.next = add i32 %lsr.iv, 1 + %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1 + br label %tailrecurse + +sw.bb6: ; preds = %tailrecurse.switch + ret %struct.Foo* %lsr.iv2 + +sw.bb8: ; preds = %tailrecurse.switch + %tmp1 = add i32 %acc.tr, %lsr.iv + %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1 + ret %struct.Foo* %add.ptr11 + +sw.epilog: ; preds = %tailrecurse.switch + ret %struct.Foo* undef +} From clchiou at gmail.com Tue Sep 14 03:59:41 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Tue, 14 Sep 2010 16:59:41 +0800 Subject: [llvm-commits] [PATCH] Add exit instruction to PTX backend Message-ID: Hi, I have created a patch that adds "exit" instruction to PTX backend. SVN revision: 113836 TEST: $ cd llvm/test/ $ llvm-lit CodeGen/PTX/exit.ll -- Testing: 1 tests, 8 threads -- PASS: LLVM :: CodeGen/PTX/exit.ll (1 of 1) Testing Time: 0.01s Expected Passes : 1 Note: Compiling auto generated cpp file produces warning. I suspect the it is because of too few instructions in .td file for now. The warning message should look like this: In file included from PTXAsmPrinter.cpp:50: /usr/local/google/clchiou/llvm/llvm/lib/Target/PTX/AsmPrinter/../PTXGenAsmWriter.inc: In member function ?void::PTXAsmPrinter::printInstruction(const llvm::MachineInstr*, llvm::raw_ostream&)?: /usr/local/google/clchiou/llvm/llvm/lib/Target/PTX/AsmPrinter/../PTXGenAsmWriter.inc:43: warning: right shift count >= width of type This warning should disappear after more instructions are added. Regards, Che-Liang -------------- next part -------------- A non-text attachment was scrubbed... Name: r113836-add-exit.patch Type: text/x-patch Size: 31003 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/0fcb873e/attachment.bin From ggreif at gmail.com Tue Sep 14 04:23:22 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 09:23:22 -0000 Subject: [llvm-commits] [llvm] r113839 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100914092322.8404F2A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 04:23:22 2010 New Revision: 113839 URL: http://llvm.org/viewvc/llvm-project?rev=113839&view=rev Log: Eliminate a 'tst' that immediately follows an 'and' by morphing the 'and' to its recording form 'andS'. This is basically a test commit into this area, to see whether the bots like me. Several generalizations can be applied and various avenues of code simplification are open. I'll introduce those as I go. I am aware of stylistic input from Bill Wendling, about where put the analysis complexity, but I am positive that we can move things around easily and will find a satisfactory solution. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113839&r1=113838&r2=113839&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 14 04:23:22 2010 @@ -1372,6 +1372,19 @@ SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; + case ARM::TSTri: { + if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI)) + return false; + const MachineInstr *AND = llvm::prior(MI); + if (AND->getOpcode() != ARM::ANDri) + return false; + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) { + SrcReg = AND->getOperand(0).getReg(); + CmpValue = 0; + return true; + } + } } return false; @@ -1421,6 +1434,8 @@ switch (MI->getOpcode()) { default: break; case ARM::ADDri: + case ARM::ANDri: + case ARM::t2ANDri: case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: From ggreif at gmail.com Tue Sep 14 04:30:17 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 09:30:17 -0000 Subject: [llvm-commits] [llvm] r113840 - /llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Message-ID: <20100914093017.4321B2A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 04:30:17 2010 New Revision: 113840 URL: http://llvm.org/viewvc/llvm-project?rev=113840&view=rev Log: forgot the testcase change for r113839 Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=113840&r1=113839&r2=113840&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Tue Sep 14 04:30:17 2010 @@ -17,8 +17,7 @@ %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; CHECK: and lr, r12, #3 -; CHECK-NEXT: tst r12, #3 +; CHECK: ands r12, r12, #3 ; CHECK-NEXT: beq LBB0_4 ; T2: movs r5, #3 From nicholas at mxc.ca Tue Sep 14 04:42:38 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 14 Sep 2010 02:42:38 -0700 Subject: [llvm-commits] [PATCH][EXPERIMENTAL] Building LLVMgold.dll In-Reply-To: References: Message-ID: <4C8F438E.4040901@mxc.ca> NAKAMURA Takumi wrote: > Good evening, guys! > > This patch enables building LTO.dll, libLTO.a and LLVMgold.dll on cygming. Does gold run on cygming? > I know it is still incomplete, and I would say it is "experimental". > > Known issue: > > - dependency between libs would be incomplete. > - I don't know how to test functionality. > > ...Takumi > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From criswell at uiuc.edu Tue Sep 14 07:10:45 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 14 Sep 2010 12:10:45 -0000 Subject: [llvm-commits] [poolalloc] r113841 - /poolalloc/trunk/README Message-ID: <20100914121045.F3C4D2A6C12D@llvm.org> Author: criswell Date: Tue Sep 14 07:10:45 2010 New Revision: 113841 URL: http://llvm.org/viewvc/llvm-project?rev=113841&view=rev Log: TEst commit. Modified: poolalloc/trunk/README Modified: poolalloc/trunk/README URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/README?rev=113841&r1=113840&r2=113841&view=diff ============================================================================== --- poolalloc/trunk/README (original) +++ poolalloc/trunk/README Tue Sep 14 07:10:45 2010 @@ -82,3 +82,4 @@ The LLVM Developer's Mailing List provides announcements and general discussion about LLVM. The list is low volume. You can subscribe to it at http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev. + From espindola at google.com Tue Sep 14 08:44:36 2010 From: espindola at google.com (Rafael Espindola) Date: Tue, 14 Sep 2010 09:44:36 -0400 Subject: [llvm-commits] [patch] Fix handling of common symbols In-Reply-To: <20100914072830.GA18152@freebsd.org> References: <20100914072830.GA18152@freebsd.org> Message-ID: > this one is a little better but still broken :( Rafael, try > to compile "gnu screen" (version 4.0.3?), it compiles now > but hungs when running. with vanilla SVN llvm it links/runs > just fine... > Going to give it a try, but I must say that building and running screen is probably not the best test for MC :-) Cheers, -- Rafael ?vila de Esp?ndola From bob.wilson at apple.com Tue Sep 14 11:14:13 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 14 Sep 2010 09:14:13 -0700 Subject: [llvm-commits] [llvm] r113837 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp In-Reply-To: <20100914083126.287212A6C12C@llvm.org> References: <20100914083126.287212A6C12C@llvm.org> Message-ID: <03D227FD-251D-4FA2-8521-ECCDDD57290B@apple.com> Oops. Thanks. On Sep 14, 2010, at 1:31 AM, Eric Christopher wrote: > Author: echristo > Date: Tue Sep 14 03:31:25 2010 > New Revision: 113837 > > URL: http://llvm.org/viewvc/llvm-project?rev=113837&view=rev > Log: > Fix QOpcode assignment to Opc. > > Modified: > llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=113837&r1=113836&r2=113837&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Sep 14 03:31:25 2010 > @@ -1278,8 +1278,8 @@ > Ops.push_back(MemAddr); > Ops.push_back(Align); > > - unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : > - Opc = QOpcodes[OpcodeIndex]); > + unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : > + QOpcodes[OpcodeIndex]); > > SDValue SuperReg; > SDValue V0 = N->getOperand(0+3); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Tue Sep 14 11:49:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 14 Sep 2010 09:49:05 -0700 Subject: [llvm-commits] some thoughts on lowering for calling conventions In-Reply-To: <20100911173742.2316C2A6C12C@llvm.org> References: <20100911173742.2316C2A6C12C@llvm.org> Message-ID: This patch and an unrelated comment from Eric got me thinking some more about llvm's handling of calling conventions. I'm not very happy with our current approach. The specific issue I'm thinking about now is that we lower either too early or too late. Lowering in the front-end should be minimized. It's too early. Interprocedural analyses and optimizations will suffer. (E.g., when an f64 argument is lowered to a pair of i32 values, it's hard for an analysis to track how that argument is used.) Since we currently support 2 front-ends, it also means that we need to do the front-end lowering in 2 places and keep both of them up to date. The front-end has to do some lowering in cases where the back-end doesn't have the language-specific information to do the job, but otherwise, I'd like to see the front-end avoid lowering for calling conventions. Aside from the front-ends, the rest of our calling convention support is handled with selection DAGs. That is too late. We'd really like the optimizer to see all the code for splitting up and recombining arguments. The DAG combiner and machine instruction optimizations clean up some of expanded code, but it's not ideal. I assume that is the motivation for Rafael's patch here. Eric is working on fast isel for ARM, and he mentioned to me recently that since fast isel doesn't build selection DAGs, it has to duplicate all the support for lowering calling conventions. Can we do better? If we had a target-specific lowering for calling conventions at the llvm IR level, instead of for selection DAGs, then we could run that lowering pass after any high-level interprocedural analyses and optimizations but before things like instcombine. That would avoid the need for front-ends to "pre-lower" things like this patch, avoid duplicating effort across front-ends and across selection DAGs and fast-isel, preserve information for high-level passes, and hopefully give us better optimization of the code resulting from lowering. Thoughts? (I fully expect there to be many obstacles to such a change, but I'm curious to hear if there's any consensus about the right solution for the long term. I'm not necessarily advocating that we change anything right now.) On Sep 11, 2010, at 10:37 AM, Rafael Espindola wrote: > Author: rafael > Date: Sat Sep 11 12:37:41 2010 > New Revision: 113694 > > URL: http://llvm.org/viewvc/llvm-project?rev=113694&view=rev > Log: > Lower ARM function signatures a bit more. I implemented only AAPCS since that > is what I can test. With this patch we convert > > struct foo {double a; int b;}; > void f(int, struct foo); > void g(int a, double b, int c) { > struct foo x = {b, c}; > f(a, x); > } > > into > ------------------------------------------------------ > define void @g(i32 %a.0, i32, i32 %b.0, i32 %b.1, i32 %c.0) nounwind optsize { > entry: > tail call void @f(i32 %a.0, i32 undef, i32 %b.0, i32 %b.1, i32 %c.0, > i32 0) nounwind > ret void > } > declare void @f(i32, i32, i32, i32, i32, i32) > ---------------------------------------------------- > > instead of > > --------------------------------------------------- > define void @g(i32 %a, double %b, i32 %c) nounwind optsize { > entry: > %tmp11 = bitcast double %b to i64 > %tmp5 = zext i32 %c to i64 > tail call void @f(i32 %a, i64 %tmp11, i64 %tmp5) nounwind > ret void > } > declare void @f(i32, i64, i64) > -------------------------------------------------- > > The IL for > > ------------------------------------------ > double foo(double X, double Y) { return X+Y; } > ----------------------------------------- > > now shows that the arguments being passed in the integer registres: > > ---------------------------------------------------------------------- > define double @foo(i32 %X.0, i32 %X.1, i32 %Y.0, i32 %Y.1) nounwind > readnone optsize { > entry: > %tmp17 = zext i32 %X.0 to i64 > %tmp12 = zext i32 %X.1 to i64 > %tmp13 = shl i64 %tmp12, 32 > %ins15 = or i64 %tmp13, %tmp17 > %tmp6 = zext i32 %Y.0 to i64 > %tmp3 = zext i32 %Y.1 to i64 > %tmp4 = shl i64 %tmp3, 32 > %ins = or i64 %tmp4, %tmp6 > %tmp10 = bitcast i64 %ins15 to double > %tmp2 = bitcast i64 %ins to double > %0 = fadd double %tmp10, %tmp2 > ret double %0 > } > --------------------------------------------------------------------- > > And the produces assembly is the same as before: > > ---------------------------------------------------------------- > foo: > vmov d0, r2, r3 > vmov d1, r0, r1 > vadd.f64 d0, d1, d0 > vmov r0, r1, d0 > bx lr > ---------------------------------------------------------------- > > Modified: > llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h > llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp > llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp > llvm-gcc-4.2/trunk/gcc/llvm-abi.h > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=113694&r1=113693&r2=113694&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Sat Sep 11 12:37:41 2010 > @@ -55,6 +55,15 @@ > #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, CC, E) \ > llvm_arm_should_pass_aggregate_in_mixed_regs((T), (TY), (CC), (E)) > > +struct DefaultABIClient; > +extern bool > +llvm_arm_try_pass_aggregate_custom(tree, std::vector&, > + CallingConv::ID&, > + struct DefaultABIClient*); > + > +#define LLVM_TRY_PASS_AGGREGATE_CUSTOM(T, E, CC, C) \ > + llvm_arm_try_pass_aggregate_custom((T), (E), (CC), (C)) > + > extern > bool llvm_arm_aggregate_partially_passed_in_regs(std::vector&, > std::vector&, > > Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=113694&r1=113693&r2=113694&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Sat Sep 11 12:37:41 2010 > @@ -2557,6 +2557,91 @@ > } > } > > +static unsigned count_num_words(std::vector &ScalarElts) { > + unsigned NumWords = 0; > + for (unsigned i = 0, e = ScalarElts.size(); i != e; ++i) { > + const Type *Ty = ScalarElts[i]; > + if (Ty->isPointerTy()) { > + NumWords++; > + } else if (Ty->isIntegerTy()) { > + const unsigned TypeSize = Ty->getPrimitiveSizeInBits(); > + const unsigned NumWordsForType = (TypeSize + 31) / 32; > + > + NumWords += NumWordsForType; > + } else { > + assert (0 && "Unexpected type."); > + } > + } > + return NumWords; > +} > + > +// This function is used only on AAPCS. The difference from the generic > +// handling of arguments is that arguments larger than 32 bits are split > +// and padding arguments are added as necessary for alignment. This makes > +// the IL a bit more explicit about how arguments are handled. > +extern bool > +llvm_arm_try_pass_aggregate_custom(tree type, > + std::vector& ScalarElts, > + CallingConv::ID& CC, > + struct DefaultABIClient* C) { > + if (CC != CallingConv::ARM_AAPCS && CC != CallingConv::C) > + return false; > + > + if (CC == CallingConv::C && !TARGET_AAPCS_BASED) > + return false; > + > + if (TARGET_HARD_FLOAT_ABI) > + return false; > + const Type *Ty = ConvertType(type); > + if (Ty->isPointerTy()) > + return false; > + > + const unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; > + const unsigned Alignment = TYPE_ALIGN(type)/8; > + const unsigned NumWords = count_num_words(ScalarElts); > + const bool AddPad = Alignment >= 8 && (NumWords % 2); > + > + // First, build a type that will be bitcast to the original one and > + // from where elements will be extracted. > + std::vector Elts; > + const Type* Int32Ty = Type::getInt32Ty(getGlobalContext()); > + const unsigned NumRegularArgs = Size / 4; > + for (unsigned i = 0; i < NumRegularArgs; ++i) { > + Elts.push_back(Int32Ty); > + } > + const unsigned RestSize = Size % 4; > + const llvm::Type *RestType = NULL; > + if (RestSize> 2) { > + RestType = Type::getInt32Ty(getGlobalContext()); > + } else if (RestSize > 1) { > + RestType = Type::getInt16Ty(getGlobalContext()); > + } else if (RestSize > 0) { > + RestType = Type::getInt8Ty(getGlobalContext()); > + } > + if (RestType) > + Elts.push_back(RestType); > + const StructType *STy = StructType::get(getGlobalContext(), Elts, false); > + > + if (AddPad) { > + ScalarElts.push_back(Int32Ty); > + C->HandlePad(Int32Ty); > + } > + > + for (unsigned i = 0; i < NumRegularArgs; ++i) { > + C->EnterField(i, STy); > + C->HandleScalarArgument(Int32Ty, 0); > + ScalarElts.push_back(Int32Ty); > + C->ExitField(); > + } > + if (RestType) { > + C->EnterField(NumRegularArgs, STy); > + C->HandleScalarArgument(RestType, 0, RestSize); > + ScalarElts.push_back(RestType); > + C->ExitField(); > + } > + return true; > +} > + > // Target hook for llvm-abi.h. It returns true if an aggregate of the > // specified type should be passed in a number of registers of mixed types. > // It also returns a vector of types that correspond to the registers used > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=113694&r1=113693&r2=113694&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Sat Sep 11 12:37:41 2010 > @@ -8,7 +8,8 @@ > /// return type. It potentially breaks down the argument and invokes methods > /// on the client that indicate how its pieces should be handled. This > /// handles things like returning structures via hidden parameters. > -void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin) { > +void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin, > + std::vector &ScalarElts) { > unsigned Offset = 0; > const Type *Ty = ConvertType(type); > if (Ty->isVectorTy()) { > @@ -52,7 +53,9 @@ > > // FIXME: should return the hidden first argument for some targets > // (e.g. ELF i386). > - C.HandleAggregateShadowResult(Ty->getPointerTo(), false); > + const PointerType *PTy = Ty->getPointerTo(); > + C.HandleAggregateShadowResult(PTy, false); > + ScalarElts.push_back(PTy); > } > } > > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=113694&r1=113693&r2=113694&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Sat Sep 11 12:37:41 2010 > @@ -396,7 +396,8 @@ > /// return type. It potentially breaks down the argument and invokes methods > /// on the client that indicate how its pieces should be handled. This > /// handles things like returning structures via hidden parameters. > - void HandleReturnType(tree type, tree fn, bool isBuiltin); > + void HandleReturnType(tree type, tree fn, bool isBuiltin, > + std::vector &ScalarElts); > > /// HandleArgument - This is invoked by the target-independent code for each > /// argument type passed into the function. It potentially breaks down the > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113694&r1=113693&r2=113694&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Sep 11 12:37:41 2010 > @@ -673,17 +673,19 @@ > FunctionPrologArgumentConversion Client(FnDecl, AI, Builder, CallingConv); > DefaultABI ABIConverter(Client); > > + // Scalar arguments processed so far. > + std::vector ScalarArgs; > + > // Handle the DECL_RESULT. > ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl)), FnDecl, > - DECL_BUILT_IN(FnDecl)); > + DECL_BUILT_IN(FnDecl), > + ScalarArgs); > // Remember this for use by FinishFunctionBody. > ReturnOffset = Client.Offset; > > // Prepend the static chain (if any) to the list of arguments. > tree Args = static_chain ? static_chain : DECL_ARGUMENTS(FnDecl); > > - // Scalar arguments processed so far. > - std::vector ScalarArgs; > while (Args) { > const char *Name = "unnamed_arg"; > if (DECL_NAME(Args)) Name = IDENTIFIER_POINTER(DECL_NAME(Args)); > @@ -3012,16 +3014,17 @@ > DefaultABI ABIConverter(Client); > > // Handle the result, including struct returns. > + std::vector ScalarArgs; > ABIConverter.HandleReturnType(TREE_TYPE(exp), > fndecl ? fndecl : exp, > - fndecl ? DECL_BUILT_IN(fndecl) : false); > + fndecl ? DECL_BUILT_IN(fndecl) : false, > + ScalarArgs); > > // Pass the static chain, if any, as the first parameter. > if (TREE_OPERAND(exp, 2)) > CallOperands.push_back(Emit(TREE_OPERAND(exp, 2), 0)); > > // Loop over the arguments, expanding them and adding them to the op list. > - std::vector ScalarArgs; > for (tree arg = TREE_OPERAND(exp, 1); arg; arg = TREE_CHAIN(arg)) { > tree type = TREE_TYPE(TREE_VALUE(arg)); > const Type *ArgTy = ConvertType(type); > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=113694&r1=113693&r2=113694&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Sat Sep 11 12:37:41 2010 > @@ -1082,8 +1082,10 @@ > TARGET_ADJUST_LLVM_CC(CallingConv, type); > #endif > > + std::vector ScalarArgs; > // Builtins are always prototyped, so this isn't one. > - ABIConverter.HandleReturnType(ReturnType, current_function_decl, false); > + ABIConverter.HandleReturnType(ReturnType, current_function_decl, false, > + ScalarArgs); > > SmallVector Attrs; > > @@ -1110,7 +1112,6 @@ > Attrs.push_back(AttributeWithIndex::get(ArgTys.size(), > Attribute::StructRet)); > > - std::vector ScalarArgs; > if (static_chain) { > // Pass the static chain as the first parameter. > ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); > @@ -1152,8 +1153,10 @@ > TARGET_ADJUST_LLVM_CC(CallingConv, type); > #endif > > + std::vector ScalarArgs; > ABIConverter.HandleReturnType(TREE_TYPE(type), current_function_decl, > - decl ? DECL_BUILT_IN(decl) : false); > + decl ? DECL_BUILT_IN(decl) : false, > + ScalarArgs); > > // Compute attributes for return type (and function attributes). > SmallVector Attrs; > @@ -1218,7 +1221,6 @@ > Attrs.push_back(AttributeWithIndex::get(ArgTypes.size(), > Attribute::StructRet | Attribute::NoAlias)); > > - std::vector ScalarArgs; > if (static_chain) { > // Pass the static chain as the first parameter. > ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From john.thompson.jtsoftware at gmail.com Tue Sep 14 12:52:57 2010 From: john.thompson.jtsoftware at gmail.com (John Thompson) Date: Tue, 14 Sep 2010 10:52:57 -0700 Subject: [llvm-commits] [llvm] r113771 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: <20100913183057.98B542A6C12C@llvm.org> References: <20100913183057.98B542A6C12C@llvm.org> Message-ID: Sorry about that. I should have looked closer at my gcc build output, as I mostly use VC++. I'm learning. -John On Mon, Sep 13, 2010 at 11:30 AM, Eric Christopher wrote: > Author: echristo > Date: Mon Sep 13 13:30:57 2010 > New Revision: 113771 > > URL: http://llvm.org/viewvc/llvm-project?rev=113771&view=rev > Log: > Silence more warnings. Two more unused variables. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=113771&r1=113770&r2=113771&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Sep 13 > 13:30:57 2010 > @@ -2829,8 +2829,6 @@ > int TargetLowering::getMultipleConstraintMatchWeight( > AsmOperandInfo &info, int maIndex) const { > std::vector &rCodes = > info.multipleAlternatives[maIndex].Codes; > - int matchingInput = info.multipleAlternatives[maIndex].MatchingInput; > - TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; > int BestWeight = -1; > > // Loop over the options, keeping track of the most general one. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- John Thompson John.Thompson.JTSoftware at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/d72e5664/attachment.html From dpatel at apple.com Tue Sep 14 15:29:31 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 14 Sep 2010 20:29:31 -0000 Subject: [llvm-commits] [llvm] r113843 - /llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Message-ID: <20100914202931.73F722A6C12C@llvm.org> Author: dpatel Date: Tue Sep 14 15:29:31 2010 New Revision: 113843 URL: http://llvm.org/viewvc/llvm-project?rev=113843&view=rev Log: Use frame index, if available for byval argument while lowering dbg_declare. Otherwise let getRegForValue() find register for this argument. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=113843&r1=113842&r2=113843&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Sep 14 15:29:31 2010 @@ -467,24 +467,28 @@ return true; const Value *Address = DI->getAddress(); - if (!Address) + if (!Address || isa(Address) || isa(Address)) return true; - if (isa(Address)) - return true; - const AllocaInst *AI = dyn_cast(Address); - // Don't handle byval struct arguments or VLAs, for example. - if (!AI) { - // Building the map above is target independent. Generating DBG_VALUE - // inline is target dependent; do this now. - DenseMap::iterator It = - FuncInfo.ValueMap.find(Address); - if (0 && It != FuncInfo.ValueMap.end()) { - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(TargetOpcode::DBG_VALUE)) - .addReg(It->second, RegState::Debug).addImm(0).addMetadata(DI->getVariable()); - } else - (void)TargetSelectInstruction(cast(I)); + + unsigned Reg = 0; + unsigned Offset = 0; + if (const Argument *Arg = dyn_cast(Address)) { + if (Arg->hasByValAttr()) { + // Byval arguments' frame index is recorded during argument lowering. + // Use this info directly. + Offset = FuncInfo.getByValArgumentFrameIndex(Arg); + if (Offset) + Reg = TRI.getFrameRegister(*FuncInfo.MF); + } } + if (!Reg) + Reg = getRegForValue(Address); + + if (Reg) + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(TargetOpcode::DBG_VALUE)) + .addReg(Reg, RegState::Debug).addImm(Offset) + .addMetadata(DI->getVariable()); return true; } case Intrinsic::dbg_value: { From dpatel at apple.com Tue Sep 14 15:32:58 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 14 Sep 2010 20:32:58 -0000 Subject: [llvm-commits] [llvm] r113845 - /llvm/trunk/include/llvm/Metadata.h Message-ID: <20100914203258.93CB12A6C12C@llvm.org> Author: dpatel Date: Tue Sep 14 15:32:58 2010 New Revision: 113845 URL: http://llvm.org/viewvc/llvm-project?rev=113845&view=rev Log: After Dan's recent commit this is no longer true. Now isFunctionLocal is reset, if required, when operands are modified. Modified: llvm/trunk/include/llvm/Metadata.h Modified: llvm/trunk/include/llvm/Metadata.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=113845&r1=113844&r2=113845&view=diff ============================================================================== --- llvm/trunk/include/llvm/Metadata.h (original) +++ llvm/trunk/include/llvm/Metadata.h Tue Sep 14 15:32:58 2010 @@ -144,9 +144,6 @@ unsigned getNumOperands() const { return NumOperands; } /// isFunctionLocal - Return whether MDNode is local to a function. - /// Note: MDNodes are designated as function-local when created, and keep - /// that designation even if their operands are modified to no longer - /// refer to function-local IR. bool isFunctionLocal() const { return (getSubclassDataFromValue() & FunctionLocalBit) != 0; } From grosbach at apple.com Tue Sep 14 15:35:46 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 20:35:46 -0000 Subject: [llvm-commits] [llvm] r113846 - /llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Message-ID: <20100914203546.90DE72A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 15:35:46 2010 New Revision: 113846 URL: http://llvm.org/viewvc/llvm-project?rev=113846&view=rev Log: Clarify comment Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=113846&r1=113845&r2=113846&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Tue Sep 14 15:35:46 2010 @@ -217,8 +217,8 @@ /// Old opcode has an optional def of CPSR. if (HasCC) return true; - // If both old opcode does not implicit CPSR def, then it's not ok since - // these new opcodes CPSR def is not meant to be thrown away. e.g. CMP. + // If old opcode does not implicitly define CPSR, then it's not ok since + // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP. if (!HasImplicitCPSRDef(MI->getDesc())) return false; HasCC = true; From grosbach at apple.com Tue Sep 14 15:41:27 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 20:41:27 -0000 Subject: [llvm-commits] [llvm] r113847 - /llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Message-ID: <20100914204127.495822A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 15:41:27 2010 New Revision: 113847 URL: http://llvm.org/viewvc/llvm-project?rev=113847&view=rev Log: Don't ignore the CPSR implicit def when lowering a MachineInstruction to an MCInst. Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=113847&r1=113846&r2=113847&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Tue Sep 14 15:41:27 2010 @@ -12,6 +12,7 @@ // //===----------------------------------------------------------------------===// +#include "ARM.h" #include "ARMMCInstLower.h" //#include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/AsmPrinter.h" @@ -126,8 +127,8 @@ MI->dump(); assert(0 && "unknown operand type"); case MachineOperand::MO_Register: - // Ignore all implicit register operands. - if (MO.isImplicit()) continue; + // Ignore all non-CPSR implicit register operands. + if (MO.isImplicit() && MO.getReg() != ARM::CPSR) continue; assert(!MO.getSubReg() && "Subregs should be eliminated!"); MCOp = MCOperand::CreateReg(MO.getReg()); break; From ggreif at gmail.com Tue Sep 14 15:46:08 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 20:46:08 -0000 Subject: [llvm-commits] [llvm] r113848 - /llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Message-ID: <20100914204608.4453F2A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 15:46:08 2010 New Revision: 113848 URL: http://llvm.org/viewvc/llvm-project?rev=113848&view=rev Log: must not peephole away side effects Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=113848&r1=113847&r2=113848&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Sep 14 15:46:08 2010 @@ -269,7 +269,8 @@ MII = I->begin(), MIE = I->end(); MII != MIE; ) { MachineInstr *MI = &*MII; - if (MI->getDesc().isCompare()) { + if (MI->getDesc().isCompare() && + !MI->getDesc().hasUnmodeledSideEffects()) { if (OptimizeCmpInstr(MI, MBB, MII)) Changed = true; else From ggreif at gmail.com Tue Sep 14 15:47:43 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 20:47:43 -0000 Subject: [llvm-commits] [llvm] r113849 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20100914204744.081112A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 15:47:43 2010 New Revision: 113849 URL: http://llvm.org/viewvc/llvm-project?rev=113849&view=rev Log: set comparable for a bunch of Thumb instructions Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=113849&r1=113848&r2=113849&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Sep 14 15:47:43 2010 @@ -656,7 +656,7 @@ } // CMP register -let Defs = [CPSR] in { +let isCompare = 1, Defs = [CPSR] in { def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, "cmp", "\t$lhs, $rhs", [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>, @@ -837,7 +837,7 @@ T1Misc<{0,0,1,0,0,0,?}>; // test -let isCommutable = 1, Defs = [CPSR] in +let isCompare = 1, isCommutable = 1, Defs = [CPSR] in def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, "tst", "\t$lhs, $rhs", [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>, From benny.kra at googlemail.com Tue Sep 14 15:49:01 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 14 Sep 2010 20:49:01 -0000 Subject: [llvm-commits] [llvm] r113850 - in /llvm/trunk/include/llvm: Constants.h DerivedTypes.h Type.h Message-ID: <20100914204901.1A97B2A6C12C@llvm.org> Author: d0k Date: Tue Sep 14 15:49:00 2010 New Revision: 113850 URL: http://llvm.org/viewvc/llvm-project?rev=113850&view=rev Log: Prune includes. Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/include/llvm/DerivedTypes.h llvm/trunk/include/llvm/Type.h Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=113850&r1=113849&r2=113850&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Tue Sep 14 15:49:00 2010 @@ -25,7 +25,6 @@ #include "llvm/OperandTraits.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/APFloat.h" -#include "llvm/ADT/SmallVector.h" #include namespace llvm { @@ -40,6 +39,8 @@ struct ConstantCreator; template struct ConvertConstantType; +template +class SmallVector; //===----------------------------------------------------------------------===// /// This is the shared class of boolean and integer constants. This class Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=113850&r1=113849&r2=113850&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Tue Sep 14 15:49:00 2010 @@ -19,6 +19,7 @@ #define LLVM_DERIVED_TYPES_H #include "llvm/Type.h" +#include "llvm/System/DataTypes.h" namespace llvm { Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=113850&r1=113849&r2=113850&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Sep 14 15:49:00 2010 @@ -12,7 +12,6 @@ #include "llvm/AbstractTypeUser.h" #include "llvm/Support/Casting.h" -#include "llvm/System/DataTypes.h" #include "llvm/ADT/GraphTraits.h" #include #include From echristo at apple.com Tue Sep 14 15:52:03 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 14 Sep 2010 13:52:03 -0700 Subject: [llvm-commits] [llvm] r113849 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td In-Reply-To: <20100914204744.081112A6C12C@llvm.org> References: <20100914204744.081112A6C12C@llvm.org> Message-ID: <2D65ECAD-72C5-43EB-8F36-408881F4A2B3@apple.com> On Sep 14, 2010, at 1:47 PM, Gabor Greif wrote: > Author: ggreif > Date: Tue Sep 14 15:47:43 2010 > New Revision: 113849 > > URL: http://llvm.org/viewvc/llvm-project?rev=113849&view=rev > Log: > set comparable for a bunch of Thumb instructions Thanks, missed a few though. :) I'll grab 'em if you don't get them soon. -eric From resistor at mac.com Tue Sep 14 15:57:41 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 14 Sep 2010 20:57:41 -0000 Subject: [llvm-commits] [llvm] r113852 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100914205741.D7D032A6C12C@llvm.org> Author: resistor Date: Tue Sep 14 15:57:41 2010 New Revision: 113852 URL: http://llvm.org/viewvc/llvm-project?rev=113852&view=rev Log: Remove the option to disable LazyValueInfo in JumpThreading, as it is now on by default and has received significant testing. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=113852&r1=113851&r2=113852&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Tue Sep 14 15:57:41 2010 @@ -44,15 +44,6 @@ cl::desc("Max block size to duplicate for jump threading"), cl::init(6), cl::Hidden); -// Turn on use of LazyValueInfo. -static cl::opt -EnableLVI("enable-jump-threading-lvi", - cl::desc("Use LVI for jump threading"), - cl::init(true), - cl::ReallyHidden); - - - namespace { /// This pass performs 'jump threading', which looks at blocks that have /// multiple predecessors and multiple successors. If one or more of the @@ -100,10 +91,8 @@ bool runOnFunction(Function &F); virtual void getAnalysisUsage(AnalysisUsage &AU) const { - if (EnableLVI) { - AU.addRequired(); - AU.addPreserved(); - } + AU.addRequired(); + AU.addPreserved(); } void FindLoopHeaders(Function &F); @@ -143,7 +132,7 @@ bool JumpThreading::runOnFunction(Function &F) { DEBUG(dbgs() << "Jump threading on function '" << F.getName() << "'\n"); TD = getAnalysisIfAvailable(); - LVI = EnableLVI ? &getAnalysis() : 0; + LVI = &getAnalysis(); FindLoopHeaders(F); @@ -165,7 +154,7 @@ DEBUG(dbgs() << " JT: Deleting dead block '" << BB->getName() << "' with terminator: " << *BB->getTerminator() << '\n'); LoopHeaders.erase(BB); - if (LVI) LVI->eraseBlock(BB); + LVI->eraseBlock(BB); DeleteDeadBlock(BB); Changed = true; } else if (BranchInst *BI = dyn_cast(BB->getTerminator())) { @@ -190,7 +179,7 @@ // for a block even if it doesn't get erased. This isn't totally // awesome, but it allows us to use AssertingVH to prevent nasty // dangling pointer issues within LazyValueInfo. - if (LVI) LVI->eraseBlock(BB); + LVI->eraseBlock(BB); if (TryToSimplifyUncondBranchFromEmptyBlock(BB)) { Changed = true; // If we deleted BB and BB was the header of a loop, then the @@ -331,29 +320,25 @@ /// TODO: Per PR2563, we could infer value range information about a /// predecessor based on its terminator. // - if (LVI) { - // FIXME: change this to use the more-rich 'getPredicateOnEdge' method if - // "I" is a non-local compare-with-a-constant instruction. This would be - // able to handle value inequalities better, for example if the compare is - // "X < 4" and "X < 3" is known true but "X < 4" itself is not available. - // Perhaps getConstantOnEdge should be smart enough to do this? - - for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) { - BasicBlock *P = *PI; - // If the value is known by LazyValueInfo to be a constant in a - // predecessor, use that information to try to thread this block. - Constant *PredCst = LVI->getConstantOnEdge(V, P, BB); - if (PredCst == 0 || - (!isa(PredCst) && !isa(PredCst))) - continue; + // FIXME: change this to use the more-rich 'getPredicateOnEdge' method if + // "I" is a non-local compare-with-a-constant instruction. This would be + // able to handle value inequalities better, for example if the compare is + // "X < 4" and "X < 3" is known true but "X < 4" itself is not available. + // Perhaps getConstantOnEdge should be smart enough to do this? + + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) { + BasicBlock *P = *PI; + // If the value is known by LazyValueInfo to be a constant in a + // predecessor, use that information to try to thread this block. + Constant *PredCst = LVI->getConstantOnEdge(V, P, BB); + if (PredCst == 0 || + (!isa(PredCst) && !isa(PredCst))) + continue; - Result.push_back(std::make_pair(dyn_cast(PredCst), P)); - } - - return !Result.empty(); + Result.push_back(std::make_pair(dyn_cast(PredCst), P)); } - - return false; + + return !Result.empty(); } /// If I is a PHI node, then we know the incoming values for any constants. @@ -363,7 +348,7 @@ if (isa(InVal) || isa(InVal)) { ConstantInt *CI = dyn_cast(InVal); Result.push_back(std::make_pair(CI, PN->getIncomingBlock(i))); - } else if (LVI) { + } else { Constant *CI = LVI->getConstantOnEdge(InVal, PN->getIncomingBlock(i), BB); // LVI returns null is no value could be determined. @@ -467,7 +452,7 @@ Value *Res = SimplifyCmpInst(Cmp->getPredicate(), LHS, RHS, TD); if (Res == 0) { - if (!LVI || !isa(RHS)) + if (!isa(RHS)) continue; LazyValueInfo::Tristate @@ -488,8 +473,7 @@ // If comparing a live-in value against a constant, see if we know the // live-in value on any predecessors. - if (LVI && isa(Cmp->getOperand(1)) && - Cmp->getType()->isIntegerTy()) { + if (isa(Cmp->getOperand(1)) && Cmp->getType()->isIntegerTy()) { if (!isa(Cmp->getOperand(0)) || cast(Cmp->getOperand(0))->getParent() != BB) { Constant *RHSCst = cast(Cmp->getOperand(1)); @@ -530,19 +514,15 @@ } } - if (LVI) { - // If all else fails, see if LVI can figure out a constant value for us. - Constant *CI = LVI->getConstant(V, BB); - ConstantInt *CInt = dyn_cast_or_null(CI); - if (CInt) { - for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) - Result.push_back(std::make_pair(CInt, *PI)); - } - - return !Result.empty(); + // If all else fails, see if LVI can figure out a constant value for us. + Constant *CI = LVI->getConstant(V, BB); + ConstantInt *CInt = dyn_cast_or_null(CI); + if (CInt) { + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) + Result.push_back(std::make_pair(CInt, *PI)); } - - return false; + + return !Result.empty(); } @@ -592,7 +572,7 @@ // Remember if SinglePred was the entry block of the function. If so, we // will need to move BB back to the entry position. bool isEntry = SinglePred == &SinglePred->getParent()->getEntryBlock(); - if (LVI) LVI->eraseBlock(SinglePred); + LVI->eraseBlock(SinglePred); MergeBasicBlockIntoOnlyPred(BB); if (isEntry && BB != &BB->getParent()->getEntryBlock()) @@ -645,75 +625,23 @@ Instruction *CondInst = dyn_cast(Condition); - // If the condition is an instruction defined in another block, see if a - // predecessor has the same condition: - // br COND, BBX, BBY - // BBX: - // br COND, BBZ, BBW - if (!LVI && - !Condition->hasOneUse() && // Multiple uses. - (CondInst == 0 || CondInst->getParent() != BB)) { // Non-local definition. - pred_iterator PI = pred_begin(BB), E = pred_end(BB); - if (isa(BB->getTerminator())) { - for (; PI != E; ++PI) { - BasicBlock *P = *PI; - if (BranchInst *PBI = dyn_cast(P->getTerminator())) - if (PBI->isConditional() && PBI->getCondition() == Condition && - ProcessBranchOnDuplicateCond(P, BB)) - return true; - } - } else { - assert(isa(BB->getTerminator()) && "Unknown jump terminator"); - for (; PI != E; ++PI) { - BasicBlock *P = *PI; - if (SwitchInst *PSI = dyn_cast(P->getTerminator())) - if (PSI->getCondition() == Condition && - ProcessSwitchOnDuplicateCond(P, BB)) - return true; - } - } - } - // All the rest of our checks depend on the condition being an instruction. if (CondInst == 0) { // FIXME: Unify this with code below. - if (LVI && ProcessThreadableEdges(Condition, BB)) + if (ProcessThreadableEdges(Condition, BB)) return true; return false; } if (CmpInst *CondCmp = dyn_cast(CondInst)) { - if (!LVI && - (!isa(CondCmp->getOperand(0)) || - cast(CondCmp->getOperand(0))->getParent() != BB)) { - // If we have a comparison, loop over the predecessors to see if there is - // a condition with a lexically identical value. - pred_iterator PI = pred_begin(BB), E = pred_end(BB); - for (; PI != E; ++PI) { - BasicBlock *P = *PI; - if (BranchInst *PBI = dyn_cast(P->getTerminator())) - if (PBI->isConditional() && P != BB) { - if (CmpInst *CI = dyn_cast(PBI->getCondition())) { - if (CI->getOperand(0) == CondCmp->getOperand(0) && - CI->getOperand(1) == CondCmp->getOperand(1) && - CI->getPredicate() == CondCmp->getPredicate()) { - // TODO: Could handle things like (x != 4) --> (x == 17) - if (ProcessBranchOnDuplicateCond(P, BB)) - return true; - } - } - } - } - } - // For a comparison where the LHS is outside this block, it's possible // that we've branched on it before. Used LVI to see if we can simplify // the branch based on that. BranchInst *CondBr = dyn_cast(BB->getTerminator()); Constant *CondConst = dyn_cast(CondCmp->getOperand(1)); pred_iterator PI = pred_begin(BB), PE = pred_end(BB); - if (LVI && CondBr && CondConst && CondBr->isConditional() && PI != PE && + if (CondBr && CondConst && CondBr->isConditional() && PI != PE && (!isa(CondCmp->getOperand(0)) || cast(CondCmp->getOperand(0))->getParent() != BB)) { // For predecessor edge, determine if the comparison is true or false @@ -1455,8 +1383,7 @@ << ", across block:\n " << *BB << "\n"); - if (LVI) - LVI->threadEdge(PredBB, BB, SuccBB); + LVI->threadEdge(PredBB, BB, SuccBB); // We are going to have to map operands from the original BB block to the new // copy of the block 'NewBB'. If there are PHI nodes in BB, evaluate them to From bob.wilson at apple.com Tue Sep 14 15:59:49 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 14 Sep 2010 20:59:49 -0000 Subject: [llvm-commits] [llvm] r113854 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20100914205949.4B6BC2A6C12C@llvm.org> Author: bwilson Date: Tue Sep 14 15:59:49 2010 New Revision: 113854 URL: http://llvm.org/viewvc/llvm-project?rev=113854&view=rev Log: Make NEON ld/st pseudo instruction classes take the instruction itinerary as an argument, so that we can distinguish instructions with the same register classes but different numbers of registers (e.g., vld3 and vld4). Fix some of the non-pseudo NEON ld/st instruction itineraries to reflect the number of registers loaded or stored, not just the opcode name. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113854&r1=113853&r2=113854&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 14 15:59:49 2010 @@ -169,21 +169,21 @@ // Classes for VLD* pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. -class VLDQPseudo - : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD2, "">; -class VLDQWBPseudo +class VLDQPseudo + : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">; +class VLDQWBPseudo : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, + (ins addrmode6:$addr, am6offset:$offset), itin, "$addr.addr = $wb">; -class VLDQQPseudo - : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), IIC_VLD4, "">; -class VLDQQWBPseudo +class VLDQQPseudo + : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">; +class VLDQQWBPseudo : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, + (ins addrmode6:$addr, am6offset:$offset), itin, "$addr.addr = $wb">; -class VLDQQQQWBPseudo +class VLDQQQQWBPseudo : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VLD4, + (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, "$addr.addr = $wb, $src = $dst">; // VLD1 : Vector Load (multiple single elements) @@ -193,7 +193,7 @@ "vld1", Dt, "\\{$dst\\}, $addr", "", []>; class VLD1Q op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr), IIC_VLD1, + (ins addrmode6:$addr), IIC_VLD2, "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>; def VLD1d8 : VLD1D<0b0000, "8">; @@ -206,10 +206,10 @@ def VLD1q32 : VLD1Q<0b1000, "32">; def VLD1q64 : VLD1Q<0b1100, "64">; -def VLD1q8Pseudo : VLDQPseudo; -def VLD1q16Pseudo : VLDQPseudo; -def VLD1q32Pseudo : VLDQPseudo; -def VLD1q64Pseudo : VLDQPseudo; +def VLD1q8Pseudo : VLDQPseudo; +def VLD1q16Pseudo : VLDQPseudo; +def VLD1q32Pseudo : VLDQPseudo; +def VLD1q64Pseudo : VLDQPseudo; // ...with address register writeback: class VLD1DWB op7_4, string Dt> @@ -219,7 +219,7 @@ "$addr.addr = $wb", []>; class VLD1QWB op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, "vld1", Dt, "${dst:dregpair}, $addr$offset", "$addr.addr = $wb", []>; @@ -233,19 +233,19 @@ def VLD1q32_UPD : VLD1QWB<0b1000, "32">; def VLD1q64_UPD : VLD1QWB<0b1100, "64">; -def VLD1q8Pseudo_UPD : VLDQWBPseudo; -def VLD1q16Pseudo_UPD : VLDQWBPseudo; -def VLD1q32Pseudo_UPD : VLDQWBPseudo; -def VLD1q64Pseudo_UPD : VLDQWBPseudo; +def VLD1q8Pseudo_UPD : VLDQWBPseudo; +def VLD1q16Pseudo_UPD : VLDQWBPseudo; +def VLD1q32Pseudo_UPD : VLDQWBPseudo; +def VLD1q64Pseudo_UPD : VLDQWBPseudo; // ...with 3 registers (some of these are only for the disassembler): class VLD1D3 op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt, + (ins addrmode6:$addr), IIC_VLD3, "vld1", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>; class VLD1D3WB op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3, "vld1", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>; def VLD1d8T : VLD1D3<0b0000, "8">; @@ -258,18 +258,18 @@ def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">; def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">; -def VLD1d64TPseudo : VLDQQPseudo; -def VLD1d64TPseudo_UPD : VLDQQWBPseudo; +def VLD1d64TPseudo : VLDQQPseudo; +def VLD1d64TPseudo_UPD : VLDQQWBPseudo; // ...with 4 registers (some of these are only for the disassembler): class VLD1D4 op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD1, "vld1", Dt, + (ins addrmode6:$addr), IIC_VLD4, "vld1", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; class VLD1D4WB op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "vld1", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb", []>; @@ -283,8 +283,8 @@ def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">; def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">; -def VLD1d64QPseudo : VLDQQPseudo; -def VLD1d64QPseudo_UPD : VLDQQWBPseudo; +def VLD1d64QPseudo : VLDQQPseudo; +def VLD1d64QPseudo_UPD : VLDQQWBPseudo; // VLD2 : Vector Load (multiple 2-element structures) class VLD2D op11_8, bits<4> op7_4, string Dt> @@ -294,7 +294,7 @@ class VLD2Q op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD2, + (ins addrmode6:$addr), IIC_VLD4, "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; def VLD2d8 : VLD2D<0b1000, 0b0000, "8">; @@ -305,13 +305,13 @@ def VLD2q16 : VLD2Q<0b0100, "16">; def VLD2q32 : VLD2Q<0b1000, "32">; -def VLD2d8Pseudo : VLDQPseudo; -def VLD2d16Pseudo : VLDQPseudo; -def VLD2d32Pseudo : VLDQPseudo; - -def VLD2q8Pseudo : VLDQQPseudo; -def VLD2q16Pseudo : VLDQQPseudo; -def VLD2q32Pseudo : VLDQQPseudo; +def VLD2d8Pseudo : VLDQPseudo; +def VLD2d16Pseudo : VLDQPseudo; +def VLD2d32Pseudo : VLDQPseudo; + +def VLD2q8Pseudo : VLDQQPseudo; +def VLD2q16Pseudo : VLDQQPseudo; +def VLD2q32Pseudo : VLDQQPseudo; // ...with address register writeback: class VLD2DWB op11_8, bits<4> op7_4, string Dt> @@ -322,7 +322,7 @@ class VLD2QWB op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb", []>; @@ -334,13 +334,13 @@ def VLD2q16_UPD : VLD2QWB<0b0100, "16">; def VLD2q32_UPD : VLD2QWB<0b1000, "32">; -def VLD2d8Pseudo_UPD : VLDQWBPseudo; -def VLD2d16Pseudo_UPD : VLDQWBPseudo; -def VLD2d32Pseudo_UPD : VLDQWBPseudo; - -def VLD2q8Pseudo_UPD : VLDQQWBPseudo; -def VLD2q16Pseudo_UPD : VLDQQWBPseudo; -def VLD2q32Pseudo_UPD : VLDQQWBPseudo; +def VLD2d8Pseudo_UPD : VLDQWBPseudo; +def VLD2d16Pseudo_UPD : VLDQWBPseudo; +def VLD2d32Pseudo_UPD : VLDQWBPseudo; + +def VLD2q8Pseudo_UPD : VLDQQWBPseudo; +def VLD2q16Pseudo_UPD : VLDQQWBPseudo; +def VLD2q32Pseudo_UPD : VLDQQWBPseudo; // ...with double-spaced registers (for disassembly only): def VLD2b8 : VLD2D<0b1001, 0b0000, "8">; @@ -360,9 +360,9 @@ def VLD3d16 : VLD3D<0b0100, 0b0100, "16">; def VLD3d32 : VLD3D<0b0100, 0b1000, "32">; -def VLD3d8Pseudo : VLDQQPseudo; -def VLD3d16Pseudo : VLDQQPseudo; -def VLD3d32Pseudo : VLDQQPseudo; +def VLD3d8Pseudo : VLDQQPseudo; +def VLD3d16Pseudo : VLDQQPseudo; +def VLD3d32Pseudo : VLDQQPseudo; // ...with address register writeback: class VLD3DWB op11_8, bits<4> op7_4, string Dt> @@ -376,9 +376,9 @@ def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">; def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">; -def VLD3d8Pseudo_UPD : VLDQQWBPseudo; -def VLD3d16Pseudo_UPD : VLDQQWBPseudo; -def VLD3d32Pseudo_UPD : VLDQQWBPseudo; +def VLD3d8Pseudo_UPD : VLDQQWBPseudo; +def VLD3d16Pseudo_UPD : VLDQQWBPseudo; +def VLD3d32Pseudo_UPD : VLDQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): def VLD3q8 : VLD3D<0b0101, 0b0000, "8">; @@ -388,14 +388,14 @@ def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">; def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">; -def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo; -def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo; -def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo; +def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo; +def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo; +def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo; // ...alternate versions to be allocated odd register numbers: -def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo; -def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo; -def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo; // VLD4 : Vector Load (multiple 4-element structures) class VLD4D op11_8, bits<4> op7_4, string Dt> @@ -408,9 +408,9 @@ def VLD4d16 : VLD4D<0b0000, 0b0100, "16">; def VLD4d32 : VLD4D<0b0000, 0b1000, "32">; -def VLD4d8Pseudo : VLDQQPseudo; -def VLD4d16Pseudo : VLDQQPseudo; -def VLD4d32Pseudo : VLDQQPseudo; +def VLD4d8Pseudo : VLDQQPseudo; +def VLD4d16Pseudo : VLDQQPseudo; +def VLD4d32Pseudo : VLDQQPseudo; // ...with address register writeback: class VLD4DWB op11_8, bits<4> op7_4, string Dt> @@ -424,9 +424,9 @@ def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">; def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">; -def VLD4d8Pseudo_UPD : VLDQQWBPseudo; -def VLD4d16Pseudo_UPD : VLDQQWBPseudo; -def VLD4d32Pseudo_UPD : VLDQQWBPseudo; +def VLD4d8Pseudo_UPD : VLDQQWBPseudo; +def VLD4d16Pseudo_UPD : VLDQQWBPseudo; +def VLD4d32Pseudo_UPD : VLDQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): def VLD4q8 : VLD4D<0b0001, 0b0000, "8">; @@ -436,14 +436,14 @@ def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">; def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">; -def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo; -def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo; -def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo; +def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo; +def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo; +def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo; // ...alternate versions to be allocated odd register numbers: -def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo; -def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo; -def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo; // Classes for VLD*LN pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. @@ -627,19 +627,19 @@ // Classes for VST* pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. -class VSTQPseudo - : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, "">; -class VSTQWBPseudo +class VSTQPseudo + : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">; +class VSTQWBPseudo : PseudoNLdSt<(outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST, + (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin, "$addr.addr = $wb">; -class VSTQQPseudo - : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">; -class VSTQQWBPseudo +class VSTQQPseudo + : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">; +class VSTQQWBPseudo : PseudoNLdSt<(outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), IIC_VST, + (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin, "$addr.addr = $wb">; -class VSTQQQQWBPseudo +class VSTQQQQWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST, "$addr.addr = $wb">; @@ -663,10 +663,10 @@ def VST1q32 : VST1Q<0b1000, "32">; def VST1q64 : VST1Q<0b1100, "64">; -def VST1q8Pseudo : VSTQPseudo; -def VST1q16Pseudo : VSTQPseudo; -def VST1q32Pseudo : VSTQPseudo; -def VST1q64Pseudo : VSTQPseudo; +def VST1q8Pseudo : VSTQPseudo; +def VST1q16Pseudo : VSTQPseudo; +def VST1q32Pseudo : VSTQPseudo; +def VST1q64Pseudo : VSTQPseudo; // ...with address register writeback: class VST1DWB op7_4, string Dt> @@ -688,10 +688,10 @@ def VST1q32_UPD : VST1QWB<0b1000, "32">; def VST1q64_UPD : VST1QWB<0b1100, "64">; -def VST1q8Pseudo_UPD : VSTQWBPseudo; -def VST1q16Pseudo_UPD : VSTQWBPseudo; -def VST1q32Pseudo_UPD : VSTQWBPseudo; -def VST1q64Pseudo_UPD : VSTQWBPseudo; +def VST1q8Pseudo_UPD : VSTQWBPseudo; +def VST1q16Pseudo_UPD : VSTQWBPseudo; +def VST1q32Pseudo_UPD : VSTQWBPseudo; +def VST1q64Pseudo_UPD : VSTQWBPseudo; // ...with 3 registers (some of these are only for the disassembler): class VST1D3 op7_4, string Dt> @@ -715,8 +715,8 @@ def VST1d32T_UPD : VST1D3WB<0b1000, "32">; def VST1d64T_UPD : VST1D3WB<0b1100, "64">; -def VST1d64TPseudo : VSTQQPseudo; -def VST1d64TPseudo_UPD : VSTQQWBPseudo; +def VST1d64TPseudo : VSTQQPseudo; +def VST1d64TPseudo_UPD : VSTQQWBPseudo; // ...with 4 registers (some of these are only for the disassembler): class VST1D4 op7_4, string Dt> @@ -741,8 +741,8 @@ def VST1d32Q_UPD : VST1D4WB<0b1000, "32">; def VST1d64Q_UPD : VST1D4WB<0b1100, "64">; -def VST1d64QPseudo : VSTQQPseudo; -def VST1d64QPseudo_UPD : VSTQQWBPseudo; +def VST1d64QPseudo : VSTQQPseudo; +def VST1d64QPseudo_UPD : VSTQQWBPseudo; // VST2 : Vector Store (multiple 2-element structures) class VST2D op11_8, bits<4> op7_4, string Dt> @@ -763,13 +763,13 @@ def VST2q16 : VST2Q<0b0100, "16">; def VST2q32 : VST2Q<0b1000, "32">; -def VST2d8Pseudo : VSTQPseudo; -def VST2d16Pseudo : VSTQPseudo; -def VST2d32Pseudo : VSTQPseudo; - -def VST2q8Pseudo : VSTQQPseudo; -def VST2q16Pseudo : VSTQQPseudo; -def VST2q32Pseudo : VSTQQPseudo; +def VST2d8Pseudo : VSTQPseudo; +def VST2d16Pseudo : VSTQPseudo; +def VST2d32Pseudo : VSTQPseudo; + +def VST2q8Pseudo : VSTQQPseudo; +def VST2q16Pseudo : VSTQQPseudo; +def VST2q32Pseudo : VSTQQPseudo; // ...with address register writeback: class VST2DWB op11_8, bits<4> op7_4, string Dt> @@ -792,13 +792,13 @@ def VST2q16_UPD : VST2QWB<0b0100, "16">; def VST2q32_UPD : VST2QWB<0b1000, "32">; -def VST2d8Pseudo_UPD : VSTQWBPseudo; -def VST2d16Pseudo_UPD : VSTQWBPseudo; -def VST2d32Pseudo_UPD : VSTQWBPseudo; - -def VST2q8Pseudo_UPD : VSTQQWBPseudo; -def VST2q16Pseudo_UPD : VSTQQWBPseudo; -def VST2q32Pseudo_UPD : VSTQQWBPseudo; +def VST2d8Pseudo_UPD : VSTQWBPseudo; +def VST2d16Pseudo_UPD : VSTQWBPseudo; +def VST2d32Pseudo_UPD : VSTQWBPseudo; + +def VST2q8Pseudo_UPD : VSTQQWBPseudo; +def VST2q16Pseudo_UPD : VSTQQWBPseudo; +def VST2q32Pseudo_UPD : VSTQQWBPseudo; // ...with double-spaced registers (for disassembly only): def VST2b8 : VST2D<0b1001, 0b0000, "8">; @@ -818,9 +818,9 @@ def VST3d16 : VST3D<0b0100, 0b0100, "16">; def VST3d32 : VST3D<0b0100, 0b1000, "32">; -def VST3d8Pseudo : VSTQQPseudo; -def VST3d16Pseudo : VSTQQPseudo; -def VST3d32Pseudo : VSTQQPseudo; +def VST3d8Pseudo : VSTQQPseudo; +def VST3d16Pseudo : VSTQQPseudo; +def VST3d32Pseudo : VSTQQPseudo; // ...with address register writeback: class VST3DWB op11_8, bits<4> op7_4, string Dt> @@ -834,9 +834,9 @@ def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">; def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">; -def VST3d8Pseudo_UPD : VSTQQWBPseudo; -def VST3d16Pseudo_UPD : VSTQQWBPseudo; -def VST3d32Pseudo_UPD : VSTQQWBPseudo; +def VST3d8Pseudo_UPD : VSTQQWBPseudo; +def VST3d16Pseudo_UPD : VSTQQWBPseudo; +def VST3d32Pseudo_UPD : VSTQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): def VST3q8 : VST3D<0b0101, 0b0000, "8">; @@ -846,14 +846,14 @@ def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">; def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">; -def VST3q8Pseudo_UPD : VSTQQQQWBPseudo; -def VST3q16Pseudo_UPD : VSTQQQQWBPseudo; -def VST3q32Pseudo_UPD : VSTQQQQWBPseudo; +def VST3q8Pseudo_UPD : VSTQQQQWBPseudo; +def VST3q16Pseudo_UPD : VSTQQQQWBPseudo; +def VST3q32Pseudo_UPD : VSTQQQQWBPseudo; // ...alternate versions to be allocated odd register numbers: -def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo; -def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo; -def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo; +def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo; +def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo; +def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo; // VST4 : Vector Store (multiple 4-element structures) class VST4D op11_8, bits<4> op7_4, string Dt> @@ -866,9 +866,9 @@ def VST4d16 : VST4D<0b0000, 0b0100, "16">; def VST4d32 : VST4D<0b0000, 0b1000, "32">; -def VST4d8Pseudo : VSTQQPseudo; -def VST4d16Pseudo : VSTQQPseudo; -def VST4d32Pseudo : VSTQQPseudo; +def VST4d8Pseudo : VSTQQPseudo; +def VST4d16Pseudo : VSTQQPseudo; +def VST4d32Pseudo : VSTQQPseudo; // ...with address register writeback: class VST4DWB op11_8, bits<4> op7_4, string Dt> @@ -882,9 +882,9 @@ def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">; def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">; -def VST4d8Pseudo_UPD : VSTQQWBPseudo; -def VST4d16Pseudo_UPD : VSTQQWBPseudo; -def VST4d32Pseudo_UPD : VSTQQWBPseudo; +def VST4d8Pseudo_UPD : VSTQQWBPseudo; +def VST4d16Pseudo_UPD : VSTQQWBPseudo; +def VST4d32Pseudo_UPD : VSTQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): def VST4q8 : VST4D<0b0001, 0b0000, "8">; @@ -894,14 +894,14 @@ def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">; def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">; -def VST4q8Pseudo_UPD : VSTQQQQWBPseudo; -def VST4q16Pseudo_UPD : VSTQQQQWBPseudo; -def VST4q32Pseudo_UPD : VSTQQQQWBPseudo; +def VST4q8Pseudo_UPD : VSTQQQQWBPseudo; +def VST4q16Pseudo_UPD : VSTQQQQWBPseudo; +def VST4q32Pseudo_UPD : VSTQQQQWBPseudo; // ...alternate versions to be allocated odd register numbers: -def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo; -def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo; -def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo; +def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo; +def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo; +def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo; // Classes for VST*LN pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. From resistor at mac.com Tue Sep 14 16:03:40 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 14 Sep 2010 21:03:40 -0000 Subject: [llvm-commits] [llvm] r113855 - in /llvm/trunk/test/Transforms/JumpThreading: 2010-08-26-and.ll basic.ll lvi-load.ll Message-ID: <20100914210340.E94632A6C12C@llvm.org> Author: resistor Date: Tue Sep 14 16:03:40 2010 New Revision: 113855 URL: http://llvm.org/viewvc/llvm-project?rev=113855&view=rev Log: Remove dead option from tests. Modified: llvm/trunk/test/Transforms/JumpThreading/2010-08-26-and.ll llvm/trunk/test/Transforms/JumpThreading/basic.ll llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll Modified: llvm/trunk/test/Transforms/JumpThreading/2010-08-26-and.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/2010-08-26-and.ll?rev=113855&r1=113854&r2=113855&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/2010-08-26-and.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/2010-08-26-and.ll Tue Sep 14 16:03:40 2010 @@ -1,4 +1,4 @@ -; RUN: opt -jump-threading -enable-jump-threading-lvi -S < %s | FileCheck %s +; RUN: opt -jump-threading -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" Modified: llvm/trunk/test/Transforms/JumpThreading/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/basic.ll?rev=113855&r1=113854&r2=113855&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/basic.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/basic.ll Tue Sep 14 16:03:40 2010 @@ -1,4 +1,4 @@ -; RUN: opt %s -jump-threading -S -enable-jump-threading-lvi | FileCheck %s +; RUN: opt %s -jump-threading -S | FileCheck %s declare i32 @f1() declare i32 @f2() Modified: llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll?rev=113855&r1=113854&r2=113855&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll Tue Sep 14 16:03:40 2010 @@ -1,4 +1,4 @@ -; RUN: opt -S -jump-threading -enable-jump-threading-lvi -dce < %s | FileCheck %s +; RUN: opt -S -jump-threading -dce < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.4" From bigcheesegs at gmail.com Tue Sep 14 16:06:20 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 14 Sep 2010 17:06:20 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add isObjectFile() Message-ID: The attached patch adds isObjectFile() const; to Path. This patch is a prerequisite for the object file library I am writing. This implementation just checks to see if IdentifyFileType returns anything other than Unknown_FileType, as it only currently recognizes object files. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-System-Path-Add-isObjectFile.patch Type: application/octet-stream Size: 1672 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/c70bbf59/attachment.obj From grosbach at apple.com Tue Sep 14 16:05:34 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 21:05:34 -0000 Subject: [llvm-commits] [llvm] r113856 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20100914210534.3C53E2A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 16:05:34 2010 New Revision: 113856 URL: http://llvm.org/viewvc/llvm-project?rev=113856&view=rev Log: fix comment typo Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=113856&r1=113855&r2=113856&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Sep 14 16:05:34 2010 @@ -1343,7 +1343,7 @@ OutStreamer.EmitLabel(Label); - // Form and emit tha dd. + // Form and emit the add. MCInst AddInst; AddInst.setOpcode(ARM::ADDrr); AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); From bigcheesegs at gmail.com Tue Sep 14 16:12:12 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 14 Sep 2010 17:12:12 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add x86-64 COFF to IdentifyFileType Message-ID: The attached patch adds x86-64 COFF to Path::IdentifyFileType. This patch is a prerequisite for the object file library I am writing, although makes sense in general. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-System-Path-Add-x86-64-COFF-to-IdentifyFileType.patch Type: application/octet-stream Size: 416 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/3c093e5d/attachment.obj From bob.wilson at apple.com Tue Sep 14 16:12:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 14 Sep 2010 21:12:05 -0000 Subject: [llvm-commits] [llvm] r113857 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100914211205.886912A6C12C@llvm.org> Author: bwilson Date: Tue Sep 14 16:12:05 2010 New Revision: 113857 URL: http://llvm.org/viewvc/llvm-project?rev=113857&view=rev Log: Avoid warnings. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113857&r1=113856&r2=113857&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Sep 14 16:12:05 2010 @@ -450,8 +450,9 @@ } assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); - unsigned DstReg, D0, D1, D2, D3; - bool DstIsDead; + unsigned D0, D1, D2, D3; + unsigned DstReg = 0; + bool DstIsDead = false; if (TableEntry->IsLoad) { DstIsDead = MI.getOperand(OpIdx).isDead(); DstReg = MI.getOperand(OpIdx++).getReg(); From bigcheesegs at gmail.com Tue Sep 14 16:18:44 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 14 Sep 2010 17:18:44 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. Message-ID: The attached patch adds the SwapByteOrder function template to System. This patch is a prerequisite for the object file library I am writing. I want to replace the functions in MathExtras.h with SwapByteOrder because it is a generic implementation that makes it easier to write generic byte order independent code. This patch has no functionality changes. The optimized versions are platform dependent, and thus belong in System anyway. - Michael Spencer From gohman at apple.com Tue Sep 14 16:25:10 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 14 Sep 2010 21:25:10 -0000 Subject: [llvm-commits] [llvm] r113858 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/LibCallAliasAnalysis.h include/llvm/Analysis/LibCallSemantics.h include/llvm/LLVMContext.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp lib/Analysis/LibCallAliasAnalysis.cpp lib/Analysis/ScalarEvolutionAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/VMCore/LLVMContext.cpp Message-ID: <20100914212510.DD2912A6C12C@llvm.org> Author: djg Date: Tue Sep 14 16:25:10 2010 New Revision: 113858 URL: http://llvm.org/viewvc/llvm-project?rev=113858&view=rev Log: Remove the experimental AliasAnalysis::getDependency interface, which isn't a good level of abstraction for memdep. Instead, generalize AliasAnalysis::alias and related interfaces with a new Location class for describing a memory location. For now, this is the same Pointer and Size as before, plus an additional field for a TBAA tag. Also, introduce a fixed MD_tbaa metadata tag kind. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h llvm/trunk/include/llvm/Analysis/LibCallSemantics.h llvm/trunk/include/llvm/LLVMContext.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp llvm/trunk/lib/Analysis/AliasDebugger.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp llvm/trunk/lib/VMCore/LLVMContext.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Sep 14 16:25:10 2010 @@ -83,6 +83,22 @@ /// Alias Queries... /// + /// Location - A description of a memory location. + struct Location { + /// Ptr - The address of the start of the location. + const Value *Ptr; + /// Size - The size of the location. + unsigned Size; + /// TBAATag - The metadata node which describes the TBAA type of + /// the location, or null if there is no (unique) tag. + const MDNode *TBAATag; + + explicit Location(const Value *P = 0, + unsigned S = UnknownSize, + const MDNode *N = 0) + : Ptr(P), Size(S), TBAATag(N) {} + }; + /// Alias analysis result - Either we know for sure that it does not alias, we /// know for sure it must alias, or we don't know anything: The two pointers /// _might_ alias. This enum is designed so you can do things like: @@ -98,27 +114,41 @@ /// Returns a Result indicating whether the two pointers are aliased to each /// other. This is the interface that must be implemented by specific alias /// analysis implementations. - /// - virtual AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size); + virtual AliasResult alias(const Location &LocA, const Location &LocB); - /// alias - A convenience wrapper for the case where the sizes are unknown. + /// alias - A convenience wrapper. + AliasResult alias(const Value *V1, unsigned V1Size, + const Value *V2, unsigned V2Size) { + return alias(Location(V1, V1Size), Location(V2, V2Size)); + } + + /// alias - A convenience wrapper. AliasResult alias(const Value *V1, const Value *V2) { return alias(V1, UnknownSize, V2, UnknownSize); } /// isNoAlias - A trivial helper function to check to see if the specified /// pointers are no-alias. + bool isNoAlias(const Location &LocA, const Location &LocB) { + return alias(LocA, LocB) == NoAlias; + } + + /// isNoAlias - A convenience wrapper. bool isNoAlias(const Value *V1, unsigned V1Size, const Value *V2, unsigned V2Size) { - return alias(V1, V1Size, V2, V2Size) == NoAlias; + return isNoAlias(Location(V1, V1Size), Location(V2, V2Size)); } - /// pointsToConstantMemory - If the specified pointer is known to point into - /// constant global memory, return true. This allows disambiguation of store + /// pointsToConstantMemory - If the specified memory location is known to be + /// constant, return true. This allows disambiguation of store /// instructions from constant pointers. /// - virtual bool pointsToConstantMemory(const Value *P); + virtual bool pointsToConstantMemory(const Location &Loc); + + /// pointsToConstantMemory - A convenient wrapper. + bool pointsToConstantMemory(const Value *P) { + return pointsToConstantMemory(Location(P)); + } //===--------------------------------------------------------------------===// /// Simple mod/ref information... @@ -220,55 +250,87 @@ /// getModRefInfo - Return information about whether or not an instruction may - /// read or write memory specified by the pointer operand. An instruction + /// read or write the specified memory location. An instruction /// that doesn't read or write memory may be trivially LICM'd for example. ModRefResult getModRefInfo(const Instruction *I, - const Value *P, unsigned Size) { + const Location &Loc) { switch (I->getOpcode()) { - case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, P,Size); - case Instruction::Load: return getModRefInfo((const LoadInst*)I, P, Size); - case Instruction::Store: return getModRefInfo((const StoreInst*)I, P,Size); - case Instruction::Call: return getModRefInfo((const CallInst*)I, P, Size); - case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,P,Size); + case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, Loc); + case Instruction::Load: return getModRefInfo((const LoadInst*)I, Loc); + case Instruction::Store: return getModRefInfo((const StoreInst*)I, Loc); + case Instruction::Call: return getModRefInfo((const CallInst*)I, Loc); + case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,Loc); default: return NoModRef; } } + /// getModRefInfo - A convenience wrapper. + ModRefResult getModRefInfo(const Instruction *I, + const Value *P, unsigned Size) { + return getModRefInfo(I, Location(P, Size)); + } + /// getModRefInfo (for call sites) - Return whether information about whether - /// a particular call site modifies or reads the memory specified by the - /// pointer. + /// a particular call site modifies or reads the specified memory location. virtual ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size); + const Location &Loc); + + /// getModRefInfo (for call sites) - A convenience wrapper. + ModRefResult getModRefInfo(ImmutableCallSite CS, + const Value *P, unsigned Size) { + return getModRefInfo(CS, Location(P, Size)); + } /// getModRefInfo (for calls) - Return whether information about whether - /// a particular call modifies or reads the memory specified by the - /// pointer. + /// a particular call modifies or reads the specified memory location. + ModRefResult getModRefInfo(const CallInst *C, const Location &Loc) { + return getModRefInfo(ImmutableCallSite(C), Loc); + } + + /// getModRefInfo (for calls) - A convenience wrapper. ModRefResult getModRefInfo(const CallInst *C, const Value *P, unsigned Size) { - return getModRefInfo(ImmutableCallSite(C), P, Size); + return getModRefInfo(C, Location(P, Size)); } /// getModRefInfo (for invokes) - Return whether information about whether - /// a particular invoke modifies or reads the memory specified by the - /// pointer. + /// a particular invoke modifies or reads the specified memory location. + ModRefResult getModRefInfo(const InvokeInst *I, + const Location &Loc) { + return getModRefInfo(ImmutableCallSite(I), Loc); + } + + /// getModRefInfo (for invokes) - A convenience wrapper. ModRefResult getModRefInfo(const InvokeInst *I, const Value *P, unsigned Size) { - return getModRefInfo(ImmutableCallSite(I), P, Size); + return getModRefInfo(I, Location(P, Size)); } /// getModRefInfo (for loads) - Return whether information about whether - /// a particular load modifies or reads the memory specified by the - /// pointer. - ModRefResult getModRefInfo(const LoadInst *L, const Value *P, unsigned Size); + /// a particular load modifies or reads the specified memory location. + ModRefResult getModRefInfo(const LoadInst *L, const Location &Loc); + + /// getModRefInfo (for loads) - A convenience wrapper. + ModRefResult getModRefInfo(const LoadInst *L, const Value *P, unsigned Size) { + return getModRefInfo(L, Location(P, Size)); + } /// getModRefInfo (for stores) - Return whether information about whether - /// a particular store modifies or reads the memory specified by the - /// pointer. - ModRefResult getModRefInfo(const StoreInst *S, const Value *P, unsigned Size); + /// a particular store modifies or reads the specified memory location. + ModRefResult getModRefInfo(const StoreInst *S, const Location &Loc); + + /// getModRefInfo (for stores) - A convenience wrapper. + ModRefResult getModRefInfo(const StoreInst *S, const Value *P, unsigned Size) { + return getModRefInfo(S, Location(P, Size)); + } /// getModRefInfo (for va_args) - Return whether information about whether - /// a particular va_arg modifies or reads the memory specified by the - /// pointer. - ModRefResult getModRefInfo(const VAArgInst* I, const Value* P, unsigned Size); + /// a particular va_arg modifies or reads the specified memory location. + ModRefResult getModRefInfo(const VAArgInst* I, const Location &Loc); + + /// getModRefInfo (for va_args) - A convenience wrapper. + ModRefResult getModRefInfo(const VAArgInst* I, const Value* P, unsigned Size) { + return getModRefInfo(I, Location(P, Size)); + } /// getModRefInfo - Return information about whether two call sites may refer /// to the same set of memory locations. See @@ -278,100 +340,30 @@ ImmutableCallSite CS2); //===--------------------------------------------------------------------===// - /// Dependence queries. - /// - - /// DependenceResult - These are the return values for getDependence queries. - /// They are defined in terms of "memory", but they are also used to model - /// other side effects, such as I/O and volatility. - enum DependenceResult { - /// ReadThenRead - The instructions are ReadThenReadSome and the second - /// instruction reads from exactly the same memory read from by the first. - ReadThenRead, - - /// ReadThenReadSome - The instructions are Independent, both are read-only, - /// and the second instruction reads from a subset of the memory read from - /// by the first. - ReadThenReadSome, - - /// Independent - Neither instruction reads from or writes to memory written - /// to by the other. All enum values lower than this one are special cases - /// of Indepenent. - Independent, - - /// WriteThenRead - The instructions are WriteThenReadSome and the second - /// instruction reads from exactly the same memory written by the first. - WriteThenRead, - - /// WriteThenReadSome - The first instruction is write-only, the second - /// instruction is read-only, and the second only reads from memory - /// written to by the first. - WriteThenReadSome, - - /// ReadThenWrite - The first instruction is read-only, the second - /// instruction is write-only, and the second wrotes to exactly the - /// same memory read from by the first. - ReadThenWrite, - - /// WriteThenWrite - The instructions are WriteThenWriteSome, and the - /// second instruction writes to exactly the same memory written to by - /// the first. - WriteThenWrite, - - /// WriteSomeThenWrite - Both instructions are write-only, and the second - /// instruction writes to a superset of the memory written to by the first. - WriteSomeThenWrite, - - /// Unknown - The relationship between the instructions cannot be - /// determined or does not fit into any of the cases defined here. - Unknown - }; - - /// DependenceQueryFlags - Flags for refining dependence queries. - enum DependenceQueryFlags { - Default = 0, - IgnoreLoads = 1, - IgnoreStores = 2 - }; - - /// getDependence - Determine the dependence relationship between the - /// instructions. This does not include "register" dependencies; it just - /// considers memory references and other side effects. - /// WARNING: This is an experimental interface. - DependenceResult getDependence(const Instruction *First, - const Instruction *Second) { - return getDependence(First, 0, Default, Second, 0, Default); - } - - /// getDependence - Determine the dependence relationship between the - /// instructions. This does not include "register" dependencies; it just - /// considers memory references and other side effects. This overload - /// has additional parameters to allow phi-translated addresses to be - /// specified, and additional flags to refine the query. - /// WARNING: This is an experimental interface. - virtual DependenceResult getDependence(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags); - - //===--------------------------------------------------------------------===// /// Higher level methods for querying mod/ref information. /// /// canBasicBlockModify - Return true if it is possible for execution of the /// specified basic block to modify the value pointed to by Ptr. - /// - bool canBasicBlockModify(const BasicBlock &BB, const Value *P, unsigned Size); + bool canBasicBlockModify(const BasicBlock &BB, const Location &Loc); + + /// canBasicBlockModify - A convenience wrapper. + bool canBasicBlockModify(const BasicBlock &BB, const Value *P, unsigned Size){ + return canBasicBlockModify(BB, Location(P, Size)); + } /// canInstructionRangeModify - Return true if it is possible for the /// execution of the specified instructions to modify the value pointed to by /// Ptr. The instructions to consider are all of the instructions in the /// range of [I1,I2] INCLUSIVE. I1 and I2 must be in the same basic block. - /// bool canInstructionRangeModify(const Instruction &I1, const Instruction &I2, - const Value *Ptr, unsigned Size); + const Location &Loc); + + /// canInstructionRangeModify - A convenience wrapper. + bool canInstructionRangeModify(const Instruction &I1, const Instruction &I2, + const Value *Ptr, unsigned Size) { + return canInstructionRangeModify(I1, I2, Location(Ptr, Size)); + } //===--------------------------------------------------------------------===// /// Methods that clients should call when they transform the program to allow @@ -401,17 +393,6 @@ copyValue(Old, New); deleteValue(Old); } - -protected: - /// getDependenceViaModRefInfo - Helper function for implementing getDependence - /// in implementations which already have getModRefInfo implementations. - DependenceResult getDependenceViaModRefInfo(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags); - }; /// isNoAliasCall - Return true if this pointer is returned by a noalias Modified: llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h Tue Sep 14 16:25:10 2010 @@ -36,7 +36,7 @@ ~LibCallAliasAnalysis(); ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size); + const Location &Loc); ModRefResult getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2) { @@ -64,7 +64,7 @@ private: ModRefResult AnalyzeLibCallDetails(const LibCallFunctionInfo *FI, ImmutableCallSite CS, - const Value *P, unsigned Size); + const Location &Loc); }; } // End of llvm namespace Modified: llvm/trunk/include/llvm/Analysis/LibCallSemantics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LibCallSemantics.h?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LibCallSemantics.h (original) +++ llvm/trunk/include/llvm/Analysis/LibCallSemantics.h Tue Sep 14 16:25:10 2010 @@ -48,7 +48,7 @@ Yes, No, Unknown }; LocResult (*isLocation)(ImmutableCallSite CS, - const Value *Ptr, unsigned Size); + const AliasAnalysis::Location &Loc); }; /// LibCallFunctionInfo - Each record in the array of FunctionInfo structs Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Tue Sep 14 16:25:10 2010 @@ -37,7 +37,8 @@ // Pinned metadata names, which always have the same value. This is a // compile-time performance optimization, not a correctness optimization. enum { - MD_dbg = 0 // "dbg" + MD_dbg = 0, // "dbg" + MD_tbaa = 1 // "tbaa" }; /// getMDKindID - Return a unique non-zero ID for the specified metadata kind. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Sep 14 16:25:10 2010 @@ -30,6 +30,7 @@ #include "llvm/Function.h" #include "llvm/IntrinsicInst.h" #include "llvm/Instructions.h" +#include "llvm/LLVMContext.h" #include "llvm/Type.h" #include "llvm/Target/TargetData.h" using namespace llvm; @@ -43,15 +44,14 @@ //===----------------------------------------------------------------------===// AliasAnalysis::AliasResult -AliasAnalysis::alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size) { +AliasAnalysis::alias(const Location &LocA, const Location &LocB) { assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); - return AA->alias(V1, V1Size, V2, V2Size); + return AA->alias(LocA, LocB); } -bool AliasAnalysis::pointsToConstantMemory(const Value *P) { +bool AliasAnalysis::pointsToConstantMemory(const Location &Loc) { assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); - return AA->pointsToConstantMemory(P); + return AA->pointsToConstantMemory(Loc); } void AliasAnalysis::deleteValue(Value *V) { @@ -66,7 +66,7 @@ AliasAnalysis::ModRefResult AliasAnalysis::getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { + const Location &Loc) { // Don't assert AA because BasicAA calls us in order to make use of the // logic here. @@ -81,7 +81,7 @@ bool doesAlias = false; for (ImmutableCallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); AI != AE; ++AI) - if (!isNoAlias(*AI, ~0U, P, Size)) { + if (!isNoAlias(Location(*AI), Loc)) { doesAlias = true; break; } @@ -90,9 +90,9 @@ return NoModRef; } - // If P points to a constant memory location, the call definitely could not + // If Loc is a constant memory location, the call definitely could not // modify the memory location. - if ((Mask & Mod) && pointsToConstantMemory(P)) + if ((Mask & Mod) && pointsToConstantMemory(Loc)) Mask = ModRefResult(Mask & ~Mod); // If this is BasicAA, don't forward. @@ -100,7 +100,7 @@ // Otherwise, fall back to the next AA in the chain. But we can merge // in any mask we've managed to compute. - return ModRefResult(AA->getModRefInfo(CS, P, Size) & Mask); + return ModRefResult(AA->getModRefInfo(CS, Loc) & Mask); } AliasAnalysis::ModRefResult @@ -188,31 +188,22 @@ return AA->getModRefBehavior(F); } -AliasAnalysis::DependenceResult -AliasAnalysis::getDependence(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags) { - assert(AA && "AA didn't call InitializeAliasAnalyais in its run method!"); - return AA->getDependence(First, FirstPHITranslatedAddr, FirstFlags, - Second, SecondPHITranslatedAddr, SecondFlags); -} - //===----------------------------------------------------------------------===// // AliasAnalysis non-virtual helper method implementation //===----------------------------------------------------------------------===// AliasAnalysis::ModRefResult -AliasAnalysis::getModRefInfo(const LoadInst *L, const Value *P, unsigned Size) { +AliasAnalysis::getModRefInfo(const LoadInst *L, const Location &Loc) { // Be conservative in the face of volatile. if (L->isVolatile()) return ModRef; // If the load address doesn't alias the given address, it doesn't read // or write the specified memory. - if (!alias(L->getOperand(0), getTypeStoreSize(L->getType()), P, Size)) + if (!alias(Location(L->getOperand(0), + getTypeStoreSize(L->getType()), + L->getMetadata(LLVMContext::MD_tbaa)), + Loc)) return NoModRef; // Otherwise, a load just reads. @@ -220,20 +211,22 @@ } AliasAnalysis::ModRefResult -AliasAnalysis::getModRefInfo(const StoreInst *S, const Value *P, unsigned Size) { +AliasAnalysis::getModRefInfo(const StoreInst *S, const Location &Loc) { // Be conservative in the face of volatile. if (S->isVolatile()) return ModRef; // If the store address cannot alias the pointer in question, then the // specified memory cannot be modified by the store. - if (!alias(S->getOperand(1), - getTypeStoreSize(S->getOperand(0)->getType()), P, Size)) + if (!alias(Location(S->getOperand(1), + getTypeStoreSize(S->getOperand(0)->getType()), + S->getMetadata(LLVMContext::MD_tbaa)), + Loc)) return NoModRef; // If the pointer is a pointer to constant memory, then it could not have been // modified by this store. - if (pointsToConstantMemory(P)) + if (pointsToConstantMemory(Loc)) return NoModRef; // Otherwise, a store just writes. @@ -241,240 +234,24 @@ } AliasAnalysis::ModRefResult -AliasAnalysis::getModRefInfo(const VAArgInst *V, const Value *P, unsigned Size) { +AliasAnalysis::getModRefInfo(const VAArgInst *V, const Location &Loc) { // If the va_arg address cannot alias the pointer in question, then the // specified memory cannot be accessed by the va_arg. - if (!alias(V->getOperand(0), UnknownSize, P, Size)) + if (!alias(Location(V->getOperand(0), + UnknownSize, + V->getMetadata(LLVMContext::MD_tbaa)), + Loc)) return NoModRef; // If the pointer is a pointer to constant memory, then it could not have been // modified by this va_arg. - if (pointsToConstantMemory(P)) + if (pointsToConstantMemory(Loc)) return NoModRef; // Otherwise, a va_arg reads and writes. return ModRef; } -AliasAnalysis::DependenceResult -AliasAnalysis::getDependenceViaModRefInfo(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags) { - if (const LoadInst *L = dyn_cast(First)) { - // Be over-conservative with volatile for now. - if (L->isVolatile()) - return Unknown; - - // If we don't have a phi-translated address, use the actual one. - if (!FirstPHITranslatedAddr) - FirstPHITranslatedAddr = L->getPointerOperand(); - - // Forward this query to getModRefInfo. - switch (getModRefInfo(Second, - FirstPHITranslatedAddr, - getTypeStoreSize(L->getType()))) { - case NoModRef: - // Second doesn't reference First's memory, so they're independent. - return Independent; - - case Ref: - // Second only reads from the memory read from by First. If it - // also writes to any other memory, be conservative. - if (Second->mayWriteToMemory()) - return Unknown; - - // If it's loading the same size from the same address, we can - // give a more precise result. - if (const LoadInst *SecondL = dyn_cast(Second)) { - // If we don't have a phi-translated address, use the actual one. - if (!SecondPHITranslatedAddr) - SecondPHITranslatedAddr = SecondL->getPointerOperand(); - - unsigned LSize = getTypeStoreSize(L->getType()); - unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); - if (alias(FirstPHITranslatedAddr, LSize, - SecondPHITranslatedAddr, SecondLSize) == - MustAlias) { - // If the loads are the same size, it's ReadThenRead. - if (LSize == SecondLSize) - return ReadThenRead; - - // If the second load is smaller, it's only ReadThenReadSome. - if (LSize > SecondLSize) - return ReadThenReadSome; - } - } - - // Otherwise it's just two loads. - return Independent; - - case Mod: - // Second only writes to the memory read from by First. If it - // also reads from any other memory, be conservative. - if (Second->mayReadFromMemory()) - return Unknown; - - // If it's storing the same size to the same address, we can - // give a more precise result. - if (const StoreInst *SecondS = dyn_cast(Second)) { - // If we don't have a phi-translated address, use the actual one. - if (!SecondPHITranslatedAddr) - SecondPHITranslatedAddr = SecondS->getPointerOperand(); - - unsigned LSize = getTypeStoreSize(L->getType()); - unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); - if (alias(FirstPHITranslatedAddr, LSize, - SecondPHITranslatedAddr, SecondSSize) == - MustAlias) { - // If the load and the store are the same size, it's ReadThenWrite. - if (LSize == SecondSSize) - return ReadThenWrite; - } - } - - // Otherwise we don't know if it could be writing to other memory. - return Unknown; - - case ModRef: - // Second reads and writes to the memory read from by First. - // We don't have a way to express that. - return Unknown; - } - - } else if (const StoreInst *S = dyn_cast(First)) { - // Be over-conservative with volatile for now. - if (S->isVolatile()) - return Unknown; - - // If we don't have a phi-translated address, use the actual one. - if (!FirstPHITranslatedAddr) - FirstPHITranslatedAddr = S->getPointerOperand(); - - // Forward this query to getModRefInfo. - switch (getModRefInfo(Second, - FirstPHITranslatedAddr, - getTypeStoreSize(S->getValueOperand()->getType()))) { - case NoModRef: - // Second doesn't reference First's memory, so they're independent. - return Independent; - - case Ref: - // Second only reads from the memory written to by First. If it - // also writes to any other memory, be conservative. - if (Second->mayWriteToMemory()) - return Unknown; - - // If it's loading the same size from the same address, we can - // give a more precise result. - if (const LoadInst *SecondL = dyn_cast(Second)) { - // If we don't have a phi-translated address, use the actual one. - if (!SecondPHITranslatedAddr) - SecondPHITranslatedAddr = SecondL->getPointerOperand(); - - unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); - unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); - if (alias(FirstPHITranslatedAddr, SSize, - SecondPHITranslatedAddr, SecondLSize) == - MustAlias) { - // If the store and the load are the same size, it's WriteThenRead. - if (SSize == SecondLSize) - return WriteThenRead; - - // If the load is smaller, it's only WriteThenReadSome. - if (SSize > SecondLSize) - return WriteThenReadSome; - } - } - - // Otherwise we don't know if it could be reading from other memory. - return Unknown; - - case Mod: - // Second only writes to the memory written to by First. If it - // also reads from any other memory, be conservative. - if (Second->mayReadFromMemory()) - return Unknown; - - // If it's storing the same size to the same address, we can - // give a more precise result. - if (const StoreInst *SecondS = dyn_cast(Second)) { - // If we don't have a phi-translated address, use the actual one. - if (!SecondPHITranslatedAddr) - SecondPHITranslatedAddr = SecondS->getPointerOperand(); - - unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); - unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); - if (alias(FirstPHITranslatedAddr, SSize, - SecondPHITranslatedAddr, SecondSSize) == - MustAlias) { - // If the stores are the same size, it's WriteThenWrite. - if (SSize == SecondSSize) - return WriteThenWrite; - - // If the second store is larger, it's only WriteSomeThenWrite. - if (SSize < SecondSSize) - return WriteSomeThenWrite; - } - } - - // Otherwise we don't know if it could be writing to other memory. - return Unknown; - - case ModRef: - // Second reads and writes to the memory written to by First. - // We don't have a way to express that. - return Unknown; - } - - } else if (const VAArgInst *V = dyn_cast(First)) { - // If we don't have a phi-translated address, use the actual one. - if (!FirstPHITranslatedAddr) - FirstPHITranslatedAddr = V->getPointerOperand(); - - // Forward this query to getModRefInfo. - if (getModRefInfo(Second, FirstPHITranslatedAddr, UnknownSize) == NoModRef) - // Second doesn't reference First's memory, so they're independent. - return Independent; - - } else if (ImmutableCallSite FirstCS = cast(First)) { - assert(!FirstPHITranslatedAddr && - !SecondPHITranslatedAddr && - "PHI translation with calls not supported yet!"); - - // If both instructions are calls/invokes we can use the two-callsite - // form of getModRefInfo. - if (ImmutableCallSite SecondCS = cast(Second)) - // getModRefInfo's arguments are backwards from intuition. - switch (getModRefInfo(SecondCS, FirstCS)) { - case NoModRef: - // Second doesn't reference First's memory, so they're independent. - return Independent; - - case Ref: - // If they're both read-only, there's no dependence. - if (FirstCS.onlyReadsMemory() && SecondCS.onlyReadsMemory()) - return Independent; - - // Otherwise it's not obvious what we can do here. - return Unknown; - - case Mod: - // It's not obvious what we can do here. - return Unknown; - - case ModRef: - // I know, right? - return Unknown; - } - } - - // For anything else, be conservative. - return Unknown; -} - AliasAnalysis::ModRefBehavior AliasAnalysis::getIntrinsicModRefBehavior(unsigned iid) { #define GET_INTRINSIC_MODREF_BEHAVIOR @@ -514,8 +291,8 @@ /// specified basic block to modify the value pointed to by Ptr. /// bool AliasAnalysis::canBasicBlockModify(const BasicBlock &BB, - const Value *Ptr, unsigned Size) { - return canInstructionRangeModify(BB.front(), BB.back(), Ptr, Size); + const Location &Loc) { + return canInstructionRangeModify(BB.front(), BB.back(), Loc); } /// canInstructionRangeModify - Return true if it is possible for the execution @@ -525,7 +302,7 @@ /// bool AliasAnalysis::canInstructionRangeModify(const Instruction &I1, const Instruction &I2, - const Value *Ptr, unsigned Size) { + const Location &Loc) { assert(I1.getParent() == I2.getParent() && "Instructions not in same basic block!"); BasicBlock::const_iterator I = &I1; @@ -533,7 +310,7 @@ ++E; // Convert from inclusive to exclusive range. for (; I != E; ++I) // Check every instruction in range - if (getModRefInfo(I, Ptr, Size) & Mod) + if (getModRefInfo(I, Loc) & Mod) return true; return false; } Modified: llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp Tue Sep 14 16:25:10 2010 @@ -94,17 +94,16 @@ } // FIXME: We could count these too... - bool pointsToConstantMemory(const Value *P) { - return getAnalysis().pointsToConstantMemory(P); + bool pointsToConstantMemory(const Location &Loc) { + return getAnalysis().pointsToConstantMemory(Loc); } // Forwarding functions: just delegate to a real AA implementation, counting // the number of responses... - AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size); + AliasResult alias(const Location &LocA, const Location &LocB); ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size); + const Location &Loc); ModRefResult getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2) { return AliasAnalysis::getModRefInfo(CS1,CS2); @@ -121,9 +120,8 @@ } AliasAnalysis::AliasResult -AliasAnalysisCounter::alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size) { - AliasResult R = getAnalysis().alias(V1, V1Size, V2, V2Size); +AliasAnalysisCounter::alias(const Location &LocA, const Location &LocB) { + AliasResult R = getAnalysis().alias(LocA, LocB); const char *AliasString; switch (R) { @@ -135,11 +133,11 @@ if (PrintAll || (PrintAllFailures && R == MayAlias)) { errs() << AliasString << ":\t"; - errs() << "[" << V1Size << "B] "; - WriteAsOperand(errs(), V1, true, M); + errs() << "[" << LocA.Size << "B] "; + WriteAsOperand(errs(), LocA.Ptr, true, M); errs() << ", "; - errs() << "[" << V2Size << "B] "; - WriteAsOperand(errs(), V2, true, M); + errs() << "[" << LocB.Size << "B] "; + WriteAsOperand(errs(), LocB.Ptr, true, M); errs() << "\n"; } @@ -148,8 +146,8 @@ AliasAnalysis::ModRefResult AliasAnalysisCounter::getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { - ModRefResult R = getAnalysis().getModRefInfo(CS, P, Size); + const Location &Loc) { + ModRefResult R = getAnalysis().getModRefInfo(CS, Loc); const char *MRString; switch (R) { @@ -162,8 +160,8 @@ if (PrintAll || (PrintAllFailures && R == ModRef)) { errs() << MRString << ": Ptr: "; - errs() << "[" << Size << "B] "; - WriteAsOperand(errs(), P, true, M); + errs() << "[" << Loc.Size << "B] "; + WriteAsOperand(errs(), Loc.Ptr, true, M); errs() << "\t<->" << *CS.getInstruction() << '\n'; } return R; Modified: llvm/trunk/lib/Analysis/AliasDebugger.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasDebugger.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasDebugger.cpp (original) +++ llvm/trunk/lib/Analysis/AliasDebugger.cpp Tue Sep 14 16:25:10 2010 @@ -92,17 +92,18 @@ //------------------------------------------------ // Implement the AliasAnalysis API // - AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size) { - assert(Vals.find(V1) != Vals.end() && "Never seen value in AA before"); - assert(Vals.find(V2) != Vals.end() && "Never seen value in AA before"); - return AliasAnalysis::alias(V1, V1Size, V2, V2Size); + AliasResult alias(const Location &LocA, const Location &LocB) { + assert(Vals.find(LocA.Ptr) != Vals.end() && + "Never seen value in AA before"); + assert(Vals.find(LocB.Ptr) != Vals.end() && + "Never seen value in AA before"); + return AliasAnalysis::alias(LocA, LocB); } ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { - assert(Vals.find(P) != Vals.end() && "Never seen value in AA before"); - return AliasAnalysis::getModRefInfo(CS, P, Size); + const Location &Loc) { + assert(Vals.find(Loc.Ptr) != Vals.end() && "Never seen value in AA before"); + return AliasAnalysis::getModRefInfo(CS, Loc); } ModRefResult getModRefInfo(ImmutableCallSite CS1, @@ -110,9 +111,9 @@ return AliasAnalysis::getModRefInfo(CS1,CS2); } - bool pointsToConstantMemory(const Value *P) { - assert(Vals.find(P) != Vals.end() && "Never seen value in AA before"); - return AliasAnalysis::pointsToConstantMemory(P); + bool pointsToConstantMemory(const Location &Loc) { + assert(Vals.find(Loc.Ptr) != Vals.end() && "Never seen value in AA before"); + return AliasAnalysis::pointsToConstantMemory(Loc); } virtual void deleteValue(Value *V) { Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep 14 16:25:10 2010 @@ -22,6 +22,7 @@ #include "llvm/GlobalVariable.h" #include "llvm/Instructions.h" #include "llvm/IntrinsicInst.h" +#include "llvm/LLVMContext.h" #include "llvm/Operator.h" #include "llvm/Pass.h" #include "llvm/Analysis/CaptureTracking.h" @@ -149,8 +150,7 @@ TD = getAnalysisIfAvailable(); } - virtual AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size) { + virtual AliasResult alias(const Location &LocA, const Location &LocB) { return MayAlias; } @@ -161,9 +161,9 @@ return UnknownModRefBehavior; } - virtual bool pointsToConstantMemory(const Value *P) { return false; } + virtual bool pointsToConstantMemory(const Location &Loc) { return false; } virtual ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { + const Location &Loc) { return ModRef; } virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, @@ -171,15 +171,6 @@ return ModRef; } - virtual DependenceResult getDependence(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags) { - return Unknown; - } - virtual void deleteValue(Value *V) {} virtual void copyValue(Value *From, Value *To) {} @@ -501,18 +492,18 @@ static char ID; // Class identification, replacement for typeinfo BasicAliasAnalysis() : NoAA(ID) {} - virtual AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size) { + virtual AliasResult alias(const Location &LocA, + const Location &LocB) { assert(Visited.empty() && "Visited must be cleared after use!"); - assert(notDifferentParent(V1, V2) && + assert(notDifferentParent(LocA.Ptr, LocB.Ptr) && "BasicAliasAnalysis doesn't support interprocedural queries."); - AliasResult Alias = aliasCheck(V1, V1Size, V2, V2Size); + AliasResult Alias = aliasCheck(LocA.Ptr, LocA.Size, LocB.Ptr, LocB.Size); Visited.clear(); return Alias; } virtual ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size); + const Location &Loc); virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2) { @@ -522,7 +513,7 @@ /// pointsToConstantMemory - Chase pointers until we find a (constant /// global) or not. - virtual bool pointsToConstantMemory(const Value *P); + virtual bool pointsToConstantMemory(const Location &Loc); /// getModRefBehavior - Return the behavior when calling the given /// call site. @@ -532,13 +523,6 @@ /// For use when the call site is not known. virtual ModRefBehavior getModRefBehavior(const Function *F); - virtual DependenceResult getDependence(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags); - /// getAdjustedAnalysisPointer - This method is used when a pass implements /// an analysis interface through multiple inheritance. If needed, it /// should override this to adjust the this pointer as needed for the @@ -586,15 +570,15 @@ /// pointsToConstantMemory - Chase pointers until we find a (constant /// global) or not. -bool BasicAliasAnalysis::pointsToConstantMemory(const Value *P) { +bool BasicAliasAnalysis::pointsToConstantMemory(const Location &Loc) { if (const GlobalVariable *GV = - dyn_cast(P->getUnderlyingObject())) + dyn_cast(Loc.Ptr->getUnderlyingObject())) // Note: this doesn't require GV to be "ODR" because it isn't legal for a // global to be marked constant in some modules and non-constant in others. // GV may even be a declaration, not a definition. return GV->isConstant(); - return NoAA::pointsToConstantMemory(P); + return NoAA::pointsToConstantMemory(Loc); } /// getModRefBehavior - Return the behavior when calling the given call site. @@ -636,13 +620,13 @@ /// simple "address taken" analysis on local objects. AliasAnalysis::ModRefResult BasicAliasAnalysis::getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { - assert(notDifferentParent(CS.getInstruction(), P) && + const Location &Loc) { + assert(notDifferentParent(CS.getInstruction(), Loc.Ptr) && "AliasAnalysis query involving multiple functions!"); - const Value *Object = P->getUnderlyingObject(); + const Value *Object = Loc.Ptr->getUnderlyingObject(); - // If this is a tail call and P points to a stack location, we know that + // If this is a tail call and Loc.Ptr points to a stack location, we know that // the tail call cannot access or modify the local stack. // We cannot exclude byval arguments here; these belong to the caller of // the current function not to the current function, and a tail callee @@ -666,11 +650,11 @@ !CS.paramHasAttr(ArgNo+1, Attribute::NoCapture)) continue; - // If this is a no-capture pointer argument, see if we can tell that it + // If this is a no-capture pointer argument, see if we can tell that it // is impossible to alias the pointer we're checking. If not, we have to // assume that the call could touch the pointer, even though it doesn't // escape. - if (!isNoAlias(cast(CI), UnknownSize, P, UnknownSize)) { + if (!isNoAlias(Location(cast(CI)), Loc)) { PassedAsArg = true; break; } @@ -692,8 +676,8 @@ Len = LenCI->getZExtValue(); Value *Dest = II->getArgOperand(0); Value *Src = II->getArgOperand(1); - if (isNoAlias(Dest, Len, P, Size)) { - if (isNoAlias(Src, Len, P, Size)) + if (isNoAlias(Location(Dest, Len), Loc)) { + if (isNoAlias(Location(Src, Len), Loc)) return NoModRef; return Ref; } @@ -705,7 +689,7 @@ if (ConstantInt *LenCI = dyn_cast(II->getArgOperand(2))) { unsigned Len = LenCI->getZExtValue(); Value *Dest = II->getArgOperand(0); - if (isNoAlias(Dest, Len, P, Size)) + if (isNoAlias(Location(Dest, Len), Loc)) return NoModRef; } break; @@ -724,7 +708,8 @@ if (TD) { Value *Op1 = II->getArgOperand(0); unsigned Op1Size = TD->getTypeStoreSize(Op1->getType()); - if (isNoAlias(Op1, Op1Size, P, Size)) + MDNode *Tag = II->getMetadata(LLVMContext::MD_tbaa); + if (isNoAlias(Location(Op1, Op1Size, Tag), Loc)) return NoModRef; } break; @@ -733,33 +718,27 @@ case Intrinsic::invariant_start: { unsigned PtrSize = cast(II->getArgOperand(0))->getZExtValue(); - if (isNoAlias(II->getArgOperand(1), PtrSize, P, Size)) + if (isNoAlias(Location(II->getArgOperand(1), + PtrSize, + II->getMetadata(LLVMContext::MD_tbaa)), + Loc)) return NoModRef; break; } case Intrinsic::invariant_end: { unsigned PtrSize = cast(II->getArgOperand(1))->getZExtValue(); - if (isNoAlias(II->getArgOperand(2), PtrSize, P, Size)) + if (isNoAlias(Location(II->getArgOperand(2), + PtrSize, + II->getMetadata(LLVMContext::MD_tbaa)), + Loc)) return NoModRef; break; } } // The AliasAnalysis base class has some smarts, lets use them. - return AliasAnalysis::getModRefInfo(CS, P, Size); -} - -AliasAnalysis::DependenceResult -BasicAliasAnalysis::getDependence(const Instruction *First, - const Value *FirstPHITranslatedAddr, - DependenceQueryFlags FirstFlags, - const Instruction *Second, - const Value *SecondPHITranslatedAddr, - DependenceQueryFlags SecondFlags) { - // We don't have anything special to say yet. - return getDependenceViaModRefInfo(First, FirstPHITranslatedAddr, FirstFlags, - Second, SecondPHITranslatedAddr, SecondFlags); + return AliasAnalysis::getModRefInfo(CS, Loc); } /// aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP instruction @@ -1103,7 +1082,7 @@ if (const SelectInst *S1 = dyn_cast(V1)) return aliasSelect(S1, V1Size, V2, V2Size); - return NoAA::alias(V1, V1Size, V2, V2Size); + return NoAA::alias(Location(V1, V1Size), Location(V2, V2Size)); } // Make sure that anything that uses AliasAnalysis pulls in this file. Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Tue Sep 14 16:25:10 2010 @@ -106,10 +106,9 @@ //------------------------------------------------ // Implement the AliasAnalysis API // - AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size); + AliasResult alias(const Location &LocA, const Location &LocB); ModRefResult getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size); + const Location &Loc); ModRefResult getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2) { return AliasAnalysis::getModRefInfo(CS1, CS2); @@ -476,11 +475,11 @@ /// other is some random pointer, we know there cannot be an alias, because the /// address of the global isn't taken. AliasAnalysis::AliasResult -GlobalsModRef::alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size) { +GlobalsModRef::alias(const Location &LocA, + const Location &LocB) { // Get the base object these pointers point to. - const Value *UV1 = V1->getUnderlyingObject(); - const Value *UV2 = V2->getUnderlyingObject(); + const Value *UV1 = LocA.Ptr->getUnderlyingObject(); + const Value *UV2 = LocB.Ptr->getUnderlyingObject(); // If either of the underlying values is a global, they may be non-addr-taken // globals, which we can answer queries about. @@ -528,17 +527,18 @@ if ((GV1 || GV2) && GV1 != GV2) return NoAlias; - return AliasAnalysis::alias(V1, V1Size, V2, V2Size); + return AliasAnalysis::alias(LocA, LocB); } AliasAnalysis::ModRefResult GlobalsModRef::getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { + const Location &Loc) { unsigned Known = ModRef; // If we are asking for mod/ref info of a direct call with a pointer to a // global we are tracking, return information if we have it. - if (const GlobalValue *GV = dyn_cast(P->getUnderlyingObject())) + if (const GlobalValue *GV = + dyn_cast(Loc.Ptr->getUnderlyingObject())) if (GV->hasLocalLinkage()) if (const Function *F = CS.getCalledFunction()) if (NonAddressTakenGlobals.count(GV)) @@ -547,7 +547,7 @@ if (Known == NoModRef) return NoModRef; // No need to query other mod/ref analyses - return ModRefResult(Known & AliasAnalysis::getModRefInfo(CS, P, Size)); + return ModRefResult(Known & AliasAnalysis::getModRefInfo(CS, Loc)); } Modified: llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp Tue Sep 14 16:25:10 2010 @@ -43,8 +43,8 @@ /// vs the specified pointer/size. AliasAnalysis::ModRefResult LibCallAliasAnalysis::AnalyzeLibCallDetails(const LibCallFunctionInfo *FI, - ImmutableCallSite CS, const Value *P, - unsigned Size) { + ImmutableCallSite CS, + const Location &Loc) { // If we have a function, check to see what kind of mod/ref effects it // has. Start by including any info globally known about the function. AliasAnalysis::ModRefResult MRInfo = FI->UniversalBehavior; @@ -64,9 +64,9 @@ if (FI->DetailsType == LibCallFunctionInfo::DoesNot) { // Find out if the pointer refers to a known location. for (unsigned i = 0; Details[i].LocationID != ~0U; ++i) { - const LibCallLocationInfo &Loc = + const LibCallLocationInfo &LocInfo = LCI->getLocationInfo(Details[i].LocationID); - LibCallLocationInfo::LocResult Res = Loc.isLocation(CS, P, Size); + LibCallLocationInfo::LocResult Res = LocInfo.isLocation(CS, Loc); if (Res != LibCallLocationInfo::Yes) continue; // If we find a match against a location that we 'do not' interact with, @@ -85,9 +85,9 @@ // Find out if the pointer refers to a known location. bool NoneMatch = true; for (unsigned i = 0; Details[i].LocationID != ~0U; ++i) { - const LibCallLocationInfo &Loc = + const LibCallLocationInfo &LocInfo = LCI->getLocationInfo(Details[i].LocationID); - LibCallLocationInfo::LocResult Res = Loc.isLocation(CS, P, Size); + LibCallLocationInfo::LocResult Res = LocInfo.isLocation(CS, Loc); if (Res == LibCallLocationInfo::No) continue; // If we don't know if this pointer points to the location, then we have to @@ -118,7 +118,7 @@ // AliasAnalysis::ModRefResult LibCallAliasAnalysis::getModRefInfo(ImmutableCallSite CS, - const Value *P, unsigned Size) { + const Location &Loc) { ModRefResult MRInfo = ModRef; // If this is a direct call to a function that LCI knows about, get the @@ -126,12 +126,12 @@ if (LCI) { if (const Function *F = CS.getCalledFunction()) { if (const LibCallFunctionInfo *FI = LCI->getFunctionInfo(F)) { - MRInfo = ModRefResult(MRInfo & AnalyzeLibCallDetails(FI, CS, P, Size)); + MRInfo = ModRefResult(MRInfo & AnalyzeLibCallDetails(FI, CS, Loc)); if (MRInfo == NoModRef) return NoModRef; } } } // The AliasAnalysis base class has some smarts, lets use them. - return (ModRefResult)(MRInfo | AliasAnalysis::getModRefInfo(CS, P, Size)); + return (ModRefResult)(MRInfo | AliasAnalysis::getModRefInfo(CS, Loc)); } Modified: llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp Tue Sep 14 16:25:10 2010 @@ -49,8 +49,7 @@ private: virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual bool runOnFunction(Function &F); - virtual AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size); + virtual AliasResult alias(const Location &LocA, const Location &LocB); Value *GetBaseValue(const SCEV *S); }; @@ -101,17 +100,17 @@ } AliasAnalysis::AliasResult -ScalarEvolutionAliasAnalysis::alias(const Value *A, unsigned ASize, - const Value *B, unsigned BSize) { +ScalarEvolutionAliasAnalysis::alias(const Location &LocA, + const Location &LocB) { // If either of the memory references is empty, it doesn't matter what the // pointer values are. This allows the code below to ignore this special // case. - if (ASize == 0 || BSize == 0) + if (LocA.Size == 0 || LocB.Size == 0) return NoAlias; // This is ScalarEvolutionAliasAnalysis. Get the SCEVs! - const SCEV *AS = SE->getSCEV(const_cast(A)); - const SCEV *BS = SE->getSCEV(const_cast(B)); + const SCEV *AS = SE->getSCEV(const_cast(LocA.Ptr)); + const SCEV *BS = SE->getSCEV(const_cast(LocB.Ptr)); // If they evaluate to the same expression, it's a MustAlias. if (AS == BS) return MustAlias; @@ -121,8 +120,8 @@ if (SE->getEffectiveSCEVType(AS->getType()) == SE->getEffectiveSCEVType(BS->getType())) { unsigned BitWidth = SE->getTypeSizeInBits(AS->getType()); - APInt ASizeInt(BitWidth, ASize); - APInt BSizeInt(BitWidth, BSize); + APInt ASizeInt(BitWidth, LocA.Size); + APInt BSizeInt(BitWidth, LocB.Size); // Compute the difference between the two pointers. const SCEV *BA = SE->getMinusSCEV(BS, AS); @@ -154,11 +153,15 @@ // inttoptr and ptrtoint operators. Value *AO = GetBaseValue(AS); Value *BO = GetBaseValue(BS); - if ((AO && AO != A) || (BO && BO != B)) - if (alias(AO ? AO : A, AO ? UnknownSize : ASize, - BO ? BO : B, BO ? UnknownSize : BSize) == NoAlias) + if ((AO && AO != LocA.Ptr) || (BO && BO != LocB.Ptr)) + if (alias(Location(AO ? AO : LocA.Ptr, + AO ? +UnknownSize : LocA.Size, + AO ? 0 : LocA.TBAATag), + Location(BO ? BO : LocB.Ptr, + BO ? +UnknownSize : LocB.Size, + BO ? 0 : LocB.TBAATag)) == NoAlias) return NoAlias; // Forward the query to the next analysis. - return AliasAnalysis::alias(A, ASize, B, BSize); + return AliasAnalysis::alias(LocA, LocB); } Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Tue Sep 14 16:25:10 2010 @@ -96,9 +96,8 @@ private: virtual void getAnalysisUsage(AnalysisUsage &AU) const; - virtual AliasResult alias(const Value *V1, unsigned V1Size, - const Value *V2, unsigned V2Size); - virtual bool pointsToConstantMemory(const Value *P); + virtual AliasResult alias(const Location &LocA, const Location &LocB); + virtual bool pointsToConstantMemory(const Location &Loc); }; } // End of anonymous namespace @@ -118,12 +117,12 @@ } AliasAnalysis::AliasResult -TypeBasedAliasAnalysis::alias(const Value *A, unsigned ASize, - const Value *B, unsigned BSize) { +TypeBasedAliasAnalysis::alias(const Location &LocA, + const Location &LocB) { // Currently, metadata can only be attached to Instructions. - const Instruction *AI = dyn_cast(A); + const Instruction *AI = dyn_cast(LocA.Ptr); if (!AI) return MayAlias; - const Instruction *BI = dyn_cast(B); + const Instruction *BI = dyn_cast(LocB.Ptr); if (!BI) return MayAlias; // Get the attached MDNodes. If either value lacks a tbaa MDNode, we must @@ -175,9 +174,9 @@ return MayAlias; } -bool TypeBasedAliasAnalysis::pointsToConstantMemory(const Value *P) { +bool TypeBasedAliasAnalysis::pointsToConstantMemory(const Location &Loc) { // Currently, metadata can only be attached to Instructions. - const Instruction *I = dyn_cast(P); + const Instruction *I = dyn_cast(Loc.Ptr); if (!I) return false; MDNode *M = Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=113858&r1=113857&r2=113858&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Tue Sep 14 16:25:10 2010 @@ -28,9 +28,16 @@ } LLVMContext::LLVMContext() : pImpl(new LLVMContextImpl(*this)) { - // Create the first metadata kind, which is always 'dbg'. + // Create the fixed metadata kinds. This is done in the same order as the + // MD_* enum values so that they correspond. + + // Create the 'dbg' metadata kind. unsigned DbgID = getMDKindID("dbg"); assert(DbgID == MD_dbg && "dbg kind id drifted"); (void)DbgID; + + // Create the 'tbaa' metadata kind. + unsigned TBAAID = getMDKindID("tbaa"); + assert(TBAAID == MD_tbaa && "tbaa kind id drifted"); (void)TBAAID; } LLVMContext::~LLVMContext() { delete pImpl; } From benny.kra at googlemail.com Tue Sep 14 16:25:38 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 14 Sep 2010 21:25:38 -0000 Subject: [llvm-commits] [llvm] r113859 - /llvm/trunk/include/llvm/TypeSymbolTable.h Message-ID: <20100914212538.4A5B62A6C12C@llvm.org> Author: d0k Date: Tue Sep 14 16:25:38 2010 New Revision: 113859 URL: http://llvm.org/viewvc/llvm-project?rev=113859&view=rev Log: Add missing include. Modified: llvm/trunk/include/llvm/TypeSymbolTable.h Modified: llvm/trunk/include/llvm/TypeSymbolTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/TypeSymbolTable.h?rev=113859&r1=113858&r2=113859&view=diff ============================================================================== --- llvm/trunk/include/llvm/TypeSymbolTable.h (original) +++ llvm/trunk/include/llvm/TypeSymbolTable.h Tue Sep 14 16:25:38 2010 @@ -16,12 +16,11 @@ #include "llvm/Type.h" #include "llvm/ADT/StringRef.h" +#include "llvm/System/DataTypes.h" #include namespace llvm { -class StringRef; - /// This class provides a symbol table of name/type pairs with operations to /// support constructing, searching and iterating over the symbol table. The /// class derives from AbstractTypeUser so that the contents of the symbol From grosbach at apple.com Tue Sep 14 16:28:17 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 21:28:17 -0000 Subject: [llvm-commits] [llvm] r113860 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20100914212817.42C292A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 16:28:17 2010 New Revision: 113860 URL: http://llvm.org/viewvc/llvm-project?rev=113860&view=rev Log: Add predicate and 's' bit operands to PICADD instruction lowering. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=113860&r1=113859&r2=113860&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Sep 14 16:28:17 2010 @@ -1349,6 +1349,11 @@ AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); + // Add predicate operands. + AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); + AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); + // Add 's' bit operand (always reg0 for this) + AddInst.addOperand(MCOperand::CreateReg(0)); OutStreamer.EmitInstruction(AddInst); return; } From bigcheesegs at gmail.com Tue Sep 14 16:31:02 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 14 Sep 2010 17:31:02 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: References: Message-ID: On Tue, Sep 14, 2010 at 5:18 PM, Michael Spencer wrote: > The attached patch adds the SwapByteOrder function template to System. > This patch is a > prerequisite for the object file library I am writing. > > I want to replace the functions in MathExtras.h with SwapByteOrder > because it is a generic implementation that makes it easier to write > generic byte order independent code. This patch has no functionality > changes. > > The optimized versions are platform dependent, and thus belong in System anyway. > > - Michael Spencer > It had to happen eventually :(. Now the patch it attached. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-System-Add-SwapByteOrder-and-update-Support-MathExtr.patch Type: application/octet-stream Size: 5012 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/159ac754/attachment.obj From bigcheesegs at gmail.com Tue Sep 14 16:53:26 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 14 Sep 2010 17:53:26 -0400 Subject: [llvm-commits] [PATCH][Support] Add Endian.h which contains generic code to deal with endian specific data. Message-ID: The attached patch adds Endian.h to Support. This patch is a prerequisite for the object file library I am writing. Endian.h contains: * SwapByteOrderIfDifferent This is a templated function that takes a value_type, and returns the value if host and target are the same, or returns the value with its endianness swapped if they are different. (host and target are int's because MSVC doesn't support enums used like this. see: http://stackoverflow.com/questions/2763836/sfinae-failing-with-enum-template-parameter) * endian This is a templated struct for reading endian specific data directly from memory. It is typedefed based on the host platform's endianness (well, not yet, because there's no LLVM_IS_BIG_ENDIAN or such yet). * packed_endian_specific_integral This is the most important thing included in this patch. This class allows the portable creation of packed structs of any integral integer value_type and endianness. Any struct that would be POD if it used normal integral data types is still POD if it uses these. This is used extensively in the object file library to directly access memory mapped object files. In the case when host and target endianness match (and the compiler inlines), using these should produce identical code to "*reinterpret_cast(memory)". - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-Support-Add-Endian.h.patch Type: application/octet-stream Size: 5854 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/5421b98d/attachment.obj From bob.wilson at apple.com Tue Sep 14 16:52:34 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 14 Sep 2010 21:52:34 -0000 Subject: [llvm-commits] [llvm] r113865 - /llvm/trunk/utils/TableGen/NeonEmitter.cpp Message-ID: <20100914215234.83E972A6C12C@llvm.org> Author: bwilson Date: Tue Sep 14 16:52:34 2010 New Revision: 113865 URL: http://llvm.org/viewvc/llvm-project?rev=113865&view=rev Log: Tidy whitespace in generated arm_neon.h. Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=113865&r1=113864&r2=113865&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Tue Sep 14 16:52:34 2010 @@ -912,7 +912,7 @@ OS << "typedef __attribute__(( __vector_size__("; OS << utostr(8*v*(quad ? 2 : 1)) << ") )) "; - if (!quad) + if (!quad && v == 1) OS << " "; OS << TypeString('s', TDTypeVec[i]); From ggreif at gmail.com Tue Sep 14 17:00:50 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 22:00:50 -0000 Subject: [llvm-commits] [llvm] r113867 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20100914220050.ADD372A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 17:00:50 2010 New Revision: 113867 URL: http://llvm.org/viewvc/llvm-project?rev=113867&view=rev Log: set isCompare for another three Thumb1 instructions Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=113867&r1=113866&r2=113867&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Sep 14 17:00:50 2010 @@ -630,7 +630,7 @@ T1DataProcessing<0b1110>; // CMN register -let Defs = [CPSR] in { +let isCompare = 1, Defs = [CPSR] in { //FIXME: Disable CMN, as CCodes are backwards from compare expectations // Compare-to-zero still works out, just not the relationals //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, @@ -644,7 +644,7 @@ } // CMP immediate -let Defs = [CPSR] in { +let isCompare = 1, Defs = [CPSR] in { def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, "cmp", "\t$lhs, $rhs", [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>, From echristo at apple.com Tue Sep 14 17:14:28 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 14 Sep 2010 15:14:28 -0700 Subject: [llvm-commits] [llvm] r113867 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td In-Reply-To: <20100914220050.ADD372A6C12C@llvm.org> References: <20100914220050.ADD372A6C12C@llvm.org> Message-ID: <78C11996-9A06-4692-B56A-2C17D127D12D@apple.com> On Sep 14, 2010, at 3:00 PM, Gabor Greif wrote: > Author: ggreif > Date: Tue Sep 14 17:00:50 2010 > New Revision: 113867 > > URL: http://llvm.org/viewvc/llvm-project?rev=113867&view=rev > Log: > set isCompare for another three Thumb1 instructions Looks like that's all of them. Thanks! -eric From grosbach at apple.com Tue Sep 14 17:20:33 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 22:20:33 -0000 Subject: [llvm-commits] [llvm] r113875 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100914222033.36E342A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 17:20:33 2010 New Revision: 113875 URL: http://llvm.org/viewvc/llvm-project?rev=113875&view=rev Log: The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01]). Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113875&r1=113874&r2=113875&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Tue Sep 14 17:20:33 2010 @@ -29,73 +29,27 @@ #undef MachineInstr #undef ARMAsmPrinter -static unsigned NextReg(unsigned Reg) { - switch (Reg) { +// Get the constituent sub-regs for a dregpair from a Q register. +static std::pair GetDRegPair(unsigned QReg) { + switch (QReg) { default: assert(0 && "Unexpected register enum"); - - case ARM::D0: - return ARM::D1; - case ARM::D1: - return ARM::D2; - case ARM::D2: - return ARM::D3; - case ARM::D3: - return ARM::D4; - case ARM::D4: - return ARM::D5; - case ARM::D5: - return ARM::D6; - case ARM::D6: - return ARM::D7; - case ARM::D7: - return ARM::D8; - case ARM::D8: - return ARM::D9; - case ARM::D9: - return ARM::D10; - case ARM::D10: - return ARM::D11; - case ARM::D11: - return ARM::D12; - case ARM::D12: - return ARM::D13; - case ARM::D13: - return ARM::D14; - case ARM::D14: - return ARM::D15; - case ARM::D15: - return ARM::D16; - case ARM::D16: - return ARM::D17; - case ARM::D17: - return ARM::D18; - case ARM::D18: - return ARM::D19; - case ARM::D19: - return ARM::D20; - case ARM::D20: - return ARM::D21; - case ARM::D21: - return ARM::D22; - case ARM::D22: - return ARM::D23; - case ARM::D23: - return ARM::D24; - case ARM::D24: - return ARM::D25; - case ARM::D25: - return ARM::D26; - case ARM::D26: - return ARM::D27; - case ARM::D27: - return ARM::D28; - case ARM::D28: - return ARM::D29; - case ARM::D29: - return ARM::D30; - case ARM::D30: - return ARM::D31; + case ARM::Q0: return std::pair(ARM::D0, ARM::D1); + case ARM::Q1: return std::pair(ARM::D2, ARM::D3); + case ARM::Q2: return std::pair(ARM::D4, ARM::D5); + case ARM::Q3: return std::pair(ARM::D6, ARM::D7); + case ARM::Q4: return std::pair(ARM::D8, ARM::D9); + case ARM::Q5: return std::pair(ARM::D10, ARM::D11); + case ARM::Q6: return std::pair(ARM::D12, ARM::D13); + case ARM::Q7: return std::pair(ARM::D14, ARM::D15); + case ARM::Q8: return std::pair(ARM::D16, ARM::D17); + case ARM::Q9: return std::pair(ARM::D18, ARM::D19); + case ARM::Q10: return std::pair(ARM::D20, ARM::D21); + case ARM::Q11: return std::pair(ARM::D22, ARM::D23); + case ARM::Q12: return std::pair(ARM::D24, ARM::D25); + case ARM::Q13: return std::pair(ARM::D26, ARM::D27); + case ARM::Q14: return std::pair(ARM::D28, ARM::D29); + case ARM::Q15: return std::pair(ARM::D30, ARM::D31); } } @@ -189,19 +143,11 @@ if (Op.isReg()) { unsigned Reg = Op.getReg(); if (Modifier && strcmp(Modifier, "dregpair") == 0) { - O << '{' << getRegisterName(Reg) << ", " - << getRegisterName(NextReg(Reg)) << '}'; -#if 0 - // FIXME: Breaks e.g. ARM/vmul.ll. - assert(0); - /* - unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0); - unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1); - O << '{' - << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) - << '}';*/ -#endif + std::pair dregpair = GetDRegPair(Reg); + O << '{' << getRegisterName(dregpair.first) << ", " + << getRegisterName(dregpair.second) << '}'; } else if (Modifier && strcmp(Modifier, "lane") == 0) { + // FIXME assert(0); /* unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); From ggreif at gmail.com Tue Sep 14 17:25:16 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 14 Sep 2010 22:25:16 -0000 Subject: [llvm-commits] [llvm] r113876 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100914222516.58A032A6C12C@llvm.org> Author: ggreif Date: Tue Sep 14 17:25:16 2010 New Revision: 113876 URL: http://llvm.org/viewvc/llvm-project?rev=113876&view=rev Log: an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113876&r1=113875&r2=113876&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 14 17:25:16 2010 @@ -1373,7 +1373,7 @@ CmpValue = MI->getOperand(1).getImm(); return true; case ARM::TSTri: { - if (MI->getParent()->begin() == MachineBasicBlock::const_iterator(MI)) + if (&*MI->getParent()->begin() == MI) return false; const MachineInstr *AND = llvm::prior(MI); if (AND->getOpcode() != ARM::ANDri) @@ -1385,6 +1385,7 @@ return true; } } + break; } return false; From grosbach at apple.com Tue Sep 14 17:27:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 22:27:15 -0000 Subject: [llvm-commits] [llvm] r113877 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100914222715.7A7132A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 17:27:15 2010 New Revision: 113877 URL: http://llvm.org/viewvc/llvm-project?rev=113877&view=rev Log: trailing whitespace cleanup Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113877&r1=113876&r2=113877&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Tue Sep 14 17:27:15 2010 @@ -175,10 +175,10 @@ // Break it up into two parts that make up a shifter immediate. V = ARM_AM::getSOImmVal(V); assert(V != -1 && "Not a valid so_imm value!"); - + unsigned Imm = ARM_AM::getSOImmValImm(V); unsigned Rot = ARM_AM::getSOImmValRot(V); - + // Print low-level immediate formation info, per // A5.1.3: "Data-processing operands - Immediate". if (Rot) { @@ -220,9 +220,9 @@ const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); - + O << getRegisterName(MO1.getReg()); - + // Print the shift opc. ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); O << ", " << ARM_AM::getShiftOpcStr(ShOpc); @@ -240,14 +240,14 @@ const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); - + if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, Op, O); return; } - + O << "[" << getRegisterName(MO1.getReg()); - + if (!MO2.getReg()) { if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0. O << ", #" @@ -256,24 +256,24 @@ O << "]"; return; } - + O << ", " << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) << getRegisterName(MO2.getReg()); - + if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) O << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm())) << " #" << ShImm; O << "]"; -} +} void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - + if (!MO1.getReg()) { unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); O << '#' @@ -281,10 +281,10 @@ << ImmOffs; return; } - + O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << getRegisterName(MO1.getReg()); - + if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm())) O << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm())) @@ -296,15 +296,15 @@ const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); - + O << '[' << getRegisterName(MO1.getReg()); - + if (MO2.getReg()) { O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm()) << getRegisterName(MO2.getReg()) << ']'; return; } - + if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) O << ", #" << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm())) @@ -317,13 +317,13 @@ raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - + if (MO1.getReg()) { O << (char)ARM_AM::getAM3Op(MO2.getImm()) << getRegisterName(MO1.getReg()); return; } - + unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); O << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) @@ -352,14 +352,14 @@ const char *Modifier) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - + if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, OpNum, O); return; } - + O << "[" << getRegisterName(MO1.getReg()); - + if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) { O << ", #" << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) @@ -372,7 +372,7 @@ raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); - + O << "[" << getRegisterName(MO1.getReg()); if (MO2.getImm()) { // FIXME: Both darwin as and GNU as violate ARM docs here. @@ -496,7 +496,7 @@ O << ARMCondCodeToString(CC); } -void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, +void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); From grosbach at apple.com Tue Sep 14 17:38:39 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 22:38:39 -0000 Subject: [llvm-commits] [llvm] r113878 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100914223839.A2B6F2A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 17:38:39 2010 New Revision: 113878 URL: http://llvm.org/viewvc/llvm-project?rev=113878&view=rev Log: revert 113875 momentarilly. Need to fix the MC disassembler to handle the change. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113878&r1=113877&r2=113878&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Tue Sep 14 17:38:39 2010 @@ -29,27 +29,73 @@ #undef MachineInstr #undef ARMAsmPrinter -// Get the constituent sub-regs for a dregpair from a Q register. -static std::pair GetDRegPair(unsigned QReg) { - switch (QReg) { +static unsigned NextReg(unsigned Reg) { + switch (Reg) { default: assert(0 && "Unexpected register enum"); - case ARM::Q0: return std::pair(ARM::D0, ARM::D1); - case ARM::Q1: return std::pair(ARM::D2, ARM::D3); - case ARM::Q2: return std::pair(ARM::D4, ARM::D5); - case ARM::Q3: return std::pair(ARM::D6, ARM::D7); - case ARM::Q4: return std::pair(ARM::D8, ARM::D9); - case ARM::Q5: return std::pair(ARM::D10, ARM::D11); - case ARM::Q6: return std::pair(ARM::D12, ARM::D13); - case ARM::Q7: return std::pair(ARM::D14, ARM::D15); - case ARM::Q8: return std::pair(ARM::D16, ARM::D17); - case ARM::Q9: return std::pair(ARM::D18, ARM::D19); - case ARM::Q10: return std::pair(ARM::D20, ARM::D21); - case ARM::Q11: return std::pair(ARM::D22, ARM::D23); - case ARM::Q12: return std::pair(ARM::D24, ARM::D25); - case ARM::Q13: return std::pair(ARM::D26, ARM::D27); - case ARM::Q14: return std::pair(ARM::D28, ARM::D29); - case ARM::Q15: return std::pair(ARM::D30, ARM::D31); + + case ARM::D0: + return ARM::D1; + case ARM::D1: + return ARM::D2; + case ARM::D2: + return ARM::D3; + case ARM::D3: + return ARM::D4; + case ARM::D4: + return ARM::D5; + case ARM::D5: + return ARM::D6; + case ARM::D6: + return ARM::D7; + case ARM::D7: + return ARM::D8; + case ARM::D8: + return ARM::D9; + case ARM::D9: + return ARM::D10; + case ARM::D10: + return ARM::D11; + case ARM::D11: + return ARM::D12; + case ARM::D12: + return ARM::D13; + case ARM::D13: + return ARM::D14; + case ARM::D14: + return ARM::D15; + case ARM::D15: + return ARM::D16; + case ARM::D16: + return ARM::D17; + case ARM::D17: + return ARM::D18; + case ARM::D18: + return ARM::D19; + case ARM::D19: + return ARM::D20; + case ARM::D20: + return ARM::D21; + case ARM::D21: + return ARM::D22; + case ARM::D22: + return ARM::D23; + case ARM::D23: + return ARM::D24; + case ARM::D24: + return ARM::D25; + case ARM::D25: + return ARM::D26; + case ARM::D26: + return ARM::D27; + case ARM::D27: + return ARM::D28; + case ARM::D28: + return ARM::D29; + case ARM::D29: + return ARM::D30; + case ARM::D30: + return ARM::D31; } } @@ -143,11 +189,19 @@ if (Op.isReg()) { unsigned Reg = Op.getReg(); if (Modifier && strcmp(Modifier, "dregpair") == 0) { - std::pair dregpair = GetDRegPair(Reg); - O << '{' << getRegisterName(dregpair.first) << ", " - << getRegisterName(dregpair.second) << '}'; + O << '{' << getRegisterName(Reg) << ", " + << getRegisterName(NextReg(Reg)) << '}'; +#if 0 + // FIXME: Breaks e.g. ARM/vmul.ll. + assert(0); + /* + unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0); + unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1); + O << '{' + << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) + << '}';*/ +#endif } else if (Modifier && strcmp(Modifier, "lane") == 0) { - // FIXME assert(0); /* unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); From gkistanova at gmail.com Tue Sep 14 17:52:45 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 14 Sep 2010 22:52:45 -0000 Subject: [llvm-commits] [zorg] r113882 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100914225245.71B212A6C12C@llvm.org> Author: gkistanova Date: Tue Sep 14 17:52:45 2010 New Revision: 113882 URL: http://llvm.org/viewvc/llvm-project?rev=113882&view=rev Log: Increased number of threads for llvm-gcc-native-mingw32-win7 builder. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=113882&r1=113881&r2=113882&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Tue Sep 14 17:52:45 2010 @@ -494,12 +494,14 @@ 'haltOnFailure' : True }, {'name' : 'make_llvm', 'description' : 'make llvm', + 'extra_args' : ['-j4'], # Extra step-specific properties 'haltOnFailure' : True }, {'name' : 'configure_llvmgcc', 'description' : 'configure llvm-gcc', 'haltOnFailure' : True }, {'name' : 'make_llvmgcc', 'description' : 'make llvm-gcc', + 'extra_args' : ['-j4'], 'haltOnFailure' : True }, {'name' : 'install_llvmgcc', 'description' : 'install llvm-gcc', From echristo at apple.com Tue Sep 14 18:03:37 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 14 Sep 2010 23:03:37 -0000 Subject: [llvm-commits] [llvm] r113886 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100914230337.CAE6D2A6C12C@llvm.org> Author: echristo Date: Tue Sep 14 18:03:37 2010 New Revision: 113886 URL: http://llvm.org/viewvc/llvm-project?rev=113886&view=rev Log: Emit libcalls for SDIV, this requires some call infrastructure that needs to be shared a bit more widely around. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113886&r1=113885&r2=113886&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Sep 14 18:03:37 2010 @@ -24,6 +24,7 @@ #include "llvm/GlobalVariable.h" #include "llvm/Instructions.h" #include "llvm/IntrinsicInst.h" +#include "llvm/Module.h" #include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/FastISel.h" #include "llvm/CodeGen/FunctionLoweringInfo.h" @@ -121,6 +122,7 @@ virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode); virtual bool ARMSelectSIToFP(const Instruction *I); virtual bool ARMSelectFPToSI(const Instruction *I); + virtual bool ARMSelectSDiv(const Instruction *I); // Utility routines. private: @@ -139,6 +141,7 @@ // Call handling routines. private: CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return); + bool ARMEmitLibcall(const Instruction *I, Function *F); // OptionalDef handling routines. private: @@ -931,6 +934,155 @@ } } +// A quick function that will emit a call for a named libcall in F with the +// vector of passed arguments for the Instruction in I. We can assume that we +// can emit a call for any libcall we can produce. This is an abridged version +// of the full call infrastructure since we won't need to worry about things +// like computed function pointers or strange arguments at call sites. +// TODO: Try to unify this and the normal call bits for ARM, then try to unify +// with X86. +bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) { + CallingConv::ID CC = F->getCallingConv(); + + // Handle *simple* calls for now. + const Type *RetTy = F->getReturnType(); + EVT RetVT; + if (RetTy->isVoidTy()) + RetVT = MVT::isVoid; + else if (!isTypeLegal(RetTy, RetVT)) + return false; + + assert(!F->isVarArg() && "Vararg libcall?!"); + + // Abridged from the X86 FastISel call selection mechanism + SmallVector Args; + SmallVector ArgRegs; + SmallVector ArgVTs; + SmallVector ArgFlags; + Args.reserve(I->getNumOperands()); + ArgRegs.reserve(I->getNumOperands()); + ArgVTs.reserve(I->getNumOperands()); + ArgFlags.reserve(I->getNumOperands()); + for (unsigned i = 0; i < Args.size(); ++i) { + Value *Op = I->getOperand(i); + unsigned Arg = getRegForValue(Op); + if (Arg == 0) return false; + + const Type *ArgTy = Op->getType(); + EVT ArgVT; + if (!isTypeLegal(ArgTy, ArgVT)) return false; + + ISD::ArgFlagsTy Flags; + unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); + Flags.setOrigAlign(OriginalAlignment); + + Args.push_back(Op); + ArgRegs.push_back(Arg); + ArgVTs.push_back(ArgVT); + ArgFlags.push_back(Flags); + } + + SmallVector ArgLocs; + CCState CCInfo(CC, false, TM, ArgLocs, F->getContext()); + CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false)); + + // Process the args. + SmallVector RegArgs; + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + unsigned Arg = ArgRegs[VA.getValNo()]; + EVT ArgVT = ArgVTs[VA.getValNo()]; + + // Should we ever have to promote? + switch (VA.getLocInfo()) { + case CCValAssign::Full: break; + default: + assert(false && "Handle arg promotion for libcalls?"); + return false; + } + + // Now copy/store arg to correct locations. + if (VA.isRegLoc()) { + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), + VA.getLocReg()).addReg(Arg); + RegArgs.push_back(VA.getLocReg()); + } else { + // Need to store + return false; + } + } + + // Issue the call, BLr9 for darwin, BL otherwise. + MachineInstrBuilder MIB; + unsigned CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL; + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) + .addGlobalAddress(F, 0, 0); + + // Add implicit physical register uses to the call. + for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) + MIB.addReg(RegArgs[i]); + + // Now the return value. + SmallVector UsedRegs; + if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { + SmallVector RVLocs; + CCState CCInfo(CC, false, TM, RVLocs, F->getContext()); + CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true)); + + // Copy all of the result registers out of their specified physreg. + assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); + EVT CopyVT = RVLocs[0].getValVT(); + TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); + + unsigned ResultReg = createResultReg(DstRC); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), + ResultReg).addReg(RVLocs[0].getLocReg()); + UsedRegs.push_back(RVLocs[0].getLocReg()); + + // Finally update the result. + UpdateValueMap(I, ResultReg); + } + + // Set all unused physreg defs as dead. + static_cast(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); + + return true; +} + +bool ARMFastISel::ARMSelectSDiv(const Instruction *I) { + EVT VT; + const Type *Ty = I->getType(); + if (!isTypeLegal(Ty, VT)) + return false; + + // If we have integer div support we should have gotten already, emit a + // libcall. + RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; + if (VT == MVT::i16) + LC = RTLIB::SDIV_I16; + else if (VT == MVT::i32) + LC = RTLIB::SDIV_I32; + else if (VT == MVT::i64) + LC = RTLIB::SDIV_I64; + else if (VT == MVT::i128) + LC = RTLIB::SDIV_I128; + assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); + + // Binary operand with all the same type. + std::vector ArgTys; + ArgTys.push_back(Ty); + ArgTys.push_back(Ty); + const FunctionType *FTy = FunctionType::get(Ty, ArgTys, false); + Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage, + TLI.getLibcallName(LC)); + if (Subtarget->isAAPCS_ABI()) + F->setCallingConv(CallingConv::ARM_AAPCS); + else + F->setCallingConv(I->getParent()->getParent()->getCallingConv()); + + return ARMEmitLibcall(I, F); +} + // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. @@ -960,6 +1112,8 @@ return ARMSelectBinaryOp(I, ISD::FSUB); case Instruction::FMul: return ARMSelectBinaryOp(I, ISD::FMUL); + case Instruction::SDiv: + return ARMSelectSDiv(I); default: break; } return false; From dirty at apple.com Tue Sep 14 18:13:31 2010 From: dirty at apple.com (Cameron Esfahani) Date: Tue, 14 Sep 2010 16:13:31 -0700 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple Message-ID: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> Attached is a small patch which adds better support for the environment portion of the triple. No environments are defined with this patch, but the plumbing is in place. -------------- next part -------------- A non-text attachment was scrubbed... Name: environment.patch Type: application/octet-stream Size: 3732 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/3b0140b1/attachment.obj -------------- next part -------------- Cameron Esfahani dirty at apple.com "There are times in the life of a nation when the only place a decent man can find himself is in prison." From stoklund at 2pi.dk Tue Sep 14 18:22:35 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 14 Sep 2010 16:22:35 -0700 Subject: [llvm-commits] [llvm] r113875 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <20100914222033.36E342A6C12C@llvm.org> References: <20100914222033.36E342A6C12C@llvm.org> Message-ID: <0EF6B4B3-56CA-41FD-96CA-BB6F7C4B7E45@2pi.dk> On Sep 14, 2010, at 3:20 PM, Jim Grosbach wrote: > Author: grosbach > Date: Tue Sep 14 17:20:33 2010 > New Revision: 113875 > > URL: http://llvm.org/viewvc/llvm-project?rev=113875&view=rev > Log: > The register specified for a dregpair is the corresponding Q register, so to > get the pair, we need to look up the sub-regs based on the qreg. Create a > lookup function since we don't have access to TargetRegisterInfo here to > be able to use getSubReg(ARM::dsub_[01]). > +// Get the constituent sub-regs for a dregpair from a Q register. > +static std::pair GetDRegPair(unsigned QReg) { > + switch (QReg) { > + case ARM::Q0: return std::pair(ARM::D0, ARM::D1); > + case ARM::Q1: return std::pair(ARM::D2, ARM::D3); > + case ARM::Q2: return std::pair(ARM::D4, ARM::D5); > + case ARM::Q3: return std::pair(ARM::D6, ARM::D7); > + case ARM::Q4: return std::pair(ARM::D8, ARM::D9); > + case ARM::Q5: return std::pair(ARM::D10, ARM::D11); > + case ARM::Q6: return std::pair(ARM::D12, ARM::D13); > + case ARM::Q7: return std::pair(ARM::D14, ARM::D15); > + case ARM::Q8: return std::pair(ARM::D16, ARM::D17); > + case ARM::Q9: return std::pair(ARM::D18, ARM::D19); > + case ARM::Q10: return std::pair(ARM::D20, ARM::D21); > + case ARM::Q11: return std::pair(ARM::D22, ARM::D23); > + case ARM::Q12: return std::pair(ARM::D24, ARM::D25); > + case ARM::Q13: return std::pair(ARM::D26, ARM::D27); > + case ARM::Q14: return std::pair(ARM::D28, ARM::D29); > + case ARM::Q15: return std::pair(ARM::D30, ARM::D31); I am not really sure if I want to encourage this or not, but the registers are in fact sorted numerically, so you can go: unsigned DReg = ARM::D0 + 2*(QReg - ARM::Q0) This requires at least 'assert(Q0+15 == Q15)' Either way is gross. From gohman at apple.com Tue Sep 14 18:28:12 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 14 Sep 2010 23:28:12 -0000 Subject: [llvm-commits] [llvm] r113892 - /llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Message-ID: <20100914232812.D88F72A6C12C@llvm.org> Author: djg Date: Tue Sep 14 18:28:12 2010 New Revision: 113892 URL: http://llvm.org/viewvc/llvm-project?rev=113892&view=rev Log: Convert TBAA to use the new TBAATag field of AliasAnalysis::Location. Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=113892&r1=113891&r2=113892&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Tue Sep 14 18:28:12 2010 @@ -44,7 +44,7 @@ public: TBAANode() : Node(0) {} - explicit TBAANode(MDNode *N) : Node(N) {} + explicit TBAANode(const MDNode *N) : Node(N) {} /// getNode - Get the MDNode for this TBAANode. const MDNode *getNode() const { return Node; } @@ -119,21 +119,11 @@ AliasAnalysis::AliasResult TypeBasedAliasAnalysis::alias(const Location &LocA, const Location &LocB) { - // Currently, metadata can only be attached to Instructions. - const Instruction *AI = dyn_cast(LocA.Ptr); - if (!AI) return MayAlias; - const Instruction *BI = dyn_cast(LocB.Ptr); - if (!BI) return MayAlias; - // Get the attached MDNodes. If either value lacks a tbaa MDNode, we must // be conservative. - MDNode *AM = - AI->getMetadata(AI->getParent()->getParent()->getParent() - ->getMDKindID("tbaa")); + const MDNode *AM = LocA.TBAATag; if (!AM) return MayAlias; - MDNode *BM = - BI->getMetadata(BI->getParent()->getParent()->getParent() - ->getMDKindID("tbaa")); + const MDNode *BM = LocB.TBAATag; if (!BM) return MayAlias; // Keep track of the root node for A and B. @@ -175,13 +165,7 @@ } bool TypeBasedAliasAnalysis::pointsToConstantMemory(const Location &Loc) { - // Currently, metadata can only be attached to Instructions. - const Instruction *I = dyn_cast(Loc.Ptr); - if (!I) return false; - - MDNode *M = - I->getMetadata(I->getParent()->getParent()->getParent() - ->getMDKindID("tbaa")); + const MDNode *M = Loc.TBAATag; if (!M) return false; // If this is an "immutable" type, we can assume the pointer is pointing From grosbach at apple.com Tue Sep 14 18:32:20 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 16:32:20 -0700 Subject: [llvm-commits] [llvm] r113875 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <0EF6B4B3-56CA-41FD-96CA-BB6F7C4B7E45@2pi.dk> References: <20100914222033.36E342A6C12C@llvm.org> <0EF6B4B3-56CA-41FD-96CA-BB6F7C4B7E45@2pi.dk> Message-ID: <6FB78DFE-9FF8-4A9D-880C-E91D7EEFE71B@apple.com> On Sep 14, 2010, at 4:22 PM, Jakob Stoklund Olesen wrote: > > On Sep 14, 2010, at 3:20 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Tue Sep 14 17:20:33 2010 >> New Revision: 113875 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113875&view=rev >> Log: >> The register specified for a dregpair is the corresponding Q register, so to >> get the pair, we need to look up the sub-regs based on the qreg. Create a >> lookup function since we don't have access to TargetRegisterInfo here to >> be able to use getSubReg(ARM::dsub_[01]). > >> +// Get the constituent sub-regs for a dregpair from a Q register. >> +static std::pair GetDRegPair(unsigned QReg) { >> + switch (QReg) { >> + case ARM::Q0: return std::pair(ARM::D0, ARM::D1); >> + case ARM::Q1: return std::pair(ARM::D2, ARM::D3); >> + case ARM::Q2: return std::pair(ARM::D4, ARM::D5); >> + case ARM::Q3: return std::pair(ARM::D6, ARM::D7); >> + case ARM::Q4: return std::pair(ARM::D8, ARM::D9); >> + case ARM::Q5: return std::pair(ARM::D10, ARM::D11); >> + case ARM::Q6: return std::pair(ARM::D12, ARM::D13); >> + case ARM::Q7: return std::pair(ARM::D14, ARM::D15); >> + case ARM::Q8: return std::pair(ARM::D16, ARM::D17); >> + case ARM::Q9: return std::pair(ARM::D18, ARM::D19); >> + case ARM::Q10: return std::pair(ARM::D20, ARM::D21); >> + case ARM::Q11: return std::pair(ARM::D22, ARM::D23); >> + case ARM::Q12: return std::pair(ARM::D24, ARM::D25); >> + case ARM::Q13: return std::pair(ARM::D26, ARM::D27); >> + case ARM::Q14: return std::pair(ARM::D28, ARM::D29); >> + case ARM::Q15: return std::pair(ARM::D30, ARM::D31); > > I am not really sure if I want to encourage this or not, but the registers are in fact sorted numerically, so you can go: > > unsigned DReg = ARM::D0 + 2*(QReg - ARM::Q0) > > This requires at least 'assert(Q0+15 == Q15)' > > Either way is gross. > Yeah. It's definitely ugly all the way around. I'm planning to refactor the way we handle these dregpair operands as part of this whole process with MC inst printing, and hopefully I'll be able to get rid of this ugliness altogether. We shall see. In the meantime, I think I prefer the longer, but more explicit, ugly rather than the short and tricky ugly. Specifically, I'd like to avoid tying your hands with regards to register ordering. As I recall, you've been tossing around ideas that might change that sort of thing(?) That said, I don't feel strongly about it, so if you think the short and tricky version is better, I'll be easy to convince. :) -Jim From sabre at nondot.org Tue Sep 14 18:34:29 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 14 Sep 2010 23:34:29 -0000 Subject: [llvm-commits] [llvm] r113894 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100914233429.4D3032A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 18:34:29 2010 New Revision: 113894 URL: http://llvm.org/viewvc/llvm-project?rev=113894&view=rev Log: add a terrible hack to allow out with dx is parens, a gas bug. This fixes PR8114 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113894&r1=113893&r2=113894&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 18:34:29 2010 @@ -857,6 +857,20 @@ std::swap(Operands[1], Operands[2]); } + // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx". + if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") && + Operands.size() == 3) { + X86Operand &Op = *(X86Operand*)Operands.back(); + if (Op.isMem() && Op.Mem.SegReg == 0 && + isa(Op.Mem.Disp) && + cast(Op.Mem.Disp)->getValue() == 0 && + Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) { + SMLoc Loc = Op.getEndLoc(); + Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); + delete &Op; + } + } + // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as // "f{mul*,add*,sub*,div*} $op" if ((Name.startswith("fmul") || Name.startswith("fadd") || Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113894&r1=113893&r2=113894&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 18:34:29 2010 @@ -200,3 +200,13 @@ outb $0x7f outw %dx inl %dx + + +// PR8114 +// CHECK: outb %al, %dx +// CHECK: outw %ax, %dx +// CHECK: outl %eax, %dx + +out %al, (%dx) +out %ax, (%dx) +outl %eax, (%dx) From clattner at apple.com Tue Sep 14 18:37:09 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 14 Sep 2010 16:37:09 -0700 Subject: [llvm-commits] [llvm] r113875 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <6FB78DFE-9FF8-4A9D-880C-E91D7EEFE71B@apple.com> References: <20100914222033.36E342A6C12C@llvm.org> <0EF6B4B3-56CA-41FD-96CA-BB6F7C4B7E45@2pi.dk> <6FB78DFE-9FF8-4A9D-880C-E91D7EEFE71B@apple.com> Message-ID: On Sep 14, 2010, at 4:32 PM, Jim Grosbach wrote: >> I am not really sure if I want to encourage this or not, but the registers are in fact sorted numerically, so you can go: >> >> unsigned DReg = ARM::D0 + 2*(QReg - ARM::Q0) >> >> This requires at least 'assert(Q0+15 == Q15)' >> >> Either way is gross. >> > > Yeah. It's definitely ugly all the way around. I'm planning to refactor the way we handle these dregpair operands as part of this whole process with MC inst printing, and hopefully I'll be able to get rid of this ugliness altogether. We shall see. In the meantime, I think I prefer the longer, but more explicit, ugly rather than the short and tricky ugly. I agree :) -Chris From dirty at apple.com Tue Sep 14 18:49:27 2010 From: dirty at apple.com (Cameron Esfahani) Date: Tue, 14 Sep 2010 16:49:27 -0700 Subject: [llvm-commits] [PATCH] Win64 var arg support In-Reply-To: References: Message-ID: <1A2D1BAA-35B7-4C5D-8D94-2ADD687361CB@apple.com> Okay, here's a version which reverts the listed change below. I'm using the TargetFrameInfo to determine how far we are from the caller allocated portion of the stack. I've also written a test case to verify that the non-var arg, more than 4 parameter, function calls still work. Hopefully this should address all the remaining issues for the Windows 64 var args patch. On Sep 2, 2010, at 8:42 PM, Cameron Esfahani wrote: > This is required for the var arg support. Without this change, there's no way to know how far the home register space allocated by the caller is from the top of the stack. Any fixed object created via MFI is put at it's offset after the frame info stuff is calculated. So, if you wanted to put something into the caller's frame, it's pretty difficult. > > On Sep 2, 2010, at 4:13 PM, Anton Korobeynikov wrote: > >> Hello, Cameron >> >>> Here's the corresponding llvm changes to support the Win64 ABI version of var args. With a test case! >> This hunk seems to be unrelated to the patch and in wrong in general: >> - (Subtarget.isTargetWin64() ? -40 : >> - (Subtarget.is64Bit() ? -8 : -4))), >> + (Subtarget.is64Bit() ? -8 : -4)), >> Why do you need it? >> >> -- >> With best regards, Anton Korobeynikov >> Faculty of Mathematics and Mechanics, Saint Petersburg State University > > Cameron Esfahani > dirty at apple.com > > "You only live once, and the way I live, once is enough" > > Frank Sinatra Cameron Esfahani dirty at apple.com "Americans are very skilled at creating a custom meaning from something that's mass-produced." Ann Powers -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/5e94c08b/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_va.patch Type: application/octet-stream Size: 5873 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/5e94c08b/attachment.obj -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/5e94c08b/attachment-0001.html From dirty at apple.com Tue Sep 14 18:52:41 2010 From: dirty at apple.com (Cameron Esfahani) Date: Tue, 14 Sep 2010 16:52:41 -0700 Subject: [llvm-commits] [PATCH] Win64 var arg support In-Reply-To: <1A2D1BAA-35B7-4C5D-8D94-2ADD687361CB@apple.com> References: <1A2D1BAA-35B7-4C5D-8D94-2ADD687361CB@apple.com> Message-ID: <96C22D1D-AE17-4353-835B-B062A34C57AA@apple.com> -Sigh- It would help if I added that new test case to my patch... Here's the patch with the new non-var arg, more than 4 parameter, function call test. On Sep 14, 2010, at 4:49 PM, Cameron Esfahani wrote: > Okay, here's a version which reverts the listed change below. I'm using the TargetFrameInfo to determine how far we are from the caller allocated portion of the stack. > > I've also written a test case to verify that the non-var arg, more than 4 parameter, function calls still work. > > Hopefully this should address all the remaining issues for the Windows 64 var args patch. > > > > On Sep 2, 2010, at 8:42 PM, Cameron Esfahani wrote: > >> This is required for the var arg support. Without this change, there's no way to know how far the home register space allocated by the caller is from the top of the stack. Any fixed object created via MFI is put at it's offset after the frame info stuff is calculated. So, if you wanted to put something into the caller's frame, it's pretty difficult. >> >> On Sep 2, 2010, at 4:13 PM, Anton Korobeynikov wrote: >> >>> Hello, Cameron >>> >>>> Here's the corresponding llvm changes to support the Win64 ABI version of var args. With a test case! >>> This hunk seems to be unrelated to the patch and in wrong in general: >>> - (Subtarget.isTargetWin64() ? -40 : >>> - (Subtarget.is64Bit() ? -8 : -4))), >>> + (Subtarget.is64Bit() ? -8 : -4)), >>> Why do you need it? >>> >>> -- >>> With best regards, Anton Korobeynikov >>> Faculty of Mathematics and Mechanics, Saint Petersburg State University >> >> Cameron Esfahani >> dirty at apple.com >> >> "You only live once, and the way I live, once is enough" >> >> Frank Sinatra > > Cameron Esfahani > dirty at apple.com > > "Americans are very skilled at creating a custom meaning from something that's mass-produced." > > Ann Powers > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits Cameron Esfahani dirty at apple.com "You only live once, and the way I live, once is enough" Frank Sinatra -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/b9bb6aaf/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_va.patch Type: application/octet-stream Size: 6475 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/b9bb6aaf/attachment.obj -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/b9bb6aaf/attachment-0001.html From grosbach at apple.com Tue Sep 14 18:54:06 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 23:54:06 -0000 Subject: [llvm-commits] [llvm] r113903 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/neon-tests.txt Message-ID: <20100914235406.954B32A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 18:54:06 2010 New Revision: 113903 URL: http://llvm.org/viewvc/llvm-project?rev=113903&view=rev Log: Reapply r113875 with additional cleanups. "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113903&r1=113902&r2=113903&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 14 18:54:06 2010 @@ -218,9 +218,9 @@ "vld1", Dt, "\\{$dst\\}, $addr$offset", "$addr.addr = $wb", []>; class VLD1QWB op7_4, string Dt> - : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb), + : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, - "vld1", Dt, "${dst:dregpair}, $addr$offset", + "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset", "$addr.addr = $wb", []>; def VLD1d8_UPD : VLD1DWB<0b0000, "8">; @@ -675,8 +675,9 @@ "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>; class VST1QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST, - "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>; + (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2), + IIC_VST, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset", + "$addr.addr = $wb", []>; def VST1d8_UPD : VST1DWB<0b0000, "8">; def VST1d16_UPD : VST1DWB<0b0100, "16">; Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113903&r1=113902&r2=113903&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Tue Sep 14 18:54:06 2010 @@ -29,73 +29,27 @@ #undef MachineInstr #undef ARMAsmPrinter -static unsigned NextReg(unsigned Reg) { - switch (Reg) { +// Get the constituent sub-regs for a dregpair from a Q register. +static std::pair GetDRegPair(unsigned QReg) { + switch (QReg) { default: assert(0 && "Unexpected register enum"); - - case ARM::D0: - return ARM::D1; - case ARM::D1: - return ARM::D2; - case ARM::D2: - return ARM::D3; - case ARM::D3: - return ARM::D4; - case ARM::D4: - return ARM::D5; - case ARM::D5: - return ARM::D6; - case ARM::D6: - return ARM::D7; - case ARM::D7: - return ARM::D8; - case ARM::D8: - return ARM::D9; - case ARM::D9: - return ARM::D10; - case ARM::D10: - return ARM::D11; - case ARM::D11: - return ARM::D12; - case ARM::D12: - return ARM::D13; - case ARM::D13: - return ARM::D14; - case ARM::D14: - return ARM::D15; - case ARM::D15: - return ARM::D16; - case ARM::D16: - return ARM::D17; - case ARM::D17: - return ARM::D18; - case ARM::D18: - return ARM::D19; - case ARM::D19: - return ARM::D20; - case ARM::D20: - return ARM::D21; - case ARM::D21: - return ARM::D22; - case ARM::D22: - return ARM::D23; - case ARM::D23: - return ARM::D24; - case ARM::D24: - return ARM::D25; - case ARM::D25: - return ARM::D26; - case ARM::D26: - return ARM::D27; - case ARM::D27: - return ARM::D28; - case ARM::D28: - return ARM::D29; - case ARM::D29: - return ARM::D30; - case ARM::D30: - return ARM::D31; + case ARM::Q0: return std::pair(ARM::D0, ARM::D1); + case ARM::Q1: return std::pair(ARM::D2, ARM::D3); + case ARM::Q2: return std::pair(ARM::D4, ARM::D5); + case ARM::Q3: return std::pair(ARM::D6, ARM::D7); + case ARM::Q4: return std::pair(ARM::D8, ARM::D9); + case ARM::Q5: return std::pair(ARM::D10, ARM::D11); + case ARM::Q6: return std::pair(ARM::D12, ARM::D13); + case ARM::Q7: return std::pair(ARM::D14, ARM::D15); + case ARM::Q8: return std::pair(ARM::D16, ARM::D17); + case ARM::Q9: return std::pair(ARM::D18, ARM::D19); + case ARM::Q10: return std::pair(ARM::D20, ARM::D21); + case ARM::Q11: return std::pair(ARM::D22, ARM::D23); + case ARM::Q12: return std::pair(ARM::D24, ARM::D25); + case ARM::Q13: return std::pair(ARM::D26, ARM::D27); + case ARM::Q14: return std::pair(ARM::D28, ARM::D29); + case ARM::Q15: return std::pair(ARM::D30, ARM::D31); } } @@ -189,19 +143,11 @@ if (Op.isReg()) { unsigned Reg = Op.getReg(); if (Modifier && strcmp(Modifier, "dregpair") == 0) { - O << '{' << getRegisterName(Reg) << ", " - << getRegisterName(NextReg(Reg)) << '}'; -#if 0 - // FIXME: Breaks e.g. ARM/vmul.ll. - assert(0); - /* - unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0); - unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1); - O << '{' - << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) - << '}';*/ -#endif + std::pair dregpair = GetDRegPair(Reg); + O << '{' << getRegisterName(dregpair.first) << ", " + << getRegisterName(dregpair.second) << '}'; } else if (Modifier && strcmp(Modifier, "lane") == 0) { + // FIXME assert(0); /* unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=113903&r1=113902&r2=113903&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Sep 14 18:54:06 2010 @@ -79,22 +79,9 @@ } // Return the register enum Based on RegClass and the raw register number. -// For DRegPair, see comments below. // FIXME: Auto-gened? -static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister, - bool DRegPair = false) { - - if (DRegPair && RegClassID == ARM::QPRRegClassID) { - // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified - // in the ARM Architecture Manual as far as I understand it (A8.6.307). - // Therefore, we morph the RegClassID to be the sub register class and don't - // subsequently transform the RawRegister encoding when calculating RegNum. - // - // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part - // where this workaround is meant for. - RegClassID = ARM::DPRRegClassID; - } - +static unsigned +getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) { // For this purpose, we can treat rGPR as if it were GPR. if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID; @@ -2201,22 +2188,6 @@ return (insn >> 8) & 0xF; } -static bool UseDRegPair(unsigned Opcode) { - switch (Opcode) { - default: - return false; - case ARM::VLD1q8_UPD: - case ARM::VLD1q16_UPD: - case ARM::VLD1q32_UPD: - case ARM::VLD1q64_UPD: - case ARM::VST1q8_UPD: - case ARM::VST1q16_UPD: - case ARM::VST1q32_UPD: - case ARM::VST1q64_UPD: - return true; - } -} - // VLD* // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] // VLD*LN* @@ -2243,10 +2214,9 @@ // We have homogeneous NEON registers for Load/Store. unsigned RegClass = 0; - bool DRegPair = UseDRegPair(Opcode); // Double-spaced registers have increments of 2. - unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1; + unsigned Inc = DblSpaced ? 2 : 1; unsigned Rn = decodeRn(insn); unsigned Rm = decodeRm(insn); @@ -2292,7 +2262,7 @@ RegClass = OpInfo[OpIdx].RegClass; while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { MI.addOperand(MCOperand::CreateReg( - getRegisterEnum(B, RegClass, Rd, DRegPair))); + getRegisterEnum(B, RegClass, Rd))); Rd += Inc; ++OpIdx; } @@ -2311,7 +2281,7 @@ while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { MI.addOperand(MCOperand::CreateReg( - getRegisterEnum(B, RegClass, Rd, DRegPair))); + getRegisterEnum(B, RegClass, Rd))); Rd += Inc; ++OpIdx; } Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=113903&r1=113902&r2=113903&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Tue Sep 14 18:54:06 2010 @@ -9,10 +9,12 @@ # CHECK: vdup.32 q3, d1[0] 0x41 0x6c 0xb4 0xf3 -# VLD1q8_UPD (with ${dst:dregpair} operand) # CHECK: vld1.8 {d17, d18}, [r6], r5 0x05 0x1a 0x66 0xf4 +# CHECK: vld1.8 {d17, d18, d19}, [r6], r5 +0x05 0x16 0x66 0xf4 + # CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 0x07 0x00 0x22 0xf4 From stoklund at 2pi.dk Tue Sep 14 18:58:36 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 14 Sep 2010 16:58:36 -0700 Subject: [llvm-commits] [llvm] r113875 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <6FB78DFE-9FF8-4A9D-880C-E91D7EEFE71B@apple.com> References: <20100914222033.36E342A6C12C@llvm.org> <0EF6B4B3-56CA-41FD-96CA-BB6F7C4B7E45@2pi.dk> <6FB78DFE-9FF8-4A9D-880C-E91D7EEFE71B@apple.com> Message-ID: On Sep 14, 2010, at 4:32 PM, Jim Grosbach wrote: > > Yeah. It's definitely ugly all the way around. I'm planning to refactor the way we handle these dregpair operands as part of this whole process with MC inst printing, and hopefully I'll be able to get rid of this ugliness altogether. We shall see. In the meantime, I think I prefer the longer, but more explicit, ugly rather than the short and tricky ugly. Specifically, I'd like to avoid tying your hands with regards to register ordering. As I recall, you've been tossing around ideas that might change that sort of thing(?) That said, I don't feel strongly about it, so if you think the short and tricky version is better, I'll be easy to convince. :) I was playing with ordering registers topologically to permit a better implementation of TRI.regsOverlap. It didn't really work out to be an improvement, but its probably good to leave the door open for such tinkering. Let's all not look at SSEDomainFixPass::RegIndex and X86FloatingPoint::getFPReg now ;-) /jakob From pichet2000 at gmail.com Tue Sep 14 18:59:30 2010 From: pichet2000 at gmail.com (Francois Pichet) Date: Tue, 14 Sep 2010 19:59:30 -0400 Subject: [llvm-commits] [llvm] r113834 - in /llvm/trunk: lib/Target/CBackend/CBackend.cpp utils/TableGen/IntrinsicEmitter.cpp In-Reply-To: <20100914042739.2B7CF2A6C12C@llvm.org> References: <20100914042739.2B7CF2A6C12C@llvm.org> Message-ID: hi, Can't you not rewrite EmitSuffix like this to get rid of the warning? void IntrinsicEmitter::EmitSuffix(raw_ostream &OS) { OS << "#if defined(_MSC_VER) && defined(setjmp)\n" "// let's return it to _setjmp state\n" "# pragma pop_macro(\"setjmp\")\n" "#endif\n\n"; } On Tue, Sep 14, 2010 at 12:27 AM, Michael J. Spencer wrote: > Author: mspencer > Date: Mon Sep 13 23:27:38 2010 > New Revision: 113834 > > URL: http://llvm.org/viewvc/llvm-project?rev=113834&view=rev > Log: > CBackend: Fix MSVC build. > > This may produce warnings on MSVS, but it's better than failures. > > Modified: > ? ?llvm/trunk/lib/Target/CBackend/CBackend.cpp > ? ?llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp > > Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=113834&r1=113833&r2=113834&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) > +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Sep 13 23:27:38 2010 > @@ -50,6 +50,10 @@ > ?#include "llvm/System/Host.h" > ?#include "llvm/Config/config.h" > ?#include > +// Some ms header decided to define setjmp as _setjmp, undo this for this file. > +#ifdef _MSC_VER > +#undef setjmp > +#endif > ?using namespace llvm; > > ?extern "C" void LLVMInitializeCBackendTarget() { > > Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=113834&r1=113833&r2=113834&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Mon Sep 13 23:27:38 2010 > @@ -69,15 +69,15 @@ > ?void IntrinsicEmitter::EmitPrefix(raw_ostream &OS) { > ? OS << "// VisualStudio defines setjmp as _setjmp\n" > ? ? ? ? "#if defined(_MSC_VER) && defined(setjmp)\n" > - ? ? ? ?"#define setjmp_undefined_for_visual_studio\n" > - ? ? ? ?"#undef setjmp\n" > + ? ? ? ?"# ?pragma push_macro(\"setjmp\")\n" > + ? ? ? ?"# ?undef setjmp\n" > ? ? ? ? "#endif\n\n"; > ?} > > ?void IntrinsicEmitter::EmitSuffix(raw_ostream &OS) { > - ?OS << "#if defined(_MSC_VER) && defined(setjmp_undefined_for_visual_studio)\n" > + ?OS << "#if defined(_MSC_VER)\n" > ? ? ? ? "// let's return it to _setjmp state\n" > - ? ? ? ?"#define setjmp _setjmp\n" > + ? ? ? ?"# ?pragma pop_macro(\"setjmp\")\n" > ? ? ? ? "#endif\n\n"; > ?} > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bigcheesegs at gmail.com Tue Sep 14 19:17:54 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 14 Sep 2010 20:17:54 -0400 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple In-Reply-To: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> References: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> Message-ID: On Tue, Sep 14, 2010 at 7:13 PM, Cameron Esfahani wrote: > Attached is a small patch which adds better support for the environment portion of the triple. ?No environments are defined with this patch, but the plumbing is in place. > > > > Cameron Esfahani > dirty at apple.com > > "There are times in the life of a nation when the only place a decent man can find himself is in prison." Looks good. Someone should, in another patch, switch iphoneos over to this. - Michael Spencer From bob.wilson at apple.com Tue Sep 14 19:19:29 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 14 Sep 2010 17:19:29 -0700 Subject: [llvm-commits] [llvm] r113903 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/neon-tests.txt In-Reply-To: <20100914235406.954B32A6C12C@llvm.org> References: <20100914235406.954B32A6C12C@llvm.org> Message-ID: I tried earlier to get rid of the dregpair modifier altogether. I did not succeed, but I have learned a few things since my last attempt. I will try again.... It would sure be nice to avoid all this trouble. On Sep 14, 2010, at 4:54 PM, Jim Grosbach wrote: > Author: grosbach > Date: Tue Sep 14 18:54:06 2010 > New Revision: 113903 > > URL: http://llvm.org/viewvc/llvm-project?rev=113903&view=rev > Log: > Reapply r113875 with additional cleanups. > > "The register specified for a dregpair is the corresponding Q register, so to > get the pair, we need to look up the sub-regs based on the qreg. Create a > lookup function since we don't have access to TargetRegisterInfo here to > be able to use getSubReg(ARM::dsub_[01])." > > Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use > the dregpair modifier for the 2xdreg versions. Explicitly specifying the two > registers as operands is more correct and more consistent with the other > instruction patterns. This enables further cleanup of special case code in the > disassembler as a nice side-effect. > > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp > llvm/trunk/test/MC/Disassembler/neon-tests.txt > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113903&r1=113902&r2=113903&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 14 18:54:06 2010 > @@ -218,9 +218,9 @@ > "vld1", Dt, "\\{$dst\\}, $addr$offset", > "$addr.addr = $wb", []>; > class VLD1QWB op7_4, string Dt> > - : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb), > + : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), > (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, > - "vld1", Dt, "${dst:dregpair}, $addr$offset", > + "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset", > "$addr.addr = $wb", []>; > > def VLD1d8_UPD : VLD1DWB<0b0000, "8">; > @@ -675,8 +675,9 @@ > "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>; > class VST1QWB op7_4, string Dt> > : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), > - (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST, > - "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>; > + (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2), > + IIC_VST, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset", > + "$addr.addr = $wb", []>; > > def VST1d8_UPD : VST1DWB<0b0000, "8">; > def VST1d16_UPD : VST1DWB<0b0100, "16">; > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113903&r1=113902&r2=113903&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Tue Sep 14 18:54:06 2010 > @@ -29,73 +29,27 @@ > #undef MachineInstr > #undef ARMAsmPrinter > > -static unsigned NextReg(unsigned Reg) { > - switch (Reg) { > +// Get the constituent sub-regs for a dregpair from a Q register. > +static std::pair GetDRegPair(unsigned QReg) { > + switch (QReg) { > default: > assert(0 && "Unexpected register enum"); > - > - case ARM::D0: > - return ARM::D1; > - case ARM::D1: > - return ARM::D2; > - case ARM::D2: > - return ARM::D3; > - case ARM::D3: > - return ARM::D4; > - case ARM::D4: > - return ARM::D5; > - case ARM::D5: > - return ARM::D6; > - case ARM::D6: > - return ARM::D7; > - case ARM::D7: > - return ARM::D8; > - case ARM::D8: > - return ARM::D9; > - case ARM::D9: > - return ARM::D10; > - case ARM::D10: > - return ARM::D11; > - case ARM::D11: > - return ARM::D12; > - case ARM::D12: > - return ARM::D13; > - case ARM::D13: > - return ARM::D14; > - case ARM::D14: > - return ARM::D15; > - case ARM::D15: > - return ARM::D16; > - case ARM::D16: > - return ARM::D17; > - case ARM::D17: > - return ARM::D18; > - case ARM::D18: > - return ARM::D19; > - case ARM::D19: > - return ARM::D20; > - case ARM::D20: > - return ARM::D21; > - case ARM::D21: > - return ARM::D22; > - case ARM::D22: > - return ARM::D23; > - case ARM::D23: > - return ARM::D24; > - case ARM::D24: > - return ARM::D25; > - case ARM::D25: > - return ARM::D26; > - case ARM::D26: > - return ARM::D27; > - case ARM::D27: > - return ARM::D28; > - case ARM::D28: > - return ARM::D29; > - case ARM::D29: > - return ARM::D30; > - case ARM::D30: > - return ARM::D31; > + case ARM::Q0: return std::pair(ARM::D0, ARM::D1); > + case ARM::Q1: return std::pair(ARM::D2, ARM::D3); > + case ARM::Q2: return std::pair(ARM::D4, ARM::D5); > + case ARM::Q3: return std::pair(ARM::D6, ARM::D7); > + case ARM::Q4: return std::pair(ARM::D8, ARM::D9); > + case ARM::Q5: return std::pair(ARM::D10, ARM::D11); > + case ARM::Q6: return std::pair(ARM::D12, ARM::D13); > + case ARM::Q7: return std::pair(ARM::D14, ARM::D15); > + case ARM::Q8: return std::pair(ARM::D16, ARM::D17); > + case ARM::Q9: return std::pair(ARM::D18, ARM::D19); > + case ARM::Q10: return std::pair(ARM::D20, ARM::D21); > + case ARM::Q11: return std::pair(ARM::D22, ARM::D23); > + case ARM::Q12: return std::pair(ARM::D24, ARM::D25); > + case ARM::Q13: return std::pair(ARM::D26, ARM::D27); > + case ARM::Q14: return std::pair(ARM::D28, ARM::D29); > + case ARM::Q15: return std::pair(ARM::D30, ARM::D31); > } > } > > @@ -189,19 +143,11 @@ > if (Op.isReg()) { > unsigned Reg = Op.getReg(); > if (Modifier && strcmp(Modifier, "dregpair") == 0) { > - O << '{' << getRegisterName(Reg) << ", " > - << getRegisterName(NextReg(Reg)) << '}'; > -#if 0 > - // FIXME: Breaks e.g. ARM/vmul.ll. > - assert(0); > - /* > - unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0); > - unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1); > - O << '{' > - << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) > - << '}';*/ > -#endif > + std::pair dregpair = GetDRegPair(Reg); > + O << '{' << getRegisterName(dregpair.first) << ", " > + << getRegisterName(dregpair.second) << '}'; > } else if (Modifier && strcmp(Modifier, "lane") == 0) { > + // FIXME > assert(0); > /* > unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=113903&r1=113902&r2=113903&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Sep 14 18:54:06 2010 > @@ -79,22 +79,9 @@ > } > > // Return the register enum Based on RegClass and the raw register number. > -// For DRegPair, see comments below. > // FIXME: Auto-gened? > -static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister, > - bool DRegPair = false) { > - > - if (DRegPair && RegClassID == ARM::QPRRegClassID) { > - // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified > - // in the ARM Architecture Manual as far as I understand it (A8.6.307). > - // Therefore, we morph the RegClassID to be the sub register class and don't > - // subsequently transform the RawRegister encoding when calculating RegNum. > - // > - // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part > - // where this workaround is meant for. > - RegClassID = ARM::DPRRegClassID; > - } > - > +static unsigned > +getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) { > // For this purpose, we can treat rGPR as if it were GPR. > if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID; > > @@ -2201,22 +2188,6 @@ > return (insn >> 8) & 0xF; > } > > -static bool UseDRegPair(unsigned Opcode) { > - switch (Opcode) { > - default: > - return false; > - case ARM::VLD1q8_UPD: > - case ARM::VLD1q16_UPD: > - case ARM::VLD1q32_UPD: > - case ARM::VLD1q64_UPD: > - case ARM::VST1q8_UPD: > - case ARM::VST1q16_UPD: > - case ARM::VST1q32_UPD: > - case ARM::VST1q64_UPD: > - return true; > - } > -} > - > // VLD* > // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] > // VLD*LN* > @@ -2243,10 +2214,9 @@ > > // We have homogeneous NEON registers for Load/Store. > unsigned RegClass = 0; > - bool DRegPair = UseDRegPair(Opcode); > > // Double-spaced registers have increments of 2. > - unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1; > + unsigned Inc = DblSpaced ? 2 : 1; > > unsigned Rn = decodeRn(insn); > unsigned Rm = decodeRm(insn); > @@ -2292,7 +2262,7 @@ > RegClass = OpInfo[OpIdx].RegClass; > while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { > MI.addOperand(MCOperand::CreateReg( > - getRegisterEnum(B, RegClass, Rd, DRegPair))); > + getRegisterEnum(B, RegClass, Rd))); > Rd += Inc; > ++OpIdx; > } > @@ -2311,7 +2281,7 @@ > > while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { > MI.addOperand(MCOperand::CreateReg( > - getRegisterEnum(B, RegClass, Rd, DRegPair))); > + getRegisterEnum(B, RegClass, Rd))); > Rd += Inc; > ++OpIdx; > } > > Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=113903&r1=113902&r2=113903&view=diff > ============================================================================== > --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) > +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Tue Sep 14 18:54:06 2010 > @@ -9,10 +9,12 @@ > # CHECK: vdup.32 q3, d1[0] > 0x41 0x6c 0xb4 0xf3 > > -# VLD1q8_UPD (with ${dst:dregpair} operand) > # CHECK: vld1.8 {d17, d18}, [r6], r5 > 0x05 0x1a 0x66 0xf4 > > +# CHECK: vld1.8 {d17, d18, d19}, [r6], r5 > +0x05 0x16 0x66 0xf4 > + > # CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 > 0x07 0x00 0x22 0xf4 > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Sep 14 19:30:18 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 17:30:18 -0700 Subject: [llvm-commits] [llvm] r113903 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/neon-tests.txt In-Reply-To: References: <20100914235406.954B32A6C12C@llvm.org> Message-ID: Agreed. I'm looking forward to getting rid of these sorts of things. Chris suggested doing something like X86 does with machineoperand target flags to denote things we currently use modifier strings for, which made sense to me. I haven't looked at in more detail than that chat and what you see in this patch yet, though. -Jim On Sep 14, 2010, at 5:19 PM, Bob Wilson wrote: > I tried earlier to get rid of the dregpair modifier altogether. I did not succeed, but I have learned a few things since my last attempt. I will try again.... It would sure be nice to avoid all this trouble. > > On Sep 14, 2010, at 4:54 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Tue Sep 14 18:54:06 2010 >> New Revision: 113903 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113903&view=rev >> Log: >> Reapply r113875 with additional cleanups. >> >> "The register specified for a dregpair is the corresponding Q register, so to >> get the pair, we need to look up the sub-regs based on the qreg. Create a >> lookup function since we don't have access to TargetRegisterInfo here to >> be able to use getSubReg(ARM::dsub_[01])." >> >> Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use >> the dregpair modifier for the 2xdreg versions. Explicitly specifying the two >> registers as operands is more correct and more consistent with the other >> instruction patterns. This enables further cleanup of special case code in the >> disassembler as a nice side-effect. >> >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp >> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp >> llvm/trunk/test/MC/Disassembler/neon-tests.txt >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113903&r1=113902&r2=113903&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 14 18:54:06 2010 >> @@ -218,9 +218,9 @@ >> "vld1", Dt, "\\{$dst\\}, $addr$offset", >> "$addr.addr = $wb", []>; >> class VLD1QWB op7_4, string Dt> >> - : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb), >> + : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), >> (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, >> - "vld1", Dt, "${dst:dregpair}, $addr$offset", >> + "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset", >> "$addr.addr = $wb", []>; >> >> def VLD1d8_UPD : VLD1DWB<0b0000, "8">; >> @@ -675,8 +675,9 @@ >> "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>; >> class VST1QWB op7_4, string Dt> >> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), >> - (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST, >> - "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>; >> + (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2), >> + IIC_VST, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset", >> + "$addr.addr = $wb", []>; >> >> def VST1d8_UPD : VST1DWB<0b0000, "8">; >> def VST1d16_UPD : VST1DWB<0b0100, "16">; >> >> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113903&r1=113902&r2=113903&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Tue Sep 14 18:54:06 2010 >> @@ -29,73 +29,27 @@ >> #undef MachineInstr >> #undef ARMAsmPrinter >> >> -static unsigned NextReg(unsigned Reg) { >> - switch (Reg) { >> +// Get the constituent sub-regs for a dregpair from a Q register. >> +static std::pair GetDRegPair(unsigned QReg) { >> + switch (QReg) { >> default: >> assert(0 && "Unexpected register enum"); >> - >> - case ARM::D0: >> - return ARM::D1; >> - case ARM::D1: >> - return ARM::D2; >> - case ARM::D2: >> - return ARM::D3; >> - case ARM::D3: >> - return ARM::D4; >> - case ARM::D4: >> - return ARM::D5; >> - case ARM::D5: >> - return ARM::D6; >> - case ARM::D6: >> - return ARM::D7; >> - case ARM::D7: >> - return ARM::D8; >> - case ARM::D8: >> - return ARM::D9; >> - case ARM::D9: >> - return ARM::D10; >> - case ARM::D10: >> - return ARM::D11; >> - case ARM::D11: >> - return ARM::D12; >> - case ARM::D12: >> - return ARM::D13; >> - case ARM::D13: >> - return ARM::D14; >> - case ARM::D14: >> - return ARM::D15; >> - case ARM::D15: >> - return ARM::D16; >> - case ARM::D16: >> - return ARM::D17; >> - case ARM::D17: >> - return ARM::D18; >> - case ARM::D18: >> - return ARM::D19; >> - case ARM::D19: >> - return ARM::D20; >> - case ARM::D20: >> - return ARM::D21; >> - case ARM::D21: >> - return ARM::D22; >> - case ARM::D22: >> - return ARM::D23; >> - case ARM::D23: >> - return ARM::D24; >> - case ARM::D24: >> - return ARM::D25; >> - case ARM::D25: >> - return ARM::D26; >> - case ARM::D26: >> - return ARM::D27; >> - case ARM::D27: >> - return ARM::D28; >> - case ARM::D28: >> - return ARM::D29; >> - case ARM::D29: >> - return ARM::D30; >> - case ARM::D30: >> - return ARM::D31; >> + case ARM::Q0: return std::pair(ARM::D0, ARM::D1); >> + case ARM::Q1: return std::pair(ARM::D2, ARM::D3); >> + case ARM::Q2: return std::pair(ARM::D4, ARM::D5); >> + case ARM::Q3: return std::pair(ARM::D6, ARM::D7); >> + case ARM::Q4: return std::pair(ARM::D8, ARM::D9); >> + case ARM::Q5: return std::pair(ARM::D10, ARM::D11); >> + case ARM::Q6: return std::pair(ARM::D12, ARM::D13); >> + case ARM::Q7: return std::pair(ARM::D14, ARM::D15); >> + case ARM::Q8: return std::pair(ARM::D16, ARM::D17); >> + case ARM::Q9: return std::pair(ARM::D18, ARM::D19); >> + case ARM::Q10: return std::pair(ARM::D20, ARM::D21); >> + case ARM::Q11: return std::pair(ARM::D22, ARM::D23); >> + case ARM::Q12: return std::pair(ARM::D24, ARM::D25); >> + case ARM::Q13: return std::pair(ARM::D26, ARM::D27); >> + case ARM::Q14: return std::pair(ARM::D28, ARM::D29); >> + case ARM::Q15: return std::pair(ARM::D30, ARM::D31); >> } >> } >> >> @@ -189,19 +143,11 @@ >> if (Op.isReg()) { >> unsigned Reg = Op.getReg(); >> if (Modifier && strcmp(Modifier, "dregpair") == 0) { >> - O << '{' << getRegisterName(Reg) << ", " >> - << getRegisterName(NextReg(Reg)) << '}'; >> -#if 0 >> - // FIXME: Breaks e.g. ARM/vmul.ll. >> - assert(0); >> - /* >> - unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0); >> - unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1); >> - O << '{' >> - << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) >> - << '}';*/ >> -#endif >> + std::pair dregpair = GetDRegPair(Reg); >> + O << '{' << getRegisterName(dregpair.first) << ", " >> + << getRegisterName(dregpair.second) << '}'; >> } else if (Modifier && strcmp(Modifier, "lane") == 0) { >> + // FIXME >> assert(0); >> /* >> unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); >> >> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=113903&r1=113902&r2=113903&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Sep 14 18:54:06 2010 >> @@ -79,22 +79,9 @@ >> } >> >> // Return the register enum Based on RegClass and the raw register number. >> -// For DRegPair, see comments below. >> // FIXME: Auto-gened? >> -static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister, >> - bool DRegPair = false) { >> - >> - if (DRegPair && RegClassID == ARM::QPRRegClassID) { >> - // LLVM expects { Dd, Dd+1 } to form a super register; this is not specified >> - // in the ARM Architecture Manual as far as I understand it (A8.6.307). >> - // Therefore, we morph the RegClassID to be the sub register class and don't >> - // subsequently transform the RawRegister encoding when calculating RegNum. >> - // >> - // See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part >> - // where this workaround is meant for. >> - RegClassID = ARM::DPRRegClassID; >> - } >> - >> +static unsigned >> +getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) { >> // For this purpose, we can treat rGPR as if it were GPR. >> if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID; >> >> @@ -2201,22 +2188,6 @@ >> return (insn >> 8) & 0xF; >> } >> >> -static bool UseDRegPair(unsigned Opcode) { >> - switch (Opcode) { >> - default: >> - return false; >> - case ARM::VLD1q8_UPD: >> - case ARM::VLD1q16_UPD: >> - case ARM::VLD1q32_UPD: >> - case ARM::VLD1q64_UPD: >> - case ARM::VST1q8_UPD: >> - case ARM::VST1q16_UPD: >> - case ARM::VST1q32_UPD: >> - case ARM::VST1q64_UPD: >> - return true; >> - } >> -} >> - >> // VLD* >> // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] >> // VLD*LN* >> @@ -2243,10 +2214,9 @@ >> >> // We have homogeneous NEON registers for Load/Store. >> unsigned RegClass = 0; >> - bool DRegPair = UseDRegPair(Opcode); >> >> // Double-spaced registers have increments of 2. >> - unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1; >> + unsigned Inc = DblSpaced ? 2 : 1; >> >> unsigned Rn = decodeRn(insn); >> unsigned Rm = decodeRm(insn); >> @@ -2292,7 +2262,7 @@ >> RegClass = OpInfo[OpIdx].RegClass; >> while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { >> MI.addOperand(MCOperand::CreateReg( >> - getRegisterEnum(B, RegClass, Rd, DRegPair))); >> + getRegisterEnum(B, RegClass, Rd))); >> Rd += Inc; >> ++OpIdx; >> } >> @@ -2311,7 +2281,7 @@ >> >> while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { >> MI.addOperand(MCOperand::CreateReg( >> - getRegisterEnum(B, RegClass, Rd, DRegPair))); >> + getRegisterEnum(B, RegClass, Rd))); >> Rd += Inc; >> ++OpIdx; >> } >> >> Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=113903&r1=113902&r2=113903&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) >> +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Tue Sep 14 18:54:06 2010 >> @@ -9,10 +9,12 @@ >> # CHECK: vdup.32 q3, d1[0] >> 0x41 0x6c 0xb4 0xf3 >> >> -# VLD1q8_UPD (with ${dst:dregpair} operand) >> # CHECK: vld1.8 {d17, d18}, [r6], r5 >> 0x05 0x1a 0x66 0xf4 >> >> +# CHECK: vld1.8 {d17, d18, d19}, [r6], r5 >> +0x05 0x16 0x66 0xf4 >> + >> # CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 >> 0x07 0x00 0x22 0xf4 >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From sabre at nondot.org Tue Sep 14 19:30:11 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 00:30:11 -0000 Subject: [llvm-commits] [llvm] r113911 - in /llvm/trunk: lib/Transforms/IPO/ConstantMerge.cpp test/Transforms/ConstantMerge/dont-merge.ll Message-ID: <20100915003011.373C12A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 19:30:11 2010 New Revision: 113911 URL: http://llvm.org/viewvc/llvm-project?rev=113911&view=rev Log: fix PR8144, a bug where constant merge would merge globals marked attribute(used). Modified: llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp llvm/trunk/test/Transforms/ConstantMerge/dont-merge.ll Modified: llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp?rev=113911&r1=113910&r2=113911&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ConstantMerge.cpp Tue Sep 14 19:30:11 2010 @@ -19,10 +19,12 @@ #define DEBUG_TYPE "constmerge" #include "llvm/Transforms/IPO.h" +#include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" using namespace llvm; @@ -46,7 +48,27 @@ ModulePass *llvm::createConstantMergePass() { return new ConstantMerge(); } + + +/// Find values that are marked as llvm.used. +static void FindUsedValues(GlobalVariable *LLVMUsed, + SmallPtrSet &UsedValues) { + if (LLVMUsed == 0) return; + ConstantArray *Inits = dyn_cast(LLVMUsed->getInitializer()); + if (Inits == 0) return; + + for (unsigned i = 0, e = Inits->getNumOperands(); i != e; ++i) + if (GlobalValue *GV = + dyn_cast(Inits->getOperand(i)->stripPointerCasts())) + UsedValues.insert(GV); +} + bool ConstantMerge::runOnModule(Module &M) { + // Find all the globals that are marked "used". These cannot be merged. + SmallPtrSet UsedGlobals; + FindUsedValues(M.getGlobalVariable("llvm.used"), UsedGlobals); + FindUsedValues(M.getGlobalVariable("llvm.compiler.used"), UsedGlobals); + // Map unique constant/section pairs to globals. We don't want to merge // globals in different sections. DenseMap CMap; @@ -79,9 +101,13 @@ // Only process constants with initializers in the default addres space. if (!GV->isConstant() ||!GV->hasDefinitiveInitializer() || - GV->getType()->getAddressSpace() != 0 || !GV->getSection().empty()) + GV->getType()->getAddressSpace() != 0 || !GV->getSection().empty() || + // Don't touch values marked with attribute(used). + UsedGlobals.count(GV)) continue; + + Constant *Init = GV->getInitializer(); // Check to see if the initializer is already known. Modified: llvm/trunk/test/Transforms/ConstantMerge/dont-merge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantMerge/dont-merge.ll?rev=113911&r1=113910&r2=113911&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ConstantMerge/dont-merge.ll (original) +++ llvm/trunk/test/Transforms/ConstantMerge/dont-merge.ll Tue Sep 14 19:30:11 2010 @@ -28,3 +28,17 @@ store i32 addrspace(30)* @T2b, i32 addrspace(30)** %P2 ret void } + +; PR8144 - Don't merge globals marked attribute(used) +; CHECK: @T3A = +; CHECK: @T3B = + + at T3A = internal constant i32 0 + at T3B = internal constant i32 0 + at llvm.used = appending global [2 x i32*] [i32* @T3A, i32* @T3B], section +"llvm.metadata" + +define void @test3() { + call void asm sideeffect "T3A, T3B",""() ; invisible use of T3A and T3B + ret void +} From grosbach at apple.com Tue Sep 14 19:49:43 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 14 Sep 2010 17:49:43 -0700 Subject: [llvm-commits] [llvm] r113886 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <20100914230337.CAE6D2A6C12C@llvm.org> References: <20100914230337.CAE6D2A6C12C@llvm.org> Message-ID: Very cool. This should be useful for all kinds of stuff. A few minor comments below. On Sep 14, 2010, at 4:03 PM, Eric Christopher wrote: > Author: echristo > Date: Tue Sep 14 18:03:37 2010 > New Revision: 113886 > > URL: http://llvm.org/viewvc/llvm-project?rev=113886&view=rev > Log: > Emit libcalls for SDIV, this requires some call infrastructure > that needs to be shared a bit more widely around. > > Modified: > llvm/trunk/lib/Target/ARM/ARMFastISel.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113886&r1=113885&r2=113886&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Sep 14 18:03:37 2010 > @@ -24,6 +24,7 @@ > #include "llvm/GlobalVariable.h" > #include "llvm/Instructions.h" > #include "llvm/IntrinsicInst.h" > +#include "llvm/Module.h" > #include "llvm/CodeGen/Analysis.h" > #include "llvm/CodeGen/FastISel.h" > #include "llvm/CodeGen/FunctionLoweringInfo.h" > @@ -121,6 +122,7 @@ > virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode); > virtual bool ARMSelectSIToFP(const Instruction *I); > virtual bool ARMSelectFPToSI(const Instruction *I); > + virtual bool ARMSelectSDiv(const Instruction *I); > You can remove the "ARM" prefix from these function names. They're members of the ARMFastISel class already, so no need to specify "ARM" twice. If the idea is to differentiate from Thumb, it might be better to follow the idiom of the RegisterInfo classes and have a completely separate class for that, perhaps with a common base class if there's shared bits (probably will be; there is for the not-so-fast-isel). > // Utility routines. > private: > @@ -139,6 +141,7 @@ > // Call handling routines. > private: > CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return); > + bool ARMEmitLibcall(const Instruction *I, Function *F); > // OptionalDef handling routines. > private: > @@ -931,6 +934,155 @@ > } > } > > +// A quick function that will emit a call for a named libcall in F with the > +// vector of passed arguments for the Instruction in I. We can assume that we > +// can emit a call for any libcall we can produce. This is an abridged version > +// of the full call infrastructure since we won't need to worry about things > +// like computed function pointers or strange arguments at call sites. > +// TODO: Try to unify this and the normal call bits for ARM, then try to unify > +// with X86. This stuff assumes the arguments all fit in registers for the time being if I follow right. Is that correct? Probably worth putting in a "return false" for cases where that's not true. > +bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) { > + CallingConv::ID CC = F->getCallingConv(); > + > + // Handle *simple* calls for now. > + const Type *RetTy = F->getReturnType(); > + EVT RetVT; > + if (RetTy->isVoidTy()) > + RetVT = MVT::isVoid; > + else if (!isTypeLegal(RetTy, RetVT)) > + return false; > + > + assert(!F->isVarArg() && "Vararg libcall?!"); > + > + // Abridged from the X86 FastISel call selection mechanism > + SmallVector Args; > + SmallVector ArgRegs; > + SmallVector ArgVTs; > + SmallVector ArgFlags; > + Args.reserve(I->getNumOperands()); > + ArgRegs.reserve(I->getNumOperands()); > + ArgVTs.reserve(I->getNumOperands()); > + ArgFlags.reserve(I->getNumOperands()); > + for (unsigned i = 0; i < Args.size(); ++i) { > + Value *Op = I->getOperand(i); > + unsigned Arg = getRegForValue(Op); > + if (Arg == 0) return false; > + > + const Type *ArgTy = Op->getType(); > + EVT ArgVT; > + if (!isTypeLegal(ArgTy, ArgVT)) return false; > + > + ISD::ArgFlagsTy Flags; > + unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); > + Flags.setOrigAlign(OriginalAlignment); > + > + Args.push_back(Op); > + ArgRegs.push_back(Arg); > + ArgVTs.push_back(ArgVT); > + ArgFlags.push_back(Flags); > + } > + > + SmallVector ArgLocs; > + CCState CCInfo(CC, false, TM, ArgLocs, F->getContext()); > + CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false)); > + > + // Process the args. > + SmallVector RegArgs; > + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { > + CCValAssign &VA = ArgLocs[i]; > + unsigned Arg = ArgRegs[VA.getValNo()]; > + EVT ArgVT = ArgVTs[VA.getValNo()]; > + > + // Should we ever have to promote? > + switch (VA.getLocInfo()) { > + case CCValAssign::Full: break; > + default: > + assert(false && "Handle arg promotion for libcalls?"); > + return false; > + } > + > + // Now copy/store arg to correct locations. > + if (VA.isRegLoc()) { > + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), > + VA.getLocReg()).addReg(Arg); The COPY opcode automatically handles stuff like moving a value across register classes (e.g., floating point values being passed in GPRs), if I recall correctly, so this should be fine. Possibly worth validating that, though. > + RegArgs.push_back(VA.getLocReg()); > + } else { > + // Need to store > + return false; > + } > + } > + > + // Issue the call, BLr9 for darwin, BL otherwise. > + MachineInstrBuilder MIB; > + unsigned CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL; > + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) > + .addGlobalAddress(F, 0, 0); > + > + // Add implicit physical register uses to the call. > + for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) > + MIB.addReg(RegArgs[i]); > + > + // Now the return value. > + SmallVector UsedRegs; > + if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { > + SmallVector RVLocs; > + CCState CCInfo(CC, false, TM, RVLocs, F->getContext()); > + CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true)); > + > + // Copy all of the result registers out of their specified physreg. > + assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); > + EVT CopyVT = RVLocs[0].getValVT(); > + TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); > + > + unsigned ResultReg = createResultReg(DstRC); > + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), > + ResultReg).addReg(RVLocs[0].getLocReg()); > + UsedRegs.push_back(RVLocs[0].getLocReg()); > + > + // Finally update the result. > + UpdateValueMap(I, ResultReg); > + } > + > + // Set all unused physreg defs as dead. > + static_cast(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); > + > + return true; > +} > + > +bool ARMFastISel::ARMSelectSDiv(const Instruction *I) { > + EVT VT; > + const Type *Ty = I->getType(); > + if (!isTypeLegal(Ty, VT)) > + return false; > + > + // If we have integer div support we should have gotten already, emit a Should have gotten what already? Might be worth considering an assert on !Subtarget->hasHWDiv() just for giggles. > + // libcall. > + RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; > + if (VT == MVT::i16) > + LC = RTLIB::SDIV_I16; > + else if (VT == MVT::i32) > + LC = RTLIB::SDIV_I32; > + else if (VT == MVT::i64) > + LC = RTLIB::SDIV_I64; > + else if (VT == MVT::i128) > + LC = RTLIB::SDIV_I128; > + assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); > + > + // Binary operand with all the same type. > + std::vector ArgTys; > + ArgTys.push_back(Ty); > + ArgTys.push_back(Ty); > + const FunctionType *FTy = FunctionType::get(Ty, ArgTys, false); > + Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage, > + TLI.getLibcallName(LC)); > + if (Subtarget->isAAPCS_ABI()) > + F->setCallingConv(CallingConv::ARM_AAPCS); > + else > + F->setCallingConv(I->getParent()->getParent()->getCallingConv()); > + > + return ARMEmitLibcall(I, F); > +} > + > // TODO: SoftFP support. > bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { > // No Thumb-1 for now. > @@ -960,6 +1112,8 @@ > return ARMSelectBinaryOp(I, ISD::FSUB); > case Instruction::FMul: > return ARMSelectBinaryOp(I, ISD::FMUL); > + case Instruction::SDiv: > + return ARMSelectSDiv(I); > default: break; > } > return false; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/2ff6f4d0/attachment.html From dalej at apple.com Tue Sep 14 19:52:23 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 15 Sep 2010 00:52:23 -0000 Subject: [llvm-commits] [llvm] r113914 - in /llvm/trunk: include/llvm/Type.h lib/Target/TargetData.cpp lib/VMCore/ValueTypes.cpp Message-ID: <20100915005223.EFA9A2A6C12C@llvm.org> Author: johannes Date: Tue Sep 14 19:52:23 2010 New Revision: 113914 URL: http://llvm.org/viewvc/llvm-project?rev=113914&view=rev Log: Add x86MMX a few more places. Modified: llvm/trunk/include/llvm/Type.h llvm/trunk/lib/Target/TargetData.cpp llvm/trunk/lib/VMCore/ValueTypes.cpp Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=113914&r1=113913&r2=113914&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Tue Sep 14 19:52:23 2010 @@ -313,7 +313,8 @@ /// bool isSized() const { // If it's a primitive, it is always sized. - if (ID == IntegerTyID || isFloatingPointTy() || ID == PointerTyID) + if (ID == IntegerTyID || isFloatingPointTy() || ID == PointerTyID || + ID == X86_MMXTyID) return true; // If it is not something that can have a size (e.g. a function or label), // it doesn't have a size. Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=113914&r1=113913&r2=113914&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Tue Sep 14 19:52:23 2010 @@ -524,6 +524,7 @@ case Type::X86_FP80TyID: AlignType = FLOAT_ALIGN; break; + case Type::X86_MMXTyID: case Type::VectorTyID: AlignType = VECTOR_ALIGN; break; Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=113914&r1=113913&r2=113914&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ValueTypes.cpp (original) +++ llvm/trunk/lib/VMCore/ValueTypes.cpp Tue Sep 14 19:52:23 2010 @@ -198,6 +198,7 @@ case Type::FloatTyID: return MVT(MVT::f32); case Type::DoubleTyID: return MVT(MVT::f64); case Type::X86_FP80TyID: return MVT(MVT::f80); + case Type::X86_MMXTyID: return MVT(MVT::x86mmx); case Type::FP128TyID: return MVT(MVT::f128); case Type::PPC_FP128TyID: return MVT(MVT::ppcf128); case Type::PointerTyID: return MVT(MVT::iPTR); From grosbach at apple.com Tue Sep 14 20:01:45 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 01:01:45 -0000 Subject: [llvm-commits] [llvm] r113915 - /llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <20100915010145.94C332A6C12C@llvm.org> Author: grosbach Date: Tue Sep 14 20:01:45 2010 New Revision: 113915 URL: http://llvm.org/viewvc/llvm-project?rev=113915&view=rev Log: trailing whitespace Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=113915&r1=113914&r2=113915&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Tue Sep 14 20:01:45 2010 @@ -62,7 +62,7 @@ if (Subtarget->isTargetCOFF()) { bool Intrn = MF.getFunction()->hasInternalLinkage(); OutStreamer.BeginCOFFSymbolDef(CurrentFnSym); - OutStreamer.EmitCOFFSymbolStorageClass(Intrn ? COFF::IMAGE_SYM_CLASS_STATIC + OutStreamer.EmitCOFFSymbolStorageClass(Intrn ? COFF::IMAGE_SYM_CLASS_STATIC : COFF::IMAGE_SYM_CLASS_EXTERNAL); OutStreamer.EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT); @@ -95,7 +95,7 @@ break; case MachineOperand::MO_GlobalAddress: { const GlobalValue *GV = MO.getGlobal(); - + MCSymbol *GVSym; if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) GVSym = GetSymbolWithGlobalValueBase(GV, "$stub"); @@ -109,11 +109,11 @@ // Handle dllimport linkage. if (MO.getTargetFlags() == X86II::MO_DLLIMPORT) GVSym = OutContext.GetOrCreateSymbol(Twine("__imp_") + GVSym->getName()); - + if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY || MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE) { MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); - MachineModuleInfoImpl::StubValueTy &StubSym = + MachineModuleInfoImpl::StubValueTy &StubSym = MMI->getObjFileInfo().getGVStubEntry(Sym); if (StubSym.getPointer() == 0) StubSym = MachineModuleInfoImpl:: @@ -133,7 +133,7 @@ StubSym = MachineModuleInfoImpl:: StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage()); } - + // If the name begins with a dollar-sign, enclose it in parens. We do this // to avoid having it look like an integer immediate to the assembler. if (GVSym->getName()[0] != '$') @@ -149,7 +149,7 @@ SmallString<128> TempNameStr; TempNameStr += StringRef(MO.getSymbolName()); TempNameStr += StringRef("$stub"); - + MCSymbol *Sym = GetExternalSymbolSymbol(TempNameStr.str()); MachineModuleInfoImpl::StubValueTy &StubSym = MMI->getObjFileInfo().getFnStubEntry(Sym); @@ -163,17 +163,17 @@ } else { SymToPrint = GetExternalSymbolSymbol(MO.getSymbolName()); } - + // If the name begins with a dollar-sign, enclose it in parens. We do this // to avoid having it look like an integer immediate to the assembler. - if (SymToPrint->getName()[0] != '$') + if (SymToPrint->getName()[0] != '$') O << *SymToPrint; else O << '(' << *SymToPrint << '('; break; } } - + switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); @@ -188,7 +188,7 @@ O << " + [.-"; PrintPICBaseSymbol(O); O << ']'; - break; + break; case X86II::MO_PIC_BASE_OFFSET: case X86II::MO_DARWIN_NONLAZY_PIC_BASE: case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: @@ -262,7 +262,7 @@ case MachineOperand::MO_JumpTableIndex: case MachineOperand::MO_ConstantPoolIndex: - case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_ExternalSymbol: { O << '$'; printSymbolOperand(MO, O); @@ -298,10 +298,10 @@ if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && BaseReg.getReg() == X86::RIP) HasBaseReg = false; - + // HasParenPart - True if we will print out the () part of the mem ref. bool HasParenPart = IndexReg.getReg() || HasBaseReg; - + if (DispSpec.isImm()) { int DispVal = DispSpec.getImm(); if (DispVal || !HasParenPart) @@ -386,14 +386,14 @@ if (ExtraCode[1] != 0) return true; // Unknown modifier. const MachineOperand &MO = MI->getOperand(OpNo); - + switch (ExtraCode[0]) { default: return true; // Unknown modifier. case 'a': // This is an address. Currently only 'i' and 'r' are expected. if (MO.isImm()) { O << MO.getImm(); return false; - } + } if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) { printSymbolOperand(MO, O); if (Subtarget->isPICStyleRIPRel()) @@ -490,13 +490,13 @@ // All darwin targets use mach-o. MachineModuleInfoMachO &MMIMacho = MMI->getObjFileInfo(); - + // Output stubs for dynamically-linked functions. MachineModuleInfoMachO::SymbolListTy Stubs; Stubs = MMIMacho.GetFnStubList(); if (!Stubs.empty()) { - const MCSection *TheSection = + const MCSection *TheSection = OutContext.getMachOSection("__IMPORT", "__jump_table", MCSectionMachO::S_SYMBOL_STUBS | MCSectionMachO::S_ATTR_SELF_MODIFYING_CODE | @@ -514,7 +514,7 @@ const char HltInsts[] = { -12, -12, -12, -12, -12 }; OutStreamer.EmitBytes(StringRef(HltInsts, 5), 0/*addrspace*/); } - + Stubs.clear(); OutStreamer.AddBlankLine(); } @@ -522,7 +522,7 @@ // Output stubs for external and common global variables. Stubs = MMIMacho.GetGVStubList(); if (!Stubs.empty()) { - const MCSection *TheSection = + const MCSection *TheSection = OutContext.getMachOSection("__IMPORT", "__pointers", MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, SectionKind::getMetadata()); @@ -661,12 +661,12 @@ } } -MachineLocation +MachineLocation X86AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const { MachineLocation Location; assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!"); // Frame address. Currently handles register +- offset only. - + if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm()) Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); else { @@ -690,9 +690,9 @@ O << V.getName(); O << " <- "; // Frame address. Currently handles register +- offset only. - O << '['; + O << '['; if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg()) - printOperand(MI, 0, O); + printOperand(MI, 0, O); else O << "undef"; O << '+'; printOperand(MI, 3, O); @@ -718,10 +718,10 @@ } // Force static initialization. -extern "C" void LLVMInitializeX86AsmPrinter() { +extern "C" void LLVMInitializeX86AsmPrinter() { RegisterAsmPrinter X(TheX86_32Target); RegisterAsmPrinter Y(TheX86_64Target); - + TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,createX86MCInstPrinter); TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,createX86MCInstPrinter); } From rafael.espindola at gmail.com Tue Sep 14 20:13:57 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 14 Sep 2010 21:13:57 -0400 Subject: [llvm-commits] some thoughts on lowering for calling conventions In-Reply-To: References: <20100911173742.2316C2A6C12C@llvm.org> Message-ID: On 14 September 2010 12:49, Bob Wilson wrote: > This patch and an unrelated comment from Eric got me thinking some more about llvm's handling of calling conventions. ?I'm not very happy with our current approach. ?The specific issue I'm thinking about now is that we lower either too early or too late. Nice to have you on board! This has been one of by pet peeves for some time ... > Lowering in the front-end should be minimized. ?It's too early. ?Interprocedural analyses and optimizations will suffer. (E.g., when an f64 argument is lowered to a pair of i32 values, it's hard for an analysis to track how that argument is used.) Since we currently support 2 front-ends, it also means that we need to do the front-end lowering in 2 places and keep both of them up to date. ?The front-end has to do some lowering in cases where the back-end doesn't have the language-specific information to do the job, but otherwise, I'd like to see the front-end avoid lowering for calling conventions. > > Aside from the front-ends, the rest of our calling convention support is handled with selection DAGs. ?That is too late. ?We'd really like the optimizer to see all the code for splitting up and recombining arguments. ?The DAG combiner and machine instruction optimizations clean up some of expanded code, but it's not ideal. ?I assume that is the motivation for Rafael's patch here. ?Eric is working on fast isel for ARM, and he mentioned to me recently that since fast isel doesn't build selection DAGs, it has to duplicate all the support for lowering calling conventions. I agree with this in general. Since these were the only two places I could see the lowering being done, it looked better to have it done in the FE. The current implementation has some really annoying problems: *) Has to be reimplemented for fast isel or any other instruction selection solution we want to create. *) Less things are explicit in the IL, so more arch specific knowledge is needed in any pass that wants to take advantage of it. *) I think the IL has multiple ways to represent the "same" function. Two examples: *) By extending the use of pad arguments it is probably possible to remove the alignment of byval attributes. *) By having the FE lower floating point argument to integers when the ABI mandates that FP values be passed on integer registers we might be able to drop most of the extra logic for handing the aapcs_vfp calling convention. *) Doing it all in the DAG produces code that is hard to read. Things are a *lot* better these days, but moving the of C specific knowledge out would help. *) There is a mismatch on what the IL means and what it needs. For example, on x86-64 clang will compile --------------------------------- struct foo { long a; long b; char c; }; void f(struct foo x); void g(void) { struct foo y = {1, 2, 3}; f(y); } ---------------------------------- into ----------------------------------------- %struct.foo = type { i64, i64, i8 } define void @g() nounwind optsize { entry: %agg.tmp = alloca %struct.foo, align 8 %0 = bitcast %struct.foo* %agg.tmp to i192* store i192 1020847100762815390427017310442723737601, i192* %0, align 8 call void @f(%struct.foo* byval %agg.tmp) nounwind optsize ret void } declare void @f(%struct.foo* byval) ---------------------------------------- This is bad, because there is no requirement for the caller to have this data in memory. If the struct was passed with FCA or similar solution then the callee would suffer from not knowing that the data was already in memory and something like void h(struct foo *x); void f(struct foo x){ h(&x); } Would produce low quality code. Some solution where the call instruction implicitly does the copy is probably what is needed. That way f, in the above example can be declared to take a byval argument and knows it is in memory and the IL for g can use a FCA and not have to allocate stack for it. *) Function with variable number of arguments have another set of problems. Hopefully a move to use va_arg will let us avoid some dead stores and maybe even make it possible to inline some basic va_arg functions :-) Having two FE is an issue. If we get really serious about lowering in the FE it might be possible to factor out some of the ABI bits from clang into a mini library and use it in llvm-gcc. It not very familiar with IPO to know how hard it is for them to follow argument splitting, but cannot be as easy as without splitting. > Can we do better? > > If we had a target-specific lowering for calling conventions at the llvm IR level, instead of for selection DAGs, then we could run that lowering pass after any high-level interprocedural analyses and optimizations but before things like instcombine. ?That would avoid the need for front-ends to "pre-lower" things like this patch, avoid duplicating effort across front-ends and across selection DAGs and fast-isel, preserve information for high-level passes, and hopefully give us better optimization of the code resulting from lowering. > > Thoughts? ?(I fully expect there to be many obstacles to such a change, but I'm curious to hear if there's any consensus about the right solution for the long term. ?I'm not necessarily advocating that we change anything right now.) I like it, with the only note that when doing something in the FE could simplify the IL definition by removing the need for an attribute or a new calling convention then we should probably do it there. Cheers, Rafael From bob.wilson at apple.com Tue Sep 14 20:48:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 15 Sep 2010 01:48:05 -0000 Subject: [llvm-commits] [llvm] r113918 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMInstrNEON.td Message-ID: <20100915014805.8745E2A6C12C@llvm.org> Author: bwilson Date: Tue Sep 14 20:48:05 2010 New Revision: 113918 URL: http://llvm.org/viewvc/llvm-project?rev=113918&view=rev Log: Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and storeRegToStackSlot. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113918&r1=113917&r2=113918&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 14 20:48:05 2010 @@ -748,7 +748,7 @@ case ARM::QPR_VFP2RegClassID: case ARM::QPR_8RegClassID: if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo)) .addFrameIndex(FI).addImm(16) .addReg(SrcReg, getKillRegState(isKill)) .addMemOperand(MMO)); @@ -765,13 +765,10 @@ if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { // FIXME: It's possible to only store part of the QQ register if the // spilled def has a sub-register index. - MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1d64Q)) - .addFrameIndex(FI).addImm(16); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); - MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); - AddDefaultPred(MIB.addMemOperand(MMO)); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) + .addFrameIndex(FI).addImm(16) + .addReg(SrcReg, getKillRegState(isKill)) + .addMemOperand(MMO)); } else { MachineInstrBuilder MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) @@ -846,7 +843,7 @@ case ARM::QPR_VFP2RegClassID: case ARM::QPR_8RegClassID: if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg) .addFrameIndex(FI).addImm(16) .addMemOperand(MMO)); } else { @@ -859,12 +856,9 @@ case ARM::QQPRRegClassID: case ARM::QQPR_VFP2RegClassID: if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { - MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1d64Q)); - MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); - MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); - MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); - MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI); - AddDefaultPred(MIB.addFrameIndex(FI).addImm(16).addMemOperand(MMO)); + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) + .addFrameIndex(FI).addImm(16) + .addMemOperand(MMO)); } else { MachineInstrBuilder MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113918&r1=113917&r2=113918&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 14 20:48:05 2010 @@ -138,15 +138,6 @@ "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "", [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>; -let mayLoad = 1, neverHasSideEffects = 1 in { -// Use vld1 to load a Q register as a D register pair. -// This alternative to VLDMQ allows an alignment to be specified. -// This is equivalent to VLD1q64 except that it has a Q register operand. -def VLD1q - : NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr), - IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>; -} // mayLoad = 1, neverHasSideEffects = 1 - // Use vstmia to store a Q register as a D register pair. // This is equivalent to VSTMD except that it has a Q register operand // instead of a pair of D registers. @@ -156,15 +147,6 @@ "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "", [(store (v2f64 QPR:$src), addrmode4:$addr)]>; -let mayStore = 1, neverHasSideEffects = 1 in { -// Use vst1 to store a Q register as a D register pair. -// This alternative to VSTMQ allows an alignment to be specified. -// This is equivalent to VST1q64 except that it has a Q register operand. -def VST1q - : NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src), - IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>; -} // mayStore = 1, neverHasSideEffects = 1 - let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { // Classes for VLD* pseudo-instructions with multi-register operands. From bob.wilson at apple.com Tue Sep 14 20:52:33 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 15 Sep 2010 01:52:33 -0000 Subject: [llvm-commits] [llvm] r113919 - /llvm/trunk/utils/TableGen/NeonEmitter.cpp Message-ID: <20100915015233.2AE2A2A6C12C@llvm.org> Author: bwilson Date: Tue Sep 14 20:52:33 2010 New Revision: 113919 URL: http://llvm.org/viewvc/llvm-project?rev=113919&view=rev Log: Use float64 instead of int64 vector elements for NEON vget_low and vget_high functions, since int64 is not a legal type and using it leads to inefficient code. PR8036. Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=113919&r1=113918&r2=113919&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Tue Sep 14 20:52:33 2010 @@ -552,10 +552,14 @@ } std::string ts = TypeString(proto[0], typestr); - std::string s = ts + " r; r"; - - if (structTypes) - s += ".val"; + std::string s; + if (op == OpHi || op == OpLo) { + s = "union { " + ts + " r; double d; } u; u.d"; + } else { + s = ts + " r; r"; + if (structTypes) + s += ".val"; + } s += " = "; @@ -631,10 +635,10 @@ s += ", (__neon_int64x1_t)" + b + ", 0, 1)"; break; case OpHi: - s += "(__neon_int64x1_t)(((__neon_int64x2_t)" + a + ")[1])"; + s += "(((__neon_float64x2_t)" + a + ")[1])"; break; case OpLo: - s += "(__neon_int64x1_t)(((__neon_int64x2_t)" + a + ")[0])"; + s += "(((__neon_float64x2_t)" + a + ")[0])"; break; case OpDup: s += Duplicate(nElts << (int)quad, typestr, a); @@ -671,7 +675,10 @@ throw "unknown OpKind!"; break; } - s += "; return r;"; + if (op == OpHi || op == OpLo) + s += "; return u.r;"; + else + s += "; return r;"; return s; } @@ -923,6 +930,11 @@ } } OS << "\n"; + OS << "typedef __attribute__(( __vector_size__(8) )) " + "double __neon_float64x1_t;\n"; + OS << "typedef __attribute__(( __vector_size__(16) )) " + "double __neon_float64x2_t;\n"; + OS << "\n"; // Emit struct typedefs. for (unsigned vi = 1; vi != 5; ++vi) { From sabre at nondot.org Tue Sep 14 22:50:11 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 03:50:11 -0000 Subject: [llvm-commits] [llvm] r113921 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100915035011.4C1A02A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 22:50:11 2010 New Revision: 113921 URL: http://llvm.org/viewvc/llvm-project?rev=113921&view=rev Log: Diagnose invalid instructions like "incl" with "too few operands for instruction" instead of crashing. This fixes: rdar://8431815 - crash when invalid operand is one that isn't present Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113921&r1=113920&r2=113921&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 22:50:11 2010 @@ -1066,12 +1066,14 @@ // Recover location info for the operand if we know which was the problem. SMLoc ErrorLoc = IDLoc; if (OrigErrorInfo != ~0U) { + if (OrigErrorInfo >= Operands.size()) + return Error(IDLoc, "too few operands for instruction"); + ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc(); if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; } - Error(ErrorLoc, "invalid operand for instruction"); - return true; + return Error(ErrorLoc, "invalid operand for instruction"); } // If one instruction matched with a missing feature, report this as a From daniel at zuster.org Tue Sep 14 22:52:32 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 15 Sep 2010 03:52:32 -0000 Subject: [llvm-commits] [llvm] r113922 - in /llvm/trunk/utils/lit/lit: __init__.py lit.py main.py Message-ID: <20100915035232.24D192A6C12C@llvm.org> Author: ddunbar Date: Tue Sep 14 22:52:31 2010 New Revision: 113922 URL: http://llvm.org/viewvc/llvm-project?rev=113922&view=rev Log: lit: Rename main lit module to main.py, lit/lit/lit.py was a bit too, err, alliterate. Added: llvm/trunk/utils/lit/lit/main.py - copied, changed from r113919, llvm/trunk/utils/lit/lit/lit.py Removed: llvm/trunk/utils/lit/lit/lit.py Modified: llvm/trunk/utils/lit/lit/__init__.py Modified: llvm/trunk/utils/lit/lit/__init__.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/__init__.py?rev=113922&r1=113921&r2=113922&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/__init__.py (original) +++ llvm/trunk/utils/lit/lit/__init__.py Tue Sep 14 22:52:31 2010 @@ -1,6 +1,6 @@ """'lit' Testing Tool""" -from lit import main +from main import main __author__ = 'Daniel Dunbar' __email__ = 'daniel at zuster.org' Removed: llvm/trunk/utils/lit/lit/lit.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/lit.py?rev=113921&view=auto ============================================================================== --- llvm/trunk/utils/lit/lit/lit.py (original) +++ llvm/trunk/utils/lit/lit/lit.py (removed) @@ -1,648 +0,0 @@ -#!/usr/bin/env python - -""" -lit - LLVM Integrated Tester. - -See lit.pod for more information. -""" - -import math, os, platform, random, re, sys, time, threading, traceback - -import ProgressBar -import TestRunner -import Util - -from TestingConfig import TestingConfig -import LitConfig -import Test - -# Configuration files to look for when discovering test suites. These can be -# overridden with --config-prefix. -# -# FIXME: Rename to 'config.lit', 'site.lit', and 'local.lit' ? -gConfigName = 'lit.cfg' -gSiteConfigName = 'lit.site.cfg' - -kLocalConfigName = 'lit.local.cfg' - -class TestingProgressDisplay: - def __init__(self, opts, numTests, progressBar=None): - self.opts = opts - self.numTests = numTests - self.current = None - self.lock = threading.Lock() - self.progressBar = progressBar - self.completed = 0 - - def update(self, test): - # Avoid locking overhead in quiet mode - if self.opts.quiet and not test.result.isFailure: - self.completed += 1 - return - - # Output lock. - self.lock.acquire() - try: - self.handleUpdate(test) - finally: - self.lock.release() - - def finish(self): - if self.progressBar: - self.progressBar.clear() - elif self.opts.quiet: - pass - elif self.opts.succinct: - sys.stdout.write('\n') - - def handleUpdate(self, test): - self.completed += 1 - if self.progressBar: - self.progressBar.update(float(self.completed)/self.numTests, - test.getFullName()) - - if self.opts.succinct and not test.result.isFailure: - return - - if self.progressBar: - self.progressBar.clear() - - print '%s: %s (%d of %d)' % (test.result.name, test.getFullName(), - self.completed, self.numTests) - - if test.result.isFailure and self.opts.showOutput: - print "%s TEST '%s' FAILED %s" % ('*'*20, test.getFullName(), - '*'*20) - print test.output - print "*" * 20 - - sys.stdout.flush() - -class TestProvider: - def __init__(self, tests, maxTime): - self.maxTime = maxTime - self.iter = iter(tests) - self.lock = threading.Lock() - self.startTime = time.time() - - def get(self): - # Check if we have run out of time. - if self.maxTime is not None: - if time.time() - self.startTime > self.maxTime: - return None - - # Otherwise take the next test. - self.lock.acquire() - try: - item = self.iter.next() - except StopIteration: - item = None - self.lock.release() - return item - -class Tester(threading.Thread): - def __init__(self, litConfig, provider, display): - threading.Thread.__init__(self) - self.litConfig = litConfig - self.provider = provider - self.display = display - - def run(self): - while 1: - item = self.provider.get() - if item is None: - break - self.runTest(item) - - def runTest(self, test): - result = None - startTime = time.time() - try: - result, output = test.config.test_format.execute(test, - self.litConfig) - except KeyboardInterrupt: - # This is a sad hack. Unfortunately subprocess goes - # bonkers with ctrl-c and we start forking merrily. - print '\nCtrl-C detected, goodbye.' - os.kill(0,9) - except: - if self.litConfig.debug: - raise - result = Test.UNRESOLVED - output = 'Exception during script execution:\n' - output += traceback.format_exc() - output += '\n' - elapsed = time.time() - startTime - - test.setResult(result, output, elapsed) - self.display.update(test) - -def dirContainsTestSuite(path): - cfgpath = os.path.join(path, gSiteConfigName) - if os.path.exists(cfgpath): - return cfgpath - cfgpath = os.path.join(path, gConfigName) - if os.path.exists(cfgpath): - return cfgpath - -def getTestSuite(item, litConfig, cache): - """getTestSuite(item, litConfig, cache) -> (suite, relative_path) - - Find the test suite containing @arg item. - - @retval (None, ...) - Indicates no test suite contains @arg item. - @retval (suite, relative_path) - The suite that @arg item is in, and its - relative path inside that suite. - """ - def search1(path): - # Check for a site config or a lit config. - cfgpath = dirContainsTestSuite(path) - - # If we didn't find a config file, keep looking. - if not cfgpath: - parent,base = os.path.split(path) - if parent == path: - return (None, ()) - - ts, relative = search(parent) - return (ts, relative + (base,)) - - # We found a config file, load it. - if litConfig.debug: - litConfig.note('loading suite config %r' % cfgpath) - - cfg = TestingConfig.frompath(cfgpath, None, litConfig, mustExist = True) - source_root = os.path.realpath(cfg.test_source_root or path) - exec_root = os.path.realpath(cfg.test_exec_root or path) - return Test.TestSuite(cfg.name, source_root, exec_root, cfg), () - - def search(path): - # Check for an already instantiated test suite. - res = cache.get(path) - if res is None: - cache[path] = res = search1(path) - return res - - # Canonicalize the path. - item = os.path.realpath(item) - - # Skip files and virtual components. - components = [] - while not os.path.isdir(item): - parent,base = os.path.split(item) - if parent == item: - return (None, ()) - components.append(base) - item = parent - components.reverse() - - ts, relative = search(item) - return ts, tuple(relative + tuple(components)) - -def getLocalConfig(ts, path_in_suite, litConfig, cache): - def search1(path_in_suite): - # Get the parent config. - if not path_in_suite: - parent = ts.config - else: - parent = search(path_in_suite[:-1]) - - # Load the local configuration. - source_path = ts.getSourcePath(path_in_suite) - cfgpath = os.path.join(source_path, kLocalConfigName) - if litConfig.debug: - litConfig.note('loading local config %r' % cfgpath) - return TestingConfig.frompath(cfgpath, parent, litConfig, - mustExist = False, - config = parent.clone(cfgpath)) - - def search(path_in_suite): - key = (ts, path_in_suite) - res = cache.get(key) - if res is None: - cache[key] = res = search1(path_in_suite) - return res - - return search(path_in_suite) - -def getTests(path, litConfig, testSuiteCache, localConfigCache): - # Find the test suite for this input and its relative path. - ts,path_in_suite = getTestSuite(path, litConfig, testSuiteCache) - if ts is None: - litConfig.warning('unable to find test suite for %r' % path) - return (),() - - if litConfig.debug: - litConfig.note('resolved input %r to %r::%r' % (path, ts.name, - path_in_suite)) - - return ts, getTestsInSuite(ts, path_in_suite, litConfig, - testSuiteCache, localConfigCache) - -def getTestsInSuite(ts, path_in_suite, litConfig, - testSuiteCache, localConfigCache): - # Check that the source path exists (errors here are reported by the - # caller). - source_path = ts.getSourcePath(path_in_suite) - if not os.path.exists(source_path): - return - - # Check if the user named a test directly. - if not os.path.isdir(source_path): - lc = getLocalConfig(ts, path_in_suite[:-1], litConfig, localConfigCache) - yield Test.Test(ts, path_in_suite, lc) - return - - # Otherwise we have a directory to search for tests, start by getting the - # local configuration. - lc = getLocalConfig(ts, path_in_suite, litConfig, localConfigCache) - - # Search for tests. - if lc.test_format is not None: - for res in lc.test_format.getTestsInDirectory(ts, path_in_suite, - litConfig, lc): - yield res - - # Search subdirectories. - for filename in os.listdir(source_path): - # FIXME: This doesn't belong here? - if filename in ('Output', '.svn') or filename in lc.excludes: - continue - - # Ignore non-directories. - file_sourcepath = os.path.join(source_path, filename) - if not os.path.isdir(file_sourcepath): - continue - - # Check for nested test suites, first in the execpath in case there is a - # site configuration and then in the source path. - file_execpath = ts.getExecPath(path_in_suite + (filename,)) - if dirContainsTestSuite(file_execpath): - sub_ts, subiter = getTests(file_execpath, litConfig, - testSuiteCache, localConfigCache) - elif dirContainsTestSuite(file_sourcepath): - sub_ts, subiter = getTests(file_sourcepath, litConfig, - testSuiteCache, localConfigCache) - else: - # Otherwise, continue loading from inside this test suite. - subiter = getTestsInSuite(ts, path_in_suite + (filename,), - litConfig, testSuiteCache, - localConfigCache) - sub_ts = None - - N = 0 - for res in subiter: - N += 1 - yield res - if sub_ts and not N: - litConfig.warning('test suite %r contained no tests' % sub_ts.name) - -def runTests(numThreads, litConfig, provider, display): - # If only using one testing thread, don't use threads at all; this lets us - # profile, among other things. - if numThreads == 1: - t = Tester(litConfig, provider, display) - t.run() - return - - # Otherwise spin up the testing threads and wait for them to finish. - testers = [Tester(litConfig, provider, display) - for i in range(numThreads)] - for t in testers: - t.start() - try: - for t in testers: - t.join() - except KeyboardInterrupt: - sys.exit(2) - -def load_test_suite(inputs): - import unittest - - # Create the global config object. - litConfig = LitConfig.LitConfig(progname = 'lit', - path = [], - quiet = False, - useValgrind = False, - valgrindLeakCheck = False, - valgrindArgs = [], - useTclAsSh = False, - noExecute = False, - debug = False, - isWindows = (platform.system()=='Windows'), - params = {}) - - # Load the tests from the inputs. - tests = [] - testSuiteCache = {} - localConfigCache = {} - for input in inputs: - prev = len(tests) - tests.extend(getTests(input, litConfig, - testSuiteCache, localConfigCache)[1]) - if prev == len(tests): - litConfig.warning('input %r contained no tests' % input) - - # If there were any errors during test discovery, exit now. - if litConfig.numErrors: - print >>sys.stderr, '%d errors, exiting.' % litConfig.numErrors - sys.exit(2) - - # Return a unittest test suite which just runs the tests in order. - def get_test_fn(test): - return unittest.FunctionTestCase( - lambda: test.config.test_format.execute( - test, litConfig), - description = test.getFullName()) - - from LitTestCase import LitTestCase - return unittest.TestSuite([LitTestCase(test, litConfig) for test in tests]) - -def main(builtinParameters = {}): # Bump the GIL check interval, its more important to get any one thread to a - # blocking operation (hopefully exec) than to try and unblock other threads. - # - # FIXME: This is a hack. - import sys - sys.setcheckinterval(1000) - - global options - from optparse import OptionParser, OptionGroup - parser = OptionParser("usage: %prog [options] {file-or-path}") - - parser.add_option("-j", "--threads", dest="numThreads", metavar="N", - help="Number of testing threads", - type=int, action="store", default=None) - parser.add_option("", "--config-prefix", dest="configPrefix", - metavar="NAME", help="Prefix for 'lit' config files", - action="store", default=None) - parser.add_option("", "--param", dest="userParameters", - metavar="NAME=VAL", - help="Add 'NAME' = 'VAL' to the user defined parameters", - type=str, action="append", default=[]) - - group = OptionGroup(parser, "Output Format") - # FIXME: I find these names very confusing, although I like the - # functionality. - group.add_option("-q", "--quiet", dest="quiet", - help="Suppress no error output", - action="store_true", default=False) - group.add_option("-s", "--succinct", dest="succinct", - help="Reduce amount of output", - action="store_true", default=False) - group.add_option("-v", "--verbose", dest="showOutput", - help="Show all test output", - action="store_true", default=False) - group.add_option("", "--no-progress-bar", dest="useProgressBar", - help="Do not use curses based progress bar", - action="store_false", default=True) - parser.add_option_group(group) - - group = OptionGroup(parser, "Test Execution") - group.add_option("", "--path", dest="path", - help="Additional paths to add to testing environment", - action="append", type=str, default=[]) - group.add_option("", "--vg", dest="useValgrind", - help="Run tests under valgrind", - action="store_true", default=False) - group.add_option("", "--vg-leak", dest="valgrindLeakCheck", - help="Check for memory leaks under valgrind", - action="store_true", default=False) - group.add_option("", "--vg-arg", dest="valgrindArgs", metavar="ARG", - help="Specify an extra argument for valgrind", - type=str, action="append", default=[]) - group.add_option("", "--time-tests", dest="timeTests", - help="Track elapsed wall time for each test", - action="store_true", default=False) - group.add_option("", "--no-execute", dest="noExecute", - help="Don't execute any tests (assume PASS)", - action="store_true", default=False) - parser.add_option_group(group) - - group = OptionGroup(parser, "Test Selection") - group.add_option("", "--max-tests", dest="maxTests", metavar="N", - help="Maximum number of tests to run", - action="store", type=int, default=None) - group.add_option("", "--max-time", dest="maxTime", metavar="N", - help="Maximum time to spend testing (in seconds)", - action="store", type=float, default=None) - group.add_option("", "--shuffle", dest="shuffle", - help="Run tests in random order", - action="store_true", default=False) - parser.add_option_group(group) - - group = OptionGroup(parser, "Debug and Experimental Options") - group.add_option("", "--debug", dest="debug", - help="Enable debugging (for 'lit' development)", - action="store_true", default=False) - group.add_option("", "--show-suites", dest="showSuites", - help="Show discovered test suites", - action="store_true", default=False) - group.add_option("", "--no-tcl-as-sh", dest="useTclAsSh", - help="Don't run Tcl scripts using 'sh'", - action="store_false", default=True) - group.add_option("", "--repeat", dest="repeatTests", metavar="N", - help="Repeat tests N times (for timing)", - action="store", default=None, type=int) - parser.add_option_group(group) - - (opts, args) = parser.parse_args() - - if not args: - parser.error('No inputs specified') - - if opts.configPrefix is not None: - global gConfigName, gSiteConfigName - gConfigName = '%s.cfg' % opts.configPrefix - gSiteConfigName = '%s.site.cfg' % opts.configPrefix - - if opts.numThreads is None: -# Python <2.5 has a race condition causing lit to always fail with numThreads>1 -# http://bugs.python.org/issue1731717 -# I haven't seen this bug occur with 2.5.2 and later, so only enable multiple -# threads by default there. - if sys.hexversion >= 0x2050200: - opts.numThreads = Util.detectCPUs() - else: - opts.numThreads = 1 - - inputs = args - - # Create the user defined parameters. - userParams = dict(builtinParameters) - for entry in opts.userParameters: - if '=' not in entry: - name,val = entry,'' - else: - name,val = entry.split('=', 1) - userParams[name] = val - - # Create the global config object. - litConfig = LitConfig.LitConfig(progname = os.path.basename(sys.argv[0]), - path = opts.path, - quiet = opts.quiet, - useValgrind = opts.useValgrind, - valgrindLeakCheck = opts.valgrindLeakCheck, - valgrindArgs = opts.valgrindArgs, - useTclAsSh = opts.useTclAsSh, - noExecute = opts.noExecute, - debug = opts.debug, - isWindows = (platform.system()=='Windows'), - params = userParams) - - # Expand '@...' form in inputs. - actual_inputs = [] - for input in inputs: - if os.path.exists(input) or not input.startswith('@'): - actual_inputs.append(input) - else: - f = open(input[1:]) - try: - for ln in f: - ln = ln.strip() - if ln: - actual_inputs.append(ln) - finally: - f.close() - - - # Load the tests from the inputs. - tests = [] - testSuiteCache = {} - localConfigCache = {} - for input in actual_inputs: - prev = len(tests) - tests.extend(getTests(input, litConfig, - testSuiteCache, localConfigCache)[1]) - if prev == len(tests): - litConfig.warning('input %r contained no tests' % input) - - # If there were any errors during test discovery, exit now. - if litConfig.numErrors: - print >>sys.stderr, '%d errors, exiting.' % litConfig.numErrors - sys.exit(2) - - if opts.showSuites: - suitesAndTests = dict([(ts,[]) - for ts,_ in testSuiteCache.values() - if ts]) - for t in tests: - suitesAndTests[t.suite].append(t) - - print '-- Test Suites --' - suitesAndTests = suitesAndTests.items() - suitesAndTests.sort(key = lambda (ts,_): ts.name) - for ts,ts_tests in suitesAndTests: - print ' %s - %d tests' %(ts.name, len(ts_tests)) - print ' Source Root: %s' % ts.source_root - print ' Exec Root : %s' % ts.exec_root - - # Select and order the tests. - numTotalTests = len(tests) - if opts.shuffle: - random.shuffle(tests) - else: - tests.sort(key = lambda t: t.getFullName()) - if opts.maxTests is not None: - tests = tests[:opts.maxTests] - - extra = '' - if len(tests) != numTotalTests: - extra = ' of %d' % numTotalTests - header = '-- Testing: %d%s tests, %d threads --'%(len(tests),extra, - opts.numThreads) - - if opts.repeatTests: - tests = [t.copyWithIndex(i) - for t in tests - for i in range(opts.repeatTests)] - - progressBar = None - if not opts.quiet: - if opts.succinct and opts.useProgressBar: - try: - tc = ProgressBar.TerminalController() - progressBar = ProgressBar.ProgressBar(tc, header) - except ValueError: - print header - progressBar = ProgressBar.SimpleProgressBar('Testing: ') - else: - print header - - # Don't create more threads than tests. - opts.numThreads = min(len(tests), opts.numThreads) - - startTime = time.time() - display = TestingProgressDisplay(opts, len(tests), progressBar) - provider = TestProvider(tests, opts.maxTime) - runTests(opts.numThreads, litConfig, provider, display) - display.finish() - - if not opts.quiet: - print 'Testing Time: %.2fs'%(time.time() - startTime) - - # Update results for any tests which weren't run. - for t in tests: - if t.result is None: - t.setResult(Test.UNRESOLVED, '', 0.0) - - # List test results organized by kind. - hasFailures = False - byCode = {} - for t in tests: - if t.result not in byCode: - byCode[t.result] = [] - byCode[t.result].append(t) - if t.result.isFailure: - hasFailures = True - - # FIXME: Show unresolved and (optionally) unsupported tests. - for title,code in (('Unexpected Passing Tests', Test.XPASS), - ('Failing Tests', Test.FAIL)): - elts = byCode.get(code) - if not elts: - continue - print '*'*20 - print '%s (%d):' % (title, len(elts)) - for t in elts: - print ' %s' % t.getFullName() - print - - if opts.timeTests: - # Collate, in case we repeated tests. - times = {} - for t in tests: - key = t.getFullName() - times[key] = times.get(key, 0.) + t.elapsed - - byTime = list(times.items()) - byTime.sort(key = lambda (name,elapsed): elapsed) - if byTime: - Util.printHistogram(byTime, title='Tests') - - for name,code in (('Expected Passes ', Test.PASS), - ('Expected Failures ', Test.XFAIL), - ('Unsupported Tests ', Test.UNSUPPORTED), - ('Unresolved Tests ', Test.UNRESOLVED), - ('Unexpected Passes ', Test.XPASS), - ('Unexpected Failures', Test.FAIL),): - if opts.quiet and not code.isFailure: - continue - N = len(byCode.get(code,[])) - if N: - print ' %s: %d' % (name,N) - - # If we encountered any additional errors, exit abnormally. - if litConfig.numErrors: - print >>sys.stderr, '\n%d error(s), exiting.' % litConfig.numErrors - sys.exit(2) - - # Warn about warnings. - if litConfig.numWarnings: - print >>sys.stderr, '\n%d warning(s) in tests.' % litConfig.numWarnings - - if hasFailures: - sys.exit(1) - sys.exit(0) - -if __name__=='__main__': - main() Copied: llvm/trunk/utils/lit/lit/main.py (from r113919, llvm/trunk/utils/lit/lit/lit.py) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/main.py?p2=llvm/trunk/utils/lit/lit/main.py&p1=llvm/trunk/utils/lit/lit/lit.py&r1=113919&r2=113922&rev=113922&view=diff ============================================================================== (empty) From daniel at zuster.org Tue Sep 14 22:52:38 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 15 Sep 2010 03:52:38 -0000 Subject: [llvm-commits] [llvm] r113923 - in /llvm/trunk/utils/lit/lit: LitConfig.py LitFormats.py Message-ID: <20100915035238.47D452A6C12D@llvm.org> Author: ddunbar Date: Tue Sep 14 22:52:38 2010 New Revision: 113923 URL: http://llvm.org/viewvc/llvm-project?rev=113923&view=rev Log: lit: Expose FileBasedTest object and Test module via 'lit' object that gets exposed to config files. Modified: llvm/trunk/utils/lit/lit/LitConfig.py llvm/trunk/utils/lit/lit/LitFormats.py Modified: llvm/trunk/utils/lit/lit/LitConfig.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/LitConfig.py?rev=113923&r1=113922&r2=113923&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/LitConfig.py (original) +++ llvm/trunk/utils/lit/lit/LitConfig.py Tue Sep 14 22:52:38 2010 @@ -8,6 +8,9 @@ easily. """ + # Provide access to Test module. + import Test + # Provide access to built-in formats. import LitFormats as formats Modified: llvm/trunk/utils/lit/lit/LitFormats.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/LitFormats.py?rev=113923&r1=113922&r2=113923&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/LitFormats.py (original) +++ llvm/trunk/utils/lit/lit/LitFormats.py Tue Sep 14 22:52:38 2010 @@ -1,2 +1,3 @@ +from TestFormats import FileBasedTest from TestFormats import GoogleTest, ShTest, TclTest from TestFormats import SyntaxCheckTest, OneCommandPerFileTest From bigcheesegs at gmail.com Tue Sep 14 22:58:25 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 15 Sep 2010 03:58:25 -0000 Subject: [llvm-commits] [llvm] r113926 - /llvm/trunk/test/Scripts/coff-dump.py Message-ID: <20100915035825.1473E2A6C12C@llvm.org> Author: mspencer Date: Tue Sep 14 22:58:24 2010 New Revision: 113926 URL: http://llvm.org/viewvc/llvm-project?rev=113926&view=rev Log: Cleanup coff-dump.py Modified: llvm/trunk/test/Scripts/coff-dump.py Modified: llvm/trunk/test/Scripts/coff-dump.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/coff-dump.py?rev=113926&r1=113925&r2=113926&view=diff ============================================================================== --- llvm/trunk/test/Scripts/coff-dump.py (original) +++ llvm/trunk/test/Scripts/coff-dump.py Tue Sep 14 22:58:24 2010 @@ -17,14 +17,14 @@ def secname(value): if value[0] == '/': - return string_table_entry (value [1:].rstrip('\0')) + return string_table_entry(value[1:].rstrip('\0')) else: return '%s' def symname(value): parts = struct.unpack("<2L", value) - if parts [0] == 0: - return string_table_entry (parts [1]) + if parts[0] == 0: + return string_table_entry(parts[1]) else: return '%s' @@ -261,16 +261,16 @@ if char == '\n': NewLine = True - sys.stdout.write (output) + sys.stdout.write(output) def read(format): - return struct.unpack (format, Input.read(struct.calcsize(format))) + return struct.unpack(format, Input.read(struct.calcsize(format))) -def read_cstr (): +def read_cstr(): output = "" while True: - char = Input.read (1) - if len (char) == 0: + char = Input.read(1) + if len(char) == 0: raise RuntimeError ("EOF while reading cstr") if char == '\0': break @@ -278,14 +278,14 @@ return output def push_pos(seek_to = None): - Stack [0:0] = [Input.tell ()] + Stack [0:0] = [Input.tell()] if seek_to: - Input.seek (seek_to) + Input.seek(seek_to) def pop_pos(): - assert(len (Stack) > 0) - Input.seek (Stack [0]) - del Stack [0] + assert(len(Stack) > 0) + Input.seek(Stack[0]) + del Stack[0] def print_binary_data(size): value = "" @@ -299,14 +299,14 @@ value += data bytes = "" text = "" - for index in xrange (16): - if index < len (data): + for index in xrange(16): + if index < len(data): if index == 8: bytes += "- " - ch = ord (data [index]) + ch = ord(data[index]) bytes += "%02X " % ch if ch >= 0x20 and ch <= 0x7F: - text += data [index] + text += data[index] else: text += "." else: @@ -314,47 +314,47 @@ bytes += " " bytes += " " - write ("%s|%s|\n" % (bytes, text)) + write("%s|%s|\n" % (bytes, text)) return value -idlit = re.compile ("[a-zA-Z][a-zA-Z0-9_-]*") -numlit = re.compile ("[0-9]+") +idlit = re.compile("[a-zA-Z][a-zA-Z0-9_-]*") +numlit = re.compile("[0-9]+") def read_value(expr): - input = iter (expr.split ()) + input = iter(expr.split()) def eval(): - token = input.next () + token = input.next() if expr == 'cstr': - return read_cstr () + return read_cstr() if expr == 'true': return True if expr == 'false': return False - if len (token) > 1 and token [0] in ('=', '@', '<', '!', '>'): + if len(token) > 1 and token[0] in ('=', '@', '<', '!', '>'): val = read(expr) - assert (len (val) == 1) - return val [0] + assert(len(val) == 1) + return val[0] if token == '+': - return eval () + eval () + return eval() + eval() if token == '-': - return eval () - eval () + return eval() - eval() if token == '*': - return eval () * eval () + return eval() * eval() if token == '/': - return eval () / eval () + return eval() / eval() - if idlit.match (token): - return Fields [token] - if numlit.match (token): - return int (token) + if idlit.match(token): + return Fields[token] + if numlit.match(token): + return int(token) - raise RuntimeError ("unexpected token %s" % repr(token)) + raise RuntimeError("unexpected token %s" % repr(token)) value = eval () @@ -365,88 +365,88 @@ raise RuntimeError("unexpected input at end of expression") def write_value(format,value): - format_type = type (format) + format_type = type(format) if format_type is types.StringType: - write (format%value) + write(format % value) elif format_type is types.FunctionType: - write_value (format (value), value) + write_value(format(value), value) elif format_type is types.TupleType: - Fields ['this'] = value - handle_element (format) + Fields['this'] = value + handle_element(format) else: raise RuntimeError("unexpected type: %s" % repr(format_type)) def handle_scalar(entry): - iformat = entry [1] - oformat = entry [2] + iformat = entry[1] + oformat = entry[2] - value = read_value (iformat) + value = read_value(iformat) - write_value (oformat, value) + write_value(oformat, value) return value def handle_enum(entry): - iformat = entry [1] - oformat = entry [2] - definitions = entry [3] - - value = read_value (iformat) - - if type (definitions) is types.TupleType: - selector = read_value (definitions [0]) - definitions = definitions [1] [selector] + iformat = entry[1] + oformat = entry[2] + definitions = entry[3] + + value = read_value(iformat) + + if type(definitions) is types.TupleType: + selector = read_value(definitions[0]) + definitions = definitions[1][selector] if value in definitions: description = definitions[value] else: description = "unknown" - write ("%s (" % description) - write_value (oformat, value) - write (")") + write("%s (" % description) + write_value(oformat, value) + write(")") return value def handle_flags(entry): - iformat = entry [1] - oformat = entry [2] - definitions = entry [3] + iformat = entry[1] + oformat = entry[2] + definitions = entry[3] - value = read_value (iformat) + value = read_value(iformat) - write_value (oformat, value) + write_value(oformat, value) - indent () + indent() for entry in definitions: - mask = entry [0] - name = entry [1] + mask = entry[0] + name = entry[1] if len (entry) == 3: - map = entry [2] + map = entry[2] selection = value & mask if selection in map: write("\n%s" % map[selection]) else: write("\n%s <%d>" % (name, selection)) - elif len (entry) == 2: + elif len(entry) == 2: if value & mask != 0: write("\n%s" % name) - dedent () + dedent() return value def handle_struct(entry): global Fields - members = entry [1] + members = entry[1] newFields = {} - write ("{\n"); - indent () + write("{\n"); + indent() for member in members: - name = member [0] - type = member [1] + name = member[0] + type = member[1] write("%s = "%name.ljust(24)) @@ -454,90 +454,90 @@ write("\n") - Fields [name] = value - newFields [name] = value + Fields[name] = value + newFields[name] = value - dedent () - write ("}") + dedent() + write("}") return newFields def handle_array(entry): - length = entry [1] - element = entry [2] + length = entry[1] + element = entry[2] newItems = [] - write ("[\n") - indent () + write("[\n") + indent() - value = read_value (length) + value = read_value(length) - for index in xrange (value): - write ("%d = "%index) + for index in xrange(value): + write("%d = "%index) value = handle_element(element) - write ("\n") - newItems.append (value) + write("\n") + newItems.append(value) - dedent () - write ("]") + dedent() + write("]") return newItems def handle_byte_array(entry): - length = entry [1] - element = entry [2] + length = entry[1] + element = entry[2] newItems = [] - write ("[\n") - indent () + write("[\n") + indent() - value = read_value (length) - end_of_array = Input.tell () + value + value = read_value(length) + end_of_array = Input.tell() + value index = 0 - while Input.tell () < end_of_array: - write ("%d = "%index) + while Input.tell() < end_of_array: + write("%d = "%index) value = handle_element(element) - write ("\n") - newItems.append (value) + write("\n") + newItems.append(value) index += 1 - dedent () - write ("]") + dedent() + write("]") return newItems def handle_ptr(entry): offset = entry[1] - element = entry [2] + element = entry[2] value = None - offset = read_value (offset) + offset = read_value(offset) if offset != 0: - push_pos (offset) + push_pos(offset) - value = handle_element (element) + value = handle_element(element) - pop_pos () + pop_pos() else: - write ("None") + write("None") return value def handle_blob(entry): - length = entry [1] + length = entry[1] - write ("\n") - indent () + write("\n") + indent() - value = print_binary_data (read_value (length)) + value = print_binary_data(read_value(length)) - dedent () + dedent() return value @@ -553,14 +553,14 @@ 'byte-array': handle_byte_array, } - if not entry [0] in handlers: + if not entry[0] in handlers: raise RuntimeError ("unexpected type '%s'" % str (entry[0])) - return handlers [entry [0]] (entry) + return handlers[entry[0]](entry) -Input = open (sys.argv [1], "rb") +Input = open (sys.argv[1], "rb") try: - handle_element (file) + handle_element(file) finally: - Input.close () + Input.close() Input = None From bigcheesegs at gmail.com Tue Sep 14 22:58:40 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 15 Sep 2010 03:58:40 -0000 Subject: [llvm-commits] [llvm] r113927 - /llvm/trunk/test/Scripts/coff-dump.py Message-ID: <20100915035840.0F78D2A6C12C@llvm.org> Author: mspencer Date: Tue Sep 14 22:58:39 2010 New Revision: 113927 URL: http://llvm.org/viewvc/llvm-project?rev=113927&view=rev Log: Tabs to spaces Modified: llvm/trunk/test/Scripts/coff-dump.py Modified: llvm/trunk/test/Scripts/coff-dump.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/coff-dump.py?rev=113927&r1=113926&r2=113927&view=diff ============================================================================== --- llvm/trunk/test/Scripts/coff-dump.py (original) +++ llvm/trunk/test/Scripts/coff-dump.py Tue Sep 14 22:58:39 2010 @@ -13,216 +13,216 @@ # def string_table_entry (offset): - return ('ptr', '+ + PointerToSymbolTable * NumberOfSymbols 18 %s' % offset, ('scalar', 'cstr', '%s')) + return ('ptr', '+ + PointerToSymbolTable * NumberOfSymbols 18 %s' % offset, ('scalar', 'cstr', '%s')) def secname(value): - if value[0] == '/': - return string_table_entry(value[1:].rstrip('\0')) - else: - return '%s' + if value[0] == '/': + return string_table_entry(value[1:].rstrip('\0')) + else: + return '%s' def symname(value): - parts = struct.unpack("<2L", value) - if parts[0] == 0: - return string_table_entry(parts[1]) - else: - return '%s' + parts = struct.unpack("<2L", value) + if parts[0] == 0: + return string_table_entry(parts[1]) + else: + return '%s' file = ('struct', [ - ('MachineType', ('enum', ' 0) - Input.seek(Stack[0]) - del Stack[0] + assert(len(Stack) > 0) + Input.seek(Stack[0]) + del Stack[0] def print_binary_data(size): - value = "" - while size > 0: - if size >= 16: - data = Input.read(16) - size -= 16 - else: - data = Input.read(size) - size = 0 - value += data - bytes = "" - text = "" - for index in xrange(16): - if index < len(data): - if index == 8: - bytes += "- " - ch = ord(data[index]) - bytes += "%02X " % ch - if ch >= 0x20 and ch <= 0x7F: - text += data[index] - else: - text += "." - else: - if index == 8: - bytes += " " - bytes += " " - - write("%s|%s|\n" % (bytes, text)) - return value + value = "" + while size > 0: + if size >= 16: + data = Input.read(16) + size -= 16 + else: + data = Input.read(size) + size = 0 + value += data + bytes = "" + text = "" + for index in xrange(16): + if index < len(data): + if index == 8: + bytes += "- " + ch = ord(data[index]) + bytes += "%02X " % ch + if ch >= 0x20 and ch <= 0x7F: + text += data[index] + else: + text += "." + else: + if index == 8: + bytes += " " + bytes += " " + + write("%s|%s|\n" % (bytes, text)) + return value idlit = re.compile("[a-zA-Z][a-zA-Z0-9_-]*") numlit = re.compile("[0-9]+") def read_value(expr): - input = iter(expr.split()) - - def eval(): - - token = input.next() - - if expr == 'cstr': - return read_cstr() - if expr == 'true': - return True - if expr == 'false': - return False - - if len(token) > 1 and token[0] in ('=', '@', '<', '!', '>'): - val = read(expr) - assert(len(val) == 1) - return val[0] - - if token == '+': - return eval() + eval() - if token == '-': - return eval() - eval() - if token == '*': - return eval() * eval() - if token == '/': - return eval() / eval() - - if idlit.match(token): - return Fields[token] - if numlit.match(token): - return int(token) - - raise RuntimeError("unexpected token %s" % repr(token)) - - value = eval () - - try: - input.next () - except StopIteration: - return value - raise RuntimeError("unexpected input at end of expression") + input = iter(expr.split()) + + def eval(): + + token = input.next() + + if expr == 'cstr': + return read_cstr() + if expr == 'true': + return True + if expr == 'false': + return False + + if len(token) > 1 and token[0] in ('=', '@', '<', '!', '>'): + val = read(expr) + assert(len(val) == 1) + return val[0] + + if token == '+': + return eval() + eval() + if token == '-': + return eval() - eval() + if token == '*': + return eval() * eval() + if token == '/': + return eval() / eval() + + if idlit.match(token): + return Fields[token] + if numlit.match(token): + return int(token) + + raise RuntimeError("unexpected token %s" % repr(token)) + + value = eval () + + try: + input.next () + except StopIteration: + return value + raise RuntimeError("unexpected input at end of expression") def write_value(format,value): - format_type = type(format) - if format_type is types.StringType: - write(format % value) - elif format_type is types.FunctionType: - write_value(format(value), value) - elif format_type is types.TupleType: - Fields['this'] = value - handle_element(format) - else: - raise RuntimeError("unexpected type: %s" % repr(format_type)) + format_type = type(format) + if format_type is types.StringType: + write(format % value) + elif format_type is types.FunctionType: + write_value(format(value), value) + elif format_type is types.TupleType: + Fields['this'] = value + handle_element(format) + else: + raise RuntimeError("unexpected type: %s" % repr(format_type)) def handle_scalar(entry): - iformat = entry[1] - oformat = entry[2] - - value = read_value(iformat) - - write_value(oformat, value) - - return value + iformat = entry[1] + oformat = entry[2] + + value = read_value(iformat) + + write_value(oformat, value) + + return value def handle_enum(entry): - iformat = entry[1] - oformat = entry[2] - definitions = entry[3] - - value = read_value(iformat) - - if type(definitions) is types.TupleType: - selector = read_value(definitions[0]) - definitions = definitions[1][selector] - - if value in definitions: - description = definitions[value] - else: - description = "unknown" - - write("%s (" % description) - write_value(oformat, value) - write(")") - - return value + iformat = entry[1] + oformat = entry[2] + definitions = entry[3] + + value = read_value(iformat) + + if type(definitions) is types.TupleType: + selector = read_value(definitions[0]) + definitions = definitions[1][selector] + + if value in definitions: + description = definitions[value] + else: + description = "unknown" + + write("%s (" % description) + write_value(oformat, value) + write(")") + + return value def handle_flags(entry): - iformat = entry[1] - oformat = entry[2] - definitions = entry[3] - - value = read_value(iformat) - - write_value(oformat, value) - - indent() - for entry in definitions: - mask = entry[0] - name = entry[1] - if len (entry) == 3: - map = entry[2] - selection = value & mask - if selection in map: - write("\n%s" % map[selection]) - else: - write("\n%s <%d>" % (name, selection)) - elif len(entry) == 2: - if value & mask != 0: - write("\n%s" % name) - dedent() - - return value + iformat = entry[1] + oformat = entry[2] + definitions = entry[3] + + value = read_value(iformat) + + write_value(oformat, value) + + indent() + for entry in definitions: + mask = entry[0] + name = entry[1] + if len (entry) == 3: + map = entry[2] + selection = value & mask + if selection in map: + write("\n%s" % map[selection]) + else: + write("\n%s <%d>" % (name, selection)) + elif len(entry) == 2: + if value & mask != 0: + write("\n%s" % name) + dedent() + + return value def handle_struct(entry): - global Fields - members = entry[1] - - newFields = {} - - write("{\n"); - indent() - - for member in members: - name = member[0] - type = member[1] - - write("%s = "%name.ljust(24)) - - value = handle_element(type) - - write("\n") - - Fields[name] = value - newFields[name] = value - - dedent() - write("}") - - return newFields + global Fields + members = entry[1] + + newFields = {} + + write("{\n"); + indent() + + for member in members: + name = member[0] + type = member[1] + + write("%s = "%name.ljust(24)) + + value = handle_element(type) + + write("\n") + + Fields[name] = value + newFields[name] = value + + dedent() + write("}") + + return newFields def handle_array(entry): - length = entry[1] - element = entry[2] - - newItems = [] - - write("[\n") - indent() - - value = read_value(length) - - for index in xrange(value): - write("%d = "%index) - value = handle_element(element) - write("\n") - newItems.append(value) - - dedent() - write("]") - - return newItems + length = entry[1] + element = entry[2] + + newItems = [] + + write("[\n") + indent() + + value = read_value(length) + + for index in xrange(value): + write("%d = "%index) + value = handle_element(element) + write("\n") + newItems.append(value) + + dedent() + write("]") + + return newItems def handle_byte_array(entry): - length = entry[1] - element = entry[2] - - newItems = [] - - write("[\n") - indent() - - value = read_value(length) - end_of_array = Input.tell() + value - - index = 0 - while Input.tell() < end_of_array: - write("%d = "%index) - value = handle_element(element) - write("\n") - newItems.append(value) - index += 1 - - dedent() - write("]") - - return newItems + length = entry[1] + element = entry[2] + + newItems = [] + + write("[\n") + indent() + + value = read_value(length) + end_of_array = Input.tell() + value + + index = 0 + while Input.tell() < end_of_array: + write("%d = "%index) + value = handle_element(element) + write("\n") + newItems.append(value) + index += 1 + + dedent() + write("]") + + return newItems def handle_ptr(entry): - offset = entry[1] - element = entry[2] - - value = None - offset = read_value(offset) - - if offset != 0: - - push_pos(offset) - - value = handle_element(element) - - pop_pos() - - else: - write("None") - - return value + offset = entry[1] + element = entry[2] + + value = None + offset = read_value(offset) + + if offset != 0: + + push_pos(offset) + + value = handle_element(element) + + pop_pos() + + else: + write("None") + + return value def handle_blob(entry): - length = entry[1] - - write("\n") - indent() - - value = print_binary_data(read_value(length)) - - dedent() - - return value + length = entry[1] + + write("\n") + indent() + + value = print_binary_data(read_value(length)) + + dedent() + + return value def handle_element(entry): - handlers = { - 'struct': handle_struct, - 'scalar': handle_scalar, - 'enum': handle_enum, - 'flags': handle_flags, - 'ptr': handle_ptr, - 'blob': handle_blob, - 'array': handle_array, - 'byte-array': handle_byte_array, - } - - if not entry[0] in handlers: - raise RuntimeError ("unexpected type '%s'" % str (entry[0])) - - return handlers[entry[0]](entry) + handlers = { + 'struct': handle_struct, + 'scalar': handle_scalar, + 'enum': handle_enum, + 'flags': handle_flags, + 'ptr': handle_ptr, + 'blob': handle_blob, + 'array': handle_array, + 'byte-array': handle_byte_array, + } + + if not entry[0] in handlers: + raise RuntimeError ("unexpected type '%s'" % str (entry[0])) + + return handlers[entry[0]](entry) Input = open (sys.argv[1], "rb") try: - handle_element(file) + handle_element(file) finally: - Input.close() - Input = None + Input.close() + Input = None From bigcheesegs at gmail.com Tue Sep 14 22:58:52 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 15 Sep 2010 03:58:52 -0000 Subject: [llvm-commits] [llvm] r113928 - in /llvm/trunk/test: MC/COFF/basic-coff.ll MC/COFF/symbol-fragment-offset.ll Scripts/coff-dump.py Message-ID: <20100915035852.267772A6C12C@llvm.org> Author: mspencer Date: Tue Sep 14 22:58:51 2010 New Revision: 113928 URL: http://llvm.org/viewvc/llvm-project?rev=113928&view=rev Log: test: Fix coff-dump section array indicies to 1 based to match file format. Modified: llvm/trunk/test/MC/COFF/basic-coff.ll llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll llvm/trunk/test/Scripts/coff-dump.py Modified: llvm/trunk/test/MC/COFF/basic-coff.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/COFF/basic-coff.ll?rev=113928&r1=113927&r2=113928&view=diff ============================================================================== --- llvm/trunk/test/MC/COFF/basic-coff.ll (original) +++ llvm/trunk/test/MC/COFF/basic-coff.ll Tue Sep 14 22:58:51 2010 @@ -24,7 +24,7 @@ ; CHECK: SizeOfOptionalHeader = 0 ; CHECK: Characteristics = 0x0 ; CHECK: Sections = [ -; CHECK: 0 = { +; CHECK: 1 = { ; CHECK: Name = .text ; CHECK: VirtualSize = 0 ; CHECK: VirtualAddress = 0 @@ -57,7 +57,7 @@ ; CHECK: } ; CHECK: ] ; CHECK: } -; CHECK: 1 = { +; CHECK: 2 = { ; CHECK: Name = .data ; CHECK: VirtualSize = 0 ; CHECK: VirtualAddress = 0 Modified: llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll?rev=113928&r1=113927&r2=113928&view=diff ============================================================================== --- llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll (original) +++ llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll Tue Sep 14 22:58:51 2010 @@ -28,7 +28,7 @@ ; CHECK: SizeOfOptionalHeader = 0 ; CHECK: Characteristics = 0x0 ; CHECK: Sections = [ -; CHECK: 0 = { +; CHECK: 1 = { ; CHECK: Name = .text ; CHECK: VirtualSize = 0 ; CHECK: VirtualAddress = 0 @@ -75,7 +75,7 @@ ; CHECK: } ; CHECK: ] ; CHECK: } -; CHECK: 1 = { +; CHECK: 2 = { ; CHECK: Name = .data ; CHECK: VirtualSize = 0 ; CHECK: VirtualAddress = 0 Modified: llvm/trunk/test/Scripts/coff-dump.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/coff-dump.py?rev=113928&r1=113927&r2=113928&view=diff ============================================================================== --- llvm/trunk/test/Scripts/coff-dump.py (original) +++ llvm/trunk/test/Scripts/coff-dump.py Tue Sep 14 22:58:51 2010 @@ -73,7 +73,7 @@ (0x4000, 'IMAGE_FILE_UP_SYSTEM_ONLY', ), (0x8000, 'IMAGE_FILE_BYTES_REVERSED_HI', ), ])), - ('Sections', ('array', 'NumberOfSections', ('struct', [ + ('Sections', ('array', '1', 'NumberOfSections', ('struct', [ ('Name', ('scalar', '<8s', secname)), ('VirtualSize', ('scalar', ' Author: lattner Date: Tue Sep 14 23:04:33 2010 New Revision: 113929 URL: http://llvm.org/viewvc/llvm-project?rev=113929&view=rev Log: add a bunch of aliases for fp operations with no operand, rdar://8431422 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113929&r1=113928&r2=113929&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 23:04:33 2010 @@ -923,6 +923,24 @@ std::swap(Operands[1], Operands[2]); } + // The assembler accepts these instructions with no operand as a synonym for + // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)". + if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" || + Name == "faddp" || Name == "fsubp" || Name == "fsubrp" || + Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") && + Operands.size() == 1) { + Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), + NameLoc, NameLoc)); + } + + // The assembler accepts these instructions with no operand as a synonym for + // an instruction acting on st,st(1). e.g. "faddp" -> "faddp %st(0),%st(1)". + //if (() && + // Operands.size() == 1) { + // Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), + // NameLoc, NameLoc)); + //} + return false; } @@ -959,11 +977,10 @@ } -bool -X86ATTAsmParser::MatchInstruction(SMLoc IDLoc, - const SmallVectorImpl - &Operands, - MCInst &Inst) { +bool X86ATTAsmParser:: +MatchInstruction(SMLoc IDLoc, + const SmallVectorImpl &Operands, + MCInst &Inst) { assert(!Operands.empty() && "Unexpect empty operand list!"); bool WasOriginallyInvalidOperand = false; Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113929&r1=113928&r2=113929&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 23:04:33 2010 @@ -210,3 +210,28 @@ out %al, (%dx) out %ax, (%dx) outl %eax, (%dx) + + +// rdar://8431422 + +// CHECK: fxch %st(1) +// CHECK: fucom %st(1) +// CHECK: fucomp %st(1) +// CHECK: faddp %st(1) +// CHECK: faddp %st(0) +// CHECK: fsubp %st(1) +// CHECK: fsubrp %st(1) +// CHECK: fmulp %st(1) +// CHECK: fdivp %st(1) +// CHECK: fdivrp %st(1) + +fxch +fucom +fucomp +faddp +faddp %st +fsubp +fsubrp +fmulp +fdivp +fdivrp From sabre at nondot.org Tue Sep 14 23:08:38 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 04:08:38 -0000 Subject: [llvm-commits] [llvm] r113930 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915040838.F126A2A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 23:08:38 2010 New Revision: 113930 URL: http://llvm.org/viewvc/llvm-project?rev=113930&view=rev Log: add some aliases for f[u]comi, part of rdar://8431422 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113930&r1=113929&r2=113930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 23:08:38 2010 @@ -933,13 +933,15 @@ NameLoc, NameLoc)); } - // The assembler accepts these instructions with no operand as a synonym for - // an instruction acting on st,st(1). e.g. "faddp" -> "faddp %st(0),%st(1)". - //if (() && - // Operands.size() == 1) { - // Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), - // NameLoc, NameLoc)); - //} + // The assembler accepts these instructions with two few operands as a synonym + // for taking %st(1),%st(0) or X, %st(0). + if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) { + if (Operands.size() == 1) + Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), + NameLoc, NameLoc)); + Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"), + NameLoc, NameLoc)); + } return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113930&r1=113929&r2=113930&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 23:08:38 2010 @@ -235,3 +235,17 @@ fmulp fdivp fdivrp + +// CHECK: fcomi %st(1), %st(0) +// CHECK: fcomi %st(2), %st(0) +// CHECK: fucomi %st(1), %st(0) +// CHECK: fucomi %st(2), %st(0) +// CHECK: fucomi %st(2), %st(0) + +fcomi +fcomi %st(2) +fucomi +fucomi %st(2) +fucomi %st(2), %st + + From sabre at nondot.org Tue Sep 14 23:15:16 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 04:15:16 -0000 Subject: [llvm-commits] [llvm] r113932 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915041516.C8C0C2A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 23:15:16 2010 New Revision: 113932 URL: http://llvm.org/viewvc/llvm-project?rev=113932&view=rev Log: add various broken forms of fnstsw. I didn't add the %rax version because it adds a prefix and makes even less sense than the other broken forms. This wraps up rdar://8431422 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113932&r1=113931&r2=113932&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 23:15:16 2010 @@ -943,6 +943,25 @@ NameLoc, NameLoc)); } + // The assembler accepts various amounts of brokenness for fnstsw. + if (Name == "fnstsw") { + if (Operands.size() == 2 && + static_cast(Operands[1])->isReg()) { + // "fnstsw al" and "fnstsw eax" -> "fnstw" + unsigned Reg = static_cast(Operands[1])->Reg.RegNo; + if (Reg == MatchRegisterName("eax") || + Reg == MatchRegisterName("al")) { + delete Operands[1]; + Operands.pop_back(); + } + } + + // "fnstw" -> "fnstw %ax" + if (Operands.size() == 1) + Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"), + NameLoc, NameLoc)); + } + return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113932&r1=113931&r2=113932&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 23:15:16 2010 @@ -248,4 +248,12 @@ fucomi %st(2) fucomi %st(2), %st +// CHECK: fnstsw %ax +// CHECK: fnstsw %ax +// CHECK: fnstsw %ax +// CHECK: fnstsw %ax +fnstsw +fnstsw %ax +fnstsw %eax +fnstsw %al From sabre at nondot.org Tue Sep 14 23:33:27 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 04:33:27 -0000 Subject: [llvm-commits] [llvm] r113936 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915043327.4DC9E2A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 23:33:27 2010 New Revision: 113936 URL: http://llvm.org/viewvc/llvm-project?rev=113936&view=rev Log: fix rdar://8431880 - rcl/rcr with no shift amount not recognized Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113936&r1=113935&r2=113936&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 23:33:27 2010 @@ -813,7 +813,7 @@ if (getLexer().is(AsmToken::EndOfStatement)) Parser.Lex(); // Consume the EndOfStatement - // FIXME: Hack to handle recognize s{hr,ar,hl} , $1. Canonicalize to + // FIXME: Hack to handle recognize s{hr,ar,hl} $1, . Canonicalize to // "shift ". if ((Name.startswith("shr") || Name.startswith("sar") || Name.startswith("shl")) && @@ -825,6 +825,14 @@ Operands.erase(Operands.begin() + 1); } } + + // FIXME: Hack to handle recognize "rc[lr] " -> "rcl $1, ". + if ((Name.startswith("rcl") || Name.startswith("rcr")) && + Operands.size() == 2) { + const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext()); + Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc)); + std::swap(Operands[1], Operands[2]); + } // FIXME: Hack to handle recognize "in[bwl] ". Canonicalize it to // "inb , %al". Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113936&r1=113935&r2=113936&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 23:33:27 2010 @@ -257,3 +257,14 @@ fnstsw %ax fnstsw %eax fnstsw %al + +// rdar://8431880 +// CHECK: rclb $1, %bl +// CHECK: rcll $1, 3735928559(%ebx,%ecx,8) +// CHECK: rcrl $1, %ecx +// CHECK: rcrl $1, 305419896 + +rcl %bl +rcll 0xdeadbeef(%ebx,%ecx,8) +rcr %ecx +rcrl 0x12345678 From sabre at nondot.org Tue Sep 14 23:37:19 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 04:37:19 -0000 Subject: [llvm-commits] [llvm] r113937 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915043719.141FE2A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 23:37:18 2010 New Revision: 113937 URL: http://llvm.org/viewvc/llvm-project?rev=113937&view=rev Log: implement aliases for shld/shrd, part of rdar://8418316 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113937&r1=113936&r2=113937&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 14 23:37:18 2010 @@ -833,6 +833,15 @@ Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc)); std::swap(Operands[1], Operands[2]); } + + // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op". + if ((Name.startswith("shld") || Name.startswith("shrd")) && + Operands.size() == 3) { + const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext()); + Operands.insert(Operands.begin()+1, + X86Operand::CreateImm(One, NameLoc, NameLoc)); + } + // FIXME: Hack to handle recognize "in[bwl] ". Canonicalize it to // "inb , %al". Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113937&r1=113936&r2=113937&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 23:37:18 2010 @@ -268,3 +268,14 @@ rcll 0xdeadbeef(%ebx,%ecx,8) rcr %ecx rcrl 0x12345678 + +// rdar://8418316 +// CHECK: shldw $1, %bx, %bx +// CHECK: shldw $1, %bx, %bx +// CHECK: shrdw $1, %bx, %bx +// CHECK: shrdw $1, %bx, %bx + +shld %bx,%bx +shld $1, %bx,%bx +shrd %bx,%bx +shrd $1, %bx,%bx From sabre at nondot.org Tue Sep 14 23:45:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 04:45:10 -0000 Subject: [llvm-commits] [llvm] r113938 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915044510.E65542A6C12C@llvm.org> Author: lattner Date: Tue Sep 14 23:45:10 2010 New Revision: 113938 URL: http://llvm.org/viewvc/llvm-project?rev=113938&view=rev Log: fix the encoding of sldt GR16 to have the 0x66 prefix, and add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113938&r1=113937&r2=113938&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 14 23:45:10 2010 @@ -4359,9 +4359,11 @@ def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins), "sidt\t$dst", []>, TB; def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), - "sldt{w}\t$dst", []>, TB; + "sldt{w}\t$dst", []>, TB, OpSize; def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins), "sldt{w}\t$dst", []>, TB; +def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), + "sldt{l}\t$dst", []>, TB; def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), "lgdt\t$src", []>, TB; def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src), Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113938&r1=113937&r2=113938&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 14 23:45:10 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown %s > %t 2> %t.err +// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s > %t 2> %t.err // RUN: FileCheck < %t %s // RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s @@ -279,3 +279,12 @@ shld $1, %bx,%bx shrd %bx,%bx shrd $1, %bx,%bx + +// CHECK: sldtl %ecx +// CHECK: encoding: [0x0f,0x00,0xc1] +// CHECK: sldtw %cx +// CHECK: encoding: [0x66,0x0f,0x00,0xc1] + +sldt %ecx +sldt %cx + From stoklund at 2pi.dk Tue Sep 14 23:47:15 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 14 Sep 2010 21:47:15 -0700 Subject: [llvm-commits] [llvm] r113918 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMInstrNEON.td In-Reply-To: <20100915014805.8745E2A6C12C@llvm.org> References: <20100915014805.8745E2A6C12C@llvm.org> Message-ID: On Sep 14, 2010, at 6:48 PM, Bob Wilson wrote: > Author: bwilson > Date: Tue Sep 14 20:48:05 2010 > New Revision: 113918 > > URL: http://llvm.org/viewvc/llvm-project?rev=113918&view=rev > Log: > Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and > storeRegToStackSlot. Nice! It looks like the is{StoreTo,LoadFrom}StackSlot hooks need an update as well. /jakob -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100914/1b511c60/attachment.bin From sabre at nondot.org Wed Sep 15 00:14:54 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 05:14:54 -0000 Subject: [llvm-commits] [llvm] r113945 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915051454.75D522A6C12D@llvm.org> Author: lattner Date: Wed Sep 15 00:14:54 2010 New Revision: 113945 URL: http://llvm.org/viewvc/llvm-project?rev=113945&view=rev Log: Disambiguate lcall/ljmp to the 32-bit version. This happens even in 64-bit mode apparently. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113945&r1=113944&r2=113945&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 15 00:14:54 2010 @@ -979,6 +979,16 @@ NameLoc, NameLoc)); } + // lcall *x and ljmp *x -> lcalll and ljmpl + if ((Name == "lcall" || Name == "ljmp") && + Operands.size() == 3 && + static_cast(Operands[1])->isToken() && + static_cast(Operands[1])->getToken() == "*") { + delete Operands[0]; + Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl", + NameLoc); + } + return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113945&r1=113944&r2=113945&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Wed Sep 15 00:14:54 2010 @@ -288,3 +288,9 @@ sldt %ecx sldt %cx +// CHECK: lcalll *3135175374 +// CHECK: ljmpl *3135175374 +lcall *0xbadeface +ljmp *0xbadeface + + From sabre at nondot.org Wed Sep 15 00:25:21 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 05:25:21 -0000 Subject: [llvm-commits] [llvm] r113948 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_32-new-encoder.s test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100915052521.ECE5B2A6C12C@llvm.org> Author: lattner Date: Wed Sep 15 00:25:21 2010 New Revision: 113948 URL: http://llvm.org/viewvc/llvm-project?rev=113948&view=rev Log: apparently jmpl $1,$2 is an alias for ljmpl, similiarly for call. Add this. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113948&r1=113947&r2=113948&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 15 00:25:21 2010 @@ -989,6 +989,27 @@ NameLoc); } + // jmp $42,$5 -> ljmp, similarly for call. + if ((Name.startswith("call") || Name.startswith("jmp")) && + Operands.size() == 3 && + static_cast(Operands[1])->isImm() && + static_cast(Operands[2])->isImm()) { + const char *NewOpName = StringSwitch(Name) + .Case("jmp", "ljmp") + .Case("jmpw", "ljmpw") + .Case("jmpl", "ljmpl") + .Case("jmpq", "ljmpq") + .Case("call", "lcall") + .Case("callw", "lcallw") + .Case("calll", "lcalll") + .Case("callq", "lcallq") + .Default(0); + if (NewOpName) { + delete Operands[0]; + Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc); + } + } + return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113948&r1=113947&r2=113948&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 15 00:25:21 2010 @@ -537,3 +537,18 @@ setnl %bl setng %bl setnle %bl + + + + +// CHECK: lcalll $31438, $31438 +// CHECK: lcalll $31438, $31438 +// CHECK: ljmpl $31438, $31438 +// CHECK: ljmpl $31438, $31438 + +calll $0x7ace,$0x7ace +lcalll $0x7ace,$0x7ace +jmpl $0x7ace,$0x7ace +ljmpl $0x7ace,$0x7ace + + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113948&r1=113947&r2=113948&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Wed Sep 15 00:25:21 2010 @@ -293,4 +293,3 @@ lcall *0xbadeface ljmp *0xbadeface - From sabre at nondot.org Wed Sep 15 00:30:20 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 15 Sep 2010 05:30:20 -0000 Subject: [llvm-commits] [llvm] r113949 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_32-new-encoder.s Message-ID: <20100915053021.03FEE2A6C12C@llvm.org> Author: lattner Date: Wed Sep 15 00:30:20 2010 New Revision: 113949 URL: http://llvm.org/viewvc/llvm-project?rev=113949&view=rev Log: lcall and ljmp always default to lcalll and ljmpl. This finally wraps up r8418316 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113949&r1=113948&r2=113949&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 15 00:30:20 2010 @@ -979,16 +979,6 @@ NameLoc, NameLoc)); } - // lcall *x and ljmp *x -> lcalll and ljmpl - if ((Name == "lcall" || Name == "ljmp") && - Operands.size() == 3 && - static_cast(Operands[1])->isToken() && - static_cast(Operands[1])->getToken() == "*") { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl", - NameLoc); - } - // jmp $42,$5 -> ljmp, similarly for call. if ((Name.startswith("call") || Name.startswith("jmp")) && Operands.size() == 3 && @@ -1007,9 +997,17 @@ if (NewOpName) { delete Operands[0]; Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc); + Name = NewOpName; } } + // lcall and ljmp -> lcalll and ljmpl + if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) { + delete Operands[0]; + Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl", + NameLoc); + } + return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113949&r1=113948&r2=113949&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 15 00:30:20 2010 @@ -551,4 +551,14 @@ jmpl $0x7ace,$0x7ace ljmpl $0x7ace,$0x7ace +// CHECK: lcalll $31438, $31438 +// CHECK: lcalll $31438, $31438 +// CHECK: ljmpl $31438, $31438 +// CHECK: ljmpl $31438, $31438 + +call $0x7ace,$0x7ace +lcall $0x7ace,$0x7ace +jmp $0x7ace,$0x7ace +ljmp $0x7ace,$0x7ace + From baldrick at free.fr Wed Sep 15 02:01:25 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 15 Sep 2010 07:01:25 -0000 Subject: [llvm-commits] [dragonegg] r113954 - /dragonegg/trunk/llvm-backend.cpp Message-ID: <20100915070125.DBB3E2A6C12D@llvm.org> Author: baldrick Date: Wed Sep 15 02:01:25 2010 New Revision: 113954 URL: http://llvm.org/viewvc/llvm-project?rev=113954&view=rev Log: Replace LLVM_GLOBAL_VISIBILITY with __attribute__ ((visibility("default"))). There should probably be a configure test to see if the compiler can handle this, but since we already always compile with -fvisibility=hidden, things should not be worse than they were before. Modified: dragonegg/trunk/llvm-backend.cpp Modified: dragonegg/trunk/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=113954&r1=113953&r2=113954&view=diff ============================================================================== --- dragonegg/trunk/llvm-backend.cpp (original) +++ dragonegg/trunk/llvm-backend.cpp Wed Sep 15 02:01:25 2010 @@ -1549,7 +1549,7 @@ // This plugin's code is licensed under the GPLv2 or later. The LLVM libraries // use the GPL compatible University of Illinois/NCSA Open Source License. The // plugin is GPL compatible. -int plugin_is_GPL_compatible LLVM_GLOBAL_VISIBILITY; +int plugin_is_GPL_compatible __attribute__ ((visibility("default"))); /// llvm_start_unit - Perform late initialization. This is called by GCC just @@ -2424,8 +2424,9 @@ /// plugin_init - Plugin initialization routine, called by GCC. This is the /// first code executed in the plugin (except for constructors). Configure /// the plugin and setup GCC, taking over optimization and code generation. -int LLVM_GLOBAL_VISIBILITY plugin_init(struct plugin_name_args *plugin_info, - struct plugin_gcc_version *version) { +int __attribute__ ((visibility("default"))) +plugin_init(struct plugin_name_args *plugin_info, + struct plugin_gcc_version *version) { const char *plugin_name = plugin_info->base_name; struct register_pass_info pass_info; From isanbard at gmail.com Wed Sep 15 02:39:08 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 15 Sep 2010 07:39:08 -0000 Subject: [llvm-commits] [test-suite] r113958 - /test-suite/tags/RELEASE_28/rc2/ Message-ID: <20100915073908.960FB2A6C12F@llvm.org> Author: void Date: Wed Sep 15 02:39:08 2010 New Revision: 113958 URL: http://llvm.org/viewvc/llvm-project?rev=113958&view=rev Log: Creating release candidate 2 from 2.8 release branch. Added: test-suite/tags/RELEASE_28/rc2/ - copied from r113957, test-suite/branches/release_28/ From baldrick at free.fr Wed Sep 15 03:09:56 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 15 Sep 2010 08:09:56 -0000 Subject: [llvm-commits] [llvm] r113959 - /llvm/trunk/include/llvm/Support/Compiler.h Message-ID: <20100915080956.1BCCE2A6C12D@llvm.org> Author: baldrick Date: Wed Sep 15 03:09:55 2010 New Revision: 113959 URL: http://llvm.org/viewvc/llvm-project?rev=113959&view=rev Log: Remove LLVM_GLOBAL_VISIBILITY, which is unused, and was not working properly. The problem was that the test for whether a compiler supports it or not was inaccurate, but has to be accurate: LLVM_LOCAL_VISIBILITY is an optimization and not needed for correctness, so wrongly thinking a compiler doesn't support it is not a big deal, but LLVM_GLOBAL_VISIBILITY is for correctness, and not an optimization: getting it wrong is fatal: it needs to be set based on a configure test not testing the gcc version. Since dragonegg has moved to a different scheme, and it was the only user of LLVM_GLOBAL_VISIBILITY, just remove this macro. Modified: llvm/trunk/include/llvm/Support/Compiler.h Modified: llvm/trunk/include/llvm/Support/Compiler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=113959&r1=113958&r2=113959&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Compiler.h (original) +++ llvm/trunk/include/llvm/Support/Compiler.h Wed Sep 15 03:09:55 2010 @@ -19,20 +19,10 @@ /// into a shared library, then the class should be private to the library and /// not accessible from outside it. Can also be used to mark variables and /// functions, making them private to any shared library they are linked into. - -/// LLVM_GLOBAL_VISIBILITY - If a class marked with this attribute is linked -/// into a shared library, then the class will be accessible from outside the -/// the library. Can also be used to mark variables and functions, making them -/// accessible from outside any shared library they are linked into. -#if defined(__MINGW32__) || defined(__CYGWIN__) -#define LLVM_LIBRARY_VISIBILITY -#define LLVM_GLOBAL_VISIBILITY __declspec(dllexport) -#elif (__GNUC__ >= 4) +#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__) #define LLVM_LIBRARY_VISIBILITY __attribute__ ((visibility("hidden"))) -#define LLVM_GLOBAL_VISIBILITY __attribute__ ((visibility("default"))) #else #define LLVM_LIBRARY_VISIBILITY -#define LLVM_GLOBAL_VISIBILITY #endif #if (__GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1)) From baldrick at free.fr Wed Sep 15 03:17:10 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 15 Sep 2010 08:17:10 -0000 Subject: [llvm-commits] [llvm] r113960 - /llvm/trunk/bindings/ada/ Message-ID: <20100915081710.BC0D52A6C12D@llvm.org> Author: baldrick Date: Wed Sep 15 03:17:10 2010 New Revision: 113960 URL: http://llvm.org/viewvc/llvm-project?rev=113960&view=rev Log: Remove the Ada bindings which are unmaintained and unused. The project which was the main putative user of the binding is actually maintaining its own different binding, see http://git.ada.cx/cgi-bin/cgit.cgi/draco.git/ Removed: llvm/trunk/bindings/ada/ From baldrick at free.fr Wed Sep 15 03:56:39 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 15 Sep 2010 10:56:39 +0200 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple In-Reply-To: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> References: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> Message-ID: <4C908A47.9070103@free.fr> Hi Cameron, > + explicit Triple(StringRef ArchStr, StringRef VendorStr, StringRef OSStr, > + StringRef EnvironmentStr ) there is an extraneous space before the closing bracket. > + /// getEnvironment - Get the parsed environment type of this triple. > + EnvironmentType getEnvironment() const { > + if (!isInitialized()) Parse(); > + if (!hasEnvironment()) return UnknownEnvironment; If there is no environment, won't Environment be equal to UnknownEnvironment, making the above line useless? > + return Environment; > + } > + As well as the above, you should also add some unit tests and enhance the normalize method to take the environment into account. Ciao, Duncan. From baldrick at free.fr Wed Sep 15 07:30:35 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 15 Sep 2010 12:30:35 -0000 Subject: [llvm-commits] [llvm] r113965 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100915123035.939382A6C12C@llvm.org> Author: baldrick Date: Wed Sep 15 07:30:35 2010 New Revision: 113965 URL: http://llvm.org/viewvc/llvm-project?rev=113965&view=rev Log: Release-Asserts no longer exists. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113965&r1=113964&r2=113965&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Wed Sep 15 07:30:35 2010 @@ -307,7 +307,7 @@ fi ( -Flavors="Debug Release Release-Asserts" +Flavors="Debug Release Release+Asserts" if [ "$do_64bit" = "yes" ]; then Flavors="$Flavors Release-64" fi From dpatel at apple.com Wed Sep 15 09:48:53 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 15 Sep 2010 14:48:53 -0000 Subject: [llvm-commits] [llvm] r113967 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100915144853.7DC962A6C12C@llvm.org> Author: dpatel Date: Wed Sep 15 09:48:53 2010 New Revision: 113967 URL: http://llvm.org/viewvc/llvm-project?rev=113967&view=rev Log: If dbg.declare from non-entry block is using alloca from entry block then use offset available in StaticAllocaMap to emit DBG_VALUE. Right now, this has no material impact because varible info also collected using offset table maintained in machine module info. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=113967&r1=113966&r2=113967&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Sep 15 09:48:53 2010 @@ -4117,9 +4117,21 @@ DAG.AddDbgValue(SDV, N.getNode(), isParameter); } else { // If Address is an arugment then try to emits its dbg value using - // virtual register info from the FuncInfo.ValueMap. Otherwise add undef - // to help track missing debug info. + // virtual register info from the FuncInfo.ValueMap. if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { + // If variable is pinned by a alloca in dominating bb then + // use StaticAllocaMap. + if (const AllocaInst *AI = dyn_cast(Address)) { + DenseMap::iterator SI = + FuncInfo.StaticAllocaMap.find(AI); + if (SI != FuncInfo.StaticAllocaMap.end()) { + SDV = DAG.getDbgValue(Variable, SI->second, + 0, dl, SDNodeOrder); + DAG.AddDbgValue(SDV, 0, false); + return 0; + } + } + // Otherwise add undef to help track missing debug info. SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 0, dl, SDNodeOrder); DAG.AddDbgValue(SDV, 0, false); From gvenn.cfe.dev at gmail.com Wed Sep 15 09:55:32 2010 From: gvenn.cfe.dev at gmail.com (Garrison Venn) Date: Wed, 15 Sep 2010 14:55:32 -0000 Subject: [llvm-commits] [llvm] r113970 - /llvm/trunk/examples/Makefile Message-ID: <20100915145532.D9D252A6C12C@llvm.org> Author: gvenn Date: Wed Sep 15 09:55:32 2010 New Revision: 113970 URL: http://llvm.org/viewvc/llvm-project?rev=113970&view=rev Log: Removed TracingBrainF from examples Makefile. Modified: llvm/trunk/examples/Makefile Modified: llvm/trunk/examples/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Makefile?rev=113970&r1=113969&r2=113970&view=diff ============================================================================== --- llvm/trunk/examples/Makefile (original) +++ llvm/trunk/examples/Makefile Wed Sep 15 09:55:32 2010 @@ -10,8 +10,7 @@ include $(LEVEL)/Makefile.config -PARALLEL_DIRS:= BrainF Fibonacci HowToUseJIT Kaleidoscope ModuleMaker \ - TracingBrainF +PARALLEL_DIRS:= BrainF Fibonacci HowToUseJIT Kaleidoscope ModuleMaker ifeq ($(HAVE_PTHREAD),1) PARALLEL_DIRS += ParallelJIT From gvenn.cfe.dev at gmail.com Wed Sep 15 10:00:25 2010 From: gvenn.cfe.dev at gmail.com (Garrison Venn) Date: Wed, 15 Sep 2010 11:00:25 -0400 Subject: [llvm-commits] Removed TracingBrainF entry from examples/Makefile Message-ID: <90327D5C-9AFA-44FF-9F3E-0EDB0FF5C5E3@gmail.com> I just commited the following patch: -------------- next part -------------- A non-text attachment was scrubbed... Name: FixExamplesMakefile.patch Type: application/octet-stream Size: 459 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100915/cfbe7b37/attachment.obj From foldr at codedgers.com Wed Sep 15 10:20:41 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 15 Sep 2010 15:20:41 -0000 Subject: [llvm-commits] [llvm] r113972 - in /llvm/trunk: lib/CompilerDriver/CompilationGraph.cpp test/LLVMC/C++/dg.exp test/LLVMC/C++/unknown_suffix.unk Message-ID: <20100915152041.542E52A6C12C@llvm.org> Author: foldr Date: Wed Sep 15 10:20:41 2010 New Revision: 113972 URL: http://llvm.org/viewvc/llvm-project?rev=113972&view=rev Log: llvmc: make -x work with unknown suffixes. Added: llvm/trunk/test/LLVMC/C++/unknown_suffix.unk Modified: llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp llvm/trunk/test/LLVMC/C++/dg.exp Modified: llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp?rev=113972&r1=113971&r2=113972&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp (original) +++ llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp Wed Sep 15 10:20:41 2010 @@ -218,10 +218,11 @@ InputLanguagesSet& InLangs, const LanguageMap& LangMap) const { // Determine the input language. - const std::string* InLang = LangMap.GetLanguage(In); + const std::string* InLang = (ForceLanguage ? ForceLanguage + : LangMap.GetLanguage(In)); if (InLang == 0) return 0; - const std::string& InLanguage = (ForceLanguage ? *ForceLanguage : *InLang); + const std::string& InLanguage = *InLang; // Add the current input language to the input language set. InLangs.insert(InLanguage); Modified: llvm/trunk/test/LLVMC/C++/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/C%2B%2B/dg.exp?rev=113972&r1=113971&r2=113972&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/C++/dg.exp (original) +++ llvm/trunk/test/LLVMC/C++/dg.exp Wed Sep 15 10:20:41 2010 @@ -1,5 +1,5 @@ load_lib llvm.exp if [ llvm_gcc_supports c++ ] then { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{unk,ll,c,cpp}]] } Added: llvm/trunk/test/LLVMC/C++/unknown_suffix.unk URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/C%2B%2B/unknown_suffix.unk?rev=113972&view=auto ============================================================================== --- llvm/trunk/test/LLVMC/C++/unknown_suffix.unk (added) +++ llvm/trunk/test/LLVMC/C++/unknown_suffix.unk Wed Sep 15 10:20:41 2010 @@ -0,0 +1,9 @@ +// Test that the -x option works for files with unknown suffixes. +// RUN: llvmc -x c++ %s -o %t +// RUN: %abs_tmp | grep hello +// XFAIL: vg +#include + +int main() { + std::cout << "hello" << '\n'; +} From baldrick at free.fr Wed Sep 15 10:30:11 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 15 Sep 2010 15:30:11 -0000 Subject: [llvm-commits] [zorg] r113973 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100915153011.B1DBB2A6C12C@llvm.org> Author: baldrick Date: Wed Sep 15 10:30:11 2010 New Revision: 113973 URL: http://llvm.org/viewvc/llvm-project?rev=113973&view=rev Log: Add an i386-linux llvm-selfhost buildbot. The sharp eyed may notice that the machine it runs on is a 64 bit machine. However it runs in a partial 32 bit environment which, along with the triple, should result in there being no difference to running on a real 32 bit machine. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=113973&r1=113972&r2=113973&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Sep 15 10:30:11 2010 @@ -248,6 +248,13 @@ extra_configure_args=['--disable-multilib']), 'category' : 'llvm-gcc.exp' }, + {'name' : "llvm-gcc-i386-linux-selfhost", + 'slavenames':["gcc10"], + 'builddir':"llvm-gcc-i386-linux-selfhost", + 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', + extra_configure_args=['--disable-multilib']), + 'category' : 'llvm-gcc.exp' }, + {'name' : "llvm-gcc-x86_64-darwin10-self-mingw32", 'slavenames': [ "kistanova1" ], 'builddir' : "llvm-gcc-x86_64-darwin10-self-mingw32", From espindola at google.com Wed Sep 15 10:59:11 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 11:59:11 -0400 Subject: [llvm-commits] [patch] Add a InitSections method to the streamer interface Message-ID: I was having a hard time debugging my lest patch so I decided to code something that makes testing easier first. What this patch does is move the hard coded initial section selection into a MC streamer method. This way we can use the ELF streamer without passing the -n option to llvm-mc and the initial sections created matches those created by gnu as. This make comparing the output of "readelf -aW" a lot easier. I also tested this by compiling and running screen :-) A small part of the hack remains in the text streamer in that it still uses the macho section. I would think that the text streamer should not set the initial sections, since the real assembler using the text we are printing will. If others agree, I will change this in a followup patch. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: init-sections.patch Type: application/octet-stream Size: 10400 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100915/90072395/attachment.obj From grosbach at apple.com Wed Sep 15 11:08:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 16:08:15 -0000 Subject: [llvm-commits] [llvm] r113975 - /llvm/trunk/include/llvm/CodeGen/MachineOperand.h Message-ID: <20100915160815.71F232A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 11:08:15 2010 New Revision: 113975 URL: http://llvm.org/viewvc/llvm-project?rev=113975&view=rev Log: trailing whitespace Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=113975&r1=113974&r2=113975&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Wed Sep 15 11:08:15 2010 @@ -18,7 +18,7 @@ #include namespace llvm { - + class BlockAddress; class ConstantFP; class GlobalValue; @@ -30,7 +30,7 @@ class TargetRegisterInfo; class raw_ostream; class MCSymbol; - + /// MachineOperand class - Representation of each machine instruction operand. /// class MachineOperand { @@ -54,21 +54,21 @@ /// OpKind - Specify what kind of operand this is. This discriminates the /// union. unsigned char OpKind; // MachineOperandType - + /// SubReg - Subregister number, only valid for MO_Register. A value of 0 /// indicates the MO_Register has no subReg. unsigned char SubReg; - + /// TargetFlags - This is a set of target-specific operand flags. unsigned char TargetFlags; - + /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register /// operands. - + /// IsDef - True if this is a def, false if this is a use of the register. /// bool IsDef : 1; - + /// IsImp - True if this is an implicit def or use, false if it is explicit. /// bool IsImp : 1; @@ -94,7 +94,7 @@ /// not a real instruction. Such uses should be ignored during codegen. bool IsDebug : 1; - /// ParentMI - This is the instruction that this operand is embedded into. + /// ParentMI - This is the instruction that this operand is embedded into. /// This is valid for all operand types, when the operand is in an instr. MachineInstr *ParentMI; @@ -111,7 +111,7 @@ MachineOperand **Prev; // Access list for register. MachineOperand *Next; } Reg; - + /// OffsetedInfo - This struct contains the offset and an object identifier. /// this represent the object as with an optional offset from it. struct { @@ -124,7 +124,7 @@ int64_t Offset; // An offset from the object. } OffsetedInfo; } Contents; - + explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) { TargetFlags = 0; } @@ -132,17 +132,17 @@ /// getType - Returns the MachineOperandType for this operand. /// MachineOperandType getType() const { return (MachineOperandType)OpKind; } - + unsigned char getTargetFlags() const { return TargetFlags; } void setTargetFlags(unsigned char F) { TargetFlags = F; } void addTargetFlag(unsigned char F) { TargetFlags |= F; } - + /// getParent - Return the instruction that this operand belongs to. /// MachineInstr *getParent() { return ParentMI; } const MachineInstr *getParent() const { return ParentMI; } - + void print(raw_ostream &os, const TargetMachine *TM = 0) const; //===--------------------------------------------------------------------===// @@ -182,42 +182,42 @@ assert(isReg() && "This is not a register operand!"); return Contents.Reg.RegNo; } - + unsigned getSubReg() const { assert(isReg() && "Wrong MachineOperand accessor"); return (unsigned)SubReg; } - - bool isUse() const { + + bool isUse() const { assert(isReg() && "Wrong MachineOperand accessor"); return !IsDef; } - + bool isDef() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsDef; } - - bool isImplicit() const { + + bool isImplicit() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsImp; } - + bool isDead() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsDead; } - + bool isKill() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsKill; } - + bool isUndef() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsUndef; } - + bool isEarlyClobber() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsEarlyClobber; @@ -238,11 +238,11 @@ //===--------------------------------------------------------------------===// // Mutators for Register Operands //===--------------------------------------------------------------------===// - + /// Change the register this operand corresponds to. /// void setReg(unsigned Reg); - + void setSubReg(unsigned subReg) { assert(isReg() && "Wrong MachineOperand accessor"); SubReg = (unsigned char)subReg; @@ -266,14 +266,14 @@ assert((Val || !isDebug()) && "Marking a debug operation as def"); IsDef = !Val; } - + void setIsDef(bool Val = true) { assert(isReg() && "Wrong MachineOperand accessor"); assert((!Val || !isDebug()) && "Marking a debug operation as def"); IsDef = Val; } - void setImplicit(bool Val = true) { + void setImplicit(bool Val = true) { assert(isReg() && "Wrong MachineOperand accessor"); IsImp = Val; } @@ -283,7 +283,7 @@ assert((!Val || !isDebug()) && "Marking a debug operation as kill"); IsKill = Val; } - + void setIsDead(bool Val = true) { assert(isReg() && IsDef && "Wrong MachineOperand accessor"); IsDead = Val; @@ -293,7 +293,7 @@ assert(isReg() && "Wrong MachineOperand accessor"); IsUndef = Val; } - + void setIsEarlyClobber(bool Val = true) { assert(isReg() && IsDef && "Wrong MachineOperand accessor"); IsEarlyClobber = Val; @@ -307,17 +307,17 @@ //===--------------------------------------------------------------------===// // Accessors for various operand types. //===--------------------------------------------------------------------===// - + int64_t getImm() const { assert(isImm() && "Wrong MachineOperand accessor"); return Contents.ImmVal; } - + const ConstantFP *getFPImm() const { assert(isFPImm() && "Wrong MachineOperand accessor"); return Contents.CFP; } - + MachineBasicBlock *getMBB() const { assert(isMBB() && "Wrong MachineOperand accessor"); return Contents.MBB; @@ -328,7 +328,7 @@ "Wrong MachineOperand accessor"); return Contents.OffsetedInfo.Val.Index; } - + const GlobalValue *getGlobal() const { assert(isGlobal() && "Wrong MachineOperand accessor"); return Contents.OffsetedInfo.Val.GV; @@ -343,7 +343,7 @@ assert(isMCSymbol() && "Wrong MachineOperand accessor"); return Contents.Sym; } - + /// getOffset - Return the offset from the symbol in this operand. This always /// returns 0 for ExternalSymbol operands. int64_t getOffset() const { @@ -351,7 +351,7 @@ "Wrong MachineOperand accessor"); return Contents.OffsetedInfo.Offset; } - + const char *getSymbolName() const { assert(isSymbol() && "Wrong MachineOperand accessor"); return Contents.OffsetedInfo.Val.SymbolName; @@ -361,11 +361,11 @@ assert(isMetadata() && "Wrong MachineOperand accessor"); return Contents.MD; } - + //===--------------------------------------------------------------------===// // Mutators for various operand types. //===--------------------------------------------------------------------===// - + void setImm(int64_t immVal) { assert(isImm() && "Wrong MachineOperand mutator"); Contents.ImmVal = immVal; @@ -376,54 +376,54 @@ "Wrong MachineOperand accessor"); Contents.OffsetedInfo.Offset = Offset; } - + void setIndex(int Idx) { assert((isFI() || isCPI() || isJTI()) && "Wrong MachineOperand accessor"); Contents.OffsetedInfo.Val.Index = Idx; } - + void setMBB(MachineBasicBlock *MBB) { assert(isMBB() && "Wrong MachineOperand accessor"); Contents.MBB = MBB; } - + //===--------------------------------------------------------------------===// // Other methods. //===--------------------------------------------------------------------===// - + /// isIdenticalTo - Return true if this operand is identical to the specified /// operand. Note: This method ignores isKill and isDead properties. bool isIdenticalTo(const MachineOperand &Other) const; - + /// ChangeToImmediate - Replace this operand with a new immediate operand of /// the specified value. If an operand is known to be an immediate already, /// the setImm method should be used. void ChangeToImmediate(int64_t ImmVal); - + /// ChangeToRegister - Replace this operand with a new register operand of /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, bool isKill = false, bool isDead = false, bool isUndef = false, bool isDebug = false); - + //===--------------------------------------------------------------------===// // Construction methods. //===--------------------------------------------------------------------===// - + static MachineOperand CreateImm(int64_t Val) { MachineOperand Op(MachineOperand::MO_Immediate); Op.setImm(Val); return Op; } - + static MachineOperand CreateFPImm(const ConstantFP *CFP) { MachineOperand Op(MachineOperand::MO_FPImmediate); Op.Contents.CFP = CFP; return Op; } - + static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, bool isKill = false, bool isDead = false, bool isUndef = false, @@ -506,7 +506,7 @@ Op.Contents.Sym = Sym; return Op; } - + friend class MachineInstr; friend class MachineRegisterInfo; private: @@ -521,7 +521,7 @@ assert(isReg() && "Can only add reg operand to use lists"); return Contents.Reg.Prev != 0; } - + /// AddRegOperandToRegInfo - Add this register operand to the specified /// MachineRegisterInfo. If it is null, then the next/prev fields should be /// explicitly nulled out. From espindola at google.com Wed Sep 15 11:14:22 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 12:14:22 -0400 Subject: [llvm-commits] [patch] Add a InitSections method to the streamer interface In-Reply-To: References: Message-ID: Forgot to include a test. Added it to the patch. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: init-sections.patch Type: application/octet-stream Size: 11722 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100915/cfb2e0c6/attachment.obj From grosbach at apple.com Wed Sep 15 11:24:01 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 16:24:01 -0000 Subject: [llvm-commits] [llvm] r113977 - in /llvm/trunk/include/llvm/MC: MCInst.h MCStreamer.h Message-ID: <20100915162401.578A82A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 11:24:01 2010 New Revision: 113977 URL: http://llvm.org/viewvc/llvm-project?rev=113977&view=rev Log: trailing whitespace and 80 column cleanup Modified: llvm/trunk/include/llvm/MC/MCInst.h llvm/trunk/include/llvm/MC/MCStreamer.h Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=113977&r1=113976&r2=113977&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Wed Sep 15 11:24:01 2010 @@ -36,21 +36,21 @@ kExpr ///< Relocatable immediate operand. }; unsigned char Kind; - + union { unsigned RegVal; int64_t ImmVal; const MCExpr *ExprVal; }; public: - + MCOperand() : Kind(kInvalid) {} bool isValid() const { return Kind != kInvalid; } bool isReg() const { return Kind == kRegister; } bool isImm() const { return Kind == kImmediate; } bool isExpr() const { return Kind == kExpr; } - + /// getReg - Returns the register number. unsigned getReg() const { assert(isReg() && "This is not a register operand!"); @@ -62,7 +62,7 @@ assert(isReg() && "This is not a register operand!"); RegVal = Reg; } - + int64_t getImm() const { assert(isImm() && "This is not an immediate"); return ImmVal; @@ -71,7 +71,7 @@ assert(isImm() && "This is not an immediate"); ImmVal = Val; } - + const MCExpr *getExpr() const { assert(isExpr() && "This is not an expression"); return ExprVal; @@ -80,7 +80,7 @@ assert(isExpr() && "This is not an expression"); ExprVal = Val; } - + static MCOperand CreateReg(unsigned Reg) { MCOperand Op; Op.Kind = kRegister; @@ -104,23 +104,23 @@ void dump() const; }; - + /// MCInst - Instances of this class represent a single low-level machine -/// instruction. +/// instruction. class MCInst { unsigned Opcode; SmallVector Operands; public: MCInst() : Opcode(0) {} - + void setOpcode(unsigned Op) { Opcode = Op; } - + unsigned getOpcode() const { return Opcode; } const MCOperand &getOperand(unsigned i) const { return Operands[i]; } MCOperand &getOperand(unsigned i) { return Operands[i]; } unsigned getNumOperands() const { return Operands.size(); } - + void addOperand(const MCOperand &Op) { Operands.push_back(Op); } Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=113977&r1=113976&r2=113977&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Sep 15 11:24:01 2010 @@ -54,8 +54,8 @@ /// kept up to date by SwitchSection. const MCSection *CurSection; - /// PrevSection - This is the previous section code is being emitted to, it is - /// kept up to date by SwitchSection. + /// PrevSection - This is the previous section code is being emitted to, it + /// is kept up to date by SwitchSection. const MCSection *PrevSection; public: @@ -65,11 +65,11 @@ /// @name Assembly File Formatting. /// @{ - + /// isVerboseAsm - Return true if this streamer supports verbose assembly /// and if it is enabled. virtual bool isVerboseAsm() const { return false; } - + /// hasRawTextSupport - Return true if this asm streamer supports emitting /// unformatted text to the .s file with EmitRawText. virtual bool hasRawTextSupport() const { return false; } @@ -82,20 +82,20 @@ /// If the comment includes embedded \n's, they will each get the comment /// prefix as appropriate. The added comment should not end with a \n. virtual void AddComment(const Twine &T) {} - + /// GetCommentOS - Return a raw_ostream that comments can be written to. /// Unlike AddComment, you are required to terminate comments with \n if you /// use this method. virtual raw_ostream &GetCommentOS(); - + /// AddBlankLine - Emit a blank line to a .s file to pretty it up. virtual void AddBlankLine() {} - + /// @} - + /// @name Symbol & Section Management /// @{ - + /// getCurrentSection - Return the current section that the streamer is /// emitting code to. const MCSection *getCurrentSection() const { return CurSection; } @@ -109,7 +109,7 @@ /// /// This corresponds to assembler directives like .section, .text, etc. virtual void SwitchSection(const MCSection *Section) = 0; - + /// EmitLabel - Emit a label for @p Symbol into the current section. /// /// This corresponds to an assembler statement such as: @@ -170,7 +170,7 @@ /// .size symbol, expression /// virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) = 0; - + /// EmitCommonSymbol - Emit a common symbol. /// /// @param Symbol - The common symbol to emit. @@ -185,7 +185,7 @@ /// @param Symbol - The common symbol to emit. /// @param Size - The size of the common symbol. virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size) = 0; - + /// EmitZerofill - Emit the zerofill section and an optional symbol. /// /// @param Section - The zerofill section to create and or to put the symbol @@ -204,7 +204,7 @@ /// @param ByteAlignment - The alignment of the thread local common symbol /// if non-zero. This must be a power of 2 on some targets. virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, - uint64_t Size, unsigned ByteAlignment = 0) = 0; + uint64_t Size, unsigned ByteAlignment = 0) = 0; /// @} /// @name Generating Data /// @{ @@ -231,31 +231,31 @@ /// to pass in a MCExpr for constant integers. virtual void EmitIntValue(uint64_t Value, unsigned Size, unsigned AddrSpace = 0); - + /// EmitSymbolValue - Special case of EmitValue that avoids the client /// having to pass in a MCExpr for MCSymbols. virtual void EmitSymbolValue(const MCSymbol *Sym, unsigned Size, unsigned AddrSpace); - + /// EmitGPRel32Value - Emit the expression @p Value into the output as a /// gprel32 (32-bit GP relative) value. /// /// This is used to implement assembler directives such as .gprel32 on /// targets that support them. virtual void EmitGPRel32Value(const MCExpr *Value) = 0; - + /// EmitFill - Emit NumBytes bytes worth of the value specified by /// FillValue. This implements directives such as '.space'. virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue, unsigned AddrSpace); - + /// EmitZeros - Emit NumBytes worth of zeros. This is a convenience /// function that just wraps EmitFill. void EmitZeros(uint64_t NumBytes, unsigned AddrSpace) { EmitFill(NumBytes, 0, AddrSpace); } - + /// EmitValueToAlignment - Emit some number of copies of @p Value until /// the byte alignment @p ByteAlignment is reached. /// @@ -301,13 +301,13 @@ /// @param Value - The value to use when filling bytes. virtual void EmitValueToOffset(const MCExpr *Offset, unsigned char Value = 0) = 0; - + /// @} - + /// EmitFileDirective - Switch to a new logical file. This is used to /// implement the '.file "foo.c"' assembler directive. virtual void EmitFileDirective(StringRef Filename) = 0; - + /// EmitDwarfFileDirective - Associate a filename with a specified logical /// file number. This implements the DWARF2 '.file 4 "foo.c"' assembler /// directive. @@ -322,7 +322,7 @@ /// indicated by the hasRawTextSupport() predicate. By default this aborts. virtual void EmitRawText(StringRef String); void EmitRawText(const Twine &String); - + /// Finish - Finish emission of machine code. virtual void Finish() = 0; }; From stoklund at 2pi.dk Wed Sep 15 11:36:26 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 16:36:26 -0000 Subject: [llvm-commits] [llvm] r113979 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100915163626.B164A2A6C12C@llvm.org> Author: stoklund Date: Wed Sep 15 11:36:26 2010 New Revision: 113979 URL: http://llvm.org/viewvc/llvm-project?rev=113979&view=rev Log: Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be forgotten in the future. Coalesce identical cases in switch. No functional changes intended. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113979&r1=113978&r2=113979&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 11:36:26 2010 @@ -573,84 +573,6 @@ return 0; // Not reached } -unsigned -ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, - int &FrameIndex) const { - switch (MI->getOpcode()) { - default: break; - case ARM::LDR: - case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. - if (MI->getOperand(1).isFI() && - MI->getOperand(2).isReg() && - MI->getOperand(3).isImm() && - MI->getOperand(2).getReg() == 0 && - MI->getOperand(3).getImm() == 0) { - FrameIndex = MI->getOperand(1).getIndex(); - return MI->getOperand(0).getReg(); - } - break; - case ARM::t2LDRi12: - case ARM::tRestore: - if (MI->getOperand(1).isFI() && - MI->getOperand(2).isImm() && - MI->getOperand(2).getImm() == 0) { - FrameIndex = MI->getOperand(1).getIndex(); - return MI->getOperand(0).getReg(); - } - break; - case ARM::VLDRD: - case ARM::VLDRS: - if (MI->getOperand(1).isFI() && - MI->getOperand(2).isImm() && - MI->getOperand(2).getImm() == 0) { - FrameIndex = MI->getOperand(1).getIndex(); - return MI->getOperand(0).getReg(); - } - break; - } - - return 0; -} - -unsigned -ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, - int &FrameIndex) const { - switch (MI->getOpcode()) { - default: break; - case ARM::STR: - case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. - if (MI->getOperand(1).isFI() && - MI->getOperand(2).isReg() && - MI->getOperand(3).isImm() && - MI->getOperand(2).getReg() == 0 && - MI->getOperand(3).getImm() == 0) { - FrameIndex = MI->getOperand(1).getIndex(); - return MI->getOperand(0).getReg(); - } - break; - case ARM::t2STRi12: - case ARM::tSpill: - if (MI->getOperand(1).isFI() && - MI->getOperand(2).isImm() && - MI->getOperand(2).getImm() == 0) { - FrameIndex = MI->getOperand(1).getIndex(); - return MI->getOperand(0).getReg(); - } - break; - case ARM::VSTRD: - case ARM::VSTRS: - if (MI->getOperand(1).isFI() && - MI->getOperand(2).isImm() && - MI->getOperand(2).getImm() == 0) { - FrameIndex = MI->getOperand(1).getIndex(); - return MI->getOperand(0).getReg(); - } - break; - } - - return 0; -} - void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, @@ -802,6 +724,38 @@ } } +unsigned +ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { + switch (MI->getOpcode()) { + default: break; + case ARM::STR: + case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. + if (MI->getOperand(1).isFI() && + MI->getOperand(2).isReg() && + MI->getOperand(3).isImm() && + MI->getOperand(2).getReg() == 0 && + MI->getOperand(3).getImm() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; + case ARM::t2STRi12: + case ARM::tSpill: + case ARM::VSTRD: + case ARM::VSTRS: + if (MI->getOperand(1).isFI() && + MI->getOperand(2).isImm() && + MI->getOperand(2).getImm() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; + } + + return 0; +} + void ARMBaseInstrInfo:: loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, @@ -892,6 +846,38 @@ } } +unsigned +ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const { + switch (MI->getOpcode()) { + default: break; + case ARM::LDR: + case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. + if (MI->getOperand(1).isFI() && + MI->getOperand(2).isReg() && + MI->getOperand(3).isImm() && + MI->getOperand(2).getReg() == 0 && + MI->getOperand(3).getImm() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; + case ARM::t2LDRi12: + case ARM::tRestore: + case ARM::VLDRD: + case ARM::VLDRS: + if (MI->getOperand(1).isFI() && + MI->getOperand(2).isImm() && + MI->getOperand(2).getImm() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; + } + + return 0; +} + MachineInstr* ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, From ggreif at gmail.com Wed Sep 15 11:53:07 2010 From: ggreif at gmail.com (Gabor Greif) Date: Wed, 15 Sep 2010 16:53:07 -0000 Subject: [llvm-commits] [llvm] r113980 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll Message-ID: <20100915165307.E1A922A6C12C@llvm.org> Author: ggreif Date: Wed Sep 15 11:53:07 2010 New Revision: 113980 URL: http://llvm.org/viewvc/llvm-project?rev=113980&view=rev Log: the darwin9-powerpc buildbot keeps consistently crashing, backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113980&r1=113979&r2=113980&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 11:53:07 2010 @@ -1352,20 +1352,6 @@ SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; - case ARM::TSTri: { - if (&*MI->getParent()->begin() == MI) - return false; - const MachineInstr *AND = llvm::prior(MI); - if (AND->getOpcode() != ARM::ANDri) - return false; - if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && - MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) { - SrcReg = AND->getOperand(0).getReg(); - CmpValue = 0; - return true; - } - } - break; } return false; @@ -1415,8 +1401,6 @@ switch (MI->getOpcode()) { default: break; case ARM::ADDri: - case ARM::ANDri: - case ARM::t2ANDri: case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=113980&r1=113979&r2=113980&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Wed Sep 15 11:53:07 2010 @@ -17,7 +17,8 @@ %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; CHECK: ands r12, r12, #3 +; CHECK: and lr, r12, #3 +; CHECK-NEXT: tst r12, #3 ; CHECK-NEXT: beq LBB0_4 ; T2: movs r5, #3 From wdietz2 at illinois.edu Wed Sep 15 12:02:01 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 17:02:01 -0000 Subject: [llvm-commits] [poolalloc] r113982 - /poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <20100915170201.D0D6D2A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 12:02:01 2010 New Revision: 113982 URL: http://llvm.org/viewvc/llvm-project?rev=113982&view=rev Log: Add newlines to the DEBUG prints so the result is readable. Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=113982&r1=113981&r2=113982&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Wed Sep 15 12:02:01 2010 @@ -814,7 +814,7 @@ // For indirect callees, find any callee since all DS graphs have been // merged. if (CF) { // Direct calls are nice and simple. - DEBUG(errs() << " Handling direct call: " << *TheCall); + DEBUG(errs() << " Handling direct call: " << *TheCall << "\n"); // // Do not try to add pool handles to the function if it: @@ -839,7 +839,7 @@ assert ((Graphs.hasDSGraph (*CF)) && "Function has no ECGraph!\n"); CalleeGraph = Graphs.getDSGraph(*CF); } else { - DEBUG(errs() << " Handling indirect call: " << *TheCall); + DEBUG(errs() << " Handling indirect call: " << *TheCall << "\n"); // Here we fill in CF with one of the possible called functions. Because we // merged together all of the arguments to all of the functions in the @@ -1087,7 +1087,7 @@ AddPoolUse(*NewCall, Args[i], PoolUses); TheCall->replaceAllUsesWith(NewCall); - DEBUG(errs() << " Result Call: " << *NewCall); + DEBUG(errs() << " Result Call: " << *NewCall << "\n"); if (!TheCall->getType()->isVoidTy()) { // If we are modifying the original function, update the DSGraph... From bob.wilson at apple.com Wed Sep 15 12:12:08 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 15 Sep 2010 17:12:08 -0000 Subject: [llvm-commits] [llvm] r113983 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll Message-ID: <20100915171208.A9D132A6C12C@llvm.org> Author: bwilson Date: Wed Sep 15 12:12:08 2010 New Revision: 113983 URL: http://llvm.org/viewvc/llvm-project?rev=113983&view=rev Log: Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem encountered while building llvm-gcc for arm. This is probably the same issue that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, not a plain MachineInstr. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113983&r1=113982&r2=113983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 12:12:08 2010 @@ -1352,6 +1352,21 @@ SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; + case ARM::TSTri: { + MachineBasicBlock::const_iterator MII(MI); + if (MI->getParent()->begin() == MII) + return false; + const MachineInstr *AND = llvm::prior(MII); + if (AND->getOpcode() != ARM::ANDri) + return false; + if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && + MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) { + SrcReg = AND->getOperand(0).getReg(); + CmpValue = 0; + return true; + } + } + break; } return false; @@ -1401,6 +1416,8 @@ switch (MI->getOpcode()) { default: break; case ARM::ADDri: + case ARM::ANDri: + case ARM::t2ANDri: case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=113983&r1=113982&r2=113983&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Wed Sep 15 12:12:08 2010 @@ -17,8 +17,7 @@ %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; CHECK: and lr, r12, #3 -; CHECK-NEXT: tst r12, #3 +; CHECK: ands r12, r12, #3 ; CHECK-NEXT: beq LBB0_4 ; T2: movs r5, #3 From criswell at uiuc.edu Wed Sep 15 12:14:56 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 15 Sep 2010 17:14:56 -0000 Subject: [llvm-commits] [poolalloc] r113984 - /poolalloc/trunk/lib/DSA/Local.cpp Message-ID: <20100915171457.0AFEE2A6C12C@llvm.org> Author: criswell Date: Wed Sep 15 12:14:56 2010 New Revision: 113984 URL: http://llvm.org/viewvc/llvm-project?rev=113984&view=rev Log: Fixed bug in 176.gcc: when expanding a DSNode to 24 bytes, make sure that to expand it if it has less than 24 bytes. Modified: poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=113984&r1=113983&r2=113984&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Wed Sep 15 12:14:56 2010 @@ -694,7 +694,7 @@ // be used also to pass arguments by register. // We model this by having both the i8*'s point to an array of pointers // to the arguments. - if (N->getSize() < 1) + if (N->getSize() < 24) N->growSize(24); //sizeof the va_list struct mentioned above N->setLink(8,VAArray); //first i8* N->setLink(16,VAArray); //second i8* From stoklund at 2pi.dk Wed Sep 15 12:27:09 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 17:27:09 -0000 Subject: [llvm-commits] [llvm] r113985 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100915172709.48D902A6C12C@llvm.org> Author: stoklund Date: Wed Sep 15 12:27:09 2010 New Revision: 113985 URL: http://llvm.org/viewvc/llvm-project?rev=113985&view=rev Log: Recognize VST1q64Pseudo and VSTMQ as stack slot stores. Recognize VLD1q64Pseudo as a stack slot load. Reject these if they are loading or storing a subregister. The API (and VirtRegRewriter) doesn't know how to deal with that. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113985&r1=113984&r2=113985&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 12:27:09 2010 @@ -751,6 +751,21 @@ return MI->getOperand(0).getReg(); } break; + case ARM::VST1q64Pseudo: + if (MI->getOperand(0).isFI() && + MI->getOperand(2).getSubReg() == 0) { + FrameIndex = MI->getOperand(0).getIndex(); + return MI->getOperand(2).getReg(); + } + case ARM::VSTMQ: + if (MI->getOperand(1).isFI() && + MI->getOperand(2).isImm() && + MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && + MI->getOperand(0).getSubReg() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; } return 0; @@ -873,6 +888,13 @@ return MI->getOperand(0).getReg(); } break; + case ARM::VLD1q64Pseudo: + if (MI->getOperand(1).isFI() && + MI->getOperand(0).getSubReg() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; } return 0; From dpatel at apple.com Wed Sep 15 13:13:55 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 15 Sep 2010 18:13:55 -0000 Subject: [llvm-commits] [llvm] r113992 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100915181355.D2FDC2A6C12C@llvm.org> Author: dpatel Date: Wed Sep 15 13:13:55 2010 New Revision: 113992 URL: http://llvm.org/viewvc/llvm-project?rev=113992&view=rev Log: Check bb to ensure that alloca is in separate basic block. This fixes funcargs.exp regression reported by gdb testsuite. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=113992&r1=113991&r2=113992&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Sep 15 13:13:55 2010 @@ -4122,13 +4122,15 @@ // If variable is pinned by a alloca in dominating bb then // use StaticAllocaMap. if (const AllocaInst *AI = dyn_cast(Address)) { - DenseMap::iterator SI = - FuncInfo.StaticAllocaMap.find(AI); - if (SI != FuncInfo.StaticAllocaMap.end()) { - SDV = DAG.getDbgValue(Variable, SI->second, - 0, dl, SDNodeOrder); - DAG.AddDbgValue(SDV, 0, false); - return 0; + if (AI->getParent() != DI.getParent()) { + DenseMap::iterator SI = + FuncInfo.StaticAllocaMap.find(AI); + if (SI != FuncInfo.StaticAllocaMap.end()) { + SDV = DAG.getDbgValue(Variable, SI->second, + 0, dl, SDNodeOrder); + DAG.AddDbgValue(SDV, 0, false); + return 0; + } } } // Otherwise add undef to help track missing debug info. From grosbach at apple.com Wed Sep 15 13:47:10 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 18:47:10 -0000 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100915184711.B22272A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 13:47:08 2010 New Revision: 113996 URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev Log: Add support for floating point immediates to MC instruction printing. ARM VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... Modified: llvm/trunk/include/llvm/MC/MCInst.h llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=113996&r1=113995&r2=113996&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Wed Sep 15 13:47:08 2010 @@ -16,6 +16,7 @@ #ifndef LLVM_MC_MCINST_H #define LLVM_MC_MCINST_H +#include "llvm/ADT/APFloat.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/System/DataTypes.h" @@ -33,6 +34,7 @@ kInvalid, ///< Uninitialized. kRegister, ///< Register operand. kImmediate, ///< Immediate operand. + kFPImmediate, ///< Floating-point immediate operand. kExpr ///< Relocatable immediate operand. }; unsigned char Kind; @@ -42,13 +44,17 @@ int64_t ImmVal; const MCExpr *ExprVal; }; + // This can't go in the union due to the non-trivial copy constructor + // of APFloat. It's still only valid for Kind == kFPImmediate, though. + APFloat FPImmVal; public: - MCOperand() : Kind(kInvalid) {} + MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} bool isValid() const { return Kind != kInvalid; } bool isReg() const { return Kind == kRegister; } bool isImm() const { return Kind == kImmediate; } + bool isFPImm() const { return Kind == kFPImmediate; } bool isExpr() const { return Kind == kExpr; } /// getReg - Returns the register number. @@ -72,6 +78,16 @@ ImmVal = Val; } + const APFloat &getFPImm() const { + assert(isFPImm() && "This is not an FP immediate"); + return FPImmVal; + } + + void setFPImm(const APFloat &Val) { + assert(isFPImm() && "This is not an FP immediate"); + FPImmVal = Val; + } + const MCExpr *getExpr() const { assert(isExpr() && "This is not an expression"); return ExprVal; @@ -93,6 +109,12 @@ Op.ImmVal = Val; return Op; } + static MCOperand CreateFPImm(const APFloat &Val) { + MCOperand Op; + Op.Kind = kFPImmediate; + Op.FPImmVal = Val; + return Op; + } static MCOperand CreateExpr(const MCExpr *Val) { MCOperand Op; Op.Kind = kExpr; Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=113996&r1=113995&r2=113996&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Sep 15 13:47:08 2010 @@ -16,6 +16,7 @@ #include "ARMMCInstLower.h" //#include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/Constants.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" @@ -155,6 +156,9 @@ MCOp = LowerSymbolOperand(MO, Printer.GetBlockAddressSymbol( MO.getBlockAddress())); break; + case MachineOperand::MO_FPImmediate: + MCOp = MCOperand::CreateFPImm(MO.getFPImm()->getValueAPF()); + break; } OutMI.addOperand(MCOp); Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113996&r1=113995&r2=113996&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 13:47:08 2010 @@ -729,12 +729,12 @@ void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - O << '#' << MI->getOperand(OpNum).getImm(); + O << '#' << MI->getOperand(OpNum).getFPImm().convertToFloat(); } void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - O << '#' << MI->getOperand(OpNum).getImm(); + O << '#' << MI->getOperand(OpNum).getFPImm().convertToDouble(); } void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, From fjahanian at apple.com Wed Sep 15 13:58:05 2010 From: fjahanian at apple.com (Fariborz Jahanian) Date: Wed, 15 Sep 2010 18:58:05 -0000 Subject: [llvm-commits] [test-suite] r113997 - /test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m Message-ID: <20100915185806.536802A6C12C@llvm.org> Author: fjahanian Date: Wed Sep 15 13:58:05 2010 New Revision: 113997 URL: http://llvm.org/viewvc/llvm-project?rev=113997&view=rev Log: Added comments to explain new behavior under the default -fobjc-nonfragile-abi2. Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m?rev=113997&r1=113996&r2=113997&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m (original) +++ test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m Wed Sep 15 13:58:05 2010 @@ -85,6 +85,9 @@ @end @implementation Bot2 +// default synthesis of Bot2 synthesizes Bot2::_setX as a setter. +// So it gets called instead of Top2's _setX when Bot2 is not +// default synthesized. -(int) _getX { printf("-[ Bot2 _getX ]\n"); return 0; @@ -116,6 +119,9 @@ @end @implementation Bot3 +// default synthesis of Bot3 synthesizes Bot3::_getX as getter +// which is then called, instead of calling Top3::_getX which +// would get called had Bot3 not default synthesized. -(int) x { printf("-[ Bot3 x ]\n"); return 0; From wdietz2 at illinois.edu Wed Sep 15 13:59:41 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 18:59:41 -0000 Subject: [llvm-commits] [poolalloc] r113998 - in /poolalloc/trunk/test/pa/regression: 2010-07-09-ArgAttrMismatch.ll 2010-08-17-InvalidIterator.ll Message-ID: <20100915185942.4BA9B2A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 13:59:41 2010 New Revision: 113998 URL: http://llvm.org/viewvc/llvm-project?rev=113998&view=rev Log: Keep the output, just redirect stderr debug messages (that are apparently on by default) to stdout. Modified: poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll poolalloc/trunk/test/pa/regression/2010-08-17-InvalidIterator.ll Modified: poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll?rev=113998&r1=113997&r2=113998&view=diff ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll (original) +++ poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll Wed Sep 15 13:59:41 2010 @@ -1,4 +1,4 @@ -;RUN: paopt %s -poolalloc -disable-output |& grep "Pool allocating.*nodes!" +;RUN: paopt %s -poolalloc -disable-output 2>&1 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: poolalloc/trunk/test/pa/regression/2010-08-17-InvalidIterator.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-08-17-InvalidIterator.ll?rev=113998&r1=113997&r2=113998&view=diff ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-08-17-InvalidIterator.ll (original) +++ poolalloc/trunk/test/pa/regression/2010-08-17-InvalidIterator.ll Wed Sep 15 13:59:41 2010 @@ -1,5 +1,5 @@ ; ModuleID = 'bugpoint-reduced-simplified.bc' -;RUN: paopt %s -poolalloc -disable-output >& /dev/null +;RUN: paopt %s -poolalloc -disable-output 2>&1 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" From gvenn.cfe.dev at gmail.com Wed Sep 15 14:01:14 2010 From: gvenn.cfe.dev at gmail.com (Garrison Venn) Date: Wed, 15 Sep 2010 15:01:14 -0400 Subject: [llvm-commits] CMake flag for turning on exceptions Message-ID: <979ADF94-149D-42D6-BADE-972854615028@gmail.com> When using REQUIRES_EH = 1 in a Makefile for a LLVM directory target, is the equivalent: set(LLVM_REQUIRES_EH 1), in the analogous CMakeLists.txt? I just noticed that I did not set this, and don't have time right this second to generate a CMake build structure, though I thought I did this when I initially inserted code into the repository. I'm a little concerned about the use of two build systems becoming out of whack for infrequently used subsections of LLVM. It would be nice if we could generate one from the other; or just use one. Sorry for touching on a can of worms, and I know I probably could have generated a CMake build structure in the time it took for me to write this. Oh well, I suppose I'm pressing the self flame button. :-) Garrison From wdietz2 at illinois.edu Wed Sep 15 14:14:03 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 19:14:03 -0000 Subject: [llvm-commits] [poolalloc] r113999 - /poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c Message-ID: <20100915191403.C1BE42A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 14:14:03 2010 New Revision: 113999 URL: http://llvm.org/viewvc/llvm-project?rev=113999&view=rev Log: Added (failing) test case for indirect call to cloned functions. Illustrates issue where an original function can indirectly call a cloned function as if it were an original (making the arguments wrong). Added: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c Added: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c?rev=113999&view=auto ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c (added) +++ poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c Wed Sep 15 14:14:03 2010 @@ -0,0 +1,42 @@ +/* + * Build this file into bitcode and run poolalloc on it + * RUN: llvm-gcc -O0 %s --emit-llvm -c -o %t.bc + * RUN: paopt %t.bc -poolalloc -o %t.pa.bc 2>&1 + * RUN: llc %t.pa.bc -o %t.pa.s + * RUN: llvm-gcc %t.pa.s -o %t.pa + * + * Build the program without poolalloc: + * RUN: llvm-gcc -o %t.native %s + * + * Execute the program to verify it's correct: + * RUN: ./%t.pa >& %t.pa.out + * RUN: /%t.native >& %t.native.out + * + * Diff the two executions + * RUN: diff %t.pa.out %t.native.out + */ + +#include +#include +#include + +#define MAGIC 0xBEEF + +typedef void (*FP)(int *); + +void callee(int * v) +{ + printf("*v: %d\n", *v); + assert(*v == MAGIC); +} + +FP getFP() +{ + return callee; +} + +int main(int argc, char ** argv) +{ + int val = MAGIC; + getFP()(&val); +} From espindola at google.com Wed Sep 15 14:17:49 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 15:17:49 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add isObjectFile() In-Reply-To: References: Message-ID: So, do you consider "native object file" to include llvm bitcode files, right? You should probably make this explicit. Using a switch on the output of IdentifyFileType should accomplish that and also produce a warning if anyone adds something else is added to LLVMFileType. Also, should this function returns true for core files? Cheers, -- Rafael ?vila de Esp?ndola From ofv at wanadoo.es Wed Sep 15 14:21:36 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Wed, 15 Sep 2010 21:21:36 +0200 Subject: [llvm-commits] CMake flag for turning on exceptions References: <979ADF94-149D-42D6-BADE-972854615028@gmail.com> Message-ID: <87aanibynz.fsf@telefonica.net> Garrison Venn writes: > When using REQUIRES_EH = 1 in a Makefile for a LLVM directory target, is the > equivalent: set(LLVM_REQUIRES_EH 1), in the analogous CMakeLists.txt? At least on the LLVM part, the variable LLVM_REQUIRES_EH (if it exists) has no effect. The cmake build uses the default RTTI and exception settings of the compiler (which is ON on all cases, AFAIK) > I just noticed that I did not set this, and don't have time right this > second to generate a CMake build structure, though I thought I did > this when I initially inserted code into the repository. I'm a little > concerned about the use of two build systems becoming out of whack for > infrequently used subsections of LLVM. Although there was some effort to implement the most popular features of the traditional build on the cmake build, a total one-to-one match was not a goal. On this case, I dind't perceive too much interest on RTTI-less, exception-less builds. This can change at any moment, though. Do you *need* it? Anyone else using cmake needs that? > It would be nice if we could generate one from the other; CMake can generate makefiles, no problem. But the traditional build doesn't work outside of autoconf&&gmake, so it can't be used on environments like MSVC++. That was the main motivation for creating the CMake build. > or just use one. It is not up to me to decide that, but if the project leaders want that to happen, I'm willing to contribute the necessary time to implement whatever extra requirements required by the switch. [snip] From espindola at google.com Wed Sep 15 14:23:02 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 15:23:02 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add x86-64 COFF to IdentifyFileType In-Reply-To: References: Message-ID: On 14 September 2010 17:12, Michael Spencer wrote: > The attached patch adds x86-64 COFF to Path::IdentifyFileType. This patch is a > prerequisite for the object file library I am writing, although makes > sense in general. Coff uses the same magic for all objecs (relocatable, libs and executables)? I think this is fine anyway. Can you just add a comment saying it is x86-64 windows? There are similar comments for the other windows arches. > - Michael Spencer > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > Cheers, -- Rafael ?vila de Esp?ndola From grosbach at apple.com Wed Sep 15 14:26:06 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 19:26:06 -0000 Subject: [llvm-commits] [llvm] r114007 - in /llvm/trunk/lib/Target/ARM: ARM.h ARMBaseInfo.h Message-ID: <20100915192606.EAA662A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 14:26:06 2010 New Revision: 114007 URL: http://llvm.org/viewvc/llvm-project?rev=114007&view=rev Log: Factor out basic enums and hleper functions from ARM.h for cleaner sharing between the compiler back end and the MC libraries. Added: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Modified: llvm/trunk/lib/Target/ARM/ARM.h Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=114007&r1=114006&r2=114007&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Wed Sep 15 14:26:06 2010 @@ -15,6 +15,7 @@ #ifndef TARGET_ARM_H #define TARGET_ARM_H +#include "ARMBaseInfo.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" #include @@ -26,97 +27,6 @@ class JITCodeEmitter; class formatted_raw_ostream; -// Enums corresponding to ARM condition codes -namespace ARMCC { - // The CondCodes constants map directly to the 4-bit encoding of the - // condition field for predicated instructions. - enum CondCodes { // Meaning (integer) Meaning (floating-point) - EQ, // Equal Equal - NE, // Not equal Not equal, or unordered - HS, // Carry set >, ==, or unordered - LO, // Carry clear Less than - MI, // Minus, negative Less than - PL, // Plus, positive or zero >, ==, or unordered - VS, // Overflow Unordered - VC, // No overflow Not unordered - HI, // Unsigned higher Greater than, or unordered - LS, // Unsigned lower or same Less than or equal - GE, // Greater than or equal Greater than or equal - LT, // Less than Less than, or unordered - GT, // Greater than Greater than - LE, // Less than or equal <, ==, or unordered - AL // Always (unconditional) Always (unconditional) - }; - - inline static CondCodes getOppositeCondition(CondCodes CC) { - switch (CC) { - default: llvm_unreachable("Unknown condition code"); - case EQ: return NE; - case NE: return EQ; - case HS: return LO; - case LO: return HS; - case MI: return PL; - case PL: return MI; - case VS: return VC; - case VC: return VS; - case HI: return LS; - case LS: return HI; - case GE: return LT; - case LT: return GE; - case GT: return LE; - case LE: return GT; - } - } -} // namespace ARMCC - -inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { - switch (CC) { - default: llvm_unreachable("Unknown condition code"); - case ARMCC::EQ: return "eq"; - case ARMCC::NE: return "ne"; - case ARMCC::HS: return "hs"; - case ARMCC::LO: return "lo"; - case ARMCC::MI: return "mi"; - case ARMCC::PL: return "pl"; - case ARMCC::VS: return "vs"; - case ARMCC::VC: return "vc"; - case ARMCC::HI: return "hi"; - case ARMCC::LS: return "ls"; - case ARMCC::GE: return "ge"; - case ARMCC::LT: return "lt"; - case ARMCC::GT: return "gt"; - case ARMCC::LE: return "le"; - case ARMCC::AL: return "al"; - } -} - -namespace ARM_MB { - // The Memory Barrier Option constants map directly to the 4-bit encoding of - // the option field for memory barrier operations. - enum MemBOpt { - ST = 14, - ISH = 11, - ISHST = 10, - NSH = 7, - NSHST = 6, - OSH = 3, - OSHST = 2 - }; - - inline static const char *MemBOptToString(unsigned val) { - switch (val) { - default: llvm_unreachable("Unknown memory opetion"); - case ST: return "st"; - case ISH: return "ish"; - case ISHST: return "ishst"; - case NSH: return "nsh"; - case NSHST: return "nshst"; - case OSH: return "osh"; - case OSHST: return "oshst"; - } - } -} // namespace ARM_MB - FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel); @@ -135,14 +45,4 @@ } // end namespace llvm; -// Defines symbolic names for ARM registers. This defines a mapping from -// register name to register number. -// -#include "ARMGenRegisterNames.inc" - -// Defines symbolic names for the ARM instructions. -// -#include "ARMGenInstrNames.inc" - - #endif Added: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=114007&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (added) +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Wed Sep 15 14:26:06 2010 @@ -0,0 +1,128 @@ +//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the ARM target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef ARMBASEINFO_H +#define ARMBASEINFO_H + +#include "llvm/Support/ErrorHandling.h" + +namespace llvm { + +// Enums corresponding to ARM condition codes +namespace ARMCC { + // The CondCodes constants map directly to the 4-bit encoding of the + // condition field for predicated instructions. + enum CondCodes { // Meaning (integer) Meaning (floating-point) + EQ, // Equal Equal + NE, // Not equal Not equal, or unordered + HS, // Carry set >, ==, or unordered + LO, // Carry clear Less than + MI, // Minus, negative Less than + PL, // Plus, positive or zero >, ==, or unordered + VS, // Overflow Unordered + VC, // No overflow Not unordered + HI, // Unsigned higher Greater than, or unordered + LS, // Unsigned lower or same Less than or equal + GE, // Greater than or equal Greater than or equal + LT, // Less than Less than, or unordered + GT, // Greater than Greater than + LE, // Less than or equal <, ==, or unordered + AL // Always (unconditional) Always (unconditional) + }; + + inline static CondCodes getOppositeCondition(CondCodes CC) { + switch (CC) { + default: llvm_unreachable("Unknown condition code"); + case EQ: return NE; + case NE: return EQ; + case HS: return LO; + case LO: return HS; + case MI: return PL; + case PL: return MI; + case VS: return VC; + case VC: return VS; + case HI: return LS; + case LS: return HI; + case GE: return LT; + case LT: return GE; + case GT: return LE; + case LE: return GT; + } + } +} // namespace ARMCC + +inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { + switch (CC) { + default: llvm_unreachable("Unknown condition code"); + case ARMCC::EQ: return "eq"; + case ARMCC::NE: return "ne"; + case ARMCC::HS: return "hs"; + case ARMCC::LO: return "lo"; + case ARMCC::MI: return "mi"; + case ARMCC::PL: return "pl"; + case ARMCC::VS: return "vs"; + case ARMCC::VC: return "vc"; + case ARMCC::HI: return "hi"; + case ARMCC::LS: return "ls"; + case ARMCC::GE: return "ge"; + case ARMCC::LT: return "lt"; + case ARMCC::GT: return "gt"; + case ARMCC::LE: return "le"; + case ARMCC::AL: return "al"; + } +} + +namespace ARM_MB { + // The Memory Barrier Option constants map directly to the 4-bit encoding of + // the option field for memory barrier operations. + enum MemBOpt { + ST = 14, + ISH = 11, + ISHST = 10, + NSH = 7, + NSHST = 6, + OSH = 3, + OSHST = 2 + }; + + inline static const char *MemBOptToString(unsigned val) { + switch (val) { + default: llvm_unreachable("Unknown memory opetion"); + case ST: return "st"; + case ISH: return "ish"; + case ISHST: return "ishst"; + case NSH: return "nsh"; + case NSHST: return "nshst"; + case OSH: return "osh"; + case OSHST: return "oshst"; + } + } +} // namespace ARM_MB +} // end namespace llvm; + +// Note that the following auto-generated files only defined enum types, and +// so are safe to include here. + +// Defines symbolic names for ARM registers. This defines a mapping from +// register name to register number. +// +#include "ARMGenRegisterNames.inc" + +// Defines symbolic names for the ARM instructions. +// +#include "ARMGenInstrNames.inc" + +#endif From grosbach at apple.com Wed Sep 15 14:26:50 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 19:26:50 -0000 Subject: [llvm-commits] [llvm] r114008 - /llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Message-ID: <20100915192650.EFB1F2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 14:26:50 2010 New Revision: 114008 URL: http://llvm.org/viewvc/llvm-project?rev=114008&view=rev Log: Fix spelling typo. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=114008&r1=114007&r2=114008&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Wed Sep 15 14:26:50 2010 @@ -100,7 +100,7 @@ inline static const char *MemBOptToString(unsigned val) { switch (val) { - default: llvm_unreachable("Unknown memory opetion"); + default: llvm_unreachable("Unknown memory operation"); case ST: return "st"; case ISH: return "ish"; case ISHST: return "ishst"; From grosbach at apple.com Wed Sep 15 14:27:50 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 19:27:50 -0000 Subject: [llvm-commits] [llvm] r114009 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100915192750.A22462A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 14:27:50 2010 New Revision: 114009 URL: http://llvm.org/viewvc/llvm-project?rev=114009&view=rev Log: Reduce dependencies in the ARM MC instruction printer. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114009&r1=114008&r2=114009&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 14:27:50 2010 @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "asm-printer" -#include "ARM.h" // FIXME: FACTOR ENUMS BETTER. +#include "ARMBaseInfo.h" #include "ARMInstPrinter.h" #include "ARMAddressingModes.h" #include "llvm/MC/MCInst.h" From criswell at uiuc.edu Wed Sep 15 14:34:47 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 15 Sep 2010 19:34:47 -0000 Subject: [llvm-commits] [poolalloc] r114010 - /poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Message-ID: <20100915193449.EE0AC2A6C12C@llvm.org> Author: criswell Date: Wed Sep 15 14:34:40 2010 New Revision: 114010 URL: http://llvm.org/viewvc/llvm-project?rev=114010&view=rev Log: Fixed one of the SPEC benchmarks by making the pool node size be 1. This is because the preferred allocation size is also the alignment used in alignment checks, and it needs to be 1 to avoid spurious failures. Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp?rev=114010&r1=114009&r2=114010&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PASimple.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Wed Sep 15 14:34:40 2010 @@ -70,6 +70,35 @@ return CastInst::CreateZExtOrBitCast (V, Ty, Name, InsertPt); } +// +// Function: replacePoolArgument() +// +// Description: +// This function determines if the specified function has a pool argument that +// should be replaced, and if so, returns the index of the argument to +// replace. +// +// Inputs: +// funcname - A reference to a string containing the name of the function. +// +// Return value: +// 0 - The function does not have any pool arguments to replace. +// Otherwise, the index of the single pool argument to replace is returned. +// +static unsigned +replacePoolArgument (const std::string & funcname) { + if ((funcname == "sc.lscheck") || + (funcname == "sc.lscheckui") || + (funcname == "sc.lscheckalign") || + (funcname == "sc.lscheckalignui") || + (funcname == "sc.boundscheck") || + (funcname == "sc.boundscheckui")) { + return 1; + } + + return 0; +} + void PoolAllocateSimple::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); // Get the Target Data information and the Graphs @@ -163,7 +192,7 @@ // // Create the global pool. // - TheGlobalPool = CreateGlobalPool(32, 1, M); + TheGlobalPool = CreateGlobalPool(1, 1, M); // // Now that all call targets are available, rewrite the function bodies of @@ -408,6 +437,19 @@ Value* args[] = {TheGlobalPool, FreedNode}; CallInst::Create(PoolFree, &args[0], &args[2], "", ii); } + + // + // Transform SAFECode run-time checks. For these calls, all we need to + // do is to replace the pool argument with a pointer to the global + // pool. + // + if (CF) { + if (unsigned index = replacePoolArgument (CF->getName())) { + Type * VoidPtrTy = PointerType::getUnqual(Int8Type); + Value * Pool = castTo (TheGlobalPool, VoidPtrTy, "pool", ii); + CI->setOperand (index, Pool); + } + } } } } From wdietz2 at illinois.edu Wed Sep 15 14:43:10 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 19:43:10 -0000 Subject: [llvm-commits] [poolalloc] r114011 - /poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c Message-ID: <20100915194313.01D6B2A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 14:43:03 2010 New Revision: 114011 URL: http://llvm.org/viewvc/llvm-project?rev=114011&view=rev Log: Added duplicate of '2010-09-14-Fptr' test case, illustrating that the issue isn't just main-specific, and to catch fixes that attempt to classify it as such. Added: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c Added: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c?rev=114011&view=auto ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c (added) +++ poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c Wed Sep 15 14:43:03 2010 @@ -0,0 +1,50 @@ +// This is the same as 2010-09-Fptr.c, but does it with a helper +// to verify/illustrate that the issue is /not/ "main"-specific. +// (and to catch fixes that attempt to fix it as such) +/* + * Build this file into bitcode and run poolalloc on it + * RUN: llvm-gcc -O0 %s --emit-llvm -c -o %t.bc + * RUN: paopt %t.bc -poolalloc -o %t.pa.bc 2>&1 + * RUN: llc %t.pa.bc -o %t.pa.s + * RUN: llvm-gcc %t.pa.s -o %t.pa + * + * Build the program without poolalloc: + * RUN: llvm-gcc -o %t.native %s + * + * Execute the program to verify it's correct: + * RUN: ./%t.pa >& %t.pa.out + * RUN: /%t.native >& %t.native.out + * + * Diff the two executions + * RUN: diff %t.pa.out %t.native.out + */ + +#include +#include +#include + +#define MAGIC 0xBEEF + +typedef void (*FP)(int *); + +void callee(int * v) +{ + printf("*v: %d\n", *v); + assert(*v == MAGIC); +} + +FP getFP() +{ + return callee; +} + +void helper(int *v) +{ + getFP()(v); +} + +int main(int argc, char ** argv) +{ + int val = MAGIC; + helper(&val); +} From grosbach at apple.com Wed Sep 15 14:45:02 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 19:45:02 -0000 Subject: [llvm-commits] [llvm] r114012 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Message-ID: <20100915194504.E0A322A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 14:44:57 2010 New Revision: 114012 URL: http://llvm.org/viewvc/llvm-project?rev=114012&view=rev Log: Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check if the register is a member of the SPR register class directly instead. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=114012&r1=114011&r2=114012&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Sep 15 14:44:57 2010 @@ -1356,8 +1356,8 @@ static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP); + bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); + RegD = ARMRegisterInfo::getRegisterNumbering(RegD); if (!isSPVFP) Binary |= RegD << ARMII::RegRdShift; else { @@ -1370,8 +1370,8 @@ static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { unsigned RegN = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; - bool isSPVFP = false; - RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP); + bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); + RegN = ARMRegisterInfo::getRegisterNumbering(RegN); if (!isSPVFP) Binary |= RegN << ARMII::RegRnShift; else { @@ -1384,8 +1384,8 @@ static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { unsigned RegM = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; - bool isSPVFP = false; - RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP); + bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); + RegM = ARMRegisterInfo::getRegisterNumbering(RegM); if (!isSPVFP) Binary |= RegM; else { From grosbach at apple.com Wed Sep 15 14:52:24 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 19:52:24 -0000 Subject: [llvm-commits] [llvm] r114013 - in /llvm/trunk/lib/Target/ARM: ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h Message-ID: <20100915195225.C10222A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 14:52:17 2010 New Revision: 114013 URL: http://llvm.org/viewvc/llvm-project?rev=114013&view=rev Log: simplify getRegisterNumbering(). Remove the unused isSPVFP argument and merge the common cases. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=114013&r1=114012&r2=114013&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Sep 15 14:52:17 2010 @@ -54,95 +54,44 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames")); -unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, - bool *isSPVFP) { - if (isSPVFP) - *isSPVFP = false; - +unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned Reg) { using namespace ARM; - switch (RegEnum) { + switch (Reg) { default: llvm_unreachable("Unknown ARM register!"); - case R0: case D0: case Q0: return 0; - case R1: case D1: case Q1: return 1; - case R2: case D2: case Q2: return 2; - case R3: case D3: case Q3: return 3; - case R4: case D4: case Q4: return 4; - case R5: case D5: case Q5: return 5; - case R6: case D6: case Q6: return 6; - case R7: case D7: case Q7: return 7; - case R8: case D8: case Q8: return 8; - case R9: case D9: case Q9: return 9; - case R10: case D10: case Q10: return 10; - case R11: case D11: case Q11: return 11; - case R12: case D12: case Q12: return 12; - case SP: case D13: case Q13: return 13; - case LR: case D14: case Q14: return 14; - case PC: case D15: case Q15: return 15; - - case D16: return 16; - case D17: return 17; - case D18: return 18; - case D19: return 19; - case D20: return 20; - case D21: return 21; - case D22: return 22; - case D23: return 23; - case D24: return 24; - case D25: return 25; - case D26: return 26; - case D27: return 27; - case D28: return 28; - case D29: return 29; - case D30: return 30; - case D31: return 31; - - case S0: case S1: case S2: case S3: - case S4: case S5: case S6: case S7: - case S8: case S9: case S10: case S11: - case S12: case S13: case S14: case S15: - case S16: case S17: case S18: case S19: - case S20: case S21: case S22: case S23: - case S24: case S25: case S26: case S27: - case S28: case S29: case S30: case S31: { - if (isSPVFP) - *isSPVFP = true; - switch (RegEnum) { - default: return 0; // Avoid compile time warning. - case S0: return 0; - case S1: return 1; - case S2: return 2; - case S3: return 3; - case S4: return 4; - case S5: return 5; - case S6: return 6; - case S7: return 7; - case S8: return 8; - case S9: return 9; - case S10: return 10; - case S11: return 11; - case S12: return 12; - case S13: return 13; - case S14: return 14; - case S15: return 15; - case S16: return 16; - case S17: return 17; - case S18: return 18; - case S19: return 19; - case S20: return 20; - case S21: return 21; - case S22: return 22; - case S23: return 23; - case S24: return 24; - case S25: return 25; - case S26: return 26; - case S27: return 27; - case S28: return 28; - case S29: return 29; - case S30: return 30; - case S31: return 31; - } - } + case R0: case S0: case D0: case Q0: return 0; + case R1: case S1: case D1: case Q1: return 1; + case R2: case S2: case D2: case Q2: return 2; + case R3: case S3: case D3: case Q3: return 3; + case R4: case S4: case D4: case Q4: return 4; + case R5: case S5: case D5: case Q5: return 5; + case R6: case S6: case D6: case Q6: return 6; + case R7: case S7: case D7: case Q7: return 7; + case R8: case S8: case D8: case Q8: return 8; + case R9: case S9: case D9: case Q9: return 9; + case R10: case S10: case D10: case Q10: return 10; + case R11: case S11: case D11: case Q11: return 11; + case R12: case S12: case D12: case Q12: return 12; + case SP: case S13: case D13: case Q13: return 13; + case LR: case S14: case D14: case Q14: return 14; + case PC: case S15: case D15: case Q15: return 15; + + case S16: case D16: return 16; + case S17: case D17: return 17; + case S18: case D18: return 18; + case S19: case D19: return 19; + case S20: case D20: return 20; + case S21: case D21: return 21; + case S22: case D22: return 22; + case S23: case D23: return 23; + case S24: case D24: return 24; + case S25: case D25: return 25; + case S26: case D26: return 26; + case S27: case D27: return 27; + case S28: case D28: return 28; + case S29: case D29: return 29; + case S30: case D30: return 30; + case S31: case D31: return 31; } } Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=114013&r1=114012&r2=114013&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Wed Sep 15 14:52:17 2010 @@ -66,10 +66,8 @@ public: /// getRegisterNumbering - Given the enum value for some register, e.g. - /// ARM::LR, return the number that it corresponds to (e.g. 14). It - /// also returns true in isSPVFP if the register is a single precision - /// VFP register. - static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0); + /// ARM::LR, return the number that it corresponds to (e.g. 14). + static unsigned getRegisterNumbering(unsigned Reg); /// Code Generation virtual methods... const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; From dalej at apple.com Wed Sep 15 15:05:19 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 15 Sep 2010 13:05:19 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <20100915184711.B22272A6C12C@llvm.org> References: <20100915184711.B22272A6C12C@llvm.org> Message-ID: On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: > Author: grosbach > Date: Wed Sep 15 13:47:08 2010 > New Revision: 113996 > > URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev > Log: > Add support for floating point immediates to MC instruction printing. ARM > VFP instructions use it for loading some constants, so implement that > handling. > > Not thrilled with adding a member to MCOperand, but not sure there's much of > a better option that's not pretty fragile (like putting a double in the > union instead and just assuming that's good enough). Suggestions welcome... This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. From eli.friedman at gmail.com Wed Sep 15 15:08:06 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 15 Sep 2010 20:08:06 -0000 Subject: [llvm-commits] [llvm] r114015 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Message-ID: <20100915200807.853652A6C12C@llvm.org> Author: efriedma Date: Wed Sep 15 15:08:03 2010 New Revision: 114015 URL: http://llvm.org/viewvc/llvm-project?rev=114015&view=rev Log: PR7959: Handle negative scales in GEPs correctly in BasicAA for non-64-bit targets. Added: llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=114015&r1=114014&r2=114015&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Wed Sep 15 15:08:03 2010 @@ -386,8 +386,8 @@ // The GEP index scale ("Scale") scales C1*V+C2, yielding (C1*V+C2)*Scale. // This gives us an aggregate computation of (C1*Scale)*V + C2*Scale. - BaseOffs += IndexOffset.getZExtValue()*Scale; - Scale *= IndexScale.getZExtValue(); + BaseOffs += IndexOffset.getSExtValue()*Scale; + Scale *= IndexScale.getSExtValue(); // If we already had an occurrance of this index variable, merge this @@ -407,7 +407,7 @@ // pointer size. if (unsigned ShiftBits = 64-TD->getPointerSizeInBits()) { Scale <<= ShiftBits; - Scale >>= ShiftBits; + Scale = (int64_t)Scale >> ShiftBits; } if (Scale) { Added: llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll?rev=114015&view=auto ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll (added) +++ llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Wed Sep 15 15:08:03 2010 @@ -0,0 +1,15 @@ +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 may alias} +; PR7959 + +target datalayout = "e-p:32:32:32" + +define i32 @test(i32* %tab, i32 %indvar) nounwind { + %tmp31 = mul i32 %indvar, -2 + %tmp32 = add i32 %tmp31, 30 + %t.5 = getelementptr i32* %tab, i32 %tmp32 + %loada = load i32* %tab + store i32 0, i32* %t.5 + %loadb = load i32* %tab + %rval = add i32 %loada, %loadb + ret i32 %rval +} From scanon at apple.com Wed Sep 15 15:19:36 2010 From: scanon at apple.com (Stephen Canon) Date: Wed, 15 Sep 2010 13:19:36 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: References: <20100915184711.B22272A6C12C@llvm.org> Message-ID: On Sep 15, 2010, at 1:05 PM, Dale Johannesen wrote: > On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Sep 15 13:47:08 2010 >> New Revision: 113996 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >> Log: >> Add support for floating point immediates to MC instruction printing. ARM >> VFP instructions use it for loading some constants, so implement that >> handling. >> >> Not thrilled with adding a member to MCOperand, but not sure there's much of >> a better option that's not pretty fragile (like putting a double in the >> union instead and just assuming that's good enough). Suggestions welcome... > > This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. Fortunately, ARM doesn't support NaN or infinity as FP immediates; the allowed FP immediates of the form: +/-(1 + m/16)*2^e where m is an integer in [0,15] and e is an integer in [-3,4]. I agree with Dale that the hex format would be ideal if the assembler will swallow it. Leave conversions between binary and decimal out of it. From grosbach at apple.com Wed Sep 15 15:22:13 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 13:22:13 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: References: <20100915184711.B22272A6C12C@llvm.org> Message-ID: <73079B90-A684-4BB3-B5DD-B3E1F0D578CA@apple.com> On Sep 15, 2010, at 1:19 PM, Stephen Canon wrote: > On Sep 15, 2010, at 1:05 PM, Dale Johannesen wrote: > >> On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Wed Sep 15 13:47:08 2010 >>> New Revision: 113996 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >>> Log: >>> Add support for floating point immediates to MC instruction printing. ARM >>> VFP instructions use it for loading some constants, so implement that >>> handling. >>> >>> Not thrilled with adding a member to MCOperand, but not sure there's much of >>> a better option that's not pretty fragile (like putting a double in the >>> union instead and just assuming that's good enough). Suggestions welcome... >> >> This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. > > Fortunately, ARM doesn't support NaN or infinity as FP immediates; the allowed FP immediates of the form: > > +/-(1 + m/16)*2^e > > where m is an integer in [0,15] and e is an integer in [-3,4]. > > I agree with Dale that the hex format would be ideal if the assembler will swallow it. Leave conversions between binary and decimal out of it. I wish I could, but unified syntax requires the immediate be a floating point immediate. Pre-unified syntax it was a binary 8 bit immediate as encoded into the instruction. I wish it hadn't been changed, but... -Jim From grosbach at apple.com Wed Sep 15 15:26:27 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 20:26:27 -0000 Subject: [llvm-commits] [llvm] r114016 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMBaseInfo.h ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h ARMCodeEmitter.cpp ARMJITInfo.cpp ARMLoadStoreOptimizer.cpp Message-ID: <20100915202628.E97D32A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 15:26:25 2010 New Revision: 114016 URL: http://llvm.org/viewvc/llvm-project?rev=114016&view=rev Log: move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper functions in ARMBaseInfo.h so it can be used in the MC library as well. For anything bigger than this, we may want a means to have a small support library for shared helper functions like this. Cross that bridge when we come to it. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMBaseInfo.h llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 15 15:26:25 2010 @@ -344,7 +344,7 @@ << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi) << '}'; } else if (Modifier && strcmp(Modifier, "lane") == 0) { - unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); + unsigned RegNum = getARMRegisterNumbering(Reg); unsigned DReg = TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass); Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Wed Sep 15 15:26:25 2010 @@ -19,6 +19,18 @@ #include "llvm/Support/ErrorHandling.h" +// Note that the following auto-generated files only defined enum types, and +// so are safe to include here. + +// Defines symbolic names for ARM registers. This defines a mapping from +// register name to register number. +// +#include "ARMGenRegisterNames.inc" + +// Defines symbolic names for the ARM instructions. +// +#include "ARMGenInstrNames.inc" + namespace llvm { // Enums corresponding to ARM condition codes @@ -111,18 +123,50 @@ } } } // namespace ARM_MB -} // end namespace llvm; -// Note that the following auto-generated files only defined enum types, and -// so are safe to include here. - -// Defines symbolic names for ARM registers. This defines a mapping from -// register name to register number. -// -#include "ARMGenRegisterNames.inc" +/// getARMRegisterNumbering - Given the enum value for some register, e.g. +/// ARM::LR, return the number that it corresponds to (e.g. 14). +inline static unsigned getARMRegisterNumbering(unsigned Reg) { + using namespace ARM; + switch (Reg) { + default: + llvm_unreachable("Unknown ARM register!"); + case R0: case S0: case D0: case Q0: return 0; + case R1: case S1: case D1: case Q1: return 1; + case R2: case S2: case D2: case Q2: return 2; + case R3: case S3: case D3: case Q3: return 3; + case R4: case S4: case D4: case Q4: return 4; + case R5: case S5: case D5: case Q5: return 5; + case R6: case S6: case D6: case Q6: return 6; + case R7: case S7: case D7: case Q7: return 7; + case R8: case S8: case D8: case Q8: return 8; + case R9: case S9: case D9: case Q9: return 9; + case R10: case S10: case D10: case Q10: return 10; + case R11: case S11: case D11: case Q11: return 11; + case R12: case S12: case D12: case Q12: return 12; + case SP: case S13: case D13: case Q13: return 13; + case LR: case S14: case D14: case Q14: return 14; + case PC: case S15: case D15: case Q15: return 15; + + case S16: case D16: return 16; + case S17: case D17: return 17; + case S18: case D18: return 18; + case S19: case D19: return 19; + case S20: case D20: return 20; + case S21: case D21: return 21; + case S22: case D22: return 22; + case S23: case D23: return 23; + case S24: case D24: return 24; + case S25: case D25: return 25; + case S26: case D26: return 26; + case S27: case D27: return 27; + case S28: case D28: return 28; + case S29: case D29: return 29; + case S30: case D30: return 30; + case S31: case D31: return 31; + } +} -// Defines symbolic names for the ARM instructions. -// -#include "ARMGenInstrNames.inc" +} // end namespace llvm; #endif Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Sep 15 15:26:25 2010 @@ -54,46 +54,6 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames")); -unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned Reg) { - using namespace ARM; - switch (Reg) { - default: - llvm_unreachable("Unknown ARM register!"); - case R0: case S0: case D0: case Q0: return 0; - case R1: case S1: case D1: case Q1: return 1; - case R2: case S2: case D2: case Q2: return 2; - case R3: case S3: case D3: case Q3: return 3; - case R4: case S4: case D4: case Q4: return 4; - case R5: case S5: case D5: case Q5: return 5; - case R6: case S6: case D6: case Q6: return 6; - case R7: case S7: case D7: case Q7: return 7; - case R8: case S8: case D8: case Q8: return 8; - case R9: case S9: case D9: case Q9: return 9; - case R10: case S10: case D10: case Q10: return 10; - case R11: case S11: case D11: case Q11: return 11; - case R12: case S12: case D12: case Q12: return 12; - case SP: case S13: case D13: case Q13: return 13; - case LR: case S14: case D14: case Q14: return 14; - case PC: case S15: case D15: case Q15: return 15; - - case S16: case D16: return 16; - case S17: case D17: return 17; - case S18: case D18: return 18; - case S19: case D19: return 19; - case S20: case D20: return 20; - case S21: case D21: return 21; - case S22: case D22: return 22; - case S23: case D23: return 23; - case S24: case D24: return 24; - case S25: case D25: return 25; - case S26: case D26: return 26; - case S27: case D27: return 27; - case S28: case D28: return 28; - case S29: case D29: return 29; - case S30: case D30: return 30; - case S31: case D31: return 31; - } -} ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Wed Sep 15 15:26:25 2010 @@ -65,10 +65,6 @@ unsigned getOpcode(int Op) const; public: - /// getRegisterNumbering - Given the enum value for some register, e.g. - /// ARM::LR, return the number that it corresponds to (e.g. 14). - static unsigned getRegisterNumbering(unsigned Reg); - /// Code Generation virtual methods... const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Sep 15 15:26:25 2010 @@ -264,7 +264,7 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) { if (MO.isReg()) - return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); + return getARMRegisterNumbering(MO.getReg()); else if (MO.isImm()) return static_cast(MO.getImm()); else if (MO.isGlobal()) @@ -596,7 +596,7 @@ Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; // Encode Rn which is PC. - Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; + Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; // Encode the displacement. Binary |= 1 << ARMII::I_BitShift; @@ -785,8 +785,7 @@ if (Rs) { // Encode Rs bit[11:8]. assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); - return Binary | - (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift); + return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); } // Encode shift_imm bit[11:7]. @@ -837,8 +836,7 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; else if (ImplicitRd) // Special handling for implicit use (e.g. PC). - Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) - << ARMII::RegRdShift); + Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); if (TID.Opcode == ARM::MOVi16) { // Get immediate from MI. @@ -888,8 +886,7 @@ if (!isUnary) { if (ImplicitRn) // Special handling for implicit use (e.g. PC). - Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) - << ARMII::RegRnShift); + Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); else { Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; ++OpIdx; @@ -906,7 +903,7 @@ if (MO.isReg()) { // Encode register Rm. - emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg())); + emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); return; } @@ -942,16 +939,14 @@ // Set first operand if (ImplicitRd) // Special handling for implicit use (e.g. PC). - Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) - << ARMII::RegRdShift); + Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); else Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; // Set second operand if (ImplicitRn) // Special handling for implicit use (e.g. PC). - Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) - << ARMII::RegRnShift); + Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); else Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; @@ -978,7 +973,7 @@ Binary |= 1 << ARMII::I_BitShift; assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); // Set bit[3:0] to the corresponding Rm register - Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); + Binary |= getARMRegisterNumbering(MO2.getReg()); // If this instr is in scaled register offset/index instruction, set // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. @@ -1022,8 +1017,7 @@ // Set second operand if (ImplicitRn) // Special handling for implicit use (e.g. PC). - Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) - << ARMII::RegRnShift); + Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); else Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; @@ -1042,7 +1036,7 @@ // If this instr is in register offset/index encoding, set bit[3:0] // to the corresponding Rm register. if (MO2.getReg()) { - Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); + Binary |= getARMRegisterNumbering(MO2.getReg()); emitWordLE(Binary); return; } @@ -1108,7 +1102,7 @@ const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || MO.isImplicit()) break; - unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); + unsigned RegNum = getARMRegisterNumbering(MO.getReg()); assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && RegNum < 16); Binary |= 0x1 << RegNum; @@ -1345,7 +1339,7 @@ if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) // The return register is LR. - Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); + Binary |= getARMRegisterNumbering(ARM::LR); else // otherwise, set the return register Binary |= getMachineOpValue(MI, 0); @@ -1357,7 +1351,7 @@ unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); - RegD = ARMRegisterInfo::getRegisterNumbering(RegD); + RegD = getARMRegisterNumbering(RegD); if (!isSPVFP) Binary |= RegD << ARMII::RegRdShift; else { @@ -1371,7 +1365,7 @@ unsigned RegN = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); - RegN = ARMRegisterInfo::getRegisterNumbering(RegN); + RegN = getARMRegisterNumbering(RegN); if (!isSPVFP) Binary |= RegN << ARMII::RegRnShift; else { @@ -1385,7 +1379,7 @@ unsigned RegM = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); - RegM = ARMRegisterInfo::getRegisterNumbering(RegM); + RegM = getARMRegisterNumbering(RegM); if (!isSPVFP) Binary |= RegM; else { @@ -1592,8 +1586,7 @@ case ARM::VMSR: { const MachineOperand &MO0 = MI.getOperand(0); // Encode Rt. - Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg()) - << ARMII::RegRdShift; + Binary |= getARMRegisterNumbering(MO0.getReg()) << ARMII::RegRdShift; break; } @@ -1628,7 +1621,7 @@ static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD); + RegD = getARMRegisterNumbering(RegD); Binary |= (RegD & 0xf) << ARMII::RegRdShift; Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; return Binary; @@ -1637,7 +1630,7 @@ static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { unsigned RegN = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; - RegN = ARMRegisterInfo::getRegisterNumbering(RegN); + RegN = getARMRegisterNumbering(RegN); Binary |= (RegN & 0xf) << ARMII::RegRnShift; Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; return Binary; @@ -1646,7 +1639,7 @@ static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { unsigned RegM = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; - RegM = ARMRegisterInfo::getRegisterNumbering(RegM); + RegM = getARMRegisterNumbering(RegM); Binary |= (RegM & 0xf); Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; return Binary; @@ -1680,7 +1673,7 @@ Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); - RegT = ARMRegisterInfo::getRegisterNumbering(RegT); + RegT = getARMRegisterNumbering(RegT); Binary |= (RegT << ARMII::RegRdShift); Binary |= encodeNEONRn(MI, RegNOpIdx); @@ -1709,7 +1702,7 @@ Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; unsigned RegT = MI.getOperand(1).getReg(); - RegT = ARMRegisterInfo::getRegisterNumbering(RegT); + RegT = getARMRegisterNumbering(RegT); Binary |= (RegT << ARMII::RegRdShift); Binary |= encodeNEONRn(MI, 0); emitWordLE(Binary); Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Wed Sep 15 15:26:25 2010 @@ -290,7 +290,7 @@ *((intptr_t*)RelocPos) |= ResultPtr; // Set register Rn to PC. *((intptr_t*)RelocPos) |= - ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; + getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; break; } case ARM::reloc_arm_pic_jt: Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=114016&r1=114015&r2=114016&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Sep 15 15:26:25 2010 @@ -349,7 +349,7 @@ const MachineOperand &PMO = Loc->getOperand(0); unsigned PReg = PMO.getReg(); unsigned PRegNum = PMO.isUndef() ? UINT_MAX - : ARMRegisterInfo::getRegisterNumbering(PReg); + : getARMRegisterNumbering(PReg); unsigned Count = 1; for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) { @@ -357,7 +357,7 @@ const MachineOperand &MO = MemOps[i].MBBI->getOperand(0); unsigned Reg = MO.getReg(); unsigned RegNum = MO.isUndef() ? UINT_MAX - : ARMRegisterInfo::getRegisterNumbering(Reg); + : getARMRegisterNumbering(Reg); // Register numbers must be in ascending order. For VFP, the registers // must also be consecutive and there is a limit of 16 double-word // registers per instruction. From scanon at apple.com Wed Sep 15 15:28:23 2010 From: scanon at apple.com (Stephen Canon) Date: Wed, 15 Sep 2010 13:28:23 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <73079B90-A684-4BB3-B5DD-B3E1F0D578CA@apple.com> References: <20100915184711.B22272A6C12C@llvm.org> <73079B90-A684-4BB3-B5DD-B3E1F0D578CA@apple.com> Message-ID: <368ACC98-CDAE-4230-A12F-7E1A8AFDFBBA@apple.com> On Sep 15, 2010, at 1:22 PM, Jim Grosbach wrote: > I wish I could, but unified syntax requires the immediate be a floating point immediate. Pre-unified syntax it was a binary 8 bit immediate as encoded into the instruction. I wish it hadn't been changed, but... Does it forbid a hex-encoded FP immediate? #0x1.ap2, for example? From grosbach at apple.com Wed Sep 15 15:31:38 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 13:31:38 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <368ACC98-CDAE-4230-A12F-7E1A8AFDFBBA@apple.com> References: <20100915184711.B22272A6C12C@llvm.org> <73079B90-A684-4BB3-B5DD-B3E1F0D578CA@apple.com> <368ACC98-CDAE-4230-A12F-7E1A8AFDFBBA@apple.com> Message-ID: <71E9B4E5-0F5A-4528-81B2-66F1D02A76DA@apple.com> On Sep 15, 2010, at 1:28 PM, Stephen Canon wrote: > On Sep 15, 2010, at 1:22 PM, Jim Grosbach wrote: > >> I wish I could, but unified syntax requires the immediate be a floating point immediate. Pre-unified syntax it was a binary 8 bit immediate as encoded into the instruction. I wish it hadn't been changed, but... > > Does it forbid a hex-encoded FP immediate? #0x1.ap2, for example? Yes. :( x.s:3:garbage following instruction -- `vmov.f32 s0,#0x1.ap2' For context, note that nothing in this patch is changing how we're printing FP immediates for these instructions. Rather, this is implementing for MC-based printing the same logic that's currently used for the old assembly printer. That's certainly not to say that there isn't room for improvement. :) -Jim From fjahanian at apple.com Wed Sep 15 15:39:23 2010 From: fjahanian at apple.com (Fariborz Jahanian) Date: Wed, 15 Sep 2010 20:39:23 -0000 Subject: [llvm-commits] [test-suite] r114017 - /test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output Message-ID: <20100915203924.41FE42A6C12C@llvm.org> Author: fjahanian Date: Wed Sep 15 15:39:21 2010 New Revision: 114017 URL: http://llvm.org/viewvc/llvm-project?rev=114017&view=rev Log: Change output file to correspond to new non-fragile-abi2 default option. Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output?rev=114017&r1=114016&r2=114017&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output (original) +++ test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output Wed Sep 15 15:39:21 2010 @@ -3,8 +3,6 @@ -[ Bot1 _getX ] -[ Bot1 _setX: 10 ] -[ Bot2 _getX ] --[ Top2 _setX: 10 ] --[ Top3 _getX ] -[ Bot3 _setX: 10 ] -[ Bot4 _getX ] -[ Top4 _setX: 10 ] From scanon at apple.com Wed Sep 15 15:52:13 2010 From: scanon at apple.com (Stephen Canon) Date: Wed, 15 Sep 2010 13:52:13 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: References: <20100915184711.B22272A6C12C@llvm.org> Message-ID: <6D478F55-916F-47A7-BEB3-ADD9F671C21B@apple.com> On Sep 15, 2010, at 1:05 PM, Dale Johannesen wrote: > On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Sep 15 13:47:08 2010 >> New Revision: 113996 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >> Log: >> Add support for floating point immediates to MC instruction printing. ARM >> VFP instructions use it for loading some constants, so implement that >> handling. >> >> Not thrilled with adding a member to MCOperand, but not sure there's much of >> a better option that's not pretty fragile (like putting a double in the >> union instead and just assuming that's good enough). Suggestions welcome... > > This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. My reading of the C++ standard is that << does not guarantee that the value will be printed exactly. You need 7 digits after the decimal point in order to print all expressible immediates exactly, but you only get 6 digits. A test on the immediate value 0x1.1p-3 seems to confirm this. - Steve From espindola at google.com Wed Sep 15 15:57:13 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 16:57:13 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: References: Message-ID: On 14 September 2010 17:18, Michael Spencer wrote: > The attached patch adds the SwapByteOrder function template to System. > This patch is a > prerequisite for the object file library I am writing. > > I want to replace the functions in MathExtras.h with SwapByteOrder > because it is a generic implementation that makes it easier to write > generic byte order independent code. This patch has no functionality > changes. > > The optimized versions are platform dependent, and thus belong in System anyway. Do you have an use for sizes other than 16, 32,and 64 or are you adding support just in case? What happens if a signed integer is used, we get the generic code? Maybe it is better if it failed to compile? > - Michael Spencer > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > Cheers, -- Rafael ?vila de Esp?ndola From grosbach at apple.com Wed Sep 15 16:04:56 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 21:04:56 -0000 Subject: [llvm-commits] [llvm] r114021 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/neon-tests.txt Message-ID: <20100915210456.3C89F2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 16:04:54 2010 New Revision: 114021 URL: http://llvm.org/viewvc/llvm-project?rev=114021&view=rev Log: Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=114021&r1=114020&r2=114021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Sep 15 16:04:54 2010 @@ -1573,8 +1573,7 @@ } // A7.5.1 -#if 0 -static uint64_t VFPExpandImm(unsigned char byte, unsigned N) { +static APInt VFPExpandImm(unsigned char byte, unsigned N) { assert(N == 32 || N == 64); uint64_t Result; @@ -1593,9 +1592,8 @@ else Result |= 0x1L << 62; } - return Result; + return APInt(N, Result); } -#endif // VFP Unary Format Instructions: // @@ -1972,10 +1970,11 @@ // Extract/decode the f64/f32 immediate. if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { - // The asm syntax specifies the before-expanded . - // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), - // Opcode == ARM::FCONSTD ? 64 : 32) - MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0))); + // The asm syntax specifies the floating point value, not the 8-bit literal. + APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), + Opcode == ARM::FCONSTD ? 64 : 32); + MI.addOperand(MCOperand::CreateFPImm(APFloat(immRaw, true))); + ++OpIdx; } Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=114021&r1=114020&r2=114021&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Wed Sep 15 16:04:54 2010 @@ -51,3 +51,5 @@ # CHECK: vtbx.8 d18, {d4, d5, d6}, d7 0x47 0x2a 0xf4 0xf3 +# CHECK: vmov.f32 s0, #5.000000e-01 +0x00 0x0a 0xb6 0xee From dirty at apple.com Wed Sep 15 16:08:45 2010 From: dirty at apple.com (Cameron Esfahani) Date: Wed, 15 Sep 2010 14:08:45 -0700 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple In-Reply-To: <4C908A47.9070103@free.fr> References: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> <4C908A47.9070103@free.fr> Message-ID: On Sep 15, 2010, at 1:56 AM, Duncan Sands wrote: > Hi Cameron, > >> + explicit Triple(StringRef ArchStr, StringRef VendorStr, StringRef OSStr, >> + StringRef EnvironmentStr ) > > there is an extraneous space before the closing bracket. > Yes >> + /// getEnvironment - Get the parsed environment type of this triple. >> + EnvironmentType getEnvironment() const { >> + if (!isInitialized()) Parse(); >> + if (!hasEnvironment()) return UnknownEnvironment; > > If there is no environment, won't Environment be equal to UnknownEnvironment, > making the above line useless? > Fixed >> + return Environment; >> + } >> + > > As well as the above, you should also add some unit tests and enhance the > normalize method to take the environment into account. > I'm not sure how to write a test to test this functionality. Any suggestions? > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits Cameron Esfahani dirty at apple.com "You only live once, and the way I live, once is enough" Frank Sinatra From espindola at google.com Wed Sep 15 16:15:16 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 17:15:16 -0400 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple In-Reply-To: References: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> <4C908A47.9070103@free.fr> Message-ID: > I'm not sure how to write a test to test this functionality. ?Any suggestions? Can you add to unittests/ADT/TripleTest.cpp? > Cameron Esfahani > dirty at apple.com > > "You only live once, and the way I live, once is enough" > > Frank Sinatra Cheers, -- Rafael ?vila de Esp?ndola From wendling at apple.com Wed Sep 15 16:23:05 2010 From: wendling at apple.com (Bill Wendling) Date: Wed, 15 Sep 2010 14:23:05 -0700 Subject: [llvm-commits] [llvm] r113985 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp In-Reply-To: <20100915172709.48D902A6C12C@llvm.org> References: <20100915172709.48D902A6C12C@llvm.org> Message-ID: On Sep 15, 2010, at 10:27 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Wed Sep 15 12:27:09 2010 > New Revision: 113985 > > URL: http://llvm.org/viewvc/llvm-project?rev=113985&view=rev > Log: > Recognize VST1q64Pseudo and VSTMQ as stack slot stores. > Recognize VLD1q64Pseudo as a stack slot load. > > Reject these if they are loading or storing a subregister. The API (and > VirtRegRewriter) doesn't know how to deal with that. > > Modified: > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113985&r1=113984&r2=113985&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 12:27:09 2010 > @@ -751,6 +751,21 @@ > return MI->getOperand(0).getReg(); > } > break; > + case ARM::VST1q64Pseudo: > + if (MI->getOperand(0).isFI() && > + MI->getOperand(2).getSubReg() == 0) { > + FrameIndex = MI->getOperand(0).getIndex(); > + return MI->getOperand(2).getReg(); > + } Should there be a "break" statement here? If not maybe a comment? :-) -bw > + case ARM::VSTMQ: > + if (MI->getOperand(1).isFI() && > + MI->getOperand(2).isImm() && > + MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && > + MI->getOperand(0).getSubReg() == 0) { > + FrameIndex = MI->getOperand(1).getIndex(); > + return MI->getOperand(0).getReg(); > + } > + break; > } > > return 0; > @@ -873,6 +888,13 @@ > return MI->getOperand(0).getReg(); > } > break; > + case ARM::VLD1q64Pseudo: > + if (MI->getOperand(1).isFI() && > + MI->getOperand(0).getSubReg() == 0) { > + FrameIndex = MI->getOperand(1).getIndex(); > + return MI->getOperand(0).getReg(); > + } > + break; > } > > return 0; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Wed Sep 15 16:24:27 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 15 Sep 2010 14:24:27 -0700 Subject: [llvm-commits] [llvm] r113985 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp In-Reply-To: <20100915172709.48D902A6C12C@llvm.org> References: <20100915172709.48D902A6C12C@llvm.org> Message-ID: <7F39DB7F-31AA-4825-9EFA-009C3C2E9D5F@apple.com> You missed VLDMQ. Will you add that? On Sep 15, 2010, at 10:27 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Wed Sep 15 12:27:09 2010 > New Revision: 113985 > > URL: http://llvm.org/viewvc/llvm-project?rev=113985&view=rev > Log: > Recognize VST1q64Pseudo and VSTMQ as stack slot stores. > Recognize VLD1q64Pseudo as a stack slot load. > > Reject these if they are loading or storing a subregister. The API (and > VirtRegRewriter) doesn't know how to deal with that. > > Modified: > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113985&r1=113984&r2=113985&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 12:27:09 2010 > @@ -751,6 +751,21 @@ > return MI->getOperand(0).getReg(); > } > break; > + case ARM::VST1q64Pseudo: > + if (MI->getOperand(0).isFI() && > + MI->getOperand(2).getSubReg() == 0) { > + FrameIndex = MI->getOperand(0).getIndex(); > + return MI->getOperand(2).getReg(); > + } > + case ARM::VSTMQ: > + if (MI->getOperand(1).isFI() && > + MI->getOperand(2).isImm() && > + MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && > + MI->getOperand(0).getSubReg() == 0) { > + FrameIndex = MI->getOperand(1).getIndex(); > + return MI->getOperand(0).getReg(); > + } > + break; > } > > return 0; > @@ -873,6 +888,13 @@ > return MI->getOperand(0).getReg(); > } > break; > + case ARM::VLD1q64Pseudo: > + if (MI->getOperand(1).isFI() && > + MI->getOperand(0).getSubReg() == 0) { > + FrameIndex = MI->getOperand(1).getIndex(); > + return MI->getOperand(0).getReg(); > + } > + break; > } > > return 0; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From fjahanian at apple.com Wed Sep 15 16:25:37 2010 From: fjahanian at apple.com (Fariborz Jahanian) Date: Wed, 15 Sep 2010 21:25:37 -0000 Subject: [llvm-commits] [test-suite] r114022 - in /test-suite/trunk/SingleSource/UnitTests/ObjC: dot-syntax-1.m dot-syntax-1.reference_output Message-ID: <20100915212537.2B7E02A6C12C@llvm.org> Author: fjahanian Date: Wed Sep 15 16:25:36 2010 New Revision: 114022 URL: http://llvm.org/viewvc/llvm-project?rev=114022&view=rev Log: Modified test case to generate same output with old and new nonfragile abi. Thanks Daniel for the suggestion. Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m?rev=114022&r1=114021&r2=114022&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m (original) +++ test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.m Wed Sep 15 16:25:36 2010 @@ -85,9 +85,7 @@ @end @implementation Bot2 -// default synthesis of Bot2 synthesizes Bot2::_setX as a setter. -// So it gets called instead of Top2's _setX when Bot2 is not -// default synthesized. + at dynamic x; -(int) _getX { printf("-[ Bot2 _getX ]\n"); return 0; @@ -119,9 +117,7 @@ @end @implementation Bot3 -// default synthesis of Bot3 synthesizes Bot3::_getX as getter -// which is then called, instead of calling Top3::_getX which -// would get called had Bot3 not default synthesized. + at dynamic x; -(int) x { printf("-[ Bot3 x ]\n"); return 0; Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output?rev=114022&r1=114021&r2=114022&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output (original) +++ test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-1.reference_output Wed Sep 15 16:25:36 2010 @@ -3,6 +3,8 @@ -[ Bot1 _getX ] -[ Bot1 _setX: 10 ] -[ Bot2 _getX ] +-[ Top2 _setX: 10 ] +-[ Top3 _getX ] -[ Bot3 _setX: 10 ] -[ Bot4 _getX ] -[ Top4 _setX: 10 ] From bigcheesegs at gmail.com Wed Sep 15 16:32:20 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 15 Sep 2010 17:32:20 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add isObjectFile() In-Reply-To: References: Message-ID: On Wed, Sep 15, 2010 at 3:17 PM, Rafael Espindola wrote: > So, do you consider "native object file" to include llvm bitcode > files, right? You should probably make this explicit. Using a switch > on the output of IdentifyFileType should accomplish that and also > produce a warning if anyone adds something else is added to > LLVMFileType. > > Also, should this function returns true for core files? > > Cheers, > -- > Rafael ?vila de Esp?ndola > I'm still not 100% sure how to treat bitcode files. It will really depend on how well they fit the API. What I don't want is to end up with special case code everywhere just for bitcode files. Optimally a linker would be able to treat it just like every other object file during symbol resolution, and then assemble the functions/data that matter before layout and output. The issue I have with explicitly listing every file type is that IdentifyFileType returns more than just MachO or ELF. It also reads the headers and tries to figure out a bunch of stuff that I don't care about when constructing. What I would actually prefer is adding enum members like ELF_ObjectStart_FileType and ELF_ObjectEnd_FileType. With all the subtypes in the middle. That way more file types can be added without requiring updating other places that can already deal with whatever is being added. And core files are definitely object files. Thanks for the review! - Michael Spencer From stoklund at 2pi.dk Wed Sep 15 16:33:34 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 14:33:34 -0700 Subject: [llvm-commits] [llvm] r113985 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp In-Reply-To: References: <20100915172709.48D902A6C12C@llvm.org> Message-ID: <63564D56-F713-4ED9-A121-E6C14DACB741@2pi.dk> On Sep 15, 2010, at 2:23 PM, Bill Wendling wrote: > > On Sep 15, 2010, at 10:27 AM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Wed Sep 15 12:27:09 2010 >> New Revision: 113985 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113985&view=rev >> Log: >> Recognize VST1q64Pseudo and VSTMQ as stack slot stores. >> Recognize VLD1q64Pseudo as a stack slot load. >> >> Reject these if they are loading or storing a subregister. The API (and >> VirtRegRewriter) doesn't know how to deal with that. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113985&r1=113984&r2=113985&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 12:27:09 2010 >> @@ -751,6 +751,21 @@ >> return MI->getOperand(0).getReg(); >> } >> break; >> + case ARM::VST1q64Pseudo: >> + if (MI->getOperand(0).isFI() && >> + MI->getOperand(2).getSubReg() == 0) { >> + FrameIndex = MI->getOperand(0).getIndex(); >> + return MI->getOperand(2).getReg(); >> + } > > Should there be a "break" statement here? If not maybe a comment? :-) Uack! Nice catch. From stoklund at 2pi.dk Wed Sep 15 16:33:54 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 14:33:54 -0700 Subject: [llvm-commits] [llvm] r113985 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp In-Reply-To: <7F39DB7F-31AA-4825-9EFA-009C3C2E9D5F@apple.com> References: <20100915172709.48D902A6C12C@llvm.org> <7F39DB7F-31AA-4825-9EFA-009C3C2E9D5F@apple.com> Message-ID: On Sep 15, 2010, at 2:24 PM, Bob Wilson wrote: > You missed VLDMQ. Will you add that? I'll add it. Thanks. From espindola at google.com Wed Sep 15 16:39:43 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 15 Sep 2010 17:39:43 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add isObjectFile() In-Reply-To: References: Message-ID: > I'm still not 100% sure how to treat bitcode files. It will really > depend on how well they fit the API. What I don't want is to end up > with special case code everywhere just for bitcode files. Optimally a > linker would be able to treat it just like every other object file > during symbol resolution, and then assemble the functions/data that > matter before layout and output. Looks a lot like what gold does with plugins, so I agree :-) > The issue I have with explicitly listing every file type is that > IdentifyFileType returns more than just MachO or ELF. It also reads > the headers and tries to figure out a bunch of stuff that I don't care > about when constructing. > > What I would actually prefer is adding enum members like > ELF_ObjectStart_FileType and ELF_ObjectEnd_FileType. With all the > subtypes in the middle. That way more file types can be added without > requiring updating other places that can already deal with whatever is > being added. > > And core files are definitely object files. Thanks for the explanation. I think the patch is OK, just add a comment that bitcode files are accepted as object files. > Thanks for the review! > > - Michael Spencer > Cheers, -- Rafael ?vila de Esp?ndola From stoklund at 2pi.dk Wed Sep 15 16:40:09 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 21:40:09 -0000 Subject: [llvm-commits] [llvm] r114025 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100915214009.934232A6C12C@llvm.org> Author: stoklund Date: Wed Sep 15 16:40:09 2010 New Revision: 114025 URL: http://llvm.org/viewvc/llvm-project?rev=114025&view=rev Log: Add missing break. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114025&r1=114024&r2=114025&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 16:40:09 2010 @@ -757,6 +757,7 @@ FrameIndex = MI->getOperand(0).getIndex(); return MI->getOperand(2).getReg(); } + break; case ARM::VSTMQ: if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && From stoklund at 2pi.dk Wed Sep 15 16:40:12 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 21:40:12 -0000 Subject: [llvm-commits] [llvm] r114026 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100915214012.16D5E2A6C12D@llvm.org> Author: stoklund Date: Wed Sep 15 16:40:11 2010 New Revision: 114026 URL: http://llvm.org/viewvc/llvm-project?rev=114026&view=rev Log: Remember VLDMQ. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114026&r1=114025&r2=114026&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 16:40:11 2010 @@ -896,6 +896,15 @@ return MI->getOperand(0).getReg(); } break; + case ARM::VLDMQ: + if (MI->getOperand(1).isFI() && + MI->getOperand(2).isImm() && + MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) && + MI->getOperand(0).getSubReg() == 0) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + break; } return 0; From grosbach at apple.com Wed Sep 15 16:41:43 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 14:41:43 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <6D478F55-916F-47A7-BEB3-ADD9F671C21B@apple.com> References: <20100915184711.B22272A6C12C@llvm.org> <6D478F55-916F-47A7-BEB3-ADD9F671C21B@apple.com> Message-ID: <1BF71661-2903-49AE-8AEC-B37FDA778F7F@apple.com> On Sep 15, 2010, at 1:52 PM, Stephen Canon wrote: > On Sep 15, 2010, at 1:05 PM, Dale Johannesen wrote: > >> On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Wed Sep 15 13:47:08 2010 >>> New Revision: 113996 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >>> Log: >>> Add support for floating point immediates to MC instruction printing. ARM >>> VFP instructions use it for loading some constants, so implement that >>> handling. >>> >>> Not thrilled with adding a member to MCOperand, but not sure there's much of >>> a better option that's not pretty fragile (like putting a double in the >>> union instead and just assuming that's good enough). Suggestions welcome... >> >> This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. > > My reading of the C++ standard is that << does not guarantee that the value will be printed exactly. You need 7 digits after the decimal point in order to print all expressible immediates exactly, but you only get 6 digits. A test on the immediate value 0x1.1p-3 seems to confirm this. I get #1.328125e-01 for 0x1.1p-3, which seems right? Note that LLVM's output streamer is a raw_ostream, not standard C++ streams. -Jim From scanon at apple.com Wed Sep 15 16:47:36 2010 From: scanon at apple.com (Stephen Canon) Date: Wed, 15 Sep 2010 14:47:36 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <1BF71661-2903-49AE-8AEC-B37FDA778F7F@apple.com> References: <20100915184711.B22272A6C12C@llvm.org> <6D478F55-916F-47A7-BEB3-ADD9F671C21B@apple.com> <1BF71661-2903-49AE-8AEC-B37FDA778F7F@apple.com> Message-ID: On Sep 15, 2010, at 2:41 PM, Jim Grosbach wrote: > On Sep 15, 2010, at 1:52 PM, Stephen Canon wrote: > >> On Sep 15, 2010, at 1:05 PM, Dale Johannesen wrote: >> >>> On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: >>> >>>> Author: grosbach >>>> Date: Wed Sep 15 13:47:08 2010 >>>> New Revision: 113996 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >>>> Log: >>>> Add support for floating point immediates to MC instruction printing. ARM >>>> VFP instructions use it for loading some constants, so implement that >>>> handling. >>>> >>>> Not thrilled with adding a member to MCOperand, but not sure there's much of >>>> a better option that's not pretty fragile (like putting a double in the >>>> union instead and just assuming that's good enough). Suggestions welcome... >>> >>> This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. >> >> My reading of the C++ standard is that << does not guarantee that the value will be printed exactly. You need 7 digits after the decimal point in order to print all expressible immediates exactly, but you only get 6 digits. A test on the immediate value 0x1.1p-3 seems to confirm this. > > I get #1.328125e-01 for 0x1.1p-3, which seems right? Note that LLVM's output streamer is a raw_ostream, not standard C++ streams. Yes, that's the correct value. With "std::cout << 0x1.1p-3" I was seeing "0.132812". - Steve From bigcheesegs at gmail.com Wed Sep 15 16:48:45 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 15 Sep 2010 17:48:45 -0400 Subject: [llvm-commits] [PATCH][System::Path] Add x86-64 COFF to IdentifyFileType In-Reply-To: References: Message-ID: On Wed, Sep 15, 2010 at 3:23 PM, Rafael Espindola wrote: > On 14 September 2010 17:12, Michael Spencer wrote: >> The attached patch adds x86-64 COFF to Path::IdentifyFileType. This patch is a >> prerequisite for the object file library I am writing, although makes >> sense in general. > > Coff uses the same magic for all objecs (relocatable, libs and executables)? > > I think this is fine anyway. Can you just add a comment saying it is > x86-64 windows? There are similar comments for the other windows > arches. There are actually two different formats on windows that people refer to as COFF. The first is pure COFF, which has no magic number, and the first uint16_t of the file is the machine type. This file is only ever an object file. It's never anything else on windows. And there is no difference between a i386 COFF file and a x86-64 one except for these first two bytes. The second format is PE/COFF. This is what windows uses for images such as exe's and dll's. This format does have magic number 0x3c bytes into the file. I'll add a comment saying what type it is. Thanks for the review! - Michael Spencer >> - Michael Spencer >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> > > > Cheers, > -- > Rafael ?vila de Esp?ndola > From rafael.espindola at gmail.com Wed Sep 15 16:48:40 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 15 Sep 2010 21:48:40 -0000 Subject: [llvm-commits] [llvm] r114027 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCAssembler.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCMachOStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/WinCOFFStreamer.cpp test/MC/ELF/empty.s test/MC/ELF/sleb.s test/MC/ELF/uleb.s Message-ID: <20100915214840.E47612A6C12C@llvm.org> Author: rafael Date: Wed Sep 15 16:48:40 2010 New Revision: 114027 URL: http://llvm.org/viewvc/llvm-project?rev=114027&view=rev Log: Add a InitSections method to the streamer interface. The ELF implementation now creates text, data and bss to match the gnu as behavior. The text streamer still has the old MachO specific behavior since the testsuite checks that it will error when a directive is given before a setting the current section for example. A nice benefit is that -n is not required anymore when producing ELF files. Added: llvm/trunk/test/MC/ELF/empty.s Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCLoggingStreamer.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCNullStreamer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/WinCOFFStreamer.cpp llvm/trunk/test/MC/ELF/sleb.s llvm/trunk/test/MC/ELF/uleb.s Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Sep 15 16:48:40 2010 @@ -110,6 +110,9 @@ /// This corresponds to assembler directives like .section, .text, etc. virtual void SwitchSection(const MCSection *Section) = 0; + /// InitSections - Create the default sections and set the initial one. + virtual void InitSections() = 0; + /// EmitLabel - Emit a label for @p Symbol into the current section. /// /// This corresponds to an assembler statement such as: Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Sep 15 16:48:40 2010 @@ -100,6 +100,14 @@ virtual void SwitchSection(const MCSection *Section); + virtual void InitSections() { + // FIXME, this is MachO specific, but the testsuite + // expects this. + SwitchSection(getContext().getMachOSection("__TEXT", "__text", + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + 0, SectionKind::getText())); + } + virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Sep 15 16:48:40 2010 @@ -739,7 +739,7 @@ // Create dummy fragments to eliminate any empty sections, this simplifies // layout. if (it->getFragmentList().empty()) - new MCFillFragment(0, 1, 0, it); + new MCDataFragment(it); it->setOrdinal(SectionIndex++); } Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Wed Sep 15 16:48:40 2010 @@ -46,6 +46,7 @@ /// @name MCStreamer Interface /// @{ + virtual void InitSections(); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); @@ -109,10 +110,42 @@ virtual void Finish(); /// @} + void SetSection(StringRef Section, unsigned Type, unsigned Flags, + SectionKind Kind) { + SwitchSection(getContext().getELFSection(Section, Type, Flags, Kind)); + } + + void SetSectionData() { + SetSection(".data", MCSectionELF::SHT_PROGBITS, + MCSectionELF::SHF_WRITE |MCSectionELF::SHF_ALLOC, + SectionKind::getDataRel()); + EmitCodeAlignment(4, 0); + } + void SetSectionText() { + SetSection(".text", MCSectionELF::SHT_PROGBITS, + MCSectionELF::SHF_EXECINSTR | + MCSectionELF::SHF_ALLOC, SectionKind::getText()); + EmitCodeAlignment(4, 0); + } + void SetSectionBss() { + SetSection(".bss", MCSectionELF::SHT_NOBITS, + MCSectionELF::SHF_WRITE | + MCSectionELF::SHF_ALLOC, SectionKind::getBSS()); + EmitCodeAlignment(4, 0); + } }; } // end anonymous namespace. +void MCELFStreamer::InitSections() { + // This emulates the same behavior of GNU as. This makes it easier + // to compare the output as the major sections are in the same order. + SetSectionText(); + SetSectionData(); + SetSectionBss(); + SetSectionText(); +} + void MCELFStreamer::EmitLabel(MCSymbol *Symbol) { assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); Modified: llvm/trunk/lib/MC/MCLoggingStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLoggingStreamer.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCLoggingStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCLoggingStreamer.cpp Wed Sep 15 16:48:40 2010 @@ -54,6 +54,10 @@ return Child->SwitchSection(Section); } + virtual void InitSections() { + LogCall("InitSections"); + } + virtual void EmitLabel(MCSymbol *Symbol) { LogCall("EmitLabel"); return Child->EmitLabel(Symbol); Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Wed Sep 15 16:48:40 2010 @@ -46,6 +46,7 @@ /// @name MCStreamer Interface /// @{ + virtual void InitSections(); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); @@ -110,6 +111,13 @@ } // end anonymous namespace. +void MCMachOStreamer::InitSections() { + SwitchSection(getContext().getMachOSection("__TEXT", "__text", + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + 0, SectionKind::getText())); + +} + void MCMachOStreamer::EmitLabel(MCSymbol *Symbol) { // TODO: This is almost exactly the same as WinCOFFStreamer. Consider merging // into MCObjectStreamer. Modified: llvm/trunk/lib/MC/MCNullStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCNullStreamer.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCNullStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCNullStreamer.cpp Wed Sep 15 16:48:40 2010 @@ -25,6 +25,9 @@ /// @name MCStreamer Interface /// @{ + virtual void InitSections() { + } + virtual void SwitchSection(const MCSection *Section) { PrevSection = CurSection; CurSection = Section; Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Sep 15 16:48:40 2010 @@ -365,12 +365,8 @@ bool AsmParser::Run(bool NoInitialTextSection, bool NoFinalize) { // Create the initial section, if requested. - // - // FIXME: Target hook & command line option for initial section. if (!NoInitialTextSection) - Out.SwitchSection(Ctx.getMachOSection("__TEXT", "__text", - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - 0, SectionKind::getText())); + Out.InitSections(); // Prime the lexer. Lex(); Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Wed Sep 15 16:48:40 2010 @@ -51,20 +51,28 @@ AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous"); } + // FIXME: Part of this logic is duplicated in the MCELFStreamer. What is + // the best way for us to get access to it? bool ParseSectionDirectiveData(StringRef, SMLoc) { - return ParseSectionSwitch(".data", MCSectionELF::SHT_PROGBITS, + bool ret = ParseSectionSwitch(".data", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_WRITE |MCSectionELF::SHF_ALLOC, SectionKind::getDataRel()); + getStreamer().EmitCodeAlignment(4, 0); + return ret; } bool ParseSectionDirectiveText(StringRef, SMLoc) { - return ParseSectionSwitch(".text", MCSectionELF::SHT_PROGBITS, + bool ret = ParseSectionSwitch(".text", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_EXECINSTR | MCSectionELF::SHF_ALLOC, SectionKind::getText()); + getStreamer().EmitCodeAlignment(4, 0); + return ret; } bool ParseSectionDirectiveBSS(StringRef, SMLoc) { - return ParseSectionSwitch(".bss", MCSectionELF::SHT_NOBITS, + bool ret = ParseSectionSwitch(".bss", MCSectionELF::SHT_NOBITS, MCSectionELF::SHF_WRITE | MCSectionELF::SHF_ALLOC, SectionKind::getBSS()); + getStreamer().EmitCodeAlignment(4, 0); + return ret; } bool ParseSectionDirectiveRoData(StringRef, SMLoc) { return ParseSectionSwitch(".rodata", MCSectionELF::SHT_PROGBITS, Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Wed Sep 15 16:48:40 2010 @@ -48,6 +48,7 @@ // MCStreamer interface + virtual void InitSections(); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); @@ -126,6 +127,9 @@ // MCStreamer interface +void WinCOFFStreamer::InitSections() { +} + void WinCOFFStreamer::EmitLabel(MCSymbol *Symbol) { // TODO: This is copied almost exactly from the MachOStreamer. Consider // merging into MCObjectStreamer? Added: llvm/trunk/test/MC/ELF/empty.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/empty.s?rev=114027&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/empty.s (added) +++ llvm/trunk/test/MC/ELF/empty.s Wed Sep 15 16:48:40 2010 @@ -0,0 +1,36 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that like gnu as we create text, data and bss by default. + +// CHECK: ('sh_name', 1) # '.text' +// CHECK-NEXT: ('sh_type', 1) +// CHECK-NEXT: ('sh_flags', 6) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', 64) +// CHECK-NEXT: ('sh_size', 0) +// CHECK-NEXT: ('sh_link', 0) +// CHECK-NEXT: ('sh_info', 0) +// CHECK-NEXT: ('sh_addralign', 4) +// CHECK-NEXT: ('sh_entsize', 0) + +// CHECK: ('sh_name', 7) # '.data' +// CHECK-NEXT: ('sh_type', 1) +// CHECK-NEXT: ('sh_flags', 3) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', 64) +// CHECK-NEXT: ('sh_size', 0) +// CHECK-NEXT: ('sh_link', 0) +// CHECK-NEXT: ('sh_info', 0) +// CHECK-NEXT: ('sh_addralign', 4) +// CHECK-NEXT: ('sh_entsize', 0) + +// CHECK: ('sh_name', 13) # '.bss' +// CHECK-NEXT: ('sh_type', 8) +// CHECK-NEXT: ('sh_flags', 3) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', 64) +// CHECK-NEXT: ('sh_size', 0) +// CHECK-NEXT: ('sh_link', 0) +// CHECK-NEXT: ('sh_info', 0) +// CHECK-NEXT: ('sh_addralign', 4) +// CHECK-NEXT: ('sh_entsize', 0) Modified: llvm/trunk/test/MC/ELF/sleb.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/sleb.s?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/sleb.s (original) +++ llvm/trunk/test/MC/ELF/sleb.s Wed Sep 15 16:48:40 2010 @@ -1,5 +1,5 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s // RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_32 %s // RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_64 %s Modified: llvm/trunk/test/MC/ELF/uleb.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/uleb.s?rev=114027&r1=114026&r2=114027&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/uleb.s (original) +++ llvm/trunk/test/MC/ELF/uleb.s Wed Sep 15 16:48:40 2010 @@ -1,5 +1,5 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s // RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_32 %s // RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_64 %s From grosbach at apple.com Wed Sep 15 16:51:21 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 14:51:21 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: References: <20100915184711.B22272A6C12C@llvm.org> <6D478F55-916F-47A7-BEB3-ADD9F671C21B@apple.com> <1BF71661-2903-49AE-8AEC-B37FDA778F7F@apple.com> Message-ID: <2053C175-1E78-4046-B37E-EECF2A111129@apple.com> On Sep 15, 2010, at 2:47 PM, Stephen Canon wrote: > On Sep 15, 2010, at 2:41 PM, Jim Grosbach wrote: > >> On Sep 15, 2010, at 1:52 PM, Stephen Canon wrote: >> >>> On Sep 15, 2010, at 1:05 PM, Dale Johannesen wrote: >>> >>>> On Sep 15, 2010, at 11:47 AMPDT, Jim Grosbach wrote: >>>> >>>>> Author: grosbach >>>>> Date: Wed Sep 15 13:47:08 2010 >>>>> New Revision: 113996 >>>>> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >>>>> Log: >>>>> Add support for floating point immediates to MC instruction printing. ARM >>>>> VFP instructions use it for loading some constants, so implement that >>>>> handling. >>>>> >>>>> Not thrilled with adding a member to MCOperand, but not sure there's much of >>>>> a better option that's not pretty fragile (like putting a double in the >>>>> union instead and just assuming that's good enough). Suggestions welcome... >>>> >>>> This doesn't seem to handle NaNs and infinities. Also, I wonder whether you're guaranteed to get enough precision to represent the value accurately with << (printf does not guarantee this). Will the assembler take a hex format? That would be better. >>> >>> My reading of the C++ standard is that << does not guarantee that the value will be printed exactly. You need 7 digits after the decimal point in order to print all expressible immediates exactly, but you only get 6 digits. A test on the immediate value 0x1.1p-3 seems to confirm this. >> >> I get #1.328125e-01 for 0x1.1p-3, which seems right? Note that LLVM's output streamer is a raw_ostream, not standard C++ streams. > > Yes, that's the correct value. With "std::cout << 0x1.1p-3" I was seeing "0.132812". OK, cool. LLVM uses the equivalent to the printf() style format string "%e" for floating point, which should, if I follow properly, handle the necessary value range. Standard C++ streams use the equivalent to "%f" IIRC. Thanks for mentioning this. It's very good to explicitly check for this sort of thing. I'll add a testcase with the above value in it as a literal. -Jim From grosbach at apple.com Wed Sep 15 16:52:13 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 21:52:13 -0000 Subject: [llvm-commits] [llvm] r114028 - /llvm/trunk/test/MC/Disassembler/neon-tests.txt Message-ID: <20100915215213.A3B412A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 16:52:13 2010 New Revision: 114028 URL: http://llvm.org/viewvc/llvm-project?rev=114028&view=rev Log: add a test of an edge case value for the FP immediate (needs all digits of precision) Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=114028&r1=114027&r2=114028&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Wed Sep 15 16:52:13 2010 @@ -53,3 +53,6 @@ # CHECK: vmov.f32 s0, #5.000000e-01 0x00 0x0a 0xb6 0xee + +# CHECK: vmov.f32 s0, #1.328125e-01 +0x01 0x0a 0xb4 0xee From bigcheesegs at gmail.com Wed Sep 15 17:02:47 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 15 Sep 2010 18:02:47 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: References: Message-ID: On Wed, Sep 15, 2010 at 4:57 PM, Rafael Espindola wrote: > On 14 September 2010 17:18, Michael Spencer wrote: >> The attached patch adds the SwapByteOrder function template to System. >> This patch is a >> prerequisite for the object file library I am writing. >> >> I want to replace the functions in MathExtras.h with SwapByteOrder >> because it is a generic implementation that makes it easier to write >> generic byte order independent code. This patch has no functionality >> changes. >> >> The optimized versions are platform dependent, and thus belong in System anyway. > > Do you have an use for sizes other than 16, 32,and 64 or are you > adding support just in case? What happens if a signed integer is used, > we get the generic code? Maybe it is better if it failed to compile? The generic code is actually being used for both COFF and ELF with signed types, but it hasn't been tested because I've only tried out x86{,-64} so far (and thus this function isn't called). If someone could send me a small bigendian ELF file I could add a test for it and make sure everything works. Thanks for the review! - Michael Spencer >> - Michael Spencer >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > Cheers, > -- > Rafael ?vila de Esp?ndola > From stoklund at 2pi.dk Wed Sep 15 17:05:57 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 15 Sep 2010 15:05:57 -0700 Subject: [llvm-commits] [llvm] r113983 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll In-Reply-To: <20100915171208.A9D132A6C12C@llvm.org> References: <20100915171208.A9D132A6C12C@llvm.org> Message-ID: <284974CB-ECB9-4748-AB7E-0E25F41C5FCB@2pi.dk> On Sep 15, 2010, at 10:12 AM, Bob Wilson wrote: > Author: bwilson > Date: Wed Sep 15 12:12:08 2010 > New Revision: 113983 > > URL: http://llvm.org/viewvc/llvm-project?rev=113983&view=rev > Log: > Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem > encountered while building llvm-gcc for arm. This is probably the same issue > that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, > not a plain MachineInstr. Thanks, Bob! The ppc buildbot now made it past both test.llvm.stage1 and test.llvm.stage2. I isn't finished yet, but it looks like it will go green. /jakob From grosbach at apple.com Wed Sep 15 17:13:24 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 22:13:24 -0000 Subject: [llvm-commits] [llvm] r114030 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100915221324.1E6292A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 17:13:23 2010 New Revision: 114030 URL: http://llvm.org/viewvc/llvm-project?rev=114030&view=rev Log: Add support for the 'lane' modifier on vdup operands Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114030&r1=114029&r2=114030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 17:13:23 2010 @@ -53,6 +53,29 @@ } } +static unsigned getDPRSuperRegForSPR(unsigned Reg) { + switch (Reg) { + default: + assert(0 && "Unexpected register enum"); + case ARM::S0: case ARM::S1: return ARM::D0; + case ARM::S2: case ARM::S3: return ARM::D1; + case ARM::S4: case ARM::S5: return ARM::D2; + case ARM::S6: case ARM::S7: return ARM::D3; + case ARM::S8: case ARM::S9: return ARM::D4; + case ARM::S10: case ARM::S11: return ARM::D5; + case ARM::S12: case ARM::S13: return ARM::D6; + case ARM::S14: case ARM::S15: return ARM::D7; + case ARM::S16: case ARM::S17: return ARM::D8; + case ARM::S18: case ARM::S19: return ARM::D9; + case ARM::S20: case ARM::S21: return ARM::D10; + case ARM::S22: case ARM::S23: return ARM::D11; + case ARM::S24: case ARM::S25: return ARM::D12; + case ARM::S26: case ARM::S27: return ARM::D13; + case ARM::S28: case ARM::S29: return ARM::D14; + case ARM::S30: case ARM::S31: return ARM::D15; + } +} + void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for MOVs and print canonical forms, instead. if (MI->getOpcode() == ARM::MOVs) { @@ -147,14 +170,9 @@ O << '{' << getRegisterName(dregpair.first) << ", " << getRegisterName(dregpair.second) << '}'; } else if (Modifier && strcmp(Modifier, "lane") == 0) { - // FIXME - assert(0); - /* - unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); - unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1, - &ARM::DPR_VFP2RegClass); + unsigned RegNum = getARMRegisterNumbering(Reg); + unsigned DReg = getDPRSuperRegForSPR(Reg); O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; - */ } else { O << getRegisterName(Reg); } From ggreif at gmail.com Wed Sep 15 17:29:20 2010 From: ggreif at gmail.com (Gabor Greif) Date: Wed, 15 Sep 2010 15:29:20 -0700 (PDT) Subject: [llvm-commits] [llvm] r113983 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll In-Reply-To: <20100915171208.A9D132A6C12C@llvm.org> References: <20100915171208.A9D132A6C12C@llvm.org> Message-ID: <983b8c48-c3c7-4c16-9f87-bc6cc00b84bc@h25g2000vba.googlegroups.com> Thanks! ... and I definitely owe you a beer, should we ever meet in person. I was almost checking out the LLVM tree to my old Mac Mini when I heard the news :-) Thanks again, Gabor From clattner at apple.com Wed Sep 15 17:34:18 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 15:34:18 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <20100915184711.B22272A6C12C@llvm.org> References: <20100915184711.B22272A6C12C@llvm.org> Message-ID: <0F5FF4A8-39A2-4B97-8E6B-5ABE0FCD6567@apple.com> On Sep 15, 2010, at 11:47 AM, Jim Grosbach wrote: > Author: grosbach > Date: Wed Sep 15 13:47:08 2010 > New Revision: 113996 > > URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev > Log: > Add support for floating point immediates to MC instruction printing. ARM > VFP instructions use it for loading some constants, so implement that > handling. > > Not thrilled with adding a member to MCOperand, but not sure there's much of > a better option that's not pretty fragile (like putting a double in the > union instead and just assuming that's good enough). Suggestions welcome... Please just use "double" or, better yet, "int64_t" instead, and have an accessor turn that into an apfloat. The new kFPImmediate kind is great, we just really want MCOperand to avoid a dtor. Thanks Jim, -Chris > > > Modified: > llvm/trunk/include/llvm/MC/MCInst.h > llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp > llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > > Modified: llvm/trunk/include/llvm/MC/MCInst.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=113996&r1=113995&r2=113996&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/MC/MCInst.h (original) > +++ llvm/trunk/include/llvm/MC/MCInst.h Wed Sep 15 13:47:08 2010 > @@ -16,6 +16,7 @@ > #ifndef LLVM_MC_MCINST_H > #define LLVM_MC_MCINST_H > > +#include "llvm/ADT/APFloat.h" > #include "llvm/ADT/SmallVector.h" > #include "llvm/ADT/StringRef.h" > #include "llvm/System/DataTypes.h" > @@ -33,6 +34,7 @@ > kInvalid, ///< Uninitialized. > kRegister, ///< Register operand. > kImmediate, ///< Immediate operand. > + kFPImmediate, ///< Floating-point immediate operand. > kExpr ///< Relocatable immediate operand. > }; > unsigned char Kind; > @@ -42,13 +44,17 @@ > int64_t ImmVal; > const MCExpr *ExprVal; > }; > + // This can't go in the union due to the non-trivial copy constructor > + // of APFloat. It's still only valid for Kind == kFPImmediate, though. > + APFloat FPImmVal; > public: > > - MCOperand() : Kind(kInvalid) {} > + MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} > > bool isValid() const { return Kind != kInvalid; } > bool isReg() const { return Kind == kRegister; } > bool isImm() const { return Kind == kImmediate; } > + bool isFPImm() const { return Kind == kFPImmediate; } > bool isExpr() const { return Kind == kExpr; } > > /// getReg - Returns the register number. > @@ -72,6 +78,16 @@ > ImmVal = Val; > } > > + const APFloat &getFPImm() const { > + assert(isFPImm() && "This is not an FP immediate"); > + return FPImmVal; > + } > + > + void setFPImm(const APFloat &Val) { > + assert(isFPImm() && "This is not an FP immediate"); > + FPImmVal = Val; > + } > + > const MCExpr *getExpr() const { > assert(isExpr() && "This is not an expression"); > return ExprVal; > @@ -93,6 +109,12 @@ > Op.ImmVal = Val; > return Op; > } > + static MCOperand CreateFPImm(const APFloat &Val) { > + MCOperand Op; > + Op.Kind = kFPImmediate; > + Op.FPImmVal = Val; > + return Op; > + } > static MCOperand CreateExpr(const MCExpr *Val) { > MCOperand Op; > Op.Kind = kExpr; > > Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=113996&r1=113995&r2=113996&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Sep 15 13:47:08 2010 > @@ -16,6 +16,7 @@ > #include "ARMMCInstLower.h" > //#include "llvm/CodeGen/MachineModuleInfoImpls.h" > #include "llvm/CodeGen/AsmPrinter.h" > +#include "llvm/Constants.h" > #include "llvm/CodeGen/MachineBasicBlock.h" > #include "llvm/MC/MCAsmInfo.h" > #include "llvm/MC/MCContext.h" > @@ -155,6 +156,9 @@ > MCOp = LowerSymbolOperand(MO, Printer.GetBlockAddressSymbol( > MO.getBlockAddress())); > break; > + case MachineOperand::MO_FPImmediate: > + MCOp = MCOperand::CreateFPImm(MO.getFPImm()->getValueAPF()); > + break; > } > > OutMI.addOperand(MCOp); > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=113996&r1=113995&r2=113996&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 13:47:08 2010 > @@ -729,12 +729,12 @@ > > void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, > raw_ostream &O) { > - O << '#' << MI->getOperand(OpNum).getImm(); > + O << '#' << MI->getOperand(OpNum).getFPImm().convertToFloat(); > } > > void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, > raw_ostream &O) { > - O << '#' << MI->getOperand(OpNum).getImm(); > + O << '#' << MI->getOperand(OpNum).getFPImm().convertToDouble(); > } > > void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dirty at apple.com Wed Sep 15 17:45:29 2010 From: dirty at apple.com (Cameron Esfahani) Date: Wed, 15 Sep 2010 15:45:29 -0700 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple In-Reply-To: <4C908A47.9070103@free.fr> References: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> <4C908A47.9070103@free.fr> Message-ID: <53F36670-C33C-4BE8-B41B-E0B721BA5F26@apple.com> Attached is a newer patch which resolves these issues. I was able to add some level of testing to the TripleTest.cpp unittest, but until we define some environments, there are some holes in the coverage. -------------- next part -------------- A non-text attachment was scrubbed... Name: environment.patch Type: application/octet-stream Size: 8447 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100915/9613d00a/attachment.obj -------------- next part -------------- On Sep 15, 2010, at 1:56 AM, Duncan Sands wrote: > Hi Cameron, > >> + explicit Triple(StringRef ArchStr, StringRef VendorStr, StringRef OSStr, >> + StringRef EnvironmentStr ) > > there is an extraneous space before the closing bracket. > >> + /// getEnvironment - Get the parsed environment type of this triple. >> + EnvironmentType getEnvironment() const { >> + if (!isInitialized()) Parse(); >> + if (!hasEnvironment()) return UnknownEnvironment; > > If there is no environment, won't Environment be equal to UnknownEnvironment, > making the above line useless? > >> + return Environment; >> + } >> + > > As well as the above, you should also add some unit tests and enhance the > normalize method to take the environment into account. > > Ciao, > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits Cameron Esfahani dirty at apple.com "Americans are very skilled at creating a custom meaning from something that's mass-produced." Ann Powers From bigcheesegs at gmail.com Wed Sep 15 17:45:46 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 15 Sep 2010 22:45:46 -0000 Subject: [llvm-commits] [llvm] r114032 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Path.cpp Message-ID: <20100915224546.301EF2A6C12C@llvm.org> Author: mspencer Date: Wed Sep 15 17:45:45 2010 New Revision: 114032 URL: http://llvm.org/viewvc/llvm-project?rev=114032&view=rev Log: System/Path: Add isObjectFile(). Modified: llvm/trunk/include/llvm/System/Path.h llvm/trunk/lib/System/Path.cpp Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=114032&r1=114031&r2=114032&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Wed Sep 15 17:45:45 2010 @@ -342,6 +342,17 @@ /// @brief Determine if the path references a dynamic library. bool isDynamicLibrary() const; + /// This function determines if the path name in the object references a + /// native object file by looking at it's magic number. The term object + /// file is defined as "an organized collection of separate, named + /// sequences of binary data." This covers the obvious file formats such as + /// COFF and ELF, but it also includes llvm ir bitcode, archives, + /// libraries, etc... + /// @returns true if the file starts with the magic number for an object + /// file. + /// @brief Determine if the path references an object file. + bool isObjectFile() const; + /// This function determines if the path name references an existing file /// or directory in the file system. /// @returns true if the pathname references an existing file or Modified: llvm/trunk/lib/System/Path.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Path.cpp?rev=114032&r1=114031&r2=114032&view=diff ============================================================================== --- llvm/trunk/lib/System/Path.cpp (original) +++ llvm/trunk/lib/System/Path.cpp Wed Sep 15 17:45:45 2010 @@ -156,6 +156,20 @@ return false; } +bool +Path::isObjectFile() const { + std::string Magic; + if (getMagicNumber(Magic, 64)) + if (IdentifyFileType(Magic.c_str(), + static_cast(Magic.length())) + != Unknown_FileType) { + // Everything in LLVMFileType is currently an object file. + return true; + } + + return false; +} + Path Path::FindLibrary(std::string& name) { std::vector LibPaths; From clattner at apple.com Wed Sep 15 17:50:33 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 15:50:33 -0700 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: References: Message-ID: <39CF6631-84D5-46D7-BB2E-86DF88D01592@apple.com> On Sep 14, 2010, at 2:31 PM, Michael Spencer wrote: > On Tue, Sep 14, 2010 at 5:18 PM, Michael Spencer wrote: >> The attached patch adds the SwapByteOrder function template to System. >> This patch is a >> prerequisite for the object file library I am writing. >> >> I want to replace the functions in MathExtras.h with SwapByteOrder >> because it is a generic implementation that makes it easier to write >> generic byte order independent code. This patch has no functionality >> changes. >> >> The optimized versions are platform dependent, and thus belong in System anyway. >> >> - Michael Spencer >> > > It had to happen eventually :(. Now the patch it attached. Hi Michael, What's wrong with the existing ByteSwap_XX functions? Why is a template better? Can you give an example of how this is better? Note that you're likely to run into problems on some systems (cygwin?) where uint32_t != unsigned. -Chris From clattner at apple.com Wed Sep 15 17:51:12 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 15:51:12 -0700 Subject: [llvm-commits] [PATCH][System::Path] Add x86-64 COFF to IdentifyFileType In-Reply-To: References: Message-ID: Sure, go for it. On Sep 14, 2010, at 2:12 PM, Michael Spencer wrote: > The attached patch adds x86-64 COFF to Path::IdentifyFileType. This patch is a > prerequisite for the object file library I am writing, although makes > sense in general. > > - Michael Spencer > <0001-System-Path-Add-x86-64-COFF-to-IdentifyFileType.patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Sep 15 17:54:05 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 15:54:05 -0700 Subject: [llvm-commits] [PATCH] Add exit instruction to PTX backend In-Reply-To: References: Message-ID: On Sep 14, 2010, at 1:59 AM, Che-Liang Chiou wrote: > Hi, > > I have created a patch that adds "exit" instruction to PTX backend. > > SVN revision: > 113836 > > TEST: > $ cd llvm/test/ > $ llvm-lit CodeGen/PTX/exit.ll > -- Testing: 1 tests, 8 threads -- > PASS: LLVM :: CodeGen/PTX/exit.ll (1 of 1) > Testing Time: 0.01s > Expected Passes : 1 Looks good to me. Please make sure to update the cmake file. Also, please put your {'s on the "previous line" instead of on a new line. -Chris > > Note: > Compiling auto generated cpp file produces warning. I suspect the it > is because of too few instructions in .td file for now. The warning > message should look like this: > > In file included from PTXAsmPrinter.cpp:50: > /usr/local/google/clchiou/llvm/llvm/lib/Target/PTX/AsmPrinter/../PTXGenAsmWriter.inc: > In member function > ?void::PTXAsmPrinter::printInstruction(const > llvm::MachineInstr*, llvm::raw_ostream&)?: > /usr/local/google/clchiou/llvm/llvm/lib/Target/PTX/AsmPrinter/../PTXGenAsmWriter.inc:43: > warning: right shift count >= width of type > > This warning should disappear after more instructions are added. > > Regards, > Che-Liang > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Wed Sep 15 18:03:33 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 15 Sep 2010 23:03:33 -0000 Subject: [llvm-commits] [llvm] r114036 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp Message-ID: <20100915230333.98BEA2A6C12C@llvm.org> Author: resistor Date: Wed Sep 15 18:03:33 2010 New Revision: 114036 URL: http://llvm.org/viewvc/llvm-project?rev=114036&view=rev Log: Since PassRegistry is currently a shared global object, it needs locking. While it might intuitively seem that all the setup of this class currently happens at static initialization time, this misses the fact that some later events can cause mutation of the PassRegistrationListeners list, and thus cause race issues. Modified: llvm/trunk/include/llvm/PassRegistry.h llvm/trunk/lib/VMCore/PassRegistry.cpp Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=114036&r1=114035&r2=114036&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Wed Sep 15 18:03:33 2010 @@ -18,6 +18,7 @@ #define LLVM_PASSREGISTRY_H #include "llvm/ADT/StringRef.h" +#include "llvm/System/Mutex.h" namespace llvm { @@ -32,6 +33,7 @@ /// each thread. class PassRegistry { mutable void *pImpl; + mutable sys::SmartMutex Lock; void *getImpl() const; public: Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=114036&r1=114035&r2=114036&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Wed Sep 15 18:03:33 2010 @@ -88,6 +88,7 @@ // void PassRegistry::registerPass(const PassInfo &PI) { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(getImpl()); bool Inserted = Impl->PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second; @@ -101,6 +102,7 @@ } void PassRegistry::unregisterPass(const PassInfo &PI) { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::MapType::iterator I = Impl->PassInfoMap.find(PI.getTypeInfo()); @@ -112,6 +114,7 @@ } void PassRegistry::enumerateWith(PassRegistrationListener *L) { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(getImpl()); for (PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.begin(), E = Impl->PassInfoMap.end(); I != E; ++I) @@ -124,6 +127,7 @@ const void *PassID, PassInfo& Registeree, bool isDefault) { + sys::SmartScopedLock Guard(Lock); PassInfo *InterfaceInfo = const_cast(getPassInfo(InterfaceID)); if (InterfaceInfo == 0) { // First reference to Interface, register it now. @@ -159,11 +163,14 @@ } void PassRegistry::addRegistrationListener(PassRegistrationListener *L) { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(getImpl()); Impl->Listeners.push_back(L); } void PassRegistry::removeRegistrationListener(PassRegistrationListener *L) { + sys::SmartScopedLock Guard(Lock); + // NOTE: This is necessary, because removeRegistrationListener() can be called // as part of the llvm_shutdown sequence. Since we have no control over the // order of that sequence, we need to gracefully handle the case where the From bigcheesegs at gmail.com Wed Sep 15 18:04:14 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 15 Sep 2010 23:04:14 -0000 Subject: [llvm-commits] [llvm] r114037 - /llvm/trunk/lib/System/Path.cpp Message-ID: <20100915230414.696272A6C12C@llvm.org> Author: mspencer Date: Wed Sep 15 18:04:14 2010 New Revision: 114037 URL: http://llvm.org/viewvc/llvm-project?rev=114037&view=rev Log: System/Path: Add x86-64 COFF to IdentifyFileType. Modified: llvm/trunk/lib/System/Path.cpp Modified: llvm/trunk/lib/System/Path.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Path.cpp?rev=114037&r1=114036&r2=114037&view=diff ============================================================================== --- llvm/trunk/lib/System/Path.cpp (original) +++ llvm/trunk/lib/System/Path.cpp Wed Sep 15 18:04:14 2010 @@ -127,6 +127,10 @@ if (magic[1] == 0x02) return COFF_FileType; break; + case 0x64: // x86-64 Windows. + if (magic[1] == char(0x86)) + return COFF_FileType; + break; default: break; From wdietz2 at illinois.edu Wed Sep 15 18:22:25 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 23:22:25 -0000 Subject: [llvm-commits] [poolalloc] r114040 - in /poolalloc/trunk/test/pa/regression: 2010-09-14-Fptr.c 2010-09-14-Fptr_helper.c Message-ID: <20100915232225.A786E2A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 18:22:25 2010 New Revision: 114040 URL: http://llvm.org/viewvc/llvm-project?rev=114040&view=rev Log: Fix up 'Fptr' tests. Modified: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c Modified: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c?rev=114040&r1=114039&r2=114040&view=diff ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c (original) +++ poolalloc/trunk/test/pa/regression/2010-09-14-Fptr.c Wed Sep 15 18:22:25 2010 @@ -9,8 +9,8 @@ * RUN: llvm-gcc -o %t.native %s * * Execute the program to verify it's correct: - * RUN: ./%t.pa >& %t.pa.out - * RUN: /%t.native >& %t.native.out + * RUN: %t.pa >& %t.pa.out + * RUN: %t.native >& %t.native.out * * Diff the two executions * RUN: diff %t.pa.out %t.native.out @@ -39,4 +39,5 @@ { int val = MAGIC; getFP()(&val); + return 0; } Modified: poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c?rev=114040&r1=114039&r2=114040&view=diff ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c (original) +++ poolalloc/trunk/test/pa/regression/2010-09-14-Fptr_helper.c Wed Sep 15 18:22:25 2010 @@ -12,8 +12,8 @@ * RUN: llvm-gcc -o %t.native %s * * Execute the program to verify it's correct: - * RUN: ./%t.pa >& %t.pa.out - * RUN: /%t.native >& %t.native.out + * RUN: %t.pa >& %t.pa.out + * RUN: %t.native >& %t.native.out * * Diff the two executions * RUN: diff %t.pa.out %t.native.out @@ -47,4 +47,5 @@ { int val = MAGIC; helper(&val); + return 0; } From wdietz2 at illinois.edu Wed Sep 15 18:23:14 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 23:23:14 -0000 Subject: [llvm-commits] [poolalloc] r114041 - /poolalloc/trunk/test/dsa/td/params2.ll Message-ID: <20100915232314.8DD522A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 18:23:14 2010 New Revision: 114041 URL: http://llvm.org/viewvc/llvm-project?rev=114041&view=rev Log: XFAIL the 'params2' test as a temporary fix to clean up testing results. We should either remove this test or add proper runlines. Modified: poolalloc/trunk/test/dsa/td/params2.ll Modified: poolalloc/trunk/test/dsa/td/params2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/params2.ll?rev=114041&r1=114040&r2=114041&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/td/params2.ll (original) +++ poolalloc/trunk/test/dsa/td/params2.ll Wed Sep 15 18:23:14 2010 @@ -1,4 +1,7 @@ ; ModuleID = 'params2.bc' +;FIXME: Remove this test entirely or add a RUN line! +;XFAIL:* +;RUN: not target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" From wdietz2 at illinois.edu Wed Sep 15 18:24:27 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 15 Sep 2010 23:24:27 -0000 Subject: [llvm-commits] [poolalloc] r114042 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100915232427.1B7902A6C12C@llvm.org> Author: wdietz2 Date: Wed Sep 15 18:24:26 2010 New Revision: 114042 URL: http://llvm.org/viewvc/llvm-project?rev=114042&view=rev Log: Don't clone main! Fixes 'Fptr' and 'Fptr_helper', still need to explore this behavior with external code like 'qsort'. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=114042&r1=114041&r2=114042&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Sep 15 18:24:26 2010 @@ -168,6 +168,7 @@ // FIXME: Should use a isClone() method. // std::set ClonedFunctions; + Function *MainFunc = M.getFunction("main"); while (FunctionsToClone.size()) { // // Remove a function from the list of functions to clone. @@ -175,6 +176,11 @@ Function * Original = FunctionsToClone.back(); FunctionsToClone.pop_back (); + // Don't clone 'main'! + if (Original == MainFunc) { + continue; + } + // // Clone the function. Record a pointer to the new clone if one was // created. From bigcheesegs at gmail.com Wed Sep 15 18:44:44 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 15 Sep 2010 19:44:44 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: <39CF6631-84D5-46D7-BB2E-86DF88D01592@apple.com> References: <39CF6631-84D5-46D7-BB2E-86DF88D01592@apple.com> Message-ID: On Wed, Sep 15, 2010 at 6:50 PM, Chris Lattner wrote: > > On Sep 14, 2010, at 2:31 PM, Michael Spencer wrote: > >> On Tue, Sep 14, 2010 at 5:18 PM, Michael Spencer wrote: >>> The attached patch adds the SwapByteOrder function template to System. >>> This patch is a >>> prerequisite for the object file library I am writing. >>> >>> I want to replace the functions in MathExtras.h with SwapByteOrder >>> because it is a generic implementation that makes it easier to write >>> generic byte order independent code. This patch has no functionality >>> changes. >>> >>> The optimized versions are platform dependent, and thus belong in System anyway. >>> >>> - Michael Spencer >>> >> >> It had to happen eventually :(. Now the patch it attached. > > Hi Michael, > > What's wrong with the existing ByteSwap_XX functions? ?Why is a template better? ?Can you give an example of how this is better? > > Note that you're likely to run into problems on some systems (cygwin?) where uint32_t != unsigned. > > -Chris If you look at the other patch I posted ([PATCH][Support] Add Endian.h which contains generic code to deal with endian specific data) it is used to byte swap an arbitrary integral type like so: template static typename enable_if_c::type SwapByteOrderIfDifferent(value_type value) { return sys::SwapByteOrder(value); } Which is then used to directly read from memory (in this case a memory mapped file): template struct endian_impl { template static value_type read_le(const void *memory) { return SwapByteOrderIfDifferent( *reinterpret_cast(memory)); } // other read and write functions. }; Which is then used to create structs with "normal" looking members that can directly reference memory mapped files: template class packed_endian_specific_integral; template class packed_endian_specific_integral { public: operator value_type() const { return endian::read_le(Value); } private: uint8_t Value[sizeof(value_type)]; }; // Other specializations... Which then have typedefs like: typedef packed_endian_specific_integral little_uint32_t; As you can see, the value_type is defined a long way away from where the byte swap occurs. SwapByteOrderIfDifferent could be specialized to deal with the different value_types, but that belongs in System, and is useful for others. In short. It reduces the number of explicit template specializations required, and therefore complexity. And as for uint32_t != unsigned. Two things: 1) By unsigned you mean the the keyword unsigned, by itself. Like "unsigned hey_look_im_a_var = 0;" right? 2) The ByteSwap_XX functions already have uintxx_t types, so I don't see how that affects this code. Thanks - Michael Spencer From grosbach at apple.com Wed Sep 15 18:44:37 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 15 Sep 2010 16:44:37 -0700 Subject: [llvm-commits] [llvm] r113996 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <0F5FF4A8-39A2-4B97-8E6B-5ABE0FCD6567@apple.com> References: <20100915184711.B22272A6C12C@llvm.org> <0F5FF4A8-39A2-4B97-8E6B-5ABE0FCD6567@apple.com> Message-ID: On Sep 15, 2010, at 3:34 PM, Chris Lattner wrote: > > On Sep 15, 2010, at 11:47 AM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Sep 15 13:47:08 2010 >> New Revision: 113996 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113996&view=rev >> Log: >> Add support for floating point immediates to MC instruction printing. ARM >> VFP instructions use it for loading some constants, so implement that >> handling. >> >> Not thrilled with adding a member to MCOperand, but not sure there's much of >> a better option that's not pretty fragile (like putting a double in the >> union instead and just assuming that's good enough). Suggestions welcome... > > Please just use "double" or, better yet, "int64_t" instead, and have an accessor turn that into an apfloat. The new kFPImmediate kind is great, we just really want MCOperand to avoid a dtor. That makes sense. Should be able to get to that this evening. Thanks! -Jim From stoklund at 2pi.dk Wed Sep 15 19:01:37 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 16 Sep 2010 00:01:37 -0000 Subject: [llvm-commits] [llvm] r114043 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h Message-ID: <20100916000137.2395D2A6C12C@llvm.org> Author: stoklund Date: Wed Sep 15 19:01:36 2010 New Revision: 114043 URL: http://llvm.org/viewvc/llvm-project?rev=114043&view=rev Log: Use the value mapping provided by LiveIntervalMap. This simplifies the code a great deal because we don't have to worry about maintaining SSA form. Unconditionally copy back to dupli when the register is live out of the split range, even if the live-out value was defined outside the range. Skipping the back-copy only makes sense when the live range is going to spill outside the split range, and we don't know that it will. Besides, this was a hack to avoid SSA update issues. Clear up some confusion about the end point of a half-open LiveRange. Methinks LiveRanges need to be closed so both start and end are included in the range. The low bits of a SlotIndex are symbolic, so a half-open range doesn't really make sense. This would be a pervasive change, though. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=114043&r1=114042&r2=114043&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Sep 15 19:01:36 2010 @@ -363,10 +363,8 @@ if (Idx == ParentVNI->def) return mapValue(ParentVNI, Idx); - // This is a complex def. Mark with a NULL in valueMap. - VNInfo *&OldVNI = valueMap_[ParentVNI]; - assert(!OldVNI && "Simple/Complex values mixed"); - OldVNI = 0; + // This is now a complex def. Mark with a NULL in valueMap. + valueMap_[ParentVNI] = 0; // Should we insert a minimal snippet of VNI LiveRange, or can we count on // callers to do that? We need it for lookups of complex values. @@ -417,10 +415,10 @@ IDFI = idf_begin(IdxMBB), IDFE = idf_end(IdxMBB); IDFI != IDFE;) { MachineBasicBlock *MBB = *IDFI; - SlotIndex End = lis_.getMBBEndIdx(MBB); + SlotIndex End = lis_.getMBBEndIdx(MBB).getPrevSlot(); // We are operating on the restricted CFG where ParentVNI is live. - if (parentli_.getVNInfoAt(End.getPrevSlot()) != ParentVNI) { + if (parentli_.getVNInfoAt(End) != ParentVNI) { IDFI.skipChildren(); continue; } @@ -489,7 +487,7 @@ if (MBB == IdxMBB) { // Don't add full liveness to IdxMBB, stop at Idx. if (Start != Idx) - li_->addRange(LiveRange(Start, Idx, VNI)); + li_->addRange(LiveRange(Start, Idx.getNextSlot(), VNI)); // The caller had better add some liveness to IdxVNI, or it leaks. IdxVNI = VNI; } else @@ -511,8 +509,8 @@ --I; if (I->start < lis_.getMBBStartIdx(MBB)) return 0; - if (I->end < Idx) - I->end = Idx; + if (I->end <= Idx) + I->end = Idx.getNextSlot(); return I->valno; } @@ -574,6 +572,20 @@ addSimpleRange(I->start, std::min(End, I->end), I->valno); } +VNInfo *LiveIntervalMap::defByCopyFrom(unsigned Reg, + const VNInfo *ParentVNI, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) { + const TargetInstrDesc &TID = MBB.getParent()->getTarget().getInstrInfo()-> + get(TargetOpcode::COPY); + MachineInstr *MI = BuildMI(MBB, I, DebugLoc(), TID, li_->reg).addReg(Reg); + SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); + VNInfo *VNI = defValue(ParentVNI, DefIdx); + VNI->setCopy(MI); + li_->addRange(LiveRange(DefIdx, DefIdx.getNextSlot(), VNI)); + return VNI; +} + //===----------------------------------------------------------------------===// // Split Editor //===----------------------------------------------------------------------===// @@ -600,122 +612,56 @@ } LiveInterval *SplitEditor::createInterval() { - unsigned curli = sa_.getCurLI()->reg; - unsigned Reg = mri_.createVirtualRegister(mri_.getRegClass(curli)); + unsigned Reg = mri_.createVirtualRegister(mri_.getRegClass(curli_->reg)); LiveInterval &Intv = lis_.getOrCreateInterval(Reg); vrm_.grow(); - vrm_.assignVirt2StackSlot(Reg, vrm_.getStackSlot(curli)); + vrm_.assignVirt2StackSlot(Reg, vrm_.getStackSlot(curli_->reg)); return &Intv; } -LiveInterval *SplitEditor::getDupLI() { +/// Create a new virtual register and live interval. +void SplitEditor::openIntv() { + assert(!openli_.getLI() && "Previous LI not closed before openIntv"); + if (!dupli_.getLI()) { // Create an interval for dupli that is a copy of curli. dupli_.reset(createInterval()); dupli_.getLI()->Copy(*curli_, &mri_, lis_.getVNInfoAllocator()); } - return dupli_.getLI(); -} - -VNInfo *SplitEditor::mapValue(const VNInfo *curliVNI) { - VNInfo *&VNI = valueMap_[curliVNI]; - if (!VNI) - VNI = openli_.getLI()->createValueCopy(curliVNI, lis_.getVNInfoAllocator()); - return VNI; -} -/// Insert a COPY instruction curli -> li. Allocate a new value from li -/// defined by the COPY. Note that rewrite() will deal with the curli -/// register, so this function can be used to copy from any interval - openli, -/// curli, or dupli. -VNInfo *SplitEditor::insertCopy(LiveInterval &LI, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) { - MachineInstr *MI = BuildMI(MBB, I, DebugLoc(), tii_.get(TargetOpcode::COPY), - LI.reg).addReg(curli_->reg); - SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); - return LI.getNextValue(DefIdx, MI, true, lis_.getVNInfoAllocator()); -} - -/// Create a new virtual register and live interval. -void SplitEditor::openIntv() { - assert(!openli_.getLI() && "Previous LI not closed before openIntv"); openli_.reset(createInterval()); intervals_.push_back(openli_.getLI()); - liveThrough_ = false; } /// enterIntvBefore - Enter openli before the instruction at Idx. If curli is /// not live before Idx, a COPY is not inserted. void SplitEditor::enterIntvBefore(SlotIndex Idx) { assert(openli_.getLI() && "openIntv not called before enterIntvBefore"); - - // Copy from curli_ if it is live. - if (VNInfo *CurVNI = curli_->getVNInfoAt(Idx.getUseIndex())) { - MachineInstr *MI = lis_.getInstructionFromIndex(Idx); - assert(MI && "enterIntvBefore called with invalid index"); - VNInfo *VNI = insertCopy(*openli_.getLI(), *MI->getParent(), MI); - openli_.getLI()->addRange(LiveRange(VNI->def, Idx.getDefIndex(), VNI)); - - // Make sure CurVNI is properly mapped. - VNInfo *&mapVNI = valueMap_[CurVNI]; - // We dont have SSA update yet, so only one entry per value is allowed. - assert(!mapVNI && "enterIntvBefore called more than once for the same value"); - mapVNI = VNI; + VNInfo *ParentVNI = curli_->getVNInfoAt(Idx.getUseIndex()); + if (!ParentVNI) { + DEBUG(dbgs() << " enterIntvBefore " << Idx << ": not live\n"); + return; } + MachineInstr *MI = lis_.getInstructionFromIndex(Idx); + assert(MI && "enterIntvBefore called with invalid index"); + openli_.defByCopyFrom(curli_->reg, ParentVNI, *MI->getParent(), MI); DEBUG(dbgs() << " enterIntvBefore " << Idx << ": " << *openli_.getLI() << '\n'); } /// enterIntvAtEnd - Enter openli at the end of MBB. -/// PhiMBB is a successor inside openli where a PHI value is created. -/// Currently, all entries must share the same PhiMBB. -void SplitEditor::enterIntvAtEnd(MachineBasicBlock &A, MachineBasicBlock &B) { +void SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(openli_.getLI() && "openIntv not called before enterIntvAtEnd"); - - SlotIndex EndA = lis_.getMBBEndIdx(&A); - VNInfo *CurVNIA = curli_->getVNInfoAt(EndA.getPrevIndex()); - if (!CurVNIA) { - DEBUG(dbgs() << " enterIntvAtEnd, curli not live out of BB#" - << A.getNumber() << ".\n"); - return; - } - - // Add a phi kill value and live range out of A. - VNInfo *VNIA = insertCopy(*openli_.getLI(), A, A.getFirstTerminator()); - openli_.getLI()->addRange(LiveRange(VNIA->def, EndA, VNIA)); - - // FIXME: If this is the only entry edge, we don't need the extra PHI value. - // FIXME: If there are multiple entry blocks (so not a loop), we need proper - // SSA update. - - // Now look at the start of B. - SlotIndex StartB = lis_.getMBBStartIdx(&B); - SlotIndex EndB = lis_.getMBBEndIdx(&B); - const LiveRange *CurB = curli_->getLiveRangeContaining(StartB); - if (!CurB) { - DEBUG(dbgs() << " enterIntvAtEnd: curli not live in to BB#" - << B.getNumber() << ".\n"); + SlotIndex End = lis_.getMBBEndIdx(&MBB); + VNInfo *ParentVNI = curli_->getVNInfoAt(End.getPrevSlot()); + if (!ParentVNI) { + DEBUG(dbgs() << " enterIntvAtEnd " << End << ": not live\n"); return; } - - VNInfo *VNIB = openli_.getLI()->getVNInfoAt(StartB); - if (!VNIB) { - // Create a phi value. - VNIB = openli_.getLI()->getNextValue(SlotIndex(StartB, true), 0, false, - lis_.getVNInfoAllocator()); - VNIB->setIsPHIDef(true); - VNInfo *&mapVNI = valueMap_[CurB->valno]; - if (mapVNI) { - // Multiple copies - must create PHI value. - abort(); - } else { - // This is the first copy of dupLR. Mark the mapping. - mapVNI = VNIB; - } - - } - + VNInfo *VNI = openli_.defByCopyFrom(curli_->reg, ParentVNI, + MBB, MBB.getFirstTerminator()); + // Make sure openli is live out of MBB. + openli_.getLI()->addRange(LiveRange(VNI->def, End, VNI)); DEBUG(dbgs() << " enterIntvAtEnd: " << *openli_.getLI() << '\n'); } @@ -726,24 +672,7 @@ void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) { assert(openli_.getLI() && "openIntv not called before useIntv"); - - // Map the curli values from the interval into openli_ - LiveInterval::const_iterator B = curli_->begin(), E = curli_->end(); - LiveInterval::const_iterator I = std::lower_bound(B, E, Start); - - if (I != B) { - --I; - // I begins before Start, but overlaps. - if (I->end > Start) - openli_.getLI()->addRange(LiveRange(Start, std::min(End, I->end), - mapValue(I->valno))); - ++I; - } - - // The remaining ranges begin after Start. - for (;I != E && I->start < End; ++I) - openli_.getLI()->addRange(LiveRange(I->start, std::min(End, I->end), - mapValue(I->valno))); + openli_.addRange(Start, End); DEBUG(dbgs() << " use [" << Start << ';' << End << "): " << *openli_.getLI() << '\n'); } @@ -752,32 +681,24 @@ void SplitEditor::leaveIntvAfter(SlotIndex Idx) { assert(openli_.getLI() && "openIntv not called before leaveIntvAfter"); - const LiveRange *CurLR = curli_->getLiveRangeContaining(Idx.getDefIndex()); - if (!CurLR || CurLR->end <= Idx.getBoundaryIndex()) { + // The interval must be live beyond the instruction at Idx. + SlotIndex EndIdx = Idx.getNextIndex().getBaseIndex(); + VNInfo *ParentVNI = curli_->getVNInfoAt(EndIdx); + if (!ParentVNI) { DEBUG(dbgs() << " leaveIntvAfter " << Idx << ": not live\n"); return; } - // Was this value of curli live through openli? - if (!openli_.getLI()->liveAt(CurLR->valno->def)) { - DEBUG(dbgs() << " leaveIntvAfter " << Idx << ": using external value\n"); - liveThrough_ = true; - return; - } + MachineInstr *MI = lis_.getInstructionFromIndex(Idx); + assert(MI && "leaveIntvAfter called with invalid index"); - // We are going to insert a back copy, so we must have a dupli_. - LiveRange *DupLR = getDupLI()->getLiveRangeContaining(Idx.getDefIndex()); - assert(DupLR && "dupli not live into block, but curli is?"); + VNInfo *VNI = dupli_.defByCopyFrom(openli_.getLI()->reg, ParentVNI, + *MI->getParent(), MI); + + // Finally we must make sure that openli is properly extended from Idx to the + // new copy. + openli_.mapValue(ParentVNI, VNI->def.getUseIndex()); - // Insert the COPY instruction. - MachineBasicBlock::iterator I = lis_.getInstructionFromIndex(Idx); - MachineInstr *MI = BuildMI(*I->getParent(), llvm::next(I), I->getDebugLoc(), - tii_.get(TargetOpcode::COPY), dupli_.getLI()->reg) - .addReg(openli_.getLI()->reg); - SlotIndex CopyIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); - openli_.getLI()->addRange(LiveRange(Idx.getDefIndex(), CopyIdx, - mapValue(CurLR->valno))); - DupLR->valno->def = CopyIdx; DEBUG(dbgs() << " leaveIntvAfter " << Idx << ": " << *openli_.getLI() << '\n'); } @@ -788,68 +709,23 @@ assert(openli_.getLI() && "openIntv not called before leaveIntvAtTop"); SlotIndex Start = lis_.getMBBStartIdx(&MBB); - const LiveRange *CurLR = curli_->getLiveRangeContaining(Start); + VNInfo *ParentVNI = curli_->getVNInfoAt(Start); // Is curli even live-in to MBB? - if (!CurLR) { + if (!ParentVNI) { DEBUG(dbgs() << " leaveIntvAtTop at " << Start << ": not live\n"); return; } - // Is curli defined by PHI at the beginning of MBB? - bool isPHIDef = CurLR->valno->isPHIDef() && - CurLR->valno->def.getBaseIndex() == Start; - - // If MBB is using a value of curli that was defined outside the openli range, - // we don't want to copy it back here. - if (!isPHIDef && !openli_.getLI()->liveAt(CurLR->valno->def)) { - DEBUG(dbgs() << " leaveIntvAtTop at " << Start - << ": using external value\n"); - liveThrough_ = true; - return; - } - // We are going to insert a back copy, so we must have a dupli_. - LiveRange *DupLR = getDupLI()->getLiveRangeContaining(Start); - assert(DupLR && "dupli not live into block, but curli is?"); + VNInfo *VNI = dupli_.defByCopyFrom(openli_.getLI()->reg, ParentVNI, + MBB, MBB.begin()); - // Insert the COPY instruction. - MachineInstr *MI = BuildMI(MBB, MBB.begin(), DebugLoc(), - tii_.get(TargetOpcode::COPY), dupli_.getLI()->reg) - .addReg(openli_.getLI()->reg); - SlotIndex Idx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); - - // Adjust dupli and openli values. - if (isPHIDef) { - // dupli was already a PHI on entry to MBB. Simply insert an openli PHI, - // and shift the dupli def down to the COPY. - VNInfo *VNI = openli_.getLI()->getNextValue(SlotIndex(Start,true), 0, false, - lis_.getVNInfoAllocator()); - VNI->setIsPHIDef(true); - openli_.getLI()->addRange(LiveRange(VNI->def, Idx, VNI)); - - dupli_.getLI()->removeRange(Start, Idx); - DupLR->valno->def = Idx; - DupLR->valno->setIsPHIDef(false); - } else { - // The dupli value was defined somewhere inside the openli range. - DEBUG(dbgs() << " leaveIntvAtTop source value defined at " - << DupLR->valno->def << "\n"); - // FIXME: We may not need a PHI here if all predecessors have the same - // value. - VNInfo *VNI = openli_.getLI()->getNextValue(SlotIndex(Start,true), 0, false, - lis_.getVNInfoAllocator()); - VNI->setIsPHIDef(true); - openli_.getLI()->addRange(LiveRange(VNI->def, Idx, VNI)); - - // FIXME: What if DupLR->valno is used by multiple exits? SSA Update. - - // closeIntv is going to remove the superfluous live ranges. - DupLR->valno->def = Idx; - DupLR->valno->setIsPHIDef(false); - } + // Finally we must make sure that openli is properly extended from Start to + // the new copy. + openli_.mapValue(ParentVNI, VNI->def.getUseIndex()); - DEBUG(dbgs() << " leaveIntvAtTop at " << Idx << ": " << *openli_.getLI() + DEBUG(dbgs() << " leaveIntvAtTop at " << Start << ": " << *openli_.getLI() << '\n'); } @@ -861,22 +737,14 @@ DEBUG(dbgs() << " closeIntv cleaning up\n"); DEBUG(dbgs() << " open " << *openli_.getLI() << '\n'); - if (liveThrough_) { - DEBUG(dbgs() << " value live through region, leaving dupli as is.\n"); - } else { - // live out with copies inserted, or killed by region. Either way we need to - // remove the overlapping region from dupli. - getDupLI(); - for (LiveInterval::iterator I = openli_.getLI()->begin(), - E = openli_.getLI()->end(); I != E; ++I) { - dupli_.getLI()->removeRange(I->start, I->end); - } - // FIXME: A block branching to the entry block may also branch elsewhere - // curli is live. We need both openli and curli to be live in that case. - DEBUG(dbgs() << " dup2 " << *dupli_.getLI() << '\n'); - } + for (LiveInterval::iterator I = openli_.getLI()->begin(), + E = openli_.getLI()->end(); I != E; ++I) { + dupli_.getLI()->removeRange(I->start, I->end); + } + // FIXME: A block branching to the entry block may also branch elsewhere + // curli is live. We need both openli and curli to be live in that case. + DEBUG(dbgs() << " dup2 " << *dupli_.getLI() << '\n'); openli_.reset(0); - valueMap_.clear(); } /// rewrite - after all the new live ranges have been created, rewrite @@ -957,7 +825,7 @@ for (SplitAnalysis::BlockPtrSet::iterator I = Blocks.Preds.begin(), E = Blocks.Preds.end(); I != E; ++I) { MachineBasicBlock &MBB = const_cast(**I); - enterIntvAtEnd(MBB, *Loop->getHeader()); + enterIntvAtEnd(MBB); } // Switch all loop blocks. Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=114043&r1=114042&r2=114043&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Wed Sep 15 19:01:36 2010 @@ -162,8 +162,8 @@ ValueMap valueMap_; // extendTo - Find the last li_ value defined in MBB at or before Idx. The - // parentli_ is assumed to be live at Idx. Extend the live range to Idx. - // Return the found VNInfo, or NULL. + // parentli is assumed to be live at Idx. Extend the live range to include + // Idx. Return the found VNInfo, or NULL. VNInfo *extendTo(MachineBasicBlock *MBB, SlotIndex Idx); // addSimpleRange - Add a simple range from parentli_ to li_. @@ -200,6 +200,14 @@ /// All needed values whose def is not inside [Start;End) must be defined /// beforehand so mapValue will work. void addRange(SlotIndex Start, SlotIndex End); + + /// defByCopyFrom - Insert a copy from Reg to li, assuming that Reg carries + /// ParentVNI. Add a minimal live range for the new value and return it. + VNInfo *defByCopyFrom(unsigned Reg, + const VNInfo *ParentVNI, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I); + }; @@ -236,20 +244,6 @@ /// register class and spill slot as curli. LiveInterval *createInterval(); - /// getDupLI - Ensure dupli is created and return it. - LiveInterval *getDupLI(); - - /// valueMap_ - Map values in cupli to values in openli. These are direct 1-1 - /// mappings, and do not include values created by inserted copies. - DenseMap valueMap_; - - /// mapValue - Return the openIntv value that corresponds to the given curli - /// value. - VNInfo *mapValue(const VNInfo *curliVNI); - - /// A dupli value is live through openIntv. - bool liveThrough_; - /// All the new intervals created for this split are added to intervals_. SmallVectorImpl &intervals_; @@ -259,7 +253,7 @@ /// Insert a COPY instruction curli -> li. Allocate a new value from li /// defined by the COPY - VNInfo *insertCopy(LiveInterval &LI, + VNInfo *insertCopy(LiveIntervalMap &LI, MachineBasicBlock &MBB, MachineBasicBlock::iterator I); @@ -280,9 +274,7 @@ void enterIntvBefore(SlotIndex Idx); /// enterIntvAtEnd - Enter openli at the end of MBB. - /// PhiMBB is a successor inside openli where a PHI value is created. - /// Currently, all entries must share the same PhiMBB. - void enterIntvAtEnd(MachineBasicBlock &MBB, MachineBasicBlock &PhiMBB); + void enterIntvAtEnd(MachineBasicBlock &MBB); /// useIntv - indicate that all instructions in MBB should use openli. void useIntv(const MachineBasicBlock &MBB); From resistor at mac.com Wed Sep 15 19:27:35 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 00:27:35 -0000 Subject: [llvm-commits] [llvm] r114046 - /llvm/trunk/lib/VMCore/Attributes.cpp Message-ID: <20100916002735.393862A6C12C@llvm.org> Author: resistor Date: Wed Sep 15 19:27:35 2010 New Revision: 114046 URL: http://llvm.org/viewvc/llvm-project?rev=114046&view=rev Log: Fix a threaded LLVM bug due the need for operator= on reference counted AttrListImpl's. It might be possible to implement this very carefully to allow a lock-free implementation while still avoiding illegal interleavings, but I haven't been able to figure one out. Modified: llvm/trunk/lib/VMCore/Attributes.cpp Modified: llvm/trunk/lib/VMCore/Attributes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=114046&r1=114045&r2=114046&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Attributes.cpp (original) +++ llvm/trunk/lib/VMCore/Attributes.cpp Wed Sep 15 19:27:35 2010 @@ -195,6 +195,7 @@ } const AttrListPtr &AttrListPtr::operator=(const AttrListPtr &RHS) { + sys::SmartScopedLock Lock(*ALMutex); if (AttrList == RHS.AttrList) return *this; if (AttrList) AttrList->DropRef(); AttrList = RHS.AttrList; From bob.wilson at apple.com Wed Sep 15 19:31:02 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 16 Sep 2010 00:31:02 -0000 Subject: [llvm-commits] [llvm] r114047 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMInstrFormats.td ARMInstrNEON.td Message-ID: <20100916003102.56DE32A6C12C@llvm.org> Author: bwilson Date: Wed Sep 15 19:31:02 2010 New Revision: 114047 URL: http://llvm.org/viewvc/llvm-project?rev=114047&view=rev Log: Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=114047&r1=114046&r2=114047&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep 15 19:31:02 2010 @@ -640,6 +640,56 @@ MI.eraseFromParent(); } + case ARM::VLDMQ: { + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD)); + unsigned OpIdx = 0; + // Grab the Q register destination. + bool DstIsDead = MI.getOperand(OpIdx).isDead(); + unsigned DstReg = MI.getOperand(OpIdx++).getReg(); + // Copy the addrmode4 operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Add the destination operands (D subregs). + unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); + unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) + .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); + // Add an implicit def for the super-register. + MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); + break; + } + + case ARM::VSTMQ: { + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD)); + unsigned OpIdx = 0; + // Grab the Q register source. + bool SrcIsKill = MI.getOperand(OpIdx).isKill(); + unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); + // Copy the addrmode4 operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Add the source operands (D subregs). + unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); + unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); + MIB.addReg(D0).addReg(D1); + if (SrcIsKill) + // Add an implicit kill for the Q register. + (*MIB).addRegisterKilled(SrcReg, TRI, true); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); + break; + } + case ARM::VLD1q8Pseudo: case ARM::VLD1q16Pseudo: case ARM::VLD1q32Pseudo: Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=114047&r1=114046&r2=114047&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Sep 15 19:31:02 2010 @@ -1331,6 +1331,17 @@ let Inst{11-8} = 0b1010; } +// VFP Load / store multiple pseudo instructions. +class PseudoVFPLdStM pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ins pred:$p)); + let Pattern = pattern; + list Predicates = [HasVFP2]; +} + // Load / store multiple class AXDI4 pattern> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=114047&r1=114046&r2=114047&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Sep 15 19:31:02 2010 @@ -129,23 +129,17 @@ // NEON load / store instructions //===----------------------------------------------------------------------===// -// Use vldmia to load a Q register as a D register pair. -// This is equivalent to VLDMD except that it has a Q register operand -// instead of a pair of D registers. +// Use VLDM to load a Q register as a D register pair. +// This is a pseudo instruction that is expanded to VLDMD after reg alloc. def VLDMQ - : AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p), - IndexModeNone, IIC_fpLoadm, - "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "", - [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>; - -// Use vstmia to store a Q register as a D register pair. -// This is equivalent to VSTMD except that it has a Q register operand -// instead of a pair of D registers. + : PseudoVFPLdStM<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoadm, "", + [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>; + +// Use VSTM to store a Q register as a D register pair. +// This is a pseudo instruction that is expanded to VSTMD after reg alloc. def VSTMQ - : AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p), - IndexModeNone, IIC_fpStorem, - "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "", - [(store (v2f64 QPR:$src), addrmode4:$addr)]>; + : PseudoVFPLdStM<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStorem, "", + [(store (v2f64 QPR:$src), addrmode4:$addr)]>; let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { From bob.wilson at apple.com Wed Sep 15 19:31:32 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 16 Sep 2010 00:31:32 -0000 Subject: [llvm-commits] [llvm] r114048 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100916003132.8DA022A6C12C@llvm.org> Author: bwilson Date: Wed Sep 15 19:31:32 2010 New Revision: 114048 URL: http://llvm.org/viewvc/llvm-project?rev=114048&view=rev Log: Add missing break. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=114048&r1=114047&r2=114048&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep 15 19:31:32 2010 @@ -638,6 +638,7 @@ .addReg(OddSrc, getKillRegState(SrcIsKill))); TransferImpOps(MI, Even, Odd); MI.eraseFromParent(); + break; } case ARM::VLDMQ: { From daniel at zuster.org Wed Sep 15 19:42:32 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 16 Sep 2010 00:42:32 -0000 Subject: [llvm-commits] [llvm] r114050 - /llvm/trunk/Makefile.rules Message-ID: <20100916004233.074552A6C12C@llvm.org> Author: ddunbar Date: Wed Sep 15 19:42:32 2010 New Revision: 114050 URL: http://llvm.org/viewvc/llvm-project?rev=114050&view=rev Log: build: Add support for a TOOL_ORDER_FILE variable so commands can build with an order file on Darwin. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=114050&r1=114049&r2=114050&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Sep 15 19:42:32 2010 @@ -1326,6 +1326,18 @@ endif #--------------------------------------------------------- +# Tool Order File Support +#--------------------------------------------------------- + +ifeq ($(HOST_OS),Darwin) +ifdef TOOL_ORDER_FINE + +LD.Flags += -Wl,-order_file,$(TOOL_ORDER_FILE) + +endif +endif + +#--------------------------------------------------------- # Tool Version Info Support #--------------------------------------------------------- From daniel at zuster.org Wed Sep 15 19:42:35 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 16 Sep 2010 00:42:35 -0000 Subject: [llvm-commits] [llvm] r114051 - /llvm/trunk/tools/llvm-mc/llvm-mc.cpp Message-ID: <20100916004235.6312D2A6C12D@llvm.org> Author: ddunbar Date: Wed Sep 15 19:42:35 2010 New Revision: 114051 URL: http://llvm.org/viewvc/llvm-project?rev=114051&view=rev Log: llvm-mc: Teach -as-lex to print more token kinds. Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=114051&r1=114050&r2=114051&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Sep 15 19:42:35 2010 @@ -205,19 +205,24 @@ case AsmToken::Identifier: Out->os() << "identifier: " << Lexer.getTok().getString() << '\n'; break; - case AsmToken::String: - Out->os() << "string: " << Lexer.getTok().getString() << '\n'; - break; case AsmToken::Integer: Out->os() << "int: " << Lexer.getTok().getString() << '\n'; break; + case AsmToken::Register: + Out->os() << "register: " << Lexer.getTok().getRegVal() << '\n'; + break; + case AsmToken::String: + Out->os() << "string: " << Lexer.getTok().getString() << '\n'; + break; case AsmToken::Amp: Out->os() << "Amp\n"; break; case AsmToken::AmpAmp: Out->os() << "AmpAmp\n"; break; + case AsmToken::At: Out->os() << "At\n"; break; case AsmToken::Caret: Out->os() << "Caret\n"; break; case AsmToken::Colon: Out->os() << "Colon\n"; break; case AsmToken::Comma: Out->os() << "Comma\n"; break; case AsmToken::Dollar: Out->os() << "Dollar\n"; break; + case AsmToken::Dot: Out->os() << "Dot\n"; break; case AsmToken::EndOfStatement: Out->os() << "EndOfStatement\n"; break; case AsmToken::Eof: Out->os() << "Eof\n"; break; case AsmToken::Equal: Out->os() << "Equal\n"; break; @@ -227,6 +232,9 @@ case AsmToken::Greater: Out->os() << "Greater\n"; break; case AsmToken::GreaterEqual: Out->os() << "GreaterEqual\n"; break; case AsmToken::GreaterGreater: Out->os() << "GreaterGreater\n"; break; + case AsmToken::Hash: Out->os() << "Hash\n"; break; + case AsmToken::LBrac: Out->os() << "LBrac\n"; break; + case AsmToken::LCurly: Out->os() << "LCurly\n"; break; case AsmToken::LParen: Out->os() << "LParen\n"; break; case AsmToken::Less: Out->os() << "Less\n"; break; case AsmToken::LessEqual: Out->os() << "LessEqual\n"; break; @@ -237,6 +245,8 @@ case AsmToken::Pipe: Out->os() << "Pipe\n"; break; case AsmToken::PipePipe: Out->os() << "PipePipe\n"; break; case AsmToken::Plus: Out->os() << "Plus\n"; break; + case AsmToken::RBrac: Out->os() << "RBrac\n"; break; + case AsmToken::RCurly: Out->os() << "RCurly\n"; break; case AsmToken::RParen: Out->os() << "RParen\n"; break; case AsmToken::Slash: Out->os() << "Slash\n"; break; case AsmToken::Star: Out->os() << "Star\n"; break; From clattner at apple.com Wed Sep 15 20:12:05 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 18:12:05 -0700 Subject: [llvm-commits] [llvm] r114036 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp In-Reply-To: <20100915230333.98BEA2A6C12C@llvm.org> References: <20100915230333.98BEA2A6C12C@llvm.org> Message-ID: On Sep 15, 2010, at 4:03 PM, Owen Anderson wrote: > Author: resistor > Date: Wed Sep 15 18:03:33 2010 > New Revision: 114036 > > URL: http://llvm.org/viewvc/llvm-project?rev=114036&view=rev > Log: > Since PassRegistry is currently a shared global object, it needs locking. While it might intuitively seem > that all the setup of this class currently happens at static initialization time, this misses the fact > that some later events can cause mutation of the PassRegistrationListeners list, and thus cause race issues. Ok, but please don't add the mutex to PassRegistry, add it to the impl. -Chris > > Modified: > llvm/trunk/include/llvm/PassRegistry.h > llvm/trunk/lib/VMCore/PassRegistry.cpp > > Modified: llvm/trunk/include/llvm/PassRegistry.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=114036&r1=114035&r2=114036&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/PassRegistry.h (original) > +++ llvm/trunk/include/llvm/PassRegistry.h Wed Sep 15 18:03:33 2010 > @@ -18,6 +18,7 @@ > #define LLVM_PASSREGISTRY_H > > #include "llvm/ADT/StringRef.h" > +#include "llvm/System/Mutex.h" > > namespace llvm { > > @@ -32,6 +33,7 @@ > /// each thread. > class PassRegistry { > mutable void *pImpl; > + mutable sys::SmartMutex Lock; > void *getImpl() const; > > public: > > Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=114036&r1=114035&r2=114036&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) > +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Wed Sep 15 18:03:33 2010 > @@ -88,6 +88,7 @@ > // > > void PassRegistry::registerPass(const PassInfo &PI) { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > bool Inserted = > Impl->PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second; > @@ -101,6 +102,7 @@ > } > > void PassRegistry::unregisterPass(const PassInfo &PI) { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > PassRegistryImpl::MapType::iterator I = > Impl->PassInfoMap.find(PI.getTypeInfo()); > @@ -112,6 +114,7 @@ > } > > void PassRegistry::enumerateWith(PassRegistrationListener *L) { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > for (PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.begin(), > E = Impl->PassInfoMap.end(); I != E; ++I) > @@ -124,6 +127,7 @@ > const void *PassID, > PassInfo& Registeree, > bool isDefault) { > + sys::SmartScopedLock Guard(Lock); > PassInfo *InterfaceInfo = const_cast(getPassInfo(InterfaceID)); > if (InterfaceInfo == 0) { > // First reference to Interface, register it now. > @@ -159,11 +163,14 @@ > } > > void PassRegistry::addRegistrationListener(PassRegistrationListener *L) { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > Impl->Listeners.push_back(L); > } > > void PassRegistry::removeRegistrationListener(PassRegistrationListener *L) { > + sys::SmartScopedLock Guard(Lock); > + > // NOTE: This is necessary, because removeRegistrationListener() can be called > // as part of the llvm_shutdown sequence. Since we have no control over the > // order of that sequence, we need to gracefully handle the case where the > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Sep 15 20:13:15 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 18:13:15 -0700 Subject: [llvm-commits] [llvm] r114046 - /llvm/trunk/lib/VMCore/Attributes.cpp In-Reply-To: <20100916002735.393862A6C12C@llvm.org> References: <20100916002735.393862A6C12C@llvm.org> Message-ID: <9264D13F-9DDA-40B2-8FC9-33959EEDA5E6@apple.com> On Sep 15, 2010, at 5:27 PM, Owen Anderson wrote: > Author: resistor > Date: Wed Sep 15 19:27:35 2010 > New Revision: 114046 > > URL: http://llvm.org/viewvc/llvm-project?rev=114046&view=rev > Log: > Fix a threaded LLVM bug due the need for operator= on reference counted AttrListImpl's. It might > be possible to implement this very carefully to allow a lock-free implementation while still > avoiding illegal interleavings, but I haven't been able to figure one out. What is the compile-time performance impact of this for the non-threaded case? -Chris > > Modified: > llvm/trunk/lib/VMCore/Attributes.cpp > > Modified: llvm/trunk/lib/VMCore/Attributes.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=114046&r1=114045&r2=114046&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Attributes.cpp (original) > +++ llvm/trunk/lib/VMCore/Attributes.cpp Wed Sep 15 19:27:35 2010 > @@ -195,6 +195,7 @@ > } > > const AttrListPtr &AttrListPtr::operator=(const AttrListPtr &RHS) { > + sys::SmartScopedLock Lock(*ALMutex); > if (AttrList == RHS.AttrList) return *this; > if (AttrList) AttrList->DropRef(); > AttrList = RHS.AttrList; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Sep 15 20:24:04 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 15 Sep 2010 18:24:04 -0700 Subject: [llvm-commits] [llvm] r113858 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/LibCallAliasAnalysis.h include/llvm/Analysis/LibCallSemantics.h include/llvm/LLVMContext.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp lib/Analysis/LibCallAliasAnalysis.cpp lib/Analysis/ScalarEvolutionAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/VMCore/LLVMContext.cpp In-Reply-To: <20100914212510.DD2912A6C12C@llvm.org> References: <20100914212510.DD2912A6C12C@llvm.org> Message-ID: <4AF054A2-3D4A-4D33-B83B-BD69A0210AEF@apple.com> On Sep 14, 2010, at 2:25 PM, Dan Gohman wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=113858&view=rev > Log: > Remove the experimental AliasAnalysis::getDependency interface, which > isn't a good level of abstraction for memdep. Instead, generalize > AliasAnalysis::alias and related interfaces with a new Location > class for describing a memory location. For now, this is the same > Pointer and Size as before, plus an additional field for a TBAA tag. Great! > +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Sep 14 16:25:10 2010 > @@ -83,6 +83,22 @@ > /// Alias Queries... > /// > > + /// Location - A description of a memory location. > + struct Location { > + /// Ptr - The address of the start of the location. > + const Value *Ptr; > + /// Size - The size of the location. > + unsigned Size; > + /// TBAATag - The metadata node which describes the TBAA type of > + /// the location, or null if there is no (unique) tag. > + const MDNode *TBAATag; > + > + explicit Location(const Value *P = 0, Should the pointer be allowed to be null? Is Location() something that is useful? > + /// pointsToConstantMemory - If the specified memory location is known to be > + /// constant, return true. This allows disambiguation of store > /// instructions from constant pointers. > /// > + virtual bool pointsToConstantMemory(const Location &Loc); Interesting. I agree with the change, but I'll have to think about what this can be used for. -Chris From bigcheesegs at gmail.com Wed Sep 15 21:03:28 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 15 Sep 2010 22:03:28 -0400 Subject: [llvm-commits] [llvm] r113834 - in /llvm/trunk: lib/Target/CBackend/CBackend.cpp utils/TableGen/IntrinsicEmitter.cpp In-Reply-To: References: <20100914042739.2B7CF2A6C12C@llvm.org> Message-ID: On Tue, Sep 14, 2010 at 7:59 PM, Francois Pichet wrote: > hi, > > Can't you not rewrite EmitSuffix like this to get rid of the warning? > > void IntrinsicEmitter::EmitSuffix(raw_ostream &OS) { > ?OS << "#if defined(_MSC_VER) && defined(setjmp)\n" > ? ? ? ?"// let's return it to _setjmp state\n" > ? ? ? ?"# ?pragma pop_macro(\"setjmp\")\n" > ? ? ? ?"#endif\n\n"; > } No, because EmitPrefix has #undef setjmp. What I actually need to do is add back setjmp_undefined_for_visual_studio, but this time undefine it in the suffix. Without this, the next time this is encountered (which is included 2x in CBackend), setjmp will be popped more than it should. The push/pop macro is still required because setjmp isn't just defined as _setjmp, it can be other things. - Michael Spencer > > > On Tue, Sep 14, 2010 at 12:27 AM, Michael J. Spencer > wrote: >> Author: mspencer >> Date: Mon Sep 13 23:27:38 2010 >> New Revision: 113834 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113834&view=rev >> Log: >> CBackend: Fix MSVC build. >> >> This may produce warnings on MSVS, but it's better than failures. >> >> Modified: >> ? ?llvm/trunk/lib/Target/CBackend/CBackend.cpp >> ? ?llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp >> >> Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=113834&r1=113833&r2=113834&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) >> +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Sep 13 23:27:38 2010 >> @@ -50,6 +50,10 @@ >> ?#include "llvm/System/Host.h" >> ?#include "llvm/Config/config.h" >> ?#include >> +// Some ms header decided to define setjmp as _setjmp, undo this for this file. >> +#ifdef _MSC_VER >> +#undef setjmp >> +#endif >> ?using namespace llvm; >> >> ?extern "C" void LLVMInitializeCBackendTarget() { >> >> Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=113834&r1=113833&r2=113834&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Mon Sep 13 23:27:38 2010 >> @@ -69,15 +69,15 @@ >> ?void IntrinsicEmitter::EmitPrefix(raw_ostream &OS) { >> ? OS << "// VisualStudio defines setjmp as _setjmp\n" >> ? ? ? ? "#if defined(_MSC_VER) && defined(setjmp)\n" >> - ? ? ? ?"#define setjmp_undefined_for_visual_studio\n" >> - ? ? ? ?"#undef setjmp\n" >> + ? ? ? ?"# ?pragma push_macro(\"setjmp\")\n" >> + ? ? ? ?"# ?undef setjmp\n" >> ? ? ? ? "#endif\n\n"; >> ?} >> >> ?void IntrinsicEmitter::EmitSuffix(raw_ostream &OS) { >> - ?OS << "#if defined(_MSC_VER) && defined(setjmp_undefined_for_visual_studio)\n" >> + ?OS << "#if defined(_MSC_VER)\n" >> ? ? ? ? "// let's return it to _setjmp state\n" >> - ? ? ? ?"#define setjmp _setjmp\n" >> + ? ? ? ?"# ?pragma pop_macro(\"setjmp\")\n" >> ? ? ? ? "#endif\n\n"; >> ?} >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From criswell at uiuc.edu Wed Sep 15 22:29:22 2010 From: criswell at uiuc.edu (John Criswell) Date: Thu, 16 Sep 2010 03:29:22 -0000 Subject: [llvm-commits] [poolalloc] r114063 - /poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Message-ID: <20100916032922.EE4E92A6C12C@llvm.org> Author: criswell Date: Wed Sep 15 22:29:22 2010 New Revision: 114063 URL: http://llvm.org/viewvc/llvm-project?rev=114063&view=rev Log: Modifed the simple pool allocation pass so that it does not recreate the global pool if it already exists. This allows it to yield correct code when executed multiple times. Also added support for transforming stack registration. Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp?rev=114063&r1=114062&r2=114063&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PASimple.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Wed Sep 15 22:29:22 2010 @@ -92,7 +92,9 @@ (funcname == "sc.lscheckalign") || (funcname == "sc.lscheckalignui") || (funcname == "sc.boundscheck") || - (funcname == "sc.boundscheckui")) { + (funcname == "sc.boundscheckui") || + (funcname == "sc.pool_register_stack") || + (funcname == "sc.pool_unregister_stack")) { return 1; } @@ -469,6 +471,14 @@ unsigned Align, Module& M) { // + // See if the global pool has already been created. If so, then just return + // it. + // + if (GlobalVariable * GV = M.getNamedGlobal ("__poolalloc_GlobalPool")) { + return GV; + } + + // // Give poolinit() a dummy body. A later transform will remove the dummy // body. // From grosbach at apple.com Wed Sep 15 22:45:22 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 03:45:22 -0000 Subject: [llvm-commits] [llvm] r114064 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Message-ID: <20100916034522.196BA2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 15 22:45:21 2010 New Revision: 114064 URL: http://llvm.org/viewvc/llvm-project?rev=114064&view=rev Log: store MC FP immediates as a double instead of as an APFloat, thus avoiding an unnecessary dtor for MCOperand. Modified: llvm/trunk/include/llvm/MC/MCInst.h llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=114064&r1=114063&r2=114064&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Wed Sep 15 22:45:21 2010 @@ -16,7 +16,6 @@ #ifndef LLVM_MC_MCINST_H #define LLVM_MC_MCINST_H -#include "llvm/ADT/APFloat.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/System/DataTypes.h" @@ -42,11 +41,9 @@ union { unsigned RegVal; int64_t ImmVal; + double FPImmVal; const MCExpr *ExprVal; }; - // This can't go in the union due to the non-trivial copy constructor - // of APFloat. It's still only valid for Kind == kFPImmediate, though. - APFloat FPImmVal; public: MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} @@ -78,12 +75,12 @@ ImmVal = Val; } - const APFloat &getFPImm() const { + const double &getFPImm() const { assert(isFPImm() && "This is not an FP immediate"); return FPImmVal; } - void setFPImm(const APFloat &Val) { + void setFPImm(double Val) { assert(isFPImm() && "This is not an FP immediate"); FPImmVal = Val; } @@ -109,7 +106,7 @@ Op.ImmVal = Val; return Op; } - static MCOperand CreateFPImm(const APFloat &Val) { + static MCOperand CreateFPImm(double Val) { MCOperand Op; Op.Kind = kFPImmediate; Op.FPImmVal = Val; Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=114064&r1=114063&r2=114064&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Sep 15 22:45:21 2010 @@ -157,7 +157,8 @@ MO.getBlockAddress())); break; case MachineOperand::MO_FPImmediate: - MCOp = MCOperand::CreateFPImm(MO.getFPImm()->getValueAPF()); + MCOp = + MCOperand::CreateFPImm(MO.getFPImm()->getValueAPF().convertToDouble()); break; } Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114064&r1=114063&r2=114064&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 22:45:21 2010 @@ -747,12 +747,12 @@ void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - O << '#' << MI->getOperand(OpNum).getFPImm().convertToFloat(); + O << '#' << (float)MI->getOperand(OpNum).getFPImm(); } void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - O << '#' << MI->getOperand(OpNum).getFPImm().convertToDouble(); + O << '#' << MI->getOperand(OpNum).getFPImm(); } void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=114064&r1=114063&r2=114064&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Sep 15 22:45:21 2010 @@ -1973,7 +1973,10 @@ // The asm syntax specifies the floating point value, not the 8-bit literal. APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), Opcode == ARM::FCONSTD ? 64 : 32); - MI.addOperand(MCOperand::CreateFPImm(APFloat(immRaw, true))); + APFloat immFP = APFloat(immRaw, true); + double imm = Opcode == ARM::FCONSTD ? immFP.convertToDouble() : + immFP.convertToFloat(); + MI.addOperand(MCOperand::CreateFPImm(imm)); ++OpIdx; } From bob.wilson at apple.com Wed Sep 15 23:25:37 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 16 Sep 2010 04:25:37 -0000 Subject: [llvm-commits] [llvm] r114066 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100916042537.AEFCB2A6C12C@llvm.org> Author: bwilson Date: Wed Sep 15 23:25:37 2010 New Revision: 114066 URL: http://llvm.org/viewvc/llvm-project?rev=114066&view=rev Log: When expanding ARM pseudo registers, copy the existing predicate operands instead of using default predicates on the expanded instructions. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=114066&r1=114065&r2=114066&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep 15 23:25:37 2010 @@ -367,12 +367,21 @@ if (TableEntry->HasWriteBack) MIB.addOperand(MI.getOperand(OpIdx++)); - MIB = AddDefaultPred(MIB); // For an instruction writing double-spaced subregs, the pseudo instruction - // has an extra operand that is a use of the super-register. Copy that over + // has an extra operand that is a use of the super-register. Record the + // operand index and skip over it. + unsigned SrcOpIdx = 0; + if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) + SrcOpIdx = OpIdx++; + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + + // Copy the super-register source operand used for double-spaced subregs over // to the new instruction as an implicit operand. - if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) { - MachineOperand MO = MI.getOperand(OpIdx); + if (SrcOpIdx != 0) { + MachineOperand MO = MI.getOperand(SrcOpIdx); MO.setImplicit(true); MIB.addOperand(MO); } @@ -407,7 +416,7 @@ MIB.addOperand(MI.getOperand(OpIdx++)); bool SrcIsKill = MI.getOperand(OpIdx).isKill(); - unsigned SrcReg = MI.getOperand(OpIdx).getReg(); + unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); unsigned D0, D1, D2, D3; GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); MIB.addReg(D0).addReg(D1); @@ -415,7 +424,11 @@ MIB.addReg(D2); if (NumRegs > 3) MIB.addReg(D3); - MIB = AddDefaultPred(MIB); + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + if (SrcIsKill) // Add an implicit kill for the super-reg. (*MIB).addRegisterKilled(SrcReg, TRI, true); @@ -491,8 +504,12 @@ // Add the lane number operand. MIB.addImm(Lane); + OpIdx += 1; + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); - MIB = AddDefaultPred(MIB); // Copy the super-register source to be an implicit source. MO.setImplicit(true); MIB.addOperand(MO); @@ -529,9 +546,12 @@ MIB.addReg(D3); // Copy the other source register operand. - MIB.addOperand(MI.getOperand(OpIdx)); + MIB.addOperand(MI.getOperand(OpIdx++)); + + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); - MIB = AddDefaultPred(MIB); if (SrcIsKill) // Add an implicit kill for the super-reg. (*MIB).addRegisterKilled(SrcReg, TRI, true); From bob.wilson at apple.com Wed Sep 15 23:55:00 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 16 Sep 2010 04:55:00 -0000 Subject: [llvm-commits] [llvm] r114067 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100916045500.320B72A6C12C@llvm.org> Author: bwilson Date: Wed Sep 15 23:55:00 2010 New Revision: 114067 URL: http://llvm.org/viewvc/llvm-project?rev=114067&view=rev Log: Remove support for "dregpair" operand modifier, now that it is no longer being used for anything. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114067&r1=114066&r2=114067&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 15 23:55:00 2010 @@ -337,13 +337,7 @@ case MachineOperand::MO_Register: { unsigned Reg = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(Reg)); - if (Modifier && strcmp(Modifier, "dregpair") == 0) { - unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0); - unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1); - O << '{' - << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi) - << '}'; - } else if (Modifier && strcmp(Modifier, "lane") == 0) { + if (Modifier && strcmp(Modifier, "lane") == 0) { unsigned RegNum = getARMRegisterNumbering(Reg); unsigned DReg = TM.getRegisterInfo()->getMatchingSuperReg(Reg, Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114067&r1=114066&r2=114067&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 23:55:00 2010 @@ -29,30 +29,6 @@ #undef MachineInstr #undef ARMAsmPrinter -// Get the constituent sub-regs for a dregpair from a Q register. -static std::pair GetDRegPair(unsigned QReg) { - switch (QReg) { - default: - assert(0 && "Unexpected register enum"); - case ARM::Q0: return std::pair(ARM::D0, ARM::D1); - case ARM::Q1: return std::pair(ARM::D2, ARM::D3); - case ARM::Q2: return std::pair(ARM::D4, ARM::D5); - case ARM::Q3: return std::pair(ARM::D6, ARM::D7); - case ARM::Q4: return std::pair(ARM::D8, ARM::D9); - case ARM::Q5: return std::pair(ARM::D10, ARM::D11); - case ARM::Q6: return std::pair(ARM::D12, ARM::D13); - case ARM::Q7: return std::pair(ARM::D14, ARM::D15); - case ARM::Q8: return std::pair(ARM::D16, ARM::D17); - case ARM::Q9: return std::pair(ARM::D18, ARM::D19); - case ARM::Q10: return std::pair(ARM::D20, ARM::D21); - case ARM::Q11: return std::pair(ARM::D22, ARM::D23); - case ARM::Q12: return std::pair(ARM::D24, ARM::D25); - case ARM::Q13: return std::pair(ARM::D26, ARM::D27); - case ARM::Q14: return std::pair(ARM::D28, ARM::D29); - case ARM::Q15: return std::pair(ARM::D30, ARM::D31); - } -} - static unsigned getDPRSuperRegForSPR(unsigned Reg) { switch (Reg) { default: @@ -165,11 +141,7 @@ const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { unsigned Reg = Op.getReg(); - if (Modifier && strcmp(Modifier, "dregpair") == 0) { - std::pair dregpair = GetDRegPair(Reg); - O << '{' << getRegisterName(dregpair.first) << ", " - << getRegisterName(dregpair.second) << '}'; - } else if (Modifier && strcmp(Modifier, "lane") == 0) { + if (Modifier && strcmp(Modifier, "lane") == 0) { unsigned RegNum = getARMRegisterNumbering(Reg); unsigned DReg = getDPRSuperRegForSPR(Reg); O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; From baldrick at free.fr Thu Sep 16 03:20:49 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 16 Sep 2010 08:20:49 -0000 Subject: [llvm-commits] [llvm] r114072 - /llvm/trunk/lib/Support/ErrorHandling.cpp Message-ID: <20100916082049.567F32A6C12C@llvm.org> Author: baldrick Date: Thu Sep 16 03:20:49 2010 New Revision: 114072 URL: http://llvm.org/viewvc/llvm-project?rev=114072&view=rev Log: Some versions of gcc still warn about "ignoring return value ... declared with attribute warn_unused_result" here - suppress the warning harder. Modified: llvm/trunk/lib/Support/ErrorHandling.cpp Modified: llvm/trunk/lib/Support/ErrorHandling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ErrorHandling.cpp?rev=114072&r1=114071&r2=114072&view=diff ============================================================================== --- llvm/trunk/lib/Support/ErrorHandling.cpp (original) +++ llvm/trunk/lib/Support/ErrorHandling.cpp Thu Sep 16 03:20:49 2010 @@ -69,7 +69,8 @@ raw_svector_ostream OS(Buffer); OS << "LLVM ERROR: " << Reason << "\n"; StringRef MessageStr = OS.str(); - (void)::write(2, MessageStr.data(), MessageStr.size()); + ssize_t written = ::write(2, MessageStr.data(), MessageStr.size()); + (void)written; // If something went wrong, we deliberately just give up. } // If we reached here, we are failing ungracefully. Run the interrupt handlers From baldrick at free.fr Thu Sep 16 03:25:48 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 16 Sep 2010 08:25:48 -0000 Subject: [llvm-commits] [llvm] r114073 - in /llvm/trunk: include/llvm/ADT/Triple.h lib/Support/Triple.cpp unittests/ADT/TripleTest.cpp Message-ID: <20100916082548.A6B7B2A6C12C@llvm.org> Author: baldrick Date: Thu Sep 16 03:25:48 2010 New Revision: 114073 URL: http://llvm.org/viewvc/llvm-project?rev=114073&view=rev Log: Add better support for environment portion of triple. Original patch by Cameron Esfahani, tweaked to use array_lengthof. Modified: llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/lib/Support/Triple.cpp llvm/trunk/unittests/ADT/TripleTest.cpp Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=114073&r1=114072&r2=114073&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Thu Sep 16 03:25:48 2010 @@ -95,6 +95,9 @@ Haiku, Minix }; + enum EnvironmentType { + UnknownEnvironment + }; private: std::string Data; @@ -108,10 +111,14 @@ /// The parsed OS type. mutable OSType OS; + /// The parsed Environment type. + mutable EnvironmentType Environment; + bool isInitialized() const { return Arch != InvalidArch; } static ArchType ParseArch(StringRef ArchName); static VendorType ParseVendor(StringRef VendorName); static OSType ParseOS(StringRef OSName); + static EnvironmentType ParseEnvironment(StringRef EnvironmentName); void Parse() const; public: @@ -128,6 +135,17 @@ Data += OSStr; } + explicit Triple(StringRef ArchStr, StringRef VendorStr, StringRef OSStr, + StringRef EnvironmentStr) + : Data(ArchStr), Arch(InvalidArch) { + Data += '-'; + Data += VendorStr; + Data += '-'; + Data += OSStr; + Data += '-'; + Data += EnvironmentStr; + } + /// @} /// @name Normalization /// @{ @@ -166,6 +184,12 @@ return getEnvironmentName() != ""; } + /// getEnvironment - Get the parsed environment type of this triple. + EnvironmentType getEnvironment() const { + if (!isInitialized()) Parse(); + return Environment; + } + /// @} /// @name Direct Component Access /// @{ @@ -225,6 +249,10 @@ /// to a known type. void setOS(OSType Kind); + /// setEnvironment - Set the environment (fourth) component of the triple + /// to a known type. + void setEnvironment(EnvironmentType Kind); + /// setTriple - Set all components to the new triple \arg Str. void setTriple(const Twine &Str); @@ -272,9 +300,14 @@ /// vendor. static const char *getVendorTypeName(VendorType Kind); - /// getOSTypeName - Get the canonical name for the \arg Kind vendor. + /// getOSTypeName - Get the canonical name for the \arg Kind operating + /// system. static const char *getOSTypeName(OSType Kind); + /// getEnvironmentTypeName - Get the canonical name for the \arg Kind + /// environment. + static const char *getEnvironmentTypeName(EnvironmentType Kind); + /// @} /// @name Static helpers for converting alternate architecture names. /// @{ Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=114073&r1=114072&r2=114073&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Thu Sep 16 03:25:48 2010 @@ -10,6 +10,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Twine.h" #include #include @@ -114,6 +115,14 @@ return ""; } +const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) { + switch (Kind) { + case UnknownEnvironment: return "unknown"; + } + + return ""; +} + Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { if (Name == "alpha") return alpha; @@ -329,12 +338,17 @@ return UnknownOS; } +Triple::EnvironmentType Triple::ParseEnvironment(StringRef EnvironmentName) { + return UnknownEnvironment; +} + void Triple::Parse() const { assert(!isInitialized() && "Invalid parse call."); Arch = ParseArch(getArchName()); Vendor = ParseVendor(getVendorName()); OS = ParseOS(getOSName()); + Environment = ParseEnvironment(getEnvironmentName()); assert(isInitialized() && "Failed to initialize!"); } @@ -361,24 +375,28 @@ OSType OS = UnknownOS; if (Components.size() > 2) OS = ParseOS(Components[2]); + EnvironmentType Environment = UnknownEnvironment; + if (Components.size() > 3) + Environment = ParseEnvironment(Components[3]); // Note which components are already in their final position. These will not // be moved. - bool Found[3]; + bool Found[4]; Found[0] = Arch != UnknownArch; Found[1] = Vendor != UnknownVendor; Found[2] = OS != UnknownOS; + Found[3] = Environment != UnknownEnvironment; // If they are not there already, permute the components into their canonical // positions by seeing if they parse as a valid architecture, and if so moving // the component to the architecture position etc. - for (unsigned Pos = 0; Pos != 3; ++Pos) { + for (unsigned Pos = 0; Pos != array_lengthof(Found); ++Pos) { if (Found[Pos]) continue; // Already in the canonical position. for (unsigned Idx = 0; Idx != Components.size(); ++Idx) { // Do not reparse any components that already matched. - if (Idx < 3 && Found[Idx]) + if (Idx < array_lengthof(Found) && Found[Idx]) continue; // Does this component parse as valid for the target position? @@ -399,6 +417,10 @@ OS = ParseOS(Comp); Valid = OS != UnknownOS; break; + case 3: + Environment = ParseEnvironment(Comp); + Valid = Environment != UnknownEnvironment; + break; } if (!Valid) continue; // Nope, try the next component. @@ -417,7 +439,7 @@ // components to the right. for (unsigned i = Pos; !CurrentComponent.empty(); ++i) { // Skip over any fixed components. - while (i < 3 && Found[i]) ++i; + while (i < array_lengthof(Found) && Found[i]) ++i; // Place the component at the new position, getting the component // that was at this position - it will be moved right. std::swap(CurrentComponent, Components[i]); @@ -431,7 +453,7 @@ StringRef CurrentComponent(""); // The empty component. for (unsigned i = Idx; i < Components.size(); ++i) { // Skip over any fixed components. - while (i < 3 && Found[i]) ++i; + while (i < array_lengthof(Found) && Found[i]) ++i; // Place the component at the new position, getting the component // that was at this position - it will be moved right. std::swap(CurrentComponent, Components[i]); @@ -444,7 +466,7 @@ Components.push_back(CurrentComponent); // Advance Idx to the component's new position. - while (++Idx < 3 && Found[Idx]) {} + while (++Idx < array_lengthof(Found) && Found[Idx]) {} } while (Idx < Pos); // Add more until the final position is reached. } assert(Pos < Components.size() && Components[Pos] == Comp && @@ -574,6 +596,10 @@ setOSName(getOSTypeName(Kind)); } +void Triple::setEnvironment(EnvironmentType Kind) { + setEnvironmentName(getEnvironmentTypeName(Kind)); +} + void Triple::setArchName(StringRef Str) { // Work around a miscompilation bug for Twines in gcc 4.0.3. SmallString<64> Triple; Modified: llvm/trunk/unittests/ADT/TripleTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/TripleTest.cpp?rev=114073&r1=114072&r2=114073&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/TripleTest.cpp (original) +++ llvm/trunk/unittests/ADT/TripleTest.cpp Thu Sep 16 03:25:48 2010 @@ -79,16 +79,21 @@ EXPECT_EQ(Triple::x86, T.getArch()); EXPECT_EQ(Triple::Apple, T.getVendor()); EXPECT_EQ(Triple::Darwin, T.getOS()); + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); T = Triple("x86_64-pc-linux-gnu"); EXPECT_EQ(Triple::x86_64, T.getArch()); EXPECT_EQ(Triple::PC, T.getVendor()); EXPECT_EQ(Triple::Linux, T.getOS()); + // When environments are defined, change this test to verify the "gnu" + // environment. + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); T = Triple("powerpc-dunno-notsure"); EXPECT_EQ(Triple::ppc, T.getArch()); EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); EXPECT_EQ(Triple::UnknownOS, T.getOS()); + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); T = Triple("huh"); EXPECT_EQ(Triple::UnknownArch, T.getArch()); @@ -119,10 +124,12 @@ EXPECT_EQ("i386-b-c", Triple::normalize("i386-b-c")); EXPECT_EQ("i386-a-c", Triple::normalize("a-i386-c")); EXPECT_EQ("i386-a-b", Triple::normalize("a-b-i386")); + EXPECT_EQ("i386-a-b-c", Triple::normalize("a-b-c-i386")); EXPECT_EQ("a-pc-c", Triple::normalize("a-pc-c")); EXPECT_EQ("-pc-b-c", Triple::normalize("pc-b-c")); EXPECT_EQ("a-pc-b", Triple::normalize("a-b-pc")); + EXPECT_EQ("a-pc-b-c", Triple::normalize("a-b-c-pc")); EXPECT_EQ("a-b-linux", Triple::normalize("a-b-linux")); EXPECT_EQ("--linux-b-c", Triple::normalize("linux-b-c")); @@ -210,6 +217,7 @@ EXPECT_EQ(Triple::UnknownArch, T.getArch()); EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); EXPECT_EQ(Triple::UnknownOS, T.getOS()); + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); T.setArchName("i386"); EXPECT_EQ(Triple::x86, T.getArch()); From baldrick at free.fr Thu Sep 16 03:28:28 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 16 Sep 2010 10:28:28 +0200 Subject: [llvm-commits] [PATCH] Add better support for environment portion of triple In-Reply-To: <53F36670-C33C-4BE8-B41B-E0B721BA5F26@apple.com> References: <71F87371-10DB-49BB-AB6C-CD78208A23E6@apple.com> <4C908A47.9070103@free.fr> <53F36670-C33C-4BE8-B41B-E0B721BA5F26@apple.com> Message-ID: <4C91D52C.9080703@free.fr> Hi Cameron, I applied this in commit 114073 (tweaked to use array_lengthof rather than 4). Ciao, Duncan. From clchiou at gmail.com Thu Sep 16 04:43:55 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Thu, 16 Sep 2010 17:43:55 +0800 Subject: [llvm-commits] [PATCH] Add exit instruction to PTX backend In-Reply-To: References: Message-ID: Hi Chris, Thanks for the comments. I've put {'s on the previous line and removed accidentally added tab characters. I've also checked again that cmake file was updated. Thanks for reminding. I regenerate patch against r114073. Please take a look. Regards, Che-Liang On Thu, Sep 16, 2010 at 6:54 AM, Chris Lattner wrote: > > On Sep 14, 2010, at 1:59 AM, Che-Liang Chiou wrote: > >> Hi, >> >> I have created a patch that adds "exit" instruction to PTX backend. >> >> SVN revision: >> 113836 >> >> TEST: >> $ cd llvm/test/ >> $ llvm-lit CodeGen/PTX/exit.ll >> -- Testing: 1 tests, 8 threads -- >> PASS: LLVM :: CodeGen/PTX/exit.ll (1 of 1) >> Testing Time: 0.01s >> ?Expected Passes ? ?: 1 > > Looks good to me. ?Please make sure to update the cmake file. ?Also, please put your {'s on the "previous line" instead of on a new line. > > -Chris > >> >> Note: >> Compiling auto generated cpp file produces warning. ?I suspect the it >> is because of too few instructions in .td file for now. ?The warning >> message should look like this: >> >> In file included from PTXAsmPrinter.cpp:50: >> /usr/local/google/clchiou/llvm/llvm/lib/Target/PTX/AsmPrinter/../PTXGenAsmWriter.inc: >> In member function >> ?void::PTXAsmPrinter::printInstruction(const >> llvm::MachineInstr*, llvm::raw_ostream&)?: >> /usr/local/google/clchiou/llvm/llvm/lib/Target/PTX/AsmPrinter/../PTXGenAsmWriter.inc:43: >> warning: right shift count >= width of type >> >> This warning should disappear after more instructions are added. >> >> Regards, >> Che-Liang >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- A non-text attachment was scrubbed... Name: r114073-add-exit.patch Type: text/x-patch Size: 31614 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/87cdf8a6/attachment-0001.bin From kalle.raiskila at nokia.com Thu Sep 16 07:29:33 2010 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Thu, 16 Sep 2010 12:29:33 -0000 Subject: [llvm-commits] [llvm] r114074 - in /llvm/trunk: lib/Target/CellSPU/SPU64InstrInfo.td lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUInstrInfo.td test/CodeGen/CellSPU/v2i32.ll Message-ID: <20100916122933.9B2B72A6C12C@llvm.org> Author: kraiskil Date: Thu Sep 16 07:29:33 2010 New Revision: 114074 URL: http://llvm.org/viewvc/llvm-project?rev=114074&view=rev Log: Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. Modified: llvm/trunk/lib/Target/CellSPU/SPU64InstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/test/CodeGen/CellSPU/v2i32.ll Modified: llvm/trunk/lib/Target/CellSPU/SPU64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU64InstrInfo.td?rev=114074&r1=114073&r2=114074&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPU64InstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPU64InstrInfo.td Thu Sep 16 07:29:33 2010 @@ -54,8 +54,8 @@ // The i64 seteq fragment that does the scalar->vector conversion and // comparison: def CEQr64compare: - CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (ORv2i64_i64 R64C:$rA), - (ORv2i64_i64 R64C:$rB))), 0xb)>; + CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG))), 0xb)>; // The i64 seteq fragment that does the vector comparison def CEQv2i64compare: @@ -67,12 +67,14 @@ // v2i64 seteq (equality): the setcc result is v4i32 multiclass CompareEqual64 { // Plain old comparison, converts back to i32 scalar - def r64: CodeFrag<(ORi32_v4i32 CEQr64compare.Fragment)>; - def v2i64: CodeFrag<(ORi32_v4i32 CEQv2i64compare.Fragment)>; + def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQr64compare.Fragment, R32C))>; + def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>; // SELB mask from FSM: - def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQr64compare.Fragment))>; - def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQv2i64compare.Fragment))>; + def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CEQr64compare.Fragment), R32C))>; + def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CEQv2i64compare.Fragment), R32C))>; } defm I64EQ: CompareEqual64; @@ -89,10 +91,12 @@ //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ def CLGTr64ugt: - CodeFrag<(CLGTv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>; + CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG))>; def CLGTr64eq: - CodeFrag<(CEQv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>; + CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG))>; def CLGTr64compare: CodeFrag<(SELBv2i64 CLGTr64ugt.Fragment, @@ -112,12 +116,14 @@ multiclass CompareLogicalGreaterThan64 { // Plain old comparison, converts back to i32 scalar - def r64: CodeFrag<(ORi32_v4i32 CLGTr64compare.Fragment)>; + def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CLGTr64compare.Fragment, R32C))>; def v2i64: CodeFrag; // SELB mask from FSM: - def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTr64compare.Fragment))>; - def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTv2i64compare.Fragment))>; + def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CLGTr64compare.Fragment), R32C))>; + def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CLGTv2i64compare.Fragment), R32C))>; } defm I64LGT: CompareLogicalGreaterThan64; @@ -144,12 +150,14 @@ multiclass CompareLogicalGreaterEqual64 { // Plain old comparison, converts back to i32 scalar - def r64: CodeFrag<(ORi32_v4i32 CLGEr64compare.Fragment)>; + def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CLGEr64compare.Fragment, R32C))>; def v2i64: CodeFrag; // SELB mask from FSM: - def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGEr64compare.Fragment))>; - def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGEv2i64compare.Fragment))>; + def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CLGEr64compare.Fragment), R32C))>; + def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CLGEv2i64compare.Fragment),R32C))>; } defm I64LGE: CompareLogicalGreaterEqual64; @@ -168,10 +176,12 @@ //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ def CGTr64sgt: - CodeFrag<(CGTv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>; + CodeFrag<(CGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG))>; def CGTr64eq: - CodeFrag<(CEQv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>; + CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG))>; def CGTr64compare: CodeFrag<(SELBv2i64 CGTr64sgt.Fragment, @@ -191,12 +201,14 @@ multiclass CompareGreaterThan64 { // Plain old comparison, converts back to i32 scalar - def r64: CodeFrag<(ORi32_v4i32 CGTr64compare.Fragment)>; + def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CGTr64compare.Fragment, R32C))>; def v2i64: CodeFrag; // SELB mask from FSM: - def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGTr64compare.Fragment))>; - def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGTv2i64compare.Fragment))>; + def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CGTr64compare.Fragment), R32C))>; + def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS + (FSMv4i32 CGTv2i64compare.Fragment), R32C))>; } defm I64GT: CompareLogicalGreaterThan64; @@ -223,12 +235,12 @@ multiclass CompareGreaterEqual64 { // Plain old comparison, converts back to i32 scalar - def r64: CodeFrag<(ORi32_v4i32 CGEr64compare.Fragment)>; + def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CGEr64compare.Fragment, R32C))>; def v2i64: CodeFrag; // SELB mask from FSM: - def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGEr64compare.Fragment))>; - def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CGEv2i64compare.Fragment))>; + def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS (FSMv4i32 CGEr64compare.Fragment),R32C))>; + def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS (FSMv4i32 CGEv2i64compare.Fragment),R32C))>; } defm I64GE: CompareGreaterEqual64; @@ -255,9 +267,9 @@ v2i64_add_1.Fragment, cg_mask>; def : Pat<(SPUadd64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)), - (ORi64_v2i64 v2i64_add<(ORv2i64_i64 R64C:$rA), - (ORv2i64_i64 R64C:$rB), - (v4i32 VECREG:$rCGmask)>.Fragment)>; + (COPY_TO_REGCLASS v2i64_add<(COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG), + (v4i32 VECREG:$rCGmask)>.Fragment, R64C)>; def : Pat<(SPUadd64 (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), (v4i32 VECREG:$rCGmask)), @@ -275,11 +287,12 @@ CodeFrag<(SFXv4i32 lhs, rhs, (SHUFBv4i32 bg, bg, bg_mask))>; def : Pat<(SPUsub64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)), - (ORi64_v2i64 v2i64_sub<(ORv2i64_i64 R64C:$rA), - (ORv2i64_i64 R64C:$rB), - v2i64_sub_bg<(ORv2i64_i64 R64C:$rA), - (ORv2i64_i64 R64C:$rB)>.Fragment, - (v4i32 VECREG:$rCGmask)>.Fragment)>; + (COPY_TO_REGCLASS + v2i64_sub<(COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG), + v2i64_sub_bg<(COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG)>.Fragment, + (v4i32 VECREG:$rCGmask)>.Fragment, R64C)>; def : Pat<(SPUsub64 (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), (v4i32 VECREG:$rCGmask)), @@ -374,9 +387,9 @@ rCGmask>; def : Pat<(SPUmul64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)), - (ORi64_v2i64 v2i64_mul<(ORv2i64_i64 R64C:$rA), - (ORv2i64_i64 R64C:$rB), - (v4i32 VECREG:$rCGmask)>.Fragment)>; + (COPY_TO_REGCLASS v2i64_mul<(COPY_TO_REGCLASS R64C:$rA, VECREG), + (COPY_TO_REGCLASS R64C:$rB, VECREG), + (v4i32 VECREG:$rCGmask)>.Fragment, R64C)>; def : Pat<(SPUmul64 (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), (v4i32 VECREG:$rCGmask)), Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=114074&r1=114073&r2=114074&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Sep 16 07:29:33 2010 @@ -357,6 +357,9 @@ assert(II && "No InstrInfo?"); return new SPUHazardRecognizer(*II); } + + private: + SDValue getRC( MVT ); // Include the pieces autogenerated from the target description. #include "SPUGenDAGISel.inc" @@ -619,6 +622,29 @@ return false; } +/*! + Utility function to use with COPY_TO_REGCLASS instructions. Returns a SDValue + to be used as the last parameter of a +CurDAG->getMachineNode(COPY_TO_REGCLASS,..., ) function call + \arg VT the value type for which we want a register class +*/ +SDValue SPUDAGToDAGISel::getRC( MVT VT ) { + switch( VT.SimpleTy ) { + case MVT::i32: + return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32); + break; + case MVT::i64: + return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32); + break; + case MVT::v2i64: + return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32); + break; + default: + assert( false && "add a new case here" ); + } + return SDValue(); +} + //! Convert the operand from a target-independent to a target-specific node /*! */ @@ -773,8 +799,8 @@ if (shift_amt >= 32) { SDNode *hi32 = - CurDAG->getMachineNode(SPU::ORr32_r64, dl, OpVT, - Op0.getOperand(0)); + CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, + Op0.getOperand(0), getRC(MVT::i32)); shift_amt -= 32; if (shift_amt > 0) { @@ -941,7 +967,8 @@ SDValue SelMaskVal; DebugLoc dl = N->getDebugLoc(); - VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0); + VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, + Op0, getRC(MVT::v2i64) ); SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16); SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal); ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT, @@ -985,7 +1012,8 @@ SDValue(Shift, 0), SDValue(Bits, 0)); } - return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); + return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, + OpVT, SDValue(Shift, 0), getRC(MVT::i64)); } /*! @@ -1006,7 +1034,8 @@ SDNode *VecOp0, *Shift = 0; DebugLoc dl = N->getDebugLoc(); - VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0); + VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, + Op0, getRC(MVT::v2i64) ); if (ConstantSDNode *CN = dyn_cast(ShiftAmt)) { unsigned bytes = unsigned(CN->getZExtValue()) >> 3; @@ -1052,7 +1081,8 @@ SDValue(Shift, 0), SDValue(Bits, 0)); } - return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); + return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, + OpVT, SDValue(Shift, 0), getRC(MVT::i64)); } /*! @@ -1073,14 +1103,16 @@ DebugLoc dl = N->getDebugLoc(); SDNode *VecOp0 = - CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, N->getOperand(0)); + CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, + VecVT, N->getOperand(0), getRC(MVT::v2i64)); SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT); SDNode *SignRot = CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64, SDValue(VecOp0, 0), SignRotAmt); SDNode *UpperHalfSign = - CurDAG->getMachineNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0)); + CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, + MVT::i32, SDValue(SignRot, 0), getRC(MVT::i32)); SDNode *UpperHalfSignMask = CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0)); @@ -1127,7 +1159,8 @@ SDValue(Shift, 0), SDValue(NegShift, 0)); } - return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0)); + return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, + OpVT, SDValue(Shift, 0), getRC(MVT::i64)); } /*! @@ -1154,8 +1187,9 @@ SDValue Op0 = i64vec.getOperand(0); ReplaceUses(i64vec, Op0); - return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, - SDValue(emitBuildVector(Op0.getNode()), 0)); + return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, + SDValue(emitBuildVector(Op0.getNode()), 0), + getRC(MVT::i64)); } else if (i64vec.getOpcode() == SPUISD::SHUFB) { SDValue lhs = i64vec.getOperand(0); SDValue rhs = i64vec.getOperand(1); @@ -1196,10 +1230,12 @@ SDNode *SN = SelectCode(Dummy.getValue().getNode()); if (SN == 0) SN = Dummy.getValue().getNode(); - return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(SN, 0)); + return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, + OpVT, SDValue(SN, 0), getRC(MVT::i64)); } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) { - return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, - SDValue(emitBuildVector(i64vec.getNode()), 0)); + return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, + SDValue(emitBuildVector(i64vec.getNode()), 0), + getRC(MVT::i64)); } else { report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec" "condition"); Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=114074&r1=114073&r2=114074&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Thu Sep 16 07:29:33 2010 @@ -1385,59 +1385,6 @@ ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>; -// ORCvtForm: OR conversion form -// -// This is used to "convert" the preferred slot to its vector equivalent, as -// well as convert a vector back to its preferred slot. -// -// These are effectively no-ops, but need to exist for proper type conversion -// and type coercion. - -class ORCvtForm pattern = [/* no pattern */]> - : SPUInstr { - bits<7> RA; - bits<7> RT; - - let Pattern = pattern; - - let Inst{0-10} = 0b10000010000; - let Inst{11-17} = RA; - let Inst{18-24} = RA; - let Inst{25-31} = RT; -} - -class ORPromoteScalar: - ORCvtForm<(outs VECREG:$rT), (ins rclass:$rA)>; - -class ORExtractElt: - ORCvtForm<(outs rclass:$rT), (ins VECREG:$rA)>; - -/* class ORCvtRegGPRC: - ORCvtForm<(outs GPRC:$rT), (ins rclass:$rA)>; */ - -/* class ORCvtGPRCReg: - ORCvtForm<(outs rclass:$rT), (ins GPRC:$rA)>; */ - -class ORCvtFormR32Reg pattern = [ ]>: - ORCvtForm<(outs rclass:$rT), (ins R32C:$rA), pattern>; - -class ORCvtFormRegR32 pattern = [ ]>: - ORCvtForm<(outs R32C:$rT), (ins rclass:$rA), pattern>; - -class ORCvtFormR64Reg pattern = [ ]>: - ORCvtForm<(outs rclass:$rT), (ins R64C:$rA), pattern>; - -class ORCvtFormRegR64 pattern = [ ]>: - ORCvtForm<(outs R64C:$rT), (ins rclass:$rA), pattern>; - -class ORCvtGPRCVec: - ORCvtForm<(outs VECREG:$rT), (ins GPRC:$rA)>; - -class ORCvtVecGPRC: - ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>; - -class ORCvtVecVec: - ORCvtForm<(outs VECREG:$rT), (ins VECREG:$rA)>; multiclass BitwiseOr { @@ -1468,119 +1415,48 @@ def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB), [/* no pattern */]>; - - // scalar->vector promotion, prefslot2vec: - def v16i8_i8: ORPromoteScalar; - def v8i16_i16: ORPromoteScalar; - def v4i32_i32: ORPromoteScalar; - def v2i64_i64: ORPromoteScalar; - def v4f32_f32: ORPromoteScalar; - def v2f64_f64: ORPromoteScalar; - - // vector->scalar demotion, vec2prefslot: - def i8_v16i8: ORExtractElt; - def i16_v8i16: ORExtractElt; - def i32_v4i32: ORExtractElt; - def i64_v2i64: ORExtractElt; - def f32_v4f32: ORExtractElt; - def f64_v2f64: ORExtractElt; - - // Conversion from vector to GPRC - def i128_vec: ORCvtVecGPRC; - - // Conversion from GPRC to vector - def vec_i128: ORCvtGPRCVec; - -/* - // Conversion from register to GPRC - def i128_r64: ORCvtRegGPRC; - def i128_f64: ORCvtRegGPRC; - def i128_r32: ORCvtRegGPRC; - def i128_f32: ORCvtRegGPRC; - def i128_r16: ORCvtRegGPRC; - def i128_r8: ORCvtRegGPRC; - - // Conversion from GPRC to register - def r64_i128: ORCvtGPRCReg; - def f64_i128: ORCvtGPRCReg; - def r32_i128: ORCvtGPRCReg; - def f32_i128: ORCvtGPRCReg; - def r16_i128: ORCvtGPRCReg; - def r8_i128: ORCvtGPRCReg; -*/ -/* - // Conversion from register to R32C: - def r32_r16: ORCvtFormRegR32; - def r32_r8: ORCvtFormRegR32; - - // Conversion from R32C to register - def r32_r16: ORCvtFormR32Reg; - def r32_r8: ORCvtFormR32Reg; -*/ - - // Conversion from R64C to register: - def r32_r64: ORCvtFormR64Reg; - // def r16_r64: ORCvtFormR64Reg; - // def r8_r64: ORCvtFormR64Reg; - - // Conversion to R64C from register: - def r64_r32: ORCvtFormRegR64; - // def r64_r16: ORCvtFormRegR64; - // def r64_r8: ORCvtFormRegR64; - - // bitconvert patterns: - def r32_f32: ORCvtFormR32Reg; - def f32_r32: ORCvtFormRegR32; - - def r64_f64: ORCvtFormR64Reg; - def f64_r64: ORCvtFormRegR64; } defm OR : BitwiseOr; -// scalar->vector promotion patterns (preferred slot to vector): +//===----------------------------------------------------------------------===// +// SPU::PREFSLOT2VEC and VEC2PREFSLOT re-interpretations of registers +//===----------------------------------------------------------------------===// def : Pat<(v16i8 (SPUprefslot2vec R8C:$rA)), - (ORv16i8_i8 R8C:$rA)>; + (COPY_TO_REGCLASS R8C:$rA, VECREG)>; def : Pat<(v8i16 (SPUprefslot2vec R16C:$rA)), - (ORv8i16_i16 R16C:$rA)>; + (COPY_TO_REGCLASS R16C:$rA, VECREG)>; def : Pat<(v4i32 (SPUprefslot2vec R32C:$rA)), - (ORv4i32_i32 R32C:$rA)>; + (COPY_TO_REGCLASS R32C:$rA, VECREG)>; def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)), - (ORv2i64_i64 R64C:$rA)>; + (COPY_TO_REGCLASS R64C:$rA, VECREG)>; def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)), - (ORv4f32_f32 R32FP:$rA)>; + (COPY_TO_REGCLASS R32FP:$rA, VECREG)>; def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)), - (ORv2f64_f64 R64FP:$rA)>; - -// ORi*_v*: Used to extract vector element 0 (the preferred slot), otherwise -// known as converting the vector back to its preferred slot + (COPY_TO_REGCLASS R64FP:$rA, VECREG)>; + +def : Pat<(i8 (SPUvec2prefslot (v16i8 VECREG:$rA))), + (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>; -def : Pat<(SPUvec2prefslot (v16i8 VECREG:$rA)), - (ORi8_v16i8 VECREG:$rA)>; +def : Pat<(i16 (SPUvec2prefslot (v8i16 VECREG:$rA))), + (COPY_TO_REGCLASS (v8i16 VECREG:$rA), R16C)>; -def : Pat<(SPUvec2prefslot (v8i16 VECREG:$rA)), - (ORi16_v8i16 VECREG:$rA)>; +def : Pat<(i32 (SPUvec2prefslot (v4i32 VECREG:$rA))), + (COPY_TO_REGCLASS (v4i32 VECREG:$rA), R32C)>; -def : Pat<(SPUvec2prefslot (v4i32 VECREG:$rA)), - (ORi32_v4i32 VECREG:$rA)>; +def : Pat<(i64 (SPUvec2prefslot (v2i64 VECREG:$rA))), + (COPY_TO_REGCLASS (v2i64 VECREG:$rA), R64C)>; -def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)), - (ORi64_v2i64 VECREG:$rA)>; +def : Pat<(f32 (SPUvec2prefslot (v4f32 VECREG:$rA))), + (COPY_TO_REGCLASS (v4f32 VECREG:$rA), R32FP)>; -def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)), - (ORf32_v4f32 VECREG:$rA)>; - -def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)), - (ORf64_v2f64 VECREG:$rA)>; +def : Pat<(f64 (SPUvec2prefslot (v2f64 VECREG:$rA))), + (COPY_TO_REGCLASS (v2f64 VECREG:$rA), R64FP)>; // Load Register: This is an assembler alias for a bitwise OR of a register // against itself. It's here because it brings some clarity to assembly @@ -4379,30 +4255,43 @@ def : Pat<(v2f64 (bitconvert (v4f32 VECREG:$src))), (v2f64 VECREG:$src)>; def : Pat<(i128 (bitconvert (v16i8 VECREG:$src))), - (ORi128_vec VECREG:$src)>; + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; def : Pat<(i128 (bitconvert (v8i16 VECREG:$src))), - (ORi128_vec VECREG:$src)>; + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; def : Pat<(i128 (bitconvert (v4i32 VECREG:$src))), - (ORi128_vec VECREG:$src)>; + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; def : Pat<(i128 (bitconvert (v2i64 VECREG:$src))), - (ORi128_vec VECREG:$src)>; + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; def : Pat<(i128 (bitconvert (v4f32 VECREG:$src))), - (ORi128_vec VECREG:$src)>; + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; def : Pat<(i128 (bitconvert (v2f64 VECREG:$src))), - (ORi128_vec VECREG:$src)>; + (COPY_TO_REGCLASS VECREG:$src, GPRC)>; def : Pat<(v16i8 (bitconvert (i128 GPRC:$src))), - (v16i8 (ORvec_i128 GPRC:$src))>; + (v16i8 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; def : Pat<(v8i16 (bitconvert (i128 GPRC:$src))), - (v8i16 (ORvec_i128 GPRC:$src))>; + (v8i16 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; def : Pat<(v4i32 (bitconvert (i128 GPRC:$src))), - (v4i32 (ORvec_i128 GPRC:$src))>; + (v4i32 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; def : Pat<(v2i64 (bitconvert (i128 GPRC:$src))), - (v2i64 (ORvec_i128 GPRC:$src))>; + (v2i64 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; def : Pat<(v4f32 (bitconvert (i128 GPRC:$src))), - (v4f32 (ORvec_i128 GPRC:$src))>; + (v4f32 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; def : Pat<(v2f64 (bitconvert (i128 GPRC:$src))), - (v2f64 (ORvec_i128 GPRC:$src))>; + (v2f64 (COPY_TO_REGCLASS GPRC:$src, VECREG))>; + +def : Pat<(i32 (bitconvert R32FP:$rA)), + (COPY_TO_REGCLASS R32FP:$rA, R32C)>; + +def : Pat<(f32 (bitconvert R32C:$rA)), + (COPY_TO_REGCLASS R32C:$rA, R32FP)>; + +def : Pat<(i64 (bitconvert R64FP:$rA)), + (COPY_TO_REGCLASS R64FP:$rA, R64C)>; + +def : Pat<(f64 (bitconvert R64C:$rA)), + (COPY_TO_REGCLASS R64C:$rA, R64FP)>; + //===----------------------------------------------------------------------===// // Instruction patterns: @@ -4453,11 +4342,12 @@ // zext 8->64: Zero extend bytes to double words def : Pat<(i64 (zext R8C:$rSrc)), - (ORi64_v2i64 (SELBv4i32 (ROTQMBYv4i32 - (ORv4i32_i32 (ANDIi8i32 R8C:$rSrc, 0xff)), + (COPY_TO_REGCLASS (SELBv4i32 (ROTQMBYv4i32 + (COPY_TO_REGCLASS + (ANDIi8i32 R8C:$rSrc,0xff), VECREG), 0x4), (ILv4i32 0x0), - (FSMBIv4i32 0x0f0f)))>; + (FSMBIv4i32 0x0f0f)), R64C)>; // anyext 8->16: Extend 8->16 bits, irrespective of sign, preserves high bits def : Pat<(i16 (anyext R8C:$rSrc)), @@ -4498,61 +4388,61 @@ //===----------------------------------------------------------------------===// def : Pat<(i8 (trunc GPRC:$src)), - (ORi8_v16i8 + (COPY_TO_REGCLASS (SHUFBgprc GPRC:$src, GPRC:$src, - (IOHLv4i32 (ILHUv4i32 0x0f0f), 0x0f0f)))>; + (IOHLv4i32 (ILHUv4i32 0x0f0f), 0x0f0f)), R8C)>; def : Pat<(i8 (trunc R64C:$src)), - (ORi8_v16i8 + (COPY_TO_REGCLASS (SHUFBv2i64_m32 - (ORv2i64_i64 R64C:$src), - (ORv2i64_i64 R64C:$src), - (IOHLv4i32 (ILHUv4i32 0x0707), 0x0707)))>; + (COPY_TO_REGCLASS R64C:$src, VECREG), + (COPY_TO_REGCLASS R64C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0707), 0x0707)), R8C)>; def : Pat<(i8 (trunc R32C:$src)), - (ORi8_v16i8 + (COPY_TO_REGCLASS (SHUFBv4i32_m32 - (ORv4i32_i32 R32C:$src), - (ORv4i32_i32 R32C:$src), - (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)))>; + (COPY_TO_REGCLASS R32C:$src, VECREG), + (COPY_TO_REGCLASS R32C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)), R8C)>; def : Pat<(i8 (trunc R16C:$src)), - (ORi8_v16i8 + (COPY_TO_REGCLASS (SHUFBv4i32_m32 - (ORv8i16_i16 R16C:$src), - (ORv8i16_i16 R16C:$src), - (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)))>; + (COPY_TO_REGCLASS R16C:$src, VECREG), + (COPY_TO_REGCLASS R16C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)), R8C)>; def : Pat<(i16 (trunc GPRC:$src)), - (ORi16_v8i16 + (COPY_TO_REGCLASS (SHUFBgprc GPRC:$src, GPRC:$src, - (IOHLv4i32 (ILHUv4i32 0x0e0f), 0x0e0f)))>; + (IOHLv4i32 (ILHUv4i32 0x0e0f), 0x0e0f)), R16C)>; def : Pat<(i16 (trunc R64C:$src)), - (ORi16_v8i16 + (COPY_TO_REGCLASS (SHUFBv2i64_m32 - (ORv2i64_i64 R64C:$src), - (ORv2i64_i64 R64C:$src), - (IOHLv4i32 (ILHUv4i32 0x0607), 0x0607)))>; + (COPY_TO_REGCLASS R64C:$src, VECREG), + (COPY_TO_REGCLASS R64C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0607), 0x0607)), R16C)>; def : Pat<(i16 (trunc R32C:$src)), - (ORi16_v8i16 + (COPY_TO_REGCLASS (SHUFBv4i32_m32 - (ORv4i32_i32 R32C:$src), - (ORv4i32_i32 R32C:$src), - (IOHLv4i32 (ILHUv4i32 0x0203), 0x0203)))>; + (COPY_TO_REGCLASS R32C:$src, VECREG), + (COPY_TO_REGCLASS R32C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0203), 0x0203)), R16C)>; def : Pat<(i32 (trunc GPRC:$src)), - (ORi32_v4i32 + (COPY_TO_REGCLASS (SHUFBgprc GPRC:$src, GPRC:$src, - (IOHLv4i32 (ILHUv4i32 0x0c0d), 0x0e0f)))>; + (IOHLv4i32 (ILHUv4i32 0x0c0d), 0x0e0f)), R32C)>; def : Pat<(i32 (trunc R64C:$src)), - (ORi32_v4i32 + (COPY_TO_REGCLASS (SHUFBv2i64_m32 - (ORv2i64_i64 R64C:$src), - (ORv2i64_i64 R64C:$src), - (IOHLv4i32 (ILHUv4i32 0x0405), 0x0607)))>; + (COPY_TO_REGCLASS R64C:$src, VECREG), + (COPY_TO_REGCLASS R64C:$src, VECREG), + (IOHLv4i32 (ILHUv4i32 0x0405), 0x0607)), R32C)>; //===----------------------------------------------------------------------===// // Address generation: SPU, like PPC, has to split addresses into high and Modified: llvm/trunk/test/CodeGen/CellSPU/v2i32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/v2i32.ll?rev=114074&r1=114073&r2=114074&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/v2i32.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/v2i32.ll Thu Sep 16 07:29:33 2010 @@ -37,9 +37,8 @@ } define <2 x i32> @test_splat(i32 %param ) { -;TODO insertelement transforms to a PREFSLOT2VEC, that trasforms to the -; somewhat redundant: -;CHECK-NOT or $3, $3, $3 +;see svn log for why this is here... +;CHECK-NOT: or $3, $3, $3 ;CHECK: lqa ;CHECK: shufb %sv = insertelement <1 x i32> undef, i32 %param, i32 0 From criswell at uiuc.edu Thu Sep 16 09:31:45 2010 From: criswell at uiuc.edu (John Criswell) Date: Thu, 16 Sep 2010 14:31:45 -0000 Subject: [llvm-commits] [poolalloc] r114076 - /poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Message-ID: <20100916143145.79C0C2A6C12C@llvm.org> Author: criswell Date: Thu Sep 16 09:31:45 2010 New Revision: 114076 URL: http://llvm.org/viewvc/llvm-project?rev=114076&view=rev Log: Added in the missing runtime checks added by SAFECode. Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp?rev=114076&r1=114075&r2=114076&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PASimple.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Thu Sep 16 09:31:45 2010 @@ -94,7 +94,12 @@ (funcname == "sc.boundscheck") || (funcname == "sc.boundscheckui") || (funcname == "sc.pool_register_stack") || - (funcname == "sc.pool_unregister_stack")) { + (funcname == "sc.pool_unregister_stack") || + (funcname == "sc.pool_register_global") || + (funcname == "sc.pool_unregister_global") || + (funcname == "sc.pool_register") || + (funcname == "sc.pool_unregister") || + (funcname == "sc.get_actual_val")) { return 1; } From rafael.espindola at gmail.com Thu Sep 16 10:03:59 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 16 Sep 2010 15:03:59 -0000 Subject: [llvm-commits] [llvm] r114077 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/ELF/zero.s Message-ID: <20100916150359.653832A6C12C@llvm.org> Author: rafael Date: Thu Sep 16 10:03:59 2010 New Revision: 114077 URL: http://llvm.org/viewvc/llvm-project?rev=114077&view=rev Log: Add support for the .zero directive. Added: llvm/trunk/test/MC/ELF/zero.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114077&r1=114076&r2=114077&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Sep 16 10:03:59 2010 @@ -180,6 +180,7 @@ bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... bool ParseDirectiveFill(); // ".fill" bool ParseDirectiveSpace(); // ".space" + bool ParseDirectiveZero(); // ".zero" bool ParseDirectiveSet(); // ".set" bool ParseDirectiveOrg(); // ".org" // ".align{,32}", ".p2align{,w,l}" @@ -871,6 +872,8 @@ return ParseDirectiveFill(); if (IDVal == ".space") return ParseDirectiveSpace(); + if (IDVal == ".zero") + return ParseDirectiveZero(); // Symbol attribute directives @@ -1353,6 +1356,25 @@ return false; } +/// ParseDirectiveZero +/// ::= .zero expression +bool AsmParser::ParseDirectiveZero() { + CheckForValidSection(); + + int64_t NumBytes; + if (ParseAbsoluteExpression(NumBytes)) + return true; + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.zero' directive"); + + Lex(); + + getStreamer().EmitFill(NumBytes, 0, DEFAULT_ADDRSPACE); + + return false; +} + /// ParseDirectiveFill /// ::= .fill expression , expression , expression bool AsmParser::ParseDirectiveFill() { Added: llvm/trunk/test/MC/ELF/zero.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/zero.s?rev=114077&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/zero.s (added) +++ llvm/trunk/test/MC/ELF/zero.s Thu Sep 16 10:03:59 2010 @@ -0,0 +1,15 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +.zero 4 + +// CHECK: ('sh_name', 1) # '.text' +// CHECK: ('sh_type', 1) +// CHECK: ('sh_flags', 6) +// CHECK: ('sh_addr', 0) +// CHECK: ('sh_offset', 64) +// CHECK: ('sh_size', 4) +// CHECK: ('sh_link', 0) +// CHECK: ('sh_info', 0) +// CHECK: ('sh_addralign', 4) +// CHECK: ('sh_entsize', 0) +// CHECK: ('_section_data', '00000000') From grosbach at apple.com Thu Sep 16 10:11:00 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 08:11:00 -0700 Subject: [llvm-commits] [llvm] r114067 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.cpp In-Reply-To: <20100916045500.320B72A6C12C@llvm.org> References: <20100916045500.320B72A6C12C@llvm.org> Message-ID: <106468B7-833D-4693-BB2A-1C158BB7F30A@apple.com> Very nice! On Sep 15, 2010, at 9:55 PM, Bob Wilson wrote: > Author: bwilson > Date: Wed Sep 15 23:55:00 2010 > New Revision: 114067 > > URL: http://llvm.org/viewvc/llvm-project?rev=114067&view=rev > Log: > Remove support for "dregpair" operand modifier, now that it is no longer being > used for anything. > > Modified: > llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114067&r1=114066&r2=114067&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 15 23:55:00 2010 > @@ -337,13 +337,7 @@ > case MachineOperand::MO_Register: { > unsigned Reg = MO.getReg(); > assert(TargetRegisterInfo::isPhysicalRegister(Reg)); > - if (Modifier && strcmp(Modifier, "dregpair") == 0) { > - unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0); > - unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1); > - O << '{' > - << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi) > - << '}'; > - } else if (Modifier && strcmp(Modifier, "lane") == 0) { > + if (Modifier && strcmp(Modifier, "lane") == 0) { > unsigned RegNum = getARMRegisterNumbering(Reg); > unsigned DReg = > TM.getRegisterInfo()->getMatchingSuperReg(Reg, > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114067&r1=114066&r2=114067&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 15 23:55:00 2010 > @@ -29,30 +29,6 @@ > #undef MachineInstr > #undef ARMAsmPrinter > > -// Get the constituent sub-regs for a dregpair from a Q register. > -static std::pair GetDRegPair(unsigned QReg) { > - switch (QReg) { > - default: > - assert(0 && "Unexpected register enum"); > - case ARM::Q0: return std::pair(ARM::D0, ARM::D1); > - case ARM::Q1: return std::pair(ARM::D2, ARM::D3); > - case ARM::Q2: return std::pair(ARM::D4, ARM::D5); > - case ARM::Q3: return std::pair(ARM::D6, ARM::D7); > - case ARM::Q4: return std::pair(ARM::D8, ARM::D9); > - case ARM::Q5: return std::pair(ARM::D10, ARM::D11); > - case ARM::Q6: return std::pair(ARM::D12, ARM::D13); > - case ARM::Q7: return std::pair(ARM::D14, ARM::D15); > - case ARM::Q8: return std::pair(ARM::D16, ARM::D17); > - case ARM::Q9: return std::pair(ARM::D18, ARM::D19); > - case ARM::Q10: return std::pair(ARM::D20, ARM::D21); > - case ARM::Q11: return std::pair(ARM::D22, ARM::D23); > - case ARM::Q12: return std::pair(ARM::D24, ARM::D25); > - case ARM::Q13: return std::pair(ARM::D26, ARM::D27); > - case ARM::Q14: return std::pair(ARM::D28, ARM::D29); > - case ARM::Q15: return std::pair(ARM::D30, ARM::D31); > - } > -} > - > static unsigned getDPRSuperRegForSPR(unsigned Reg) { > switch (Reg) { > default: > @@ -165,11 +141,7 @@ > const MCOperand &Op = MI->getOperand(OpNo); > if (Op.isReg()) { > unsigned Reg = Op.getReg(); > - if (Modifier && strcmp(Modifier, "dregpair") == 0) { > - std::pair dregpair = GetDRegPair(Reg); > - O << '{' << getRegisterName(dregpair.first) << ", " > - << getRegisterName(dregpair.second) << '}'; > - } else if (Modifier && strcmp(Modifier, "lane") == 0) { > + if (Modifier && strcmp(Modifier, "lane") == 0) { > unsigned RegNum = getARMRegisterNumbering(Reg); > unsigned DReg = getDPRSuperRegForSPR(Reg); > O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Thu Sep 16 10:43:17 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 16 Sep 2010 15:43:17 -0000 Subject: [llvm-commits] [zorg] r114080 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100916154317.954512A6C12C@llvm.org> Author: baldrick Date: Thu Sep 16 10:43:17 2010 New Revision: 114080 URL: http://llvm.org/viewvc/llvm-project?rev=114080&view=rev Log: Move this builder to gcc11, which has some needed libraries installed. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114080&r1=114079&r2=114080&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Sep 16 10:43:17 2010 @@ -249,7 +249,7 @@ 'category' : 'llvm-gcc.exp' }, {'name' : "llvm-gcc-i386-linux-selfhost", - 'slavenames':["gcc10"], + 'slavenames':["gcc11"], 'builddir':"llvm-gcc-i386-linux-selfhost", 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', extra_configure_args=['--disable-multilib']), From llvm-dev at code2develop.com Thu Sep 16 08:26:11 2010 From: llvm-dev at code2develop.com (F van der Meeren) Date: Thu, 16 Sep 2010 15:26:11 +0200 Subject: [llvm-commits] LLVM-C Patch: LLVMConvertModuleToC Patch Message-ID: <2CA791E9-8F4E-49AB-8CEA-3726020788CB@code2develop.com> A non-text attachment was scrubbed... Name: LLVMConvertModuleToCPatch.diff Type: application/octet-stream Size: 3188 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/a8b03144/attachment.obj -------------- next part -------------- - Filip From rafael.espindola at gmail.com Thu Sep 16 12:05:56 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 16 Sep 2010 17:05:56 -0000 Subject: [llvm-commits] [llvm] r114091 - in /llvm/trunk: lib/MC/MCParser/ELFAsmParser.cpp test/MC/ELF/section.s Message-ID: <20100916170556.2578F2A6C12C@llvm.org> Author: rafael Date: Thu Sep 16 12:05:55 2010 New Revision: 114091 URL: http://llvm.org/viewvc/llvm-project?rev=114091&view=rev Log: Make sure that names like .note.GNU-stack are accepted as valid section names. Added: llvm/trunk/test/MC/ELF/section.s Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=114091&r1=114090&r2=114091&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Thu Sep 16 12:05:55 2010 @@ -118,6 +118,9 @@ bool ParseDirectiveSection(StringRef, SMLoc); bool ParseDirectiveSize(StringRef, SMLoc); bool ParseDirectivePrevious(StringRef, SMLoc); + +private: + bool ParseSectionName(StringRef &SectionName); }; } @@ -155,11 +158,43 @@ return false; } +bool ELFAsmParser::ParseSectionName(StringRef &SectionName) { + // A section name can contain -, so we cannot just use + // ParseIdentifier. + SMLoc FirstLoc = getLexer().getLoc(); + unsigned Size = 0; + + for (;;) { + StringRef Tmp; + unsigned CurSize; + + SMLoc PrevLoc = getLexer().getLoc(); + if (getLexer().is(AsmToken::Minus)) { + CurSize = 1; + Lex(); // Consume the "-". + } else if (!getParser().ParseIdentifier(Tmp)) + CurSize = Tmp.size(); + else + break; + + Size += CurSize; + SectionName = StringRef(FirstLoc.getPointer(), Size); + + // Make sure the following token is adjacent. + if (PrevLoc.getPointer() + CurSize != getTok().getLoc().getPointer()) + break; + } + if (Size == 0) + return true; + + return false; +} + // FIXME: This is a work in progress. bool ELFAsmParser::ParseDirectiveSection(StringRef, SMLoc) { StringRef SectionName; - // FIXME: This doesn't parse section names like ".note.GNU-stack" correctly. - if (getParser().ParseIdentifier(SectionName)) + + if (ParseSectionName(SectionName)) return TokError("expected identifier in directive"); std::string FlagsStr; Added: llvm/trunk/test/MC/ELF/section.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/section.s?rev=114091&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/section.s (added) +++ llvm/trunk/test/MC/ELF/section.s Thu Sep 16 12:05:55 2010 @@ -0,0 +1,11 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that these names are accepted. + +.section .note.GNU-stack,"", at progbits +.section .note.GNU-,"", at progbits +.section -.note.GNU,"", at progbits + +// CHECK: ('sh_name', 18) # '.note.GNU-stack' +// CHECK: ('sh_name', 34) # '.note.GNU-' +// CHECK: ('sh_name', 45) # '-.note.GNU' From llvm-dev at code2develop.com Thu Sep 16 12:22:22 2010 From: llvm-dev at code2develop.com (F van der Meeren) Date: Thu, 16 Sep 2010 19:22:22 +0200 Subject: [llvm-commits] LLVM-C Addition: LLVMCombineModules Message-ID: <9A2AFD14-514E-4E42-92C2-F270E65B0676@code2develop.com> - author: Filip van der Meeren Index: include/llvm-c/Core.h =================================================================== --- include/llvm-c/Core.h (revision 114074) +++ include/llvm-c/Core.h (working copy) @@ -303,6 +303,20 @@ LLVMModuleRef LLVMModuleCreateWithNameInContext(const char *ModuleID, LLVMContextRef C); +/** + * Combines all the given modules into one. + * The list of modules must end with a NULL pointer. + * The returned module must be disposed by the user by using LLVMDisposeModule. + * + * If an error occurs, the message will be returned through the errMsg + * which also must be disposed by the user by using LLVMDisposeMessage. + */ +LLVMModuleRef +LLVMCombineModules(char const * const newModuleName, + char ** const errMsg, + LLVMModuleRef aFirstModule, + ...); + /** See llvm::Module::~Module. */ void LLVMDisposeModule(LLVMModuleRef M); Index: lib/VMCore/Core.cpp =================================================================== --- lib/VMCore/Core.cpp (revision 114074) +++ lib/VMCore/Core.cpp (working copy) @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "llvm-c/Core.h" +#include "llvm/ADT/StringRef.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" @@ -22,6 +23,7 @@ #include "llvm/TypeSymbolTable.h" #include "llvm/InlineAsm.h" #include "llvm/IntrinsicInst.h" +#include "llvm/Linker.h" #include "llvm/PassManager.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/Debug.h" @@ -30,7 +32,10 @@ #include "llvm/Support/raw_ostream.h" #include #include +#include #include +#include +#include using namespace llvm; @@ -77,6 +82,40 @@ return wrap(new Module(ModuleID, *unwrap(C))); } +LLVMModuleRef +LLVMCombineModules(char const * const newModuleName, + char ** const errMsg, + LLVMModuleRef aFirstModule, + ...) { + va_list argptr; + std::string error; + Module * result = NULL; + Module * const firstModule = unwrap(aFirstModule); + Module * toLink = firstModule; + std::auto_ptr linker(new Linker(StringRef(""), + StringRef(newModuleName), + firstModule->getContext(), + 0)); + + va_start(argptr, aFirstModule); + while(toLink != NULL) { + + error.clear(); + if(linker->LinkInModule(toLink, &error) || !error.empty()) { + if(errMsg) + (*errMsg) = strdup(error.c_str()); + break; + } + + toLink = unwrap(va_arg(argptr, LLVMModuleRef)); + } + va_end(argptr); + + result = linker->getModule(); + linker->releaseModule(); + return wrap(result); +} + void LLVMDisposeModule(LLVMModuleRef M) { delete unwrap(M); } -------------- next part -------------- A non-text attachment was scrubbed... Name: LLVMCombineModules.diff Type: application/octet-stream Size: 2977 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/3fcc0251/attachment.obj From jasonwkim at google.com Thu Sep 16 11:32:24 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 16 Sep 2010 09:32:24 -0700 Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH) Message-ID: This patch is an initial cut (stub) at an ARM MC ELF emitter. It was generated by svn diff from r114077. Comments, corrections and general feedback will be greatly appreciated. AFAIK, I am following the LLVM style guidelines. Tests are forthcoming. Thank you. M lib/Target/ARM/ARM.h A lib/Target/ARM/ARMMCCodeEmitter.cpp M lib/Target/ARM/CMakeLists.txt -Jason Kim -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf.patch2 Type: application/octet-stream Size: 5736 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/c36fc07f/attachment.obj From grosbach at apple.com Thu Sep 16 12:37:30 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 17:37:30 -0000 Subject: [llvm-commits] [llvm] r114096 - /llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Message-ID: <20100916173730.E635A2A6C12C@llvm.org> Author: grosbach Date: Thu Sep 16 12:37:30 2010 New Revision: 114096 URL: http://llvm.org/viewvc/llvm-project?rev=114096&view=rev Log: Make sure to promote single precision floats to double before extracting them from the APFloat. Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=114096&r1=114095&r2=114096&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Thu Sep 16 12:37:30 2010 @@ -157,8 +157,10 @@ MO.getBlockAddress())); break; case MachineOperand::MO_FPImmediate: - MCOp = - MCOperand::CreateFPImm(MO.getFPImm()->getValueAPF().convertToDouble()); + APFloat Val = MO.getFPImm()->getValueAPF(); + bool ignored; + Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored); + MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); break; } From resistor at mac.com Thu Sep 16 12:42:36 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 17:42:36 -0000 Subject: [llvm-commits] [llvm] r114097 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/CorrelatedValuePropagation/crash.ll Message-ID: <20100916174236.EC7D22A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 12:42:36 2010 New Revision: 114097 URL: http://llvm.org/viewvc/llvm-project?rev=114097&view=rev Log: Fix PR8161, in which an unreachable loop causes recursive instruction simplification to try to replace an instruction with itself. Add a predicate to the simplifier to prevent this case. Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=114097&r1=114096&r2=114097&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Sep 16 12:42:36 2010 @@ -423,31 +423,44 @@ /// SimplifyInstruction - See if we can compute a simplified version of this /// instruction. If not, this returns null. Value *llvm::SimplifyInstruction(Instruction *I, const TargetData *TD) { + Value *Ret = 0; switch (I->getOpcode()) { default: return ConstantFoldInstruction(I, TD); case Instruction::Add: - return SimplifyAddInst(I->getOperand(0), I->getOperand(1), - cast(I)->hasNoSignedWrap(), - cast(I)->hasNoUnsignedWrap(), TD); + Ret = SimplifyAddInst(I->getOperand(0), I->getOperand(1), + cast(I)->hasNoSignedWrap(), + cast(I)->hasNoUnsignedWrap(), TD); + break; case Instruction::And: - return SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD); + Ret = SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD); + break; case Instruction::Or: - return SimplifyOrInst(I->getOperand(0), I->getOperand(1), TD); + Ret = SimplifyOrInst(I->getOperand(0), I->getOperand(1), TD); + break; case Instruction::ICmp: - return SimplifyICmpInst(cast(I)->getPredicate(), - I->getOperand(0), I->getOperand(1), TD); + Ret = SimplifyICmpInst(cast(I)->getPredicate(), + I->getOperand(0), I->getOperand(1), TD); + break; case Instruction::FCmp: - return SimplifyFCmpInst(cast(I)->getPredicate(), - I->getOperand(0), I->getOperand(1), TD); + Ret = SimplifyFCmpInst(cast(I)->getPredicate(), + I->getOperand(0), I->getOperand(1), TD); + break; case Instruction::Select: - return SimplifySelectInst(I->getOperand(0), I->getOperand(1), + Ret = SimplifySelectInst(I->getOperand(0), I->getOperand(1), I->getOperand(2), TD); + break; case Instruction::GetElementPtr: { SmallVector Ops(I->op_begin(), I->op_end()); - return SimplifyGEPInst(&Ops[0], Ops.size(), TD); + Ret = SimplifyGEPInst(&Ops[0], Ops.size(), TD); + break; } } + + // It is possible, in situations involving unreachable loops, to + // have a replacement that, through recursive simplification, ends up + // simplifying to itself. + return Ret != I ? Ret : 0; } /// ReplaceAndSimplifyAllUses - Perform From->replaceAllUsesWith(To) and then Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll?rev=114097&view=auto ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll (added) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll Thu Sep 16 12:42:36 2010 @@ -0,0 +1,20 @@ +; RUN: opt < %s -correlated-propagation + +; PR8161 +define void @test1() nounwind ssp { +entry: + br label %for.end + +for.cond.us.us: ; preds = %for.cond.us.us + %cmp6.i.us.us = icmp sgt i32 1, 0 + %lor.ext.i.us.us = zext i1 %cmp6.i.us.us to i32 + %lor.ext.add.i.us.us = select i1 %cmp6.i.us.us, i32 %lor.ext.i.us.us, i32 undef + %conv.i.us.us = trunc i32 %lor.ext.add.i.us.us to i16 + %sext.us.us = shl i16 %conv.i.us.us, 8 + %conv6.us.us = ashr i16 %sext.us.us, 8 + %and.us.us = and i16 %conv6.us.us, %and.us.us + br i1 false, label %for.end, label %for.cond.us.us + +for.end: ; preds = %for.cond.us, %for.cond.us.us, %entry + ret void +} From grosbach at apple.com Thu Sep 16 12:43:25 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 17:43:25 -0000 Subject: [llvm-commits] [llvm] r114098 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100916174325.C68712A6C12C@llvm.org> Author: grosbach Date: Thu Sep 16 12:43:25 2010 New Revision: 114098 URL: http://llvm.org/viewvc/llvm-project?rev=114098&view=rev Log: MC-ization of the PICLDR pseudo. Next up, adding the other variants (PICLDRB, et. al.) and PICSTR* Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114098&r1=114097&r2=114098&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 16 12:43:25 2010 @@ -1351,6 +1351,35 @@ OutStreamer.EmitInstruction(AddInst); return; } + case ARM::PICLDR: { + // This is a pseudo op for a label + instruction sequence, which looks like: + // LPC0: + // ldr r0, [pc, r0] + // The LCP0 label is referenced by a constant pool entry in order to get + // a PC-relative address at the ldr instruction. + + // Emit the label. + // FIXME: MOVE TO SHARED PLACE. + unsigned Id = (unsigned)MI->getOperand(2).getImm(); + const char *Prefix = MAI->getPrivateGlobalPrefix(); + MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix) + + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id)); + OutStreamer.EmitLabel(Label); + + // Form and emit the load + MCInst LdrInst; + LdrInst.setOpcode(ARM::LDR); + LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); + LdrInst.addOperand(MCOperand::CreateReg(ARM::PC)); + LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); + LdrInst.addOperand(MCOperand::CreateImm(0)); + // Add predicate operands. + LdrInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); + LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); + OutStreamer.EmitInstruction(LdrInst); + + return; + } case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file. /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool /// in the function. The first operand is the ID# for this instruction, the Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114098&r1=114097&r2=114098&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Thu Sep 16 12:43:25 2010 @@ -384,7 +384,10 @@ void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier) { - assert(0 && "FIXME: Implement printAddrModePCOperand"); + // All instructions using addrmodepc are pseudos and should have been + // handled explicitly in printInstructionThroughMCStreamer(). If one got + // here, it wasn't, so something's wrong. + assert(0 && "Unhandled addrmodepc operand!"); } void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, From grosbach at apple.com Thu Sep 16 12:45:21 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 17:45:21 -0000 Subject: [llvm-commits] [llvm] r114099 - /llvm/trunk/include/llvm/MC/MCInst.h Message-ID: <20100916174521.3CF232A6C12C@llvm.org> Author: grosbach Date: Thu Sep 16 12:45:21 2010 New Revision: 114099 URL: http://llvm.org/viewvc/llvm-project?rev=114099&view=rev Log: Remove unnecessary by-reference return. Modified: llvm/trunk/include/llvm/MC/MCInst.h Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=114099&r1=114098&r2=114099&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Thu Sep 16 12:45:21 2010 @@ -75,7 +75,7 @@ ImmVal = Val; } - const double &getFPImm() const { + const double getFPImm() const { assert(isFPImm() && "This is not an FP immediate"); return FPImmVal; } From grosbach at apple.com Thu Sep 16 12:48:08 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 17:48:08 -0000 Subject: [llvm-commits] [llvm] r114100 - /llvm/trunk/include/llvm/MC/MCInst.h Message-ID: <20100916174808.A266E2A6C12C@llvm.org> Author: grosbach Date: Thu Sep 16 12:48:08 2010 New Revision: 114100 URL: http://llvm.org/viewvc/llvm-project?rev=114100&view=rev Log: make this non brain dead... Modified: llvm/trunk/include/llvm/MC/MCInst.h Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=114100&r1=114099&r2=114100&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Thu Sep 16 12:48:08 2010 @@ -75,7 +75,7 @@ ImmVal = Val; } - const double getFPImm() const { + double getFPImm() const { assert(isFPImm() && "This is not an FP immediate"); return FPImmVal; } From grosbach at apple.com Thu Sep 16 12:50:17 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 10:50:17 -0700 Subject: [llvm-commits] [llvm] r114064 - in /llvm/trunk: include/llvm/MC/MCInst.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp In-Reply-To: <9909CDE4-F76B-4D7D-9D70-CCB3A5C97523@apple.com> References: <20100916034522.196BA2A6C12C@llvm.org> <08D3429C-F637-40FB-A789-33FE44F81904@apple.com> <9909CDE4-F76B-4D7D-9D70-CCB3A5C97523@apple.com> Message-ID: <1D065183-EBB3-4978-AE5F-EDE40CD19EDA@apple.com> On Sep 16, 2010, at 10:46 AM, Jim Grosbach wrote: > > On Sep 16, 2010, at 10:44 AM, Chris Lattner wrote: > >> >> On Sep 15, 2010, at 8:45 PM, Jim Grosbach wrote: >> >>> + const double &getFPImm() const { >>> assert(isFPImm() && "This is not an FP immediate"); >>> return FPImmVal; >>> } >> >> This can just return it by value. > > > Woops! Quite right, of course. Thanks for catching that. Fixed in r114099. And fixed a follow-up brain fart in r114100.... *blush* From stoklund at 2pi.dk Thu Sep 16 13:09:54 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 16 Sep 2010 11:09:54 -0700 Subject: [llvm-commits] [llvm] r114074 - in /llvm/trunk: lib/Target/CellSPU/SPU64InstrInfo.td lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUInstrInfo.td test/CodeGen/CellSPU/v2i32.ll In-Reply-To: <20100916122933.9B2B72A6C12C@llvm.org> References: <20100916122933.9B2B72A6C12C@llvm.org> Message-ID: On Sep 16, 2010, at 5:29 AM, Kalle Raiskila wrote: > Author: kraiskil > Date: Thu Sep 16 07:29:33 2010 > New Revision: 114074 > > URL: http://llvm.org/viewvc/llvm-project?rev=114074&view=rev > Log: > Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. > > This cleans up after the mess r108567 left in the CellSPU backend. > ORCvt-instruction were used to reinterpret registers, and the ORs were then > removed by isMoveInstr(). This patch now removes 350 instrucions of format: > or $3, $3, $3 > (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is > checked for. > > Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. Hi Kalle, When I introduced the COPY instruction, I had a hard time figuring out which SPU instructions were used as copies and which ones had side effects, so it is very likely I left some intended copies behind. The intention is that COPY gets used for all copies, and it is the only copy instruction that gets coalesced and folded when spilling. The isMoveInstr hook is gone, and 'ori' and 'ai' look like any other instruction to the register allocator. It looks like you are on the right track, COPY_TO_REGCLASS will be translated to a COPY instruction. /jakob From grosbach at apple.com Thu Sep 16 13:19:08 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 16 Sep 2010 11:19:08 -0700 Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH) In-Reply-To: References: Message-ID: <461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com> Hi Jason, Glad to see this moving forward! This looks like a great start. A few minor comments on the patch itself inline below. Apologies in advance for being nitpicky. I don't recall whether we covered this bit specifically before, so at the risk of repeating myself... On a general note, it seems to me that a reasonable first milestone would be to have the target independent layer recognize that the ARM target wants to support object file emission. That is, have llc recognize "-filetype=obj". Right now it issues an error "target does not support generation of this file type!" (which is, of course, entirely correct for the moment). Once the classes are in place to do that, you'll start hitting all of the placeholder asserts(), which is exactly what you want, as you can interactively follow more easily the path the code wants to follow for simple cases and fill in the bits that as you go. Thanks again for working on this! -Jim > Index: lib/Target/ARM/ARM.h > =================================================================== > --- lib/Target/ARM/ARM.h (revision 114081) > +++ lib/Target/ARM/ARM.h (working copy) > @@ -26,7 +26,14 @@ > class FunctionPass; > class JITCodeEmitter; > class formatted_raw_ostream; > +class MCCodeEmitter; > > + > +MCCodeEmitter *createARM_MCCodeEmitter(const Target &, As a style thing, LLVM doesn't use underscores in symbol names. Just createARMMCCodeEmitter() is fine. (The underscore in the X86 equivalent is there as part of the target name, X86_32 vs. X86_64, and so is a bit misleading in this regard). > + TargetMachine &TM, > + MCContext &Ctx); > + > + Extra vertical whitespace here can be removed. > FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, > CodeGenOpt::Level OptLevel); > > @@ -41,6 +48,9 @@ > FunctionPass *createThumb2ITBlockPass(); > FunctionPass *createThumb2SizeReductionPass(); > > + > + > + Ditto. There's other instances below that can be similarly cleaned up. > extern Target TheARMTarget, TheThumbTarget; > > } // end namespace llvm; > Index: lib/Target/ARM/ARMMCCodeEmitter.cpp > =================================================================== > --- lib/Target/ARM/ARMMCCodeEmitter.cpp (revision 0) > +++ lib/Target/ARM/ARMMCCodeEmitter.cpp (revision 0) > @@ -0,0 +1,134 @@ > +//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file implements the ARMMCCodeEmitter class. > +// > +//===----------------------------------------------------------------------===// > + > +#define DEBUG_TYPE "ARM-emitter" Lower-case here, i.e., "arm-emitter" is more consistent with other options of this sort. > +#include "ARM.h" > +#include "ARMInstrInfo.h" > +//#include "ARMFixupKinds.h" > +#include "llvm/MC/MCCodeEmitter.h" > +#include "llvm/MC/MCExpr.h" > +#include "llvm/MC/MCInst.h" > +#include "llvm/Support/raw_ostream.h" > +using namespace llvm; > + > +namespace { > +class ARMMCCodeEmitter : public MCCodeEmitter { > + ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT > + void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT > + const TargetMachine &TM; > + const TargetInstrInfo &TII; > + MCContext &Ctx; > + bool Is64BitMode; Can just remove the extra hold-over bool from the x86 bit here. No 64-bit mode on ARM. :) > +public: > + ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) > + : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { > + } > + > + ~ARMMCCodeEmitter() {} > + > + unsigned getNumFixupKinds() const { > + assert(0 && "ARMCodeEmitter will be implemented soon"); > + } > + > + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { > + static MCFixupKindInfo rtn; > + assert(0 && "ARMCodeEmitter will be implemented soon"); Totally not a big deal, but I tend to phrase these sorts of things as simply " not yet implemented." Personal preference to simply state accurately the status of things rather than indicate anything about the future. Plus, then when I see the assert, I know specifically which function is being hit, rather than just the general name of the feature. > + return rtn; > + } > + > + static unsigned GetARMRegNum(const MCOperand &MO) { > + assert(0 && "ARMCodeEmitter will be implemented soon"); > + return 0; > + } > + > + void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { > + OS << (char)C; > + ++CurByte; > + } > + > + void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, > + raw_ostream &OS) const { > + assert(0 && "ARMCodeEmitter will be implemented soon"); Is this assert necessary? I don't know any reason why the implementation below wouldn't be sufficient. > + // Output the constant in little endian byte order. > + for (unsigned i = 0; i != Size; ++i) { > + EmitByte(Val & 255, CurByte, OS); > + Val >>= 8; > + } > + } > + > + void EmitImmediate(const MCOperand &Disp, > + unsigned ImmSize, MCFixupKind FixupKind, > + unsigned &CurByte, raw_ostream &OS, > + SmallVectorImpl &Fixups, > + int ImmOffset = 0) const; > + > + > + > + > + > + void EncodeInstruction(const MCInst &MI, raw_ostream &OS, > + SmallVectorImpl &Fixups) const; > + > + void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, > + const MCInst &MI, const TargetInstrDesc &Desc, > + raw_ostream &OS) const; > +}; > + > +} // end anonymous namespace > + > + > +MCCodeEmitter *llvm::createARM_MCCodeEmitter(const Target &, > + TargetMachine &TM, > + MCContext &Ctx) { > + return new ARMMCCodeEmitter(TM, Ctx); > +} > + > + > + > +/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate > +/// in an instruction with the specified TSFlags. > +static MCFixupKind getImmFixupKind(uint64_t TSFlags) { > + static MCFixupKind rtn; > + assert(0 && "ARMCodeEmitter will be implemented soon"); > + return rtn; > +} > + > + > +void ARMMCCodeEmitter:: > +EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, > + unsigned &CurByte, raw_ostream &OS, > + SmallVectorImpl &Fixups, int ImmOffset) const { > + assert(0 && "ARMCodeEmitter will be implemented soon"); > +} > + > + > + > + > + > + > +/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. > +/// > +/// MemOperand is the operand # of the start of a memory operand if present. If > +/// Not present, it is -1. > +void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, > + int MemOperand, const MCInst &MI, > + const TargetInstrDesc &Desc, > + raw_ostream &OS) const { > + assert(0 && "ARMCodeEmitter will be implemented soon"); > +} > + > +void ARMMCCodeEmitter:: > +EncodeInstruction(const MCInst &MI, raw_ostream &OS, > + SmallVectorImpl &Fixups) const { > + assert(0 && "ARMCodeEmitter will be implemented soon"); > +} > Index: lib/Target/ARM/CMakeLists.txt > =================================================================== > --- lib/Target/ARM/CMakeLists.txt (revision 114081) > +++ lib/Target/ARM/CMakeLists.txt (working copy) > @@ -28,6 +28,7 @@ > ARMISelLowering.cpp > ARMInstrInfo.cpp > ARMJITInfo.cpp > + ARMMCCodeEmitter.cpp > ARMLoadStoreOptimizer.cpp > ARMMCAsmInfo.cpp > ARMMCInstLower.cpp > From clattner at apple.com Thu Sep 16 13:21:33 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 16 Sep 2010 11:21:33 -0700 Subject: [llvm-commits] [llvm] r114097 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/CorrelatedValuePropagation/crash.ll In-Reply-To: <20100916174236.EC7D22A6C12C@llvm.org> References: <20100916174236.EC7D22A6C12C@llvm.org> Message-ID: On Sep 16, 2010, at 10:42 AM, Owen Anderson wrote: > Author: resistor > Date: Thu Sep 16 12:42:36 2010 > New Revision: 114097 > > URL: http://llvm.org/viewvc/llvm-project?rev=114097&view=rev > Log: > Fix PR8161, in which an unreachable loop causes recursive instruction simplification to try > to replace an instruction with itself. Add a predicate to the simplifier to prevent this case. Why is CVP doing simplifications in unreachable blocks? Why not do a quick DFS of the CFG to find the reachable blocks? -Chris > > Added: > llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll > Modified: > llvm/trunk/lib/Analysis/InstructionSimplify.cpp > > Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=114097&r1=114096&r2=114097&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) > +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Sep 16 12:42:36 2010 > @@ -423,31 +423,44 @@ > /// SimplifyInstruction - See if we can compute a simplified version of this > /// instruction. If not, this returns null. > Value *llvm::SimplifyInstruction(Instruction *I, const TargetData *TD) { > + Value *Ret = 0; > switch (I->getOpcode()) { > default: > return ConstantFoldInstruction(I, TD); > case Instruction::Add: > - return SimplifyAddInst(I->getOperand(0), I->getOperand(1), > - cast(I)->hasNoSignedWrap(), > - cast(I)->hasNoUnsignedWrap(), TD); > + Ret = SimplifyAddInst(I->getOperand(0), I->getOperand(1), > + cast(I)->hasNoSignedWrap(), > + cast(I)->hasNoUnsignedWrap(), TD); > + break; > case Instruction::And: > - return SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD); > + Ret = SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD); > + break; > case Instruction::Or: > - return SimplifyOrInst(I->getOperand(0), I->getOperand(1), TD); > + Ret = SimplifyOrInst(I->getOperand(0), I->getOperand(1), TD); > + break; > case Instruction::ICmp: > - return SimplifyICmpInst(cast(I)->getPredicate(), > - I->getOperand(0), I->getOperand(1), TD); > + Ret = SimplifyICmpInst(cast(I)->getPredicate(), > + I->getOperand(0), I->getOperand(1), TD); > + break; > case Instruction::FCmp: > - return SimplifyFCmpInst(cast(I)->getPredicate(), > - I->getOperand(0), I->getOperand(1), TD); > + Ret = SimplifyFCmpInst(cast(I)->getPredicate(), > + I->getOperand(0), I->getOperand(1), TD); > + break; > case Instruction::Select: > - return SimplifySelectInst(I->getOperand(0), I->getOperand(1), > + Ret = SimplifySelectInst(I->getOperand(0), I->getOperand(1), > I->getOperand(2), TD); > + break; > case Instruction::GetElementPtr: { > SmallVector Ops(I->op_begin(), I->op_end()); > - return SimplifyGEPInst(&Ops[0], Ops.size(), TD); > + Ret = SimplifyGEPInst(&Ops[0], Ops.size(), TD); > + break; > } > } > + > + // It is possible, in situations involving unreachable loops, to > + // have a replacement that, through recursive simplification, ends up > + // simplifying to itself. > + return Ret != I ? Ret : 0; > } > > /// ReplaceAndSimplifyAllUses - Perform From->replaceAllUsesWith(To) and then > > Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll?rev=114097&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll (added) > +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll Thu Sep 16 12:42:36 2010 > @@ -0,0 +1,20 @@ > +; RUN: opt < %s -correlated-propagation > + > +; PR8161 > +define void @test1() nounwind ssp { > +entry: > + br label %for.end > + > +for.cond.us.us: ; preds = %for.cond.us.us > + %cmp6.i.us.us = icmp sgt i32 1, 0 > + %lor.ext.i.us.us = zext i1 %cmp6.i.us.us to i32 > + %lor.ext.add.i.us.us = select i1 %cmp6.i.us.us, i32 %lor.ext.i.us.us, i32 undef > + %conv.i.us.us = trunc i32 %lor.ext.add.i.us.us to i16 > + %sext.us.us = shl i16 %conv.i.us.us, 8 > + %conv6.us.us = ashr i16 %sext.us.us, 8 > + %and.us.us = and i16 %conv6.us.us, %and.us.us > + br i1 false, label %for.end, label %for.cond.us.us > + > +for.end: ; preds = %for.cond.us, %for.cond.us.us, %entry > + ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Sep 16 13:28:33 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 18:28:33 -0000 Subject: [llvm-commits] [llvm] r114103 - in /llvm/trunk: lib/Analysis/LazyValueInfo.cpp test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll Message-ID: <20100916182833.DDA4C2A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 13:28:33 2010 New Revision: 114103 URL: http://llvm.org/viewvc/llvm-project?rev=114103&view=rev Log: It is possible, under specific circumstances involving ptrtoint ConstantExpr's, for LVI to end up trying to merge a Constant into a ConstantRange. Handle this conservatively for now, rather than asserting. The testcase is more complex that I would like, but the manifestation of the problem is sensitive to iteration orders and the state of the LVI cache, and I have not been able to reproduce it with manually constructed or simplified cases. Fixes PR8162. Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=114103&r1=114102&r2=114103&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Thu Sep 16 13:28:33 2010 @@ -201,6 +201,7 @@ return markOverdefined(); return markNotConstant(RHS.getNotConstant()); } else if (isConstantRange()) { + // FIXME: This could be made more precise. return markOverdefined(); } @@ -223,9 +224,12 @@ return markConstantRange(RHS.getConstantRange()); } - // RHS must be a constant, we must be undef, constant, or notconstant. - assert(!isConstantRange() && - "Constant and ConstantRange cannot be merged."); + // RHS must be a constant, we must be constantrange, + // undef, constant, or notconstant. + if (isConstantRange()) { + // FIXME: This could be made more precise. + return markOverdefined(); + } if (isUndefined()) return markConstant(RHS.getConstant()); Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll?rev=114103&view=auto ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll (added) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll Thu Sep 16 13:28:33 2010 @@ -0,0 +1,84 @@ +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0.0" + +%struct.S2 = type {} + + at g_128 = external global %struct.S2, align 1 + at g_106 = external global i16, align 2 + +define void @int328(i16 signext %p_82) noreturn nounwind ssp { +entry: + %tobool3 = icmp eq i16 %p_82, 0 + br label %for.cond.outer + +for.cond.outer: ; preds = %for.cond.loopexit, %entry + br label %for.cond + +for.cond.loopexit: ; preds = %bb.nph, %for.cond9.preheader + br label %for.cond.outer + +for.cond.loopexit4.us-lcssa: ; preds = %if.then + br label %for.cond.loopexit4 + +for.cond.loopexit4: ; preds = %for.cond.loopexit4.us-lcssa.us, %for.cond.loopexit4.us-lcssa + br label %for.cond.backedge + +for.cond: ; preds = %for.cond.backedge, %for.cond.outer + br i1 %tobool3, label %for.cond.split.us, label %for.cond.for.cond.split_crit_edge + +for.cond.for.cond.split_crit_edge: ; preds = %for.cond + br label %lbl_133 + +for.cond.split.us: ; preds = %for.cond + br label %lbl_133.us + +lbl_133.us: ; preds = %lbl_134.us, %for.cond.split.us + br i1 undef, label %if.else14.us-lcssa.us, label %if.then.us + +lbl_134.us: ; preds = %if.then.us + br i1 icmp eq (i16 ptrtoint (%struct.S2* @g_128 to i16), i16 0), label %for.cond9.preheader.us-lcssa.us, label %lbl_133.us + +if.then.us: ; preds = %lbl_133.us + br i1 true, label %for.cond.loopexit4.us-lcssa.us, label %lbl_134.us + +if.else14.us-lcssa.us: ; preds = %lbl_133.us + br label %if.else14 + +for.cond9.preheader.us-lcssa.us: ; preds = %lbl_134.us + br label %for.cond9.preheader + +for.cond.loopexit4.us-lcssa.us: ; preds = %if.then.us + br label %for.cond.loopexit4 + +lbl_133: ; preds = %lbl_134, %for.cond.for.cond.split_crit_edge + %l_109.0 = phi i16 [ 0, %for.cond.for.cond.split_crit_edge ], [ ptrtoint (%struct.S2* @g_128 to i16), %lbl_134 ] + %tobool = icmp eq i32 undef, 0 + br i1 %tobool, label %if.else14.us-lcssa, label %if.then + +if.then: ; preds = %lbl_133 + br i1 false, label %for.cond.loopexit4.us-lcssa, label %lbl_134 + +lbl_134: ; preds = %if.then + br i1 icmp eq (i16 ptrtoint (%struct.S2* @g_128 to i16), i16 0), label %for.cond9.preheader.us-lcssa, label %lbl_133 + +for.cond9.preheader.us-lcssa: ; preds = %lbl_134 + br label %for.cond9.preheader + +for.cond9.preheader: ; preds = %for.cond9.preheader.us-lcssa, %for.cond9.preheader.us-lcssa.us + br i1 undef, label %bb.nph, label %for.cond.loopexit + +bb.nph: ; preds = %for.cond9.preheader + br label %for.cond.loopexit + +if.else14.us-lcssa: ; preds = %lbl_133 + br label %if.else14 + +if.else14: ; preds = %if.else14.us-lcssa, %if.else14.us-lcssa.us + %l_109.0.lcssa = phi i16 [ %l_109.0, %if.else14.us-lcssa ], [ 0, %if.else14.us-lcssa.us ] + store i16 undef, i16* @g_106, align 2 + br label %for.cond.backedge + +for.cond.backedge: ; preds = %if.else14, %for.cond.loopexit4 + br label %for.cond +} From dalej at apple.com Thu Sep 16 13:30:55 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 16 Sep 2010 18:30:55 -0000 Subject: [llvm-commits] [llvm] r114104 - in /llvm/trunk: lib/Transforms/Scalar/CodeGenPrepare.cpp test/CodeGen/X86/2010-09-16-asmcrash.ll Message-ID: <20100916183055.DD2802A6C12C@llvm.org> Author: johannes Date: Thu Sep 16 13:30:55 2010 New Revision: 114104 URL: http://llvm.org/viewvc/llvm-project?rev=114104&view=rev Log: When substituting sunkaddrs into indirect arguments an asm, we were walking the asm arguments once and stashing their Values. This is wrong because the same memory location can be in the list twice, and if the first one has a sunkaddr substituted, the stashed value for the second one will be wrong (use-after-free). PR 8154. Added: llvm/trunk/test/CodeGen/X86/2010-09-16-asmcrash.ll Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=114104&r1=114103&r2=114104&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Thu Sep 16 13:30:55 2010 @@ -738,6 +738,7 @@ bool MadeChange = false; std::vector TargetConstraints = TLI->ParseConstraints(CS); + unsigned ArgNo = 0; for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; @@ -746,9 +747,10 @@ if (OpInfo.ConstraintType == TargetLowering::C_Memory && OpInfo.isIndirect) { - Value *OpVal = OpInfo.CallOperandVal; + Value *OpVal = const_cast(CS.getArgument(ArgNo++)); MadeChange |= OptimizeMemoryInst(I, OpVal, OpVal->getType(), SunkAddrs); - } + } else if (OpInfo.Type == InlineAsm::isInput) + ArgNo++; } return MadeChange; Added: llvm/trunk/test/CodeGen/X86/2010-09-16-asmcrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-16-asmcrash.ll?rev=114104&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-09-16-asmcrash.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-09-16-asmcrash.ll Thu Sep 16 13:30:55 2010 @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-freebsd8.1 -o /dev/null +; This formerly crashed, PR 8154. + +module asm ".weak sem_close" +module asm ".equ sem_close, _sem_close" +module asm ".weak sem_destroy" +module asm ".equ sem_destroy, _sem_destroy" +module asm ".weak sem_getvalue" +module asm ".equ sem_getvalue, _sem_getvalue" +module asm ".weak sem_init" +module asm ".equ sem_init, _sem_init" +module asm ".weak sem_open" +module asm ".equ sem_open, _sem_open" +module asm ".weak sem_post" +module asm ".equ sem_post, _sem_post" +module asm ".weak sem_timedwait" +module asm ".equ sem_timedwait, _sem_timedwait" +module asm ".weak sem_trywait" +module asm ".equ sem_trywait, _sem_trywait" +module asm ".weak sem_unlink" +module asm ".equ sem_unlink, _sem_unlink" +module asm ".weak sem_wait" +module asm ".equ sem_wait, _sem_wait" + +%struct._sem = type { i32, %struct._usem } +%struct._usem = type { i32, i32, i32 } + +define void @_sem_timedwait(%struct._sem* noalias %sem) nounwind ssp { +entry: + br i1 undef, label %while.cond.preheader, label %sem_check_validity.exit + +while.cond.preheader: ; preds = %entry + %tmp4 = getelementptr inbounds %struct._sem* %sem, i64 0, i32 1, i32 1 + br label %while.cond + +sem_check_validity.exit: ; preds = %entry + ret void + +while.cond: ; preds = %while.body, %while.cond.preheader + br i1 undef, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call i8 asm sideeffect "\09lock ; \09\09\09cmpxchgl $2,$1 ;\09 sete\09$0 ;\09\091:\09\09\09\09# atomic_cmpset_int", "={ax},=*m,r,{ax},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %tmp4, i32 undef, i32 undef, i32* %tmp4) nounwind, !srcloc !0 + br i1 undef, label %while.cond, label %return + +while.end: ; preds = %while.cond + br i1 undef, label %if.end18, label %return + +if.end18: ; preds = %while.end + unreachable + +return: ; preds = %while.end, %while.body + ret void +} + +!0 = metadata !{i32 158484} From resistor at mac.com Thu Sep 16 13:35:07 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 18:35:07 -0000 Subject: [llvm-commits] [llvm] r114105 - /llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Message-ID: <20100916183507.E74452A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 13:35:07 2010 New Revision: 114105 URL: http://llvm.org/viewvc/llvm-project?rev=114105&view=rev Log: Use a depth-first iteratation in CorrelatedValuePropagation to avoid wasting time trying to optimize unreachable blocks. Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=114105&r1=114104&r2=114105&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Thu Sep 16 13:35:07 2010 @@ -19,6 +19,7 @@ #include "llvm/Analysis/LazyValueInfo.h" #include "llvm/Support/CFG.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/Statistic.h" using namespace llvm; @@ -166,7 +167,10 @@ bool FnChanged = false; - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { + // Perform a depth-first walk of the CFG so that we don't waste time + // optimizing unreachable blocks. + for (df_iterator FI = df_begin(&F.getEntryBlock()), + FE = df_end(&F.getEntryBlock()); FI != FE; ++FI) { bool BBChanged = false; for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { Instruction *II = BI++; @@ -191,7 +195,7 @@ // Propagating correlated values might leave cruft around. // Try to clean it up before we continue. if (BBChanged) - SimplifyInstructionsInBlock(FI); + SimplifyInstructionsInBlock(*FI); FnChanged |= BBChanged; } From resistor at mac.com Thu Sep 16 13:46:23 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 18:46:23 -0000 Subject: [llvm-commits] [llvm] r114106 - /llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll Message-ID: <20100916184623.987182A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 13:46:23 2010 New Revision: 114106 URL: http://llvm.org/viewvc/llvm-project?rev=114106&view=rev Log: Add missing RUN line to this test. Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll?rev=114106&r1=114105&r2=114106&view=diff ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll (original) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll Thu Sep 16 13:46:23 2010 @@ -1,6 +1,4 @@ -; ModuleID = 'bugpoint-reduced-simplified.bc' -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin11.0.0" +; RUN: opt < %s -jump-threading -correlated-propagation %struct.S2 = type {} From rafael.espindola at gmail.com Thu Sep 16 14:46:31 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 16 Sep 2010 19:46:31 -0000 Subject: [llvm-commits] [llvm] r114109 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp test/MC/ELF/empty.s Message-ID: <20100916194631.9F5AA2A6C12C@llvm.org> Author: rafael Date: Thu Sep 16 14:46:31 2010 New Revision: 114109 URL: http://llvm.org/viewvc/llvm-project?rev=114109&view=rev Log: Print the address of sections as 0 and create the metadata sections in the same order as gnu as. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/test/MC/ELF/empty.s Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114109&r1=114108&r2=114109&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 16 14:46:31 2010 @@ -205,7 +205,8 @@ const MCAsmLayout &Layout); void WriteSymbolTable(MCDataFragment *F, const MCAssembler &Asm, - const MCAsmLayout &Layout); + const MCAsmLayout &Layout, + unsigned NumRegularSections); void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, @@ -405,7 +406,8 @@ void ELFObjectWriterImpl::WriteSymbolTable(MCDataFragment *F, const MCAssembler &Asm, - const MCAsmLayout &Layout) { + const MCAsmLayout &Layout, + unsigned NumRegularSections) { // The string table must be emitted first because we need the index // into the string table for all the symbol names. assert(StringTable.size() && "Missing string table"); @@ -423,20 +425,16 @@ WriteSymbol(F, MSD, Layout); } - // Write out a symbol table entry for each section. - // leaving out the just added .symtab which is at - // the very end + // Write out a symbol table entry for each regular section. unsigned Index = 1; - for (MCAssembler::const_iterator it = Asm.begin(), - ie = Asm.end(); it != ie; ++it, ++Index) { + for (MCAssembler::const_iterator it = Asm.begin(); + Index <= NumRegularSections; ++it, ++Index) { const MCSectionELF &Section = static_cast(it->getSection()); // Leave out relocations so we don't have indexes within // the relocations messed up if (Section.getType() == ELF::SHT_RELA || Section.getType() == ELF::SHT_REL) continue; - if (Index == Asm.size()) - continue; WriteSymbolEntry(F, 0, ELF::STT_SECTION, 0, 0, ELF::STV_DEFAULT, Index); LastLocalSymbolIndex++; } @@ -785,48 +783,41 @@ const MCSection *SymtabSection; unsigned EntrySize = Is64Bit ? ELF::SYMENTRY_SIZE64 : ELF::SYMENTRY_SIZE32; + unsigned NumRegularSections = Asm.size(); + + // We construct .shstrtab, .symtab and .strtab is this order to match gnu as. + const MCSection *ShstrtabSection; + ShstrtabSection = Ctx.getELFSection(".shstrtab", ELF::SHT_STRTAB, 0, + SectionKind::getReadOnly(), false); + MCSectionData &ShstrtabSD = Asm.getOrCreateSectionData(*ShstrtabSection); + ShstrtabSD.setAlignment(1); + ShstrtabIndex = Asm.size(); + SymtabSection = Ctx.getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), false, EntrySize); - MCSectionData &SymtabSD = Asm.getOrCreateSectionData(*SymtabSection); - SymtabSD.setAlignment(Is64Bit ? 8 : 4); - F = new MCDataFragment(&SymtabSD); - - // Symbol table - WriteSymbolTable(F, Asm, Layout); - Asm.AddSectionToTheEnd(SymtabSD, Layout); - const MCSection *StrtabSection; StrtabSection = Ctx.getELFSection(".strtab", ELF::SHT_STRTAB, 0, SectionKind::getReadOnly(), false); - MCSectionData &StrtabSD = Asm.getOrCreateSectionData(*StrtabSection); StrtabSD.setAlignment(1); - - // FIXME: This isn't right. If the sections get rearranged this will - // be wrong. We need a proper lookup. StringTableIndex = Asm.size(); + + // Symbol table + F = new MCDataFragment(&SymtabSD); + WriteSymbolTable(F, Asm, Layout, NumRegularSections); + Asm.AddSectionToTheEnd(SymtabSD, Layout); + F = new MCDataFragment(&StrtabSD); F->getContents().append(StringTable.begin(), StringTable.end()); Asm.AddSectionToTheEnd(StrtabSD, Layout); - const MCSection *ShstrtabSection; - ShstrtabSection = Ctx.getELFSection(".shstrtab", ELF::SHT_STRTAB, 0, - SectionKind::getReadOnly(), false); - - MCSectionData &ShstrtabSD = Asm.getOrCreateSectionData(*ShstrtabSection); - ShstrtabSD.setAlignment(1); - F = new MCDataFragment(&ShstrtabSD); - // FIXME: This isn't right. If the sections get rearranged this will - // be wrong. We need a proper lookup. - ShstrtabIndex = Asm.size(); - // Section header string table. // // The first entry of a string table holds a null character so skip @@ -974,7 +965,7 @@ WriteSecHdrEntry(SectionStringTableIndex[&it->getSection()], Section.getType(), Section.getFlags(), - Layout.getSectionAddress(&SD), + 0, SectionOffsetMap.lookup(&SD.getSection()), Layout.getSectionSize(&SD), sh_link, sh_info, SD.getAlignment(), Modified: llvm/trunk/test/MC/ELF/empty.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/empty.s?rev=114109&r1=114108&r2=114109&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/empty.s (original) +++ llvm/trunk/test/MC/ELF/empty.s Thu Sep 16 14:46:31 2010 @@ -1,6 +1,7 @@ // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s -// Test that like gnu as we create text, data and bss by default. +// Test that like gnu as we create text, data and bss by default. Also test +// that shstrtab, symtab and strtab are listed in that order. // CHECK: ('sh_name', 1) # '.text' // CHECK-NEXT: ('sh_type', 1) @@ -34,3 +35,36 @@ // CHECK-NEXT: ('sh_info', 0) // CHECK-NEXT: ('sh_addralign', 4) // CHECK-NEXT: ('sh_entsize', 0) + +// CHECK: ('sh_name', 18) # '.shstrtab' +// CHECK-NEXT: ('sh_type', 3) +// CHECK-NEXT: ('sh_flags', 0) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', 64) +// CHECK-NEXT: ('sh_size', 44) +// CHECK-NEXT: ('sh_link', 0) +// CHECK-NEXT: ('sh_info', 0) +// CHECK-NEXT: ('sh_addralign', 1) +// CHECK-NEXT: ('sh_entsize', 0) + +// CHECK: ('sh_name', 28) # '.symtab' +// CHECK-NEXT: ('sh_type', 2) +// CHECK-NEXT: ('sh_flags', 0) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', +// CHECK-NEXT: ('sh_size', 96) +// CHECK-NEXT: ('sh_link', 6) +// CHECK-NEXT: ('sh_info', 4) +// CHECK-NEXT: ('sh_addralign', 8) +// CHECK-NEXT: ('sh_entsize', 24) + +// CHECK: ('sh_name', 36) # '.strtab' +// CHECK-NEXT: ('sh_type', 3) +// CHECK-NEXT: ('sh_flags', 0) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', +// CHECK-NEXT: ('sh_size', 1) +// CHECK-NEXT: ('sh_link', 0) +// CHECK-NEXT: ('sh_info', 0) +// CHECK-NEXT: ('sh_addralign', 1) +// CHECK-NEXT: ('sh_entsize', 0) From sabre at nondot.org Thu Sep 16 15:46:39 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 16 Sep 2010 20:46:39 -0000 Subject: [llvm-commits] [llvm] r114116 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_64-new-encoder.s Message-ID: <20100916204639.2EACC2A6C12C@llvm.org> Author: lattner Date: Thu Sep 16 15:46:38 2010 New Revision: 114116 URL: http://llvm.org/viewvc/llvm-project?rev=114116&view=rev Log: fix rdar://8438816 - unrecognized 'fildq' instruction Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114116&r1=114115&r2=114116&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Sep 16 15:46:38 2010 @@ -681,7 +681,8 @@ .Case("cmovzw", "cmovew") .Case("cmovzl", "cmovel") .Case("cmovzq", "cmoveq") .Case("cmovz", "cmove") .Case("fwait", "wait") - .Case("movzx", "movzb") + .Case("movzx", "movzb") // FIXME: Not correct. + .Case("fildq", "fildll") .Default(Name); // FIXME: Hack to recognize cmp{ss,sd,ps,pd}. Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=114116&r1=114115&r2=114116&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Thu Sep 16 15:46:38 2010 @@ -248,5 +248,15 @@ // CHECK: popw %gs // CHECK: encoding: [0x66,0x0f,0xa9] +// rdar://8438816 +fildq -8(%rsp) +fildll -8(%rsp) +// CHECK: fildll -8(%rsp) +// CHECK: encoding: [0xdf,0x6c,0x24,0xf8] +// CHECK: fildll -8(%rsp) +// CHECK: encoding: [0xdf,0x6c,0x24,0xf8] + + + From resistor at mac.com Thu Sep 16 15:51:41 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 20:51:41 -0000 Subject: [llvm-commits] [llvm] r114117 - in /llvm/trunk: include/llvm/Analysis/InstructionSimplify.h include/llvm/Transforms/Utils/Local.h lib/Analysis/InstructionSimplify.cpp Message-ID: <20100916205141.A52302A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 15:51:41 2010 New Revision: 114117 URL: http://llvm.org/viewvc/llvm-project?rev=114117&view=rev Log: Revert r114097, adding back in the assertion against replacing an Instruction by itself. Now that CorrelatedValuePropagation is more careful not to call SimplifyInstructionsInBlock() on an unreachable block, the issue has been fixed at a higher level. Add a big warning to SimplifyInstructionsInBlock() to hopefully prevent this in the future. Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h llvm/trunk/include/llvm/Transforms/Utils/Local.h llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InstructionSimplify.h?rev=114117&r1=114116&r2=114117&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/InstructionSimplify.h (original) +++ llvm/trunk/include/llvm/Analysis/InstructionSimplify.h Thu Sep 16 15:51:41 2010 @@ -71,6 +71,8 @@ /// SimplifyInstruction - See if we can compute a simplified version of this /// instruction. If not, this returns null. + /// WARNING: If called on unreachable code, an instruction may be reported + /// to simplify to itself. Value *SimplifyInstruction(Instruction *I, const TargetData *TD = 0); Modified: llvm/trunk/include/llvm/Transforms/Utils/Local.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/Local.h?rev=114117&r1=114116&r2=114117&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/Local.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/Local.h Thu Sep 16 15:51:41 2010 @@ -69,6 +69,10 @@ /// /// This returns true if it changed the code, note that it can delete /// instructions in other blocks as well in this block. +/// +/// WARNING: Do not use this function on unreachable blocks, as recursive +/// simplification is not able to handle corner-case scenarios that can +/// arise in them. bool SimplifyInstructionsInBlock(BasicBlock *BB, const TargetData *TD = 0); //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=114117&r1=114116&r2=114117&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Sep 16 15:51:41 2010 @@ -423,44 +423,31 @@ /// SimplifyInstruction - See if we can compute a simplified version of this /// instruction. If not, this returns null. Value *llvm::SimplifyInstruction(Instruction *I, const TargetData *TD) { - Value *Ret = 0; switch (I->getOpcode()) { default: return ConstantFoldInstruction(I, TD); case Instruction::Add: - Ret = SimplifyAddInst(I->getOperand(0), I->getOperand(1), - cast(I)->hasNoSignedWrap(), - cast(I)->hasNoUnsignedWrap(), TD); - break; + return SimplifyAddInst(I->getOperand(0), I->getOperand(1), + cast(I)->hasNoSignedWrap(), + cast(I)->hasNoUnsignedWrap(), TD); case Instruction::And: - Ret = SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD); - break; + return SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD); case Instruction::Or: - Ret = SimplifyOrInst(I->getOperand(0), I->getOperand(1), TD); - break; + return SimplifyOrInst(I->getOperand(0), I->getOperand(1), TD); case Instruction::ICmp: - Ret = SimplifyICmpInst(cast(I)->getPredicate(), - I->getOperand(0), I->getOperand(1), TD); - break; + return SimplifyICmpInst(cast(I)->getPredicate(), + I->getOperand(0), I->getOperand(1), TD); case Instruction::FCmp: - Ret = SimplifyFCmpInst(cast(I)->getPredicate(), - I->getOperand(0), I->getOperand(1), TD); - break; + return SimplifyFCmpInst(cast(I)->getPredicate(), + I->getOperand(0), I->getOperand(1), TD); case Instruction::Select: - Ret = SimplifySelectInst(I->getOperand(0), I->getOperand(1), + return SimplifySelectInst(I->getOperand(0), I->getOperand(1), I->getOperand(2), TD); - break; case Instruction::GetElementPtr: { SmallVector Ops(I->op_begin(), I->op_end()); - Ret = SimplifyGEPInst(&Ops[0], Ops.size(), TD); - break; + return SimplifyGEPInst(&Ops[0], Ops.size(), TD); } } - - // It is possible, in situations involving unreachable loops, to - // have a replacement that, through recursive simplification, ends up - // simplifying to itself. - return Ret != I ? Ret : 0; } /// ReplaceAndSimplifyAllUses - Perform From->replaceAllUsesWith(To) and then From jasonwkim at google.com Thu Sep 16 15:54:49 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 16 Sep 2010 13:54:49 -0700 Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH) In-Reply-To: <461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com> References: <461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com> Message-ID: Hi Jim. Thanks for the feedback. Much appreciated. Here's the revised patch. On Thu, Sep 16, 2010 at 11:19 AM, Jim Grosbach wrote: > Hi Jason, > > Glad to see this moving forward! This looks like a great start. A few minor comments on the patch itself inline below. Apologies in advance for being nitpicky. > > I don't recall whether we covered this bit specifically before, so at the risk of repeating myself... On a general note, it seems to me that a reasonable first milestone would be to have the target independent layer recognize that the ARM target wants to support object file emission. That is, have llc recognize "-filetype=obj". Right now it issues an error "target does not support generation of this file type!" (which is, of course, entirely correct for the moment). Once the classes are in place to do that, you'll start hitting all of the placeholder asserts(), which is exactly what you want, as you can interactively follow more easily the path the code wants to follow for simple cases and fill in the bits that as you go. > Sounds like a plan! Up for that next. > >> Index: lib/Target/ARM/ARM.h >> =================================================================== >> --- lib/Target/ARM/ARM.h ? ? ?(revision 114081) >> +++ lib/Target/ARM/ARM.h ? ? ?(working copy) >> @@ -26,7 +26,14 @@ >> ?class FunctionPass; >> ?class JITCodeEmitter; >> ?class formatted_raw_ostream; >> +class MCCodeEmitter; >> >> + >> +MCCodeEmitter *createARM_MCCodeEmitter(const Target &, > > As a style thing, LLVM doesn't use underscores in symbol names. Just createARMMCCodeEmitter() is fine. (The underscore in the X86 equivalent is there as part of the target name, X86_32 vs. X86_64, and so is a bit misleading in this regard). > > >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx); >> + >> + > > Extra vertical whitespace here can be removed. > >> ?FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenOpt::Level OptLevel); >> >> @@ -41,6 +48,9 @@ >> ?FunctionPass *createThumb2ITBlockPass(); >> ?FunctionPass *createThumb2SizeReductionPass(); >> >> + >> + >> + > > Ditto. There's other instances below that can be similarly cleaned up. > >> ?extern Target TheARMTarget, TheThumbTarget; >> >> ?} // end namespace llvm; >> Index: lib/Target/ARM/ARMMCCodeEmitter.cpp >> =================================================================== >> --- lib/Target/ARM/ARMMCCodeEmitter.cpp ? ? ? (revision 0) >> +++ lib/Target/ARM/ARMMCCodeEmitter.cpp ? ? ? (revision 0) >> @@ -0,0 +1,134 @@ >> +//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// >> +// >> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure >> +// >> +// This file is distributed under the University of Illinois Open Source >> +// License. See LICENSE.TXT for details. >> +// >> +//===----------------------------------------------------------------------===// >> +// >> +// This file implements the ARMMCCodeEmitter class. >> +// >> +//===----------------------------------------------------------------------===// >> + >> +#define DEBUG_TYPE "ARM-emitter" > > Lower-case here, i.e., "arm-emitter" is more consistent with other options of this sort. > >> +#include "ARM.h" >> +#include "ARMInstrInfo.h" >> +//#include "ARMFixupKinds.h" >> +#include "llvm/MC/MCCodeEmitter.h" >> +#include "llvm/MC/MCExpr.h" >> +#include "llvm/MC/MCInst.h" >> +#include "llvm/Support/raw_ostream.h" >> +using namespace llvm; >> + >> +namespace { >> +class ARMMCCodeEmitter : public MCCodeEmitter { >> + ?ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT >> + ?void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT >> + ?const TargetMachine &TM; >> + ?const TargetInstrInfo &TII; >> + ?MCContext &Ctx; >> + ?bool Is64BitMode; > > Can just remove the extra hold-over bool from the x86 bit here. No 64-bit mode on ARM. :) > >> +public: >> + ?ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) >> + ? ?: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { >> + ?} >> + >> + ?~ARMMCCodeEmitter() {} >> + >> + ?unsigned getNumFixupKinds() const { >> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); >> + ?} >> + >> + ?const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { >> + ? ?static MCFixupKindInfo rtn; >> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); > > Totally not a big deal, but I tend to phrase these sorts of things as simply " not yet implemented." Personal preference to simply state accurately the status of things rather than indicate anything about the future. Plus, then when I see the assert, I know specifically which function is being hit, rather than just the general name of the feature. > >> + ? ?return rtn; >> + ?} >> + >> + ?static unsigned GetARMRegNum(const MCOperand &MO) { >> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); >> + ? ?return 0; >> + ?} >> + >> + ?void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { >> + ? ?OS << (char)C; >> + ? ?++CurByte; >> + ?} >> + >> + ?void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, >> + ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const { >> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); > > Is this assert necessary? I don't know any reason why the implementation below wouldn't be sufficient. > >> + ? ?// Output the constant in little endian byte order. >> + ? ?for (unsigned i = 0; i != Size; ++i) { >> + ? ? ?EmitByte(Val & 255, CurByte, OS); >> + ? ? ?Val >>= 8; >> + ? ?} >> + ?} >> + >> + ?void EmitImmediate(const MCOperand &Disp, >> + ? ? ? ? ? ? ? ? ? ? unsigned ImmSize, MCFixupKind FixupKind, >> + ? ? ? ? ? ? ? ? ? ? unsigned &CurByte, raw_ostream &OS, >> + ? ? ? ? ? ? ? ? ? ? SmallVectorImpl &Fixups, >> + ? ? ? ? ? ? ? ? ? ? int ImmOffset = 0) const; >> + >> + >> + >> + >> + >> + ?void EncodeInstruction(const MCInst &MI, raw_ostream &OS, >> + ? ? ? ? ? ? ? ? ? ? ? ? SmallVectorImpl &Fixups) const; >> + >> + ?void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, >> + ? ? ? ? ? ? ? ? ? ? ? ?const MCInst &MI, const TargetInstrDesc &Desc, >> + ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const; >> +}; >> + >> +} // end anonymous namespace >> + >> + >> +MCCodeEmitter *llvm::createARM_MCCodeEmitter(const Target &, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx) { >> + ?return new ARMMCCodeEmitter(TM, Ctx); >> +} >> + >> + >> + >> +/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate >> +/// in an instruction with the specified TSFlags. >> +static MCFixupKind getImmFixupKind(uint64_t TSFlags) { >> + ?static MCFixupKind rtn; >> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >> + ?return rtn; >> +} >> + >> + >> +void ARMMCCodeEmitter:: >> +EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, >> + ? ? ? ? ? ? ?unsigned &CurByte, raw_ostream &OS, >> + ? ? ? ? ? ? ?SmallVectorImpl &Fixups, int ImmOffset) const { >> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >> +} >> + >> + >> + >> + >> + >> + >> +/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. >> +/// >> +/// MemOperand is the operand # of the start of a memory operand if present. ?If >> +/// Not present, it is -1. >> +void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int MemOperand, const MCInst &MI, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetInstrDesc &Desc, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const { >> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >> +} >> + >> +void ARMMCCodeEmitter:: >> +EncodeInstruction(const MCInst &MI, raw_ostream &OS, >> + ? ? ? ? ? ? ? ? ?SmallVectorImpl &Fixups) const { >> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >> +} >> Index: lib/Target/ARM/CMakeLists.txt >> =================================================================== >> --- lib/Target/ARM/CMakeLists.txt ? ? (revision 114081) >> +++ lib/Target/ARM/CMakeLists.txt ? ? (working copy) >> @@ -28,6 +28,7 @@ >> ? ?ARMISelLowering.cpp >> ? ?ARMInstrInfo.cpp >> ? ?ARMJITInfo.cpp >> + ?ARMMCCodeEmitter.cpp >> ? ?ARMLoadStoreOptimizer.cpp >> ? ?ARMMCAsmInfo.cpp >> ? ?ARMMCInstLower.cpp >> > -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf.patch3 Type: application/octet-stream Size: 5546 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/f5c9ff3f/attachment.obj From dpatel at apple.com Thu Sep 16 15:57:50 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 16 Sep 2010 20:57:50 -0000 Subject: [llvm-commits] [llvm] r114119 - in /llvm/trunk: lib/CodeGen/AsmPrinter/DwarfDebug.cpp test/DebugInfo/2010-09-16-EmptyFilename.ll Message-ID: <20100916205750.2AAE32A6C12C@llvm.org> Author: dpatel Date: Thu Sep 16 15:57:49 2010 New Revision: 114119 URL: http://llvm.org/viewvc/llvm-project?rev=114119&view=rev Log: If FE forgot to provide a file name (usually it uses "stdin" as name in such situation) then make one up to ensure that debug info is not malformed. Added: llvm/trunk/test/DebugInfo/2010-09-16-EmptyFilename.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=114119&r1=114118&r2=114119&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Sep 16 15:57:49 2010 @@ -1750,6 +1750,10 @@ unsigned DId; assert (DirName.empty() == false && "Invalid directory name!"); + // If FE did not provide a file name, then assume stdin. + if (FileName.empty()) + return GetOrCreateSourceID(DirName, ""); + StringMap::iterator DI = DirectoryIdMap.find(DirName); if (DI != DirectoryIdMap.end()) { DId = DI->getValue(); Added: llvm/trunk/test/DebugInfo/2010-09-16-EmptyFilename.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-09-16-EmptyFilename.ll?rev=114119&view=auto ============================================================================== --- llvm/trunk/test/DebugInfo/2010-09-16-EmptyFilename.ll (added) +++ llvm/trunk/test/DebugInfo/2010-09-16-EmptyFilename.ll Thu Sep 16 15:57:49 2010 @@ -0,0 +1,31 @@ +; RUN: llc -O0 < %s - | FileCheck %s +; Radar 8286101 +; CHECK: File size +; CHECK-NEXT: stdin +; CHECK-NEXT: Directory + +define i32 @foo() nounwind ssp { +entry: + ret i32 42, !dbg !8 +} + +define i32 @bar() nounwind ssp { +entry: + ret i32 21, !dbg !10 +} + +!llvm.dbg.sp = !{!0, !6} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"bug.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114084)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", metadata !7, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524329, metadata !"bug.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!8 = metadata !{i32 53, i32 13, metadata !9, null} +!9 = metadata !{i32 524299, metadata !0, i32 53, i32 11, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 4, i32 13, metadata !11, null} +!11 = metadata !{i32 524299, metadata !12, i32 4, i32 13, metadata !7, i32 2} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 524299, metadata !6, i32 4, i32 11, metadata !7, i32 1} ; [ DW_TAG_lexical_block ] From gohman at apple.com Thu Sep 16 17:08:33 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 16 Sep 2010 22:08:33 -0000 Subject: [llvm-commits] [llvm] r114121 - in /llvm/trunk: include/llvm/Analysis/Passes.h include/llvm/LinkAllPasses.h lib/Analysis/MemDepPrinter.cpp Message-ID: <20100916220833.284482A6C12C@llvm.org> Author: djg Date: Thu Sep 16 17:08:32 2010 New Revision: 114121 URL: http://llvm.org/viewvc/llvm-project?rev=114121&view=rev Log: Add a pass which prints out all the memdep dependencies. Added: llvm/trunk/lib/Analysis/MemDepPrinter.cpp Modified: llvm/trunk/include/llvm/Analysis/Passes.h llvm/trunk/include/llvm/LinkAllPasses.h Modified: llvm/trunk/include/llvm/Analysis/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=114121&r1=114120&r2=114121&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Passes.h (original) +++ llvm/trunk/include/llvm/Analysis/Passes.h Thu Sep 16 17:08:32 2010 @@ -170,6 +170,13 @@ // Print module-level debug info metadata in human-readable form. ModulePass *createModuleDebugInfoPrinterPass(); + + //===--------------------------------------------------------------------===// + // + // createMemDepPrinter - This pass exhaustively collects all memdep + // information and prints it with -analyze. + // + FunctionPass *createMemDepPrinter(); } #endif Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=114121&r1=114120&r2=114121&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Thu Sep 16 17:08:32 2010 @@ -147,6 +147,7 @@ (void) llvm::createSinkingPass(); (void) llvm::createLowerAtomicPass(); (void) llvm::createCorrelatedValuePropagationPass(); + (void) llvm::createMemDepPrinter(); (void)new llvm::IntervalPartition(); (void)new llvm::FindUsedTypes(); Added: llvm/trunk/lib/Analysis/MemDepPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=114121&view=auto ============================================================================== --- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (added) +++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Thu Sep 16 17:08:32 2010 @@ -0,0 +1,153 @@ +//===- MemDepPrinter.cpp - Printer for MemoryDependenceAnalysis -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "llvm/Analysis/MemoryDependenceAnalysis.h" +#include "llvm/Analysis/Passes.h" +#include "llvm/Assembly/Writer.h" +#include "llvm/Support/CallSite.h" +#include "llvm/Support/InstIterator.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/SetVector.h" +using namespace llvm; + +namespace { + struct MemDepPrinter : public FunctionPass { + const Function *F; + + typedef PointerIntPair InstAndClobberFlag; + typedef std::pair Dep; + typedef SmallSetVector DepSet; + typedef DenseMap DepSetMap; + DepSetMap Deps; + + static char ID; // Pass identifcation, replacement for typeid + MemDepPrinter() : FunctionPass(ID) {} + + virtual bool runOnFunction(Function &F); + + void print(raw_ostream &OS, const Module * = 0) const; + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesAll(); + } + + virtual void releaseMemory() { + Deps.clear(); + F = 0; + } + }; +} + +char MemDepPrinter::ID = 0; +INITIALIZE_PASS(MemDepPrinter, "print-memdeps", "Print MemDeps of function", false, true); + +FunctionPass *llvm::createMemDepPrinter() { + return new MemDepPrinter(); +} + +bool MemDepPrinter::runOnFunction(Function &F) { + this->F = &F; + MemoryDependenceAnalysis &MDA = getAnalysis(); + + // All this code uses non-const interfaces because MemDep is not + // const-friendly, though nothing is actually modified. + for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) { + Instruction *Inst = &*I; + + if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory()) + continue; + + MemDepResult Res = MDA.getDependency(Inst); + if (!Res.isNonLocal()) { + assert(Res.isClobber() != Res.isDef() && + "Local dep should be def or clobber!"); + Deps[Inst].insert(std::make_pair(InstAndClobberFlag(Res.getInst(), + Res.isClobber()), + static_cast(0))); + } else if (CallSite CS = cast(Inst)) { + const MemoryDependenceAnalysis::NonLocalDepInfo &NLDI = + MDA.getNonLocalCallDependency(CS); + + DepSet &InstDeps = Deps[Inst]; + for (MemoryDependenceAnalysis::NonLocalDepInfo::const_iterator + I = NLDI.begin(), E = NLDI.end(); I != E; ++I) { + const MemDepResult &Res = I->getResult(); + assert(Res.isClobber() != Res.isDef() && + "Resolved non-local call dep should be def or clobber!"); + InstDeps.insert(std::make_pair(InstAndClobberFlag(Res.getInst(), + Res.isClobber()), + I->getBB())); + } + } else { + SmallVector NLDI; + if (LoadInst *LI = dyn_cast(Inst)) { + // FIXME: Volatile is not handled properly here. + MDA.getNonLocalPointerDependency(LI->getPointerOperand(), !LI->isVolatile(), + LI->getParent(), NLDI); + } else if (StoreInst *SI = dyn_cast(Inst)) { + // FIXME: Volatile is not handled properly here. + MDA.getNonLocalPointerDependency(SI->getPointerOperand(), false, + SI->getParent(), NLDI); + } else if (VAArgInst *VI = dyn_cast(Inst)) { + MDA.getNonLocalPointerDependency(VI->getPointerOperand(), false, + VI->getParent(), NLDI); + } else { + llvm_unreachable("Unknown memory instruction!"); + } + + DepSet &InstDeps = Deps[Inst]; + for (SmallVectorImpl::const_iterator + I = NLDI.begin(), E = NLDI.end(); I != E; ++I) { + const MemDepResult &Res = I->getResult(); + assert(Res.isClobber() != Res.isDef() && + "Resolved non-local pointer dep should be def or clobber!"); + InstDeps.insert(std::make_pair(InstAndClobberFlag(Res.getInst(), + Res.isClobber()), + I->getBB())); + } + } + } + + return false; +} + +void MemDepPrinter::print(raw_ostream &OS, const Module *M) const { + for (const_inst_iterator I = inst_begin(*F), E = inst_end(*F); I != E; ++I) { + const Instruction *Inst = &*I; + + DepSetMap::const_iterator I = Deps.find(Inst); + if (I == Deps.end()) + continue; + + const DepSet &InstDeps = I->second; + + for (DepSet::const_iterator I = InstDeps.begin(), E = InstDeps.end(); + I != E; ++I) { + const Instruction *DepInst = I->first.getPointer(); + bool isClobber = I->first.getInt(); + const BasicBlock *DepBB = I->second; + + OS << " " << (isClobber ? "Clobber" : " Def"); + if (DepBB) { + OS << " in block "; + WriteAsOperand(OS, DepBB, /*PrintType=*/false, M); + } + OS << " from: "; + DepInst->print(OS); + OS << "\n"; + } + + Inst->print(OS); + OS << "\n\n"; + } +} From gohman at apple.com Thu Sep 16 17:50:09 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 16 Sep 2010 22:50:09 -0000 Subject: [llvm-commits] [llvm] r114126 - /llvm/trunk/lib/Analysis/MemDepPrinter.cpp Message-ID: <20100916225009.ACBA62A6C12C@llvm.org> Author: djg Date: Thu Sep 16 17:50:09 2010 New Revision: 114126 URL: http://llvm.org/viewvc/llvm-project?rev=114126&view=rev Log: Rename a variable to avoid a declaration conflict. Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=114126&r1=114125&r2=114126&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Thu Sep 16 17:50:09 2010 @@ -125,11 +125,11 @@ for (const_inst_iterator I = inst_begin(*F), E = inst_end(*F); I != E; ++I) { const Instruction *Inst = &*I; - DepSetMap::const_iterator I = Deps.find(Inst); - if (I == Deps.end()) + DepSetMap::const_iterator DI = Deps.find(Inst); + if (DI == Deps.end()) continue; - const DepSet &InstDeps = I->second; + const DepSet &InstDeps = DI->second; for (DepSet::const_iterator I = InstDeps.begin(), E = InstDeps.end(); I != E; ++I) { From gkistanova at gmail.com Thu Sep 16 18:02:15 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Thu, 16 Sep 2010 23:02:15 -0000 Subject: [llvm-commits] [zorg] r114127 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100916230215.CFCF92A6C12C@llvm.org> Author: gkistanova Date: Thu Sep 16 18:02:15 2010 New Revision: 114127 URL: http://llvm.org/viewvc/llvm-project?rev=114127&view=rev Log: Removed extra_args for Windows 7 slave. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114127&r1=114126&r2=114127&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Sep 16 18:02:15 2010 @@ -501,14 +501,12 @@ 'haltOnFailure' : True }, {'name' : 'make_llvm', 'description' : 'make llvm', - 'extra_args' : ['-j4'], # Extra step-specific properties 'haltOnFailure' : True }, {'name' : 'configure_llvmgcc', 'description' : 'configure llvm-gcc', 'haltOnFailure' : True }, {'name' : 'make_llvmgcc', 'description' : 'make llvm-gcc', - 'extra_args' : ['-j4'], 'haltOnFailure' : True }, {'name' : 'install_llvmgcc', 'description' : 'install llvm-gcc', From benny.kra at googlemail.com Thu Sep 16 18:06:18 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 16 Sep 2010 23:06:18 -0000 Subject: [llvm-commits] [llvm] r114128 - /llvm/trunk/lib/Analysis/CMakeLists.txt Message-ID: <20100916230618.67B462A6C12C@llvm.org> Author: d0k Date: Thu Sep 16 18:06:18 2010 New Revision: 114128 URL: http://llvm.org/viewvc/llvm-project?rev=114128&view=rev Log: Update CMake build. Modified: llvm/trunk/lib/Analysis/CMakeLists.txt Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=114128&r1=114127&r2=114128&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Thu Sep 16 18:06:18 2010 @@ -27,6 +27,7 @@ LoopDependenceAnalysis.cpp LoopInfo.cpp LoopPass.cpp + MemDepPrinter.cpp MemoryBuiltins.cpp MemoryDependenceAnalysis.cpp ModuleDebugInfoPrinter.cpp From clattner at apple.com Thu Sep 16 18:32:52 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 16 Sep 2010 16:32:52 -0700 Subject: [llvm-commits] [llvm] r114121 - in /llvm/trunk: include/llvm/Analysis/Passes.h include/llvm/LinkAllPasses.h lib/Analysis/MemDepPrinter.cpp In-Reply-To: <20100916220833.284482A6C12C@llvm.org> References: <20100916220833.284482A6C12C@llvm.org> Message-ID: On Sep 16, 2010, at 3:08 PM, Dan Gohman wrote: > Author: djg > Date: Thu Sep 16 17:08:32 2010 > New Revision: 114121 > > URL: http://llvm.org/viewvc/llvm-project?rev=114121&view=rev > Log: > Add a pass which prints out all the memdep dependencies. Cool, testcase? -Chris > > Added: > llvm/trunk/lib/Analysis/MemDepPrinter.cpp > Modified: > llvm/trunk/include/llvm/Analysis/Passes.h > llvm/trunk/include/llvm/LinkAllPasses.h > > Modified: llvm/trunk/include/llvm/Analysis/Passes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=114121&r1=114120&r2=114121&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/Passes.h (original) > +++ llvm/trunk/include/llvm/Analysis/Passes.h Thu Sep 16 17:08:32 2010 > @@ -170,6 +170,13 @@ > > // Print module-level debug info metadata in human-readable form. > ModulePass *createModuleDebugInfoPrinterPass(); > + > + //===--------------------------------------------------------------------===// > + // > + // createMemDepPrinter - This pass exhaustively collects all memdep > + // information and prints it with -analyze. > + // > + FunctionPass *createMemDepPrinter(); > } > > #endif > > Modified: llvm/trunk/include/llvm/LinkAllPasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=114121&r1=114120&r2=114121&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/LinkAllPasses.h (original) > +++ llvm/trunk/include/llvm/LinkAllPasses.h Thu Sep 16 17:08:32 2010 > @@ -147,6 +147,7 @@ > (void) llvm::createSinkingPass(); > (void) llvm::createLowerAtomicPass(); > (void) llvm::createCorrelatedValuePropagationPass(); > + (void) llvm::createMemDepPrinter(); > > (void)new llvm::IntervalPartition(); > (void)new llvm::FindUsedTypes(); > > Added: llvm/trunk/lib/Analysis/MemDepPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=114121&view=auto > ============================================================================== > --- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (added) > +++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Thu Sep 16 17:08:32 2010 > @@ -0,0 +1,153 @@ > +//===- MemDepPrinter.cpp - Printer for MemoryDependenceAnalysis -----------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// > +//===----------------------------------------------------------------------===// > + > +#include "llvm/Analysis/MemoryDependenceAnalysis.h" > +#include "llvm/Analysis/Passes.h" > +#include "llvm/Assembly/Writer.h" > +#include "llvm/Support/CallSite.h" > +#include "llvm/Support/InstIterator.h" > +#include "llvm/Support/ErrorHandling.h" > +#include "llvm/ADT/SetVector.h" > +using namespace llvm; > + > +namespace { > + struct MemDepPrinter : public FunctionPass { > + const Function *F; > + > + typedef PointerIntPair InstAndClobberFlag; > + typedef std::pair Dep; > + typedef SmallSetVector DepSet; > + typedef DenseMap DepSetMap; > + DepSetMap Deps; > + > + static char ID; // Pass identifcation, replacement for typeid > + MemDepPrinter() : FunctionPass(ID) {} > + > + virtual bool runOnFunction(Function &F); > + > + void print(raw_ostream &OS, const Module * = 0) const; > + > + virtual void getAnalysisUsage(AnalysisUsage &AU) const { > + AU.addRequired(); > + AU.setPreservesAll(); > + } > + > + virtual void releaseMemory() { > + Deps.clear(); > + F = 0; > + } > + }; > +} > + > +char MemDepPrinter::ID = 0; > +INITIALIZE_PASS(MemDepPrinter, "print-memdeps", "Print MemDeps of function", false, true); > + > +FunctionPass *llvm::createMemDepPrinter() { > + return new MemDepPrinter(); > +} > + > +bool MemDepPrinter::runOnFunction(Function &F) { > + this->F = &F; > + MemoryDependenceAnalysis &MDA = getAnalysis(); > + > + // All this code uses non-const interfaces because MemDep is not > + // const-friendly, though nothing is actually modified. > + for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) { > + Instruction *Inst = &*I; > + > + if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory()) > + continue; > + > + MemDepResult Res = MDA.getDependency(Inst); > + if (!Res.isNonLocal()) { > + assert(Res.isClobber() != Res.isDef() && > + "Local dep should be def or clobber!"); > + Deps[Inst].insert(std::make_pair(InstAndClobberFlag(Res.getInst(), > + Res.isClobber()), > + static_cast(0))); > + } else if (CallSite CS = cast(Inst)) { > + const MemoryDependenceAnalysis::NonLocalDepInfo &NLDI = > + MDA.getNonLocalCallDependency(CS); > + > + DepSet &InstDeps = Deps[Inst]; > + for (MemoryDependenceAnalysis::NonLocalDepInfo::const_iterator > + I = NLDI.begin(), E = NLDI.end(); I != E; ++I) { > + const MemDepResult &Res = I->getResult(); > + assert(Res.isClobber() != Res.isDef() && > + "Resolved non-local call dep should be def or clobber!"); > + InstDeps.insert(std::make_pair(InstAndClobberFlag(Res.getInst(), > + Res.isClobber()), > + I->getBB())); > + } > + } else { > + SmallVector NLDI; > + if (LoadInst *LI = dyn_cast(Inst)) { > + // FIXME: Volatile is not handled properly here. > + MDA.getNonLocalPointerDependency(LI->getPointerOperand(), !LI->isVolatile(), > + LI->getParent(), NLDI); > + } else if (StoreInst *SI = dyn_cast(Inst)) { > + // FIXME: Volatile is not handled properly here. > + MDA.getNonLocalPointerDependency(SI->getPointerOperand(), false, > + SI->getParent(), NLDI); > + } else if (VAArgInst *VI = dyn_cast(Inst)) { > + MDA.getNonLocalPointerDependency(VI->getPointerOperand(), false, > + VI->getParent(), NLDI); > + } else { > + llvm_unreachable("Unknown memory instruction!"); > + } > + > + DepSet &InstDeps = Deps[Inst]; > + for (SmallVectorImpl::const_iterator > + I = NLDI.begin(), E = NLDI.end(); I != E; ++I) { > + const MemDepResult &Res = I->getResult(); > + assert(Res.isClobber() != Res.isDef() && > + "Resolved non-local pointer dep should be def or clobber!"); > + InstDeps.insert(std::make_pair(InstAndClobberFlag(Res.getInst(), > + Res.isClobber()), > + I->getBB())); > + } > + } > + } > + > + return false; > +} > + > +void MemDepPrinter::print(raw_ostream &OS, const Module *M) const { > + for (const_inst_iterator I = inst_begin(*F), E = inst_end(*F); I != E; ++I) { > + const Instruction *Inst = &*I; > + > + DepSetMap::const_iterator I = Deps.find(Inst); > + if (I == Deps.end()) > + continue; > + > + const DepSet &InstDeps = I->second; > + > + for (DepSet::const_iterator I = InstDeps.begin(), E = InstDeps.end(); > + I != E; ++I) { > + const Instruction *DepInst = I->first.getPointer(); > + bool isClobber = I->first.getInt(); > + const BasicBlock *DepBB = I->second; > + > + OS << " " << (isClobber ? "Clobber" : " Def"); > + if (DepBB) { > + OS << " in block "; > + WriteAsOperand(OS, DepBB, /*PrintType=*/false, M); > + } > + OS << " from: "; > + DepInst->print(OS); > + OS << "\n"; > + } > + > + Inst->print(OS); > + OS << "\n\n"; > + } > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Sep 16 18:32:36 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 23:32:36 -0000 Subject: [llvm-commits] [llvm] r114130 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp Message-ID: <20100916233236.2C5592A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 18:32:35 2010 New Revision: 114130 URL: http://llvm.org/viewvc/llvm-project?rev=114130&view=rev Log: Do not expose the locking for the PassRegistry in the header. Be careful to synchronize any method that might lazily initialize the pImpl. Modified: llvm/trunk/include/llvm/PassRegistry.h llvm/trunk/lib/VMCore/PassRegistry.cpp Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=114130&r1=114129&r2=114130&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Thu Sep 16 18:32:35 2010 @@ -18,7 +18,6 @@ #define LLVM_PASSREGISTRY_H #include "llvm/ADT/StringRef.h" -#include "llvm/System/Mutex.h" namespace llvm { @@ -33,7 +32,6 @@ /// each thread. class PassRegistry { mutable void *pImpl; - mutable sys::SmartMutex Lock; void *getImpl() const; public: Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=114130&r1=114129&r2=114130&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Thu Sep 16 18:32:35 2010 @@ -16,6 +16,7 @@ #include "llvm/PassSupport.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/System/Mutex.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/StringMap.h" @@ -33,6 +34,8 @@ return &*PassRegistryObj; } +sys::SmartMutex Lock; + //===----------------------------------------------------------------------===// // PassRegistryImpl // @@ -65,18 +68,21 @@ // PassRegistry::~PassRegistry() { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(pImpl); if (Impl) delete Impl; pImpl = 0; } const PassInfo *PassRegistry::getPassInfo(const void *TI) const { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.find(TI); return I != Impl->PassInfoMap.end() ? I->second : 0; } const PassInfo *PassRegistry::getPassInfo(StringRef Arg) const { + sys::SmartScopedLock Guard(Lock); PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::StringMapType::const_iterator I = Impl->PassInfoStringMap.find(Arg); @@ -127,7 +133,6 @@ const void *PassID, PassInfo& Registeree, bool isDefault) { - sys::SmartScopedLock Guard(Lock); PassInfo *InterfaceInfo = const_cast(getPassInfo(InterfaceID)); if (InterfaceInfo == 0) { // First reference to Interface, register it now. @@ -142,6 +147,8 @@ assert(ImplementationInfo && "Must register pass before adding to AnalysisGroup!"); + sys::SmartScopedLock Guard(Lock); + // Make sure we keep track of the fact that the implementation implements // the interface. ImplementationInfo->addInterfaceImplemented(InterfaceInfo); From clattner at apple.com Thu Sep 16 18:40:47 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 16 Sep 2010 16:40:47 -0700 Subject: [llvm-commits] [llvm] r114130 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp In-Reply-To: <20100916233236.2C5592A6C12C@llvm.org> References: <20100916233236.2C5592A6C12C@llvm.org> Message-ID: On Sep 16, 2010, at 4:32 PM, Owen Anderson wrote: > Author: resistor > Date: Thu Sep 16 18:32:35 2010 > New Revision: 114130 > > URL: http://llvm.org/viewvc/llvm-project?rev=114130&view=rev > Log: > Do not expose the locking for the PassRegistry in the header. Be careful to > synchronize any method that might lazily initialize the pImpl. $ make CXX.Flags=-Wglobal-constructors llvm[0]: Compiling PassRegistry.cpp for Debug+Asserts build PassRegistry.cpp:37:23: warning: declaration requires a global constructor [-Wglobal-constructors] sys::SmartMutex Lock; ^ PassRegistry.cpp:37:23: warning: declaration requires a global destructor [-Wglobal-constructors] 2 warnings generated. Why not ManagedStatic? -Chris > > Modified: > llvm/trunk/include/llvm/PassRegistry.h > llvm/trunk/lib/VMCore/PassRegistry.cpp > > Modified: llvm/trunk/include/llvm/PassRegistry.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=114130&r1=114129&r2=114130&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/PassRegistry.h (original) > +++ llvm/trunk/include/llvm/PassRegistry.h Thu Sep 16 18:32:35 2010 > @@ -18,7 +18,6 @@ > #define LLVM_PASSREGISTRY_H > > #include "llvm/ADT/StringRef.h" > -#include "llvm/System/Mutex.h" > > namespace llvm { > > @@ -33,7 +32,6 @@ > /// each thread. > class PassRegistry { > mutable void *pImpl; > - mutable sys::SmartMutex Lock; > void *getImpl() const; > > public: > > Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=114130&r1=114129&r2=114130&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) > +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Thu Sep 16 18:32:35 2010 > @@ -16,6 +16,7 @@ > #include "llvm/PassSupport.h" > #include "llvm/Support/Compiler.h" > #include "llvm/Support/ManagedStatic.h" > +#include "llvm/System/Mutex.h" > #include "llvm/ADT/DenseMap.h" > #include "llvm/ADT/SmallPtrSet.h" > #include "llvm/ADT/StringMap.h" > @@ -33,6 +34,8 @@ > return &*PassRegistryObj; > } > > +sys::SmartMutex Lock; > + > //===----------------------------------------------------------------------===// > // PassRegistryImpl > // > @@ -65,18 +68,21 @@ > // > > PassRegistry::~PassRegistry() { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(pImpl); > if (Impl) delete Impl; > pImpl = 0; > } > > const PassInfo *PassRegistry::getPassInfo(const void *TI) const { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.find(TI); > return I != Impl->PassInfoMap.end() ? I->second : 0; > } > > const PassInfo *PassRegistry::getPassInfo(StringRef Arg) const { > + sys::SmartScopedLock Guard(Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > PassRegistryImpl::StringMapType::const_iterator > I = Impl->PassInfoStringMap.find(Arg); > @@ -127,7 +133,6 @@ > const void *PassID, > PassInfo& Registeree, > bool isDefault) { > - sys::SmartScopedLock Guard(Lock); > PassInfo *InterfaceInfo = const_cast(getPassInfo(InterfaceID)); > if (InterfaceInfo == 0) { > // First reference to Interface, register it now. > @@ -142,6 +147,8 @@ > assert(ImplementationInfo && > "Must register pass before adding to AnalysisGroup!"); > > + sys::SmartScopedLock Guard(Lock); > + > // Make sure we keep track of the fact that the implementation implements > // the interface. > ImplementationInfo->addInterfaceImplemented(InterfaceInfo); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Sep 16 18:44:50 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 16 Sep 2010 23:44:50 -0000 Subject: [llvm-commits] [llvm] r114131 - /llvm/trunk/lib/VMCore/PassRegistry.cpp Message-ID: <20100916234450.9689A2A6C12C@llvm.org> Author: resistor Date: Thu Sep 16 18:44:50 2010 New Revision: 114131 URL: http://llvm.org/viewvc/llvm-project?rev=114131&view=rev Log: Allow the PassRegistry mutex to be lazily initialized, and clean up the global namespace at the same time. Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=114131&r1=114130&r2=114131&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Thu Sep 16 18:44:50 2010 @@ -34,7 +34,7 @@ return &*PassRegistryObj; } -sys::SmartMutex Lock; +static ManagedStatic > Lock; //===----------------------------------------------------------------------===// // PassRegistryImpl @@ -68,21 +68,21 @@ // PassRegistry::~PassRegistry() { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(pImpl); if (Impl) delete Impl; pImpl = 0; } const PassInfo *PassRegistry::getPassInfo(const void *TI) const { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.find(TI); return I != Impl->PassInfoMap.end() ? I->second : 0; } const PassInfo *PassRegistry::getPassInfo(StringRef Arg) const { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::StringMapType::const_iterator I = Impl->PassInfoStringMap.find(Arg); @@ -94,7 +94,7 @@ // void PassRegistry::registerPass(const PassInfo &PI) { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(getImpl()); bool Inserted = Impl->PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second; @@ -108,7 +108,7 @@ } void PassRegistry::unregisterPass(const PassInfo &PI) { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::MapType::iterator I = Impl->PassInfoMap.find(PI.getTypeInfo()); @@ -120,7 +120,7 @@ } void PassRegistry::enumerateWith(PassRegistrationListener *L) { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(getImpl()); for (PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.begin(), E = Impl->PassInfoMap.end(); I != E; ++I) @@ -147,7 +147,7 @@ assert(ImplementationInfo && "Must register pass before adding to AnalysisGroup!"); - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); // Make sure we keep track of the fact that the implementation implements // the interface. @@ -170,13 +170,13 @@ } void PassRegistry::addRegistrationListener(PassRegistrationListener *L) { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); PassRegistryImpl *Impl = static_cast(getImpl()); Impl->Listeners.push_back(L); } void PassRegistry::removeRegistrationListener(PassRegistrationListener *L) { - sys::SmartScopedLock Guard(Lock); + sys::SmartScopedLock Guard(*Lock); // NOTE: This is necessary, because removeRegistrationListener() can be called // as part of the llvm_shutdown sequence. Since we have no control over the From gohman at apple.com Thu Sep 16 19:15:39 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 16 Sep 2010 17:15:39 -0700 Subject: [llvm-commits] [llvm] r113858 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/LibCallAliasAnalysis.h include/llvm/Analysis/LibCallSemantics.h include/llvm/LLVMContext.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp lib/Analysis/LibCallAliasAnalysis.cpp lib/Analysis/ScalarEvolutionAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/VMCore/LLVMContext.cpp In-Reply-To: <4AF054A2-3D4A-4D33-B83B-BD69A0210AEF@apple.com> References: <20100914212510.DD2912A6C12C@llvm.org> <4AF054A2-3D4A-4D33-B83B-BD69A0210AEF@apple.com> Message-ID: <6B7BBA7C-4C68-4CE9-A41E-68008265E337@apple.com> On Sep 15, 2010, at 6:24 PM, Chris Lattner wrote: > On Sep 14, 2010, at 2:25 PM, Dan Gohman wrote: >> >> + explicit Location(const Value *P = 0, > > Should the pointer be allowed to be null? Is Location() something that is useful? It's convenient, though not necessary. > > >> + /// pointsToConstantMemory - If the specified memory location is known to be >> + /// constant, return true. This allows disambiguation of store >> /// instructions from constant pointers. >> /// >> + virtual bool pointsToConstantMemory(const Location &Loc); > > Interesting. I agree with the change, but I'll have to think about what this can be used for. TBAA metadata can mark arbitrary memory as constant, which could be more fine-grained than just marking global-variables constant. It would be less precise than llvm.invariant.* though. Dan From ofv at wanadoo.es Thu Sep 16 19:30:52 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 17 Sep 2010 00:30:52 -0000 Subject: [llvm-commits] [llvm] r114139 - /llvm/trunk/docs/UsingLibraries.html Message-ID: <20100917003052.D9E432A6C12C@llvm.org> Author: ofv Date: Thu Sep 16 19:30:52 2010 New Revision: 114139 URL: http://llvm.org/viewvc/llvm-project?rev=114139&view=rev Log: Direct CMake users to the right place for up-to-date info about using LLVM libraries. Modified: llvm/trunk/docs/UsingLibraries.html Modified: llvm/trunk/docs/UsingLibraries.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/UsingLibraries.html?rev=114139&r1=114138&r2=114139&view=diff ============================================================================== --- llvm/trunk/docs/UsingLibraries.html (original) +++ llvm/trunk/docs/UsingLibraries.html Thu Sep 16 19:30:52 2010 @@ -23,7 +23,11 @@

    Written by Reid Spencer

    -

    Warning: This document is out of date, please see llvm-config for more information.

    +

    Warning: This document is out of date, for more + information please + see llvm-config or, + if you use CMake, the CMake LLVM + guide.

    Abstract
    From isanbard at gmail.com Thu Sep 16 19:33:03 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 17 Sep 2010 00:33:03 -0000 Subject: [llvm-commits] [llvm] r114140 - /llvm/trunk/include/llvm/Intrinsics.td Message-ID: <20100917003303.B9E8F2A6C12C@llvm.org> Author: void Date: Thu Sep 16 19:33:03 2010 New Revision: 114140 URL: http://llvm.org/viewvc/llvm-project?rev=114140&view=rev Log: Add "pointer to x86mmx" type to the intrinsics. Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=114140&r1=114139&r2=114140&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Thu Sep 16 19:33:03 2010 @@ -110,6 +110,7 @@ def llvm_metadata_ty : LLVMType; // !{...} def llvm_x86mmx_ty : LLVMType; +def llvm_ptrx86mmx_ty : LLVMPointerType; // <1 x i64>* def llvm_v2i8_ty : LLVMType; // 2 x i8 def llvm_v4i8_ty : LLVMType; // 4 x i8 From gohman at apple.com Thu Sep 16 19:33:43 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 00:33:43 -0000 Subject: [llvm-commits] [llvm] r114141 - /llvm/trunk/lib/Analysis/MemDepPrinter.cpp Message-ID: <20100917003343.2BB502A6C12C@llvm.org> Author: djg Date: Thu Sep 16 19:33:43 2010 New Revision: 114141 URL: http://llvm.org/viewvc/llvm-project?rev=114141&view=rev Log: Add an #include of raw_ostream.h. Previously, this only compiled because it was using Twine.h's declaration of operator<<(const Twine &). Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=114141&r1=114140&r2=114141&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Thu Sep 16 19:33:43 2010 @@ -16,6 +16,7 @@ #include "llvm/Support/CallSite.h" #include "llvm/Support/InstIterator.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/SetVector.h" using namespace llvm; From ofv at wanadoo.es Thu Sep 16 19:43:54 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 17 Sep 2010 00:43:54 -0000 Subject: [llvm-commits] [llvm] r114143 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20100917004354.19CC52A6C12C@llvm.org> Author: ofv Date: Thu Sep 16 19:43:53 2010 New Revision: 114143 URL: http://llvm.org/viewvc/llvm-project?rev=114143&view=rev Log: Updated LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=114143&r1=114142&r2=114143&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Thu Sep 16 19:43:53 2010 @@ -1,8 +1,8 @@ -set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget) @@ -11,12 +11,12 @@ set(MSVC_LIB_DEPS_LLVMAsmPrinter LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMBitReader LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) -set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) @@ -35,7 +35,7 @@ set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmPrinter LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430AsmPrinter LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPIC16AsmPrinter LLVMPIC16CodeGen LLVMPIC16Info LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430CodeGen LLVMMSP430Info LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsCodeGen LLVMMipsInfo LLVMSupport LLVMTarget) @@ -44,17 +44,17 @@ set(MSVC_LIB_DEPS_LLVMPIC16AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPIC16CodeGen LLVMPIC16Info LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPIC16CodeGen LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMPIC16Info LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPIC16Info LLVMSupport) -set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSparcInfo LLVMSupport LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMSystem ) -set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystemZInfo LLVMTarget) +set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystemZCodeGen LLVMSystemZInfo LLVMTarget) set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZInfo LLVMTarget) set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) @@ -64,7 +64,7 @@ set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMX86AsmPrinter LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Info LLVMSupport) -set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget LLVMXCoreCodeGen LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport LLVMSystem) From clattner at apple.com Thu Sep 16 19:53:42 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 16 Sep 2010 17:53:42 -0700 Subject: [llvm-commits] [llvm] r114131 - /llvm/trunk/lib/VMCore/PassRegistry.cpp In-Reply-To: <20100916234450.9689A2A6C12C@llvm.org> References: <20100916234450.9689A2A6C12C@llvm.org> Message-ID: <6495BF04-2C1C-4F17-A3F7-841713C5075E@apple.com> On Sep 16, 2010, at 4:44 PM, Owen Anderson wrote: > Author: resistor > Date: Thu Sep 16 18:44:50 2010 > New Revision: 114131 > > URL: http://llvm.org/viewvc/llvm-project?rev=114131&view=rev > Log: > Allow the PassRegistry mutex to be lazily initialized, and clean up the global namespace at the same time. Thanks! Next question, why not ManagedStatic and put the lock in PassRegistryImpl? -Chris > > Modified: > llvm/trunk/lib/VMCore/PassRegistry.cpp > > Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=114131&r1=114130&r2=114131&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) > +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Thu Sep 16 18:44:50 2010 > @@ -34,7 +34,7 @@ > return &*PassRegistryObj; > } > > -sys::SmartMutex Lock; > +static ManagedStatic > Lock; > > //===----------------------------------------------------------------------===// > // PassRegistryImpl > @@ -68,21 +68,21 @@ > // > > PassRegistry::~PassRegistry() { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(pImpl); > if (Impl) delete Impl; > pImpl = 0; > } > > const PassInfo *PassRegistry::getPassInfo(const void *TI) const { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.find(TI); > return I != Impl->PassInfoMap.end() ? I->second : 0; > } > > const PassInfo *PassRegistry::getPassInfo(StringRef Arg) const { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > PassRegistryImpl::StringMapType::const_iterator > I = Impl->PassInfoStringMap.find(Arg); > @@ -94,7 +94,7 @@ > // > > void PassRegistry::registerPass(const PassInfo &PI) { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > bool Inserted = > Impl->PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second; > @@ -108,7 +108,7 @@ > } > > void PassRegistry::unregisterPass(const PassInfo &PI) { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > PassRegistryImpl::MapType::iterator I = > Impl->PassInfoMap.find(PI.getTypeInfo()); > @@ -120,7 +120,7 @@ > } > > void PassRegistry::enumerateWith(PassRegistrationListener *L) { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > for (PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.begin(), > E = Impl->PassInfoMap.end(); I != E; ++I) > @@ -147,7 +147,7 @@ > assert(ImplementationInfo && > "Must register pass before adding to AnalysisGroup!"); > > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > > // Make sure we keep track of the fact that the implementation implements > // the interface. > @@ -170,13 +170,13 @@ > } > > void PassRegistry::addRegistrationListener(PassRegistrationListener *L) { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > PassRegistryImpl *Impl = static_cast(getImpl()); > Impl->Listeners.push_back(L); > } > > void PassRegistry::removeRegistrationListener(PassRegistrationListener *L) { > - sys::SmartScopedLock Guard(Lock); > + sys::SmartScopedLock Guard(*Lock); > > // NOTE: This is necessary, because removeRegistrationListener() can be called > // as part of the llvm_shutdown sequence. Since we have no control over the > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Thu Sep 16 19:54:40 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 16 Sep 2010 17:54:40 -0700 Subject: [llvm-commits] [llvm] r113858 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/LibCallAliasAnalysis.h include/llvm/Analysis/LibCallSemantics.h include/llvm/LLVMContext.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp lib/Analysis/LibCallAliasAnalysis.cpp lib/Analysis/ScalarEvolutionAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/VMCore/LLVMContext.cpp In-Reply-To: <6B7BBA7C-4C68-4CE9-A41E-68008265E337@apple.com> References: <20100914212510.DD2912A6C12C@llvm.org> <4AF054A2-3D4A-4D33-B83B-BD69A0210AEF@apple.com> <6B7BBA7C-4C68-4CE9-A41E-68008265E337@apple.com> Message-ID: <53C9C01C-779C-4759-9BFD-736A31F1CB8E@apple.com> On Sep 16, 2010, at 5:15 PM, Dan Gohman wrote: On Sep 15, 2010, at 6:24 PM, Chris Lattner wrote: > >> On Sep 14, 2010, at 2:25 PM, Dan Gohman wrote: >>> >>> + explicit Location(const Value *P = 0, >> >> Should the pointer be allowed to be null? Is Location() something that is useful? > > It's convenient, though not necessary. Sure, I'm asking whether you think it is the "right" thing for the API. I'm not challenging your decision, just making sure you thought about it. Previously, the pointer provided to alias() was not allowed to be null. -Chris From gohman at apple.com Thu Sep 16 20:38:06 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 01:38:06 -0000 Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll Message-ID: <20100917013806.562CB2A6C12C@llvm.org> Author: djg Date: Thu Sep 16 20:38:06 2010 New Revision: 114148 URL: http://llvm.org/viewvc/llvm-project?rev=114148&view=rev Log: Fix the folding of floating-point math library calls, like sin(infinity), so that it detects errors on platforms where libm doesn't set errno. It's still subject to host libm details though. Added: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=114148&r1=114147&r2=114148&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Sep 16 20:38:06 2010 @@ -32,6 +32,7 @@ #include "llvm/Support/MathExtras.h" #include #include +#include using namespace llvm; //===----------------------------------------------------------------------===// @@ -1039,9 +1040,12 @@ static Constant *ConstantFoldFP(double (*NativeFP)(double), double V, const Type *Ty) { + feclearexcept(FE_ALL_EXCEPT); errno = 0; V = NativeFP(V); - if (errno != 0) { + if (errno != 0 || + fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) { + feclearexcept(FE_ALL_EXCEPT); errno = 0; return 0; } @@ -1056,9 +1060,12 @@ static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double), double V, double W, const Type *Ty) { + feclearexcept(FE_ALL_EXCEPT); errno = 0; V = NativeFP(V, W); - if (errno != 0) { + if (errno != 0 || + fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) { + feclearexcept(FE_ALL_EXCEPT); errno = 0; return 0; } Added: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114148&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Thu Sep 16 20:38:06 2010 @@ -0,0 +1,19 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s + +; This shouldn't fold, because sin(inf) is invalid. +; CHECK: @foo +; CHECK: %t = call double @sin(double 0x7FF0000000000000) +define double @foo() { + %t = call double @sin(double 0x7FF0000000000000) + ret double %t +} + +; This should fold. +; CHECK: @bar +; CHECK: ret double 0x3FDA6026360C2F91 +define double @bar() { + %t = call double @sin(double 9.0) + ret double %t +} + +declare double @sin(double) From daniel at zuster.org Thu Sep 16 21:07:51 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 17 Sep 2010 02:07:51 -0000 Subject: [llvm-commits] [zorg] r114150 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100917020751.35CA52A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 16 21:07:51 2010 New Revision: 114150 URL: http://llvm.org/viewvc/llvm-project?rev=114150&view=rev Log: LNT/nt: Record 'as' and 'ld' versions. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=114150&r1=114149&r2=114150&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Thu Sep 16 21:07:51 2010 @@ -443,6 +443,11 @@ # Create the machine entry. machine = lnt.testing.Machine(nick, machine_info) + # Capture binary tool versions. + run_info['as_version'] = capture(["gcc", "-c", "-xassembler", "/dev/null", + "-Wa,-v"], include_stderr=True).strip() + run_info['ld_version'] = capture(["ld", "-v"], include_stderr=True).strip() + # FIXME: Hack, use better method of getting versions. Ideally, from binaries # so we are more likely to be accurate. run_info['llvm_revision'] = llvm_source_version @@ -685,7 +690,7 @@ help="Don't automatically derive submission name", action="store_false", default=True) group.add_option("", "--no-machdep-info", dest="use_machdep_info", - help=("Don't put machine (instance) dependent " + help=("Don't put machine (instance) dependent " "variables with machine info"), action="store_false", default=True) group.add_option("", "--run-order", dest="run_order", metavar="STR", From ofv at wanadoo.es Thu Sep 16 21:17:13 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 17 Sep 2010 02:17:13 -0000 Subject: [llvm-commits] [llvm] r114151 - /llvm/trunk/docs/GettingStartedVS.html Message-ID: <20100917021713.4DA572A6C12C@llvm.org> Author: ofv Date: Thu Sep 16 21:17:13 2010 New Revision: 114151 URL: http://llvm.org/viewvc/llvm-project?rev=114151&view=rev Log: Updated GettingStartedVS.html to reflect current state. Reorganized it too. Modified: llvm/trunk/docs/GettingStartedVS.html Modified: llvm/trunk/docs/GettingStartedVS.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStartedVS.html?rev=114151&r1=114150&r2=114151&view=diff ============================================================================== --- llvm/trunk/docs/GettingStartedVS.html (original) +++ llvm/trunk/docs/GettingStartedVS.html Thu Sep 16 21:17:13 2010 @@ -14,19 +14,12 @@
    • Overview -
    • Getting Started Quickly (A Summary)
    • Requirements
      1. Hardware
      2. Software
      • - -
    • Getting Started with LLVM -
        -
      1. Terminology and Notation -
      2. The Location of LLVM Object Files -
      • - +
    • Getting Started
    • An Example Using the LLVM Tool Chain
    • Common Problems
    • Links @@ -47,26 +40,23 @@
      -

      The Visual Studio port at this time is experimental. It is suitable for - use only if you are writing your own compiler front end or otherwise have a +

      The Visual Studio port has some limitations. It is suitable for + use if you are writing your own compiler front end or otherwise have a need to dynamically generate machine code. The JIT and interpreter are functional, but it is currently not possible to generate assembly code which - is then assembled into an executable. You can indirectly create executables - by using the C back end.

      + is then assembled into an executable. You can output object files + in COFF format, though. You can also indirectly create executables + by using the C backend.

      + +

      llvm-gcc is based on GCC, which cannot be bootstrapped + using VC++. There are llvm-gcc binaries based on MinGW + available on the + LLVM download + page. Eventually, Clang + will be able to produce executables on Windows.

      -

      To emphasize, there is no C/C++ front end currently available. - llvm-gcc is based on GCC, which cannot be bootstrapped using VC++. - Eventually there should be a llvm-gcc based on Cygwin or MinGW that - is usable. There is also the option of generating bitcode files on Unix and - copying them over to Windows. But be aware the odds of linking C++ code - compiled with llvm-gcc with code compiled with VC++ is essentially - zero.

      - -

      The LLVM test suite cannot be run on the Visual Studio port at this - time.

      - -

      Most of the tools build and work. bugpoint does build, but does - not work. The other tools 'should' work, but have not been fully tested.

      +

      bugpoint does build, but does not work. The other tools + 'should' work, but have not been fully tested.

      Additional information about the LLVM directory structure and tool chain can be found on the main Getting Started @@ -76,89 +66,6 @@

      - Getting Started Quickly (A Summary) -
      - - -
      - -

      Here's the short story for getting up and running quickly with LLVM:

      - -
        -
      1. Read the documentation.
        2. -
      2. Seriously, read the documentation.
        3. -
      3. Remember that you were warned twice about reading the documentation.
        4. - -
      4. Get the Source Code -
          -
        • With the distributed files: -
            -
          1. cd where-you-want-llvm-to-live -
          2. gunzip --stdout llvm-version.tar.gz | tar -xvf - -       or use WinZip -
          3. cd llvm
            4. -
          • - -
        • With anonymous Subversion access: -
            -
          1. cd where-you-want-llvm-to-live
            2. -
          2. svn co http://llvm.org/svn/llvm-project/llvm-top/trunk llvm-top -
            3. -
          3. make checkout MODULE=llvm -
          4. cd llvm
            5. -
          • -
        5. - -
      5. Use CMake to generate up-to-date - project files: -
        • This step is currently optional as LLVM does still come with a - normal Visual Studio solution file, but it is not always kept up-to-date - and will soon be deprecated in favor of the multi-platform generator - CMake.
          • -
        • If CMake is installed then the most simple way is to just start the - CMake GUI, select the directory where you have LLVM extracted to, and - the default options should all be fine. The one option you may really - want to change, regardless of anything else, might be the - CMAKE_INSTALL_PREFIX setting to select a directory to INSTALL to once - compiling is complete.
          • -
        • If you use CMake to generate the Visual Studio solution and project - files, then the Solution will have a few extra options compared to the - current included one. The projects may still be built individually, but - to build them all do not just select all of them in batch build (as some - are meant as configuration projects), but rather select and build just - the ALL_BUILD project to build everything, or the INSTALL project, which - first builds the ALL_BUILD project, then installs the LLVM headers, libs, - and other useful things to the directory set by the CMAKE_INSTALL_PREFIX - setting when you first configured CMake.
          • -
        -
        6. - -
      6. Start Visual Studio -
          -
        • If you did not use CMake, then simply double click on the solution - file llvm/win32/llvm.sln.
          • -
        • If you used CMake, then the directory you created the project files, - the root directory will have an llvm.sln file, just - double-click on that to open Visual Studio.
          • -
        7. - -
      7. Build the LLVM Suite: -
          -
        • Simply build the solution.
          • -
        • The Fibonacci project is a sample program that uses the JIT. Modify - the project's debugging properties to provide a numeric command line - argument. The program will print the corresponding fibonacci value.
          • -
        8. - -
      - -

      It is strongly encouraged that you get the latest version from Subversion as -changes are continually making the VS support better.

      - -
      - - -
      Requirements
      @@ -206,59 +113,82 @@
      - Getting Started with LLVM + Getting Started
      -

      The remainder of this guide is meant to get you up and running with -LLVM using Visual Studio and to give you some basic information about the LLVM -environment.

      - -
      - - -
      - Terminology and Notation -
      +

      Here's the short story for getting up and running quickly with LLVM:

      -
      +
        +
      1. Read the documentation.
        2. +
      2. Seriously, read the documentation.
        3. +
      3. Remember that you were warned twice about reading the documentation.
        4. -

        Throughout this manual, the following names are used to denote paths -specific to the local system and working environment. These are not -environment variables you need to set but just strings used in the rest -of this document below. In any of the examples below, simply replace -each of these names with the appropriate pathname on your local system. -All these paths are absolute:

        - -
        -
        SRC_ROOT
        -

        This is the top level directory of the LLVM source tree.

        - -
        OBJ_ROOT
        -

        This is the top level directory of the LLVM object tree (i.e. the - tree where object files and compiled programs will be placed. It is - fixed at SRC_ROOT/win32).

        -
        +
      4. Get the Source Code +
          +
        • With the distributed files: +
            +
          1. cd where-you-want-llvm-to-live +
          2. gunzip --stdout llvm-version.tar.gz | tar -xvf - +       or use WinZip +
          3. cd llvm
            4. +
          • -
      +
    • With anonymous Subversion access: +
        +
      1. cd where-you-want-llvm-to-live
        2. +
      2. svn co http://llvm.org/svn/llvm-project/llvm-top/trunk llvm-top +
        3. +
      3. make checkout MODULE=llvm +
      4. cd llvm
        5. +
      • +
    + +
  • Use CMake to generate up-to-date + project files: +
      +
    • Once CMake is installed then the most simple way is to just + start the CMake GUI, select the directory where you have LLVM + extracted to, and the default options should all be fine. One + option you may really want to change, regardless of anything + else, might be the CMAKE_INSTALL_PREFIX setting to select a + directory to INSTALL to once compiling is complete, although + installation is not mandatory for using LLVM. Another + important option is LLVM_TARGETS_TO_BUILD, which controls the + LLVM target architectures that are included on the build. If + you want to run the example described + below you must set that variable to "X86;CBackend".
      • +
    • See the LLVM CMake guide for + detailed information about how to configure the LLVM + build.
      • +
    +
    • - -
    - The Location of LLVM Object Files -
    +
  • Start Visual Studio +
      +
    • In the directory you created the project files will have + an llvm.sln file, just double-click on that to open + Visual Studio.
      • +
    • -
    +
  • Build the LLVM Suite: +
      +
    • The projects may still be built individually, but + to build them all do not just select all of them in batch build (as some + are meant as configuration projects), but rather select and build just + the ALL_BUILD project to build everything, or the INSTALL project, which + first builds the ALL_BUILD project, then installs the LLVM headers, libs, + and other useful things to the directory set by the CMAKE_INSTALL_PREFIX + setting when you first configured CMake.
      • +
    • The Fibonacci project is a sample program that uses the JIT. + Modify the project's debugging properties to provide a numeric + command line argument or run it from the command line. The + program will print the corresponding fibonacci value.
      • +
    • -

    The object files are placed under OBJ_ROOT/Debug for debug builds - and OBJ_ROOT/Release for release (optimized) builds. These include - both executables and libararies that your application can link against.

    - -

    The files that configure would create when building on Unix are - created by the Configure project and placed in - OBJ_ROOT/llvm. You application must have OBJ_ROOT in its include - search path just before SRC_ROOT/include.

    +
    @@ -296,9 +226,9 @@ lli tool, compile it to native assembly with the llc, optimize or analyze it further with the opt tool, etc.

    -

    Note: while you cannot do this step on Windows, you can do it on a - Unix system and transfer hello.bc to Windows. Important: - transfer as a binary file!

    +

    Note: you will need the llvm-gcc binaries from the + LLVM + download page

  • Run the program using the just-in-time compiler:

    @@ -327,6 +257,15 @@ 
     % llc -march=c hello.bc
    + +

    Note: you need to add the C backend to the LLVM build, + which amounts to setting the CMake + variable LLVM_TARGETS_TO_BUILD to "X86;CBackend" when + you generate the VS solution files. See + the LLVM CMake guide for more + information about how to configure the LLVM + build.

    • +

  • Compile to binary using Microsoft C:

    @@ -360,17 +299,6 @@
    -
      -
    • In Visual C++, if you are linking with the x86 target statically, the - linker will remove the x86 target library from your generated executable or - shared library because there are no references to it. You can force the - linker to include these references by using - "/INCLUDE:_X86TargetMachineModule" when linking. In the Visual - Studio IDE, this can be added in -Project Properties->Linker->Input->Force Symbol References. -
      • -
    -

    If you are having problems building or using LLVM, or if you have any other general questions about LLVM, please consult the Frequently Asked Questions page.

    From daniel at zuster.org Thu Sep 16 21:47:07 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 17 Sep 2010 02:47:07 -0000 Subject: [llvm-commits] [llvm] r114154 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/expr_symbol_modifiers.s Message-ID: <20100917024707.E6E852A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 16 21:47:07 2010 New Revision: 114154 URL: http://llvm.org/viewvc/llvm-project?rev=114154&view=rev Log: MC/AsmParser: Add support for 'a + 4 at GOTPCREL' and friends, by reconsing the expression to include the modifier. - Gross, but this a corner case we don't expect to see often in practice, but it is worth accepting. - Also improves diagnostics on invalid modifiers. Added: llvm/trunk/test/MC/AsmParser/expr_symbol_modifiers.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114154&r1=114153&r2=114154&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Sep 16 21:47:07 2010 @@ -204,6 +204,9 @@ /// ParseEscapedString - Parse the current token as a string which may include /// escaped characters and return the string contents. bool ParseEscapedString(std::string &Data); + + const MCExpr *ApplyModifierToExpr(const MCExpr *E, + MCSymbolRefExpr::VariantKind Variant); }; /// \brief Generic implementations of directive handling, etc. which is shared @@ -485,8 +488,13 @@ // Lookup the symbol variant if used. MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; - if (Split.first.size() != Identifier.size()) + if (Split.first.size() != Identifier.size()) { Variant = MCSymbolRefExpr::getVariantKindForName(Split.second); + if (Variant == MCSymbolRefExpr::VK_Invalid) { + Variant = MCSymbolRefExpr::VK_None; + TokError("invalid variant '" + Split.second + "'"); + } + } // If this is an absolute variable reference, substitute it now to preserve // semantics in the face of reassignment. @@ -564,6 +572,52 @@ return ParseExpression(Res, EndLoc); } +const MCExpr * +AsmParser::ApplyModifierToExpr(const MCExpr *E, + MCSymbolRefExpr::VariantKind Variant) { + // Recurse over the given expression, rebuilding it to apply the given variant + // if there is exactly one symbol. + switch (E->getKind()) { + case MCExpr::Target: + case MCExpr::Constant: + return 0; + + case MCExpr::SymbolRef: { + const MCSymbolRefExpr *SRE = cast(E); + + if (SRE->getKind() != MCSymbolRefExpr::VK_None) { + TokError("invalid variant on expression '" + + getTok().getIdentifier() + "' (already modified)"); + return E; + } + + return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); + } + + case MCExpr::Unary: { + const MCUnaryExpr *UE = cast(E); + const MCExpr *Sub = ApplyModifierToExpr(UE->getSubExpr(), Variant); + if (!Sub) + return 0; + return MCUnaryExpr::Create(UE->getOpcode(), Sub, getContext()); + } + + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(E); + const MCExpr *LHS = ApplyModifierToExpr(BE->getLHS(), Variant); + const MCExpr *RHS = ApplyModifierToExpr(BE->getRHS(), Variant); + + if (!LHS && !RHS) + return 0; + + if (!LHS) LHS = BE->getLHS(); + if (!RHS) RHS = BE->getRHS(); + + return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); + } + } +} + /// ParseExpression - Parse an expression and return it. /// /// expr ::= expr +,- expr -> lowest. @@ -577,6 +631,31 @@ if (ParsePrimaryExpr(Res, EndLoc) || ParseBinOpRHS(1, Res, EndLoc)) return true; + // As a special case, we support 'a op b @ modifier' by rewriting the + // expression to include the modifier. This is inefficient, but in general we + // expect users to use 'a at modifier op b'. + if (Lexer.getKind() == AsmToken::At) { + Lex(); + + if (Lexer.isNot(AsmToken::Identifier)) + return TokError("unexpected symbol modifier following '@'"); + + MCSymbolRefExpr::VariantKind Variant = + MCSymbolRefExpr::getVariantKindForName(getTok().getIdentifier()); + if (Variant == MCSymbolRefExpr::VK_Invalid) + return TokError("invalid variant '" + getTok().getIdentifier() + "'"); + + const MCExpr *ModifiedRes = ApplyModifierToExpr(Res, Variant); + if (!ModifiedRes) { + return TokError("invalid modifier '" + getTok().getIdentifier() + + "' (no symbols present)"); + return true; + } + + Res = ModifiedRes; + Lex(); + } + // Try to constant fold it up front, if possible. int64_t Value; if (Res->EvaluateAsAbsolute(Value)) @@ -610,7 +689,7 @@ default: return 0; // not a binop. - // Lowest Precedence: &&, || + // Lowest Precedence: &&, ||, @ case AsmToken::AmpAmp: Kind = MCBinaryExpr::LAnd; return 1; Added: llvm/trunk/test/MC/AsmParser/expr_symbol_modifiers.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/expr_symbol_modifiers.s?rev=114154&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/expr_symbol_modifiers.s (added) +++ llvm/trunk/test/MC/AsmParser/expr_symbol_modifiers.s Thu Sep 16 21:47:07 2010 @@ -0,0 +1,14 @@ +// RUN: not llvm-mc -triple x86_64-unknown-unknown %s > %t 2> %t.err +// RUN: FileCheck < %t %s +// RUN: FileCheck -check-prefix=CHECK-STDERR < %t.err %s + +// CHECK: .long 1 +.long 1 +// CHECK-STDERR: invalid modifier 'GOTPCREL' (no symbols present) +.long 10 + 4 at GOTPCREL +// CHECK: .long a at GOTPCREL+4 +.long a + 4 at GOTPCREL +// CHECK: .long a at GOTPCREL+b@GOTPCREL +.long (a + b)@GOTPCREL +// CHECK: .long (10+b at GOTPCREL)+4 +.long 10 + b + 4 at GOTPCREL From ofv at wanadoo.es Thu Sep 16 22:22:21 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 17 Sep 2010 03:22:21 -0000 Subject: [llvm-commits] [llvm] r114158 - /llvm/trunk/test/CMakeLists.txt Message-ID: <20100917032221.678822A6C12C@llvm.org> Author: ofv Date: Thu Sep 16 22:22:21 2010 New Revision: 114158 URL: http://llvm.org/viewvc/llvm-project?rev=114158&view=rev Log: tests/CMakeLists.txt: use `configure_file' instead of `sed'. The Windows users will appreciate this. Modified: llvm/trunk/test/CMakeLists.txt Modified: llvm/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=114158&r1=114157&r2=114158&view=diff ============================================================================== --- llvm/trunk/test/CMakeLists.txt (original) +++ llvm/trunk/test/CMakeLists.txt Thu Sep 16 22:22:21 2010 @@ -47,23 +47,25 @@ MAKE_DIRECTORY(${CMAKE_CURRENT_BINARY_DIR}/Unit) + set(LLVM_SOURCE_DIR ${LLVM_MAIN_SRC_DIR}) + set(LLVM_BINARY_DIR ${LLVM_BINARY_DIR}) + set(LLVM_TOOLS_DIR "${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}") + set(LLVMGCCDIR "") + set(PYTHON_EXECUTABLE ${PYTHON_EXECUTABLE}) + set(LLVM_BUILD_MODE ${CMAKE_CFG_INTDIR}) + set(ENABLE_SHARED ${LLVM_SHARED_LIBS_ENABLED}) + set(SHLIBPATH_VAR ${SHLIBPATH_VAR}) + + configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in + ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg + @ONLY) + configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in + ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg + @ONLY) + add_custom_target(check - COMMAND sed -e "s#\@LLVM_SOURCE_DIR\@#${LLVM_MAIN_SRC_DIR}#" - -e "s#\@LLVM_BINARY_DIR\@#${LLVM_BINARY_DIR}#" - -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}#" - -e "s#\@LLVMGCCDIR\@##" - -e "s#\@PYTHON_EXECUTABLE\@#${PYTHON_EXECUTABLE}#" - ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in > - ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg - COMMAND sed -e "s#\@LLVM_SOURCE_DIR\@#${LLVM_MAIN_SRC_DIR}#" - -e "s#\@LLVM_BINARY_DIR\@#${LLVM_BINARY_DIR}#" - -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}#" - -e "s#\@LLVMGCCDIR\@##" - -e "s#\@LLVM_BUILD_MODE\@#${CMAKE_CFG_INTDIR}#" - -e "s#\@ENABLE_SHARED\@#${LLVM_SHARED_LIBS_ENABLED}#" - -e "s#\@SHLIBPATH_VAR\@#${SHLIBPATH_VAR}#" - ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in > - ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg COMMAND ${PYTHON_EXECUTABLE} ${LLVM_SOURCE_DIR}/utils/lit/lit.py --param llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg From baldrick at free.fr Thu Sep 16 23:01:53 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 17 Sep 2010 06:01:53 +0200 Subject: [llvm-commits] [llvm] r114121 - in /llvm/trunk: include/llvm/Analysis/Passes.h include/llvm/LinkAllPasses.h lib/Analysis/MemDepPrinter.cpp In-Reply-To: <20100916220833.284482A6C12C@llvm.org> References: <20100916220833.284482A6C12C@llvm.org> Message-ID: <4C92E831.9040206@free.fr> Hi Dan, > Add a pass which prints out all the memdep dependencies. I guess you should mention it in Passes.html. Ciao, Duncan. From daniel at zuster.org Thu Sep 16 23:25:24 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 17 Sep 2010 04:25:24 -0000 Subject: [llvm-commits] [llvm] r114165 - /llvm/trunk/lib/System/SearchForAddressOfSpecialSymbol.cpp Message-ID: <20100917042524.509942A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 16 23:25:24 2010 New Revision: 114165 URL: http://llvm.org/viewvc/llvm-project?rev=114165&view=rev Log: System: Don't reexport ___eprintf when building with Clang; this symbol isn't used on Darwin anymore, and Clang might not always link with the library it is currently found in. Modified: llvm/trunk/lib/System/SearchForAddressOfSpecialSymbol.cpp Modified: llvm/trunk/lib/System/SearchForAddressOfSpecialSymbol.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/SearchForAddressOfSpecialSymbol.cpp?rev=114165&r1=114164&r2=114165&view=diff ============================================================================== --- llvm/trunk/lib/System/SearchForAddressOfSpecialSymbol.cpp (original) +++ llvm/trunk/lib/System/SearchForAddressOfSpecialSymbol.cpp Thu Sep 16 23:25:24 2010 @@ -32,7 +32,14 @@ EXPLICIT_SYMBOL(__ashrdi3); EXPLICIT_SYMBOL(__cmpdi2); EXPLICIT_SYMBOL(__divdi3); + + // Clang doesn't always link against libgcc.a, which is the only thing which + // defines ___eprintf in the modern world. Just don't attempt to export this + // symbol when building with Clang. +#ifndef __clang__ EXPLICIT_SYMBOL(__eprintf); +#endif + EXPLICIT_SYMBOL(__fixdfdi); EXPLICIT_SYMBOL(__fixsfdi); EXPLICIT_SYMBOL(__fixunsdfdi); From viridia at gmail.com Fri Sep 17 01:32:13 2010 From: viridia at gmail.com (Talin) Date: Thu, 16 Sep 2010 23:32:13 -0700 Subject: [llvm-commits] Patch to allow llvm.gcroot to work with non-pointer allocas. Message-ID: This patch modifies Verifier.cpp to allow the first argument to llvm.gcroot to be a "non-pointer" alloca. This allows you to have an alloca of, say, struct type which may contain pointers that need to be traced. Note that the first argument is still required to be an alloca, but is no longer required to be an alloca of a pointer. For safety, the code requires the metadata argument to llvm.gcroot to be a non-null constant if the first argument is anything but a pointer. The theory is that gcroot will need some kind of information about the structure of the item being traced in order to interpret it. Allocas which are pointers can point to tagged objects of some sort, so the metadata is optional in that case. I've currently written a bunch of code for my own compiler which relies on this patch. (I'm fairly far along on a non-shadow-stack gc, which creates static call frame descriptor maps that store all of the offsets of pointers within the call frame. This will make it possible to handle concurrent collection, which shadow-stack cannot do. The hardest part so far has been supporting union types, which may or may not be traced depending on what's in the union at the moment.) -- -- Talin -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/c89a8c71/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: gcroot.patch Type: text/x-patch Size: 1024 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100916/c89a8c71/attachment.bin From bigcheesegs at gmail.com Fri Sep 17 01:33:20 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Fri, 17 Sep 2010 06:33:20 -0000 Subject: [llvm-commits] [llvm] r114167 - /llvm/trunk/docs/GettingStartedVS.html Message-ID: <20100917063320.A46DB2A6C12C@llvm.org> Author: mspencer Date: Fri Sep 17 01:33:20 2010 New Revision: 114167 URL: http://llvm.org/viewvc/llvm-project?rev=114167&view=rev Log: docs: Update GettingStartedVS to reflect current state. Modified: llvm/trunk/docs/GettingStartedVS.html Modified: llvm/trunk/docs/GettingStartedVS.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStartedVS.html?rev=114167&r1=114166&r2=114167&view=diff ============================================================================== --- llvm/trunk/docs/GettingStartedVS.html (original) +++ llvm/trunk/docs/GettingStartedVS.html Fri Sep 17 01:33:20 2010 @@ -26,7 +26,7 @@
    -

    Written by: +

    Written by: Jeff Cohen

    @@ -40,23 +40,30 @@
    -

    The Visual Studio port has some limitations. It is suitable for - use if you are writing your own compiler front end or otherwise have a - need to dynamically generate machine code. The JIT and interpreter are - functional, but it is currently not possible to generate assembly code which - is then assembled into an executable. You can output object files - in COFF format, though. You can also indirectly create executables - by using the C backend.

    - -

    llvm-gcc is based on GCC, which cannot be bootstrapped - using VC++. There are llvm-gcc binaries based on MinGW - available on the - LLVM download - page. Eventually, Clang - will be able to produce executables on Windows.

    +

    Welcome to LLVM on Windows! This document only covers native Windows, not + mingw or cygwin. In order to get started, you first need to know some basic + information.

    + +

    There are many different projects that compose LLVM. The first is the LLVM + suite. This contains all of the tools, libraries, and header files needed to + use the low level virtual machine. It contains an assembler, disassembler, + bitcode analyzer and bitcode optimizer. It also contains a test suite that can + be used to test the LLVM tools.

    + +

    Another useful project on Windows is + clang. Clang is a C family + ([Objective]C/C++) compiler. Clang fully works on Windows, but does not + currently understand all of the Microsoft extensions to C and C++. Because of + this, clang cannot parse the C++ standard library included with Visual Studio, + nor parts of the Windows Platform SDK. However, most standard C programs do + compile. Clang can be used to emit bitcode, directly emit object files or + even linked executables using Visual Studio's link.exe

    -

    bugpoint does build, but does not work. The other tools - 'should' work, but have not been fully tested.

    +

    The LLVM test suite cannot be run on the Visual Studio port at this + time.

    + +

    Most of the tools build and work. bugpoint does build, but does + not work.

    Additional information about the LLVM directory structure and tool chain can be found on the main Getting Started @@ -85,7 +92,7 @@

    -

    Any system that can adequately run Visual Studio .NET 2005 SP1 is fine. +

    Any system that can adequately run Visual Studio .NET 2005 SP1 is fine. The LLVM source tree and object files, libraries and executables will consume approximately 3GB.

    @@ -97,16 +104,17 @@

    You will need Visual Studio .NET 2005 SP1 or higher. The VS2005 SP1 beta and the normal VS2005 still have bugs that are not completely - compatible. VS2003 would work except (at last check) it has a bug with - friend classes that you can work-around with some minor code rewriting - (and please submit a patch if you do). Earlier versions of Visual Studio - do not support the C++ standard well enough and will not work.

    - + compatible. Earlier versions of Visual Studio do not support the C++ standard + well enough and will not work.

    +

    You will also need the CMake build system since it generates the project files you will use to build with.

    -

    - Do not install the LLVM directory tree into a path containing spaces (e.g. +

    If you would like to run the LLVM tests you will need + Python. Versions 2.4-2.7 are known to + work.

    + +

    Do not install the LLVM directory tree into a path containing spaces (e.g. C:\Documents and Settings\...) as the configure step will fail.

    @@ -139,27 +147,22 @@
  • With anonymous Subversion access:
    1. cd where-you-want-llvm-to-live
      2. -
    2. svn co http://llvm.org/svn/llvm-project/llvm-top/trunk llvm-top -
      3. -
    3. make checkout MODULE=llvm +
    4. svn co http://llvm.org/svn/llvm-project/llvm/trunk llvm
    5. cd llvm
    • - +
  • Use CMake to generate up-to-date project files:
      -
    • Once CMake is installed then the most simple way is to just - start the CMake GUI, select the directory where you have LLVM - extracted to, and the default options should all be fine. One - option you may really want to change, regardless of anything - else, might be the CMAKE_INSTALL_PREFIX setting to select a - directory to INSTALL to once compiling is complete, although - installation is not mandatory for using LLVM. Another - important option is LLVM_TARGETS_TO_BUILD, which controls the - LLVM target architectures that are included on the build. If - you want to run the example described - below you must set that variable to "X86;CBackend".
      • +
    • Once CMake is installed then the simplest way is to just start the + CMake GUI, select the directory where you have LLVM extracted to, and the + default options should all be fine. One option you may really want to + change, regardless of anything else, might be the CMAKE_INSTALL_PREFIX + setting to select a directory to INSTALL to once compiling is complete, + although installation is not mandatory for using LLVM. Another important + option is LLVM_TARGETS_TO_BUILD, which controls the LLVM target + architectures that are included on the build.
    • See the LLVM CMake guide for detailed information about how to configure the LLVM build.
      • @@ -188,6 +191,28 @@ program will print the corresponding fibonacci value.
    • +
  • Test LLVM: +
      +
    • The LLVM tests can be run by cding to the llvm source directory + and running: + +
      +
      +% llvm-lit test
+
      +
      + +

      Note that quite a few of these test will fail.

      +
      • + +
    • A specific test or test directory can be run with:
      • + +
      +
      +% llvm-lit test/path/to/test
+
      +
      + @@ -216,7 +241,7 @@ 
      -% llvm-gcc -c hello.c -emit-llvm -o hello.bc
+% clang -c hello.c -emit-llvm -o hello.bc
      @@ -225,23 +250,27 @@ facilities that it required. You can execute this file directly using lli tool, compile it to native assembly with the llc, optimize or analyze it further with the opt tool, etc.

      - -

      Note: you will need the llvm-gcc binaries from the - LLVM - download page

      + +

      Alternatively you can directly output an executable with clang with: +

      + +
      +
      +% clang hello.c -o hello.exe
+
      +
      + +

      The -o hello.exe is required because clang currently outputs + a.out when neither -o nor -c are given.

    • Run the program using the just-in-time compiler:

      - + 
       % lli hello.bc
      -

      Note: this will only work for trivial C programs. Non-trivial programs - (and any C++ program) will have dependencies on the GCC runtime that - won't be satisfied by the Microsoft runtime libraries.

      • -

    • Use the llvm-dis utility to take a look at the LLVM assembly code:

      @@ -251,40 +280,27 @@
      • -

    • Compile the program to C using the LLC code generator:

      +

    • Compile the program to object code using the LLC code generator:

      -% llc -march=c hello.bc
+% llc -filetype=obj hello.bc
      - -

      Note: you need to add the C backend to the LLVM build, - which amounts to setting the CMake - variable LLVM_TARGETS_TO_BUILD to "X86;CBackend" when - you generate the VS solution files. See - the LLVM CMake guide for more - information about how to configure the LLVM - build.

      • - -

    • Compile to binary using Microsoft C:

      +

    • Link to binary using Microsoft link:

      -% cl hello.cbe.c
+% link hello.obj -defaultlib:libcmt
      -

      Note: this will only work for trivial C programs. Non-trivial programs - (and any C++ program) will have dependencies on the GCC runtime that won't - be satisfied by the Microsoft runtime libraries.

      • -

    • Execute the native code program:

      -% hello.cbe.exe
+% hello.exe
      • From baldrick at free.fr Fri Sep 17 02:01:59 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 17 Sep 2010 07:01:59 -0000 Subject: [llvm-commits] [zorg] r114168 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100917070159.832B32A6C12C@llvm.org> Author: baldrick Date: Fri Sep 17 02:01:59 2010 New Revision: 114168 URL: http://llvm.org/viewvc/llvm-project?rev=114168&view=rev Log: Add a useful llvm-gcc option when building a 32 bit compiler on a 64 bit machine. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114168&r1=114167&r2=114168&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Sep 17 02:01:59 2010 @@ -252,7 +252,7 @@ 'slavenames':["gcc11"], 'builddir':"llvm-gcc-i386-linux-selfhost", 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', - extra_configure_args=['--disable-multilib']), + extra_configure_args=['--disable-multilib','--enable-targets=all']), 'category' : 'llvm-gcc.exp' }, {'name' : "llvm-gcc-x86_64-darwin10-self-mingw32", From baldrick at free.fr Fri Sep 17 02:09:38 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 17 Sep 2010 07:09:38 -0000 Subject: [llvm-commits] [zorg] r114169 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100917070938.EB6A82A6C12C@llvm.org> Author: baldrick Date: Fri Sep 17 02:09:38 2010 New Revision: 114169 URL: http://llvm.org/viewvc/llvm-project?rev=114169&view=rev Log: Arrange for --32 to be passed to the assembler when targetting i386 on a 64 bit machine by passing a shell script that adds --32 to the assembler options to llvm-gcc as the assembler. The fact that this is not done automatically is a gcc bug (fixed in latest gcc). Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114169&r1=114168&r2=114169&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Sep 17 02:09:38 2010 @@ -252,7 +252,8 @@ 'slavenames':["gcc11"], 'builddir':"llvm-gcc-i386-linux-selfhost", 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', - extra_configure_args=['--disable-multilib','--enable-targets=all']), + extra_configure_args=['--disable-multilib', + '--enable-targets=all','--with-as=$HOME/bin32/as']), 'category' : 'llvm-gcc.exp' }, {'name' : "llvm-gcc-x86_64-darwin10-self-mingw32", From baldrick at free.fr Fri Sep 17 02:32:45 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 17 Sep 2010 09:32:45 +0200 Subject: [llvm-commits] Patch to allow llvm.gcroot to work with non-pointer allocas. In-Reply-To: References: Message-ID: <4C93199D.2090300@free.fr> Hi Talin, > This patch modifies Verifier.cpp to allow the first argument to llvm.gcroot to > be a "non-pointer" alloca. This allows you to have an alloca of, say, struct > type which may contain pointers that need to be traced. Note that the first > argument is still required to be an alloca, but is no longer required to be an > alloca of a pointer. is this really needed? In this situation, can't you just declare two allocas: your struct alloca, and a pointer alloca that contains the address of the struct alloca. You then pass the pointer alloca as the gc root. Ciao, Duncan. From baldrick at free.fr Fri Sep 17 02:34:50 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 17 Sep 2010 07:34:50 -0000 Subject: [llvm-commits] [zorg] r114170 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100917073450.C75DC2A6C12D@llvm.org> Author: baldrick Date: Fri Sep 17 02:34:50 2010 New Revision: 114170 URL: http://llvm.org/viewvc/llvm-project?rev=114170&view=rev Log: The $HOME variable was not being expanded - expand it by hand. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114170&r1=114169&r2=114170&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Sep 17 02:34:50 2010 @@ -253,7 +253,7 @@ 'builddir':"llvm-gcc-i386-linux-selfhost", 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', extra_configure_args=['--disable-multilib', - '--enable-targets=all','--with-as=$HOME/bin32/as']), + '--enable-targets=all','--with-as=/home/baldrick/bin32/as']), 'category' : 'llvm-gcc.exp' }, {'name' : "llvm-gcc-x86_64-darwin10-self-mingw32", From bigcheesegs at gmail.com Fri Sep 17 02:43:31 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Fri, 17 Sep 2010 03:43:31 -0400 Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll In-Reply-To: <20100917013806.562CB2A6C12C@llvm.org> References: <20100917013806.562CB2A6C12C@llvm.org> Message-ID: On Thu, Sep 16, 2010 at 9:38 PM, Dan Gohman wrote: > Author: djg > Date: Thu Sep 16 20:38:06 2010 > New Revision: 114148 > > URL: http://llvm.org/viewvc/llvm-project?rev=114148&view=rev > Log: > Fix the folding of floating-point math library calls, like sin(infinity), > so that it detects errors on platforms where libm doesn't set errno. > It's still subject to host libm details though. > > Added: > ? ?llvm/trunk/test/Transforms/InstCombine/fold-calls.ll > Modified: > ? ?llvm/trunk/lib/Analysis/ConstantFolding.cpp > > Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=114148&r1=114147&r2=114148&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) > +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Sep 16 20:38:06 2010 > @@ -32,6 +32,7 @@ > ?#include "llvm/Support/MathExtras.h" > ?#include > ?#include > +#include Windows doesn't have fenv.h. Please fix. - Michael Spencer > ?using namespace llvm; > > ?//===----------------------------------------------------------------------===// > @@ -1039,9 +1040,12 @@ > > ?static Constant *ConstantFoldFP(double (*NativeFP)(double), double V, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const Type *Ty) { > + ?feclearexcept(FE_ALL_EXCEPT); > ? errno = 0; > ? V = NativeFP(V); > - ?if (errno != 0) { > + ?if (errno != 0 || > + ? ? ?fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) { > + ? ?feclearexcept(FE_ALL_EXCEPT); > ? ? errno = 0; > ? ? return 0; > ? } > @@ -1056,9 +1060,12 @@ > > ?static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double), > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? double V, double W, const Type *Ty) { > + ?feclearexcept(FE_ALL_EXCEPT); > ? errno = 0; > ? V = NativeFP(V, W); > - ?if (errno != 0) { > + ?if (errno != 0 || > + ? ? ?fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) { > + ? ?feclearexcept(FE_ALL_EXCEPT); > ? ? errno = 0; > ? ? return 0; > ? } > > Added: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114148&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (added) > +++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Thu Sep 16 20:38:06 2010 > @@ -0,0 +1,19 @@ > +; RUN: opt -instcombine -S < %s | FileCheck %s > + > +; This shouldn't fold, because sin(inf) is invalid. > +; CHECK: @foo > +; CHECK: ? %t = call double @sin(double 0x7FF0000000000000) > +define double @foo() { > + ?%t = call double @sin(double 0x7FF0000000000000) > + ?ret double %t > +} > + > +; This should fold. > +; CHECK: @bar > +; CHECK: ? ret double 0x3FDA6026360C2F91 > +define double @bar() { > + ?%t = call double @sin(double 9.0) > + ?ret double %t > +} > + > +declare double @sin(double) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From Edmund.Grimley-Evans at arm.com Fri Sep 17 04:22:18 2010 From: Edmund.Grimley-Evans at arm.com (Edmund Grimley-Evans) Date: Fri, 17 Sep 2010 10:22:18 +0100 Subject: [llvm-commits] [PATCH] Comments in CodeGen/ValueTypes.td Message-ID: <680044E4997F5343A2C58032DDD099160705C4@ZIPPY.Emea.Arm.com> Fix two comments. Completely trivial, but the errors confuse me as I maintain my own local diff. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -------------- next part -------------- A non-text attachment was scrubbed... Name: trivial.patch Type: text/x-patch Size: 790 bytes Desc: trivial.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100917/e7655509/attachment.bin From geek4civic at gmail.com Fri Sep 17 04:56:43 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 17 Sep 2010 09:56:43 -0000 Subject: [llvm-commits] [llvm] r114173 - /llvm/trunk/lib/Target/Alpha/AlphaSchedule.td Message-ID: <20100917095643.F26922A6C12C@llvm.org> Author: chapuni Date: Fri Sep 17 04:56:43 2010 New Revision: 114173 URL: http://llvm.org/viewvc/llvm-project?rev=114173&view=rev Log: AlphaSchedule.td: 7bit-ize. Modified: llvm/trunk/lib/Target/Alpha/AlphaSchedule.td Modified: llvm/trunk/lib/Target/Alpha/AlphaSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSchedule.td?rev=114173&r1=114172&r2=114173&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSchedule.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSchedule.td Fri Sep 17 04:56:43 2010 @@ -50,7 +50,7 @@ def s_itof : InstrItinClass; def s_pseudo : InstrItinClass; -//Table 2?4 Instruction Class Latency in Cycles +//Table 2-4 Instruction Class Latency in Cycles //modified some def Alpha21264Itineraries : ProcessorItineraries< From geek4civic at gmail.com Fri Sep 17 06:14:19 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 17 Sep 2010 11:14:19 -0000 Subject: [llvm-commits] [llvm] r114175 - /llvm/trunk/lib/System/Win32/Program.inc Message-ID: <20100917111419.1DA9C2A6C12C@llvm.org> Author: chapuni Date: Fri Sep 17 06:14:18 2010 New Revision: 114175 URL: http://llvm.org/viewvc/llvm-project?rev=114175&view=rev Log: Move the declaration SetInformationJobObject() outside of namespace. It is also workaround for PR7927. Modified: llvm/trunk/lib/System/Win32/Program.inc Modified: llvm/trunk/lib/System/Win32/Program.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Program.inc?rev=114175&r1=114174&r2=114175&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Program.inc (original) +++ llvm/trunk/lib/System/Win32/Program.inc Fri Sep 17 06:14:18 2010 @@ -22,6 +22,15 @@ //=== and must not be UNIX code //===----------------------------------------------------------------------===// +#ifdef __MINGW32__ +// Ancient mingw32's w32api might not have this declaration. +extern "C" +BOOL WINAPI SetInformationJobObject(HANDLE hJob, + JOBOBJECTINFOCLASS JobObjectInfoClass, + LPVOID lpJobObjectInfo, + DWORD cbJobObjectInfoLength); +#endif + namespace { struct Win32ProcessInfo { HANDLE hProcess; @@ -123,15 +132,6 @@ return h; } -#ifdef __MINGW32__ - // Due to unknown reason, mingw32's w32api doesn't have this declaration. - extern "C" - BOOL WINAPI SetInformationJobObject(HANDLE hJob, - JOBOBJECTINFOCLASS JobObjectInfoClass, - LPVOID lpJobObjectInfo, - DWORD cbJobObjectInfoLength); -#endif - /// ArgNeedsQuotes - Check whether argument needs to be quoted when calling /// CreateProcess. static bool ArgNeedsQuotes(const char *Str) { From ofv at wanadoo.es Fri Sep 17 06:33:30 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Fri, 17 Sep 2010 13:33:30 +0200 Subject: [llvm-commits] [llvm] r114167 - /llvm/trunk/docs/GettingStartedVS.html References: <20100917063320.A46DB2A6C12C@llvm.org> Message-ID: <87eicsob91.fsf@telefonica.net> Hello Michael. Thanks for updating the information about testing and replacing llvm-gcc with clang. Some comments follow. "Michael J. Spencer" writes: [snip] > +

      Welcome to LLVM on Windows! This document only covers native Windows, not > + mingw or cygwin. MinGW is "native" by any definition of the word. > [+] In order to get started, you first need to know some basic > + information.

      This is not in line with the "read the documentation twice and then do it again" advice of GettingStarted.html. This document is not for learning what LLVM is, but for putting it to work. [snip] > +

      Another useful project on Windows is > + clang. Clang is a C family > + ([Objective]C/C++) compiler. Clang fully works on Windows, but does not > + currently understand all of the Microsoft extensions to C and C++. Because of > + this, clang cannot parse the C++ standard library included with Visual Studio, > + nor parts of the Windows Platform SDK. A C++ compiler that can't compile programs that use the SC++L or the platform SDK hardly deserves the "fully works" tag, IMO. [snip] > +

      The LLVM test suite cannot be run on the Visual Studio port at this > + time.

      Apparently, you contradict yourself a few lines below by giving instructions on how to run the tests. You should mention that the LLVM test suite is not the same as the tests included with LLVM and Clang: [snip] > +

      If you would like to run the LLVM tests you will need > + Python. Versions 2.4-2.7 are known to > + work.

      [snip] > +
    • Test LLVM: > +
        > +
      • The LLVM tests can be run by cding to the llvm source directory > + and running: [snip] From ofv at wanadoo.es Fri Sep 17 06:52:18 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Fri, 17 Sep 2010 13:52:18 +0200 Subject: [llvm-commits] [llvm] r114167 - /llvm/trunk/docs/GettingStartedVS.html References: <20100917063320.A46DB2A6C12C@llvm.org> <87eicsob91.fsf@telefonica.net> Message-ID: <878w30oadp.fsf@telefonica.net> ?scar Fuentes writes: [snip] >> [+] In order to get started, you first need to know some basic >> + information.

        > > This is not in line with the "read the documentation twice and then do > it again" advice of GettingStarted.html. This document is not for > learning what LLVM is, but for putting it to work. Scratch this. Just noticed that GettingStarted.html does the same introduction. From viridia at gmail.com Fri Sep 17 10:07:38 2010 From: viridia at gmail.com (Talin) Date: Fri, 17 Sep 2010 15:07:38 +0000 (UTC) Subject: [llvm-commits] Patch to allow llvm.gcroot to work with non-pointer allocas. References: <4C93199D.2090300@free.fr> Message-ID: Duncan Sands writes: > is this really needed? In this situation, can't you just declare two allocas: > your struct alloca, and a pointer alloca that contains the address of the struct > alloca. You then pass the pointer alloca as the gc root. Yes, that has been suggested before. It's clumsy and inefficient IMHO. -- Talin From daniel at zuster.org Fri Sep 17 10:21:51 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 17 Sep 2010 15:21:51 -0000 Subject: [llvm-commits] [llvm] r114176 - in /llvm/trunk: lib/MC/MachObjectWriter.cpp test/MC/MachO/reloc.s Message-ID: <20100917152151.23D662A6C12D@llvm.org> Author: ddunbar Date: Fri Sep 17 10:21:50 2010 New Revision: 114176 URL: http://llvm.org/viewvc/llvm-project?rev=114176&view=rev Log: MC/Mach-O/i386: Fix a crash in relocation handling. Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp llvm/trunk/test/MC/MachO/reloc.s Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=114176&r1=114175&r2=114176&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Fri Sep 17 10:21:50 2010 @@ -797,7 +797,8 @@ unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); // If this is a 32-bit TLVP reloc it's handled a bit differently. - if (Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) { + if (Target.getSymA() && + Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) { RecordTLVPRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue); return; } Modified: llvm/trunk/test/MC/MachO/reloc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/reloc.s?rev=114176&r1=114175&r2=114176&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/reloc.s (original) +++ llvm/trunk/test/MC/MachO/reloc.s Fri Sep 17 10:21:50 2010 @@ -37,6 +37,7 @@ .text _f0: L1: + jmp 0xbabecafe jmp L0 jmp L1 ret @@ -64,9 +65,9 @@ // CHECK: ('size', 260) // CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('vm_addr', 0) -// CHECK: ('vm_size', 71) +// CHECK: ('vm_size', 76) // CHECK: ('file_offset', 392) -// CHECK: ('file_size', 71) +// CHECK: ('file_size', 76) // CHECK: ('maxprot', 7) // CHECK: ('initprot', 7) // CHECK: ('num_sections', 3) @@ -76,29 +77,32 @@ // CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('address', 0) -// CHECK: ('size', 8) +// CHECK: ('size', 13) // CHECK: ('offset', 392) // CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 464) -// CHECK: ('num_reloc', 1) +// CHECK: ('reloc_offset', 468) +// CHECK: ('num_reloc', 2) // CHECK: ('flags', 0x80000400) // CHECK: ('reserved1', 0) // CHECK: ('reserved2', 0) // CHECK: ), // CHECK: ('_relocations', [ // CHECK: # Relocation 0 -// CHECK: (('word-0', 0x1), +// CHECK: (('word-0', 0x6), // CHECK: ('word-1', 0x5000003)), +// CHECK: # Relocation 1 +// CHECK: (('word-0', 0x1), +// CHECK: ('word-1', 0x5000000)), // CHECK: ]) -// CHECK: ('_section_data', 'e93a0000 00ebf9c3') +// CHECK: ('_section_data', 'e9f9cabe bae93a00 0000ebf4 c3') // CHECK: # Section 1 // CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('address', 8) +// CHECK: ('address', 13) // CHECK: ('size', 51) -// CHECK: ('offset', 400) +// CHECK: ('offset', 405) // CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 472) +// CHECK: ('reloc_offset', 484) // CHECK: ('num_reloc', 11) // CHECK: ('flags', 0x0) // CHECK: ('reserved1', 0) @@ -113,22 +117,22 @@ // CHECK: ('word-1', 0xc000007)), // CHECK: # Relocation 2 // CHECK: (('word-0', 0x8000002a), -// CHECK: ('word-1', 0x18)), +// CHECK: ('word-1', 0x1d)), // CHECK: # Relocation 3 // CHECK: (('word-0', 0x90000028), -// CHECK: ('word-1', 0x18)), +// CHECK: ('word-1', 0x1d)), // CHECK: # Relocation 4 // CHECK: (('word-0', 0xa0000024), -// CHECK: ('word-1', 0x18)), +// CHECK: ('word-1', 0x1d)), // CHECK: # Relocation 5 // CHECK: (('word-0', 0xa0000020), -// CHECK: ('word-1', 0x18)), +// CHECK: ('word-1', 0x1d)), // CHECK: # Relocation 6 // CHECK: (('word-0', 0xa4000014), -// CHECK: ('word-1', 0x1c)), +// CHECK: ('word-1', 0x21)), // CHECK: # Relocation 7 // CHECK: (('word-0', 0xa1000000), -// CHECK: ('word-1', 0x24)), +// CHECK: ('word-1', 0x29)), // CHECK: # Relocation 8 // CHECK: (('word-0', 0x8), // CHECK: ('word-1', 0x4000002)), @@ -139,15 +143,15 @@ // CHECK: (('word-0', 0x0), // CHECK: ('word-1', 0xc000009)), // CHECK: ]) -// CHECK: ('_section_data', '00000000 04000000 10000000 00000000 00000000 ed000000 00000000 00000000 19000000 22000000 2c007100 00000004 000000') +// CHECK: ('_section_data', '00000000 04000000 15000000 00000000 00000000 ed000000 00000000 00000000 1e000000 27000000 31007600 00000004 000000') // CHECK: # Section 2 // CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') -// CHECK: ('address', 59) +// CHECK: ('address', 64) // CHECK: ('size', 12) -// CHECK: ('offset', 451) +// CHECK: ('offset', 456) // CHECK: ('alignment', 0) -// CHECK: ('reloc_offset', 560) +// CHECK: ('reloc_offset', 572) // CHECK: ('num_reloc', 4) // CHECK: ('flags', 0x0) // CHECK: ('reserved1', 0) @@ -162,20 +166,20 @@ // CHECK: ('word-1', 0x4000003)), // CHECK: # Relocation 2 // CHECK: (('word-0', 0xa4000000), -// CHECK: ('word-1', 0x18)), +// CHECK: ('word-1', 0x1d)), // CHECK: # Relocation 3 // CHECK: (('word-0', 0xa1000000), -// CHECK: ('word-1', 0x3b)), +// CHECK: ('word-1', 0x40)), // CHECK: ]) -// CHECK: ('_section_data', 'feffffff 3f000000 00000000') +// CHECK: ('_section_data', 'feffffff 44000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 // CHECK: (('command', 2) // CHECK: ('size', 24) -// CHECK: ('symoff', 592) +// CHECK: ('symoff', 604) // CHECK: ('nsyms', 10) -// CHECK: ('stroff', 712) +// CHECK: ('stroff', 724) // CHECK: ('strsize', 88) // CHECK: ('_string_data', '\x00undef\x00local_a_ext\x00.objc_class_name_A\x00_f1\x00local_a\x00local_a_elt\x00local_b\x00local_c\x00bar\x00_f0\x00\x00\x00') // CHECK: ('_symbols', [ @@ -184,7 +188,7 @@ // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 20) +// CHECK: ('n_value', 25) // CHECK: ('_string', 'local_a') // CHECK: ), // CHECK: # Symbol 1 @@ -192,7 +196,7 @@ // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 24) +// CHECK: ('n_value', 29) // CHECK: ('_string', 'local_a_elt') // CHECK: ), // CHECK: # Symbol 2 @@ -200,7 +204,7 @@ // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 28) +// CHECK: ('n_value', 33) // CHECK: ('_string', 'local_b') // CHECK: ), // CHECK: # Symbol 3 @@ -208,7 +212,7 @@ // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 36) +// CHECK: ('n_value', 41) // CHECK: ('_string', 'local_c') // CHECK: ), // CHECK: # Symbol 4 @@ -216,7 +220,7 @@ // CHECK: ('n_type', 0xe) // CHECK: ('n_sect', 3) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 59) +// CHECK: ('n_value', 64) // CHECK: ('_string', 'bar') // CHECK: ), // CHECK: # Symbol 5 @@ -240,7 +244,7 @@ // CHECK: ('n_type', 0xf) // CHECK: ('n_sect', 1) // CHECK: ('n_desc', 128) -// CHECK: ('n_value', 8) +// CHECK: ('n_value', 13) // CHECK: ('_string', '_f1') // CHECK: ), // CHECK: # Symbol 8 @@ -248,7 +252,7 @@ // CHECK: ('n_type', 0xf) // CHECK: ('n_sect', 2) // CHECK: ('n_desc', 0) -// CHECK: ('n_value', 16) +// CHECK: ('n_value', 21) // CHECK: ('_string', 'local_a_ext') // CHECK: ), // CHECK: # Symbol 9 From criswell at uiuc.edu Fri Sep 17 10:38:26 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 17 Sep 2010 15:38:26 -0000 Subject: [llvm-commits] [test-suite] r114177 - /test-suite/trunk/README.txt Message-ID: <20100917153826.36B292A6C12D@llvm.org> Author: criswell Date: Fri Sep 17 10:38:26 2010 New Revision: 114177 URL: http://llvm.org/viewvc/llvm-project?rev=114177&view=rev Log: Test commit. Modified: test-suite/trunk/README.txt Modified: test-suite/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/README.txt?rev=114177&r1=114176&r2=114177&view=diff ============================================================================== --- test-suite/trunk/README.txt (original) +++ test-suite/trunk/README.txt Fri Sep 17 10:38:26 2010 @@ -8,3 +8,4 @@ In the future, given 'make thorough' we can add trace instrumentation and diff the trace logs as well. + From espindola at google.com Fri Sep 17 10:40:44 2010 From: espindola at google.com (Rafael Espindola) Date: Fri, 17 Sep 2010 11:40:44 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: References: Message-ID: > The generic code is actually being used for both COFF and ELF with > signed types, but it hasn't been tested because I've only tried out > x86{,-64} so far (and thus this function isn't called). If someone > could send me a small bigendian ELF file I could add a test for it and > make sure everything works. Is it common to try to byteswap signed integers? If not, it is probably a bit safer to just not support it. Things like int32_t foo; int64_t bar = SwapByteOrder(foo); can be a bit surprising. The user might have intended to sign extend foo first, but that is not what is going to happen. I compiled gas with at target of ppc64-linux-gnu and passed it an empty .s. The produced .o is attached. > Thanks for the review! > > - Michael Spencer Cheers, -- Rafael ?vila de Esp?ndola From criswell at uiuc.edu Fri Sep 17 10:42:02 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 17 Sep 2010 15:42:02 -0000 Subject: [llvm-commits] [test-suite] r114178 - /test-suite/trunk/README.txt Message-ID: <20100917154202.72FD92A6C12C@llvm.org> Author: criswell Date: Fri Sep 17 10:42:02 2010 New Revision: 114178 URL: http://llvm.org/viewvc/llvm-project?rev=114178&view=rev Log: Test commit. Modified: test-suite/trunk/README.txt Modified: test-suite/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/README.txt?rev=114178&r1=114177&r2=114178&view=diff ============================================================================== --- test-suite/trunk/README.txt (original) +++ test-suite/trunk/README.txt Fri Sep 17 10:42:02 2010 @@ -8,4 +8,3 @@ In the future, given 'make thorough' we can add trace instrumentation and diff the trace logs as well. - From espindola at google.com Fri Sep 17 10:45:23 2010 From: espindola at google.com (Rafael Espindola) Date: Fri, 17 Sep 2010 11:45:23 -0400 Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move implementation from Support/MathExtras.h. In-Reply-To: References: Message-ID: > I compiled gas with at target of ppc64-linux-gnu and passed it an > empty .s. The produced .o is attached. Now it is. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: test.o Type: application/x-object Size: 657 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100917/cf0d87fb/attachment.bin From criswell at uiuc.edu Fri Sep 17 10:45:20 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 17 Sep 2010 15:45:20 -0000 Subject: [llvm-commits] [test-suite] r114179 - /test-suite/trunk/README.txt Message-ID: <20100917154520.D01482A6C12C@llvm.org> Author: criswell Date: Fri Sep 17 10:45:20 2010 New Revision: 114179 URL: http://llvm.org/viewvc/llvm-project?rev=114179&view=rev Log: Test commit. Modified: test-suite/trunk/README.txt Modified: test-suite/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/README.txt?rev=114179&r1=114178&r2=114179&view=diff ============================================================================== --- test-suite/trunk/README.txt (original) +++ test-suite/trunk/README.txt Fri Sep 17 10:45:20 2010 @@ -8,3 +8,4 @@ In the future, given 'make thorough' we can add trace instrumentation and diff the trace logs as well. + From criswell at uiuc.edu Fri Sep 17 10:46:28 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 17 Sep 2010 15:46:28 -0000 Subject: [llvm-commits] [test-suite] r114180 - /test-suite/trunk/README.txt Message-ID: <20100917154628.5B8342A6C12C@llvm.org> Author: criswell Date: Fri Sep 17 10:46:28 2010 New Revision: 114180 URL: http://llvm.org/viewvc/llvm-project?rev=114180&view=rev Log: Test commit. Modified: test-suite/trunk/README.txt Modified: test-suite/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/README.txt?rev=114180&r1=114179&r2=114180&view=diff ============================================================================== --- test-suite/trunk/README.txt (original) +++ test-suite/trunk/README.txt Fri Sep 17 10:46:28 2010 @@ -8,4 +8,3 @@ In the future, given 'make thorough' we can add trace instrumentation and diff the trace logs as well. - From renato.golin at arm.com Fri Sep 17 10:48:58 2010 From: renato.golin at arm.com (Renato Golin) Date: Fri, 17 Sep 2010 16:48:58 +0100 Subject: [llvm-commits] Support for ARM Run-Time ABI Message-ID: Rationale: When choosing EABI variant for ARM targets, LLVM should use functions as defined by the RTABI document [1] to be compatible with other compilers that follow the same standard, including armcc and CodeSourcery's GCC. This patch includes some of the specifications that get automatically selected when the Target Triple is chosen to conform to the EABI ("arm/thumb*-eabi-*"). Comments are provided, indicating the specific section of the document it conforms to. Contents: This patch contains three changes: 1. Floating-Point helpers: LLVM selects EABI helpers instead of the default GNU ones, also compatible with CodeSourcery's GCC. 2. Remainder helper: LLVM lowers the remainder operation by selecting the helper function and reading the remainder from the appropriate register. 3. Memset: EABI memset has a different order of parameters, so we need to do custom lowering to move them around. Authors: Renato Golin & Evzen Muller (ARM Ltd.) [1] http://infocenter.arm.com/help/topic/com.arm.doc.ihi0043c/IHI0043C_rtabi.pdf -------------------------------------------------------------------------------- PATCH Index: lib/Target/ARM/ARMISelLowering.h =================================================================== --- lib/Target/ARM/ARMISelLowering.h (.../import/current) (revision 160856) +++ lib/Target/ARM/ARMISelLowering.h (.../trunk) (revision 160856) @@ -351,6 +351,8 @@ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; + // Lowers using REM helpers, see RTABI section 4.2/4.3 + SDValue LowerREM(SDNode *N, SelectionDAG &DAG, bool isSigned) const; SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCallResult(SDValue Chain, SDValue InFlag, Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp (.../import/current) (revision 160856) +++ lib/Target/ARM/ARMISelLowering.cpp (.../trunk) (revision 160856) @@ -26,6 +26,7 @@ #include "ARMTargetObjectFile.h" #include "llvm/CallingConv.h" #include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/GlobalValue.h" #include "llvm/Instruction.h" @@ -252,7 +253,117 @@ setLibcallCallingConv(static_cast(i), CallingConv::ARM_AAPCS); } + + // generate calls to runtime FP helpers, see RTABI section 4.1 + // Single-precision floating-point arithmetic. + setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); + setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); + setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); + setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); + + // Single-precision comparisons. + setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); + setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); + setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); + setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); + setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); + setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); + setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); + setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); + + // Condition used to check result + setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); + setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); + setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); + + // Double-precision floating-point arithmetic. + setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); + setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); + setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); + setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); + + // Double-precision comparisons. + setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); + setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); + setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); + setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); + setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); + setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); + setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); + setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); + + // Condition used to check result + setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); + setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); + setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); + setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); + setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); + setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); + setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); + setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); + + // Conversions between floating types. + setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); + setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); + + // Floating-point to integer conversions. + setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); + setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); + setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); + setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); + setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); + setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); + setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); + setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); + + // Integer to floating-point conversions. + setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); + setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); + setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); + setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); + setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); + setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); + setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); + setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); + + // Memory operations + setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); + setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); + setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); + + // Integer division + setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); + setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); + setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); + setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); + + setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); + setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); + setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); + setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); + + // Lowers using REM helpers, see RTABI section 4.2/4.3 + // Use custom actions for srem/urem + setOperationAction(ISD::SREM, MVT::i8, Custom); + setOperationAction(ISD::SREM, MVT::i16, Custom); + setOperationAction(ISD::SREM, MVT::i32, Custom); + setOperationAction(ISD::SREM, MVT::i64, Custom); + + setOperationAction(ISD::UREM, MVT::i8, Custom); + setOperationAction(ISD::UREM, MVT::i16, Custom); + setOperationAction(ISD::UREM, MVT::i32, Custom); + setOperationAction(ISD::UREM, MVT::i64, Custom); } + else { + // These are expanded into libcalls. + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + } if (Subtarget->isThumb1Only()) addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); @@ -381,17 +492,6 @@ if (!Subtarget->hasV6Ops()) setOperationAction(ISD::BSWAP, MVT::i32, Expand); - // These are expanded into libcalls. - if (!Subtarget->hasDivide()) { - // v7M has a hardware divider - setOperationAction(ISD::SDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIV, MVT::i32, Expand); - } - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom); setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); @@ -526,6 +626,11 @@ } } + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + setOperationAction(ISD::SDIVREM, MVT::i32, Expand); + setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + // We have target-specific dag combine patterns for the following nodes: // ARMISD::VMOVRRD - No need to call setTargetDAGCombine setTargetDAGCombine(ISD::ADD); @@ -2775,6 +2880,47 @@ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } +// Lowers using REM helpers, see RTABI section 4.2/4.3 +SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG, bool isSigned) const { + ArgListTy Args; + ArgListEntry Entry; + EVT PtrVT = getPointerTy(); + SDValue Chain = DAG.getEntryNode(); + // Setup arguments + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { + EVT ArgVT = N->getOperand(i).getValueType(); + const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); + Entry.Node = N->getOperand(i); + Entry.Ty = ArgTy; + Entry.isSExt = isSigned; + Entry.isZExt = !isSigned; + Args.push_back(Entry); + } + // Build return type + std::vector RetTyParams; + bool is64bit = N->getValueSizeInBits(0) == 64; + const Type *RetTyElement = is64bit ? + (const Type *)Type::getInt64Ty(*DAG.getContext()) : + (const Type *)Type::getInt32Ty(*DAG.getContext()); + RetTyParams.push_back(RetTyElement); + RetTyParams.push_back(RetTyElement); + const Type *RetTy = (const Type *)StructType::get(*DAG.getContext(), RetTyParams); + // Get ABI function name + SDValue Callee = DAG.getExternalSymbol( + isSigned ? (is64bit ? "__aeabi_ldivmod" : "__aeabi_idivmod") : + (is64bit ? "__aeabi_uldivmod" : "__aeabi_uidivmod") , PtrVT); + // Lower call + std::pair CallResult = + LowerCallTo(Chain, RetTy, isSigned, !isSigned, false /*vararg*/, + /*isInreg=*/false, /*NumFixedArgs=*/0, CallingConv::ARM_AAPCS, + /*isTailCall*/false, /*isReturnValueUsed=*/true, + Callee, Args, DAG, N->getDebugLoc()); + // Return second result operand (first operand contains div value) + SDNode *ResNode = CallResult.first.getNode(); + assert(ResNode->getNumOperands() == 2 && "divmod should return two operands"); + return ResNode->getOperand(1); +} + static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { SDValue TmpOp0, TmpOp1; bool Invert = false; @@ -3686,6 +3832,8 @@ case ISD::SHL: case ISD::SRL: case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); + case ISD::SREM: return LowerREM(Op.getNode(), DAG, true); + case ISD::UREM: return LowerREM(Op.getNode(), DAG, false); case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); case ISD::SRL_PARTS: case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); @@ -3718,6 +3866,12 @@ case ISD::SRA: Res = LowerShift(N, DAG, Subtarget); break; + case ISD::UREM: + Res = LowerREM(N, DAG, false); + break; + case ISD::SREM: + Res = LowerREM(N, DAG, true); + break; } if (Res.getNode()) Results.push_back(Res); Index: lib/Target/ARM/ARMSelectionDAGInfo.h =================================================================== --- lib/Target/ARM/ARMSelectionDAGInfo.h (.../import/current) (revision 160856) +++ lib/Target/ARM/ARMSelectionDAGInfo.h (.../trunk) (revision 160856) @@ -37,6 +37,13 @@ uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff) const; + // Adjust parameters for memset, see RTABI section 4.3.4 + virtual + SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool isVolatile, + const Value *DstSV, uint64_t DstOff) const; }; } Index: lib/Target/ARM/ARMSelectionDAGInfo.cpp =================================================================== --- lib/Target/ARM/ARMSelectionDAGInfo.cpp (.../import/current) (revision 160856) +++ lib/Target/ARM/ARMSelectionDAGInfo.cpp (.../trunk) (revision 160856) @@ -13,6 +13,8 @@ #define DEBUG_TYPE "arm-selectiondag-info" #include "ARMTargetMachine.h" +#include "llvm/DerivedTypes.h" +#include "llvm/CodeGen/SelectionDAG.h" using namespace llvm; ARMSelectionDAGInfo::ARMSelectionDAGInfo(const TargetMachine &TM) @@ -132,3 +134,56 @@ } return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); } + +// Adjust parameters for memset, see RTABI section 4.3.4 +SDValue +ARMSelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, + SDValue Chain, SDValue Dst, + SDValue Src, SDValue Size, + unsigned Align, bool isVolatile, + const Value *DstSV, uint64_t DstOff) const +{ + // use default for non AAPCS subtargets + if (!Subtarget->isAAPCS_ABI()) { + return SDValue(); + } + + const ARMTargetLowering &TLI = + *static_cast(DAG.getTarget().getTargetLowering()); + + + // Emit __eabi_memset call + // ptr + const Type *IntPtrTy = + cast(TLI.getTargetData()->getIntPtrType(*DAG.getContext())); + TargetLowering::ArgListTy Args; + TargetLowering::ArgListEntry Entry; + Entry.Node = Dst; Entry.Ty = IntPtrTy; + Args.push_back(Entry); + // size + Entry.Node = Size; + Entry.Ty = IntPtrTy; + Entry.isSExt = false; + Args.push_back(Entry); + + // Extend or truncate the argument to be an i32 value for the call. + if (Src.getValueType().bitsGT(MVT::i32)) + Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); + else + Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); + + Entry.Node = Src; + Entry.Ty = Type::getInt32Ty(*DAG.getContext()); + Entry.isSExt = true; + Args.push_back(Entry); + + std::pair CallResult = + TLI.LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), + false, false, false, false, 0, + TLI.getLibcallCallingConv(RTLIB::MEMSET), false, + /*isReturnValueUsed=*/false, + DAG.getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET), + TLI.getPointerTy()), + Args, DAG, dl); + return CallResult.second; +} From criswell at uiuc.edu Fri Sep 17 10:50:57 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 17 Sep 2010 15:50:57 -0000 Subject: [llvm-commits] [test-suite] r114181 - /test-suite/trunk/MultiSource/Applications/Makefile Message-ID: <20100917155057.B8ECA2A6C12C@llvm.org> Author: criswell Date: Fri Sep 17 10:50:57 2010 New Revision: 114181 URL: http://llvm.org/viewvc/llvm-project?rev=114181&view=rev Log: Added missing slash. Modified: test-suite/trunk/MultiSource/Applications/Makefile Modified: test-suite/trunk/MultiSource/Applications/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/Makefile?rev=114181&r1=114180&r2=114181&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Applications/Makefile (original) +++ test-suite/trunk/MultiSource/Applications/Makefile Fri Sep 17 10:50:57 2010 @@ -1,4 +1,4 @@ -# MultiSource/Applications Makefile: Build all subdirectories automatically +# MultiSource/Applications/Makefile: Build all subdirectories automatically LEVEL = ../.. From anton at korobeynikov.info Fri Sep 17 10:52:32 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Fri, 17 Sep 2010 19:52:32 +0400 Subject: [llvm-commits] Support for ARM Run-Time ABI In-Reply-To: References: Message-ID: Hello Renato, > Contents: This patch contains three changes: Could you please attach the file to the message? Please check http://llvm.org/docs/DeveloperPolicy.html#patches for more information -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From renato.golin at arm.com Fri Sep 17 10:55:52 2010 From: renato.golin at arm.com (Renato Golin) Date: Fri, 17 Sep 2010 16:55:52 +0100 Subject: [llvm-commits] Support for ARM Run-Time ABI Message-ID: Patch: Attached Rationale: When choosing EABI variant for ARM targets, LLVM should use functions as defined by the RTABI document [1] to be compatible with other compilers that follow the same standard, including armcc and CodeSourcery's GCC. This patch includes some of the specifications that get automatically selected when the Target Triple is chosen to conform to the EABI ("arm/thumb*-eabi-*"). Comments are provided, indicating the specific section of the document it conforms to. Contents: This patch contains three changes: 1. Floating-Point helpers: LLVM selects EABI helpers instead of the default GNU ones, also compatible with CodeSourcery's GCC. 2. Remainder helper: LLVM lowers the remainder operation by selecting the helper function and reading the remainder from the appropriate register. 3. Memset: EABI memset has a different order of parameters, so we need to do custom lowering to move them around. Authors: Renato Golin & Evzen Muller (ARM Ltd.) [1] http://infocenter.arm.com/help/topic/com.arm.doc.ihi0043c/IHI0043C_rtabi.pdf -- cheers, --renato -------------- next part -------------- A non-text attachment was scrubbed... Name: eabi.patch Type: text/x-patch Size: 13937 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100917/ebb848cd/attachment.bin From anton at korobeynikov.info Fri Sep 17 10:59:07 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Fri, 17 Sep 2010 19:59:07 +0400 Subject: [llvm-commits] Support for ARM Run-Time ABI In-Reply-To: References: Message-ID: Hello, Renato > + ? ?setOperationAction(ISD::UREM, MVT::i32, Custom); > + ? ?setOperationAction(ISD::UREM, MVT::i64, Custom); > ? } > + ?else { Please be consistent with the code style. > - ?// These are expanded into libcalls. > - ?if (!Subtarget->hasDivide()) { You dropped this check. At least this will affect non-EABI targets. > + ?const Type *RetTyElement = is64bit ? > + ? ?(const Type *)Type::getInt64Ty(*DAG.getContext()) : > + ? ?(const Type *)Type::getInt32Ty(*DAG.getContext()); These casts are not needed here. > + ?RetTyParams.push_back(RetTyElement); > + ?RetTyParams.push_back(RetTyElement); > + ?const Type *RetTy = (const Type > *)StructType::get(*DAG.getContext(), RetTyParams); Ditto > + ?case ISD::SREM: ? ? ? ? ?return LowerREM(Op.getNode(), DAG, true); > + ?case ISD::UREM: ? ? ? ? ?return LowerREM(Op.getNode(), DAG, false); What's about non-EABI targets? You're expanding stuff without checking for them. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From grosbach at apple.com Fri Sep 17 11:25:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 16:25:53 -0000 Subject: [llvm-commits] [llvm] r114183 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20100917162553.24C552A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 11:25:52 2010 New Revision: 114183 URL: http://llvm.org/viewvc/llvm-project?rev=114183&view=rev Log: expand PICLDR MC lowering to handle other PICLDR and PICSTR versions. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114183&r1=114182&r2=114183&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 17 11:25:52 2010 @@ -1351,10 +1351,17 @@ OutStreamer.EmitInstruction(AddInst); return; } - case ARM::PICLDR: { + case ARM::PICSTR: + case ARM::PICSTRB: + case ARM::PICSTRH: + case ARM::PICLDR: + case ARM::PICLDRB: + case ARM::PICLDRH: + case ARM::PICLDRSB: + case ARM::PICLDRSH: { // This is a pseudo op for a label + instruction sequence, which looks like: // LPC0: - // ldr r0, [pc, r0] + // OP r0, [pc, r0] // The LCP0 label is referenced by a constant pool entry in order to get // a PC-relative address at the ldr instruction. @@ -1367,16 +1374,29 @@ OutStreamer.EmitLabel(Label); // Form and emit the load - MCInst LdrInst; - LdrInst.setOpcode(ARM::LDR); - LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - LdrInst.addOperand(MCOperand::CreateReg(ARM::PC)); - LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); - LdrInst.addOperand(MCOperand::CreateImm(0)); + unsigned Opcode; + switch (MI->getOpcode()) { + default: + llvm_unreachable("Unexpected opcode!"); + case ARM::PICSTR: Opcode = ARM::STR; break; + case ARM::PICSTRB: Opcode = ARM::STRB; break; + case ARM::PICSTRH: Opcode = ARM::STRH; break; + case ARM::PICLDR: Opcode = ARM::LDR; break; + case ARM::PICLDRB: Opcode = ARM::LDRB; break; + case ARM::PICLDRH: Opcode = ARM::LDRH; break; + case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; + case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; + } + MCInst LdStInst; + LdStInst.setOpcode(Opcode); + LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); + LdStInst.addOperand(MCOperand::CreateReg(ARM::PC)); + LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); + LdStInst.addOperand(MCOperand::CreateImm(0)); // Add predicate operands. - LdrInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); - LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); - OutStreamer.EmitInstruction(LdrInst); + LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); + LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); + OutStreamer.EmitInstruction(LdStInst); return; } From daniel at zuster.org Fri Sep 17 11:34:24 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 17 Sep 2010 16:34:24 -0000 Subject: [llvm-commits] [llvm] r114184 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20100917163424.B25A82A6C12C@llvm.org> Author: ddunbar Date: Fri Sep 17 11:34:24 2010 New Revision: 114184 URL: http://llvm.org/viewvc/llvm-project?rev=114184&view=rev Log: Fix an MSVC warning. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114184&r1=114183&r2=114184&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Fri Sep 17 11:34:24 2010 @@ -616,6 +616,9 @@ return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); } } + + assert(0 && "Invalid expression kind!"); + return 0; } /// ParseExpression - Parse an expression and return it. From bob.wilson at apple.com Fri Sep 17 11:58:14 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 17 Sep 2010 09:58:14 -0700 Subject: [llvm-commits] some thoughts on lowering for calling conventions In-Reply-To: References: <20100911173742.2316C2A6C12C@llvm.org> Message-ID: On Sep 14, 2010, at 6:13 PM, Rafael Esp?ndola wrote: > On 14 September 2010 12:49, Bob Wilson wrote: >> This patch and an unrelated comment from Eric got me thinking some more about llvm's handling of calling conventions. I'm not very happy with our current approach. The specific issue I'm thinking about now is that we lower either too early or too late. > > Nice to have you on board! This has been one of by pet peeves for some time ... It (obviously) bothers me, too, but I hesitate to say that I'm "on board". After reflecting on this for a few days, my current thought is that calling convention issues should be handled later in the compiler. It is generally a good thing for the higher-level IR to be as simple and uncluttered as possible. I'd like to move away from having frontends generate code with: * Pad arguments * Aggregates split into scalars * Large scalars (e.g., f64) split into smaller scalars These are unnecessary complications for interprocedural passes and they make the IR cluttered and harder to deal with in general. In light of that, I'm less and less enthusiastic about your recent patch that splits up 64-bit arguments for AAPCS. Can you provide some more information about the motivation? Do you have any data to show whether it makes a difference? I can imagine scenarios where it might actually be harmful (e.g., if the additional extends and shifts are not removed after inlining a function). Some more comments below. > >> Lowering in the front-end should be minimized. It's too early. Interprocedural analyses and optimizations will suffer. (E.g., when an f64 argument is lowered to a pair of i32 values, it's hard for an analysis to track how that argument is used.) Since we currently support 2 front-ends, it also means that we need to do the front-end lowering in 2 places and keep both of them up to date. The front-end has to do some lowering in cases where the back-end doesn't have the language-specific information to do the job, but otherwise, I'd like to see the front-end avoid lowering for calling conventions. >> >> Aside from the front-ends, the rest of our calling convention support is handled with selection DAGs. That is too late. We'd really like the optimizer to see all the code for splitting up and recombining arguments. The DAG combiner and machine instruction optimizations clean up some of expanded code, but it's not ideal. I assume that is the motivation for Rafael's patch here. Eric is working on fast isel for ARM, and he mentioned to me recently that since fast isel doesn't build selection DAGs, it has to duplicate all the support for lowering calling conventions. > > I agree with this in general. Since these were the only two places I > could see the lowering being done, it looked better to have it done in the FE. > > The current implementation has some really annoying problems: > > *) Has to be reimplemented for fast isel or any other instruction > selection solution we want to create. Yes, this is a nuisance. I'd still like to see a calling convention lowering pass that could be shared for fast-isel and selection DAGs, but that would be tough because we currently have no way to represent some of the necessary constructs (e.g., physical machine registers) in llvm IR. > > *) Less things are explicit in the IL, so more arch specific knowledge > is needed in any pass that wants to take advantage of it. This cuts both ways. If you expose the low-level details too early, it will make higher-level analyses more difficult. Making _everything_ explicit in the front-end is not good. The argument splitting you've done is closely related to type legalization. Since we're currently doing type legalization on selection DAGs, we have pretty good support for optimizing (e.g., in the DAG combiner) the kind of code that results from splitting up 64-bit values. If you're seeing cases where you get better code by splitting the arguments in the front-end, that suggests there may be weaknesses in the DAG optimization that we should investigate. If you have examples of that, I'd like to take a look at them. > > *) I think the IL has multiple ways to represent the "same" > function. Two examples: > > *) By extending the use of pad arguments it is probably possible > to remove the alignment of byval attributes. > > *) By having the FE lower floating point argument to integers when > the ABI mandates that FP values be passed on integer registers we > might be able to drop most of the extra logic for handing the aapcs_vfp > calling convention. I really dislike both of these ideas. Sorry. They might simplify some things, but they cause other problems. > > *) Doing it all in the DAG produces code that is hard to read. Things > are a *lot* better these days, but moving the of C specific > knowledge out would help. I don't think I understand this point. What is it that is hard to read? > > *) There is a mismatch on what the IL means and what it needs. For example, > on x86-64 clang will compile > > --------------------------------- > struct foo { > long a; > long b; > char c; > }; > void f(struct foo x); > void g(void) { > struct foo y = {1, 2, 3}; > f(y); > } > ---------------------------------- > > into > > ----------------------------------------- > %struct.foo = type { i64, i64, i8 } > define void @g() nounwind optsize { > entry: > %agg.tmp = alloca %struct.foo, align 8 > %0 = bitcast %struct.foo* %agg.tmp to i192* > store i192 1020847100762815390427017310442723737601, i192* %0, align 8 > call void @f(%struct.foo* byval %agg.tmp) nounwind optsize > ret void > } > declare void @f(%struct.foo* byval) > ---------------------------------------- > > This is bad, because there is no requirement for the caller to have this > data in memory. If the struct was passed with FCA or similar solution then > the callee would suffer from not knowing that the data was already in memory > and something like > > void h(struct foo *x); > void f(struct foo x){ > h(&x); > } > > Would produce low quality code. Some solution where the call instruction > implicitly does the copy is probably what is needed. That way f, in the above > example can be declared to take a byval argument and knows it is in memory and > the IL for g can use a FCA and not have to allocate stack for it. OK. > > *) Function with variable number of arguments have another set of problems. > Hopefully a move to use va_arg will let us avoid some dead stores and maybe > even make it possible to inline some basic va_arg functions :-) Yes, I haven't looked closely at the va_arg features in llvm but from what I've seen, it definitely looks like a step in the right direction. > > Having two FE is an issue. If we get really serious about lowering in > the FE it might be possible to factor out some of the ABI bits from > clang into a mini library and use it in llvm-gcc. I don't at all want to go in that direction. The front-ends should only have to do the lowering that cannot be done later (due to language-specific information not available in the IR). > > It not very familiar with IPO to know how hard it is for them to > follow argument splitting, but cannot be as easy as without splitting. It's not. > >> Can we do better? >> >> If we had a target-specific lowering for calling conventions at the llvm IR level, instead of for selection DAGs, then we could run that lowering pass after any high-level interprocedural analyses and optimizations but before things like instcombine. That would avoid the need for front-ends to "pre-lower" things like this patch, avoid duplicating effort across front-ends and across selection DAGs and fast-isel, preserve information for high-level passes, and hopefully give us better optimization of the code resulting from lowering. >> >> Thoughts? (I fully expect there to be many obstacles to such a change, but I'm curious to hear if there's any consensus about the right solution for the long term. I'm not necessarily advocating that we change anything right now.) > > I like it, with the only note that when doing something in the FE could > simplify the IL definition by removing the need for an attribute or a new > calling convention then we should probably do it there. I much prefer adding the attributes or other information in the IR to allow the calling convention lowering to be done later. This will be important as llvm gains more advanced interprocedural passes. From baldrick at free.fr Fri Sep 17 12:05:27 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 17 Sep 2010 17:05:27 -0000 Subject: [llvm-commits] [llvm] r114186 - /llvm/trunk/utils/lit/lit/TestingConfig.py Message-ID: <20100917170527.2A3502A6C12C@llvm.org> Author: baldrick Date: Fri Sep 17 12:05:27 2010 New Revision: 114186 URL: http://llvm.org/viewvc/llvm-project?rev=114186&view=rev Log: Some of the tests build an executable with llvm-gcc. For this to work, llvm-gcc needs to find some libraries, which may require searching the directories given by LIBRARY_PATH on curiously configured systems. So pass on LIBRARY_PATH. Modified: llvm/trunk/utils/lit/lit/TestingConfig.py Modified: llvm/trunk/utils/lit/lit/TestingConfig.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestingConfig.py?rev=114186&r1=114185&r2=114186&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/TestingConfig.py (original) +++ llvm/trunk/utils/lit/lit/TestingConfig.py Fri Sep 17 12:05:27 2010 @@ -10,6 +10,7 @@ if config is None: # Set the environment based on the command line arguments. environment = { + 'LIBRARY_PATH' : os.environ.get('LIBRARY_PATH',''), 'LD_LIBRARY_PATH' : os.environ.get('LD_LIBRARY_PATH',''), 'PATH' : os.pathsep.join(litConfig.path + [os.environ.get('PATH','')]), From ggreif at gmail.com Fri Sep 17 12:52:00 2010 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 17 Sep 2010 17:52:00 -0000 Subject: [llvm-commits] [llvm] r114189 - /llvm/trunk/include/llvm/CodeGen/ValueTypes.td Message-ID: <20100917175200.BD9782A6C12C@llvm.org> Author: ggreif Date: Fri Sep 17 12:52:00 2010 New Revision: 114189 URL: http://llvm.org/viewvc/llvm-project?rev=114189&view=rev Log: fix comments; patch by Edmund Grimley-Evans\! Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.td?rev=114189&r1=114188&r2=114189&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.td (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.td Fri Sep 17 12:52:00 2010 @@ -46,8 +46,8 @@ def v8i32 : ValueType<256, 23>; // 8 x i32 vector value def v1i64 : ValueType<64 , 24>; // 1 x i64 vector value def v2i64 : ValueType<128, 25>; // 2 x i64 vector value -def v4i64 : ValueType<256, 26>; // 4 x f64 vector value -def v8i64 : ValueType<512, 27>; // 4 x f64 vector value +def v4i64 : ValueType<256, 26>; // 4 x i64 vector value +def v8i64 : ValueType<512, 27>; // 8 x i64 vector value def v2f32 : ValueType<64 , 28>; // 2 x f32 vector value def v4f32 : ValueType<128, 29>; // 4 x f32 vector value From sabre at nondot.org Fri Sep 17 13:02:29 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 17 Sep 2010 18:02:29 -0000 Subject: [llvm-commits] [llvm] r114190 - in /llvm/trunk: lib/Target/X86/X86InstrFormats.td lib/Target/X86/X86InstrInfo.h lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86MCCodeEmitter.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100917180229.4F6C62A6C12C@llvm.org> Author: lattner Date: Fri Sep 17 13:02:29 2010 New Revision: 114190 URL: http://llvm.org/viewvc/llvm-project?rev=114190&view=rev Log: fix rdar://8444631 - encoder crash on 'enter' What a weird instruction. Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=114190&r1=114189&r2=114190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Fri Sep 17 13:02:29 2010 @@ -39,7 +39,8 @@ def MRM_F0 : Format<40>; def MRM_F8 : Format<41>; def MRM_F9 : Format<42>; -def RawFrmImm16 : Format<43>; +def RawFrmImm8 : Format<43>; +def RawFrmImm16 : Format<44>; // ImmType - This specifies the immediate type used by an instruction. This is // part of the ad-hoc solution used to emit machine instruction encodings by our Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=114190&r1=114189&r2=114190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Sep 17 13:02:29 2010 @@ -311,12 +311,17 @@ MRM_F0 = 40, MRM_F8 = 41, MRM_F9 = 42, + + /// RawFrmImm8 - This is used for the ENTER instruction, which has two + /// immediates, the first of which is a 16-bit immediate (specified by + /// the imm encoding) and the second is a 8-bit fixed value. + RawFrmImm8 = 43, /// RawFrmImm16 - This is used for CALL FAR instructions, which have two /// immediates, the first of which is a 16 or 32-bit immediate (specified by /// the imm encoding) and the second is a 16-bit fixed value. In the AMD /// manual, this operand is described as pntr16:32 and pntr16:16 - RawFrmImm16 = 43, + RawFrmImm16 = 44, FormMask = 63, @@ -528,6 +533,7 @@ case X86II::AddRegFrm: case X86II::MRMDestReg: case X86II::MRMSrcReg: + case X86II::RawFrmImm8: case X86II::RawFrmImm16: return -1; case X86II::MRMDestMem: Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114190&r1=114189&r2=114190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Sep 17 13:02:29 2010 @@ -757,8 +757,8 @@ // Constructing a stack frame. -def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl), - "enter\t$len, $lvl", []>; +def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), + "enter\t$len, $lvl", []>; // Tail call stuff. Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=114190&r1=114189&r2=114190&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Fri Sep 17 13:02:29 2010 @@ -828,6 +828,13 @@ EmitByte(BaseOpcode, CurByte, OS); break; + case X86II::RawFrmImm8: + EmitByte(BaseOpcode, CurByte, OS); + EmitImmediate(MI.getOperand(CurOp++), + X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), + CurByte, OS, Fixups); + EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups); + break; case X86II::RawFrmImm16: EmitByte(BaseOpcode, CurByte, OS); EmitImmediate(MI.getOperand(CurOp++), Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114190&r1=114189&r2=114190&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Fri Sep 17 13:02:29 2010 @@ -293,3 +293,15 @@ lcall *0xbadeface ljmp *0xbadeface + +// rdar://8444631 +// CHECK: enter $31438, $0 +// CHECK: encoding: [0xc8,0xce,0x7a,0x00] +// CHECK: enter $31438, $1 +// CHECK: encoding: [0xc8,0xce,0x7a,0x01] +// CHECK: enter $31438, $127 +// CHECK: encoding: [0xc8,0xce,0x7a,0x7f] +enter $0x7ace,$0 +enter $0x7ace,$1 +enter $0x7ace,$0x7f + From grosbach at apple.com Fri Sep 17 13:25:25 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 18:25:25 -0000 Subject: [llvm-commits] [llvm] r114191 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMBaseInfo.h ARMBaseInstrInfo.h ARMMCInstLower.cpp ARMMCInstLower.h Message-ID: <20100917182525.4EF1D2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 13:25:25 2010 New Revision: 114191 URL: http://llvm.org/viewvc/llvm-project?rev=114191&view=rev Log: handle the upper16/lower16 target operand flags on symbol references for MC instruction lowering. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMBaseInfo.h llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp llvm/trunk/lib/Target/ARM/ARMMCInstLower.h Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114191&r1=114190&r2=114191&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 17 13:25:25 2010 @@ -1466,7 +1466,7 @@ V1 = MCOperand::CreateImm(ImmVal & 65535); V2 = MCOperand::CreateImm(ImmVal >> 16); } else if (MO.isGlobal()) { - MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO); + MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal()); const MCSymbolRefExpr *SymRef1 = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_LO16, OutContext); Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=114191&r1=114190&r2=114191&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Fri Sep 17 13:25:25 2010 @@ -167,6 +167,24 @@ } } +namespace ARMII { + /// Target Operand Flag enum. + enum TOF { + //===------------------------------------------------------------------===// + // ARM Specific MachineOperand flags. + + MO_NO_FLAG, + + /// MO_LO16 - On a symbol operand, this represents a relocation containing + /// lower 16 bit of the address. Used only via movw instruction. + MO_LO16, + + /// MO_HI16 - On a symbol operand, this represents a relocation containing + /// higher 16 bit of the address. Used only via movt instruction. + MO_HI16 + }; +} // end namespace ARMII + } // end namespace llvm; #endif Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=114191&r1=114190&r2=114191&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Sep 17 13:25:25 2010 @@ -181,22 +181,6 @@ I_BitShift = 25, CondShift = 28 }; - - /// Target Operand Flag enum. - enum TOF { - //===------------------------------------------------------------------===// - // ARM Specific MachineOperand flags. - - MO_NO_FLAG, - - /// MO_LO16 - On a symbol operand, this represents a relocation containing - /// lower 16 bit of the address. Used only via movw instruction. - MO_LO16, - - /// MO_HI16 - On a symbol operand, this represents a relocation containing - /// higher 16 bit of the address. Used only via movt instruction. - MO_HI16 - }; } class ARMBaseInstrInfo : public TargetInstrInfoImpl { Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=114191&r1=114190&r2=114191&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Fri Sep 17 13:25:25 2010 @@ -40,20 +40,39 @@ } #endif -MCSymbol *ARMMCInstLower:: -GetGlobalAddressSymbol(const MachineOperand &MO) const { +MCSymbol *ARMMCInstLower::GetGlobalAddressSymbol(const GlobalValue *GV) const { + return Printer.Mang->getSymbol(GV); +} + +const MCSymbolRefExpr *ARMMCInstLower:: +GetSymbolRef(const MachineOperand &MO) const { + assert(MO.isGlobal() && "Isn't a global address reference?"); // FIXME: HANDLE PLT references how?? + + const MCSymbolRefExpr *SymRef; + const MCSymbol *Symbol = GetGlobalAddressSymbol(MO.getGlobal()); + switch (MO.getTargetFlags()) { default: assert(0 && "Unknown target flag on GV operand"); - case 0: break; + case 0: + SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); + break; + case ARMII::MO_LO16: + SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_LO16, Ctx); + break; + case ARMII::MO_HI16: + SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_HI16, Ctx); + break; } - return Printer.Mang->getSymbol(MO.getGlobal()); + return SymRef; } MCSymbol *ARMMCInstLower:: GetExternalSymbolSymbol(const MachineOperand &MO) const { // FIXME: HANDLE PLT references how?? + // FIXME: This probably needs to be merged with the above SymbolRef stuff + // to handle :lower16: and :upper16: (?) switch (MO.getTargetFlags()) { default: assert(0 && "Unknown target flag on GV operand"); case 0: break; @@ -115,6 +134,17 @@ return MCOperand::CreateExpr(Expr); } +MCOperand ARMMCInstLower:: +LowerSymbolRefOperand(const MachineOperand &MO, + const MCSymbolRefExpr *Sym) const { + const MCExpr *Expr = Sym; + if (!MO.isJTI() && MO.getOffset()) + Expr = MCBinaryExpr::CreateAdd(Expr, + MCConstantExpr::Create(MO.getOffset(), Ctx), + Ctx); + return MCOperand::CreateExpr(Expr); +} + void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); @@ -141,7 +171,7 @@ MO.getMBB()->getSymbol(), Ctx)); break; case MachineOperand::MO_GlobalAddress: - MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO)); + MCOp = LowerSymbolRefOperand(MO, GetSymbolRef(MO)); break; case MachineOperand::MO_ExternalSymbol: MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO)); Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.h?rev=114191&r1=114190&r2=114191&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.h (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.h Fri Sep 17 13:25:25 2010 @@ -14,11 +14,13 @@ namespace llvm { class AsmPrinter; + class GlobalValue; class MCAsmInfo; class MCContext; class MCInst; class MCOperand; class MCSymbol; + class MCSymbolRefExpr; class MachineInstr; class MachineModuleInfoMachO; class MachineOperand; @@ -39,10 +41,13 @@ void Lower(const MachineInstr *MI, MCInst &OutMI) const; //MCSymbol *GetPICBaseSymbol() const; - MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const; + MCSymbol *GetGlobalAddressSymbol(const GlobalValue *GV) const; + const MCSymbolRefExpr *GetSymbolRef(const MachineOperand &MO) const; MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const; MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; + MCOperand LowerSymbolRefOperand(const MachineOperand &MO, + const MCSymbolRefExpr *Expr) const; MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; /* From grosbach at apple.com Fri Sep 17 13:46:17 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 18:46:17 -0000 Subject: [llvm-commits] [llvm] r114195 - in /llvm/trunk/lib/Target/ARM: ARM.h ARMMCCodeEmitter.cpp CMakeLists.txt Message-ID: <20100917184617.3C1AC2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 13:46:17 2010 New Revision: 114195 URL: http://llvm.org/viewvc/llvm-project?rev=114195&view=rev Log: Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim! Added: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARM.h llvm/trunk/lib/Target/ARM/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=114195&r1=114194&r2=114195&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Fri Sep 17 13:46:17 2010 @@ -26,6 +26,11 @@ class FunctionPass; class JITCodeEmitter; class formatted_raw_ostream; +class MCCodeEmitter; + +MCCodeEmitter *createARMMCCodeEmitter(const Target &, + TargetMachine &TM, + MCContext &Ctx); FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel); Added: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=114195&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (added) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Fri Sep 17 13:46:17 2010 @@ -0,0 +1,114 @@ +//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the ARMMCCodeEmitter class. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "arm-emitter" +#include "ARM.h" +#include "ARMInstrInfo.h" +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +namespace { +class ARMMCCodeEmitter : public MCCodeEmitter { + ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT + void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT + const TargetMachine &TM; + const TargetInstrInfo &TII; + MCContext &Ctx; + +public: + ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) + : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { + assert(0 && "ARMMCCodeEmitter::ARMMCCodeEmitter() not yet implemented."); + } + + ~ARMMCCodeEmitter() {} + + unsigned getNumFixupKinds() const { + assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); + } + + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + static MCFixupKindInfo rtn; + assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented."); + return rtn; + } + + static unsigned GetARMRegNum(const MCOperand &MO) { + // FIXME: getARMRegisterNumbering() is sufficient? + assert(0 && "ARMMCCodeEmitter::GetARMRegNum() not yet implemented."); + return 0; + } + + void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { + OS << (char)C; + ++CurByte; + } + + void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, + raw_ostream &OS) const { + // Output the constant in little endian byte order. + for (unsigned i = 0; i != Size; ++i) { + EmitByte(Val & 255, CurByte, OS); + Val >>= 8; + } + } + + void EmitImmediate(const MCOperand &Disp, + unsigned ImmSize, MCFixupKind FixupKind, + unsigned &CurByte, raw_ostream &OS, + SmallVectorImpl &Fixups, + int ImmOffset = 0) const; + + void EncodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups) const; + + void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, + const MCInst &MI, const TargetInstrDesc &Desc, + raw_ostream &OS) const; +}; + +} // end anonymous namespace + + +MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, + TargetMachine &TM, + MCContext &Ctx) { + return new ARMMCCodeEmitter(TM, Ctx); +} + +void ARMMCCodeEmitter:: +EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, + unsigned &CurByte, raw_ostream &OS, + SmallVectorImpl &Fixups, int ImmOffset) const { + assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented."); +} + +/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. +/// +/// MemOperand is the operand # of the start of a memory operand if present. If +/// Not present, it is -1. +void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, + int MemOperand, const MCInst &MI, + const TargetInstrDesc &Desc, + raw_ostream &OS) const { + assert(0 && "ARMMCCodeEmitter::EmitOpcodePrefix() not yet implemented."); +} + +void ARMMCCodeEmitter:: +EncodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups) const { + assert(0 && "ARMMCCodeEmitter::EncodeInstruction() not yet implemented."); +} Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=114195&r1=114194&r2=114195&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Fri Sep 17 13:46:17 2010 @@ -28,6 +28,7 @@ ARMISelLowering.cpp ARMInstrInfo.cpp ARMJITInfo.cpp + ARMMCCodeEmitter.cpp ARMLoadStoreOptimizer.cpp ARMMCAsmInfo.cpp ARMMCInstLower.cpp From grosbach at apple.com Fri Sep 17 13:48:18 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 11:48:18 -0700 Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH) In-Reply-To: References: <461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com> Message-ID: Applied, with a couple of very minor tweaks, as r114195. Thanks for the patch! -Jim On Sep 16, 2010, at 1:54 PM, Jason Kim wrote: > Hi Jim. > > Thanks for the feedback. Much appreciated. > Here's the revised patch. > > > On Thu, Sep 16, 2010 at 11:19 AM, Jim Grosbach wrote: >> Hi Jason, >> >> Glad to see this moving forward! This looks like a great start. A few minor comments on the patch itself inline below. Apologies in advance for being nitpicky. >> >> I don't recall whether we covered this bit specifically before, so at the risk of repeating myself... On a general note, it seems to me that a reasonable first milestone would be to have the target independent layer recognize that the ARM target wants to support object file emission. That is, have llc recognize "-filetype=obj". Right now it issues an error "target does not support generation of this file type!" (which is, of course, entirely correct for the moment). Once the classes are in place to do that, you'll start hitting all of the placeholder asserts(), which is exactly what you want, as you can interactively follow more easily the path the code wants to follow for simple cases and fill in the bits that as you go. >> > > Sounds like a plan! Up for that next. > >> >>> Index: lib/Target/ARM/ARM.h >>> =================================================================== >>> --- lib/Target/ARM/ARM.h (revision 114081) >>> +++ lib/Target/ARM/ARM.h (working copy) >>> @@ -26,7 +26,14 @@ >>> class FunctionPass; >>> class JITCodeEmitter; >>> class formatted_raw_ostream; >>> +class MCCodeEmitter; >>> >>> + >>> +MCCodeEmitter *createARM_MCCodeEmitter(const Target &, >> >> As a style thing, LLVM doesn't use underscores in symbol names. Just createARMMCCodeEmitter() is fine. (The underscore in the X86 equivalent is there as part of the target name, X86_32 vs. X86_64, and so is a bit misleading in this regard). >> >> >>> + TargetMachine &TM, >>> + MCContext &Ctx); >>> + >>> + >> >> Extra vertical whitespace here can be removed. >> >>> FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, >>> CodeGenOpt::Level OptLevel); >>> >>> @@ -41,6 +48,9 @@ >>> FunctionPass *createThumb2ITBlockPass(); >>> FunctionPass *createThumb2SizeReductionPass(); >>> >>> + >>> + >>> + >> >> Ditto. There's other instances below that can be similarly cleaned up. >> >>> extern Target TheARMTarget, TheThumbTarget; >>> >>> } // end namespace llvm; >>> Index: lib/Target/ARM/ARMMCCodeEmitter.cpp >>> =================================================================== >>> --- lib/Target/ARM/ARMMCCodeEmitter.cpp (revision 0) >>> +++ lib/Target/ARM/ARMMCCodeEmitter.cpp (revision 0) >>> @@ -0,0 +1,134 @@ >>> +//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// >>> +// >>> +// The LLVM Compiler Infrastructure >>> +// >>> +// This file is distributed under the University of Illinois Open Source >>> +// License. See LICENSE.TXT for details. >>> +// >>> +//===----------------------------------------------------------------------===// >>> +// >>> +// This file implements the ARMMCCodeEmitter class. >>> +// >>> +//===----------------------------------------------------------------------===// >>> + >>> +#define DEBUG_TYPE "ARM-emitter" >> >> Lower-case here, i.e., "arm-emitter" is more consistent with other options of this sort. >> >>> +#include "ARM.h" >>> +#include "ARMInstrInfo.h" >>> +//#include "ARMFixupKinds.h" >>> +#include "llvm/MC/MCCodeEmitter.h" >>> +#include "llvm/MC/MCExpr.h" >>> +#include "llvm/MC/MCInst.h" >>> +#include "llvm/Support/raw_ostream.h" >>> +using namespace llvm; >>> + >>> +namespace { >>> +class ARMMCCodeEmitter : public MCCodeEmitter { >>> + ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT >>> + void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT >>> + const TargetMachine &TM; >>> + const TargetInstrInfo &TII; >>> + MCContext &Ctx; >>> + bool Is64BitMode; >> >> Can just remove the extra hold-over bool from the x86 bit here. No 64-bit mode on ARM. :) >> >>> +public: >>> + ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) >>> + : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { >>> + } >>> + >>> + ~ARMMCCodeEmitter() {} >>> + >>> + unsigned getNumFixupKinds() const { >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >>> + } >>> + >>> + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { >>> + static MCFixupKindInfo rtn; >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >> >> Totally not a big deal, but I tend to phrase these sorts of things as simply " not yet implemented." Personal preference to simply state accurately the status of things rather than indicate anything about the future. Plus, then when I see the assert, I know specifically which function is being hit, rather than just the general name of the feature. >> >>> + return rtn; >>> + } >>> + >>> + static unsigned GetARMRegNum(const MCOperand &MO) { >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >>> + return 0; >>> + } >>> + >>> + void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { >>> + OS << (char)C; >>> + ++CurByte; >>> + } >>> + >>> + void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, >>> + raw_ostream &OS) const { >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >> >> Is this assert necessary? I don't know any reason why the implementation below wouldn't be sufficient. >> >>> + // Output the constant in little endian byte order. >>> + for (unsigned i = 0; i != Size; ++i) { >>> + EmitByte(Val & 255, CurByte, OS); >>> + Val >>= 8; >>> + } >>> + } >>> + >>> + void EmitImmediate(const MCOperand &Disp, >>> + unsigned ImmSize, MCFixupKind FixupKind, >>> + unsigned &CurByte, raw_ostream &OS, >>> + SmallVectorImpl &Fixups, >>> + int ImmOffset = 0) const; >>> + >>> + >>> + >>> + >>> + >>> + void EncodeInstruction(const MCInst &MI, raw_ostream &OS, >>> + SmallVectorImpl &Fixups) const; >>> + >>> + void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, >>> + const MCInst &MI, const TargetInstrDesc &Desc, >>> + raw_ostream &OS) const; >>> +}; >>> + >>> +} // end anonymous namespace >>> + >>> + >>> +MCCodeEmitter *llvm::createARM_MCCodeEmitter(const Target &, >>> + TargetMachine &TM, >>> + MCContext &Ctx) { >>> + return new ARMMCCodeEmitter(TM, Ctx); >>> +} >>> + >>> + >>> + >>> +/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate >>> +/// in an instruction with the specified TSFlags. >>> +static MCFixupKind getImmFixupKind(uint64_t TSFlags) { >>> + static MCFixupKind rtn; >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >>> + return rtn; >>> +} >>> + >>> + >>> +void ARMMCCodeEmitter:: >>> +EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, >>> + unsigned &CurByte, raw_ostream &OS, >>> + SmallVectorImpl &Fixups, int ImmOffset) const { >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >>> +} >>> + >>> + >>> + >>> + >>> + >>> + >>> +/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. >>> +/// >>> +/// MemOperand is the operand # of the start of a memory operand if present. If >>> +/// Not present, it is -1. >>> +void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, >>> + int MemOperand, const MCInst &MI, >>> + const TargetInstrDesc &Desc, >>> + raw_ostream &OS) const { >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >>> +} >>> + >>> +void ARMMCCodeEmitter:: >>> +EncodeInstruction(const MCInst &MI, raw_ostream &OS, >>> + SmallVectorImpl &Fixups) const { >>> + assert(0 && "ARMCodeEmitter will be implemented soon"); >>> +} >>> Index: lib/Target/ARM/CMakeLists.txt >>> =================================================================== >>> --- lib/Target/ARM/CMakeLists.txt (revision 114081) >>> +++ lib/Target/ARM/CMakeLists.txt (working copy) >>> @@ -28,6 +28,7 @@ >>> ARMISelLowering.cpp >>> ARMInstrInfo.cpp >>> ARMJITInfo.cpp >>> + ARMMCCodeEmitter.cpp >>> ARMLoadStoreOptimizer.cpp >>> ARMMCAsmInfo.cpp >>> ARMMCInstLower.cpp >>> >> > From gohman at apple.com Fri Sep 17 15:06:27 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 20:06:27 -0000 Subject: [llvm-commits] [llvm] r114196 - in /llvm/trunk: autoconf/configure.ac include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/System/FEnv.h lib/Analysis/ConstantFolding.cpp Message-ID: <20100917200627.6FD682A6C12C@llvm.org> Author: djg Date: Fri Sep 17 15:06:27 2010 New Revision: 114196 URL: http://llvm.org/viewvc/llvm-project?rev=114196&view=rev Log: Attempt to support platforms which don't have fenv.h. Added: llvm/trunk/include/llvm/System/FEnv.h Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Config/config.h.in llvm/trunk/lib/Analysis/ConstantFolding.cpp Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=114196&r1=114195&r2=114196&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Fri Sep 17 15:06:27 2010 @@ -1262,6 +1262,7 @@ AC_CHECK_HEADERS([sys/mman.h sys/param.h sys/resource.h sys/time.h]) AC_CHECK_HEADERS([sys/types.h sys/ioctl.h malloc/malloc.h mach/mach.h]) AC_CHECK_HEADERS([valgrind/valgrind.h]) +AC_CHECK_HEADERS([fenv.h]) if test "$ENABLE_THREADS" -eq 1 ; then AC_CHECK_HEADERS(pthread.h, AC_SUBST(HAVE_PTHREAD, 1), Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=114196&r1=114195&r2=114196&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Fri Sep 17 15:06:27 2010 @@ -461,6 +461,9 @@ /* Define to 1 if you have the header file. */ #cmakedefine HAVE_VALGRIND_VALGRIND_H ${HAVE_VALGRIND_VALGRIND_H} +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_FENV_H ${HAVE_FENV_H} + /* Define to 1 if you have the header file. */ #cmakedefine HAVE_WINDOWS_H ${HAVE_WINDOWS_H} Modified: llvm/trunk/include/llvm/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=114196&r1=114195&r2=114196&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.in (original) +++ llvm/trunk/include/llvm/Config/config.h.in Fri Sep 17 15:06:27 2010 @@ -455,6 +455,9 @@ /* Define to 1 if you have the header file. */ #undef HAVE_VALGRIND_VALGRIND_H +/* Define to 1 if you have the header file. */ +#undef HAVE_FENV_H + /* Define to 1 if you have the header file. */ #undef HAVE_WINDOWS_H Added: llvm/trunk/include/llvm/System/FEnv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/FEnv.h?rev=114196&view=auto ============================================================================== --- llvm/trunk/include/llvm/System/FEnv.h (added) +++ llvm/trunk/include/llvm/System/FEnv.h Fri Sep 17 15:06:27 2010 @@ -0,0 +1,50 @@ +//===- llvm/System/FEnv.h - Host floating-point exceptions ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides an operating system independent interface to +// floating-point exception interfaces. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SYSTEM_FENV_H +#define LLVM_SYSTEM_FENV_H + +#include "llvm/Config/config.h" +#include +#ifdef HAVE_FENV_H +#include +#endif + +namespace llvm { +namespace sys { + +/// llvm_fenv_clearexcept - Clear the floating-point exception state. +static inline void llvm_fenv_clearexcept() { +#ifdef HAVE_FENV_H + feclearexcept(FE_ALL_EXCEPT); +#endif + errno = 0; +} + +/// llvm_fenv_testexcept - Test if a floating-point exception was raised. +static inline bool llvm_fenv_testexcept() { + int errno_val = errno; + if (errno_val == ERANGE || errno_val == EDOM) + return true; +#ifdef HAVE_FENV_H + if (fetestexcept(FE_ALL_EXCEPT)) + return true; +#endif + return false; +} + +} // End sys namespace +} // End llvm namespace + +#endif Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=114196&r1=114195&r2=114196&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Fri Sep 17 15:06:27 2010 @@ -30,6 +30,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/MathExtras.h" +#include "llvm/System/FEnv.h" #include #include #include @@ -1040,13 +1041,10 @@ static Constant *ConstantFoldFP(double (*NativeFP)(double), double V, const Type *Ty) { - feclearexcept(FE_ALL_EXCEPT); - errno = 0; + sys::llvm_fenv_clearexcept(); V = NativeFP(V); - if (errno != 0 || - fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) { - feclearexcept(FE_ALL_EXCEPT); - errno = 0; + if (sys::llvm_fenv_testexcept()) { + sys::llvm_fenv_clearexcept(); return 0; } @@ -1060,13 +1058,10 @@ static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double), double V, double W, const Type *Ty) { - feclearexcept(FE_ALL_EXCEPT); - errno = 0; + sys::llvm_fenv_clearexcept(); V = NativeFP(V, W); - if (errno != 0 || - fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) { - feclearexcept(FE_ALL_EXCEPT); - errno = 0; + if (sys::llvm_fenv_testexcept()) { + sys::llvm_fenv_clearexcept(); return 0; } From gohman at apple.com Fri Sep 17 15:08:35 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 20:08:35 -0000 Subject: [llvm-commits] [llvm] r114197 - /llvm/trunk/configure Message-ID: <20100917200835.A95F42A6C12C@llvm.org> Author: djg Date: Fri Sep 17 15:08:35 2010 New Revision: 114197 URL: http://llvm.org/viewvc/llvm-project?rev=114197&view=rev Log: Regenerate. Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=114197&r1=114196&r2=114197&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Fri Sep 17 15:08:35 2010 @@ -16604,6 +16604,175 @@ done + +for ac_header in fenv.h +do +as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + { echo "$as_me:$LINENO: checking for $ac_header" >&5 +echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +fi +ac_res=`eval echo '${'$as_ac_Header'}'` + { echo "$as_me:$LINENO: result: $ac_res" >&5 +echo "${ECHO_T}$ac_res" >&6; } +else + # Is the header compilable? +{ echo "$as_me:$LINENO: checking $ac_header usability" >&5 +echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +#include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_header_compiler=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_compiler=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 +echo "${ECHO_T}$ac_header_compiler" >&6; } + +# Is the header present? +{ echo "$as_me:$LINENO: checking $ac_header presence" >&5 +echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include <$ac_header> +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null; then + if test -s conftest.err; then + ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag + else + ac_cpp_err= + fi +else + ac_cpp_err=yes +fi +if test -z "$ac_cpp_err"; then + ac_header_preproc=yes +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_preproc=no +fi + +rm -f conftest.err conftest.$ac_ext +{ echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 +echo "${ECHO_T}$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in + yes:no: ) + { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 +echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 +echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} + ac_header_preproc=yes + ;; + no:yes:* ) + { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 +echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 +echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 +echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 +echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 +echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} + { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 +echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} + ( cat <<\_ASBOX +## ----------------------------------- ## +## Report this to llvmbugs at cs.uiuc.edu ## +## ----------------------------------- ## +_ASBOX + ) | sed "s/^/$as_me: WARNING: /" >&2 + ;; +esac +{ echo "$as_me:$LINENO: checking for $ac_header" >&5 +echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + eval "$as_ac_Header=\$ac_header_preproc" +fi +ac_res=`eval echo '${'$as_ac_Header'}'` + { echo "$as_me:$LINENO: result: $ac_res" >&5 +echo "${ECHO_T}$ac_res" >&6; } + +fi +if test `eval echo '${'$as_ac_Header'}'` = yes; then + cat >>confdefs.h <<_ACEOF +#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + if test "$ENABLE_THREADS" -eq 1 ; then for ac_header in pthread.h From gohman at apple.com Fri Sep 17 15:15:53 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 20:15:53 -0000 Subject: [llvm-commits] [llvm] r114198 - /llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Message-ID: <20100917201553.B66F72A6C12C@llvm.org> Author: djg Date: Fri Sep 17 15:15:53 2010 New Revision: 114198 URL: http://llvm.org/viewvc/llvm-project?rev=114198&view=rev Log: Fix this test so that folding doesn't depend on a potentially "inexact" result. Modified: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Modified: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114198&r1=114197&r2=114198&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Fri Sep 17 15:15:53 2010 @@ -10,9 +10,9 @@ ; This should fold. ; CHECK: @bar -; CHECK: ret double 0x3FDA6026360C2F91 +; CHECK: ret double 0.0 define double @bar() { - %t = call double @sin(double 9.0) + %t = call double @sin(double 0.0) ret double %t } From grosbach at apple.com Fri Sep 17 15:17:41 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 20:17:41 -0000 Subject: [llvm-commits] [llvm] r114199 - /llvm/trunk/test/CodeGen/ARM/constants.ll Message-ID: <20100917201741.EFBDB2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 15:17:41 2010 New Revision: 114199 URL: http://llvm.org/viewvc/llvm-project?rev=114199&view=rev Log: tweak test to check instructions rather than relying on the comment string Modified: llvm/trunk/test/CodeGen/ARM/constants.ll Modified: llvm/trunk/test/CodeGen/ARM/constants.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/constants.ll?rev=114199&r1=114198&r2=114199&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/constants.ll (original) +++ llvm/trunk/test/CodeGen/ARM/constants.ll Fri Sep 17 15:17:41 2010 @@ -14,25 +14,25 @@ define i32 @f3() { ; CHECK: f3 -; CHECK: mov r0{{.*}}256 +; CHECK: mov r0, #1, 24 ret i32 256 } define i32 @f4() { ; CHECK: f4 -; CHECK: orr{{.*}}256 +; CHECK: orr{{.*}}#1, 24 ret i32 257 } define i32 @f5() { ; CHECK: f5 -; CHECK: mov r0, {{.*}}-1073741761 +; CHECK: mov r0, #255, 2 ret i32 -1073741761 } define i32 @f6() { ; CHECK: f6 -; CHECK: mov r0, {{.*}}1008 +; CHECK: mov r0, #63, 28 ret i32 1008 } From grosbach at apple.com Fri Sep 17 15:21:03 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 20:21:03 -0000 Subject: [llvm-commits] [llvm] r114200 - /llvm/trunk/test/CodeGen/ARM/fp.ll Message-ID: <20100917202103.6C9452A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 15:21:03 2010 New Revision: 114200 URL: http://llvm.org/viewvc/llvm-project?rev=114200&view=rev Log: tweak test to check instructions rather than relying on the comment string Modified: llvm/trunk/test/CodeGen/ARM/fp.ll Modified: llvm/trunk/test/CodeGen/ARM/fp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp.ll?rev=114200&r1=114199&r2=114200&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fp.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fp.ll Fri Sep 17 15:21:03 2010 @@ -51,7 +51,7 @@ define float @h2() { ;CHECK: h2: -;CHECK: 1065353216 +;CHECK: mov r0, #254, 10 entry: ret float 1.000000e+00 } From gohman at apple.com Fri Sep 17 15:24:24 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 20:24:24 -0000 Subject: [llvm-commits] [llvm] r114201 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll Message-ID: <20100917202424.C7A922A6C12C@llvm.org> Author: djg Date: Fri Sep 17 15:24:24 2010 New Revision: 114201 URL: http://llvm.org/viewvc/llvm-project?rev=114201&view=rev Log: Avoid emitting a PIC base register if no PIC addresses are needed. This fixes rdar://8396318. Added: llvm/trunk/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=114201&r1=114200&r2=114201&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Sep 17 15:24:24 2010 @@ -3108,6 +3108,13 @@ if (TM->getRelocationModel() != Reloc::PIC_) return false; + X86MachineFunctionInfo *X86FI = MF.getInfo(); + unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); + + // If we didn't need a GlobalBaseReg, don't insert code. + if (GlobalBaseReg == 0) + return false; + // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = MF.front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); @@ -3119,7 +3126,7 @@ if (TM->getSubtarget().isPICStyleGOT()) PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); else - PC = TII->getGlobalBaseReg(&MF); + PC = GlobalBaseReg; // Operand of MovePCtoStack is completely ignored by asm printer. It's // only used in JIT code emission as displacement to pc. @@ -3128,7 +3135,6 @@ // If we're using vanilla 'GOT' PIC style, we should use relative addressing // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. if (TM->getSubtarget().isPICStyleGOT()) { - unsigned GlobalBaseReg = TII->getGlobalBaseReg(&MF); // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", Added: llvm/trunk/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll?rev=114201&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll (added) +++ llvm/trunk/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll Fri Sep 17 15:24:24 2010 @@ -0,0 +1,23 @@ +; RUN: llc -O0 -relocation-model=pic < %s | not grep call +; rdar://8396318 + +; Don't emit a PIC base register if no addresses are needed. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin11.0.0" + +define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind ssp { +entry: + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + %z.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + store i32 %y, i32* %y.addr, align 4 + store i32 %z, i32* %z.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tmp1 = load i32* %y.addr, align 4 + %add = add nsw i32 %tmp, %tmp1 + %tmp2 = load i32* %z.addr, align 4 + %add3 = add nsw i32 %add, %tmp2 + ret i32 %add3 +} From gohman at apple.com Fri Sep 17 15:25:43 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 20:25:43 -0000 Subject: [llvm-commits] [llvm] r114202 - /llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt.ll Message-ID: <20100917202544.0A3922A6C12C@llvm.org> Author: djg Date: Fri Sep 17 15:25:43 2010 New Revision: 114202 URL: http://llvm.org/viewvc/llvm-project?rev=114202&view=rev Log: Fix this test to avoid an "inexact" fold. Modified: llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt.ll Modified: llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt.ll?rev=114202&r1=114201&r2=114202&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt.ll (original) +++ llvm/trunk/test/Transforms/GlobalOpt/ctor-list-opt.ll Fri Sep 17 15:25:43 2010 @@ -74,7 +74,7 @@ declare double @cos(double) define internal void @CTOR8() { - %X = call double @cos( double 1.000000e+00 ) ; [#uses=1] + %X = call double @cos( double 0.000000e+00 ) ; [#uses=1] store double %X, double* @D ret void } From grosbach at apple.com Fri Sep 17 15:27:26 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 20:27:26 -0000 Subject: [llvm-commits] [llvm] r114204 - /llvm/trunk/test/CodeGen/ARM/long.ll Message-ID: <20100917202726.DB5402A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 15:27:26 2010 New Revision: 114204 URL: http://llvm.org/viewvc/llvm-project?rev=114204&view=rev Log: tweak test to check instructions rather than relying on the comment string Modified: llvm/trunk/test/CodeGen/ARM/long.ll Modified: llvm/trunk/test/CodeGen/ARM/long.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long.ll?rev=114204&r1=114203&r2=114204&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long.ll Fri Sep 17 15:27:26 2010 @@ -14,22 +14,22 @@ define i64 @f3() { ; CHECK: f3: -; CHECK: mvn{{.*}}-2147483648 +; CHECK: mvn r0, #2, 2 entry: ret i64 2147483647 } define i64 @f4() { ; CHECK: f4: -; CHECK: -2147483648 +; CHECK: mov r0, #2, 2 entry: ret i64 2147483648 } define i64 @f5() { ; CHECK: f5: -; CHECK: mvn -; CHECK: mvn{{.*}}-2147483648 +; CHECK: mvn r0, #0 +; CHECK: mvn r1, #2, 2 entry: ret i64 9223372036854775807 } From ofv at wanadoo.es Fri Sep 17 15:30:48 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 17 Sep 2010 20:30:48 -0000 Subject: [llvm-commits] [llvm] r114205 - /llvm/trunk/cmake/config-ix.cmake Message-ID: <20100917203048.6F3622A6C12C@llvm.org> Author: ofv Date: Fri Sep 17 15:30:48 2010 New Revision: 114205 URL: http://llvm.org/viewvc/llvm-project?rev=114205&view=rev Log: cmake: test for the presence of fenv.h Modified: llvm/trunk/cmake/config-ix.cmake Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=114205&r1=114204&r2=114205&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Fri Sep 17 15:30:48 2010 @@ -69,6 +69,7 @@ check_include_file(utime.h HAVE_UTIME_H) check_include_file(valgrind/valgrind.h HAVE_VALGRIND_VALGRIND_H) check_include_file(windows.h HAVE_WINDOWS_H) +check_include_file(fenv.h HAVE_FENV_H) # library checks if( NOT LLVM_ON_WIN32 ) From grosbach at apple.com Fri Sep 17 15:34:10 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 20:34:10 -0000 Subject: [llvm-commits] [llvm] r114206 - in /llvm/trunk/test/CodeGen: ARM/2009-08-21-PostRAKill4.ll ARM/2009-09-01-PostRAProlog.ll Thumb2/2009-08-21-PostRAKill4.ll Thumb2/2009-09-01-PostRAProlog.ll Message-ID: <20100917203410.25FE92A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 15:34:09 2010 New Revision: 114206 URL: http://llvm.org/viewvc/llvm-project?rev=114206&view=rev Log: Move thumb2 tests to the thumb2 directory Added: llvm/trunk/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll - copied unchanged from r114087, llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll llvm/trunk/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll - copied unchanged from r114087, llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll Removed: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll Removed: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll?rev=114205&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll (removed) @@ -1,26 +0,0 @@ -; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler - -; ModuleID = '' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" -target triple = "armv7-apple-darwin9" - - at .str = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=0] - at .str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] - at .str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] - -declare i32 @getUnknown(i32, ...) nounwind - -declare void @llvm.va_start(i8*) nounwind - -declare void @llvm.va_end(i8*) nounwind - -declare i32 @printf(i8* nocapture, ...) nounwind - -define i32 @main() nounwind { -entry: - %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; [#uses=0] - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; [#uses=0] - %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; [#uses=1] - %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; [#uses=0] - ret i32 0 -} Removed: llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll?rev=114205&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll (removed) @@ -1,106 +0,0 @@ -; RUN: llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s | FileCheck %s - -target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" -target triple = "thumbv7-apple-darwin9" - - at history = internal global [2 x [56 x i32]] [[56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0], [56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0]] ; <[2 x [56 x i32]]*> [#uses=3] - at nodes = internal global i64 0 ; [#uses=4] - at .str = private constant [9 x i8] c"##-<=>+#\00", align 1 ; <[9 x i8]*> [#uses=2] - at .str1 = private constant [6 x i8] c"%c%d\0A\00", align 1 ; <[6 x i8]*> [#uses=1] - at .str2 = private constant [16 x i8] c"Fhourstones 2.0\00", align 1 ; <[16 x i8]*> [#uses=1] - at .str3 = private constant [54 x i8] c"Using %d transposition table entries with %d probes.\0A\00", align 1 ; <[54 x i8]*> [#uses=1] - at .str4 = private constant [31 x i8] c"Solving %d-ply position after \00", align 1 ; <[31 x i8]*> [#uses=1] - at .str5 = private constant [7 x i8] c" . . .\00", align 1 ; <[7 x i8]*> [#uses=1] - at .str6 = private constant [28 x i8] c"score = %d (%c) work = %d\0A\00", align 1 ; <[28 x i8]*> [#uses=1] - at .str7 = private constant [36 x i8] c"%lu pos / %lu msec = %.1f Kpos/sec\0A\00", align 1 ; <[36 x i8]*> [#uses=1] - at plycnt = internal global i32 0 ; [#uses=21] - at dias = internal global [19 x i32] zeroinitializer ; <[19 x i32]*> [#uses=43] - at columns = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=18] - at height = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=21] - at rows = internal global [8 x i32] zeroinitializer ; <[8 x i32]*> [#uses=20] - at colthr = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=5] - at moves = internal global [44 x i32] zeroinitializer ; <[44 x i32]*> [#uses=9] - at .str8 = private constant [3 x i8] c"%d\00", align 1 ; <[3 x i8]*> [#uses=1] - at he = internal global i8* null ; [#uses=9] - at hits = internal global i64 0 ; [#uses=8] - at posed = internal global i64 0 ; [#uses=7] - at ht = internal global i32* null ; [#uses=5] - at .str16 = private constant [19 x i8] c"store rate = %.3f\0A\00", align 1 ; <[19 x i8]*> [#uses=1] - at .str117 = private constant [45 x i8] c"- %5.3f < %5.3f = %5.3f > %5.3f + %5.3f\0A\00", align 1 ; <[45 x i8]*> [#uses=1] - at .str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] - at .str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] - -declare i32 @puts(i8* nocapture) nounwind - -declare i32 @getchar() nounwind - -define internal i32 @transpose() nounwind readonly { -; CHECK: push -entry: - %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; [#uses=1] - %1 = shl i32 %0, 7 ; [#uses=1] - %2 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 2), align 4 ; [#uses=1] - %3 = or i32 %1, %2 ; [#uses=1] - %4 = shl i32 %3, 7 ; [#uses=1] - %5 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 3), align 4 ; [#uses=1] - %6 = or i32 %4, %5 ; [#uses=3] - %7 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 7), align 4 ; [#uses=1] - %8 = shl i32 %7, 7 ; [#uses=1] - %9 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 6), align 4 ; [#uses=1] - %10 = or i32 %8, %9 ; [#uses=1] - %11 = shl i32 %10, 7 ; [#uses=1] - %12 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 5), align 4 ; [#uses=1] - %13 = or i32 %11, %12 ; [#uses=3] - %14 = icmp ugt i32 %6, %13 ; [#uses=2] - %.pn2.in.i = select i1 %14, i32 %6, i32 %13 ; [#uses=1] - %.pn1.in.i = select i1 %14, i32 %13, i32 %6 ; [#uses=1] - %.pn2.i = shl i32 %.pn2.in.i, 7 ; [#uses=1] - %.pn3.i = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 4) ; [#uses=1] - %.pn.in.in.i = or i32 %.pn2.i, %.pn3.i ; [#uses=1] - %.pn.in.i = zext i32 %.pn.in.in.i to i64 ; [#uses=1] - %.pn.i = shl i64 %.pn.in.i, 21 ; [#uses=1] - %.pn1.i = zext i32 %.pn1.in.i to i64 ; [#uses=1] - %iftmp.22.0.i = or i64 %.pn.i, %.pn1.i ; [#uses=2] - %15 = lshr i64 %iftmp.22.0.i, 17 ; [#uses=1] - %16 = trunc i64 %15 to i32 ; [#uses=2] - %17 = urem i64 %iftmp.22.0.i, 1050011 ; [#uses=1] - %18 = trunc i64 %17 to i32 ; [#uses=1] - %19 = urem i32 %16, 179 ; [#uses=1] - %20 = or i32 %19, 131072 ; [#uses=1] - %21 = load i32** @ht, align 4 ; [#uses=1] - br label %bb5 - -bb: ; preds = %bb5 - %22 = getelementptr inbounds i32* %21, i32 %x.0 ; [#uses=1] - %23 = load i32* %22, align 4 ; [#uses=1] - %24 = icmp eq i32 %23, %16 ; [#uses=1] - br i1 %24, label %bb1, label %bb2 - -bb1: ; preds = %bb - %25 = load i8** @he, align 4 ; [#uses=1] - %26 = getelementptr inbounds i8* %25, i32 %x.0 ; [#uses=1] - %27 = load i8* %26, align 1 ; [#uses=1] - %28 = sext i8 %27 to i32 ; [#uses=1] - ret i32 %28 - -bb2: ; preds = %bb - %29 = add nsw i32 %20, %x.0 ; [#uses=3] - %30 = add i32 %29, -1050011 ; [#uses=1] - %31 = icmp sgt i32 %29, 1050010 ; [#uses=1] - %. = select i1 %31, i32 %30, i32 %29 ; [#uses=1] - %32 = add i32 %33, 1 ; [#uses=1] - br label %bb5 - -bb5: ; preds = %bb2, %entry - %33 = phi i32 [ 0, %entry ], [ %32, %bb2 ] ; [#uses=2] - %x.0 = phi i32 [ %18, %entry ], [ %., %bb2 ] ; [#uses=3] - %34 = icmp sgt i32 %33, 7 ; [#uses=1] - br i1 %34, label %bb7, label %bb - -bb7: ; preds = %bb5 - ret i32 -128 -} - -declare noalias i8* @calloc(i32, i32) nounwind - -declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind From clattner at apple.com Fri Sep 17 15:49:23 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 17 Sep 2010 13:49:23 -0700 Subject: [llvm-commits] [llvm] r114200 - /llvm/trunk/test/CodeGen/ARM/fp.ll In-Reply-To: <20100917202103.6C9452A6C12C@llvm.org> References: <20100917202103.6C9452A6C12C@llvm.org> Message-ID: On Sep 17, 2010, at 1:21 PM, Jim Grosbach wrote: > Author: grosbach > Date: Fri Sep 17 15:21:03 2010 > New Revision: 114200 > > URL: http://llvm.org/viewvc/llvm-project?rev=114200&view=rev > Log: > tweak test to check instructions rather than relying on the comment string This is a great change of course, but we do want the mcinstprinter to generate the same comments. :-) -Chris > > Modified: > llvm/trunk/test/CodeGen/ARM/fp.ll > > Modified: llvm/trunk/test/CodeGen/ARM/fp.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp.ll?rev=114200&r1=114199&r2=114200&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/fp.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/fp.ll Fri Sep 17 15:21:03 2010 > @@ -51,7 +51,7 @@ > > define float @h2() { > ;CHECK: h2: > -;CHECK: 1065353216 > +;CHECK: mov r0, #254, 10 > entry: > ret float 1.000000e+00 > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Fri Sep 17 16:04:36 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 17 Sep 2010 14:04:36 -0700 Subject: [llvm-commits] some thoughts on lowering for calling conventions In-Reply-To: References: <20100911173742.2316C2A6C12C@llvm.org> Message-ID: <5BFF9BD2-8ECA-4250-A7B2-38497F5FEBAB@apple.com> On Sep 17, 2010, at 9:58 AM, Bob Wilson wrote: >> The current implementation has some really annoying problems: >> >> *) Has to be reimplemented for fast isel or any other instruction >> selection solution we want to create. > > Yes, this is a nuisance. I'd still like to see a calling convention lowering pass that could be shared for fast-isel and selection DAGs, but that would be tough because we currently have no way to represent some of the necessary constructs (e.g., physical machine registers) in llvm IR. Speaking to this in particular I'd like to see the information in CallingConv.td sufficient enough to be able to generate lowering of all calls in either dag or fastisel. It's a dream, but it could happen :) If the optimizers at various levels need more information then we should be able to get that to them in a different way, pre-emptively lowering just makes an explosion of all new optimization problems. -eric From grosbach at apple.com Fri Sep 17 16:07:32 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 14:07:32 -0700 Subject: [llvm-commits] [llvm] r114200 - /llvm/trunk/test/CodeGen/ARM/fp.ll In-Reply-To: References: <20100917202103.6C9452A6C12C@llvm.org> Message-ID: <655FB396-72F6-4037-BFB8-C6C7D3F129F3@apple.com> On Sep 17, 2010, at 1:49 PM, Chris Lattner wrote: > > On Sep 17, 2010, at 1:21 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Fri Sep 17 15:21:03 2010 >> New Revision: 114200 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=114200&view=rev >> Log: >> tweak test to check instructions rather than relying on the comment string > > This is a great change of course, but we do want the mcinstprinter to generate the same comments. :-) > True. It looks like there's something goofy with setting VerboseAsm for the MC printer. Looking. From grosbach at apple.com Fri Sep 17 16:23:56 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 21:23:56 -0000 Subject: [llvm-commits] [llvm] r114211 - /llvm/trunk/include/llvm/MC/MCInstPrinter.h Message-ID: <20100917212356.9883C2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 16:23:56 2010 New Revision: 114211 URL: http://llvm.org/viewvc/llvm-project?rev=114211&view=rev Log: trailing whitespace Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstPrinter.h?rev=114211&r1=114210&r2=114211&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstPrinter.h (original) +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h Fri Sep 17 16:23:56 2010 @@ -28,21 +28,21 @@ public: MCInstPrinter(const MCAsmInfo &mai) : CommentStream(0), MAI(mai) {} - + virtual ~MCInstPrinter(); /// setCommentStream - Specify a stream to emit comments to. void setCommentStream(raw_ostream &OS) { CommentStream = &OS; } - + /// printInst - Print the specified MCInst to the specified raw_ostream. /// virtual void printInst(const MCInst *MI, raw_ostream &OS) = 0; - + /// getOpcodeName - Return the name of the specified opcode enum (e.g. /// "MOV32ri") or empty if we can't resolve it. virtual StringRef getOpcodeName(unsigned Opcode) const; }; - + } // namespace llvm #endif From grosbach at apple.com Fri Sep 17 16:25:11 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 21:25:11 -0000 Subject: [llvm-commits] [llvm] r114212 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Message-ID: <20100917212511.102022A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 16:25:10 2010 New Revision: 114212 URL: http://llvm.org/viewvc/llvm-project?rev=114212&view=rev Log: trailing whitespace Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=114212&r1=114211&r2=114212&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Fri Sep 17 16:25:10 2010 @@ -18,7 +18,7 @@ namespace llvm { class MCOperand; - + class ARMInstPrinter : public MCInstPrinter { bool VerboseAsm; public: @@ -26,7 +26,7 @@ : MCInstPrinter(MAI), VerboseAsm(verboseAsm) {} virtual void printInst(const MCInst *MI, raw_ostream &O); - + // Autogenerated by tblgen. void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); @@ -34,10 +34,10 @@ void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - + void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - + void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, @@ -74,7 +74,7 @@ raw_ostream &O); void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - + void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); @@ -88,7 +88,7 @@ raw_ostream &O); void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - + void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); @@ -108,11 +108,11 @@ void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); // FIXME: Implement. void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind) {} }; - + } #endif From grosbach at apple.com Fri Sep 17 16:33:26 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 21:33:26 -0000 Subject: [llvm-commits] [llvm] r114215 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.cpp AsmPrinter/ARMInstPrinter.h Message-ID: <20100917213326.1F7F82A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 16:33:25 2010 New Revision: 114215 URL: http://llvm.org/viewvc/llvm-project?rev=114215&view=rev Log: Hook up verbose asm comment printing for SOImm operands in MC printer Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114215&r1=114214&r2=114215&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 17 16:33:25 2010 @@ -1524,7 +1524,7 @@ unsigned SyntaxVariant, const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new ARMInstPrinter(MAI, false); + return new ARMInstPrinter(MAI); return 0; } Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114215&r1=114214&r2=114215&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Fri Sep 17 16:33:25 2010 @@ -160,7 +160,7 @@ } } -static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, +static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream, const MCAsmInfo *MAI) { // Break it up into two parts that make up a shifter immediate. V = ARM_AM::getSOImmVal(V); @@ -174,9 +174,8 @@ if (Rot) { O << "#" << Imm << ", " << Rot; // Pretty printed version. - if (VerboseAsm) - O << ' ' << MAI->getCommentString() - << ' ' << (int)ARM_AM::rotr32(Imm, Rot); + if (CommentStream) + *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n"; } else { O << "#" << Imm; } @@ -189,7 +188,7 @@ raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); - printSOImm(O, MO.getImm(), VerboseAsm, &MAI); + printSOImm(O, MO.getImm(), CommentStream, &MAI); } /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=114215&r1=114214&r2=114215&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Fri Sep 17 16:33:25 2010 @@ -22,8 +22,7 @@ class ARMInstPrinter : public MCInstPrinter { bool VerboseAsm; public: - ARMInstPrinter(const MCAsmInfo &MAI, bool verboseAsm) - : MCInstPrinter(MAI), VerboseAsm(verboseAsm) {} + ARMInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} virtual void printInst(const MCInst *MI, raw_ostream &O); From grosbach at apple.com Fri Sep 17 16:35:57 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 14:35:57 -0700 Subject: [llvm-commits] [llvm] r114200 - /llvm/trunk/test/CodeGen/ARM/fp.ll In-Reply-To: <655FB396-72F6-4037-BFB8-C6C7D3F129F3@apple.com> References: <20100917202103.6C9452A6C12C@llvm.org> <655FB396-72F6-4037-BFB8-C6C7D3F129F3@apple.com> Message-ID: On Sep 17, 2010, at 2:07 PM, Jim Grosbach wrote: > > On Sep 17, 2010, at 1:49 PM, Chris Lattner wrote: > >> >> On Sep 17, 2010, at 1:21 PM, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Fri Sep 17 15:21:03 2010 >>> New Revision: 114200 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=114200&view=rev >>> Log: >>> tweak test to check instructions rather than relying on the comment string >> >> This is a great change of course, but we do want the mcinstprinter to generate the same comments. :-) >> > > True. It looks like there's something goofy with setting VerboseAsm for the MC printer. Looking. Found it. Fixed in r114215. From stoklund at 2pi.dk Fri Sep 17 16:39:48 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 17 Sep 2010 14:39:48 -0700 Subject: [llvm-commits] [llvm] r114196 - in /llvm/trunk: autoconf/configure.ac include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/System/FEnv.h lib/Analysis/ConstantFolding.cpp In-Reply-To: <20100917200627.6FD682A6C12C@llvm.org> References: <20100917200627.6FD682A6C12C@llvm.org> Message-ID: <84CBDFB8-5C7E-4D3D-AB8E-EBA5FFCE0657@2pi.dk> On Sep 17, 2010, at 1:06 PM, Dan Gohman wrote: > --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) > +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Fri Sep 17 15:06:27 2010 > @@ -30,6 +30,7 @@ > #include "llvm/Support/ErrorHandling.h" > #include "llvm/Support/GetElementPtrTypeIterator.h" > #include "llvm/Support/MathExtras.h" > +#include "llvm/System/FEnv.h" > #include > #include > #include > @@ -1040,13 +1041,10 @@ Ahem. Still including /jakob From clattner at apple.com Fri Sep 17 16:44:25 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 17 Sep 2010 14:44:25 -0700 Subject: [llvm-commits] [llvm] r114200 - /llvm/trunk/test/CodeGen/ARM/fp.ll In-Reply-To: References: <20100917202103.6C9452A6C12C@llvm.org> <655FB396-72F6-4037-BFB8-C6C7D3F129F3@apple.com> Message-ID: <0DCE9117-BE1A-4C5D-A717-2122B32A36DC@apple.com> On Sep 17, 2010, at 2:35 PM, Jim Grosbach wrote: >>> >>> This is a great change of course, but we do want the mcinstprinter to generate the same comments. :-) >>> >> >> True. It looks like there's something goofy with setting VerboseAsm for the MC printer. Looking. > > > Found it. Fixed in r114215. Nice, thanks! From grosbach at apple.com Fri Sep 17 16:46:16 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 21:46:16 -0000 Subject: [llvm-commits] [llvm] r114218 - /llvm/trunk/test/CodeGen/ARM/bits.ll Message-ID: <20100917214616.833AB2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 16:46:16 2010 New Revision: 114218 URL: http://llvm.org/viewvc/llvm-project?rev=114218&view=rev Log: FileCheck-ize Modified: llvm/trunk/test/CodeGen/ARM/bits.ll Modified: llvm/trunk/test/CodeGen/ARM/bits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bits.ll?rev=114218&r1=114217&r2=114218&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bits.ll (original) +++ llvm/trunk/test/CodeGen/ARM/bits.ll Fri Sep 17 16:46:16 2010 @@ -1,36 +1,41 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep and %t | count 1 -; RUN: grep orr %t | count 1 -; RUN: grep eor %t | count 1 -; RUN: grep mov.*lsl %t | count 1 -; RUN: grep mov.*asr %t | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32 %a, i32 %b) { entry: +; CHECK: f1 +; CHECK: and r0, r1, r0 %tmp2 = and i32 %b, %a ; [#uses=1] ret i32 %tmp2 } define i32 @f2(i32 %a, i32 %b) { entry: +; CHECK: f2 +; CHECK: orr r0, r1, r0 %tmp2 = or i32 %b, %a ; [#uses=1] ret i32 %tmp2 } define i32 @f3(i32 %a, i32 %b) { entry: +; CHECK: f3 +; CHECK: eor r0, r1, r0 %tmp2 = xor i32 %b, %a ; [#uses=1] ret i32 %tmp2 } define i32 @f4(i32 %a, i32 %b) { entry: +; CHECK: f4 +; CHECK: lsl %tmp3 = shl i32 %a, %b ; [#uses=1] ret i32 %tmp3 } define i32 @f5(i32 %a, i32 %b) { entry: +; CHECK: f5 +; CHECK: asr %tmp3 = ashr i32 %a, %b ; [#uses=1] ret i32 %tmp3 } From stoklund at 2pi.dk Fri Sep 17 16:47:03 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 17 Sep 2010 21:47:03 -0000 Subject: [llvm-commits] [llvm] r114219 - /llvm/trunk/lib/Analysis/ConstantFolding.cpp Message-ID: <20100917214703.DE75F2A6C12C@llvm.org> Author: stoklund Date: Fri Sep 17 16:47:03 2010 New Revision: 114219 URL: http://llvm.org/viewvc/llvm-project?rev=114219&view=rev Log: Don't include now that we have llvm/System/FEnv.h. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=114219&r1=114218&r2=114219&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Fri Sep 17 16:47:03 2010 @@ -33,7 +33,6 @@ #include "llvm/System/FEnv.h" #include #include -#include using namespace llvm; //===----------------------------------------------------------------------===// From bigcheesegs at gmail.com Fri Sep 17 16:52:44 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Fri, 17 Sep 2010 17:52:44 -0400 Subject: [llvm-commits] [llvm] r114219 - /llvm/trunk/lib/Analysis/ConstantFolding.cpp In-Reply-To: <20100917214703.DE75F2A6C12C@llvm.org> References: <20100917214703.DE75F2A6C12C@llvm.org> Message-ID: On Fri, Sep 17, 2010 at 5:47 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Sep 17 16:47:03 2010 > New Revision: 114219 > > URL: http://llvm.org/viewvc/llvm-project?rev=114219&view=rev > Log: > Don't include now that we have llvm/System/FEnv.h. Yay! Thanks. - Michael Spencer > > Modified: > ? ?llvm/trunk/lib/Analysis/ConstantFolding.cpp > > Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=114219&r1=114218&r2=114219&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) > +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Fri Sep 17 16:47:03 2010 > @@ -33,7 +33,6 @@ > ?#include "llvm/System/FEnv.h" > ?#include > ?#include > -#include > ?using namespace llvm; > > ?//===----------------------------------------------------------------------===// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From clattner at apple.com Fri Sep 17 16:53:04 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 17 Sep 2010 14:53:04 -0700 Subject: [llvm-commits] [PATCH] Add exit instruction to PTX backend In-Reply-To: References: Message-ID: <92FD1B35-9E05-4920-9C1B-CEE5B005D652@apple.com> On Sep 16, 2010, at 2:43 AM, Che-Liang Chiou wrote: > Hi Chris, > > Thanks for the comments. I've put {'s on the previous line and > removed accidentally added tab characters. I've also checked again > that cmake file was updated. Thanks for reminding. > > I regenerate patch against r114073. Please take a look. Looks good, please commit, -Chris From evan.cheng at apple.com Fri Sep 17 16:56:26 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 17 Sep 2010 21:56:26 -0000 Subject: [llvm-commits] [llvm] r114220 - /llvm/trunk/lib/CodeGen/MachineCSE.cpp Message-ID: <20100917215626.EE4B12A6C12C@llvm.org> Author: evancheng Date: Fri Sep 17 16:56:26 2010 New Revision: 114220 URL: http://llvm.org/viewvc/llvm-project?rev=114220&view=rev Log: Fix a potential bug that can cause miscomparison with and without debug info. Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=114220&r1=114219&r2=114220&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Fri Sep 17 16:56:26 2010 @@ -101,7 +101,7 @@ unsigned Reg = MO.getReg(); if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue; - if (!MRI->hasOneUse(Reg)) + if (!MRI->hasOneNonDBGUse(Reg)) // Only coalesce single use copies. This ensure the copy will be // deleted. continue; From grosbach at apple.com Fri Sep 17 16:58:46 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 21:58:46 -0000 Subject: [llvm-commits] [llvm] r114221 - in /llvm/trunk/test/CodeGen/ARM: bfi.ll ispositive.ll long_shift.ll mul_const.ll Message-ID: <20100917215847.0609A2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 16:58:46 2010 New Revision: 114221 URL: http://llvm.org/viewvc/llvm-project?rev=114221&view=rev Log: Update tests to handle MC-inst instruction printing of shift operations. The legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. Modified: llvm/trunk/test/CodeGen/ARM/bfi.ll llvm/trunk/test/CodeGen/ARM/ispositive.ll llvm/trunk/test/CodeGen/ARM/long_shift.ll llvm/trunk/test/CodeGen/ARM/mul_const.ll Modified: llvm/trunk/test/CodeGen/ARM/bfi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfi.ll?rev=114221&r1=114220&r2=114221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bfi.ll (original) +++ llvm/trunk/test/CodeGen/ARM/bfi.ll Fri Sep 17 16:58:46 2010 @@ -19,7 +19,7 @@ define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize { entry: ; CHECK: f2 -; CHECK: mov r1, r1, lsr #7 +; CHECK: lsr{{.*}}#7 ; CHECK: bfi r0, r1, #7, #16 %and = and i32 %A, -8388481 ; [#uses=1] %and2 = and i32 %B, 8388480 ; [#uses=1] @@ -30,7 +30,7 @@ define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize { entry: ; CHECK: f3 -; CHECK: mov r2, r0, lsr #7 +; CHECK: lsr{{.*}} #7 ; CHECK: mov r0, r1 ; CHECK: bfi r0, r2, #7, #16 %and = and i32 %A, 8388480 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/ispositive.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ispositive.ll?rev=114221&r1=114220&r2=114221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ispositive.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ispositive.ll Fri Sep 17 16:58:46 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i32 @test1(i32 %X) { -; CHECK: mov r0, r0, lsr #31 +; CHECK: lsr{{.*}}#31 entry: icmp slt i32 %X, 0 ; :0 [#uses=1] zext i1 %0 to i32 ; :1 [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/long_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long_shift.ll?rev=114221&r1=114220&r2=114221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long_shift.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long_shift.ll Fri Sep 17 16:58:46 2010 @@ -14,7 +14,7 @@ define i32 @f1(i64 %x, i64 %y) { ; CHECK: f1 -; CHECK: mov r0, r0, lsl r2 +; CHECK: lsl{{.*}}r2 %a = shl i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b @@ -22,7 +22,7 @@ define i32 @f2(i64 %x, i64 %y) { ; CHECK: f2 -; CHECK: mov r0, r0, lsr r2 +; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: subs r2, r2, #32 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 @@ -34,7 +34,7 @@ define i32 @f3(i64 %x, i64 %y) { ; CHECK: f3 -; CHECK: mov r0, r0, lsr r2 +; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: subs r2, r2, #32 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 Modified: llvm/trunk/test/CodeGen/ARM/mul_const.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mul_const.ll?rev=114221&r1=114220&r2=114221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/mul_const.ll (original) +++ llvm/trunk/test/CodeGen/ARM/mul_const.ll Fri Sep 17 16:58:46 2010 @@ -36,7 +36,7 @@ entry: ; CHECK: t12288: ; CHECK: add r0, r0, r0, lsl #1 -; CHECK: mov r0, r0, lsl #12 +; CHECK: lsl{{.*}}#12 %0 = mul i32 %v, 12288 ret i32 %0 } From evan.cheng at apple.com Fri Sep 17 16:59:42 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 17 Sep 2010 21:59:42 -0000 Subject: [llvm-commits] [llvm] r114222 - /llvm/trunk/lib/CodeGen/MachineCSE.cpp Message-ID: <20100917215943.0423A2A6C12C@llvm.org> Author: evancheng Date: Fri Sep 17 16:59:42 2010 New Revision: 114222 URL: http://llvm.org/viewvc/llvm-project?rev=114222&view=rev Log: Machine CSE was forgetting to clear some data structures. Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=114222&r1=114221&r2=114222&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Fri Sep 17 16:59:42 2010 @@ -54,6 +54,11 @@ AU.addPreserved(); } + virtual void releaseMemory() { + ScopeMap.clear(); + Exps.clear(); + } + private: const unsigned LookAheadLimit; typedef ScopedHashTableScope ParentMap; DenseMap OpenChildren; + CurrVN = 0; + // Perform a DFS walk to determine the order of visit. WorkList.push_back(Node); do { From echristo at apple.com Fri Sep 17 17:28:18 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 17 Sep 2010 22:28:18 -0000 Subject: [llvm-commits] [llvm] r114226 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100917222818.A7C642A6C12C@llvm.org> Author: echristo Date: Fri Sep 17 17:28:18 2010 New Revision: 114226 URL: http://llvm.org/viewvc/llvm-project?rev=114226&view=rev Log: Rework arm fast isel branch and compare code. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=114226&r1=114225&r2=114226&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Sep 17 17:28:18 2010 @@ -694,7 +694,54 @@ if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false; - return false; + return true; +} + +static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) { + switch (Pred) { + // Needs two compares... + case CmpInst::FCMP_ONE: + case CmpInst::FCMP_UEQ: + default: + assert(false && "Unhandled CmpInst::Predicate!"); + return ARMCC::AL; + case CmpInst::ICMP_EQ: + case CmpInst::FCMP_OEQ: + return ARMCC::EQ; + case CmpInst::ICMP_SGT: + case CmpInst::FCMP_OGT: + return ARMCC::GT; + case CmpInst::ICMP_SGE: + case CmpInst::FCMP_OGE: + return ARMCC::GE; + case CmpInst::ICMP_UGT: + case CmpInst::FCMP_UGT: + return ARMCC::HI; + case CmpInst::FCMP_OLT: + return ARMCC::MI; + case CmpInst::ICMP_ULE: + case CmpInst::FCMP_OLE: + return ARMCC::LS; + case CmpInst::FCMP_ORD: + return ARMCC::VC; + case CmpInst::FCMP_UNO: + return ARMCC::VS; + case CmpInst::FCMP_UGE: + return ARMCC::PL; + case CmpInst::ICMP_SLT: + case CmpInst::FCMP_ULT: + return ARMCC::LT; + case CmpInst::ICMP_SLE: + case CmpInst::FCMP_ULE: + return ARMCC::LE; + case CmpInst::FCMP_UNE: + case CmpInst::ICMP_NE: + return ARMCC::NE; + case CmpInst::ICMP_UGE: + return ARMCC::HS; + case CmpInst::ICMP_ULT: + return ARMCC::LO; + } } bool ARMFastISel::ARMSelectBranch(const Instruction *I) { @@ -703,18 +750,28 @@ MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // Simple branch support. - unsigned CondReg = getRegForValue(BI->getCondition()); + // TODO: Hopefully we've already handled the condition since we won't + // have left an update in the value map. See the TODO below in ARMSelectCMP. + Value *Cond = BI->getCondition(); + unsigned CondReg = getRegForValue(Cond); if (CondReg == 0) return false; - unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; + ARMCC::CondCodes ARMPred = ARMCC::NE; + CmpInst *CI = dyn_cast(Cond); + if (!CI) return false; + + // Get the compare predicate. + ARMPred = getComparePred(CI->getPredicate()); + + // We may not handle every CC for now. + if (ARMPred == ARMCC::AL) return false; + unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) - .addReg(CondReg).addReg(CondReg)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) - .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR); + .addMBB(TBB).addImm(ARMPred).addReg(CondReg); FastEmitBranch(FBB, DL); FuncInfo.MBB->addSuccessor(TBB); - return true; + return true; } bool ARMFastISel::ARMSelectCmp(const Instruction *I) { @@ -730,17 +787,21 @@ return false; unsigned CmpOpc; + unsigned DestReg; switch (VT.getSimpleVT().SimpleTy) { default: return false; // TODO: Verify compares. case MVT::f32: CmpOpc = ARM::VCMPES; + DestReg = ARM::FPSCR; break; case MVT::f64: CmpOpc = ARM::VCMPED; + DestReg = ARM::FPSCR; break; case MVT::i32: CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; + DestReg = ARM::CPSR; break; } @@ -759,7 +820,8 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::FMSTAT))); - // TODO: How to update the value map when there's no result reg? + // Update the value to the implicit def reg. + UpdateValueMap(I, DestReg); return true; } From evan.cheng at apple.com Fri Sep 17 17:28:18 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 17 Sep 2010 22:28:18 -0000 Subject: [llvm-commits] [llvm] r114227 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp test/CodeGen/X86/lsr-reuse.ll test/CodeGen/X86/pr3522.ll test/CodeGen/X86/tail-opts.ll Message-ID: <20100917222818.C68D12A6C12D@llvm.org> Author: evancheng Date: Fri Sep 17 17:28:18 2010 New Revision: 114227 URL: http://llvm.org/viewvc/llvm-project?rev=114227&view=rev Log: Teach machine sink to 1) Do forward copy propagation. This makes it easier to estimate the cost of the instruction being sunk. 2) Break critical edges on demand, including cases where the value is used by PHI nodes. Critical edge splitting is not yet enabled by default. Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp llvm/trunk/test/CodeGen/X86/lsr-reuse.ll llvm/trunk/test/CodeGen/X86/pr3522.ll llvm/trunk/test/CodeGen/X86/tail-opts.ll Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=114227&r1=114226&r2=114227&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Fri Sep 17 17:28:18 2010 @@ -25,6 +25,7 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -39,19 +40,24 @@ SplitLimit("split-limit", cl::init(~0u), cl::Hidden); -STATISTIC(NumSunk, "Number of machine instructions sunk"); -STATISTIC(NumSplit, "Number of critical edges split"); +STATISTIC(NumSunk, "Number of machine instructions sunk"); +STATISTIC(NumSplit, "Number of critical edges split"); +STATISTIC(NumCoalesces, "Number of copies coalesced"); namespace { class MachineSinking : public MachineFunctionPass { const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; - MachineRegisterInfo *RegInfo; // Machine register information + MachineRegisterInfo *MRI; // Machine register information MachineDominatorTree *DT; // Machine dominator tree MachineLoopInfo *LI; AliasAnalysis *AA; BitVector AllocatableSet; // Which physregs are allocatable? + // Remember which edges have been considered for breaking. + SmallSet, 8> + CEBCandidates; + public: static char ID; // Pass identification MachineSinking() : MachineFunctionPass(ID) {} @@ -67,13 +73,27 @@ AU.addPreserved(); AU.addPreserved(); } + + virtual void releaseMemory() { + CEBCandidates.clear(); + } + private: bool ProcessBlock(MachineBasicBlock &MBB); - MachineBasicBlock *SplitCriticalEdge(MachineBasicBlock *From, - MachineBasicBlock *To); + bool isWorthBreakingCriticalEdge(MachineInstr *MI, + MachineBasicBlock *From, + MachineBasicBlock *To); + MachineBasicBlock *SplitCriticalEdge(MachineInstr *MI, + MachineBasicBlock *From, + MachineBasicBlock *To, + bool HasNonePHIUse); bool SinkInstruction(MachineInstr *MI, bool &SawStore); bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, - MachineBasicBlock *DefMBB, bool &LocalUse) const; + MachineBasicBlock *DefMBB, + SmallPtrSet &PHIUses, + bool &NonPHIUse, bool &LocalUse) const; + bool PerformTrivialForwardCoalescing(MachineInstr *MI, + MachineBasicBlock *MBB); }; } // end anonymous namespace @@ -83,14 +103,44 @@ FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } +bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI, + MachineBasicBlock *MBB) { + if (!MI->isCopy()) + return false; + + unsigned SrcReg = MI->getOperand(1).getReg(); + unsigned DstReg = MI->getOperand(0).getReg(); + if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || + !TargetRegisterInfo::isVirtualRegister(DstReg) || + !MRI->hasOneNonDBGUse(SrcReg)) + return false; + + const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); + const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); + if (SRC != DRC) + return false; + + MachineInstr *DefMI = MRI->getVRegDef(SrcReg); + if (DefMI->isCopyLike()) + return false; + DEBUG(dbgs() << "Coalescing: " << *DefMI); + DEBUG(dbgs() << "*** to: " << *MI); + MRI->replaceRegWith(DstReg, SrcReg); + MI->eraseFromParent(); + ++NumCoalesces; + return true; +} + /// AllUsesDominatedByBlock - Return true if all uses of the specified register /// occur in blocks dominated by the specified block. If any use is in the /// definition block, then return false since it is never legal to move def /// after uses. -bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, - MachineBasicBlock *MBB, - MachineBasicBlock *DefMBB, - bool &LocalUse) const { +bool +MachineSinking::AllUsesDominatedByBlock(unsigned Reg, + MachineBasicBlock *MBB, + MachineBasicBlock *DefMBB, + SmallPtrSet &PHIUses, + bool &NonPHIUse, bool &LocalUse) const { assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs"); // Ignoring debug uses is necessary so debug info doesn't affect the code. @@ -98,13 +148,33 @@ // the definition of the vreg. Dwarf generator handles this although the // user might not get the right info at runtime. for (MachineRegisterInfo::use_nodbg_iterator - I = RegInfo->use_nodbg_begin(Reg), E = RegInfo->use_nodbg_end(); + I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); I != E; ++I) { // Determine the block of the use. MachineInstr *UseInst = &*I; MachineBasicBlock *UseBlock = UseInst->getParent(); - if (UseInst->isPHI()) { + bool isPHI = UseInst->isPHI(); + if (isPHI) + PHIUses.insert(UseInst); + + if (isPHI) { + if (SplitEdges && UseBlock == MBB) + // PHI is in the successor BB. e.g. + // BB#1: derived from LLVM BB %bb4.preheader + // Predecessors according to CFG: BB#0 + // ... + // %reg16385 = DEC64_32r %reg16437, %EFLAGS + // ... + // JE_4 , %EFLAGS + // Successors according to CFG: BB#37 BB#2 + // + // BB#2: derived from LLVM BB %bb.nph + // Predecessors according to CFG: BB#0 BB#1 + // %reg16386 = PHI %reg16434, , %reg16385, + // + // Machine sink should break the critical edge first. + continue; // PHI nodes use the operand in the predecessor block, not the block with // the PHI. UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB(); @@ -127,7 +197,7 @@ const TargetMachine &TM = MF.getTarget(); TII = TM.getInstrInfo(); TRI = TM.getRegisterInfo(); - RegInfo = &MF.getRegInfo(); + MRI = &MF.getRegInfo(); DT = &getAnalysis(); LI = &getAnalysis(); AA = &getAnalysis(); @@ -139,6 +209,7 @@ bool MadeChange = false; // Process all basic blocks. + CEBCandidates.clear(); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) MadeChange |= ProcessBlock(*I); @@ -177,6 +248,9 @@ if (MI->isDebugValue()) continue; + if (PerformTrivialForwardCoalescing(MI, &MBB)) + continue; + if (SinkInstruction(MI, SawStore)) ++NumSunk, MadeChange = true; @@ -186,51 +260,92 @@ return MadeChange; } -MachineBasicBlock *MachineSinking::SplitCriticalEdge(MachineBasicBlock *FromBB, - MachineBasicBlock *ToBB) { +bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr *MI, + MachineBasicBlock *From, + MachineBasicBlock *To) { + // FIXME: Need much better heuristics. + + // If the pass has already considered breaking this edge (during this pass + // through the function), then let's go ahead and break it. This means + // sinking multiple "cheap" instructions into the same block. + if (!CEBCandidates.insert(std::make_pair(From, To))) + return true; + + if (!(MI->isCopyLike() || MI->getDesc().isAsCheapAsAMove())) + return true; + + // MI is cheap, we probably don't want to break the critical edge for it. + // However, if this would allow some definitions of its source operands + // to be sunk then it's probably worth it. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) continue; + unsigned Reg = MO.getReg(); + if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) + continue; + if (MRI->hasOneNonDBGUse(Reg)) + return true; + } + + return false; +} + +MachineBasicBlock *MachineSinking::SplitCriticalEdge(MachineInstr *MI, + MachineBasicBlock *FromBB, + MachineBasicBlock *ToBB, + bool HasNonePHIUse) { + if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB)) + return 0; + // Avoid breaking back edge. From == To means backedge for single BB loop. if (!SplitEdges || NumSplit == SplitLimit || FromBB == ToBB) return 0; - // Check for more "complex" loops. - if (LI->getLoopFor(FromBB) != LI->getLoopFor(ToBB) || - !LI->isLoopHeader(ToBB)) { - // It's not always legal to break critical edges and sink the computation - // to the edge. - // - // BB#1: - // v1024 - // Beq BB#3 - // - // BB#2: - // ... no uses of v1024 - // - // BB#3: - // ... - // = v1024 - // - // If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted: - // - // BB#1: - // ... - // Bne BB#2 - // BB#4: - // v1024 = - // B BB#3 - // BB#2: - // ... no uses of v1024 - // - // BB#3: - // ... - // = v1024 - // - // This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3 - // flow. We need to ensure the new basic block where the computation is - // sunk to dominates all the uses. - // It's only legal to break critical edge and sink the computation to the - // new block if all the predecessors of "To", except for "From", are - // not dominated by "From". Given SSA property, this means these - // predecessors are dominated by "To". + // Check for backedges of more "complex" loops. + if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) && + LI->isLoopHeader(ToBB)) + return 0; + + // It's not always legal to break critical edges and sink the computation + // to the edge. + // + // BB#1: + // v1024 + // Beq BB#3 + // + // BB#2: + // ... no uses of v1024 + // + // BB#3: + // ... + // = v1024 + // + // If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted: + // + // BB#1: + // ... + // Bne BB#2 + // BB#4: + // v1024 = + // B BB#3 + // BB#2: + // ... no uses of v1024 + // + // BB#3: + // ... + // = v1024 + // + // This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3 + // flow. We need to ensure the new basic block where the computation is + // sunk to dominates all the uses. + // It's only legal to break critical edge and sink the computation to the + // new block if all the predecessors of "To", except for "From", are + // not dominated by "From". Given SSA property, this means these + // predecessors are dominated by "To". + // + // There is no need to do this check if all the uses are PHI nodes. PHI + // sources are only defined on the specific predecessor edges. + if (HasNonePHIUse) { for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(), E = ToBB->pred_end(); PI != E; ++PI) { if (*PI == FromBB) @@ -238,12 +353,9 @@ if (!DT->dominates(ToBB, *PI)) return 0; } - - // FIXME: Determine if it's cost effective to break this edge. - return FromBB->SplitCriticalEdge(ToBB, this); } - return 0; + return FromBB->SplitCriticalEdge(ToBB, this); } /// SinkInstruction - Determine whether it is safe to sink the specified machine @@ -269,6 +381,9 @@ // decide. MachineBasicBlock *SuccToSinkTo = 0; + SmallSet Defs; + SmallPtrSet PHIUses; + bool HasNonPHIUse = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; // Ignore non-register operands. @@ -281,7 +396,7 @@ // If the physreg has no defs anywhere, it's just an ambient register // and we can freely move its uses. Alternatively, if it's allocatable, // it could get allocated to something with a def during allocation. - if (!RegInfo->def_empty(Reg)) + if (!MRI->def_empty(Reg)) return false; if (AllocatableSet.test(Reg)) @@ -290,7 +405,7 @@ // Check for a def among the register's aliases too. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { unsigned AliasReg = *Alias; - if (!RegInfo->def_empty(AliasReg)) + if (!MRI->def_empty(AliasReg)) return false; if (AllocatableSet.test(AliasReg)) @@ -303,9 +418,10 @@ } else { // Virtual register uses are always safe to sink. if (MO.isUse()) continue; + Defs.insert(Reg); // If it's not safe to move defs of the register class, then abort. - if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg))) + if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) return false; // FIXME: This picks a successor to sink into based on having one @@ -327,7 +443,8 @@ // If a previous operand picked a block to sink to, then this operand // must be sinkable to the same block. bool LocalUse = false; - if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, LocalUse)) + if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, PHIUses, + HasNonPHIUse, LocalUse)) return false; continue; @@ -338,7 +455,8 @@ for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), E = ParentBlock->succ_end(); SI != E; ++SI) { bool LocalUse = false; - if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock, LocalUse)) { + if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock, PHIUses, + HasNonPHIUse, LocalUse)) { SuccToSinkTo = *SI; break; } @@ -384,7 +502,6 @@ // If the block has multiple predecessors, this would introduce computation on // a path that it doesn't already exist. We could split the critical edge, // but for now we just punt. - // FIXME: Split critical edges if not backedges. if (SuccToSinkTo->pred_size() > 1) { // We cannot sink a load across a critical edge - there may be stores in // other code paths. @@ -412,10 +529,11 @@ if (!TryBreak) DEBUG(dbgs() << "Sinking along critical edge.\n"); else { - MachineBasicBlock *NewSucc = SplitCriticalEdge(ParentBlock, SuccToSinkTo); + MachineBasicBlock *NewSucc = + SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, HasNonPHIUse); if (!NewSucc) { - DEBUG(dbgs() << - " *** PUNTING: Not legal or profitable to break critical edge\n"); + DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " + "break critical edge\n"); return false; } else { DEBUG(dbgs() << " *** Splitting critical edge:" @@ -430,9 +548,41 @@ // Determine where to insert into. Skip phi nodes. MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); - while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) + while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) { + MachineInstr *PHI = &*InsertPos; ++InsertPos; + if (SplitEdges && PHIUses.count(PHI)) { + if (NumSplit == SplitLimit) + return false; + + // A PHI use is in the destination successor so we can't sink the + // instruction here. Break the critical edge first! + for (unsigned i = 1, e = PHI->getNumOperands(); i != e; i += 2) { + unsigned SrcReg = PHI->getOperand(i).getReg(); + if (Defs.count(SrcReg)) { + MachineBasicBlock *SrcMBB = PHI->getOperand(i+1).getMBB(); + MachineBasicBlock *NewSucc = + SplitCriticalEdge(MI, SrcMBB, SuccToSinkTo, HasNonPHIUse); + if (!NewSucc) { + DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " + "break critical edge\n"); + return false; + } + + DEBUG(dbgs() << " *** Splitting critical edge:" + " BB#" << SrcMBB->getNumber() + << " -- BB#" << NewSucc->getNumber() + << " -- BB#" << SuccToSinkTo->getNumber() << '\n'); + SuccToSinkTo = NewSucc; + InsertPos = NewSucc->begin(); + ++NumSplit; + break; + } + } + } + } + // Move the instruction. SuccToSinkTo->splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse.ll?rev=114227&r1=114226&r2=114227&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-reuse.ll (original) +++ llvm/trunk/test/CodeGen/X86/lsr-reuse.ll Fri Sep 17 17:28:18 2010 @@ -353,11 +353,11 @@ ; CHECK: count_me_3: ; CHECK: call -; CHECK: movsd (%r15,%r13,8), %xmm0 -; CHECK: mulsd (%r14,%r13,8), %xmm0 -; CHECK: movsd %xmm0, (%r12,%r13,8) -; CHECK: incq %r13 -; CHECK: cmpq %r13, %rbx +; CHECK: movsd (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0 +; CHECK: mulsd (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0 +; CHECK: movsd %xmm0, (%r{{[^,]*}},%r{{[^,]*}},8) +; CHECK: incq %r{{.*}} +; CHECK: cmpq %r{{.*}}, %r{{.*}} ; CHECK: jne declare void @use(i64) Modified: llvm/trunk/test/CodeGen/X86/pr3522.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3522.ll?rev=114227&r1=114226&r2=114227&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr3522.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr3522.ll Fri Sep 17 17:28:18 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -stats |& not grep machine-sink +; RUN: llc < %s -march=x86 -stats |& not grep {instructions sunk} ; PR3522 target triple = "i386-pc-linux-gnu" Modified: llvm/trunk/test/CodeGen/X86/tail-opts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-opts.ll?rev=114227&r1=114226&r2=114227&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/tail-opts.ll (original) +++ llvm/trunk/test/CodeGen/X86/tail-opts.ll Fri Sep 17 17:28:18 2010 @@ -62,11 +62,11 @@ ; CHECK: tail_duplicate_me: ; CHECK: movl $0, GHJK(%rip) -; CHECK-NEXT: jmpq *%rbx +; CHECK-NEXT: jmpq *%r ; CHECK: movl $0, GHJK(%rip) -; CHECK-NEXT: jmpq *%rbx +; CHECK-NEXT: jmpq *%r ; CHECK: movl $0, GHJK(%rip) -; CHECK-NEXT: jmpq *%rbx +; CHECK-NEXT: jmpq *%r define void @tail_duplicate_me() nounwind { entry: From rafael.espindola at gmail.com Fri Sep 17 17:34:41 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 17 Sep 2010 22:34:41 -0000 Subject: [llvm-commits] [llvm] r114229 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100917223441.7B1D72A6C12C@llvm.org> Author: rafael Date: Fri Sep 17 17:34:41 2010 New Revision: 114229 URL: http://llvm.org/viewvc/llvm-project?rev=114229&view=rev Log: Avoid relocations in a common case. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114229&r1=114228&r2=114229&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Fri Sep 17 17:34:41 2010 @@ -470,12 +470,22 @@ unsigned Index = 0; int64_t Value = Target.getConstant(); + bool IsPCRel = isFixupKindX86PCRel(Fixup.getKind()); if (!Target.isAbsolute()) { const MCSymbol *Symbol = &Target.getSymA()->getSymbol(); MCSymbolData &SD = Asm.getSymbolData(*Symbol); const MCSymbolData *Base = Asm.getAtom(Layout, &SD); MCFragment *F = SD.getFragment(); + // Avoid relocations for cases like jumps and calls in the same file. + if (Symbol->isDefined() && !SD.isExternal() && + IsPCRel && + &Fragment->getParent()->getSection() == &Symbol->getSection()) { + uint64_t FixupAddr = Layout.getFragmentAddress(Fragment) + Fixup.getOffset(); + FixedValue = Layout.getSymbolAddress(&SD) + Target.getConstant() - FixupAddr; + return; + } + if (Base) { if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) { Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1; @@ -507,7 +517,6 @@ FixedValue = Value; // determine the type of the relocation - bool IsPCRel = isFixupKindX86PCRel(Fixup.getKind()); unsigned Type; if (Is64Bit) { if (IsPCRel) { From grosbach at apple.com Fri Sep 17 17:36:38 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 22:36:38 -0000 Subject: [llvm-commits] [llvm] r114230 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll test/CodeGen/ARM/ifcvt10.ll test/CodeGen/ARM/stm.ll test/CodeGen/Thumb2/large-stack.ll Message-ID: <20100917223638.BB4962A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 17:36:38 2010 New Revision: 114230 URL: http://llvm.org/viewvc/llvm-project?rev=114230&view=rev Log: Teach the (non-MC) instruction printer to use the cannonical names for push/pop, and shift instructions on ARM. Update the tests to match. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll llvm/trunk/test/CodeGen/ARM/ifcvt10.ll llvm/trunk/test/CodeGen/ARM/stm.ll llvm/trunk/test/CodeGen/Thumb2/large-stack.ll Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114230&r1=114229&r2=114230&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 17 17:36:38 2010 @@ -1147,11 +1147,78 @@ OS << ']'; OS << "+"; printOperand(MI, NOps-2, OS); - OutStreamer.EmitRawText(OS.str()); - return; - } + } else if (MI->getOpcode() == ARM::MOVs) { + // FIXME: Thumb variants? + const MachineOperand &Dst = MI->getOperand(0); + const MachineOperand &MO1 = MI->getOperand(1); + const MachineOperand &MO2 = MI->getOperand(2); + const MachineOperand &MO3 = MI->getOperand(3); + + OS << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); + printSBitModifierOperand(MI, 6, OS); + printPredicateOperand(MI, 4, OS); + + OS << '\t' << getRegisterName(Dst.getReg()) + << ", " << getRegisterName(MO1.getReg()); + + if (ARM_AM::getSORegShOp(MO3.getImm()) != ARM_AM::rrx) { + OS << ", "; + + if (MO2.getReg()) { + OS << getRegisterName(MO2.getReg()); + assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); + } else { + OS << "#" << ARM_AM::getSORegOffset(MO3.getImm()); + } + } + } else + // A8.6.123 PUSH + if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { + OS << '\t' << "push"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + // A8.6.122 POP + if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { + OS << '\t' << "pop"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + // A8.6.355 VPUSH + if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { + OS << '\t' << "vpush"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + // A8.6.354 VPOP + if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { + OS << '\t' << "vpop"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + printInstruction(MI, OS); - printInstruction(MI, OS); + // Output the instruction to the stream OutStreamer.EmitRawText(OS.str()); // Make sure the instruction that follows TBB is 2-byte aligned. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114230&r1=114229&r2=114230&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Fri Sep 17 17:36:38 2010 @@ -55,6 +55,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for MOVs and print canonical forms, instead. if (MI->getOpcode() == ARM::MOVs) { + // FIXME: Thumb variants? const MCOperand &Dst = MI->getOperand(0); const MCOperand &MO1 = MI->getOperand(1); const MCOperand &MO2 = MI->getOperand(2); Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=114230&r1=114229&r2=114230&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Fri Sep 17 17:36:38 2010 @@ -9,7 +9,7 @@ entry: ; Make sure to use base-updating stores for saving callee-saved registers. ; CHECK-NOT: sub sp -; CHECK: vstmdb sp! +; CHECK: vpush %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] br label %cond_next489 Modified: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=114230&r1=114229&r2=114230&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt10.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Fri Sep 17 17:36:38 2010 @@ -12,10 +12,10 @@ ; CHECK: aaa: ; CHECK: vldr.32 ; CHECK-NOT: vldrne -; CHECK-NOT: vldmiane -; CHECK-NOT: ldmiane -; CHECK: vldmia sp! -; CHECK: ldmia sp! +; CHECK-NOT: vpopne +; CHECK-NOT: popne +; CHECK: vpop +; CHECK: pop entry: br i1 undef, label %bb81, label %bb48 Modified: llvm/trunk/test/CodeGen/ARM/stm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/stm.ll?rev=114230&r1=114229&r2=114230&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/stm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/stm.ll Fri Sep 17 17:36:38 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2 +; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s @"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1] @"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1] @@ -7,6 +7,9 @@ define i32 @main() nounwind { entry: +; CHECK: main +; CHECK: push +; CHECK: stmib %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; [#uses=0] %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; [#uses=0] ret i32 0 Modified: llvm/trunk/test/CodeGen/Thumb2/large-stack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/large-stack.ll?rev=114230&r1=114229&r2=114230&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/large-stack.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/large-stack.ll Fri Sep 17 17:36:38 2010 @@ -27,7 +27,7 @@ ; DARWIN: sub.w sp, sp, #805306368 ; DARWIN: sub sp, #20 ; LINUX: test3: -; LINUX: stmdb sp!, {r4, r7, r11, lr} +; LINUX: push {r4, r7, r11, lr} ; LINUX: sub.w sp, sp, #805306368 ; LINUX: sub sp, #16 %retval = alloca i32, align 4 From ismail at namtrac.org Fri Sep 17 15:12:04 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Fri, 17 Sep 2010 23:12:04 +0300 Subject: [llvm-commits] Detect Intel CPU family: 6 model number: 37 as Core i7 Message-ID: Hi; I have a late MacBook Pro 2010 laptop, equipped with Core i7; [~/Sources/llvm]> sysctl -a|grep -i model hw.model = MacBookPro6,2 machdep.cpu.model: 37 machdep.cpu.extmodel: 2 [~/Sources/llvm]> sysctl -a|grep -i family hw.cpufamily: 1463508716 machdep.cpu.family: 6 machdep.cpu.extfamily: 0 Attached patch fixes llvm to detect this as corei7 cpu. Regards, ismail -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100917/100eed0f/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: i7.patch Type: application/octet-stream Size: 561 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100917/100eed0f/attachment.obj From bob.wilson at apple.com Fri Sep 17 17:59:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 17 Sep 2010 22:59:05 -0000 Subject: [llvm-commits] [llvm] r114233 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll Message-ID: <20100917225905.9FF9F2A6C12C@llvm.org> Author: bwilson Date: Fri Sep 17 17:59:05 2010 New Revision: 114233 URL: http://llvm.org/viewvc/llvm-project?rev=114233&view=rev Log: Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. Added: llvm/trunk/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114233&r1=114232&r2=114233&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep 17 17:59:05 2010 @@ -326,6 +326,7 @@ setTargetDAGCombine(ISD::ZERO_EXTEND); setTargetDAGCombine(ISD::ANY_EXTEND); setTargetDAGCombine(ISD::SELECT_CC); + setTargetDAGCombine(ISD::BUILD_VECTOR); } computeRegisterProperties(); @@ -4342,6 +4343,31 @@ return SDValue(); } +/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for +/// ISD::BUILD_VECTOR. +static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) { + // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): + // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value + // into a pair of GPRs, which is fine when the value is used as a scalar, + // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. + if (N->getNumOperands() == 2) { + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + if (Op0.getOpcode() == ISD::BIT_CONVERT) + Op0 = Op0.getOperand(0); + if (Op1.getOpcode() == ISD::BIT_CONVERT) + Op1 = Op1.getOperand(0); + if (Op0.getOpcode() == ARMISD::VMOVRRD && + Op0.getNode() == Op1.getNode() && + Op0.getResNo() == 0 && Op1.getResNo() == 1) { + return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), + N->getValueType(0), Op0.getOperand(0)); + } + } + + return SDValue(); +} + /// PerformVMOVRRDCombine - Target-specific dag combine xforms for /// ARMISD::VMOVRRD. static SDValue PerformVMOVRRDCombine(SDNode *N, @@ -4760,6 +4786,7 @@ case ISD::SUB: return PerformSUBCombine(N, DCI); case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); case ISD::OR: return PerformORCombine(N, DCI, Subtarget); + case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); Added: llvm/trunk/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll?rev=114233&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll Fri Sep 17 17:59:05 2010 @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is +; converted back to be used as a vector type. + +; CHECK: test: +define <4 x i32> @test() nounwind { +entry: + br i1 undef, label %bb1, label %bb2 + +bb1: + %0 = bitcast <2 x i64> zeroinitializer to <2 x double> + %1 = extractelement <2 x double> %0, i32 0 + %2 = bitcast double %1 to i64 + %3 = insertelement <1 x i64> undef, i64 %2, i32 0 +; CHECK-NOT: vmov s +; CHECK: vext.8 + %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> + %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8> + %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> + %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32> + br i1 undef, label %bb2, label %bb1 + +bb2: + %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ] + ret <4 x i32> %result +} From grosbach at apple.com Fri Sep 17 18:41:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 17 Sep 2010 23:41:53 -0000 Subject: [llvm-commits] [llvm] r114237 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20100917234153.DFBEB2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 18:41:53 2010 New Revision: 114237 URL: http://llvm.org/viewvc/llvm-project?rev=114237&view=rev Log: Add MC-inst handling for tPICADD Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114237&r1=114236&r2=114237&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 17 18:41:53 2010 @@ -1389,6 +1389,32 @@ case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass"); default: break; + case ARM::tPICADD: { + // This is a pseudo op for a label + instruction sequence, which looks like: + // LPC0: + // add r0, pc + // This adds the address of LPC0 to r0. + + // Emit the label. + // FIXME: MOVE TO SHARED PLACE. + unsigned Id = (unsigned)MI->getOperand(2).getImm(); + const char *Prefix = MAI->getPrivateGlobalPrefix(); + MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix) + + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id)); + OutStreamer.EmitLabel(Label); + + // Form and emit the add. + MCInst AddInst; + AddInst.setOpcode(ARM::tADDhirr); + AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); + AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); + AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); + // Add predicate operands. + AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); + AddInst.addOperand(MCOperand::CreateReg(0)); + OutStreamer.EmitInstruction(AddInst); + return; + } case ARM::PICADD: { // FIXME: Remove asm string from td file. // This is a pseudo op for a label + instruction sequence, which looks like: // LPC0: From benny.kra at googlemail.com Fri Sep 17 18:48:07 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 17 Sep 2010 23:48:07 -0000 Subject: [llvm-commits] [llvm] r114240 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/neon-tests.txt Message-ID: <20100917234807.73ADB2A6C12C@llvm.org> Author: d0k Date: Fri Sep 17 18:48:07 2010 New Revision: 114240 URL: http://llvm.org/viewvc/llvm-project?rev=114240&view=rev Log: Fix vmov.f64 disassembly on targets where sizeof(long) != 8. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=114240&r1=114239&r2=114240&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Sep 17 18:48:07 2010 @@ -1588,9 +1588,9 @@ Result = (uint64_t)slice(byte, 7, 7) << 63 | (uint64_t)slice(byte, 5, 0) << 48; if (bit6) - Result |= 0xffL << 54; + Result |= 0xffULL << 54; else - Result |= 0x1L << 62; + Result |= 0x1ULL << 62; } return APInt(N, Result); } Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=114240&r1=114239&r2=114240&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Fri Sep 17 18:48:07 2010 @@ -56,3 +56,6 @@ # CHECK: vmov.f32 s0, #1.328125e-01 0x01 0x0a 0xb4 0xee + +# CHECK: vmov.f64 d0, #5.000000e-01 +0x00 0x0b 0xb6 0xee From gohman at apple.com Fri Sep 17 19:04:37 2010 From: gohman at apple.com (Dan Gohman) Date: Sat, 18 Sep 2010 00:04:37 -0000 Subject: [llvm-commits] [llvm] r114241 - /llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Message-ID: <20100918000438.063012A6C12C@llvm.org> Author: djg Date: Fri Sep 17 19:04:37 2010 New Revision: 114241 URL: http://llvm.org/viewvc/llvm-project?rev=114241&view=rev Log: Attempt to XFAIL this test on arm-linux, which is inexplicably failing. Modified: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Modified: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114241&r1=114240&r2=114241&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Fri Sep 17 19:04:37 2010 @@ -1,5 +1,9 @@ ; RUN: opt -instcombine -S < %s | FileCheck %s +; This test is inexplicably still failing, which suggests a +; bug in the host libm. +; XFAIL: arm-linux + ; This shouldn't fold, because sin(inf) is invalid. ; CHECK: @foo ; CHECK: %t = call double @sin(double 0x7FF0000000000000) From grosbach at apple.com Fri Sep 17 19:04:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 18 Sep 2010 00:04:53 -0000 Subject: [llvm-commits] [llvm] r114242 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100918000453.A69512A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 19:04:53 2010 New Revision: 114242 URL: http://llvm.org/viewvc/llvm-project?rev=114242&view=rev Log: PC-relative pseudo instructions are lowered and printed directly. Any encounter with one in the generic printing code is an error. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114242&r1=114241&r2=114242&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Fri Sep 17 19:04:53 2010 @@ -387,7 +387,7 @@ // All instructions using addrmodepc are pseudos and should have been // handled explicitly in printInstructionThroughMCStreamer(). If one got // here, it wasn't, so something's wrong. - assert(0 && "Unhandled addrmodepc operand!"); + llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); } void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, @@ -522,8 +522,7 @@ void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - // FIXME: remove this. - abort(); + llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); } void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, From grosbach at apple.com Fri Sep 17 19:05:05 2010 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 18 Sep 2010 00:05:05 -0000 Subject: [llvm-commits] [llvm] r114243 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20100918000505.8AD782A6C12C@llvm.org> Author: grosbach Date: Fri Sep 17 19:05:05 2010 New Revision: 114243 URL: http://llvm.org/viewvc/llvm-project?rev=114243&view=rev Log: factor out a simple helper function to create a label for PC-relative instructions (PICADD, PICLDR, et.al.) Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114243&r1=114242&r2=114243&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 17 19:05:05 2010 @@ -1383,6 +1383,14 @@ //===----------------------------------------------------------------------===// +static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber, + unsigned LabelId, MCContext &Ctx) { + + MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix) + + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId)); + return Label; +} + void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) { ARMMCInstLower MCInstLowering(OutContext, *Mang, *this); switch (MI->getOpcode()) { @@ -1396,12 +1404,9 @@ // This adds the address of LPC0 to r0. // Emit the label. - // FIXME: MOVE TO SHARED PLACE. - unsigned Id = (unsigned)MI->getOperand(2).getImm(); - const char *Prefix = MAI->getPrivateGlobalPrefix(); - MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix) - + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id)); - OutStreamer.EmitLabel(Label); + OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), + getFunctionNumber(), MI->getOperand(2).getImm(), + OutContext)); // Form and emit the add. MCInst AddInst; @@ -1422,13 +1427,9 @@ // This adds the address of LPC0 to r0. // Emit the label. - // FIXME: MOVE TO SHARED PLACE. - unsigned Id = (unsigned)MI->getOperand(2).getImm(); - const char *Prefix = MAI->getPrivateGlobalPrefix(); - MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix) - + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id)); - OutStreamer.EmitLabel(Label); - + OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), + getFunctionNumber(), MI->getOperand(2).getImm(), + OutContext)); // Form and emit the add. MCInst AddInst; @@ -1459,12 +1460,9 @@ // a PC-relative address at the ldr instruction. // Emit the label. - // FIXME: MOVE TO SHARED PLACE. - unsigned Id = (unsigned)MI->getOperand(2).getImm(); - const char *Prefix = MAI->getPrivateGlobalPrefix(); - MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix) - + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id)); - OutStreamer.EmitLabel(Label); + OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(), + getFunctionNumber(), MI->getOperand(2).getImm(), + OutContext)); // Form and emit the load unsigned Opcode; From rafael.espindola at gmail.com Fri Sep 17 19:37:28 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sat, 18 Sep 2010 00:37:28 -0000 Subject: [llvm-commits] [llvm] r114248 - /llvm/trunk/test/MC/ELF/norelocation.s Message-ID: <20100918003728.091952A6C12C@llvm.org> Author: rafael Date: Fri Sep 17 19:37:27 2010 New Revision: 114248 URL: http://llvm.org/viewvc/llvm-project?rev=114248&view=rev Log: Add test that was missing in my previous commit. Added: llvm/trunk/test/MC/ELF/norelocation.s Added: llvm/trunk/test/MC/ELF/norelocation.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/norelocation.s?rev=114248&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/norelocation.s (added) +++ llvm/trunk/test/MC/ELF/norelocation.s Fri Sep 17 19:37:27 2010 @@ -0,0 +1,18 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + + call bar +bar: + +// CHECK: ('sh_name', 1) # '.text' +// CHECK-NEXT: ('sh_type', 1) +// CHECK-NEXT: ('sh_flags', 6) +// CHECK-NEXT: ('sh_addr', 0) +// CHECK-NEXT: ('sh_offset', 64) +// CHECK-NEXT: ('sh_size', 5) +// CHECK-NEXT: ('sh_link', 0) +// CHECK-NEXT: ('sh_info', 0) +// CHECK-NEXT: ('sh_addralign', 4) +// CHECK-NEXT: ('sh_entsize', 0) +// CHECK-NEXT: ('_section_data', 'e8000000 00') +// CHECK-NOT: .rela.text +// CHECK: shstrtab From clattner at apple.com Fri Sep 17 19:44:08 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 17 Sep 2010 17:44:08 -0700 Subject: [llvm-commits] [llvm] r114241 - /llvm/trunk/test/Transforms/InstCombine/fold-calls.ll In-Reply-To: <20100918000438.063012A6C12C@llvm.org> References: <20100918000438.063012A6C12C@llvm.org> Message-ID: <69EFC494-A4B4-4234-8DDD-C46812EF2CD2@apple.com> On Sep 17, 2010, at 5:04 PM, Dan Gohman wrote: > Author: djg > Date: Fri Sep 17 19:04:37 2010 > New Revision: 114241 > > URL: http://llvm.org/viewvc/llvm-project?rev=114241&view=rev > Log: > Attempt to XFAIL this test on arm-linux, which is inexplicably failing. Dan, why are you relying on the host's libm to do this anyway? Why not just check the apfloat for inf? Depending on this level of sanity from a host libm seems like a bad idea. -Chris > > Modified: > llvm/trunk/test/Transforms/InstCombine/fold-calls.ll > > Modified: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114241&r1=114240&r2=114241&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Fri Sep 17 19:04:37 2010 > @@ -1,5 +1,9 @@ > ; RUN: opt -instcombine -S < %s | FileCheck %s > > +; This test is inexplicably still failing, which suggests a > +; bug in the host libm. > +; XFAIL: arm-linux > + > ; This shouldn't fold, because sin(inf) is invalid. > ; CHECK: @foo > ; CHECK: %t = call double @sin(double 0x7FF0000000000000) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Fri Sep 17 20:23:39 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 18 Sep 2010 01:23:39 -0000 Subject: [llvm-commits] [llvm] r114254 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100918012339.196982A6C12C@llvm.org> Author: echristo Date: Fri Sep 17 20:23:38 2010 New Revision: 114254 URL: http://llvm.org/viewvc/llvm-project?rev=114254&view=rev Log: Floating point stores have a 3rd addressing mode type. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=114254&r1=114253&r2=114254&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Sep 17 20:23:38 2010 @@ -555,7 +555,6 @@ assert(VT.isSimple() && "Non-simple types are invalid here!"); unsigned Opc; - switch (VT.getSimpleVT().SimpleTy) { default: assert(false && "Trying to emit for an unhandled type!"); @@ -637,6 +636,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, unsigned DstReg, int Offset) { unsigned StrOpc; + bool isFloat = false; switch (VT.getSimpleVT().SimpleTy) { default: return false; case MVT::i1: @@ -646,17 +646,25 @@ case MVT::f32: if (!Subtarget->hasVFP2()) return false; StrOpc = ARM::VSTRS; + isFloat = true; break; case MVT::f64: if (!Subtarget->hasVFP2()) return false; StrOpc = ARM::VSTRD; + isFloat = true; break; } + // The thumb addressing mode has operands swapped from the arm addressing + // mode, the floating point one only has two operands. if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) .addReg(DstReg).addImm(Offset).addReg(0)); + else if (isFloat) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(StrOpc), SrcReg) + .addReg(DstReg).addImm(Offset)); else AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) From gohman at apple.com Fri Sep 17 20:26:30 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 17 Sep 2010 18:26:30 -0700 Subject: [llvm-commits] [llvm] r114241 - /llvm/trunk/test/Transforms/InstCombine/fold-calls.ll In-Reply-To: <69EFC494-A4B4-4234-8DDD-C46812EF2CD2@apple.com> References: <20100918000438.063012A6C12C@llvm.org> <69EFC494-A4B4-4234-8DDD-C46812EF2CD2@apple.com> Message-ID: <2FC393C3-C7B1-4B83-964E-0BA2166DC37B@apple.com> On Sep 17, 2010, at 5:44 PM, Chris Lattner wrote: > > On Sep 17, 2010, at 5:04 PM, Dan Gohman wrote: > >> Author: djg >> Date: Fri Sep 17 19:04:37 2010 >> New Revision: 114241 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=114241&view=rev >> Log: >> Attempt to XFAIL this test on arm-linux, which is inexplicably failing. > > Dan, why are you relying on the host's libm to do this anyway? Why not just check the apfloat for inf? Depending on this level of sanity from a host libm seems like a bad idea. It would be tricky to test for all exceptional cases for all the libm functions that code knows about. LLVM's reliance on the host libm goes way back. Alternatives to using the host libm for constant folding exist, but LLVM has not yet pursued them. Dan From echristo at apple.com Fri Sep 17 20:59:37 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 18 Sep 2010 01:59:37 -0000 Subject: [llvm-commits] [llvm] r114256 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100918015937.A24582A6C12C@llvm.org> Author: echristo Date: Fri Sep 17 20:59:37 2010 New Revision: 114256 URL: http://llvm.org/viewvc/llvm-project?rev=114256&view=rev Log: Add addrmode5 fp load support. Swap float/thumb operand adding to handle thumb with floating point. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=114256&r1=114255&r2=114256&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Sep 17 20:59:37 2010 @@ -555,6 +555,7 @@ assert(VT.isSimple() && "Non-simple types are invalid here!"); unsigned Opc; + bool isFloat = false; switch (VT.getSimpleVT().SimpleTy) { default: assert(false && "Trying to emit for an unhandled type!"); @@ -570,13 +571,27 @@ case MVT::i32: Opc = isThumb ? ARM::tLDR : ARM::LDR; break; + case MVT::f32: + Opc = ARM::VLDRS; + isFloat = true; + break; + case MVT::f64: + Opc = ARM::VLDRD; + isFloat = true; + break; } ResultReg = createResultReg(TLI.getRegClassFor(VT)); // TODO: Fix the Addressing modes so that these can share some code. // Since this is a Thumb1 load this will work in Thumb1 or 2 mode. - if (isThumb) + // The thumb addressing mode has operands swapped from the arm addressing + // mode, the floating point one only has two operands. + if (isFloat) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Reg).addImm(Offset)); + else if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Reg).addImm(Offset).addReg(0)); @@ -657,14 +672,15 @@ // The thumb addressing mode has operands swapped from the arm addressing // mode, the floating point one only has two operands. - if (isThumb) + if (isFloat) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) - .addReg(DstReg).addImm(Offset).addReg(0)); - else if (isFloat) + .addReg(DstReg).addImm(Offset)); + else if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) - .addReg(DstReg).addImm(Offset)); + .addReg(DstReg).addImm(Offset).addReg(0)); + else AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) From daniel at zuster.org Fri Sep 17 21:28:09 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sat, 18 Sep 2010 02:28:09 -0000 Subject: [llvm-commits] [llvm] r114260 - /llvm/trunk/utils/lit/TODO Message-ID: <20100918022809.A39342A6C12C@llvm.org> Author: ddunbar Date: Fri Sep 17 21:28:09 2010 New Revision: 114260 URL: http://llvm.org/viewvc/llvm-project?rev=114260&view=rev Log: lit: These TODOs are done(ish). Modified: llvm/trunk/utils/lit/TODO Modified: llvm/trunk/utils/lit/TODO URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/TODO?rev=114260&r1=114259&r2=114260&view=diff ============================================================================== --- llvm/trunk/utils/lit/TODO (original) +++ llvm/trunk/utils/lit/TODO Fri Sep 17 21:28:09 2010 @@ -2,18 +2,8 @@ - Add --show-unsupported, don't show by default? - - Finish documentation. - - Optionally use multiprocessing. - - Support llvmc and ocaml tests. - - Support valgrind in all configs, and LLVM style valgrind. - - Provide test suite config for running unit tests. - - Support a timeout / ulimit. - - - Support "disabling" tests? The advantage of making this distinct from XFAIL - is it makes it more obvious that it is a temporary measure (and lit can put - in a separate category). From daniel at zuster.org Fri Sep 17 21:28:12 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sat, 18 Sep 2010 02:28:12 -0000 Subject: [llvm-commits] [llvm] r114261 - /llvm/trunk/utils/lit/setup.py Message-ID: <20100918022812.7A6882A6C12D@llvm.org> Author: ddunbar Date: Fri Sep 17 21:28:12 2010 New Revision: 114261 URL: http://llvm.org/viewvc/llvm-project?rev=114261&view=rev Log: lit: Tweak setup.py. Modified: llvm/trunk/utils/lit/setup.py Modified: llvm/trunk/utils/lit/setup.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/setup.py?rev=114261&r1=114260&r2=114261&view=diff ============================================================================== --- llvm/trunk/utils/lit/setup.py (original) +++ llvm/trunk/utils/lit/setup.py Fri Sep 17 21:28:12 2010 @@ -3,7 +3,7 @@ # FIXME: Support distutils? from setuptools import setup, find_packages setup( - name = "Lit", + name = "lit", version = lit.__version__, author = lit.__author__, @@ -14,15 +14,16 @@ description = "A Software Testing Tool", keywords = 'test C++ automatic discovery', long_description = """\ -Lit -+++ +*lit* ++++++ About ===== -Lit is a portable tool for executing LLVM and Clang style test suites, -summarizing their results, and providing indication of failures. Lit is designed -to be a lightweight testing tool with as simple a user interface as possible. +*lit* is a portable tool for executing LLVM and Clang style test suites, +summarizing their results, and providing indication of failures. *lit* is +designed to be a lightweight testing tool with as simple a user interface as +possible. Features @@ -37,15 +38,15 @@ Documentation ============= -The offical Lit documentation is in the man page, available online in the `LLVM -Command Guide http://llvm.org/cmds/lit.html`_. +The offical *lit* documentation is in the man page, available online at the LLVM +Command Guide: http://llvm.org/cmds/lit.html. Source ====== -The Lit source is available as part of LLVM, in the `LLVM SVN repository - Author: ddunbar Date: Fri Sep 17 21:28:15 2010 New Revision: 114262 URL: http://llvm.org/viewvc/llvm-project?rev=114262&view=rev Log: lit: Bump version to 0.2.0dev, for no apparent reason. Modified: llvm/trunk/utils/lit/lit/__init__.py Modified: llvm/trunk/utils/lit/lit/__init__.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/__init__.py?rev=114262&r1=114261&r2=114262&view=diff ============================================================================== --- llvm/trunk/utils/lit/lit/__init__.py (original) +++ llvm/trunk/utils/lit/lit/__init__.py Fri Sep 17 21:28:15 2010 @@ -4,7 +4,7 @@ __author__ = 'Daniel Dunbar' __email__ = 'daniel at zuster.org' -__versioninfo__ = (0, 1, 0) -__version__ = '.'.join(map(str, __versioninfo__)) +__versioninfo__ = (0, 2, 0) +__version__ = '.'.join(map(str, __versioninfo__)) + 'dev' __all__ = [] From echristo at apple.com Fri Sep 17 21:32:38 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 18 Sep 2010 02:32:38 -0000 Subject: [llvm-commits] [llvm] r114263 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100918023239.070D22A6C12C@llvm.org> Author: echristo Date: Fri Sep 17 21:32:38 2010 New Revision: 114263 URL: http://llvm.org/viewvc/llvm-project?rev=114263&view=rev Log: Thumb opcodes for thumb calls. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=114263&r1=114262&r2=114263&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Sep 17 21:32:38 2010 @@ -1100,7 +1100,11 @@ // Issue the call, BLr9 for darwin, BL otherwise. MachineInstrBuilder MIB; - unsigned CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL; + unsigned CallOpc; + if(isThumb) + CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLr9 : ARM::tBL; + else + CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL; MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) .addGlobalAddress(F, 0, 0); From rjmccall at apple.com Fri Sep 17 22:12:52 2010 From: rjmccall at apple.com (John McCall) Date: Sat, 18 Sep 2010 03:12:52 -0000 Subject: [llvm-commits] [test-suite] r114264 - /test-suite/trunk/SingleSource/Regression/C++/fixups.cpp Message-ID: <20100918031252.36E772A6C12C@llvm.org> Author: rjmccall Date: Fri Sep 17 22:12:52 2010 New Revision: 114264 URL: http://llvm.org/viewvc/llvm-project?rev=114264&view=rev Log: Regression test for fixups. Added: test-suite/trunk/SingleSource/Regression/C++/fixups.cpp Added: test-suite/trunk/SingleSource/Regression/C++/fixups.cpp URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Regression/C%2B%2B/fixups.cpp?rev=114264&view=auto ============================================================================== --- test-suite/trunk/SingleSource/Regression/C++/fixups.cpp (added) +++ test-suite/trunk/SingleSource/Regression/C++/fixups.cpp Fri Sep 17 22:12:52 2010 @@ -0,0 +1,50 @@ +#include "stdlib.h" + +// PR8175 + +int count = 0; + +struct L { + int n; + L(int n) : n(n) { count += n; } + ~L() { count -= n; } +}; + +void test0(int n) { + { + L b(n); + if (n) goto l; + } + + l: if (count) abort(); +} + +void test1(int n) { + { + L a(n); + L b(n); + if (n) goto l; + } + + l: if (count) abort(); +} + +void test2(int n) { + { + L a(n); + { + L b(n); + if (n) goto l1; + } + + l1: goto l2; + } + l2: if (count) abort(); +} + +int main(int argc, char *argv[]) { + test0(1); + test1(1); + test2(1); + return 0; +} From resistor at mac.com Fri Sep 17 23:45:14 2010 From: resistor at mac.com (Owen Anderson) Date: Sat, 18 Sep 2010 04:45:14 -0000 Subject: [llvm-commits] [llvm] r114268 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Message-ID: <20100918044514.611CB2A6C12C@llvm.org> Author: resistor Date: Fri Sep 17 23:45:14 2010 New Revision: 114268 URL: http://llvm.org/viewvc/llvm-project?rev=114268&view=rev Log: Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is NO path to the destination containing side effects, not that SOME path contains no side effects. In practice, this only manifests with CombinerAA enabled, because otherwise the chain has little to no branching, so "any" is effectively equivalent to "all". Added: llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114268&r1=114267&r2=114268&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Sep 17 23:45:14 2010 @@ -5478,9 +5478,9 @@ /// reachesChainWithoutSideEffects - Return true if this operand (which must /// be a chain) reaches the specified operand without crossing any -/// side-effecting instructions. In practice, this looks through token -/// factors and non-volatile loads. In order to remain efficient, this only -/// looks a couple of nodes in, it does not do an exhaustive search. +/// side-effecting instructions on any chain path. In practice, this looks +/// through token factors and non-volatile loads. In order to remain efficient, +/// this only looks a couple of nodes in, it does not do an exhaustive search. bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth) const { if (*this == Dest) return true; @@ -5490,12 +5490,12 @@ if (Depth == 0) return false; // If this is a token factor, all inputs to the TF happen in parallel. If any - // of the operands of the TF reach dest, then we can do the xform. + // of the operands of the TF does not reach dest, then we cannot do the xform. if (getOpcode() == ISD::TokenFactor) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) - if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) - return true; - return false; + if (!getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) + return false; + return true; } // Loads don't have side effects, look through them. Added: llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll?rev=114268&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Fri Sep 17 23:45:14 2010 @@ -0,0 +1,26 @@ +; RUN: llc < %s -combiner-alias-analysis -march=x86-64 | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.4" +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +define fastcc i32 @cli_magic_scandesc(i8* %in) nounwind ssp { +entry: + %a = alloca [64 x i8] + %b = getelementptr inbounds [64 x i8]* %a, i64 0, i32 0 + %c = getelementptr inbounds [64 x i8]* %a, i64 0, i32 30 + %d = load i8* %b, align 8 + %e = load i8* %c, align 8 + %f = bitcast [64 x i8]* %a to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %f, i8* %in, i64 64, i32 8, i1 false) nounwind + store i8 %d, i8* %b, align 8 + store i8 %e, i8* %c, align 8 + ret i32 0 +} + +; CHECK: movq ___stack_chk_guard at GOTPCREL(%rip), %rax +; CHECK: movb (%rsp), %dl +; CHECK-NEXT: movb 30(%rsp), %sil +; CHECK: movb %dl, (%rsp) +; CHECK-NEXT: movb %sil, 30(%rsp) +; CHECK: callq ___stack_chk_fail From evan.cheng at apple.com Sat Sep 18 01:42:17 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 18 Sep 2010 06:42:17 -0000 Subject: [llvm-commits] [llvm] r114270 - /llvm/trunk/lib/CodeGen/MachineSink.cpp Message-ID: <20100918064217.740AD2A6C12C@llvm.org> Author: evancheng Date: Sat Sep 18 01:42:17 2010 New Revision: 114270 URL: http://llvm.org/viewvc/llvm-project?rev=114270&view=rev Log: Fix code that break critical edges for PHI uses. Watch out for multiple PHIs in different blocks. Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=114270&r1=114269&r2=114270&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Sat Sep 18 01:42:17 2010 @@ -86,12 +86,11 @@ MachineBasicBlock *SplitCriticalEdge(MachineInstr *MI, MachineBasicBlock *From, MachineBasicBlock *To, - bool HasNonePHIUse); + bool AllPHIUse); bool SinkInstruction(MachineInstr *MI, bool &SawStore); bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, MachineBasicBlock *DefMBB, - SmallPtrSet &PHIUses, - bool &NonPHIUse, bool &LocalUse) const; + bool &AllPHIUse, bool &LocalUse) const; bool PerformTrivialForwardCoalescing(MachineInstr *MI, MachineBasicBlock *MBB); }; @@ -139,42 +138,54 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, MachineBasicBlock *DefMBB, - SmallPtrSet &PHIUses, - bool &NonPHIUse, bool &LocalUse) const { + bool &AllPHIUse, bool &LocalUse) const { assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs"); + + if (MRI->use_nodbg_empty(Reg)) + return true; + // Ignoring debug uses is necessary so debug info doesn't affect the code. // This may leave a referencing dbg_value in the original block, before // the definition of the vreg. Dwarf generator handles this although the // user might not get the right info at runtime. + + // PHI is in the successor BB. e.g. + // BB#1: derived from LLVM BB %bb4.preheader + // Predecessors according to CFG: BB#0 + // ... + // %reg16385 = DEC64_32r %reg16437, %EFLAGS + // ... + // JE_4 , %EFLAGS + // Successors according to CFG: BB#37 BB#2 + // + // BB#2: derived from LLVM BB %bb.nph + // Predecessors according to CFG: BB#0 BB#1 + // %reg16386 = PHI %reg16434, , %reg16385, + // + // Machine sink should break the critical edge first. + AllPHIUse = true; for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); I != E; ++I) { - // Determine the block of the use. MachineInstr *UseInst = &*I; MachineBasicBlock *UseBlock = UseInst->getParent(); + if (!(UseBlock == MBB && UseInst->isPHI() && + UseInst->getOperand(I.getOperandNo()+1).getMBB() == DefMBB)) { + AllPHIUse = false; + break; + } + } + if (AllPHIUse) + return true; - bool isPHI = UseInst->isPHI(); - if (isPHI) - PHIUses.insert(UseInst); - - if (isPHI) { - if (SplitEdges && UseBlock == MBB) - // PHI is in the successor BB. e.g. - // BB#1: derived from LLVM BB %bb4.preheader - // Predecessors according to CFG: BB#0 - // ... - // %reg16385 = DEC64_32r %reg16437, %EFLAGS - // ... - // JE_4 , %EFLAGS - // Successors according to CFG: BB#37 BB#2 - // - // BB#2: derived from LLVM BB %bb.nph - // Predecessors according to CFG: BB#0 BB#1 - // %reg16386 = PHI %reg16434, , %reg16385, - // - // Machine sink should break the critical edge first. - continue; + for (MachineRegisterInfo::use_nodbg_iterator + I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); + I != E; ++I) { + // Determine the block of the use. + MachineInstr *UseInst = &*I; + MachineBasicBlock *UseBlock = UseInst->getParent(); + if (UseInst->isPHI()) { // PHI nodes use the operand in the predecessor block, not the block with // the PHI. UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB(); @@ -293,7 +304,7 @@ MachineBasicBlock *MachineSinking::SplitCriticalEdge(MachineInstr *MI, MachineBasicBlock *FromBB, MachineBasicBlock *ToBB, - bool HasNonePHIUse) { + bool AllPHIUse) { if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB)) return 0; @@ -345,7 +356,7 @@ // // There is no need to do this check if all the uses are PHI nodes. PHI // sources are only defined on the specific predecessor edges. - if (HasNonePHIUse) { + if (!AllPHIUse) { for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(), E = ToBB->pred_end(); PI != E; ++PI) { if (*PI == FromBB) @@ -381,9 +392,7 @@ // decide. MachineBasicBlock *SuccToSinkTo = 0; - SmallSet Defs; - SmallPtrSet PHIUses; - bool HasNonPHIUse = false; + bool AllPHIUse = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; // Ignore non-register operands. @@ -418,7 +427,6 @@ } else { // Virtual register uses are always safe to sink. if (MO.isUse()) continue; - Defs.insert(Reg); // If it's not safe to move defs of the register class, then abort. if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) @@ -443,8 +451,8 @@ // If a previous operand picked a block to sink to, then this operand // must be sinkable to the same block. bool LocalUse = false; - if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, PHIUses, - HasNonPHIUse, LocalUse)) + if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, + AllPHIUse, LocalUse)) return false; continue; @@ -455,8 +463,8 @@ for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), E = ParentBlock->succ_end(); SI != E; ++SI) { bool LocalUse = false; - if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock, PHIUses, - HasNonPHIUse, LocalUse)) { + if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock, + AllPHIUse, LocalUse)) { SuccToSinkTo = *SI; break; } @@ -530,7 +538,7 @@ DEBUG(dbgs() << "Sinking along critical edge.\n"); else { MachineBasicBlock *NewSucc = - SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, HasNonPHIUse); + SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, AllPHIUse); if (!NewSucc) { DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); @@ -546,43 +554,30 @@ } } + if (AllPHIUse) { + if (NumSplit == SplitLimit) + return false; + MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock, + SuccToSinkTo, AllPHIUse); + if (!NewSucc) { + DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " + "break critical edge\n"); + return false; + } + + DEBUG(dbgs() << " *** Splitting critical edge:" + " BB#" << ParentBlock->getNumber() + << " -- BB#" << NewSucc->getNumber() + << " -- BB#" << SuccToSinkTo->getNumber() << '\n'); + SuccToSinkTo = NewSucc; + ++NumSplit; + } + // Determine where to insert into. Skip phi nodes. MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); - while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) { - MachineInstr *PHI = &*InsertPos; + while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) ++InsertPos; - if (SplitEdges && PHIUses.count(PHI)) { - if (NumSplit == SplitLimit) - return false; - - // A PHI use is in the destination successor so we can't sink the - // instruction here. Break the critical edge first! - for (unsigned i = 1, e = PHI->getNumOperands(); i != e; i += 2) { - unsigned SrcReg = PHI->getOperand(i).getReg(); - if (Defs.count(SrcReg)) { - MachineBasicBlock *SrcMBB = PHI->getOperand(i+1).getMBB(); - MachineBasicBlock *NewSucc = - SplitCriticalEdge(MI, SrcMBB, SuccToSinkTo, HasNonPHIUse); - if (!NewSucc) { - DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " - "break critical edge\n"); - return false; - } - - DEBUG(dbgs() << " *** Splitting critical edge:" - " BB#" << SrcMBB->getNumber() - << " -- BB#" << NewSucc->getNumber() - << " -- BB#" << SuccToSinkTo->getNumber() << '\n'); - SuccToSinkTo = NewSucc; - InsertPos = NewSucc->begin(); - ++NumSplit; - break; - } - } - } - } - // Move the instruction. SuccToSinkTo->splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); From baldrick at free.fr Sat Sep 18 03:18:49 2010 From: baldrick at free.fr (Duncan Sands) Date: Sat, 18 Sep 2010 10:18:49 +0200 Subject: [llvm-commits] Detect Intel CPU family: 6 model number: 37 as Core i7 In-Reply-To: References: Message-ID: <4C9475E9.2070606@free.fr> Hi ?smail, > I have a late MacBook Pro 2010 laptop, equipped with Core i7; I think it would be better to find the Intel docs that describe all of their recent processors, and add them all in one fell swoop. Otherwise we will end up with a random list of models where someone happened to notice that their machine was detected wrong. Ciao, Duncan. From bigcheesegs at gmail.com Sat Sep 18 03:32:32 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Sat, 18 Sep 2010 08:32:32 -0000 Subject: [llvm-commits] [llvm] r114271 - /llvm/trunk/docs/GettingStartedVS.html Message-ID: <20100918083232.ADC072A6C12C@llvm.org> Author: mspencer Date: Sat Sep 18 03:32:32 2010 New Revision: 114271 URL: http://llvm.org/viewvc/llvm-project?rev=114271&view=rev Log: docs: Tweak wording. Modified: llvm/trunk/docs/GettingStartedVS.html Modified: llvm/trunk/docs/GettingStartedVS.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStartedVS.html?rev=114271&r1=114270&r2=114271&view=diff ============================================================================== --- llvm/trunk/docs/GettingStartedVS.html (original) +++ llvm/trunk/docs/GettingStartedVS.html Sat Sep 18 03:32:32 2010 @@ -40,9 +40,9 @@
        -

        Welcome to LLVM on Windows! This document only covers native Windows, not - mingw or cygwin. In order to get started, you first need to know some basic - information.

        +

        Welcome to LLVM on Windows! This document only covers LLVM on Windows using + Visual Studio, not mingw or cygwin. In order to get started, you first need to + know some basic information.

        There are many different projects that compose LLVM. The first is the LLVM suite. This contains all of the tools, libraries, and header files needed to @@ -52,14 +52,14 @@

        Another useful project on Windows is clang. Clang is a C family - ([Objective]C/C++) compiler. Clang fully works on Windows, but does not + ([Objective]C/C++) compiler. Clang mostly works on Windows, but does not currently understand all of the Microsoft extensions to C and C++. Because of this, clang cannot parse the C++ standard library included with Visual Studio, nor parts of the Windows Platform SDK. However, most standard C programs do compile. Clang can be used to emit bitcode, directly emit object files or even linked executables using Visual Studio's link.exe

        -

        The LLVM test suite cannot be run on the Visual Studio port at this +

        The large LLVM test suite cannot be run on the Visual Studio port at this time.

        Most of the tools build and work. bugpoint does build, but does From lhames at gmail.com Sat Sep 18 04:07:10 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 18 Sep 2010 09:07:10 -0000 Subject: [llvm-commits] [llvm] r114272 - in /llvm/trunk: include/llvm/CodeGen/PBQP/ include/llvm/CodeGen/PBQP/Solution.h include/llvm/CodeGen/RegAllocPBQP.h lib/CodeGen/PBQP/ lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20100918090710.482542A6C12C@llvm.org> Author: lhames Date: Sat Sep 18 04:07:10 2010 New Revision: 114272 URL: http://llvm.org/viewvc/llvm-project?rev=114272&view=rev Log: Added a separate class (PBQPBuilder) for PBQP Problem construction. This class can be extended to support custom constraints. For now the allocator still uses the old (internal) construction mechanism by default. This will be phased out soon assuming no issues with the builder system come up. To invoke the new construction mechanism just pass '-regalloc=pbqp -pbqp-builder' to llc. To provide custom constraints a Target just needs to extend PBQPBuilder and pass an instance of their derived builder to the RegAllocPBQP constructor. Added: llvm/trunk/include/llvm/CodeGen/PBQP/ - copied from r113673, llvm/trunk/lib/CodeGen/PBQP/ llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Removed: llvm/trunk/lib/CodeGen/PBQP/ Modified: llvm/trunk/include/llvm/CodeGen/PBQP/Solution.h llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/include/llvm/CodeGen/PBQP/Solution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PBQP/Solution.h?rev=114272&r1=113673&r2=114272&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PBQP/Solution.h (original) +++ llvm/trunk/include/llvm/CodeGen/PBQP/Solution.h Sat Sep 18 04:07:10 2010 @@ -27,7 +27,8 @@ class Solution { private: - typedef std::map SelectionsMap; + typedef std::map SelectionsMap; SelectionsMap selections; unsigned r0Reductions, r1Reductions, r2Reductions, rNReductions; @@ -80,7 +81,7 @@ /// \brief Get a node's selection. /// @param nItr Node iterator. /// @return The selection for nItr; - unsigned getSelection(Graph::NodeItr nItr) const { + unsigned getSelection(Graph::ConstNodeItr nItr) const { SelectionsMap::const_iterator sItr = selections.find(nItr); assert(sItr != selections.end() && "No selection for node."); return sItr->second; Added: llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h?rev=114272&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h (added) +++ llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Sat Sep 18 04:07:10 2010 @@ -0,0 +1,260 @@ +//===-- RegAllocPBQP.h ------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the PBQPBuilder interface, for classes which build PBQP +// instances to represent register allocation problems, and the RegAllocPBQP +// interface. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_REGALLOCPBQP_H +#define LLVM_CODEGEN_REGALLOCPBQP_H + +#include "llvm/ADT/DenseMap.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/PBQP/Graph.h" +#include "llvm/CodeGen/PBQP/Solution.h" + +#include + +namespace llvm { + + class LiveInterval; + class MachineFunction; + + /// This class wraps up a PBQP instance representing a register allocation + /// problem, plus the structures necessary to map back from the PBQP solution + /// to a register allocation solution. (i.e. The PBQP-node <--> vreg map, + /// and the PBQP option <--> storage location map). + + class PBQPRAProblem { + public: + + typedef SmallVector AllowedSet; + + PBQP::Graph& getGraph() { return graph; } + + const PBQP::Graph& getGraph() const { return graph; } + + /// Record the mapping between the given virtual register and PBQP node, + /// and the set of allowed pregs for the vreg. + /// + /// If you are extending + /// PBQPBuilder you are unlikely to need this: Nodes and options for all + /// vregs will already have been set up for you by the base class. + template + void recordVReg(unsigned vreg, PBQP::Graph::NodeItr node, + AllowedRegsItr arBegin, AllowedRegsItr arEnd) { + assert(node2VReg.find(node) == node2VReg.end() && "Re-mapping node."); + assert(vreg2Node.find(vreg) == vreg2Node.end() && "Re-mapping vreg."); + assert(allowedSets[vreg].empty() && "vreg already has pregs."); + + node2VReg[node] = vreg; + vreg2Node[vreg] = node; + std::copy(arBegin, arEnd, std::back_inserter(allowedSets[vreg])); + } + + /// Get the virtual register corresponding to the given PBQP node. + unsigned getVRegForNode(PBQP::Graph::ConstNodeItr node) const; + + /// Get the PBQP node corresponding to the given virtual register. + PBQP::Graph::NodeItr getNodeForVReg(unsigned vreg) const; + + /// Returns true if the given PBQP option represents a physical register, + /// false otherwise. + bool isPRegOption(unsigned vreg, unsigned option) const { + // At present we only have spills or pregs, so anything that's not a + // spill is a preg. (This might be extended one day to support remat). + return !isSpillOption(vreg, option); + } + + /// Returns true if the given PBQP option represents spilling, false + /// otherwise. + bool isSpillOption(unsigned vreg, unsigned option) const { + // We hardcode option zero as the spill option. + return option == 0; + } + + /// Returns the allowed set for the given virtual register. + const AllowedSet& getAllowedSet(unsigned vreg) const; + + /// Get PReg for option. + unsigned getPRegForOption(unsigned vreg, unsigned option) const; + + private: + + typedef std::map Node2VReg; + typedef DenseMap VReg2Node; + typedef std::map AllowedSetMap; + + PBQP::Graph graph; + Node2VReg node2VReg; + VReg2Node vreg2Node; + + AllowedSetMap allowedSets; + + }; + + /// Builds PBQP instances to represent register allocation problems. Includes + /// spill, interference and coalescing costs by default. You can extend this + /// class to support additional constraints for your architecture. + class PBQPBuilder { + private: + PBQPBuilder(const PBQPBuilder&) {} + void operator=(const PBQPBuilder&) {} + public: + + typedef std::set RegSet; + + + /// Default constructor. + PBQPBuilder() {} + + /// Clean up a PBQPBuilder. + virtual ~PBQPBuilder() {} + + /// Build a PBQP instance to represent the register allocation problem for + /// the given MachineFunction. + virtual std::auto_ptr build( + MachineFunction *mf, + const LiveIntervals *lis, + const RegSet &vregs); + private: + + void addSpillCosts(PBQP::Vector &costVec, PBQP::PBQPNum spillCost); + + void addInterferenceCosts(PBQP::Matrix &costMat, + const PBQPRAProblem::AllowedSet &vr1Allowed, + const PBQPRAProblem::AllowedSet &vr2Allowed, + const TargetRegisterInfo *tri); + }; + + /// + /// PBQP based allocators solve the register allocation problem by mapping + /// register allocation problems to Partitioned Boolean Quadratic + /// Programming problems. + class RegAllocPBQP : public MachineFunctionPass { + public: + + static char ID; + + /// Construct a PBQP register allocator. + RegAllocPBQP(std::auto_ptr b) : MachineFunctionPass(ID), builder(b) {} + + /// Return the pass name. + virtual const char* getPassName() const { + return "PBQP Register Allocator"; + } + + /// PBQP analysis usage. + virtual void getAnalysisUsage(AnalysisUsage &au) const; + + /// Perform register allocation + virtual bool runOnMachineFunction(MachineFunction &MF); + + private: + + typedef std::map LI2NodeMap; + typedef std::vector Node2LIMap; + typedef std::vector AllowedSet; + typedef std::vector AllowedSetMap; + typedef std::pair RegPair; + typedef std::map CoalesceMap; + typedef std::vector NodeVector; + typedef std::set RegSet; + + + std::auto_ptr builder; + + MachineFunction *mf; + const TargetMachine *tm; + const TargetRegisterInfo *tri; + const TargetInstrInfo *tii; + const MachineLoopInfo *loopInfo; + MachineRegisterInfo *mri; + RenderMachineFunction *rmf; + + LiveIntervals *lis; + LiveStacks *lss; + VirtRegMap *vrm; + + LI2NodeMap li2Node; + Node2LIMap node2LI; + AllowedSetMap allowedSets; + RegSet vregsToAlloc, emptyIntervalVRegs; + NodeVector problemNodes; + + + /// Builds a PBQP cost vector. + template + PBQP::Vector buildCostVector(unsigned vReg, + const RegContainer &allowed, + const CoalesceMap &cealesces, + PBQP::PBQPNum spillCost) const; + + /// \brief Builds a PBQP interference matrix. + /// + /// @return Either a pointer to a non-zero PBQP matrix representing the + /// allocation option costs, or a null pointer for a zero matrix. + /// + /// Expects allowed sets for two interfering LiveIntervals. These allowed + /// sets should contain only allocable registers from the LiveInterval's + /// register class, with any interfering pre-colored registers removed. + template + PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1, + const RegContainer &allowed2) const; + + /// + /// Expects allowed sets for two potentially coalescable LiveIntervals, + /// and an estimated benefit due to coalescing. The allowed sets should + /// contain only allocable registers from the LiveInterval's register + /// classes, with any interfering pre-colored registers removed. + template + PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1, + const RegContainer &allowed2, + PBQP::PBQPNum cBenefit) const; + + /// \brief Finds coalescing opportunities and returns them as a map. + /// + /// Any entries in the map are guaranteed coalescable, even if their + /// corresponding live intervals overlap. + CoalesceMap findCoalesces(); + + /// \brief Finds the initial set of vreg intervals to allocate. + void findVRegIntervalsToAlloc(); + + /// \brief Constructs a PBQP problem representation of the register + /// allocation problem for this function. + /// + /// @return a PBQP solver object for the register allocation problem. + PBQP::Graph constructPBQPProblem(); + + /// \brief Adds a stack interval if the given live interval has been + /// spilled. Used to support stack slot coloring. + void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri); + + /// \brief Given a solved PBQP problem maps this solution back to a register + /// assignment. + bool mapPBQPToRegAlloc(const PBQP::Solution &solution); + + /// \brief Given a solved PBQP problem maps this solution back to a register + /// assignment. + bool mapPBQPToRegAlloc2(const PBQPRAProblem &problem, + const PBQP::Solution &solution); + + /// \brief Postprocessing before final spilling. Sets basic block "live in" + /// variables. + void finalizeAlloc() const; + + }; + +} + +#endif /* LLVM_CODEGEN_REGALLOCPBQP_H */ Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114272&r1=114271&r2=114272&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sat Sep 18 04:07:10 2010 @@ -31,9 +31,6 @@ #define DEBUG_TYPE "regalloc" -#include "PBQP/HeuristicSolver.h" -#include "PBQP/Graph.h" -#include "PBQP/Heuristics/Briggs.h" #include "RenderMachineFunction.h" #include "Splitter.h" #include "VirtRegMap.h" @@ -41,9 +38,13 @@ #include "llvm/CodeGen/CalcSpillWeights.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/RegAllocPBQP.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PBQP/HeuristicSolver.h" +#include "llvm/CodeGen/PBQP/Graph.h" +#include "llvm/CodeGen/PBQP/Heuristics/Briggs.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/Support/Debug.h" @@ -51,12 +52,14 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include -#include #include #include #include -using namespace llvm; +namespace llvm { + +using namespace PBQP; + using namespace PBQP::Heuristics; static RegisterRegAlloc registerPBQPRepAlloc("pbqp", "PBQP register allocator", @@ -68,156 +71,212 @@ cl::init(false), cl::Hidden); static cl::opt +pbqpBuilder("pbqp-builder", + cl::desc("Use new builder system."), + cl::init(false), cl::Hidden); + + +static cl::opt pbqpPreSplitting("pbqp-pre-splitting", cl::desc("Pre-splite before PBQP register allocation."), cl::init(false), cl::Hidden); -namespace { +char RegAllocPBQP::ID = 0; + +unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const { + Node2VReg::const_iterator vregItr = node2VReg.find(node); + assert(vregItr != node2VReg.end() && "No vreg for node."); + return vregItr->second; +} + +PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const { + VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg); + assert(nodeItr != vreg2Node.end() && "No node for vreg."); + return nodeItr->second; + +} - /// - /// PBQP based allocators solve the register allocation problem by mapping - /// register allocation problems to Partitioned Boolean Quadratic - /// Programming problems. - class PBQPRegAlloc : public MachineFunctionPass { - public: - - static char ID; - - /// Construct a PBQP register allocator. - PBQPRegAlloc() : MachineFunctionPass(ID) {} - - /// Return the pass name. - virtual const char* getPassName() const { - return "PBQP Register Allocator"; - } - - /// PBQP analysis usage. - virtual void getAnalysisUsage(AnalysisUsage &au) const { - au.addRequired(); - au.addPreserved(); - au.addRequired(); - //au.addRequiredID(SplitCriticalEdgesID); - au.addRequired(); - au.addRequired(); - au.addRequired(); - au.addPreserved(); - au.addRequired(); - au.addPreserved(); - if (pbqpPreSplitting) - au.addRequired(); - au.addRequired(); - au.addRequired(); - MachineFunctionPass::getAnalysisUsage(au); - } - - /// Perform register allocation - virtual bool runOnMachineFunction(MachineFunction &MF); - - private: - - class LIOrdering { - public: - bool operator()(const LiveInterval *li1, const LiveInterval *li2) const { - return li1->reg < li2->reg; - } - }; - - typedef std::map LI2NodeMap; - typedef std::vector Node2LIMap; - typedef std::vector AllowedSet; - typedef std::vector AllowedSetMap; - typedef std::set RegSet; - typedef std::pair RegPair; - typedef std::map CoalesceMap; - - typedef std::set LiveIntervalSet; - - typedef std::vector NodeVector; - - MachineFunction *mf; - const TargetMachine *tm; - const TargetRegisterInfo *tri; - const TargetInstrInfo *tii; - const MachineLoopInfo *loopInfo; - MachineRegisterInfo *mri; - RenderMachineFunction *rmf; - - LiveIntervals *lis; - LiveStacks *lss; - VirtRegMap *vrm; - - LI2NodeMap li2Node; - Node2LIMap node2LI; - AllowedSetMap allowedSets; - LiveIntervalSet vregIntervalsToAlloc, - emptyVRegIntervals; - NodeVector problemNodes; - - - /// Builds a PBQP cost vector. - template - PBQP::Vector buildCostVector(unsigned vReg, - const RegContainer &allowed, - const CoalesceMap &cealesces, - PBQP::PBQPNum spillCost) const; - - /// \brief Builds a PBQP interference matrix. - /// - /// @return Either a pointer to a non-zero PBQP matrix representing the - /// allocation option costs, or a null pointer for a zero matrix. - /// - /// Expects allowed sets for two interfering LiveIntervals. These allowed - /// sets should contain only allocable registers from the LiveInterval's - /// register class, with any interfering pre-colored registers removed. - template - PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1, - const RegContainer &allowed2) const; - - /// - /// Expects allowed sets for two potentially coalescable LiveIntervals, - /// and an estimated benefit due to coalescing. The allowed sets should - /// contain only allocable registers from the LiveInterval's register - /// classes, with any interfering pre-colored registers removed. - template - PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1, - const RegContainer &allowed2, - PBQP::PBQPNum cBenefit) const; - - /// \brief Finds coalescing opportunities and returns them as a map. - /// - /// Any entries in the map are guaranteed coalescable, even if their - /// corresponding live intervals overlap. - CoalesceMap findCoalesces(); - - /// \brief Finds the initial set of vreg intervals to allocate. - void findVRegIntervalsToAlloc(); - - /// \brief Constructs a PBQP problem representation of the register - /// allocation problem for this function. - /// - /// @return a PBQP solver object for the register allocation problem. - PBQP::Graph constructPBQPProblem(); - - /// \brief Adds a stack interval if the given live interval has been - /// spilled. Used to support stack slot coloring. - void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri); - - /// \brief Given a solved PBQP problem maps this solution back to a register - /// assignment. - bool mapPBQPToRegAlloc(const PBQP::Solution &solution); - - /// \brief Postprocessing before final spilling. Sets basic block "live in" - /// variables. - void finalizeAlloc() const; +const PBQPRAProblem::AllowedSet& + PBQPRAProblem::getAllowedSet(unsigned vreg) const { + AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg); + assert(allowedSetItr != allowedSets.end() && "No pregs for vreg."); + const AllowedSet &allowedSet = allowedSetItr->second; + return allowedSet; +} - }; +unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const { + assert(isPRegOption(vreg, option) && "Not a preg option."); - char PBQPRegAlloc::ID = 0; + const AllowedSet& allowedSet = getAllowedSet(vreg); + assert(option <= allowedSet.size() && "Option outside allowed set."); + return allowedSet[option - 1]; } +std::auto_ptr PBQPBuilder::build( + MachineFunction *mf, + const LiveIntervals *lis, + const RegSet &vregs) { + + typedef std::vector LIVector; + + MachineRegisterInfo *mri = &mf->getRegInfo(); + const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo(); + + std::auto_ptr p(new PBQPRAProblem()); + PBQP::Graph &g = p->getGraph(); + RegSet pregs; + + // Collect the set of preg intervals, record that they're used in the MF. + for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end(); + itr != end; ++itr) { + if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { + pregs.insert(itr->first); + mri->setPhysRegUsed(itr->first); + } + } + + BitVector reservedRegs = tri->getReservedRegs(*mf); + + // Iterate over vregs. + for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end(); + vregItr != vregEnd; ++vregItr) { + unsigned vreg = *vregItr; + const TargetRegisterClass *trc = mri->getRegClass(vreg); + const LiveInterval *vregLI = &lis->getInterval(vreg); + + // Compute an initial allowed set for the current vreg. + typedef std::vector VRAllowed; + VRAllowed vrAllowed; + for (TargetRegisterClass::iterator aoItr = trc->allocation_order_begin(*mf), + aoEnd = trc->allocation_order_end(*mf); + aoItr != aoEnd; ++aoItr) { + unsigned preg = *aoItr; + if (!reservedRegs.test(preg)) { + vrAllowed.push_back(preg); + } + } + + // Remove any physical registers which overlap. + for (RegSet::const_iterator pregItr = pregs.begin(), + pregEnd = pregs.end(); + pregItr != pregEnd; ++pregItr) { + unsigned preg = *pregItr; + const LiveInterval *pregLI = &lis->getInterval(preg); + + if (pregLI->empty()) + continue; + + if (!vregLI->overlaps(*pregLI)) + continue; + + // Remove the register from the allowed set. + VRAllowed::iterator eraseItr = + std::find(vrAllowed.begin(), vrAllowed.end(), preg); + + if (eraseItr != vrAllowed.end()) { + vrAllowed.erase(eraseItr); + } + + // Also remove any aliases. + const unsigned *aliasItr = tri->getAliasSet(preg); + if (aliasItr != 0) { + for (; *aliasItr != 0; ++aliasItr) { + VRAllowed::iterator eraseItr = + std::find(vrAllowed.begin(), vrAllowed.end(), *aliasItr); + + if (eraseItr != vrAllowed.end()) { + vrAllowed.erase(eraseItr); + } + } + } + } + + // Construct the node. + PBQP::Graph::NodeItr node = + g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0)); + + // Record the mapping and allowed set in the problem. + p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end()); + + PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ? + vregLI->weight : std::numeric_limits::min(); + + addSpillCosts(g.getNodeCosts(node), spillCost); + } + + for (RegSet::iterator vr1Itr = vregs.begin(), vrEnd = vregs.end(); + vr1Itr != vrEnd; ++vr1Itr) { + unsigned vr1 = *vr1Itr; + const LiveInterval &l1 = lis->getInterval(vr1); + const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1); + + for (RegSet::iterator vr2Itr = llvm::next(vr1Itr); + vr2Itr != vrEnd; ++vr2Itr) { + unsigned vr2 = *vr2Itr; + const LiveInterval &l2 = lis->getInterval(vr2); + const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2); + + assert(!l2.empty() && "Empty interval in vreg set?"); + if (l1.overlaps(l2)) { + PBQP::Graph::EdgeItr edge = + g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2), + PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0)); + + addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri); + } + } + } + + return p; +} + +void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec, + PBQP::PBQPNum spillCost) { + costVec[0] = spillCost; +} + +void PBQPBuilder::addInterferenceCosts(PBQP::Matrix &costMat, + const PBQPRAProblem::AllowedSet &vr1Allowed, + const PBQPRAProblem::AllowedSet &vr2Allowed, + const TargetRegisterInfo *tri) { + assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch."); + assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch."); + + for (unsigned i = 0; i < vr1Allowed.size(); ++i) { + unsigned preg1 = vr1Allowed[i]; + + for (unsigned j = 0; j < vr2Allowed.size(); ++j) { + unsigned preg2 = vr2Allowed[j]; + + if (tri->regsOverlap(preg1, preg2)) { + costMat[i + 1][j + 1] = std::numeric_limits::infinity(); + } + } + } +} + + + +void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const { + au.addRequired(); + au.addPreserved(); + au.addRequired(); + //au.addRequiredID(SplitCriticalEdgesID); + au.addRequired(); + au.addRequired(); + au.addRequired(); + au.addPreserved(); + au.addRequired(); + au.addPreserved(); + if (pbqpPreSplitting) + au.addRequired(); + au.addRequired(); + au.addRequired(); + MachineFunctionPass::getAnalysisUsage(au); +} template -PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg, +PBQP::Vector RegAllocPBQP::buildCostVector(unsigned vReg, const RegContainer &allowed, const CoalesceMap &coalesces, PBQP::PBQPNum spillCost) const { @@ -252,7 +311,7 @@ } template -PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix( +PBQP::Matrix* RegAllocPBQP::buildInterferenceMatrix( const RegContainer &allowed1, const RegContainer &allowed2) const { typedef typename RegContainer::const_iterator RegContainerIterator; @@ -318,7 +377,7 @@ } template -PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix( +PBQP::Matrix* RegAllocPBQP::buildCoalescingMatrix( const RegContainer &allowed1, const RegContainer &allowed2, PBQP::PBQPNum cBenefit) const { @@ -379,7 +438,7 @@ return m; } -PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { +RegAllocPBQP::CoalesceMap RegAllocPBQP::findCoalesces() { typedef MachineFunction::const_iterator MFIterator; typedef MachineBasicBlock::const_iterator MBBIterator; @@ -516,7 +575,7 @@ return coalescesFound; } -void PBQPRegAlloc::findVRegIntervalsToAlloc() { +void RegAllocPBQP::findVRegIntervalsToAlloc() { // Iterate over all live ranges. for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); @@ -532,15 +591,15 @@ // Empty intervals we allocate in a simple post-processing stage in // finalizeAlloc. if (!li->empty()) { - vregIntervalsToAlloc.insert(li); + vregsToAlloc.insert(li->reg); } else { - emptyVRegIntervals.insert(li); + emptyIntervalVRegs.insert(li->reg); } } } -PBQP::Graph PBQPRegAlloc::constructPBQPProblem() { +PBQP::Graph RegAllocPBQP::constructPBQPProblem() { typedef std::vector LIVector; typedef std::vector RegVector; @@ -565,10 +624,10 @@ // Iterate over vreg intervals, construct live interval <-> node number // mappings. - for (LiveIntervalSet::const_iterator - itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); + for (RegSet::const_iterator itr = vregsToAlloc.begin(), + end = vregsToAlloc.end(); itr != end; ++itr) { - const LiveInterval *li = *itr; + const LiveInterval *li = &lis->getInterval(*itr); li2Node[li] = node2LI.size(); node2LI.push_back(li); @@ -583,10 +642,10 @@ // Construct a PBQP solver for this problem PBQP::Graph problem; - problemNodes.resize(vregIntervalsToAlloc.size()); + problemNodes.resize(vregsToAlloc.size()); // Resize allowedSets container appropriately. - allowedSets.resize(vregIntervalsToAlloc.size()); + allowedSets.resize(vregsToAlloc.size()); BitVector ReservedRegs = tri->getReservedRegs(*mf); @@ -617,8 +676,10 @@ // If we get here then the live intervals overlap, but we're still ok // if they're coalescable. - if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) + if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) { + DEBUG(dbgs() << "CoalescingOverride: (" << li->reg << ", " << pReg << ")\n"); continue; + } // If we get here then we have a genuine exclusion. @@ -703,7 +764,7 @@ return problem; } -void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, +void RegAllocPBQP::addStackInterval(const LiveInterval *spilled, MachineRegisterInfo* mri) { int stackSlot = vrm->getStackSlot(spilled->reg); @@ -724,7 +785,7 @@ stackInterval.MergeRangesInAsValue(rhsInterval, vni); } -bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) { +bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQP::Solution &solution) { // Set to true if we have any spills bool anotherRoundNeeded = false; @@ -744,7 +805,7 @@ unsigned physReg = allowedSets[node][allocSelection - 1]; DEBUG(dbgs() << "VREG " << virtReg << " -> " - << tri->getName(physReg) << "\n"); + << tri->getName(physReg) << " (Option: " << allocSelection << ")\n"); assert(physReg != 0); @@ -756,7 +817,7 @@ // Make sure we ignore this virtual reg on the next round // of allocation - vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); + vregsToAlloc.erase(virtReg); // Insert spill ranges for this live range const LiveInterval *spillInterval = node2LI[node]; @@ -769,7 +830,7 @@ rmf->rememberSpills(spillInterval, newSpills); (void) oldSpillWeight; - DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: " + DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Option: 0, Cost: " << oldSpillWeight << ", New vregs: "); // Copy any newly inserted live intervals into the list of regs to @@ -782,28 +843,88 @@ DEBUG(dbgs() << (*itr)->reg << " "); - vregIntervalsToAlloc.insert(*itr); + vregsToAlloc.insert((*itr)->reg); + } + + DEBUG(dbgs() << ")\n"); + + // We need another round if spill intervals were added. + anotherRoundNeeded |= !newSpills.empty(); + } + } + + return !anotherRoundNeeded; +} + +bool RegAllocPBQP::mapPBQPToRegAlloc2(const PBQPRAProblem &problem, + const PBQP::Solution &solution) { + // Set to true if we have any spills + bool anotherRoundNeeded = false; + + // Clear the existing allocation. + vrm->clearAllVirt(); + + const PBQP::Graph &g = problem.getGraph(); + // Iterate over the nodes mapping the PBQP solution to a register + // assignment. + for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(), + nodeEnd = g.nodesEnd(); + node != nodeEnd; ++node) { + unsigned vreg = problem.getVRegForNode(node); + unsigned alloc = solution.getSelection(node); + + if (problem.isPRegOption(vreg, alloc)) { + unsigned preg = problem.getPRegForOption(vreg, alloc); + DEBUG(dbgs() << "VREG " << vreg << " -> " << tri->getName(preg) << "\n"); + assert(preg != 0 && "Invalid preg selected."); + vrm->assignVirt2Phys(vreg, preg); + } else if (problem.isSpillOption(vreg, alloc)) { + vregsToAlloc.erase(vreg); + const LiveInterval* spillInterval = &lis->getInterval(vreg); + double oldWeight = spillInterval->weight; + SmallVector spillIs; + rmf->rememberUseDefs(spillInterval); + std::vector newSpills = + lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm); + addStackInterval(spillInterval, mri); + rmf->rememberSpills(spillInterval, newSpills); + + (void) oldWeight; + DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: " + << oldWeight << ", New vregs: "); + + // Copy any newly inserted live intervals into the list of regs to + // allocate. + for (std::vector::const_iterator + itr = newSpills.begin(), end = newSpills.end(); + itr != end; ++itr) { + assert(!(*itr)->empty() && "Empty spill range."); + DEBUG(dbgs() << (*itr)->reg << " "); + vregsToAlloc.insert((*itr)->reg); } DEBUG(dbgs() << ")\n"); // We need another round if spill intervals were added. anotherRoundNeeded |= !newSpills.empty(); + } else { + assert(false && "Unknown allocation option."); } } return !anotherRoundNeeded; } -void PBQPRegAlloc::finalizeAlloc() const { + +void RegAllocPBQP::finalizeAlloc() const { typedef LiveIntervals::iterator LIIterator; typedef LiveInterval::Ranges::const_iterator LRIterator; // First allocate registers for the empty intervals. - for (LiveIntervalSet::const_iterator - itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); + for (RegSet::const_iterator + itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end(); itr != end; ++itr) { - LiveInterval *li = *itr; + LiveInterval *li = &lis->getInterval(*itr); unsigned physReg = vrm->getRegAllocPref(li->reg); @@ -863,7 +984,7 @@ } -bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { +bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { mf = &MF; tm = &mf->getTarget(); @@ -894,21 +1015,36 @@ findVRegIntervalsToAlloc(); // If there are non-empty intervals allocate them using pbqp. - if (!vregIntervalsToAlloc.empty()) { + if (!vregsToAlloc.empty()) { bool pbqpAllocComplete = false; unsigned round = 0; - while (!pbqpAllocComplete) { - DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n"); + if (!pbqpBuilder) { + while (!pbqpAllocComplete) { + DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n"); + + PBQP::Graph problem = constructPBQPProblem(); + PBQP::Solution solution = + PBQP::HeuristicSolver::solve(problem); + + pbqpAllocComplete = mapPBQPToRegAlloc(solution); - PBQP::Graph problem = constructPBQPProblem(); - PBQP::Solution solution = - PBQP::HeuristicSolver::solve(problem); + ++round; + } + } else { + while (!pbqpAllocComplete) { + DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n"); + + std::auto_ptr problem = + builder->build(mf, lis, vregsToAlloc); + PBQP::Solution solution = + HeuristicSolver::solve(problem->getGraph()); - pbqpAllocComplete = mapPBQPToRegAlloc(solution); + pbqpAllocComplete = mapPBQPToRegAlloc2(*problem, solution); - ++round; + ++round; + } } } @@ -917,8 +1053,8 @@ rmf->renderMachineFunction("After PBQP register allocation.", vrm); - vregIntervalsToAlloc.clear(); - emptyVRegIntervals.clear(); + vregsToAlloc.clear(); + emptyIntervalVRegs.clear(); li2Node.clear(); node2LI.clear(); allowedSets.clear(); @@ -934,9 +1070,10 @@ return true; } -FunctionPass* llvm::createPBQPRegisterAllocator() { - return new PBQPRegAlloc(); +FunctionPass* createPBQPRegisterAllocator() { + return new RegAllocPBQP(std::auto_ptr(new PBQPBuilder())); } +} #undef DEBUG_TYPE From lhames at gmail.com Sat Sep 18 04:49:08 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 18 Sep 2010 09:49:08 -0000 Subject: [llvm-commits] [llvm] r114273 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20100918094908.ECF722A6C12C@llvm.org> Author: lhames Date: Sat Sep 18 04:49:08 2010 New Revision: 114273 URL: http://llvm.org/viewvc/llvm-project?rev=114273&view=rev Log: Fixed non-const iterator error. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114273&r1=114272&r2=114273&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sat Sep 18 04:49:08 2010 @@ -204,7 +204,7 @@ addSpillCosts(g.getNodeCosts(node), spillCost); } - for (RegSet::iterator vr1Itr = vregs.begin(), vrEnd = vregs.end(); + for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end(); vr1Itr != vrEnd; ++vr1Itr) { unsigned vr1 = *vr1Itr; const LiveInterval &l1 = lis->getInterval(vr1); From ggreif at gmail.com Sat Sep 18 06:48:36 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 11:48:36 -0000 Subject: [llvm-commits] [llvm] r114275 - /llvm/trunk/include/llvm/Support/CallSite.h Message-ID: <20100918114836.9B0C42A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 06:48:36 2010 New Revision: 114275 URL: http://llvm.org/viewvc/llvm-project?rev=114275&view=rev Log: remove CallSite::get; it is still present (as protected) in the baseclass, use one of the constructors intead Modified: llvm/trunk/include/llvm/Support/CallSite.h Modified: llvm/trunk/include/llvm/Support/CallSite.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=114275&r1=114274&r2=114275&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CallSite.h (original) +++ llvm/trunk/include/llvm/Support/CallSite.h Sat Sep 18 06:48:36 2010 @@ -57,7 +57,7 @@ *this = get(II); assert(I.getPointer() && "Not a call?"); } - +protected: /// CallSiteBase::get - This static method is sort of like a constructor. It /// will create an appropriate call site for a Call or Invoke instruction, but /// it can also create a null initialized CallSiteBase object for something @@ -72,7 +72,7 @@ } return CallSiteBase(); } - +public: /// isCall - true if a CallInst is enclosed. /// Note that !isCall() does not mean it is an InvokeInst enclosed, /// it also could signify a NULL Instruction pointer. @@ -282,16 +282,6 @@ bool operator==(const CallSite &CS) const { return I == CS.I; } bool operator!=(const CallSite &CS) const { return I != CS.I; } - - /// CallSite::get - This static method is sort of like a constructor. It will - /// create an appropriate call site for a Call or Invoke instruction, but it - /// can also create a null initialized CallSite object for something which is - /// NOT a call site. - /// - static CallSite get(Value *V) { - return Base::get(V); - } - bool operator<(const CallSite &CS) const { return getInstruction() < CS.getInstruction(); } From ggreif at gmail.com Sat Sep 18 06:52:02 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 11:52:02 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r114276 - /llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Message-ID: <20100918115202.5B96B2A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 06:52:02 2010 New Revision: 114276 URL: http://llvm.org/viewvc/llvm-project?rev=114276&view=rev Log: do not rely on the implicit-dereference semantics of dyn_cast_or_null Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp?rev=114276&r1=114275&r2=114276&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-debug.cpp Sat Sep 18 06:52:02 2010 @@ -505,7 +505,7 @@ std::map::iterator I = RegionMap.find(Node); if (I != RegionMap.end()) - if (MDNode *R = dyn_cast_or_null(I->second)) + if (MDNode *R = dyn_cast_or_null(&*I->second)) return DIDescriptor(R); if (TYPE_P (Node)) { @@ -1004,7 +1004,7 @@ // descriptor. std::map::iterator I = TypeCache.find(type); if (I != TypeCache.end()) - if (MDNode *TN = dyn_cast_or_null(I->second)) + if (MDNode *TN = dyn_cast_or_null(&*I->second)) return DIType(TN); // forward declaration, From ggreif at gmail.com Sat Sep 18 06:53:39 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 11:53:39 -0000 Subject: [llvm-commits] [llvm] r114277 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20100918115339.ECA142A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 06:53:39 2010 New Revision: 114277 URL: http://llvm.org/viewvc/llvm-project?rev=114277&view=rev Log: do not rely on the implicit-dereference semantics of dyn_cast_or_null Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=114277&r1=114276&r2=114277&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Sat Sep 18 06:53:39 2010 @@ -346,7 +346,7 @@ PHIs.push_back(PN); for (unsigned i = 0, e = PHIs.size(); i != e; ++i) - if (PHINode *PN = dyn_cast_or_null(PHIs[i])) + if (PHINode *PN = dyn_cast_or_null(&*PHIs[i])) HandleFloatingPointIV(L, PN); // If the loop previously had floating-point IV, ScalarEvolution @@ -395,7 +395,7 @@ // which are now dead. while (!DeadInsts.empty()) if (Instruction *Inst = - dyn_cast_or_null(DeadInsts.pop_back_val())) + dyn_cast_or_null(&*DeadInsts.pop_back_val())) RecursivelyDeleteTriviallyDeadInstructions(Inst); } @@ -462,7 +462,7 @@ // which are now dead. while (!DeadInsts.empty()) if (Instruction *Inst = - dyn_cast_or_null(DeadInsts.pop_back_val())) + dyn_cast_or_null(&*DeadInsts.pop_back_val())) RecursivelyDeleteTriviallyDeadInstructions(Inst); } @@ -725,7 +725,7 @@ // which are now dead. while (!DeadInsts.empty()) if (Instruction *Inst = - dyn_cast_or_null(DeadInsts.pop_back_val())) + dyn_cast_or_null(&*DeadInsts.pop_back_val())) RecursivelyDeleteTriviallyDeadInstructions(Inst); } From ggreif at gmail.com Sat Sep 18 06:55:34 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 11:55:34 -0000 Subject: [llvm-commits] [llvm] r114278 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20100918115534.EB49F2A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 06:55:34 2010 New Revision: 114278 URL: http://llvm.org/viewvc/llvm-project?rev=114278&view=rev Log: do not rely on the implicit-dereference semantics of dyn_cast_or_null Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=114278&r1=114277&r2=114278&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sat Sep 18 06:55:34 2010 @@ -608,7 +608,7 @@ bool Changed = false; while (!DeadInsts.empty()) { - Instruction *I = dyn_cast_or_null(DeadInsts.pop_back_val()); + Instruction *I = dyn_cast_or_null(&*DeadInsts.pop_back_val()); if (I == 0 || !isInstructionTriviallyDead(I)) continue; From ismail at namtrac.org Sat Sep 18 07:28:45 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Sat, 18 Sep 2010 15:28:45 +0300 Subject: [llvm-commits] Detect Intel CPU family: 6 model number: 37 as Core i7 In-Reply-To: <4C9475E9.2070606@free.fr> References: <4C9475E9.2070606@free.fr> Message-ID: Hi Duncan; On Sat, Sep 18, 2010 at 11:18 AM, Duncan Sands wrote: > > Hi ?smail, > > > I have a late MacBook Pro 2010 laptop, equipped with Core i7; > > I think it would be better to find the Intel docs that describe all of > their recent processors, and add them all in one fell swoop. ?Otherwise > we will end up with a random list of models where someone happened to > notice that their machine was detected wrong. Indeed that would be good but their official document over at http://www.intel.com/Assets/PDF/appnote/241618.pdf does not mention all of the model numbers. It would be great if someone knows an updated document. Regards, ismail From ggreif at gmail.com Sat Sep 18 07:30:15 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 12:30:15 -0000 Subject: [llvm-commits] [llvm] r114279 - /llvm/trunk/include/llvm/Support/Casting.h Message-ID: <20100918123015.31D562A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 07:30:15 2010 New Revision: 114279 URL: http://llvm.org/viewvc/llvm-project?rev=114279&view=rev Log: restrict dyn_cast_or_null to pointer types, just like cast_or_null Modified: llvm/trunk/include/llvm/Support/Casting.h Modified: llvm/trunk/include/llvm/Support/Casting.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Casting.h?rev=114279&r1=114278&r2=114279&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Casting.h (original) +++ llvm/trunk/include/llvm/Support/Casting.h Sat Sep 18 07:30:15 2010 @@ -232,8 +232,8 @@ // value is accepted. // template -inline typename cast_retty::ret_type dyn_cast_or_null(const Y &Val) { - return (Val && isa(Val)) ? cast(Val) : 0; +inline typename cast_retty::ret_type dyn_cast_or_null(Y *Val) { + return (Val && isa(Val)) ? cast(Val) : 0; } } // End llvm namespace From ggreif at gmail.com Sat Sep 18 07:56:47 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 12:56:47 -0000 Subject: [llvm-commits] [llvm] r114280 - /llvm/trunk/include/llvm/Support/Casting.h Message-ID: <20100918125647.5E3732A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 07:56:47 2010 New Revision: 114280 URL: http://llvm.org/viewvc/llvm-project?rev=114280&view=rev Log: back out r114279 as some darwin buildbots get errors compiling clang: svn merge -c -114279 llvm/include/llvm/Support/Casting.h Modified: llvm/trunk/include/llvm/Support/Casting.h Modified: llvm/trunk/include/llvm/Support/Casting.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Casting.h?rev=114280&r1=114279&r2=114280&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Casting.h (original) +++ llvm/trunk/include/llvm/Support/Casting.h Sat Sep 18 07:56:47 2010 @@ -232,8 +232,8 @@ // value is accepted. // template -inline typename cast_retty::ret_type dyn_cast_or_null(Y *Val) { - return (Val && isa(Val)) ? cast(Val) : 0; +inline typename cast_retty::ret_type dyn_cast_or_null(const Y &Val) { + return (Val && isa(Val)) ? cast(Val) : 0; } } // End llvm namespace From ggreif at gmail.com Sat Sep 18 08:03:32 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 13:03:32 -0000 Subject: [llvm-commits] [llvm] r114282 - /llvm/trunk/include/llvm/Support/Casting.h Message-ID: <20100918130332.F07EA2A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 08:03:32 2010 New Revision: 114282 URL: http://llvm.org/viewvc/llvm-project?rev=114282&view=rev Log: restrict dyn_cast_or_null to pointer types, just like cast_or_null; re-commit of r114279, backed out in r114280 Modified: llvm/trunk/include/llvm/Support/Casting.h Modified: llvm/trunk/include/llvm/Support/Casting.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Casting.h?rev=114282&r1=114281&r2=114282&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Casting.h (original) +++ llvm/trunk/include/llvm/Support/Casting.h Sat Sep 18 08:03:32 2010 @@ -232,8 +232,8 @@ // value is accepted. // template -inline typename cast_retty::ret_type dyn_cast_or_null(const Y &Val) { - return (Val && isa(Val)) ? cast(Val) : 0; +inline typename cast_retty::ret_type dyn_cast_or_null(Y *Val) { + return (Val && isa(Val)) ? cast(Val) : 0; } } // End llvm namespace From ggreif at gmail.com Sat Sep 18 09:27:02 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 18 Sep 2010 14:27:02 -0000 Subject: [llvm-commits] [dragonegg] r114283 - /dragonegg/trunk/llvm-debug.cpp Message-ID: <20100918142702.BE3522A6C12C@llvm.org> Author: ggreif Date: Sat Sep 18 09:27:02 2010 New Revision: 114283 URL: http://llvm.org/viewvc/llvm-project?rev=114283&view=rev Log: port r114276 from llvm-gcc Modified: dragonegg/trunk/llvm-debug.cpp Modified: dragonegg/trunk/llvm-debug.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-debug.cpp?rev=114283&r1=114282&r2=114283&view=diff ============================================================================== --- dragonegg/trunk/llvm-debug.cpp (original) +++ dragonegg/trunk/llvm-debug.cpp Sat Sep 18 09:27:02 2010 @@ -349,7 +349,7 @@ std::map::iterator I = RegionMap.find(Node); if (I != RegionMap.end()) - if (MDNode *R = dyn_cast_or_null(I->second)) + if (MDNode *R = dyn_cast_or_null(&*I->second)) return DIDescriptor(R); if (TYPE_P (Node)) { @@ -758,7 +758,7 @@ // descriptor. std::map::iterator I = TypeCache.find(type); if (I != TypeCache.end()) - if (MDNode *TN = dyn_cast_or_null(I->second)) + if (MDNode *TN = dyn_cast_or_null(&*I->second)) return DIType(TN); // forward declaration, From benny.kra at googlemail.com Sat Sep 18 09:41:26 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sat, 18 Sep 2010 14:41:26 -0000 Subject: [llvm-commits] [llvm] r114284 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20100918144126.827642A6C12C@llvm.org> Author: d0k Date: Sat Sep 18 09:41:26 2010 New Revision: 114284 URL: http://llvm.org/viewvc/llvm-project?rev=114284&view=rev Log: Unbreak msvc build. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114284&r1=114283&r2=114284&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sat Sep 18 09:41:26 2010 @@ -210,7 +210,7 @@ const LiveInterval &l1 = lis->getInterval(vr1); const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1); - for (RegSet::iterator vr2Itr = llvm::next(vr1Itr); + for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr); vr2Itr != vrEnd; ++vr2Itr) { unsigned vr2 = *vr2Itr; const LiveInterval &l2 = lis->getInterval(vr2); From rafael.espindola at gmail.com Sat Sep 18 10:03:21 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sat, 18 Sep 2010 15:03:21 -0000 Subject: [llvm-commits] [llvm] r114285 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp test/MC/ELF/file.s Message-ID: <20100918150321.EDA432A6C12C@llvm.org> Author: rafael Date: Sat Sep 18 10:03:21 2010 New Revision: 114285 URL: http://llvm.org/viewvc/llvm-project?rev=114285&view=rev Log: Make sure the STT_FILE symbol is the first one in the symbol table. Added: llvm/trunk/test/MC/ELF/file.s Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114285&r1=114284&r2=114285&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Sat Sep 18 10:03:21 2010 @@ -34,6 +34,15 @@ #include using namespace llvm; +static unsigned GetType(const MCSymbolData &SD) { + uint32_t Type = (SD.getFlags() & (0xf << ELF_STT_Shift)) >> ELF_STT_Shift; + assert(Type == ELF::STT_NOTYPE || Type == ELF::STT_OBJECT || + Type == ELF::STT_FUNC || Type == ELF::STT_SECTION || + Type == ELF::STT_FILE || Type == ELF::STT_COMMON || + Type == ELF::STT_TLS); + return Type; +} + namespace { class ELFObjectWriterImpl { @@ -64,6 +73,10 @@ // Support lexicographic sorting. bool operator<(const ELFSymbolData &RHS) const { + if (GetType(*SymbolData) == ELF::STT_FILE) + return true; + if (GetType(*RHS.SymbolData) == ELF::STT_FILE) + return false; return SymbolData->getSymbol().getName() < RHS.SymbolData->getSymbol().getName(); } Added: llvm/trunk/test/MC/ELF/file.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/file.s?rev=114285&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/file.s (added) +++ llvm/trunk/test/MC/ELF/file.s Sat Sep 18 10:03:21 2010 @@ -0,0 +1,23 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that the STT_FILE symbol precedes the other local symbols. + +.file "foo" +foa: +// CHECK: # Symbol 1 +// CHECK-NEXT: (('st_name', 1) # 'foo' +// CHECK-NEXT: ('st_bind', 0) +// CHECK-NEXT: ('st_type', 4) +// CHECK-NEXT: ('st_other', 0) +// CHECK-NEXT: ('st_shndx', 65521) +// CHECK-NEXT: ('st_value', 0) +// CHECK-NEXT: ('st_size', 0) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 2 +// CHECK-NEXT: (('st_name', 5) # 'foa' +// CHECK-NEXT: ('st_bind', 0) +// CHECK-NEXT: ('st_type', 0) +// CHECK-NEXT: ('st_other', 0) +// CHECK-NEXT: ('st_shndx', 1) +// CHECK-NEXT: ('st_value', 0) +// CHECK-NEXT: ('st_size', 0) From clchiou at gmail.com Sat Sep 18 12:31:03 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Sun, 19 Sep 2010 01:31:03 +0800 Subject: [llvm-commits] [PATCH] Add exit instruction to PTX backend In-Reply-To: <92FD1B35-9E05-4920-9C1B-CEE5B005D652@apple.com> References: <92FD1B35-9E05-4920-9C1B-CEE5B005D652@apple.com> Message-ID: Hi Michael, This patch has been code reviewed. Would you mind help me submit it? Regards, Che-Liang On Sat, Sep 18, 2010 at 5:53 AM, Chris Lattner wrote: > > On Sep 16, 2010, at 2:43 AM, Che-Liang Chiou wrote: > >> Hi Chris, >> >> Thanks for the comments. ?I've put {'s on the previous line and >> removed accidentally added tab characters. ?I've also checked again >> that cmake file was updated. ?Thanks for reminding. >> >> I regenerate patch against r114073. ?Please take a look. > > Looks good, please commit, > > -Chris > > -------------- next part -------------- A non-text attachment was scrubbed... Name: r114073-add-exit.patch Type: text/x-diff Size: 31614 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100919/66add688/attachment.bin From bigcheesegs at gmail.com Sat Sep 18 12:54:37 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Sat, 18 Sep 2010 17:54:37 -0000 Subject: [llvm-commits] [llvm] r114292 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20100918175437.373432A6C12C@llvm.org> Author: mspencer Date: Sat Sep 18 12:54:37 2010 New Revision: 114292 URL: http://llvm.org/viewvc/llvm-project?rev=114292&view=rev Log: Fix build. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=114292&r1=114291&r2=114292&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Sat Sep 18 12:54:37 2010 @@ -38,6 +38,7 @@ unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); + return 0; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { From echristo at apple.com Sat Sep 18 13:50:27 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 18 Sep 2010 18:50:27 -0000 Subject: [llvm-commits] [llvm] r114293 - /llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <20100918185027.31E322A6C12C@llvm.org> Author: echristo Date: Sat Sep 18 13:50:27 2010 New Revision: 114293 URL: http://llvm.org/viewvc/llvm-project?rev=114293&view=rev Log: Handle the odd case where we only have one instruction. Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=114293&r1=114292&r2=114293&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Sat Sep 18 13:50:27 2010 @@ -403,6 +403,9 @@ << " } else {\n" << Commands[0] << " }\n\n"; + } else if (Commands.size() == 1) { + // Emit a single possibility. + O << Commands[0] << "\n\n"; } else { O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " << ((1 << NumBits)-1) << ") {\n" From echristo at apple.com Sat Sep 18 13:52:28 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 18 Sep 2010 18:52:28 -0000 Subject: [llvm-commits] [llvm] r114294 - in /llvm/trunk: lib/Target/PTX/ lib/Target/PTX/AsmPrinter/ lib/Target/PTX/TargetInfo/ test/CodeGen/PTX/ Message-ID: <20100918185229.062732A6C12C@llvm.org> Author: echristo Date: Sat Sep 18 13:52:28 2010 New Revision: 114294 URL: http://llvm.org/viewvc/llvm-project?rev=114294&view=rev Log: Add the exit instruction to the PTX target. Patch by Che-Liang Chiou ! Added: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXISelLowering.h llvm/trunk/lib/Target/PTX/PTXInstrFormats.td llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.h llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.cpp llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.h llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.h llvm/trunk/test/CodeGen/PTX/ llvm/trunk/test/CodeGen/PTX/dg.exp llvm/trunk/test/CodeGen/PTX/exit.ll Modified: llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/Makefile llvm/trunk/lib/Target/PTX/PTX.h llvm/trunk/lib/Target/PTX/PTX.td llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp Modified: llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp Sat Sep 18 13:52:28 2010 @@ -14,7 +14,11 @@ #include "PTX.h" #include "PTXTargetMachine.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/SmallString.h" #include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/Target/TargetRegistry.h" using namespace llvm; @@ -25,11 +29,26 @@ explicit PTXAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) : AsmPrinter(TM, Streamer) {} const char *getPassName() const { return "PTX Assembly Printer"; } + + virtual void EmitInstruction(const MachineInstr *MI); + + // autogen'd. + void printInstruction(const MachineInstr *MI, raw_ostream &OS); + static const char *getRegisterName(unsigned RegNo); }; } // namespace +void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) { + SmallString<128> str; + raw_svector_ostream os(str); + printInstruction(MI, os); + os << ';'; + OutStreamer.EmitRawText(os.str()); +} + +#include "PTXGenAsmWriter.inc" + // Force static initialization. -extern "C" void LLVMInitializePTXAsmPrinter() -{ +extern "C" void LLVMInitializePTXAsmPrinter() { RegisterAsmPrinter X(ThePTXTarget); } Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Sat Sep 18 13:52:28 2010 @@ -1,6 +1,22 @@ set(LLVM_TARGET_DEFINITIONS PTX.td) +tablegen(PTXGenAsmWriter.inc -gen-asm-writer) +tablegen(PTXGenDAGISel.inc -gen-dag-isel) +tablegen(PTXGenInstrInfo.inc -gen-instr-desc) +tablegen(PTXGenInstrNames.inc -gen-instr-enums) +tablegen(PTXGenRegisterInfo.inc -gen-register-desc) +tablegen(PTXGenRegisterInfo.h.inc -gen-register-desc-header) +tablegen(PTXGenRegisterNames.inc -gen-register-enums) +tablegen(PTXGenSubtarget.inc -gen-subtarget) + add_llvm_target(PTXCodeGen + PTXISelDAGToDAG.cpp + PTXISelLowering.cpp + PTXInstrInfo.cpp + PTXMCAsmInfo.cpp + PTXRegisterInfo.cpp + PTXSubtarget.cpp + PTXTargetMachine.cpp ) target_link_libraries (LLVMPTXCodeGen LLVMSelectionDAG) Modified: llvm/trunk/lib/Target/PTX/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/Makefile (original) +++ llvm/trunk/lib/Target/PTX/Makefile Sat Sep 18 13:52:28 2010 @@ -12,7 +12,14 @@ TARGET = PTX # Make sure that tblgen is run, first thing. -BUILT_SOURCES = +BUILT_SOURCES = PTXGenAsmWriter.inc \ + PTXGenDAGISel.inc \ + PTXGenInstrInfo.inc \ + PTXGenInstrNames.inc \ + PTXGenRegisterInfo.inc \ + PTXGenRegisterInfo.h.inc \ + PTXGenRegisterNames.inc \ + PTXGenSubtarget.inc DIRS = AsmPrinter TargetInfo Modified: llvm/trunk/lib/Target/PTX/PTX.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.h?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.h (original) +++ llvm/trunk/lib/Target/PTX/PTX.h Sat Sep 18 13:52:28 2010 @@ -18,7 +18,19 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { + class PTXTargetMachine; + class FunctionPass; + + FunctionPass *createPTXISelDag(PTXTargetMachine &TM, + CodeGenOpt::Level OptLevel); + extern Target ThePTXTarget; } // namespace llvm; +// Defines symbolic names for PTX registers. +#include "PTXGenRegisterNames.inc" + +// Defines symbolic names for the PTX instructions. +#include "PTXGenInstrNames.inc" + #endif // PTX_H Modified: llvm/trunk/lib/Target/PTX/PTX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.td (original) +++ llvm/trunk/lib/Target/PTX/PTX.td Sat Sep 18 13:52:28 2010 @@ -8,3 +8,47 @@ //===----------------------------------------------------------------------===// // This is the top level entry point for the PTX target. //===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Target-independent interfaces +//===----------------------------------------------------------------------===// + +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// Subtarget Features. +//===----------------------------------------------------------------------===// + +def FeatureSM20 : SubtargetFeature<"sm20", "is_sm20", "true", + "Enable sm_20 target architecture">; + +//===----------------------------------------------------------------------===// +// PTX supported processors. +//===----------------------------------------------------------------------===// + +class Proc Features> + : Processor; + +def : Proc<"generic", []>; + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "PTXRegisterInfo.td" + +//===----------------------------------------------------------------------===// +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "PTXInstrInfo.td" + +def PTXInstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// Target Declaration +//===----------------------------------------------------------------------===// + +def PTX : Target { + let InstructionSet = PTXInstrInfo; +} Added: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,53 @@ +//===-- PTXISelDAGToDAG.cpp - A dag to dag inst selector for PTX ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines an instruction selector for the PTX target. +// +//===----------------------------------------------------------------------===// + +#include "PTX.h" +#include "PTXTargetMachine.h" +#include "llvm/CodeGen/SelectionDAGISel.h" + +using namespace llvm; + +namespace { +// PTXDAGToDAGISel - PTX specific code to select PTX machine +// instructions for SelectionDAG operations. +class PTXDAGToDAGISel : public SelectionDAGISel { + public: + PTXDAGToDAGISel(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel); + + virtual const char *getPassName() const { + return "PTX DAG->DAG Pattern Instruction Selection"; + } + + SDNode *Select(SDNode *Node); + + // Include the pieces auto'gened from the target description +#include "PTXGenDAGISel.inc" + +}; // class PTXDAGToDAGISel +} // namespace + +// createPTXISelDag - This pass converts a legalized DAG into a +// PTX-specific DAG, ready for instruction scheduling +FunctionPass *llvm::createPTXISelDag(PTXTargetMachine &TM, + CodeGenOpt::Level OptLevel) { + return new PTXDAGToDAGISel(TM, OptLevel); +} + +PTXDAGToDAGISel::PTXDAGToDAGISel(PTXTargetMachine &TM, + CodeGenOpt::Level OptLevel) + : SelectionDAGISel(TM, OptLevel) {} + +SDNode *PTXDAGToDAGISel::Select(SDNode *Node) { + // SelectCode() is auto'gened + return SelectCode(Node); +} Added: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,62 @@ +//===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PTXTargetLowering class. +// +//===----------------------------------------------------------------------===// + +#include "PTXISelLowering.h" +#include "PTXRegisterInfo.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" + +using namespace llvm; + +PTXTargetLowering::PTXTargetLowering(TargetMachine &TM) + : TargetLowering(TM, new TargetLoweringObjectFileELF()) { + // Set up the register classes. + addRegisterClass(MVT::i1, PTX::PredsRegisterClass); + + // Compute derived properties from the register classes + computeRegisterProperties(); +} + +const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch (Opcode) { + default: llvm_unreachable("Unknown opcode"); + case PTXISD::EXIT: return "PTXISD::EXIT"; + } +} + +//===----------------------------------------------------------------------===// +// Calling Convention Implementation +//===----------------------------------------------------------------------===// + +SDValue PTXTargetLowering:: + LowerFormalArguments(SDValue Chain, + CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Ins, + DebugLoc dl, + SelectionDAG &DAG, + SmallVectorImpl &InVals) const { + return Chain; +} + +SDValue PTXTargetLowering:: + LowerReturn(SDValue Chain, + CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, + DebugLoc dl, + SelectionDAG &DAG) const { + return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain); +} Added: llvm/trunk/lib/Target/PTX/PTXISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.h?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.h (added) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.h Sat Sep 18 13:52:28 2010 @@ -0,0 +1,60 @@ +//==-- PTXISelLowering.h - PTX DAG Lowering Interface ------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that PTX uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_ISEL_LOWERING_H +#define PTX_ISEL_LOWERING_H + +#include "llvm/Target/TargetLowering.h" + +namespace llvm { +class PTXSubtarget; +class PTXTargetMachine; + +namespace PTXISD { + enum NodeType { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + EXIT + }; +} // namespace PTXISD + +class PTXTargetLowering : public TargetLowering { + public: + explicit PTXTargetLowering(TargetMachine &TM); + + virtual const char *getTargetNodeName(unsigned Opcode) const; + + virtual unsigned getFunctionAlignment(const Function *F) const { + return 2; } + + virtual SDValue + LowerFormalArguments(SDValue Chain, + CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Ins, + DebugLoc dl, + SelectionDAG &DAG, + SmallVectorImpl &InVals) const; + + virtual SDValue + LowerReturn(SDValue Chain, + CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, + DebugLoc dl, + SelectionDAG &DAG) const; +}; // class PTXTargetLowering +} // namespace llvm + +#endif // PTX_ISEL_LOWERING_H Added: llvm/trunk/lib/Target/PTX/PTXInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrFormats.td?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrFormats.td (added) +++ llvm/trunk/lib/Target/PTX/PTXInstrFormats.td Sat Sep 18 13:52:28 2010 @@ -0,0 +1,24 @@ +//===- PTXInstrFormats.td - PTX Instruction Formats ----------*- tblgen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// PTX Predicate operand, default to (0, 0) = (zero-reg, always). +// Leave PrintMethod empty; predicate printing is defined elsewhere. +def pred : PredicateOperand; + +let Namespace = "PTX" in { + class InstPTX pattern> + : Instruction { + dag OutOperandList = oops; + dag InOperandList = !con(iops, (ins pred:$_p)); + let AsmString = asmstr; // Predicate printing is defined elsewhere. + let Pattern = pattern; + let isPredicable = 1; + } +} Added: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,22 @@ +//===- PTXInstrInfo.cpp - PTX Instruction Information ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the PTX implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#include "PTXInstrInfo.h" + +using namespace llvm; + +#include "PTXGenInstrInfo.inc" + +PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM) + : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)), + RI(_TM, *this), TM(_TM) {} Added: llvm/trunk/lib/Target/PTX/PTXInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.h?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.h (added) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.h Sat Sep 18 13:52:28 2010 @@ -0,0 +1,35 @@ +//===- PTXInstrInfo.h - PTX Instruction Information -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the PTX implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_INSTR_INFO_H +#define PTX_INSTR_INFO_H + +#include "PTXRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" + +namespace llvm { +class PTXTargetMachine; + +class PTXInstrInfo : public TargetInstrInfoImpl { + private: + const PTXRegisterInfo RI; + PTXTargetMachine &TM; + + public: + explicit PTXInstrInfo(PTXTargetMachine &_TM); + + virtual const PTXRegisterInfo &getRegisterInfo() const { return RI; } + }; // class PTXInstrInfo +} // namespace llvm + +#endif // PTX_INSTR_INFO_H Added: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (added) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Sat Sep 18 13:52:28 2010 @@ -0,0 +1,33 @@ +//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the PTX instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction format superclass +//===----------------------------------------------------------------------===// + +include "PTXInstrFormats.td" + +//===----------------------------------------------------------------------===// +// PTX Specific Node Definitions +//===----------------------------------------------------------------------===// + +def PTXexit + : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>; + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let isReturn = 1, isTerminator = 1, isBarrier = 1 in { + def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>; +} Added: llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.cpp?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.cpp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,30 @@ +//===-- PTXMCAsmInfo.cpp - PTX asm properties -----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declarations of the PTXMCAsmInfo properties. +// +//===----------------------------------------------------------------------===// + +#include "PTXMCAsmInfo.h" + +using namespace llvm; + +PTXMCAsmInfo::PTXMCAsmInfo(const Target &T, const StringRef &TT) { + CommentString = "//"; + + PrivateGlobalPrefix = "$L__"; + + AllowPeriodsInName = false; + + HasSetDirective = false; + + HasDotTypeDotSizeDirective = false; + + HasSingleParameterDotFile = false; +} Added: llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.h?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.h (added) +++ llvm/trunk/lib/Target/PTX/PTXMCAsmInfo.h Sat Sep 18 13:52:28 2010 @@ -0,0 +1,28 @@ +//=====-- PTXMCAsmInfo.h - PTX asm properties -----------------*- C++ -*--====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the PTXMCAsmInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_MCASM_INFO_H +#define PTX_MCASM_INFO_H + +#include "llvm/MC/MCAsmInfo.h" + +namespace llvm { + class Target; + class StringRef; + + struct PTXMCAsmInfo : public MCAsmInfo { + explicit PTXMCAsmInfo(const Target &T, const StringRef &TT); + }; +} // namespace llvm + +#endif // PTX_MCASM_INFO_H Added: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,19 @@ +//===- PTXRegisterInfo.cpp - PTX Register Information ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the PTX implementation of the TargetRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#include "PTX.h" +#include "PTXRegisterInfo.h" + +using namespace llvm; + +#include "PTXGenRegisterInfo.inc" Added: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (added) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Sat Sep 18 13:52:28 2010 @@ -0,0 +1,68 @@ +//===- PTXRegisterInfo.h - PTX Register Information Impl --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the PTX implementation of the MRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_REGISTER_INFO_H +#define PTX_REGISTER_INFO_H + +#include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/BitVector.h" + +#include "PTXGenRegisterInfo.h.inc" + +namespace llvm { +class PTXTargetMachine; +class MachineFunction; + +struct PTXRegisterInfo : public PTXGenRegisterInfo { + PTXRegisterInfo(PTXTargetMachine &TM, + const TargetInstrInfo &TII) {} + + virtual const unsigned + *getCalleeSavedRegs(const MachineFunction *MF = 0) const { + static const unsigned CalleeSavedRegs[] = { 0 }; + return CalleeSavedRegs; // save nothing + } + + virtual BitVector getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + return Reserved; // reserve no regs + } + + virtual bool hasFP(const MachineFunction &MF) const { return false; } + + // FIXME: Given that PTX does not support stack frame, what should we do here? + virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, + int SPAdj, + RegScavenger *RS = NULL) const {} + + virtual void emitPrologue(MachineFunction &MF) const {} + virtual void emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const {} + + virtual unsigned getFrameRegister(const MachineFunction &MF) const { + llvm_unreachable("PTX does not have a frame register"); + return 0; + } + + virtual unsigned getRARegister() const { + llvm_unreachable("PTX does not have a return address register"); + return 0; + } + + virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const { + return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); + } +}; // struct PTXRegisterInfo +} // namespace llvm + +#endif // PTX_REGISTER_INFO_H Added: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td (added) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td Sat Sep 18 13:52:28 2010 @@ -0,0 +1,63 @@ +//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Declarations that describe the PTX register file +//===----------------------------------------------------------------------===// + +class PTXReg : Register { + let Namespace = "PTX"; +} + +//===----------------------------------------------------------------------===// +// Registers +//===----------------------------------------------------------------------===// + +def P0 : PTXReg<"p0">; +def P1 : PTXReg<"p1">; +def P2 : PTXReg<"p2">; +def P3 : PTXReg<"p3">; +def P4 : PTXReg<"p4">; +def P5 : PTXReg<"p5">; +def P6 : PTXReg<"p6">; +def P7 : PTXReg<"p7">; +def P8 : PTXReg<"p8">; +def P9 : PTXReg<"p9">; +def P10 : PTXReg<"p10">; +def P11 : PTXReg<"p11">; +def P12 : PTXReg<"p12">; +def P13 : PTXReg<"p13">; +def P14 : PTXReg<"p14">; +def P15 : PTXReg<"p15">; +def P16 : PTXReg<"p16">; +def P17 : PTXReg<"p17">; +def P18 : PTXReg<"p18">; +def P19 : PTXReg<"p19">; +def P20 : PTXReg<"p20">; +def P21 : PTXReg<"p21">; +def P22 : PTXReg<"p22">; +def P23 : PTXReg<"p23">; +def P24 : PTXReg<"p24">; +def P25 : PTXReg<"p25">; +def P26 : PTXReg<"p26">; +def P27 : PTXReg<"p27">; +def P28 : PTXReg<"p28">; +def P29 : PTXReg<"p29">; +def P30 : PTXReg<"p30">; +def P31 : PTXReg<"p31">; + +//===----------------------------------------------------------------------===// +// Register classes +//===----------------------------------------------------------------------===// + +def Preds : RegisterClass<"PTX", [i1], 8, + [P0, P1, P2, P3, P4, P5, P6, P7, + P8, P9, P10, P11, P12, P13, P14, P15, + P16, P17, P18, P19, P20, P21, P22, P23, + P24, P25, P26, P27, P28, P29, P30, P31]>; Added: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,23 @@ +//===- PTXSubtarget.cpp - PTX Subtarget Information ---------------*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PTX specific subclass of TargetSubtarget. +// +//===----------------------------------------------------------------------===// + +#include "PTXSubtarget.h" + +using namespace llvm; + +PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &FS) { + std::string TARGET = "sm_20"; + // TODO: call ParseSubtargetFeatures(FS, TARGET); +} + +#include "PTXGenSubtarget.inc" Added: llvm/trunk/lib/Target/PTX/PTXSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=114294&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (added) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Sat Sep 18 13:52:28 2010 @@ -0,0 +1,32 @@ +//====-- PTXSubtarget.h - Define Subtarget for the PTX ---------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the PTX specific subclass of TargetSubtarget. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_SUBTARGET_H +#define PTX_SUBTARGET_H + +#include "llvm/Target/TargetSubtarget.h" + +namespace llvm { + class PTXSubtarget : public TargetSubtarget { + private: + bool is_sm20; + + public: + PTXSubtarget(const std::string &TT, const std::string &FS); + + std::string ParseSubtargetFeatures(const std::string &FS, + const std::string &CPU); + }; // class PTXSubtarget +} // namespace llvm + +#endif // PTX_SUBTARGET_H Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Sat Sep 18 13:52:28 2010 @@ -12,20 +12,32 @@ //===----------------------------------------------------------------------===// #include "PTX.h" +#include "PTXMCAsmInfo.h" #include "PTXTargetMachine.h" +#include "llvm/PassManager.h" #include "llvm/Target/TargetRegistry.h" using namespace llvm; -extern "C" void LLVMInitializePTXTarget() -{ - // Register the target +extern "C" void LLVMInitializePTXTarget() { RegisterTargetMachine X(ThePTXTarget); + RegisterAsmInfo Y(ThePTXTarget); } +// DataLayout and FrameInfo are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, const std::string &TT, - const std::string &FS) : - LLVMTargetMachine(T, TT) -{ + const std::string &FS) + : LLVMTargetMachine(T, TT), + DataLayout("e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64"), + FrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), + InstrInfo(*this), + TLInfo(*this), + Subtarget(TT, FS) { +} + +bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { + PM.add(createPTXISelDag(*this, OptLevel)); + return false; } Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Sat Sep 18 13:52:28 2010 @@ -14,14 +14,42 @@ #ifndef PTX_TARGET_MACHINE_H #define PTX_TARGET_MACHINE_H +#include "PTXISelLowering.h" +#include "PTXInstrInfo.h" +#include "PTXSubtarget.h" +#include "llvm/Target/TargetData.h" +#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" namespace llvm { - class PTXTargetMachine : public LLVMTargetMachine { - public: - PTXTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); - }; // class PTXTargetMachine +class PTXTargetMachine : public LLVMTargetMachine { + private: + const TargetData DataLayout; + TargetFrameInfo FrameInfo; + PTXInstrInfo InstrInfo; + PTXTargetLowering TLInfo; + PTXSubtarget Subtarget; + + public: + PTXTargetMachine(const Target &T, const std::string &TT, + const std::string &FS); + + virtual const TargetData *getTargetData() const { return &DataLayout; } + + virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + + virtual const PTXInstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const TargetRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); } + + virtual const PTXTargetLowering *getTargetLowering() const { + return &TLInfo; } + + virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; } + + virtual bool addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel); +}; // class PTXTargetMachine } // namespace llvm #endif // PTX_TARGET_MACHINE_H Modified: llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp?rev=114294&r1=114293&r2=114294&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp Sat Sep 18 13:52:28 2010 @@ -15,8 +15,7 @@ Target llvm::ThePTXTarget; -extern "C" void LLVMInitializePTXTargetInfo() -{ +extern "C" void LLVMInitializePTXTargetInfo() { // see llvm/ADT/Triple.h RegisterTarget X(ThePTXTarget, "ptx", "PTX"); } Added: llvm/trunk/test/CodeGen/PTX/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/dg.exp?rev=114294&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PTX/dg.exp (added) +++ llvm/trunk/test/CodeGen/PTX/dg.exp Sat Sep 18 13:52:28 2010 @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target PTX] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} Added: llvm/trunk/test/CodeGen/PTX/exit.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/exit.ll?rev=114294&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PTX/exit.ll (added) +++ llvm/trunk/test/CodeGen/PTX/exit.ll Sat Sep 18 13:52:28 2010 @@ -0,0 +1,6 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define void @t1() { +;CHECK: exit; + ret void +} From echristo at apple.com Sat Sep 18 13:54:20 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 18 Sep 2010 11:54:20 -0700 Subject: [llvm-commits] [PATCH] Add exit instruction to PTX backend In-Reply-To: References: <92FD1B35-9E05-4920-9C1B-CEE5B005D652@apple.com> Message-ID: <90E50CA2-B1E7-4657-B2ED-75FB951A2B04@apple.com> On Sep 18, 2010, at 10:31 AM, Che-Liang Chiou wrote: > Hi Michael, > > This patch has been code reviewed. > Would you mind help me submit it? I've gone ahead and committed it. There were some warnings that I had to make a change to TableGen to fix, please make sure there aren't any warnings in the future :) Thanks! -eric From viridia at gmail.com Sat Sep 18 14:03:46 2010 From: viridia at gmail.com (Talin) Date: Sat, 18 Sep 2010 19:03:46 +0000 (UTC) Subject: [llvm-commits] Patch to allow llvm.gcroot to work with non-pointer allocas. References: <4C93199D.2090300@free.fr> Message-ID: Duncan Sands writes: > is this really needed? In this situation, can't you just declare two allocas: > your struct alloca, and a pointer alloca that contains the address of the struct > alloca. You then pass the pointer alloca as the gc root. Let me restate my argument. I think that this patch is clearly the "right thing" for llvm.gcroot(), and that the use of an auxiliary pointer is an unnecessary hack which only serves to (a) make the frontend code generator more complicated, and (b) make stack frames bigger than they should be. Here's my reasoning: Originally, when I discovered that the code in Verifier.cpp would not allow me to use llvm.gcroot with a non-pointer alloca, I assumed that there was a reason for this guard condition to be there - that if I were to look deeper into the mechanics of the GC lowering pass, I would find some limitation that made the lowering pass unable to work with non-pointer allocas. However, I discovered no such limitation. The lowering pass works just fine (as far as I can tell - more on this in a minute) with non-pointer allocas. The only thing that doesn't work is the automatic initialization of roots to NULL, which I am not using anyway and which can be turned off in your GC strategy. By "working fine" in this case, what I mean is that my GC strategy plugin appears to be getting valid stack offsets and metadata for both pointer and non- pointer allocas. I won't say for certain that it's working until I actually get to the point where I can run a collection pass, and I'm not quite there yet. So my argument is that the restriction to pointer allocas is both unnecessary and inconvenient, and therefore should be removed. That's what this patch does. BTW, I'm curious - is anyone using the second argument to llvm.gcroot other than myself? From baldrick at free.fr Sat Sep 18 14:13:52 2010 From: baldrick at free.fr (Duncan Sands) Date: Sat, 18 Sep 2010 21:13:52 +0200 Subject: [llvm-commits] [dragonegg] r114283 - /dragonegg/trunk/llvm-debug.cpp In-Reply-To: <20100918142702.BE3522A6C12C@llvm.org> References: <20100918142702.BE3522A6C12C@llvm.org> Message-ID: <4C950F70.9040005@free.fr> > port r114276 from llvm-gcc Thanks Gabor! Ciao, Duncan. From geek4civic at gmail.com Sat Sep 18 14:50:42 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 18 Sep 2010 19:50:42 -0000 Subject: [llvm-commits] [llvm] r114297 - /llvm/trunk/lib/Target/X86/X86Subtarget.h Message-ID: <20100918195042.461292A6C12C@llvm.org> Author: chapuni Date: Sat Sep 18 14:50:42 2010 New Revision: 114297 URL: http://llvm.org/viewvc/llvm-project?rev=114297&view=rev Log: X86Subtarget.h: Fix Cygwin's TD. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=114297&r1=114296&r2=114297&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Sat Sep 18 14:50:42 2010 @@ -196,7 +196,7 @@ p = "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-n8:16:32:64"; else if (isTargetDarwin()) p = "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-n8:16:32"; - else if (isTargetMingw() || isTargetWindows()) + else if (isTargetCygMing() || isTargetWindows()) p = "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-n8:16:32"; else p = "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-n8:16:32"; From ismail at namtrac.org Sat Sep 18 15:47:20 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Sat, 18 Sep 2010 23:47:20 +0300 Subject: [llvm-commits] Detect Intel CPU family: 6 model number: 37 as Core i7 In-Reply-To: References: <4C9475E9.2070606@free.fr> Message-ID: Hi; On Sat, Sep 18, 2010 at 3:28 PM, ?smail D?nmez wrote: > Hi Duncan; > > On Sat, Sep 18, 2010 at 11:18 AM, Duncan Sands wrote: > > > > Hi ?smail, > > > > > I have a late MacBook Pro 2010 laptop, equipped with Core i7; > > > > I think it would be better to find the Intel docs that describe all of > > their recent processors, and add them all in one fell swoop. Otherwise > > we will end up with a random list of models where someone happened to > > notice that their machine was detected wrong. > > Indeed that would be good but their official document over at > http://www.intel.com/Assets/PDF/appnote/241618.pdf does not mention > all of the model numbers. It would be great if someone knows an > updated document. > Ok I figured the correct numbers; Extended model is 2, and model number is 5, hence (2<<4)+5 = 37. But the document still has no match for this model. Regards, ismail -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100918/47a322b7/attachment.html From sabre at nondot.org Sat Sep 18 19:31:58 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 19 Sep 2010 00:31:58 -0000 Subject: [llvm-commits] [llvm] r114302 - /llvm/trunk/lib/System/Host.cpp Message-ID: <20100919003158.CB9352A6C12C@llvm.org> Author: lattner Date: Sat Sep 18 19:31:58 2010 New Revision: 114302 URL: http://llvm.org/viewvc/llvm-project?rev=114302&view=rev Log: add corei7, the laptop version. Modified: llvm/trunk/lib/System/Host.cpp Modified: llvm/trunk/lib/System/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=114302&r1=114301&r2=114302&view=diff ============================================================================== --- llvm/trunk/lib/System/Host.cpp (original) +++ llvm/trunk/lib/System/Host.cpp Sat Sep 18 19:31:58 2010 @@ -210,6 +210,7 @@ // processors are manufactured using the 45 nm process. case 29: // Intel Xeon processor MP. All processors are manufactured using // the 45 nm process. + case 37: // Intel Core i7, laptop version. return "corei7"; case 28: // Intel Atom processor. All processors are manufactured using From clattner at apple.com Sat Sep 18 19:33:28 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 18 Sep 2010 17:33:28 -0700 Subject: [llvm-commits] Detect Intel CPU family: 6 model number: 37 as Core i7 In-Reply-To: References: Message-ID: On Sep 17, 2010, at 1:12 PM, ?smail D?nmez wrote: > Hi; > > I have a late MacBook Pro 2010 laptop, equipped with Core i7; > > [~/Sources/llvm]> sysctl -a|grep -i model > hw.model = MacBookPro6,2 > machdep.cpu.model: 37 > machdep.cpu.extmodel: 2 > > [~/Sources/llvm]> sysctl -a|grep -i family > hw.cpufamily: 1463508716 > machdep.cpu.family: 6 > machdep.cpu.extfamily: 0 Hey, me too! Applied in r114302. While a more encompassing solution is appreciated, this is good progress in the right direction. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100918/b946beea/attachment.html From sabre at nondot.org Sat Sep 18 19:34:58 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 19 Sep 2010 00:34:58 -0000 Subject: [llvm-commits] [llvm] r114303 - /llvm/trunk/lib/Target/PowerPC/README.txt Message-ID: <20100919003458.F2BC02A6C12C@llvm.org> Author: lattner Date: Sat Sep 18 19:34:58 2010 New Revision: 114303 URL: http://llvm.org/viewvc/llvm-project?rev=114303&view=rev Log: add a readme. Modified: llvm/trunk/lib/Target/PowerPC/README.txt Modified: llvm/trunk/lib/Target/PowerPC/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README.txt?rev=114303&r1=114302&r2=114303&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/README.txt (original) +++ llvm/trunk/lib/Target/PowerPC/README.txt Sat Sep 18 19:34:58 2010 @@ -37,6 +37,31 @@ ori r3, r2, 65535 blr +===-------------------------------------------------------------------------=== + +This code: + +unsigned add32carry(unsigned sum, unsigned x) { + unsigned z = sum + x; + if (sum + x < x) + z++; + return z; +} + +Should compile to something like: + + addc r3,r3,r4 + addze r3,r3 + +instead we get: + + add r3, r4, r3 + cmplw cr7, r3, r4 + mfcr r4 ; 1 + rlwinm r4, r4, 29, 31, 31 + add r3, r3, r4 + +Ick. ===-------------------------------------------------------------------------=== From sabre at nondot.org Sat Sep 18 19:37:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 19 Sep 2010 00:37:34 -0000 Subject: [llvm-commits] [llvm] r114304 - /llvm/trunk/lib/Target/README.txt Message-ID: <20100919003735.015A42A6C12C@llvm.org> Author: lattner Date: Sat Sep 18 19:37:34 2010 New Revision: 114304 URL: http://llvm.org/viewvc/llvm-project?rev=114304&view=rev Log: idiom recognition should catch this. Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=114304&r1=114303&r2=114304&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Sat Sep 18 19:37:34 2010 @@ -2,6 +2,38 @@ //===---------------------------------------------------------------------===// +We should recognize idioms for add-with-carry and turn it into the appropriate +intrinsics. This example: + +unsigned add32carry(unsigned sum, unsigned x) { + unsigned z = sum + x; + if (sum + x < x) + z++; + return z; +} + +Compiles to: clang t.c -S -o - -O3 -fomit-frame-pointer -m64 -mkernel + +_add32carry: ## @add32carry + addl %esi, %edi + cmpl %esi, %edi + sbbl %eax, %eax + andl $1, %eax + addl %edi, %eax + ret + +with clang, but to: + +_add32carry: + leal (%rsi,%rdi), %eax + cmpl %esi, %eax + adcl $0, %eax + ret + +with gcc. + +//===---------------------------------------------------------------------===// + Dead argument elimination should be enhanced to handle cases when an argument is dead to an externally visible function. Though the argument can't be removed from the externally visible function, the caller doesn't need to pass it in. From brukman+llvm at gmail.com Sat Sep 18 22:44:22 2010 From: brukman+llvm at gmail.com (Misha Brukman) Date: Sun, 19 Sep 2010 03:44:22 -0000 Subject: [llvm-commits] [llvm] r114308 - in /llvm/trunk/utils/emacs: llvm-mode.el tablegen-mode.el Message-ID: <20100919034422.BB2FD2A6C12C@llvm.org> Author: brukman Date: Sat Sep 18 22:44:22 2010 New Revision: 114308 URL: http://llvm.org/viewvc/llvm-project?rev=114308&view=rev Log: Using regexp-opt for keyword regex declarations makes the word lists more readable and easier to edit. Modified: llvm/trunk/utils/emacs/llvm-mode.el llvm/trunk/utils/emacs/tablegen-mode.el Modified: llvm/trunk/utils/emacs/llvm-mode.el URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/emacs/llvm-mode.el?rev=114308&r1=114307&r2=114308&view=diff ============================================================================== --- llvm/trunk/utils/emacs/llvm-mode.el (original) +++ llvm/trunk/utils/emacs/llvm-mode.el Sat Sep 18 22:44:22 2010 @@ -19,7 +19,7 @@ ;; Unnamed variable slots '("%[-]?[0-9]+" . font-lock-variable-name-face) ;; Types - '("\\bvoid\\b\\|\\bi[0-9]+\\b\\|\\float\\b\\|\\bdouble\\b\\|\\btype\\b\\|\\blabel\\b\\|\\bopaque\\b" . font-lock-type-face) + `(,(regexp-opt '("void" "i[0-9]+" "float" "double" "type" "label" "opaque") 'words) . font-lock-type-face) ;; Integer literals '("\\b[-]?[0-9]+\\b" . font-lock-preprocessor-face) ;; Floating point constants @@ -27,15 +27,20 @@ ;; Hex constants '("\\b0x[0-9A-Fa-f]+\\b" . font-lock-preprocessor-face) ;; Keywords - '("\\bbegin\\b\\|\\bend\\b\\|\\btrue\\b\\|\\bfalse\\b\\|\\bzeroinitializer\\b\\|\\bdeclare\\b\\|\\bdefine\\b\\|\\bglobal\\b\\|\\bconstant\\b\\|\\bconst\\b\\|\\binternal\\b\\|\\blinkonce\\b\\|\\blinkonce_odr\\b\\|\\bweak\\b\\|\\bweak_odr\\b\\|\\bappending\\b\\|\\buninitialized\\b\\|\\bimplementation\\b\\|\\b\\.\\.\\.\\b\\|\\bnull\\b\\|\\bundef\\b\\|\\bto\\b\\|\\bexcept\\b\\|\\bnot\\b\\|\\btarget\\b\\|\\bendian\\b\\|\\blittle\\b\\|\\bbig\\b\\|\\bpointersize\\b\\|\\bdeplibs\\b\\|\\bvolatile\\b\\|\\bfastcc\\b\\|\\bcoldcc\\b\\|\\bcc\\b" . font-lock-keyword-face) + `(,(regexp-opt '("begin" "end" "true" "false" "zeroinitializer" "declare" + "define" "global" "constant" "const" "internal" "linkonce" "linkonce_odr" + "weak" "weak_odr" "appending" "uninitialized" "implementation" "..." + "null" "undef" "to" "except" "not" "target" "endian" "little" "big" + "pointersize" "deplibs" "volatile" "fastcc" "coldcc" "cc") 'words) . font-lock-keyword-face) ;; Arithmetic and Logical Operators - '("\\badd\\b\\|\\bsub\\b\\|\\bmul\\b\\|\\bdiv\\b\\|\\brem\\b\\|\\band\\b\\|\\bor\\b\\|\\bxor\\b\\|\\bset\\(ne\\b\\|\\beq\\b\\|\\blt\\b\\|\\bgt\\b\\|\\ble\\b\\|\\bge\\b\\)" . font-lock-keyword-face) + `(,(regexp-opt '("add" "sub" "mul" "div" "rem" "and" "or" "xor" + "setne" "seteq" "setlt" "setgt" "setle" "setge") 'words) . font-lock-keyword-face) ;; Special instructions - '("\\bphi\\b\\|\\btail\\b\\|\\bcall\\b\\|\\bcast\\b\\|\\bselect\\b\\|\\bto\\b\\|\\bshl\\b\\|\\bshr\\b\\|\\bvaarg\\b\\|\\bvanext\\b" . font-lock-keyword-face) + `(,(regexp-opt '("phi" "tail" "call" "cast" "select" "to" "shl" "shr" "vaarg" "vanext") 'words) . font-lock-keyword-face) ;; Control instructions - '("\\bret\\b\\|\\bbr\\b\\|\\bswitch\\b\\|\\binvoke\\b\\|\\bunwind\\b\\|\\bunreachable\\b" . font-lock-keyword-face) + `(,(regexp-opt '("ret" "br" "switch" "invoke" "unwind" "unreachable") 'words) . font-lock-keyword-face) ;; Memory operators - '("\\bmalloc\\b\\|\\balloca\\b\\|\\bfree\\b\\|\\bload\\b\\|\\bstore\\b\\|\\bgetelementptr\\b" . font-lock-keyword-face) + `(,(regexp-opt '("malloc" "alloca" "free" "load" "store" "getelementptr") 'words) . font-lock-keyword-face) ) "Syntax highlighting for LLVM" ) Modified: llvm/trunk/utils/emacs/tablegen-mode.el URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/emacs/tablegen-mode.el?rev=114308&r1=114307&r2=114308&view=diff ============================================================================== --- llvm/trunk/utils/emacs/tablegen-mode.el (original) +++ llvm/trunk/utils/emacs/tablegen-mode.el Sat Sep 18 22:44:22 2010 @@ -12,13 +12,11 @@ (make-face 'td-decorators-face) (defvar tablegen-font-lock-keywords - (let ((kw (mapconcat 'identity - '("class" "defm" "def" "field" "include" "in" + (let ((kw (regexp-opt '("class" "defm" "def" "field" "include" "in" "let" "multiclass") - "\\|")) - (type-kw (mapconcat 'identity - '("bit" "bits" "code" "dag" "int" "list" "string") - "\\|")) + 'words)) + (type-kw (regexp-opt '("bit" "bits" "code" "dag" "int" "list" "string") + 'words)) ) (list ;; Comments @@ -36,10 +34,10 @@ '("^[ \t]*\\(@.+\\)" 1 'td-decorators-face) ;; Keywords - (cons (concat "\\<\\(" kw "\\)\\>[ \n\t(]") 1) + (cons (concat kw "[ \n\t(]") 1) ;; Type keywords - (cons (concat "\\<\\(" type-kw "\\)[ \n\t(]") 1) + (cons (concat type-kw "[ \n\t(]") 1) )) "Additional expressions to highlight in TableGen mode.") (put 'tablegen-mode 'font-lock-defaults '(tablegen-font-lock-keywords)) From ismail at namtrac.org Sun Sep 19 03:37:18 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Sun, 19 Sep 2010 11:37:18 +0300 Subject: [llvm-commits] Detect Intel CPU family: 6 model number: 37 as Core i7 In-Reply-To: References: Message-ID: On Sun, Sep 19, 2010 at 3:33 AM, Chris Lattner wrote: > > On Sep 17, 2010, at 1:12 PM, ?smail D?nmez wrote: > > Hi; > > I have a late MacBook Pro 2010 laptop, equipped with Core i7; > > [~/Sources/llvm]> sysctl -a|grep -i model > hw.model = MacBookPro6,2 > machdep.cpu.model: 37 > machdep.cpu.extmodel: 2 > > [~/Sources/llvm]> sysctl -a|grep -i family > hw.cpufamily: 1463508716 > machdep.cpu.family: 6 > machdep.cpu.extfamily: 0 > > > Hey, me too! Applied in r114302. While a more encompassing solution is > appreciated, this is good progress in the right direction. > Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100919/2eb2825e/attachment.html From baldrick at free.fr Sun Sep 19 07:07:03 2010 From: baldrick at free.fr (Duncan Sands) Date: Sun, 19 Sep 2010 12:07:03 -0000 Subject: [llvm-commits] [zorg] r114309 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100919120704.060C32A6C12C@llvm.org> Author: baldrick Date: Sun Sep 19 07:07:03 2010 New Revision: 114309 URL: http://llvm.org/viewvc/llvm-project?rev=114309&view=rev Log: Now that the llvm-gcc-i386-linux-selfhost builder seems to be working fine, make it non-experimental. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114309&r1=114308&r2=114309&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Sun Sep 19 07:07:03 2010 @@ -82,6 +82,12 @@ 'builddir':"llvm-gcc-x86_64-darwin10-selfhost", 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='x86_64-apple-darwin10', gxxincludedir='/usr/include/c++/4.2.1')}, + {'name' : "llvm-gcc-i386-linux-selfhost", + 'slavenames':["gcc11"], + 'builddir':"llvm-gcc-i386-linux-selfhost", + 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', + extra_configure_args=['--disable-multilib', + '--enable-targets=all','--with-as=/home/baldrick/bin32/as'])}, ] # Offline, no free x86_64 resources. @@ -248,14 +254,6 @@ extra_configure_args=['--disable-multilib']), 'category' : 'llvm-gcc.exp' }, - {'name' : "llvm-gcc-i386-linux-selfhost", - 'slavenames':["gcc11"], - 'builddir':"llvm-gcc-i386-linux-selfhost", - 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='i686-pc-linux-gnu', - extra_configure_args=['--disable-multilib', - '--enable-targets=all','--with-as=/home/baldrick/bin32/as']), - 'category' : 'llvm-gcc.exp' }, - {'name' : "llvm-gcc-x86_64-darwin10-self-mingw32", 'slavenames': [ "kistanova1" ], 'builddir' : "llvm-gcc-x86_64-darwin10-self-mingw32", From stoklund at 2pi.dk Sun Sep 19 12:54:29 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 19 Sep 2010 17:54:29 -0000 Subject: [llvm-commits] [llvm] r114310 - /llvm/trunk/lib/System/Host.cpp Message-ID: <20100919175429.19C342A6C12C@llvm.org> Author: stoklund Date: Sun Sep 19 12:54:28 2010 New Revision: 114310 URL: http://llvm.org/viewvc/llvm-project?rev=114310&view=rev Log: Add one more Core i7 model number. Modified: llvm/trunk/lib/System/Host.cpp Modified: llvm/trunk/lib/System/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=114310&r1=114309&r2=114310&view=diff ============================================================================== --- llvm/trunk/lib/System/Host.cpp (original) +++ llvm/trunk/lib/System/Host.cpp Sun Sep 19 12:54:28 2010 @@ -210,6 +210,8 @@ // processors are manufactured using the 45 nm process. case 29: // Intel Xeon processor MP. All processors are manufactured using // the 45 nm process. + case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. + // As found in a Summer 2010 model iMac. case 37: // Intel Core i7, laptop version. return "corei7"; From pichet2000 at gmail.com Sun Sep 19 13:13:14 2010 From: pichet2000 at gmail.com (Francois Pichet) Date: Sun, 19 Sep 2010 14:13:14 -0400 Subject: [llvm-commits] [PATCH][MS][Review request] - Fix index lit tests failing on Windows again Message-ID: This patch implements Path::renamePathOnDisk as a copy+delete on Windows. This fixes the intermittent ACCESS_DENIED lit test problems on Windows. See thread "Windows Lit problems again. What should we do?" on clang mailing list for details. ok to commit? -------------- next part -------------- A non-text attachment was scrubbed... Name: win32_rename_fix.patch Type: application/octet-stream Size: 864 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100919/05e3247f/attachment.obj From jasonwkim at google.com Sun Sep 19 13:33:31 2010 From: jasonwkim at google.com (Jason Kim) Date: Sun, 19 Sep 2010 11:33:31 -0700 Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH) In-Reply-To: References: <461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com> Message-ID: Please find enclosed a follow up on the prior patch The patch adds additional stub framework for the ARM MC ELF emission, as well as quashing a few trailing blanks here and there. Specifically, two new files are added ARMELFWriterInfo.(cpp|h) llc now recognizes the "intent" to support MC/obj emission for ARM, but given that they are all stubs, it asserts on --filetype=obj --march=arm The attachment arm-elf-s01-patch2 is an output of svn diff from -r114212 It applies cleanly, but the two new files will need to be svn added. More work to follow. make check passes. M lib/Target/X86/X86TargetMachine.cpp M lib/Target/ARM/ARMTargetMachine.cpp A + lib/Target/ARM/ARMELFWriterInfo.h A + lib/Target/ARM/ARMELFWriterInfo.cpp M lib/Target/ARM/CMakeLists.txt M lib/Target/ARM/ARMTargetMachine.h M lib/Target/TargetELFWriterInfo.cpp Thanks to Jim for guidance. As always, corrections, comments and general advice is greatly appreciated. Thank you. On Fri, Sep 17, 2010 at 11:48 AM, Jim Grosbach wrote: > Applied, with a couple of very minor tweaks, as r114195. Thanks for the patch! > > -Jim > > On Sep 16, 2010, at 1:54 PM, Jason Kim wrote: > >> Hi Jim. >> >> Thanks for the feedback. Much appreciated. >> Here's the revised patch. >> >> >> On Thu, Sep 16, 2010 at 11:19 AM, Jim Grosbach wrote: >>> Hi Jason, >>> >>> Glad to see this moving forward! This looks like a great start. A few minor comments on the patch itself inline below. Apologies in advance for being nitpicky. >>> >>> I don't recall whether we covered this bit specifically before, so at the risk of repeating myself... On a general note, it seems to me that a reasonable first milestone would be to have the target independent layer recognize that the ARM target wants to support object file emission. That is, have llc recognize "-filetype=obj". Right now it issues an error "target does not support generation of this file type!" (which is, of course, entirely correct for the moment). Once the classes are in place to do that, you'll start hitting all of the placeholder asserts(), which is exactly what you want, as you can interactively follow more easily the path the code wants to follow for simple cases and fill in the bits that as you go. >>> >> >> Sounds like a plan! Up for that next. >> >>> >>>> Index: lib/Target/ARM/ARM.h >>>> =================================================================== >>>> --- lib/Target/ARM/ARM.h ? ? ?(revision 114081) >>>> +++ lib/Target/ARM/ARM.h ? ? ?(working copy) >>>> @@ -26,7 +26,14 @@ >>>> ?class FunctionPass; >>>> ?class JITCodeEmitter; >>>> ?class formatted_raw_ostream; >>>> +class MCCodeEmitter; >>>> >>>> + >>>> +MCCodeEmitter *createARM_MCCodeEmitter(const Target &, >>> >>> As a style thing, LLVM doesn't use underscores in symbol names. Just createARMMCCodeEmitter() is fine. (The underscore in the X86 equivalent is there as part of the target name, X86_32 vs. X86_64, and so is a bit misleading in this regard). >>> >>> >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx); >>>> + >>>> + >>> >>> Extra vertical whitespace here can be removed. >>> >>>> ?FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, >>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenOpt::Level OptLevel); >>>> >>>> @@ -41,6 +48,9 @@ >>>> ?FunctionPass *createThumb2ITBlockPass(); >>>> ?FunctionPass *createThumb2SizeReductionPass(); >>>> >>>> + >>>> + >>>> + >>> >>> Ditto. There's other instances below that can be similarly cleaned up. >>> >>>> ?extern Target TheARMTarget, TheThumbTarget; >>>> >>>> ?} // end namespace llvm; >>>> Index: lib/Target/ARM/ARMMCCodeEmitter.cpp >>>> =================================================================== >>>> --- lib/Target/ARM/ARMMCCodeEmitter.cpp ? ? ? (revision 0) >>>> +++ lib/Target/ARM/ARMMCCodeEmitter.cpp ? ? ? (revision 0) >>>> @@ -0,0 +1,134 @@ >>>> +//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// >>>> +// >>>> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure >>>> +// >>>> +// This file is distributed under the University of Illinois Open Source >>>> +// License. See LICENSE.TXT for details. >>>> +// >>>> +//===----------------------------------------------------------------------===// >>>> +// >>>> +// This file implements the ARMMCCodeEmitter class. >>>> +// >>>> +//===----------------------------------------------------------------------===// >>>> + >>>> +#define DEBUG_TYPE "ARM-emitter" >>> >>> Lower-case here, i.e., "arm-emitter" is more consistent with other options of this sort. >>> >>>> +#include "ARM.h" >>>> +#include "ARMInstrInfo.h" >>>> +//#include "ARMFixupKinds.h" >>>> +#include "llvm/MC/MCCodeEmitter.h" >>>> +#include "llvm/MC/MCExpr.h" >>>> +#include "llvm/MC/MCInst.h" >>>> +#include "llvm/Support/raw_ostream.h" >>>> +using namespace llvm; >>>> + >>>> +namespace { >>>> +class ARMMCCodeEmitter : public MCCodeEmitter { >>>> + ?ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT >>>> + ?void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT >>>> + ?const TargetMachine &TM; >>>> + ?const TargetInstrInfo &TII; >>>> + ?MCContext &Ctx; >>>> + ?bool Is64BitMode; >>> >>> Can just remove the extra hold-over bool from the x86 bit here. No 64-bit mode on ARM. :) >>> >>>> +public: >>>> + ?ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) >>>> + ? ?: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { >>>> + ?} >>>> + >>>> + ?~ARMMCCodeEmitter() {} >>>> + >>>> + ?unsigned getNumFixupKinds() const { >>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>>> + ?} >>>> + >>>> + ?const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { >>>> + ? ?static MCFixupKindInfo rtn; >>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>> >>> Totally not a big deal, but I tend to phrase these sorts of things as simply " not yet implemented." Personal preference to simply state accurately the status of things rather than indicate anything about the future. Plus, then when I see the assert, I know specifically which function is being hit, rather than just the general name of the feature. >>> >>>> + ? ?return rtn; >>>> + ?} >>>> + >>>> + ?static unsigned GetARMRegNum(const MCOperand &MO) { >>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>>> + ? ?return 0; >>>> + ?} >>>> + >>>> + ?void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { >>>> + ? ?OS << (char)C; >>>> + ? ?++CurByte; >>>> + ?} >>>> + >>>> + ?void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, >>>> + ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const { >>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>> >>> Is this assert necessary? I don't know any reason why the implementation below wouldn't be sufficient. >>> >>>> + ? ?// Output the constant in little endian byte order. >>>> + ? ?for (unsigned i = 0; i != Size; ++i) { >>>> + ? ? ?EmitByte(Val & 255, CurByte, OS); >>>> + ? ? ?Val >>= 8; >>>> + ? ?} >>>> + ?} >>>> + >>>> + ?void EmitImmediate(const MCOperand &Disp, >>>> + ? ? ? ? ? ? ? ? ? ? unsigned ImmSize, MCFixupKind FixupKind, >>>> + ? ? ? ? ? ? ? ? ? ? unsigned &CurByte, raw_ostream &OS, >>>> + ? ? ? ? ? ? ? ? ? ? SmallVectorImpl &Fixups, >>>> + ? ? ? ? ? ? ? ? ? ? int ImmOffset = 0) const; >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + ?void EncodeInstruction(const MCInst &MI, raw_ostream &OS, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? SmallVectorImpl &Fixups) const; >>>> + >>>> + ?void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, >>>> + ? ? ? ? ? ? ? ? ? ? ? ?const MCInst &MI, const TargetInstrDesc &Desc, >>>> + ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const; >>>> +}; >>>> + >>>> +} // end anonymous namespace >>>> + >>>> + >>>> +MCCodeEmitter *llvm::createARM_MCCodeEmitter(const Target &, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx) { >>>> + ?return new ARMMCCodeEmitter(TM, Ctx); >>>> +} >>>> + >>>> + >>>> + >>>> +/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate >>>> +/// in an instruction with the specified TSFlags. >>>> +static MCFixupKind getImmFixupKind(uint64_t TSFlags) { >>>> + ?static MCFixupKind rtn; >>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>>> + ?return rtn; >>>> +} >>>> + >>>> + >>>> +void ARMMCCodeEmitter:: >>>> +EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, >>>> + ? ? ? ? ? ? ?unsigned &CurByte, raw_ostream &OS, >>>> + ? ? ? ? ? ? ?SmallVectorImpl &Fixups, int ImmOffset) const { >>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>>> +} >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> +/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. >>>> +/// >>>> +/// MemOperand is the operand # of the start of a memory operand if present. ?If >>>> +/// Not present, it is -1. >>>> +void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int MemOperand, const MCInst &MI, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetInstrDesc &Desc, >>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const { >>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>>> +} >>>> + >>>> +void ARMMCCodeEmitter:: >>>> +EncodeInstruction(const MCInst &MI, raw_ostream &OS, >>>> + ? ? ? ? ? ? ? ? ?SmallVectorImpl &Fixups) const { >>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon"); >>>> +} >>>> Index: lib/Target/ARM/CMakeLists.txt >>>> =================================================================== >>>> --- lib/Target/ARM/CMakeLists.txt ? ? (revision 114081) >>>> +++ lib/Target/ARM/CMakeLists.txt ? ? (working copy) >>>> @@ -28,6 +28,7 @@ >>>> ? ?ARMISelLowering.cpp >>>> ? ?ARMInstrInfo.cpp >>>> ? ?ARMJITInfo.cpp >>>> + ?ARMMCCodeEmitter.cpp >>>> ? ?ARMLoadStoreOptimizer.cpp >>>> ? ?ARMMCAsmInfo.cpp >>>> ? ?ARMMCInstLower.cpp >>>> >>> >> > > -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf-s01.patch2 Type: application/octet-stream Size: 16078 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100919/af597b1f/attachment.obj From resistor at mac.com Sun Sep 19 14:51:55 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 19 Sep 2010 19:51:55 -0000 Subject: [llvm-commits] [llvm] r114312 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20100919195156.0FF242A6C12E@llvm.org> Author: resistor Date: Sun Sep 19 14:51:55 2010 New Revision: 114312 URL: http://llvm.org/viewvc/llvm-project?rev=114312&view=rev Log: Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know, r114268 fixed the last of the blockers to enabling it. I will be monitoring for failures. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114312&r1=114311&r2=114312&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Sep 19 14:51:55 2010 @@ -46,7 +46,7 @@ namespace { static cl::opt - CombinerAA("combiner-alias-analysis", cl::Hidden, + CombinerAA("combiner-alias-analysis", cl::init(true), cl::Hidden, cl::desc("Turn on alias analysis during testing")); static cl::opt From clattner at apple.com Sun Sep 19 15:12:09 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 19 Sep 2010 13:12:09 -0700 Subject: [llvm-commits] [llvm] r114312 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <20100919195156.0FF242A6C12E@llvm.org> References: <20100919195156.0FF242A6C12E@llvm.org> Message-ID: <94477953-0100-4B20-B3AC-45B084D04FCD@apple.com> On Sep 19, 2010, at 12:51 PM, Owen Anderson wrote: > Author: resistor > Date: Sun Sep 19 14:51:55 2010 > New Revision: 114312 > > URL: http://llvm.org/viewvc/llvm-project?rev=114312&view=rev > Log: > Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know, > r114268 fixed the last of the blockers to enabling it. I will be monitoring > for failures. What is the compile-time performance impact of this? -Chris > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114312&r1=114311&r2=114312&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Sep 19 14:51:55 2010 > @@ -46,7 +46,7 @@ > > namespace { > static cl::opt > - CombinerAA("combiner-alias-analysis", cl::Hidden, > + CombinerAA("combiner-alias-analysis", cl::init(true), cl::Hidden, > cl::desc("Turn on alias analysis during testing")); > > static cl::opt > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Sun Sep 19 16:01:26 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 19 Sep 2010 21:01:26 -0000 Subject: [llvm-commits] [llvm] r114313 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20100919210126.A5A442A6C12C@llvm.org> Author: resistor Date: Sun Sep 19 16:01:26 2010 New Revision: 114313 URL: http://llvm.org/viewvc/llvm-project?rev=114313&view=rev Log: Revert r114312 while I sort out some issues. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114313&r1=114312&r2=114313&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Sep 19 16:01:26 2010 @@ -46,7 +46,7 @@ namespace { static cl::opt - CombinerAA("combiner-alias-analysis", cl::init(true), cl::Hidden, + CombinerAA("combiner-alias-analysis", cl::Hidden, cl::desc("Turn on alias analysis during testing")); static cl::opt From geek4civic at gmail.com Sun Sep 19 16:58:55 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sun, 19 Sep 2010 21:58:55 -0000 Subject: [llvm-commits] [llvm] r114317 - in /llvm/trunk/test/CodeGen/X86: 2008-06-13-VolatileLoadStore.ll store_op_load_fold2.ll vec_set-F.ll Message-ID: <20100919215855.C20E02A6C12C@llvm.org> Author: chapuni Date: Sun Sep 19 16:58:55 2010 New Revision: 114317 URL: http://llvm.org/viewvc/llvm-project?rev=114317&view=rev Log: test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen. r114297 raises 3 failures. They might fail also on mingw. Modified: llvm/trunk/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll llvm/trunk/test/CodeGen/X86/vec_set-F.ll Modified: llvm/trunk/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll?rev=114317&r1=114316&r2=114317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll Sun Sep 19 16:58:55 2010 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 5 -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movl | count 2 +; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movsd | count 5 +; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movl | count 2 @atomic = global double 0.000000e+00 ; [#uses=1] @atomic2 = global double 0.000000e+00 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll?rev=114317&r1=114316&r2=114317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll (original) +++ llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll Sun Sep 19 16:58:55 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | FileCheck %s +; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=intel | FileCheck %s target datalayout = "e-p:32:32" %struct.Macroblock = type { i32, i32, i32, i32, i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 } Modified: llvm/trunk/test/CodeGen/X86/vec_set-F.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-F.ll?rev=114317&r1=114316&r2=114317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_set-F.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_set-F.ll Sun Sep 19 16:58:55 2010 @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 3 +; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movq +; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movsd +; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep mov | count 3 define <2 x i64> @t1(<2 x i64>* %ptr) nounwind { %tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>* From clattner at apple.com Sun Sep 19 17:46:12 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 19 Sep 2010 15:46:12 -0700 Subject: [llvm-commits] [PATCH][MS][Review request] - Fix index lit tests failing on Windows again In-Reply-To: References: Message-ID: <1363001D-E69E-47DB-B540-7437494D795A@apple.com> On Sep 19, 2010, at 11:13 AM, Francois Pichet wrote: > This patch implements Path::renamePathOnDisk as a copy+delete on Windows. > > This fixes the intermittent ACCESS_DENIED lit test problems on Windows. > See thread "Windows Lit problems again. What should we do?" on clang > mailing list for details. Works for me, if it fixes the problem, thanks! -Chris From sabre at nondot.org Sun Sep 19 22:58:32 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 20 Sep 2010 03:58:32 -0000 Subject: [llvm-commits] [llvm] r114319 - /llvm/trunk/include/llvm/DerivedTypes.h Message-ID: <20100920035832.457AD2A6C12C@llvm.org> Author: lattner Date: Sun Sep 19 22:58:32 2010 New Revision: 114319 URL: http://llvm.org/viewvc/llvm-project?rev=114319&view=rev Log: fix a bug I introduced back in the hayday of version #2. Modified: llvm/trunk/include/llvm/DerivedTypes.h Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=114319&r1=114318&r2=114319&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Sun Sep 19 22:58:32 2010 @@ -9,7 +9,7 @@ // // This file contains the declarations of classes that represent "derived // types". These are things like "arrays of x" or "structure of x, y, z" or -// "method returning x taking (y,z) as parameters", etc... +// "function returning x taking (y,z) as parameters", etc... // // The implementations of these classes live in the Type.cpp file. // From pichet2000 at gmail.com Sun Sep 19 23:03:07 2010 From: pichet2000 at gmail.com (Francois Pichet) Date: Mon, 20 Sep 2010 04:03:07 -0000 Subject: [llvm-commits] [llvm] r114320 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20100920040307.EA3592A6C12C@llvm.org> Author: fpichet Date: Sun Sep 19 23:03:07 2010 New Revision: 114320 URL: http://llvm.org/viewvc/llvm-project?rev=114320&view=rev Log: Fix the "unable to rename temporary" lit test failing on Windows. rename is now copy + delete on Windows. Problem to be revisited for a permanent and clean solution. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=114320&r1=114319&r2=114320&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Sun Sep 19 23:03:07 2010 @@ -745,12 +745,19 @@ return true; } +// Implements renamePathOnDisk as a CopyFile + eraseFromDisk on Windows. +// Using MoveFileEx was causing mysterious ACCESS_DENIED error when used +// within a multithreaded lit/python context. +// FIXME: put back MoveFileEx when the source of the problem is resolved. bool Path::renamePathOnDisk(const Path& newName, std::string* ErrMsg) { - if (!MoveFileEx(path.c_str(), newName.c_str(), MOVEFILE_REPLACE_EXISTING)) - return MakeErrMsg(ErrMsg, "Can't move '" + path + "' to '" + newName.path - + "': "); - return false; + if (*this == newName) + return false; + + if (CopyFile(newName, *this, ErrMsg)) + return true; + + return eraseFromDisk(true, ErrMsg); } bool From geek4civic at gmail.com Sun Sep 19 23:46:28 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 20 Sep 2010 13:46:28 +0900 Subject: [llvm-commits] [LLVMdev] RFC: change build order (or location) of LLVMHello plugin In-Reply-To: References: Message-ID: A trivial patch is attached. Checked on x86_64-centos5, ppc64-f12 and cygming with both ENABLE_SHARED. I think it would be better eg. the directory plugins/ should be had. good afternoon...Takumi 2010/9/6 NAKAMURA Takumi : > Good evening, Michael. > > 2010/9/5 Michael Spencer : >> Do you know what the exact problem is? It would be best to fix the >> Makefile instead of moving it. And sense it is a transformation, the >> build system is broken if you _have_ to move it. > > I am sorry, I don't understand what *the exact problem" is. > I can describe facts; > > ?- Hello is the only LOADABLE_MODULE under lib/ > ?- Other plugin, eg. tools/bugpoint-passes, can be built. > > ...Takumi > -------------- next part -------------- diff --git a/Makefile b/Makefile index ae650b7..77fc833 100644 --- a/Makefile +++ b/Makefile @@ -31,7 +31,7 @@ ifeq ($(BUILD_DIRS_ONLY),1) OPTIONAL_DIRS := else DIRS := lib/System lib/Support utils lib/VMCore lib tools/llvm-shlib \ - tools/llvm-config tools runtime docs unittests + tools/llvm-config tools lib/Transforms/Hello runtime unittests OPTIONAL_DIRS := projects bindings endif @@ -45,6 +45,9 @@ include $(LEVEL)/Makefile.config ifneq ($(ENABLE_SHARED),1) DIRS := $(filter-out tools/llvm-shlib, $(DIRS)) + ifneq (,$(filter $(HOST_OS), Cygwin MingW Minix)) + DIRS := $(filter-out lib/Transforms/Hello, $(DIRS)) + endif endif ifeq ($(MAKECMDGOALS),libs-only) diff --git a/lib/Transforms/Makefile b/lib/Transforms/Makefile index e527be2..e560113 100644 --- a/lib/Transforms/Makefile +++ b/lib/Transforms/Makefile @@ -8,13 +8,6 @@ ##===----------------------------------------------------------------------===## LEVEL = ../.. -PARALLEL_DIRS = Utils Instrumentation Scalar InstCombine IPO Hello - -include $(LEVEL)/Makefile.config - -# No support for plugins on windows targets -ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW Minix)) - PARALLEL_DIRS := $(filter-out Hello, $(PARALLEL_DIRS)) -endif +PARALLEL_DIRS = Utils Instrumentation Scalar InstCombine IPO include $(LEVEL)/Makefile.common