From jasonwkim at google.com  Mon Sep 20 00:03:33 2010
From: jasonwkim at google.com (Jason Kim)
Date: Sun, 19 Sep 2010 22:03:33 -0700
Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
Message-ID: <AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>

Oops, here's a slightly updated version of the patch.
I added static declaration to createARMMCStreamer function.


On Sun, Sep 19, 2010 at 11:33 AM, Jason Kim <jasonwkim at google.com> wrote:
> Please find enclosed a follow up on the prior patch
> The patch adds additional stub framework for the ARM MC ELF emission,
> as well as quashing a few trailing blanks here and there.
> Specifically, two new files are added ARMELFWriterInfo.(cpp|h)
> llc now recognizes the "intent" to support MC/obj emission for ARM, but
> given that they are all stubs, it asserts on --filetype=obj --march=arm
>
> The attachment arm-elf-s01-patch2 is an output of svn diff from -r114212
> It applies cleanly, but the two new files will need to be svn added.
>
> More work to follow.
> make check passes.
>
>
> M ? ? ? lib/Target/X86/X86TargetMachine.cpp
> M ? ? ? lib/Target/ARM/ARMTargetMachine.cpp
> A ?+ ? ?lib/Target/ARM/ARMELFWriterInfo.h
> A ?+ ? ?lib/Target/ARM/ARMELFWriterInfo.cpp
> M ? ? ? lib/Target/ARM/CMakeLists.txt
> M ? ? ? lib/Target/ARM/ARMTargetMachine.h
> M ? ? ? lib/Target/TargetELFWriterInfo.cpp
>
> Thanks to Jim for guidance.
> As always, corrections, comments and general advice is greatly appreciated.
>
> Thank you.
>
> On Fri, Sep 17, 2010 at 11:48 AM, Jim Grosbach <grosbach at apple.com> wrote:
>> Applied, with a couple of very minor tweaks, as r114195. Thanks for the patch!
>>
>> -Jim
>>
>> On Sep 16, 2010, at 1:54 PM, Jason Kim wrote:
>>
>>> Hi Jim.
>>>
>>> Thanks for the feedback. Much appreciated.
>>> Here's the revised patch.
>>>
>>>
>>> On Thu, Sep 16, 2010 at 11:19 AM, Jim Grosbach <grosbach at apple.com> wrote:
>>>> Hi Jason,
>>>>
>>>> Glad to see this moving forward! This looks like a great start. A few minor comments on the patch itself inline below. Apologies in advance for being nitpicky.
>>>>
>>>> I don't recall whether we covered this bit specifically before, so at the risk of repeating myself... On a general note, it seems to me that a reasonable first milestone would be to have the target independent layer recognize that the ARM target wants to support object file emission. That is, have llc recognize "-filetype=obj". Right now it issues an error "target does not support generation of this file type!" (which is, of course, entirely correct for the moment). Once the classes are in place to do that, you'll start hitting all of the placeholder asserts(), which is exactly what you want, as you can interactively follow more easily the path the code wants to follow for simple cases and fill in the bits that as you go.
>>>>
>>>
>>> Sounds like a plan! Up for that next.
>>>
>>>>
>>>>> Index: lib/Target/ARM/ARM.h
>>>>> ===================================================================
>>>>> --- lib/Target/ARM/ARM.h ? ? ?(revision 114081)
>>>>> +++ lib/Target/ARM/ARM.h ? ? ?(working copy)
>>>>> @@ -26,7 +26,14 @@
>>>>> ?class FunctionPass;
>>>>> ?class JITCodeEmitter;
>>>>> ?class formatted_raw_ostream;
>>>>> +class MCCodeEmitter;
>>>>>
>>>>> +
>>>>> +MCCodeEmitter *createARM_MCCodeEmitter(const Target &,
>>>>
>>>> As a style thing, LLVM doesn't use underscores in symbol names. Just createARMMCCodeEmitter() is fine. (The underscore in the X86 equivalent is there as part of the target name, X86_32 vs. X86_64, and so is a bit misleading in this regard).
>>>>
>>>>
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx);
>>>>> +
>>>>> +
>>>>
>>>> Extra vertical whitespace here can be removed.
>>>>
>>>>> ?FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
>>>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CodeGenOpt::Level OptLevel);
>>>>>
>>>>> @@ -41,6 +48,9 @@
>>>>> ?FunctionPass *createThumb2ITBlockPass();
>>>>> ?FunctionPass *createThumb2SizeReductionPass();
>>>>>
>>>>> +
>>>>> +
>>>>> +
>>>>
>>>> Ditto. There's other instances below that can be similarly cleaned up.
>>>>
>>>>> ?extern Target TheARMTarget, TheThumbTarget;
>>>>>
>>>>> ?} // end namespace llvm;
>>>>> Index: lib/Target/ARM/ARMMCCodeEmitter.cpp
>>>>> ===================================================================
>>>>> --- lib/Target/ARM/ARMMCCodeEmitter.cpp ? ? ? (revision 0)
>>>>> +++ lib/Target/ARM/ARMMCCodeEmitter.cpp ? ? ? (revision 0)
>>>>> @@ -0,0 +1,134 @@
>>>>> +//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
>>>>> +//
>>>>> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
>>>>> +//
>>>>> +// This file is distributed under the University of Illinois Open Source
>>>>> +// License. See LICENSE.TXT for details.
>>>>> +//
>>>>> +//===----------------------------------------------------------------------===//
>>>>> +//
>>>>> +// This file implements the ARMMCCodeEmitter class.
>>>>> +//
>>>>> +//===----------------------------------------------------------------------===//
>>>>> +
>>>>> +#define DEBUG_TYPE "ARM-emitter"
>>>>
>>>> Lower-case here, i.e., "arm-emitter" is more consistent with other options of this sort.
>>>>
>>>>> +#include "ARM.h"
>>>>> +#include "ARMInstrInfo.h"
>>>>> +//#include "ARMFixupKinds.h"
>>>>> +#include "llvm/MC/MCCodeEmitter.h"
>>>>> +#include "llvm/MC/MCExpr.h"
>>>>> +#include "llvm/MC/MCInst.h"
>>>>> +#include "llvm/Support/raw_ostream.h"
>>>>> +using namespace llvm;
>>>>> +
>>>>> +namespace {
>>>>> +class ARMMCCodeEmitter : public MCCodeEmitter {
>>>>> + ?ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
>>>>> + ?void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
>>>>> + ?const TargetMachine &TM;
>>>>> + ?const TargetInstrInfo &TII;
>>>>> + ?MCContext &Ctx;
>>>>> + ?bool Is64BitMode;
>>>>
>>>> Can just remove the extra hold-over bool from the x86 bit here. No 64-bit mode on ARM. :)
>>>>
>>>>> +public:
>>>>> + ?ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
>>>>> + ? ?: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
>>>>> + ?}
>>>>> +
>>>>> + ?~ARMMCCodeEmitter() {}
>>>>> +
>>>>> + ?unsigned getNumFixupKinds() const {
>>>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>> + ?}
>>>>> +
>>>>> + ?const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
>>>>> + ? ?static MCFixupKindInfo rtn;
>>>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>
>>>> Totally not a big deal, but I tend to phrase these sorts of things as simply "<function name> not yet implemented." Personal preference to simply state accurately the status of things rather than indicate anything about the future. Plus, then when I see the assert, I know specifically which function is being hit, rather than just the general name of the feature.
>>>>
>>>>> + ? ?return rtn;
>>>>> + ?}
>>>>> +
>>>>> + ?static unsigned GetARMRegNum(const MCOperand &MO) {
>>>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>> + ? ?return 0;
>>>>> + ?}
>>>>> +
>>>>> + ?void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
>>>>> + ? ?OS << (char)C;
>>>>> + ? ?++CurByte;
>>>>> + ?}
>>>>> +
>>>>> + ?void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
>>>>> + ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const {
>>>>> + ? ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>
>>>> Is this assert necessary? I don't know any reason why the implementation below wouldn't be sufficient.
>>>>
>>>>> + ? ?// Output the constant in little endian byte order.
>>>>> + ? ?for (unsigned i = 0; i != Size; ++i) {
>>>>> + ? ? ?EmitByte(Val & 255, CurByte, OS);
>>>>> + ? ? ?Val >>= 8;
>>>>> + ? ?}
>>>>> + ?}
>>>>> +
>>>>> + ?void EmitImmediate(const MCOperand &Disp,
>>>>> + ? ? ? ? ? ? ? ? ? ? unsigned ImmSize, MCFixupKind FixupKind,
>>>>> + ? ? ? ? ? ? ? ? ? ? unsigned &CurByte, raw_ostream &OS,
>>>>> + ? ? ? ? ? ? ? ? ? ? SmallVectorImpl<MCFixup> &Fixups,
>>>>> + ? ? ? ? ? ? ? ? ? ? int ImmOffset = 0) const;
>>>>> +
>>>>> +
>>>>> +
>>>>> +
>>>>> +
>>>>> + ?void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? SmallVectorImpl<MCFixup> &Fixups) const;
>>>>> +
>>>>> + ?void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ?const MCInst &MI, const TargetInstrDesc &Desc,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const;
>>>>> +};
>>>>> +
>>>>> +} // end anonymous namespace
>>>>> +
>>>>> +
>>>>> +MCCodeEmitter *llvm::createARM_MCCodeEmitter(const Target &,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TargetMachine &TM,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx) {
>>>>> + ?return new ARMMCCodeEmitter(TM, Ctx);
>>>>> +}
>>>>> +
>>>>> +
>>>>> +
>>>>> +/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
>>>>> +/// in an instruction with the specified TSFlags.
>>>>> +static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
>>>>> + ?static MCFixupKind rtn;
>>>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>> + ?return rtn;
>>>>> +}
>>>>> +
>>>>> +
>>>>> +void ARMMCCodeEmitter::
>>>>> +EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
>>>>> + ? ? ? ? ? ? ?unsigned &CurByte, raw_ostream &OS,
>>>>> + ? ? ? ? ? ? ?SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
>>>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>> +}
>>>>> +
>>>>> +
>>>>> +
>>>>> +
>>>>> +
>>>>> +
>>>>> +/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
>>>>> +///
>>>>> +/// MemOperand is the operand # of the start of a memory operand if present. ?If
>>>>> +/// Not present, it is -1.
>>>>> +void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int MemOperand, const MCInst &MI,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetInstrDesc &Desc,
>>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &OS) const {
>>>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>> +}
>>>>> +
>>>>> +void ARMMCCodeEmitter::
>>>>> +EncodeInstruction(const MCInst &MI, raw_ostream &OS,
>>>>> + ? ? ? ? ? ? ? ? ?SmallVectorImpl<MCFixup> &Fixups) const {
>>>>> + ?assert(0 && "ARMCodeEmitter will be implemented soon");
>>>>> +}
>>>>> Index: lib/Target/ARM/CMakeLists.txt
>>>>> ===================================================================
>>>>> --- lib/Target/ARM/CMakeLists.txt ? ? (revision 114081)
>>>>> +++ lib/Target/ARM/CMakeLists.txt ? ? (working copy)
>>>>> @@ -28,6 +28,7 @@
>>>>> ? ?ARMISelLowering.cpp
>>>>> ? ?ARMInstrInfo.cpp
>>>>> ? ?ARMJITInfo.cpp
>>>>> + ?ARMMCCodeEmitter.cpp
>>>>> ? ?ARMLoadStoreOptimizer.cpp
>>>>> ? ?ARMMCAsmInfo.cpp
>>>>> ? ?ARMMCInstLower.cpp
>>>>>
>>>>
>>> <arm-mc-elf.patch3>
>>
>>
>
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From jasonwkim at google.com  Mon Sep 20 00:37:26 2010
From: jasonwkim at google.com (Jason Kim)
Date: Sun, 19 Sep 2010 22:37:26 -0700
Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
Message-ID: <AANLkTin7esVNJY9rN6Cy242k-HqxX1zi5da+esYBpoKj@mail.gmail.com>

Double oops.
I somehow missed a compile breaking typo.
Apologies for the noise.
Tested against clean build dir.
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From anton at korobeynikov.info  Mon Sep 20 02:11:25 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Mon, 20 Sep 2010 11:11:25 +0400
Subject: [llvm-commits] [llvm] r114312 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
In-Reply-To: <94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
References: <20100919195156.0FF242A6C12E@llvm.org>
	<94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
Message-ID: <AANLkTimd64MJJTpY5CFagEH=N6S8G+k2xgfqnijiEaHz@mail.gmail.com>

> What is the compile-time performance impact of this?
Even if the impact is significant - will it make sense to enable it
at, say,  -O3 ?

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From daniel at zuster.org  Mon Sep 20 10:17:19 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 20 Sep 2010 15:17:19 -0000
Subject: [llvm-commits] [test-suite] r114322 -
 /test-suite/trunk/SingleSource/Regression/C++/fixups.reference_output
Message-ID: <20100920151719.87D6F2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Sep 20 10:17:19 2010
New Revision: 114322

URL: http://llvm.org/viewvc/llvm-project?rev=114322&view=rev
Log:
Add fixups reference output.

Added:
    test-suite/trunk/SingleSource/Regression/C++/fixups.reference_output

Added: test-suite/trunk/SingleSource/Regression/C++/fixups.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Regression/C%2B%2B/fixups.reference_output?rev=114322&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/Regression/C++/fixups.reference_output (added)
+++ test-suite/trunk/SingleSource/Regression/C++/fixups.reference_output Mon Sep 20 10:17:19 2010
@@ -0,0 +1 @@
+exit 0



From clattner at apple.com  Mon Sep 20 10:33:34 2010
From: clattner at apple.com (Chris Lattner)
Date: Mon, 20 Sep 2010 08:33:34 -0700
Subject: [llvm-commits] [llvm] r114312 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
In-Reply-To: <AANLkTimd64MJJTpY5CFagEH=N6S8G+k2xgfqnijiEaHz@mail.gmail.com>
References: <20100919195156.0FF242A6C12E@llvm.org>
	<94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
	<AANLkTimd64MJJTpY5CFagEH=N6S8G+k2xgfqnijiEaHz@mail.gmail.com>
Message-ID: <596F175E-F5E0-47D4-86BE-99CE650B5BF7@apple.com>


On Sep 20, 2010, at 12:11 AM, Anton Korobeynikov wrote:

>> What is the compile-time performance impact of this?
> Even if the impact is significant - will it make sense to enable it
> at, say,  -O3 ?

It depends on how significant.  If it explodes compile time in some case, then we should fix that before enabling it anywhere.

On a random note, Owen why do you need to enable things on mainline to see if they'll break regression tests and llvm-test?

-Chris

From anton at korobeynikov.info  Mon Sep 20 10:42:25 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Mon, 20 Sep 2010 19:42:25 +0400
Subject: [llvm-commits] [llvm] r114312 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
In-Reply-To: <596F175E-F5E0-47D4-86BE-99CE650B5BF7@apple.com>
References: <20100919195156.0FF242A6C12E@llvm.org>
	<94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
	<AANLkTimd64MJJTpY5CFagEH=N6S8G+k2xgfqnijiEaHz@mail.gmail.com>
	<596F175E-F5E0-47D4-86BE-99CE650B5BF7@apple.com>
Message-ID: <AANLkTi=KK=HqR7J8JyC3poPseyTy7Co2UciTuJHHaqo6@mail.gmail.com>

> It depends on how significant. ?If it explodes compile time in some case, then we should fix that before enabling it anywhere.
Well, yes, surely :) However right now combiner-aa is a prerequisite
for, for example, mem-mem instructions on msp430

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From clattner at apple.com  Mon Sep 20 10:46:11 2010
From: clattner at apple.com (Chris Lattner)
Date: Mon, 20 Sep 2010 08:46:11 -0700
Subject: [llvm-commits] [llvm] r114312 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
In-Reply-To: <AANLkTi=KK=HqR7J8JyC3poPseyTy7Co2UciTuJHHaqo6@mail.gmail.com>
References: <20100919195156.0FF242A6C12E@llvm.org>
	<94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
	<AANLkTimd64MJJTpY5CFagEH=N6S8G+k2xgfqnijiEaHz@mail.gmail.com>
	<596F175E-F5E0-47D4-86BE-99CE650B5BF7@apple.com>
	<AANLkTi=KK=HqR7J8JyC3poPseyTy7Co2UciTuJHHaqo6@mail.gmail.com>
Message-ID: <4AA0AA44-C2A9-4A43-84D4-1A93FB02FDAD@apple.com>


On Sep 20, 2010, at 8:42 AM, Anton Korobeynikov wrote:

>> It depends on how significant.  If it explodes compile time in some case, then we should fix that before enabling it anywhere.
> Well, yes, surely :) However right now combiner-aa is a prerequisite
> for, for example, mem-mem instructions on msp430

I'm not suggesting it be ripped out, it should be fixed and turned on by default - ideally at -O2.

-Chris

From espindola at google.com  Mon Sep 20 10:46:37 2010
From: espindola at google.com (Rafael Espindola)
Date: Mon, 20 Sep 2010 11:46:37 -0400
Subject: [llvm-commits] [llvm] r114241 -
	/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <2FC393C3-C7B1-4B83-964E-0BA2166DC37B@apple.com>
References: <20100918000438.063012A6C12C@llvm.org>
	<69EFC494-A4B4-4234-8DDD-C46812EF2CD2@apple.com>
	<2FC393C3-C7B1-4B83-964E-0BA2166DC37B@apple.com>
Message-ID: <AANLkTimNbX_HmuVSV9HsVmoW74VTyDoyk8SSf=fqDhtc@mail.gmail.com>

> LLVM's reliance on the host libm goes way back. Alternatives to using the
> host libm for constant folding exist, but LLVM has not yet pursued them.

Do we have a bug for this? Should we?

> Dan

Cheers,
-- 
Rafael ?vila de Esp?ndola


From clattner at apple.com  Mon Sep 20 10:56:34 2010
From: clattner at apple.com (Chris Lattner)
Date: Mon, 20 Sep 2010 08:56:34 -0700
Subject: [llvm-commits] [llvm] r114241 -
	/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <AANLkTimNbX_HmuVSV9HsVmoW74VTyDoyk8SSf=fqDhtc@mail.gmail.com>
References: <20100918000438.063012A6C12C@llvm.org>
	<69EFC494-A4B4-4234-8DDD-C46812EF2CD2@apple.com>
	<2FC393C3-C7B1-4B83-964E-0BA2166DC37B@apple.com>
	<AANLkTimNbX_HmuVSV9HsVmoW74VTyDoyk8SSf=fqDhtc@mail.gmail.com>
Message-ID: <EE7BCD96-B509-4DDF-A0DB-B7E239F8D935@apple.com>


On Sep 20, 2010, at 8:46 AM, Rafael Espindola wrote:

>> LLVM's reliance on the host libm goes way back. Alternatives to using the
>> host libm for constant folding exist, but LLVM has not yet pursued them.
> 
> Do we have a bug for this? Should we?

This would require writing a native "sin" implementation for APFloat, for example.  I think that handling the exceptional cases explicitly is easy, implementing the native version is more work (but clearly not intractable).

-Chris

From daniel at zuster.org  Mon Sep 20 11:38:06 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 20 Sep 2010 09:38:06 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
 lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <20100917013806.562CB2A6C12C@llvm.org>
References: <20100917013806.562CB2A6C12C@llvm.org>
Message-ID: <AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>

Hi Dan,

This change doesn't seem right to me. It is introducing a host ==
target dependency of sorts. Somehow this information should be coming
from the Target definitions or information in the IR file, not from
the host's fenv() implementation.

 - Daniel

On Thu, Sep 16, 2010 at 6:38 PM, Dan Gohman <gohman at apple.com> wrote:
> Author: djg
> Date: Thu Sep 16 20:38:06 2010
> New Revision: 114148
>
> URL: http://llvm.org/viewvc/llvm-project?rev=114148&view=rev
> Log:
> Fix the folding of floating-point math library calls, like sin(infinity),
> so that it detects errors on platforms where libm doesn't set errno.
> It's still subject to host libm details though.
>
> Added:
> ? ?llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
> Modified:
> ? ?llvm/trunk/lib/Analysis/ConstantFolding.cpp
>
> Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=114148&r1=114147&r2=114148&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Sep 16 20:38:06 2010
> @@ -32,6 +32,7 @@
> ?#include "llvm/Support/MathExtras.h"
> ?#include <cerrno>
> ?#include <cmath>
> +#include <fenv.h>
> ?using namespace llvm;
>
> ?//===----------------------------------------------------------------------===//
> @@ -1039,9 +1040,12 @@
>
> ?static Constant *ConstantFoldFP(double (*NativeFP)(double), double V,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const Type *Ty) {
> + ?feclearexcept(FE_ALL_EXCEPT);
> ? errno = 0;
> ? V = NativeFP(V);
> - ?if (errno != 0) {
> + ?if (errno != 0 ||
> + ? ? ?fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) {
> + ? ?feclearexcept(FE_ALL_EXCEPT);
> ? ? errno = 0;
> ? ? return 0;
> ? }
> @@ -1056,9 +1060,12 @@
>
> ?static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? double V, double W, const Type *Ty) {
> + ?feclearexcept(FE_ALL_EXCEPT);
> ? errno = 0;
> ? V = NativeFP(V, W);
> - ?if (errno != 0) {
> + ?if (errno != 0 ||
> + ? ? ?fetestexcept(FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)) {
> + ? ?feclearexcept(FE_ALL_EXCEPT);
> ? ? errno = 0;
> ? ? return 0;
> ? }
>
> Added: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114148&view=auto
> ==============================================================================
> --- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (added)
> +++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Thu Sep 16 20:38:06 2010
> @@ -0,0 +1,19 @@
> +; RUN: opt -instcombine -S < %s | FileCheck %s
> +
> +; This shouldn't fold, because sin(inf) is invalid.
> +; CHECK: @foo
> +; CHECK: ? %t = call double @sin(double 0x7FF0000000000000)
> +define double @foo() {
> + ?%t = call double @sin(double 0x7FF0000000000000)
> + ?ret double %t
> +}
> +
> +; This should fold.
> +; CHECK: @bar
> +; CHECK: ? ret double 0x3FDA6026360C2F91
> +define double @bar() {
> + ?%t = call double @sin(double 9.0)
> + ?ret double %t
> +}
> +
> +declare double @sin(double)
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From espindola at google.com  Mon Sep 20 11:40:09 2010
From: espindola at google.com (Rafael Espindola)
Date: Mon, 20 Sep 2010 12:40:09 -0400
Subject: [llvm-commits] [patch] Don't relax all references to non temporary
	symbols
Message-ID: <AANLkTikZ9k==N=Hx4UHsEJmvE2-ynQpaBi=SgxuRT2jr@mail.gmail.com>

Currently llvm-mc will relax both jmp instructions in:

--------------------
.globl foo
        jmp bar
        jmp foo
bar:
foo:
------------------

I think that by changing HasReliableSymbolDifference to true in ELF we
should be able to avoid both relaxations. That is probably the best
thing to do, but unfortunately that is not what gnu as does. In the
above example it will relax the jump to foo, but not to bar. Matching
GNU as behavior for now makes debugging easier, so, if possible, I
would like to check something similar to the attached patch.

The patch is clearly hackish. The two ways I can think of improving it a bit are
*) Changing the isELF to something like HasScatteredGlobalSymbols. Not
sure if that helps a lot.
*) Moving the isScatteredFixupFullyResolved,
isScatteredFixupFullyResolvedSimple and isFixupFullyResolvedELF to the
backend.

Please let me know if you have any preferences.

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From resistor at mac.com  Mon Sep 20 12:12:01 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 20 Sep 2010 10:12:01 -0700
Subject: [llvm-commits] [llvm] r114312 -
 /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
In-Reply-To: <94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
References: <20100919195156.0FF242A6C12E@llvm.org>
	<94477953-0100-4B20-B3AC-45B084D04FCD@apple.com>
Message-ID: <F824B849-4AA4-463C-9161-80CFC4A4E91D@mac.com>


On Sep 19, 2010, at 1:12 PM, Chris Lattner wrote:

> 
> On Sep 19, 2010, at 12:51 PM, Owen Anderson wrote:
> 
>> Author: resistor
>> Date: Sun Sep 19 14:51:55 2010
>> New Revision: 114312
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=114312&view=rev
>> Log:
>> Tentatively enabled DAGCombiner Alias Analysis by default.  As far as I know,
>> r114268 fixed the last of the blockers to enabling it.  I will be monitoring
>> for failures.
> 
> What is the compile-time performance impact of this?

It exists, but doesn't seem to be very large.  I've measure a codegen time slowdown of ~1% on 403.gcc, for instance.

--Owen

From espindola at google.com  Mon Sep 20 12:59:51 2010
From: espindola at google.com (Rafael Espindola)
Date: Mon, 20 Sep 2010 13:59:51 -0400
Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <AANLkTin7esVNJY9rN6Cy242k-HqxX1zi5da+esYBpoKj@mail.gmail.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
	<AANLkTin7esVNJY9rN6Cy242k-HqxX1zi5da+esYBpoKj@mail.gmail.com>
Message-ID: <AANLkTikP9SZwbuRFk9yaQj33j4Jr3iTDC4+EsHB13kXd@mail.gmail.com>

On 20 September 2010 01:37, Jason Kim <jasonwkim at google.com> wrote:
> Double oops.
> I somehow missed a compile breaking typo.
> Apologies for the noise.
> Tested against clean build dir.

There something strange with the patch. I cannot apply it to 114212. I
have attached the .rej file.

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From eli.friedman at gmail.com  Mon Sep 20 13:42:38 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 20 Sep 2010 11:42:38 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
 lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
References: <20100917013806.562CB2A6C12C@llvm.org>
	<AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
Message-ID: <AANLkTikph85dp7fSpPX6-izkP0DBGs2f6rFAfMdxdM44@mail.gmail.com>

On Mon, Sep 20, 2010 at 9:38 AM, Daniel Dunbar <daniel at zuster.org> wrote:
> Hi Dan,
>
> This change doesn't seem right to me. It is introducing a host ==
> target dependency of sorts. Somehow this information should be coming
> from the Target definitions or information in the IR file, not from
> the host's fenv() implementation.

What are you talking about?  This change is just to detect errors
coming out of the host's math functions, and doesn't really have much
to do with the target's implementation of sin().

-Eli

From evan.cheng at apple.com  Mon Sep 20 14:12:56 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 20 Sep 2010 19:12:56 -0000
Subject: [llvm-commits] [llvm] r114338 -
	/llvm/trunk/lib/CodeGen/MachineSink.cpp
Message-ID: <20100920191256.2502B2A6C12C@llvm.org>

Author: evancheng
Date: Mon Sep 20 14:12:55 2010
New Revision: 114338

URL: http://llvm.org/viewvc/llvm-project?rev=114338&view=rev
Log:
Avoid splitting critical edge twice for a set of PHI uses.

Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=114338&r1=114337&r2=114338&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Mon Sep 20 14:12:55 2010
@@ -86,11 +86,11 @@
     MachineBasicBlock *SplitCriticalEdge(MachineInstr *MI,
                                          MachineBasicBlock *From,
                                          MachineBasicBlock *To,
-                                         bool AllPHIUse);
+                                         bool BreakPHIEdge);
     bool SinkInstruction(MachineInstr *MI, bool &SawStore);
     bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
                                  MachineBasicBlock *DefMBB,
-                                 bool &AllPHIUse, bool &LocalUse) const;
+                                 bool &BreakPHIEdge, bool &LocalUse) const;
     bool PerformTrivialForwardCoalescing(MachineInstr *MI,
                                          MachineBasicBlock *MBB);
   };
@@ -138,7 +138,8 @@
 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
                                         MachineBasicBlock *MBB,
                                         MachineBasicBlock *DefMBB,
-                                        bool &AllPHIUse, bool &LocalUse) const {
+                                        bool &BreakPHIEdge,
+                                        bool &LocalUse) const {
   assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
          "Only makes sense for vregs");
 
@@ -150,7 +151,10 @@
   // the definition of the vreg.  Dwarf generator handles this although the
   // user might not get the right info at runtime.
 
-  // PHI is in the successor BB. e.g.
+  // BreakPHIEdge is true if all the uses are in the successor MBB being sunken
+  // into and they are all PHI nodes. In this case, machine-sink must break
+  // the critical edge first. e.g.
+  //
   // BB#1: derived from LLVM BB %bb4.preheader
   //   Predecessors according to CFG: BB#0
   //     ...
@@ -162,9 +166,7 @@
   // BB#2: derived from LLVM BB %bb.nph
   //   Predecessors according to CFG: BB#0 BB#1
   //     %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
-  //
-  // Machine sink should break the critical edge first.
-  AllPHIUse = true;
+  BreakPHIEdge = true;
   for (MachineRegisterInfo::use_nodbg_iterator
          I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end();
        I != E; ++I) {
@@ -172,11 +174,11 @@
     MachineBasicBlock *UseBlock = UseInst->getParent();
     if (!(UseBlock == MBB && UseInst->isPHI() &&
           UseInst->getOperand(I.getOperandNo()+1).getMBB() == DefMBB)) {
-      AllPHIUse = false;
+      BreakPHIEdge = false;
       break;
     }
   }
-  if (AllPHIUse)
+  if (BreakPHIEdge)
     return true;
 
   for (MachineRegisterInfo::use_nodbg_iterator
@@ -304,7 +306,7 @@
 MachineBasicBlock *MachineSinking::SplitCriticalEdge(MachineInstr *MI,
                                                      MachineBasicBlock *FromBB,
                                                      MachineBasicBlock *ToBB,
-                                                     bool AllPHIUse) {
+                                                     bool BreakPHIEdge) {
   if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB))
     return 0;
 
@@ -356,7 +358,7 @@
   //
   // There is no need to do this check if all the uses are PHI nodes. PHI
   // sources are only defined on the specific predecessor edges.
-  if (!AllPHIUse) {
+  if (!BreakPHIEdge) {
     for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(),
            E = ToBB->pred_end(); PI != E; ++PI) {
       if (*PI == FromBB)
@@ -392,7 +394,7 @@
   // decide.
   MachineBasicBlock *SuccToSinkTo = 0;
 
-  bool AllPHIUse = false;
+  bool BreakPHIEdge = false;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg()) continue;  // Ignore non-register operands.
@@ -452,7 +454,7 @@
         // must be sinkable to the same block.
         bool LocalUse = false;
         if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock,
-                                     AllPHIUse, LocalUse))
+                                     BreakPHIEdge, LocalUse))
           return false;
 
         continue;
@@ -464,7 +466,7 @@
            E = ParentBlock->succ_end(); SI != E; ++SI) {
         bool LocalUse = false;
         if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock,
-                                    AllPHIUse, LocalUse)) {
+                                    BreakPHIEdge, LocalUse)) {
           SuccToSinkTo = *SI;
           break;
         }
@@ -538,7 +540,7 @@
       DEBUG(dbgs() << "Sinking along critical edge.\n");
     else {
       MachineBasicBlock *NewSucc =
-        SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, AllPHIUse);
+        SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
       if (!NewSucc) {
         DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
                         "break critical edge\n");
@@ -550,15 +552,19 @@
               << " -- BB#" << SuccToSinkTo->getNumber() << '\n');
         SuccToSinkTo = NewSucc;
         ++NumSplit;
+        BreakPHIEdge = false;
       }
     }
   }
 
-  if (AllPHIUse) {
+  if (BreakPHIEdge) {
+    // BreakPHIEdge is true if all the uses are in the successor MBB being
+    // sunken into and they are all PHI nodes. In this case, machine-sink must
+    // break the critical edge first.
     if (NumSplit == SplitLimit)
       return false;
     MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock,
-                                                   SuccToSinkTo, AllPHIUse);
+                                                   SuccToSinkTo, BreakPHIEdge);
     if (!NewSucc) {
       DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
             "break critical edge\n");



From rafael.espindola at gmail.com  Mon Sep 20 14:20:47 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 20 Sep 2010 19:20:47 -0000
Subject: [llvm-commits] [llvm] r114339 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/basic-elf.ll
 test/MC/ELF/relocation.s
Message-ID: <20100920192047.452002A6C12C@llvm.org>

Author: rafael
Date: Mon Sep 20 14:20:47 2010
New Revision: 114339

URL: http://llvm.org/viewvc/llvm-project?rev=114339&view=rev
Log:
Produce a R_X86_64_32 when the value is >=0.

Added:
    llvm/trunk/test/MC/ELF/relocation.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/test/MC/ELF/basic-elf.ll

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114339&r1=114338&r2=114339&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Sep 20 14:20:47 2010
@@ -541,10 +541,13 @@
       case X86::reloc_pcrel_4byte:
       case FK_Data_4:
         // check that the offset fits within a signed long
-        if (isInt<32>(Target.getConstant()))
+        if (Target.getConstant() < 0) {
+          assert(isInt<32>(Target.getConstant()));
           Type = ELF::R_X86_64_32S;
-        else
+        } else {
+          assert(isUInt<32>(Target.getConstant()));
           Type = ELF::R_X86_64_32;
+        }
         break;
       case FK_Data_2: Type = ELF::R_X86_64_16; break;
       case X86::reloc_pcrel_1byte:

Modified: llvm/trunk/test/MC/ELF/basic-elf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/basic-elf.ll?rev=114339&r1=114338&r2=114339&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/basic-elf.ll (original)
+++ llvm/trunk/test/MC/ELF/basic-elf.ll Mon Sep 20 14:20:47 2010
@@ -72,7 +72,7 @@
 ; 64:   ('_relocations', [
 ; 64:     # Relocation 0
 ; 64:     (('r_offset', 5)
-; 64:      ('r_type', 11)
+; 64:      ('r_type', 10)
 ; 64:      ('r_addend', 0)
 ; 64:     ),
 ; 64:     # Relocation 1
@@ -82,7 +82,7 @@
 ; 64:     ),
 ; 64:     # Relocation 2
 ; 64:     (('r_offset', 15)
-; 64:      ('r_type', 11)
+; 64:      ('r_type', 10)
 ; 64:      ('r_addend', 6)
 ; 64:     ),
 ; 64:     # Relocation 3

Added: llvm/trunk/test/MC/ELF/relocation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relocation.s?rev=114339&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/relocation.s (added)
+++ llvm/trunk/test/MC/ELF/relocation.s Mon Sep 20 14:20:47 2010
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
+
+// Test that we produce a R_X86_64_32.
+
+        .long   Lset1
+
+
+// CHECK: # Relocation 0
+// CHECK-NEXT:  (('r_offset', 0)
+// CHECK-NEXT:   ('r_sym', 4)
+// CHECK-NEXT:   ('r_type', 10)
+// CHECK-NEXT:   ('r_addend', 0)



From grosbach at apple.com  Mon Sep 20 14:32:20 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 20 Sep 2010 19:32:20 -0000
Subject: [llvm-commits] [llvm] r114340 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseRegisterInfo.cpp
 lib/Target/ARM/ARMMachineFunctionInfo.h
 lib/Target/ARM/Thumb1RegisterInfo.cpp
 test/CodeGen/ARM/lsr-code-insertion.ll
 test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
Message-ID: <20100920193220.B347B2A6C12C@llvm.org>

Author: grosbach
Date: Mon Sep 20 14:32:20 2010
New Revision: 114340

URL: http://llvm.org/viewvc/llvm-project?rev=114340&view=rev
Log:
Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635


Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll
    llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=114340&r1=114339&r2=114340&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Sep 20 14:32:20 2010
@@ -77,8 +77,8 @@
   static const unsigned DarwinCalleeSavedRegs[] = {
     // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
     // register.
-    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
-    ARM::R11, ARM::R10, ARM::R8,
+    ARM::LR, ARM::R11, ARM::R10, ARM::R8,
+    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
 
     ARM::D15, ARM::D14, ARM::D13, ARM::D12,
     ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
@@ -701,7 +701,6 @@
   bool LRSpilled = false;
   unsigned NumGPRSpills = 0;
   SmallVector<unsigned, 4> UnspilledCS1GPRs;
-  SmallVector<unsigned, 4> UnspilledCS2GPRs;
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   MachineFrameInfo *MFI = MF.getFrameInfo();
 
@@ -768,23 +767,7 @@
         break;
       }
     } else {
-      if (!STI.isTargetDarwin()) {
-        UnspilledCS1GPRs.push_back(Reg);
-        continue;
-      }
-
-      switch (Reg) {
-      case ARM::R4:
-      case ARM::R5:
-      case ARM::R6:
-      case ARM::R7:
-      case ARM::LR:
-        UnspilledCS1GPRs.push_back(Reg);
-        break;
-      default:
-        UnspilledCS2GPRs.push_back(Reg);
-        break;
-      }
+      UnspilledCS1GPRs.push_back(Reg);
     }
   }
 
@@ -860,13 +843,6 @@
             break;
           }
         }
-      } else if (!UnspilledCS2GPRs.empty() &&
-                 !AFI->isThumb1OnlyFunction()) {
-        unsigned Reg = UnspilledCS2GPRs.front();
-        MF.getRegInfo().setPhysRegUsed(Reg);
-        AFI->setCSRegisterIsSpilled(Reg);
-        if (!isReservedReg(MF, Reg))
-          ExtraCSSpill = true;
       }
     }
 
@@ -890,17 +866,6 @@
           NumExtras--;
         }
       }
-      // For non-Thumb1 functions, also check for hi-reg CS registers
-      if (!AFI->isThumb1OnlyFunction()) {
-        while (NumExtras && !UnspilledCS2GPRs.empty()) {
-          unsigned Reg = UnspilledCS2GPRs.back();
-          UnspilledCS2GPRs.pop_back();
-          if (!isReservedReg(MF, Reg)) {
-            Extras.push_back(Reg);
-            NumExtras--;
-          }
-        }
-      }
       if (Extras.size() && NumExtras == 0) {
         for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
           MF.getRegInfo().setPhysRegUsed(Extras[i]);
@@ -958,10 +923,8 @@
 
   FrameReg = ARM::SP;
   Offset += SPAdj;
-  if (AFI->isGPRCalleeSavedArea1Frame(FI))
-    return Offset - AFI->getGPRCalleeSavedArea1Offset();
-  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
-    return Offset - AFI->getGPRCalleeSavedArea2Offset();
+  if (AFI->isGPRCalleeSavedAreaFrame(FI))
+    return Offset - AFI->getGPRCalleeSavedAreaOffset();
   else if (AFI->isDPRCalleeSavedAreaFrame(FI))
     return Offset - AFI->getDPRCalleeSavedAreaOffset();
 
@@ -1651,8 +1614,7 @@
 }
 
 /// Move iterator past the next bunch of callee save load / store ops for
-/// the particular spill area (1: integer area 1, 2: integer area 2,
-/// 3: fp area, 0: don't care).
+/// the particular spill area (1: integer area 1, 2: fp area, 0: don't care).
 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator &MBBI,
                                    int Opc1, int Opc2, unsigned Area,
@@ -1665,15 +1627,13 @@
       unsigned Category = 0;
       switch (MBBI->getOperand(0).getReg()) {
       case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
+      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
       case ARM::LR:
         Category = 1;
         break;
-      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
-        Category = STI.isTargetDarwin() ? 2 : 1;
-        break;
       case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
       case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
-        Category = 3;
+        Category = 2;
         break;
       default:
         Done = true;
@@ -1703,7 +1663,7 @@
 
   // Determine the sizes of each callee-save spill areas and record which frame
   // belongs to which callee-save spill areas.
-  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
+  unsigned GPRCSSize = 0/*, GPRCS2Size = 0*/, DPRCSSize = 0;
   int FramePtrSpillFI = 0;
 
   // Allocate the vararg register save area. This is not counted in NumBytes.
@@ -1724,25 +1684,15 @@
     case ARM::R5:
     case ARM::R6:
     case ARM::R7:
-    case ARM::LR:
-      if (Reg == FramePtr)
-        FramePtrSpillFI = FI;
-      AFI->addGPRCalleeSavedArea1Frame(FI);
-      GPRCS1Size += 4;
-      break;
     case ARM::R8:
     case ARM::R9:
     case ARM::R10:
     case ARM::R11:
+    case ARM::LR:
       if (Reg == FramePtr)
         FramePtrSpillFI = FI;
-      if (STI.isTargetDarwin()) {
-        AFI->addGPRCalleeSavedArea2Frame(FI);
-        GPRCS2Size += 4;
-      } else {
-        AFI->addGPRCalleeSavedArea1Frame(FI);
-        GPRCS1Size += 4;
-      }
+      AFI->addGPRCalleeSavedAreaFrame(FI);
+      GPRCSSize += 4;
       break;
     default:
       AFI->addDPRCalleeSavedAreaFrame(FI);
@@ -1750,15 +1700,11 @@
     }
   }
 
-  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
-  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
+  // Build the new SUBri to adjust SP for integer callee-save spill area.
+  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize);
   movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
 
   // Set FP to point to the stack slot that contains the previous FP.
-  // For Darwin, FP is R7, which has now been stored in spill area 1.
-  // Otherwise, if this is not Darwin, all the callee-saved registers go
-  // into spill area 1, including the FP in R11.  In either case, it is
-  // now safe to emit this assignment.
   bool HasFP = hasFP(MF);
   if (HasFP) {
     unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
@@ -1768,25 +1714,19 @@
     AddDefaultCC(AddDefaultPred(MIB));
   }
 
-  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
-  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
-
   // Build the new SUBri to adjust SP for FP callee-save spill area.
-  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
   emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
 
   // Determine starting offsets of spill areas.
-  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
-  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
-  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
+  unsigned DPRCSOffset  = NumBytes - (GPRCSSize + DPRCSSize);
+  unsigned GPRCSOffset = DPRCSOffset + DPRCSSize;
   if (HasFP)
     AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
                                 NumBytes);
-  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
-  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
+  AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset);
   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
 
-  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
+  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 2, STI);
   NumBytes = DPRCSOffset;
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
@@ -1801,8 +1741,7 @@
     AFI->setShouldRestoreSPFromFP(true);
   }
 
-  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
-  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
+  AFI->setGPRCalleeSavedAreaSize(GPRCSSize);
   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 
   // If we need dynamic stack realignment, do it here. Be paranoid and make
@@ -1904,8 +1843,7 @@
     }
 
     // Move SP to start of FP callee save spill area.
-    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
-                 AFI->getGPRCalleeSavedArea2Size() +
+    NumBytes -= (AFI->getGPRCalleeSavedAreaSize() +
                  AFI->getDPRCalleeSavedAreaSize());
 
     // Reset SP based on frame pointer only if the stack frame extends beyond
@@ -1931,17 +1869,13 @@
     } else if (NumBytes)
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
 
-    // Move SP to start of integer callee save spill area 2.
-    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
+    // Move SP to start of integer callee save spill area.
+    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 2, STI);
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
 
-    // Move SP to start of integer callee save spill area 1.
-    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
-    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
-
     // Move SP to SP upon entry to the function.
     movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
-    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
+    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize());
   }
 
   if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||

Modified: llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h?rev=114340&r1=114339&r2=114340&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h Mon Sep 20 14:32:20 2010
@@ -55,28 +55,23 @@
   /// spill stack offset.
   unsigned FramePtrSpillOffset;
 
-  /// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
-  /// register spills areas. For Mac OS X:
+  /// GPRCSOffset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
+  /// register spills areas (excluding R9 for Mac OS X):
   ///
-  /// GPR callee-saved (1) : r4, r5, r6, r7, lr
-  /// --------------------------------------------
-  /// GPR callee-saved (2) : r8, r10, r11
+  /// GPR callee-saved (1) : r4, r5, r6, r7, r8, r9, r10, r11, lr
   /// --------------------------------------------
   /// DPR callee-saved : d8 - d15
-  unsigned GPRCS1Offset;
-  unsigned GPRCS2Offset;
+  unsigned GPRCSOffset;
   unsigned DPRCSOffset;
 
-  /// GPRCS1Size, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills
+  /// GPRCSSize, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills
   /// areas.
-  unsigned GPRCS1Size;
-  unsigned GPRCS2Size;
+  unsigned GPRCSSize;
   unsigned DPRCSSize;
 
-  /// GPRCS1Frames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices
+  /// GPRCSFrames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices
   /// which belong to these spill areas.
-  BitVector GPRCS1Frames;
-  BitVector GPRCS2Frames;
+  BitVector GPRCSFrames;
   BitVector DPRCSFrames;
 
   /// SpilledCSRegs - A BitVector mask of all spilled callee-saved registers.
@@ -101,9 +96,9 @@
     hasThumb2(false),
     VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false),
     LRSpilledForFarJump(false),
-    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
-    GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
-    GPRCS1Frames(0), GPRCS2Frames(0), DPRCSFrames(0),
+    FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0),
+    GPRCSSize(0), DPRCSSize(0),
+    GPRCSFrames(0), DPRCSFrames(0),
     JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0),
     HasITBlocks(false) {}
 
@@ -112,9 +107,9 @@
     hasThumb2(MF.getTarget().getSubtarget<ARMSubtarget>().hasThumb2()),
     VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false),
     LRSpilledForFarJump(false),
-    FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
-    GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
-    GPRCS1Frames(32), GPRCS2Frames(32), DPRCSFrames(32),
+    FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0),
+    GPRCSSize(0), DPRCSSize(0),
+    GPRCSFrames(32), DPRCSFrames(32),
     SpilledCSRegs(MF.getTarget().getRegisterInfo()->getNumRegs()),
     JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0),
     HasITBlocks(false) {}
@@ -138,31 +133,22 @@
   unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; }
   void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; }
 
-  unsigned getGPRCalleeSavedArea1Offset() const { return GPRCS1Offset; }
-  unsigned getGPRCalleeSavedArea2Offset() const { return GPRCS2Offset; }
+  unsigned getGPRCalleeSavedAreaOffset() const { return GPRCSOffset; }
   unsigned getDPRCalleeSavedAreaOffset()  const { return DPRCSOffset; }
 
-  void setGPRCalleeSavedArea1Offset(unsigned o) { GPRCS1Offset = o; }
-  void setGPRCalleeSavedArea2Offset(unsigned o) { GPRCS2Offset = o; }
+  void setGPRCalleeSavedAreaOffset(unsigned o) { GPRCSOffset = o; }
   void setDPRCalleeSavedAreaOffset(unsigned o)  { DPRCSOffset = o; }
 
-  unsigned getGPRCalleeSavedArea1Size() const { return GPRCS1Size; }
-  unsigned getGPRCalleeSavedArea2Size() const { return GPRCS2Size; }
+  unsigned getGPRCalleeSavedAreaSize() const { return GPRCSSize; }
   unsigned getDPRCalleeSavedAreaSize()  const { return DPRCSSize; }
 
-  void setGPRCalleeSavedArea1Size(unsigned s) { GPRCS1Size = s; }
-  void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; }
+  void setGPRCalleeSavedAreaSize(unsigned s) { GPRCSSize = s; }
   void setDPRCalleeSavedAreaSize(unsigned s)  { DPRCSSize = s; }
 
-  bool isGPRCalleeSavedArea1Frame(int fi) const {
-    if (fi < 0 || fi >= (int)GPRCS1Frames.size())
-      return false;
-    return GPRCS1Frames[fi];
-  }
-  bool isGPRCalleeSavedArea2Frame(int fi) const {
-    if (fi < 0 || fi >= (int)GPRCS2Frames.size())
+  bool isGPRCalleeSavedAreaFrame(int fi) const {
+    if (fi < 0 || fi >= (int)GPRCSFrames.size())
       return false;
-    return GPRCS2Frames[fi];
+    return GPRCSFrames[fi];
   }
   bool isDPRCalleeSavedAreaFrame(int fi) const {
     if (fi < 0 || fi >= (int)DPRCSFrames.size())
@@ -170,28 +156,16 @@
     return DPRCSFrames[fi];
   }
 
-  void addGPRCalleeSavedArea1Frame(int fi) {
-    if (fi >= 0) {
-      int Size = GPRCS1Frames.size();
-      if (fi >= Size) {
-        Size *= 2;
-        if (fi >= Size)
-          Size = fi+1;
-        GPRCS1Frames.resize(Size);
-      }
-      GPRCS1Frames[fi] = true;
-    }
-  }
-  void addGPRCalleeSavedArea2Frame(int fi) {
+  void addGPRCalleeSavedAreaFrame(int fi) {
     if (fi >= 0) {
-      int Size = GPRCS2Frames.size();
+      int Size = GPRCSFrames.size();
       if (fi >= Size) {
         Size *= 2;
         if (fi >= Size)
           Size = fi+1;
-        GPRCS2Frames.resize(Size);
+        GPRCSFrames.resize(Size);
       }
-      GPRCS2Frames[fi] = true;
+      GPRCSFrames[fi] = true;
     }
   }
   void addDPRCalleeSavedAreaFrame(int fi) {

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=114340&r1=114339&r2=114340&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Sep 20 14:32:20 2010
@@ -597,10 +597,8 @@
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
                MF.getFrameInfo()->getStackSize() + SPAdj;
 
-  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
-    Offset -= AFI->getGPRCalleeSavedArea1Offset();
-  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
-    Offset -= AFI->getGPRCalleeSavedArea2Offset();
+  if (AFI->isGPRCalleeSavedAreaFrame(FrameIndex))
+    Offset -= AFI->getGPRCalleeSavedAreaOffset();
   else if (MF.getFrameInfo()->hasVarSizedObjects()) {
     assert(SPAdj == 0 && hasFP(MF) && "Unexpected");
     // There are alloca()'s in this function, must reference off the frame
@@ -709,7 +707,7 @@
 
   // Determine the sizes of each callee-save spill areas and record which frame
   // belongs to which callee-save spill areas.
-  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
+  unsigned GPRCSSize = 0, DPRCSSize = 0;
   int FramePtrSpillFI = 0;
 
   if (VARegSaveSize)
@@ -729,25 +727,15 @@
     case ARM::R5:
     case ARM::R6:
     case ARM::R7:
-    case ARM::LR:
-      if (Reg == FramePtr)
-        FramePtrSpillFI = FI;
-      AFI->addGPRCalleeSavedArea1Frame(FI);
-      GPRCS1Size += 4;
-      break;
     case ARM::R8:
     case ARM::R9:
     case ARM::R10:
     case ARM::R11:
+    case ARM::LR:
       if (Reg == FramePtr)
         FramePtrSpillFI = FI;
-      if (STI.isTargetDarwin()) {
-        AFI->addGPRCalleeSavedArea2Frame(FI);
-        GPRCS2Size += 4;
-      } else {
-        AFI->addGPRCalleeSavedArea1Frame(FI);
-        GPRCS1Size += 4;
-      }
+      AFI->addGPRCalleeSavedAreaFrame(FI);
+      GPRCSSize += 4;
       break;
     default:
       AFI->addDPRCalleeSavedAreaFrame(FI);
@@ -769,12 +757,10 @@
   }
 
   // Determine starting offsets of spill areas.
-  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
-  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
-  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
+  unsigned DPRCSOffset  = NumBytes - (GPRCSSize + DPRCSSize);
+  unsigned GPRCSOffset = DPRCSOffset + DPRCSSize;
   AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
-  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
-  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
+  AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset);
   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
 
   NumBytes = DPRCSOffset;
@@ -787,8 +773,7 @@
     MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
                              AFI->getFramePtrSpillOffset());
 
-  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
-  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
+  AFI->setGPRCalleeSavedAreaSize(GPRCSSize);
   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 
   // If we need a base pointer, set it up here. It's whatever the value
@@ -849,8 +834,7 @@
     }
 
     // Move SP to start of FP callee save spill area.
-    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
-                 AFI->getGPRCalleeSavedArea2Size() +
+    NumBytes -= (AFI->getGPRCalleeSavedAreaSize() +
                  AFI->getDPRCalleeSavedAreaSize());
 
     if (AFI->shouldRestoreSPFromFP()) {

Modified: llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll?rev=114340&r1=114339&r2=114340&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll Mon Sep 20 14:32:20 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed}
+; RUN: llc < %s -stats |& grep {36.*Number of machine instrs printed}
 ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization}
 ; This test really wants to check that the resultant "cond_true" block only 
 ; has a single store in it, and that cond_true55 only has code to materialize 

Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll?rev=114340&r1=114339&r2=114340&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll Mon Sep 20 14:32:20 2010
@@ -32,15 +32,14 @@
 
 define fastcc i32 @parse_percent_token() nounwind {
 entry:
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
+; CHECK: itt eq
+; CHECK: itt eq
+; CHECK: itt eq
+; CHECK: itt eq
+; CHECK: itt eq
 ; CHECK: moveq r0
 ; CHECK-NOT: LBB0_
-; CHECK: ldreq
-; CHECK: popeq
+; CHECK: ldmiaeq
   switch i32 undef, label %bb7 [
     i32 37, label %bb43
     i32 48, label %bb5



From daniel at zuster.org  Mon Sep 20 15:20:06 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 20 Sep 2010 13:20:06 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
 lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <AANLkTikph85dp7fSpPX6-izkP0DBGs2f6rFAfMdxdM44@mail.gmail.com>
References: <20100917013806.562CB2A6C12C@llvm.org>
	<AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
	<AANLkTikph85dp7fSpPX6-izkP0DBGs2f6rFAfMdxdM44@mail.gmail.com>
Message-ID: <AANLkTim=zA0S+SU4ri+SoaJ37J=fswsP2AeQMYUOmFRv@mail.gmail.com>

On Mon, Sep 20, 2010 at 11:42 AM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Mon, Sep 20, 2010 at 9:38 AM, Daniel Dunbar <daniel at zuster.org> wrote:
>> Hi Dan,
>>
>> This change doesn't seem right to me. It is introducing a host ==
>> target dependency of sorts. Somehow this information should be coming
>> from the Target definitions or information in the IR file, not from
>> the host's fenv() implementation.
>
> What are you talking about? ?This change is just to detect errors
> coming out of the host's math functions, and doesn't really have much
> to do with the target's implementation of sin().

Aren't the hosts math functions being used in this case to make
optimization decisions?

 - Daniel

>
> -Eli
>


From gohman at apple.com  Mon Sep 20 15:27:06 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 20 Sep 2010 13:27:06 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
	lib/Analysis/ConstantFolding.cpp
	test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
References: <20100917013806.562CB2A6C12C@llvm.org>
	<AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
Message-ID: <48FD485A-4282-4C5C-947F-1BACA4E638E8@apple.com>


On Sep 20, 2010, at 9:38 AM, Daniel Dunbar wrote:

> Hi Dan,
> 
> This change doesn't seem right to me. It is introducing a host ==
> target dependency of sorts. Somehow this information should be coming
> from the Target definitions or information in the IR file, not from
> the host's fenv() implementation.

There is a host == target dependence, but it's been there for many
years, at a quick thumb through SVN history. My recent change just
fixed a specific class of bugs. Other classes of bugs remain.

The real way to fix this is to do something like implement sin, cos,
etc. within APFloat.  GCC uses libmpfr to provide this functionality,
for reference.

Dan


From resistor at mac.com  Mon Sep 20 15:39:59 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 20 Sep 2010 20:39:59 -0000
Subject: [llvm-commits] [llvm] r114348 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
Message-ID: <20100920203959.670542A6C12C@llvm.org>

Author: resistor
Date: Mon Sep 20 15:39:59 2010
New Revision: 114348

URL: http://llvm.org/viewvc/llvm-project?rev=114348&view=rev
Log:
When TCO is turned on, it is possible to end up with aliasing FrameIndex's.  Therefore,
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114348&r1=114347&r2=114348&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Sep 20 15:39:59 2010
@@ -7030,8 +7030,19 @@
   if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
     return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
 
-  // If we know what the bases are, and they aren't identical, then we know they
-  // cannot alias.
+  // It is possible for different frame indices to alias each other, mostly
+  // when tail call optimization reuses return address slots for arguments.
+  // To catch this case, look up the actual index of frame indices to compute
+  // the real alias relationship.
+  if (isFrameIndex1 && isFrameIndex2) {
+    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
+    Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
+    Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
+    return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
+  }
+
+  // Otherwise, if we know what the bases are, and they aren't identical, then 
+  // we know they cannot alias.
   if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
     return false;
 

Modified: llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll?rev=114348&r1=114347&r2=114348&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Mon Sep 20 15:39:59 2010
@@ -19,8 +19,8 @@
 }
 
 ; CHECK: movq	___stack_chk_guard at GOTPCREL(%rip), %rax
-; CHECK: movb	(%rsp), %dl
-; CHECK-NEXT: movb	30(%rsp), %sil
-; CHECK: movb	%dl, (%rsp)
-; CHECK-NEXT: movb	%sil, 30(%rsp)
+; CHECK: movb	30(%rsp), %dl
+; CHECK: movb	(%rsp), %sil
+; CHECK: movb	%sil, (%rsp)
+; CHECK: movb	%dl, 30(%rsp)
 ; CHECK: callq	___stack_chk_fail



From daniel at zuster.org  Mon Sep 20 15:41:16 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 20 Sep 2010 13:41:16 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
 lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <48FD485A-4282-4C5C-947F-1BACA4E638E8@apple.com>
References: <20100917013806.562CB2A6C12C@llvm.org>
	<AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
	<48FD485A-4282-4C5C-947F-1BACA4E638E8@apple.com>
Message-ID: <AANLkTikjrF6kNwJL_MEE+i-cmue7ASyDn6Ti+M9am4Hg@mail.gmail.com>

On Mon, Sep 20, 2010 at 1:27 PM, Dan Gohman <gohman at apple.com> wrote:
>
> On Sep 20, 2010, at 9:38 AM, Daniel Dunbar wrote:
>
>> Hi Dan,
>>
>> This change doesn't seem right to me. It is introducing a host ==
>> target dependency of sorts. Somehow this information should be coming
>> from the Target definitions or information in the IR file, not from
>> the host's fenv() implementation.
>
> There is a host == target dependence, but it's been there for many
> years, at a quick thumb through SVN history. My recent change just
> fixed a specific class of bugs. Other classes of bugs remain.

I guess adding a new configure check, plus System abstraction, plus
actual change, seems like a lot of work to put towards an inherently
broken model. Do we at least have a bug somewhere tracking a proper
fix for this?

 - Daniel

> The real way to fix this is to do something like implement sin, cos,
> etc. within APFloat. ?GCC uses libmpfr to provide this functionality,
> for reference.
>
> Dan
>
>


From jasonwkim at google.com  Mon Sep 20 15:45:48 2010
From: jasonwkim at google.com (Jason Kim)
Date: Mon, 20 Sep 2010 13:45:48 -0700
Subject: [llvm-commits] Fwd:  Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <AANLkTimKAX5XaDxAdiKuDp12gUDmBbs+BtdY1fx97tk9@mail.gmail.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
	<AANLkTin7esVNJY9rN6Cy242k-HqxX1zi5da+esYBpoKj@mail.gmail.com>
	<AANLkTikP9SZwbuRFk9yaQj33j4Jr3iTDC4+EsHB13kXd@mail.gmail.com>
	<AANLkTimKAX5XaDxAdiKuDp12gUDmBbs+BtdY1fx97tk9@mail.gmail.com>
Message-ID: <AANLkTinw3YkO7VrW=g305kGspdgPqrGukv1X9oshpijf@mail.gmail.com>

Apologies once again. The whitespace issue in arm-mc-elf-s01.patch4
has been fixed.


---------- Forwarded message ----------
From: Jason Kim <jasonwkim at google.com>
Date: Mon, Sep 20, 2010 at 11:15 AM
Subject: Re: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
To: Rafael Espindola <espindola at google.com>


Hi Rafael,

Sorry about that. In a hurry, I manually patched the patch and had
forgotten that my editor mode strips out trailiing blank spaces
(required for NaCl :-)
Here's an updated patch.



On Mon, Sep 20, 2010 at 10:59 AM, Rafael Espindola <espindola at google.com> wrote:
> On 20 September 2010 01:37, Jason Kim <jasonwkim at google.com> wrote:
>> Double oops.
>> I somehow missed a compile breaking typo.
>> Apologies for the noise.
>> Tested against clean build dir.
>
> There something strange with the patch. I cannot apply it to 114212. I
> have attached the .rej file.
>
> Cheers,
> --
> Rafael ?vila de Esp?ndola
>
-------------- next part --------------
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Size: 16111 bytes
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From resistor at mac.com  Mon Sep 20 15:56:30 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 20 Sep 2010 20:56:30 -0000
Subject: [llvm-commits] [llvm] r114354 -
	/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
Message-ID: <20100920205630.14AA42A6C12C@llvm.org>

Author: resistor
Date: Mon Sep 20 15:56:29 2010
New Revision: 114354

URL: http://llvm.org/viewvc/llvm-project?rev=114354&view=rev
Log:
CombinerAA is now reordering these stores.

Modified:
    llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll

Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll?rev=114354&r1=114353&r2=114354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll Mon Sep 20 15:56:29 2010
@@ -64,6 +64,6 @@
  %0 = load i16* %retval                          ; <i16> [#uses=1]
  ret i16 %0
 ; CHECK: mov2:
-; CHECK:	mov.w	0(r1), 4(r1)
 ; CHECK:	mov.w	2(r1), 6(r1)
+; CHECK:	mov.w	0(r1), 4(r1)
 }



From anton at korobeynikov.info  Mon Sep 20 16:03:08 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Tue, 21 Sep 2010 01:03:08 +0400
Subject: [llvm-commits] [llvm] r114354 -
	/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
In-Reply-To: <20100920205630.14AA42A6C12C@llvm.org>
References: <20100920205630.14AA42A6C12C@llvm.org>
Message-ID: <AANLkTi=BQLd8gvs-iTJwC091=94qgA1=ZjBF-BFRANgG@mail.gmail.com>

Hi Owen,

> CombinerAA is now reordering these stores.
Interesting, why?

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From resistor at mac.com  Mon Sep 20 16:04:53 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 20 Sep 2010 14:04:53 -0700
Subject: [llvm-commits] [llvm] r114354 -
 /llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
In-Reply-To: <AANLkTi=BQLd8gvs-iTJwC091=94qgA1=ZjBF-BFRANgG@mail.gmail.com>
References: <20100920205630.14AA42A6C12C@llvm.org>
	<AANLkTi=BQLd8gvs-iTJwC091=94qgA1=ZjBF-BFRANgG@mail.gmail.com>
Message-ID: <0B34756F-C8DF-4D8B-B2A1-2D5E4E5AF9B9@mac.com>


On Sep 20, 2010, at 2:03 PM, Anton Korobeynikov wrote:

> Hi Owen,
> 
>> CombinerAA is now reordering these stores.
> Interesting, why?

Well, to be more precise, CombinerAA loosens the restrictions on the scheduler, allowing it to reorder them.  I have no idea why it picks that particular order for them.  As to why it changed, I just en-smartened CombinerAA to reason about FrameIndex offsets with greater precision.

--Owen

From gohman at apple.com  Mon Sep 20 16:10:06 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 20 Sep 2010 14:10:06 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
	lib/Analysis/ConstantFolding.cpp
	test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <AANLkTikjrF6kNwJL_MEE+i-cmue7ASyDn6Ti+M9am4Hg@mail.gmail.com>
References: <20100917013806.562CB2A6C12C@llvm.org>
	<AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
	<48FD485A-4282-4C5C-947F-1BACA4E638E8@apple.com>
	<AANLkTikjrF6kNwJL_MEE+i-cmue7ASyDn6Ti+M9am4Hg@mail.gmail.com>
Message-ID: <2215CF2E-CA62-4EA6-9B2F-1C9F923F1443@apple.com>


On Sep 20, 2010, at 1:41 PM, Daniel Dunbar wrote:

> On Mon, Sep 20, 2010 at 1:27 PM, Dan Gohman <gohman at apple.com> wrote:
>> 
>> On Sep 20, 2010, at 9:38 AM, Daniel Dunbar wrote:
>> 
>>> Hi Dan,
>>> 
>>> This change doesn't seem right to me. It is introducing a host ==
>>> target dependency of sorts. Somehow this information should be coming
>>> from the Target definitions or information in the IR file, not from
>>> the host's fenv() implementation.
>> 
>> There is a host == target dependence, but it's been there for many
>> years, at a quick thumb through SVN history. My recent change just
>> fixed a specific class of bugs. Other classes of bugs remain.
> 
> I guess adding a new configure check, plus System abstraction, plus
> actual change, seems like a lot of work to put towards an inherently
> broken model. Do we at least have a bug somewhere tracking a proper
> fix for this?

It really wasn't that much work, especially compared to the work
in replacing the broken model with a working one.

I didn't find a bug for this issue, so I filed PR8193.

Dan


From daniel at zuster.org  Mon Sep 20 16:13:02 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 20 Sep 2010 21:13:02 -0000
Subject: [llvm-commits] [zorg] r114357 -
	/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
Message-ID: <20100920211302.D4E6C2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Sep 20 16:13:02 2010
New Revision: 114357

URL: http://llvm.org/viewvc/llvm-project?rev=114357&view=rev
Log:
buildbot/ClangBuilder: Add parameter to enable checking out compiler-rt.

Modified:
    zorg/trunk/zorg/buildbot/builders/ClangBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=114357&r1=114356&r2=114357&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Mon Sep 20 16:13:02 2010
@@ -21,7 +21,8 @@
                          make='make', jobs="%(jobs)s",
                          stage1_config='Debug+Asserts',
                          stage2_config='Release+Asserts',
-                         extra_configure_args=[], use_pty_in_tests=False):
+                         extra_configure_args=[], use_pty_in_tests=False,
+                         checkout_compiler_rt=False):
     # Don't use in-dir builds with a two stage build process.
     inDir = not outOfDir and not useTwoStage
     if inDir:
@@ -57,13 +58,21 @@
 
     # Checkout sources.
     f.addStep(SVN(name='svn-llvm',
-                  mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/',
+                  mode='update',
+                  baseURL='http://llvm.org/svn/llvm-project/llvm/',
                   defaultBranch='trunk',
                   workdir=llvm_srcdir))
     f.addStep(SVN(name='svn-clang',
-                  mode='update', baseURL='http://llvm.org/svn/llvm-project/cfe/',
+                  mode='update',
+                  baseURL='http://llvm.org/svn/llvm-project/cfe/',
                   defaultBranch='trunk',
                   workdir='%s/tools/clang' % llvm_srcdir))
+    if checkout_compiler_rt:
+        f.addStep(SVN(name='svn-compiler-rt',
+                      mode='update',
+                      baseURL='http://llvm.org/svn/llvm-project/compiler-rt/',
+                      defaultBranch='trunk',
+                      workdir='%s/project/compiler-rt' % llvm_srcdir))
 
     # Clean up llvm (stage 1); unless in-dir.
     if clean and llvm_srcdir != llvm_1_objdir:



From gohman at apple.com  Mon Sep 20 16:16:04 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 20 Sep 2010 14:16:04 -0700
Subject: [llvm-commits] [llvm] r114241 -
	/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <AANLkTimNbX_HmuVSV9HsVmoW74VTyDoyk8SSf=fqDhtc@mail.gmail.com>
References: <20100918000438.063012A6C12C@llvm.org>
	<69EFC494-A4B4-4234-8DDD-C46812EF2CD2@apple.com>
	<2FC393C3-C7B1-4B83-964E-0BA2166DC37B@apple.com>
	<AANLkTimNbX_HmuVSV9HsVmoW74VTyDoyk8SSf=fqDhtc@mail.gmail.com>
Message-ID: <7E5A45BF-6FBE-412B-8448-E46FA53B51AF@apple.com>


On Sep 20, 2010, at 8:46 AM, Rafael Espindola wrote:

>> LLVM's reliance on the host libm goes way back. Alternatives to using the
>> host libm for constant folding exist, but LLVM has not yet pursued them.
> 
> Do we have a bug for this? Should we?

I just filed PR8193.

Dan


From gohman at apple.com  Mon Sep 20 17:32:25 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 20 Sep 2010 22:32:25 -0000
Subject: [llvm-commits] [llvm] r114368 -
	/llvm/trunk/include/llvm/System/FEnv.h
Message-ID: <20100920223225.5F7762A6C12C@llvm.org>

Author: djg
Date: Mon Sep 20 17:32:25 2010
New Revision: 114368

URL: http://llvm.org/viewvc/llvm-project?rev=114368&view=rev
Log:
Relax this check to silently swallow FE_INEXACT, following directions
from rdar://8452472. This unbreaks gcc.dg/builtins-17.c.

Modified:
    llvm/trunk/include/llvm/System/FEnv.h

Modified: llvm/trunk/include/llvm/System/FEnv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/FEnv.h?rev=114368&r1=114367&r2=114368&view=diff
==============================================================================
--- llvm/trunk/include/llvm/System/FEnv.h (original)
+++ llvm/trunk/include/llvm/System/FEnv.h Mon Sep 20 17:32:25 2010
@@ -38,7 +38,7 @@
   if (errno_val == ERANGE || errno_val == EDOM)
     return true;
 #ifdef HAVE_FENV_H
-  if (fetestexcept(FE_ALL_EXCEPT))
+  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
     return true;
 #endif
   return false;



From isanbard at gmail.com  Mon Sep 20 17:36:58 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 20 Sep 2010 22:36:58 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r114369 -
	/llvm-gcc-4.2/trunk/gcc/doc/extend.texi
Message-ID: <20100920223658.3EBC12A6C12C@llvm.org>

Author: void
Date: Mon Sep 20 17:36:58 2010
New Revision: 114369

URL: http://llvm.org/viewvc/llvm-project?rev=114369&view=rev
Log:
Pretty sure this should be __builtin_ia32_palignr128 for SSSE3.

Modified:
    llvm-gcc-4.2/trunk/gcc/doc/extend.texi

Modified: llvm-gcc-4.2/trunk/gcc/doc/extend.texi
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/doc/extend.texi?rev=114369&r1=114368&r2=114369&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/doc/extend.texi (original)
+++ llvm-gcc-4.2/trunk/gcc/doc/extend.texi Mon Sep 20 17:36:58 2010
@@ -7693,7 +7693,7 @@
 v16qi __builtin_ia32_psignb128 (v16qi, v16qi)
 v4si __builtin_ia32_psignd128 (v4si, v4si)
 v8hi __builtin_ia32_psignw128 (v8hi, v8hi)
-v2di __builtin_ia32_palignr (v2di, v2di, int)
+v2di __builtin_ia32_palignr128 (v2di, v2di, int)
 v16qi __builtin_ia32_pabsb128 (v16qi)
 v4si __builtin_ia32_pabsd128 (v4si)
 v8hi __builtin_ia32_pabsw128 (v8hi)



From daniel at zuster.org  Mon Sep 20 17:40:09 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 20 Sep 2010 15:40:09 -0700
Subject: [llvm-commits] [llvm] r114148 - in /llvm/trunk:
 lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/fold-calls.ll
In-Reply-To: <2215CF2E-CA62-4EA6-9B2F-1C9F923F1443@apple.com>
References: <20100917013806.562CB2A6C12C@llvm.org>
	<AANLkTiko5AgXNnqdEeOMUKRD9wVVOpSRXzuVDESpGXxE@mail.gmail.com>
	<48FD485A-4282-4C5C-947F-1BACA4E638E8@apple.com>
	<AANLkTikjrF6kNwJL_MEE+i-cmue7ASyDn6Ti+M9am4Hg@mail.gmail.com>
	<2215CF2E-CA62-4EA6-9B2F-1C9F923F1443@apple.com>
Message-ID: <AANLkTinErOJ_+17wEXJRQKuGWULHKnaRwhHrHN15dS0X@mail.gmail.com>

On Mon, Sep 20, 2010 at 2:10 PM, Dan Gohman <gohman at apple.com> wrote:
>
> On Sep 20, 2010, at 1:41 PM, Daniel Dunbar wrote:
>
>> On Mon, Sep 20, 2010 at 1:27 PM, Dan Gohman <gohman at apple.com> wrote:
>>>
>>> On Sep 20, 2010, at 9:38 AM, Daniel Dunbar wrote:
>>>
>>>> Hi Dan,
>>>>
>>>> This change doesn't seem right to me. It is introducing a host ==
>>>> target dependency of sorts. Somehow this information should be coming
>>>> from the Target definitions or information in the IR file, not from
>>>> the host's fenv() implementation.
>>>
>>> There is a host == target dependence, but it's been there for many
>>> years, at a quick thumb through SVN history. My recent change just
>>> fixed a specific class of bugs. Other classes of bugs remain.
>>
>> I guess adding a new configure check, plus System abstraction, plus
>> actual change, seems like a lot of work to put towards an inherently
>> broken model. Do we at least have a bug somewhere tracking a proper
>> fix for this?
>
> It really wasn't that much work, especially compared to the work
> in replacing the broken model with a working one.

Fair enough, that makes sense.

> I didn't find a bug for this issue, so I filed PR8193.

Great, thanks! I like knowing all the subtle ways the compiler can
vary per host, and this is one I was totally and blissfully unaware of
until now! :)

 - Daniel

>
> Dan
>
>

From evan.cheng at apple.com  Mon Sep 20 17:52:00 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 20 Sep 2010 22:52:00 -0000
Subject: [llvm-commits] [llvm] r114372 - in /llvm/trunk:
 lib/CodeGen/MachineSink.cpp test/CodeGen/Mips/2010-07-20-Select.ll
 test/CodeGen/X86/compare-inf.ll test/CodeGen/X86/sink-hoist.ll
 test/CodeGen/XCore/ashr.ll
Message-ID: <20100920225200.542912A6C12C@llvm.org>

Author: evancheng
Date: Mon Sep 20 17:52:00 2010
New Revision: 114372

URL: http://llvm.org/viewvc/llvm-project?rev=114372&view=rev
Log:
Enable machine sinking critical edge splitting. e.g.

define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886

Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp
    llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
    llvm/trunk/test/CodeGen/X86/compare-inf.ll
    llvm/trunk/test/CodeGen/X86/sink-hoist.ll
    llvm/trunk/test/CodeGen/XCore/ashr.ll

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=114372&r1=114371&r2=114372&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Mon Sep 20 17:52:00 2010
@@ -35,10 +35,7 @@
 static cl::opt<bool> 
 SplitEdges("machine-sink-split",
            cl::desc("Split critical edges during machine sinking"),
-           cl::init(false), cl::Hidden);
-static cl::opt<unsigned>
-SplitLimit("split-limit",
-           cl::init(~0u), cl::Hidden);
+           cl::init(true), cl::Hidden);
 
 STATISTIC(NumSunk,      "Number of machine instructions sunk");
 STATISTIC(NumSplit,     "Number of critical edges split");
@@ -311,7 +308,7 @@
     return 0;
 
   // Avoid breaking back edge. From == To means backedge for single BB loop.
-  if (!SplitEdges || NumSplit == SplitLimit || FromBB == ToBB)
+  if (!SplitEdges || FromBB == ToBB)
     return 0;
 
   // Check for backedges of more "complex" loops.
@@ -561,8 +558,6 @@
     // BreakPHIEdge is true if all the uses are in the successor MBB being
     // sunken into and they are all PHI nodes. In this case, machine-sink must
     // break the critical edge first.
-    if (NumSplit == SplitLimit)
-      return false;
     MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock,
                                                    SuccToSinkTo, BreakPHIEdge);
     if (!NewSucc) {

Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll?rev=114372&r1=114371&r2=114372&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll Mon Sep 20 17:52:00 2010
@@ -9,12 +9,12 @@
   volatile store i32 0, i32* %c, align 4
   %0 = volatile load i32* %a, align 4             ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 3
+; CHECK: addiu $3, $zero, 0
   %iftmp.0.0 = select i1 %1, i32 3, i32 0         ; <i32> [#uses=1]
   %2 = volatile load i32* %c, align 4             ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0                          ; <i1> [#uses=1]
-; CHECK: addu $4, $zero, $3
-; CHECK: addu $2, $5, $4
+; CHECK: addiu $3, $zero, 3
+; CHECK: addu $2, $5, $3
   %iftmp.2.0 = select i1 %3, i32 0, i32 5         ; <i32> [#uses=1]
   %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0         ; <i32> [#uses=1]
   ret i32 %4

Modified: llvm/trunk/test/CodeGen/X86/compare-inf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/compare-inf.ll?rev=114372&r1=114371&r2=114372&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/compare-inf.ll (original)
+++ llvm/trunk/test/CodeGen/X86/compare-inf.ll Mon Sep 20 17:52:00 2010
@@ -5,7 +5,7 @@
 
 ; CHECK: oeq_inff:
 ; CHECK: ucomiss
-; CHECK: jae
+; CHECK: jb
 define float @oeq_inff(float %x, float %y) nounwind readonly {
   %t0 = fcmp oeq float %x, 0x7FF0000000000000
   %t1 = select i1 %t0, float 1.0, float %y
@@ -14,7 +14,7 @@
 
 ; CHECK: oeq_inf:
 ; CHECK: ucomisd
-; CHECK: jae
+; CHECK: jb
 define double @oeq_inf(double %x, double %y) nounwind readonly {
   %t0 = fcmp oeq double %x, 0x7FF0000000000000
   %t1 = select i1 %t0, double 1.0, double %y
@@ -23,7 +23,7 @@
 
 ; CHECK: une_inff:
 ; CHECK: ucomiss
-; CHECK: jb
+; CHECK: jae
 define float @une_inff(float %x, float %y) nounwind readonly {
   %t0 = fcmp une float %x, 0x7FF0000000000000
   %t1 = select i1 %t0, float 1.0, float %y
@@ -32,7 +32,7 @@
 
 ; CHECK: une_inf:
 ; CHECK: ucomisd
-; CHECK: jb
+; CHECK: jae
 define double @une_inf(double %x, double %y) nounwind readonly {
   %t0 = fcmp une double %x, 0x7FF0000000000000
   %t1 = select i1 %t0, double 1.0, double %y
@@ -41,7 +41,7 @@
 
 ; CHECK: oeq_neg_inff:
 ; CHECK: ucomiss
-; CHECK: jae
+; CHECK: jb
 define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
   %t0 = fcmp oeq float %x, 0xFFF0000000000000
   %t1 = select i1 %t0, float 1.0, float %y
@@ -50,7 +50,7 @@
 
 ; CHECK: oeq_neg_inf:
 ; CHECK: ucomisd
-; CHECK: jae
+; CHECK: jb
 define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
   %t0 = fcmp oeq double %x, 0xFFF0000000000000
   %t1 = select i1 %t0, double 1.0, double %y
@@ -59,7 +59,7 @@
 
 ; CHECK: une_neg_inff:
 ; CHECK: ucomiss
-; CHECK: jb
+; CHECK: jae
 define float @une_neg_inff(float %x, float %y) nounwind readonly {
   %t0 = fcmp une float %x, 0xFFF0000000000000
   %t1 = select i1 %t0, float 1.0, float %y
@@ -68,7 +68,7 @@
 
 ; CHECK: une_neg_inf:
 ; CHECK: ucomisd
-; CHECK: jb
+; CHECK: jae
 define double @une_neg_inf(double %x, double %y) nounwind readonly {
   %t0 = fcmp une double %x, 0xFFF0000000000000
   %t1 = select i1 %t0, double 1.0, double %y

Modified: llvm/trunk/test/CodeGen/X86/sink-hoist.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sink-hoist.ll?rev=114372&r1=114371&r2=114372&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sink-hoist.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sink-hoist.ll Mon Sep 20 17:52:00 2010
@@ -6,10 +6,11 @@
 ; that it's conditionally evaluated.
 
 ; CHECK: foo:
-; CHECK:      divsd
 ; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: jne
+; CHECK-NEXT: je
 ; CHECK-NEXT: divsd
+; CHECK-NEXT: ret
+; CHECK:      divsd
 
 define double @foo(double %x, double %y, i1 %c) nounwind {
   %a = fdiv double %x, 3.2
@@ -18,6 +19,24 @@
   ret double %z
 }
 
+; Make sure the critical edge is broken so the divsd is sunken below
+; the conditional branch.
+; rdar://8454886
+
+; CHECK: split:
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: je
+; CHECK-NEXT: divsd
+; CHECK-NEXT: ret
+; CHECK:      movaps
+; CHECK-NEXT: ret
+define double @split(double %x, double %y, i1 %c) nounwind {
+  %a = fdiv double %x, 3.2
+  %z = select i1 %c, double %a, double %y
+  ret double %z
+}
+
+
 ; Hoist floating-point constant-pool loads out of loops.
 
 ; CHECK: bar:
@@ -68,9 +87,9 @@
 ; Codegen should hoist and CSE these constants.
 
 ; CHECK: vv:
-; CHECK: LCPI2_0(%rip), %xmm0
-; CHECK: LCPI2_1(%rip), %xmm1
-; CHECK: LCPI2_2(%rip), %xmm2
+; CHECK: LCPI3_0(%rip), %xmm0
+; CHECK: LCPI3_1(%rip), %xmm1
+; CHECK: LCPI3_2(%rip), %xmm2
 ; CHECK: align
 ; CHECK-NOT: LCPI
 ; CHECK: ret

Modified: llvm/trunk/test/CodeGen/XCore/ashr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/ashr.ll?rev=114372&r1=114371&r2=114372&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/ashr.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/ashr.ll Mon Sep 20 17:52:00 2010
@@ -50,9 +50,9 @@
 	ret i32 %2
 }
 ; CHECK: f3:
-; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bf r0
 ; CHECK-NEXT: ldc r0, 10
-; CHECK-NEXT: bt r1
 ; CHECK: ldc r0, 17
 
 define i32 @f4(i32 %a) {
@@ -61,9 +61,9 @@
 	ret i32 %2
 }
 ; CHECK: f4:
-; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bf r0
 ; CHECK-NEXT: ldc r0, 17
-; CHECK-NEXT: bt r1
 ; CHECK: ldc r0, 10
 
 define i32 @f5(i32 %a) {



From tonic at nondot.org  Mon Sep 20 18:05:17 2010
From: tonic at nondot.org (Tanya Lattner)
Date: Mon, 20 Sep 2010 23:05:17 -0000
Subject: [llvm-commits] [www] r114373 - /www/trunk/devmtg/2010-11/index.html
Message-ID: <20100920230517.2ADB32A6C12C@llvm.org>

Author: tbrethou
Date: Mon Sep 20 18:05:16 2010
New Revision: 114373

URL: http://llvm.org/viewvc/llvm-project?rev=114373&view=rev
Log:
Add sponsors! Thanks Apple, Qualcomm, and Google!

Modified:
    www/trunk/devmtg/2010-11/index.html

Modified: www/trunk/devmtg/2010-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=114373&r1=114372&r2=114373&view=diff
==============================================================================
--- www/trunk/devmtg/2010-11/index.html (original)
+++ www/trunk/devmtg/2010-11/index.html Mon Sep 20 18:05:16 2010
@@ -20,10 +20,8 @@
 </ul>
 </td></tr></table>
 
-<!--<p align="center"><h2><b>SPONSORED BY: <a href="http://apple.com">Apple</a>, <a href="htt
-p://google.com">Google</a>, <a href="http://www.adobe.com/">Adobe</a>, <a href="http://ww
-w.qualcomm.com/">Qualcomm Incorporated</a></b></h2></p>
--->
+<p align="center"><h2><b>SPONSORED BY: <a href="http://apple.com">Apple</a>, <a href="http://www.qualcomm.com/">Qualcomm Incorporated</a>, <a href="http://google.com">Google</a></b></h2></p>
+
 <p>The meeting serves as a forum for <a href="http://llvm.org">LLVM</a>,
 <a href="http://clang.llvm.org">Clang</a>, <a href="http://lldb.llvm.org">LLDB</a> and 
 other LLVM project developers and users to get acquainted, learn how LLVM is used, and 



From fjahanian at apple.com  Mon Sep 20 18:59:06 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Mon, 20 Sep 2010 23:59:06 -0000
Subject: [llvm-commits] [test-suite] r114378 - in
 /test-suite/trunk/SingleSource/UnitTests: conditional-gnu-ext.c
 conditional-gnu-ext.cpp
Message-ID: <20100920235906.3BF062A6C12C@llvm.org>

Author: fjahanian
Date: Mon Sep 20 18:59:06 2010
New Revision: 114378

URL: http://llvm.org/viewvc/llvm-project?rev=114378&view=rev
Log:
Test cases for testing clang's support for gnu extension's
conditional expressions with missing LHS. This is for
radar 8453812.

Added:
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.c
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp

Added: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.c?rev=114378&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.c (added)
+++ test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.c Mon Sep 20 18:59:06 2010
@@ -0,0 +1,22 @@
+// rdar://8453812
+extern void abort();
+
+_Complex int getComplex(_Complex int val) {
+  static int count;
+  if (count++)
+    abort();
+  return val;
+}
+
+_Complex int doo() {
+    _Complex int cond;
+    _Complex int rhs;
+
+    return getComplex(1+2i) ? : rhs;
+}
+
+int main() {
+  doo();
+  return 0;
+}
+

Added: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp?rev=114378&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp (added)
+++ test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp Mon Sep 20 18:59:06 2010
@@ -0,0 +1,22 @@
+// rdar://8453812
+extern "C" void abort();
+
+_Complex int getComplex(_Complex int val) {
+  static int count;
+  if (count++)
+    abort();
+  return val;
+}
+
+_Complex int doo() {
+    _Complex int cond;
+    _Complex int rhs;
+
+    return getComplex(1+2i) ? : rhs;
+}
+
+int main() {
+  doo();
+  return 0;
+}
+



From rafael.espindola at gmail.com  Mon Sep 20 19:24:38 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 21 Sep 2010 00:24:38 -0000
Subject: [llvm-commits] [llvm] r114382 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp lib/MC/MCELFStreamer.cpp
 lib/MC/MCParser/AsmParser.cpp test/MC/ELF/common.s
Message-ID: <20100921002438.3E0622A6C12C@llvm.org>

Author: rafael
Date: Mon Sep 20 19:24:38 2010
New Revision: 114382

URL: http://llvm.org/viewvc/llvm-project?rev=114382&view=rev
Log:
Implement support for .local and its "interesting" interactions with .comm.

Added:
    llvm/trunk/test/MC/ELF/common.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/MCELFStreamer.cpp
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114382&r1=114381&r2=114382&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Sep 20 19:24:38 2010
@@ -386,6 +386,8 @@
   if (Data.isCommon() && Data.isExternal())
     Value = Data.getCommonAlignment();
 
+  assert(!(Data.isCommon() && !Data.isExternal()));
+
   if (!Data.isCommon() && !(Data.getFlags() & ELF_STB_Weak))
     if (MCFragment *FF = Data.getFragment())
       Value = Layout.getSymbolAddress(&Data) -
@@ -502,7 +504,10 @@
     if (Base) {
       if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
-        Value += Layout.getSymbolAddress(&SD);
+
+        MCSectionData *FSD = F->getParent();
+        // Offset of the symbol in the section
+        Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
       } else
         Index = getSymbolIndexInSymbolTable(Asm, Symbol);
       if (Base != &SD)
@@ -672,7 +677,10 @@
     MSD.SymbolData = it;
     MSD.StringIndex = Entry;
 
-    if (Symbol.isUndefined()) {
+    if (it->isCommon()) {
+      MSD.SectionIndex = ELF::SHN_COMMON;
+      ExternalSymbolData.push_back(MSD);
+    } else if (Symbol.isUndefined()) {
       MSD.SectionIndex = ELF::SHN_UNDEF;
       // XXX: for some reason we dont Emit* this
       it->setFlags(it->getFlags() | ELF_STB_Global);
@@ -680,9 +688,6 @@
     } else if (Symbol.isAbsolute()) {
       MSD.SectionIndex = ELF::SHN_ABS;
       ExternalSymbolData.push_back(MSD);
-    } else if (it->isCommon()) {
-      MSD.SectionIndex = ELF::SHN_COMMON;
-      ExternalSymbolData.push_back(MSD);
     } else {
       MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
       assert(MSD.SectionIndex && "Invalid section index!");

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=114382&r1=114381&r2=114382&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Sep 20 19:24:38 2010
@@ -13,6 +13,7 @@
 
 #include "llvm/MC/MCStreamer.h"
 
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCCodeEmitter.h"
@@ -109,6 +110,8 @@
   virtual void EmitInstruction(const MCInst &Inst);
   virtual void Finish();
 
+private:
+  SmallPtrSet<MCSymbol *, 16> BindingExplicitlySet;
   /// @}
   void SetSection(StringRef Section, unsigned Type, unsigned Flags,
                   SectionKind Kind) {
@@ -187,6 +190,13 @@
   SD.setFlags(OtherFlags | (Binding << ELF_STB_Shift));
 }
 
+static unsigned GetBinding(const MCSymbolData &SD) {
+  uint32_t Binding = (SD.getFlags() & (0xf << ELF_STB_Shift)) >> ELF_STB_Shift;
+  assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL ||
+         Binding == ELF::STB_WEAK);
+  return Binding;
+}
+
 static void SetType(MCSymbolData &SD, unsigned Type) {
   assert(Type == ELF::STT_NOTYPE || Type == ELF::STT_OBJECT ||
          Type == ELF::STT_FUNC || Type == ELF::STT_SECTION ||
@@ -246,15 +256,19 @@
   case MCSA_Global:
     SetBinding(SD, ELF::STB_GLOBAL);
     SD.setExternal(true);
+    BindingExplicitlySet.insert(Symbol);
     break;
 
   case MCSA_WeakReference:
   case MCSA_Weak:
     SetBinding(SD, ELF::STB_WEAK);
+    BindingExplicitlySet.insert(Symbol);
     break;
 
   case MCSA_Local:
     SetBinding(SD, ELF::STB_LOCAL);
+    SD.setExternal(false);
+    BindingExplicitlySet.insert(Symbol);
     break;
 
   case MCSA_ELF_TypeFunction:
@@ -295,7 +309,12 @@
                                        unsigned ByteAlignment) {
   MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
 
-  if ((SD.getFlags() & (0xf << ELF_STB_Shift)) == ELF_STB_Local) {
+  if (!BindingExplicitlySet.count(Symbol)) {
+    SetBinding(SD, ELF::STB_GLOBAL);
+    SD.setExternal(true);
+  }
+
+  if (GetBinding(SD) == ELF_STB_Local) {
     const MCSection *Section = getAssembler().getContext().getELFSection(".bss",
                                                                     MCSectionELF::SHT_NOBITS,
                                                                     MCSectionELF::SHF_WRITE |
@@ -306,13 +325,11 @@
     MCFragment *F = new MCFillFragment(0, 0, Size, &SectData);
     SD.setFragment(F);
     Symbol->setSection(*Section);
-    SD.setSize(MCConstantExpr::Create(Size, getContext()));
+  } else {
+    SD.setCommon(Size, ByteAlignment);
   }
 
-  SetBinding(SD, ELF::STB_GLOBAL);
-  SD.setExternal(true);
-
-  SD.setCommon(Size, ByteAlignment);
+  SD.setSize(MCConstantExpr::Create(Size, getContext()));
 }
 
 void MCELFStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114382&r1=114381&r2=114382&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Sep 20 19:24:38 2010
@@ -961,6 +961,9 @@
 
     if (IDVal == ".globl" || IDVal == ".global")
       return ParseDirectiveSymbolAttribute(MCSA_Global);
+    // ELF only? Should it be here?
+    if (IDVal == ".local")
+      return ParseDirectiveSymbolAttribute(MCSA_Local);
     if (IDVal == ".hidden")
       return ParseDirectiveSymbolAttribute(MCSA_Hidden);
     if (IDVal == ".indirect_symbol")

Added: llvm/trunk/test/MC/ELF/common.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/common.s?rev=114382&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/common.s (added)
+++ llvm/trunk/test/MC/ELF/common.s Mon Sep 20 19:24:38 2010
@@ -0,0 +1,63 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck %s
+
+
+	.text
+
+// Test that this produces a regular local symbol.
+	.type	common1, at object
+	.local	common1
+	.comm	common1,1,1
+
+// CHECK: ('st_name', 1) # 'common1'
+// CHECK-NEXT: ('st_bind', 0)
+// CHECK-NEXT: ('st_type', 1)
+// CHECK-NEXT: ('st_other', 0)
+// CHECK-NEXT: ('st_shndx',
+// CHECK-NEXT: ('st_value', 0)
+// CHECK-NEXT: ('st_size', 1)
+
+
+// Same as common1, but with directives in a different order.
+	.local	common2
+	.type	common2, at object
+	.comm	common2,1,1
+
+// CHECK: ('st_name', 9) # 'common2'
+// CHECK-NEXT: ('st_bind', 0)
+// CHECK-NEXT: ('st_type', 1)
+// CHECK-NEXT: ('st_other', 0)
+// CHECK-NEXT: ('st_shndx',
+// CHECK-NEXT: ('st_value', 1)
+// CHECK-NEXT: ('st_size', 1)
+
+// Test that without an explicit .local we produce a global.
+	.type	common3, at object
+	.comm	common3,4,4
+
+// CHECK: ('st_name', 17) # 'common3'
+// CHECK-NEXT: ('st_bind', 1)
+// CHECK-NEXT: ('st_type', 1)
+// CHECK-NEXT: ('st_other', 0)
+// CHECK-NEXT: ('st_shndx', 65522)
+// CHECK-NEXT: ('st_value', 4)
+// CHECK-NEXT: ('st_size', 4)
+
+
+// Test that without an explicit .local we produce a global, even if the first
+// occurrence is not in a directive.
+	.globl	foo
+	.type	foo, at function
+foo:
+	movsbl	common4+3(%rip), %eax
+
+
+	.type	common4, at object
+	.comm	common4,40,16
+
+// CHECK: ('st_name', 29) # 'common4'
+// CHECK-NEXT: ('st_bind', 1)
+// CHECK-NEXT: ('st_type', 1)
+// CHECK-NEXT: ('st_other', 0)
+// CHECK-NEXT: ('st_shndx', 65522)
+// CHECK-NEXT: ('st_value', 16)
+// CHECK-NEXT: ('st_size', 40)



From rafael.espindola at gmail.com  Mon Sep 20 19:40:19 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 21 Sep 2010 00:40:19 -0000
Subject: [llvm-commits] [llvm] r114383 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20100921004019.C65572A6C12C@llvm.org>

Author: rafael
Date: Mon Sep 20 19:40:19 2010
New Revision: 114383

URL: http://llvm.org/viewvc/llvm-project?rev=114383&view=rev
Log:
Revert unrelated change that was accidentally included in the previous commit.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114383&r1=114382&r2=114383&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Sep 20 19:40:19 2010
@@ -504,10 +504,7 @@
     if (Base) {
       if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
-
-        MCSectionData *FSD = F->getParent();
-        // Offset of the symbol in the section
-        Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
+        Value += Layout.getSymbolAddress(&SD);
       } else
         Index = getSymbolIndexInSymbolTable(Asm, Symbol);
       if (Base != &SD)



From sabre at nondot.org  Mon Sep 20 22:37:00 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 03:37:00 -0000
Subject: [llvm-commits] [llvm] r114386 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/movgs.ll
Message-ID: <20100921033700.D32C62A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 22:37:00 2010
New Revision: 114386

URL: http://llvm.org/viewvc/llvm-project?rev=114386&view=rev
Log:
fix rdar://8453210, a crash handling a call through a GS relative load.
For now, just disable folding the load into the call.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/movgs.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114386&r1=114385&r2=114386&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Sep 20 22:37:00 2010
@@ -403,6 +403,12 @@
       LD->getExtensionType() != ISD::NON_EXTLOAD)
     return false;
 
+  // FIXME: Calls can't fold loads through segment registers yet.
+  if (const Value *Src = LD->getSrcValue())
+    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+      if (PT->getAddressSpace() >= 256)
+        return false;
+  
   // Now let's find the callseq_start.
   while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
     if (!Chain.hasOneUse())
@@ -563,7 +569,7 @@
 
   SDValue Address = N.getOperand(1);
   if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
-      !MatchSegmentBaseAddress (Address, AM))
+      !MatchSegmentBaseAddress(Address, AM))
     return false;
 
   return true;

Modified: llvm/trunk/test/CodeGen/X86/movgs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movgs.ll?rev=114386&r1=114385&r2=114386&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movgs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movgs.ll Mon Sep 20 22:37:00 2010
@@ -1,8 +1,35 @@
-; RUN: llc < %s -march=x86 | grep gs
+; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=X64
 
-define i32 @foo() nounwind readonly {
+define i32 @test1() nounwind readonly {
 entry:
 	%tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31)		; <i32*> [#uses=1]
 	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
+; X32: test1:
+; X32: 	movl	%gs:196, %eax
+; X32: 	movl	(%eax), %eax
+; X32: 	ret
+
+; X64: test1:
+; X64: 	movq	%gs:320, %rax
+; X64: 	movl	(%rax), %eax
+; X64: 	ret
+
+define i64 @test2(void (i8*)* addrspace(256)* %tmp8) nounwind {
+entry:
+  %tmp9 = load void (i8*)* addrspace(256)* %tmp8, align 8
+  tail call void %tmp9(i8* undef) nounwind optsize
+  ret i64 0
+}
+
+; rdar://8453210
+; X32: test2:
+; X32: movl	%gs:(%eax), %eax
+; X32: movl	%eax, (%esp)
+; X32: call	*%eax
+
+; X64: test2:
+; X64: movq	%gs:(%rdi), %rax
+; X64: callq	*%rax



From sabre at nondot.org  Mon Sep 20 23:03:39 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:03:39 -0000
Subject: [llvm-commits] [llvm] r114387 - /llvm/trunk/docs/CodeGenerator.html
Message-ID: <20100921040339.432592A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:03:39 2010
New Revision: 114387

URL: http://llvm.org/viewvc/llvm-project?rev=114387&view=rev
Log:
random cruft in my tree.

Modified:
    llvm/trunk/docs/CodeGenerator.html

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=114387&r1=114386&r2=114387&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Mon Sep 20 23:03:39 2010
@@ -1862,16 +1862,33 @@
 </div>
 
 
-<!-- ======================================================================= -->
+<!-- *********************************************************************** -->
 <div class="doc_section">
   <a name="nativeassembler">Implementing a Native Assembler</a>
 </div>
+<!-- *********************************************************************** -->
 
 <div class="doc_text">
 
-<p>TODO</p>
+<p>Though you're probably reading this because you want to write or maintain a
+compiler backend, LLVM also fully supports building a native assemblers too.
+We've tried hard to automate the generation of the assembler from the .td files
+(in particular the instruction syntax and encodings), which means that a large
+part of the manual and repetitive data entry can be factored and shared with the
+compiler.</p>
+
+
+
+</div>
+
 
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="proepicode">Prolog/Epilog Code Insertion</a>
 </div>
+<div class="doc_text"><p>To Be Written</p></div>
+
+
 
 
 <!-- *********************************************************************** -->



From daniel at zuster.org  Mon Sep 20 23:17:50 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 21 Sep 2010 04:17:50 -0000
Subject: [llvm-commits] [test-suite] r114388 -
 /test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.reference_output
Message-ID: <20100921041750.538F62A6C12C@llvm.org>

Author: ddunbar
Date: Mon Sep 20 23:17:50 2010
New Revision: 114388

URL: http://llvm.org/viewvc/llvm-project?rev=114388&view=rev
Log:
Add a reference output

Added:
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.reference_output

Added: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.reference_output?rev=114388&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.reference_output (added)
+++ test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.reference_output Mon Sep 20 23:17:50 2010
@@ -0,0 +1 @@
+exit 0



From sabre at nondot.org  Mon Sep 20 23:23:40 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:23:40 -0000
Subject: [llvm-commits] [llvm] r114389 - in /llvm/trunk:
 include/llvm/CodeGen/MachineMemOperand.h lib/CodeGen/MachineInstr.cpp
Message-ID: <20100921042340.2A6C52A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:23:39 2010
New Revision: 114389

URL: http://llvm.org/viewvc/llvm-project?rev=114389&view=rev
Log:
refactor the Value*/offset pair from MachineMemOperand out to a new
MachinePointerInfo struct, no functionality change.

This also adds an assert to MachineMemOperand::MachineMemOperand
that verifies that the Value* is either null or is an IR pointer type.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114389&r1=114388&r2=114389&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Mon Sep 20 23:23:39 2010
@@ -24,6 +24,17 @@
 class FoldingSetNodeID;
 class raw_ostream;
 
+/// MachinePointerInfo - This class contains a discriminated union of
+/// information about pointers in memory operands, relating them back to LLVM IR
+/// or to virtual locations (such as frame indices) that are exposed during
+/// codegen.
+struct MachinePointerInfo {
+  const Value *V;
+  int64_t Offset;
+  MachinePointerInfo(const Value *v, int64_t offset) : V(v), Offset(offset) {}
+};
+  
+  
 //===----------------------------------------------------------------------===//
 /// MachineMemOperand - A description of a memory reference used in the backend.
 /// Instead of holding a StoreInst or LoadInst, this class holds the address
@@ -33,10 +44,9 @@
 /// that aren't explicit in the regular LLVM IR.
 ///
 class MachineMemOperand {
-  int64_t Offset;
+  MachinePointerInfo PtrInfo;
   uint64_t Size;
-  const Value *V;
-  unsigned int Flags;
+  unsigned Flags;
 
 public:
   /// Flags values. These may be or'd together.
@@ -65,7 +75,7 @@
   /// other PseudoSourceValue member functions which return objects which stand
   /// for frame/stack pointer relative references and other special references
   /// which are not representable in the high-level IR.
-  const Value *getValue() const { return V; }
+  const Value *getValue() const { return PtrInfo.V; }
 
   /// getFlags - Return the raw flags of the source value, \see MemOperandFlags.
   unsigned int getFlags() const { return Flags & ((1 << MOMaxBits) - 1); }
@@ -73,7 +83,7 @@
   /// getOffset - For normal values, this is a byte offset added to the base
   /// address. For PseudoSourceValue::FPRel values, this is the FrameIndex
   /// number.
-  int64_t getOffset() const { return Offset; }
+  int64_t getOffset() const { return PtrInfo.Offset; }
 
   /// getSize - Return the size in bytes of the memory reference.
   uint64_t getSize() const { return Size; }
@@ -99,7 +109,8 @@
   /// setValue - Change the SourceValue for this MachineMemOperand. This
   /// should only be used when an object is being relocated and all references
   /// to it are being updated.
-  void setValue(const Value *NewSV) { V = NewSV; }
+  void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
+  void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
 
   /// Profile - Gather unique data for the object.
   ///

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=114389&r1=114388&r2=114389&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Sep 20 23:23:39 2010
@@ -337,8 +337,9 @@
 
 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
                                      int64_t o, uint64_t s, unsigned int a)
-  : Offset(o), Size(s), V(v),
+  : PtrInfo(v, o), Size(s),
     Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
+  assert((v == 0 || isa<PointerType>(v->getType())) && "invalid pointer value");
   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
   assert((isLoad() || isStore()) && "Not a load/store!");
 }
@@ -346,9 +347,9 @@
 /// Profile - Gather unique data for the object.
 ///
 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
-  ID.AddInteger(Offset);
+  ID.AddInteger(getOffset());
   ID.AddInteger(Size);
-  ID.AddPointer(V);
+  ID.AddPointer(getValue());
   ID.AddInteger(Flags);
 }
 
@@ -364,8 +365,7 @@
       ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
     // Also update the base and offset, because the new alignment may
     // not be applicable with the old ones.
-    V = MMO->getValue();
-    Offset = MMO->getOffset();
+    PtrInfo = MMO->PtrInfo;
   }
 }
 



From sabre at nondot.org  Mon Sep 20 23:32:08 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:32:08 -0000
Subject: [llvm-commits] [llvm] r114390 - in /llvm/trunk:
 include/llvm/CodeGen/MachineFunction.h
 include/llvm/CodeGen/MachineMemOperand.h lib/CodeGen/MachineFunction.cpp
 lib/CodeGen/MachineInstr.cpp
Message-ID: <20100921043208.E6AA72A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:32:08 2010
New Revision: 114390

URL: http://llvm.org/viewvc/llvm-project?rev=114390&view=rev
Log:
start pushing MachinePointerInfo out through the MachineMemOperand interface
to the MachineFunction construction methods.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=114390&r1=114389&r2=114390&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Sep 20 23:32:08 2010
@@ -37,6 +37,7 @@
 class Pass;
 class TargetMachine;
 class TargetRegisterClass;
+struct MachinePointerInfo;
 
 template <>
 struct ilist_traits<MachineBasicBlock>
@@ -372,6 +373,13 @@
                                           int64_t o, uint64_t s,
                                           unsigned base_alignment);
 
+  /// getMachineMemOperand - Allocate a new MachineMemOperand.
+  /// MachineMemOperands are owned by the MachineFunction and need not be
+  /// explicitly deallocated.
+  MachineMemOperand *getMachineMemOperand(MachinePointerInfo PtrInfo,
+                                          unsigned f, uint64_t s,
+                                          unsigned base_alignment);
+  
   /// getMachineMemOperand - Allocate a new MachineMemOperand by copying
   /// an existing one, adjusting by an offset and using the given size.
   /// MachineMemOperands are owned by the MachineFunction and need not be

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114390&r1=114389&r2=114390&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Mon Sep 20 23:32:08 2010
@@ -29,8 +29,14 @@
 /// or to virtual locations (such as frame indices) that are exposed during
 /// codegen.
 struct MachinePointerInfo {
+  /// V - This is the IR pointer value for the access, or it is null if unknown.
+  /// If this is null, then the access is to a pointer in the default address
+  /// space.
   const Value *V;
+  
+  /// Offset - This is an offset from the base Value*.
   int64_t Offset;
+  
   MachinePointerInfo(const Value *v, int64_t offset) : V(v), Offset(offset) {}
 };
   
@@ -64,9 +70,9 @@
   };
 
   /// MachineMemOperand - Construct an MachineMemOperand object with the
-  /// specified address Value, flags, offset, size, and base alignment.
-  MachineMemOperand(const Value *v, unsigned int f, int64_t o, uint64_t s,
-                    unsigned int base_alignment);
+  /// specified PtrInfo, flags, size, and base alignment.
+  MachineMemOperand(MachinePointerInfo PtrInfo, unsigned flags, uint64_t s,
+                    unsigned base_alignment);
 
   /// getValue - Return the base address of the memory access. This may either
   /// be a normal LLVM IR Value, or one of the special values used in CodeGen.

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=114390&r1=114389&r2=114390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Sep 20 23:32:08 2010
@@ -193,17 +193,23 @@
 MachineFunction::getMachineMemOperand(const Value *v, unsigned f,
                                       int64_t o, uint64_t s,
                                       unsigned base_alignment) {
-  return new (Allocator) MachineMemOperand(v, f, o, s, base_alignment);
+  return new (Allocator) MachineMemOperand(MachinePointerInfo(v, o), f,
+                                           s, base_alignment);
+}
+
+MachineMemOperand *
+MachineFunction::getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f,
+                                      uint64_t s, unsigned base_alignment) {
+  return new (Allocator) MachineMemOperand(PtrInfo, f, s, base_alignment);
 }
 
 MachineMemOperand *
 MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
                                       int64_t Offset, uint64_t Size) {
   return new (Allocator)
-             MachineMemOperand(MMO->getValue(), MMO->getFlags(),
-                               int64_t(uint64_t(MMO->getOffset()) +
-                                       uint64_t(Offset)),
-                               Size, MMO->getBaseAlignment());
+             MachineMemOperand(MachinePointerInfo(MMO->getValue(),
+                                                  MMO->getOffset()+Offset),
+                               MMO->getFlags(), Size, MMO->getBaseAlignment());
 }
 
 MachineInstr::mmo_iterator

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=114390&r1=114389&r2=114390&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Sep 20 23:32:08 2010
@@ -335,11 +335,12 @@
 // MachineMemOperand Implementation
 //===----------------------------------------------------------------------===//
 
-MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
-                                     int64_t o, uint64_t s, unsigned int a)
-  : PtrInfo(v, o), Size(s),
+MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
+                                     uint64_t s, unsigned int a)
+  : PtrInfo(ptrinfo), Size(s),
     Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
-  assert((v == 0 || isa<PointerType>(v->getType())) && "invalid pointer value");
+  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
+         "invalid pointer value");
   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
   assert((isLoad() || isStore()) && "Not a load/store!");
 }



From sabre at nondot.org  Mon Sep 20 23:39:44 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:39:44 -0000
Subject: [llvm-commits] [llvm] r114391 - in /llvm/trunk/lib/Target:
 ARM/ARMBaseInstrInfo.cpp ARM/Thumb1InstrInfo.cpp ARM/Thumb2InstrInfo.cpp
 MSP430/MSP430InstrInfo.cpp PowerPC/PPCISelLowering.cpp
 PowerPC/PPCInstrInfo.cpp SystemZ/SystemZInstrBuilder.h
 X86/X86ISelLowering.cpp X86/X86InstrBuilder.h
Message-ID: <20100921043944.5BBF92A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:39:43 2010
New Revision: 114391

URL: http://llvm.org/viewvc/llvm-project?rev=114391&view=rev
Log:
convert targets to the new MF.getMachineMemOperand interface.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Sep 20 23:39:43 2010
@@ -637,8 +637,9 @@
   unsigned Align = MFI.getObjectAlignment(FI);
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                            MachineMemOperand::MOStore, 0,
+    MF.getMachineMemOperand(MachinePointerInfo(
+                                         PseudoSourceValue::getFixedStack(FI)),
+                            MachineMemOperand::MOStore,
                             MFI.getObjectSize(FI),
                             Align);
 
@@ -783,8 +784,9 @@
   MachineFrameInfo &MFI = *MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                            MachineMemOperand::MOLoad, 0,
+    MF.getMachineMemOperand(
+                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                            MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FI),
                             Align);
 

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Mon Sep 20 23:39:43 2010
@@ -71,8 +71,9 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                              MachineMemOperand::MOStore, 0,
+      MF.getMachineMemOperand(
+                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                              MachineMemOperand::MOStore,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
@@ -99,8 +100,9 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                              MachineMemOperand::MOLoad, 0,
+      MF.getMachineMemOperand(
+                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                              MachineMemOperand::MOLoad,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Mon Sep 20 23:39:43 2010
@@ -155,8 +155,9 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                              MachineMemOperand::MOStore, 0,
+      MF.getMachineMemOperand(
+                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                              MachineMemOperand::MOStore,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
@@ -181,8 +182,9 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                              MachineMemOperand::MOLoad, 0,
+      MF.getMachineMemOperand(
+                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                              MachineMemOperand::MOLoad,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Mon Sep 20 23:39:43 2010
@@ -40,8 +40,9 @@
   MachineFrameInfo &MFI = *MF.getFrameInfo();
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
-                            MachineMemOperand::MOStore, 0,
+    MF.getMachineMemOperand(
+              MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+                            MachineMemOperand::MOStore,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));
 
@@ -68,8 +69,9 @@
   MachineFrameInfo &MFI = *MF.getFrameInfo();
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
-                            MachineMemOperand::MOLoad, 0,
+    MF.getMachineMemOperand(
+              MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+                            MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Sep 20 23:39:43 2010
@@ -3591,8 +3591,9 @@
 
   // STD the extended value into the stack slot.
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
-                            MachineMemOperand::MOStore, 0, 8, 8);
+    MF.getMachineMemOperand(
+                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+                            MachineMemOperand::MOStore, 8, 8);
   SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
   SDValue Store =
     DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Sep 20 23:39:43 2010
@@ -469,8 +469,9 @@
 
   const MachineFrameInfo &MFI = *MF.getFrameInfo();
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
-                            MachineMemOperand::MOStore, /*Offset=*/0,
+    MF.getMachineMemOperand(
+                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+                            MachineMemOperand::MOStore,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));
   NewMIs.back()->addMemOperand(MF, MMO);
@@ -590,8 +591,9 @@
 
   const MachineFrameInfo &MFI = *MF.getFrameInfo();
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
-                            MachineMemOperand::MOLoad, /*Offset=*/0,
+    MF.getMachineMemOperand(
+                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+                            MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));
   NewMIs.back()->addMemOperand(MF, MMO);

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h Mon Sep 20 23:39:43 2010
@@ -115,9 +115,9 @@
   if (TID.mayStore())
     Flags |= MachineMemOperand::MOStore;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                            Flags, Offset,
-                            MFI.getObjectSize(FI),
+    MF.getMachineMemOperand(MachinePointerInfo(
+                                PseudoSourceValue::getFixedStack(FI), Offset),
+                            Flags, MFI.getObjectSize(FI),
                             MFI.getObjectAlignment(FI));
   return addOffset(MIB.addFrameIndex(FI), Offset)
             .addMemOperand(MMO);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 20 23:39:43 2010
@@ -9463,8 +9463,9 @@
     int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
     MachineMemOperand *MMO =
       F->getMachineMemOperand(
-        PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
-        MachineMemOperand::MOStore, Offset,
+        MachinePointerInfo(PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
+                           Offset),
+        MachineMemOperand::MOStore,
         /*Size=*/16, /*Align=*/16);
     BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
       .addFrameIndex(RegSaveFrameIndex)

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=114391&r1=114390&r2=114391&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Mon Sep 20 23:39:43 2010
@@ -157,9 +157,9 @@
   if (TID.mayStore())
     Flags |= MachineMemOperand::MOStore;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                            Flags, Offset,
-                            MFI.getObjectSize(FI),
+    MF.getMachineMemOperand(MachinePointerInfo(
+                                 PseudoSourceValue::getFixedStack(FI), Offset),
+                            Flags, MFI.getObjectSize(FI),
                             MFI.getObjectAlignment(FI));
   return addOffset(MIB.addFrameIndex(FI), Offset)
             .addMemOperand(MMO);



From sabre at nondot.org  Mon Sep 20 23:46:39 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:46:39 -0000
Subject: [llvm-commits] [llvm] r114393 - in /llvm/trunk:
 include/llvm/CodeGen/MachineFunction.h
 include/llvm/CodeGen/MachineMemOperand.h lib/CodeGen/MachineFunction.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/TargetInstrInfoImpl.cpp
Message-ID: <20100921044639.D28082A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:46:39 2010
New Revision: 114393

URL: http://llvm.org/viewvc/llvm-project?rev=114393&view=rev
Log:
force clients of MachineFunction::getMachineMemOperand to provide a
MachinePointerInfo, propagating the type out a level of API.  Remove
the old MachineFunction::getMachineMemOperand impl.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=114393&r1=114392&r2=114393&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Sep 20 23:46:39 2010
@@ -369,13 +369,6 @@
   /// getMachineMemOperand - Allocate a new MachineMemOperand.
   /// MachineMemOperands are owned by the MachineFunction and need not be
   /// explicitly deallocated.
-  MachineMemOperand *getMachineMemOperand(const Value *v, unsigned f,
-                                          int64_t o, uint64_t s,
-                                          unsigned base_alignment);
-
-  /// getMachineMemOperand - Allocate a new MachineMemOperand.
-  /// MachineMemOperands are owned by the MachineFunction and need not be
-  /// explicitly deallocated.
   MachineMemOperand *getMachineMemOperand(MachinePointerInfo PtrInfo,
                                           unsigned f, uint64_t s,
                                           unsigned base_alignment);

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114393&r1=114392&r2=114393&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Mon Sep 20 23:46:39 2010
@@ -37,7 +37,8 @@
   /// Offset - This is an offset from the base Value*.
   int64_t Offset;
   
-  MachinePointerInfo(const Value *v, int64_t offset) : V(v), Offset(offset) {}
+  explicit MachinePointerInfo(const Value *v, int64_t offset = 0)
+    : V(v), Offset(offset) {}
 };
   
   
@@ -74,6 +75,8 @@
   MachineMemOperand(MachinePointerInfo PtrInfo, unsigned flags, uint64_t s,
                     unsigned base_alignment);
 
+  const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
+  
   /// getValue - Return the base address of the memory access. This may either
   /// be a normal LLVM IR Value, or one of the special values used in CodeGen.
   /// Special values are those obtained via

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=114393&r1=114392&r2=114393&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Sep 20 23:46:39 2010
@@ -190,14 +190,6 @@
 }
 
 MachineMemOperand *
-MachineFunction::getMachineMemOperand(const Value *v, unsigned f,
-                                      int64_t o, uint64_t s,
-                                      unsigned base_alignment) {
-  return new (Allocator) MachineMemOperand(MachinePointerInfo(v, o), f,
-                                           s, base_alignment);
-}
-
-MachineMemOperand *
 MachineFunction::getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f,
                                       uint64_t s, unsigned base_alignment) {
   return new (Allocator) MachineMemOperand(PtrInfo, f, s, base_alignment);
@@ -237,10 +229,9 @@
       else {
         // Clone the MMO and unset the store flag.
         MachineMemOperand *JustLoad =
-          getMachineMemOperand((*I)->getValue(),
+          getMachineMemOperand((*I)->getPointerInfo(),
                                (*I)->getFlags() & ~MachineMemOperand::MOStore,
-                               (*I)->getOffset(), (*I)->getSize(),
-                               (*I)->getBaseAlignment());
+                               (*I)->getSize(), (*I)->getBaseAlignment());
         Result[Index] = JustLoad;
       }
       ++Index;
@@ -269,10 +260,9 @@
       else {
         // Clone the MMO and unset the load flag.
         MachineMemOperand *JustStore =
-          getMachineMemOperand((*I)->getValue(),
+          getMachineMemOperand((*I)->getPointerInfo(),
                                (*I)->getFlags() & ~MachineMemOperand::MOLoad,
-                               (*I)->getOffset(), (*I)->getSize(),
-                               (*I)->getBaseAlignment());
+                               (*I)->getSize(), (*I)->getBaseAlignment());
         Result[Index] = JustStore;
       }
       ++Index;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114393&r1=114392&r2=114393&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Sep 20 23:46:39 2010
@@ -3671,7 +3671,7 @@
 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
                                 SDValue Chain,
                                 SDValue Ptr, SDValue Cmp,
-                                SDValue Swp, const Value* PtrVal,
+                                SDValue Swp, const Value *PtrVal,
                                 unsigned Alignment) {
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(MemVT);
@@ -3689,7 +3689,7 @@
   Flags |= MachineMemOperand::MOVolatile;
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PtrVal, Flags, 0,
+    MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags,
                             MemVT.getStoreSize(), Alignment);
 
   return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO);
@@ -3742,7 +3742,7 @@
   Flags |= MachineMemOperand::MOVolatile;
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PtrVal, Flags, 0,
+    MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags,
                             MemVT.getStoreSize(), Alignment);
 
   return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Val, MMO);
@@ -3829,7 +3829,7 @@
   if (Vol)
     Flags |= MachineMemOperand::MOVolatile;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(srcValue, Flags, SVOff,
+    MF.getMachineMemOperand(MachinePointerInfo(srcValue, SVOff), Flags,
                             MemVT.getStoreSize(), Align);
 
   return getMemIntrinsicNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO);
@@ -3890,7 +3890,7 @@
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(SV, Flags, SVOffset,
+    MF.getMachineMemOperand(MachinePointerInfo(SV, SVOffset), Flags, 
                             MemVT.getStoreSize(), Alignment);
   return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
 }
@@ -3994,7 +3994,7 @@
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(SV, Flags, SVOffset,
+    MF.getMachineMemOperand(MachinePointerInfo(SV, SVOffset), Flags,
                             Val.getValueType().getStoreSize(), Alignment);
 
   return getStore(Chain, dl, Val, Ptr, MMO);
@@ -4044,7 +4044,8 @@
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(SV, Flags, SVOffset, SVT.getStoreSize(), Alignment);
+    MF.getMachineMemOperand(MachinePointerInfo(SV, SVOffset), Flags,
+                            SVT.getStoreSize(), Alignment);
 
   return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
 }

Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=114393&r1=114392&r2=114393&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Sep 20 23:46:39 2010
@@ -252,9 +252,9 @@
     const MachineFrameInfo &MFI = *MF.getFrameInfo();
     assert(MFI.getObjectOffset(FI) != -1);
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
-                              Flags, /*Offset=*/0,
-                              MFI.getObjectSize(FI),
+      MF.getMachineMemOperand(
+                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                              Flags, MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
     NewMI->addMemOperand(MF, MMO);
 



From sabre at nondot.org  Mon Sep 20 23:51:11 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:51:11 -0000
Subject: [llvm-commits] [llvm] r114395 -
 /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Message-ID: <20100921045111.8C0482A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:51:11 2010
New Revision: 114395

URL: http://llvm.org/viewvc/llvm-project?rev=114395&view=rev
Log:
don't implicitly drop the offset of a machinememoperand when legalizing atomics.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=114395&r1=114394&r2=114395&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Sep 20 23:51:11 2010
@@ -143,7 +143,7 @@
   SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
                               N->getMemoryVT(),
                               N->getChain(), N->getBasePtr(),
-                              Op2, N->getSrcValue(), N->getAlignment());
+                              Op2, N->getMemOperand());
   // Legalized the chain result - switch anything that used the old chain to
   // use the new one.
   ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
@@ -155,7 +155,7 @@
   SDValue Op3 = GetPromotedInteger(N->getOperand(3));
   SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
                               N->getMemoryVT(), N->getChain(), N->getBasePtr(),
-                              Op2, Op3, N->getSrcValue(), N->getAlignment());
+                              Op2, Op3, N->getMemOperand());
   // Legalized the chain result - switch anything that used the old chain to
   // use the new one.
   ReplaceValueWith(SDValue(N, 1), Res.getValue(1));



From sabre at nondot.org  Mon Sep 20 23:53:42 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:53:42 -0000
Subject: [llvm-commits] [llvm] r114396 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100921045342.AEBD62A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:53:42 2010
New Revision: 114396

URL: http://llvm.org/viewvc/llvm-project?rev=114396&view=rev
Log:
chagne interface to SelectionDAG::getAtomic to take a MachinePointerInfo,
eliminating some weird "infer a frame address" logic which was dead.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114396&r1=114395&r2=114396&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Sep 20 23:53:42 2010
@@ -587,8 +587,8 @@
   /// getAtomic - Gets a node for an atomic op, produces result and chain and
   /// takes 3 operands
   SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
-                    SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
-                    unsigned Alignment=0);
+                    SDValue Ptr, SDValue Cmp, SDValue Swp,
+                    MachinePointerInfo PtrInfo, unsigned Alignment=0);
   SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
                     SDValue Ptr, SDValue Cmp, SDValue Swp,
                     MachineMemOperand *MMO);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114396&r1=114395&r2=114396&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Sep 20 23:53:42 2010
@@ -3669,19 +3669,12 @@
 }
 
 SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
-                                SDValue Chain,
-                                SDValue Ptr, SDValue Cmp,
-                                SDValue Swp, const Value *PtrVal,
+                                SDValue Chain, SDValue Ptr, SDValue Cmp,
+                                SDValue Swp, MachinePointerInfo PtrInfo,
                                 unsigned Alignment) {
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(MemVT);
 
-  // Check if the memory reference references a frame index
-  if (!PtrVal)
-    if (const FrameIndexSDNode *FI =
-          dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
-      PtrVal = PseudoSourceValue::getFixedStack(FI->getIndex());
-
   MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
 
@@ -3689,8 +3682,7 @@
   Flags |= MachineMemOperand::MOVolatile;
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(PtrVal), Flags,
-                            MemVT.getStoreSize(), Alignment);
+    MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment);
 
   return getAtomic(Opcode, dl, MemVT, Chain, Ptr, Cmp, Swp, MMO);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114396&r1=114395&r2=114396&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Sep 20 23:53:42 2010
@@ -4550,7 +4550,7 @@
                     getValue(I.getArgOperand(0)),
                     getValue(I.getArgOperand(1)),
                     getValue(I.getArgOperand(2)),
-                    I.getArgOperand(0));
+                    MachinePointerInfo(I.getArgOperand(0)));
     setValue(&I, L);
     DAG.setRoot(L.getValue(1));
     return 0;



From sabre at nondot.org  Mon Sep 20 23:57:15 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 04:57:15 -0000
Subject: [llvm-commits] [llvm] r114397 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100921045715.D4F2C2A6C12C@llvm.org>

Author: lattner
Date: Mon Sep 20 23:57:15 2010
New Revision: 114397

URL: http://llvm.org/viewvc/llvm-project?rev=114397&view=rev
Log:
simplify interface to SelectionDAG::getMemIntrinsicNode, making it take a MachinePointerInfo

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114397&r1=114396&r2=114397&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Sep 20 23:57:15 2010
@@ -609,13 +609,13 @@
   SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
                               const EVT *VTs, unsigned NumVTs,
                               const SDValue *Ops, unsigned NumOps,
-                              EVT MemVT, const Value *srcValue, int SVOff,
+                              EVT MemVT, MachinePointerInfo PtrInfo,
                               unsigned Align = 0, bool Vol = false,
                               bool ReadMem = true, bool WriteMem = true);
 
   SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
                               const SDValue *Ops, unsigned NumOps,
-                              EVT MemVT, const Value *srcValue, int SVOff,
+                              EVT MemVT, MachinePointerInfo PtrInfo,
                               unsigned Align = 0, bool Vol = false,
                               bool ReadMem = true, bool WriteMem = true);
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114397&r1=114396&r2=114397&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Sep 20 23:57:15 2010
@@ -3795,18 +3795,18 @@
 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
                                   const EVT *VTs, unsigned NumVTs,
                                   const SDValue *Ops, unsigned NumOps,
-                                  EVT MemVT, const Value *srcValue, int SVOff,
+                                  EVT MemVT, MachinePointerInfo PtrInfo,
                                   unsigned Align, bool Vol,
                                   bool ReadMem, bool WriteMem) {
   return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
-                             MemVT, srcValue, SVOff, Align, Vol,
+                             MemVT, PtrInfo, Align, Vol,
                              ReadMem, WriteMem);
 }
 
 SDValue
 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
                                   const SDValue *Ops, unsigned NumOps,
-                                  EVT MemVT, const Value *srcValue, int SVOff,
+                                  EVT MemVT, MachinePointerInfo PtrInfo,
                                   unsigned Align, bool Vol,
                                   bool ReadMem, bool WriteMem) {
   if (Align == 0)  // Ensure that codegen never sees alignment 0
@@ -3821,8 +3821,7 @@
   if (Vol)
     Flags |= MachineMemOperand::MOVolatile;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(srcValue, SVOff), Flags,
-                            MemVT.getStoreSize(), Align);
+    MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Align);
 
   return getMemIntrinsicNode(Opcode, dl, VTList, Ops, NumOps, MemVT, MMO);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114397&r1=114396&r2=114397&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Sep 20 23:57:15 2010
@@ -3062,7 +3062,8 @@
     // This is target intrinsic that touches memory
     Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
                                      VTs, &Ops[0], Ops.size(),
-                                     Info.memVT, Info.ptrVal, Info.offset,
+                                     Info.memVT,
+                                   MachinePointerInfo(Info.ptrVal, Info.offset),
                                      Info.align, Info.vol,
                                      Info.readMem, Info.writeMem);
   } else if (!HasChain) {



From daniel at zuster.org  Tue Sep 21 00:00:06 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 21 Sep 2010 05:00:06 -0000
Subject: [llvm-commits] [zorg] r114398 -
	/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
Message-ID: <20100921050006.A01C72A6C12C@llvm.org>

Author: ddunbar
Date: Tue Sep 21 00:00:06 2010
New Revision: 114398

URL: http://llvm.org/viewvc/llvm-project?rev=114398&view=rev
Log:
Spell projects correctly

Modified:
    zorg/trunk/zorg/buildbot/builders/ClangBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=114398&r1=114397&r2=114398&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Tue Sep 21 00:00:06 2010
@@ -72,7 +72,7 @@
                       mode='update',
                       baseURL='http://llvm.org/svn/llvm-project/compiler-rt/',
                       defaultBranch='trunk',
-                      workdir='%s/project/compiler-rt' % llvm_srcdir))
+                      workdir='%s/projects/compiler-rt' % llvm_srcdir))
 
     # Clean up llvm (stage 1); unless in-dir.
     if clean and llvm_srcdir != llvm_1_objdir:



From sabre at nondot.org  Tue Sep 21 00:10:46 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 05:10:46 -0000
Subject: [llvm-commits] [llvm] r114399 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <20100921051046.1CC8A2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 00:10:45 2010
New Revision: 114399

URL: http://llvm.org/viewvc/llvm-project?rev=114399&view=rev
Log:
add overloads for SelectionDAG::getLoad, getStore, getTruncStore that take a
MachinePointerInfo.  Among other virtues, this doesn't silently  truncate the
svoffset to 32-bits.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114399&r1=114398&r2=114399&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 00:10:45 2010
@@ -646,16 +646,28 @@
   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
                   EVT VT, DebugLoc dl,
                   SDValue Chain, SDValue Ptr, SDValue Offset,
+                  MachinePointerInfo PtrInfo, EVT MemVT,
+                  bool isVolatile, bool isNonTemporal, unsigned Alignment);
+  SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+                  EVT VT, DebugLoc dl,
+                  SDValue Chain, SDValue Ptr, SDValue Offset,
                   EVT MemVT, MachineMemOperand *MMO);
 
   /// getStore - Helper function to build ISD::STORE nodes.
   ///
   SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
-                   const Value *SV, int SVOffset, bool isVolatile,
+                   MachinePointerInfo PtrInfo, bool isVolatile,
+                   bool isNonTemporal, unsigned Alignment);
+  SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
+                   const Value *V, int SVOffset, bool isVolatile,
                    bool isNonTemporal, unsigned Alignment);
   SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
                    MachineMemOperand *MMO);
   SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
+                        MachinePointerInfo PtrInfo, EVT TVT,
+                        bool isNonTemporal, bool isVolatile,
+                        unsigned Alignment);
+  SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
                         const Value *SV, int SVOffset, EVT TVT,
                         bool isNonTemporal, bool isVolatile,
                         unsigned Alignment);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114399&r1=114398&r2=114399&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 00:10:45 2010
@@ -3865,14 +3865,27 @@
                       const Value *SV, int SVOffset, EVT MemVT,
                       bool isVolatile, bool isNonTemporal,
                       unsigned Alignment) {
-  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
-    Alignment = getEVTAlignment(VT);
 
   // Check if the memory reference references a frame index
   if (!SV)
     if (const FrameIndexSDNode *FI =
-          dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+        dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
       SV = PseudoSourceValue::getFixedStack(FI->getIndex());
+  
+  return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset,
+                 MachinePointerInfo(SV, SVOffset), MemVT, isVolatile,
+                 isNonTemporal, Alignment);
+}
+
+SDValue
+SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+                      EVT VT, DebugLoc dl, SDValue Chain,
+                      SDValue Ptr, SDValue Offset,
+                      MachinePointerInfo PtrInfo, EVT MemVT,
+                      bool isVolatile, bool isNonTemporal,
+                      unsigned Alignment) {
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getEVTAlignment(VT);
 
   MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOLoad;
@@ -3881,8 +3894,7 @@
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(SV, SVOffset), Flags, 
-                            MemVT.getStoreSize(), Alignment);
+    MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment);
   return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
 }
 
@@ -3966,18 +3978,12 @@
 }
 
 SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
-                               SDValue Ptr, const Value *SV, int SVOffset,
+                               SDValue Ptr, MachinePointerInfo PtrInfo,
                                bool isVolatile, bool isNonTemporal,
                                unsigned Alignment) {
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(Val.getValueType());
 
-  // Check if the memory reference references a frame index
-  if (!SV)
-    if (const FrameIndexSDNode *FI =
-          dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
-      SV = PseudoSourceValue::getFixedStack(FI->getIndex());
-
   MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOStore;
   if (isVolatile)
@@ -3985,13 +3991,28 @@
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(SV, SVOffset), Flags,
+    MF.getMachineMemOperand(PtrInfo, Flags,
                             Val.getValueType().getStoreSize(), Alignment);
 
   return getStore(Chain, dl, Val, Ptr, MMO);
 }
 
 SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
+                               SDValue Ptr,
+                 const Value *SV, int SVOffset, bool isVolatile,
+                 bool isNonTemporal, unsigned Alignment) {
+  // Check if the memory reference references a frame index
+  if (!SV)
+    if (const FrameIndexSDNode *FI =
+        dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+      SV = PseudoSourceValue::getFixedStack(FI->getIndex());
+  
+  return getStore(Chain, dl, Val, Ptr, MachinePointerInfo(SV, SVOffset),
+                  isVolatile, isNonTemporal, Alignment);
+}
+
+
+SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
                                SDValue Ptr, MachineMemOperand *MMO) {
   EVT VT = Val.getValueType();
   SDVTList VTs = getVTList(MVT::Other);
@@ -4019,14 +4040,23 @@
                                     int SVOffset, EVT SVT,
                                     bool isVolatile, bool isNonTemporal,
                                     unsigned Alignment) {
-  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
-    Alignment = getEVTAlignment(SVT);
 
   // Check if the memory reference references a frame index
   if (!SV)
     if (const FrameIndexSDNode *FI =
-          dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
+        dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
       SV = PseudoSourceValue::getFixedStack(FI->getIndex());
+ 
+  return getTruncStore(Chain, dl, Val, Ptr, MachinePointerInfo(SV, SVOffset),
+                       SVT, isVolatile, isNonTemporal, Alignment);
+}  
+  
+SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
+                                    SDValue Ptr, MachinePointerInfo PtrInfo,
+                                    EVT SVT,bool isVolatile, bool isNonTemporal,
+                                    unsigned Alignment) {
+  if (Alignment == 0)  // Ensure that codegen never sees alignment 0
+    Alignment = getEVTAlignment(SVT);
 
   MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOStore;
@@ -4035,8 +4065,7 @@
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(SV, SVOffset), Flags,
-                            SVT.getStoreSize(), Alignment);
+    MF.getMachineMemOperand(PtrInfo, Flags, SVT.getStoreSize(), Alignment);
 
   return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
 }



From sabre at nondot.org  Tue Sep 21 00:39:30 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 05:39:30 -0000
Subject: [llvm-commits] [llvm] r114400 - in /llvm/trunk:
 include/llvm/CodeGen/MachineMemOperand.h
 include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/MachineInstr.cpp
Message-ID: <20100921053930.84A402A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 00:39:30 2010
New Revision: 114400

URL: http://llvm.org/viewvc/llvm-project?rev=114400&view=rev
Log:
add some helpful accessors.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114400&r1=114399&r2=114400&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Tue Sep 21 00:39:30 2010
@@ -39,6 +39,15 @@
   
   explicit MachinePointerInfo(const Value *v, int64_t offset = 0)
     : V(v), Offset(offset) {}
+  
+  MachinePointerInfo getWithOffset(int64_t O) const {
+    if (V == 0) return MachinePointerInfo(0, 0);
+    return MachinePointerInfo(V, Offset+O);
+  }
+  
+  /// getAddrSpace - Return the LLVM IR address space number that this pointer
+  /// points into.
+  unsigned getAddrSpace() const;
 };
   
   

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=114400&r1=114399&r2=114400&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Sep 21 00:39:30 2010
@@ -909,6 +909,10 @@
   /// reference performed by operation.
   MachineMemOperand *getMemOperand() const { return MMO; }
 
+  const MachinePointerInfo &getPointerInfo() const {
+    return MMO->getPointerInfo();
+  }
+  
   /// refineAlignment - Update this MemSDNode's MachineMemOperand information
   /// to reflect the alignment of NewMMO, if it has a greater alignment.
   /// This must only be used when the new alignment applies to all users of

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=114400&r1=114399&r2=114400&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Sep 21 00:39:30 2010
@@ -335,6 +335,14 @@
 // MachineMemOperand Implementation
 //===----------------------------------------------------------------------===//
 
+/// getAddrSpace - Return the LLVM IR address space number that this pointer
+/// points into.
+unsigned MachinePointerInfo::getAddrSpace() const {
+  if (V == 0) return 0;
+  return cast<PointerType>(V->getType())->getAddressSpace();
+}
+
+
 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
                                      uint64_t s, unsigned int a)
   : PtrInfo(ptrinfo), Size(s),



From sabre at nondot.org  Tue Sep 21 00:40:29 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 05:40:29 -0000
Subject: [llvm-commits] [llvm] r114401 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 include/llvm/Target/TargetSelectionDAGInfo.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMSelectionDAGInfo.cpp
 lib/Target/ARM/ARMSelectionDAGInfo.h lib/Target/PowerPC/PPCISelLowering.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86SelectionDAGInfo.cpp
 lib/Target/X86/X86SelectionDAGInfo.h lib/Target/XCore/XCoreISelLowering.cpp
Message-ID: <20100921054029.987532A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 00:40:29 2010
New Revision: 114401

URL: http://llvm.org/viewvc/llvm-project?rev=114401&view=rev
Log:
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/Target/TargetSelectionDAGInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
    llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 00:40:29 2010
@@ -542,17 +542,17 @@
 
   SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
                     SDValue Size, unsigned Align, bool isVol, bool AlwaysInline,
-                    const Value *DstSV, uint64_t DstSVOff,
-                    const Value *SrcSV, uint64_t SrcSVOff);
+                    MachinePointerInfo DstPtrInfo,
+                    MachinePointerInfo SrcPtrInfo);
 
   SDValue getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
                      SDValue Size, unsigned Align, bool isVol,
-                     const Value *DstSV, uint64_t DstOSVff,
-                     const Value *SrcSV, uint64_t SrcSVOff);
+                     MachinePointerInfo DstPtrInfo,
+                     MachinePointerInfo SrcPtrInfo);
 
   SDValue getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
                     SDValue Size, unsigned Align, bool isVol,
-                    const Value *DstSV, uint64_t DstSVOff);
+                    MachinePointerInfo DstPtrInfo);
 
   /// getSetCC - Helper function to make it easier to build SetCC's if you just
   /// have an ISD::CondCode instead of an SDValue.
@@ -630,9 +630,16 @@
   /// determined by their operands, and they produce a value AND a token chain.
   ///
   SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
+                  MachinePointerInfo PtrInfo, bool isVolatile,
+                  bool isNonTemporal, unsigned Alignment);
+  SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
                   const Value *SV, int SVOffset, bool isVolatile,
                   bool isNonTemporal, unsigned Alignment);
   SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
+                     SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,
+                     EVT MemVT, bool isVolatile,
+                     bool isNonTemporal, unsigned Alignment);
+  SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
                      SDValue Chain, SDValue Ptr, const Value *SV,
                      int SVOffset, EVT MemVT, bool isVolatile,
                      bool isNonTemporal, unsigned Alignment);

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAGInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAGInfo.h?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAGInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAGInfo.h Tue Sep 21 00:40:29 2010
@@ -59,8 +59,8 @@
                           SDValue Op1, SDValue Op2,
                           SDValue Op3, unsigned Align, bool isVolatile,
                           bool AlwaysInline,
-                          const Value *DstSV, uint64_t DstOff,
-                          const Value *SrcSV, uint64_t SrcOff) const {
+                          MachinePointerInfo DstPtrInfo,
+                          MachinePointerInfo SrcPtrInfo) const {
     return SDValue();
   }
 
@@ -75,8 +75,8 @@
                            SDValue Chain,
                            SDValue Op1, SDValue Op2,
                            SDValue Op3, unsigned Align, bool isVolatile,
-                           const Value *DstSV, uint64_t DstOff,
-                           const Value *SrcSV, uint64_t SrcOff) const {
+                           MachinePointerInfo DstPtrInfo,
+                           MachinePointerInfo SrcPtrInfo) const {
     return SDValue();
   }
 
@@ -91,7 +91,7 @@
                           SDValue Chain,
                           SDValue Op1, SDValue Op2,
                           SDValue Op3, unsigned Align, bool isVolatile,
-                          const Value *DstSV, uint64_t DstOff) const {
+                          MachinePointerInfo DstPtrInfo) const {
     return SDValue();
   }
 };

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 00:40:29 2010
@@ -3276,8 +3276,8 @@
                                        SDValue Src, uint64_t Size,
                                        unsigned Align, bool isVol,
                                        bool AlwaysInline,
-                                       const Value *DstSV, uint64_t DstSVOff,
-                                       const Value *SrcSV, uint64_t SrcSVOff) {
+                                       MachinePointerInfo DstPtrInfo,
+                                       MachinePointerInfo SrcPtrInfo) {
   // Turn a memcpy of undef to nop.
   if (Src.getOpcode() == ISD::UNDEF)
     return Chain;
@@ -3334,7 +3334,8 @@
       Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff);
       Store = DAG.getStore(Chain, dl, Value,
                            getMemBasePlusOffset(Dst, DstOff, DAG),
-                           DstSV, DstSVOff + DstOff, isVol, false, Align);
+                           DstPtrInfo.getWithOffset(DstOff), isVol,
+                           false, Align);
     } else {
       // The type might not be legal for the target.  This should only happen
       // if the type is smaller than a legal type, as on PPC, so the right
@@ -3345,12 +3346,12 @@
       assert(NVT.bitsGE(VT));
       Value = DAG.getExtLoad(ISD::EXTLOAD, NVT, dl, Chain,
                              getMemBasePlusOffset(Src, SrcOff, DAG),
-                             SrcSV, SrcSVOff + SrcOff, VT, isVol, false,
+                             SrcPtrInfo.getWithOffset(SrcOff), VT, isVol, false,
                              MinAlign(SrcAlign, SrcOff));
       Store = DAG.getTruncStore(Chain, dl, Value,
                                 getMemBasePlusOffset(Dst, DstOff, DAG),
-                                DstSV, DstSVOff + DstOff, VT, isVol, false,
-                                Align);
+                                DstPtrInfo.getWithOffset(DstOff), VT, isVol,
+                                false, Align);
     }
     OutChains.push_back(Store);
     SrcOff += VTSize;
@@ -3366,8 +3367,8 @@
                                         SDValue Src, uint64_t Size,
                                         unsigned Align,  bool isVol,
                                         bool AlwaysInline,
-                                        const Value *DstSV, uint64_t DstSVOff,
-                                        const Value *SrcSV, uint64_t SrcSVOff) {
+                                        MachinePointerInfo DstPtrInfo,
+                                        MachinePointerInfo SrcPtrInfo) {
   // Turn a memmove of undef to nop.
   if (Src.getOpcode() == ISD::UNDEF)
     return Chain;
@@ -3414,7 +3415,8 @@
 
     Value = DAG.getLoad(VT, dl, Chain,
                         getMemBasePlusOffset(Src, SrcOff, DAG),
-                        SrcSV, SrcSVOff + SrcOff, isVol, false, SrcAlign);
+                        SrcPtrInfo.getWithOffset(SrcOff), isVol,
+                        false, SrcAlign);
     LoadValues.push_back(Value);
     LoadChains.push_back(Value.getValue(1));
     SrcOff += VTSize;
@@ -3429,7 +3431,7 @@
 
     Store = DAG.getStore(Chain, dl, LoadValues[i],
                          getMemBasePlusOffset(Dst, DstOff, DAG),
-                         DstSV, DstSVOff + DstOff, isVol, false, Align);
+                         DstPtrInfo.getWithOffset(DstOff), isVol, false, Align);
     OutChains.push_back(Store);
     DstOff += VTSize;
   }
@@ -3442,7 +3444,7 @@
                                SDValue Chain, SDValue Dst,
                                SDValue Src, uint64_t Size,
                                unsigned Align, bool isVol,
-                               const Value *DstSV, uint64_t DstSVOff) {
+                               MachinePointerInfo DstPtrInfo) {
   // Turn a memset of undef to nop.
   if (Src.getOpcode() == ISD::UNDEF)
     return Chain;
@@ -3483,7 +3485,8 @@
     SDValue Value = getMemsetValue(Src, VT, DAG, dl);
     SDValue Store = DAG.getStore(Chain, dl, Value,
                                  getMemBasePlusOffset(Dst, DstOff, DAG),
-                                 DstSV, DstSVOff + DstOff, isVol, false, 0);
+                                 DstPtrInfo.getWithOffset(DstOff),
+                                 isVol, false, 0);
     OutChains.push_back(Store);
     DstOff += VTSize;
   }
@@ -3495,8 +3498,8 @@
 SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
                                 SDValue Src, SDValue Size,
                                 unsigned Align, bool isVol, bool AlwaysInline,
-                                const Value *DstSV, uint64_t DstSVOff,
-                                const Value *SrcSV, uint64_t SrcSVOff) {
+                                MachinePointerInfo DstPtrInfo,
+                                MachinePointerInfo SrcPtrInfo) {
 
   // Check to see if we should lower the memcpy to loads and stores first.
   // For cases within the target-specified limits, this is the best choice.
@@ -3508,7 +3511,7 @@
 
     SDValue Result = getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
                                              ConstantSize->getZExtValue(),Align,
-                                isVol, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
+                                isVol, false, DstPtrInfo, SrcPtrInfo);
     if (Result.getNode())
       return Result;
   }
@@ -3518,7 +3521,7 @@
   SDValue Result =
     TSI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align,
                                 isVol, AlwaysInline,
-                                DstSV, DstSVOff, SrcSV, SrcSVOff);
+                                DstPtrInfo, SrcPtrInfo);
   if (Result.getNode())
     return Result;
 
@@ -3528,7 +3531,7 @@
     assert(ConstantSize && "AlwaysInline requires a constant size!");
     return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
                                    ConstantSize->getZExtValue(), Align, isVol,
-                                   true, DstSV, DstSVOff, SrcSV, SrcSVOff);
+                                   true, DstPtrInfo, SrcPtrInfo);
   }
 
   // FIXME: If the memcpy is volatile (isVol), lowering it to a plain libc
@@ -3559,8 +3562,8 @@
 SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
                                  SDValue Src, SDValue Size,
                                  unsigned Align, bool isVol,
-                                 const Value *DstSV, uint64_t DstSVOff,
-                                 const Value *SrcSV, uint64_t SrcSVOff) {
+                                 MachinePointerInfo DstPtrInfo,
+                                 MachinePointerInfo SrcPtrInfo) {
 
   // Check to see if we should lower the memmove to loads and stores first.
   // For cases within the target-specified limits, this is the best choice.
@@ -3573,7 +3576,7 @@
     SDValue Result =
       getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src,
                                ConstantSize->getZExtValue(), Align, isVol,
-                               false, DstSV, DstSVOff, SrcSV, SrcSVOff);
+                               false, DstPtrInfo, SrcPtrInfo);
     if (Result.getNode())
       return Result;
   }
@@ -3582,7 +3585,7 @@
   // code. If the target chooses to do this, this is the next best.
   SDValue Result =
     TSI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, isVol,
-                                 DstSV, DstSVOff, SrcSV, SrcSVOff);
+                                 DstPtrInfo, SrcPtrInfo);
   if (Result.getNode())
     return Result;
 
@@ -3611,7 +3614,7 @@
 SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
                                 SDValue Src, SDValue Size,
                                 unsigned Align, bool isVol,
-                                const Value *DstSV, uint64_t DstSVOff) {
+                                MachinePointerInfo DstPtrInfo) {
 
   // Check to see if we should lower the memset to stores first.
   // For cases within the target-specified limits, this is the best choice.
@@ -3623,7 +3626,7 @@
 
     SDValue Result =
       getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
-                      Align, isVol, DstSV, DstSVOff);
+                      Align, isVol, DstPtrInfo);
 
     if (Result.getNode())
       return Result;
@@ -3633,7 +3636,7 @@
   // code. If the target chooses to do this, this is the next best.
   SDValue Result =
     TSI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, isVol,
-                                DstSV, DstSVOff);
+                                DstPtrInfo);
   if (Result.getNode())
     return Result;
 
@@ -3954,6 +3957,15 @@
                  SV, SVOffset, VT, isVolatile, isNonTemporal, Alignment);
 }
 
+SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
+                              SDValue Chain, SDValue Ptr,
+                              MachinePointerInfo PtrInfo,
+                              bool isVolatile, bool isNonTemporal,
+                              unsigned Alignment) {
+  SDValue Undef = getUNDEF(Ptr.getValueType());
+  return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
+                 PtrInfo, VT, isVolatile, isNonTemporal, Alignment);
+}
 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
                                  SDValue Chain, SDValue Ptr,
                                  const Value *SV,
@@ -3965,6 +3977,17 @@
                  SV, SVOffset, MemVT, isVolatile, isNonTemporal, Alignment);
 }
 
+SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
+                                 SDValue Chain, SDValue Ptr,
+                                 MachinePointerInfo PtrInfo, EVT MemVT,
+                                 bool isVolatile, bool isNonTemporal,
+                                 unsigned Alignment) {
+  SDValue Undef = getUNDEF(Ptr.getValueType());
+  return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
+                 PtrInfo, MemVT, isVolatile, isNonTemporal, Alignment);
+}
+
+
 SDValue
 SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
                              SDValue Offset, ISD::MemIndexedMode AM) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep 21 00:40:29 2010
@@ -4014,7 +4014,8 @@
     unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
     bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
     DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
-                              I.getArgOperand(0), 0, I.getArgOperand(1), 0));
+                              MachinePointerInfo(I.getArgOperand(0)),
+                              MachinePointerInfo(I.getArgOperand(1))));
     return 0;
   }
   case Intrinsic::memset: {
@@ -4029,7 +4030,7 @@
     unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
     bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
     DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
-                              I.getArgOperand(0), 0));
+                              MachinePointerInfo(I.getArgOperand(0))));
     return 0;
   }
   case Intrinsic::memmove: {
@@ -4054,13 +4055,14 @@
     if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) ==
         AliasAnalysis::NoAlias) {
       DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 
-                                false, I.getArgOperand(0), 0,
-                                I.getArgOperand(1), 0));
+                                false, MachinePointerInfo(I.getArgOperand(0)),
+                                MachinePointerInfo(I.getArgOperand(1))));
       return 0;
     }
 
     DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
-                               I.getArgOperand(0), 0, I.getArgOperand(1), 0));
+                               MachinePointerInfo(I.getArgOperand(0)),
+                               MachinePointerInfo(I.getArgOperand(1))));
     return 0;
   }
   case Intrinsic::dbg_declare: {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep 21 00:40:29 2010
@@ -928,7 +928,7 @@
   SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
   return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
                        /*isVolatile=*/false, /*AlwaysInline=*/false,
-                       NULL, 0, NULL, 0);
+                       MachinePointerInfo(0), MachinePointerInfo(0));
 }
 
 /// LowerMemOpCallTo - Store the argument to the stack.

Modified: llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp Tue Sep 21 00:40:29 2010
@@ -29,10 +29,8 @@
                                              SDValue Dst, SDValue Src,
                                              SDValue Size, unsigned Align,
                                              bool isVolatile, bool AlwaysInline,
-                                             const Value *DstSV,
-                                             uint64_t DstSVOff,
-                                             const Value *SrcSV,
-                                             uint64_t SrcSVOff) const {
+                                             MachinePointerInfo DstPtrInfo,
+                                          MachinePointerInfo SrcPtrInfo) const {
   // Do repeated 4-byte loads and stores. To be improved.
   // This requires 4-byte alignment.
   if ((Align & 3) != 0)
@@ -66,7 +64,8 @@
       Loads[i] = DAG.getLoad(VT, dl, Chain,
                              DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
                                          DAG.getConstant(SrcOff, MVT::i32)),
-                             SrcSV, SrcSVOff + SrcOff, isVolatile, false, 0);
+                             SrcPtrInfo.getWithOffset(SrcOff), isVolatile,
+                             false, 0);
       TFOps[i] = Loads[i].getValue(1);
       SrcOff += VTSize;
     }
@@ -77,7 +76,8 @@
       TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
                               DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
                                           DAG.getConstant(DstOff, MVT::i32)),
-                              DstSV, DstSVOff + DstOff, isVolatile, false, 0);
+                              DstPtrInfo.getWithOffset(DstOff),
+                              isVolatile, false, 0);
       DstOff += VTSize;
     }
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
@@ -103,7 +103,7 @@
     Loads[i] = DAG.getLoad(VT, dl, Chain,
                            DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
                                        DAG.getConstant(SrcOff, MVT::i32)),
-                           SrcSV, SrcSVOff + SrcOff, false, false, 0);
+                           SrcPtrInfo.getWithOffset(SrcOff), false, false, 0);
     TFOps[i] = Loads[i].getValue(1);
     ++i;
     SrcOff += VTSize;
@@ -125,7 +125,7 @@
     TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
                             DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
                                         DAG.getConstant(DstOff, MVT::i32)),
-                            DstSV, DstSVOff + DstOff, false, false, 0);
+                            DstPtrInfo.getWithOffset(DstOff), false, false, 0);
     ++i;
     DstOff += VTSize;
     BytesLeft -= VTSize;

Modified: llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h Tue Sep 21 00:40:29 2010
@@ -33,10 +33,8 @@
                                   SDValue Dst, SDValue Src,
                                   SDValue Size, unsigned Align,
                                   bool isVolatile, bool AlwaysInline,
-                                  const Value *DstSV,
-                                  uint64_t DstSVOff,
-                                  const Value *SrcSV,
-                                  uint64_t SrcSVOff) const;
+                                  MachinePointerInfo DstPtrInfo,
+                                  MachinePointerInfo SrcPtrInfo) const;
 };
 
 }

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 21 00:40:29 2010
@@ -2397,7 +2397,8 @@
                           DebugLoc dl) {
   SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
   return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
-                       false, false, NULL, 0, NULL, 0);
+                       false, false, MachinePointerInfo(0),
+                       MachinePointerInfo(0));
 }
 
 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 00:40:29 2010
@@ -1534,10 +1534,11 @@
 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
                           ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
                           DebugLoc dl) {
-  SDValue SizeNode     = DAG.getConstant(Flags.getByValSize(), MVT::i32);
+  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
+  
   return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
                        /*isVolatile*/false, /*AlwaysInline=*/true,
-                       NULL, 0, NULL, 0);
+                       MachinePointerInfo(0), MachinePointerInfo(0));
 }
 
 /// IsTailCallConvention - Return true if the calling convention is one that
@@ -7607,11 +7608,12 @@
   SDValue SrcPtr = Op.getOperand(2);
   const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
   const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
 
-  return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
+  return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
                        DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
-                       false, DstSV, 0, SrcSV, 0);
+                       false, 
+                       MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
 }
 
 SDValue

Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Tue Sep 21 00:40:29 2010
@@ -32,8 +32,7 @@
                                              SDValue Dst, SDValue Src,
                                              SDValue Size, unsigned Align,
                                              bool isVolatile,
-                                             const Value *DstSV,
-                                             uint64_t DstSVOff) const {
+                                         MachinePointerInfo DstPtrInfo) const {
   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
 
   // If not DWORD aligned or size is more than the threshold, call the library.
@@ -161,7 +160,7 @@
                                       DAG.getConstant(Offset, AddrVT)),
                           Src,
                           DAG.getConstant(BytesLeft, SizeVT),
-                          Align, isVolatile, DstSV, DstSVOff + Offset);
+                          Align, isVolatile, DstPtrInfo.getWithOffset(Offset));
   }
 
   // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
@@ -173,10 +172,8 @@
                                         SDValue Chain, SDValue Dst, SDValue Src,
                                         SDValue Size, unsigned Align,
                                         bool isVolatile, bool AlwaysInline,
-                                        const Value *DstSV,
-                                        uint64_t DstSVOff,
-                                        const Value *SrcSV,
-                                        uint64_t SrcSVOff) const {
+                                         MachinePointerInfo DstPtrInfo,
+                                         MachinePointerInfo SrcPtrInfo) const {
   // This requires the copy size to be a constant, preferrably
   // within a subtarget-specific limit.
   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -234,8 +231,8 @@
                                                 DAG.getConstant(Offset, SrcVT)),
                                     DAG.getConstant(BytesLeft, SizeVT),
                                     Align, isVolatile, AlwaysInline,
-                                    DstSV, DstSVOff + Offset,
-                                    SrcSV, SrcSVOff + Offset));
+                                    DstPtrInfo.getWithOffset(Offset),
+                                    SrcPtrInfo.getWithOffset(Offset)));
   }
 
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,

Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h Tue Sep 21 00:40:29 2010
@@ -39,8 +39,7 @@
                                   SDValue Dst, SDValue Src,
                                   SDValue Size, unsigned Align,
                                   bool isVolatile,
-                                  const Value *DstSV,
-                                  uint64_t DstSVOff) const;
+                                  MachinePointerInfo DstPtrInfo) const;
 
   virtual
   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
@@ -48,10 +47,8 @@
                                   SDValue Dst, SDValue Src,
                                   SDValue Size, unsigned Align,
                                   bool isVolatile, bool AlwaysInline,
-                                  const Value *DstSV,
-                                  uint64_t DstSVOff,
-                                  const Value *SrcSV,
-                                  uint64_t SrcSVOff) const;
+                                  MachinePointerInfo DstPtrInfo,
+                                  MachinePointerInfo SrcPtrInfo) const;
 };
 
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=114401&r1=114400&r2=114401&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep 21 00:40:29 2010
@@ -1443,9 +1443,8 @@
         return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
                               LD->getBasePtr(),
                               DAG.getConstant(StoreBits/8, MVT::i32),
-                              Alignment, false, ST->getSrcValue(),
-                              ST->getSrcValueOffset(), LD->getSrcValue(),
-                              LD->getSrcValueOffset());
+                              Alignment, false, ST->getPointerInfo(),
+                              LD->getPointerInfo());
       }
     }
     break;



From sabre at nondot.org  Tue Sep 21 00:43:35 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 05:43:35 -0000
Subject: [llvm-commits] [llvm] r114402 -
	/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
Message-ID: <20100921054335.171862A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 00:43:34 2010
New Revision: 114402

URL: http://llvm.org/viewvc/llvm-project?rev=114402&view=rev
Log:
Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations
into non-segment-relative copies.

Modified:
    llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=114402&r1=114401&r2=114402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Tue Sep 21 00:43:34 2010
@@ -35,6 +35,10 @@
                                          MachinePointerInfo DstPtrInfo) const {
   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
 
+  // If to a segment-relative address space, use the default lowering.
+  if (DstPtrInfo.getAddrSpace() >= 256)
+    return SDValue();
+  
   // If not DWORD aligned or size is more than the threshold, call the library.
   // The libc version is likely to be faster for these cases. It can use the
   // address value and run time information about the CPU.
@@ -187,6 +191,11 @@
   if ((Align & 3) != 0)
     return SDValue();
 
+  // If to a segment-relative address space, use the default lowering.
+  if (DstPtrInfo.getAddrSpace() >= 256 ||
+      SrcPtrInfo.getAddrSpace() >= 256)
+    return SDValue();
+  
   // DWORD aligned
   EVT AVT = MVT::i32;
   if (Subtarget->is64Bit() && ((Align & 0x7) == 0))  // QWORD aligned



From sabre at nondot.org  Tue Sep 21 01:02:19 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 06:02:19 -0000
Subject: [llvm-commits] [llvm] r114404 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100921060219.BAA062A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 01:02:19 2010
New Revision: 114404

URL: http://llvm.org/viewvc/llvm-project?rev=114404&view=rev
Log:
update the X86 backend to use the MachinePointerInfo version of one
of the getLoad methods.  This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114404&r1=114403&r2=114404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 01:02:19 2010
@@ -1587,7 +1587,7 @@
                                     VA.getLocMemOffset(), isImmutable);
     SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
     return DAG.getLoad(ValVT, dl, Chain, FIN,
-                       PseudoSourceValue::getFixedStack(FI), 0,
+                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
                        false, false, 0);
   }
 }
@@ -1684,8 +1684,8 @@
 
     // If value is passed via pointer - do a load.
     if (VA.getLocInfo() == CCValAssign::Indirect)
-      ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
-                             false, false, 0);
+      ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
+                             MachinePointerInfo(), false, false, 0);
 
     InVals.push_back(ArgValue);
   }
@@ -1871,7 +1871,8 @@
   OutRetAddr = getReturnAddressFrameIndex(DAG);
 
   // Load the "old" Return address.
-  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
+  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
+                           false, false, 0);
   return SDValue(OutRetAddr.getNode(), 1);
 }
 
@@ -4089,13 +4090,14 @@
     int EltNo = (Offset - StartOffset) >> 2;
     int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
     EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
-    SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
+    SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
+                             LD->getPointerInfo().getWithOffset(StartOffset),
                              false, false, 0);
     // Canonicalize it to a v4i32 shuffle.
     V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
     return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
                        DAG.getVectorShuffle(MVT::v4i32, dl, V1,
-                                            DAG.getUNDEF(MVT::v4i32), &Mask[0]));
+                                            DAG.getUNDEF(MVT::v4i32),&Mask[0]));
   }
 
   return SDValue();
@@ -4149,10 +4151,10 @@
   if (LastLoadedElt == NumElems - 1) {
     if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
       return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
-                         LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
+                         LDBase->getPointerInfo(),
                          LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
     return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
-                       LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
+                       LDBase->getPointerInfo(),
                        LDBase->isVolatile(), LDBase->isNonTemporal(),
                        LDBase->getAlignment());
   } else if (NumElems == 4 && LastLoadedElt == 1) {
@@ -6074,7 +6076,8 @@
   // load.
   if (isGlobalStubReference(OpFlags))
     Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
-                         PseudoSourceValue::getGOT(), 0, false, false, 0);
+                         MachinePointerInfo(PseudoSourceValue::getGOT()),
+                         false, false, 0);
 
   // If there was a non-zero offset that we didn't fold, create an explicit
   // addition for it.
@@ -6153,7 +6156,7 @@
                                              MVT::i32));
 
   SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
-                                      NULL, 0, false, false, 0);
+                                      MachinePointerInfo(), false, false, 0);
 
   unsigned char OperandFlags = 0;
   // Most TLS accesses are not RIP relative, even on x86-64.  One exception is
@@ -6179,7 +6182,8 @@
 
   if (model == TLSModel::InitialExec)
     Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
-                         PseudoSourceValue::getGOT(), 0, false, false, 0);
+                         MachinePointerInfo(PseudoSourceValue::getGOT()),
+                         false, false, 0);
 
   // The address of the thread local variable is the add of the thread
   // pointer with the offset of the variable.
@@ -6378,7 +6382,7 @@
     };
     Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
     Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
-                         PseudoSourceValue::getFixedStack(SSFI), 0,
+                     MachinePointerInfo(PseudoSourceValue::getFixedStack(SSFI)),
                          false, false, 0);
   }
 
@@ -6452,12 +6456,12 @@
                                         DAG.getIntPtrConstant(0)));
   SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
   SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
-                              PseudoSourceValue::getConstantPool(), 0,
+                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                               false, false, 16);
   SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
   SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
   SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
-                              PseudoSourceValue::getConstantPool(), 0,
+                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                               false, false, 16);
   SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
 
@@ -6670,7 +6674,7 @@
 
   // Load the result.
   return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
-                     FIST, StackSlot, NULL, 0, false, false, 0);
+                     FIST, StackSlot, MachinePointerInfo(), false, false, 0);
 }
 
 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
@@ -6681,7 +6685,7 @@
 
   // Load the result.
   return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
-                     FIST, StackSlot, NULL, 0, false, false, 0);
+                     FIST, StackSlot, MachinePointerInfo(), false, false, 0);
 }
 
 SDValue X86TargetLowering::LowerFABS(SDValue Op,
@@ -6707,7 +6711,7 @@
   Constant *C = ConstantVector::get(CV);
   SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                             PseudoSourceValue::getConstantPool(), 0,
+                     MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                              false, false, 16);
   return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
 }
@@ -6734,7 +6738,7 @@
   Constant *C = ConstantVector::get(CV);
   SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                             PseudoSourceValue::getConstantPool(), 0,
+                   MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                              false, false, 16);
   if (VT.isVector()) {
     return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
@@ -6783,7 +6787,7 @@
   Constant *C = ConstantVector::get(CV);
   SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
-                              PseudoSourceValue::getConstantPool(), 0,
+                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                               false, false, 16);
   SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
 
@@ -6812,7 +6816,7 @@
   C = ConstantVector::get(CV);
   CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                              PseudoSourceValue::getConstantPool(), 0,
+                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                               false, false, 16);
   SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
 
@@ -7909,13 +7913,13 @@
     return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
                        DAG.getNode(ISD::ADD, dl, getPointerTy(),
                                    FrameAddr, Offset),
-                       NULL, 0, false, false, 0);
+                       MachinePointerInfo(), false, false, 0);
   }
 
   // Just load the return address.
   SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
   return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
-                     RetAddrFI, NULL, 0, false, false, 0);
+                     RetAddrFI, MachinePointerInfo(), false, false, 0);
 }
 
 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
@@ -7928,7 +7932,8 @@
   unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
   while (Depth--)
-    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
+    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
+                            MachinePointerInfo(),
                             false, false, 0);
   return FrameAddr;
 }
@@ -8141,8 +8146,8 @@
                               DAG.getEntryNode(), StackSlot);
 
   // Load FP Control Word from stack slot
-  SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
-                            false, false, 0);
+  SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot,
+                            MachinePointerInfo(), false, false, 0);
 
   // Transform as necessary
   SDValue CWD1 =
@@ -8296,7 +8301,7 @@
     Constant *C = ConstantVector::get(CV);
     SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
     SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                                 PseudoSourceValue::getConstantPool(), 0,
+                   MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                                  false, false, 16);
 
     Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
@@ -8318,7 +8323,7 @@
     Constant *C = ConstantVector::get(CVM1);
     SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
     SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                            PseudoSourceValue::getConstantPool(), 0,
+                       MachinePointerInfo(PseudoSourceValue::getConstantPool()),
                             false, false, 16);
 
     // r = pblendv(r, psllw(r & (char16)15, 4), a);
@@ -8335,7 +8340,8 @@
     C = ConstantVector::get(CVM2);
     CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
     M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                    PseudoSourceValue::getConstantPool(), 0, false, false, 16);
+                    MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                    false, false, 16);
     
     // r = pblendv(r, psllw(r & (char16)63, 2), a);
     M = DAG.getNode(ISD::AND, dl, VT, R, M);
@@ -8654,8 +8660,8 @@
     if (FIST.getNode() != 0) {
       EVT VT = N->getValueType(0);
       // Return a load from the stack slot.
-      Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
-                                    false, false, 0));
+      Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
+                                    MachinePointerInfo(), false, false, 0));
     }
     return;
   }
@@ -10063,11 +10069,12 @@
     SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
 
     SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
-                                     OffsetVal, StackPtr);
+                                     StackPtr, OffsetVal);
 
     // Load the scalar.
     SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
-                                     ScalarAddr, NULL, 0, false, false, 0);
+                                     ScalarAddr, MachinePointerInfo(),
+                                     false, false, 0);
 
     // Replace the exact with the load.
     DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
@@ -10770,9 +10777,8 @@
     // pair instead.
     if (Subtarget->is64Bit() || F64IsLegal) {
       EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
-      SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
-                                  Ld->getBasePtr(), Ld->getSrcValue(),
-                                  Ld->getSrcValueOffset(), Ld->isVolatile(),
+      SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
+                                  Ld->getPointerInfo(), Ld->isVolatile(),
                                   Ld->isNonTemporal(), Ld->getAlignment());
       SDValue NewChain = NewLd.getValue(1);
       if (TokenFactorIndex != -1) {
@@ -10781,7 +10787,7 @@
                                Ops.size());
       }
       return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
-                          St->getSrcValue(), St->getSrcValueOffset(),
+                          St->getPointerInfo(),
                           St->isVolatile(), St->isNonTemporal(),
                           St->getAlignment());
     }
@@ -10792,11 +10798,11 @@
                                  DAG.getConstant(4, MVT::i32));
 
     SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
-                               Ld->getSrcValue(), Ld->getSrcValueOffset(),
+                               Ld->getPointerInfo(),
                                Ld->isVolatile(), Ld->isNonTemporal(),
                                Ld->getAlignment());
     SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
-                               Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
+                               Ld->getPointerInfo().getWithOffset(4),
                                Ld->isVolatile(), Ld->isNonTemporal(),
                                MinAlign(Ld->getAlignment(), 4));
 



From sabre at nondot.org  Tue Sep 21 01:16:40 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 06:16:40 -0000
Subject: [llvm-commits] [llvm] r114405 -
	/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
Message-ID: <20100921061640.4EEEA2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 01:16:40 2010
New Revision: 114405

URL: http://llvm.org/viewvc/llvm-project?rev=114405&view=rev
Log:
ugh, missed a file.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114405&r1=114404&r2=114405&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Tue Sep 21 01:16:40 2010
@@ -37,7 +37,7 @@
   /// Offset - This is an offset from the base Value*.
   int64_t Offset;
   
-  explicit MachinePointerInfo(const Value *v, int64_t offset = 0)
+  explicit MachinePointerInfo(const Value *v = 0, int64_t offset = 0)
     : V(v), Offset(offset) {}
   
   MachinePointerInfo getWithOffset(int64_t O) const {



From sabre at nondot.org  Tue Sep 21 01:22:23 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 06:22:23 -0000
Subject: [llvm-commits] [llvm] r114406 - in /llvm/trunk:
 include/llvm/CodeGen/MachineMemOperand.h lib/CodeGen/MachineInstr.cpp
 lib/Target/CellSPU/SPUISelDAGToDAG.cpp
 lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86InstrBuilder.h
Message-ID: <20100921062223.D0D842A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 01:22:23 2010
New Revision: 114406

URL: http://llvm.org/viewvc/llvm-project?rev=114406&view=rev
Log:
it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114406&r1=114405&r2=114406&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Tue Sep 21 01:22:23 2010
@@ -48,6 +48,14 @@
   /// getAddrSpace - Return the LLVM IR address space number that this pointer
   /// points into.
   unsigned getAddrSpace() const;
+  
+  /// getConstantPool - Return a MachinePointerInfo record that refers to the
+  /// constant pool.
+  static MachinePointerInfo getConstantPool();
+
+  /// getFixedStack - Return a MachinePointerInfo record that refers to the
+  /// the specified FrameIndex.
+  static MachinePointerInfo getFixedStack(int FI, int64_t offset = 0);
 };
   
   

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=114406&r1=114405&r2=114406&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Sep 21 01:22:23 2010
@@ -342,6 +342,18 @@
   return cast<PointerType>(V->getType())->getAddressSpace();
 }
 
+/// getConstantPool - Return a MachinePointerInfo record that refers to the
+/// constant pool.
+MachinePointerInfo MachinePointerInfo::getConstantPool() {
+  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
+}
+
+/// getFixedStack - Return a MachinePointerInfo record that refers to the
+/// the specified FrameIndex.
+MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
+  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
+}
+
 
 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
                                      uint64_t s, unsigned int a)

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=114406&r1=114405&r2=114406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Tue Sep 21 01:22:23 2010
@@ -265,7 +265,7 @@
       
       HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
                                          CurDAG->getEntryNode(), CGPoolOffset,
-                                         PseudoSourceValue::getConstantPool(),0,
+                                         MachinePointerInfo::getConstantPool(),
                                          false, false, Alignment));
       CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
       if (SDNode *N = SelectCode(Dummy.getValue().getNode()))

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=114406&r1=114405&r2=114406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Sep 21 01:22:23 2010
@@ -662,7 +662,7 @@
 
     // Re-emit as a v16i8 vector load
     result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
-                         LN->getSrcValue(), LN->getSrcValueOffset(),
+                         LN->getPointerInfo(),
                          LN->isVolatile(), LN->isNonTemporal(), 16);
 
     // Update the chain
@@ -812,7 +812,7 @@
 
     // Load the memory to which to store.
     alignLoadVec = DAG.getLoad(vecVT, dl, the_chain, basePtr,
-                               SN->getSrcValue(), SN->getSrcValueOffset(),
+                               SN->getPointerInfo(),
                                SN->isVolatile(), SN->isNonTemporal(), 16);
 
     // Update the chain
@@ -1080,7 +1080,8 @@
       // or we're forced to do vararg
       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
-      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, false, false, 0);
+      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
+                           false, false, 0);
       ArgOffset += StackSlotSize;
     }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114406&r1=114405&r2=114406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 01:22:23 2010
@@ -1587,7 +1587,7 @@
                                     VA.getLocMemOffset(), isImmutable);
     SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
     return DAG.getLoad(ValVT, dl, Chain, FIN,
-                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                       MachinePointerInfo::getFixedStack(FI),
                        false, false, 0);
   }
 }
@@ -1781,9 +1781,9 @@
         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
         SDValue Store =
           DAG.getStore(Val.getValue(1), dl, Val, FIN,
-                       PseudoSourceValue::getFixedStack(
-                         FuncInfo->getRegSaveFrameIndex()),
-                       Offset, false, false, 0);
+                       MachinePointerInfo::getFixedStack(
+                         FuncInfo->getRegSaveFrameIndex(), Offset),
+                       false, false, 0);
         MemOps.push_back(Store);
         Offset += 8;
       }
@@ -1891,7 +1891,7 @@
   EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
   SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
   Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
-                       PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
+                       MachinePointerInfo::getFixedStack(NewReturnAddrFI),
                        false, false, 0);
   return Chain;
 }
@@ -2005,7 +2005,7 @@
       SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
       int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
       Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
-                           PseudoSourceValue::getFixedStack(FI), 0,
+                           MachinePointerInfo::getFixedStack(FI),
                            false, false, 0);
       Arg = SpillSlot;
       break;
@@ -2148,7 +2148,7 @@
           // Store relative to framepointer.
           MemOpChains2.push_back(
             DAG.getStore(ArgChain, dl, Arg, FIN,
-                         PseudoSourceValue::getFixedStack(FI), 0,
+                         MachinePointerInfo::getFixedStack(FI),
                          false, false, 0));
         }
       }
@@ -6346,7 +6346,7 @@
   SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
   SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
                                StackSlot,
-                               PseudoSourceValue::getFixedStack(SSFI), 0,
+                               MachinePointerInfo::getFixedStack(SSFI),
                                false, false, 0);
   return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
 }
@@ -6382,7 +6382,7 @@
     };
     Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
     Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
-                     MachinePointerInfo(PseudoSourceValue::getFixedStack(SSFI)),
+                         MachinePointerInfo::getFixedStack(SSFI),
                          false, false, 0);
   }
 
@@ -6456,12 +6456,12 @@
                                         DAG.getIntPtrConstant(0)));
   SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
   SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
-                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                              MachinePointerInfo::getConstantPool(),
                               false, false, 16);
   SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
   SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
   SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
-                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                              MachinePointerInfo::getConstantPool(),
                               false, false, 16);
   SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
 
@@ -6587,8 +6587,8 @@
   // Load the value out, extending it from f32 to f80.
   // FIXME: Avoid the extend by constructing the right constant pool?
   SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
-                                 FudgePtr, PseudoSourceValue::getConstantPool(),
-                                 0, MVT::f32, false, false, 4);
+                                 FudgePtr, MachinePointerInfo::getConstantPool(),
+                                 MVT::f32, false, false, 4);
   // Extend everything to 80 bits to force it to be done on x87.
   SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
   return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
@@ -6638,7 +6638,7 @@
   if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
     assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
     Chain = DAG.getStore(Chain, dl, Value, StackSlot,
-                         PseudoSourceValue::getFixedStack(SSFI), 0,
+                         MachinePointerInfo::getFixedStack(SSFI),
                          false, false, 0);
     SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
     SDValue Ops[] = {
@@ -6711,7 +6711,7 @@
   Constant *C = ConstantVector::get(CV);
   SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                     MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                             MachinePointerInfo::getConstantPool(),
                              false, false, 16);
   return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
 }
@@ -6738,7 +6738,7 @@
   Constant *C = ConstantVector::get(CV);
   SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                   MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                             MachinePointerInfo::getConstantPool(),
                              false, false, 16);
   if (VT.isVector()) {
     return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
@@ -6787,7 +6787,7 @@
   Constant *C = ConstantVector::get(CV);
   SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
-                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                              MachinePointerInfo::getConstantPool(),
                               false, false, 16);
   SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
 
@@ -6816,7 +6816,7 @@
   C = ConstantVector::get(CV);
   CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
   SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                      MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                              MachinePointerInfo::getConstantPool(),
                               false, false, 16);
   SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
 
@@ -8301,7 +8301,7 @@
     Constant *C = ConstantVector::get(CV);
     SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
     SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                   MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                                 MachinePointerInfo::getConstantPool(),
                                  false, false, 16);
 
     Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
@@ -8323,7 +8323,7 @@
     Constant *C = ConstantVector::get(CVM1);
     SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
     SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                       MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                            MachinePointerInfo::getConstantPool(),
                             false, false, 16);
 
     // r = pblendv(r, psllw(r & (char16)15, 4), a);
@@ -8340,7 +8340,7 @@
     C = ConstantVector::get(CVM2);
     CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
     M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                    MachinePointerInfo(PseudoSourceValue::getConstantPool()),
+                    MachinePointerInfo::getConstantPool(),
                     false, false, 16);
     
     // r = pblendv(r, psllw(r & (char16)63, 2), a);
@@ -9471,8 +9471,7 @@
     int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
     MachineMemOperand *MMO =
       F->getMachineMemOperand(
-        MachinePointerInfo(PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
-                           Offset),
+          MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
         MachineMemOperand::MOStore,
         /*Size=*/16, /*Align=*/16);
     BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=114406&r1=114405&r2=114406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Sep 21 01:22:23 2010
@@ -157,8 +157,7 @@
   if (TID.mayStore())
     Flags |= MachineMemOperand::MOStore;
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(
-                                 PseudoSourceValue::getFixedStack(FI), Offset),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI, Offset),
                             Flags, MFI.getObjectSize(FI),
                             MFI.getObjectAlignment(FI));
   return addOffset(MIB.addFrameIndex(FI), Offset)



From sabre at nondot.org  Tue Sep 21 01:43:24 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 06:43:24 -0000
Subject: [llvm-commits] [llvm] r114409 - in /llvm/trunk:
 include/llvm/CodeGen/MachineMemOperand.h lib/CodeGen/MachineInstr.cpp
Message-ID: <20100921064324.DABF72A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 01:43:24 2010
New Revision: 114409

URL: http://llvm.org/viewvc/llvm-project?rev=114409&view=rev
Log:
add some accessors

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114409&r1=114408&r2=114409&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Tue Sep 21 01:43:24 2010
@@ -56,6 +56,14 @@
   /// getFixedStack - Return a MachinePointerInfo record that refers to the
   /// the specified FrameIndex.
   static MachinePointerInfo getFixedStack(int FI, int64_t offset = 0);
+  
+  /// getJumpTable - Return a MachinePointerInfo record that refers to a
+  /// jump table entry.
+  static MachinePointerInfo getJumpTable();
+  
+  /// getGOT - Return a MachinePointerInfo record that refers to a
+  /// GOT entry.
+  static MachinePointerInfo getGOT();
 };
   
   

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=114409&r1=114408&r2=114409&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Sep 21 01:43:24 2010
@@ -354,6 +354,13 @@
   return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
 }
 
+MachinePointerInfo MachinePointerInfo::getJumpTable() {
+  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
+}
+
+MachinePointerInfo MachinePointerInfo::getGOT() {
+  return MachinePointerInfo(PseudoSourceValue::getGOT());
+}
 
 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
                                      uint64_t s, unsigned int a)



From sabre at nondot.org  Tue Sep 21 01:44:06 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 06:44:06 -0000
Subject: [llvm-commits] [llvm] r114410 - in /llvm/trunk/lib/Target:
 ARM/ARMISelLowering.cpp Alpha/AlphaISelLowering.cpp
 Blackfin/BlackfinISelLowering.cpp MBlaze/MBlazeISelLowering.cpp
 MSP430/MSP430ISelLowering.cpp Mips/MipsISelLowering.cpp
 PowerPC/PPCISelLowering.cpp Sparc/SparcISelLowering.cpp
 SystemZ/SystemZISelLowering.cpp X86/X86ISelLowering.cpp
 XCore/XCoreISelLowering.cpp
Message-ID: <20100921064406.A3D8A2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 01:44:06 2010
New Revision: 114410

URL: http://llvm.org/viewvc/llvm-project?rev=114410&view=rev
Log:
convert the targets off the non-MachinePointerInfo of getLoad.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -1153,7 +1153,7 @@
       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
       Callee = DAG.getLoad(getPointerTy(), dl,
                            DAG.getEntryNode(), CPAddr,
-                           PseudoSourceValue::getConstantPool(), 0,
+                           MachinePointerInfo::getConstantPool(),
                            false, false, 0);
     } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
       const char *Sym = S->getSymbol();
@@ -1167,7 +1167,7 @@
       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
       Callee = DAG.getLoad(getPointerTy(), dl,
                            DAG.getEntryNode(), CPAddr,
-                           PseudoSourceValue::getConstantPool(), 0,
+                           MachinePointerInfo::getConstantPool(),
                            false, false, 0);
     }
   } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
@@ -1189,7 +1189,7 @@
       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
       Callee = DAG.getLoad(getPointerTy(), dl,
                            DAG.getEntryNode(), CPAddr,
-                           PseudoSourceValue::getConstantPool(), 0,
+                           MachinePointerInfo::getConstantPool(),
                            false, false, 0);
       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
       Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
@@ -1211,7 +1211,7 @@
       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
       Callee = DAG.getLoad(getPointerTy(), dl,
                            DAG.getEntryNode(), CPAddr,
-                           PseudoSourceValue::getConstantPool(), 0,
+                           MachinePointerInfo::getConstantPool(),
                            false, false, 0);
       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
       Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
@@ -1595,7 +1595,7 @@
   }
   CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
   SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
-                               PseudoSourceValue::getConstantPool(), 0,
+                               MachinePointerInfo::getConstantPool(),
                                false, false, 0);
   if (RelocM == Reloc::Static)
     return Result;
@@ -1619,7 +1619,7 @@
   SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
   Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
   Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
-                         PseudoSourceValue::getConstantPool(), 0,
+                         MachinePointerInfo::getConstantPool(),
                          false, false, 0);
   SDValue Chain = Argument.getValue(1);
 
@@ -1666,7 +1666,7 @@
     Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
     Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
     Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
-                         PseudoSourceValue::getConstantPool(), 0,
+                         MachinePointerInfo::getConstantPool(),
                          false, false, 0);
     Chain = Offset.getValue(1);
 
@@ -1674,7 +1674,7 @@
     Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
 
     Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
-                         PseudoSourceValue::getConstantPool(), 0,
+                         MachinePointerInfo::getConstantPool(),
                          false, false, 0);
   } else {
     // local exec model
@@ -1682,7 +1682,7 @@
     Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
     Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
     Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
-                         PseudoSourceValue::getConstantPool(), 0,
+                         MachinePointerInfo::getConstantPool(),
                          false, false, 0);
   }
 
@@ -1719,15 +1719,14 @@
     CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
     SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
                                  CPAddr,
-                                 PseudoSourceValue::getConstantPool(), 0,
+                                 MachinePointerInfo::getConstantPool(),
                                  false, false, 0);
     SDValue Chain = Result.getValue(1);
     SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
     Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
     if (!UseGOTOFF)
       Result = DAG.getLoad(PtrVT, dl, Chain, Result,
-                           PseudoSourceValue::getGOT(), 0,
-                           false, false, 0);
+                           MachinePointerInfo::getGOT(), false, false, 0);
     return Result;
   } else {
     // If we have T2 ops, we can materialize the address directly via movt/movw
@@ -1739,7 +1738,7 @@
       SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
       return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
-                         PseudoSourceValue::getConstantPool(), 0,
+                         MachinePointerInfo::getConstantPool(),
                          false, false, 0);
     }
   }
@@ -1767,7 +1766,7 @@
   CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
 
   SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
-                               PseudoSourceValue::getConstantPool(), 0,
+                               MachinePointerInfo::getConstantPool(),
                                false, false, 0);
   SDValue Chain = Result.getValue(1);
 
@@ -1777,8 +1776,7 @@
   }
 
   if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
-    Result = DAG.getLoad(PtrVT, dl, Chain, Result,
-                         PseudoSourceValue::getGOT(), 0,
+    Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
                          false, false, 0);
 
   return Result;
@@ -1800,7 +1798,7 @@
   SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
   CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
   SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
-                               PseudoSourceValue::getConstantPool(), 0,
+                               MachinePointerInfo::getConstantPool(),
                                false, false, 0);
   SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
   return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
@@ -1849,7 +1847,7 @@
     CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
     SDValue Result =
       DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
-                  PseudoSourceValue::getConstantPool(), 0,
+                  MachinePointerInfo::getConstantPool(),
                   false, false, 0);
 
     if (RelocM == Reloc::PIC_) {
@@ -1920,7 +1918,7 @@
     // Create load node to retrieve arguments from the stack.
     SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
     ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
-                            PseudoSourceValue::getFixedStack(FI), 0,
+                            MachinePointerInfo::getFixedStack(FI),
                             false, false, 0);
   } else {
     Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
@@ -1974,7 +1972,7 @@
             int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
             SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
             ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
-                                    PseudoSourceValue::getFixedStack(FI), 0,
+                                    MachinePointerInfo::getFixedStack(FI),
                                     false, false, 0);
           } else {
             ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
@@ -2043,7 +2041,7 @@
       // Create load nodes to retrieve arguments from the stack.
       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
-                                   PseudoSourceValue::getFixedStack(FI), 0,
+                                   MachinePointerInfo::getFixedStack(FI),
                                    false, false, 0));
     }
   }
@@ -2299,8 +2297,7 @@
 
   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
     return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
-                       Ld->getChain(), Ld->getBasePtr(),
-                       Ld->getSrcValue(), Ld->getSrcValueOffset(),
+                       Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
                        Ld->isVolatile(), Ld->isNonTemporal(),
                        Ld->getAlignment());
 
@@ -2319,7 +2316,7 @@
     SDValue Ptr = Ld->getBasePtr();
     RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
                           Ld->getChain(), Ptr,
-                          Ld->getSrcValue(), Ld->getSrcValueOffset(),
+                          Ld->getPointerInfo(),
                           Ld->isVolatile(), Ld->isNonTemporal(),
                           Ld->getAlignment());
 
@@ -2329,7 +2326,7 @@
                                  PtrType, Ptr, DAG.getConstant(4, PtrType));
     RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
                           Ld->getChain(), NewPtr,
-                          Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
+                          Ld->getPointerInfo().getWithOffset(4),
                           Ld->isVolatile(), Ld->isNonTemporal(),
                           NewAlign);
     return;
@@ -2454,14 +2451,14 @@
   }
   if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
     Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
-                       PseudoSourceValue::getJumpTable(), 0,
+                       MachinePointerInfo::getJumpTable(),
                        false, false, 0);
     Chain = Addr.getValue(1);
     Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
     return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
   } else {
     Addr = DAG.getLoad(PTy, dl, Chain, Addr,
-                       PseudoSourceValue::getJumpTable(), 0, false, false, 0);
+                       MachinePointerInfo::getJumpTable(), false, false, 0);
     Chain = Addr.getValue(1);
     return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
   }
@@ -2533,7 +2530,7 @@
     SDValue Offset = DAG.getConstant(4, MVT::i32);
     return DAG.getLoad(VT, dl, DAG.getEntryNode(),
                        DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
-                       NULL, 0, false, false, 0);
+                       MachinePointerInfo(), false, false, 0);
   }
 
   // Return LR, which contains the return address. Mark it an implicit live-in.
@@ -2552,7 +2549,8 @@
     ? ARM::R7 : ARM::R11;
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
   while (Depth--)
-    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
+    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
+                            MachinePointerInfo(),
                             false, false, 0);
   return FrameAddr;
 }
@@ -3618,8 +3616,7 @@
     return N->getOperand(0);
   LoadSDNode *LD = cast<LoadSDNode>(N);
   return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
-                     LD->getBasePtr(), LD->getSrcValue(),
-                     LD->getSrcValueOffset(), LD->isVolatile(),
+                     LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
                      LD->isNonTemporal(), LD->getAlignment());
 }
 

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -431,7 +431,7 @@
       // Create the SelectionDAG nodes corresponding to a load
       //from this parameter
       SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
-      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
+      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
                            false, false, 0);
     }
     InVals.push_back(ArgVal);
@@ -537,7 +537,8 @@
   const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
   DebugLoc dl = N->getDebugLoc();
 
-  SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0,
+  SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP,
+                             MachinePointerInfo(VAListS),
                              false, false, 0);
   SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
                               DAG.getConstant(8, MVT::i64));
@@ -709,7 +710,8 @@
       Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Chain, DataPtr,
                               NULL, 0, MVT::i32, false, false, 0);
     else
-      Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0,
+      Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr,
+                           MachinePointerInfo(),
                            false, false, 0);
     return Result;
   }
@@ -720,7 +722,8 @@
     const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
     const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
 
-    SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0,
+    SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP,
+                              MachinePointerInfo(SrcS),
                               false, false, 0);
     SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0,
                                   false, false, 0);
@@ -771,7 +774,8 @@
 
   SDValue Chain, DataPtr;
   LowerVAARG(N, Chain, DataPtr, DAG);
-  SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0,
+  SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, 
+                            MachinePointerInfo(),
                             false, false, 0);
   Results.push_back(Res);
   Results.push_back(SDValue(Res.getNode(), 1));

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -207,7 +207,8 @@
       unsigned ObjSize = VA.getLocVT().getStoreSize();
       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
-      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
+      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
+                                   MachinePointerInfo(),
                                    false, false, 0));
     }
   }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -780,7 +780,8 @@
 
       // Create load nodes to retrieve arguments from the stack
       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
-      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
+      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
+                                   MachinePointerInfo::getFixedStack(FI),
                                    false, false, 0));
     }
   }

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -376,7 +376,7 @@
       //from this parameter
       SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
       InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
-                                   PseudoSourceValue::getFixedStack(FI), 0,
+                                   MachinePointerInfo::getFixedStack(FI),
                                    false, false, 0));
     }
   }
@@ -914,13 +914,13 @@
     return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
                        DAG.getNode(ISD::ADD, dl, getPointerTy(),
                                    FrameAddr, Offset),
-                       NULL, 0, false, false, 0);
+                       MachinePointerInfo(), false, false, 0);
   }
 
   // Just load the return address.
   SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
   return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
-                     RetAddrFI, NULL, 0, false, false, 0);
+                     RetAddrFI, MachinePointerInfo(), false, false, 0);
 }
 
 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
@@ -934,7 +934,8 @@
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
                                          MSP430::FPW, VT);
   while (Depth--)
-    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
+    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
+                            MachinePointerInfo(),
                             false, false, 0);
   return FrameAddr;
 }

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -506,7 +506,7 @@
     SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
                                             MipsII::MO_GOT);
     SDValue ResNode = DAG.getLoad(MVT::i32, dl, 
-                                  DAG.getEntryNode(), GA, NULL, 0,
+                                  DAG.getEntryNode(), GA, MachinePointerInfo(),
                                   false, false, 0);
     // On functions and global targets not internal linked only
     // a load from got/GP is necessary for PIC to work.
@@ -546,7 +546,8 @@
     SDValue Ops[] = { JTI };
     HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
   } else // Emit Load from Global Pointer
-    HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0,
+    HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
+                         MachinePointerInfo(),
                          false, false, 0);
 
   SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
@@ -584,7 +585,8 @@
     SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 
                                       N->getOffset(), MipsII::MO_GOT);
     SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 
-                               CP, NULL, 0, false, false, 0);
+                               CP, MachinePointerInfo::getConstantPool(),
+                               false, false, 0);
     SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
     ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
   }
@@ -937,8 +939,9 @@
 
       // Reload GP value.
       FI = MipsFI->getGPFI();
-      SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
-      SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0,
+      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
+      SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
+                                   MachinePointerInfo::getFixedStack(FI),
                                    false, false, 0);
       Chain = GPLoad.getValue(1);
       Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32), 
@@ -1104,7 +1107,8 @@
 
       // Create load nodes to retrieve arguments from the stack
       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
-      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
+      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
+                                   MachinePointerInfo::getFixedStack(FI),
                                    false, false, 0));
     }
   }

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -1244,7 +1244,7 @@
 
   // If the global is weak or external, we have to go through the lazy
   // resolution stub.
-  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0,
+  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, MachinePointerInfo(),
                      false, false, 0);
 }
 
@@ -1635,7 +1635,8 @@
 
       // Create load nodes to retrieve arguments from the stack.
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
-      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
+      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
+                                   MachinePointerInfo(),
                                    false, false, 0));
     }
   }
@@ -2063,7 +2064,7 @@
                                       CurArgOffset + (ArgSize - ObjSize),
                                       isImmutable);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
-      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
+      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
                            false, false, 0);
     }
 
@@ -2292,8 +2293,8 @@
     int FI = TailCallArgs[i].FrameIdx;
     // Store relative to framepointer.
     MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
-                                       PseudoSourceValue::getFixedStack(FI),
-                                       0, false, false, 0));
+                                       MachinePointerInfo::getFixedStack(FI),
+                                       false, false, 0));
   }
 }
 
@@ -2318,7 +2319,7 @@
     EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
     SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
     Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
-                         PseudoSourceValue::getFixedStack(NewRetAddr), 0,
+                         MachinePointerInfo::getFixedStack(NewRetAddr),
                          false, false, 0);
 
     // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
@@ -2330,7 +2331,7 @@
                                                           true);
       SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
       Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
-                           PseudoSourceValue::getFixedStack(NewFPIdx), 0,
+                           MachinePointerInfo::getFixedStack(NewFPIdx),
                            false, false, 0);
     }
   }
@@ -2369,7 +2370,7 @@
     // Load the LR and FP stack slot for later adjusting.
     EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
     LROpOut = getReturnAddrFrameIndex(DAG);
-    LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0,
+    LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
                           false, false, 0);
     Chain = SDValue(LROpOut.getNode(), 1);
     
@@ -2377,7 +2378,7 @@
     // slot as the FP is never overwritten.
     if (isDarwinABI) {
       FPOpOut = getFramePointerFrameIndex(DAG);
-      FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0,
+      FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
                             false, false, 0);
       Chain = SDValue(FPOpOut.getNode(), 1);
     }
@@ -3105,7 +3106,8 @@
         SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
         SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
         if (GPR_idx != NumGPRs) {
-          SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0,
+          SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
+                                     MachinePointerInfo(),
                                      false, false, 0);
           MemOpChains.push_back(Load.getValue(1));
           RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@@ -3143,15 +3145,16 @@
 
           // Float varargs are always shadowed in available integer registers
           if (GPR_idx != NumGPRs) {
-            SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0,
-                                       false, false, 0);
+            SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
+                                       MachinePointerInfo(), false, false, 0);
             MemOpChains.push_back(Load.getValue(1));
             RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
           }
           if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
             SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
             PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
-            SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0,
+            SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
+                                       MachinePointerInfo(),
                                        false, false, 0);
             MemOpChains.push_back(Load.getValue(1));
             RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@@ -3199,7 +3202,8 @@
                                      false, false, 0);
         MemOpChains.push_back(Store);
         if (VR_idx != NumVRs) {
-          SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0,
+          SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 
+                                     MachinePointerInfo(),
                                      false, false, 0);
           MemOpChains.push_back(Load.getValue(1));
           RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
@@ -3210,7 +3214,7 @@
             break;
           SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
                                   DAG.getConstant(i, PtrVT));
-          SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0,
+          SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
                                      false, false, 0);
           MemOpChains.push_back(Load.getValue(1));
           RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@@ -3363,7 +3367,8 @@
   SDValue SaveSP = Op.getOperand(1);
 
   // Load the old link SP.
-  SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0,
+  SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
+                                   MachinePointerInfo(),
                                    false, false, 0);
 
   // Restore the stack pointer.
@@ -3554,7 +3559,7 @@
   if (Op.getValueType() == MVT::i32)
     FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
                         DAG.getConstant(4, FIPtr.getValueType()));
-  return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0,
+  return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
                      false, false, 0);
 }
 
@@ -3592,15 +3597,15 @@
 
   // STD the extended value into the stack slot.
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(
-                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
                             MachineMemOperand::MOStore, 8, 8);
   SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
   SDValue Store =
     DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
                             Ops, 4, MVT::i64, MMO);
   // Load the value as a double.
-  SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0, false, false, 0);
+  SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
+                           false, false, 0);
 
   // FCFID it and return it.
   SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
@@ -3651,7 +3656,7 @@
   // Load FP Control Word from low 32 bits of stack slot.
   SDValue Four = DAG.getConstant(4, PtrVT);
   SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
-  SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0,
+  SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
                             false, false, 0);
 
   // Transform as necessary
@@ -4322,7 +4327,7 @@
                                Op.getOperand(0), FIdx, NULL, 0,
                                false, false, 0);
   // Load it out.
-  return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0,
+  return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
                      false, false, 0);
 }
 
@@ -5544,13 +5549,13 @@
     return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
                        DAG.getNode(ISD::ADD, dl, getPointerTy(),
                                    FrameAddr, Offset),
-                       NULL, 0, false, false, 0);
+                       MachinePointerInfo(), false, false, 0);
   }
 
   // Just load the return address off the stack.
   SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
   return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
-                     RetAddrFI, NULL, 0, false, false, 0);
+                     RetAddrFI, MachinePointerInfo(), false, false, 0);
 }
 
 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
@@ -5573,7 +5578,7 @@
                                          PtrVT);
   while (Depth--)
     FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
-                            FrameAddr, NULL, 0, false, false, 0);
+                            FrameAddr, MachinePointerInfo(), false, false, 0);
   return FrameAddr;
 }
 

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -138,7 +138,7 @@
         SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
         SDValue Load;
         if (ObjectVT == MVT::i32) {
-          Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
+          Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(),
                              false, false, 0);
         } else {
           ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
@@ -172,7 +172,8 @@
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
                                                             true);
         SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-        SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0,
+        SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr,
+                                   MachinePointerInfo(),
                                    false, false, 0);
         InVals.push_back(Load);
       }
@@ -195,7 +196,7 @@
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
                                                               true);
           SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-          HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
+          HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(),
                               false, false, 0);
         }
 
@@ -208,7 +209,7 @@
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4,
                                                               true);
           SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-          LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
+          LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(),
                               false, false, 0);
         }
 
@@ -399,14 +400,14 @@
                                    Val, StackPtr, NULL, 0,
                                    false, false, 0);
       // Sparc is big-endian, so the high part comes first.
-      SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0,
-                               false, false, 0);
+      SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
+                               MachinePointerInfo(), false, false, 0);
       // Increment the pointer to the other half.
       StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
                              DAG.getIntPtrConstant(4));
       // Load the low part.
-      SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0,
-                               false, false, 0);
+      SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
+                               MachinePointerInfo(), false, false, 0);
 
       RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
 
@@ -774,7 +775,7 @@
   SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 
                                 GlobalBase, RelAddr);
   return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 
-                     AbsAddr, NULL, 0, false, false, 0);
+                     AbsAddr, MachinePointerInfo(), false, false, 0);
 }
 
 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
@@ -795,7 +796,7 @@
   SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
                                 GlobalBase, RelAddr);
   return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 
-                     AbsAddr, NULL, 0, false, false, 0);
+                     AbsAddr, MachinePointerInfo(), false, false, 0);
 }
 
 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
@@ -902,8 +903,8 @@
   SDValue VAListPtr = Node->getOperand(1);
   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
   DebugLoc dl = Node->getDebugLoc();
-  SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0,
-                               false, false, 0);
+  SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
+                               MachinePointerInfo(SV), false, false, 0);
   // Increment the pointer, VAList, to the next vaarg
   SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
                                   DAG.getConstant(VT.getSizeInBits()/8,
@@ -914,10 +915,11 @@
   // Load the actual argument out of the pointer VAList, unless this is an
   // f64 load.
   if (VT != MVT::f64)
-    return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0, false, false, 0);
+    return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
+                       false, false, 0);
 
   // Otherwise, load it as i64, then do a bitconvert.
-  SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0,
+  SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
                           false, false, 0);
 
   // Bit-Convert the value to f64.

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -341,7 +341,7 @@
       // from this parameter
       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
       ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
-                             PseudoSourceValue::getFixedStack(FI), 0,
+                             MachinePointerInfo::getFixedStack(FI),
                              false, false, 0);
     }
 
@@ -747,7 +747,7 @@
 
   if (ExtraLoadRequired)
     Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
-                         PseudoSourceValue::getGOT(), 0, false, false, 0);
+                         MachinePointerInfo::getGOT(), false, false, 0);
 
   // If there was a non-zero offset that we didn't fold, create an explicit
   // addition for it.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -6076,8 +6076,7 @@
   // load.
   if (isGlobalStubReference(OpFlags))
     Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
-                         MachinePointerInfo(PseudoSourceValue::getGOT()),
-                         false, false, 0);
+                         MachinePointerInfo::getGOT(), false, false, 0);
 
   // If there was a non-zero offset that we didn't fold, create an explicit
   // addition for it.
@@ -6182,8 +6181,7 @@
 
   if (model == TLSModel::InitialExec)
     Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
-                         MachinePointerInfo(PseudoSourceValue::getGOT()),
-                         false, false, 0);
+                         MachinePointerInfo::getGOT(), false, false, 0);
 
   // The address of the thread local variable is the add of the thread
   // pointer with the offset of the variable.

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=114410&r1=114409&r2=114410&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep 21 01:44:06 2010
@@ -419,10 +419,8 @@
       // We've managed to infer better alignment information than the load
       // already has. Use an aligned load.
       //
-      // FIXME: No new alignment information is actually passed here.
-      // Should the offset really be 4?
-      //
-      return DAG.getLoad(getPointerTy(), dl, Chain, BasePtr, NULL, 4,
+      return DAG.getLoad(getPointerTy(), dl, Chain, BasePtr,
+                         MachinePointerInfo(),
                          false, false, 0);
     }
     // Lower to
@@ -440,9 +438,9 @@
     SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset);
     
     SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain,
-                              LowAddr, NULL, 4, false, false, 0);
+                              LowAddr, MachinePointerInfo(), false, false, 0);
     SDValue High = DAG.getLoad(getPointerTy(), dl, Chain,
-                               HighAddr, NULL, 4, false, false, 0);
+                               HighAddr, MachinePointerInfo(), false, false, 0);
     SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift);
     SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift);
     SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted);
@@ -757,7 +755,8 @@
   const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
   EVT VT = Node->getValueType(0);
   SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
-                               Node->getOperand(1), V, 0, false, false, 0);
+                               Node->getOperand(1), MachinePointerInfo(V),
+                               false, false, 0);
   // Increment the pointer, VAList, to the next vararg
   SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, 
                      DAG.getConstant(VT.getSizeInBits(), 
@@ -766,7 +765,8 @@
   Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0,
                       false, false, 0);
   // Load the actual argument out of the pointer VAList
-  return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, false, false, 0);
+  return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
+                     false, false, 0);
 }
 
 SDValue XCoreTargetLowering::
@@ -1079,7 +1079,8 @@
       // Create the SelectionDAG nodes corresponding to a load
       //from this parameter
       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
-      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, NULL, 0,
+      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 
+                                   MachinePointerInfo::getFixedStack(FI),
                                    false, false, 0));
     }
   }



From sabre at nondot.org  Tue Sep 21 02:32:19 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 07:32:19 -0000
Subject: [llvm-commits] [llvm] r114411 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: DAGCombiner.cpp LegalizeDAG.cpp
Message-ID: <20100921073219.67CB62A6C12D@llvm.org>

Author: lattner
Date: Tue Sep 21 02:32:19 2010
New Revision: 114411

URL: http://llvm.org/viewvc/llvm-project?rev=114411&view=rev
Log:
a few more trivial updates.  This fixes PerformInsertVectorEltInMemory to not
pass a completely incorrect SrcValue, which would result in a miscompile with
combiner-aa.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114411&r1=114410&r2=114411&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 02:32:19 2010
@@ -6769,7 +6769,7 @@
         CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
                             CstOffset);
         return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
-                           PseudoSourceValue::getConstantPool(), 0, false,
+                           MachinePointerInfo::getConstantPool(), false,
                            false, Alignment);
 
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=114411&r1=114410&r2=114411&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 21 02:32:19 2010
@@ -379,10 +379,10 @@
   if (Extend)
     return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
                           DAG.getEntryNode(),
-                          CPIdx, PseudoSourceValue::getConstantPool(),
-                          0, VT, false, false, Alignment);
+                          CPIdx, MachinePointerInfo::getConstantPool(),
+                          VT, false, false, Alignment);
   return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
-                     PseudoSourceValue::getConstantPool(), 0, false, false,
+                     MachinePointerInfo::getConstantPool(), false, false,
                      Alignment);
 }
 
@@ -660,7 +660,7 @@
 
   // Store the vector.
   SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
-                            PseudoSourceValue::getFixedStack(SPFI), 0,
+                            MachinePointerInfo::getFixedStack(SPFI),
                             false, false, 0);
 
   // Truncate or zero extend offset to target pointer type.
@@ -671,13 +671,11 @@
   Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
   SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
   // Store the scalar value.
-  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
-                         PseudoSourceValue::getFixedStack(SPFI), 0, EltVT,
+  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
                          false, false, 0);
   // Load the updated vector.
   return DAG.getLoad(VT, dl, Ch, StackPtr,
-                     PseudoSourceValue::getFixedStack(SPFI), 0,
-                     false, false, 0);
+                     MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
 }
 
 
@@ -1810,11 +1808,11 @@
 
   SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
                                  StackPtr,
-                                 PseudoSourceValue::getFixedStack(SPFI), 0,
+                                 MachinePointerInfo::getFixedStack(SPFI),
                                  Node->getValueType(0).getVectorElementType(),
                                  false, false, 0);
   return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
-                     PseudoSourceValue::getFixedStack(SPFI), 0,
+                     MachinePointerInfo::getFixedStack(SPFI),
                      false, false, 0);
 }
 
@@ -1888,7 +1886,7 @@
     SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
     unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
     return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
-                       PseudoSourceValue::getConstantPool(), 0,
+                       MachinePointerInfo::getConstantPool(),
                        false, false, Alignment);
   }
 
@@ -2189,13 +2187,13 @@
   SDValue FudgeInReg;
   if (DestVT == MVT::f32)
     FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
-                             PseudoSourceValue::getConstantPool(), 0,
+                             MachinePointerInfo::getConstantPool(),
                              false, false, Alignment);
   else {
     FudgeInReg =
       LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
                                 DAG.getEntryNode(), CPIdx,
-                                PseudoSourceValue::getConstantPool(), 0,
+                                MachinePointerInfo::getConstantPool(),
                                 MVT::f32, false, false, Alignment));
   }
 
@@ -3166,7 +3164,7 @@
 
     EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
     SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
-                                PseudoSourceValue::getJumpTable(), 0, MemVT,
+                                MachinePointerInfo::getJumpTable(), MemVT,
                                 false, false, 0);
     Addr = LD;
     if (TM.getRelocationModel() == Reloc::PIC_) {



From baldrick at free.fr  Tue Sep 21 03:48:59 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 21 Sep 2010 08:48:59 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r114417 - in /llvm-gcc-4.2/trunk/gcc:
	configure configure.ac
Message-ID: <20100921084859.DF7D12A6C12C@llvm.org>

Author: baldrick
Date: Tue Sep 21 03:48:59 2010
New Revision: 114417

URL: http://llvm.org/viewvc/llvm-project?rev=114417&view=rev
Log:
Add support for building against a Release+Debug+Asserts+Checks
LLVM build.

Modified:
    llvm-gcc-4.2/trunk/gcc/configure
    llvm-gcc-4.2/trunk/gcc/configure.ac

Modified: llvm-gcc-4.2/trunk/gcc/configure
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure?rev=114417&r1=114416&r2=114417&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/configure (original)
+++ llvm-gcc-4.2/trunk/gcc/configure Tue Sep 21 03:48:59 2010
@@ -8943,6 +8943,9 @@
  elif test -x "$LLVMBASEPATH/Release+Debug+Asserts/bin/llc$EXEEXT"; then
      echo Found Release+Debug+Asserts LLVM Tree in $LLVMBASEPATH
      LLVMBUILDMODE="Release+Debug+Asserts"
+ elif test -x "$LLVMBASEPATH/Release+Debug+Asserts+Checks/bin/llc$EXEEXT"; then
+     echo Found Release+Debug+Asserts+Checks LLVM Tree in $LLVMBASEPATH
+     LLVMBUILDMODE="Release+Debug+Asserts+Checks"
  elif test -x "$LLVMBASEPATH/Debug+Asserts+Checks/bin/llc$EXEEXT"; then
      echo Found Debug+Asserts+Checks LLVM Tree in $LLVMBASEPATH
      LLVMBUILDMODE="Debug+Asserts+Checks"

Modified: llvm-gcc-4.2/trunk/gcc/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure.ac?rev=114417&r1=114416&r2=114417&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/configure.ac (original)
+++ llvm-gcc-4.2/trunk/gcc/configure.ac Tue Sep 21 03:48:59 2010
@@ -876,6 +876,9 @@
  elif test -x "$LLVMBASEPATH/Release+Debug+Asserts/bin/llc$EXEEXT"; then
      echo Found Release+Debug+Asserts LLVM Tree in $LLVMBASEPATH
      LLVMBUILDMODE="Release+Debug+Asserts"
+ elif test -x "$LLVMBASEPATH/Release+Debug+Asserts+Checks/bin/llc$EXEEXT"; then
+     echo Found Release+Debug+Asserts+Checks LLVM Tree in $LLVMBASEPATH
+     LLVMBUILDMODE="Release+Debug+Asserts+Checks"
  elif test -x "$LLVMBASEPATH/Debug+Asserts+Checks/bin/llc$EXEEXT"; then
      echo Found Debug+Asserts+Checks LLVM Tree in $LLVMBASEPATH
      LLVMBUILDMODE="Debug+Asserts+Checks"



From isanbard at gmail.com  Tue Sep 21 05:34:03 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 21 Sep 2010 10:34:03 -0000
Subject: [llvm-commits] [test-suite] r114418 -
	/test-suite/tags/RELEASE_28/rc2/
Message-ID: <20100921103403.60E852A6C12C@llvm.org>

Author: void
Date: Tue Sep 21 05:34:03 2010
New Revision: 114418

URL: http://llvm.org/viewvc/llvm-project?rev=114418&view=rev
Log:
Remove bad tag.

Removed:
    test-suite/tags/RELEASE_28/rc2/


From isanbard at gmail.com  Tue Sep 21 05:36:19 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 21 Sep 2010 10:36:19 -0000
Subject: [llvm-commits] [test-suite] r114425 -
	/test-suite/tags/RELEASE_28/rc2/
Message-ID: <20100921103619.5C7632A6C12C@llvm.org>

Author: void
Date: Tue Sep 21 05:36:19 2010
New Revision: 114425

URL: http://llvm.org/viewvc/llvm-project?rev=114425&view=rev
Log:
Creating release candidate 2 from 2.8 release branch.

Added:
    test-suite/tags/RELEASE_28/rc2/
      - copied from r114424, test-suite/tags/RELEASE_28/rc1/


From foldr at codedgers.com  Tue Sep 21 06:57:04 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Tue, 21 Sep 2010 11:57:04 -0000
Subject: [llvm-commits] [llvm] r114427 -
	/llvm/trunk/tools/llvmc/src/Base.td.in
Message-ID: <20100921115704.4383B2A6C12C@llvm.org>

Author: foldr
Date: Tue Sep 21 06:57:04 2010
New Revision: 114427

URL: http://llvm.org/viewvc/llvm-project?rev=114427&view=rev
Log:
llvmc: put linker options in a separate OptList.

Modified:
    llvm/trunk/tools/llvmc/src/Base.td.in

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=114427&r1=114426&r2=114427&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Tue Sep 21 06:57:04 2010
@@ -35,8 +35,6 @@
     (help "Stop after compilation, do not assemble")),
  (switch_option "c",
     (help "Compile and assemble, but do not link")),
- (switch_option "pthread",
-    (help "Enable threads")),
  (switch_option "m32",
     (help "Generate code for a 32-bit environment"), (hidden)),
  (switch_option "m64",
@@ -45,18 +43,10 @@
     (help "Relocation model: PIC"), (hidden)),
  (switch_option "mdynamic-no-pic",
     (help "Relocation model: dynamic-no-pic"), (hidden)),
- (switch_option "shared",
-     (help "Create a DLL instead of the regular executable")),
  (parameter_option "linker",
     (help "Choose linker (possible values: gcc, g++)")),
  (parameter_option "mtune",
     (help "Target a specific CPU type"), (hidden), (forward_not_split)),
-
- // TODO: Add a conditional compilation mechanism to make Darwin-only options
- // like '-arch' really Darwin-only.
-
- (parameter_option "arch",
-    (help "Compile for the specified target architecture"), (hidden)),
  (parameter_option "march",
     (help "A synonym for -mtune"), (hidden), (forward_not_split)),
  (parameter_option "mcpu",
@@ -73,14 +63,6 @@
  (parameter_list_option "iquote",
     (help "Search dir only for files requested with #inlcude \"file\""),
     (hidden)),
- (parameter_list_option "framework",
-    (help "Specifies a framework to link against")),
- (parameter_list_option "weak_framework",
-    (help "Specifies a framework to weakly link against"), (hidden)),
- (parameter_option "filelist", (hidden),
-    (help "Link the files listed in file")),
- (prefix_list_option "F",
-    (help "Add a directory to framework search path")),
  (prefix_list_option "I",
     (help "Add a directory to include path")),
  (prefix_list_option "D",
@@ -93,10 +75,6 @@
     (help "Pass options to assembler")),
  (prefix_list_option "Wllc,", (comma_separated),
     (help "Pass options to llc")),
- (prefix_list_option "L",
-    (help "Add a directory to link path")),
- (prefix_list_option "l",
-    (help "Search a library when linking")),
  (prefix_list_option "Wl,",
     (help "Pass options to linker")),
  (parameter_list_option "Xlinker", (hidden),
@@ -105,7 +83,56 @@
     (help "Pass options to opt")),
  (prefix_list_option "m",
      (help "Enable or disable various extensions (-mmmx, -msse, etc.)"),
-     (hidden)),
+     (hidden))
+]>;
+
+def LinkerOptList : OptionList<[
+ (prefix_list_option "L",
+    (help "Add a directory to link path")),
+ (prefix_list_option "l",
+    (help "Search a library when linking")),
+ (parameter_option "filelist", (hidden),
+    (help "Link the files listed in file")),
+ (switch_option "nostartfiles",
+    (help "Do not use the standard system startup files when linking"),
+    (hidden)),
+ (switch_option "nodefaultlibs",
+    (help "Do not use the standard system libraries when linking"), (hidden)),
+ (switch_option "nostdlib",
+    (help
+    "Do not use the standard system startup files or libraries when linking"),
+    (hidden)),
+ (switch_option "pie",
+     (help "Produce a position independent executable"), (hidden)),
+ (switch_option "rdynamic",
+     (help "Add all symbols to the dynamic export table"), (hidden)),
+ (switch_option "s",
+    (help "Strip all symbols"), (hidden)),
+ (switch_option "static",
+     (help "Do not link against shared libraries"), (hidden)),
+ (switch_option "static-libgcc",
+     (help "Use static libgcc"), (hidden)),
+ (switch_option "shared",
+     (help "Create a DLL instead of the regular executable")),
+ (switch_option "shared-libgcc",
+     (help "Use shared libgcc"), (hidden)),
+ (parameter_option "T",
+     (help "Read linker script"), (hidden)),
+ (parameter_option "u",
+     (help "Start with undefined reference to SYMBOL"), (hidden)),
+ (switch_option "pthread",
+    (help "Enable threads")),
+
+ // TODO: Add a conditional compilation mechanism to make Darwin-only options
+ // like '-arch' really Darwin-only.
+ (parameter_option "arch",
+    (help "Compile for the specified target architecture"), (hidden)),
+ (prefix_list_option "F",
+    (help "Add a directory to framework search path")),
+ (parameter_list_option "framework",
+    (help "Specifies a framework to link against")),
+ (parameter_list_option "weak_framework",
+    (help "Specifies a framework to weakly link against"), (hidden)),
  (switch_option "dynamiclib", (hidden),
      (help "Produce a dynamic library")),
  (switch_option "prebind", (hidden),
@@ -137,12 +164,12 @@
 
 // Tools
 
-class llvm_gcc_based <string cmd_prefix, string in_lang,
+class llvm_gcc_based <string cmd, string in_lang,
                       string E_ext, string out_lang> : Tool<
 [(in_language in_lang),
  (out_language "llvm-bitcode"),
  (output_suffix out_lang),
- (command cmd_prefix),
+ (command cmd),
  (actions
      (case
          (and (not_empty "o"),
@@ -261,11 +288,11 @@
 ]>;
 
 // Base class for linkers
-class llvm_gcc_based_linker <string cmd_prefix, dag on_empty> : Tool<
+class llvm_gcc_based_linker <string cmd, dag on_empty> : Tool<
 [(in_language ["object-code", "static-library", "dynamic-library"]),
  (out_language "executable"),
  (output_suffix "out"),
- (command cmd_prefix),
+ (command cmd),
  (works_on_empty (case (and (not_empty "filelist"), on_empty), true,
                        (default), false)),
  (join),
@@ -282,7 +309,18 @@
           (not_empty "l"), (forward "l"),
           (not_empty "Xlinker"), (forward "Xlinker"),
           (not_empty "Wl,"), (forward "Wl,"),
+          (switch_on "nostartfiles"), (forward "nostartfiles"),
+          (switch_on "nodefaultlibs"), (forward "nodefaultlibs"),
+          (switch_on "nostdlib"), (forward "nostdlib"),
+          (switch_on "pie"), (forward "pie"),
+          (switch_on "rdynamic"), (forward "rdynamic"),
+          (switch_on "s"), (forward "s"),
+          (switch_on "static"), (forward "static"),
+          (switch_on "static-libgcc"), (forward "static-libgcc"),
           (switch_on "shared"), (forward "shared"),
+          (switch_on "shared-libgcc"), (forward "shared-libgcc"),
+          (not_empty "T"), (forward "T"),
+          (not_empty "u"), (forward "u"),
           (switch_on "dynamiclib"), (forward "dynamiclib"),
           (switch_on "prebind"), (forward "prebind"),
           (switch_on "dead_strip"), (forward "dead_strip"),



From ggreif at gmail.com  Tue Sep 21 07:01:16 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 21 Sep 2010 12:01:16 -0000
Subject: [llvm-commits] [llvm] r114428 - in /llvm/trunk:
 include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
Message-ID: <20100921120116.175F02A6C12C@llvm.org>

Author: ggreif
Date: Tue Sep 21 07:01:15 2010
New Revision: 114428

URL: http://llvm.org/viewvc/llvm-project?rev=114428&view=rev
Log:
Move the search for the appropriate AND instruction
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.

No functionality changes.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=114428&r1=114427&r2=114428&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Sep 21 07:01:15 2010
@@ -581,7 +581,7 @@
   /// in SrcReg and the value it compares against in CmpValue. Return true if
   /// the comparison instruction can be analyzed.
   virtual bool AnalyzeCompare(const MachineInstr *MI,
-                              unsigned &SrcReg, int &CmpValue) const {
+                              unsigned &SrcReg, int &Mask, int &Value) const {
     return false;
   }
 
@@ -589,8 +589,8 @@
   /// into something more efficient. E.g., on ARM most instructions can set the
   /// flags register, obviating the need for a separate CMP. Update the iterator
   /// *only* if a transformation took place.
-  virtual bool OptimizeCompareInstr(MachineInstr * /*CmpInstr*/,
-                                    unsigned /*SrcReg*/, int /*CmpValue*/,
+  virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
+                                    unsigned SrcReg, int Mask, int Value,
                                     MachineBasicBlock::iterator &) const {
     return false;
   }

Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=114428&r1=114427&r2=114428&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Sep 21 07:01:15 2010
@@ -238,13 +238,13 @@
   // If this instruction is a comparison against zero and isn't comparing a
   // physical register, we can try to optimize it.
   unsigned SrcReg;
-  int CmpValue;
-  if (!TII->AnalyzeCompare(MI, SrcReg, CmpValue) ||
+  int CmpMask, CmpValue;
+  if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
       TargetRegisterInfo::isPhysicalRegister(SrcReg))
     return false;
 
   // Attempt to optimize the comparison instruction.
-  if (TII->OptimizeCompareInstr(MI, SrcReg, CmpValue, NextIter)) {
+  if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, NextIter)) {
     ++NumEliminated;
     return true;
   }

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114428&r1=114427&r2=114428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 21 07:01:15 2010
@@ -1376,7 +1376,7 @@
 }
 
 bool ARMBaseInstrInfo::
-AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
+AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, int &CmpValue) const {
   switch (MI->getOpcode()) {
   default: break;
   case ARM::CMPri:
@@ -1384,23 +1384,29 @@
   case ARM::t2CMPri:
   case ARM::t2CMPzri:
     SrcReg = MI->getOperand(0).getReg();
+    CmpMask = ~0;
     CmpValue = MI->getOperand(1).getImm();
     return true;
-  case ARM::TSTri: {
-    MachineBasicBlock::const_iterator MII(MI);
-    if (MI->getParent()->begin() == MII)
-      return false;
-    const MachineInstr *AND = llvm::prior(MII);
-    if (AND->getOpcode() != ARM::ANDri)
-      return false;
-    if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
-        MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
-      SrcReg = AND->getOperand(0).getReg();
-      CmpValue = 0;
-      return true;
-    }
-    }
-    break;
+  case ARM::TSTri:
+  case ARM::t2TSTri:
+    SrcReg = MI->getOperand(0).getReg();
+    CmpMask = MI->getOperand(1).getImm();
+    CmpValue = 0;
+    return true;
+  }
+
+  return false;
+}
+
+static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
+                              int CmpMask) {
+  switch (MI.getOpcode()) {
+    case ARM::ANDri:
+    case ARM::t2ANDri:
+      if (SrcReg == MI.getOperand(1).getReg() &&
+          CmpMask == MI.getOperand(2).getImm())
+        return true;
+      break;
   }
 
   return false;
@@ -1410,8 +1416,8 @@
 /// comparison into one that sets the zero bit in the flags register. Update the
 /// iterator *only* if a transformation took place.
 bool ARMBaseInstrInfo::
-OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
-                     MachineBasicBlock::iterator &MII) const {
+OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
+                     int CmpValue, MachineBasicBlock::iterator &MII) const {
   if (CmpValue != 0)
     return false;
 
@@ -1423,6 +1429,24 @@
 
   MachineInstr *MI = &*DI;
 
+  // Masked compares sometimes use the same register as the corresponding 'and'.
+  if (CmpMask != ~0) {
+    if (!isSuitableForMask(*MI, SrcReg, CmpMask)) {
+      MI = 0;
+      for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
+           UE = MRI.use_end(); UI != UE; ++UI) {
+        if (UI->getParent() != CmpInstr->getParent()) continue;
+        MachineInstr &PotentialAND = *UI;
+        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask))
+          continue;
+        SrcReg = PotentialAND.getOperand(0).getReg();
+        MI = &PotentialAND;
+        break;
+      }
+      if (!MI) return false;
+    }
+  }
+
   // Conservatively refuse to convert an instruction which isn't in the same BB
   // as the comparison.
   if (MI->getParent() != CmpInstr->getParent())

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=114428&r1=114427&r2=114428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Sep 21 07:01:15 2010
@@ -326,12 +326,12 @@
   /// in SrcReg and the value it compares against in CmpValue. Return true if
   /// the comparison instruction can be analyzed.
   virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
-                              int &CmpValue) const;
+                              int &CmpMask, int &CmpValue) const;
 
   /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
   /// that we can remove a "comparison with zero".
   virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
-                                    int CmpValue,
+                                    int CmpMask, int CmpValue,
                                     MachineBasicBlock::iterator &MII) const;
 
   virtual unsigned getNumMicroOps(const MachineInstr *MI,



From lhames at gmail.com  Tue Sep 21 08:19:36 2010
From: lhames at gmail.com (Lang Hames)
Date: Tue, 21 Sep 2010 13:19:36 -0000
Subject: [llvm-commits] [llvm] r114429 - in /llvm/trunk:
 include/llvm/CodeGen/PBQP/Heuristics/Briggs.h
 include/llvm/CodeGen/RegAllocPBQP.h lib/CodeGen/RegAllocPBQP.cpp
Message-ID: <20100921131936.528C02A6C12C@llvm.org>

Author: lhames
Date: Tue Sep 21 08:19:36 2010
New Revision: 114429

URL: http://llvm.org/viewvc/llvm-project?rev=114429&view=rev
Log:
Added an additional PBQP problem builder which adds coalescing costs (both between pairs of virtuals, and between virtuals and physicals).


Modified:
    llvm/trunk/include/llvm/CodeGen/PBQP/Heuristics/Briggs.h
    llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h
    llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp

Modified: llvm/trunk/include/llvm/CodeGen/PBQP/Heuristics/Briggs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PBQP/Heuristics/Briggs.h?rev=114429&r1=114428&r2=114429&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/PBQP/Heuristics/Briggs.h (original)
+++ llvm/trunk/include/llvm/CodeGen/PBQP/Heuristics/Briggs.h Tue Sep 21 08:19:36 2010
@@ -63,8 +63,12 @@
         SpillCostComparator(HeuristicSolverImpl<Briggs> &s)
           : s(&s), g(&s.getGraph()) {}
         bool operator()(Graph::NodeItr n1Itr, Graph::NodeItr n2Itr) const {
-          PBQPNum cost1 = g->getNodeCosts(n1Itr)[0] / s->getSolverDegree(n1Itr),
-                  cost2 = g->getNodeCosts(n2Itr)[0] / s->getSolverDegree(n2Itr);
+          const PBQP::Vector &cv1 = g->getNodeCosts(n1Itr);
+          const PBQP::Vector &cv2 = g->getNodeCosts(n2Itr);
+
+          PBQPNum cost1 = cv1[0] / s->getSolverDegree(n1Itr);
+          PBQPNum cost2 = cv2[0] / s->getSolverDegree(n2Itr);
+
           if (cost1 < cost2)
             return true;
           return false;

Modified: llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h?rev=114429&r1=114428&r2=114429&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Tue Sep 21 08:19:36 2010
@@ -27,6 +27,7 @@
 
   class LiveInterval;
   class MachineFunction;
+  class MachineLoopInfo;
 
   /// This class wraps up a PBQP instance representing a register allocation
   /// problem, plus the structures necessary to map back from the PBQP solution
@@ -113,7 +114,6 @@
 
     typedef std::set<unsigned> RegSet;
  
-
     /// Default constructor.
     PBQPBuilder() {}
 
@@ -125,6 +125,7 @@
     virtual std::auto_ptr<PBQPRAProblem> build(
                                               MachineFunction *mf,
                                               const LiveIntervals *lis,
+                                              const MachineLoopInfo *loopInfo,
                                               const RegSet &vregs);
   private:
 
@@ -136,6 +137,29 @@
                               const TargetRegisterInfo *tri);
   };
 
+  /// Extended builder which adds coalescing constraints to a problem.
+  class PBQPBuilderWithCoalescing : public PBQPBuilder {
+  public:
+ 
+    /// Build a PBQP instance to represent the register allocation problem for
+    /// the given MachineFunction.
+    virtual std::auto_ptr<PBQPRAProblem> build(
+                                              MachineFunction *mf,
+                                              const LiveIntervals *lis,
+                                              const MachineLoopInfo *loopInfo,
+                                              const RegSet &vregs);   
+
+  private:
+
+    void addPhysRegCoalesce(PBQP::Vector &costVec, unsigned pregOption,
+                            PBQP::PBQPNum benefit);
+
+    void addVirtRegCoalesce(PBQP::Matrix &costMat,
+                            const PBQPRAProblem::AllowedSet &vr1Allowed,
+                            const PBQPRAProblem::AllowedSet &vr2Allowed,
+                            PBQP::PBQPNum benefit);
+  };
+
   ///
   /// PBQP based allocators solve the register allocation problem by mapping
   /// register allocation problems to Partitioned Boolean Quadratic

Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114429&r1=114428&r2=114429&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Sep 21 08:19:36 2010
@@ -58,9 +58,6 @@
 
 namespace llvm {
 
-using namespace PBQP;
-  using namespace PBQP::Heuristics;
-
 static RegisterRegAlloc
 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
                        llvm::createPBQPRegisterAllocator);
@@ -112,10 +109,10 @@
   return allowedSet[option - 1];
 }
 
-std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(
-                                             MachineFunction *mf,
-                                             const LiveIntervals *lis,
-                                             const RegSet &vregs) {
+std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf,
+                                                const LiveIntervals *lis,
+                                                const MachineLoopInfo *loopInfo,
+                                                const RegSet &vregs) {
 
   typedef std::vector<const LiveInterval*> LIVector;
 
@@ -235,10 +232,11 @@
   costVec[0] = spillCost;
 }
 
-void PBQPBuilder::addInterferenceCosts(PBQP::Matrix &costMat,
-                                       const PBQPRAProblem::AllowedSet &vr1Allowed,
-                                       const PBQPRAProblem::AllowedSet &vr2Allowed,
-                                       const TargetRegisterInfo *tri) {
+void PBQPBuilder::addInterferenceCosts(
+                                    PBQP::Matrix &costMat,
+                                    const PBQPRAProblem::AllowedSet &vr1Allowed,
+                                    const PBQPRAProblem::AllowedSet &vr2Allowed,
+                                    const TargetRegisterInfo *tri) {
   assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
   assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
 
@@ -255,6 +253,115 @@
   }
 }
 
+std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
+                                                MachineFunction *mf,
+                                                const LiveIntervals *lis,
+                                                const MachineLoopInfo *loopInfo,
+                                                const RegSet &vregs) {
+
+  std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs);
+  PBQP::Graph &g = p->getGraph();
+
+  const TargetMachine &tm = mf->getTarget();
+  CoalescerPair cp(*tm.getInstrInfo(), *tm.getRegisterInfo());
+
+  // Scan the machine function and add a coalescing cost whenever CoalescerPair
+  // gives the Ok.
+  for (MachineFunction::const_iterator mbbItr = mf->begin(),
+                                       mbbEnd = mf->end();
+       mbbItr != mbbEnd; ++mbbItr) {
+    const MachineBasicBlock *mbb = &*mbbItr;
+
+    for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
+                                           miEnd = mbb->end();
+         miItr != miEnd; ++miItr) {
+      const MachineInstr *mi = &*miItr;
+
+      if (!mi->isCopy() && !mi->isSubregToReg())
+        continue; // Not coalescable.
+
+      if (!cp.setRegisters(mi))
+        continue; // Not coalescable.
+
+      if (cp.getSrcReg() == cp.getDstReg())
+        continue; // Already coalesced.
+
+      if (cp.isCoalescable(mi)) {
+
+        unsigned dst = cp.getDstReg(),
+                 src = cp.getSrcReg();
+
+
+
+        PBQP::PBQPNum cBenefit = std::pow(10.0f, loopInfo->getLoopDepth(mbb));
+
+        if (cp.isPhys()) {
+          if (!lis->isAllocatable(dst))
+            continue;
+
+          const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
+          unsigned pregOpt = 0;  
+          while (pregOpt < allowed.size() && allowed[pregOpt] != dst)
+            ++pregOpt;
+          if (pregOpt < allowed.size()) {
+            ++pregOpt; // +1 to account for spill option.
+            PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
+            addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
+          }
+        } else {
+          const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
+          const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
+          PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
+          PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
+          PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
+          if (edge == g.edgesEnd()) {
+            edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
+                                                        allowed2->size() + 1,
+                                                        0));
+          } else {
+            if (g.getEdgeNode1(edge) == node2) {
+              std::swap(node1, node2);
+              std::swap(allowed1, allowed2);
+            }
+          }
+            
+          addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
+                             cBenefit);
+        }
+      }
+    }
+  }
+
+  return p;
+}
+
+
+void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
+                                                   unsigned pregOption,
+                                                   PBQP::PBQPNum benefit) {
+  costVec[pregOption] += -benefit;
+}
+
+void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
+                                    PBQP::Matrix &costMat,
+                                    const PBQPRAProblem::AllowedSet &vr1Allowed,
+                                    const PBQPRAProblem::AllowedSet &vr2Allowed,
+                                    PBQP::PBQPNum benefit) {
+
+  assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
+  assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
+
+  for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
+    unsigned preg1 = vr1Allowed[i];
+    for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
+      unsigned preg2 = vr2Allowed[j];
+
+      if (preg1 == preg2) {
+        costMat[i + 1][j + 1] += -benefit;
+      } 
+    }
+  }
+}
 
 
 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
@@ -1037,9 +1144,10 @@
         DEBUG(dbgs() << "  PBQP Regalloc round " << round << ":\n");
 
         std::auto_ptr<PBQPRAProblem> problem =
-          builder->build(mf, lis, vregsToAlloc);
+          builder->build(mf, lis, loopInfo, vregsToAlloc);
         PBQP::Solution solution =
-          HeuristicSolver<Briggs>::solve(problem->getGraph());
+          PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
+            problem->getGraph());
 
         pbqpAllocComplete = mapPBQPToRegAlloc2(*problem, solution);
 
@@ -1071,7 +1179,12 @@
 }
 
 FunctionPass* createPBQPRegisterAllocator() {
-  return new RegAllocPBQP(std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));
+  if (pbqpCoalescing) {
+    return new RegAllocPBQP(
+                 std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
+  } // else
+  return new RegAllocPBQP(
+                 std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));
 }
 
 }



From ggreif at gmail.com  Tue Sep 21 08:30:57 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 21 Sep 2010 13:30:57 -0000
Subject: [llvm-commits] [llvm] r114430 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20100921133057.6DA682A6C12C@llvm.org>

Author: ggreif
Date: Tue Sep 21 08:30:57 2010
New Revision: 114430

URL: http://llvm.org/viewvc/llvm-project?rev=114430&view=rev
Log:
Fix buglet when the TST instruction directly uses the AND result.
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114430&r1=114429&r2=114430&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 21 08:30:57 2010
@@ -1399,12 +1399,13 @@
 }
 
 static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
-                              int CmpMask) {
+                              int CmpMask, bool CommonUse) {
   switch (MI.getOpcode()) {
     case ARM::ANDri:
     case ARM::t2ANDri:
-      if (SrcReg == MI.getOperand(1).getReg() &&
-          CmpMask == MI.getOperand(2).getImm())
+      if (CmpMask != MI.getOperand(2).getImm())
+        return false;
+      if (SrcReg == MI.getOperand(CommonUse ? 1 : 0).getReg())
         return true;
       break;
   }
@@ -1431,13 +1432,13 @@
 
   // Masked compares sometimes use the same register as the corresponding 'and'.
   if (CmpMask != ~0) {
-    if (!isSuitableForMask(*MI, SrcReg, CmpMask)) {
+      if (!isSuitableForMask(*MI, SrcReg, CmpMask, false)) {
       MI = 0;
       for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
            UE = MRI.use_end(); UI != UE; ++UI) {
         if (UI->getParent() != CmpInstr->getParent()) continue;
         MachineInstr &PotentialAND = *UI;
-        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask))
+        if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
           continue;
         SrcReg = PotentialAND.getOperand(0).getReg();
         MI = &PotentialAND;



From lhames at gmail.com  Tue Sep 21 08:47:10 2010
From: lhames at gmail.com (Lang Hames)
Date: Tue, 21 Sep 2010 13:47:10 -0000
Subject: [llvm-commits] [llvm] r114431 -
	/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
Message-ID: <20100921134710.AEDCA2A6C12C@llvm.org>

Author: lhames
Date: Tue Sep 21 08:47:10 2010
New Revision: 114431

URL: http://llvm.org/viewvc/llvm-project?rev=114431&view=rev
Log:
Fixed ambiguous call.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114431&r1=114430&r2=114431&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Sep 21 08:47:10 2010
@@ -293,7 +293,8 @@
 
 
 
-        PBQP::PBQPNum cBenefit = std::pow(10.0f, loopInfo->getLoopDepth(mbb));
+        PBQP::PBQPNum cBenefit =
+          std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb));
 
         if (cp.isPhys()) {
           if (!lis->isAllocatable(dst))



From ggreif at gmail.com  Tue Sep 21 08:49:05 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 21 Sep 2010 06:49:05 -0700 (PDT)
Subject: [llvm-commits] [test-suite] r114425 -
	/test-suite/tags/RELEASE_28/rc2/
In-Reply-To: <20100921103619.5C7632A6C12C@llvm.org>
References: <20100921103619.5C7632A6C12C@llvm.org>
Message-ID: <2c85a2f9-d7de-405c-8b5e-83b7e253d88b@c16g2000vbp.googlegroups.com>

Hi Bill!

On Sep 21, 12:36?pm, Bill Wendling <isanb... at gmail.com> wrote:
> Author: void
> Date: Tue Sep 21 05:36:19 2010
> New Revision: 114425
>
> URL:http://llvm.org/viewvc/llvm-project?rev=114425&view=rev
> Log:
> Creating release candidate 2 from 2.8 release branch.
>
> Added:
> ? ? test-suite/tags/RELEASE_28/rc2/
> ? ? ? - copied from r114424, test-suite/tags/RELEASE_28/rc1/

Heh, this is in conflict what you say above. You wanted to cut from
the 28*branch*, right?

Cheers,

    Gabor

>
> _______________________________________________
> llvm-commits mailing list
> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From stoklund at 2pi.dk  Tue Sep 21 09:18:44 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 07:18:44 -0700
Subject: [llvm-commits] [llvm] r114431 -
	/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
In-Reply-To: <20100921134710.AEDCA2A6C12C@llvm.org>
References: <20100921134710.AEDCA2A6C12C@llvm.org>
Message-ID: <65223A2F-E08D-44FB-A0A7-4784DC5213CF@2pi.dk>


On Sep 21, 2010, at 6:47 AM, Lang Hames wrote:
> --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Sep 21 08:47:10 2010
> @@ -293,7 +293,8 @@
> -        PBQP::PBQPNum cBenefit = std::pow(10.0f, loopInfo->getLoopDepth(mbb));
> +        PBQP::PBQPNum cBenefit =
> +          std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb));

Hi Lang,

You should consider using LiveIntervals::getSpillWeight which is tempered so it never overflows.

/jakob

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From stoklund at 2pi.dk  Tue Sep 21 09:41:39 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 07:41:39 -0700
Subject: [llvm-commits] [llvm] r114429 - in /llvm/trunk:
	include/llvm/CodeGen/PBQP/Heuristics/Briggs.h
	include/llvm/CodeGen/RegAllocPBQP.h lib/CodeGen/RegAllocPBQP.cpp
In-Reply-To: <20100921131936.528C02A6C12C@llvm.org>
References: <20100921131936.528C02A6C12C@llvm.org>
Message-ID: <F11F3360-CC6D-4C9F-AADA-BD2C98535E86@2pi.dk>


On Sep 21, 2010, at 6:19 AM, Lang Hames wrote:

> Author: lhames
> Date: Tue Sep 21 08:19:36 2010
> New Revision: 114429
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114429&view=rev
> Log:
> Added an additional PBQP problem builder which adds coalescing costs (both between pairs of virtuals, and between virtuals and physicals).

> +std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
> +                                                MachineFunction *mf,
> +                                                const LiveIntervals *lis,
> +                                                const MachineLoopInfo *loopInfo,
> +                                                const RegSet &vregs) {
> +
> +  std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs);
> +  PBQP::Graph &g = p->getGraph();
> +
> +  const TargetMachine &tm = mf->getTarget();
> +  CoalescerPair cp(*tm.getInstrInfo(), *tm.getRegisterInfo());

Yay!

> +
> +  // Scan the machine function and add a coalescing cost whenever CoalescerPair
> +  // gives the Ok.
> +  for (MachineFunction::const_iterator mbbItr = mf->begin(),
> +                                       mbbEnd = mf->end();
> +       mbbItr != mbbEnd; ++mbbItr) {
> +    const MachineBasicBlock *mbb = &*mbbItr;
> +
> +    for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
> +                                           miEnd = mbb->end();
> +         miItr != miEnd; ++miItr) {
> +      const MachineInstr *mi = &*miItr;
> +
> +      if (!mi->isCopy() && !mi->isSubregToReg())
> +        continue; // Not coalescable.

This is pretty much the first line of setRegisters(), but it is harmless.

> +      if (!cp.setRegisters(mi))
> +        continue; // Not coalescable.
> +
> +      if (cp.getSrcReg() == cp.getDstReg())
> +        continue; // Already coalesced.
> +
> +      if (cp.isCoalescable(mi)) {

Note that isCoalescable(mi) is implied by setRegisters(mi) returning true. This method is intended to check whether a second copy instruction is compatible with the one given to setRegisters. Is is possible to have a copy between src and dst that is not compatible - it may copy different subregisters.

> +
> +        unsigned dst = cp.getDstReg(),
> +                 src = cp.getSrcReg();
> +

CoalescerPair can also handle subregister joins. In that case SrcReg is joined with a subregister of DstReg indicated by getSubIdx().

This is only relevant when joining two virtual registers. When DstReg is a physreg, it is simply adjusted so no SubIdx is necessary.


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From espindola at google.com  Tue Sep 21 09:49:54 2010
From: espindola at google.com (Rafael Espindola)
Date: Tue, 21 Sep 2010 10:49:54 -0400
Subject: [llvm-commits] Fwd: Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <AANLkTinw3YkO7VrW=g305kGspdgPqrGukv1X9oshpijf@mail.gmail.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
	<AANLkTin7esVNJY9rN6Cy242k-HqxX1zi5da+esYBpoKj@mail.gmail.com>
	<AANLkTikP9SZwbuRFk9yaQj33j4Jr3iTDC4+EsHB13kXd@mail.gmail.com>
	<AANLkTimKAX5XaDxAdiKuDp12gUDmBbs+BtdY1fx97tk9@mail.gmail.com>
	<AANLkTinw3YkO7VrW=g305kGspdgPqrGukv1X9oshpijf@mail.gmail.com>
Message-ID: <AANLkTimMvvDBN-pwjDXyVyPs_Hz_gC4pe1Ka93S3Yp5T@mail.gmail.com>

On 20 September 2010 16:45, Jason Kim <jasonwkim at google.com> wrote:
> Apologies once again. The whitespace issue in arm-mc-elf-s01.patch4
> has been fixed.

Hello Jason. With this patch I got the following failures in "make check-lit"

   LLVM :: CodeGen/ARM/2009-10-27-double-align.ll
    LLVM :: CodeGen/ARM/align.ll
    LLVM :: CodeGen/ARM/arguments-nosplit-double.ll
    LLVM :: CodeGen/ARM/arguments-nosplit-i64.ll
    LLVM :: CodeGen/ARM/arguments.ll
    LLVM :: CodeGen/ARM/ldrd.ll
    LLVM :: CodeGen/ARM/va_arg.ll
    LLVM :: CodeGen/Thumb2/thumb2-ldrd.ll

Cheers,
-- 
Rafael ?vila de Esp?ndola


From foldr at codedgers.com  Tue Sep 21 09:59:34 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Tue, 21 Sep 2010 14:59:34 -0000
Subject: [llvm-commits] [llvm] r114432 -
	/llvm/trunk/include/llvm/ADT/StringMap.h
Message-ID: <20100921145934.CAA032A6C12C@llvm.org>

Author: foldr
Date: Tue Sep 21 09:59:34 2010
New Revision: 114432

URL: http://llvm.org/viewvc/llvm-project?rev=114432&view=rev
Log:
Trailing whitespace.

Modified:
    llvm/trunk/include/llvm/ADT/StringMap.h

Modified: llvm/trunk/include/llvm/ADT/StringMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=114432&r1=114431&r2=114432&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/StringMap.h (original)
+++ llvm/trunk/include/llvm/ADT/StringMap.h Tue Sep 21 09:59:34 2010
@@ -137,8 +137,8 @@
   StringMapEntry(unsigned strLen, const ValueTy &V)
     : StringMapEntryBase(strLen), second(V) {}
 
-  StringRef getKey() const { 
-    return StringRef(getKeyData(), getKeyLength()); 
+  StringRef getKey() const {
+    return StringRef(getKeyData(), getKeyLength());
   }
 
   const ValueTy &getValue() const { return second; }
@@ -216,14 +216,14 @@
   static const StringMapEntry &GetStringMapEntryFromValue(const ValueTy &V) {
     return GetStringMapEntryFromValue(const_cast<ValueTy&>(V));
   }
-  
+
   /// GetStringMapEntryFromKeyData - Given key data that is known to be embedded
   /// into a StringMapEntry, return the StringMapEntry itself.
   static StringMapEntry &GetStringMapEntryFromKeyData(const char *KeyData) {
     char *Ptr = const_cast<char*>(KeyData) - sizeof(StringMapEntry<ValueTy>);
     return *reinterpret_cast<StringMapEntry*>(Ptr);
   }
-  
+
 
   /// Destroy - Destroy this StringMapEntry, releasing memory back to the
   /// specified allocator.
@@ -244,7 +244,7 @@
 
 template <typename T> struct ReferenceAdder { typedef T& result; };
 template <typename T> struct ReferenceAdder<T&> { typedef T result; };
-  
+
 /// StringMap - This is an unconventional map that is specialized for handling
 /// keys that are "strings", which are basically ranges of bytes. This does some
 /// funky memory allocation and hashing things to make it extremely efficient,
@@ -257,7 +257,7 @@
   StringMap() : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {}
   explicit StringMap(unsigned InitialSize)
     : StringMapImpl(InitialSize, static_cast<unsigned>(sizeof(MapEntryTy))) {}
-  
+
   explicit StringMap(AllocatorTy A)
     : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))), Allocator(A) {}
 



From foldr at codedgers.com  Tue Sep 21 09:59:42 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Tue, 21 Sep 2010 14:59:42 -0000
Subject: [llvm-commits] [llvm] r114433 - in /llvm/trunk:
 include/llvm/CompilerDriver/Tool.h lib/CompilerDriver/CompilationGraph.cpp
 test/LLVMC/MultipleOutputLanguages.td
 utils/TableGen/LLVMCConfigurationEmitter.cpp
Message-ID: <20100921145942.86ED42A6C12C@llvm.org>

Author: foldr
Date: Tue Sep 21 09:59:42 2010
New Revision: 114433

URL: http://llvm.org/viewvc/llvm-project?rev=114433&view=rev
Log:
llvmc: Allow multiple output languages.

Added:
    llvm/trunk/test/LLVMC/MultipleOutputLanguages.td
Modified:
    llvm/trunk/include/llvm/CompilerDriver/Tool.h
    llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp
    llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp

Modified: llvm/trunk/include/llvm/CompilerDriver/Tool.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CompilerDriver/Tool.h?rev=114433&r1=114432&r2=114433&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CompilerDriver/Tool.h (original)
+++ llvm/trunk/include/llvm/CompilerDriver/Tool.h Tue Sep 21 09:59:42 2010
@@ -58,7 +58,7 @@
 
     virtual const char*  Name() const = 0;
     virtual const char** InputLanguages() const = 0;
-    virtual const char*  OutputLanguage() const = 0;
+    virtual const char** OutputLanguages() const = 0;
 
     virtual bool IsJoin() const = 0;
     virtual bool WorksOnEmpty() const = 0;

Modified: llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp?rev=114433&r1=114432&r2=114433&view=diff
==============================================================================
--- llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp (original)
+++ llvm/trunk/lib/CompilerDriver/CompilationGraph.cpp Tue Sep 21 09:59:42 2010
@@ -440,13 +440,17 @@
           continue;
         }
 
-        const char* OutLang = N1.ToolPtr->OutputLanguage();
+        const char** OutLangs = N1.ToolPtr->OutputLanguages();
         const char** InLangs = N2->ToolPtr->InputLanguages();
         bool eq = false;
-        for (;*InLangs; ++InLangs) {
-          if (std::strcmp(OutLang, *InLangs) == 0) {
-            eq = true;
-            break;
+        const char* OutLang = 0;
+        for (;*OutLangs; ++OutLangs) {
+          OutLang = *OutLangs;
+          for (;*InLangs; ++InLangs) {
+            if (std::strcmp(OutLang, *InLangs) == 0) {
+              eq = true;
+              break;
+            }
           }
         }
 
@@ -481,7 +485,7 @@
   for (const_nodes_iterator B = this->NodesMap.begin(),
          E = this->NodesMap.end(); B != E; ++B) {
     const Node& N = B->second;
-    int MaxWeight = 0;
+    int MaxWeight = -1024;
 
     // Ignore the root node.
     if (!N.ToolPtr)
@@ -573,6 +577,26 @@
 
 // Code related to graph visualization.
 
+namespace {
+
+std::string SquashStrArray (const char** StrArr) {
+  std::string ret;
+
+  for (; *StrArr; ++StrArr) {
+    if (*(StrArr + 1)) {
+      ret += *StrArr;
+      ret +=  ", ";
+    }
+    else {
+      ret += *StrArr;
+    }
+  }
+
+  return ret;
+}
+
+} // End anonymous namespace.
+
 namespace llvm {
   template <>
   struct DOTGraphTraits<llvmc::CompilationGraph*>
@@ -587,7 +611,8 @@
         if (N->ToolPtr->IsJoin())
           return N->Name() + "\n (join" +
             (N->HasChildren() ? ")"
-             : std::string(": ") + N->ToolPtr->OutputLanguage() + ')');
+             : std::string(": ") +
+             SquashStrArray(N->ToolPtr->OutputLanguages()) + ')');
         else
           return N->Name();
       else
@@ -597,28 +622,15 @@
     template<typename EdgeIter>
     static std::string getEdgeSourceLabel(const Node* N, EdgeIter I) {
       if (N->ToolPtr) {
-        return N->ToolPtr->OutputLanguage();
+        return SquashStrArray(N->ToolPtr->OutputLanguages());
       }
       else {
-        const char** InLangs = I->ToolPtr->InputLanguages();
-        std::string ret;
-
-        for (; *InLangs; ++InLangs) {
-          if (*(InLangs + 1)) {
-            ret += *InLangs;
-            ret +=  ", ";
-          }
-          else {
-            ret += *InLangs;
-          }
-        }
-
-        return ret;
+        return SquashStrArray(I->ToolPtr->InputLanguages());
       }
     }
   };
 
-}
+} // End namespace llvm
 
 int CompilationGraph::writeGraph(const std::string& OutputFilename) {
   std::string ErrorInfo;

Added: llvm/trunk/test/LLVMC/MultipleOutputLanguages.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/MultipleOutputLanguages.td?rev=114433&view=auto
==============================================================================
--- llvm/trunk/test/LLVMC/MultipleOutputLanguages.td (added)
+++ llvm/trunk/test/LLVMC/MultipleOutputLanguages.td Tue Sep 21 09:59:42 2010
@@ -0,0 +1,27 @@
+// Check that multiple output languages work.
+// RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t
+// RUN: FileCheck -input-file %t %s
+// RUN: %compile_cxx %t
+// XFAIL: vg_leak
+
+include "llvm/CompilerDriver/Common.td"
+
+def dummy_tool : Tool<[
+    (command "dummy_cmd"),
+    (in_language "dummy_lang"),
+    (out_language ["another_dummy_lang", "yet_another_dummy_lang"])
+]>;
+
+def another_dummy_tool : Tool<[
+    (command "another_dummy_cmd"),
+    (in_language ["another_dummy_lang", "some_other_dummy_lang"]),
+    (out_language "executable"),
+    (join)
+]>;
+
+// CHECK: new SimpleEdge("dummy_tool")
+// CHECK: new SimpleEdge("another_dummy_tool")
+def DummyGraph : CompilationGraph<[
+    (edge "root", "dummy_tool"),
+    (edge "dummy_tool", "another_dummy_tool")
+]>;

Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=114433&r1=114432&r2=114433&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Sep 21 09:59:42 2010
@@ -833,7 +833,7 @@
   StrVector InLanguage;
   std::string InFileOption;
   std::string OutFileOption;
-  std::string OutLanguage;
+  StrVector OutLanguage;
   std::string OutputSuffix;
   unsigned Flags;
   const Init* OnEmpty;
@@ -919,41 +919,43 @@
     toolDesc_.CmdLine = d.getArg(0);
   }
 
-  void onInLanguage (const DagInit& d) {
+  /// onInOutLanguage - Common implementation of on{In,Out}Language().
+  void onInOutLanguage (const DagInit& d, StrVector& OutVec) {
     CheckNumberOfArguments(d, 1);
     Init* arg = d.getArg(0);
 
     // Find out the argument's type.
     if (typeid(*arg) == typeid(StringInit)) {
       // It's a string.
-      toolDesc_.InLanguage.push_back(InitPtrToString(arg));
+      OutVec.push_back(InitPtrToString(arg));
     }
     else {
       // It's a list.
       const ListInit& lst = InitPtrToList(arg);
-      StrVector& out = toolDesc_.InLanguage;
 
       // Copy strings to the output vector.
-      for (ListInit::const_iterator B = lst.begin(), E = lst.end();
-           B != E; ++B) {
-        out.push_back(InitPtrToString(*B));
-      }
+      for (ListInit::const_iterator B = lst.begin(), E = lst.end(); B != E; ++B)
+        OutVec.push_back(InitPtrToString(*B));
 
       // Remove duplicates.
-      std::sort(out.begin(), out.end());
-      StrVector::iterator newE = std::unique(out.begin(), out.end());
-      out.erase(newE, out.end());
+      std::sort(OutVec.begin(), OutVec.end());
+      StrVector::iterator newE = std::unique(OutVec.begin(), OutVec.end());
+      OutVec.erase(newE, OutVec.end());
     }
   }
 
+
+  void onInLanguage (const DagInit& d) {
+    this->onInOutLanguage(d, toolDesc_.InLanguage);
+  }
+
   void onJoin (const DagInit& d) {
     CheckNumberOfArguments(d, 0);
     toolDesc_.setJoin();
   }
 
   void onOutLanguage (const DagInit& d) {
-    CheckNumberOfArguments(d, 1);
-    toolDesc_.OutLanguage = InitPtrToString(d.getArg(0));
+    this->onInOutLanguage(d, toolDesc_.OutLanguage);
   }
 
   void onOutFileOption (const DagInit& d) {
@@ -1062,47 +1064,62 @@
 }
 
 /// FillInToolToLang - Fills in two tables that map tool names to
-/// (input, output) languages.  Helper function used by TypecheckGraph().
+/// input & output language names.  Helper function used by TypecheckGraph().
 void FillInToolToLang (const ToolDescriptions& ToolDescs,
                        StringMap<StringSet<> >& ToolToInLang,
-                       StringMap<std::string>& ToolToOutLang) {
+                       StringMap<StringSet<> >& ToolToOutLang) {
   for (ToolDescriptions::const_iterator B = ToolDescs.begin(),
          E = ToolDescs.end(); B != E; ++B) {
     const ToolDescription& D = *(*B);
     for (StrVector::const_iterator B = D.InLanguage.begin(),
            E = D.InLanguage.end(); B != E; ++B)
       ToolToInLang[D.Name].insert(*B);
-    ToolToOutLang[D.Name] = D.OutLanguage;
+    for (StrVector::const_iterator B = D.OutLanguage.begin(),
+           E = D.OutLanguage.end(); B != E; ++B)
+      ToolToOutLang[D.Name].insert(*B);
   }
 }
 
+/// Intersect - Is set intersection non-empty?
+bool Intersect (const StringSet<>& S1, const StringSet<>& S2) {
+  for (StringSet<>::const_iterator B = S1.begin(), E = S1.end(); B != E; ++B) {
+    if (S2.count(B->first()) != 0)
+      return true;
+  }
+  return false;
+}
+
 /// TypecheckGraph - Check that names for output and input languages
 /// on all edges do match.
 void TypecheckGraph (const DagVector& EdgeVector,
                      const ToolDescriptions& ToolDescs) {
   StringMap<StringSet<> > ToolToInLang;
-  StringMap<std::string> ToolToOutLang;
+  StringMap<StringSet<> > ToolToOutLang;
 
   FillInToolToLang(ToolDescs, ToolToInLang, ToolToOutLang);
-  StringMap<std::string>::iterator IAE = ToolToOutLang.end();
-  StringMap<StringSet<> >::iterator IBE = ToolToInLang.end();
 
   for (DagVector::const_iterator B = EdgeVector.begin(),
          E = EdgeVector.end(); B != E; ++B) {
     const DagInit* Edge = *B;
     const std::string& NodeA = InitPtrToString(Edge->getArg(0));
     const std::string& NodeB = InitPtrToString(Edge->getArg(1));
-    StringMap<std::string>::iterator IA = ToolToOutLang.find(NodeA);
+    StringMap<StringSet<> >::iterator IA = ToolToOutLang.find(NodeA);
     StringMap<StringSet<> >::iterator IB = ToolToInLang.find(NodeB);
 
+    if (NodeB == "root")
+      throw "Edges back to the root are not allowed!";
+
     if (NodeA != "root") {
-      if (IA != IAE && IB != IBE && IB->second.count(IA->second) == 0)
+      if (IA == ToolToOutLang.end())
+        throw NodeA + ": no output language defined!";
+      if (IB == ToolToInLang.end())
+        throw NodeB + ": no input language defined!";
+
+      if (!Intersect(IA->second, IB->second)) {
         throw "Edge " + NodeA + "->" + NodeB
           + ": output->input language mismatch";
+      }
     }
-
-    if (NodeB == "root")
-      throw "Edges back to the root are not allowed!";
   }
 }
 
@@ -2250,11 +2267,8 @@
   O.indent(Indent2) << "return InputLanguages_;\n";
   O.indent(Indent1) << "}\n\n";
 
-  if (D.OutLanguage.empty())
-    throw "Tool " + D.Name + " has no 'out_language' property!";
-
-  O.indent(Indent1) << "const char* OutputLanguage() const {\n";
-  O.indent(Indent2) << "return \"" << D.OutLanguage << "\";\n";
+  O.indent(Indent1) << "const char** OutputLanguages() const {\n";
+  O.indent(Indent2) << "return OutputLanguages_;\n";
   O.indent(Indent1) << "}\n\n";
 }
 
@@ -2299,17 +2313,28 @@
   O.indent(Indent1) << "}\n\n";
 }
 
+/// EmitStrArray - Emit definition of a 'const char**' static member
+/// variable. Helper used by EmitStaticMemberDefinitions();
+void EmitStrArray(const std::string& Name, const std::string& VarName,
+                  const StrVector& StrVec, raw_ostream& O) {
+  O << "const char* " << Name << "::" << VarName << "[] = {";
+  for (StrVector::const_iterator B = StrVec.begin(), E = StrVec.end();
+       B != E; ++B)
+    O << '\"' << *B << "\", ";
+  O << "0};\n";
+}
+
 /// EmitStaticMemberDefinitions - Emit static member definitions for a
 /// given Tool class.
 void EmitStaticMemberDefinitions(const ToolDescription& D, raw_ostream& O) {
   if (D.InLanguage.empty())
     throw "Tool " + D.Name + " has no 'in_language' property!";
+  if (D.OutLanguage.empty())
+    throw "Tool " + D.Name + " has no 'out_language' property!";
 
-  O << "const char* " << D.Name << "::InputLanguages_[] = {";
-  for (StrVector::const_iterator B = D.InLanguage.begin(),
-         E = D.InLanguage.end(); B != E; ++B)
-    O << '\"' << *B << "\", ";
-  O << "0};\n\n";
+  EmitStrArray(D.Name, "InputLanguages_", D.InLanguage, O);
+  EmitStrArray(D.Name, "OutputLanguages_", D.OutLanguage, O);
+  O << '\n';
 }
 
 /// EmitToolClassDefinition - Emit a Tool class definition.
@@ -2327,7 +2352,8 @@
     O << "Tool";
 
   O << " {\nprivate:\n";
-  O.indent(Indent1) << "static const char* InputLanguages_[];\n\n";
+  O.indent(Indent1) << "static const char* InputLanguages_[];\n";
+  O.indent(Indent1) << "static const char* OutputLanguages_[];\n\n";
 
   O << "public:\n";
   EmitNameMethod(D, O);



From foldr at codedgers.com  Tue Sep 21 09:59:47 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Tue, 21 Sep 2010 14:59:47 -0000
Subject: [llvm-commits] [llvm] r114434 -
	/llvm/trunk/tools/llvmc/src/Base.td.in
Message-ID: <20100921145947.416EC2A6C12D@llvm.org>

Author: foldr
Date: Tue Sep 21 09:59:47 2010
New Revision: 114434

URL: http://llvm.org/viewvc/llvm-project?rev=114434&view=rev
Log:
llvmc: split llvm_gcc_based into llvm_gcc_{pch,comp}_based.

Modified:
    llvm/trunk/tools/llvmc/src/Base.td.in

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=114434&r1=114433&r2=114434&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Tue Sep 21 09:59:47 2010
@@ -165,10 +165,10 @@
 // Tools
 
 class llvm_gcc_based <string cmd, string in_lang,
-                      string E_ext, string out_lang> : Tool<
+                      string E_ext, string out_lang, string out_ext> : Tool<
 [(in_language in_lang),
- (out_language "llvm-bitcode"),
- (output_suffix out_lang),
+ (out_language out_lang),
+ (output_suffix out_ext),
  (command cmd),
  (actions
      (case
@@ -214,24 +214,29 @@
  (sink)
 ]>;
 
-def llvm_gcc_c : llvm_gcc_based<"@LLVMGCCCOMMAND@ -x c", "c", "i", "bc">;
-def llvm_gcc_cpp : llvm_gcc_based<"@LLVMGXXCOMMAND@ -x c++", "c++", "i", "bc">;
-def llvm_gcc_m : llvm_gcc_based<"@LLVMGCCCOMMAND@ -x objective-c",
-                                                  "objective-c", "mi", "bc">;
-def llvm_gcc_mxx : llvm_gcc_based<"@LLVMGCCCOMMAND@ -x objective-c++",
-                                  "objective-c++", "mi", "bc">;
-
-def llvm_gcc_c_pch : llvm_gcc_based<"@LLVMGCCCOMMAND@ -x c-header",
-                                                      "c-header", "i", "gch">;
-def llvm_gcc_cpp_pch : llvm_gcc_based<"@LLVMGXXCOMMAND@ -x c++-header",
-                                                        "c++-header",
-                                                        "i", "gch">;
-def llvm_gcc_m_pch : llvm_gcc_based<"@LLVMGCCCOMMAND@ -x objective-c-header",
-                                                      "objective-c-header",
-                                                      "mi", "gch">;
-def llvm_gcc_mxx_pch
-    : llvm_gcc_based<"@LLVMGCCCOMMAND@ -x objective-c++-header",
-                                       "objective-c++-header", "mi", "gch">;
+class llvm_gcc_comp_based <string cmd, string in_lang, string E_ext>
+: llvm_gcc_based<cmd, in_lang, E_ext, "llvm-bitcode", "bc">;
+
+class llvm_gcc_pch_based <string cmd, string in_lang, string E_ext>
+: llvm_gcc_based<cmd, in_lang, E_ext, "precompiled-header", "gch">;
+
+def llvm_gcc_c : llvm_gcc_comp_based
+    <"@LLVMGCCCOMMAND@ -x c", "c", "i">;
+def llvm_gcc_cpp : llvm_gcc_comp_based
+    <"@LLVMGXXCOMMAND@ -x c++", "c++", "i">;
+def llvm_gcc_m : llvm_gcc_comp_based
+    <"@LLVMGCCCOMMAND@ -x objective-c", "objective-c", "mi">;
+def llvm_gcc_mxx : llvm_gcc_comp_based
+    <"@LLVMGCCCOMMAND@ -x objective-c++", "objective-c++", "mi">;
+
+def llvm_gcc_c_pch : llvm_gcc_pch_based
+    <"@LLVMGCCCOMMAND@ -x c-header", "c-header", "i">;
+def llvm_gcc_cpp_pch : llvm_gcc_pch_based
+    <"@LLVMGXXCOMMAND@ -x c++-header", "c++-header", "i">;
+def llvm_gcc_m_pch : llvm_gcc_pch_based
+    <"@LLVMGCCCOMMAND@ -x objective-c-header", "objective-c-header", "mi">;
+def llvm_gcc_mxx_pch : llvm_gcc_pch_based
+    <"@LLVMGCCCOMMAND@ -x objective-c++-header", "objective-c++-header", "mi">;
 
 def opt : Tool<
 [(in_language "llvm-bitcode"),
@@ -343,6 +348,7 @@
 // Language map
 
 def LanguageMap : LanguageMap<[
+    (lang_to_suffixes "precompiled-header", ["gch", "pch"]),
     (lang_to_suffixes "c++", ["cc", "cp", "cxx", "cpp", "CPP", "c++", "C"]),
     (lang_to_suffixes "c++-header", "hpp"),
     (lang_to_suffixes "c", "c"),



From foldr at codedgers.com  Tue Sep 21 09:59:51 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Tue, 21 Sep 2010 14:59:51 -0000
Subject: [llvm-commits] [llvm] r114435 - /llvm/trunk/utils/TableGen/Record.h
Message-ID: <20100921145951.1BC0C2A6C12C@llvm.org>

Author: foldr
Date: Tue Sep 21 09:59:50 2010
New Revision: 114435

URL: http://llvm.org/viewvc/llvm-project?rev=114435&view=rev
Log:
Trailing whitespace, 80-col violations.

Modified:
    llvm/trunk/utils/TableGen/Record.h

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=114435&r1=114434&r2=114435&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Tue Sep 21 09:59:50 2010
@@ -1233,10 +1233,10 @@
     ID(LastID++), Name(N), Loc(loc) {}
   ~Record() {}
 
-  
+
   static unsigned getNewUID() { return LastID++; }
-    
-    
+
+
   unsigned getID() const { return ID; }
 
   const std::string &getName() const { return Name; }
@@ -1350,9 +1350,9 @@
   ///
   std::vector<Record*> getValueAsListOfDefs(StringRef FieldName) const;
 
-  /// getValueAsListOfInts - This method looks up the specified field and returns
-  /// its value as a vector of integers, throwing an exception if the field does
-  /// not exist or if the value is not the right type.
+  /// getValueAsListOfInts - This method looks up the specified field and
+  /// returns its value as a vector of integers, throwing an exception if the
+  /// field does not exist or if the value is not the right type.
   ///
   std::vector<int64_t> getValueAsListOfInts(StringRef FieldName) const;
 



From espindola at google.com  Tue Sep 21 10:26:23 2010
From: espindola at google.com (Rafael Espindola)
Date: Tue, 21 Sep 2010 11:26:23 -0400
Subject: [llvm-commits] Chat with Shih-wei Liao
In-Reply-To: <AANLkTikwgLLcTaSO8OQXzvR_=JtJJacs_Er=w0OiOwcM@mail.gmail.com>
References: <8626877.5419113.1285074362710.chat@gmail.com>
	<AANLkTikwgLLcTaSO8OQXzvR_=JtJJacs_Er=w0OiOwcM@mail.gmail.com>
Message-ID: <AANLkTim+kqt4yMfqJJP8VKgDTvefEbBT0+nitk9F8ro+@mail.gmail.com>

On 21 September 2010 09:44, Rafael Espindola <espindola at google.com> wrote:
> On 21 September 2010 09:06, Shih-wei Liao <sliao at google.com> wrote:
>>
>> These messages were sent while you were offline.
>> 09:06?Shih-wei: What do you think of submitting a proposal to LLVM devmtg on
>> portable bitcode?
>> ??Today is LLVM devmtg's deadline
>
> The NaCl guys are likely to give a talk. I don't know exactly about
> what. I assume we can get the interested parties to chat about it
> during a break of after the meeting proper.

OK, I am not currently working on this (doing MC work instead), but I
did put some time on this problem in the past and I think we could use
the meeting (or at least my trip to the area) to discuss it a bit and
hopefully avoid surprises along the way for anyone trying this. In
particular, I think it could be useful to discuss

* Why with a single .bc file you cannot satisfy all the currently
existing ABIs (x86, x86-64, ARM, etc)
* What should be done about the ABI?
  * Should new binary ABIs be defined or should linking of binary
files not be supported?
  * A ABI subset just sufficient for the system libraries maybe?
  * Should an ABI be defined for LLVM IL or should linking of LLVM
bitcodes be done on the dev workstation?
  * Even if an ABI is not defined at the LLVM level, what restrictions
there would be to changing the IL definition
    of some functions?
  * The effect of future LLVM IL changes.

Cheers,
-- 
Rafael ?vila de Esp?ndola


From sabre at nondot.org  Tue Sep 21 10:47:00 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 15:47:00 -0000
Subject: [llvm-commits] [llvm] r114436 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20100921154700.17D132A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 10:46:59 2010
New Revision: 114436

URL: http://llvm.org/viewvc/llvm-project?rev=114436&view=rev
Log:
substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps.
no functionality change (step #1)

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114436&r1=114435&r2=114436&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 10:46:59 2010
@@ -6582,100 +6582,91 @@
 
   // If this is a select from two identical things, try to pull the operation
   // through the select.
-  if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
-    // If this is a load and the token chain is identical, replace the select
-    // of two loads with a load through a select of the address to load from.
-    // This triggers in things like "select bool X, 10.0, 123.0" after the FP
-    // constants have been dropped into the constant pool.
-    if (LHS.getOpcode() == ISD::LOAD &&
+  if (LHS.getOpcode() != RHS.getOpcode() ||
+      !LHS.hasOneUse() || !RHS.hasOneUse())
+    return false;
+  
+  // If this is a load and the token chain is identical, replace the select
+  // of two loads with a load through a select of the address to load from.
+  // This triggers in things like "select bool X, 10.0, 123.0" after the FP
+  // constants have been dropped into the constant pool.
+  if (LHS.getOpcode() == ISD::LOAD) {
+    LoadSDNode *LLD = cast<LoadSDNode>(LHS);
+    LoadSDNode *RLD = cast<LoadSDNode>(RHS);
+    
+    // Token chains must be identical.
+    if (LHS.getOperand(0) != RHS.getOperand(0) ||
         // Do not let this transformation reduce the number of volatile loads.
-        !cast<LoadSDNode>(LHS)->isVolatile() &&
-        !cast<LoadSDNode>(RHS)->isVolatile() &&
-        // Token chains must be identical.
-        LHS.getOperand(0) == RHS.getOperand(0)) {
-      LoadSDNode *LLD = cast<LoadSDNode>(LHS);
-      LoadSDNode *RLD = cast<LoadSDNode>(RHS);
-
-      // If this is an EXTLOAD, the VT's must match.
-      if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
+        LLD->isVolatile() || RLD->isVolatile() ||
+        // If this is an EXTLOAD, the VT's must match.
+        LLD->getMemoryVT() != RLD->getMemoryVT() ||
         // FIXME: this discards src value information.  This is
         // over-conservative. It would be beneficial to be able to remember
         // both potential memory locations.  Since we are discarding
         // src value info, don't do the transformation if the memory
         // locations are not in the default address space.
-        unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
-        if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
-          if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
-            LLDAddrSpace = PT->getAddressSpace();
-        }
-        if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
-          if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
-            RLDAddrSpace = PT->getAddressSpace();
-        }
-        SDValue Addr;
-        if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
-          if (TheSelect->getOpcode() == ISD::SELECT) {
-            // Check that the condition doesn't reach either load.  If so, folding
-            // this will induce a cycle into the DAG.
-            if ((!LLD->hasAnyUseOfValue(1) ||
-                 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
-                (!RLD->hasAnyUseOfValue(1) ||
-                 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
-              Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
-                                 LLD->getBasePtr().getValueType(),
-                                 TheSelect->getOperand(0), LLD->getBasePtr(),
-                                 RLD->getBasePtr());
-            }
-          } else {
-            // Check that the condition doesn't reach either load.  If so, folding
-            // this will induce a cycle into the DAG.
-            if ((!LLD->hasAnyUseOfValue(1) ||
-                 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
-                  !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
-                (!RLD->hasAnyUseOfValue(1) ||
-                 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
-                  !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
-              Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
-                                 LLD->getBasePtr().getValueType(),
-                                 TheSelect->getOperand(0),
-                                 TheSelect->getOperand(1),
-                                 LLD->getBasePtr(), RLD->getBasePtr(),
-                                 TheSelect->getOperand(4));
-            }
-          }
-        }
+        LLD->getPointerInfo().getAddrSpace() != 0 ||
+        RLD->getPointerInfo().getAddrSpace() != 0)
+      return false;
+        
+    SDValue Addr;
+    if (TheSelect->getOpcode() == ISD::SELECT) {
+      // Check that the condition doesn't reach either load.  If so, folding
+      // this will induce a cycle into the DAG.
+      if ((!LLD->hasAnyUseOfValue(1) ||
+           !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
+          (!RLD->hasAnyUseOfValue(1) ||
+           !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
+        Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
+                           LLD->getBasePtr().getValueType(),
+                           TheSelect->getOperand(0), LLD->getBasePtr(),
+                           RLD->getBasePtr());
+      }
+    } else {  // Otherwise SELECT_CC
+      // Check that the condition doesn't reach either load.  If so, folding
+      // this will induce a cycle into the DAG.
+      if ((!LLD->hasAnyUseOfValue(1) ||
+           (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+            !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
+          (!RLD->hasAnyUseOfValue(1) ||
+           (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+            !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
+        Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
+                           LLD->getBasePtr().getValueType(),
+                           TheSelect->getOperand(0),
+                           TheSelect->getOperand(1),
+                           LLD->getBasePtr(), RLD->getBasePtr(),
+                           TheSelect->getOperand(4));
+      }
+    }
 
-        if (Addr.getNode()) {
-          SDValue Load;
-          if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
-            Load = DAG.getLoad(TheSelect->getValueType(0),
-                               TheSelect->getDebugLoc(),
-                               LLD->getChain(),
-                               Addr, 0, 0,
-                               LLD->isVolatile(),
-                               LLD->isNonTemporal(),
-                               LLD->getAlignment());
-          } else {
-            Load = DAG.getExtLoad(LLD->getExtensionType(),
-                                  TheSelect->getValueType(0),
-                                  TheSelect->getDebugLoc(),
-                                  LLD->getChain(), Addr, 0, 0,
-                                  LLD->getMemoryVT(),
-                                  LLD->isVolatile(),
-                                  LLD->isNonTemporal(),
-                                  LLD->getAlignment());
-          }
-
-          // Users of the select now use the result of the load.
-          CombineTo(TheSelect, Load);
-
-          // Users of the old loads now use the new load's chain.  We know the
-          // old-load value is dead now.
-          CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
-          CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
-          return true;
-        }
+    if (Addr.getNode()) {
+      SDValue Load;
+      if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
+        Load = DAG.getLoad(TheSelect->getValueType(0),
+                           TheSelect->getDebugLoc(),
+                           // FIXME: Discards pointer info.
+                           LLD->getChain(), Addr, MachinePointerInfo(),
+                           LLD->isVolatile(), LLD->isNonTemporal(),
+                           LLD->getAlignment());
+      } else {
+        Load = DAG.getExtLoad(LLD->getExtensionType(),
+                              TheSelect->getValueType(0),
+                              TheSelect->getDebugLoc(),
+                              // FIXME: Discards pointer info.
+                              LLD->getChain(), Addr, MachinePointerInfo(),
+                              LLD->getMemoryVT(), LLD->isVolatile(),
+                              LLD->isNonTemporal(), LLD->getAlignment());
       }
+
+      // Users of the select now use the result of the load.
+      CombineTo(TheSelect, Load);
+
+      // Users of the old loads now use the new load's chain.  We know the
+      // old-load value is dead now.
+      CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
+      CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
+      return true;
     }
   }
 



From sabre at nondot.org  Tue Sep 21 10:58:55 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 15:58:55 -0000
Subject: [llvm-commits] [llvm] r114437 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20100921155855.E433C2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 10:58:55 2010
New Revision: 114437

URL: http://llvm.org/viewvc/llvm-project?rev=114437&view=rev
Log:
simplify DAGCombiner::SimplifySelectOps step #2/2.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114437&r1=114436&r2=114437&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 10:58:55 2010
@@ -6609,65 +6609,63 @@
         RLD->getPointerInfo().getAddrSpace() != 0)
       return false;
         
+    // Check that the select condition doesn't reach either load.  If so,
+    // folding this will induce a cycle into the DAG.  If not, this is safe to
+    // xform, so create a select of the addresses.
     SDValue Addr;
     if (TheSelect->getOpcode() == ISD::SELECT) {
-      // Check that the condition doesn't reach either load.  If so, folding
-      // this will induce a cycle into the DAG.
-      if ((!LLD->hasAnyUseOfValue(1) ||
-           !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
-          (!RLD->hasAnyUseOfValue(1) ||
-           !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
-        Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
-                           LLD->getBasePtr().getValueType(),
-                           TheSelect->getOperand(0), LLD->getBasePtr(),
-                           RLD->getBasePtr());
-      }
+      SDNode *CondNode = TheSelect->getOperand(0).getNode();
+      if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
+          (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
+        return false;
+      Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
+                         LLD->getBasePtr().getValueType(),
+                         TheSelect->getOperand(0), LLD->getBasePtr(),
+                         RLD->getBasePtr());
     } else {  // Otherwise SELECT_CC
-      // Check that the condition doesn't reach either load.  If so, folding
-      // this will induce a cycle into the DAG.
-      if ((!LLD->hasAnyUseOfValue(1) ||
-           (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
-            !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
-          (!RLD->hasAnyUseOfValue(1) ||
-           (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
-            !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
-        Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
-                           LLD->getBasePtr().getValueType(),
-                           TheSelect->getOperand(0),
-                           TheSelect->getOperand(1),
-                           LLD->getBasePtr(), RLD->getBasePtr(),
-                           TheSelect->getOperand(4));
-      }
-    }
-
-    if (Addr.getNode()) {
-      SDValue Load;
-      if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
-        Load = DAG.getLoad(TheSelect->getValueType(0),
-                           TheSelect->getDebugLoc(),
-                           // FIXME: Discards pointer info.
-                           LLD->getChain(), Addr, MachinePointerInfo(),
-                           LLD->isVolatile(), LLD->isNonTemporal(),
-                           LLD->getAlignment());
-      } else {
-        Load = DAG.getExtLoad(LLD->getExtensionType(),
-                              TheSelect->getValueType(0),
-                              TheSelect->getDebugLoc(),
-                              // FIXME: Discards pointer info.
-                              LLD->getChain(), Addr, MachinePointerInfo(),
-                              LLD->getMemoryVT(), LLD->isVolatile(),
-                              LLD->isNonTemporal(), LLD->getAlignment());
-      }
-
-      // Users of the select now use the result of the load.
-      CombineTo(TheSelect, Load);
+      SDNode *CondLHS = TheSelect->getOperand(0).getNode();
+      SDNode *CondRHS = TheSelect->getOperand(1).getNode();
 
-      // Users of the old loads now use the new load's chain.  We know the
-      // old-load value is dead now.
-      CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
-      CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
-      return true;
-    }
+      if ((LLD->hasAnyUseOfValue(1) &&
+           (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
+          (LLD->hasAnyUseOfValue(1) &&
+           (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
+        return false;
+      
+      Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
+                         LLD->getBasePtr().getValueType(),
+                         TheSelect->getOperand(0),
+                         TheSelect->getOperand(1),
+                         LLD->getBasePtr(), RLD->getBasePtr(),
+                         TheSelect->getOperand(4));
+    }
+
+    SDValue Load;
+    if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
+      Load = DAG.getLoad(TheSelect->getValueType(0),
+                         TheSelect->getDebugLoc(),
+                         // FIXME: Discards pointer info.
+                         LLD->getChain(), Addr, MachinePointerInfo(),
+                         LLD->isVolatile(), LLD->isNonTemporal(),
+                         LLD->getAlignment());
+    } else {
+      Load = DAG.getExtLoad(LLD->getExtensionType(),
+                            TheSelect->getValueType(0),
+                            TheSelect->getDebugLoc(),
+                            // FIXME: Discards pointer info.
+                            LLD->getChain(), Addr, MachinePointerInfo(),
+                            LLD->getMemoryVT(), LLD->isVolatile(),
+                            LLD->isNonTemporal(), LLD->getAlignment());
+    }
+
+    // Users of the select now use the result of the load.
+    CombineTo(TheSelect, Load);
+
+    // Users of the old loads now use the new load's chain.  We know the
+    // old-load value is dead now.
+    CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
+    CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
+    return true;
   }
 
   return false;



From benny.kra at googlemail.com  Tue Sep 21 11:00:03 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 21 Sep 2010 16:00:03 -0000
Subject: [llvm-commits] [llvm] r114439 - in /llvm/trunk:
 include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp
Message-ID: <20100921160003.A40DB2A6C12D@llvm.org>

Author: d0k
Date: Tue Sep 21 11:00:03 2010
New Revision: 114439

URL: http://llvm.org/viewvc/llvm-project?rev=114439&view=rev
Log:
Make CreateComplexVariable independent of SmallVector.

Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DebugInfo.cpp

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=114439&r1=114438&r2=114439&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Sep 21 11:00:03 2010
@@ -726,10 +726,9 @@
     /// CreateComplexVariable - Create a new descriptor for the specified
     /// variable which has a complex address expression for its address.
     DIVariable CreateComplexVariable(unsigned Tag, DIDescriptor Context,
-                                     const std::string &Name,
-                                     DIFile F, unsigned LineNo,
-                                     DIType Ty,
-                                     SmallVector<Value *, 9> &addr);
+                                     StringRef Name, DIFile F, unsigned LineNo,
+                                     DIType Ty, Value *const *Addr,
+                                     unsigned NumAddr);
 
     /// CreateLexicalBlock - This creates a descriptor for a lexical block
     /// with the specified parent context.

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=114439&r1=114438&r2=114439&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Sep 21 11:00:03 2010
@@ -1181,21 +1181,20 @@
 /// CreateComplexVariable - Create a new descriptor for the specified variable
 /// which has a complex address expression for its address.
 DIVariable DIFactory::CreateComplexVariable(unsigned Tag, DIDescriptor Context,
-                                            const std::string &Name,
-                                            DIFile F,
+                                            StringRef Name, DIFile F,
                                             unsigned LineNo,
-                                            DIType Ty,
-                                            SmallVector<Value *, 9> &addr) {
-  SmallVector<Value *, 9> Elts;
+                                            DIType Ty, Value *const *Addr,
+                                            unsigned NumAddr) {
+  SmallVector<Value *, 15> Elts;
   Elts.push_back(GetTagConstant(Tag));
   Elts.push_back(Context);
   Elts.push_back(MDString::get(VMContext, Name));
   Elts.push_back(F);
   Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo));
   Elts.push_back(Ty);
-  Elts.insert(Elts.end(), addr.begin(), addr.end());
+  Elts.append(Addr, Addr+NumAddr);
 
-  return DIVariable(MDNode::get(VMContext, &Elts[0], 6+addr.size()));
+  return DIVariable(MDNode::get(VMContext, Elts.data(), Elts.size()));
 }
 
 



From sabre at nondot.org  Tue Sep 21 11:08:50 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 16:08:50 -0000
Subject: [llvm-commits] [llvm] r114442 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20100921160850.EE3022A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 11:08:50 2010
New Revision: 114442

URL: http://llvm.org/viewvc/llvm-project?rev=114442&view=rev
Log:
convert dagcombine off the old form of getLoad.  This fixes several bugs 
with SVOffset computation.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114442&r1=114441&r2=114442&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 11:08:50 2010
@@ -4107,10 +4107,10 @@
 
     SDValue Load = (ExtType == ISD::NON_EXTLOAD)
       ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
-                    LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
+                    LN0->getPointerInfo().getWithOffset(PtrOff),
                     LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
       : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
-                       LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
+                       LN0->getPointerInfo().getWithOffset(PtrOff),
                        ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
                        NewAlign);
 
@@ -4295,7 +4295,9 @@
 
   LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
   LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
-  if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
+  if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
+      LD1->getPointerInfo().getAddrSpace() !=
+         LD2->getPointerInfo().getAddrSpace())
     return SDValue();
   EVT LD1VT = LD1->getValueType(0);
 
@@ -4313,8 +4315,8 @@
     if (NewAlign <= Align &&
         (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
       return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
-                         LD1->getBasePtr(), LD1->getSrcValue(),
-                         LD1->getSrcValueOffset(), false, false, Align);
+                         LD1->getBasePtr(), LD1->getPointerInfo(),
+                         false, false, Align);
   }
 
   return SDValue();
@@ -4382,8 +4384,7 @@
 
     if (Align <= OrigAlign) {
       SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
-                                 LN0->getBasePtr(),
-                                 LN0->getSrcValue(), LN0->getSrcValueOffset(),
+                                 LN0->getBasePtr(), LN0->getPointerInfo(),
                                  LN0->isVolatile(), LN0->isNonTemporal(),
                                  OrigAlign);
       AddToWorkList(N);
@@ -5587,15 +5588,13 @@
       // Replace the chain to void dependency.
       if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
         ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
-                               BetterChain, Ptr,
-                               LD->getSrcValue(), LD->getSrcValueOffset(),
+                               BetterChain, Ptr, LD->getPointerInfo(),
                                LD->isVolatile(), LD->isNonTemporal(),
                                LD->getAlignment());
       } else {
         ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
                                   LD->getDebugLoc(),
-                                  BetterChain, Ptr, LD->getSrcValue(),
-                                  LD->getSrcValueOffset(),
+                                  BetterChain, Ptr, LD->getPointerInfo(),
                                   LD->getMemoryVT(),
                                   LD->isVolatile(),
                                   LD->isNonTemporal(),
@@ -5801,7 +5800,9 @@
   if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
       Chain == SDValue(N0.getNode(), 1)) {
     LoadSDNode *LD = cast<LoadSDNode>(N0);
-    if (LD->getBasePtr() != Ptr)
+    if (LD->getBasePtr() != Ptr ||
+        LD->getPointerInfo().getAddrSpace() !=
+        ST->getPointerInfo().getAddrSpace())
       return SDValue();
 
     // Find the type to narrow it the load / op / store to.
@@ -5850,14 +5851,14 @@
                                    DAG.getConstant(PtrOff, Ptr.getValueType()));
       SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
                                   LD->getChain(), NewPtr,
-                                  LD->getSrcValue(), LD->getSrcValueOffset(),
+                                  LD->getPointerInfo().getWithOffset(PtrOff),
                                   LD->isVolatile(), LD->isNonTemporal(),
                                   NewAlign);
       SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
                                    DAG.getConstant(NewImm, NewVT));
       SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
                                    NewVal, NewPtr,
-                                   ST->getSrcValue(), ST->getSrcValueOffset(),
+                                   ST->getPointerInfo().getWithOffset(PtrOff),
                                    false, false, NewAlign);
 
       AddToWorkList(NewPtr.getNode());
@@ -6204,8 +6205,9 @@
     }
 
     SDValue NewPtr = LN0->getBasePtr();
+    unsigned PtrOff = 0;
     if (Elt) {
-      unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
+      PtrOff = LVT.getSizeInBits() * Elt / 8;
       EVT PtrType = NewPtr.getValueType();
       if (TLI.isBigEndian())
         PtrOff = VT.getSizeInBits() / 8 - PtrOff;
@@ -6214,7 +6216,7 @@
     }
 
     return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
-                       LN0->getSrcValue(), LN0->getSrcValueOffset(),
+                       LN0->getPointerInfo().getWithOffset(PtrOff),
                        LN0->isVolatile(), LN0->isNonTemporal(), Align);
   }
 



From sabre at nondot.org  Tue Sep 21 11:36:31 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 16:36:31 -0000
Subject: [llvm-commits] [llvm] r114443 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <20100921163631.AE9E42A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 11:36:31 2010
New Revision: 114443

URL: http://llvm.org/viewvc/llvm-project?rev=114443&view=rev
Log:
continue MachinePointerInfo'izing, eliminating use of one of the old
getLoad overloads.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 11:36:31 2010
@@ -632,9 +632,6 @@
   SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
                   MachinePointerInfo PtrInfo, bool isVolatile,
                   bool isNonTemporal, unsigned Alignment);
-  SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
-                  const Value *SV, int SVOffset, bool isVolatile,
-                  bool isNonTemporal, unsigned Alignment);
   SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
                      SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,
                      EVT MemVT, bool isVolatile,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 21 11:36:31 2010
@@ -425,8 +425,8 @@
 
       // Perform the original store, only redirected to the stack slot.
       SDValue Store = DAG.getTruncStore(Chain, dl,
-                                        Val, StackPtr, NULL, 0, StoredVT,
-                                        false, false, 0);
+                                        Val, StackPtr, MachinePointerInfo(),
+                                        StoredVT, false, false, 0);
       SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
       SmallVector<SDValue, 8> Stores;
       unsigned Offset = 0;
@@ -434,11 +434,12 @@
       // Do all but one copies using the full register width.
       for (unsigned i = 1; i < NumRegs; i++) {
         // Load one integer register's worth from the stack slot.
-        SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0,
+        SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
+                                   MachinePointerInfo(),
                                    false, false, 0);
         // Store it to the final location.  Remember the store.
         Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
-                                      ST->getSrcValue(), SVOffset + Offset,
+                                    ST->getPointerInfo().getWithOffset(Offset),
                                       ST->isVolatile(), ST->isNonTemporal(),
                                       MinAlign(ST->getAlignment(), Offset)));
         // Increment the pointers.
@@ -501,7 +502,6 @@
 static
 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
                             const TargetLowering &TLI) {
-  int SVOffset = LD->getSrcValueOffset();
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   EVT VT = LD->getValueType(0);
@@ -512,8 +512,8 @@
     if (TLI.isTypeLegal(intVT)) {
       // Expand to a (misaligned) integer load of the same size,
       // then bitconvert to floating point or vector.
-      SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
-                                    SVOffset, LD->isVolatile(),
+      SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
+                                    LD->isVolatile(),
                                     LD->isNonTemporal(), LD->getAlignment());
       SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
       if (VT.isFloatingPoint() && LoadedVT != VT)
@@ -521,65 +521,66 @@
 
       SDValue Ops[] = { Result, Chain };
       return DAG.getMergeValues(Ops, 2, dl);
-    } else {
-      // Copy the value to a (aligned) stack slot using (unaligned) integer
-      // loads and stores, then do a (aligned) load from the stack slot.
-      EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
-      unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
-      unsigned RegBytes = RegVT.getSizeInBits() / 8;
-      unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
-
-      // Make sure the stack slot is also aligned for the register type.
-      SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
-
-      SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
-      SmallVector<SDValue, 8> Stores;
-      SDValue StackPtr = StackBase;
-      unsigned Offset = 0;
-
-      // Do all but one copies using the full register width.
-      for (unsigned i = 1; i < NumRegs; i++) {
-        // Load one integer register's worth from the original location.
-        SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
-                                   SVOffset + Offset, LD->isVolatile(),
-                                   LD->isNonTemporal(),
-                                   MinAlign(LD->getAlignment(), Offset));
-        // Follow the load with a store to the stack slot.  Remember the store.
-        Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
-                                      NULL, 0, false, false, 0));
-        // Increment the pointers.
-        Offset += RegBytes;
-        Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
-        StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
-                               Increment);
-      }
-
-      // The last copy may be partial.  Do an extending load.
-      EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
-                                    8 * (LoadedBytes - Offset));
-      SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
-                                    LD->getSrcValue(), SVOffset + Offset,
-                                    MemVT, LD->isVolatile(),
-                                    LD->isNonTemporal(),
-                                    MinAlign(LD->getAlignment(), Offset));
-      // Follow the load with a store to the stack slot.  Remember the store.
-      // On big-endian machines this requires a truncating store to ensure
-      // that the bits end up in the right place.
-      Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
-                                         NULL, 0, MemVT, false, false, 0));
-
-      // The order of the stores doesn't matter - say it with a TokenFactor.
-      SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
-                               Stores.size());
-
-      // Finally, perform the original load only redirected to the stack slot.
-      Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
-                            NULL, 0, LoadedVT, false, false, 0);
-
-      // Callers expect a MERGE_VALUES node.
-      SDValue Ops[] = { Load, TF };
-      return DAG.getMergeValues(Ops, 2, dl);
     }
+    
+    // Copy the value to a (aligned) stack slot using (unaligned) integer
+    // loads and stores, then do a (aligned) load from the stack slot.
+    EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
+    unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
+    unsigned RegBytes = RegVT.getSizeInBits() / 8;
+    unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
+
+    // Make sure the stack slot is also aligned for the register type.
+    SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
+
+    SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
+    SmallVector<SDValue, 8> Stores;
+    SDValue StackPtr = StackBase;
+    unsigned Offset = 0;
+
+    // Do all but one copies using the full register width.
+    for (unsigned i = 1; i < NumRegs; i++) {
+      // Load one integer register's worth from the original location.
+      SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
+                                 LD->getPointerInfo().getWithOffset(Offset),
+                                 LD->isVolatile(), LD->isNonTemporal(),
+                                 MinAlign(LD->getAlignment(), Offset));
+      // Follow the load with a store to the stack slot.  Remember the store.
+      Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
+                                    NULL, 0, false, false, 0));
+      // Increment the pointers.
+      Offset += RegBytes;
+      Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
+      StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
+                             Increment);
+    }
+
+    // The last copy may be partial.  Do an extending load.
+    EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
+                                  8 * (LoadedBytes - Offset));
+    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
+                                  LD->getPointerInfo().getWithOffset(Offset),
+                                  MemVT, LD->isVolatile(),
+                                  LD->isNonTemporal(),
+                                  MinAlign(LD->getAlignment(), Offset));
+    // Follow the load with a store to the stack slot.  Remember the store.
+    // On big-endian machines this requires a truncating store to ensure
+    // that the bits end up in the right place.
+    Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
+                                       MachinePointerInfo(), MemVT,
+                                       false, false, 0));
+
+    // The order of the stores doesn't matter - say it with a TokenFactor.
+    SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+                             Stores.size());
+
+    // Finally, perform the original load only redirected to the stack slot.
+    Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
+                          MachinePointerInfo(), LoadedVT, false, false, 0);
+
+    // Callers expect a MERGE_VALUES node.
+    SDValue Ops[] = { Load, TF };
+    return DAG.getMergeValues(Ops, 2, dl);
   }
   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
@@ -602,22 +603,24 @@
   // Load the value in two parts
   SDValue Lo, Hi;
   if (TLI.isLittleEndian()) {
-    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
-                        SVOffset, NewLoadedVT, LD->isVolatile(),
+    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(),
+                        NewLoadedVT, LD->isVolatile(),
                         LD->isNonTemporal(), Alignment);
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getConstant(IncrementSize, TLI.getPointerTy()));
-    Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
-                        SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
+    Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr,
+                        LD->getPointerInfo().getWithOffset(IncrementSize),
+                        NewLoadedVT, LD->isVolatile(),
                         LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
   } else {
-    Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
-                        SVOffset, NewLoadedVT, LD->isVolatile(),
+    Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(),
+                        NewLoadedVT, LD->isVolatile(),
                         LD->isNonTemporal(), Alignment);
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getConstant(IncrementSize, TLI.getPointerTy()));
-    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
-                        SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
+    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr,
+                        LD->getPointerInfo().getWithOffset(IncrementSize),
+                        NewLoadedVT, LD->isVolatile(),
                         LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
   }
 
@@ -1134,8 +1137,7 @@
         // Change base type to a different vector type.
         EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
 
-        Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
-                           LD->getSrcValueOffset(),
+        Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
                            LD->isVolatile(), LD->isNonTemporal(),
                            LD->getAlignment());
         Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
@@ -1312,8 +1314,8 @@
           break;
         case TargetLowering::Expand:
           if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
-            SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
-                                       LD->getSrcValueOffset(),
+            SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
+                                       LD->getPointerInfo(),
                                        LD->isVolatile(), LD->isNonTemporal(),
                                        LD->getAlignment());
             unsigned ExtendOp;
@@ -1558,11 +1560,12 @@
   StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
 
   if (Op.getValueType().isVector())
-    return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
+    return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
                        false, false, 0);
   else
     return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
-                          NULL, 0, Vec.getValueType().getVectorElementType(),
+                          MachinePointerInfo(),
+                          Vec.getValueType().getVectorElementType(),
                           false, false, 0);
 }
 
@@ -1576,7 +1579,7 @@
   DebugLoc dl = Node->getDebugLoc();
   SDValue FIPtr = DAG.CreateStackTemporary(VT);
   int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
-  const Value *SV = PseudoSourceValue::getFixedStack(FI);
+  MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
 
   // Emit a store of each element to the stack slot.
   SmallVector<SDValue, 8> Stores;
@@ -1595,11 +1598,13 @@
     // element type, only store the bits necessary.
     if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
       Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
-                                         Node->getOperand(i), Idx, SV, Offset,
+                                         Node->getOperand(i), Idx,
+                                         PtrInfo.getWithOffset(Offset),
                                          EltVT, false, false, 0));
     } else
       Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
-                                    Node->getOperand(i), Idx, SV, Offset,
+                                    Node->getOperand(i), Idx,
+                                    PtrInfo.getWithOffset(Offset),
                                     false, false, 0));
   }
 
@@ -1611,7 +1616,7 @@
     StoreChain = DAG.getEntryNode();
 
   // Result is a load from the stack slot.
-  return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0);
+  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
 }
 
 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
@@ -1639,7 +1644,8 @@
     if (TLI.isBigEndian()) {
       assert(FloatVT.isByteSized() && "Unsupported floating point type!");
       // Load out a legal integer with the same sign bit as the float.
-      SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0);
+      SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
+                            false, false, 0);
     } else { // Little endian
       SDValue LoadPtr = StackPtr;
       // The float may be wider than the integer we are going to load.  Advance
@@ -1649,7 +1655,8 @@
       LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
                             LoadPtr, DAG.getIntPtrConstant(ByteOffset));
       // Load a legal integer containing the sign bit.
-      SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0);
+      SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
+                            false, false, 0);
       // Move the sign bit to the top bit of the loaded integer.
       unsigned BitShift = LoadTy.getSizeInBits() -
         (FloatVT.getSizeInBits() - 8 * ByteOffset);
@@ -1789,11 +1796,12 @@
 
   // Result is a load from the stack slot.
   if (SlotSize == DestSize)
-    return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false,
-                       DestAlign);
+    return DAG.getLoad(DestVT, dl, Store, FIPtr, MachinePointerInfo(SV),
+                       false, false, DestAlign);
 
   assert(SlotSize < DestSize && "Unknown extension!");
-  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, SV, 0, SlotVT,
+  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr,
+                        MachinePointerInfo(SV), SlotVT,
                         false, false, DestAlign);
 }
 
@@ -2070,8 +2078,8 @@
     SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
                                 false, false, 0);
     // load the constructed double
-    SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0,
-                               false, false, 0);
+    SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
+                               MachinePointerInfo(), false, false, 0);
     // FP constant to bias correct the final result
     SDValue Bias = DAG.getConstantFP(isSigned ?
                                      BitsToDouble(0x4330000080000000ULL) :
@@ -2660,8 +2668,8 @@
     Tmp2 = Node->getOperand(1);
     unsigned Align = Node->getConstantOperandVal(3);
 
-    SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
-                                     false, false, 0);
+    SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
+                                     MachinePointerInfo(V), false, false, 0);
     SDValue VAList = VAListLoad;
 
     if (Align > TLI.getMinStackArgumentAlignment()) {
@@ -2685,7 +2693,7 @@
     Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0,
                         false, false, 0);
     // Load the actual argument out of the pointer VAList
-    Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,
+    Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
                                   false, false, 0));
     Results.push_back(Results[0].getValue(1));
     break;
@@ -2696,9 +2704,10 @@
     const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
     const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
     Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
-                       Node->getOperand(2), VS, 0, false, false, 0);
-    Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0,
-                        false, false, 0);
+                       Node->getOperand(2), MachinePointerInfo(VS),
+                       false, false, 0);
+    Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
+                        MachinePointerInfo(VD), false, false, 0);
     Results.push_back(Tmp1);
     break;
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Sep 21 11:36:31 2010
@@ -889,7 +889,6 @@
 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
   assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
   SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
-  int SVOffset = N->getSrcValueOffset();
   unsigned Alignment = N->getAlignment();
   bool isVolatile = N->isVolatile();
   bool isNonTemporal = N->isNonTemporal();
@@ -898,8 +897,8 @@
   SDValue Val = GetPromotedInteger(N->getValue());  // Get promoted value.
 
   // Truncate the value and store the result.
-  return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
-                           SVOffset, N->getMemoryVT(),
+  return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
+                           N->getMemoryVT(),
                            isVolatile, isNonTemporal, Alignment);
 }
 
@@ -1524,7 +1523,6 @@
   SDValue Ch  = N->getChain();
   SDValue Ptr = N->getBasePtr();
   ISD::LoadExtType ExtType = N->getExtensionType();
-  int SVOffset = N->getSrcValueOffset();
   unsigned Alignment = N->getAlignment();
   bool isVolatile = N->isVolatile();
   bool isNonTemporal = N->isNonTemporal();
@@ -1535,7 +1533,7 @@
   if (N->getMemoryVT().bitsLE(NVT)) {
     EVT MemVT = N->getMemoryVT();
 
-    Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
+    Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
                         MemVT, isVolatile, isNonTemporal, Alignment);
 
     // Remember the chain.
@@ -1557,7 +1555,7 @@
     }
   } else if (TLI.isLittleEndian()) {
     // Little-endian - low bits are at low addresses.
-    Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
+    Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
                      isVolatile, isNonTemporal, Alignment);
 
     unsigned ExcessBits =
@@ -1568,8 +1566,8 @@
     unsigned IncrementSize = NVT.getSizeInBits()/8;
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getIntPtrConstant(IncrementSize));
-    Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(),
-                        SVOffset+IncrementSize, NEVT,
+    Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr,
+                        N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
                         isVolatile, isNonTemporal,
                         MinAlign(Alignment, IncrementSize));
 
@@ -1586,7 +1584,7 @@
     unsigned ExcessBits = (EBytes - IncrementSize)*8;
 
     // Load both the high bits and maybe some of the low bits.
-    Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
+    Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
                         EVT::getIntegerVT(*DAG.getContext(),
                                           MemVT.getSizeInBits() - ExcessBits),
                         isVolatile, isNonTemporal, Alignment);
@@ -1595,8 +1593,8 @@
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getIntPtrConstant(IncrementSize));
     // Load the rest of the low bits.
-    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr, N->getSrcValue(),
-                        SVOffset+IncrementSize,
+    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr,
+                        N->getPointerInfo().getWithOffset(IncrementSize),
                         EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
                         isVolatile, isNonTemporal,
                         MinAlign(Alignment, IncrementSize));
@@ -2308,7 +2306,6 @@
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   SDValue Ch  = N->getChain();
   SDValue Ptr = N->getBasePtr();
-  int SVOffset = N->getSrcValueOffset();
   unsigned Alignment = N->getAlignment();
   bool isVolatile = N->isVolatile();
   bool isNonTemporal = N->isNonTemporal();
@@ -2319,14 +2316,16 @@
 
   if (N->getMemoryVT().bitsLE(NVT)) {
     GetExpandedInteger(N->getValue(), Lo, Hi);
-    return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
+    return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
                              N->getMemoryVT(), isVolatile, isNonTemporal,
                              Alignment);
-  } else if (TLI.isLittleEndian()) {
+  }
+  
+  if (TLI.isLittleEndian()) {
     // Little-endian - low bits are at low addresses.
     GetExpandedInteger(N->getValue(), Lo, Hi);
 
-    Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
+    Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
                       isVolatile, isNonTemporal, Alignment);
 
     unsigned ExcessBits =
@@ -2337,50 +2336,49 @@
     unsigned IncrementSize = NVT.getSizeInBits()/8;
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getIntPtrConstant(IncrementSize));
-    Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
-                           SVOffset+IncrementSize, NEVT,
-                           isVolatile, isNonTemporal,
-                           MinAlign(Alignment, IncrementSize));
-    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
-  } else {
-    // Big-endian - high bits are at low addresses.  Favor aligned stores at
-    // the cost of some bit-fiddling.
-    GetExpandedInteger(N->getValue(), Lo, Hi);
-
-    EVT ExtVT = N->getMemoryVT();
-    unsigned EBytes = ExtVT.getStoreSize();
-    unsigned IncrementSize = NVT.getSizeInBits()/8;
-    unsigned ExcessBits = (EBytes - IncrementSize)*8;
-    EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
-                                 ExtVT.getSizeInBits() - ExcessBits);
-
-    if (ExcessBits < NVT.getSizeInBits()) {
-      // Transfer high bits from the top of Lo to the bottom of Hi.
-      Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
-                       DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
-                                       TLI.getPointerTy()));
-      Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
-                       DAG.getNode(ISD::SRL, dl, NVT, Lo,
-                                   DAG.getConstant(ExcessBits,
-                                                   TLI.getPointerTy())));
-    }
-
-    // Store both the high bits and maybe some of the low bits.
-    Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
-                           SVOffset, HiVT, isVolatile, isNonTemporal,
-                           Alignment);
-
-    // Increment the pointer to the other half.
-    Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
-    // Store the lowest ExcessBits bits in the second half.
-    Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
-                           SVOffset+IncrementSize,
-                           EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
-                           isVolatile, isNonTemporal,
+    Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
+                           N->getPointerInfo().getWithOffset(IncrementSize),
+                           NEVT, isVolatile, isNonTemporal,
                            MinAlign(Alignment, IncrementSize));
     return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
   }
+
+  // Big-endian - high bits are at low addresses.  Favor aligned stores at
+  // the cost of some bit-fiddling.
+  GetExpandedInteger(N->getValue(), Lo, Hi);
+
+  EVT ExtVT = N->getMemoryVT();
+  unsigned EBytes = ExtVT.getStoreSize();
+  unsigned IncrementSize = NVT.getSizeInBits()/8;
+  unsigned ExcessBits = (EBytes - IncrementSize)*8;
+  EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
+                               ExtVT.getSizeInBits() - ExcessBits);
+
+  if (ExcessBits < NVT.getSizeInBits()) {
+    // Transfer high bits from the top of Lo to the bottom of Hi.
+    Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
+                     DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
+                                     TLI.getPointerTy()));
+    Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
+                     DAG.getNode(ISD::SRL, dl, NVT, Lo,
+                                 DAG.getConstant(ExcessBits,
+                                                 TLI.getPointerTy())));
+  }
+
+  // Store both the high bits and maybe some of the low bits.
+  Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
+                         HiVT, isVolatile, isNonTemporal, Alignment);
+
+  // Increment the pointer to the other half.
+  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
+                    DAG.getIntPtrConstant(IncrementSize));
+  // Store the lowest ExcessBits bits in the second half.
+  Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
+                         N->getPointerInfo().getWithOffset(IncrementSize),
+                         EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
+                         isVolatile, isNonTemporal,
+                         MinAlign(Alignment, IncrementSize));
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
 }
 
 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue Sep 21 11:36:31 2010
@@ -880,10 +880,11 @@
   // the source and destination types.
   SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT);
   // Emit a store to the stack slot.
-  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op, StackPtr, NULL, 0,
-                               false, false, 0);
+  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op, StackPtr,
+                               MachinePointerInfo(), false, false, 0);
   // Result is a load from the stack slot.
-  return DAG.getLoad(DestVT, dl, Store, StackPtr, NULL, 0, false, false, 0);
+  return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(),
+                     false, false, 0);
 }
 
 /// CustomLowerNode - Replace the node's results with custom code provided

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Sep 21 11:36:31 2010
@@ -119,14 +119,14 @@
                                               getTypeForEVT(*DAG.getContext()));
   SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
   int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
-  const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
+  MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
 
   // Emit a store to the stack slot.
-  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, SV, 0,
+  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo,
                                false, false, 0);
 
   // Load the first half from the stack slot.
-  Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, SV, 0, false, false, 0);
+  Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo, false, false, 0);
 
   // Increment the pointer to the other half.
   unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
@@ -134,7 +134,8 @@
                          DAG.getIntPtrConstant(IncrementSize));
 
   // Load the second half from the stack slot.
-  Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr, SV, IncrementSize, false,
+  Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr,
+                   PtrInfo.getWithOffset(IncrementSize), false,
                    false, MinAlign(Alignment, IncrementSize));
 
   // Handle endianness of the load.
@@ -204,22 +205,21 @@
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
-  int SVOffset = LD->getSrcValueOffset();
   unsigned Alignment = LD->getAlignment();
   bool isVolatile = LD->isVolatile();
   bool isNonTemporal = LD->isNonTemporal();
 
   assert(NVT.isByteSized() && "Expanded type not byte sized!");
 
-  Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(), SVOffset,
+  Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
                    isVolatile, isNonTemporal, Alignment);
 
   // Increment the pointer to the other half.
   unsigned IncrementSize = NVT.getSizeInBits() / 8;
   Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                     DAG.getIntPtrConstant(IncrementSize));
-  Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(),
-                   SVOffset+IncrementSize,
+  Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
+                   LD->getPointerInfo().getWithOffset(IncrementSize),
                    isVolatile, isNonTemporal,
                    MinAlign(Alignment, IncrementSize));
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Sep 21 11:36:31 2010
@@ -705,8 +705,8 @@
   EVT VecVT = Vec.getValueType();
   EVT EltVT = VecVT.getVectorElementType();
   SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
-  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
-                               false, false, 0);
+  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
+                               MachinePointerInfo(), false, false, 0);
 
   // Store the new element.  This may be larger than the vector element type,
   // so use a truncating store.
@@ -714,11 +714,11 @@
   const Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
   unsigned Alignment =
     TLI.getTargetData()->getPrefTypeAlignment(VecType);
-  Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT,
+  Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
                             false, false, 0);
 
   // Load the Lo part from the stack slot.
-  Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0,
+  Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
                    false, false, 0);
 
   // Increment the pointer to the other part.
@@ -727,8 +727,8 @@
                          DAG.getIntPtrConstant(IncrementSize));
 
   // Load the Hi part from the stack slot.
-  Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
-                   false, MinAlign(Alignment, IncrementSize));
+  Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
+                   false, false, MinAlign(Alignment, IncrementSize));
 }
 
 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
@@ -2212,8 +2212,8 @@
   return DAG.getNode(ISD::BIT_CONVERT, dl, VecTy, VecOp);
 }
 
-SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
-                                              LoadSDNode * LD) {
+SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
+                                              LoadSDNode *LD) {
   // The strategy assumes that we can efficiently load powers of two widths.
   // The routines chops the vector into the largest vector loads with the same
   // element type or scalar loads and then recombines it to the widen vector
@@ -2228,11 +2228,9 @@
   // Load information
   SDValue   Chain = LD->getChain();
   SDValue   BasePtr = LD->getBasePtr();
-  int       SVOffset = LD->getSrcValueOffset();
   unsigned  Align    = LD->getAlignment();
   bool      isVolatile = LD->isVolatile();
   bool      isNonTemporal = LD->isNonTemporal();
-  const Value *SV = LD->getSrcValue();
 
   int LdWidth = LdVT.getSizeInBits();
   int WidthDiff = WidenWidth - LdWidth;          // Difference
@@ -2241,7 +2239,7 @@
   // Find the vector type that can load from.
   EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
   int NewVTWidth = NewVT.getSizeInBits();
-  SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, SV, SVOffset,
+  SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
                              isVolatile, isNonTemporal, Align);
   LdChain.push_back(LdOp.getValue(1));
 
@@ -2286,8 +2284,9 @@
       NewVTWidth = NewVT.getSizeInBits();
     }
 
-    SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, SV,
-                               SVOffset+Offset, isVolatile,
+    SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
+                               LD->getPointerInfo().getWithOffset(Offset),
+                               isVolatile,
                                isNonTemporal, MinAlign(Align, Increment));
     LdChain.push_back(LdOp.getValue(1));
     LdOps.push_back(LdOp);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 11:36:31 2010
@@ -3949,16 +3949,6 @@
 
 SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
                               SDValue Chain, SDValue Ptr,
-                              const Value *SV, int SVOffset,
-                              bool isVolatile, bool isNonTemporal,
-                              unsigned Alignment) {
-  SDValue Undef = getUNDEF(Ptr.getValueType());
-  return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
-                 SV, SVOffset, VT, isVolatile, isNonTemporal, Alignment);
-}
-
-SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
-                              SDValue Chain, SDValue Ptr,
                               MachinePointerInfo PtrInfo,
                               bool isVolatile, bool isNonTemporal,
                               unsigned Alignment) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep 21 11:36:31 2010
@@ -2950,7 +2950,7 @@
                             PtrVT, Ptr,
                             DAG.getConstant(Offsets[i], PtrVT));
     SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
-                            A, SV, Offsets[i], isVolatile, 
+                            A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 
                             isNonTemporal, Alignment);
 
     Values[i] = L;
@@ -4616,6 +4616,7 @@
                         FTy->isVarArg(), Outs, FTy->getContext());
 
   SDValue DemoteStackSlot;
+  int DemoteStackIdx = -100;
 
   if (!CanLowerReturn) {
     uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
@@ -4623,10 +4624,10 @@
     unsigned Align  = TLI.getTargetData()->getPrefTypeAlignment(
                       FTy->getReturnType());
     MachineFunction &MF = DAG.getMachineFunction();
-    int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
+    DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
     const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
 
-    DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
+    DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
     Entry.Node = DemoteStackSlot;
     Entry.Ty = StackSlotPtrType;
     Entry.isSExt = false;
@@ -4720,7 +4721,9 @@
                                 DemoteStackSlot,
                                 DAG.getConstant(Offsets[i], PtrVT));
       SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
-                              Add, NULL, Offsets[i], false, false, 1);
+                              Add,
+                  MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
+                              false, false, 1);
       Values[i] = L;
       Chains[i] = L.getValue(1);
     }
@@ -4823,7 +4826,7 @@
 
   SDValue Ptr = Builder.getValue(PtrVal);
   SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
-                                        Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
+                                        Ptr, MachinePointerInfo(PtrVal),
                                         false /*volatile*/,
                                         false /*nontemporal*/, 1 /* align=1 */);
 
@@ -5457,7 +5460,8 @@
         int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
         SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
         Chain = DAG.getStore(Chain, getCurDebugLoc(),
-                             OpInfo.CallOperand, StackSlot, NULL, 0,
+                             OpInfo.CallOperand, StackSlot,
+                             MachinePointerInfo::getFixedStack(SSFI),
                              false, false, 0);
         OpInfo.CallOperand = StackSlot;
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=114443&r1=114442&r2=114443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Sep 21 11:36:31 2010
@@ -1916,8 +1916,7 @@
                               DAG.getConstant(bestOffset, PtrType));
           unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
           SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
-                                        Lod->getSrcValue(), 
-                                        Lod->getSrcValueOffset() + bestOffset,
+                                Lod->getPointerInfo().getWithOffset(bestOffset),
                                         false, false, NewAlign);
           return DAG.getSetCC(dl, VT, 
                               DAG.getNode(ISD::AND, dl, newVT, NewLoad,



From benny.kra at googlemail.com  Tue Sep 21 11:41:30 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 21 Sep 2010 16:41:30 -0000
Subject: [llvm-commits] [llvm] r114444 -
	/llvm/trunk/lib/Analysis/DebugInfo.cpp
Message-ID: <20100921164130.0BF552A6C12C@llvm.org>

Author: d0k
Date: Tue Sep 21 11:41:29 2010
New Revision: 114444

URL: http://llvm.org/viewvc/llvm-project?rev=114444&view=rev
Log:
Simplify code.

Modified:
    llvm/trunk/lib/Analysis/DebugInfo.cpp

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=114444&r1=114443&r2=114444&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Sep 21 11:41:29 2010
@@ -701,15 +701,13 @@
 /// GetOrCreateArray - Create an descriptor for an array of descriptors.
 /// This implicitly uniques the arrays created.
 DIArray DIFactory::GetOrCreateArray(DIDescriptor *Tys, unsigned NumTys) {
-  SmallVector<Value*, 16> Elts;
-
-  if (NumTys == 0)
-    Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)));
-  else
-    for (unsigned i = 0; i != NumTys; ++i)
-      Elts.push_back(Tys[i]);
+  if (NumTys == 0) {
+    Value *Null = llvm::Constant::getNullValue(Type::getInt32Ty(VMContext));
+    return DIArray(MDNode::get(VMContext, &Null, 1));
+  }
 
-  return DIArray(MDNode::get(VMContext,Elts.data(), Elts.size()));
+  SmallVector<Value *, 16> Elts(Tys, Tys+NumTys);
+  return DIArray(MDNode::get(VMContext, Elts.data(), Elts.size()));
 }
 
 /// GetOrCreateSubrange - Create a descriptor for a value range.  This



From grosbach at apple.com  Tue Sep 21 11:45:31 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 21 Sep 2010 16:45:31 -0000
Subject: [llvm-commits] [llvm] r114445 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100921164531.81E242A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep 21 11:45:31 2010
New Revision: 114445

URL: http://llvm.org/viewvc/llvm-project?rev=114445&view=rev
Log:
Fix errant printing of [v]ldm instructions that aren't a pop

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114445&r1=114444&r2=114445&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Sep 21 11:45:31 2010
@@ -1174,47 +1174,39 @@
   } else
   // A8.6.123 PUSH
   if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
-      MI->getOperand(0).getReg() == ARM::SP) {
-    const MachineOperand &MO1 = MI->getOperand(2);
-    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
-      OS << '\t' << "push";
-      printPredicateOperand(MI, 3, OS);
-      OS << '\t';
-      printRegisterList(MI, 5, OS);
-    }
+      MI->getOperand(0).getReg() == ARM::SP &&
+      ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
+    OS << '\t' << "push";
+    printPredicateOperand(MI, 3, OS);
+    OS << '\t';
+    printRegisterList(MI, 5, OS);
   } else
   // A8.6.122 POP
   if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
-      MI->getOperand(0).getReg() == ARM::SP) {
-    const MachineOperand &MO1 = MI->getOperand(2);
-    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
-      OS << '\t' << "pop";
-      printPredicateOperand(MI, 3, OS);
-      OS << '\t';
-      printRegisterList(MI, 5, OS);
-    }
+      MI->getOperand(0).getReg() == ARM::SP &&
+      ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
+    OS << '\t' << "pop";
+    printPredicateOperand(MI, 3, OS);
+    OS << '\t';
+    printRegisterList(MI, 5, OS);
   } else
   // A8.6.355 VPUSH
   if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
-      MI->getOperand(0).getReg() == ARM::SP) {
-    const MachineOperand &MO1 = MI->getOperand(2);
-    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
-      OS << '\t' << "vpush";
-      printPredicateOperand(MI, 3, OS);
-      OS << '\t';
-      printRegisterList(MI, 5, OS);
-    }
+      MI->getOperand(0).getReg() == ARM::SP &&
+      ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
+    OS << '\t' << "vpush";
+    printPredicateOperand(MI, 3, OS);
+    OS << '\t';
+    printRegisterList(MI, 5, OS);
   } else
   // A8.6.354 VPOP
   if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
-      MI->getOperand(0).getReg() == ARM::SP) {
-    const MachineOperand &MO1 = MI->getOperand(2);
-    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
-      OS << '\t' << "vpop";
-      printPredicateOperand(MI, 3, OS);
-      OS << '\t';
-      printRegisterList(MI, 5, OS);
-    }
+      MI->getOperand(0).getReg() == ARM::SP &&
+      ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
+    OS << '\t' << "vpop";
+    printPredicateOperand(MI, 3, OS);
+    OS << '\t';
+    printRegisterList(MI, 5, OS);
   } else
     printInstruction(MI, OS);
 



From resistor at mac.com  Tue Sep 21 11:56:28 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 21 Sep 2010 09:56:28 -0700
Subject: [llvm-commits] [llvm] r114404 -
 /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
In-Reply-To: <20100921060219.BAA062A6C12C@llvm.org>
References: <20100921060219.BAA062A6C12C@llvm.org>
Message-ID: <70E4551B-6D7A-42A9-8A04-783CF234E4BB@mac.com>


On Sep 20, 2010, at 11:02 PM, Chris Lattner wrote:

> URL: http://llvm.org/viewvc/llvm-project?rev=114404&view=rev
> Log:
> update the X86 backend to use the MachinePointerInfo version of one
> of the getLoad methods.  This fixes at least one bug where an incorrect
> svoffset is passed in (a potential combiner-aa miscompile).

FYI, there are two parts to CombinerAA: -combiner-alias-analysis, which does not use SrcValues at all, only Machine-level information, and -combiner-global-alias-analysis, which uses IR-level AA.  I have only been trying to get the former up to snuff, not the latter, which is why these miscompilations weren't detected.

--Owen

From sabre at nondot.org  Tue Sep 21 11:59:49 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 09:59:49 -0700
Subject: [llvm-commits] [llvm] r114404 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
In-Reply-To: <70E4551B-6D7A-42A9-8A04-783CF234E4BB@mac.com>
References: <20100921060219.BAA062A6C12C@llvm.org>
	<70E4551B-6D7A-42A9-8A04-783CF234E4BB@mac.com>
Message-ID: <B25E33F2-D8EB-4519-92DD-AFA5386F6244@nondot.org>


On Sep 21, 2010, at 9:56 AM, Owen Anderson wrote:

> 
> On Sep 20, 2010, at 11:02 PM, Chris Lattner wrote:
> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=114404&view=rev
>> Log:
>> update the X86 backend to use the MachinePointerInfo version of one
>> of the getLoad methods.  This fixes at least one bug where an incorrect
>> svoffset is passed in (a potential combiner-aa miscompile).
> 
> FYI, there are two parts to CombinerAA: -combiner-alias-analysis, which does not use SrcValues at all, only Machine-level information, and -combiner-global-alias-analysis, which uses IR-level AA.  I have only been trying to get the former up to snuff, not the latter, which is why these miscompilations weren't detected.

Aha, good to know!

-Chris

From sabre at nondot.org  Tue Sep 21 12:04:51 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 17:04:51 -0000
Subject: [llvm-commits] [llvm] r114446 - in /llvm/trunk:
 include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/Alpha/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/
Message-ID: <20100921170451.7E2D62A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 12:04:51 2010
New Revision: 114446

URL: http://llvm.org/viewvc/llvm-project?rev=114446&view=rev
Log:
propagate MachinePointerInfo through various uses of the old
SelectionDAG::getExtLoad overload, and eliminate it.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 12:04:51 2010
@@ -636,10 +636,10 @@
                      SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,
                      EVT MemVT, bool isVolatile,
                      bool isNonTemporal, unsigned Alignment);
-  SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
+/*  SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
                      SDValue Chain, SDValue Ptr, const Value *SV,
                      int SVOffset, EVT MemVT, bool isVolatile,
-                     bool isNonTemporal, unsigned Alignment);
+                     bool isNonTemporal, unsigned Alignment);*/
   SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
                          SDValue Offset, ISD::MemIndexedMode AM);
   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 12:04:51 2010
@@ -671,7 +671,7 @@
     Replace = true;
     return DAG.getExtLoad(ExtType, PVT, dl,
                           LD->getChain(), LD->getBasePtr(),
-                          LD->getSrcValue(), LD->getSrcValueOffset(),
+                          LD->getPointerInfo(),
                           MemVT, LD->isVolatile(),
                           LD->isNonTemporal(), LD->getAlignment());
   }
@@ -893,7 +893,7 @@
       : LD->getExtensionType();
     SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
                                    LD->getChain(), LD->getBasePtr(),
-                                   LD->getSrcValue(), LD->getSrcValueOffset(),
+                                   LD->getPointerInfo(),
                                    MemVT, LD->isVolatile(),
                                    LD->isNonTemporal(), LD->getAlignment());
     SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
@@ -2200,8 +2200,7 @@
          TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
                                        LN0->getChain(), LN0->getBasePtr(),
-                                       LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(), MemVT,
+                                       LN0->getPointerInfo(), MemVT,
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
       AddToWorkList(N);
@@ -2223,8 +2222,8 @@
          TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
                                        LN0->getChain(),
-                                       LN0->getBasePtr(), LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(), MemVT,
+                                       LN0->getBasePtr(), LN0->getPointerInfo(),
+                                       MemVT,
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
       AddToWorkList(N);
@@ -2257,7 +2256,7 @@
           SDValue NewLoad = 
             DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
                            LN0->getChain(), LN0->getBasePtr(),
-                           LN0->getSrcValue(), LN0->getSrcValueOffset(),
+                           LN0->getPointerInfo(),
                            ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
                            LN0->getAlignment());
           AddToWorkList(N);
@@ -2293,7 +2292,7 @@
           SDValue Load =
             DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
                            LN0->getChain(), NewPtr,
-                           LN0->getSrcValue(), LN0->getSrcValueOffset(),
+                           LN0->getPointerInfo(),
                            ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
                            Alignment);
           AddToWorkList(N);
@@ -3505,8 +3504,7 @@
       LoadSDNode *LN0 = cast<LoadSDNode>(N0);
       SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
                                        LN0->getChain(),
-                                       LN0->getBasePtr(), LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(),
+                                       LN0->getBasePtr(), LN0->getPointerInfo(),
                                        N0.getValueType(),
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
@@ -3549,8 +3547,8 @@
         TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
                                        LN0->getChain(),
-                                       LN0->getBasePtr(), LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(), MemVT,
+                                       LN0->getBasePtr(), LN0->getPointerInfo(),
+                                       MemVT,
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
       CombineTo(N, ExtLoad);
@@ -3694,8 +3692,7 @@
       LoadSDNode *LN0 = cast<LoadSDNode>(N0);
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
                                        LN0->getChain(),
-                                       LN0->getBasePtr(), LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(),
+                                       LN0->getBasePtr(), LN0->getPointerInfo(),
                                        N0.getValueType(),
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
@@ -3738,8 +3735,8 @@
         TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
                                        LN0->getChain(),
-                                       LN0->getBasePtr(), LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(), MemVT,
+                                       LN0->getBasePtr(), LN0->getPointerInfo(),
+                                       MemVT,
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
       CombineTo(N, ExtLoad);
@@ -3896,8 +3893,7 @@
       LoadSDNode *LN0 = cast<LoadSDNode>(N0);
       SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
                                        LN0->getChain(),
-                                       LN0->getBasePtr(), LN0->getSrcValue(),
-                                       LN0->getSrcValueOffset(),
+                                       LN0->getBasePtr(), LN0->getPointerInfo(),
                                        N0.getValueType(),
                                        LN0->isVolatile(), LN0->isNonTemporal(),
                                        LN0->getAlignment());
@@ -3941,8 +3937,7 @@
     SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
                                      N->getDebugLoc(),
                                      LN0->getChain(), LN0->getBasePtr(),
-                                     LN0->getSrcValue(),
-                                     LN0->getSrcValueOffset(), MemVT,
+                                     LN0->getPointerInfo(), MemVT,
                                      LN0->isVolatile(), LN0->isNonTemporal(),
                                      LN0->getAlignment());
     CombineTo(N, ExtLoad);
@@ -4198,8 +4193,8 @@
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
                                      LN0->getChain(),
-                                     LN0->getBasePtr(), LN0->getSrcValue(),
-                                     LN0->getSrcValueOffset(), EVT,
+                                     LN0->getBasePtr(), LN0->getPointerInfo(),
+                                     EVT,
                                      LN0->isVolatile(), LN0->isNonTemporal(),
                                      LN0->getAlignment());
     CombineTo(N, ExtLoad);
@@ -4215,8 +4210,8 @@
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
                                      LN0->getChain(),
-                                     LN0->getBasePtr(), LN0->getSrcValue(),
-                                     LN0->getSrcValueOffset(), EVT,
+                                     LN0->getBasePtr(), LN0->getPointerInfo(),
+                                     EVT,
                                      LN0->isVolatile(), LN0->isNonTemporal(),
                                      LN0->getAlignment());
     CombineTo(N, ExtLoad);
@@ -4987,8 +4982,7 @@
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
                                      LN0->getChain(),
-                                     LN0->getBasePtr(), LN0->getSrcValue(),
-                                     LN0->getSrcValueOffset(),
+                                     LN0->getBasePtr(), LN0->getPointerInfo(),
                                      N0.getValueType(),
                                      LN0->isVolatile(), LN0->isNonTemporal(),
                                      LN0->getAlignment());
@@ -5571,8 +5565,8 @@
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
                               N->getDebugLoc(),
-                              Chain, Ptr, LD->getSrcValue(),
-                              LD->getSrcValueOffset(), LD->getMemoryVT(),
+                              Chain, Ptr, LD->getPointerInfo(),
+                              LD->getMemoryVT(),
                               LD->isVolatile(), LD->isNonTemporal(), Align);
     }
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 21 12:04:51 2010
@@ -457,10 +457,12 @@
 
       // Load from the stack slot.
       SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
-                                    NULL, 0, MemVT, false, false, 0);
+                                    MachinePointerInfo(),
+                                    MemVT, false, false, 0);
 
       Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
-                                         ST->getSrcValue(), SVOffset + Offset,
+                                         ST->getPointerInfo()
+                                           .getWithOffset(Offset),
                                          MemVT, ST->isVolatile(),
                                          ST->isNonTemporal(),
                                          MinAlign(ST->getAlignment(), Offset)));
@@ -1150,221 +1152,219 @@
       AddLegalizedOperand(SDValue(Node, 0), Tmp3);
       AddLegalizedOperand(SDValue(Node, 1), Tmp4);
       return Op.getResNo() ? Tmp4 : Tmp3;
-    } else {
-      EVT SrcVT = LD->getMemoryVT();
-      unsigned SrcWidth = SrcVT.getSizeInBits();
-      int SVOffset = LD->getSrcValueOffset();
-      unsigned Alignment = LD->getAlignment();
-      bool isVolatile = LD->isVolatile();
-      bool isNonTemporal = LD->isNonTemporal();
-
-      if (SrcWidth != SrcVT.getStoreSizeInBits() &&
-          // Some targets pretend to have an i1 loading operation, and actually
-          // load an i8.  This trick is correct for ZEXTLOAD because the top 7
-          // bits are guaranteed to be zero; it helps the optimizers understand
-          // that these bits are zero.  It is also useful for EXTLOAD, since it
-          // tells the optimizers that those bits are undefined.  It would be
-          // nice to have an effective generic way of getting these benefits...
-          // Until such a way is found, don't insist on promoting i1 here.
-          (SrcVT != MVT::i1 ||
-           TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
-        // Promote to a byte-sized load if not loading an integral number of
-        // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
-        unsigned NewWidth = SrcVT.getStoreSizeInBits();
-        EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
-        SDValue Ch;
-
-        // The extra bits are guaranteed to be zero, since we stored them that
-        // way.  A zext load from NVT thus automatically gives zext from SrcVT.
-
-        ISD::LoadExtType NewExtType =
-          ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
-
-        Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
-                                Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
-                                NVT, isVolatile, isNonTemporal, Alignment);
+    }
+  
+    EVT SrcVT = LD->getMemoryVT();
+    unsigned SrcWidth = SrcVT.getSizeInBits();
+    unsigned Alignment = LD->getAlignment();
+    bool isVolatile = LD->isVolatile();
+    bool isNonTemporal = LD->isNonTemporal();
+
+    if (SrcWidth != SrcVT.getStoreSizeInBits() &&
+        // Some targets pretend to have an i1 loading operation, and actually
+        // load an i8.  This trick is correct for ZEXTLOAD because the top 7
+        // bits are guaranteed to be zero; it helps the optimizers understand
+        // that these bits are zero.  It is also useful for EXTLOAD, since it
+        // tells the optimizers that those bits are undefined.  It would be
+        // nice to have an effective generic way of getting these benefits...
+        // Until such a way is found, don't insist on promoting i1 here.
+        (SrcVT != MVT::i1 ||
+         TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
+      // Promote to a byte-sized load if not loading an integral number of
+      // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
+      unsigned NewWidth = SrcVT.getStoreSizeInBits();
+      EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
+      SDValue Ch;
+
+      // The extra bits are guaranteed to be zero, since we stored them that
+      // way.  A zext load from NVT thus automatically gives zext from SrcVT.
+
+      ISD::LoadExtType NewExtType =
+        ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
+
+      Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
+                              Tmp1, Tmp2, LD->getPointerInfo(),
+                              NVT, isVolatile, isNonTemporal, Alignment);
+
+      Ch = Result.getValue(1); // The chain.
+
+      if (ExtType == ISD::SEXTLOAD)
+        // Having the top bits zero doesn't help when sign extending.
+        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
+                             Result.getValueType(),
+                             Result, DAG.getValueType(SrcVT));
+      else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
+        // All the top bits are guaranteed to be zero - inform the optimizers.
+        Result = DAG.getNode(ISD::AssertZext, dl,
+                             Result.getValueType(), Result,
+                             DAG.getValueType(SrcVT));
+
+      Tmp1 = LegalizeOp(Result);
+      Tmp2 = LegalizeOp(Ch);
+    } else if (SrcWidth & (SrcWidth - 1)) {
+      // If not loading a power-of-2 number of bits, expand as two loads.
+      assert(!SrcVT.isVector() && "Unsupported extload!");
+      unsigned RoundWidth = 1 << Log2_32(SrcWidth);
+      assert(RoundWidth < SrcWidth);
+      unsigned ExtraWidth = SrcWidth - RoundWidth;
+      assert(ExtraWidth < RoundWidth);
+      assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
+             "Load size not an integral number of bytes!");
+      EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
+      EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
+      SDValue Lo, Hi, Ch;
+      unsigned IncrementSize;
+
+      if (TLI.isLittleEndian()) {
+        // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD at +2:i8, 16)
+        // Load the bottom RoundWidth bits.
+        Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
+                            Tmp1, Tmp2,
+                            LD->getPointerInfo(), RoundVT, isVolatile,
+                            isNonTemporal, Alignment);
 
-        Ch = Result.getValue(1); // The chain.
+        // Load the remaining ExtraWidth bits.
+        IncrementSize = RoundWidth / 8;
+        Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
+                           DAG.getIntPtrConstant(IncrementSize));
+        Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
+                            LD->getPointerInfo().getWithOffset(IncrementSize),
+                            ExtraVT, isVolatile, isNonTemporal,
+                            MinAlign(Alignment, IncrementSize));
+
+        // Build a factor node to remember that this load is independent of
+        // the other one.
+        Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+                         Hi.getValue(1));
+
+        // Move the top bits to the right place.
+        Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
+                         DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
 
-        if (ExtType == ISD::SEXTLOAD)
-          // Having the top bits zero doesn't help when sign extending.
-          Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
-                               Result.getValueType(),
-                               Result, DAG.getValueType(SrcVT));
-        else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
-          // All the top bits are guaranteed to be zero - inform the optimizers.
-          Result = DAG.getNode(ISD::AssertZext, dl,
-                               Result.getValueType(), Result,
-                               DAG.getValueType(SrcVT));
-
-        Tmp1 = LegalizeOp(Result);
-        Tmp2 = LegalizeOp(Ch);
-      } else if (SrcWidth & (SrcWidth - 1)) {
-        // If not loading a power-of-2 number of bits, expand as two loads.
-        assert(!SrcVT.isVector() && "Unsupported extload!");
-        unsigned RoundWidth = 1 << Log2_32(SrcWidth);
-        assert(RoundWidth < SrcWidth);
-        unsigned ExtraWidth = SrcWidth - RoundWidth;
-        assert(ExtraWidth < RoundWidth);
-        assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
-               "Load size not an integral number of bytes!");
-        EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
-        EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
-        SDValue Lo, Hi, Ch;
-        unsigned IncrementSize;
+        // Join the hi and lo parts.
+        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+      } else {
+        // Big endian - avoid unaligned loads.
+        // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
+        // Load the top RoundWidth bits.
+        Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
+                            LD->getPointerInfo(), RoundVT, isVolatile,
+                            isNonTemporal, Alignment);
 
-        if (TLI.isLittleEndian()) {
-          // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD at +2:i8, 16)
-          // Load the bottom RoundWidth bits.
-          Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
-                              Tmp1, Tmp2,
-                              LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
-                              isNonTemporal, Alignment);
+        // Load the remaining ExtraWidth bits.
+        IncrementSize = RoundWidth / 8;
+        Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
+                           DAG.getIntPtrConstant(IncrementSize));
+        Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
+                            Node->getValueType(0), dl, Tmp1, Tmp2,
+                            LD->getPointerInfo().getWithOffset(IncrementSize),
+                            ExtraVT, isVolatile, isNonTemporal,
+                            MinAlign(Alignment, IncrementSize));
+
+        // Build a factor node to remember that this load is independent of
+        // the other one.
+        Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+                         Hi.getValue(1));
+
+        // Move the top bits to the right place.
+        Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
+                         DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
 
-          // Load the remaining ExtraWidth bits.
-          IncrementSize = RoundWidth / 8;
-          Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
-                             DAG.getIntPtrConstant(IncrementSize));
-          Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
-                              LD->getSrcValue(), SVOffset + IncrementSize,
-                              ExtraVT, isVolatile, isNonTemporal,
-                              MinAlign(Alignment, IncrementSize));
-
-          // Build a factor node to remember that this load is independent of
-          // the other one.
-          Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
-                           Hi.getValue(1));
+        // Join the hi and lo parts.
+        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+      }
 
-          // Move the top bits to the right place.
-          Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
-                           DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
+      Tmp1 = LegalizeOp(Result);
+      Tmp2 = LegalizeOp(Ch);
+    } else {
+      switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
+      default: assert(0 && "This action is not supported yet!");
+      case TargetLowering::Custom:
+        isCustom = true;
+        // FALLTHROUGH
+      case TargetLowering::Legal:
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                Tmp1, Tmp2, LD->getOffset()),
+                         Result.getResNo());
+        Tmp1 = Result.getValue(0);
+        Tmp2 = Result.getValue(1);
 
-          // Join the hi and lo parts.
-          Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        if (isCustom) {
+          Tmp3 = TLI.LowerOperation(Result, DAG);
+          if (Tmp3.getNode()) {
+            Tmp1 = LegalizeOp(Tmp3);
+            Tmp2 = LegalizeOp(Tmp3.getValue(1));
+          }
         } else {
-          // Big endian - avoid unaligned loads.
-          // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
-          // Load the top RoundWidth bits.
-          Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
-                              LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
-                              isNonTemporal, Alignment);
-
-          // Load the remaining ExtraWidth bits.
-          IncrementSize = RoundWidth / 8;
-          Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
-                             DAG.getIntPtrConstant(IncrementSize));
-          Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
-                              Node->getValueType(0), dl, Tmp1, Tmp2,
-                              LD->getSrcValue(), SVOffset + IncrementSize,
-                              ExtraVT, isVolatile, isNonTemporal,
-                              MinAlign(Alignment, IncrementSize));
-
-          // Build a factor node to remember that this load is independent of
-          // the other one.
-          Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
-                           Hi.getValue(1));
-
-          // Move the top bits to the right place.
-          Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
-                           DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
-
-          // Join the hi and lo parts.
-          Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
-        }
-
-        Tmp1 = LegalizeOp(Result);
-        Tmp2 = LegalizeOp(Ch);
-      } else {
-        switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
-        default: assert(0 && "This action is not supported yet!");
-        case TargetLowering::Custom:
-          isCustom = true;
-          // FALLTHROUGH
-        case TargetLowering::Legal:
-          Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                  Tmp1, Tmp2, LD->getOffset()),
-                           Result.getResNo());
-          Tmp1 = Result.getValue(0);
-          Tmp2 = Result.getValue(1);
-
-          if (isCustom) {
-            Tmp3 = TLI.LowerOperation(Result, DAG);
-            if (Tmp3.getNode()) {
-              Tmp1 = LegalizeOp(Tmp3);
-              Tmp2 = LegalizeOp(Tmp3.getValue(1));
-            }
-          } else {
-            // If this is an unaligned load and the target doesn't support it,
-            // expand it.
-            if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
-              const Type *Ty =
-                LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
-              unsigned ABIAlignment =
-                TLI.getTargetData()->getABITypeAlignment(Ty);
-              if (LD->getAlignment() < ABIAlignment){
-                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
-                                             DAG, TLI);
-                Tmp1 = Result.getOperand(0);
-                Tmp2 = Result.getOperand(1);
-                Tmp1 = LegalizeOp(Tmp1);
-                Tmp2 = LegalizeOp(Tmp2);
-              }
+          // If this is an unaligned load and the target doesn't support it,
+          // expand it.
+          if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
+            const Type *Ty =
+              LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
+            unsigned ABIAlignment =
+              TLI.getTargetData()->getABITypeAlignment(Ty);
+            if (LD->getAlignment() < ABIAlignment){
+              Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+                                           DAG, TLI);
+              Tmp1 = Result.getOperand(0);
+              Tmp2 = Result.getOperand(1);
+              Tmp1 = LegalizeOp(Tmp1);
+              Tmp2 = LegalizeOp(Tmp2);
             }
           }
-          break;
-        case TargetLowering::Expand:
-          if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
-            SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
-                                       LD->getPointerInfo(),
-                                       LD->isVolatile(), LD->isNonTemporal(),
-                                       LD->getAlignment());
-            unsigned ExtendOp;
-            switch (ExtType) {
-            case ISD::EXTLOAD:
-              ExtendOp = (SrcVT.isFloatingPoint() ?
-                          ISD::FP_EXTEND : ISD::ANY_EXTEND);
-              break;
-            case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
-            case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
-            default: llvm_unreachable("Unexpected extend load type!");
-            }
-            Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
-            Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
-            Tmp2 = LegalizeOp(Load.getValue(1));
+        }
+        break;
+      case TargetLowering::Expand:
+        if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
+          SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
+                                     LD->getPointerInfo(),
+                                     LD->isVolatile(), LD->isNonTemporal(),
+                                     LD->getAlignment());
+          unsigned ExtendOp;
+          switch (ExtType) {
+          case ISD::EXTLOAD:
+            ExtendOp = (SrcVT.isFloatingPoint() ?
+                        ISD::FP_EXTEND : ISD::ANY_EXTEND);
             break;
+          case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
+          case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
+          default: llvm_unreachable("Unexpected extend load type!");
           }
-          // FIXME: This does not work for vectors on most targets.  Sign- and
-          // zero-extend operations are currently folded into extending loads,
-          // whether they are legal or not, and then we end up here without any
-          // support for legalizing them.
-          assert(ExtType != ISD::EXTLOAD &&
-                 "EXTLOAD should always be supported!");
-          // Turn the unsupported load into an EXTLOAD followed by an explicit
-          // zero/sign extend inreg.
-          Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
-                                  Tmp1, Tmp2, LD->getSrcValue(),
-                                  LD->getSrcValueOffset(), SrcVT,
-                                  LD->isVolatile(), LD->isNonTemporal(),
-                                  LD->getAlignment());
-          SDValue ValRes;
-          if (ExtType == ISD::SEXTLOAD)
-            ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
-                                 Result.getValueType(),
-                                 Result, DAG.getValueType(SrcVT));
-          else
-            ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
-          Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
-          Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
+          Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
+          Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
+          Tmp2 = LegalizeOp(Load.getValue(1));
           break;
         }
+        // FIXME: This does not work for vectors on most targets.  Sign- and
+        // zero-extend operations are currently folded into extending loads,
+        // whether they are legal or not, and then we end up here without any
+        // support for legalizing them.
+        assert(ExtType != ISD::EXTLOAD &&
+               "EXTLOAD should always be supported!");
+        // Turn the unsupported load into an EXTLOAD followed by an explicit
+        // zero/sign extend inreg.
+        Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
+                                Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
+                                LD->isVolatile(), LD->isNonTemporal(),
+                                LD->getAlignment());
+        SDValue ValRes;
+        if (ExtType == ISD::SEXTLOAD)
+          ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
+                               Result.getValueType(),
+                               Result, DAG.getValueType(SrcVT));
+        else
+          ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
+        Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
+        Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
+        break;
       }
-
-      // Since loads produce two values, make sure to remember that we legalized
-      // both of them.
-      AddLegalizedOperand(SDValue(Node, 0), Tmp1);
-      AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-      return Op.getResNo() ? Tmp2 : Tmp1;
     }
+
+    // Since loads produce two values, make sure to remember that we legalized
+    // both of them.
+    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
+    return Op.getResNo() ? Tmp2 : Tmp1;
   }
   case ISD::STORE: {
     StoreSDNode *ST = cast<StoreSDNode>(Node);
@@ -1562,11 +1562,10 @@
   if (Op.getValueType().isVector())
     return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
                        false, false, 0);
-  else
-    return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
-                          MachinePointerInfo(),
-                          Vec.getValueType().getVectorElementType(),
-                          false, false, 0);
+  return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
+                        MachinePointerInfo(),
+                        Vec.getValueType().getVectorElementType(),
+                        false, false, 0);
 }
 
 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Tue Sep 21 12:04:51 2010
@@ -1111,8 +1111,7 @@
   assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
 
   Hi = DAG.getExtLoad(LD->getExtensionType(), NVT, dl, Chain, Ptr,
-                      LD->getSrcValue(), LD->getSrcValueOffset(),
-                      LD->getMemoryVT(), LD->isVolatile(),
+                      LD->getPointerInfo(), LD->getMemoryVT(), LD->isVolatile(),
                       LD->isNonTemporal(), LD->getAlignment());
 
   // Remember the chain.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Sep 21 12:04:51 2010
@@ -372,7 +372,7 @@
     ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
   DebugLoc dl = N->getDebugLoc();
   SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
-                               N->getSrcValue(), N->getSrcValueOffset(),
+                               N->getPointerInfo(),
                                N->getMemoryVT(), N->isVolatile(),
                                N->isNonTemporal(), N->getAlignment());
 
@@ -2459,7 +2459,9 @@
     // Load the value out, extending it from f32 to the destination float type.
     // FIXME: Avoid the extend by constructing the right constant pool?
     SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
-                                   FudgePtr, NULL, 0, MVT::f32,
+                                   FudgePtr,
+                                   MachinePointerInfo::getConstantPool(),
+                                   MVT::f32,
                                    false, false, Alignment);
     return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Sep 21 12:04:51 2010
@@ -1107,7 +1107,8 @@
   // Load back the required element.
   StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
   return DAG.getExtLoad(ISD::EXTLOAD, N->getValueType(0), dl, Store, StackPtr,
-                        SV, 0, EltVT, false, false, 0);
+                        MachinePointerInfo::getFixedStack(SPFI),
+                        EltVT, false, false, 0);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
@@ -2361,11 +2362,9 @@
   // Load information
   SDValue   Chain = LD->getChain();
   SDValue   BasePtr = LD->getBasePtr();
-  int       SVOffset = LD->getSrcValueOffset();
   unsigned  Align    = LD->getAlignment();
   bool      isVolatile = LD->isVolatile();
   bool      isNonTemporal = LD->isNonTemporal();
-  const Value *SV = LD->getSrcValue();
 
   EVT EltVT = WidenVT.getVectorElementType();
   EVT LdEltVT = LdVT.getVectorElementType();
@@ -2375,16 +2374,17 @@
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
   SmallVector<SDValue, 16> Ops(WidenNumElts);
   unsigned Increment = LdEltVT.getSizeInBits() / 8;
-  Ops[0] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, BasePtr, SV, SVOffset,
+  Ops[0] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, BasePtr,
+                          LD->getPointerInfo(),
                           LdEltVT, isVolatile, isNonTemporal, Align);
   LdChain.push_back(Ops[0].getValue(1));
   unsigned i = 0, Offset = Increment;
   for (i=1; i < NumElts; ++i, Offset += Increment) {
     SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
                                      BasePtr, DAG.getIntPtrConstant(Offset));
-    Ops[i] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, NewBasePtr, SV,
-                            SVOffset + Offset, LdEltVT, isVolatile,
-                            isNonTemporal, Align);
+    Ops[i] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, NewBasePtr,
+                            LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
+                            isVolatile, isNonTemporal, Align);
     LdChain.push_back(Ops[i].getValue(1));
   }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 12:04:51 2010
@@ -3956,16 +3956,6 @@
   return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
                  PtrInfo, VT, isVolatile, isNonTemporal, Alignment);
 }
-SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
-                                 SDValue Chain, SDValue Ptr,
-                                 const Value *SV,
-                                 int SVOffset, EVT MemVT,
-                                 bool isVolatile, bool isNonTemporal,
-                                 unsigned Alignment) {
-  SDValue Undef = getUNDEF(Ptr.getValueType());
-  return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
-                 SV, SVOffset, MemVT, isVolatile, isNonTemporal, Alignment);
-}
 
 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
                                  SDValue Chain, SDValue Ptr,

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Sep 21 12:04:51 2010
@@ -543,7 +543,8 @@
   SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
                               DAG.getConstant(8, MVT::i64));
   SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Base.getValue(1),
-                                  Tmp, NULL, 0, MVT::i32, false, false, 0);
+                                  Tmp, MachinePointerInfo(),
+                                  MVT::i32, false, false, 0);
   DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
   if (N->getValueType(0).isFloatingPoint())
   {
@@ -708,7 +709,7 @@
     SDValue Result;
     if (Op.getValueType() == MVT::i32)
       Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Chain, DataPtr,
-                              NULL, 0, MVT::i32, false, false, 0);
+                              MachinePointerInfo(), MVT::i32, false, false, 0);
     else
       Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr,
                            MachinePointerInfo(),
@@ -730,7 +731,7 @@
     SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
                                DAG.getConstant(8, MVT::i64));
     Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Result,
-                         NP, NULL,0, MVT::i32, false, false, 0);
+                         NP, MachinePointerInfo(), MVT::i32, false, false, 0);
     SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
                                 DAG.getConstant(8, MVT::i64));
     return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32,

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 21 12:04:51 2010
@@ -3069,7 +3069,8 @@
         EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
         if (GPR_idx != NumGPRs) {
           SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, dl, Chain, Arg,
-                                        NULL, 0, VT, false, false, 0);
+                                        MachinePointerInfo(), VT,
+                                        false, false, 0);
           MemOpChains.push_back(Load.getValue(1));
           RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
 

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Sep 21 12:04:51 2010
@@ -148,7 +148,7 @@
           FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
                               DAG.getConstant(Offset, MVT::i32));
           Load = DAG.getExtLoad(LoadOp, MVT::i32, dl, Chain, FIPtr,
-                                NULL, 0, ObjectVT, false, false, 0);
+                                MachinePointerInfo(), ObjectVT, false, false,0);
           Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
         }
         InVals.push_back(Load);

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 12:04:51 2010
@@ -511,10 +511,11 @@
     // FIXME: optimize the case where the src/dest is a load or store?
     SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
                                           N->getOperand(0),
-                                          MemTmp, NULL, 0, MemVT,
+                                          MemTmp, MachinePointerInfo(), MemVT,
                                           false, false, 0);
     SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, dl, Store, MemTmp,
-                                        NULL, 0, MemVT, false, false, 0);
+                                        MachinePointerInfo(),
+                                        MemVT, false, false, 0);
 
     // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
     // extload we created.  This will cause general havok on the dag because

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=114446&r1=114445&r2=114446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep 21 12:04:51 2010
@@ -392,24 +392,23 @@
 }
 
 SDValue XCoreTargetLowering::
-LowerLOAD(SDValue Op, SelectionDAG &DAG) const
-{
+LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
   LoadSDNode *LD = cast<LoadSDNode>(Op);
   assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
          "Unexpected extension type");
   assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
-  if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
+  if (allowsUnalignedMemoryAccesses(LD->getMemoryVT()))
     return SDValue();
-  }
+
   unsigned ABIAlignment = getTargetData()->
     getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
   // Leave aligned load alone.
-  if (LD->getAlignment() >= ABIAlignment) {
+  if (LD->getAlignment() >= ABIAlignment)
     return SDValue();
-  }
+
   SDValue Chain = LD->getChain();
   SDValue BasePtr = LD->getBasePtr();
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
   
   SDValue Base;
   int64_t Offset;
@@ -419,7 +418,7 @@
       // We've managed to infer better alignment information than the load
       // already has. Use an aligned load.
       //
-      return DAG.getLoad(getPointerTy(), dl, Chain, BasePtr,
+      return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
                          MachinePointerInfo(),
                          false, false, 0);
     }
@@ -434,40 +433,40 @@
     SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
     SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
     
-    SDValue LowAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, LowOffset);
-    SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset);
+    SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset);
+    SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset);
     
-    SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain,
+    SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
                               LowAddr, MachinePointerInfo(), false, false, 0);
-    SDValue High = DAG.getLoad(getPointerTy(), dl, Chain,
+    SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
                                HighAddr, MachinePointerInfo(), false, false, 0);
-    SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift);
-    SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift);
-    SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted);
-    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1),
+    SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
+    SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
+    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
+    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
                              High.getValue(1));
     SDValue Ops[] = { Result, Chain };
-    return DAG.getMergeValues(Ops, 2, dl);
+    return DAG.getMergeValues(Ops, 2, DL);
   }
   
   if (LD->getAlignment() == 2) {
-    int SVOffset = LD->getSrcValueOffset();
-    SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i32, dl, Chain,
-                                 BasePtr, LD->getSrcValue(), SVOffset, MVT::i16,
+    SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i32, DL, Chain,
+                                 BasePtr, LD->getPointerInfo(), MVT::i16,
                                  LD->isVolatile(), LD->isNonTemporal(), 2);
-    SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
+    SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
                                    DAG.getConstant(2, MVT::i32));
-    SDValue High = DAG.getExtLoad(ISD::EXTLOAD, MVT::i32, dl, Chain,
-                                  HighAddr, LD->getSrcValue(), SVOffset + 2,
+    SDValue High = DAG.getExtLoad(ISD::EXTLOAD, MVT::i32, DL, Chain,
+                                  HighAddr,
+                                  LD->getPointerInfo().getWithOffset(2),
                                   MVT::i16, LD->isVolatile(),
                                   LD->isNonTemporal(), 2);
-    SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High,
+    SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
                                       DAG.getConstant(16, MVT::i32));
-    SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, Low, HighShifted);
-    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1),
+    SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
+    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
                              High.getValue(1));
     SDValue Ops[] = { Result, Chain };
-    return DAG.getMergeValues(Ops, 2, dl);
+    return DAG.getMergeValues(Ops, 2, DL);
   }
   
   // Lower to a call to __misaligned_load(BasePtr).
@@ -484,12 +483,12 @@
                     false, false, 0, CallingConv::C, false,
                     /*isReturnValueUsed=*/true,
                     DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
-                    Args, DAG, dl);
+                    Args, DAG, DL);
 
   SDValue Ops[] =
     { CallResult.first, CallResult.second };
 
-  return DAG.getMergeValues(Ops, 2, dl);
+  return DAG.getMergeValues(Ops, 2, DL);
 }
 
 SDValue XCoreTargetLowering::



From stoklund at 2pi.dk  Tue Sep 21 12:12:15 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 17:12:15 -0000
Subject: [llvm-commits] [llvm] r114447 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp
Message-ID: <20100921171215.4357C2A6C12C@llvm.org>

Author: stoklund
Date: Tue Sep 21 12:12:15 2010
New Revision: 114447

URL: http://llvm.org/viewvc/llvm-project?rev=114447&view=rev
Log:
Remove dead method.

Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=114447&r1=114446&r2=114447&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Tue Sep 21 12:12:15 2010
@@ -388,11 +388,6 @@
 
     bool liveAt(SlotIndex index) const;
 
-    // liveBeforeAndAt - Check if the interval is live at the index and the
-    // index just before it. If index is liveAt, check if it starts a new live
-    // range.If it does, then check if the previous live range ends at index-1.
-    bool liveBeforeAndAt(SlotIndex index) const;
-
     /// killedAt - Return true if a live range ends at index. Note that the kill
     /// point is not contained in the half-open live range. It is usually the
     /// getDefIndex() slot following its last use.

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=114447&r1=114446&r2=114447&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Sep 21 12:12:15 2010
@@ -47,27 +47,6 @@
   return r->contains(I);
 }
 
-// liveBeforeAndAt - Check if the interval is live at the index and the index
-// just before it. If index is liveAt, check if it starts a new live range.
-// If it does, then check if the previous live range ends at index-1.
-bool LiveInterval::liveBeforeAndAt(SlotIndex I) const {
-  Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
-
-  if (r == ranges.begin())
-    return false;
-
-  --r;
-  if (!r->contains(I))
-    return false;
-  if (I != r->start)
-    return true;
-  // I is the start of a live range. Check if the previous live range ends
-  // at I-1.
-  if (r == ranges.begin())
-    return false;
-  return r->end == I;
-}
-
 /// killedAt - Return true if a live range ends at index. Note that the kill
 /// point is not contained in the half-open live range. It is usually the
 /// getDefIndex() slot following its last use.



From stoklund at 2pi.dk  Tue Sep 21 12:12:18 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 17:12:18 -0000
Subject: [llvm-commits] [llvm] r114448 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp
Message-ID: <20100921171218.7EDE42A6C12D@llvm.org>

Author: stoklund
Date: Tue Sep 21 12:12:18 2010
New Revision: 114448

URL: http://llvm.org/viewvc/llvm-project?rev=114448&view=rev
Log:
Add LiveInterval::find and use it for most LiveRange searching operations
instead of calling lower_bound or upper_bound directly.

This cleans up the search logic a bit because {lower,upper}_bound compare
LR->start by default, and it is usually simpler to search LR->end.

Funnelling all searches through one function also makes it possible to replace
the search algorithm with something faster than binary search.

Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=114448&r1=114447&r2=114448&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Tue Sep 21 12:12:18 2010
@@ -271,6 +271,19 @@
       return I;
     }
 
+    /// find - Return an iterator pointing to the first range that ends after
+    /// Pos, or end(). This is the same as advanceTo(begin(), Pos), but faster
+    /// when searching large intervals.
+    ///
+    /// If Pos is contained in a LiveRange, that range is returned.
+    /// If Pos is in a hole, the following LiveRange is returned.
+    /// If Pos is beyond endIndex, end() is returned.
+    iterator find(SlotIndex Pos);
+
+    const_iterator find(SlotIndex Pos) const {
+      return const_cast<LiveInterval*>(this)->find(Pos);
+    }
+
     void clear() {
       valnos.clear();
       ranges.clear();
@@ -386,12 +399,18 @@
       return index >= endIndex();
     }
 
-    bool liveAt(SlotIndex index) const;
+    bool liveAt(SlotIndex index) const {
+      const_iterator r = find(index);
+      return r != end() && r->start <= index;
+    }
 
     /// killedAt - Return true if a live range ends at index. Note that the kill
     /// point is not contained in the half-open live range. It is usually the
     /// getDefIndex() slot following its last use.
-    bool killedAt(SlotIndex index) const;
+    bool killedAt(SlotIndex index) const {
+      const_iterator r = find(index.getUseIndex());
+      return r != end() && r->end == index;
+    }
 
     /// killedInRange - Return true if the interval has kills in [Start,End).
     /// Note that the kill point is considered the end of a live range, so it is
@@ -421,11 +440,15 @@
 
     /// FindLiveRangeContaining - Return an iterator to the live range that
     /// contains the specified index, or end() if there is none.
-    const_iterator FindLiveRangeContaining(SlotIndex Idx) const;
+    iterator FindLiveRangeContaining(SlotIndex Idx) {
+      iterator I = find(Idx);
+      return I != end() && I->start <= Idx ? I : end();
+    }
 
-    /// FindLiveRangeContaining - Return an iterator to the live range that
-    /// contains the specified index, or end() if there is none.
-    iterator FindLiveRangeContaining(SlotIndex Idx);
+    const_iterator FindLiveRangeContaining(SlotIndex Idx) const {
+      const_iterator I = find(Idx);
+      return I != end() && I->start <= Idx ? I : end();
+    }
 
     /// findDefinedVNInfo - Find the by the specified
     /// index (register interval) or defined
@@ -467,7 +490,10 @@
 
     /// isInOneLiveRange - Return true if the range specified is entirely in the
     /// a single LiveRange of the live interval.
-    bool isInOneLiveRange(SlotIndex Start, SlotIndex End);
+    bool isInOneLiveRange(SlotIndex Start, SlotIndex End) const {
+      const_iterator r = find(Start);
+      return r != end() && r->containsRange(Start, End);
+    }
 
     /// removeRange - Remove the specified range from this interval.  Note that
     /// the range must be a single LiveRange in its entirety.

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=114448&r1=114447&r2=114448&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Sep 21 12:12:18 2010
@@ -30,37 +30,14 @@
 #include <algorithm>
 using namespace llvm;
 
-// An example for liveAt():
-//
-// this = [1,4), liveAt(0) will return false. The instruction defining this
-// spans slots [0,3]. The interval belongs to an spilled definition of the
-// variable it represents. This is because slot 1 is used (def slot) and spans
-// up to slot 3 (store slot).
-//
-bool LiveInterval::liveAt(SlotIndex I) const {
-  Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
-
-  if (r == ranges.begin())
-    return false;
-
-  --r;
-  return r->contains(I);
+// compEnd - Compare LiveRange end to Pos.
+// This argument ordering works for upper_bound.
+static inline bool compEnd(SlotIndex Pos, const LiveRange &LR) {
+  return Pos < LR.end;
 }
 
-/// killedAt - Return true if a live range ends at index. Note that the kill
-/// point is not contained in the half-open live range. It is usually the
-/// getDefIndex() slot following its last use.
-bool LiveInterval::killedAt(SlotIndex I) const {
-  Ranges::const_iterator r = std::lower_bound(ranges.begin(), ranges.end(), I);
-
-  // Now r points to the first interval with start >= I, or ranges.end().
-  if (r == ranges.begin())
-    return false;
-
-  --r;
-  // Now r points to the last interval with end <= I.
-  // r->end is the kill point.
-  return r->end == I;
+LiveInterval::iterator LiveInterval::find(SlotIndex Pos) {
+  return std::upper_bound(begin(), end(), Pos, compEnd);
 }
 
 /// killedInRange - Return true if the interval has kills in [Start,End).
@@ -309,25 +286,14 @@
   return ranges.insert(it, LR);
 }
 
-/// isInOneLiveRange - Return true if the range specified is entirely in
-/// a single LiveRange of the live interval.
-bool LiveInterval::isInOneLiveRange(SlotIndex Start, SlotIndex End) {
-  Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
-  if (I == ranges.begin())
-    return false;
-  --I;
-  return I->containsRange(Start, End);
-}
-
 
 /// removeRange - Remove the specified range from this interval.  Note that
 /// the range must be in a single LiveRange in its entirety.
 void LiveInterval::removeRange(SlotIndex Start, SlotIndex End,
                                bool RemoveDeadValNo) {
   // Find the LiveRange containing this span.
-  Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start);
-  assert(I != ranges.begin() && "Range is not in interval!");
-  --I;
+  Ranges::iterator I = find(Start);
+  assert(I != ranges.end() && "Range is not in interval!");
   assert(I->containsRange(Start, End) && "Range is not entirely in interval!");
 
   // If the span we are removing is at the start of the LiveRange, adjust it.
@@ -384,32 +350,6 @@
   markValNoForDeletion(ValNo);
 }
 
-/// getLiveRangeContaining - Return the live range that contains the
-/// specified index, or null if there is none.
-LiveInterval::const_iterator
-LiveInterval::FindLiveRangeContaining(SlotIndex Idx) const {
-  const_iterator It = std::upper_bound(begin(), end(), Idx);
-  if (It != ranges.begin()) {
-    --It;
-    if (It->contains(Idx))
-      return It;
-  }
-
-  return end();
-}
-
-LiveInterval::iterator
-LiveInterval::FindLiveRangeContaining(SlotIndex Idx) {
-  iterator It = std::upper_bound(begin(), end(), Idx);
-  if (It != begin()) {
-    --It;
-    if (It->contains(Idx))
-      return It;
-  }
-
-  return end();
-}
-
 /// findDefinedVNInfo - Find the VNInfo defined by the specified
 /// index (register interval).
 VNInfo *LiveInterval::findDefinedVNInfoForRegInt(SlotIndex Idx) const {



From sabre at nondot.org  Tue Sep 21 12:24:05 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 17:24:05 -0000
Subject: [llvm-commits] [llvm] r114449 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <20100921172405.480632A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 12:24:05 2010
New Revision: 114449

URL: http://llvm.org/viewvc/llvm-project?rev=114449&view=rev
Log:
fix the code that infers SV info to be correct when dealing
with an indexed load/store that has an offset in the index.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114449&r1=114448&r2=114449&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 12:24:05 2010
@@ -636,10 +636,6 @@
                      SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,
                      EVT MemVT, bool isVolatile,
                      bool isNonTemporal, unsigned Alignment);
-/*  SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
-                     SDValue Chain, SDValue Ptr, const Value *SV,
-                     int SVOffset, EVT MemVT, bool isVolatile,
-                     bool isNonTemporal, unsigned Alignment);*/
   SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
                          SDValue Offset, ISD::MemIndexedMode AM);
   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114449&r1=114448&r2=114449&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 12:24:05 2010
@@ -3724,12 +3724,6 @@
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(MemVT);
 
-  // Check if the memory reference references a frame index
-  if (!PtrVal)
-    if (const FrameIndexSDNode *FI =
-          dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
-      PtrVal = PseudoSourceValue::getFixedStack(FI->getIndex());
-
   MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
 
@@ -3869,17 +3863,45 @@
                       bool isVolatile, bool isNonTemporal,
                       unsigned Alignment) {
 
-  // Check if the memory reference references a frame index
-  if (!SV)
-    if (const FrameIndexSDNode *FI =
-        dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
-      SV = PseudoSourceValue::getFixedStack(FI->getIndex());
-  
   return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset,
                  MachinePointerInfo(SV, SVOffset), MemVT, isVolatile,
                  isNonTemporal, Alignment);
 }
 
+/// InferPointerInfo - If the specified ptr/offset is a frame index, infer a
+/// MachinePointerInfo record from it.  This is particularly useful because the
+/// code generator has many cases where it doesn't bother passing in a
+/// MachinePointerInfo to getLoad or getStore when it has "FI+Cst".
+static MachinePointerInfo InferPointerInfo(SDValue Ptr, int64_t Offset = 0) {
+  // If this is FI+Offset, we can model it.
+  if (const FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr))
+    return MachinePointerInfo::getFixedStack(FI->getIndex(), Offset);
+
+  // If this is (FI+Offset1)+Offset2, we can model it.
+  if (Ptr.getOpcode() != ISD::ADD ||
+      !isa<ConstantSDNode>(Ptr.getOperand(1)) ||
+      !isa<FrameIndexSDNode>(Ptr.getOperand(0)))
+    return MachinePointerInfo();
+  
+  int FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
+  return MachinePointerInfo::getFixedStack(FI, Offset+
+                       cast<ConstantSDNode>(Ptr.getOperand(1))->getSExtValue());
+}
+
+/// InferPointerInfo - If the specified ptr/offset is a frame index, infer a
+/// MachinePointerInfo record from it.  This is particularly useful because the
+/// code generator has many cases where it doesn't bother passing in a
+/// MachinePointerInfo to getLoad or getStore when it has "FI+Cst".
+static MachinePointerInfo InferPointerInfo(SDValue Ptr, SDValue OffsetOp) {
+  // If the 'Offset' value isn't a constant, we can't handle this.
+  if (ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
+    return InferPointerInfo(Ptr, OffsetNode->getSExtValue());
+  if (OffsetOp.getOpcode() == ISD::UNDEF)
+    return InferPointerInfo(Ptr);
+  return MachinePointerInfo();
+}
+  
+
 SDValue
 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
                       EVT VT, DebugLoc dl, SDValue Chain,
@@ -3890,12 +3912,18 @@
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(VT);
 
-  MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOLoad;
   if (isVolatile)
     Flags |= MachineMemOperand::MOVolatile;
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
+  
+  // If we don't have a PtrInfo, infer the trivial frame index case to simplify
+  // clients.
+  if (PtrInfo.V == 0)
+    PtrInfo = InferPointerInfo(Ptr, Offset);
+  
+  MachineFunction &MF = getMachineFunction();
   MachineMemOperand *MMO =
     MF.getMachineMemOperand(PtrInfo, Flags, MemVT.getStoreSize(), Alignment);
   return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
@@ -3975,8 +4003,8 @@
   assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
          "Load is already a indexed load!");
   return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
-                 LD->getChain(), Base, Offset, LD->getSrcValue(),
-                 LD->getSrcValueOffset(), LD->getMemoryVT(),
+                 LD->getChain(), Base, Offset, LD->getPointerInfo(),
+                 LD->getMemoryVT(),
                  LD->isVolatile(), LD->isNonTemporal(), LD->getAlignment());
 }
 
@@ -3987,12 +4015,16 @@
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(Val.getValueType());
 
-  MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOStore;
   if (isVolatile)
     Flags |= MachineMemOperand::MOVolatile;
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
+  
+  if (PtrInfo.V == 0)
+    PtrInfo = InferPointerInfo(Ptr);
+
+  MachineFunction &MF = getMachineFunction();
   MachineMemOperand *MMO =
     MF.getMachineMemOperand(PtrInfo, Flags,
                             Val.getValueType().getStoreSize(), Alignment);
@@ -4004,11 +4036,6 @@
                                SDValue Ptr,
                  const Value *SV, int SVOffset, bool isVolatile,
                  bool isNonTemporal, unsigned Alignment) {
-  // Check if the memory reference references a frame index
-  if (!SV)
-    if (const FrameIndexSDNode *FI =
-        dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
-      SV = PseudoSourceValue::getFixedStack(FI->getIndex());
   
   return getStore(Chain, dl, Val, Ptr, MachinePointerInfo(SV, SVOffset),
                   isVolatile, isNonTemporal, Alignment);
@@ -4044,12 +4071,6 @@
                                     bool isVolatile, bool isNonTemporal,
                                     unsigned Alignment) {
 
-  // Check if the memory reference references a frame index
-  if (!SV)
-    if (const FrameIndexSDNode *FI =
-        dyn_cast<const FrameIndexSDNode>(Ptr.getNode()))
-      SV = PseudoSourceValue::getFixedStack(FI->getIndex());
- 
   return getTruncStore(Chain, dl, Val, Ptr, MachinePointerInfo(SV, SVOffset),
                        SVT, isVolatile, isNonTemporal, Alignment);
 }  
@@ -4061,12 +4082,16 @@
   if (Alignment == 0)  // Ensure that codegen never sees alignment 0
     Alignment = getEVTAlignment(SVT);
 
-  MachineFunction &MF = getMachineFunction();
   unsigned Flags = MachineMemOperand::MOStore;
   if (isVolatile)
     Flags |= MachineMemOperand::MOVolatile;
   if (isNonTemporal)
     Flags |= MachineMemOperand::MONonTemporal;
+  
+  if (PtrInfo.V == 0)
+    PtrInfo = InferPointerInfo(Ptr);
+
+  MachineFunction &MF = getMachineFunction();
   MachineMemOperand *MMO =
     MF.getMachineMemOperand(PtrInfo, Flags, SVT.getStoreSize(), Alignment);
 



From sabre at nondot.org  Tue Sep 21 12:28:52 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 17:28:52 -0000
Subject: [llvm-commits] [llvm] r114450 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <20100921172852.EB5EB2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 12:28:52 2010
New Revision: 114450

URL: http://llvm.org/viewvc/llvm-project?rev=114450&view=rev
Log:
eliminate last SelectionDAG::getLoad old entrypoint, on to stores.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114450&r1=114449&r2=114450&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 12:28:52 2010
@@ -641,11 +641,6 @@
   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
                   EVT VT, DebugLoc dl,
                   SDValue Chain, SDValue Ptr, SDValue Offset,
-                  const Value *SV, int SVOffset, EVT MemVT,
-                  bool isVolatile, bool isNonTemporal, unsigned Alignment);
-  SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
-                  EVT VT, DebugLoc dl,
-                  SDValue Chain, SDValue Ptr, SDValue Offset,
                   MachinePointerInfo PtrInfo, EVT MemVT,
                   bool isVolatile, bool isNonTemporal, unsigned Alignment);
   SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=114450&r1=114449&r2=114450&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Tue Sep 21 12:28:52 2010
@@ -455,7 +455,7 @@
   if (L->getExtensionType() == ISD::NON_EXTLOAD) {
     NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(),
                        NVT, dl, L->getChain(), L->getBasePtr(), L->getOffset(),
-                       L->getSrcValue(), L->getSrcValueOffset(), NVT,
+                       L->getPointerInfo(), NVT,
                        L->isVolatile(), L->isNonTemporal(), L->getAlignment());
     // Legalized the chain result - switch anything that used the old chain to
     // use the new one.
@@ -466,8 +466,7 @@
   // Do a non-extending load followed by FP_EXTEND.
   NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD,
                      L->getMemoryVT(), dl, L->getChain(),
-                     L->getBasePtr(), L->getOffset(),
-                     L->getSrcValue(), L->getSrcValueOffset(),
+                     L->getBasePtr(), L->getOffset(), L->getPointerInfo(),
                      L->getMemoryVT(), L->isVolatile(),
                      L->isNonTemporal(), L->getAlignment());
   // Legalized the chain result - switch anything that used the old chain to

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=114450&r1=114449&r2=114450&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Sep 21 12:28:52 2010
@@ -171,7 +171,7 @@
                                N->getDebugLoc(),
                                N->getChain(), N->getBasePtr(),
                                DAG.getUNDEF(N->getBasePtr().getValueType()),
-                               N->getSrcValue(), N->getSrcValueOffset(),
+                               N->getPointerInfo(),
                                N->getMemoryVT().getVectorElementType(),
                                N->isVolatile(), N->isNonTemporal(),
                                N->getOriginalAlignment());
@@ -751,8 +751,6 @@
   SDValue Ch = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
-  const Value *SV = LD->getSrcValue();
-  int SVOffset = LD->getSrcValueOffset();
   EVT MemoryVT = LD->getMemoryVT();
   unsigned Alignment = LD->getOriginalAlignment();
   bool isVolatile = LD->isVolatile();
@@ -762,14 +760,15 @@
   GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
 
   Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
-                   SV, SVOffset, LoMemVT, isVolatile, isNonTemporal, Alignment);
+                   LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
+                   Alignment);
 
   unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
   Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                     DAG.getIntPtrConstant(IncrementSize));
-  SVOffset += IncrementSize;
   Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
-                   SV, SVOffset, HiMemVT, isVolatile, isNonTemporal, Alignment);
+                   LD->getPointerInfo().getWithOffset(IncrementSize),
+                   HiMemVT, isVolatile, isNonTemporal, Alignment);
 
   // Build a factor node to remember that this load is independent of the
   // other one.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114450&r1=114449&r2=114450&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 12:28:52 2010
@@ -3855,19 +3855,6 @@
   return SDValue(N, 0);
 }
 
-SDValue
-SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
-                      EVT VT, DebugLoc dl, SDValue Chain,
-                      SDValue Ptr, SDValue Offset,
-                      const Value *SV, int SVOffset, EVT MemVT,
-                      bool isVolatile, bool isNonTemporal,
-                      unsigned Alignment) {
-
-  return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset,
-                 MachinePointerInfo(SV, SVOffset), MemVT, isVolatile,
-                 isNonTemporal, Alignment);
-}
-
 /// InferPointerInfo - If the specified ptr/offset is a frame index, infer a
 /// MachinePointerInfo record from it.  This is particularly useful because the
 /// code generator has many cases where it doesn't bother passing in a



From sabre at nondot.org  Tue Sep 21 12:42:32 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 17:42:32 -0000
Subject: [llvm-commits] [llvm] r114452 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/Target/Alpha/AlphaISelLowering.cpp
 lib/Target/PowerPC/PPCISelLowering.cpp
 lib/Target/XCore/XCoreISelLowering.cpp
Message-ID: <20100921174232.568232A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 12:42:31 2010
New Revision: 114452

URL: http://llvm.org/viewvc/llvm-project?rev=114452&view=rev
Log:
eliminate an old SelectionDAG::getTruncStore method, propagating
MachinePointerInfo around more.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 12:42:31 2010
@@ -663,10 +663,6 @@
                         bool isNonTemporal, bool isVolatile,
                         unsigned Alignment);
   SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
-                        const Value *SV, int SVOffset, EVT TVT,
-                        bool isNonTemporal, bool isVolatile,
-                        unsigned Alignment);
-  SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
                         EVT TVT, MachineMemOperand *MMO);
   SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
                            SDValue Offset, ISD::MemIndexedMode AM);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 12:42:31 2010
@@ -5969,8 +5969,7 @@
     if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
-                                 Ptr, ST->getSrcValue(),
-                                 ST->getSrcValueOffset(), ST->getMemoryVT(),
+                                 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
                                  ST->isVolatile(), ST->isNonTemporal(), Align);
     }
   }
@@ -5986,7 +5985,7 @@
       // Replace the chain to avoid dependency.
       if (ST->isTruncatingStore()) {
         ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
-                                      ST->getSrcValue(),ST->getSrcValueOffset(),
+                                      ST->getPointerInfo(),
                                       ST->getMemoryVT(), ST->isVolatile(),
                                       ST->isNonTemporal(), ST->getAlignment());
       } else {
@@ -6025,8 +6024,7 @@
     AddToWorkList(Value.getNode());
     if (Shorter.getNode())
       return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
-                               Ptr, ST->getSrcValue(),
-                               ST->getSrcValueOffset(), ST->getMemoryVT(),
+                               Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
                                ST->isVolatile(), ST->isNonTemporal(),
                                ST->getAlignment());
 
@@ -6059,8 +6057,7 @@
       TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
                             ST->getMemoryVT())) {
     return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
-                             Ptr, ST->getSrcValue(),
-                             ST->getSrcValueOffset(), ST->getMemoryVT(),
+                             Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
                              ST->isVolatile(), ST->isNonTemporal(),
                              ST->getAlignment());
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 21 12:42:31 2010
@@ -395,7 +395,6 @@
   SDValue Val = ST->getValue();
   EVT VT = Val.getValueType();
   int Alignment = ST->getAlignment();
-  int SVOffset = ST->getSrcValueOffset();
   DebugLoc dl = ST->getDebugLoc();
   if (ST->getMemoryVT().isFloatingPoint() ||
       ST->getMemoryVT().isVector()) {
@@ -405,9 +404,8 @@
       // same size, then a (misaligned) int store.
       // FIXME: Does not handle truncating floating point stores!
       SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
-      return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
-                          SVOffset, ST->isVolatile(), ST->isNonTemporal(),
-                          Alignment);
+      return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
+                          ST->isVolatile(), ST->isNonTemporal(), Alignment);
     } else {
       // Do a (aligned) store to a stack slot, then copy from the stack slot
       // to the final destination using (unaligned) integer loads and stores.
@@ -487,13 +485,13 @@
   // Store the two parts
   SDValue Store1, Store2;
   Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
-                             ST->getSrcValue(), SVOffset, NewStoredVT,
+                             ST->getPointerInfo(), NewStoredVT,
                              ST->isVolatile(), ST->isNonTemporal(), Alignment);
   Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                     DAG.getConstant(IncrementSize, TLI.getPointerTy()));
   Alignment = MinAlign(Alignment, IncrementSize);
   Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
-                             ST->getSrcValue(), SVOffset + IncrementSize,
+                             ST->getPointerInfo().getWithOffset(IncrementSize),
                              NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
                              Alignment);
 
@@ -722,7 +720,6 @@
   SDValue Tmp1 = ST->getChain();
   SDValue Tmp2 = ST->getBasePtr();
   SDValue Tmp3;
-  int SVOffset = ST->getSrcValueOffset();
   unsigned Alignment = ST->getAlignment();
   bool isVolatile = ST->isVolatile();
   bool isNonTemporal = ST->isNonTemporal();
@@ -733,16 +730,20 @@
       Tmp3 = DAG.getConstant(CFP->getValueAPF().
                                       bitcastToAPInt().zextOrTrunc(32),
                               MVT::i32);
-      return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
-                          SVOffset, isVolatile, isNonTemporal, Alignment);
-    } else if (CFP->getValueType(0) == MVT::f64) {
+      return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                          isVolatile, isNonTemporal, Alignment);
+    }
+    
+    if (CFP->getValueType(0) == MVT::f64) {
       // If this target supports 64-bit registers, do a single 64-bit store.
       if (getTypeAction(MVT::i64) == Legal) {
         Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
                                   zextOrTrunc(64), MVT::i64);
-        return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
-                            SVOffset, isVolatile, isNonTemporal, Alignment);
-      } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
+        return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                            isVolatile, isNonTemporal, Alignment);
+      }
+      
+      if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
         // Otherwise, if the target supports 32-bit registers, use 2 32-bit
         // stores.  If the target supports neither 32- nor 64-bits, this
         // xform is certainly not worth it.
@@ -751,11 +752,12 @@
         SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
         if (TLI.isBigEndian()) std::swap(Lo, Hi);
 
-        Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
-                          SVOffset, isVolatile, isNonTemporal, Alignment);
+        Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
+                          isNonTemporal, Alignment);
         Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
                             DAG.getIntPtrConstant(4));
-        Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
+        Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
+                          ST->getPointerInfo().getWithOffset(4),
                           isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
 
         return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
@@ -1370,7 +1372,6 @@
     StoreSDNode *ST = cast<StoreSDNode>(Node);
     Tmp1 = LegalizeOp(ST->getChain());    // Legalize the chain.
     Tmp2 = LegalizeOp(ST->getBasePtr());  // Legalize the pointer.
-    int SVOffset = ST->getSrcValueOffset();
     unsigned Alignment = ST->getAlignment();
     bool isVolatile = ST->isVolatile();
     bool isNonTemporal = ST->isNonTemporal();
@@ -1411,7 +1412,7 @@
           Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
                              TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
           Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
-                                ST->getSrcValue(), SVOffset, isVolatile,
+                                ST->getPointerInfo(), isVolatile,
                                 isNonTemporal, Alignment);
           break;
         }
@@ -1430,9 +1431,8 @@
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
                                     StVT.getStoreSizeInBits());
         Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
-        Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
-                                   SVOffset, NVT, isVolatile, isNonTemporal,
-                                   Alignment);
+        Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                   NVT, isVolatile, isNonTemporal, Alignment);
       } else if (StWidth & (StWidth - 1)) {
         // If not storing a power-of-2 number of bits, expand as two stores.
         assert(!StVT.isVector() && "Unsupported truncstore!");
@@ -1450,8 +1450,8 @@
         if (TLI.isLittleEndian()) {
           // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE at +2:i8 (srl X, 16)
           // Store the bottom RoundWidth bits.
-          Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
-                                 SVOffset, RoundVT,
+          Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                 RoundVT,
                                  isVolatile, isNonTemporal, Alignment);
 
           // Store the remaining ExtraWidth bits.
@@ -1460,9 +1460,9 @@
                              DAG.getIntPtrConstant(IncrementSize));
           Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
                            DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
-          Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
-                                 SVOffset + IncrementSize, ExtraVT, isVolatile,
-                                 isNonTemporal,
+          Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
+                             ST->getPointerInfo().getWithOffset(IncrementSize),
+                                 ExtraVT, isVolatile, isNonTemporal,
                                  MinAlign(Alignment, IncrementSize));
         } else {
           // Big endian - avoid unaligned stores.
@@ -1470,17 +1470,16 @@
           // Store the top RoundWidth bits.
           Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
                            DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
-          Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
-                                 SVOffset, RoundVT, isVolatile, isNonTemporal,
-                                 Alignment);
+          Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
+                                 RoundVT, isVolatile, isNonTemporal, Alignment);
 
           // Store the remaining ExtraWidth bits.
           IncrementSize = RoundWidth / 8;
           Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
                              DAG.getIntPtrConstant(IncrementSize));
-          Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
-                                 SVOffset + IncrementSize, ExtraVT, isVolatile,
-                                 isNonTemporal,
+          Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
+                              ST->getPointerInfo().getWithOffset(IncrementSize),
+                                 ExtraVT, isVolatile, isNonTemporal,
                                  MinAlign(Alignment, IncrementSize));
         }
 
@@ -1514,9 +1513,8 @@
           // TRUNCSTORE:i16 i32 -> STORE i16
           assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
           Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
-          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
-                                SVOffset, isVolatile, isNonTemporal,
-                                Alignment);
+          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                isVolatile, isNonTemporal, Alignment);
           break;
         }
       }
@@ -1772,7 +1770,7 @@
 
   FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
   int SPFI = StackPtrFI->getIndex();
-  const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
+  MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
 
   unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
   unsigned SlotSize = SlotVT.getSizeInBits();
@@ -1786,22 +1784,21 @@
 
   if (SrcSize > SlotSize)
     Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
-                              SV, 0, SlotVT, false, false, SrcAlign);
+                              PtrInfo, SlotVT, false, false, SrcAlign);
   else {
     assert(SrcSize == SlotSize && "Invalid store");
     Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
-                         SV, 0, false, false, SrcAlign);
+                         PtrInfo, false, false, SrcAlign);
   }
 
   // Result is a load from the stack slot.
   if (SlotSize == DestSize)
-    return DAG.getLoad(DestVT, dl, Store, FIPtr, MachinePointerInfo(SV),
+    return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
                        false, false, DestAlign);
 
   assert(SlotSize < DestSize && "Unknown extension!");
   return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr,
-                        MachinePointerInfo(SV), SlotVT,
-                        false, false, DestAlign);
+                        PtrInfo, SlotVT, false, false, DestAlign);
 }
 
 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Tue Sep 21 12:42:31 2010
@@ -1419,7 +1419,7 @@
   GetExpandedOp(ST->getValue(), Lo, Hi);
 
   return DAG.getTruncStore(Chain, N->getDebugLoc(), Hi, Ptr,
-                           ST->getSrcValue(), ST->getSrcValueOffset(),
+                           ST->getPointerInfo(),
                            ST->getMemoryVT(), ST->isVolatile(),
                            ST->isNonTemporal(), ST->getAlignment());
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Sep 21 12:42:31 2010
@@ -365,14 +365,13 @@
   if (N->isTruncatingStore())
     return DAG.getTruncStore(N->getChain(), dl,
                              GetScalarizedVector(N->getOperand(1)),
-                             N->getBasePtr(),
-                             N->getSrcValue(), N->getSrcValueOffset(),
+                             N->getBasePtr(), N->getPointerInfo(),
                              N->getMemoryVT().getVectorElementType(),
                              N->isVolatile(), N->isNonTemporal(),
                              N->getAlignment());
 
   return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
-                      N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
+                      N->getBasePtr(), N->getPointerInfo(),
                       N->isVolatile(), N->isNonTemporal(),
                       N->getOriginalAlignment());
 }
@@ -1118,7 +1117,6 @@
   bool isTruncating = N->isTruncatingStore();
   SDValue Ch  = N->getChain();
   SDValue Ptr = N->getBasePtr();
-  int SVOffset = N->getSrcValueOffset();
   EVT MemoryVT = N->getMemoryVT();
   unsigned Alignment = N->getOriginalAlignment();
   bool isVol = N->isVolatile();
@@ -1132,22 +1130,23 @@
   unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
 
   if (isTruncating)
-    Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getSrcValue(), SVOffset,
+    Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
                            LoMemVT, isVol, isNT, Alignment);
   else
-    Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getSrcValue(), SVOffset,
+    Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
                       isVol, isNT, Alignment);
 
   // Increment the pointer to the other half.
   Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
                     DAG.getIntPtrConstant(IncrementSize));
-  SVOffset += IncrementSize;
 
   if (isTruncating)
-    Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, N->getSrcValue(), SVOffset,
+    Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
+                           N->getPointerInfo().getWithOffset(IncrementSize),
                            HiMemVT, isVol, isNT, Alignment);
   else
-    Hi = DAG.getStore(Ch, DL, Hi, Ptr, N->getSrcValue(), SVOffset,
+    Hi = DAG.getStore(Ch, DL, Hi, Ptr,
+                      N->getPointerInfo().getWithOffset(IncrementSize),
                       isVol, isNT, Alignment);
 
   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
@@ -2403,8 +2402,6 @@
   // element type or scalar stores.
   SDValue  Chain = ST->getChain();
   SDValue  BasePtr = ST->getBasePtr();
-  const    Value *SV = ST->getSrcValue();
-  int      SVOffset = ST->getSrcValueOffset();
   unsigned Align = ST->getAlignment();
   bool     isVolatile = ST->isVolatile();
   bool     isNonTemporal = ST->isNonTemporal();
@@ -2431,9 +2428,9 @@
       do {
         SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
                                    DAG.getIntPtrConstant(Idx));
-        StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
-                                       SVOffset + Offset, isVolatile,
-                                       isNonTemporal,
+        StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
+                                    ST->getPointerInfo().getWithOffset(Offset),
+                                       isVolatile, isNonTemporal,
                                        MinAlign(Align, Offset)));
         StWidth -= NewVTWidth;
         Offset += Increment;
@@ -2451,9 +2448,10 @@
       do {
         SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
                       DAG.getIntPtrConstant(Idx++));
-        StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
-                                       SVOffset + Offset, isVolatile,
-                                       isNonTemporal, MinAlign(Align, Offset)));
+        StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
+                                    ST->getPointerInfo().getWithOffset(Offset),
+                                       isVolatile, isNonTemporal,
+                                       MinAlign(Align, Offset)));
         StWidth -= NewVTWidth;
         Offset += Increment;
         BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
@@ -2472,8 +2470,6 @@
   // and then store it.  Instead, we extract each element and then store it.
   SDValue  Chain = ST->getChain();
   SDValue  BasePtr = ST->getBasePtr();
-  const    Value *SV = ST->getSrcValue();
-  int      SVOffset = ST->getSrcValueOffset();
   unsigned Align = ST->getAlignment();
   bool     isVolatile = ST->isVolatile();
   bool     isNonTemporal = ST->isNonTemporal();
@@ -2497,8 +2493,8 @@
   unsigned NumElts = StVT.getVectorNumElements();
   SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
                             DAG.getIntPtrConstant(0));
-  StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
-                                      SVOffset, StEltVT,
+  StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
+                                      ST->getPointerInfo(), StEltVT,
                                       isVolatile, isNonTemporal, Align));
   unsigned Offset = Increment;
   for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
@@ -2506,9 +2502,9 @@
                                      BasePtr, DAG.getIntPtrConstant(Offset));
     SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
                             DAG.getIntPtrConstant(0));
-    StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
-                                        SVOffset + Offset, StEltVT,
-                                        isVolatile, isNonTemporal,
+    StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
+                                      ST->getPointerInfo().getWithOffset(Offset),
+                                        StEltVT, isVolatile, isNonTemporal,
                                         MinAlign(Align, Offset)));
   }
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 12:42:31 2010
@@ -4053,16 +4053,6 @@
 }
 
 SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
-                                    SDValue Ptr, const Value *SV,
-                                    int SVOffset, EVT SVT,
-                                    bool isVolatile, bool isNonTemporal,
-                                    unsigned Alignment) {
-
-  return getTruncStore(Chain, dl, Val, Ptr, MachinePointerInfo(SV, SVOffset),
-                       SVT, isVolatile, isNonTemporal, Alignment);
-}  
-  
-SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
                                     SDValue Ptr, MachinePointerInfo PtrInfo,
                                     EVT SVT,bool isVolatile, bool isNonTemporal,
                                     unsigned Alignment) {

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Sep 21 12:42:31 2010
@@ -558,7 +558,8 @@
 
   SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
                                     DAG.getConstant(8, MVT::i64));
-  Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
+  Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp,
+                            MachinePointerInfo(),
                             MVT::i32, false, false, 0);
 }
 
@@ -734,7 +735,8 @@
                          NP, MachinePointerInfo(), MVT::i32, false, false, 0);
     SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
                                 DAG.getConstant(8, MVT::i64));
-    return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32,
+    return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD,
+                             MachinePointerInfo(), MVT::i32,
                              false, false, 0);
   }
   case ISD::VASTART: {
@@ -754,7 +756,8 @@
     return DAG.getTruncStore(S1, dl,
                              DAG.getConstant(FuncInfo->getVarArgsOffset(),
                                              MVT::i64),
-                             SA2, NULL, 0, MVT::i32, false, false, 0);
+                             SA2, MachinePointerInfo(),
+                             MVT::i32, false, false, 0);
   }
   case ISD::RETURNADDR:
     return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc(), MVT::i64);

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 21 12:42:31 2010
@@ -1406,15 +1406,17 @@
 
   // Store first byte : number of int regs
   SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
-                                         Op.getOperand(1), SV, 0, MVT::i8,
-                                         false, false, 0);
+                                         Op.getOperand(1),
+                                         MachinePointerInfo(SV),
+                                         MVT::i8, false, false, 0);
   uint64_t nextOffset = FPROffset;
   SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
                                   ConstFPROffset);
 
   // Store second byte : number of float regs
   SDValue secondStore =
-    DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8,
+    DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
+                      MachinePointerInfo(SV, nextOffset), MVT::i8,
                       false, false, 0);
   nextOffset += StackOffset;
   nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
@@ -1919,7 +1921,7 @@
           unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
           SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
           SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
-                                            NULL, 0,
+                                            MachinePointerInfo(),
                                             ObjSize==1 ? MVT::i8 : MVT::i16,
                                             false, false, 0);
           MemOps.push_back(Store);

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=114452&r1=114451&r2=114452&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep 21 12:42:31 2010
@@ -512,18 +512,17 @@
   DebugLoc dl = Op.getDebugLoc();
   
   if (ST->getAlignment() == 2) {
-    int SVOffset = ST->getSrcValueOffset();
     SDValue Low = Value;
     SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
                                       DAG.getConstant(16, MVT::i32));
     SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
-                                         ST->getSrcValue(), SVOffset, MVT::i16,
+                                         ST->getPointerInfo(), MVT::i16,
                                          ST->isVolatile(), ST->isNonTemporal(),
                                          2);
     SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
                                    DAG.getConstant(2, MVT::i32));
     SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
-                                          ST->getSrcValue(), SVOffset + 2,
+                                          ST->getPointerInfo().getWithOffset(2),
                                           MVT::i16, ST->isVolatile(),
                                           ST->isNonTemporal(), 2);
     return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);



From sabre at nondot.org  Tue Sep 21 12:50:43 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 17:50:43 -0000
Subject: [llvm-commits] [llvm] r114453 - in /llvm/trunk/lib/Target:
 MBlaze/MBlazeISelLowering.cpp Mips/MipsISelLowering.cpp
 X86/X86ISelLowering.cpp
Message-ID: <20100921175043.6C93B2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 12:50:43 2010
New Revision: 114453

URL: http://llvm.org/viewvc/llvm-project?rev=114453&view=rev
Log:
eliminate some uses of the getStore overload.

Modified:
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=114453&r1=114452&r2=114453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Tue Sep 21 12:50:43 2010
@@ -456,7 +456,8 @@
   // vastart just stores the address of the VarArgsFrameIndex slot into the
   // memory location argument.
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
+  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
+                      MachinePointerInfo(SV),
                       false, false, 0);
 }
 
@@ -591,7 +592,8 @@
 
       // emit ISD::STORE whichs stores the
       // parameter value to a stack Location
-      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
+      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
+                                         MachinePointerInfo(),
                                          false, false, 0));
     }
   }
@@ -809,7 +811,8 @@
       int FI = MFI->CreateFixedObject(4, 0, true);
       MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
       SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
-      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
+      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
+                                       MachinePointerInfo(),
                                        false, false, 0));
 
       // Record the frame index of the first variable argument

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=114453&r1=114452&r2=114453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Sep 21 12:50:43 2010
@@ -605,7 +605,8 @@
   // vastart just stores the address of the VarArgsFrameIndex slot into the
   // memory location argument.
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
+  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
+                      MachinePointerInfo(SV),
                       false, false, 0);
 }
 
@@ -865,7 +866,8 @@
 
     // emit ISD::STORE whichs stores the 
     // parameter value to a stack Location
-    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
+    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
+                                       MachinePointerInfo(),
                                        false, false, 0));
   }
 
@@ -1144,7 +1146,8 @@
       int FI = MFI->CreateFixedObject(4, 0, true);
       MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
       SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
-      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
+      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
+                                       MachinePointerInfo(),
                                        false, false, 0));
 
       // Record the frame index of the first variable argument

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114453&r1=114452&r2=114453&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 12:50:43 2010
@@ -1854,8 +1854,7 @@
   if (Flags.isByVal()) {
     return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
   }
-  return DAG.getStore(Chain, dl, Arg, PtrOff,
-                      PseudoSourceValue::getStack(), LocMemOffset,
+  return DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
                       false, false, 0);
 }
 
@@ -6544,16 +6543,19 @@
     SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
                                      getPointerTy(), StackSlot, WordOff);
     SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
-                                  StackSlot, NULL, 0, false, false, 0);
+                                  StackSlot, MachinePointerInfo(),
+                                  false, false, 0);
     SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
-                                  OffsetSlot, NULL, 0, false, false, 0);
+                                  OffsetSlot, MachinePointerInfo(),
+                                  false, false, 0);
     SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
     return Fild;
   }
 
   assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
   SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
-                                StackSlot, NULL, 0, false, false, 0);
+                                StackSlot, MachinePointerInfo(),
+                               false, false, 0);
   // For i64 source, we need to add the appropriate power of 2 if the input
   // was negative.  This is the same as the optimization in
   // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
@@ -7539,15 +7541,15 @@
   X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
 
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
 
   if (!Subtarget->is64Bit()) {
     // vastart just stores the address of the VarArgsFrameIndex slot into the
     // memory location argument.
     SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
                                    getPointerTy());
-    return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
-                        false, false, 0);
+    return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
+                        MachinePointerInfo(SV), false, false, 0);
   }
 
   // __va_list_tag:
@@ -7558,39 +7560,40 @@
   SmallVector<SDValue, 8> MemOps;
   SDValue FIN = Op.getOperand(1);
   // Store gp_offset
-  SDValue Store = DAG.getStore(Op.getOperand(0), dl,
+  SDValue Store = DAG.getStore(Op.getOperand(0), DL,
                                DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
                                                MVT::i32),
-                               FIN, SV, 0, false, false, 0);
+                               FIN, MachinePointerInfo(SV), false, false, 0);
   MemOps.push_back(Store);
 
   // Store fp_offset
-  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
                     FIN, DAG.getIntPtrConstant(4));
-  Store = DAG.getStore(Op.getOperand(0), dl,
+  Store = DAG.getStore(Op.getOperand(0), DL,
                        DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
                                        MVT::i32),
-                       FIN, SV, 4, false, false, 0);
+                       FIN, MachinePointerInfo(SV, 4), false, false, 0);
   MemOps.push_back(Store);
 
   // Store ptr to overflow_arg_area
-  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
                     FIN, DAG.getIntPtrConstant(4));
   SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
                                     getPointerTy());
-  Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
+  Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
+                       MachinePointerInfo(SV, 8),
                        false, false, 0);
   MemOps.push_back(Store);
 
   // Store ptr to reg_save_area.
-  FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
                     FIN, DAG.getIntPtrConstant(8));
   SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
                                     getPointerTy());
-  Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
-                       false, false, 0);
+  Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
+                       MachinePointerInfo(SV, 16), false, false, 0);
   MemOps.push_back(Store);
-  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                      &MemOps[0], MemOps.size());
 }
 
@@ -7956,7 +7959,8 @@
   SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
                                   DAG.getIntPtrConstant(TD->getPointerSize()));
   StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
-  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
+  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
+                       false, false, 0);
   Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
   MF.getRegInfo().addLiveOut(StoreAddrReg);
 
@@ -7991,11 +7995,13 @@
     unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
     SDValue Addr = Trmp;
     OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
-                                Addr, TrmpAddr, 0, false, false, 0);
+                                Addr, MachinePointerInfo(TrmpAddr),
+                                false, false, 0);
 
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
                        DAG.getConstant(2, MVT::i64));
-    OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
+    OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
+                                MachinePointerInfo(TrmpAddr, 2),
                                 false, false, 2);
 
     // Load the 'nest' parameter value into R10.
@@ -8004,11 +8010,13 @@
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
                        DAG.getConstant(10, MVT::i64));
     OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
-                                Addr, TrmpAddr, 10, false, false, 0);
+                                Addr, MachinePointerInfo(TrmpAddr, 10),
+                                false, false, 0);
 
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
                        DAG.getConstant(12, MVT::i64));
-    OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
+    OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
+                                MachinePointerInfo(TrmpAddr, 12),
                                 false, false, 2);
 
     // Jump to the nested function.
@@ -8016,13 +8024,15 @@
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
                        DAG.getConstant(20, MVT::i64));
     OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
-                                Addr, TrmpAddr, 20, false, false, 0);
+                                Addr, MachinePointerInfo(TrmpAddr, 20),
+                                false, false, 0);
 
     unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
                        DAG.getConstant(22, MVT::i64));
     OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
-                                TrmpAddr, 22, false, false, 0);
+                                MachinePointerInfo(TrmpAddr, 22),
+                                false, false, 0);
 
     SDValue Ops[] =
       { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
@@ -8084,22 +8094,26 @@
     const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
     OutChains[0] = DAG.getStore(Root, dl,
                                 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
-                                Trmp, TrmpAddr, 0, false, false, 0);
+                                Trmp, MachinePointerInfo(TrmpAddr),
+                                false, false, 0);
 
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
                        DAG.getConstant(1, MVT::i32));
-    OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
+    OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
+                                MachinePointerInfo(TrmpAddr, 1),
                                 false, false, 1);
 
     const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
                        DAG.getConstant(5, MVT::i32));
     OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
-                                TrmpAddr, 5, false, false, 1);
+                                MachinePointerInfo(TrmpAddr, 5),
+                                false, false, 1);
 
     Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
                        DAG.getConstant(6, MVT::i32));
-    OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
+    OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
+                                MachinePointerInfo(TrmpAddr, 6),
                                 false, false, 1);
 
     SDValue Ops[] =
@@ -10050,8 +10064,8 @@
 
   // Store the value to a temporary stack slot.
   SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
-  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
-                            0, false, false, 0);
+  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
+                            MachinePointerInfo(), false, false, 0);
 
   // Replace each use (extract) with a load of the appropriate element.
   for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
@@ -10816,12 +10830,11 @@
                          DAG.getConstant(4, MVT::i32));
 
     SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
-                                St->getSrcValue(), St->getSrcValueOffset(),
+                                St->getPointerInfo(),
                                 St->isVolatile(), St->isNonTemporal(),
                                 St->getAlignment());
     SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
-                                St->getSrcValue(),
-                                St->getSrcValueOffset() + 4,
+                                St->getPointerInfo().getWithOffset(4),
                                 St->isVolatile(),
                                 St->isNonTemporal(),
                                 MinAlign(St->getAlignment(), 4));



From bob.wilson at apple.com  Tue Sep 21 12:56:22 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 21 Sep 2010 17:56:22 -0000
Subject: [llvm-commits] [llvm] r114454 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Target/ARM/ARMISelLowering.cpp
 Target/ARM/ARMISelLowering.h
Message-ID: <20100921175622.40B082A6C12C@llvm.org>

Author: bwilson
Date: Tue Sep 21 12:56:22 2010
New Revision: 114454

URL: http://llvm.org/viewvc/llvm-project?rev=114454&view=rev
Log:
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
and store intrinsics are represented with MemIntrinsicSDNodes.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114454&r1=114453&r2=114454&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep 21 12:56:22 2010
@@ -3031,7 +3031,8 @@
   bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
 
   // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
-  if (!IsTgtIntrinsic)
+  if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
+      Info.opc == ISD::INTRINSIC_W_CHAIN)
     Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
 
   // Add all operands of the call to the operand list.

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114454&r1=114453&r2=114454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep 21 12:56:22 2010
@@ -29,6 +29,7 @@
 #include "llvm/Function.h"
 #include "llvm/GlobalValue.h"
 #include "llvm/Instruction.h"
+#include "llvm/Instructions.h"
 #include "llvm/Intrinsics.h"
 #include "llvm/Type.h"
 #include "llvm/CodeGen/CallingConvLower.h"
@@ -5542,3 +5543,63 @@
     return ARM::getVFPf64Imm(Imm) != -1;
   return false;
 }
+
+/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 
+/// MemIntrinsicNodes.  The associated MachineMemOperands record the alignment
+/// specified in the intrinsic calls.
+bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
+                                           const CallInst &I,
+                                           unsigned Intrinsic) const {
+  switch (Intrinsic) {
+  case Intrinsic::arm_neon_vld1:
+  case Intrinsic::arm_neon_vld2:
+  case Intrinsic::arm_neon_vld3:
+  case Intrinsic::arm_neon_vld4:
+  case Intrinsic::arm_neon_vld2lane:
+  case Intrinsic::arm_neon_vld3lane:
+  case Intrinsic::arm_neon_vld4lane: {
+    Info.opc = ISD::INTRINSIC_W_CHAIN;
+    // Conservatively set memVT to the entire set of vectors loaded.
+    uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
+    Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
+    Info.ptrVal = I.getArgOperand(0);
+    Info.offset = 0;
+    Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
+    Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
+    Info.vol = false; // volatile loads with NEON intrinsics not supported
+    Info.readMem = true;
+    Info.writeMem = false;
+    return true;
+  }
+  case Intrinsic::arm_neon_vst1:
+  case Intrinsic::arm_neon_vst2:
+  case Intrinsic::arm_neon_vst3:
+  case Intrinsic::arm_neon_vst4:
+  case Intrinsic::arm_neon_vst2lane:
+  case Intrinsic::arm_neon_vst3lane:
+  case Intrinsic::arm_neon_vst4lane: {
+    Info.opc = ISD::INTRINSIC_VOID;
+    // Conservatively set memVT to the entire set of vectors stored.
+    unsigned NumElts = 0;
+    for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
+      const Type *ArgTy = I.getArgOperand(ArgI)->getType();
+      if (!ArgTy->isVectorTy())
+        break;
+      NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
+    }
+    Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
+    Info.ptrVal = I.getArgOperand(0);
+    Info.offset = 0;
+    Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
+    Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
+    Info.vol = false; // volatile stores with NEON intrinsics not supported
+    Info.readMem = false;
+    Info.writeMem = true;
+    return true;
+  }
+  default:
+    break;
+  }
+
+  return false;
+}

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=114454&r1=114453&r2=114454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Sep 21 12:56:22 2010
@@ -290,6 +290,9 @@
     /// materialize the FP immediate as a load from a constant pool.
     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 
+    virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
+                                    const CallInst &I,
+                                    unsigned Intrinsic) const;
   protected:
     std::pair<const TargetRegisterClass*, uint8_t>
     findRepresentativeClass(EVT VT) const;



From stoklund at 2pi.dk  Tue Sep 21 13:24:31 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 18:24:31 -0000
Subject: [llvm-commits] [llvm] r114455 -
	/llvm/trunk/lib/CodeGen/LiveInterval.cpp
Message-ID: <20100921182431.0FD662A6C12C@llvm.org>

Author: stoklund
Date: Tue Sep 21 13:24:30 2010
New Revision: 114455

URL: http://llvm.org/viewvc/llvm-project?rev=114455&view=rev
Log:
MSVC9 does not support upper_bound with an asymmetric comparator.

Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=114455&r1=114454&r2=114455&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Sep 21 13:24:30 2010
@@ -30,14 +30,18 @@
 #include <algorithm>
 using namespace llvm;
 
-// compEnd - Compare LiveRange end to Pos.
-// This argument ordering works for upper_bound.
-static inline bool compEnd(SlotIndex Pos, const LiveRange &LR) {
-  return Pos < LR.end;
-}
+// CompEnd - Compare LiveRange end to Pos.
+struct CompEnd {
+  bool operator()(SlotIndex Pos, const LiveRange &LR) const {
+    return Pos < LR.end;
+  }
+  bool operator()(const LiveRange &LR, SlotIndex Pos) const {
+    return LR.end < Pos;
+  }
+};
 
 LiveInterval::iterator LiveInterval::find(SlotIndex Pos) {
-  return std::upper_bound(begin(), end(), Pos, compEnd);
+  return std::upper_bound(begin(), end(), Pos, CompEnd());
 }
 
 /// killedInRange - Return true if the interval has kills in [Start,End).



From bigcheesegs at gmail.com  Tue Sep 21 13:30:52 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Tue, 21 Sep 2010 14:30:52 -0400
Subject: [llvm-commits] [PATCH] Program to aid in automated testing on
	windows.
Message-ID: <AANLkTimei_VrL7ouyvTpcxEtVZqmzhwFPoJ7HW0YuUT3@mail.gmail.com>

While porting test-suite over to lit so I could run it on Windows I
ran into severe issues due to Dr. Watson and the C runtime.

Windows uses Structured Exception Handling (SEH) to notify
applications about program faults such as read/write access errors
(segfaults), unaligned access, divide by 0, etc... Each application
has a SEH filter chain similar to catch blocks on the stack in C++.
When an exception occurs, Windows walks the filter chain calling the
filters until one handles it. By default the top level filter calls
Dr. Watson, which then searches the internet and pops up a dialog box
informing the user that something exploded. This makes it very
difficult to to automated testing.

The other automation blocker is the way the Microsoft C runtime
handles asserts. By default, when an assert is fired, the C Runtime
writes the message out to stderr, and then loads user32.dll and
presents a message box to the user.

This program provides an extremely hacky way to stop Dr. Watson from
starting due to unhandled exceptions in child processes.

This simply starts the process arg[1] with the arguments in arg[2:]
under a debugger. All this debugger does is catch any unhandled
exceptions thrown in the child process and close the program (and
hopefully tells someone about it).

This also provides another really hacky method to prevent assert
dialog boxes from popping up. When --no-user32 is passed, if any
process loads user32.dll, we assume it is trying to call MessageBoxEx
and so we terminate it. The proper way to do this would be to actually
set a break point, but there's quite a bit of code involved to get the
address of MessageBoxEx in the remote process's address space. This
can be added if it's ever actually needed.

OVERVIEW: Dr. Watson Assassin.

USAGE: KillTheDoctor [options] <program to run> <program arguments>...

OPTIONS:
  -help      - Display available options (-help-hidden for more)
  -no-user32 - Terminate process if it loads user32.dll.
  -t=<uint>  - Set maximum runtime in seconds. Defaults to infinite.
  -version   - Display the version of this program
  -x         - Print detailed output about what is being run to stderr.

Oh, and:

********************
Testing Time: 296.32s
********************
Failing Tests (144):
    llvm-test-suite :: SingleSource/Benchmarks/BenchmarkGame/Large/fasta.c
    llvm-test-suite :: SingleSource/Benchmarks/BenchmarkGame/partialsums.c
    llvm-test-suite :: SingleSource/Benchmarks/BenchmarkGame/puzzle.c
    llvm-test-suite :: SingleSource/Benchmarks/BenchmarkGame/spectral-norm.c
    llvm-test-suite :: SingleSource/Benchmarks/CoyoteBench/almabench.c
    llvm-test-suite :: SingleSource/Benchmarks/CoyoteBench/huffbench.c
    llvm-test-suite :: SingleSource/Benchmarks/CoyoteBench/lpbench.c
    llvm-test-suite :: SingleSource/Benchmarks/Dhrystone/dry.c
    llvm-test-suite :: SingleSource/Benchmarks/Dhrystone/fldry.c
    llvm-test-suite :: SingleSource/Benchmarks/McGill/chomp.c
    llvm-test-suite :: SingleSource/Benchmarks/McGill/exptree.c
    llvm-test-suite :: SingleSource/Benchmarks/McGill/misr.c
    llvm-test-suite :: SingleSource/Benchmarks/McGill/queens.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/ReedSolomon.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/dt.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/fbench.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/ffbench.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/flops-1.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/flops-2.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/flops-5.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/flops-7.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/flops-8.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/flops.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/fp-convert.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/himenobmtxpa.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/lowercase.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/mandel-2.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/mandel.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/oourafft.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/perlin.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/pi.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/richards_benchmark.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/salsa20.c
    llvm-test-suite :: SingleSource/Benchmarks/Misc/whetstone.c
    llvm-test-suite :: SingleSource/Benchmarks/Shootout/hash.c
    llvm-test-suite :: SingleSource/Benchmarks/Shootout/objinst.c
    llvm-test-suite :: SingleSource/Benchmarks/Shootout/sieve.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/Bubblesort.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/IntMM.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/Oscar.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/Puzzle.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/Quicksort.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/RealMM.c
    llvm-test-suite :: SingleSource/Benchmarks/Stanford/Treesort.c
    llvm-test-suite :: SingleSource/Regression/C/2003-05-21-BitfieldHandling.c
    llvm-test-suite :: SingleSource/Regression/C/2003-05-21-UnionTest.c
    llvm-test-suite :: SingleSource/Regression/C/2003-05-22-VarSizeArray.c
    llvm-test-suite :: SingleSource/Regression/C/2003-05-23-TransparentUnion.c
    llvm-test-suite ::
SingleSource/Regression/C/2003-10-12-GlobalVarInitializers.c
    llvm-test-suite :: SingleSource/Regression/C/2004-02-03-AggregateCopy.c
    llvm-test-suite :: SingleSource/Regression/C/2004-03-15-IndirectGoto.c
    llvm-test-suite :: SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c
    llvm-test-suite :: SingleSource/Regression/C/2008-01-07-LongDouble.c
    llvm-test-suite ::
SingleSource/Regression/C/ConstructorDestructorAttributes.c
    llvm-test-suite :: SingleSource/Regression/C/PR1386.c
    llvm-test-suite :: SingleSource/Regression/C/PR491.c
    llvm-test-suite :: SingleSource/Regression/C/casts.c
    llvm-test-suite :: SingleSource/Regression/C/globalrefs.c
    llvm-test-suite :: SingleSource/Regression/C/matrixTranspose.c
    llvm-test-suite :: SingleSource/UnitTests/2002-05-19-DivTest.c
    llvm-test-suite :: SingleSource/UnitTests/2002-10-09-ArrayResolution.c
    llvm-test-suite :: SingleSource/UnitTests/2003-05-07-VarArgs.c
    llvm-test-suite :: SingleSource/UnitTests/2003-05-26-Shorts.c
    llvm-test-suite :: SingleSource/UnitTests/2003-05-31-CastToBool.c
    llvm-test-suite :: SingleSource/UnitTests/2003-07-09-LoadShorts.c
    llvm-test-suite :: SingleSource/UnitTests/2003-07-09-SignedArgs.c
    llvm-test-suite :: SingleSource/UnitTests/2003-07-10-SignConversions.c
    llvm-test-suite :: SingleSource/UnitTests/2003-08-11-VaListArg.c
    llvm-test-suite :: SingleSource/UnitTests/2004-11-28-GlobalBoolLayout.c
    llvm-test-suite :: SingleSource/UnitTests/2005-05-11-Popcount-ffs-fls.c
    llvm-test-suite :: SingleSource/UnitTests/2005-05-12-Int64ToFP.c
    llvm-test-suite :: SingleSource/UnitTests/2005-07-17-INT-To-FP.c
    llvm-test-suite :: SingleSource/UnitTests/2006-01-23-UnionInit.c
    llvm-test-suite :: SingleSource/UnitTests/2007-03-02-VaCopy.c
    llvm-test-suite :: SingleSource/UnitTests/2007-04-25-weak.c
    llvm-test-suite :: SingleSource/UnitTests/2008-04-18-LoopBug.c
    llvm-test-suite :: SingleSource/UnitTests/2008-04-20-LoopBug2.c
    llvm-test-suite ::
SingleSource/UnitTests/2009-04-16-BitfieldInitialization.c
    llvm-test-suite :: SingleSource/UnitTests/2009-12-07-StructReturn.c
    llvm-test-suite :: SingleSource/UnitTests/AtomicOps.c
    llvm-test-suite :: SingleSource/UnitTests/FloatPrecision.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/SSAtest.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/arith.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/array.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/big_bit_concat.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/big_part_set.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/bigint.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/bit_concat.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/bit_select.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/bit_set.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/bitbit.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/bitlogic.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/convert.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/extern-inline-redef.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/field.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/folding.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/general-test.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/global.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/integer_all_onesp.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/large-array.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/list.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/local-array.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/local-union.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/matrix.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/memory.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/multiple_assign.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/negConst.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/offset.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/part_select.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/part_select2.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/part_set.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/pointer.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/reduce_xor.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/reductions.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/sign.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/sign2.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/static.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/struct1.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/struct2.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/structInit.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/switch.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/test4.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/test_part_set.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/trunc.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/union-init.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/union-struct.c
    llvm-test-suite :: SingleSource/UnitTests/Integer/union2.c
    llvm-test-suite :: SingleSource/UnitTests/SignlessTypes/cast-bug.c
    llvm-test-suite :: SingleSource/UnitTests/SignlessTypes/ccc.c
    llvm-test-suite :: SingleSource/UnitTests/SignlessTypes/rem.c
    llvm-test-suite :: SingleSource/UnitTests/Threads/tls.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/SSE/sse.expandfft.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/SSE/sse.isamax.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/SSE/sse.shift.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/SSE/sse.stepfft.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/build.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/build2.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/divides.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/multiplies.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/simple.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/sumarray-dbl.c
    llvm-test-suite :: SingleSource/UnitTests/Vector/sumarray.c
    llvm-test-suite :: SingleSource/UnitTests/byval-alignment.c
    llvm-test-suite :: SingleSource/UnitTests/conditional-gnu-ext.c

  Expected Passes    : 86
  Unsupported Tests  : 14
  Unexpected Failures: 144


- Michael Spencer
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From fjahanian at apple.com  Tue Sep 21 13:33:39 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Tue, 21 Sep 2010 18:33:39 -0000
Subject: [llvm-commits] [test-suite] r114458 -
 /test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp
Message-ID: <20100921183339.A89D52A6C12C@llvm.org>

Author: fjahanian
Date: Tue Sep 21 13:33:39 2010
New Revision: 114458

URL: http://llvm.org/viewvc/llvm-project?rev=114458&view=rev
Log:
Test updated for clang's implmentation of
gnu extension's missing LHS (when it was
meant to be an lvalue).

Modified:
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp

Modified: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp?rev=114458&r1=114457&r2=114458&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp (original)
+++ test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp Tue Sep 21 13:33:39 2010
@@ -8,15 +8,29 @@
   return val;
 }
 
-_Complex int doo() {
+_Complex int cmplx_test() {
     _Complex int cond;
     _Complex int rhs;
 
     return getComplex(1+2i) ? : rhs;
 }
 
-int main() {
-  doo();
-  return 0;
+// lvalue test
+int global = 1;
+void foo (int& lv) {
+  ++lv;
 }
 
+int &cond() {
+  static int count;
+  if (count++)
+    abort();
+  return global;
+}
+
+int  main() {
+    cmplx_test();
+    int rhs = 10;
+    foo (cond()? : rhs);
+    return  global-2;
+}



From stoklund at 2pi.dk  Tue Sep 21 13:34:18 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 18:34:18 -0000
Subject: [llvm-commits] [llvm] r114459 -
	/llvm/trunk/lib/CodeGen/LiveInterval.cpp
Message-ID: <20100921183418.1FC882A6C12C@llvm.org>

Author: stoklund
Date: Tue Sep 21 13:34:17 2010
New Revision: 114459

URL: http://llvm.org/viewvc/llvm-project?rev=114459&view=rev
Log:
Don't pollute the global namespace.

Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=114459&r1=114458&r2=114459&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Sep 21 13:34:17 2010
@@ -31,6 +31,7 @@
 using namespace llvm;
 
 // CompEnd - Compare LiveRange end to Pos.
+namespace {
 struct CompEnd {
   bool operator()(SlotIndex Pos, const LiveRange &LR) const {
     return Pos < LR.end;
@@ -39,6 +40,7 @@
     return LR.end < Pos;
   }
 };
+}
 
 LiveInterval::iterator LiveInterval::find(SlotIndex Pos) {
   return std::upper_bound(begin(), end(), Pos, CompEnd());



From resistor at mac.com  Tue Sep 21 13:41:19 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 21 Sep 2010 18:41:19 -0000
Subject: [llvm-commits] [llvm] r114460 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/add-of-carry.ll
Message-ID: <20100921184119.A98652A6C12C@llvm.org>

Author: resistor
Date: Tue Sep 21 13:41:19 2010
New Revision: 114460

URL: http://llvm.org/viewvc/llvm-project?rev=114460&view=rev
Log:
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

Added:
    llvm/trunk/test/CodeGen/X86/add-of-carry.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114460&r1=114459&r2=114460&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 13:41:19 2010
@@ -1021,6 +1021,7 @@
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::STORE);
   setTargetDAGCombine(ISD::ZERO_EXTEND);
+  setTargetDAGCombine(ISD::ADD);
   if (Subtarget->is64Bit())
     setTargetDAGCombine(ISD::MUL);
 
@@ -10452,6 +10453,27 @@
   return SDValue();
 }
 
+/// PerformAddCombine - Optimize ADD when combined with X86 opcodes.
+static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
+                                 TargetLowering::DAGCombinerInfo &DCI) {
+  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
+    return SDValue();
+  
+  EVT VT = N->getValueType(0);
+  SDValue Op1 = N->getOperand(1);
+  if (Op1->getOpcode() == ISD::AND) {
+    SDValue AndOp0 = Op1->getOperand(0);
+    ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(Op1->getOperand(1)); 
+    // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
+    if (AndOp0->getOpcode() == X86ISD::SETCC_CARRY &&
+        AndOp1 && AndOp1->getZExtValue() == 1) {
+      DebugLoc DL = N->getDebugLoc();
+      return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
+    }
+  }
+  
+  return SDValue();
+}
 
 /// PerformMulCombine - Optimize a single multiply with constant into two
 /// in order to implement it with two cheaper instructions, e.g.
@@ -10938,6 +10960,7 @@
                         return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
   case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
   case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
+  case ISD::ADD:            return PerformAddCombine(N, DAG, DCI);
   case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
   case ISD::SHL:
   case ISD::SRA:

Added: llvm/trunk/test/CodeGen/X86/add-of-carry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-of-carry.ll?rev=114460&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/add-of-carry.ll (added)
+++ llvm/trunk/test/CodeGen/X86/add-of-carry.ll Tue Sep 21 13:41:19 2010
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+; <rdar://problem/8449754>
+
+define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp {
+entry:
+; CHECK:	sbbl	%ecx, %ecx
+; CHECK-NOT: addl
+; CHECK: subl	%ecx, %eax
+  %add4 = add i32 %x, %sum
+  %cmp = icmp ult i32 %add4, %x
+  %inc = zext i1 %cmp to i32
+  %z.0 = add i32 %add4, %inc
+  ret i32 %z.0
+}



From sabre at nondot.org  Tue Sep 21 13:41:36 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 18:41:36 -0000
Subject: [llvm-commits] [llvm] r114461 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/ Target/Alpha/ Target/Blackfin/ Target/CellSPU/
 Target/MSP430/ Target/PIC16/ Target/PowerPC/ Target/Sparc/ Target/SystemZ/
 Target/XCore/
Message-ID: <20100921184136.A8EE52A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 13:41:36 2010
New Revision: 114461

URL: http://llvm.org/viewvc/llvm-project?rev=114461&view=rev
Log:
update a bunch of code to use the MachinePointerInfo version of getStore.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 13:41:36 2010
@@ -5741,7 +5741,7 @@
   
   ++OpsNarrowed;
   return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 
-                      St->getSrcValue(), St->getSrcValueOffset()+StOffset,
+                      St->getPointerInfo().getWithOffset(StOffset),
                       false, false, NewAlign).getNode();
 }
 
@@ -5887,8 +5887,7 @@
         ((!LegalOperations && !ST->isVolatile()) ||
          TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
       return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
-                          Ptr, ST->getSrcValue(),
-                          ST->getSrcValueOffset(), ST->isVolatile(),
+                          Ptr, ST->getPointerInfo(), ST->isVolatile(),
                           ST->isNonTemporal(), OrigAlign);
   }
 
@@ -5912,8 +5911,7 @@
           Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
                               bitcastToAPInt().getZExtValue(), MVT::i32);
           return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
-                              Ptr, ST->getSrcValue(),
-                              ST->getSrcValueOffset(), ST->isVolatile(),
+                              Ptr, ST->getPointerInfo(), ST->isVolatile(),
                               ST->isNonTemporal(), ST->getAlignment());
         }
         break;
@@ -5924,8 +5922,7 @@
           Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
                                 getZExtValue(), MVT::i64);
           return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
-                              Ptr, ST->getSrcValue(),
-                              ST->getSrcValueOffset(), ST->isVolatile(),
+                              Ptr, ST->getPointerInfo(), ST->isVolatile(),
                               ST->isNonTemporal(), ST->getAlignment());
         } else if (!ST->isVolatile() &&
                    TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
@@ -5937,23 +5934,20 @@
           SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
           if (TLI.isBigEndian()) std::swap(Lo, Hi);
 
-          int SVOffset = ST->getSrcValueOffset();
           unsigned Alignment = ST->getAlignment();
           bool isVolatile = ST->isVolatile();
           bool isNonTemporal = ST->isNonTemporal();
 
           SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
-                                     Ptr, ST->getSrcValue(),
-                                     ST->getSrcValueOffset(),
+                                     Ptr, ST->getPointerInfo(),
                                      isVolatile, isNonTemporal,
                                      ST->getAlignment());
           Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
                             DAG.getConstant(4, Ptr.getValueType()));
-          SVOffset += 4;
           Alignment = MinAlign(Alignment, 4U);
           SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
-                                     Ptr, ST->getSrcValue(),
-                                     SVOffset, isVolatile, isNonTemporal,
+                                     Ptr, ST->getPointerInfo().getWithOffset(4),
+                                     isVolatile, isNonTemporal,
                                      Alignment);
           return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
                              St0, St1);
@@ -5990,7 +5984,7 @@
                                       ST->isNonTemporal(), ST->getAlignment());
       } else {
         ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
-                                 ST->getSrcValue(), ST->getSrcValueOffset(),
+                                 ST->getPointerInfo(),
                                  ST->isVolatile(), ST->isNonTemporal(),
                                  ST->getAlignment());
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 21 13:41:36 2010
@@ -547,7 +547,7 @@
                                  MinAlign(LD->getAlignment(), Offset));
       // Follow the load with a store to the stack slot.  Remember the store.
       Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
-                                    NULL, 0, false, false, 0));
+                                    MachinePointerInfo(), false, false, 0));
       // Increment the pointers.
       Offset += RegBytes;
       Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
@@ -1541,8 +1541,8 @@
   DebugLoc dl = Op.getDebugLoc();
   // Store the value to a temporary stack slot, then LOAD the returned part.
   SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
-  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
-                            false, false, 0);
+  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
+                            MachinePointerInfo(), false, false, 0);
 
   // Add the offset to the index.
   unsigned EltSize =
@@ -1636,7 +1636,7 @@
     SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
     // Then store the float to it.
     SDValue Ch =
-      DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0,
+      DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
                    false, false, 0);
     if (TLI.isBigEndian()) {
       assert(FloatVT.isByteSized() && "Unsupported floating point type!");
@@ -2066,13 +2066,14 @@
     }
     // store the lo of the constructed double - based on integer input
     SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
-                                  Op0Mapped, Lo, NULL, 0,
+                                  Op0Mapped, Lo, MachinePointerInfo(),
                                   false, false, 0);
     // initial hi portion of constructed double
     SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
     // store the hi of the constructed double - biased exponent
-    SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
-                                false, false, 0);
+    SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
+                                  MachinePointerInfo(),
+                                  false, false, 0);
     // load the constructed double
     SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
                                MachinePointerInfo(), false, false, 0);
@@ -2686,8 +2687,8 @@
                           getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
                                        TLI.getPointerTy()));
     // Store the incremented VAList to the legalized pointer
-    Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0,
-                        false, false, 0);
+    Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
+                        MachinePointerInfo(V), false, false, 0);
     // Load the actual argument out of the pointer VAList
     Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
                                   false, false, 0));

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Tue Sep 21 13:41:36 2010
@@ -779,7 +779,7 @@
     Val = GetSoftenedFloat(Val);
 
   return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(),
-                      ST->getSrcValue(), ST->getSrcValueOffset(),
+                      ST->getPointerInfo(),
                       ST->isVolatile(), ST->isNonTemporal(),
                       ST->getAlignment());
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Sep 21 13:41:36 2010
@@ -390,7 +390,6 @@
                                      St->getValue().getValueType());
   SDValue Chain = St->getChain();
   SDValue Ptr = St->getBasePtr();
-  int SVOffset = St->getSrcValueOffset();
   unsigned Alignment = St->getAlignment();
   bool isVolatile = St->isVolatile();
   bool isNonTemporal = St->isNonTemporal();
@@ -404,14 +403,14 @@
   if (TLI.isBigEndian())
     std::swap(Lo, Hi);
 
-  Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getSrcValue(), SVOffset,
+  Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getPointerInfo(),
                     isVolatile, isNonTemporal, Alignment);
 
   Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                     DAG.getIntPtrConstant(IncrementSize));
   assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
-  Hi = DAG.getStore(Chain, dl, Hi, Ptr, St->getSrcValue(),
-                    SVOffset + IncrementSize,
+  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
+                    St->getPointerInfo().getWithOffset(IncrementSize),
                     isVolatile, isNonTemporal,
                     MinAlign(Alignment, IncrementSize));
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Sep 21 13:41:36 2010
@@ -1097,16 +1097,13 @@
   EVT EltVT = VecVT.getVectorElementType();
   DebugLoc dl = N->getDebugLoc();
   SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
-  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
-  const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
-  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0,
-                               false, false, 0);
+  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
+                               MachinePointerInfo(), false, false, 0);
 
   // Load back the required element.
   StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
   return DAG.getExtLoad(ISD::EXTLOAD, N->getValueType(0), dl, Store, StackPtr,
-                        MachinePointerInfo::getFixedStack(SPFI),
-                        EltVT, false, false, 0);
+                        MachinePointerInfo(), EltVT, false, false, 0);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -284,8 +284,7 @@
                                    DAG.getIntPtrConstant(VA.getLocMemOffset()));
 
       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
-                                         PseudoSourceValue::getStack(), 0,
-                                         false, false, 0));
+                                         MachinePointerInfo(),false, false, 0));
     }
   }
 
@@ -448,7 +447,7 @@
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true);
       if (i == 0) FuncInfo->setVarArgsBase(FI);
       SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
+      LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, MachinePointerInfo(),
                                 false, false, 0));
 
       if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
@@ -456,7 +455,7 @@
       argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true);
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
+      LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, MachinePointerInfo(),
                                 false, false, 0));
     }
 
@@ -727,7 +726,8 @@
     SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP,
                               MachinePointerInfo(SrcS),
                               false, false, 0);
-    SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0,
+    SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, 
+                                  MachinePointerInfo(DestS),
                                   false, false, 0);
     SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
                                DAG.getConstant(8, MVT::i64));
@@ -749,8 +749,8 @@
 
     // vastart stores the address of the VarArgsBase and VarArgsOffset
     SDValue FR  = DAG.getFrameIndex(FuncInfo->getVarArgsBase(), MVT::i64);
-    SDValue S1  = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0,
-                               false, false, 0);
+    SDValue S1  = DAG.getStore(Chain, dl, FR, VAListP,
+                               MachinePointerInfo(VAListS), false, false, 0);
     SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
                                 DAG.getConstant(8, MVT::i64));
     return DAG.getTruncStore(S1, dl,

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -333,8 +333,7 @@
       SDValue OffsetN = DAG.getIntPtrConstant(Offset);
       OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
-                                         PseudoSourceValue::getStack(),
-                                         Offset, false, false, 0));
+                                         MachinePointerInfo(),false, false, 0));
     }
   }
 

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -853,7 +853,7 @@
                                      MVT::v4i32, insertEltOp));
 
     result = DAG.getStore(the_chain, dl, result, basePtr,
-                          LN->getSrcValue(), LN->getSrcValueOffset(),
+                          LN->getPointerInfo(),
                           LN->isVolatile(), LN->isNonTemporal(),
                           LN->getAlignment());
 
@@ -1120,7 +1120,7 @@
       SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
       unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
       SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
-      SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0,
+      SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, MachinePointerInfo(),
                                    false, false, 0);
       Chain = Store.getOperand(0);
       MemOps.push_back(Store);
@@ -1220,7 +1220,8 @@
       if (ArgRegIdx != NumArgRegs) {
         RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
       } else {
-        MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
+        MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
+                                           MachinePointerInfo(),
                                            false, false, 0));
         ArgOffset += StackSlotSize;
       }

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -507,8 +507,7 @@
 
 
       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
-                                         PseudoSourceValue::getStack(),
-                                         VA.getLocMemOffset(), false, false, 0));
+                                         MachinePointerInfo(),false, false, 0));
     }
   }
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -644,13 +644,13 @@
       ChainLo = Chain.getOperand(0);
       ChainHi = Chain.getOperand(1);
     }
-    SDValue Store1 = DAG.getStore(ChainLo, dl, SrcLo, Ptr, NULL,
-                                  0 + StoreOffset, false, false, 0);
+    SDValue Store1 = DAG.getStore(ChainLo, dl, SrcLo, Ptr, MachinePointerInfo(),
+                                  false, false, 0);
 
     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
                       DAG.getConstant(4, Ptr.getValueType()));
-    SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL,
-                                  1 + StoreOffset, false, false, 0);
+    SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, MachinePointerInfo(),
+                                  false, false, 0);
 
     return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1,
                        Store2);

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -1353,7 +1353,8 @@
     EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
     SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
     const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-    return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
+    return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
+                        MachinePointerInfo(SV),
                         false, false, 0);
   }
 
@@ -1423,13 +1424,15 @@
 
   // Store second word : arguments given on stack
   SDValue thirdStore =
-    DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset,
+    DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
+                 MachinePointerInfo(SV, nextOffset),
                  false, false, 0);
   nextOffset += FrameOffset;
   nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
 
   // Store third word : arguments given in registers
-  return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset,
+  return DAG.getStore(thirdStore, dl, FR, nextPtr,
+                      MachinePointerInfo(SV, nextOffset),
                       false, false, 0);
 
 }
@@ -1713,7 +1716,7 @@
     unsigned GPRIndex = 0;
     for (; GPRIndex != FuncInfo->getVarArgsNumGPR(); ++GPRIndex) {
       SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
-      SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0,
+      SDValue Store = DAG.getStore(Chain, dl, Val, FIN, MachinePointerInfo(),
                                    false, false, 0);
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
@@ -1728,8 +1731,8 @@
       unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
 
       SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
-      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
-                                   false, false, 0);
+      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
+                                   MachinePointerInfo(), false, false, 0);
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
       SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
@@ -1744,7 +1747,7 @@
     unsigned FPRIndex = 0;
     for (FPRIndex = 0; FPRIndex != FuncInfo->getVarArgsNumFPR(); ++FPRIndex) {
       SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
-      SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0,
+      SDValue Store = DAG.getStore(Chain, dl, Val, FIN, MachinePointerInfo(),
                                    false, false, 0);
       MemOps.push_back(Store);
       // Increment the address by eight for the next argument to store
@@ -1757,8 +1760,8 @@
       unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
 
       SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
-      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
-                                   false, false, 0);
+      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
+                                   MachinePointerInfo(), false, false, 0);
       MemOps.push_back(Store);
       // Increment the address by eight for the next argument to store
       SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
@@ -1941,7 +1944,8 @@
           int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
           SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
           SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
-          SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
+          SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
+                                       MachinePointerInfo(),
                                        false, false, 0);
           MemOps.push_back(Store);
           ++GPR_idx;
@@ -2114,8 +2118,8 @@
         VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
 
       SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
-      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
-                                   false, false, 0);
+      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
+                                   MachinePointerInfo(), false, false, 0);
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
       SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
@@ -2411,7 +2415,7 @@
                  SDValue Arg, SDValue PtrOff, int SPDiff,
                  unsigned ArgOffset, bool isPPC64, bool isTailCall,
                  bool isVector, SmallVector<SDValue, 8> &MemOpChains,
-                 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
+                 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
                  DebugLoc dl) {
   EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   if (!isTailCall) {
@@ -2424,8 +2428,8 @@
       PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
                            DAG.getConstant(ArgOffset, PtrVT));
     }
-    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
-                                       false, false, 0));
+    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
+                                       MachinePointerInfo(), false, false, 0));
   // Calculate and remember argument location.
   } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
                                   TailCallArguments);
@@ -2907,7 +2911,7 @@
         PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
 
         MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
-                                           PseudoSourceValue::getStack(), LocMemOffset,
+                                           MachinePointerInfo(),
                                            false, false, 0));
       } else {
         // Calculate and remember argument location.
@@ -3142,8 +3146,8 @@
         RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
 
         if (isVarArg) {
-          SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
-                                       false, false, 0);
+          SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
+                                       MachinePointerInfo(), false, false, 0);
           MemOpChains.push_back(Store);
 
           // Float varargs are always shadowed in available integer registers
@@ -3201,8 +3205,8 @@
         // entirely in R registers.  Maybe later.
         PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
                             DAG.getConstant(ArgOffset, PtrVT));
-        SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
-                                     false, false, 0);
+        SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
+                                     MachinePointerInfo(), false, false, 0);
         MemOpChains.push_back(Store);
         if (VR_idx != NumVRs) {
           SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 
@@ -3283,7 +3287,7 @@
     // TOC save area offset.
     SDValue PtrOff = DAG.getIntPtrConstant(40);
     SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
-    Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0,
+    Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
                          false, false, 0);
   }
 
@@ -3378,7 +3382,7 @@
   Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
 
   // Store the old link SP.
-  return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0,
+  return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
                       false, false, 0);
 }
 
@@ -3554,8 +3558,8 @@
   SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
 
   // Emit a store to the stack slot.
-  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0,
-                               false, false, 0);
+  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
+                               MachinePointerInfo(), false, false, 0);
 
   // Result is a load from the stack slot.  If loading 4 bytes, make sure to
   // add in a bias.
@@ -3654,7 +3658,7 @@
   int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
   SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
   SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
-                               StackSlot, NULL, 0, false, false, 0);
+                               StackSlot, MachinePointerInfo(), false, false,0);
 
   // Load FP Control Word from low 32 bits of stack slot.
   SDValue Four = DAG.getConstant(4, PtrVT);
@@ -4327,7 +4331,7 @@
 
   // Store the input value into Value#0 of the stack slot.
   SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
-                               Op.getOperand(0), FIdx, NULL, 0,
+                               Op.getOperand(0), FIdx, MachinePointerInfo(),
                                false, false, 0);
   // Load it out.
   return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -244,7 +244,8 @@
                                                           true);
       SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 
-      OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0,
+      OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
+                                       MachinePointerInfo(),
                                        false, false, 0));
       ArgOffset += 4;
     }
@@ -350,7 +351,7 @@
     // FIXME: VERIFY THAT 68 IS RIGHT.
     SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
     PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
-    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0,
+    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, MachinePointerInfo(),
                                        false, false, 0));
   }
 
@@ -397,7 +398,7 @@
       // out the parts as integers.  Top part goes in a reg.
       SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
       SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 
-                                   Val, StackPtr, NULL, 0,
+                                   Val, StackPtr, MachinePointerInfo(),
                                    false, false, 0);
       // Sparc is big-endian, so the high part comes first.
       SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
@@ -450,7 +451,7 @@
       SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
       PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
       MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore, 
-                                         PtrOff, NULL, 0,
+                                         PtrOff, MachinePointerInfo(),
                                          false, false, 0));
     }
     ArgOffset += ObjSize;
@@ -892,8 +893,8 @@
                 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
                                 MVT::i32));
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-  return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0,
-                      false, false, 0);
+  return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
+                      MachinePointerInfo(SV), false, false, 0);
 }
 
 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
@@ -911,7 +912,7 @@
                                                   MVT::i32));
   // Store the incremented VAList to the legalized pointer
   InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
-                         VAListPtr, SV, 0, false, false, 0);
+                         VAListPtr, MachinePointerInfo(SV), false, false, 0);
   // Load the actual argument out of the pointer VAList, unless this is an
   // f64 load.
   if (VT != MVT::f64)

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -441,7 +441,7 @@
                                    DAG.getIntPtrConstant(Offset));
 
       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
-                                         PseudoSourceValue::getStack(), Offset,
+                                         MachinePointerInfo(),
                                          false, false, 0));
     }
   }

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=114461&r1=114460&r2=114461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep 21 13:41:36 2010
@@ -760,8 +760,8 @@
                      DAG.getConstant(VT.getSizeInBits(), 
                                      getPointerTy()));
   // Store the incremented VAList to the legalized pointer
-  Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0,
-                      false, false, 0);
+  Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
+                      MachinePointerInfo(V), false, false, 0);
   // Load the actual argument out of the pointer VAList
   return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
                      false, false, 0);
@@ -776,9 +776,8 @@
   MachineFunction &MF = DAG.getMachineFunction();
   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
   SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
-  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-  return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0,
-                      false, false, 0);
+  return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), 
+                      MachinePointerInfo(), false, false, 0);
 }
 
 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
@@ -1110,8 +1109,8 @@
         RegInfo.addLiveIn(ArgRegs[i], VReg);
         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
         // Move argument from virt reg -> stack
-        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
-                                     false, false, 0);
+        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
+                                     MachinePointerInfo(), false, false, 0);
         MemOps.push_back(Store);
       }
       if (!MemOps.empty())



From wdietz2 at illinois.edu  Tue Sep 21 13:49:55 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Tue, 21 Sep 2010 18:49:55 -0000
Subject: [llvm-commits] [poolalloc] r114462 -
	/poolalloc/trunk/lib/DSA/DSTest.cpp
Message-ID: <20100921184955.4F71C2A6C12C@llvm.org>

Author: wdietz2
Date: Tue Sep 21 13:49:55 2010
New Revision: 114462

URL: http://llvm.org/viewvc/llvm-project?rev=114462&view=rev
Log:
DSTest: Add more verbose failure message when verify-flags check fails.

Modified:
    poolalloc/trunk/lib/DSA/DSTest.cpp

Modified: poolalloc/trunk/lib/DSA/DSTest.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=114462&r1=114461&r2=114462&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSTest.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSTest.cpp Tue Sep 21 13:49:55 2010
@@ -511,12 +511,14 @@
         std::string ActualFlags = getFlags(NV.getNode());
         for (std::string::iterator I = FlagsListed.begin(), E = FlagsListed.end();
             I != E; ++I ) {
-          if (shouldHaveFlag)
-            assert((ActualFlags.find(*I) != std::string::npos)
-                && "Node doesn't have flag it should!");
-          else
-            assert((ActualFlags.find(*I) == std::string::npos)
-                && "Node has flag it shouldn't!");
+          if (shouldHaveFlag == (ActualFlags.find(*I) == std::string::npos))
+          {
+              errs() << "ERROR: Verify flags for:     \t" <<
+                NodeFlagOption  << "\n";
+              errs() << "       But found these flags:\t" <<
+                ActualFlags << "\n";
+              assert(0 && "Flag verification failed!");
+          }
         }
 
 



From clattner at apple.com  Tue Sep 21 13:51:38 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 21 Sep 2010 11:51:38 -0700
Subject: [llvm-commits] [llvm] r114460 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/add-of-carry.ll
In-Reply-To: <20100921184119.A98652A6C12C@llvm.org>
References: <20100921184119.A98652A6C12C@llvm.org>
Message-ID: <95ECED63-60E8-43D4-B036-21847DD342B0@apple.com>


On Sep 21, 2010, at 11:41 AM, Owen Anderson wrote:

> Author: resistor
> Date: Tue Sep 21 13:41:19 2010
> New Revision: 114460
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114460&view=rev
> Log:
> When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
> (sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
> the intermediate AND and the ADD into a single SUB.
> 
> This fixes <rdar://problem/8449754>.

Cool, thanks Owen.  Instead of checking for sbbl specifically, can  this just use "is num sign bits == register width"?  That would allow the xform to go into target independent code.

-Chris

> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 13:41:19 2010
> @@ -1021,6 +1021,7 @@
>   setTargetDAGCombine(ISD::OR);
>   setTargetDAGCombine(ISD::STORE);
>   setTargetDAGCombine(ISD::ZERO_EXTEND);
> +  setTargetDAGCombine(ISD::ADD);
>   if (Subtarget->is64Bit())
>     setTargetDAGCombine(ISD::MUL);
> 
> @@ -10452,6 +10453,27 @@
>   return SDValue();
> }
> 
> +/// PerformAddCombine - Optimize ADD when combined with X86 opcodes.
> +static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
> +                                 TargetLowering::DAGCombinerInfo &DCI) {
> +  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
> +    return SDValue();
> +  
> +  EVT VT = N->getValueType(0);
> +  SDValue Op1 = N->getOperand(1);
> +  if (Op1->getOpcode() == ISD::AND) {
> +    SDValue AndOp0 = Op1->getOperand(0);
> +    ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(Op1->getOperand(1)); 
> +    // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
> +    if (AndOp0->getOpcode() == X86ISD::SETCC_CARRY &&
> +        AndOp1 && AndOp1->getZExtValue() == 1) {
> +      DebugLoc DL = N->getDebugLoc();
> +      return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
> +    }
> +  }
> +  
> +  return SDValue();
> +}
> 
> /// PerformMulCombine - Optimize a single multiply with constant into two
> /// in order to implement it with two cheaper instructions, e.g.
> @@ -10938,6 +10960,7 @@
>                         return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
>   case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
>   case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
> +  case ISD::ADD:            return PerformAddCombine(N, DAG, DCI);
>   case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
>   case ISD::SHL:
>   case ISD::SRA:
> 
> Added: llvm/trunk/test/CodeGen/X86/add-of-carry.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/add-of-carry.ll?rev=114460&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/add-of-carry.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/add-of-carry.ll Tue Sep 21 13:41:19 2010
> @@ -0,0 +1,14 @@
> +; RUN: llc < %s -march=x86 | FileCheck %s
> +; <rdar://problem/8449754>
> +
> +define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp {
> +entry:
> +; CHECK:	sbbl	%ecx, %ecx
> +; CHECK-NOT: addl
> +; CHECK: subl	%ecx, %eax
> +  %add4 = add i32 %x, %sum
> +  %cmp = icmp ult i32 %add4, %x
> +  %inc = zext i1 %cmp to i32
> +  %z.0 = add i32 %add4, %inc
> +  ret i32 %z.0
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From sabre at nondot.org  Tue Sep 21 13:51:21 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 18:51:21 -0000
Subject: [llvm-commits] [llvm] r114463 - in /llvm/trunk:
 include/llvm/CodeGen/MachineMemOperand.h lib/CodeGen/MachineInstr.cpp
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100921185122.2DDA82A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 13:51:21 2010
New Revision: 114463

URL: http://llvm.org/viewvc/llvm-project?rev=114463&view=rev
Log:
convert a couple more places to use the new getStore()


Modified:
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=114463&r1=114462&r2=114463&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Tue Sep 21 13:51:21 2010
@@ -64,6 +64,9 @@
   /// getGOT - Return a MachinePointerInfo record that refers to a
   /// GOT entry.
   static MachinePointerInfo getGOT();
+  
+  /// getStack - stack pointer relative access.
+  static MachinePointerInfo getStack(int64_t Offset);
 };
   
   

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=114463&r1=114462&r2=114463&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Sep 21 13:51:21 2010
@@ -362,6 +362,10 @@
   return MachinePointerInfo(PseudoSourceValue::getGOT());
 }
 
+MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
+  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
+}
+
 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
                                      uint64_t s, unsigned int a)
   : PtrInfo(ptrinfo), Size(s),

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114463&r1=114462&r2=114463&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep 21 13:51:21 2010
@@ -942,11 +942,11 @@
   unsigned LocMemOffset = VA.getLocMemOffset();
   SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
   PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
-  if (Flags.isByVal()) {
+  if (Flags.isByVal())
     return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
-  }
+
   return DAG.getStore(Chain, dl, Arg, PtrOff,
-                      PseudoSourceValue::getStack(), LocMemOffset,
+                      MachinePointerInfo::getStack(LocMemOffset),
                       false, false, 0);
 }
 
@@ -1890,8 +1890,8 @@
   EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
-                      false, false, 0);
+  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
+                      MachinePointerInfo(SV), false, false, 0);
 }
 
 SDValue
@@ -2084,8 +2084,8 @@
         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
         SDValue Store =
           DAG.getStore(Val.getValue(1), dl, Val, FIN,
-               PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
-               0, false, false, 0);
+               MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
+                       false, false, 0);
         MemOps.push_back(Store);
         FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
                           DAG.getConstant(4, getPointerTy()));

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114463&r1=114462&r2=114463&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 13:51:21 2010
@@ -1539,7 +1539,7 @@
   
   return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
                        /*isVolatile*/false, /*AlwaysInline=*/true,
-                       MachinePointerInfo(0), MachinePointerInfo(0));
+                       MachinePointerInfo(), MachinePointerInfo());
 }
 
 /// IsTailCallConvention - Return true if the calling convention is one that
@@ -1852,10 +1852,11 @@
   unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
   SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
   PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
-  if (Flags.isByVal()) {
+  if (Flags.isByVal())
     return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
-  }
-  return DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
+
+  return DAG.getStore(Chain, dl, Arg, PtrOff,
+                      MachinePointerInfo::getStack(LocMemOffset),
                       false, false, 0);
 }
 



From sabre at nondot.org  Tue Sep 21 13:58:22 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 18:58:22 -0000
Subject: [llvm-commits] [llvm] r114464 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAG.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100921185822.62C252A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 13:58:22 2010
New Revision: 114464

URL: http://llvm.org/viewvc/llvm-project?rev=114464&view=rev
Log:
finish pushing MachinePointerInfo through selectiondags.  At this point,
I think I've audited all uses, so it should be dependable for address spaces,
and the pointer+offset info should also be accurate when there.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=114464&r1=114463&r2=114464&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 21 13:58:22 2010
@@ -654,9 +654,6 @@
                    MachinePointerInfo PtrInfo, bool isVolatile,
                    bool isNonTemporal, unsigned Alignment);
   SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
-                   const Value *V, int SVOffset, bool isVolatile,
-                   bool isNonTemporal, unsigned Alignment);
-  SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
                    MachineMemOperand *MMO);
   SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
                         MachinePointerInfo PtrInfo, EVT TVT,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=114464&r1=114463&r2=114464&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 21 13:58:22 2010
@@ -4020,16 +4020,6 @@
 }
 
 SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
-                               SDValue Ptr,
-                 const Value *SV, int SVOffset, bool isVolatile,
-                 bool isNonTemporal, unsigned Alignment) {
-  
-  return getStore(Chain, dl, Val, Ptr, MachinePointerInfo(SV, SVOffset),
-                  isVolatile, isNonTemporal, Alignment);
-}
-
-
-SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
                                SDValue Ptr, MachineMemOperand *MMO) {
   EVT VT = Val.getValueType();
   SDVTList VTs = getVTList(MVT::Other);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114464&r1=114463&r2=114464&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep 21 13:58:22 2010
@@ -1088,7 +1088,8 @@
       Chains[i] =
         DAG.getStore(Chain, getCurDebugLoc(),
                      SDValue(RetOp.getNode(), RetOp.getResNo() + i),
-                     Add, NULL, Offsets[i], false, false, 0);
+                     // FIXME: better loc info would be nice.
+                     Add, MachinePointerInfo(), false, false, 0);
     }
 
     Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
@@ -3000,8 +3001,8 @@
                               DAG.getConstant(Offsets[i], PtrVT));
     Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
                              SDValue(Src.getNode(), Src.getResNo() + i),
-                             Add, PtrV, Offsets[i], isVolatile, 
-                             isNonTemporal, Alignment);
+                             Add, MachinePointerInfo(PtrV, Offsets[i]),
+                             isVolatile, isNonTemporal, Alignment);
   }
 
   DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
@@ -4448,8 +4449,8 @@
 
     // Store the stack protector onto the stack.
     Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
-                       PseudoSourceValue::getFixedStack(FI),
-                       0, true, false, 0);
+                       MachinePointerInfo::getFixedStack(FI),
+                       true, false, 0);
     setValue(&I, Res);
     DAG.setRoot(Res);
     return 0;
@@ -5760,7 +5761,7 @@
     SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
                                StoresToEmit[i].first,
                                getValue(StoresToEmit[i].second),
-                               StoresToEmit[i].second, 0,
+                               MachinePointerInfo(StoresToEmit[i].second),
                                false, false, 0);
     OutChains.push_back(Val);
   }



From ofv at wanadoo.es  Tue Sep 21 14:37:12 2010
From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=)
Date: Tue, 21 Sep 2010 21:37:12 +0200
Subject: [llvm-commits] [PATCH] Program to aid in automated testing on
	windows.
References: <AANLkTimei_VrL7ouyvTpcxEtVZqmzhwFPoJ7HW0YuUT3@mail.gmail.com>
Message-ID: <87lj6unb13.fsf@telefonica.net>

Michael Spencer <bigcheesegs at gmail.com>
writes:

> While porting test-suite over to lit so I could run it on Windows I
> ran into severe issues due to Dr. Watson and the C runtime.

[snip]

For solving the same problem on my compiler I use something like the
chunk of code below. It works fine on Windows XP, although in one case
it still pops the dialog on Vista/7. I didn't investigate the issue but
it is probably a missing _CrtSetReportMode call. Maybe it is worth a try
before adding yet another utility.

#include <signal.h>
#include <stdio.h>
#include <stdlib.h>

#if defined(_MSC_VER) && ! defined(NDEBUG)
# include <crtdbg.h>
#endif

#if defined(_WIN32)
# include <windows.h>
#endif

void InstallSignalHandlers();

#define SIGNAL_ARGS int sig

void sig_abrt_catcher(SIGNAL_ARGS);
void sig_ill_catcher(SIGNAL_ARGS);
void sig_fpr_catcher(SIGNAL_ARGS);
void sig_segv_catcher(SIGNAL_ARGS);

int main() {
  /* ... */
  InstallSignalHandlers();
  /* ... */
}

void InstallSignalHandlers() {        
  signal(SIGFPE, &sig_abrt_catcher);
  signal(SIGFPE, &sig_ill_catcher);
  signal(SIGFPE, &sig_fpr_catcher);
  signal(SIGSEGV, &sig_segv_catcher);
#if defined(_MSC_VER) && ! defined(NDEBUG)
  _CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE);
  _CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE);
  _CrtSetReportHook(&MsvcrtReportHook);
  _set_error_mode(_OUT_TO_STDERR);
#endif // #if defined(_MSC_VER) && ! defined(NDEBUG)
#if defined(_WIN32)
  SetUnhandledExceptionFilter(&UnhandledWin32Exception);
#endif
}

void sig_abrt_catcher(SIGNAL_ARGS) {
  puts("SIGABRT\n");
  exit(3);
}
  
void sig_ill_catcher(SIGNAL_ARGS) {
  puts("SIGILL\n");
  exit(3);
}

void sig_fpr_catcher(SIGNAL_ARGS) {
  puts("SIGFPR\n");
  exit(3);
}

void sig_segv_catcher(SIGNAL_ARGS) {
  puts("SIGSEGV\n");
  exit(3);
}


From sabre at nondot.org  Tue Sep 21 14:41:58 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 19:41:58 -0000
Subject: [llvm-commits] [llvm] r114468 - in /llvm/trunk/lib/Target/X86:
 X86ISelDAGToDAG.cpp X86InstrInfo.td
Message-ID: <20100921194158.B4F3C2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 14:41:58 2010
New Revision: 114468

URL: http://llvm.org/viewvc/llvm-project?rev=114468&view=rev
Log:
even though I'm about to rip it out, simplify the address mode stuff

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114468&r1=114467&r2=114468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 14:41:58 2010
@@ -404,10 +404,8 @@
     return false;
 
   // FIXME: Calls can't fold loads through segment registers yet.
-  if (const Value *Src = LD->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() >= 256)
-        return false;
+  if (LD->getPointerInfo().getAddrSpace() > 255)
+    return false;
   
   // Now let's find the callseq_start.
   while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114468&r1=114467&r2=114468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 21 14:41:58 2010
@@ -421,25 +421,17 @@
 
 /// Load patterns: these constraint the match to the right address space.
 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() > 255)
-        return false;
+  if (cast<LoadSDNode>(N)->getPointerInfo().getAddrSpace() > 255)
+    return false;
   return true;
 }]>;
 
 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      return PT->getAddressSpace() == 256;
-  return false;
+  return cast<LoadSDNode>(N)->getPointerInfo().getAddrSpace() == 256;
 }]>;
 
 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      return PT->getAddressSpace() == 257;
-  return false;
+  return cast<LoadSDNode>(N)->getPointerInfo().getAddrSpace() == 257;
 }]>;
 
 
@@ -448,10 +440,9 @@
 // known to be 32-bit aligned or better. Ditto for i8 to i16.
 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
-  if (const Value *Src = LD->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() > 255)
-        return false;
+  if (LD->getPointerInfo().getAddrSpace() > 255)
+    return false;
+
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
@@ -462,10 +453,8 @@
 
 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
   LoadSDNode *LD = cast<LoadSDNode>(N);
-  if (const Value *Src = LD->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() > 255)
-        return false;
+  if (LD->getPointerInfo().getAddrSpace() > 255)
+    return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::EXTLOAD)
     return LD->getAlignment() >= 2 && !LD->isVolatile();
@@ -474,10 +463,8 @@
 
 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
-  if (const Value *Src = LD->getSrcValue())
-    if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
-      if (PT->getAddressSpace() > 255)
-        return false;
+  if (LD->getPointerInfo().getAddrSpace() > 255)
+    return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;



From stoklund at 2pi.dk  Tue Sep 21 15:16:12 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 20:16:12 -0000
Subject: [llvm-commits] [llvm] r114469 -
	/llvm/trunk/lib/CodeGen/LiveInterval.cpp
Message-ID: <20100921201612.4AAAA2A6C12C@llvm.org>

Author: stoklund
Date: Tue Sep 21 15:16:12 2010
New Revision: 114469

URL: http://llvm.org/viewvc/llvm-project?rev=114469&view=rev
Log:
Refix MSVC9 and upper_bound. It actually needs a fully symmetric comparator.

Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=114469&r1=114468&r2=114469&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Sep 21 15:16:12 2010
@@ -30,20 +30,18 @@
 #include <algorithm>
 using namespace llvm;
 
-// CompEnd - Compare LiveRange end to Pos.
+// CompEnd - Compare LiveRange ends.
 namespace {
 struct CompEnd {
-  bool operator()(SlotIndex Pos, const LiveRange &LR) const {
-    return Pos < LR.end;
-  }
-  bool operator()(const LiveRange &LR, SlotIndex Pos) const {
-    return LR.end < Pos;
+  bool operator()(const LiveRange &A, const LiveRange &B) const {
+    return A.end < B.end;
   }
 };
 }
 
 LiveInterval::iterator LiveInterval::find(SlotIndex Pos) {
-  return std::upper_bound(begin(), end(), Pos, CompEnd());
+  return std::upper_bound(begin(), end(), LiveRange(SlotIndex(), Pos, 0),
+                          CompEnd());
 }
 
 /// killedInRange - Return true if the interval has kills in [Start,End).



From bigcheesegs at gmail.com  Tue Sep 21 15:18:18 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Tue, 21 Sep 2010 16:18:18 -0400
Subject: [llvm-commits] [PATCH] Program to aid in automated testing on
	windows.
In-Reply-To: <87lj6unb13.fsf@telefonica.net>
References: <AANLkTimei_VrL7ouyvTpcxEtVZqmzhwFPoJ7HW0YuUT3@mail.gmail.com>
	<87lj6unb13.fsf@telefonica.net>
Message-ID: <AANLkTinQbv+C_29pwRFFSKbVqUA77BGG=_+Kb3rAS7Pb@mail.gmail.com>

On Tue, Sep 21, 2010 at 3:37 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
> The following message is a courtesy copy of an article
> that has been posted to gmane.comp.compilers.llvm.cvs as well.
>
> Michael Spencer <bigcheesegs-Re5JQEeQqe8AvxtiuMwx3w at public.gmane.org>
> writes:
>
>> While porting test-suite over to lit so I could run it on Windows I
>> ran into severe issues due to Dr. Watson and the C runtime.
>
> [snip]
>
> For solving the same problem on my compiler I use something like the
> chunk of code below. It works fine on Windows XP, although in one case
> it still pops the dialog on Vista/7. I didn't investigate the issue but
> it is probably a missing _CrtSetReportMode call. Maybe it is worth a try
> before adding yet another utility.
>
> #include <signal.h>
> #include <stdio.h>
> #include <stdlib.h>
>
> #if defined(_MSC_VER) && ! defined(NDEBUG)
> # include <crtdbg.h>
> #endif
>
> #if defined(_WIN32)
> # include <windows.h>
> #endif
>
> void InstallSignalHandlers();
>
> #define SIGNAL_ARGS int sig
>
> void sig_abrt_catcher(SIGNAL_ARGS);
> void sig_ill_catcher(SIGNAL_ARGS);
> void sig_fpr_catcher(SIGNAL_ARGS);
> void sig_segv_catcher(SIGNAL_ARGS);
>
> int main() {
> ?/* ... */
> ?InstallSignalHandlers();
> ?/* ... */
> }
>
> void InstallSignalHandlers() {
> ?signal(SIGFPE, &sig_abrt_catcher);
> ?signal(SIGFPE, &sig_ill_catcher);
> ?signal(SIGFPE, &sig_fpr_catcher);
> ?signal(SIGSEGV, &sig_segv_catcher);
> #if defined(_MSC_VER) && ! defined(NDEBUG)
> ?_CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE);
> ?_CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE);
> ?_CrtSetReportHook(&MsvcrtReportHook);
> ?_set_error_mode(_OUT_TO_STDERR);
> #endif // #if defined(_MSC_VER) && ! defined(NDEBUG)
> #if defined(_WIN32)
> ?SetUnhandledExceptionFilter(&UnhandledWin32Exception);
> #endif
> }
>
> void sig_abrt_catcher(SIGNAL_ARGS) {
> ?puts("SIGABRT\n");
> ?exit(3);
> }
>
> void sig_ill_catcher(SIGNAL_ARGS) {
> ?puts("SIGILL\n");
> ?exit(3);
> }
>
> void sig_fpr_catcher(SIGNAL_ARGS) {
> ?puts("SIGFPR\n");
> ?exit(3);
> }
>
> void sig_segv_catcher(SIGNAL_ARGS) {
> ?puts("SIGSEGV\n");
> ?exit(3);
> }
>

The problem with the above is that it only affects the program that
has the code in it. Unless it is acceptable to add this to every
single test in the test suite, then that wont work. It is also useless
for programs that we are not compiling.

- Michael Spencer


From sabre at nondot.org  Tue Sep 21 15:31:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 20:31:20 -0000
Subject: [llvm-commits] [llvm] r114471 - in /llvm/trunk:
 include/llvm/Target/ lib/Target/ARM/ lib/Target/Blackfin/
 lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/
 lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/
 lib/Target/X86/ lib/Target/XCore/ utils/TableGen/
Message-ID: <20100921203120.4868C2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 15:31:19 2010
New Revision: 114471

URL: http://llvm.org/viewvc/llvm-project?rev=114471&view=rev
Log:
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

Modified:
    llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
    llvm/trunk/lib/Target/CellSPU/SPUOperands.td
    llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
    llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.h
    llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Tue Sep 21 15:31:19 2010
@@ -224,6 +224,8 @@
 def SDNPSideEffect  : SDNodeProperty;   // Sets 'HasUnmodelledSideEffects'.
 def SDNPMemOperand  : SDNodeProperty;   // Touches memory, has assoc MemOperand
 def SDNPVariadic    : SDNodeProperty;   // Node has variable arguments.
+def SDNPWantRoot    : SDNodeProperty;   // ComplexPattern gets the root of match
+def SDNPWantParent  : SDNodeProperty;   // ComplexPattern gets the parent
 
 //===----------------------------------------------------------------------===//
 // Selection DAG Node definitions.

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -72,48 +72,44 @@
 
   SDNode *Select(SDNode *N);
 
-  bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
+  bool SelectShifterOperandReg(SDValue N, SDValue &A,
                                SDValue &B, SDValue &C);
-  bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectAddrMode2(SDValue N, SDValue &Base,
                        SDValue &Offset, SDValue &Opc);
   bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
                              SDValue &Offset, SDValue &Opc);
-  bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectAddrMode3(SDValue N, SDValue &Base,
                        SDValue &Offset, SDValue &Opc);
   bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
                              SDValue &Offset, SDValue &Opc);
-  bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
-                       SDValue &Mode);
-  bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode);
+  bool SelectAddrMode5(SDValue N, SDValue &Base,
                        SDValue &Offset);
-  bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align);
+  bool SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align);
 
-  bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
+  bool SelectAddrModePC(SDValue N, SDValue &Offset,
                         SDValue &Label);
 
-  bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
-                             SDValue &Offset);
-  bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
+  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
+  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
                               SDValue &Base, SDValue &OffImm,
                               SDValue &Offset);
-  bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
                              SDValue &OffImm, SDValue &Offset);
-  bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
                              SDValue &OffImm, SDValue &Offset);
-  bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
                              SDValue &OffImm, SDValue &Offset);
-  bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
-                             SDValue &OffImm);
+  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
 
-  bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
+  bool SelectT2ShifterOperandReg(SDValue N,
                                  SDValue &BaseReg, SDValue &Opc);
-  bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
-                             SDValue &OffImm);
-  bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
+  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
                             SDValue &OffImm);
   bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
                                  SDValue &OffImm);
-  bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
+  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
                              SDValue &OffReg, SDValue &ShImm);
 
   inline bool Pred_so_imm(SDNode *inN) const {
@@ -223,8 +219,7 @@
 }
 
 
-bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
-                                              SDValue N,
+bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
                                               SDValue &BaseReg,
                                               SDValue &ShReg,
                                               SDValue &Opc) {
@@ -250,7 +245,7 @@
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
                                       SDValue &Base, SDValue &Offset,
                                       SDValue &Opc) {
   if (N.getOpcode() == ISD::MUL) {
@@ -399,7 +394,7 @@
 }
 
 
-bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
                                       SDValue &Base, SDValue &Offset,
                                       SDValue &Opc) {
   if (N.getOpcode() == ISD::SUB) {
@@ -471,14 +466,13 @@
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
-                                      SDValue &Addr, SDValue &Mode) {
+bool ARMDAGToDAGISel::SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode) {
   Addr = N;
   Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N, 
                                       SDValue &Base, SDValue &Offset) {
   if (N.getOpcode() != ISD::ADD) {
     Base = N;
@@ -526,15 +520,14 @@
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
-                                      SDValue &Addr, SDValue &Align) {
+bool ARMDAGToDAGISel::SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align){
   Addr = N;
   // Default to no alignment.
   Align = CurDAG->getTargetConstant(0, MVT::i32);
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
                                        SDValue &Offset, SDValue &Label) {
   if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
     Offset = N.getOperand(0);
@@ -546,7 +539,7 @@
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
                                             SDValue &Base, SDValue &Offset){
   // FIXME dl should come from the parent load or store, not the address
   if (N.getOpcode() != ISD::ADD) {
@@ -564,12 +557,12 @@
 }
 
 bool
-ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
+ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
                                         unsigned Scale, SDValue &Base,
                                         SDValue &OffImm, SDValue &Offset) {
   if (Scale == 4) {
     SDValue TmpBase, TmpOffImm;
-    if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
+    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
       return false;  // We want to select tLDRspi / tSTRspi instead.
     if (N.getOpcode() == ARMISD::Wrapper &&
         N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
@@ -620,26 +613,26 @@
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
                                             SDValue &Base, SDValue &OffImm,
                                             SDValue &Offset) {
-  return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
+  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
                                             SDValue &Base, SDValue &OffImm,
                                             SDValue &Offset) {
-  return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
+  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
                                             SDValue &Base, SDValue &OffImm,
                                             SDValue &Offset) {
-  return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
+  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
-                                           SDValue &Base, SDValue &OffImm) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
+                                            SDValue &Base, SDValue &OffImm) {
   if (N.getOpcode() == ISD::FrameIndex) {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
@@ -674,8 +667,7 @@
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
-                                                SDValue &BaseReg,
+bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
                                                 SDValue &Opc) {
   if (DisableShifterOp)
     return false;
@@ -697,7 +689,7 @@
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
                                             SDValue &Base, SDValue &OffImm) {
   // Match simple R + imm12 operands.
 
@@ -722,7 +714,7 @@
   }
 
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
-    if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
+    if (SelectT2AddrModeImm8(N, Base, OffImm))
       // Let t2LDRi8 handle (R - imm8).
       return false;
 
@@ -747,7 +739,7 @@
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
                                            SDValue &Base, SDValue &OffImm) {
   // Match simple R - imm8 operands.
   if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
@@ -790,7 +782,7 @@
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
+bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
                                             SDValue &Base,
                                             SDValue &OffReg, SDValue &ShImm) {
   // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
@@ -1017,7 +1009,7 @@
   DebugLoc dl = N->getDebugLoc();
 
   SDValue MemAddr, Align;
-  if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
+  if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
     return NULL;
 
   SDValue Chain = N->getOperand(0);
@@ -1128,7 +1120,7 @@
   DebugLoc dl = N->getDebugLoc();
 
   SDValue MemAddr, Align;
-  if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
+  if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
     return NULL;
 
   SDValue Chain = N->getOperand(0);
@@ -1248,7 +1240,7 @@
   DebugLoc dl = N->getDebugLoc();
 
   SDValue MemAddr, Align;
-  if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
+  if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
     return NULL;
 
   SDValue Chain = N->getOperand(0);
@@ -1426,7 +1418,7 @@
                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
   SDValue CPTmp0;
   SDValue CPTmp1;
-  if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
+  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
     unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
     unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
     unsigned Opc = 0;
@@ -1454,7 +1446,7 @@
   SDValue CPTmp0;
   SDValue CPTmp1;
   SDValue CPTmp2;
-  if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
+  if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
     SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
     SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
     return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep 21 15:31:19 2010
@@ -379,7 +379,8 @@
 }
 
 def am2offset : Operand<i32>,
-                ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
+                ComplexPattern<i32, 2, "SelectAddrMode2Offset",
+                [], [SDNPWantRoot]> {
   let PrintMethod = "printAddrMode2OffsetOperand";
   let MIOperandInfo = (ops GPR, i32imm);
 }
@@ -394,7 +395,8 @@
 }
 
 def am3offset : Operand<i32>,
-                ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
+                ComplexPattern<i32, 2, "SelectAddrMode3Offset",
+                               [], [SDNPWantRoot]> {
   let PrintMethod = "printAddrMode3OffsetOperand";
   let MIOperandInfo = (ops GPR, i32imm);
 }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep 21 15:31:19 2010
@@ -140,7 +140,8 @@
 }
 
 def t2am_imm8_offset : Operand<i32>,
-                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
+                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
+                                      [], [SDNPWantRoot]> {
   let PrintMethod = "printT2AddrModeImm8OffsetOperand";
 }
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -51,8 +51,7 @@
 
   private:
     SDNode *Select(SDNode *N);
-    bool SelectADDRspii(SDNode *Op, SDValue Addr,
-                        SDValue &Base, SDValue &Offset);
+    bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
 
     // Walk the DAG after instruction selection, fixing register class issues.
     void FixRegisterClasses(SelectionDAG &DAG);
@@ -94,8 +93,7 @@
   return SelectCode(N);
 }
 
-bool BlackfinDAGToDAGISel::SelectADDRspii(SDNode *Op,
-                                          SDValue Addr,
+bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Addr,
                                           SDValue &Base,
                                           SDValue &Offset) {
   FrameIndexSDNode *FIN = 0;

Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Tue Sep 21 15:31:19 2010
@@ -654,7 +654,11 @@
 // A-form   : abs     (256K LSA offset)
 // D-form(2): [r+I7]  (7-bit signed offset + reg)
 
-def dform_addr   : ComplexPattern<iPTR, 2, "SelectDFormAddr",     [], []>;
-def xform_addr   : ComplexPattern<iPTR, 2, "SelectXFormAddr",     [], []>;
-def aform_addr   : ComplexPattern<iPTR, 2, "SelectAFormAddr",     [], []>;
-def dform2_addr  : ComplexPattern<iPTR, 2, "SelectDForm2Addr",    [], []>;
+def dform_addr   : ComplexPattern<iPTR, 2, "SelectDFormAddr",
+                                  [], [SDNPWantRoot]>;
+def xform_addr   : ComplexPattern<iPTR, 2, "SelectXFormAddr",
+                                  [], [SDNPWantRoot]>;
+def aform_addr   : ComplexPattern<iPTR, 2, "SelectAFormAddr",
+                                  [], [SDNPWantRoot]>;
+def dform2_addr  : ComplexPattern<iPTR, 2, "SelectDForm2Addr",
+                                  [], [SDNPWantRoot]>;

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -82,8 +82,8 @@
   SDNode *Select(SDNode *N);
 
   // Address Selection
-  bool SelectAddrRegReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index);
-  bool SelectAddrRegImm(SDNode *Op, SDValue N, SDValue &Disp, SDValue &Base);
+  bool SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index);
+  bool SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base);
 
   // getI32Imm - Return a target constant with the specified value, of type i32.
   inline SDValue getI32Imm(unsigned Imm) {
@@ -118,7 +118,7 @@
 /// can be represented as an indexed [r+r] operation.  Returns false if it
 /// can be more efficiently represented with [r+imm].
 bool MBlazeDAGToDAGISel::
-SelectAddrRegReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index) {
+SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index) {
   if (N.getOpcode() == ISD::FrameIndex) return false;
   if (N.getOpcode() == ISD::TargetExternalSymbol ||
       N.getOpcode() == ISD::TargetGlobalAddress)
@@ -145,9 +145,9 @@
 /// a signed 32-bit displacement [r+imm], and if it is not better
 /// represented as reg+reg.
 bool MBlazeDAGToDAGISel::
-SelectAddrRegImm(SDNode *Op, SDValue N, SDValue &Disp, SDValue &Base) {
+SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base) {
   // If this can be more profitably realized as r+r, fail.
-  if (SelectAddrRegReg(Op, N, Disp, Base))
+  if (SelectAddrRegReg(N, Disp, Base))
     return false;
 
   if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -120,7 +120,7 @@
     SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
                                unsigned Opc8, unsigned Opc16);
 
-    bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
+    bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
   };
 }  // end anonymous namespace
 
@@ -245,7 +245,7 @@
 /// SelectAddr - returns true if it is able pattern match an addressing mode.
 /// It returns the operands which make up the maximal addressing mode it can
 /// match by reference.
-bool MSP430DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N,
+bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
                                     SDValue &Base, SDValue &Disp) {
   MSP430ISelAddressMode AM;
 
@@ -263,7 +263,7 @@
     AM.Base.Reg;
 
   if (AM.GV)
-    Disp = CurDAG->getTargetGlobalAddress(AM.GV, Op->getDebugLoc(),
+    Disp = CurDAG->getTargetGlobalAddress(AM.GV, N->getDebugLoc(),
                                           MVT::i16, AM.Disp,
                                           0/*AM.SymbolFlags*/);
   else if (AM.CP)
@@ -289,7 +289,7 @@
   switch (ConstraintCode) {
   default: return true;
   case 'm':   // memory
-    if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
+    if (!SelectAddr(Op, Op0, Op1))
       return true;
     break;
   }

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -84,8 +84,7 @@
   SDNode *Select(SDNode *N);
 
   // Complex Pattern.
-  bool SelectAddr(SDNode *Op, SDValue N, 
-                  SDValue &Base, SDValue &Offset);
+  bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
 
   SDNode *SelectLoadFp64(SDNode *N);
   SDNode *SelectStoreFp64(SDNode *N);
@@ -110,8 +109,7 @@
 /// ComplexPattern used on MipsInstrInfo
 /// Used on Mips Load/Store instructions
 bool MipsDAGToDAGISel::
-SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base)
-{
+SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
   // if Address is FI, get the TargetFrameIndex.
   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@@ -193,7 +191,7 @@
   SDValue N1 = N->getOperand(1);
   SDValue Offset0, Offset1, Base;
 
-  if (!SelectAddr(N, N1, Offset0, Base) ||
+  if (!SelectAddr(N1, Offset0, Base) ||
       N1.getValueType() != MVT::i32)
     return NULL;
 
@@ -257,7 +255,7 @@
   SDValue N2 = N->getOperand(2);
   SDValue Offset0, Offset1, Base;
 
-  if (!SelectAddr(N, N2, Offset0, Base) ||
+  if (!SelectAddr(N2, Offset0, Base) ||
       N1.getValueType() != MVT::f64 ||
       N2.getValueType() != MVT::i32)
     return NULL;

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -37,8 +37,7 @@
 
 // SelectDirectAddr - Match a direct address for DAG. 
 // A direct address could be a globaladdress or externalsymbol.
-bool PIC16DAGToDAGISel::SelectDirectAddr(SDNode *Op, SDValue N, 
-                                      SDValue &Address) {
+bool PIC16DAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
   // Return true if TGA or ES.
   if (N.getOpcode() == ISD::TargetGlobalAddress
       || N.getOpcode() == ISD::TargetExternalSymbol) {

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelDAGToDAG.h Tue Sep 21 15:31:19 2010
@@ -52,7 +52,7 @@
   SDNode *Select(SDNode *N);
 
   // Match direct address complex pattern.
-  bool SelectDirectAddr(SDNode *Op, SDValue N, SDValue &Address);
+  bool SelectDirectAddr(SDValue N, SDValue &Address);
 
 };
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -104,7 +104,7 @@
 
     /// SelectAddrImm - Returns true if the address N can be represented by
     /// a base register plus a signed 16-bit displacement [r+imm].
-    bool SelectAddrImm(SDNode *Op, SDValue N, SDValue &Disp,
+    bool SelectAddrImm(SDValue N, SDValue &Disp,
                        SDValue &Base) {
       return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
     }
@@ -112,7 +112,7 @@
     /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
     /// immediate field.  Because preinc imms have already been validated, just
     /// accept it.
-    bool SelectAddrImmOffs(SDNode *Op, SDValue N, SDValue &Out) const {
+    bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
       Out = N;
       return true;
     }
@@ -120,23 +120,20 @@
     /// SelectAddrIdx - Given the specified addressed, check to see if it can be
     /// represented as an indexed [r+r] operation.  Returns false if it can
     /// be represented by [r+imm], which are preferred.
-    bool SelectAddrIdx(SDNode *Op, SDValue N, SDValue &Base,
-                       SDValue &Index) {
+    bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
       return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
     }
     
     /// SelectAddrIdxOnly - Given the specified addressed, force it to be
     /// represented as an indexed [r+r] operation.
-    bool SelectAddrIdxOnly(SDNode *Op, SDValue N, SDValue &Base,
-                           SDValue &Index) {
+    bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
       return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
     }
 
     /// SelectAddrImmShift - Returns true if the address N can be represented by
     /// a base register plus a signed 14-bit displacement [r+imm*4].  Suitable
     /// for use by STD and friends.
-    bool SelectAddrImmShift(SDNode *Op, SDValue N, SDValue &Disp,
-                            SDValue &Base) {
+    bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) {
       return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
     }
       

Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -44,9 +44,8 @@
   SDNode *Select(SDNode *N);
 
   // Complex Pattern Selectors.
-  bool SelectADDRrr(SDNode *Op, SDValue N, SDValue &R1, SDValue &R2);
-  bool SelectADDRri(SDNode *Op, SDValue N, SDValue &Base,
-                    SDValue &Offset);
+  bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
+  bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
@@ -71,7 +70,7 @@
   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
 }
 
-bool SparcDAGToDAGISel::SelectADDRri(SDNode *Op, SDValue Addr,
+bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
                                      SDValue &Base, SDValue &Offset) {
   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@@ -112,8 +111,7 @@
   return true;
 }
 
-bool SparcDAGToDAGISel::SelectADDRrr(SDNode *Op, SDValue Addr,
-                                     SDValue &R1,  SDValue &R2) {
+bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
   if (Addr.getOpcode() == ISD::FrameIndex) return false;
   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
       Addr.getOpcode() == ISD::TargetGlobalAddress)
@@ -196,8 +194,8 @@
   switch (ConstraintCode) {
   default: return true;
   case 'm':   // memory
-   if (!SelectADDRrr(Op.getNode(), Op, Op0, Op1))
-     SelectADDRri(Op.getNode(), Op, Op0, Op1);
+   if (!SelectADDRrr(Op, Op0, Op1))
+     SelectADDRri(Op, Op0, Op1);
    break;
   }
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -120,18 +120,17 @@
     #include "SystemZGenDAGISel.inc"
 
   private:
-    bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
+    bool SelectAddrRI12Only(SDValue& Addr,
                             SDValue &Base, SDValue &Disp);
-    bool SelectAddrRI12(SDNode *Op, SDValue& Addr,
+    bool SelectAddrRI12(SDValue& Addr,
                         SDValue &Base, SDValue &Disp,
                         bool is12BitOnly = false);
-    bool SelectAddrRI(SDNode *Op, SDValue& Addr,
-                      SDValue &Base, SDValue &Disp);
-    bool SelectAddrRRI12(SDNode *Op, SDValue Addr,
+    bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp);
+    bool SelectAddrRRI12(SDValue Addr,
                          SDValue &Base, SDValue &Disp, SDValue &Index);
-    bool SelectAddrRRI20(SDNode *Op, SDValue Addr,
+    bool SelectAddrRRI20(SDValue Addr,
                          SDValue &Base, SDValue &Disp, SDValue &Index);
-    bool SelectLAAddr(SDNode *Op, SDValue Addr,
+    bool SelectLAAddr(SDValue Addr,
                       SDValue &Base, SDValue &Disp, SDValue &Index);
 
     SDNode *Select(SDNode *Node);
@@ -353,12 +352,12 @@
 
 /// Returns true if the address can be represented by a base register plus
 /// an unsigned 12-bit displacement [r+imm].
-bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
+bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue &Addr,
                                              SDValue &Base, SDValue &Disp) {
-  return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
+  return SelectAddrRI12(Addr, Base, Disp, /*is12BitOnly*/true);
 }
 
-bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr,
+bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue &Addr,
                                          SDValue &Base, SDValue &Disp,
                                          bool is12BitOnly) {
   SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
@@ -408,7 +407,7 @@
 
 /// Returns true if the address can be represented by a base register plus
 /// a signed 20-bit displacement [r+imm].
-bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr,
+bool SystemZDAGToDAGISel::SelectAddrRI(SDValue& Addr,
                                        SDValue &Base, SDValue &Disp) {
   SystemZRRIAddressMode AM(/*isRI*/true);
   bool Done = false;
@@ -451,7 +450,7 @@
 
 /// Returns true if the address can be represented by a base register plus
 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
-bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr,
+bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Addr,
                                 SDValue &Base, SDValue &Disp, SDValue &Index) {
   SystemZRRIAddressMode AM20, AM12;
   bool Done = false;
@@ -500,7 +499,7 @@
 
 /// Returns true if the address can be represented by a base register plus
 /// index register plus a signed 20-bit displacement [base + idx + imm].
-bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr,
+bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Addr,
                                 SDValue &Base, SDValue &Disp, SDValue &Index) {
   SystemZRRIAddressMode AM;
   bool Done = false;
@@ -544,7 +543,7 @@
 
 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
-bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
+bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Addr,
                                   SDValue &Base, SDValue &Disp, SDValue &Index) {
   SystemZRRIAddressMode AM;
 
@@ -581,7 +580,7 @@
                                  SDValue &Base, SDValue &Disp, SDValue &Index) {
   if (ISD::isNON_EXTLoad(N.getNode()) &&
       IsLegalToFold(N, P, P, OptLevel))
-    return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
+    return SelectAddrRRI20(N.getOperand(1), Base, Disp, Index);
   return false;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -197,13 +197,13 @@
     bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
                                  unsigned Depth);
     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
-    bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
+    bool SelectAddr(SDValue N, SDValue &Base,
                     SDValue &Scale, SDValue &Index, SDValue &Disp,
                     SDValue &Segment);
-    bool SelectLEAAddr(SDNode *Op, SDValue N, SDValue &Base,
+    bool SelectLEAAddr(SDValue N, SDValue &Base,
                        SDValue &Scale, SDValue &Index, SDValue &Disp,
                        SDValue &Segment);
-    bool SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
+    bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
                            SDValue &Scale, SDValue &Index, SDValue &Disp,
                            SDValue &Segment);
     bool SelectScalarSSELoad(SDNode *Root, SDValue N,
@@ -1147,7 +1147,7 @@
 /// SelectAddr - returns true if it is able pattern match an addressing mode.
 /// It returns the operands which make up the maximal addressing mode it can
 /// match by reference.
-bool X86DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
+bool X86DAGToDAGISel::SelectAddr(SDValue N, SDValue &Base,
                                  SDValue &Scale, SDValue &Index,
                                  SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
@@ -1186,7 +1186,7 @@
         IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
         IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
       LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
-      if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
+      if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
         return false;
       return true;
     }
@@ -1204,7 +1204,7 @@
       IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
     // Okay, this is a zero extending load.  Fold it.
     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
-    if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
+    if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
       return false;
     PatternNodeWithChain = SDValue(LD, 0);
     return true;
@@ -1215,7 +1215,7 @@
 
 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
 /// mode it matches can be cost effectively emitted as an LEA instruction.
-bool X86DAGToDAGISel::SelectLEAAddr(SDNode *Op, SDValue N,
+bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
                                     SDValue &Base, SDValue &Scale,
                                     SDValue &Index, SDValue &Disp,
                                     SDValue &Segment) {
@@ -1277,7 +1277,7 @@
 }
 
 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
-bool X86DAGToDAGISel::SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
+bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
                                         SDValue &Scale, SDValue &Index,
                                         SDValue &Disp, SDValue &Segment) {
   assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
@@ -1310,7 +1310,7 @@
       !IsLegalToFold(N, P, P, OptLevel))
     return false;
   
-  return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
+  return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp, Segment);
 }
 
 /// getGlobalBaseReg - Return an SDNode that returns the value of
@@ -1328,7 +1328,7 @@
   SDValue In2L = Node->getOperand(2);
   SDValue In2H = Node->getOperand(3);
   SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-  if (!SelectAddr(In1.getNode(), In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
+  if (!SelectAddr(In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
     return NULL;
   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
   MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
@@ -1354,7 +1354,7 @@
   SDValue Ptr = Node->getOperand(1);
   SDValue Val = Node->getOperand(2);
   SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-  if (!SelectAddr(Ptr.getNode(), Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
+  if (!SelectAddr(Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
     return 0;
 
   bool isInc = false, isDec = false, isSub = false, isCN = false;
@@ -1970,7 +1970,7 @@
   case 'v':   // not offsetable    ??
   default: return true;
   case 'm':   // memory
-    if (!SelectAddr(Op.getNode(), Op, Op0, Op1, Op2, Op3, Op4))
+    if (!SelectAddr(Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Sep 21 15:31:19 2010
@@ -181,9 +181,11 @@
 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 // forms.
 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
-                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
+                                   SDNPWantRoot]>;
 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
-                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
+                                   SDNPWantRoot]>;
 
 def ssmem : Operand<v4f32> {
   let PrintMethod = "printf32mem";

Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Tue Sep 21 15:31:19 2010
@@ -68,12 +68,9 @@
     }
 
     // Complex Pattern Selectors.
-    bool SelectADDRspii(SDNode *Op, SDValue Addr, SDValue &Base,
-                        SDValue &Offset);
-    bool SelectADDRdpii(SDNode *Op, SDValue Addr, SDValue &Base,
-                        SDValue &Offset);
-    bool SelectADDRcpii(SDNode *Op, SDValue Addr, SDValue &Base,
-                        SDValue &Offset);
+    bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
+    bool SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset);
+    bool SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset);
     
     virtual const char *getPassName() const {
       return "XCore DAG->DAG Pattern Instruction Selection";
@@ -91,8 +88,8 @@
   return new XCoreDAGToDAGISel(TM);
 }
 
-bool XCoreDAGToDAGISel::SelectADDRspii(SDNode *Op, SDValue Addr,
-                                  SDValue &Base, SDValue &Offset) {
+bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
+                                       SDValue &Offset) {
   FrameIndexSDNode *FIN = 0;
   if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@@ -113,8 +110,8 @@
   return false;
 }
 
-bool XCoreDAGToDAGISel::SelectADDRdpii(SDNode *Op, SDValue Addr,
-                                  SDValue &Base, SDValue &Offset) {
+bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base,
+                                       SDValue &Offset) {
   if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
     Base = Addr.getOperand(0);
     Offset = CurDAG->getTargetConstant(0, MVT::i32);
@@ -134,8 +131,8 @@
   return false;
 }
 
-bool XCoreDAGToDAGISel::SelectADDRcpii(SDNode *Op, SDValue Addr,
-                                  SDValue &Base, SDValue &Offset) {
+bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base,
+                                       SDValue &Offset) {
   if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
     Base = Addr.getOperand(0);
     Offset = CurDAG->getTargetConstant(0, MVT::i32);

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Sep 21 15:31:19 2010
@@ -407,6 +407,10 @@
       Properties |= 1 << SDNPMemOperand;
     } else if (PropList[i]->getName() == "SDNPVariadic") {
       Properties |= 1 << SDNPVariadic;
+    } else if (PropList[i]->getName() == "SDNPWantRoot") {
+      Properties |= 1 << SDNPWantRoot;
+    } else if (PropList[i]->getName() == "SDNPWantParent") {
+      Properties |= 1 << SDNPWantParent;
     } else {
       errs() << "Unsupported SD Node property '" << PropList[i]->getName()
              << "' on ComplexPattern '" << R->getName() << "'!\n";

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.h Tue Sep 21 15:31:19 2010
@@ -42,7 +42,9 @@
   SDNPMayStore,
   SDNPSideEffect,
   SDNPMemOperand,
-  SDNPVariadic
+  SDNPVariadic,
+  SDNPWantRoot,
+  SDNPWantParent
 };
 
 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp?rev=114471&r1=114470&r2=114471&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Tue Sep 21 15:31:19 2010
@@ -649,7 +649,13 @@
       OS << "    Result.resize(NextRes+" << NumOps << ");\n";
       OS << "    return "  << P.getSelectFunc();
 
-      OS << "(Root, N";
+      OS << "(";
+      // If the complex pattern wants the root of the match, pass it in as the
+      // first argument.
+      if (P.hasProperty(SDNPWantRoot))
+        OS << "Root, ";
+      
+      OS << "N";
       for (unsigned i = 0; i != NumOps; ++i)
         OS << ", Result[NextRes+" << i << ']';
       OS << ");\n";



From sabre at nondot.org  Tue Sep 21 15:37:12 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 20:37:12 -0000
Subject: [llvm-commits] [llvm] r114472 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGISel.h
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 utils/TableGen/DAGISelMatcherEmitter.cpp
Message-ID: <20100921203712.B0EC02A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 15:37:12 2010
New Revision: 114472

URL: http://llvm.org/viewvc/llvm-project?rev=114472&view=rev
Log:
just like they can opt into getting the root of the pattern being
matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=114472&r1=114471&r2=114472&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Tue Sep 21 15:37:12 2010
@@ -254,7 +254,8 @@
     return 0;
   }
   
-  virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
+  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
+                                   unsigned PatternNo,
                                    SmallVectorImpl<SDValue> &Result) {
     assert(0 && "Tblgen should generate the implementation of this!");
     return false;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=114472&r1=114471&r2=114472&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Sep 21 15:37:12 2010
@@ -2086,7 +2086,11 @@
       unsigned CPNum = MatcherTable[MatcherIndex++];
       unsigned RecNo = MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
-      if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
+      SDNode *Parent = 0;
+      if (NodeStack.size() > 1)
+        Parent = NodeStack[NodeStack.size()-2].getNode();
+      
+      if (!CheckComplexPattern(NodeToMatch, Parent, RecordedNodes[RecNo], CPNum,
                                RecordedNodes))
         break;
       continue;

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp?rev=114472&r1=114471&r2=114472&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Tue Sep 21 15:37:12 2010
@@ -633,7 +633,7 @@
   // Emit CompletePattern matchers.
   // FIXME: This should be const.
   if (!ComplexPatterns.empty()) {
-    OS << "bool CheckComplexPattern(SDNode *Root, SDValue N,\n";
+    OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,\n";
     OS << "      unsigned PatternNo, SmallVectorImpl<SDValue> &Result) {\n";
     OS << "  unsigned NextRes = Result.size();\n";
     OS << "  switch (PatternNo) {\n";
@@ -655,6 +655,11 @@
       if (P.hasProperty(SDNPWantRoot))
         OS << "Root, ";
       
+      // If the complex pattern wants the parent of the operand being matched,
+      // pass it in as the next argument.
+      if (P.hasProperty(SDNPWantParent))
+        OS << "Parent, ";
+      
       OS << "N";
       for (unsigned i = 0; i != NumOps; ++i)
         OS << ", Result[NextRes+" << i << ']';



From resistor at mac.com  Tue Sep 21 15:42:50 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 21 Sep 2010 20:42:50 -0000
Subject: [llvm-commits] [llvm] r114473 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp
 Target/X86/X86ISelLowering.h
Message-ID: <20100921204250.4FA7C2A6C12C@llvm.org>

Author: resistor
Date: Tue Sep 21 15:42:50 2010
New Revision: 114473

URL: http://llvm.org/viewvc/llvm-project?rev=114473&view=rev
Log:
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using 
the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114473&r1=114472&r2=114473&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep 21 15:42:50 2010
@@ -1424,6 +1424,20 @@
                                        N0.getOperand(0).getOperand(1),
                                        N0.getOperand(1)));
 
+  if (N1.getOpcode() == ISD::AND) {
+    SDValue AndOp0 = N1.getOperand(0);
+    ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 
+    unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
+    unsigned DestBits = VT.getScalarType().getSizeInBits();
+    
+    // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
+    // and similar xforms where the inner op is either ~0 or 0.
+    if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
+      DebugLoc DL = N->getDebugLoc();
+      return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
+    }
+  }
+
   return SDValue();
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114473&r1=114472&r2=114473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 15:42:50 2010
@@ -1021,7 +1021,6 @@
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::STORE);
   setTargetDAGCombine(ISD::ZERO_EXTEND);
-  setTargetDAGCombine(ISD::ADD);
   if (Subtarget->is64Bit())
     setTargetDAGCombine(ISD::MUL);
 
@@ -9980,6 +9979,16 @@
   }
 }
 
+unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
+                                                         unsigned Depth) const {
+  // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
+  if (Op.getOpcode() == X86ISD::SETCC_CARRY)
+    return Op.getValueType().getScalarType().getSizeInBits();
+  
+  // Fallback case.
+  return 1;
+}
+
 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
 /// node is a GlobalAddress + offset.
 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
@@ -10454,27 +10463,6 @@
   return SDValue();
 }
 
-/// PerformAddCombine - Optimize ADD when combined with X86 opcodes.
-static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
-                                 TargetLowering::DAGCombinerInfo &DCI) {
-  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
-    return SDValue();
-  
-  EVT VT = N->getValueType(0);
-  SDValue Op1 = N->getOperand(1);
-  if (Op1->getOpcode() == ISD::AND) {
-    SDValue AndOp0 = Op1->getOperand(0);
-    ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(Op1->getOperand(1)); 
-    // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
-    if (AndOp0->getOpcode() == X86ISD::SETCC_CARRY &&
-        AndOp1 && AndOp1->getZExtValue() == 1) {
-      DebugLoc DL = N->getDebugLoc();
-      return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
-    }
-  }
-  
-  return SDValue();
-}
 
 /// PerformMulCombine - Optimize a single multiply with constant into two
 /// in order to implement it with two cheaper instructions, e.g.
@@ -10961,7 +10949,6 @@
                         return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
   case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
   case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
-  case ISD::ADD:            return PerformAddCombine(N, DAG, DCI);
   case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
   case ISD::SHL:
   case ISD::SRA:

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114473&r1=114472&r2=114473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 15:42:50 2010
@@ -523,6 +523,11 @@
                                                 const SelectionDAG &DAG,
                                                 unsigned Depth = 0) const;
 
+    // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
+    // operation that are sign bits.
+    virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
+                                                     unsigned Depth) const;
+
     virtual bool
     isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
     



From sabre at nondot.org  Tue Sep 21 15:46:40 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 20:46:40 -0000
Subject: [llvm-commits] [llvm] r114474 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20100921204640.EF4612A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 15:46:40 2010
New Revision: 114474

URL: http://llvm.org/viewvc/llvm-project?rev=114474&view=rev
Log:
correct this logic.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=114474&r1=114473&r2=114474&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Sep 21 15:46:40 2010
@@ -2087,8 +2087,8 @@
       unsigned RecNo = MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
       SDNode *Parent = 0;
-      if (NodeStack.size() > 1)
-        Parent = NodeStack[NodeStack.size()-2].getNode();
+      if (!NodeStack.empty())
+        Parent = NodeStack[NodeStack.size()-1].getNode();
       
       if (!CheckComplexPattern(NodeToMatch, Parent, RecordedNodes[RecNo], CPNum,
                                RecordedNodes))



From dpatel at apple.com  Tue Sep 21 15:50:32 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 21 Sep 2010 20:50:32 -0000
Subject: [llvm-commits] [llvm] r114475 -
	/llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
Message-ID: <20100921205032.C24752A6C12C@llvm.org>

Author: dpatel
Date: Tue Sep 21 15:50:32 2010
New Revision: 114475

URL: http://llvm.org/viewvc/llvm-project?rev=114475&view=rev
Log:
Use FileCheck

Modified:
    llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll

Modified: llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll?rev=114475&r1=114474&r2=114475&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll Tue Sep 21 15:50:32 2010
@@ -1,5 +1,8 @@
-; RUN: llc -march=x86-64 -O2 < %s | grep debug_loc12
-; Test to check .debug_loc support. This test case emits 13 debug_loc entries.
+; RUN: llc -march=x86-64 -O2 < %s | FileCheck %s
+; Test to check .debug_loc support. This test case emits many debug_loc entries.
+
+; CHECK: Loc expr size
+; CHECK-NEXT: DW_OP_reg
 
 %0 = type { double }
 



From wendling at apple.com  Tue Sep 21 15:54:25 2010
From: wendling at apple.com (Bill Wendling)
Date: Tue, 21 Sep 2010 13:54:25 -0700
Subject: [llvm-commits] [test-suite] r114425 -
	/test-suite/tags/RELEASE_28/rc2/
In-Reply-To: <2c85a2f9-d7de-405c-8b5e-83b7e253d88b@c16g2000vbp.googlegroups.com>
References: <20100921103619.5C7632A6C12C@llvm.org>
	<2c85a2f9-d7de-405c-8b5e-83b7e253d88b@c16g2000vbp.googlegroups.com>
Message-ID: <01ABDB2A-7534-482F-BC6B-8DC2E44662D9@apple.com>

On Sep 21, 2010, at 6:49 AM, Gabor Greif wrote:

> Hi Bill!
> 
> On Sep 21, 12:36 pm, Bill Wendling <isanb... at gmail.com> wrote:
>> Author: void
>> Date: Tue Sep 21 05:36:19 2010
>> New Revision: 114425
>> 
>> URL:http://llvm.org/viewvc/llvm-project?rev=114425&view=rev
>> Log:
>> Creating release candidate 2 from 2.8 release branch.
>> 
>> Added:
>>     test-suite/tags/RELEASE_28/rc2/
>>       - copied from r114424, test-suite/tags/RELEASE_28/rc1/
> 
> Heh, this is in conflict what you say above. You wanted to cut from
> the 28*branch*, right?
> 
Yeah, I know. But I was getting stupid errors...and the test-suite hasn't changed since rc1, so it's effectively the same. :)

-bw




From ofv at wanadoo.es  Tue Sep 21 15:54:50 2010
From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes)
Date: Tue, 21 Sep 2010 22:54:50 +0200
Subject: [llvm-commits] [PATCH] Program to aid in automated testing on
	windows.
In-Reply-To: <AANLkTinQbv+C_29pwRFFSKbVqUA77BGG=_+Kb3rAS7Pb@mail.gmail.com>
	(Michael Spencer's message of "Tue, 21 Sep 2010 16:18:18 -0400")
References: <AANLkTimei_VrL7ouyvTpcxEtVZqmzhwFPoJ7HW0YuUT3@mail.gmail.com>
	<87lj6unb13.fsf@telefonica.net>
	<AANLkTinQbv+C_29pwRFFSKbVqUA77BGG=_+Kb3rAS7Pb@mail.gmail.com>
Message-ID: <87fwx2n7fp.fsf@telefonica.net>

Michael Spencer <bigcheesegs at gmail.com> writes:

> The problem with the above is that it only affects the program that
> has the code in it. Unless it is acceptable to add this to every
> single test in the test suite, then that wont work. It is also useless
> for programs that we are not compiling.

Ops! you are right. Forgot that some tests consists on compiling *and*
running the executable.

From dpatel at apple.com  Tue Sep 21 15:56:33 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 21 Sep 2010 20:56:33 -0000
Subject: [llvm-commits] [llvm] r114478 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20100921205633.608472A6C12C@llvm.org>

Author: dpatel
Date: Tue Sep 21 15:56:33 2010
New Revision: 114478

URL: http://llvm.org/viewvc/llvm-project?rev=114478&view=rev
Log:
If only user of a vreg is an copy instruction to export copy of vreg out of current basic block then insert DBG_VALUE so that debug value of the variable is also transfered to new vreg.
Testcase is in r114476.
This fixes radar 8412415.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=114478&r1=114477&r2=114478&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Sep 21 15:56:33 2010
@@ -290,6 +290,29 @@
               TII.get(TargetOpcode::DBG_VALUE))
         .addReg(LDI->second, RegState::Debug)
         .addImm(Offset).addMetadata(Variable);
+
+      // If this vreg is directly copied into an exported register then
+      // that COPY instructions also need DBG_VALUE, if it is the only
+      // user of LDI->second.
+      MachineInstr *CopyUseMI = NULL;
+      for (MachineRegisterInfo::use_iterator 
+             UI = RegInfo->use_begin(LDI->second); 
+           MachineInstr *UseMI = UI.skipInstruction();) {
+        if (UseMI->isDebugValue()) continue;
+        if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
+          CopyUseMI = UseMI; continue;
+        }
+        // Otherwise this is another use or second copy use.
+        CopyUseMI = NULL; break;
+      }
+      if (CopyUseMI) {
+        MachineInstr *NewMI =
+          BuildMI(*MF, CopyUseMI->getDebugLoc(), 
+                  TII.get(TargetOpcode::DBG_VALUE))
+          .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
+          .addImm(Offset).addMetadata(Variable);
+        EntryMBB->insertAfter(CopyUseMI, NewMI);
+      }
     }
   }
 



From dpatel at apple.com  Tue Sep 21 16:10:42 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 21 Sep 2010 21:10:42 -0000
Subject: [llvm-commits] [llvm] r114481 -
	/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
Message-ID: <20100921211042.B35F32A6C12C@llvm.org>

Author: dpatel
Date: Tue Sep 21 16:10:42 2010
New Revision: 114481

URL: http://llvm.org/viewvc/llvm-project?rev=114481&view=rev
Log:
Add insertAfter. This should have accompanied previous check-in.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h

Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=114481&r1=114480&r2=114481&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Sep 21 16:10:42 2010
@@ -308,6 +308,9 @@
   template<typename IT>
   void insert(iterator I, IT S, IT E) { Insts.insert(I, S, E); }
   iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M); }
+  iterator insertAfter(iterator I, MachineInstr *M) { 
+    return Insts.insertAfter(I, M); 
+  }
 
   // erase - Remove the specified element or range from the instruction list.
   // These functions delete any instructions removed.



From gohman at apple.com  Tue Sep 21 16:20:14 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 21 Sep 2010 21:20:14 -0000
Subject: [llvm-commits] [llvm] r114483 -
	/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
Message-ID: <20100921212014.266B02A6C12C@llvm.org>

Author: djg
Date: Tue Sep 21 16:20:13 2010
New Revision: 114483

URL: http://llvm.org/viewvc/llvm-project?rev=114483&view=rev
Log:
Add some utility routines.

Modified:
    llvm/trunk/include/llvm/Analysis/AliasAnalysis.h

Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=114483&r1=114482&r2=114483&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Sep 21 16:20:13 2010
@@ -97,6 +97,18 @@
                       unsigned S = UnknownSize,
                       const MDNode *N = 0)
       : Ptr(P), Size(S), TBAATag(N) {}
+
+    Location getWithNewPtr(const Value *NewPtr) const {
+      Location Copy(*this);
+      Copy.Ptr = NewPtr;
+      return Copy;
+    }
+
+    Location getWithoutTBAATag() const {
+      Location Copy(*this);
+      Copy.TBAATag = 0;
+      return Copy;
+    }
   };
 
   /// Alias analysis result - Either we know for sure that it does not alias, we



From bob.wilson at apple.com  Tue Sep 21 16:44:14 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 21 Sep 2010 21:44:14 -0000
Subject: [llvm-commits] [llvm] r114487 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20100921214414.7B4002A6C12C@llvm.org>

Author: bwilson
Date: Tue Sep 21 16:44:14 2010
New Revision: 114487

URL: http://llvm.org/viewvc/llvm-project?rev=114487&view=rev
Log:
Clarify a comment.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=114487&r1=114486&r2=114487&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Sep 21 16:44:14 2010
@@ -796,7 +796,7 @@
 bool CodeGenPrepare::OptimizeExtUses(Instruction *I) {
   BasicBlock *DefBB = I->getParent();
 
-  // If both result of the {s|z}xt and its source are live out, rewrite all
+  // If the result of a {s|z}ext and its source are both live out, rewrite all
   // other uses of the source with result of extension.
   Value *Src = I->getOperand(0);
   if (Src->hasOneUse())



From bob.wilson at apple.com  Tue Sep 21 16:54:27 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 21 Sep 2010 21:54:27 -0000
Subject: [llvm-commits] [llvm] r114488 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20100921215427.BFE152A6C12C@llvm.org>

Author: bwilson
Date: Tue Sep 21 16:54:27 2010
New Revision: 114488

URL: http://llvm.org/viewvc/llvm-project?rev=114488&view=rev
Log:
Move a sign-extend or a zero-extend of a load to the same basic block as the
load when the type of the load is not legal, even if truncates are not free.
The load is going to be legalized to an extending load anyway.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=114488&r1=114487&r2=114488&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Sep 21 16:54:27 2010
@@ -772,7 +772,8 @@
   // If the load has other users and the truncate is not free, this probably
   // isn't worthwhile.
   if (!LI->hasOneUse() &&
-      TLI && !TLI->isTruncateFree(I->getType(), LI->getType()))
+      TLI && TLI->isTypeLegal(TLI->getValueType(LI->getType())) &&
+      !TLI->isTruncateFree(I->getType(), LI->getType()))
     return false;
 
   // Check whether the target supports casts folded into loads.



From sabre at nondot.org  Tue Sep 21 17:00:25 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 22:00:25 -0000
Subject: [llvm-commits] [llvm] r114489 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGISel.h
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 utils/TableGen/DAGISelMatcherEmitter.cpp
Message-ID: <20100921220025.79B1D2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 17:00:25 2010
New Revision: 114489

URL: http://llvm.org/viewvc/llvm-project?rev=114489&view=rev
Log:
Rework passing parent pointers into complexpatterns, I forgot
that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=114489&r1=114488&r2=114489&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Tue Sep 21 17:00:25 2010
@@ -256,7 +256,7 @@
   
   virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
                                    unsigned PatternNo,
-                                   SmallVectorImpl<SDValue> &Result) {
+                        SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
     assert(0 && "Tblgen should generate the implementation of this!");
     return false;
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=114489&r1=114488&r2=114489&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Sep 21 17:00:25 2010
@@ -1688,11 +1688,12 @@
 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
 ALWAYS_INLINE static bool
 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
-          SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
+          SDValue N,
+          const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
   // Accept if it is exactly the same as a previously recorded node.
   unsigned RecNo = MatcherTable[MatcherIndex++];
   assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
-  return N == RecordedNodes[RecNo];
+  return N == RecordedNodes[RecNo].first;
 }
   
 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
@@ -1801,7 +1802,7 @@
 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
                                        unsigned Index, SDValue N,
                                        bool &Result, SelectionDAGISel &SDISel,
-                                       SmallVectorImpl<SDValue> &RecordedNodes){
+                 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
   switch (Table[Index++]) {
   default:
     Result = false;
@@ -1924,8 +1925,9 @@
   SmallVector<MatchScope, 8> MatchScopes;
   
   // RecordedNodes - This is the set of nodes that have been recorded by the
-  // state machine.
-  SmallVector<SDValue, 8> RecordedNodes;
+  // state machine.  The second value is the parent of the node, or null if the
+  // root is recorded.
+  SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
   
   // MatchedMemRefs - This is the set of MemRef's we've seen in the input
   // pattern.
@@ -2051,10 +2053,14 @@
       MatchScopes.push_back(NewEntry);
       continue;
     }
-    case OPC_RecordNode:
+    case OPC_RecordNode: {
       // Remember this node, it may end up being an operand in the pattern.
-      RecordedNodes.push_back(N);
+      SDNode *Parent = 0;
+      if (NodeStack.size() > 1)
+        Parent = NodeStack[NodeStack.size()-2].getNode();
+      RecordedNodes.push_back(std::make_pair(N, Parent));
       continue;
+    }
         
     case OPC_RecordChild0: case OPC_RecordChild1:
     case OPC_RecordChild2: case OPC_RecordChild3:
@@ -2064,7 +2070,8 @@
       if (ChildNo >= N.getNumOperands())
         break;  // Match fails if out of range child #.
 
-      RecordedNodes.push_back(N->getOperand(ChildNo));
+      RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
+                                             N.getNode()));
       continue;
     }
     case OPC_RecordMemRef:
@@ -2109,11 +2116,8 @@
       unsigned CPNum = MatcherTable[MatcherIndex++];
       unsigned RecNo = MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
-      SDNode *Parent = 0;
-      if (!NodeStack.empty())
-        Parent = NodeStack[NodeStack.size()-1].getNode();
-      
-      if (!CheckComplexPattern(NodeToMatch, Parent, RecordedNodes[RecNo], CPNum,
+      if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
+                               RecordedNodes[RecNo].first, CPNum,
                                RecordedNodes))
         break;
       continue;
@@ -2242,14 +2246,16 @@
       int64_t Val = MatcherTable[MatcherIndex++];
       if (Val & 128)
         Val = GetVBR(Val, MatcherTable, MatcherIndex);
-      RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
+      RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
+                                      CurDAG->getTargetConstant(Val, VT), 0));
       continue;
     }
     case OPC_EmitRegister: {
       MVT::SimpleValueType VT =
         (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
       unsigned RegNo = MatcherTable[MatcherIndex++];
-      RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
+      RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
+                                      CurDAG->getRegister(RegNo, VT), 0));
       continue;
     }
         
@@ -2257,7 +2263,7 @@
       // Convert from IMM/FPIMM to target version.
       unsigned RecNo = MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
-      SDValue Imm = RecordedNodes[RecNo];
+      SDValue Imm = RecordedNodes[RecNo].first;
 
       if (Imm->getOpcode() == ISD::Constant) {
         int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
@@ -2267,7 +2273,7 @@
         Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
       }
       
-      RecordedNodes.push_back(Imm);
+      RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
       continue;
     }
         
@@ -2282,12 +2288,12 @@
       // Read all of the chained nodes.
       unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
       assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
-      ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
+      ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
         
       // FIXME: What if other value results of the node have uses not matched
       // by this pattern?
       if (ChainNodesMatched.back() != NodeToMatch &&
-          !RecordedNodes[RecNo].hasOneUse()) {
+          !RecordedNodes[RecNo].first.hasOneUse()) {
         ChainNodesMatched.clear();
         break;
       }
@@ -2319,12 +2325,12 @@
       for (unsigned i = 0; i != NumChains; ++i) {
         unsigned RecNo = MatcherTable[MatcherIndex++];
         assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
-        ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
+        ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
         
         // FIXME: What if other value results of the node have uses not matched
         // by this pattern?
         if (ChainNodesMatched.back() != NodeToMatch &&
-            !RecordedNodes[RecNo].hasOneUse()) {
+            !RecordedNodes[RecNo].first.hasOneUse()) {
           ChainNodesMatched.clear();
           break;
         }
@@ -2352,7 +2358,7 @@
         InputChain = CurDAG->getEntryNode();
       
       InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
-                                        DestPhysReg, RecordedNodes[RecNo],
+                                        DestPhysReg, RecordedNodes[RecNo].first,
                                         InputFlag);
       
       InputFlag = InputChain.getValue(1);
@@ -2363,7 +2369,8 @@
       unsigned XFormNo = MatcherTable[MatcherIndex++];
       unsigned RecNo = MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
-      RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
+      SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
+      RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, 0));
       continue;
     }
         
@@ -2406,7 +2413,7 @@
           RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
         
         assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
-        Ops.push_back(RecordedNodes[RecNo]);
+        Ops.push_back(RecordedNodes[RecNo].first);
       }
       
       // If there are variadic operands to add, handle them now.
@@ -2443,7 +2450,8 @@
         // Add all the non-flag/non-chain results to the RecordedNodes list.
         for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
           if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
-          RecordedNodes.push_back(SDValue(Res, i));
+          RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
+                                                             0));
         }
         
       } else {
@@ -2499,7 +2507,7 @@
           RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
 
         assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
-        FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
+        FlagResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
       }
       continue;
     }
@@ -2516,7 +2524,7 @@
           ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
         
         assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
-        SDValue Res = RecordedNodes[ResSlot];
+        SDValue Res = RecordedNodes[ResSlot].first;
         
         assert(i < NodeToMatch->getNumValues() &&
                NodeToMatch->getValueType(i) != MVT::Other &&

Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp?rev=114489&r1=114488&r2=114489&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Tue Sep 21 17:00:25 2010
@@ -634,7 +634,8 @@
   // FIXME: This should be const.
   if (!ComplexPatterns.empty()) {
     OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,\n";
-    OS << "      unsigned PatternNo, SmallVectorImpl<SDValue> &Result) {\n";
+    OS << "                         unsigned PatternNo,\n";
+    OS << "         SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {\n";
     OS << "  unsigned NextRes = Result.size();\n";
     OS << "  switch (PatternNo) {\n";
     OS << "  default: assert(0 && \"Invalid pattern # in table?\");\n";
@@ -662,7 +663,7 @@
       
       OS << "N";
       for (unsigned i = 0; i != NumOps; ++i)
-        OS << ", Result[NextRes+" << i << ']';
+        OS << ", Result[NextRes+" << i << "].first";
       OS << ");\n";
     }
     OS << "  }\n";



From John.Thompson.JTSoftware at gmail.com  Tue Sep 21 17:04:54 2010
From: John.Thompson.JTSoftware at gmail.com (John Thompson)
Date: Tue, 21 Sep 2010 22:04:54 -0000
Subject: [llvm-commits] [llvm] r114490 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <20100921220454.913392A6C124@llvm.org>

Author: jtsoftware
Date: Tue Sep 21 17:04:54 2010
New Revision: 114490

URL: http://llvm.org/viewvc/llvm-project?rev=114490&view=rev
Log:
Fixed pr20314-2.c failure, added E, F, p constraint letters.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=114490&r1=114489&r2=114490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Sep 21 17:04:54 2010
@@ -2496,7 +2496,10 @@
       return C_Memory;
     case 'i':    // Simple Integer or Relocatable Constant
     case 'n':    // Simple Integer
+    case 'E':    // Floating Point Constant
+    case 'F':    // Floating Point Constant
     case 's':    // Relocatable Constant
+    case 'p':    // Address.
     case 'X':    // Allow ANY value.
     case 'I':    // Target registers.
     case 'J':
@@ -2506,6 +2509,8 @@
     case 'N':
     case 'O':
     case 'P':
+    case '<':
+    case '>':
       return C_Other;
     }
   }
@@ -2664,6 +2669,7 @@
   /// ConstraintOperands - Information about all of the constraints.
   std::vector<AsmOperandInfo> ConstraintOperands;
   const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
+  unsigned maCount = 0; // Largest number of multiple alternative constraints.
 
   // Do a prepass over the constraints, canonicalizing them, and building up the
   // ConstraintOperands list.
@@ -2677,6 +2683,10 @@
     ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
     AsmOperandInfo &OpInfo = ConstraintOperands.back();
 
+    // Update multiple alternative constraint count.
+    if (OpInfo.multipleAlternatives.size() > maCount)
+      maCount = OpInfo.multipleAlternatives.size();
+
     EVT OpVT = MVT::Other;
 
     // Compute the value type for each operand.
@@ -2711,7 +2721,6 @@
 
   // If we have multiple alternative constraints, select the best alternative.
   if (ConstraintInfos.size()) {
-    unsigned maCount = ConstraintInfos[0].multipleAlternatives.size();
     if (maCount) {
       unsigned bestMAIndex = 0;
       int bestWeight = -1;
@@ -2727,8 +2736,6 @@
           AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
           if (OpInfo.Type == InlineAsm::isClobber)
             continue;
-          assert((OpInfo.multipleAlternatives.size() == maCount)
-            && "Constraint has inconsistent multiple alternative count.");
 
           // If this is an output operand with a matching input operand, look up the
           // matching input. If their types mismatch, e.g. one is an integer, the
@@ -2827,12 +2834,16 @@
 /// and the current alternative constraint selected.
 int TargetLowering::getMultipleConstraintMatchWeight(
     AsmOperandInfo &info, int maIndex) const {
-  std::vector<std::string> &rCodes = info.multipleAlternatives[maIndex].Codes;
+  std::vector<std::string> *rCodes;
+  if (maIndex >= (int)info.multipleAlternatives.size())
+    rCodes = &info.Codes;
+  else
+    rCodes = &info.multipleAlternatives[maIndex].Codes;
   int BestWeight = -1;
 
   // Loop over the options, keeping track of the most general one.
-  for (unsigned i = 0, e = rCodes.size(); i != e; ++i) {
-    int weight = getSingleConstraintMatchWeight(info, rCodes[i].c_str());
+  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
+    int weight = getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
     if (weight > BestWeight)
       BestWeight = weight;
   }



From sabre at nondot.org  Tue Sep 21 17:07:31 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 22:07:31 -0000
Subject: [llvm-commits] [llvm] r114491 - in /llvm/trunk/lib/Target/X86:
 X86ISelDAGToDAG.cpp X86Instr64bit.td X86InstrInfo.td
Message-ID: <20100921220731.C26E02A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 17:07:31 2010
New Revision: 114491

URL: http://llvm.org/viewvc/llvm-project?rev=114491&view=rev
Log:
reimplement support for GS and FS relative address space matching
by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.

This makes FS and GS relative accesses *far* more predictable and
work much better.  It also simplifies the X86 backend a bit, more
to come.

There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114491&r1=114490&r2=114491&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 17:07:31 2010
@@ -197,7 +197,7 @@
     bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
                                  unsigned Depth);
     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
-    bool SelectAddr(SDValue N, SDValue &Base,
+    bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
                     SDValue &Scale, SDValue &Index, SDValue &Disp,
                     SDValue &Segment);
     bool SelectLEAAddr(SDValue N, SDValue &Base,
@@ -1147,7 +1147,11 @@
 /// SelectAddr - returns true if it is able pattern match an addressing mode.
 /// It returns the operands which make up the maximal addressing mode it can
 /// match by reference.
-bool X86DAGToDAGISel::SelectAddr(SDValue N, SDValue &Base,
+///
+/// Parent is the parent node of the addr operand that is being matched.  It
+/// is always a load, store, atomic node, or null.  It is only null when
+/// checking memory operands for inline asm nodes.
+bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
                                  SDValue &Scale, SDValue &Index,
                                  SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
@@ -1163,6 +1167,31 @@
   if (!AM.IndexReg.getNode())
     AM.IndexReg = CurDAG->getRegister(0, VT);
 
+  if (Parent &&
+      // This list of opcodes are all the nodes that have an "addr:$ptr" operand
+      // that are not a MemSDNode, and thus don't have proper addrspace info.
+      Parent->getOpcode() != ISD::PREFETCH &&
+      Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
+      Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores.
+      Parent->getOpcode() != X86ISD::VZEXT_LOAD &&
+      Parent->getOpcode() != X86ISD::FLD &&
+      Parent->getOpcode() != X86ISD::FILD &&
+      Parent->getOpcode() != X86ISD::FILD_FLAG &&
+      Parent->getOpcode() != X86ISD::FP_TO_INT16_IN_MEM &&
+      Parent->getOpcode() != X86ISD::FP_TO_INT32_IN_MEM &&
+      Parent->getOpcode() != X86ISD::FP_TO_INT64_IN_MEM &&
+      Parent->getOpcode() != X86ISD::LCMPXCHG_DAG &&
+      Parent->getOpcode() != X86ISD::FST) {
+    unsigned AddrSpace =
+      cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
+    // AddrSpace 256 -> GS, 257 -> FS.
+    if (AddrSpace == 256)
+      AM.Segment = CurDAG->getRegister(X86::GS, VT);
+    if (AddrSpace == 257)
+      AM.Segment = CurDAG->getRegister(X86::FS, VT);
+  }
+  
+  
   getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
   return true;
 }
@@ -1186,7 +1215,7 @@
         IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
         IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
       LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
-      if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
+      if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
         return false;
       return true;
     }
@@ -1204,7 +1233,7 @@
       IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
     // Okay, this is a zero extending load.  Fold it.
     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
-    if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
+    if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
       return false;
     PatternNodeWithChain = SDValue(LD, 0);
     return true;
@@ -1310,7 +1339,8 @@
       !IsLegalToFold(N, P, P, OptLevel))
     return false;
   
-  return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp, Segment);
+  return SelectAddr(N.getNode(),
+                    N.getOperand(1), Base, Scale, Index, Disp, Segment);
 }
 
 /// getGlobalBaseReg - Return an SDNode that returns the value of
@@ -1328,7 +1358,7 @@
   SDValue In2L = Node->getOperand(2);
   SDValue In2H = Node->getOperand(3);
   SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-  if (!SelectAddr(In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
+  if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
     return NULL;
   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
   MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
@@ -1354,7 +1384,7 @@
   SDValue Ptr = Node->getOperand(1);
   SDValue Val = Node->getOperand(2);
   SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
-  if (!SelectAddr(Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
+  if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
     return 0;
 
   bool isInc = false, isDec = false, isSub = false, isCN = false;
@@ -1970,7 +2000,7 @@
   case 'v':   // not offsetable    ??
   default: return true;
   case 'm':   // memory
-    if (!SelectAddr(Op, Op0, Op1, Op2, Op3, Op4))
+    if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=114491&r1=114490&r2=114491&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Sep 21 17:07:31 2010
@@ -1611,16 +1611,6 @@
                   [(X86TLSCall addr:$sym)]>,
                   Requires<[In64BitMode]>;
 
-let AddedComplexity = 5, isCodeGenOnly = 1 in
-def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
-                 "movq\t%gs:$src, $dst",
-                 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
-
-let AddedComplexity = 5, isCodeGenOnly = 1 in
-def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
-                 "movq\t%fs:$src, $dst",
-                 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
-
 //===----------------------------------------------------------------------===//
 // Atomic Instructions
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114491&r1=114490&r2=114491&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 21 17:07:31 2010
@@ -337,7 +337,7 @@
 //
 
 // Define X86 specific addressing mode.
-def addr      : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
+def addr      : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
                                [add, sub, mul, X86mul_imm, shl, or, frameindex],
                                []>;
@@ -419,30 +419,11 @@
 def i16immSExt8  : PatLeaf<(i16 immSext8)>;
 def i32immSExt8  : PatLeaf<(i32 immSext8)>;
 
-/// Load patterns: these constraint the match to the right address space.
-def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  if (cast<LoadSDNode>(N)->getPointerInfo().getAddrSpace() > 255)
-    return false;
-  return true;
-}]>;
-
-def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  return cast<LoadSDNode>(N)->getPointerInfo().getAddrSpace() == 256;
-}]>;
-
-def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  return cast<LoadSDNode>(N)->getPointerInfo().getAddrSpace() == 257;
-}]>;
-
-
 // Helper fragments for loads.
 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
 // known to be 32-bit aligned or better. Ditto for i8 to i16.
 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
-  if (LD->getPointerInfo().getAddrSpace() > 255)
-    return false;
-
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
@@ -453,8 +434,6 @@
 
 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
   LoadSDNode *LD = cast<LoadSDNode>(N);
-  if (LD->getPointerInfo().getAddrSpace() > 255)
-    return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::EXTLOAD)
     return LD->getAlignment() >= 2 && !LD->isVolatile();
@@ -463,8 +442,6 @@
 
 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
   LoadSDNode *LD = cast<LoadSDNode>(N);
-  if (LD->getPointerInfo().getAddrSpace() > 255)
-    return false;
   ISD::LoadExtType ExtType = LD->getExtensionType();
   if (ExtType == ISD::NON_EXTLOAD)
     return true;
@@ -473,11 +450,11 @@
   return false;
 }]>;
 
-def loadi8  : PatFrag<(ops node:$ptr), (i8  (dsload node:$ptr))>;
-def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
-def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
-def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
-def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
+def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr))>;
+def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
+def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
+def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
+def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
 
 def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
 def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
@@ -3909,16 +3886,6 @@
                 [(X86TLSCall addr:$sym)]>,
                 Requires<[In32BitMode]>;
                 
-let AddedComplexity = 5, isCodeGenOnly = 1 in
-def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
-                   "movl\t%gs:$src, $dst",
-                   [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
-
-let AddedComplexity = 5, isCodeGenOnly = 1 in
-def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
-                   "movl\t%fs:$src, $dst",
-                   [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
-
 //===----------------------------------------------------------------------===//
 // EH Pseudo Instructions
 //



From espindola at google.com  Tue Sep 21 17:10:41 2010
From: espindola at google.com (Rafael Espindola)
Date: Tue, 21 Sep 2010 18:10:41 -0400
Subject: [llvm-commits] [patch][RFC] Correctly produce R_X86_64_32 or
	R_X86_64_32S
Message-ID: <AANLkTikmXne4afVBc_zohprP=1UWZEgJufrvCw-=n1-k@mail.gmail.com>

When processing
----------------------
movq    $foo, foo(%rip)
foo:
.long   foo
------------------------

llvm-mc should produce two relocations. This first one for movq should
be signed (R_X86_64_32S) as the cpu will sign extend the value. The
second one should be unsigned (R_X86_64_32) since that is used to
encode the eh_frame (when using DW_EH_PE_udata4).

I could not the necessary information in
ELFObjectWriterImpl::RecordRelocation. On IRC Daniel mentioned that it
might be necessary to record in the MCFixup if the relocation is
signed or not. Hopefully there is a simpler way to do this, but the
attached patch does produce the correct output for the above
test case.

If this is really the way to fix this, I will give this patch some
extra testing on OS X to update any missing code paths that can get
surprised by the new FixupKind.

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From gabor at mac.com  Tue Sep 21 17:27:25 2010
From: gabor at mac.com (Gabor Greif)
Date: Wed, 22 Sep 2010 00:27:25 +0200
Subject: [llvm-commits] Thumb2 and-tst peephole optimization
Message-ID: <18D0FB81-8383-4C2B-B848-2E26714E6A97@mac.com>

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Hi all,

I am entering deeper waters with this patch, so I'd better put it
up to review...

I managed to eliminate the 'tst.w' instruction after a thumb2 'and'
by converting the latter to 'andS'.

Unfortunately the transformation is all but straightforward:

the 'tst.t' feeds on a register that is also ARM::COPYed and ends
up as the register argument to the 'and'.
So we have look through those copies to find the 'and'.
I am unsure whether I have gotten the logic right, as I want
to avoid a wildly branching algorithm and so I look for the
'and' only immediately behind the COPY.

Any hint how to get this coded up elegantly and efficiently
is welcome. The patch is attached.

Cheers,

	Gabor


From stoklund at 2pi.dk  Tue Sep 21 17:32:21 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 21 Sep 2010 22:32:21 -0000
Subject: [llvm-commits] [llvm] r114492 - in /llvm/trunk/lib/CodeGen:
	SplitKit.cpp SplitKit.h
Message-ID: <20100921223221.B536F2A6C12C@llvm.org>

Author: stoklund
Date: Tue Sep 21 17:32:21 2010
New Revision: 114492

URL: http://llvm.org/viewvc/llvm-project?rev=114492&view=rev
Log:
Build the complement interval dupli after the split intervals instead of
creating it before and subtracting split ranges.

This way, the SSA update code in LiveIntervalMap can properly create and use new
phi values in dupli. Now it is possible to create split regions where a value
escapes along two different CFG edges, creating phi values outside the split
region.

This is a work in progress and probably quite broken.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=114492&r1=114491&r2=114492&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Sep 21 17:32:21 2010
@@ -351,6 +351,11 @@
   valueMap_.clear();
 }
 
+bool LiveIntervalMap::isComplexMapped(const VNInfo *ParentVNI) const {
+  ValueMap::const_iterator i = valueMap_.find(ParentVNI);
+  return i != valueMap_.end() && i->second == 0;
+}
+
 // defValue - Introduce a li_ def for ParentVNI that could be later than
 // ParentVNI->def.
 VNInfo *LiveIntervalMap::defValue(const VNInfo *ParentVNI, SlotIndex Idx) {
@@ -359,22 +364,25 @@
   assert(Idx.isValid() && "Invalid SlotIndex");
   assert(parentli_.getVNInfoAt(Idx) == ParentVNI && "Bad ParentVNI");
 
-  // Is this a simple 1-1 mapping? Not likely.
-  if (Idx == ParentVNI->def)
-    return mapValue(ParentVNI, Idx);
+  // Create a new value.
+  VNInfo *VNI = li_->getNextValue(Idx, 0, true, lis_.getVNInfoAllocator());
+
+  // Use insert for lookup, so we can add missing values with a second lookup.
+  std::pair<ValueMap::iterator,bool> InsP =
+    valueMap_.insert(makeVV(ParentVNI, Idx == ParentVNI->def ? VNI : 0));
 
   // This is now a complex def. Mark with a NULL in valueMap.
-  valueMap_[ParentVNI] = 0;
+  if (!InsP.second)
+    InsP.first->second = 0;
 
-  // Should we insert a minimal snippet of VNI LiveRange, or can we count on
-  // callers to do that? We need it for lookups of complex values.
-  VNInfo *VNI = li_->getNextValue(Idx, 0, true, lis_.getVNInfoAllocator());
   return VNI;
 }
 
+
 // mapValue - Find the mapped value for ParentVNI at Idx.
 // Potentially create phi-def values.
-VNInfo *LiveIntervalMap::mapValue(const VNInfo *ParentVNI, SlotIndex Idx) {
+VNInfo *LiveIntervalMap::mapValue(const VNInfo *ParentVNI, SlotIndex Idx,
+                                  bool *simple) {
   assert(li_ && "call reset first");
   assert(ParentVNI && "Mapping  NULL value");
   assert(Idx.isValid() && "Invalid SlotIndex");
@@ -385,15 +393,21 @@
     valueMap_.insert(makeVV(ParentVNI, 0));
 
   // This was an unknown value. Create a simple mapping.
-  if (InsP.second)
+  if (InsP.second) {
+    if (simple) *simple = true;
     return InsP.first->second = li_->createValueCopy(ParentVNI,
                                                      lis_.getVNInfoAllocator());
+  }
+
   // This was a simple mapped value.
-  if (InsP.first->second)
+  if (InsP.first->second) {
+    if (simple) *simple = true;
     return InsP.first->second;
+  }
 
   // This is a complex mapped value. There may be multiple defs, and we may need
   // to create phi-defs.
+  if (simple) *simple = false;
   MachineBasicBlock *IdxMBB = lis_.getMBBFromIndex(Idx);
   assert(IdxMBB && "No MBB at Idx");
 
@@ -519,9 +533,10 @@
 void LiveIntervalMap::addSimpleRange(SlotIndex Start, SlotIndex End,
                                      const VNInfo *ParentVNI) {
   assert(li_ && "call reset first");
-  VNInfo *VNI = mapValue(ParentVNI, Start);
-  // A simple mappoing is easy.
-  if (VNI->def == ParentVNI->def) {
+  bool simple;
+  VNInfo *VNI = mapValue(ParentVNI, Start, &simple);
+  // A simple mapping is easy.
+  if (simple) {
     li_->addRange(LiveRange(Start, End, VNI));
     return;
   }
@@ -619,15 +634,19 @@
   return &Intv;
 }
 
+bool SplitEditor::intervalsLiveAt(SlotIndex Idx) const {
+  for (int i = firstInterval, e = intervals_.size(); i != e; ++i)
+    if (intervals_[i]->liveAt(Idx))
+      return true;
+  return false;
+}
+
 /// Create a new virtual register and live interval.
 void SplitEditor::openIntv() {
   assert(!openli_.getLI() && "Previous LI not closed before openIntv");
 
-  if (!dupli_.getLI()) {
-    // Create an interval for dupli that is a copy of curli.
+  if (!dupli_.getLI())
     dupli_.reset(createInterval());
-    dupli_.getLI()->Copy(*curli_, &mri_, lis_.getVNInfoAllocator());
-  }
 
   openli_.reset(createInterval());
   intervals_.push_back(openli_.getLI());
@@ -642,6 +661,7 @@
     DEBUG(dbgs() << "    enterIntvBefore " << Idx << ": not live\n");
     return;
   }
+  truncatedValues.insert(ParentVNI);
   MachineInstr *MI = lis_.getInstructionFromIndex(Idx);
   assert(MI && "enterIntvBefore called with invalid index");
   openli_.defByCopyFrom(curli_->reg, ParentVNI, *MI->getParent(), MI);
@@ -658,6 +678,7 @@
     DEBUG(dbgs() << "    enterIntvAtEnd " << End << ": not live\n");
     return;
   }
+  truncatedValues.insert(ParentVNI);
   VNInfo *VNI = openli_.defByCopyFrom(curli_->reg, ParentVNI,
                                       MBB, MBB.getFirstTerminator());
   // Make sure openli is live out of MBB.
@@ -693,7 +714,7 @@
   assert(MI && "leaveIntvAfter called with invalid index");
 
   VNInfo *VNI = dupli_.defByCopyFrom(openli_.getLI()->reg, ParentVNI,
-                                  *MI->getParent(), MI);
+                                     *MI->getParent(), MI);
 
   // Finally we must make sure that openli is properly extended from Idx to the
   // new copy.
@@ -736,21 +757,93 @@
 
   DEBUG(dbgs() << "    closeIntv cleaning up\n");
   DEBUG(dbgs() << "    open " << *openli_.getLI() << '\n');
-
-  for (LiveInterval::iterator I = openli_.getLI()->begin(),
-       E = openli_.getLI()->end(); I != E; ++I) {
-    dupli_.getLI()->removeRange(I->start, I->end);
-  }
-  // FIXME: A block branching to the entry block may also branch elsewhere
-  // curli is live. We need both openli and curli to be live in that case.
-  DEBUG(dbgs() << "    dup2 " << *dupli_.getLI() << '\n');
   openli_.reset(0);
 }
 
+void
+SplitEditor::addTruncSimpleRange(SlotIndex Start, SlotIndex End, VNInfo *VNI) {
+  SlotIndex sidx = Start;
+
+  // Break [Start;End) into segments that don't overlap any intervals.
+  for (;;) {
+    SlotIndex next = sidx, eidx = End;
+    // Find overlapping intervals.
+    for (int i = firstInterval, e = intervals_.size(); i != e && sidx < eidx;
+         ++i) {
+      LiveInterval::const_iterator I = intervals_[i]->find(sidx);
+      LiveInterval::const_iterator E = intervals_[i]->end();
+      if (I == E)
+        continue;
+      // Interval I is overlapping [sidx;eidx). Trim sidx.
+      if (I->start <= sidx) {
+        sidx = I->end;
+        if (++I == E)
+          continue;
+      }
+      // Trim eidx too if needed.
+      if (I->start >= eidx)
+        continue;
+      eidx = I->start;
+      if (I->end > next)
+        next = I->end;
+    }
+    // Now, [sidx;eidx) doesn't overlap anything in intervals_.
+    if (sidx < eidx)
+      dupli_.addSimpleRange(sidx, eidx, VNI);
+    // If the interval end was truncated, we can try again from next.
+    if (next <= sidx)
+      break;
+    sidx = next;
+  }
+}
+
 /// rewrite - after all the new live ranges have been created, rewrite
 /// instructions using curli to use the new intervals.
 bool SplitEditor::rewrite() {
   assert(!openli_.getLI() && "Previous LI not closed before rewrite");
+
+  // First we need to fill in the live ranges in dupli.
+  // If values were redefined, we need a full recoloring with SSA update.
+  // If values were truncated, we only need to truncate the ranges.
+  // If values were partially rematted, we should shrink to uses.
+  // If values were fully rematted, they should be omitted.
+  // FIXME: If a single value is redefined, just move the def and truncate.
+
+  // Values that are fully contained in the split intervals.
+  SmallPtrSet<const VNInfo*, 8> deadValues;
+
+  // Map all curli values that should have live defs in dupli.
+  for (LiveInterval::const_vni_iterator I = curli_->vni_begin(),
+       E = curli_->vni_end(); I != E; ++I) {
+    const VNInfo *VNI = *I;
+    // Original def is contained in the split intervals.
+    if (intervalsLiveAt(VNI->def)) {
+      // Did this value escape?
+      if (dupli_.isMapped(VNI))
+        truncatedValues.insert(VNI);
+      else
+        deadValues.insert(VNI);
+      continue;
+    }
+    // Add minimal live range at the definition.
+    VNInfo *DVNI = dupli_.defValue(VNI, VNI->def);
+    dupli_.getLI()->addRange(LiveRange(VNI->def, VNI->def.getNextSlot(), DVNI));
+  }
+
+  // Add all ranges to dupli.
+  for (LiveInterval::const_iterator I = curli_->begin(), E = curli_->end();
+       I != E; ++I) {
+    const LiveRange &LR = *I;
+    if (truncatedValues.count(LR.valno)) {
+      // recolor after removing intervals_.
+      addTruncSimpleRange(LR.start, LR.end, LR.valno);
+    } else if (!deadValues.count(LR.valno)) {
+      // recolor without truncation.
+      dupli_.addSimpleRange(LR.start, LR.end, LR.valno);
+    }
+  }
+
+
   const LiveInterval *curli = sa_.getCurLI();
   for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(curli->reg),
        RE = mri_.reg_end(); RI != RE;) {

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=114492&r1=114491&r2=114492&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Sep 21 17:32:21 2010
@@ -166,10 +166,6 @@
   // Idx. Return the found VNInfo, or NULL.
   VNInfo *extendTo(MachineBasicBlock *MBB, SlotIndex Idx);
 
-  // addSimpleRange - Add a simple range from parentli_ to li_.
-  // ParentVNI must be live in the [Start;End) interval.
-  void addSimpleRange(SlotIndex Start, SlotIndex End, const VNInfo *ParentVNI);
-
 public:
   LiveIntervalMap(LiveIntervals &lis,
                   const LiveInterval &parentli)
@@ -194,7 +190,23 @@
   /// If ParentVNI has been defined by defValue one or more times, a value that
   /// dominates Idx will be returned. This may require creating extra phi-def
   /// values and adding live ranges to li_.
-  VNInfo *mapValue(const VNInfo *ParentVNI, SlotIndex Idx);
+  /// If simple is not NULL, *simple will indicate if ParentVNI is a simply
+  /// mapped value.
+  VNInfo *mapValue(const VNInfo *ParentVNI, SlotIndex Idx, bool *simple = 0);
+
+  /// isMapped - Return true is ParentVNI is a known mapped value. It may be a
+  /// simple 1-1 mapping or a complex mapping to later defs.
+  bool isMapped(const VNInfo *ParentVNI) const {
+    return valueMap_.count(ParentVNI);
+  }
+
+  /// isComplexMapped - Return true if ParentVNI has received new definitions
+  /// with defValue.
+  bool isComplexMapped(const VNInfo *ParentVNI) const;
+
+  // addSimpleRange - Add a simple range from parentli_ to li_.
+  // ParentVNI must be live in the [Start;End) interval.
+  void addSimpleRange(SlotIndex Start, SlotIndex End, const VNInfo *ParentVNI);
 
   /// addRange - Add live ranges to li_ where [Start;End) intersects parentli_.
   /// All needed values whose def is not inside [Start;End) must be defined
@@ -251,11 +263,16 @@
   /// others from before we got it.
   unsigned firstInterval;
 
-  /// Insert a COPY instruction curli -> li. Allocate a new value from li
-  /// defined by the COPY
-  VNInfo *insertCopy(LiveIntervalMap &LI,
-                     MachineBasicBlock &MBB,
-                     MachineBasicBlock::iterator I);
+  /// intervalsLiveAt - Return true if any member of intervals_ is live at Idx.
+  bool intervalsLiveAt(SlotIndex Idx) const;
+
+  /// Values in curli whose live range has been truncated when entering an open
+  /// li.
+  SmallPtrSet<const VNInfo*, 8> truncatedValues;
+
+  /// addTruncSimpleRange - Add the given simple range to dupli_ after
+  /// truncating any overlap with intervals_.
+  void addTruncSimpleRange(SlotIndex Start, SlotIndex End, VNInfo *VNI);
 
 public:
   /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.



From resistor at mac.com  Tue Sep 21 17:51:46 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 21 Sep 2010 22:51:46 -0000
Subject: [llvm-commits] [llvm] r114494 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/Thumb2/thumb2-badreg-operands.ll test/CodeGen/thumb2-mul.ll
Message-ID: <20100921225146.7E17B2A6C12C@llvm.org>

Author: resistor
Date: Tue Sep 21 17:51:46 2010
New Revision: 114494

URL: http://llvm.org/viewvc/llvm-project?rev=114494&view=rev
Log:
Enable target-specific mul-lowering on ARM, even at -Os.  Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.

Added:
    llvm/trunk/test/CodeGen/thumb2-mul.ll
Removed:
    llvm/trunk/test/CodeGen/Thumb2/thumb2-badreg-operands.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114494&r1=114493&r2=114494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep 21 17:51:46 2010
@@ -4194,10 +4194,6 @@
   if (Subtarget->isThumb1Only())
     return SDValue();
 
-  if (DAG.getMachineFunction().
-      getFunction()->hasFnAttr(Attribute::OptimizeForSize))
-    return SDValue();
-
   if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
     return SDValue();
 

Removed: llvm/trunk/test/CodeGen/Thumb2/thumb2-badreg-operands.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-badreg-operands.ll?rev=114493&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-badreg-operands.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-badreg-operands.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
-
-define void @b(i32 %x) nounwind optsize {
-entry:
-; CHECK: b
-; CHECK: mov r2, sp
-; CHECK: mls r0, r0, r1, r2
-; CHECK: mov sp, r0
-  %0 = mul i32 %x, 24                             ; <i32> [#uses=1]
-  %vla = alloca i8, i32 %0, align 1               ; <i8*> [#uses=1]
-  call arm_aapcscc  void @a(i8* %vla) nounwind optsize
-  ret void
-}
-
-declare void @a(i8*) optsize

Added: llvm/trunk/test/CodeGen/thumb2-mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/thumb2-mul.ll?rev=114494&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/thumb2-mul.ll (added)
+++ llvm/trunk/test/CodeGen/thumb2-mul.ll Tue Sep 21 17:51:46 2010
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
+
+%struct.CMPoint = type { %struct.Point, float, float, [5 x float] }
+%struct.Point = type { float, float }
+
+define %struct.CMPoint* @t1(i32 %i, i32 %j, i32 %n, %struct.CMPoint* %thePoints) nounwind readnone ssp {
+entry:
+; CHECK: mla     r0, r2, r0, r1
+; CHECK: add.w   r0, r0, r0, lsl #3
+; CHECL: add.w   r0, r3, r0, lsl #2
+  %mul = mul i32 %n, %i
+  %add = add i32 %mul, %j
+  %0 = ptrtoint %struct.CMPoint* %thePoints to i32
+  %mul5 = mul i32 %add, 36
+  %add6 = add i32 %mul5, %0
+  %1 = inttoptr i32 %add6 to %struct.CMPoint*
+  ret %struct.CMPoint* %1
+}



From grosbach at apple.com  Tue Sep 21 18:28:16 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 21 Sep 2010 23:28:16 -0000
Subject: [llvm-commits] [llvm] r114500 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.h
Message-ID: <20100921232816.665ED2A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep 21 18:28:16 2010
New Revision: 114500

URL: http://llvm.org/viewvc/llvm-project?rev=114500&view=rev
Log:
Add start of support for MC instruction printer of ARM jump tables. Filling in
the rest of it is next up.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114500&r1=114499&r2=114500&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Sep 21 18:28:16 2010
@@ -91,6 +91,8 @@
       return "ARM Assembly Printer";
     }
 
+    void EmitJumpTable(const MachineInstr *MI);
+    void EmitJump2Table(const MachineInstr *MI);
     void printInstructionThroughMCStreamer(const MachineInstr *MI);
 
 
@@ -1383,6 +1385,59 @@
   return Label;
 }
 
+void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
+  unsigned Opcode = MI->getOpcode();
+  int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
+  const MachineOperand &MO1 = MI->getOperand(OpNum);
+  const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
+  unsigned JTI = MO1.getIndex();
+
+  // Emit a label for the jump table.
+  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
+  OutStreamer.EmitLabel(JTISymbol);
+
+  // Emit each entry of the table.
+  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
+  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
+  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
+  bool ByteOffset = false, HalfWordOffset = false;
+  if (MI->getOpcode() == ARM::t2TBB)
+    ByteOffset = true;
+  else if (MI->getOpcode() == ARM::t2TBH)
+    HalfWordOffset = true;
+
+  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
+    MachineBasicBlock *MBB = JTBBs[i];
+    // If this isn't a TBB or TBH, the entries are direct branch instructions.
+    if (!ByteOffset && !HalfWordOffset) {
+      MCInst BrInst;
+      BrInst.setOpcode(ARM::t2B);
+      BrInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+            MBB->getSymbol(), OutContext)));
+      OutStreamer.EmitInstruction(BrInst);
+      continue;
+    }
+    // Otherwise it's an offset from the dispatch instruction. Construct an
+    // MCExpr for the entry.
+    assert(0 && "FIXME: TB[BH] jump table!!");
+
+#if 0
+    if (ByteOffset)
+      O << MAI->getData8bitsDirective();
+    else if (HalfWordOffset)
+      O << MAI->getData16bitsDirective();
+
+    if (ByteOffset || HalfWordOffset)
+      O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
+    else
+      O << "\tb.w " << *MBB->getSymbol();
+
+    if (i != e-1)
+      O << '\n';
+#endif
+  }
+}
+
 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
   ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
   switch (MI->getOpcode()) {
@@ -1592,6 +1647,23 @@
 
     return;
   }
+  case ARM::t2TBB:
+  case ARM::t2TBH:
+  case ARM::t2BR_JT: {
+    // Lower and emit the instruction itself, then the jump table following it.
+    MCInst TmpInst;
+    MCInstLowering.Lower(MI, TmpInst);
+    OutStreamer.EmitInstruction(TmpInst);
+
+    EmitJump2Table(MI);
+    return;
+  }
+  case ARM::tBR_JTr:
+  case ARM::BR_JTr:
+  case ARM::BR_JTm:
+  case ARM::BR_JTadd:
+    abort();
+    break;
   }
 
   MCInst TmpInst;

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=114500&r1=114499&r2=114500&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Tue Sep 21 18:28:16 2010
@@ -99,6 +99,8 @@
   void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printCPInstOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O,
                           const char *Modifier);
+  // The jump table instructions have custom handling in ARMAsmPrinter
+  // to output the jump table. Nothing further is necessary here.
   void printJTBlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {}
   void printJT2BlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {}
   void printTBAddrMode(const MCInst *MI, unsigned OpNum, raw_ostream &O);



From daniel at zuster.org  Tue Sep 21 18:42:49 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 21 Sep 2010 23:42:49 -0000
Subject: [llvm-commits] [compiler-rt] r114504 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20100921234249.93FFA2A6C12C@llvm.org>

Author: ddunbar
Date: Tue Sep 21 18:42:49 2010
New Revision: 114504

URL: http://llvm.org/viewvc/llvm-project?rev=114504&view=rev
Log:
compiler-rt/clang/Darwin: Add a new library configuration which has nothing
other than eprintf for i386.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=114504&r1=114503&r2=114504&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Tue Sep 21 18:42:49 2010
@@ -9,6 +9,12 @@
 Configs :=
 UniversalArchs :=
 
+# Configuration solely for providing access to an eprintf symbol, which may
+# still be referenced from Darwin system headers. This symbol is only ever
+# needed on i386.
+Configs += eprintf
+UniversalArchs.eprintf := i386
+
 # Configuration for targetting 10.4. We need a few functions missing from
 # libgcc_s.10.4.dylib. We only build x86 slices since clang doesn't really
 # support targetting PowerPC.
@@ -38,6 +44,7 @@
 
 CFLAGS := -Wall -Werror -O3 -fomit-frame-pointer
 
+FUNCTIONS.eprintf := eprintf
 FUNCTIONS.10.4 := eprintf floatundidf floatundisf floatundixf
 FUNCTIONS.armv6 := switch16 switch32 switch8 switchu8 \
                    save_vfp_d8_d15_regs restore_vfp_d8_d15_regs



From evan.cheng at apple.com  Tue Sep 21 18:49:08 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 21 Sep 2010 23:49:08 -0000
Subject: [llvm-commits] [llvm] r114506 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp
 test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
Message-ID: <20100921234908.2B6822A6C12C@llvm.org>

Author: evancheng
Date: Tue Sep 21 18:49:07 2010
New Revision: 114506

URL: http://llvm.org/viewvc/llvm-project?rev=114506&view=rev
Log:
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114506&r1=114505&r2=114506&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 21 18:49:07 2010
@@ -1455,7 +1455,8 @@
 
   // Check that CPSR isn't set between the comparison instruction and the one we
   // want to change.
-  MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+  MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+    B = MI->getParent()->begin();
   --I;
   for (; I != E; --I) {
     const MachineInstr &Instr = *I;
@@ -1469,6 +1470,10 @@
       if (MO.getReg() == ARM::CPSR)
         return false;
     }
+
+    if (I == B)
+      // The 'and' is below the comparison instruction.
+      return false;
   }
 
   // Set the "zero" bit in CPSR.

Added: llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll?rev=114506&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll Tue Sep 21 18:49:07 2010
@@ -0,0 +1,84 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
+
+declare noalias i8* @malloc(i32) nounwind
+
+define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, i8* %pixels) nounwind {
+entry:
+  br i1 undef, label %bb3.i, label %bb3
+
+bb3.i:                                            ; preds = %entry
+  unreachable
+
+gl_error.exit:                                    ; preds = %bb22
+  ret void
+
+bb3:                                              ; preds = %entry
+  br i1 false, label %bb5, label %bb4
+
+bb4:                                              ; preds = %bb3
+  br label %bb5
+
+bb5:                                              ; preds = %bb4, %bb3
+  br i1 undef, label %bb19, label %bb22
+
+bb19:                                             ; preds = %bb5
+  switch i32 %type, label %bb3.i6.i [
+    i32 5120, label %bb1.i13
+    i32 5121, label %bb1.i13
+    i32 6656, label %bb9.i.i6
+  ]
+
+bb9.i.i6:                                         ; preds = %bb19
+  br label %bb1.i13
+
+bb3.i6.i:                                         ; preds = %bb19
+  unreachable
+
+bb1.i13:                                          ; preds = %bb9.i.i6, %bb19, %bb19
+  br i1 undef, label %bb3.i17, label %bb2.i16
+
+bb2.i16:                                          ; preds = %bb1.i13
+  unreachable
+
+bb3.i17:                                          ; preds = %bb1.i13
+  br i1 undef, label %bb4.i18, label %bb23.i
+
+bb4.i18:                                          ; preds = %bb3.i17
+  %0 = mul nsw i32 %height, %width
+  %1 = and i32 %0, 7
+  %not..i = icmp ne i32 %1, 0
+  %2 = zext i1 %not..i to i32
+  %storemerge2.i = add i32 0, %2
+  %3 = call noalias i8* @malloc(i32 %storemerge2.i) nounwind
+  br i1 undef, label %bb3.i9, label %bb9.i
+
+bb9.i:                                            ; preds = %bb4.i18
+  br i1 undef, label %bb13.i19, label %bb.i24.i
+
+bb13.i19:                                         ; preds = %bb9.i
+  br i1 undef, label %bb14.i20, label %bb15.i
+
+bb14.i20:                                         ; preds = %bb13.i19
+  unreachable
+
+bb15.i:                                           ; preds = %bb13.i19
+  unreachable
+
+bb.i24.i:                                         ; preds = %bb.i24.i, %bb9.i
+  %storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ]
+  %4 = add i32 %storemerge1.i21.i, 1
+  %exitcond47.i = icmp eq i32 %4, %storemerge2.i
+  br i1 %exitcond47.i, label %bb22, label %bb.i24.i
+
+bb23.i:                                           ; preds = %bb3.i17
+  unreachable
+
+bb3.i9:                                           ; preds = %bb4.i18
+  unreachable
+
+bb22:                                             ; preds = %bb.i24.i, %bb5
+  br i1 undef, label %gl_error.exit, label %bb23
+
+bb23:                                             ; preds = %bb22
+  ret void
+}



From sabre at nondot.org  Tue Sep 21 18:57:27 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 23:57:27 -0000
Subject: [llvm-commits] [llvm] r114507 -
	/llvm/trunk/test/CodeGen/X86/atomic_op.ll
Message-ID: <20100921235727.EE4BE2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 18:57:27 2010
New Revision: 114507

URL: http://llvm.org/viewvc/llvm-project?rev=114507&view=rev
Log:
filecheckize

Modified:
    llvm/trunk/test/CodeGen/X86/atomic_op.ll

Modified: llvm/trunk/test/CodeGen/X86/atomic_op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_op.ll?rev=114507&r1=114506&r2=114507&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic_op.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic_op.ll Tue Sep 21 18:57:27 2010
@@ -1,16 +1,8 @@
-; RUN: llc < %s -march=x86 -o %t1
-; RUN: grep "lock" %t1 | count 17
-; RUN: grep "xaddl" %t1 | count 4 
-; RUN: grep "cmpxchgl"  %t1 | count 13 
-; RUN: grep "xchgl" %t1 | count 14
-; RUN: grep "cmova" %t1 | count 2
-; RUN: grep "cmovb" %t1 | count 2
-; RUN: grep "cmovg" %t1 | count 2
-; RUN: grep "cmovl" %t1 | count 2
+; RUN: llc < %s -march=x86 | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 
-define void @main(i32 %argc, i8** %argv) {
+define void @main(i32 %argc, i8** %argv) nounwind {
 entry:
 	%argc.addr = alloca i32		; <i32*> [#uses=1]
 	%argv.addr = alloca i8**		; <i8***> [#uses=1]
@@ -29,43 +21,89 @@
 	store i32 3855, i32* %ort
 	store i32 3855, i32* %xort
 	store i32 4, i32* %temp
-	%tmp = load i32* %temp		; <i32> [#uses=1]
+	%tmp = load i32* %temp
+        ; CHECK: lock
+        ; CHECK: xaddl
 	call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp )		; <i32>:0 [#uses=1]
 	store i32 %0, i32* %old
+        ; CHECK: lock
+        ; CHECK: xaddl
 	call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 )		; <i32>:1 [#uses=1]
 	store i32 %1, i32* %old
+        ; CHECK: lock
+        ; CHECK: xaddl
 	call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 )		; <i32>:2 [#uses=1]
 	store i32 %2, i32* %old
+        ; CHECK: lock
+        ; CHECK: xaddl
 	call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 )		; <i32>:3 [#uses=1]
 	store i32 %3, i32* %old
+        ; CHECK: andl
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 )		; <i32>:4 [#uses=1]
 	store i32 %4, i32* %old
+        ; CHECK: orl
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 )		; <i32>:5 [#uses=1]
 	store i32 %5, i32* %old
+        ; CHECK: xorl
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 )		; <i32>:6 [#uses=1]
 	store i32 %6, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 )		; <i32>:7 [#uses=1]
 	store i32 %7, i32* %old
 	%neg = sub i32 0, 1		; <i32> [#uses=1]
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg )		; <i32>:8 [#uses=1]
 	store i32 %8, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 )		; <i32>:9 [#uses=1]
 	store i32 %9, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 )		; <i32>:10 [#uses=1]
 	store i32 %10, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 65535 )		; <i32>:11 [#uses=1]
 	store i32 %11, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 10 )		; <i32>:12 [#uses=1]
 	store i32 %12, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 1 )		; <i32>:13 [#uses=1]
 	store i32 %13, i32* %old
+        ; CHECK: cmov
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 10 )		; <i32>:14 [#uses=1]
 	store i32 %14, i32* %old
+        ; CHECK: xchgl   %{{.*}}, {{.*}}(%esp)
 	call i32 @llvm.atomic.swap.i32.p0i32( i32* %val2, i32 1976 )		; <i32>:15 [#uses=1]
 	store i32 %15, i32* %old
 	%neg1 = sub i32 0, 10		; <i32> [#uses=1]
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 %neg1, i32 1 )		; <i32>:16 [#uses=1]
 	store i32 %16, i32* %old
+        ; CHECK: lock
+        ; CHECK: cmpxchgl
 	call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 1976, i32 1 )		; <i32>:17 [#uses=1]
 	store i32 %17, i32* %old
 	ret void



From sabre at nondot.org  Tue Sep 21 18:59:42 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 23:59:42 -0000
Subject: [llvm-commits] [llvm] r114508 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/atomic_op.ll
Message-ID: <20100921235943.20DB52A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 18:59:42 2010
New Revision: 114508

URL: http://llvm.org/viewvc/llvm-project?rev=114508&view=rev
Log:
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/test/CodeGen/X86/atomic_op.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114508&r1=114507&r2=114508&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 18:59:42 2010
@@ -1180,7 +1180,6 @@
       Parent->getOpcode() != X86ISD::FP_TO_INT16_IN_MEM &&
       Parent->getOpcode() != X86ISD::FP_TO_INT32_IN_MEM &&
       Parent->getOpcode() != X86ISD::FP_TO_INT64_IN_MEM &&
-      Parent->getOpcode() != X86ISD::LCMPXCHG_DAG &&
       Parent->getOpcode() != X86ISD::FST) {
     unsigned AddrSpace =
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114508&r1=114507&r2=114508&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 18:59:42 2010
@@ -8490,7 +8490,7 @@
 
 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
   EVT T = Op.getValueType();
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
   unsigned Reg = 0;
   unsigned size = 0;
   switch(T.getSimpleVT().SimpleTy) {
@@ -8504,7 +8504,7 @@
     Reg = X86::RAX; size = 8;
     break;
   }
-  SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
+  SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
                                     Op.getOperand(2), SDValue());
   SDValue Ops[] = { cpIn.getValue(0),
                     Op.getOperand(1),
@@ -8512,9 +8512,11 @@
                     DAG.getTargetConstant(size, MVT::i8),
                     cpIn.getValue(1) };
   SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
-  SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
+  MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
+  SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
+                                           Ops, 5, T, MMO);
   SDValue cpOut =
-    DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
+    DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
   return cpOut;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114508&r1=114507&r2=114508&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 18:59:42 2010
@@ -214,10 +214,6 @@
       ///   operand #3 optional in flag
       TC_RETURN,
 
-      // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
-      LCMPXCHG_DAG,
-      LCMPXCHG8_DAG,
-
       // FNSTCW16m - Store FP control world into i16 memory.
       FNSTCW16m,
 
@@ -309,7 +305,11 @@
       MEMBARRIER,
       MFENCE,
       SFENCE,
-      LFENCE
+      LFENCE,
+      
+      // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
+      LCMPXCHG_DAG,
+      LCMPXCHG8_DAG
 
       // WARNING: Do not add anything in the end unless you want the node to
       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be

Modified: llvm/trunk/test/CodeGen/X86/atomic_op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_op.ll?rev=114508&r1=114507&r2=114508&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic_op.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic_op.ll Tue Sep 21 18:59:42 2010
@@ -109,6 +109,17 @@
 	ret void
 }
 
+define void @test2(i32 addrspace(256)* nocapture %P) nounwind {
+entry:
+; CHECK: lock
+; CEHCK:	cmpxchgl	%{{.*}}, %gs:(%{{.*}})
+
+  %0 = tail call i32 @llvm.atomic.cmp.swap.i32.p256i32(i32 addrspace(256)* %P, i32 0, i32 1)
+  ret void
+}
+
+declare i32 @llvm.atomic.cmp.swap.i32.p256i32(i32 addrspace(256)* nocapture, i32, i32) nounwind
+
 declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind 
 
 declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind 



From sabre at nondot.org  Tue Sep 21 19:11:32 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 00:11:32 -0000
Subject: [llvm-commits] [llvm] r114510 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/movgs.ll
Message-ID: <20100922001132.14A392A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 19:11:31 2010
New Revision: 114510

URL: http://llvm.org/viewvc/llvm-project?rev=114510&view=rev
Log:
revert r114386 now that address modes work correctly, we get a nice
call through gs-relative memory now.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/movgs.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114510&r1=114509&r2=114510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 19:11:31 2010
@@ -403,10 +403,6 @@
       LD->getExtensionType() != ISD::NON_EXTLOAD)
     return false;
 
-  // FIXME: Calls can't fold loads through segment registers yet.
-  if (LD->getPointerInfo().getAddrSpace() > 255)
-    return false;
-  
   // Now let's find the callseq_start.
   while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
     if (!Chain.hasOneUse())

Modified: llvm/trunk/test/CodeGen/X86/movgs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movgs.ll?rev=114510&r1=114509&r2=114510&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movgs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movgs.ll Tue Sep 21 19:11:31 2010
@@ -26,10 +26,8 @@
 
 ; rdar://8453210
 ; X32: test2:
-; X32: movl	%gs:(%eax), %eax
-; X32: movl	%eax, (%esp)
-; X32: call	*%eax
+; X32: movl	16(%esp), %eax
+; X32: call	*%gs:(%eax)
 
 ; X64: test2:
-; X64: movq	%gs:(%rdi), %rax
-; X64: callq	*%rax
+; X64: callq	*%gs:(%rdi)



From espindola at google.com  Tue Sep 21 19:29:11 2010
From: espindola at google.com (Rafael Espindola)
Date: Tue, 21 Sep 2010 20:29:11 -0400
Subject: [llvm-commits] [patch][RFC] Correctly produce R_X86_64_32 or
	R_X86_64_32S
In-Reply-To: <AANLkTikmXne4afVBc_zohprP=1UWZEgJufrvCw-=n1-k@mail.gmail.com>
References: <AANLkTikmXne4afVBc_zohprP=1UWZEgJufrvCw-=n1-k@mail.gmail.com>
Message-ID: <AANLkTi=ABAVxcn7mdkQfiLLVHEveH237gtO_db2ArYdd@mail.gmail.com>

The attached patch survived a bit more testing :-)

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From sabre at nondot.org  Tue Sep 21 19:34:38 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 00:34:38 -0000
Subject: [llvm-commits] [llvm] r114515 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td
 lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/movgs.ll
 test/CodeGen/X86/widen_select-1.ll
Message-ID: <20100922003438.7F2622A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 19:34:38 2010
New Revision: 114515

URL: http://llvm.org/viewvc/llvm-project?rev=114515&view=rev
Log:
give VZEXT_LOAD a memory operand, it now works with segment registers.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/CodeGen/X86/movgs.ll
    llvm/trunk/test/CodeGen/X86/widen_select-1.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 19:34:38 2010
@@ -1169,7 +1169,6 @@
       Parent->getOpcode() != ISD::PREFETCH &&
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores.
-      Parent->getOpcode() != X86ISD::VZEXT_LOAD &&
       Parent->getOpcode() != X86ISD::FLD &&
       Parent->getOpcode() != X86ISD::FILD &&
       Parent->getOpcode() != X86ISD::FILD_FLAG &&

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 19:34:38 2010
@@ -4113,7 +4113,7 @@
 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
 /// There's even a handy isZeroNode for that purpose.
 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
-                                        DebugLoc &dl, SelectionDAG &DAG) {
+                                        DebugLoc &DL, SelectionDAG &DAG) {
   EVT EltVT = VT.getVectorElementType();
   unsigned NumElems = Elts.size();
   
@@ -4150,18 +4150,20 @@
   // consecutive loads for the low half, generate a vzext_load node.
   if (LastLoadedElt == NumElems - 1) {
     if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
-      return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
+      return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
                          LDBase->getPointerInfo(),
                          LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
-    return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
+    return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
                        LDBase->getPointerInfo(),
                        LDBase->isVolatile(), LDBase->isNonTemporal(),
                        LDBase->getAlignment());
   } else if (NumElems == 4 && LastLoadedElt == 1) {
     SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
     SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
-    SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
-    return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
+    SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
+                                              Ops, 2, MVT::i32,
+                                              LDBase->getMemOperand());
+    return DAG.getNode(ISD::BIT_CONVERT, DL, VT, ResNode);
   }
   return SDValue();
 }

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 19:34:38 2010
@@ -220,9 +220,6 @@
       // VZEXT_MOVL - Vector move low and zero extend.
       VZEXT_MOVL,
 
-      // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
-      VZEXT_LOAD,
-
       // VSHL, VSRL - Vector logical left / right shift.
       VSHL, VSRL,
 
@@ -309,8 +306,11 @@
       
       // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
       LCMPXCHG_DAG,
-      LCMPXCHG8_DAG
+      LCMPXCHG8_DAG,
 
+      // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
+      VZEXT_LOAD
+      
       // WARNING: Do not add anything in the end unless you want the node to
       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
       // thought as target memory ops!

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Sep 21 19:34:38 2010
@@ -102,7 +102,7 @@
 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
-                        [SDNPHasChain, SDNPMayLoad]>;
+                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def X86vshl    : SDNode<"X86ISD::VSHL",      SDTIntShiftOp>;
 def X86vshr    : SDNode<"X86ISD::VSRL",      SDTIntShiftOp>;
 def X86cmpps   : SDNode<"X86ISD::CMPPS",     SDTX86VFCMP>;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 21 19:34:38 2010
@@ -111,10 +111,10 @@
 
 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
                         [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
-                         SDNPMayLoad]>;
+                         SDNPMayLoad, SDNPMemOperand]>;
 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
                         [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
-                         SDNPMayLoad]>;
+                         SDNPMayLoad, SDNPMemOperand]>;
 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
                         [SDNPHasChain, SDNPMayStore, 
                          SDNPMayLoad, SDNPMemOperand]>;

Modified: llvm/trunk/test/CodeGen/X86/movgs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movgs.ll?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movgs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movgs.ll Tue Sep 21 19:34:38 2010
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s --check-prefix=X64
 
 define i32 @test1() nounwind readonly {
 entry:
@@ -31,3 +31,27 @@
 
 ; X64: test2:
 ; X64: callq	*%gs:(%rdi)
+
+
+
+
+define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly {
+entry:
+  %0 = load i64 addrspace(256)* %p
+  %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0
+  %1 = bitcast <2 x i64> %tmp2 to <8 x i16>
+  %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
+  %3 = bitcast <4 x i32> %2 to <2 x i64>
+  ret <2 x i64> %3
+  
+; X32: pmovsxwd_1:
+; X32: 	movl	4(%esp), %eax
+; X32: 	pmovsxwd	%gs:(%eax), %xmm0
+; X32: 	ret
+
+; X64: pmovsxwd_1:
+; X64:	pmovsxwd	%gs:(%rdi), %xmm0
+; X64:	ret
+}
+
+declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone

Modified: llvm/trunk/test/CodeGen/X86/widen_select-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_select-1.ll?rev=114515&r1=114514&r2=114515&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_select-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_select-1.ll Tue Sep 21 19:34:38 2010
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
-; CHECK: jne
+; CHECK: je
 
 ; widening select v6i32 and then a sub
 



From sabre at nondot.org  Tue Sep 21 19:46:27 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 00:46:27 -0000
Subject: [llvm-commits] [llvm] r114519 -
	/llvm/trunk/test/CodeGen/X86/movgs.ll
Message-ID: <20100922004627.1E1992A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 19:46:26 2010
New Revision: 114519

URL: http://llvm.org/viewvc/llvm-project?rev=114519&view=rev
Log:
linux has a different stack alignment than the mac, relax this a bit.

Modified:
    llvm/trunk/test/CodeGen/X86/movgs.ll

Modified: llvm/trunk/test/CodeGen/X86/movgs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movgs.ll?rev=114519&r1=114518&r2=114519&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movgs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movgs.ll Tue Sep 21 19:46:26 2010
@@ -26,7 +26,7 @@
 
 ; rdar://8453210
 ; X32: test2:
-; X32: movl	16(%esp), %eax
+; X32: movl	{{.*}}(%esp), %eax
 ; X32: call	*%gs:(%eax)
 
 ; X64: test2:



From isanbard at gmail.com  Tue Sep 21 19:47:28 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 22 Sep 2010 00:47:28 -0000
Subject: [llvm-commits] [www] r114520 - /www/trunk/index.html
Message-ID: <20100922004728.223B82A6C12C@llvm.org>

Author: void
Date: Tue Sep 21 19:47:27 2010
New Revision: 114520

URL: http://llvm.org/viewvc/llvm-project?rev=114520&view=rev
Log:
Update the release schedule.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=114520&r1=114519&r2=114520&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Tue Sep 21 19:47:27 2010
@@ -133,10 +133,10 @@
 <p>The LLVM 2.8 release schedule has been announced:</p>
 
 <ul>
-<li><b>9/3&mdash; Branching</b></li>
-<li>9/6 &mdash; Pre-release 1 testing begins</li>
+<li>9/3&nbsp;&nbsp;&mdash; Branching</li>
+<li>9/6&nbsp;&nbsp;&mdash; Pre-release 1 testing begins</li>
 <li>9/12 &mdash; Pre-release 1 testing ends</li>
-<li>9/20 &mdash; Pre-release 2 testing begins</li>
+<li><b>9/20 &mdash; Pre-release 2 testing begins</b></li>
 <li>9/26 &mdash; Pre-release 2 testing ends</li>
 <li>9/29 &mdash; Release!</li>
 </ul>



From sabre at nondot.org  Tue Sep 21 20:05:16 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 01:05:16 -0000
Subject: [llvm-commits] [llvm] r114521 - in /llvm/trunk/lib/Target/X86:
 X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h
 X86InstrFPStack.td
Message-ID: <20100922010516.922EE2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 20:05:16 2010
New Revision: 114521

URL: http://llvm.org/viewvc/llvm-project?rev=114521&view=rev
Log:
give FP_TO_INT16_IN_MEM and friends a memoperand.  They are only
used with stack slots, but hey, lets be safe.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFPStack.td

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114521&r1=114520&r2=114521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 20:05:16 2010
@@ -1169,12 +1169,10 @@
       Parent->getOpcode() != ISD::PREFETCH &&
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores.
+      Parent->getOpcode() != X86ISD::FNSTCW16m &&
       Parent->getOpcode() != X86ISD::FLD &&
       Parent->getOpcode() != X86ISD::FILD &&
       Parent->getOpcode() != X86ISD::FILD_FLAG &&
-      Parent->getOpcode() != X86ISD::FP_TO_INT16_IN_MEM &&
-      Parent->getOpcode() != X86ISD::FP_TO_INT32_IN_MEM &&
-      Parent->getOpcode() != X86ISD::FP_TO_INT64_IN_MEM &&
       Parent->getOpcode() != X86ISD::FST) {
     unsigned AddrSpace =
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114521&r1=114520&r2=114521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 20:05:16 2010
@@ -6599,7 +6599,7 @@
 
 std::pair<SDValue,SDValue> X86TargetLowering::
 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
 
   EVT DstTy = Op.getValueType();
 
@@ -6628,6 +6628,8 @@
   int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
   SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
 
+  
+  
   unsigned Opc;
   switch (DstTy.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
@@ -6640,22 +6642,27 @@
   SDValue Value = Op.getOperand(0);
   if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
     assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
-    Chain = DAG.getStore(Chain, dl, Value, StackSlot,
+    Chain = DAG.getStore(Chain, DL, Value, StackSlot,
                          MachinePointerInfo::getFixedStack(SSFI),
                          false, false, 0);
     SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
     SDValue Ops[] = {
       Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
     };
-    Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
+    Value = DAG.getNode(X86ISD::FLD, DL, Tys, Ops, 3);
     Chain = Value.getValue(1);
     SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
     StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
   }
+  
+  MachineMemOperand *MMO =
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
+                            MachineMemOperand::MOStore, MemSize, MemSize);
 
   // Build the FP_TO_INT*_IN_MEM
   SDValue Ops[] = { Chain, Value, StackSlot };
-  SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
+  SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
+                                         Ops, 3, DstTy, MMO);
 
   return std::make_pair(FIST, StackSlot);
 }

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114521&r1=114520&r2=114521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 20:05:16 2010
@@ -64,16 +64,7 @@
       /// also produces a flag).
       FILD,
       FILD_FLAG,
-
-      /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
-      /// integer destination in memory and a FP reg source.  This corresponds
-      /// to the X86::FIST*m instructions and the rounding mode change stuff. It
-      /// has two inputs (token chain and address) and two outputs (int value
-      /// and token chain).
-      FP_TO_INT16_IN_MEM,
-      FP_TO_INT32_IN_MEM,
-      FP_TO_INT64_IN_MEM,
-
+      
       /// FLD - This instruction implements an extending load to FP stack slots.
       /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
       /// operand, ptr to load from, and a ValueType node indicating the type
@@ -309,7 +300,17 @@
       LCMPXCHG8_DAG,
 
       // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
-      VZEXT_LOAD
+      VZEXT_LOAD,
+      
+      
+      /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
+      /// integer destination in memory and a FP reg source.  This corresponds
+      /// to the X86::FIST*m instructions and the rounding mode change stuff. It
+      /// has two inputs (token chain and address) and two outputs (int value
+      /// and token chain).
+      FP_TO_INT16_IN_MEM,
+      FP_TO_INT32_IN_MEM,
+      FP_TO_INT64_IN_MEM
       
       // WARNING: Do not add anything in the end unless you want the node to
       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be

Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=114521&r1=114520&r2=114521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Sep 21 20:05:16 2010
@@ -40,13 +40,14 @@
 def X86fildflag     : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
                              [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
-                             [SDNPHasChain, SDNPMayStore]>;
+                             [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
-                             [SDNPHasChain, SDNPMayStore]>;
+                             [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
-                             [SDNPHasChain, SDNPMayStore]>;
+                             [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m",          SDTX86CwdStore,
-                             [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
+                             [SDNPHasChain, SDNPMayStore, SDNPSideEffect,
+                              SDNPMemOperand]>;
 
 //===----------------------------------------------------------------------===//
 // FPStack pattern fragments



From sabre at nondot.org  Tue Sep 21 20:11:26 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 01:11:26 -0000
Subject: [llvm-commits] [llvm] r114522 - in /llvm/trunk/lib/Target/X86:
 X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h
Message-ID: <20100922011126.DCA2A2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 20:11:26 2010
New Revision: 114522

URL: http://llvm.org/viewvc/llvm-project?rev=114522&view=rev
Log:
give X86ISD::FNSTCW16m a memoperand, since it touches memory.  It only
can access the stack due to how it is generated though.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114522&r1=114521&r2=114522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 20:11:26 2010
@@ -1169,7 +1169,6 @@
       Parent->getOpcode() != ISD::PREFETCH &&
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores.
-      Parent->getOpcode() != X86ISD::FNSTCW16m &&
       Parent->getOpcode() != X86ISD::FLD &&
       Parent->getOpcode() != X86ISD::FILD &&
       Parent->getOpcode() != X86ISD::FILD_FLAG &&

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114522&r1=114521&r2=114522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 20:11:26 2010
@@ -8158,41 +8158,48 @@
   const TargetFrameInfo &TFI = *TM.getFrameInfo();
   unsigned StackAlignment = TFI.getStackAlignment();
   EVT VT = Op.getValueType();
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
 
   // Save FP Control Word to stack slot
   int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
   SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
 
-  SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
-                              DAG.getEntryNode(), StackSlot);
+  
+  MachineMemOperand *MMO =
+   MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
+                           MachineMemOperand::MOStore, 2, 2);
+  
+  SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
+  SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
+                                          DAG.getVTList(MVT::Other),
+                                          Ops, 2, MVT::i16, MMO);
 
   // Load FP Control Word from stack slot
-  SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot,
+  SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
                             MachinePointerInfo(), false, false, 0);
 
   // Transform as necessary
   SDValue CWD1 =
-    DAG.getNode(ISD::SRL, dl, MVT::i16,
-                DAG.getNode(ISD::AND, dl, MVT::i16,
+    DAG.getNode(ISD::SRL, DL, MVT::i16,
+                DAG.getNode(ISD::AND, DL, MVT::i16,
                             CWD, DAG.getConstant(0x800, MVT::i16)),
                 DAG.getConstant(11, MVT::i8));
   SDValue CWD2 =
-    DAG.getNode(ISD::SRL, dl, MVT::i16,
-                DAG.getNode(ISD::AND, dl, MVT::i16,
+    DAG.getNode(ISD::SRL, DL, MVT::i16,
+                DAG.getNode(ISD::AND, DL, MVT::i16,
                             CWD, DAG.getConstant(0x400, MVT::i16)),
                 DAG.getConstant(9, MVT::i8));
 
   SDValue RetVal =
-    DAG.getNode(ISD::AND, dl, MVT::i16,
-                DAG.getNode(ISD::ADD, dl, MVT::i16,
-                            DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
+    DAG.getNode(ISD::AND, DL, MVT::i16,
+                DAG.getNode(ISD::ADD, DL, MVT::i16,
+                            DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
                             DAG.getConstant(1, MVT::i16)),
                 DAG.getConstant(3, MVT::i16));
 
 
   return DAG.getNode((VT.getSizeInBits() < 16 ?
-                      ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
+                      ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
 }
 
 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114522&r1=114521&r2=114522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 20:11:26 2010
@@ -205,9 +205,6 @@
       ///   operand #3 optional in flag
       TC_RETURN,
 
-      // FNSTCW16m - Store FP control world into i16 memory.
-      FNSTCW16m,
-
       // VZEXT_MOVL - Vector move low and zero extend.
       VZEXT_MOVL,
 
@@ -302,6 +299,8 @@
       // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
       VZEXT_LOAD,
       
+      // FNSTCW16m - Store FP control world into i16 memory.
+      FNSTCW16m,
       
       /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
       /// integer destination in memory and a FP reg source.  This corresponds



From sabre at nondot.org  Tue Sep 21 20:28:21 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 01:28:21 -0000
Subject: [llvm-commits] [llvm] r114523 - in /llvm/trunk/lib/Target/X86:
 X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h
 X86InstrFPStack.td
Message-ID: <20100922012822.19AD62A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 20:28:21 2010
New Revision: 114523

URL: http://llvm.org/viewvc/llvm-project?rev=114523&view=rev
Log:
convert the last 4 X86ISD nodes that should have memoperands to have them.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFPStack.td

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114523&r1=114522&r2=114523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 20:28:21 2010
@@ -1168,11 +1168,7 @@
       // that are not a MemSDNode, and thus don't have proper addrspace info.
       Parent->getOpcode() != ISD::PREFETCH &&
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
-      Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores.
-      Parent->getOpcode() != X86ISD::FLD &&
-      Parent->getOpcode() != X86ISD::FILD &&
-      Parent->getOpcode() != X86ISD::FILD_FLAG &&
-      Parent->getOpcode() != X86ISD::FST) {
+      Parent->getOpcode() != ISD::INTRINSIC_VOID) { // nontemporal stores.
     unsigned AddrSpace =
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
     // AddrSpace 256 -> GS, 257 -> FS.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114523&r1=114522&r2=114523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 20:28:21 2010
@@ -6321,9 +6321,8 @@
   EVT SrcVT = Op.getOperand(0).getValueType();
 
   if (SrcVT.isVector()) {
-    if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
+    if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64)
       return Op;
-    }
     return SDValue();
   }
 
@@ -6355,16 +6354,27 @@
                                      SDValue StackSlot, 
                                      SelectionDAG &DAG) const {
   // Build the FILD
-  DebugLoc dl = Op.getDebugLoc();
+  DebugLoc DL = Op.getDebugLoc();
   SDVTList Tys;
   bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
   if (useSSE)
     Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
   else
     Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
+  
+  unsigned ByteSize = SrcVT.getSizeInBits()/8;
+  
+  int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
+  MachineMemOperand *MMO =
+    DAG.getMachineFunction()
+    .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
+                          MachineMemOperand::MOLoad, ByteSize, ByteSize);
+  
   SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
-  SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
-                               Tys, Ops, array_lengthof(Ops));
+  SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
+                                           X86ISD::FILD, DL,
+                                           Tys, Ops, array_lengthof(Ops),
+                                           SrcVT, MMO);
 
   if (useSSE) {
     Chain = Result.getValue(1);
@@ -6380,8 +6390,15 @@
     SDValue Ops[] = {
       Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
     };
-    Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
-    Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
+    MachineMemOperand *MMO =
+      DAG.getMachineFunction()
+      .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
+                            MachineMemOperand::MOStore, 8, 8);
+    
+    Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
+                                    Ops, array_lengthof(Ops),
+                                    Op.getValueType(), MMO);
+    Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
                          MachinePointerInfo::getFixedStack(SSFI),
                          false, false, 0);
   }
@@ -6564,9 +6581,16 @@
   // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
   // we must be careful to do the computation in x87 extended precision, not
   // in SSE. (The generic code can't know it's OK to do this, or how to.)
+  int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
+  MachineMemOperand *MMO =
+    DAG.getMachineFunction()
+    .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
+                          MachineMemOperand::MOLoad, 8, 8);
+  
   SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
   SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
-  SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
+  SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
+                                         MVT::i64, MMO);
 
   APInt FF(32, 0x5F800000ULL);
 
@@ -6640,16 +6664,22 @@
 
   SDValue Chain = DAG.getEntryNode();
   SDValue Value = Op.getOperand(0);
-  if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
+  EVT TheVT = Op.getOperand(0).getValueType();
+  if (isScalarFPTypeInSSEReg(TheVT)) {
     assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
     Chain = DAG.getStore(Chain, DL, Value, StackSlot,
                          MachinePointerInfo::getFixedStack(SSFI),
                          false, false, 0);
     SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
     SDValue Ops[] = {
-      Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
+      Chain, StackSlot, DAG.getValueType(TheVT)
     };
-    Value = DAG.getNode(X86ISD::FLD, DL, Tys, Ops, 3);
+    
+    MachineMemOperand *MMO =
+      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
+                              MachineMemOperand::MOLoad, MemSize, MemSize);
+    Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
+                                    DstTy, MMO);
     Chain = Value.getValue(1);
     SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
     StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114523&r1=114522&r2=114523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 20:28:21 2010
@@ -57,26 +57,6 @@
       /// corresponds to X86::PSRLDQ.
       FSRL,
 
-      /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
-      /// integer source in memory and FP reg result.  This corresponds to the
-      /// X86::FILD*m instructions. It has three inputs (token chain, address,
-      /// and source type) and two outputs (FP value and token chain). FILD_FLAG
-      /// also produces a flag).
-      FILD,
-      FILD_FLAG,
-      
-      /// FLD - This instruction implements an extending load to FP stack slots.
-      /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
-      /// operand, ptr to load from, and a ValueType node indicating the type
-      /// to load to.
-      FLD,
-
-      /// FST - This instruction implements a truncating store to FP stack
-      /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
-      /// chain operand, value to store, address, and a ValueType to store it
-      /// as.
-      FST,
-
       /// CALL - These operations represent an abstract X86 call
       /// instruction, which includes a bunch of information.  In particular the
       /// operands of these node are:
@@ -309,7 +289,27 @@
       /// and token chain).
       FP_TO_INT16_IN_MEM,
       FP_TO_INT32_IN_MEM,
-      FP_TO_INT64_IN_MEM
+      FP_TO_INT64_IN_MEM,
+      
+      /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
+      /// integer source in memory and FP reg result.  This corresponds to the
+      /// X86::FILD*m instructions. It has three inputs (token chain, address,
+      /// and source type) and two outputs (FP value and token chain). FILD_FLAG
+      /// also produces a flag).
+      FILD,
+      FILD_FLAG,
+      
+      /// FLD - This instruction implements an extending load to FP stack slots.
+      /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
+      /// operand, ptr to load from, and a ValueType node indicating the type
+      /// to load to.
+      FLD,
+      
+      /// FST - This instruction implements a truncating store to FP stack
+      /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
+      /// chain operand, value to store, address, and a ValueType to store it
+      /// as.
+      FST
       
       // WARNING: Do not add anything in the end unless you want the node to
       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be

Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=114523&r1=114522&r2=114523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Sep 21 20:28:21 2010
@@ -32,13 +32,15 @@
 def SDTX86CwdStore  : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
 
 def X86fld          : SDNode<"X86ISD::FLD", SDTX86Fld,
-                             [SDNPHasChain, SDNPMayLoad]>;
+                             [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def X86fst          : SDNode<"X86ISD::FST", SDTX86Fst,
-                             [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
+                             [SDNPHasChain, SDNPInFlag, SDNPMayStore,
+                              SDNPMemOperand]>;
 def X86fild         : SDNode<"X86ISD::FILD", SDTX86Fild,
-                             [SDNPHasChain, SDNPMayLoad]>;
+                             [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def X86fildflag     : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
-                             [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
+                             [SDNPHasChain, SDNPOutFlag, SDNPMayLoad,
+                              SDNPMemOperand]>;
 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
                              [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,



From aggarwa4 at illinois.edu  Tue Sep 21 21:03:09 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Sep 2010 02:03:09 -0000
Subject: [llvm-commits] [poolalloc] r114524 -
	/poolalloc/trunk/test/dsa/local/arrays4.c
Message-ID: <20100922020309.A2C122A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Sep 21 21:03:09 2010
New Revision: 114524

URL: http://llvm.org/viewvc/llvm-project?rev=114524&view=rev
Log:
Test case for array of structs

Added:
    poolalloc/trunk/test/dsa/local/arrays4.c

Added: poolalloc/trunk/test/dsa/local/arrays4.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrays4.c?rev=114524&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrays4.c (added)
+++ poolalloc/trunk/test/dsa/local/arrays4.c Tue Sep 21 21:03:09 2010
@@ -0,0 +1,26 @@
+//--Make sure we can run DSA on it! 
+//RUN: llvm-gcc %s -c --emit-llvm -o - |  \
+//RUN: dsaopt -dsa-bu -dsa-td -disable-output
+
+//H, S, G, R, M
+
+#include <stdlib.h>
+
+struct StructType {
+
+  int a;
+  int *b;
+};
+
+void func() {
+
+  struct StructType tmp[10];
+  int i;
+  for(i=0;i<10;i++) {
+    tmp[i].a = i;
+  }
+  
+  struct StructType s2 = tmp[0];
+  int * c = s2.b;
+}
+



From aggarwa4 at illinois.edu  Tue Sep 21 21:03:32 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Sep 2010 02:03:32 -0000
Subject: [llvm-commits] [poolalloc] r114525 -
	/poolalloc/trunk/test/dsa/local/arrays4.ll
Message-ID: <20100922020332.E878B2A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Sep 21 21:03:32 2010
New Revision: 114525

URL: http://llvm.org/viewvc/llvm-project?rev=114525&view=rev
Log:
Test case for array of structs

Added:
    poolalloc/trunk/test/dsa/local/arrays4.ll

Added: poolalloc/trunk/test/dsa/local/arrays4.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrays4.ll?rev=114525&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrays4.ll (added)
+++ poolalloc/trunk/test/dsa/local/arrays4.ll Tue Sep 21 21:03:32 2010
@@ -0,0 +1,55 @@
+
+;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:s2:8,func:c:0,func:tmp:8
+
+
+; ModuleID = 'arrays4.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.StructType = type { i32, i32* }
+
+define void @func() nounwind {
+entry:
+  %tmp = alloca [10 x %struct.StructType]         ; <[10 x %struct.StructType]*> [#uses=2]
+  %i = alloca i32                                 ; <i32*> [#uses=6]
+  %s2 = alloca %struct.StructType                 ; <%struct.StructType*> [#uses=3]
+  %c = alloca i32*                                ; <i32**> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 0, i32* %i, align 4
+  br label %bb1
+
+bb:                                               ; preds = %bb1
+  %0 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %1 = sext i32 %0 to i64                         ; <i64> [#uses=1]
+  %2 = getelementptr inbounds [10 x %struct.StructType]* %tmp, i64 0, i64 %1 ; <%struct.StructType*> [#uses=1]
+  %3 = getelementptr inbounds %struct.StructType* %2, i32 0, i32 0 ; <i32*> [#uses=1]
+  %4 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  store i32 %4, i32* %3, align 8
+  %5 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %6 = add nsw i32 %5, 1                          ; <i32> [#uses=1]
+  store i32 %6, i32* %i, align 4
+  br label %bb1
+
+bb1:                                              ; preds = %bb, %entry
+  %7 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %8 = icmp sle i32 %7, 9                         ; <i1> [#uses=1]
+  br i1 %8, label %bb, label %bb2
+
+bb2:                                              ; preds = %bb1
+  %9 = getelementptr inbounds [10 x %struct.StructType]* %tmp, i64 0, i64 0 ; <%struct.StructType*> [#uses=2]
+  %10 = getelementptr inbounds %struct.StructType* %s2, i32 0, i32 0 ; <i32*> [#uses=1]
+  %11 = getelementptr inbounds %struct.StructType* %9, i32 0, i32 0 ; <i32*> [#uses=1]
+  %12 = load i32* %11, align 8                    ; <i32> [#uses=1]
+  store i32 %12, i32* %10, align 8
+  %13 = getelementptr inbounds %struct.StructType* %s2, i32 0, i32 1 ; <i32**> [#uses=1]
+  %14 = getelementptr inbounds %struct.StructType* %9, i32 0, i32 1 ; <i32**> [#uses=1]
+  %15 = load i32** %14, align 8                   ; <i32*> [#uses=1]
+  store i32* %15, i32** %13, align 8
+  %16 = getelementptr inbounds %struct.StructType* %s2, i32 0, i32 1 ; <i32**> [#uses=1]
+  %17 = load i32** %16, align 8                   ; <i32*> [#uses=1]
+  store i32* %17, i32** %c, align 8
+  br label %return
+
+return:                                           ; preds = %bb2
+  ret void
+}



From sabre at nondot.org  Tue Sep 21 22:50:33 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 03:50:33 -0000
Subject: [llvm-commits] [llvm] r114526 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922035033.1735B2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 22:50:32 2010
New Revision: 114526

URL: http://llvm.org/viewvc/llvm-project?rev=114526&view=rev
Log:
fix rdar://8456361 - llvm-mc rejects 'rep movsd'

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114526&r1=114525&r2=114526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 21 22:50:32 2010
@@ -1009,6 +1009,12 @@
                                           NameLoc);
   }
   
+  // movsd -> movsl (when no operands are specified).
+  if (Name == "movsd" && Operands.size() == 1) {
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
+  }
+  
   return false;
 }
 

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114526&r1=114525&r2=114526&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 21 22:50:32 2010
@@ -83,6 +83,11 @@
 // CHECK: movsb
         rep;movsb
 
+// rdar://8456361
+// CHECK: rep
+// CHECK: movsl
+        rep movsd
+
 // CHECK: rep
 // CHECK: lodsb
         rep;lodsb



From sabre at nondot.org  Tue Sep 21 23:04:03 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 04:04:03 -0000
Subject: [llvm-commits] [llvm] r114527 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922040403.9DC0B2A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 23:04:03 2010
New Revision: 114527

URL: http://llvm.org/viewvc/llvm-project?rev=114527&view=rev
Log:
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'

-This line, and those below, will be ignored--

M    test/MC/AsmParser/X86/x86_instructions.s
M    lib/Target/X86/AsmParser/X86AsmParser.cpp

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114527&r1=114526&r2=114527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 21 23:04:03 2010
@@ -1015,6 +1015,14 @@
     Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
   }
   
+  // fstp <mem> -> fstps <mem>.  Without this, we'll default to fstpl due to
+  // suffix searching.
+  if (Name == "fstp" && Operands.size() == 2 &&
+      static_cast<X86Operand*>(Operands[1])->isMem()) {
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
+  }
+  
   return false;
 }
 

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114527&r1=114526&r2=114527&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 21 23:04:03 2010
@@ -310,3 +310,9 @@
 enter $0x7ace,$1
 enter $0x7ace,$0x7f
 
+
+// rdar://8456389
+// CHECK: fstps	(%eax)
+// CHECK: encoding: [0xd9,0x18]
+fstp	(%eax)
+



From sabre at nondot.org  Tue Sep 21 23:11:10 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 04:11:10 -0000
Subject: [llvm-commits] [llvm] r114528 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922041110.EBAD22A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 23:11:10 2010
New Revision: 114528

URL: http://llvm.org/viewvc/llvm-project?rev=114528&view=rev
Log:
Fix rdar://8456364 - llvm-mc rejects '%CS'

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114528&r1=114527&r2=114528&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 21 23:11:10 2010
@@ -10,20 +10,21 @@
 #include "llvm/Target/TargetAsmParser.h"
 #include "X86.h"
 #include "X86Subtarget.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/ADT/Twine.h"
+#include "llvm/Target/TargetRegistry.h"
+#include "llvm/Target/TargetAsmParser.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegistry.h"
-#include "llvm/Target/TargetAsmParser.h"
 using namespace llvm;
 
 namespace {
@@ -373,14 +374,18 @@
   // validation later, so maybe there is no need for this here.
   RegNo = MatchRegisterName(Tok.getString());
 
+  // If the match failed, try the register name as lowercase.
+  if (RegNo == 0)
+    RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
+  
   // FIXME: This should be done using Requires<In32BitMode> and
   // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
   // can be also checked.
   if (RegNo == X86::RIZ && !Is64Bit)
     return Error(Tok.getLoc(), "riz register in 64-bit mode only");
 
-  // Parse %st(1) and "%st" as "%st(0)"
-  if (RegNo == 0 && Tok.getString() == "st") {
+  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
+  if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
     RegNo = X86::ST0;
     EndLoc = Tok.getLoc();
     Parser.Lex(); // Eat 'st'

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114528&r1=114527&r2=114528&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 21 23:11:10 2010
@@ -316,3 +316,6 @@
 // CHECK: encoding: [0xd9,0x18]
 fstp	(%eax)
 
+// rdar://8456364
+// CHECK: movw	%cs, %ax
+mov %CS, %ax



From sabre at nondot.org  Tue Sep 21 23:39:11 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 04:39:11 -0000
Subject: [llvm-commits] [llvm] r114529 - in /llvm/trunk:
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrInfo.td
 test/CodeGen/X86/tls9.ll
Message-ID: <20100922043912.18C142A6C12C@llvm.org>

Author: lattner
Date: Tue Sep 21 23:39:11 2010
New Revision: 114529

URL: http://llvm.org/viewvc/llvm-project?rev=114529&view=rev
Log:
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/CodeGen/X86/tls9.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114529&r1=114528&r2=114529&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 21 23:39:11 2010
@@ -190,8 +190,7 @@
     SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
     SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
 
-    bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
-    bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
+    bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
     bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
     bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
     bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
@@ -544,29 +543,27 @@
 }
 
 
-bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
-                                              X86ISelAddressMode &AM) {
-  assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
-  SDValue Segment = N.getOperand(0);
-
-  if (AM.Segment.getNode() == 0) {
-    AM.Segment = Segment;
-    return false;
-  }
-
-  return true;
-}
-
-bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
+bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
+  SDValue Address = N->getOperand(1);
+  
+  // load gs:0 -> GS segment register.
+  // load fs:0 -> FS segment register.
+  //
   // This optimization is valid because the GNU TLS model defines that
   // gs:0 (or fs:0 on X86-64) contains its own address.
   // For more information see http://people.redhat.com/drepper/tls.pdf
-
-  SDValue Address = N.getOperand(1);
-  if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
-      !MatchSegmentBaseAddress(Address, AM))
-    return false;
-
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
+    if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
+        Subtarget->isTargetELF())
+      switch (N->getPointerInfo().getAddrSpace()) {
+      case 256:
+        AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
+        return false;
+      case 257:
+        AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
+        return false;
+      }
+  
   return true;
 }
 
@@ -751,11 +748,6 @@
     break;
   }
 
-  case X86ISD::SegmentBaseAddress:
-    if (!MatchSegmentBaseAddress(N, AM))
-      return false;
-    break;
-
   case X86ISD::Wrapper:
   case X86ISD::WrapperRIP:
     if (!MatchWrapper(N, AM))
@@ -763,7 +755,7 @@
     break;
 
   case ISD::LOAD:
-    if (!MatchLoad(N, AM))
+    if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
       return false;
     break;
 
@@ -1151,18 +1143,7 @@
                                  SDValue &Scale, SDValue &Index,
                                  SDValue &Disp, SDValue &Segment) {
   X86ISelAddressMode AM;
-  if (MatchAddress(N, AM))
-    return false;
-
-  EVT VT = N.getValueType();
-  if (AM.BaseType == X86ISelAddressMode::RegBase) {
-    if (!AM.Base_Reg.getNode())
-      AM.Base_Reg = CurDAG->getRegister(0, VT);
-  }
-
-  if (!AM.IndexReg.getNode())
-    AM.IndexReg = CurDAG->getRegister(0, VT);
-
+  
   if (Parent &&
       // This list of opcodes are all the nodes that have an "addr:$ptr" operand
       // that are not a MemSDNode, and thus don't have proper addrspace info.
@@ -1173,12 +1154,23 @@
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
     // AddrSpace 256 -> GS, 257 -> FS.
     if (AddrSpace == 256)
-      AM.Segment = CurDAG->getRegister(X86::GS, VT);
+      AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
     if (AddrSpace == 257)
-      AM.Segment = CurDAG->getRegister(X86::FS, VT);
+      AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
   }
   
-  
+  if (MatchAddress(N, AM))
+    return false;
+
+  EVT VT = N.getValueType();
+  if (AM.BaseType == X86ISelAddressMode::RegBase) {
+    if (!AM.Base_Reg.getNode())
+      AM.Base_Reg = CurDAG->getRegister(0, VT);
+  }
+
+  if (!AM.IndexReg.getNode())
+    AM.IndexReg = CurDAG->getRegister(0, VT);
+
   getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
   return true;
 }

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114529&r1=114528&r2=114529&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 21 23:39:11 2010
@@ -6150,14 +6150,14 @@
                                    const EVT PtrVT, TLSModel::Model model,
                                    bool is64Bit) {
   DebugLoc dl = GA->getDebugLoc();
-  // Get the Thread Pointer
-  SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
-                             DebugLoc(), PtrVT,
-                             DAG.getRegister(is64Bit? X86::FS : X86::GS,
-                                             MVT::i32));
-
-  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
-                                      MachinePointerInfo(), false, false, 0);
+  
+  // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
+  Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
+                                                         is64Bit ? 257 : 256));
+
+  SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 
+                                      DAG.getIntPtrConstant(0),
+                                      MachinePointerInfo(Ptr), false, false, 0);
 
   unsigned char OperandFlags = 0;
   // Most TLS accesses are not RIP relative, even on x86-64.  One exception is
@@ -8845,7 +8845,6 @@
   case X86ISD::FRCP:               return "X86ISD::FRCP";
   case X86ISD::TLSADDR:            return "X86ISD::TLSADDR";
   case X86ISD::TLSCALL:            return "X86ISD::TLSCALL";
-  case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
   case X86ISD::EH_RETURN:          return "X86ISD::EH_RETURN";
   case X86ISD::TC_RETURN:          return "X86ISD::TC_RETURN";
   case X86ISD::FNSTCW16m:          return "X86ISD::FNSTCW16m";

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=114529&r1=114528&r2=114529&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 21 23:39:11 2010
@@ -172,9 +172,6 @@
       // thunk at the address from an earlier relocation.
       TLSCALL,
 
-      // SegmentBaseAddress - The address segment:0
-      SegmentBaseAddress,
-
       // EH_RETURN - Exception Handling helpers.
       EH_RETURN,
       

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114529&r1=114528&r2=114529&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 21 23:39:11 2010
@@ -74,8 +74,6 @@
 
 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
 
-def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
-
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
@@ -169,8 +167,6 @@
 
 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
-                                 SDT_X86SegmentBaseAddress, []>;
 
 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
                         [SDNPHasChain]>;

Modified: llvm/trunk/test/CodeGen/X86/tls9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls9.ll?rev=114529&r1=114528&r2=114529&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls9.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls9.ll Tue Sep 21 23:39:11 2010
@@ -5,7 +5,7 @@
 
 @i = external hidden thread_local global i32
 
-define i32 @f() {
+define i32 @f() nounwind {
 entry:
 	%tmp1 = load i32* @i
 	ret i32 %tmp1



From sabre at nondot.org  Tue Sep 21 23:56:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 04:56:20 -0000
Subject: [llvm-commits] [llvm] r114531 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922045620.6CE312A6C12E@llvm.org>

Author: lattner
Date: Tue Sep 21 23:56:20 2010
New Revision: 114531

URL: http://llvm.org/viewvc/llvm-project?rev=114531&view=rev
Log:
add the missing aliases for fp stack cmovs, rdar://8456391

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114531&r1=114530&r2=114531&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 21 23:56:20 2010
@@ -685,6 +685,12 @@
     .Case("cmovnzq", "cmovneq").Case("cmovnz",  "cmovne")
     .Case("cmovzw",  "cmovew") .Case("cmovzl",  "cmovel")
     .Case("cmovzq",  "cmoveq") .Case("cmovz",   "cmove")
+    // Floating point stack cmov aliases.
+    .Case("fcmovz", "fcmove")
+    .Case("fcmova", "fcmovnbe")
+    .Case("fcmovnae", "fcmovb")
+    .Case("fcmovna", "fcmovbe")
+    .Case("fcmovae", "fcmovnb")
     .Case("fwait", "wait")
     .Case("movzx", "movzb")  // FIXME: Not correct.
     .Case("fildq", "fildll")

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114531&r1=114530&r2=114531&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Tue Sep 21 23:56:20 2010
@@ -319,3 +319,20 @@
 // rdar://8456364
 // CHECK: movw	%cs, %ax
 mov %CS, %ax
+
+// rdar://8456391
+fcmovb %st(1), %st(0)   // CHECK: fcmovb	%st(1), %st(0)
+fcmove %st(1), %st(0)   // CHECK: fcmove	%st(1), %st(0)
+fcmovbe %st(1), %st(0)  // CHECK: fcmovbe	%st(1), %st(0)
+fcmovu %st(1), %st(0)   // CHECK: fcmovu	 %st(1), %st(0)
+
+fcmovnb %st(1), %st(0)  // CHECK: fcmovnb	%st(1), %st(0)
+fcmovne %st(1), %st(0)  // CHECK: fcmovne	%st(1), %st(0)
+fcmovnbe %st(1), %st(0) // CHECK: fcmovnbe	%st(1), %st(0)
+fcmovnu %st(1), %st(0)  // CHECK: fcmovnu	%st(1), %st(0)
+
+fcmovnae %st(1), %st(0) // CHECK: fcmovb	%st(1), %st(0)
+fcmovna %st(1), %st(0)  // CHECK: fcmovbe	%st(1), %st(0)
+
+fcmovae %st(1), %st(0)  // CHECK: fcmovnb	%st(1), %st(0)
+fcmova %st(1), %st(0)   // CHECK: fcmovnbe	%st(1), %st(0)



From sabre at nondot.org  Wed Sep 22 00:05:16 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 05:05:16 -0000
Subject: [llvm-commits] [llvm] r114532 - in /llvm/trunk:
 lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922050516.3626C2A6C12C@llvm.org>

Author: lattner
Date: Wed Sep 22 00:05:16 2010
New Revision: 114532

URL: http://llvm.org/viewvc/llvm-project?rev=114532&view=rev
Log:
fix rdar://8456417 - llvm-mc can't do basic math


Modified:
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114532&r1=114531&r2=114532&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Sep 22 00:05:16 2010
@@ -700,44 +700,45 @@
     Kind = MCBinaryExpr::LOr;
     return 1;
 
-    // Low Precedence: +, -, ==, !=, <>, <, <=, >, >=
+    
+    // Low Precedence: |, &, ^
+    //
+    // FIXME: gas seems to support '!' as an infix operator?
+  case AsmToken::Pipe:
+    Kind = MCBinaryExpr::Or;
+    return 2;
+  case AsmToken::Caret:
+    Kind = MCBinaryExpr::Xor;
+    return 2;
+  case AsmToken::Amp:
+    Kind = MCBinaryExpr::And;
+    return 2;
+      
+    // Intermediate Precedence: +, -, ==, !=, <>, <, <=, >, >=
   case AsmToken::Plus:
     Kind = MCBinaryExpr::Add;
-    return 2;
+    return 3;
   case AsmToken::Minus:
     Kind = MCBinaryExpr::Sub;
-    return 2;
+    return 3;
   case AsmToken::EqualEqual:
     Kind = MCBinaryExpr::EQ;
-    return 2;
+    return 3;
   case AsmToken::ExclaimEqual:
   case AsmToken::LessGreater:
     Kind = MCBinaryExpr::NE;
-    return 2;
+    return 3;
   case AsmToken::Less:
     Kind = MCBinaryExpr::LT;
-    return 2;
+    return 3;
   case AsmToken::LessEqual:
     Kind = MCBinaryExpr::LTE;
-    return 2;
+    return 3;
   case AsmToken::Greater:
     Kind = MCBinaryExpr::GT;
-    return 2;
+    return 3;
   case AsmToken::GreaterEqual:
     Kind = MCBinaryExpr::GTE;
-    return 2;
-
-    // Intermediate Precedence: |, &, ^
-    //
-    // FIXME: gas seems to support '!' as an infix operator?
-  case AsmToken::Pipe:
-    Kind = MCBinaryExpr::Or;
-    return 3;
-  case AsmToken::Caret:
-    Kind = MCBinaryExpr::Xor;
-    return 3;
-  case AsmToken::Amp:
-    Kind = MCBinaryExpr::And;
     return 3;
 
     // Highest Precedence: *, /, %, <<, >>

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114532&r1=114531&r2=114532&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Wed Sep 22 00:05:16 2010
@@ -336,3 +336,8 @@
 
 fcmovae %st(1), %st(0)  // CHECK: fcmovnb	%st(1), %st(0)
 fcmova %st(1), %st(0)   // CHECK: fcmovnbe	%st(1), %st(0)
+
+// rdar://8456417
+.byte 88 + 1 & 15  // CHECK: .byte	9
+
+



From sabre at nondot.org  Wed Sep 22 00:29:50 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 05:29:50 -0000
Subject: [llvm-commits] [llvm] r114533 - in /llvm/trunk:
 lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86RegisterInfo.cpp
 lib/Target/X86/X86RegisterInfo.td test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922052950.EBA412A6C12C@llvm.org>

Author: lattner
Date: Wed Sep 22 00:29:50 2010
New Revision: 114533

URL: http://llvm.org/viewvc/llvm-project?rev=114533&view=rev
Log:
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
Teaching the code generator about CR8-15, how to rex them up, etc.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=114533&r1=114532&r2=114533&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Sep 22 00:29:50 2010
@@ -2993,6 +2993,8 @@
   case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
   case X86::YMM8:  case X86::YMM9:  case X86::YMM10: case X86::YMM11:
   case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
+  case X86::CR8:   case X86::CR9:   case X86::CR10:  case X86::CR11:
+  case X86::CR12:  case X86::CR13:  case X86::CR14:  case X86::CR15:
     return true;
   }
   return false;

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=114533&r1=114532&r2=114533&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Sep 22 00:29:50 2010
@@ -159,46 +159,21 @@
   case X86::YMM7: case X86::YMM15: case X86::MM7:
     return 7;
 
-  case X86::ES:
-    return 0;
-  case X86::CS:
-    return 1;
-  case X86::SS:
-    return 2;
-  case X86::DS:
-    return 3;
-  case X86::FS:
-    return 4;
-  case X86::GS:
-    return 5;
-
-  case X86::CR0:
-    return 0;
-  case X86::CR1:
-    return 1;
-  case X86::CR2:
-    return 2;
-  case X86::CR3:
-    return 3;
-  case X86::CR4:
-    return 4;
-
-  case X86::DR0:
-    return 0;
-  case X86::DR1:
-    return 1;
-  case X86::DR2:
-    return 2;
-  case X86::DR3:
-    return 3;
-  case X86::DR4:
-    return 4;
-  case X86::DR5:
-    return 5;
-  case X86::DR6:
-    return 6;
-  case X86::DR7:
-    return 7;
+  case X86::ES: return 0;
+  case X86::CS: return 1;
+  case X86::SS: return 2;
+  case X86::DS: return 3;
+  case X86::FS: return 4;
+  case X86::GS: return 5;
+
+  case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
+  case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
+  case X86::CR2: case X86::CR10: case X86::DR2: return 2;
+  case X86::CR3: case X86::CR11: case X86::DR3: return 3;
+  case X86::CR4: case X86::CR12: case X86::DR4: return 4;
+  case X86::CR5: case X86::CR13: case X86::DR5: return 5;
+  case X86::CR6: case X86::CR14: case X86::DR6: return 6;
+  case X86::CR7: case X86::CR15: case X86::DR7: return 7;
 
   // Pseudo index registers are equivalent to a "none"
   // scaled index (See Intel Manual 2A, table 2-3)

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=114533&r1=114532&r2=114533&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Wed Sep 22 00:29:50 2010
@@ -231,7 +231,7 @@
   def DR6 : Register<"dr6">;
   def DR7 : Register<"dr7">;
   
-  // Condition registers
+  // Control registers
   def CR0 : Register<"cr0">;
   def CR1 : Register<"cr1">;
   def CR2 : Register<"cr2">;
@@ -241,6 +241,13 @@
   def CR6 : Register<"cr6">;
   def CR7 : Register<"cr7">;
   def CR8 : Register<"cr8">;
+  def CR9 : Register<"cr9">;
+  def CR10 : Register<"cr10">;
+  def CR11 : Register<"cr11">;
+  def CR12 : Register<"cr12">;
+  def CR13 : Register<"cr13">;
+  def CR14 : Register<"cr14">;
+  def CR15 : Register<"cr15">;
 
   // Pseudo index registers
   def EIZ : Register<"eiz">;
@@ -456,7 +463,8 @@
 
 // Control registers.
 def CONTROL_REG : RegisterClass<"X86", [i64], 64,
-                                [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8]> {
+                                [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8,
+                                 CR9, CR10, CR11, CR12, CR13, CR14, CR15]> {
 }
 
 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114533&r1=114532&r2=114533&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Wed Sep 22 00:29:50 2010
@@ -340,4 +340,16 @@
 // rdar://8456417
 .byte 88 + 1 & 15  // CHECK: .byte	9
 
-
+// rdar://8456412
+mov %rdx, %cr0
+// CHECK: movq	%rdx, %cr0
+// CHECK: encoding: [0x0f,0x22,0xc2]
+mov %rdx, %cr4
+// CHECK: movq	%rdx, %cr4
+// CHECK: encoding: [0x0f,0x22,0xe2]
+mov %rdx, %cr8
+// CHECK: movq	%rdx, %cr8
+// CHECK: encoding: [0x44,0x0f,0x22,0xc2]
+mov %rdx, %cr15
+// CHECK: movq	%rdx, %cr15
+// CHECK: encoding: [0x44,0x0f,0x22,0xfa]



From sabre at nondot.org  Wed Sep 22 00:49:14 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 05:49:14 -0000
Subject: [llvm-commits] [llvm] r114534 - in /llvm/trunk: lib/Target/X86/
 lib/Target/X86/AsmParser/ test/CodeGen/X86/ test/MC/AsmParser/X86/
Message-ID: <20100922054914.E4D562A6C12C@llvm.org>

Author: lattner
Date: Wed Sep 22 00:49:14 2010
New Revision: 114534

URL: http://llvm.org/viewvc/llvm-project?rev=114534&view=rev
Log:
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll
    llvm/trunk/test/CodeGen/X86/abi-isel.ll
    llvm/trunk/test/CodeGen/X86/dll-linkage.ll
    llvm/trunk/test/CodeGen/X86/dollar-name.ll
    llvm/trunk/test/CodeGen/X86/ghc-cc.ll
    llvm/trunk/test/CodeGen/X86/memmove-0.ll
    llvm/trunk/test/CodeGen/X86/memmove-1.ll
    llvm/trunk/test/CodeGen/X86/memmove-3.ll
    llvm/trunk/test/CodeGen/X86/memset-2.ll
    llvm/trunk/test/CodeGen/X86/mingw-alloca.ll
    llvm/trunk/test/CodeGen/X86/movgs.ll
    llvm/trunk/test/CodeGen/X86/pic.ll
    llvm/trunk/test/CodeGen/X86/sibcall-3.ll
    llvm/trunk/test/CodeGen/X86/sibcall.ll
    llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll
    llvm/trunk/test/CodeGen/X86/unaligned-load.ll
    llvm/trunk/test/CodeGen/X86/win_chkstk.ll
    llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s
    llvm/trunk/test/MC/AsmParser/X86/x86_operands.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 22 00:49:14 2010
@@ -1020,6 +1020,14 @@
                                           NameLoc);
   }
   
+  // call foo is not ambiguous with callw.
+  if (Name == "call" && Operands.size() == 2) {
+    const char *NewName = Is64Bit ? "callq" : "calll";
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
+    Name = NewName;
+  }
+  
   // movsd -> movsl (when no operands are specified).
   if (Name == "movsd" && Operands.size() == 1) {
     delete Operands[0];

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Sep 22 00:49:14 2010
@@ -148,10 +148,10 @@
                         Requires<[In64BitMode, NotWin64]>;
     def CALL64r       : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
                           "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
-                        Requires<[NotWin64]>;
+                        Requires<[In64BitMode, NotWin64]>;
     def CALL64m       : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
                           "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
-                        Requires<[NotWin64]>;
+                        Requires<[In64BitMode, NotWin64]>;
                         
     def FARCALL64   : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
                          "lcall{q}\t{*}$dst", []>;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Sep 22 00:49:14 2010
@@ -690,11 +690,13 @@
       Uses = [ESP] in {
     def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
                            (outs), (ins i32imm_pcrel:$dst,variable_ops),
-                           "call\t$dst", []>;
+                           "call{l}\t$dst", []>, Requires<[In32BitMode]>;
     def CALL32r     : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
-                        "call\t{*}$dst", [(X86call GR32:$dst)]>;
+                        "call{l}\t{*}$dst", [(X86call GR32:$dst)]>,
+                         Requires<[In32BitMode]>;
     def CALL32m     : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
-                        "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
+                        "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
+                        Requires<[In32BitMode]>;
   
     def FARCALL16i  : Iseg16<0x9A, RawFrmImm16, (outs), 
                              (ins i16imm:$off, i16imm:$seg),

Modified: llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll Wed Sep 22 00:49:14 2010
@@ -11,7 +11,7 @@
 ; Verify that %esi gets spilled before the call.
 ; CHECK: Z4test1SiS
 ; CHECK: movl %esi,{{.*}}(%ebp) 
-; CHECK: call __Z6throwsv
+; CHECK: calll __Z6throwsv
 
 define i8* @_Z4test1SiS_(%struct.S* byval %s1, i32 %n, %struct.S* byval %s2) ssp {
 entry:

Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Wed Sep 22 00:49:14 2010
@@ -72,7 +72,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo00:
-; DARWIN-32-PIC: 	call	L0$pb
+; DARWIN-32-PIC: 	calll	L0$pb
 ; DARWIN-32-PIC-NEXT: L0$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L0$pb(%eax), %ecx
@@ -144,7 +144,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _fxo00:
-; DARWIN-32-PIC: 	call	L1$pb
+; DARWIN-32-PIC: 	calll	L1$pb
 ; DARWIN-32-PIC-NEXT: L1$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L1$pb(%eax), %ecx
@@ -208,7 +208,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo01:
-; DARWIN-32-PIC: 	call	L2$pb
+; DARWIN-32-PIC: 	calll	L2$pb
 ; DARWIN-32-PIC-NEXT: L2$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L2$pb(%eax), %ecx
@@ -268,7 +268,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _fxo01:
-; DARWIN-32-PIC: 	call	L3$pb
+; DARWIN-32-PIC: 	calll	L3$pb
 ; DARWIN-32-PIC-NEXT: L3$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L3$pb(%eax), %ecx
@@ -342,7 +342,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo02:
-; DARWIN-32-PIC: 	call	L4$pb
+; DARWIN-32-PIC: 	calll	L4$pb
 ; DARWIN-32-PIC-NEXT: L4$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L4$pb(%eax), %ecx
@@ -424,7 +424,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _fxo02:
-; DARWIN-32-PIC: 	call	L5$pb
+; DARWIN-32-PIC: 	calll	L5$pb
 ; DARWIN-32-PIC-NEXT: L5$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L5$pb(%eax), %ecx
@@ -497,7 +497,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo03:
-; DARWIN-32-PIC: 	call	L6$pb
+; DARWIN-32-PIC: 	calll	L6$pb
 ; DARWIN-32-PIC-NEXT: L6$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L6$pb(%eax), %ecx
@@ -551,7 +551,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo04:
-; DARWIN-32-PIC: 	call	L7$pb
+; DARWIN-32-PIC: 	calll	L7$pb
 ; DARWIN-32-PIC-NEXT: L7$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_ddst-L7$pb(%eax), %ecx
@@ -619,7 +619,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo05:
-; DARWIN-32-PIC: 	call	L8$pb
+; DARWIN-32-PIC: 	calll	L8$pb
 ; DARWIN-32-PIC-NEXT: L8$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L8$pb(%eax), %ecx
@@ -682,7 +682,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo06:
-; DARWIN-32-PIC: 	call	L9$pb
+; DARWIN-32-PIC: 	calll	L9$pb
 ; DARWIN-32-PIC-NEXT: L9$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L9$pb(%eax), %ecx
@@ -735,7 +735,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo07:
-; DARWIN-32-PIC: 	call	L10$pb
+; DARWIN-32-PIC: 	calll	L10$pb
 ; DARWIN-32-PIC-NEXT: L10$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_ldst-L10$pb(%eax), %ecx
@@ -801,7 +801,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo08:
-; DARWIN-32-PIC: 	call	L11$pb
+; DARWIN-32-PIC: 	calll	L11$pb
 ; DARWIN-32-PIC-NEXT: L11$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L11$pb(%eax), %ecx
@@ -868,7 +868,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux00:
-; DARWIN-32-PIC: 	call	L12$pb
+; DARWIN-32-PIC: 	calll	L12$pb
 ; DARWIN-32-PIC-NEXT: L12$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L12$pb(%eax), %ecx
@@ -939,7 +939,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qxx00:
-; DARWIN-32-PIC: 	call	L13$pb
+; DARWIN-32-PIC: 	calll	L13$pb
 ; DARWIN-32-PIC-NEXT: L13$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L13$pb(%eax), %ecx
@@ -1005,7 +1005,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux01:
-; DARWIN-32-PIC: 	call	L14$pb
+; DARWIN-32-PIC: 	calll	L14$pb
 ; DARWIN-32-PIC-NEXT: L14$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L14$pb(%eax), %ecx
@@ -1071,7 +1071,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qxx01:
-; DARWIN-32-PIC: 	call	L15$pb
+; DARWIN-32-PIC: 	calll	L15$pb
 ; DARWIN-32-PIC-NEXT: L15$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L15$pb(%eax), %ecx
@@ -1150,7 +1150,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux02:
-; DARWIN-32-PIC: 	call	L16$pb
+; DARWIN-32-PIC: 	calll	L16$pb
 ; DARWIN-32-PIC-NEXT: L16$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L16$pb(%eax), %ecx
@@ -1233,7 +1233,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qxx02:
-; DARWIN-32-PIC: 	call	L17$pb
+; DARWIN-32-PIC: 	calll	L17$pb
 ; DARWIN-32-PIC-NEXT: L17$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L17$pb(%eax), %ecx
@@ -1306,7 +1306,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux03:
-; DARWIN-32-PIC: 	call	L18$pb
+; DARWIN-32-PIC: 	calll	L18$pb
 ; DARWIN-32-PIC-NEXT: L18$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L18$pb)+64(%eax), %ecx
@@ -1361,7 +1361,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux04:
-; DARWIN-32-PIC: 	call	L19$pb
+; DARWIN-32-PIC: 	calll	L19$pb
 ; DARWIN-32-PIC-NEXT: L19$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L19$pb)+64(%eax), %ecx
@@ -1430,7 +1430,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux05:
-; DARWIN-32-PIC: 	call	L20$pb
+; DARWIN-32-PIC: 	calll	L20$pb
 ; DARWIN-32-PIC-NEXT: L20$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L20$pb)+64(%eax), %ecx
@@ -1493,7 +1493,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux06:
-; DARWIN-32-PIC: 	call	L21$pb
+; DARWIN-32-PIC: 	calll	L21$pb
 ; DARWIN-32-PIC-NEXT: L21$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L21$pb)+64(%eax), %ecx
@@ -1546,7 +1546,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux07:
-; DARWIN-32-PIC: 	call	L22$pb
+; DARWIN-32-PIC: 	calll	L22$pb
 ; DARWIN-32-PIC-NEXT: L22$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L22$pb)+64(%eax), %ecx
@@ -1613,7 +1613,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux08:
-; DARWIN-32-PIC: 	call	L23$pb
+; DARWIN-32-PIC: 	calll	L23$pb
 ; DARWIN-32-PIC-NEXT: L23$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L23$pb)+64(%eax), %ecx
@@ -1686,7 +1686,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind00:
-; DARWIN-32-PIC: 	call	L24$pb
+; DARWIN-32-PIC: 	calll	L24$pb
 ; DARWIN-32-PIC-NEXT: L24$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -1764,7 +1764,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ixd00:
-; DARWIN-32-PIC: 	call	L25$pb
+; DARWIN-32-PIC: 	calll	L25$pb
 ; DARWIN-32-PIC-NEXT: L25$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -1840,7 +1840,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind01:
-; DARWIN-32-PIC: 	call	L26$pb
+; DARWIN-32-PIC: 	calll	L26$pb
 ; DARWIN-32-PIC-NEXT: L26$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -1916,7 +1916,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ixd01:
-; DARWIN-32-PIC: 	call	L27$pb
+; DARWIN-32-PIC: 	calll	L27$pb
 ; DARWIN-32-PIC-NEXT: L27$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2001,7 +2001,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind02:
-; DARWIN-32-PIC: 	call	L28$pb
+; DARWIN-32-PIC: 	calll	L28$pb
 ; DARWIN-32-PIC-NEXT: L28$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2090,7 +2090,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ixd02:
-; DARWIN-32-PIC: 	call	L29$pb
+; DARWIN-32-PIC: 	calll	L29$pb
 ; DARWIN-32-PIC-NEXT: L29$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2170,7 +2170,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind03:
-; DARWIN-32-PIC: 	call	L30$pb
+; DARWIN-32-PIC: 	calll	L30$pb
 ; DARWIN-32-PIC-NEXT: L30$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2242,7 +2242,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind04:
-; DARWIN-32-PIC: 	call	L31$pb
+; DARWIN-32-PIC: 	calll	L31$pb
 ; DARWIN-32-PIC-NEXT: L31$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2320,7 +2320,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind05:
-; DARWIN-32-PIC: 	call	L32$pb
+; DARWIN-32-PIC: 	calll	L32$pb
 ; DARWIN-32-PIC-NEXT: L32$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2395,7 +2395,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind06:
-; DARWIN-32-PIC: 	call	L33$pb
+; DARWIN-32-PIC: 	calll	L33$pb
 ; DARWIN-32-PIC-NEXT: L33$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2466,7 +2466,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind07:
-; DARWIN-32-PIC: 	call	L34$pb
+; DARWIN-32-PIC: 	calll	L34$pb
 ; DARWIN-32-PIC-NEXT: L34$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2543,7 +2543,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind08:
-; DARWIN-32-PIC: 	call	L35$pb
+; DARWIN-32-PIC: 	calll	L35$pb
 ; DARWIN-32-PIC-NEXT: L35$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2621,7 +2621,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off00:
-; DARWIN-32-PIC: 	call	L36$pb
+; DARWIN-32-PIC: 	calll	L36$pb
 ; DARWIN-32-PIC-NEXT: L36$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2700,7 +2700,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _oxf00:
-; DARWIN-32-PIC: 	call	L37$pb
+; DARWIN-32-PIC: 	calll	L37$pb
 ; DARWIN-32-PIC-NEXT: L37$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2777,7 +2777,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off01:
-; DARWIN-32-PIC: 	call	L38$pb
+; DARWIN-32-PIC: 	calll	L38$pb
 ; DARWIN-32-PIC-NEXT: L38$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2854,7 +2854,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _oxf01:
-; DARWIN-32-PIC: 	call	L39$pb
+; DARWIN-32-PIC: 	calll	L39$pb
 ; DARWIN-32-PIC-NEXT: L39$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -2940,7 +2940,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off02:
-; DARWIN-32-PIC: 	call	L40$pb
+; DARWIN-32-PIC: 	calll	L40$pb
 ; DARWIN-32-PIC-NEXT: L40$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3030,7 +3030,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _oxf02:
-; DARWIN-32-PIC: 	call	L41$pb
+; DARWIN-32-PIC: 	calll	L41$pb
 ; DARWIN-32-PIC-NEXT: L41$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3111,7 +3111,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off03:
-; DARWIN-32-PIC: 	call	L42$pb
+; DARWIN-32-PIC: 	calll	L42$pb
 ; DARWIN-32-PIC-NEXT: L42$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3184,7 +3184,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off04:
-; DARWIN-32-PIC: 	call	L43$pb
+; DARWIN-32-PIC: 	calll	L43$pb
 ; DARWIN-32-PIC-NEXT: L43$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3263,7 +3263,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off05:
-; DARWIN-32-PIC: 	call	L44$pb
+; DARWIN-32-PIC: 	calll	L44$pb
 ; DARWIN-32-PIC-NEXT: L44$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3339,7 +3339,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off06:
-; DARWIN-32-PIC: 	call	L45$pb
+; DARWIN-32-PIC: 	calll	L45$pb
 ; DARWIN-32-PIC-NEXT: L45$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3411,7 +3411,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off07:
-; DARWIN-32-PIC: 	call	L46$pb
+; DARWIN-32-PIC: 	calll	L46$pb
 ; DARWIN-32-PIC-NEXT: L46$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3489,7 +3489,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off08:
-; DARWIN-32-PIC: 	call	L47$pb
+; DARWIN-32-PIC: 	calll	L47$pb
 ; DARWIN-32-PIC-NEXT: L47$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -3560,7 +3560,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo00:
-; DARWIN-32-PIC: 	call	L48$pb
+; DARWIN-32-PIC: 	calll	L48$pb
 ; DARWIN-32-PIC-NEXT: L48$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L48$pb(%eax), %ecx
@@ -3626,7 +3626,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo01:
-; DARWIN-32-PIC: 	call	L49$pb
+; DARWIN-32-PIC: 	calll	L49$pb
 ; DARWIN-32-PIC-NEXT: L49$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %ecx
@@ -3705,7 +3705,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo02:
-; DARWIN-32-PIC: 	call	L50$pb
+; DARWIN-32-PIC: 	calll	L50$pb
 ; DARWIN-32-PIC-NEXT: L50$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L50$pb(%eax), %ecx
@@ -3778,7 +3778,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo03:
-; DARWIN-32-PIC: 	call	L51$pb
+; DARWIN-32-PIC: 	calll	L51$pb
 ; DARWIN-32-PIC-NEXT: L51$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L51$pb)+262144(%eax), %ecx
@@ -3833,7 +3833,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo04:
-; DARWIN-32-PIC: 	call	L52$pb
+; DARWIN-32-PIC: 	calll	L52$pb
 ; DARWIN-32-PIC-NEXT: L52$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L52$pb)+262144(%eax), %ecx
@@ -3902,7 +3902,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo05:
-; DARWIN-32-PIC: 	call	L53$pb
+; DARWIN-32-PIC: 	calll	L53$pb
 ; DARWIN-32-PIC-NEXT: L53$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L53$pb)+262144(%eax), %ecx
@@ -3965,7 +3965,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo06:
-; DARWIN-32-PIC: 	call	L54$pb
+; DARWIN-32-PIC: 	calll	L54$pb
 ; DARWIN-32-PIC-NEXT: L54$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L54$pb)+262144(%eax), %ecx
@@ -4018,7 +4018,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo07:
-; DARWIN-32-PIC: 	call	L55$pb
+; DARWIN-32-PIC: 	calll	L55$pb
 ; DARWIN-32-PIC-NEXT: L55$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L55$pb)+262144(%eax), %ecx
@@ -4085,7 +4085,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo08:
-; DARWIN-32-PIC: 	call	L56$pb
+; DARWIN-32-PIC: 	calll	L56$pb
 ; DARWIN-32-PIC-NEXT: L56$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L56$pb)+262144(%eax), %ecx
@@ -4159,7 +4159,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big00:
-; DARWIN-32-PIC: 	call	L57$pb
+; DARWIN-32-PIC: 	calll	L57$pb
 ; DARWIN-32-PIC-NEXT: L57$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4236,7 +4236,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big01:
-; DARWIN-32-PIC: 	call	L58$pb
+; DARWIN-32-PIC: 	calll	L58$pb
 ; DARWIN-32-PIC-NEXT: L58$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4322,7 +4322,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big02:
-; DARWIN-32-PIC: 	call	L59$pb
+; DARWIN-32-PIC: 	calll	L59$pb
 ; DARWIN-32-PIC-NEXT: L59$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4403,7 +4403,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big03:
-; DARWIN-32-PIC: 	call	L60$pb
+; DARWIN-32-PIC: 	calll	L60$pb
 ; DARWIN-32-PIC-NEXT: L60$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4476,7 +4476,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big04:
-; DARWIN-32-PIC: 	call	L61$pb
+; DARWIN-32-PIC: 	calll	L61$pb
 ; DARWIN-32-PIC-NEXT: L61$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4555,7 +4555,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big05:
-; DARWIN-32-PIC: 	call	L62$pb
+; DARWIN-32-PIC: 	calll	L62$pb
 ; DARWIN-32-PIC-NEXT: L62$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4631,7 +4631,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big06:
-; DARWIN-32-PIC: 	call	L63$pb
+; DARWIN-32-PIC: 	calll	L63$pb
 ; DARWIN-32-PIC-NEXT: L63$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4703,7 +4703,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big07:
-; DARWIN-32-PIC: 	call	L64$pb
+; DARWIN-32-PIC: 	calll	L64$pb
 ; DARWIN-32-PIC-NEXT: L64$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4781,7 +4781,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big08:
-; DARWIN-32-PIC: 	call	L65$pb
+; DARWIN-32-PIC: 	calll	L65$pb
 ; DARWIN-32-PIC-NEXT: L65$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -4840,7 +4840,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar00:
-; DARWIN-32-PIC: 	call	L66$pb
+; DARWIN-32-PIC: 	calll	L66$pb
 ; DARWIN-32-PIC-NEXT: L66$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L66$pb(%eax), %eax
@@ -4887,7 +4887,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bxr00:
-; DARWIN-32-PIC: 	call	L67$pb
+; DARWIN-32-PIC: 	calll	L67$pb
 ; DARWIN-32-PIC-NEXT: L67$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L67$pb(%eax), %eax
@@ -4934,7 +4934,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar01:
-; DARWIN-32-PIC: 	call	L68$pb
+; DARWIN-32-PIC: 	calll	L68$pb
 ; DARWIN-32-PIC-NEXT: L68$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L68$pb(%eax), %eax
@@ -4981,7 +4981,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bxr01:
-; DARWIN-32-PIC: 	call	L69$pb
+; DARWIN-32-PIC: 	calll	L69$pb
 ; DARWIN-32-PIC-NEXT: L69$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L69$pb(%eax), %eax
@@ -5028,7 +5028,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar02:
-; DARWIN-32-PIC: 	call	L70$pb
+; DARWIN-32-PIC: 	calll	L70$pb
 ; DARWIN-32-PIC-NEXT: L70$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L70$pb(%eax), %eax
@@ -5075,7 +5075,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar03:
-; DARWIN-32-PIC: 	call	L71$pb
+; DARWIN-32-PIC: 	calll	L71$pb
 ; DARWIN-32-PIC-NEXT: L71$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_dsrc-L71$pb(%eax), %eax
@@ -5122,7 +5122,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar04:
-; DARWIN-32-PIC: 	call	L72$pb
+; DARWIN-32-PIC: 	calll	L72$pb
 ; DARWIN-32-PIC-NEXT: L72$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_ddst-L72$pb(%eax), %eax
@@ -5169,7 +5169,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar05:
-; DARWIN-32-PIC: 	call	L73$pb
+; DARWIN-32-PIC: 	calll	L73$pb
 ; DARWIN-32-PIC-NEXT: L73$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_dptr-L73$pb(%eax), %eax
@@ -5216,7 +5216,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar06:
-; DARWIN-32-PIC: 	call	L74$pb
+; DARWIN-32-PIC: 	calll	L74$pb
 ; DARWIN-32-PIC-NEXT: L74$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_lsrc-L74$pb(%eax), %eax
@@ -5263,7 +5263,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar07:
-; DARWIN-32-PIC: 	call	L75$pb
+; DARWIN-32-PIC: 	calll	L75$pb
 ; DARWIN-32-PIC-NEXT: L75$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_ldst-L75$pb(%eax), %eax
@@ -5310,7 +5310,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bar08:
-; DARWIN-32-PIC: 	call	L76$pb
+; DARWIN-32-PIC: 	calll	L76$pb
 ; DARWIN-32-PIC-NEXT: L76$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_lptr-L76$pb(%eax), %eax
@@ -5357,7 +5357,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har00:
-; DARWIN-32-PIC: 	call	L77$pb
+; DARWIN-32-PIC: 	calll	L77$pb
 ; DARWIN-32-PIC-NEXT: L77$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L77$pb(%eax), %eax
@@ -5404,7 +5404,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _hxr00:
-; DARWIN-32-PIC: 	call	L78$pb
+; DARWIN-32-PIC: 	calll	L78$pb
 ; DARWIN-32-PIC-NEXT: L78$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L78$pb(%eax), %eax
@@ -5451,7 +5451,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har01:
-; DARWIN-32-PIC: 	call	L79$pb
+; DARWIN-32-PIC: 	calll	L79$pb
 ; DARWIN-32-PIC-NEXT: L79$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L79$pb(%eax), %eax
@@ -5498,7 +5498,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _hxr01:
-; DARWIN-32-PIC: 	call	L80$pb
+; DARWIN-32-PIC: 	calll	L80$pb
 ; DARWIN-32-PIC-NEXT: L80$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L80$pb(%eax), %eax
@@ -5549,7 +5549,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har02:
-; DARWIN-32-PIC: 	call	L81$pb
+; DARWIN-32-PIC: 	calll	L81$pb
 ; DARWIN-32-PIC-NEXT: L81$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L81$pb(%eax), %eax
@@ -5600,7 +5600,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har03:
-; DARWIN-32-PIC: 	call	L82$pb
+; DARWIN-32-PIC: 	calll	L82$pb
 ; DARWIN-32-PIC-NEXT: L82$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_dsrc-L82$pb(%eax), %eax
@@ -5647,7 +5647,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har04:
-; DARWIN-32-PIC: 	call	L83$pb
+; DARWIN-32-PIC: 	calll	L83$pb
 ; DARWIN-32-PIC-NEXT: L83$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_ddst-L83$pb(%eax), %eax
@@ -5697,7 +5697,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har05:
-; DARWIN-32-PIC: 	call	L84$pb
+; DARWIN-32-PIC: 	calll	L84$pb
 ; DARWIN-32-PIC-NEXT: L84$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_dptr-L84$pb(%eax), %eax
@@ -5744,7 +5744,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har06:
-; DARWIN-32-PIC: 	call	L85$pb
+; DARWIN-32-PIC: 	calll	L85$pb
 ; DARWIN-32-PIC-NEXT: L85$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_lsrc-L85$pb(%eax), %eax
@@ -5791,7 +5791,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har07:
-; DARWIN-32-PIC: 	call	L86$pb
+; DARWIN-32-PIC: 	calll	L86$pb
 ; DARWIN-32-PIC-NEXT: L86$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_ldst-L86$pb(%eax), %eax
@@ -5840,7 +5840,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har08:
-; DARWIN-32-PIC: 	call	L87$pb
+; DARWIN-32-PIC: 	calll	L87$pb
 ; DARWIN-32-PIC-NEXT: L87$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_lptr-L87$pb(%eax), %eax
@@ -5889,7 +5889,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat00:
-; DARWIN-32-PIC: 	call	L88$pb
+; DARWIN-32-PIC: 	calll	L88$pb
 ; DARWIN-32-PIC-NEXT: L88$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L88$pb(%eax), %eax
@@ -5942,7 +5942,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bxt00:
-; DARWIN-32-PIC: 	call	L89$pb
+; DARWIN-32-PIC: 	calll	L89$pb
 ; DARWIN-32-PIC-NEXT: L89$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L89$pb(%eax), %eax
@@ -5995,7 +5995,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat01:
-; DARWIN-32-PIC: 	call	L90$pb
+; DARWIN-32-PIC: 	calll	L90$pb
 ; DARWIN-32-PIC-NEXT: L90$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L90$pb(%eax), %eax
@@ -6048,7 +6048,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bxt01:
-; DARWIN-32-PIC: 	call	L91$pb
+; DARWIN-32-PIC: 	calll	L91$pb
 ; DARWIN-32-PIC-NEXT: L91$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L91$pb(%eax), %eax
@@ -6110,7 +6110,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat02:
-; DARWIN-32-PIC: 	call	L92$pb
+; DARWIN-32-PIC: 	calll	L92$pb
 ; DARWIN-32-PIC-NEXT: L92$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L92$pb(%eax), %eax
@@ -6166,7 +6166,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat03:
-; DARWIN-32-PIC: 	call	L93$pb
+; DARWIN-32-PIC: 	calll	L93$pb
 ; DARWIN-32-PIC-NEXT: L93$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L93$pb)+64(%eax), %eax
@@ -6214,7 +6214,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat04:
-; DARWIN-32-PIC: 	call	L94$pb
+; DARWIN-32-PIC: 	calll	L94$pb
 ; DARWIN-32-PIC-NEXT: L94$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L94$pb)+64(%eax), %eax
@@ -6271,7 +6271,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat05:
-; DARWIN-32-PIC: 	call	L95$pb
+; DARWIN-32-PIC: 	calll	L95$pb
 ; DARWIN-32-PIC-NEXT: L95$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_dptr-L95$pb(%eax), %eax
@@ -6322,7 +6322,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat06:
-; DARWIN-32-PIC: 	call	L96$pb
+; DARWIN-32-PIC: 	calll	L96$pb
 ; DARWIN-32-PIC-NEXT: L96$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L96$pb)+64(%eax), %eax
@@ -6369,7 +6369,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat07:
-; DARWIN-32-PIC: 	call	L97$pb
+; DARWIN-32-PIC: 	calll	L97$pb
 ; DARWIN-32-PIC-NEXT: L97$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L97$pb)+64(%eax), %eax
@@ -6425,7 +6425,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat08:
-; DARWIN-32-PIC: 	call	L98$pb
+; DARWIN-32-PIC: 	calll	L98$pb
 ; DARWIN-32-PIC-NEXT: L98$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	_lptr-L98$pb(%eax), %eax
@@ -6478,7 +6478,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam00:
-; DARWIN-32-PIC: 	call	L99$pb
+; DARWIN-32-PIC: 	calll	L99$pb
 ; DARWIN-32-PIC-NEXT: L99$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%ecx
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
@@ -6531,7 +6531,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam01:
-; DARWIN-32-PIC: 	call	L100$pb
+; DARWIN-32-PIC: 	calll	L100$pb
 ; DARWIN-32-PIC-NEXT: L100$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%ecx
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
@@ -6584,7 +6584,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bxm01:
-; DARWIN-32-PIC: 	call	L101$pb
+; DARWIN-32-PIC: 	calll	L101$pb
 ; DARWIN-32-PIC-NEXT: L101$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%ecx
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
@@ -6646,7 +6646,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam02:
-; DARWIN-32-PIC: 	call	L102$pb
+; DARWIN-32-PIC: 	calll	L102$pb
 ; DARWIN-32-PIC-NEXT: L102$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L102$pb(%eax), %ecx
@@ -6702,7 +6702,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam03:
-; DARWIN-32-PIC: 	call	L103$pb
+; DARWIN-32-PIC: 	calll	L103$pb
 ; DARWIN-32-PIC-NEXT: L103$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L103$pb)+262144(%eax), %eax
@@ -6750,7 +6750,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam04:
-; DARWIN-32-PIC: 	call	L104$pb
+; DARWIN-32-PIC: 	calll	L104$pb
 ; DARWIN-32-PIC-NEXT: L104$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L104$pb)+262144(%eax), %eax
@@ -6807,7 +6807,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam05:
-; DARWIN-32-PIC: 	call	L105$pb
+; DARWIN-32-PIC: 	calll	L105$pb
 ; DARWIN-32-PIC-NEXT: L105$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%ecx
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
@@ -6858,7 +6858,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam06:
-; DARWIN-32-PIC: 	call	L106$pb
+; DARWIN-32-PIC: 	calll	L106$pb
 ; DARWIN-32-PIC-NEXT: L106$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L106$pb)+262144(%eax), %eax
@@ -6905,7 +6905,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam07:
-; DARWIN-32-PIC: 	call	L107$pb
+; DARWIN-32-PIC: 	calll	L107$pb
 ; DARWIN-32-PIC-NEXT: L107$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L107$pb)+262144(%eax), %eax
@@ -6961,7 +6961,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam08:
-; DARWIN-32-PIC: 	call	L108$pb
+; DARWIN-32-PIC: 	calll	L108$pb
 ; DARWIN-32-PIC-NEXT: L108$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%ecx
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
@@ -7021,7 +7021,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat00:
-; DARWIN-32-PIC: 	call	L109$pb
+; DARWIN-32-PIC: 	calll	L109$pb
 ; DARWIN-32-PIC-NEXT: L109$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7082,7 +7082,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxt00:
-; DARWIN-32-PIC: 	call	L110$pb
+; DARWIN-32-PIC: 	calll	L110$pb
 ; DARWIN-32-PIC-NEXT: L110$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7143,7 +7143,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat01:
-; DARWIN-32-PIC: 	call	L111$pb
+; DARWIN-32-PIC: 	calll	L111$pb
 ; DARWIN-32-PIC-NEXT: L111$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7204,7 +7204,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxt01:
-; DARWIN-32-PIC: 	call	L112$pb
+; DARWIN-32-PIC: 	calll	L112$pb
 ; DARWIN-32-PIC-NEXT: L112$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7272,7 +7272,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat02:
-; DARWIN-32-PIC: 	call	L113$pb
+; DARWIN-32-PIC: 	calll	L113$pb
 ; DARWIN-32-PIC-NEXT: L113$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L113$pb(%eax), %eax
@@ -7336,7 +7336,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat03:
-; DARWIN-32-PIC: 	call	L114$pb
+; DARWIN-32-PIC: 	calll	L114$pb
 ; DARWIN-32-PIC-NEXT: L114$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7395,7 +7395,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat04:
-; DARWIN-32-PIC: 	call	L115$pb
+; DARWIN-32-PIC: 	calll	L115$pb
 ; DARWIN-32-PIC-NEXT: L115$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7461,7 +7461,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat05:
-; DARWIN-32-PIC: 	call	L116$pb
+; DARWIN-32-PIC: 	calll	L116$pb
 ; DARWIN-32-PIC-NEXT: L116$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7521,7 +7521,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat06:
-; DARWIN-32-PIC: 	call	L117$pb
+; DARWIN-32-PIC: 	calll	L117$pb
 ; DARWIN-32-PIC-NEXT: L117$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7580,7 +7580,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat07:
-; DARWIN-32-PIC: 	call	L118$pb
+; DARWIN-32-PIC: 	calll	L118$pb
 ; DARWIN-32-PIC-NEXT: L118$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7645,7 +7645,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat08:
-; DARWIN-32-PIC: 	call	L119$pb
+; DARWIN-32-PIC: 	calll	L119$pb
 ; DARWIN-32-PIC-NEXT: L119$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7706,7 +7706,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam00:
-; DARWIN-32-PIC: 	call	L120$pb
+; DARWIN-32-PIC: 	calll	L120$pb
 ; DARWIN-32-PIC-NEXT: L120$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7767,7 +7767,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxm00:
-; DARWIN-32-PIC: 	call	L121$pb
+; DARWIN-32-PIC: 	calll	L121$pb
 ; DARWIN-32-PIC-NEXT: L121$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7828,7 +7828,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam01:
-; DARWIN-32-PIC: 	call	L122$pb
+; DARWIN-32-PIC: 	calll	L122$pb
 ; DARWIN-32-PIC-NEXT: L122$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7889,7 +7889,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxm01:
-; DARWIN-32-PIC: 	call	L123$pb
+; DARWIN-32-PIC: 	calll	L123$pb
 ; DARWIN-32-PIC-NEXT: L123$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -7957,7 +7957,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam02:
-; DARWIN-32-PIC: 	call	L124$pb
+; DARWIN-32-PIC: 	calll	L124$pb
 ; DARWIN-32-PIC-NEXT: L124$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L124$pb(%eax), %eax
@@ -8021,7 +8021,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam03:
-; DARWIN-32-PIC: 	call	L125$pb
+; DARWIN-32-PIC: 	calll	L125$pb
 ; DARWIN-32-PIC-NEXT: L125$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -8080,7 +8080,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam04:
-; DARWIN-32-PIC: 	call	L126$pb
+; DARWIN-32-PIC: 	calll	L126$pb
 ; DARWIN-32-PIC-NEXT: L126$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -8146,7 +8146,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam05:
-; DARWIN-32-PIC: 	call	L127$pb
+; DARWIN-32-PIC: 	calll	L127$pb
 ; DARWIN-32-PIC-NEXT: L127$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -8206,7 +8206,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam06:
-; DARWIN-32-PIC: 	call	L128$pb
+; DARWIN-32-PIC: 	calll	L128$pb
 ; DARWIN-32-PIC-NEXT: L128$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -8265,7 +8265,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam07:
-; DARWIN-32-PIC: 	call	L129$pb
+; DARWIN-32-PIC: 	calll	L129$pb
 ; DARWIN-32-PIC-NEXT: L129$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -8330,7 +8330,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam08:
-; DARWIN-32-PIC: 	call	L130$pb
+; DARWIN-32-PIC: 	calll	L130$pb
 ; DARWIN-32-PIC-NEXT: L130$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
@@ -8376,25 +8376,25 @@
 
 ; LINUX-32-STATIC: lcallee:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	x
-; LINUX-32-STATIC-NEXT: 	call	x
-; LINUX-32-STATIC-NEXT: 	call	x
-; LINUX-32-STATIC-NEXT: 	call	x
-; LINUX-32-STATIC-NEXT: 	call	x
-; LINUX-32-STATIC-NEXT: 	call	x
-; LINUX-32-STATIC-NEXT: 	call	x
+; LINUX-32-STATIC-NEXT: 	calll	x
+; LINUX-32-STATIC-NEXT: 	calll	x
+; LINUX-32-STATIC-NEXT: 	calll	x
+; LINUX-32-STATIC-NEXT: 	calll	x
+; LINUX-32-STATIC-NEXT: 	calll	x
+; LINUX-32-STATIC-NEXT: 	calll	x
+; LINUX-32-STATIC-NEXT: 	calll	x
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: lcallee:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	x
-; LINUX-32-PIC-NEXT: 	call	x
-; LINUX-32-PIC-NEXT: 	call	x
-; LINUX-32-PIC-NEXT: 	call	x
-; LINUX-32-PIC-NEXT: 	call	x
-; LINUX-32-PIC-NEXT: 	call	x
-; LINUX-32-PIC-NEXT: 	call	x
+; LINUX-32-PIC-NEXT: 	calll	x
+; LINUX-32-PIC-NEXT: 	calll	x
+; LINUX-32-PIC-NEXT: 	calll	x
+; LINUX-32-PIC-NEXT: 	calll	x
+; LINUX-32-PIC-NEXT: 	calll	x
+; LINUX-32-PIC-NEXT: 	calll	x
+; LINUX-32-PIC-NEXT: 	calll	x
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -8412,37 +8412,37 @@
 
 ; DARWIN-32-STATIC: _lcallee:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_x
-; DARWIN-32-STATIC-NEXT: 	call	_x
-; DARWIN-32-STATIC-NEXT: 	call	_x
-; DARWIN-32-STATIC-NEXT: 	call	_x
-; DARWIN-32-STATIC-NEXT: 	call	_x
-; DARWIN-32-STATIC-NEXT: 	call	_x
-; DARWIN-32-STATIC-NEXT: 	call	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
+; DARWIN-32-STATIC-NEXT: 	calll	_x
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _lcallee:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_x$stub
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _lcallee:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
-; DARWIN-32-PIC-NEXT: 	call	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_x$stub
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -8507,25 +8507,25 @@
 
 ; LINUX-32-STATIC: dcallee:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	y
-; LINUX-32-STATIC-NEXT: 	call	y
-; LINUX-32-STATIC-NEXT: 	call	y
-; LINUX-32-STATIC-NEXT: 	call	y
-; LINUX-32-STATIC-NEXT: 	call	y
-; LINUX-32-STATIC-NEXT: 	call	y
-; LINUX-32-STATIC-NEXT: 	call	y
+; LINUX-32-STATIC-NEXT: 	calll	y
+; LINUX-32-STATIC-NEXT: 	calll	y
+; LINUX-32-STATIC-NEXT: 	calll	y
+; LINUX-32-STATIC-NEXT: 	calll	y
+; LINUX-32-STATIC-NEXT: 	calll	y
+; LINUX-32-STATIC-NEXT: 	calll	y
+; LINUX-32-STATIC-NEXT: 	calll	y
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: dcallee:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	y
-; LINUX-32-PIC-NEXT: 	call	y
-; LINUX-32-PIC-NEXT: 	call	y
-; LINUX-32-PIC-NEXT: 	call	y
-; LINUX-32-PIC-NEXT: 	call	y
-; LINUX-32-PIC-NEXT: 	call	y
-; LINUX-32-PIC-NEXT: 	call	y
+; LINUX-32-PIC-NEXT: 	calll	y
+; LINUX-32-PIC-NEXT: 	calll	y
+; LINUX-32-PIC-NEXT: 	calll	y
+; LINUX-32-PIC-NEXT: 	calll	y
+; LINUX-32-PIC-NEXT: 	calll	y
+; LINUX-32-PIC-NEXT: 	calll	y
+; LINUX-32-PIC-NEXT: 	calll	y
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -8543,37 +8543,37 @@
 
 ; DARWIN-32-STATIC: _dcallee:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_y
-; DARWIN-32-STATIC-NEXT: 	call	_y
-; DARWIN-32-STATIC-NEXT: 	call	_y
-; DARWIN-32-STATIC-NEXT: 	call	_y
-; DARWIN-32-STATIC-NEXT: 	call	_y
-; DARWIN-32-STATIC-NEXT: 	call	_y
-; DARWIN-32-STATIC-NEXT: 	call	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
+; DARWIN-32-STATIC-NEXT: 	calll	_y
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _dcallee:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_y$stub
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _dcallee:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
-; DARWIN-32-PIC-NEXT: 	call	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_y$stub
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -8644,7 +8644,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _address:
-; DARWIN-32-PIC: 	call	L133$pb
+; DARWIN-32-PIC: 	calll	L133$pb
 ; DARWIN-32-PIC-NEXT: L133$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_callee$non_lazy_ptr-L133$pb(%eax), %eax
@@ -8693,7 +8693,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _laddress:
-; DARWIN-32-PIC: 	call	L134$pb
+; DARWIN-32-PIC: 	calll	L134$pb
 ; DARWIN-32-PIC-NEXT: L134$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_lcallee-L134$pb(%eax), %eax
@@ -8740,7 +8740,7 @@
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _daddress:
-; DARWIN-32-PIC: 	call	L135$pb
+; DARWIN-32-PIC: 	calll	L135$pb
 ; DARWIN-32-PIC-NEXT: L135$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	leal	_dcallee-L135$pb(%eax), %eax
@@ -8771,15 +8771,15 @@
 
 ; LINUX-32-STATIC: caller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	callee
-; LINUX-32-STATIC-NEXT: 	call	callee
+; LINUX-32-STATIC-NEXT: 	calll	callee
+; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: caller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	callee
-; LINUX-32-PIC-NEXT: 	call	callee
+; LINUX-32-PIC-NEXT: 	calll	callee
+; LINUX-32-PIC-NEXT: 	calll	callee
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -8792,22 +8792,22 @@
 
 ; DARWIN-32-STATIC: _caller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_callee
-; DARWIN-32-STATIC-NEXT: 	call	_callee
+; DARWIN-32-STATIC-NEXT: 	calll	_callee
+; DARWIN-32-STATIC-NEXT: 	calll	_callee
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _caller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_callee$stub
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_callee$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_callee$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_callee$stub
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _caller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	L_callee$stub
-; DARWIN-32-PIC-NEXT: 	call	L_callee$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_callee$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_callee$stub
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -8845,15 +8845,15 @@
 
 ; LINUX-32-STATIC: dcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	dcallee
-; LINUX-32-STATIC-NEXT: 	call	dcallee
+; LINUX-32-STATIC-NEXT: 	calll	dcallee
+; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: dcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	dcallee
-; LINUX-32-PIC-NEXT: 	call	dcallee
+; LINUX-32-PIC-NEXT: 	calll	dcallee
+; LINUX-32-PIC-NEXT: 	calll	dcallee
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -8866,22 +8866,22 @@
 
 ; DARWIN-32-STATIC: _dcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_dcallee
-; DARWIN-32-STATIC-NEXT: 	call	_dcallee
+; DARWIN-32-STATIC-NEXT: 	calll	_dcallee
+; DARWIN-32-STATIC-NEXT: 	calll	_dcallee
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _dcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	_dcallee
-; DARWIN-32-DYNAMIC-NEXT: 	call	_dcallee
+; DARWIN-32-DYNAMIC-NEXT: 	calll	_dcallee
+; DARWIN-32-DYNAMIC-NEXT: 	calll	_dcallee
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _dcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	_dcallee
-; DARWIN-32-PIC-NEXT: 	call	_dcallee
+; DARWIN-32-PIC-NEXT: 	calll	_dcallee
+; DARWIN-32-PIC-NEXT: 	calll	_dcallee
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -8919,15 +8919,15 @@
 
 ; LINUX-32-STATIC: lcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	lcallee
-; LINUX-32-STATIC-NEXT: 	call	lcallee
+; LINUX-32-STATIC-NEXT: 	calll	lcallee
+; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: lcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	lcallee
-; LINUX-32-PIC-NEXT: 	call	lcallee
+; LINUX-32-PIC-NEXT: 	calll	lcallee
+; LINUX-32-PIC-NEXT: 	calll	lcallee
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -8940,22 +8940,22 @@
 
 ; DARWIN-32-STATIC: _lcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_lcallee
-; DARWIN-32-STATIC-NEXT: 	call	_lcallee
+; DARWIN-32-STATIC-NEXT: 	calll	_lcallee
+; DARWIN-32-STATIC-NEXT: 	calll	_lcallee
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _lcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	_lcallee
-; DARWIN-32-DYNAMIC-NEXT: 	call	_lcallee
+; DARWIN-32-DYNAMIC-NEXT: 	calll	_lcallee
+; DARWIN-32-DYNAMIC-NEXT: 	calll	_lcallee
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _lcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	_lcallee
-; DARWIN-32-PIC-NEXT: 	call	_lcallee
+; DARWIN-32-PIC-NEXT: 	calll	_lcallee
+; DARWIN-32-PIC-NEXT: 	calll	_lcallee
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -8991,13 +8991,13 @@
 
 ; LINUX-32-STATIC: tailcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	callee
+; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: tailcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	callee
+; LINUX-32-PIC-NEXT: 	calll	callee
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9009,19 +9009,19 @@
 
 ; DARWIN-32-STATIC: _tailcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_callee
+; DARWIN-32-STATIC-NEXT: 	calll	_callee
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _tailcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	L_callee$stub
+; DARWIN-32-DYNAMIC-NEXT: 	calll	L_callee$stub
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _tailcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	L_callee$stub
+; DARWIN-32-PIC-NEXT: 	calll	L_callee$stub
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -9054,13 +9054,13 @@
 
 ; LINUX-32-STATIC: dtailcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	dcallee
+; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: dtailcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	dcallee
+; LINUX-32-PIC-NEXT: 	calll	dcallee
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9072,19 +9072,19 @@
 
 ; DARWIN-32-STATIC: _dtailcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_dcallee
+; DARWIN-32-STATIC-NEXT: 	calll	_dcallee
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _dtailcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	_dcallee
+; DARWIN-32-DYNAMIC-NEXT: 	calll	_dcallee
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _dtailcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	_dcallee
+; DARWIN-32-PIC-NEXT: 	calll	_dcallee
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -9117,13 +9117,13 @@
 
 ; LINUX-32-STATIC: ltailcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	lcallee
+; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ltailcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	lcallee
+; LINUX-32-PIC-NEXT: 	calll	lcallee
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9135,19 +9135,19 @@
 
 ; DARWIN-32-STATIC: _ltailcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	_lcallee
+; DARWIN-32-STATIC-NEXT: 	calll	_lcallee
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ltailcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	_lcallee
+; DARWIN-32-DYNAMIC-NEXT: 	calll	_lcallee
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ltailcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	_lcallee
+; DARWIN-32-PIC-NEXT: 	calll	_lcallee
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -9184,15 +9184,15 @@
 
 ; LINUX-32-STATIC: icaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	*ifunc
-; LINUX-32-STATIC-NEXT: 	call	*ifunc
+; LINUX-32-STATIC-NEXT: 	calll	*ifunc
+; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: icaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	*ifunc
-; LINUX-32-PIC-NEXT: 	call	*ifunc
+; LINUX-32-PIC-NEXT: 	calll	*ifunc
+; LINUX-32-PIC-NEXT: 	calll	*ifunc
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9206,8 +9206,8 @@
 
 ; DARWIN-32-STATIC: _icaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	*_ifunc
-; DARWIN-32-STATIC-NEXT: 	call	*_ifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_ifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_ifunc
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
@@ -9215,8 +9215,8 @@
 ; DARWIN-32-DYNAMIC: 	pushl	%esi
 ; DARWIN-32-DYNAMIC-NEXT: 	subl	$8, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ifunc$non_lazy_ptr, %esi
-; DARWIN-32-DYNAMIC-NEXT: 	call	*(%esi)
-; DARWIN-32-DYNAMIC-NEXT: 	call	*(%esi)
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*(%esi)
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$8, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	popl	%esi
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
@@ -9224,12 +9224,12 @@
 ; DARWIN-32-PIC: _icaller:
 ; DARWIN-32-PIC: 	pushl	%esi
 ; DARWIN-32-PIC-NEXT: 	subl	$8, %esp
-; DARWIN-32-PIC-NEXT: 	call	L142$pb
+; DARWIN-32-PIC-NEXT: 	calll	L142$pb
 ; DARWIN-32-PIC-NEXT: L142$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ifunc$non_lazy_ptr-L142$pb(%eax), %esi
-; DARWIN-32-PIC-NEXT: 	call	*(%esi)
-; DARWIN-32-PIC-NEXT: 	call	*(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-PIC-NEXT: 	addl	$8, %esp
 ; DARWIN-32-PIC-NEXT: 	popl	%esi
 ; DARWIN-32-PIC-NEXT: 	ret
@@ -9273,15 +9273,15 @@
 
 ; LINUX-32-STATIC: dicaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	*difunc
-; LINUX-32-STATIC-NEXT: 	call	*difunc
+; LINUX-32-STATIC-NEXT: 	calll	*difunc
+; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: dicaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	*difunc
-; LINUX-32-PIC-NEXT: 	call	*difunc
+; LINUX-32-PIC-NEXT: 	calll	*difunc
+; LINUX-32-PIC-NEXT: 	calll	*difunc
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9295,26 +9295,26 @@
 
 ; DARWIN-32-STATIC: _dicaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	*_difunc
-; DARWIN-32-STATIC-NEXT: 	call	*_difunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_difunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_difunc
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _dicaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	*_difunc
-; DARWIN-32-DYNAMIC-NEXT: 	call	*_difunc
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*_difunc
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*_difunc
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _dicaller:
 ; DARWIN-32-PIC: 	pushl	%esi
 ; DARWIN-32-PIC-NEXT: 	subl	$8, %esp
-; DARWIN-32-PIC-NEXT: 	call	L143$pb
+; DARWIN-32-PIC-NEXT: 	calll	L143$pb
 ; DARWIN-32-PIC-NEXT: L143$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%esi
-; DARWIN-32-PIC-NEXT: 	call	*_difunc-L143$pb(%esi)
-; DARWIN-32-PIC-NEXT: 	call	*_difunc-L143$pb(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*_difunc-L143$pb(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*_difunc-L143$pb(%esi)
 ; DARWIN-32-PIC-NEXT: 	addl	$8, %esp
 ; DARWIN-32-PIC-NEXT: 	popl	%esi
 ; DARWIN-32-PIC-NEXT: 	ret
@@ -9355,15 +9355,15 @@
 
 ; LINUX-32-STATIC: licaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	*lifunc
-; LINUX-32-STATIC-NEXT: 	call	*lifunc
+; LINUX-32-STATIC-NEXT: 	calll	*lifunc
+; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: licaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	*lifunc
-; LINUX-32-PIC-NEXT: 	call	*lifunc
+; LINUX-32-PIC-NEXT: 	calll	*lifunc
+; LINUX-32-PIC-NEXT: 	calll	*lifunc
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9376,26 +9376,26 @@
 
 ; DARWIN-32-STATIC: _licaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	*_lifunc
-; DARWIN-32-STATIC-NEXT: 	call	*_lifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_lifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_lifunc
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _licaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	*_lifunc
-; DARWIN-32-DYNAMIC-NEXT: 	call	*_lifunc
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*_lifunc
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*_lifunc
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _licaller:
 ; DARWIN-32-PIC: 	pushl	%esi
 ; DARWIN-32-PIC-NEXT: 	subl	$8, %esp
-; DARWIN-32-PIC-NEXT: 	call	L144$pb
+; DARWIN-32-PIC-NEXT: 	calll	L144$pb
 ; DARWIN-32-PIC-NEXT: L144$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%esi
-; DARWIN-32-PIC-NEXT: 	call	*_lifunc-L144$pb(%esi)
-; DARWIN-32-PIC-NEXT: 	call	*_lifunc-L144$pb(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*_lifunc-L144$pb(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*_lifunc-L144$pb(%esi)
 ; DARWIN-32-PIC-NEXT: 	addl	$8, %esp
 ; DARWIN-32-PIC-NEXT: 	popl	%esi
 ; DARWIN-32-PIC-NEXT: 	ret
@@ -9436,15 +9436,15 @@
 
 ; LINUX-32-STATIC: itailcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	*ifunc
-; LINUX-32-STATIC-NEXT: 	call	*ifunc
+; LINUX-32-STATIC-NEXT: 	calll	*ifunc
+; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: itailcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	*ifunc
-; LINUX-32-PIC-NEXT: 	call	*ifunc
+; LINUX-32-PIC-NEXT: 	calll	*ifunc
+; LINUX-32-PIC-NEXT: 	calll	*ifunc
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9458,8 +9458,8 @@
 
 ; DARWIN-32-STATIC: _itailcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	*_ifunc
-; DARWIN-32-STATIC-NEXT: 	call	*_ifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_ifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_ifunc
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
@@ -9467,8 +9467,8 @@
 ; DARWIN-32-DYNAMIC: 	pushl	%esi
 ; DARWIN-32-DYNAMIC-NEXT: 	subl	$8, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ifunc$non_lazy_ptr, %esi
-; DARWIN-32-DYNAMIC-NEXT: 	call	*(%esi)
-; DARWIN-32-DYNAMIC-NEXT: 	call	*(%esi)
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*(%esi)
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$8, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	popl	%esi
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
@@ -9476,12 +9476,12 @@
 ; DARWIN-32-PIC: _itailcaller:
 ; DARWIN-32-PIC: 	pushl	%esi
 ; DARWIN-32-PIC-NEXT: 	subl	$8, %esp
-; DARWIN-32-PIC-NEXT: 	call	L145$pb
+; DARWIN-32-PIC-NEXT: 	calll	L145$pb
 ; DARWIN-32-PIC-NEXT: L145$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
 ; DARWIN-32-PIC-NEXT: 	movl	L_ifunc$non_lazy_ptr-L145$pb(%eax), %esi
-; DARWIN-32-PIC-NEXT: 	call	*(%esi)
-; DARWIN-32-PIC-NEXT: 	call	*(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
+; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-PIC-NEXT: 	addl	$8, %esp
 ; DARWIN-32-PIC-NEXT: 	popl	%esi
 ; DARWIN-32-PIC-NEXT: 	ret
@@ -9522,13 +9522,13 @@
 
 ; LINUX-32-STATIC: ditailcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	*difunc
+; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ditailcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	*difunc
+; LINUX-32-PIC-NEXT: 	calll	*difunc
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9541,22 +9541,22 @@
 
 ; DARWIN-32-STATIC: _ditailcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	*_difunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_difunc
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ditailcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	*_difunc
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*_difunc
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ditailcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	L146$pb
+; DARWIN-32-PIC-NEXT: 	calll	L146$pb
 ; DARWIN-32-PIC-NEXT: L146$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	call	*_difunc-L146$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	calll	*_difunc-L146$pb(%eax)
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -9589,13 +9589,13 @@
 
 ; LINUX-32-STATIC: litailcaller:
 ; LINUX-32-STATIC: 	subl	$4, %esp
-; LINUX-32-STATIC-NEXT: 	call	*lifunc
+; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: litailcaller:
 ; LINUX-32-PIC: 	subl	$4, %esp
-; LINUX-32-PIC-NEXT: 	call	*lifunc
+; LINUX-32-PIC-NEXT: 	calll	*lifunc
 ; LINUX-32-PIC-NEXT: 	addl	$4, %esp
 ; LINUX-32-PIC-NEXT: 	ret
 
@@ -9607,22 +9607,22 @@
 
 ; DARWIN-32-STATIC: _litailcaller:
 ; DARWIN-32-STATIC: 	subl	$12, %esp
-; DARWIN-32-STATIC-NEXT: 	call	*_lifunc
+; DARWIN-32-STATIC-NEXT: 	calll	*_lifunc
 ; DARWIN-32-STATIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _litailcaller:
 ; DARWIN-32-DYNAMIC: 	subl	$12, %esp
-; DARWIN-32-DYNAMIC-NEXT: 	call	*_lifunc
+; DARWIN-32-DYNAMIC-NEXT: 	calll	*_lifunc
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _litailcaller:
 ; DARWIN-32-PIC: 	subl	$12, %esp
-; DARWIN-32-PIC-NEXT: 	call	L147$pb
+; DARWIN-32-PIC-NEXT: 	calll	L147$pb
 ; DARWIN-32-PIC-NEXT: L147$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	call	*_lifunc-L147$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	calll	*_lifunc-L147$pb(%eax)
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 

Modified: llvm/trunk/test/CodeGen/X86/dll-linkage.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dll-linkage.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dll-linkage.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dll-linkage.ll Wed Sep 22 00:49:14 2010
@@ -3,7 +3,7 @@
 declare dllimport void @foo()
 
 define void @bar() nounwind {
-; CHECK: call	*__imp__foo
+; CHECK: calll	*__imp__foo
   call void @foo()
   ret void
 }

Modified: llvm/trunk/test/CodeGen/X86/dollar-name.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dollar-name.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dollar-name.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dollar-name.ll Wed Sep 22 00:49:14 2010
@@ -7,7 +7,7 @@
 define i32 @"$foo"() nounwind {
 ; CHECK: movl	($bar),
 ; CHECK: addl	($qux),
-; CHECK: call	($hen)
+; CHECK: calll	($hen)
   %m = load i32* @"$bar"
   %n = load i32* @"$qux"
   %t = add i32 %m, %n

Modified: llvm/trunk/test/CodeGen/X86/ghc-cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ghc-cc.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ghc-cc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ghc-cc.ll Wed Sep 22 00:49:14 2010
@@ -11,9 +11,9 @@
 entry:
   ; CHECK: movl {{[0-9]*}}(%esp), %ebx
   ; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp
-  ; CHECK-NEXT: call addtwo
+  ; CHECK-NEXT: calll addtwo
   %0 = call cc 10 i32 @addtwo(i32 %a, i32 %b)
-  ; CHECK: call foo
+  ; CHECK: calll foo
   call void @foo() nounwind
   ret void
 }

Modified: llvm/trunk/test/CodeGen/X86/memmove-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-0.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memmove-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-0.ll Wed Sep 22 00:49:14 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call	memcpy}
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {calll	memcpy}
 
 declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
 

Modified: llvm/trunk/test/CodeGen/X86/memmove-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-1.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memmove-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-1.ll Wed Sep 22 00:49:14 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call	memmove}
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {calll	memmove}
 
 declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
 

Modified: llvm/trunk/test/CodeGen/X86/memmove-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-3.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memmove-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-3.ll Wed Sep 22 00:49:14 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call	memmove}
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {calll	memmove}
 
 declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
 

Modified: llvm/trunk/test/CodeGen/X86/memset-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memset-2.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memset-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memset-2.ll Wed Sep 22 00:49:14 2010
@@ -5,7 +5,7 @@
 define fastcc void @t1() nounwind {
 entry:
 ; CHECK: t1:
-; CHECK: call _memset
+; CHECK: calll _memset
   call void @llvm.memset.i32( i8* null, i8 0, i32 188, i32 1 ) nounwind
   unreachable
 }
@@ -13,7 +13,7 @@
 define fastcc void @t2(i8 signext %c) nounwind {
 entry:
 ; CHECK: t2:
-; CHECK: call _memset
+; CHECK: calll _memset
   call void @llvm.memset.i32( i8* undef, i8 %c, i32 76, i32 1 ) nounwind
   unreachable
 }

Modified: llvm/trunk/test/CodeGen/X86/mingw-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mingw-alloca.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mingw-alloca.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mingw-alloca.ll Wed Sep 22 00:49:14 2010
@@ -6,7 +6,7 @@
 define void @foo1(i32 %N) nounwind {
 entry:
 ; CHECK: _foo1:
-; CHECK: call __alloca
+; CHECK: calll __alloca
 	%tmp14 = alloca i32, i32 %N		; <i32*> [#uses=1]
 	call void @bar1( i32* %tmp14 )
 	ret void
@@ -19,7 +19,7 @@
 ; CHECK: _foo2:
 ; CHECK: andl $-16, %esp
 ; CHECK: pushl %eax
-; CHECK: call __alloca
+; CHECK: calll __alloca
 ; CHECK: movl	8028(%esp), %eax
 	%A2 = alloca [2000 x i32], align 16		; <[2000 x i32]*> [#uses=1]
 	%A2.sub = getelementptr [2000 x i32]* %A2, i32 0, i32 0		; <i32*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/movgs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movgs.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movgs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movgs.ll Wed Sep 22 00:49:14 2010
@@ -27,7 +27,7 @@
 ; rdar://8453210
 ; X32: test2:
 ; X32: movl	{{.*}}(%esp), %eax
-; X32: call	*%gs:(%eax)
+; X32: calll	*%gs:(%eax)
 
 ; X64: test2:
 ; X64: callq	*%gs:(%rdi)

Modified: llvm/trunk/test/CodeGen/X86/pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pic.ll Wed Sep 22 00:49:14 2010
@@ -12,7 +12,7 @@
     ret void
     
 ; LINUX:    test0:
-; LINUX:	call	.L0$pb
+; LINUX:	calll	.L0$pb
 ; LINUX-NEXT: .L0$pb:
 ; LINUX-NEXT:	popl
 ; LINUX:	addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L0$pb),
@@ -34,7 +34,7 @@
     ret void
     
 ; LINUX: test1:
-; LINUX:	call	.L1$pb
+; LINUX:	calll	.L1$pb
 ; LINUX-NEXT: .L1$pb:
 ; LINUX-NEXT:	popl
 ; LINUX:	addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), %eax
@@ -54,12 +54,12 @@
 ; LINUX: test2:
 ; LINUX: 	pushl	%ebx
 ; LINUX-NEXT: 	subl	$8, %esp
-; LINUX-NEXT: 	call	.L2$pb
+; LINUX-NEXT: 	calll	.L2$pb
 ; LINUX-NEXT: .L2$pb:
 ; LINUX-NEXT: 	popl	%ebx
 ; LINUX: 	addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %ebx
 ; LINUX: 	movl	$40, (%esp)
-; LINUX: 	call	malloc at PLT
+; LINUX: 	calll	malloc at PLT
 ; LINUX: 	addl	$8, %esp
 ; LINUX: 	popl	%ebx
 ; LINUX: 	ret
@@ -75,13 +75,13 @@
     call void(...)* %tmp1()
     ret void
 ; LINUX: test3:
-; LINUX: 	call	.L3$pb
+; LINUX: 	calll	.L3$pb
 ; LINUX-NEXT: .L3$pb:
 ; LINUX: 	popl
 ; LINUX: 	addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %[[REG3:e..]]
 ; LINUX: 	movl	pfoo at GOT(%[[REG3]]),
-; LINUX: 	call	afoo at PLT
-; LINUX: 	call	*
+; LINUX: 	calll	afoo at PLT
+; LINUX: 	calll	*
 }
 
 declare void(...)* @afoo(...)
@@ -91,10 +91,10 @@
     call void(...)* @foo()
     ret void
 ; LINUX: test4:
-; LINUX: call	.L4$pb
+; LINUX: calll	.L4$pb
 ; LINUX: popl	%ebx
 ; LINUX: addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx
-; LINUX: call	foo at PLT
+; LINUX: calll	foo at PLT
 }
 
 declare void @foo(...)
@@ -112,7 +112,7 @@
     ret void
     
 ; LINUX: test5:
-; LINUX: 	call	.L5$pb
+; LINUX: 	calll	.L5$pb
 ; LINUX-NEXT: .L5$pb:
 ; LINUX-NEXT: 	popl	%eax
 ; LINUX: 	addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %eax
@@ -134,7 +134,7 @@
 ; LINUX: .LCPI6_0:
 
 ; LINUX: test6:
-; LINUX:    call .L6$pb
+; LINUX:    calll .L6$pb
 ; LINUX: .L6$pb:
 ; LINUX:    addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), 
 ; LINUX:    fldl	.LCPI6_0 at GOTOFF(
@@ -186,7 +186,7 @@
     ret void
     
 ; LINUX: test7:
-; LINUX:   call	.L7$pb
+; LINUX:   calll	.L7$pb
 ; LINUX: .L7$pb:
 ; LINUX:   addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb),
 ; LINUX:   .LJTI7_0 at GOTOFF(

Modified: llvm/trunk/test/CodeGen/X86/sibcall-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall-3.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sibcall-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sibcall-3.ll Wed Sep 22 00:49:14 2010
@@ -3,7 +3,7 @@
 
 define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
 ; CHECK: t1:
-; CHECK: call 0
+; CHECK: calll 0
   tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
   ret void
 }

Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sibcall.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sibcall.ll Wed Sep 22 00:49:14 2010
@@ -45,7 +45,7 @@
 define void @t4(void (i32)* nocapture %x) nounwind ssp {
 entry:
 ; 32: t4:
-; 32: call *
+; 32: calll *
 ; FIXME: gcc can generate a tailcall for this. But it's tricky.
 
 ; 64: t4:
@@ -71,7 +71,7 @@
 define i32 @t6(i32 %x) nounwind ssp {
 entry:
 ; 32: t6:
-; 32: call {{_?}}t6
+; 32: calll {{_?}}t6
 ; 32: jmp {{_?}}bar
 
 ; 64: t6:
@@ -108,7 +108,7 @@
 define signext i16 @t8() nounwind ssp {
 entry:
 ; 32: t8:
-; 32: call {{_?}}bar3
+; 32: calll {{_?}}bar3
 
 ; 64: t8:
 ; 64: callq {{_?}}bar3
@@ -121,7 +121,7 @@
 define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
 entry:
 ; 32: t9:
-; 32: call *
+; 32: calll *
 
 ; 64: t9:
 ; 64: callq *
@@ -133,7 +133,7 @@
 define void @t10() nounwind ssp {
 entry:
 ; 32: t10:
-; 32: call
+; 32: calll
 
 ; 64: t10:
 ; 64: callq
@@ -205,12 +205,12 @@
 define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
 ; 32: t13:
 ; 32-NOT: jmp
-; 32: call
+; 32: calll
 ; 32: ret
 
 ; 64: t13:
 ; 64-NOT: jmp
-; 64: call
+; 64: callq
 ; 64: ret
 entry:
   %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind
@@ -248,7 +248,7 @@
 
 define void @t15(%struct.foo* noalias sret %agg.result) nounwind  {
 ; 32: t15:
-; 32: call {{_?}}f
+; 32: calll {{_?}}f
 ; 32: ret $4
 
 ; 64: t15:
@@ -263,7 +263,7 @@
 define void @t16() nounwind ssp {
 entry:
 ; 32: t16:
-; 32: call {{_?}}bar4
+; 32: calll {{_?}}bar4
 ; 32: fstp
 
 ; 64: t16:
@@ -293,7 +293,7 @@
 define void @t18() nounwind ssp {
 entry:
 ; 32: t18:
-; 32: call {{_?}}bar6
+; 32: calll {{_?}}bar6
 ; 32: fstp %st(0)
 
 ; 64: t18:
@@ -309,7 +309,7 @@
 entry:
 ; CHECK: t19:
 ; CHECK: andl $-32
-; CHECK: call {{_?}}foo
+; CHECK: calll {{_?}}foo
   tail call void @foo() nounwind
   ret void
 }
@@ -323,7 +323,7 @@
 define double @t20(double %x) nounwind {
 entry:
 ; 32: t20:
-; 32: call {{_?}}foo20
+; 32: calll {{_?}}foo20
 ; 32: fldl (%esp)
 
 ; 64: t20:

Modified: llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tailcall-stackalign.ll Wed Sep 22 00:49:14 2010
@@ -19,5 +19,5 @@
  ret i32 0
 }
 
-; CHECK: call tailcaller
+; CHECK: calll tailcaller
 ; CHECK-NEXT: subl $12

Modified: llvm/trunk/test/CodeGen/X86/unaligned-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unaligned-load.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/unaligned-load.ll (original)
+++ llvm/trunk/test/CodeGen/X86/unaligned-load.ll Wed Sep 22 00:49:14 2010
@@ -13,7 +13,7 @@
 bb:
   %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0
   call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1)
-; I386: call {{_?}}memcpy
+; I386: calll {{_?}}memcpy
 
 ; CORE2: movabsq
 ; CORE2: movabsq

Modified: llvm/trunk/test/CodeGen/X86/win_chkstk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win_chkstk.ll?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/win_chkstk.ll (original)
+++ llvm/trunk/test/CodeGen/X86/win_chkstk.ll Wed Sep 22 00:49:14 2010
@@ -12,10 +12,10 @@
 ; Stack allocation >= 4096 bytes will require call to __chkstk in the Windows ABI.
 define i32 @main4k() nounwind {
 entry:
-; WIN_X32:    call __chkstk
+; WIN_X32:    calll __chkstk
 ; WIN_X64:    call __chkstk
-; MINGW_X32:  call __alloca
-; MINGW_X64:  call _alloca
+; MINGW_X32:  calll __alloca
+; MINGW_X64:  calll _alloca
 ; LINUX-NOT:  call __chkstk
   %array4096 = alloca [4096 x i8], align 16       ; <[4096 x i8]*> [#uses=0]
   ret i32 0
@@ -26,7 +26,7 @@
 define i32 @main128() nounwind {
 entry:
 ; WIN_X32:       # BB#0:
-; WIN_X32-NOT:   call __chkstk
+; WIN_X32-NOT:   calll __chkstk
 ; WIN_X32:       ret
 
 ; WIN_X64:       # BB#0:

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 22 00:49:14 2010
@@ -561,4 +561,6 @@
 jmp	$0x7ace,$0x7ace
 ljmp	$0x7ace,$0x7ace
 
-
+// rdar://8456370
+// CHECK: calll a
+ calll a

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_operands.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_operands.s?rev=114534&r1=114533&r2=114534&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_operands.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_operands.s Wed Sep 22 00:49:14 2010
@@ -46,11 +46,11 @@
         addl $1, 1(,%ebx,(2+2))
 
 # '*'
-# CHECK: call a
+# CHECK: calll a
         call a
-# CHECK: call *%eax
+# CHECK: calll *%eax
         call *%eax
-# CHECK: call *4(%eax)
+# CHECK: calll *4(%eax)
         call *4(%eax)
 
 # CHECK: movl	%gs:8, %eax



From eli.friedman at gmail.com  Wed Sep 22 01:16:06 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 21 Sep 2010 23:16:06 -0700
Subject: [llvm-commits] [llvm] r114534 - in /llvm/trunk: lib/Target/X86/
 lib/Target/X86/AsmParser/ test/CodeGen/X86/ test/MC/AsmParser/X86/
In-Reply-To: <20100922054914.E4D562A6C12C@llvm.org>
References: <20100922054914.E4D562A6C12C@llvm.org>
Message-ID: <AANLkTikAggNyMKcao8MCJaYWkcYfpc0AY4nNY852NHCE@mail.gmail.com>

On Tue, Sep 21, 2010 at 10:49 PM, Chris Lattner <sabre at nondot.org> wrote:
> Author: lattner
> Date: Wed Sep 22 00:49:14 2010
> New Revision: 114534
>
> URL: http://llvm.org/viewvc/llvm-project?rev=114534&view=rev
> Log:
> Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
> x86-32: 32-bit calls were named "call" not "calll". ?64-bit calls were correctly
> named "callq", so this only impacted x86-32.
>
> This fixes rdar://8456370 - llvm-mc rejects 'calll'
>
> This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
> I will file a bugzilla.

What's the assembly size impact of the "l"s?  :)

-Eli


From sabre at nondot.org  Wed Sep 22 01:18:22 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Sep 2010 23:18:22 -0700
Subject: [llvm-commits] [llvm] r114534 - in /llvm/trunk: lib/Target/X86/
	lib/Target/X86/AsmParser/ test/CodeGen/X86/ test/MC/AsmParser/X86/
In-Reply-To: <AANLkTikAggNyMKcao8MCJaYWkcYfpc0AY4nNY852NHCE@mail.gmail.com>
References: <20100922054914.E4D562A6C12C@llvm.org>
	<AANLkTikAggNyMKcao8MCJaYWkcYfpc0AY4nNY852NHCE@mail.gmail.com>
Message-ID: <938209E6-DF59-4B16-AC23-FCD3156AF60A@nondot.org>


On Sep 21, 2010, at 11:16 PM, Eli Friedman wrote:

> On Tue, Sep 21, 2010 at 10:49 PM, Chris Lattner <sabre at nondot.org> wrote:
>> Author: lattner
>> Date: Wed Sep 22 00:49:14 2010
>> New Revision: 114534
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=114534&view=rev
>> Log:
>> Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
>> x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
>> named "callq", so this only impacted x86-32.
>> 
>> This fixes rdar://8456370 - llvm-mc rejects 'calll'
>> 
>> This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
>> I will file a bugzilla.
> 
> What's the assembly size impact of the "l"s?  :)

Hehe, everyone should use an integrated assembler ;-)

-Chris

From sabre at nondot.org  Wed Sep 22 01:26:39 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 06:26:39 -0000
Subject: [llvm-commits] [llvm] r114536 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100922062639.9EF6A2A6C12C@llvm.org>

Author: lattner
Date: Wed Sep 22 01:26:39 2010
New Revision: 114536

URL: http://llvm.org/viewvc/llvm-project?rev=114536&view=rev
Log:
fix rdar://8456371 - Handle commutable instructions written backward.


Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114536&r1=114535&r2=114536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 22 01:26:39 2010
@@ -911,6 +911,16 @@
     Operands.erase(Operands.begin() + 2);
   }
 
+  // FIXME: Hack to handle "f{mul*,add*} st(0), $op" the same as
+  // "f{mul*,add*} $op", since they commute.
+  if ((Name.startswith("fmul") || Name.startswith("fadd")) &&
+      Operands.size() == 3 &&
+      static_cast<X86Operand*>(Operands[1])->isReg() &&
+      static_cast<X86Operand*>(Operands[1])->getReg() == X86::ST0) {
+    delete Operands[1];
+    Operands.erase(Operands.begin() + 1);
+  }
+  
   // FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
   // B".
   if (Name.startswith("imul") && Operands.size() == 3 &&

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114536&r1=114535&r2=114536&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Wed Sep 22 01:26:39 2010
@@ -353,3 +353,11 @@
 mov %rdx, %cr15
 // CHECK: movq	%rdx, %cr15
 // CHECK: encoding: [0x44,0x0f,0x22,0xfa]
+
+// rdar://8456371 - Handle commutable instructions written backward.
+// CHECK: 	faddp	%st(1)
+// CHECK:	fmulp	%st(2)
+faddp %st, %st(1)
+fmulp %st, %st(2)
+
+



From baldrick at free.fr  Wed Sep 22 01:44:20 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 22 Sep 2010 08:44:20 +0200
Subject: [llvm-commits] [llvm] r114488
	-	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
In-Reply-To: <20100921215427.BFE152A6C12C@llvm.org>
References: <20100921215427.BFE152A6C12C@llvm.org>
Message-ID: <4C99A5C4.5030505@free.fr>

Hi Bob,

> Move a sign-extend or a zero-extend of a load to the same basic block as the
> load when the type of the load is not legal, even if truncates are not free.
> The load is going to be legalized to an extending load anyway.

an extending load is not used for illegal integer types that are too large
(eg: i512).  Instead a pair of half-sized loads is used.

Ciao,

Duncan.

From foldr at codedgers.com  Wed Sep 22 04:00:35 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 22 Sep 2010 09:00:35 -0000
Subject: [llvm-commits] [llvm] r114540 -
	/llvm/trunk/tools/llvmc/src/Base.td.in
Message-ID: <20100922090035.CE84F2A6C12C@llvm.org>

Author: foldr
Date: Wed Sep 22 04:00:35 2010
New Revision: 114540

URL: http://llvm.org/viewvc/llvm-project?rev=114540&view=rev
Log:
A more informative output suffix for the opt tool.

Modified:
    llvm/trunk/tools/llvmc/src/Base.td.in

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=114540&r1=114539&r2=114540&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Wed Sep 22 04:00:35 2010
@@ -241,7 +241,7 @@
 def opt : Tool<
 [(in_language "llvm-bitcode"),
  (out_language "llvm-bitcode"),
- (output_suffix "bc"),
+ (output_suffix "opt.bc"),
  (actions (case (not_empty "Wo,"), (forward_value "Wo,"),
                 (switch_on "O1"), (forward "O1"),
                 (switch_on "O2"), (forward "O2"),



From foldr at codedgers.com  Wed Sep 22 04:00:42 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 22 Sep 2010 09:00:42 -0000
Subject: [llvm-commits] [llvm] r114541 - in /llvm/trunk:
 test/LLVMC/C/emit-llvm-opt.c test/LLVMC/C/emit-llvm.c
 tools/llvmc/src/Base.td.in
Message-ID: <20100922090042.29B782A6C12D@llvm.org>

Author: foldr
Date: Wed Sep 22 04:00:41 2010
New Revision: 114541

URL: http://llvm.org/viewvc/llvm-project?rev=114541&view=rev
Log:
llvmc: Support '-emit-llvm -S' with -opt.

Added:
    llvm/trunk/test/LLVMC/C/emit-llvm-opt.c
Modified:
    llvm/trunk/test/LLVMC/C/emit-llvm.c
    llvm/trunk/tools/llvmc/src/Base.td.in

Added: llvm/trunk/test/LLVMC/C/emit-llvm-opt.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/C/emit-llvm-opt.c?rev=114541&view=auto
==============================================================================
--- llvm/trunk/test/LLVMC/C/emit-llvm-opt.c (added)
+++ llvm/trunk/test/LLVMC/C/emit-llvm-opt.c Wed Sep 22 04:00:41 2010
@@ -0,0 +1,7 @@
+// RUN: llvmc -c -opt -emit-llvm -o - %s | llvm-dis | grep "@f0()" | count 1
+// RUN: llvmc -c -opt -emit-llvm -S -o - %s | grep "@f0()" | count 1
+// RUN: llvmc --dry-run -c -opt -emit-llvm %s |& grep "^opt"
+// XFAIL: vg_leak
+
+int f0(void) {
+}

Modified: llvm/trunk/test/LLVMC/C/emit-llvm.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/C/emit-llvm.c?rev=114541&r1=114540&r2=114541&view=diff
==============================================================================
--- llvm/trunk/test/LLVMC/C/emit-llvm.c (original)
+++ llvm/trunk/test/LLVMC/C/emit-llvm.c Wed Sep 22 04:00:41 2010
@@ -1,4 +1,5 @@
 // RUN: llvmc -c -emit-llvm -o - %s | llvm-dis | grep "@f0()" | count 1
+// RUN: llvmc -c -emit-llvm -S -o - %s | grep "@f0()" | count 1
 // XFAIL: vg_leak
 
 int f0(void) {

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=114541&r1=114540&r2=114541&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Wed Sep 22 04:00:41 2010
@@ -178,14 +178,20 @@
          (switch_on "E"),
               [(forward "E"), (stop_compilation), (output_suffix E_ext)],
          (and (switch_on "E"), (empty "o")), (no_out_file),
-         (switch_on ["emit-llvm", "S"]),
-              [(output_suffix "ll"), (stop_compilation)],
-         (switch_on ["emit-llvm", "c"]), (stop_compilation),
+
+         // ('-emit-llvm') && !('opt') -> stop compilation
+         (and (switch_on "emit-llvm"), (not (switch_on "opt"))),
+              (stop_compilation),
+         // ('-S' && '-emit-llvm') && !('opt') -> output .ll
+         (and (switch_on ["emit-llvm", "S"]), (not (switch_on "opt"))),
+              [(forward "S"), (output_suffix "ll")],
+         // Ususally just output .bc
+         (not (switch_on "fsyntax-only")),
+              [(append_cmd "-c"), (append_cmd "-emit-llvm")],
+
+         // -fsyntax-only
          (switch_on "fsyntax-only"), [(forward "fsyntax-only"),
                                       (no_out_file), (stop_compilation)],
-         (switch_on ["S", "emit-llvm"]), [(forward "S"), (forward "emit-llvm")],
-         (not (or (switch_on ["S", "emit-llvm"]), (switch_on "fsyntax-only"))),
-             [(append_cmd "-c"), (append_cmd "-emit-llvm")],
 
          // Forwards
          (not_empty "Xpreprocessor"), (forward "Xpreprocessor"),
@@ -242,7 +248,10 @@
 [(in_language "llvm-bitcode"),
  (out_language "llvm-bitcode"),
  (output_suffix "opt.bc"),
- (actions (case (not_empty "Wo,"), (forward_value "Wo,"),
+ (actions (case (switch_on "emit-llvm"), (stop_compilation),
+                (switch_on ["emit-llvm", "S"]),
+                [(append_cmd "-S"), (output_suffix "ll")],
+                (not_empty "Wo,"), (forward_value "Wo,"),
                 (switch_on "O1"), (forward "O1"),
                 (switch_on "O2"), (forward "O2"),
                 (switch_on "O3"), (forward "O3"))),



From baldrick at free.fr  Wed Sep 22 04:52:00 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 22 Sep 2010 09:52:00 -0000
Subject: [llvm-commits] [dragonegg] r114542 - /dragonegg/trunk/TODO
Message-ID: <20100922095200.918CC2A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep 22 04:52:00 2010
New Revision: 114542

URL: http://llvm.org/viewvc/llvm-project?rev=114542&view=rev
Log:
LLVM and GCC both support non-temporal moves, so why not have dragonegg
feed the GCC information to LLVM?

Modified:
    dragonegg/trunk/TODO

Modified: dragonegg/trunk/TODO
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/TODO?rev=114542&r1=114541&r2=114542&view=diff
==============================================================================
--- dragonegg/trunk/TODO (original)
+++ dragonegg/trunk/TODO Wed Sep 22 04:52:00 2010
@@ -74,3 +74,5 @@
 bitcode in ELF sections like gcc does for gimple when doing LTO.
 
 Add support for address spaces.
+
+Add support for non-temporal stores.



From clchiou at gmail.com  Wed Sep 22 05:37:45 2010
From: clchiou at gmail.com (Che-Liang Chiou)
Date: Wed, 22 Sep 2010 18:37:45 +0800
Subject: [llvm-commits] [PATCH] Add ret instruction to PTX backend
Message-ID: <AANLkTikOi+Gwcf6ApheMm9dvU-zDAmEVQi9=tUN1On9h@mail.gmail.com>

Hi,

This patch adds 'ret' instruction to PTX backend.

SVN revisioin: r114539.

TEST:
$ llvm-lit test/CodeGen/PTX
-- Testing: 2 tests, 8 threads --
PASS: LLVM :: CodeGen/PTX/exit.ll (1 of 2)
PASS: LLVM :: CodeGen/PTX/ret.ll (2 of 2)
Testing Time: 0.02s
  Expected Passes    : 2

Regards,
Che-Liang
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From ggreif at gmail.com  Wed Sep 22 05:50:57 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 22 Sep 2010 03:50:57 -0700 (PDT)
Subject: [llvm-commits] [llvm] r114506 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp
 test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
In-Reply-To: <20100921234908.2B6822A6C12C@llvm.org>
References: <20100921234908.2B6822A6C12C@llvm.org>
Message-ID: <548d15b2-8188-493f-bfcd-3dfa6b028717@m16g2000vbs.googlegroups.com>

Hi Evan, All,

my observations inline below...

On Sep 22, 1:49?am, Evan Cheng <evan.ch... at apple.com> wrote:
> Author: evancheng
> Date: Tue Sep 21 18:49:07 2010
> New Revision: 114506
>
> URL:http://llvm.org/viewvc/llvm-project?rev=114506&view=rev
> Log:
> OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
>
> Added:
> ? ? llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
> Modified:
> ? ? llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBase...
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 21 18:49:07 2010
> @@ -1455,7 +1455,8 @@
>
> ? ?// Check that CPSR isn't set between the comparison instruction and the one we
> ? ?// want to change.
> - ?MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
> + ?MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
> + ? ?B = MI->getParent()->begin();
> ? ?--I;
> ? ?for (; I != E; --I) {
> ? ? ?const MachineInstr &Instr = *I;
> @@ -1469,6 +1470,10 @@
> ? ? ? ?if (MO.getReg() == ARM::CPSR)
> ? ? ? ? ?return false;
> ? ? ?}
> +
> + ? ?if (I == B)
> + ? ? ?// The 'and' is below the comparison instruction.
> + ? ? ?return false;
> ? ?}
>
> ? ?// Set the "zero" bit in CPSR.
>
> Added: llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-...
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll Tue Sep 21 18:49:07 2010
> @@ -0,0 +1,84 @@
> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
> +
> +declare noalias i8* @malloc(i32) nounwind
> +
> +define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, i8* %pixels) nounwind {
> +entry:
> + ?br i1 undef, label %bb3.i, label %bb3
> +
> +bb3.i: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry
> + ?unreachable
> +
> +gl_error.exit: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb22
> + ?ret void
> +
> +bb3: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry
> + ?br i1 false, label %bb5, label %bb4
> +
> +bb4: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb3
> + ?br label %bb5
> +
> +bb5: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb4, %bb3
> + ?br i1 undef, label %bb19, label %bb22
> +
> +bb19: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb5
> + ?switch i32 %type, label %bb3.i6.i [
> + ? ?i32 5120, label %bb1.i13
> + ? ?i32 5121, label %bb1.i13
> + ? ?i32 6656, label %bb9.i.i6
> + ?]
> +
> +bb9.i.i6: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb19
> + ?br label %bb1.i13
> +
> +bb3.i6.i: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb19
> + ?unreachable
> +
> +bb1.i13: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb9.i.i6, %bb19, %bb19
> + ?br i1 undef, label %bb3.i17, label %bb2.i16
> +
> +bb2.i16: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb1.i13
> + ?unreachable
> +
> +bb3.i17: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb1.i13
> + ?br i1 undef, label %bb4.i18, label %bb23.i
> +
> +bb4.i18: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb3.i17
> + ?%0 = mul nsw i32 %height, %width
> + ?%1 = and i32 %0, 7
> + ?%not..i = icmp ne i32 %1, 0
> + ?%2 = zext i1 %not..i to i32
> + ?%storemerge2.i = add i32 0, %2
> + ?%3 = call noalias i8* @malloc(i32 %storemerge2.i) nounwind
> + ?br i1 undef, label %bb3.i9, label %bb9.i

This seems to instruction select to:

BB#10: derived from LLVM BB %bb4.i18
    Predecessors according to CFG: BB#9
        %reg16402<def> = COPY %reg16385; rGPR:%reg16402 GPR:%reg16385
        %reg16403<def> = COPY %reg16384; rGPR:%reg16403 GPR:%reg16384
        %reg16401<def> = t2MUL %reg16402, %reg16403, pred:14, pred:
%reg0; rGPR:%reg16401,16402,16403
        %reg16404<def> = t2MOVi 0, pred:14, pred:%reg0, opt:%reg0;
rGPR:%reg16404
        t2TSTri %reg16401, 7, pred:14, pred:%reg0, %CPSR<imp-def>;
rGPR:%reg16401
        %reg16405<def> = t2MOVCCi %reg16404, 1, pred:1, pred:%CPSR;
rGPR:%reg16405,16404
        ADJCALLSTACKDOWN 0, pred:14, pred:%reg0, %SP<imp-def,dead>,
%SP<imp-use>
        %R0<def> = COPY %reg16405; rGPR:%reg16405
        tBLXi_r9 <ga:@malloc>, %R0, %R0<imp-def>, %R1<imp-def,dead>,
%R3<imp-def,dead>, %CPSR<imp-def,dead>, ...
        ADJCALLSTACKUP 0, 0, pred:14, pred:%reg0, %SP<imp-def,dead>,
%SP<imp-use>
        %reg16407<def> = t2ANDri %reg16401, 7, pred:14, pred:%reg0,
opt:%reg0; rGPR:%reg16407,16401
        %reg16387<def> = COPY %reg16407; GPR:%reg16387 rGPR:%reg16407
        %reg16408<def> = IMPLICIT_DEF; GPR:%reg16408
        t2CMPzri %reg16408<kill>, 0, pred:14, pred:%reg0, %CPSR<imp-
def>; GPR:%reg16408
        t2Bcc <BB#18>, pred:1, pred:%CPSR
    Successors according to CFG: BB#18 BB#11

The TST and the AND indeed both consume %reg16401 and the AND is below
the TST. Your fix is correct to bail out at the start of the BB.

But I see a missed opportunity here, and I'd like to understand
whether our arsenal is good enough to recognize it.

Finally the above ends up to output:

@ BB#4:                                 @ %bb.i24.i.preheader
        and     r0, r4, #7
        movs    r1, #0        ;; why movS? can we change to mov?
        cmp     r0, #0        ;; equivalent to tst r0, #7, elidable
        it      ne
        movne   r1, #1
        b       LBB0_6

But I guess the optimal sequence would be:

@ BB#4:                                 @ %bb.i24.i.preheader
        andS     r0, r4, #7
        ite     ne
        movne   r1, #1
        moveq   r1, #0  ;; or perhaps equivalently: moveq r1, r0
        b       LBB0_6

Please correct me if I missed something :-)

Anyway, to get here, I must understand a few things:

        %reg16387<def> = COPY %reg16407; GPR:%reg16387 rGPR:%reg16407

1) Why is this copy present at all?

        %reg16408<def> = IMPLICIT_DEF; GPR:%reg16408

2) What is defined implicitly here?

3) Third question: which MachineInst is responsible for the "movs r1,
#0" above?

Hopefully someone can explain this all to me ;-)

Cheers,

   Gabor


> +
> +bb9.i: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %bb4.i18
> + ?br i1 undef, label %bb13.i19, label %bb.i24.i
> +
> +bb13.i19: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb9.i
> + ?br i1 undef, label %bb14.i20, label %bb15.i
> +
> +bb14.i20: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb13.i19
> + ?unreachable
> +
> +bb15.i: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb13.i19
> + ?unreachable
> +
> +bb.i24.i: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb.i24.i, %bb9.i
> + ?%storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ]
> + ?%4 = add i32 %storemerge1.i21.i, 1
> + ?%exitcond47.i = icmp eq i32 %4, %storemerge2.i
> + ?br i1 %exitcond47.i, label %bb22, label %bb.i24.i
> +
> +bb23.i: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb3.i17
> + ?unreachable
> +
> +bb3.i9: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb4.i18
> + ?unreachable
> +
> +bb22: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb.i24.i, %bb5
> + ?br i1 undef, label %gl_error.exit, label %bb23
> +
> +bb23: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %bb22
> + ?ret void
> +}
>
> _______________________________________________
> llvm-commits mailing list
> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dirty at apple.com  Wed Sep 22 06:26:04 2010
From: dirty at apple.com (Cameron Esfahani)
Date: Wed, 22 Sep 2010 04:26:04 -0700
Subject: [llvm-commits] [PATCH] Fix for bug #8201
Message-ID: <8F433E34-28A7-46CB-AF1C-F7E8BB26E8AA@apple.com>

Small patch to fix http://llvm.org/bugs/show_bug.cgi?id=8201

Update the code to call via X86::CALL64pcrel32 in the 64-bit case.  Also, update the win_chkstk.ll test case to look for "callq _alloca" in the Mingw 64-bit case.


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Cameron Esfahani
dirty at apple.com

Imagine how pissed Zander would have been if Jobs pulled the Nano out of his pocket and it started RINGING...and it was Paris Hilton, and she was all like "where you at, bitch?" and Steve was all like "totally rocking a keynote, girlfriend," and then the pirates flew in on their burning sharks and totally wailed.

And then he pulled back the curtain to reveal a Beowulf cluster of Nanophones.

That's what I'm talking about.




From anton at korobeynikov.info  Wed Sep 22 09:48:08 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 22 Sep 2010 18:48:08 +0400
Subject: [llvm-commits] [PATCH] Fix for bug #8201
In-Reply-To: <8F433E34-28A7-46CB-AF1C-F7E8BB26E8AA@apple.com>
References: <8F433E34-28A7-46CB-AF1C-F7E8BB26E8AA@apple.com>
Message-ID: <AANLkTimhzEhRGpBJ6XxcT3yykh8y+LYREC8TuF5K2CjM@mail.gmail.com>

Hi Cameron,

> Update the code to call via X86::CALL64pcrel32 in the 64-bit case. ?Also, update the win_chkstk.ll test case to look for "callq _alloca" in the Mingw 64-bit case.
Looks ok for me. Please commit.

Thanks!

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From espindola at google.com  Wed Sep 22 10:33:38 2010
From: espindola at google.com (Rafael Espindola)
Date: Wed, 22 Sep 2010 11:33:38 -0400
Subject: [llvm-commits] [patch][RFC] Correctly produce R_X86_64_32 or
	R_X86_64_32S
In-Reply-To: <AANLkTi=ABAVxcn7mdkQfiLLVHEveH237gtO_db2ArYdd@mail.gmail.com>
References: <AANLkTikmXne4afVBc_zohprP=1UWZEgJufrvCw-=n1-k@mail.gmail.com>
	<AANLkTi=ABAVxcn7mdkQfiLLVHEveH237gtO_db2ArYdd@mail.gmail.com>
Message-ID: <AANLkTi=qf+oWGf4tpGR14r9XYKMsQ7Wb0Jd5gZnwBo8p@mail.gmail.com>

On 21 September 2010 20:29, Rafael Espindola <espindola at google.com> wrote:
> The attached patch survived a bit more testing :-)

The patch just survived a opt bootstrap on Darwin and a debug
bootstrap is on stage3.

Cheers,
-- 
Rafael ?vila de Esp?ndola


From baldrick at free.fr  Wed Sep 22 10:40:20 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 22 Sep 2010 15:40:20 -0000
Subject: [llvm-commits] [zorg] r114546 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100922154020.DF2A12A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep 22 10:40:20 2010
New Revision: 114546

URL: http://llvm.org/viewvc/llvm-project?rev=114546&view=rev
Log:
Re-enable the expensive checks builder on a different machine.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114546&r1=114545&r2=114546&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Sep 22 10:40:20 2010
@@ -82,6 +82,10 @@
          'builddir':"llvm-gcc-x86_64-darwin10-selfhost",
          'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='x86_64-apple-darwin10',
                                                          gxxincludedir='/usr/include/c++/4.2.1')},
+        {'name' : "llvm-x86_64-linux-checks",
+        'slavenames':["gcc10"],
+        'builddir':"llvm-x86_64-linux-checks",
+        'factory':LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", expensive_checks=True)}
         {'name' : "llvm-gcc-i386-linux-selfhost",
          'slavenames':["gcc11"],
          'builddir':"llvm-gcc-i386-linux-selfhost",
@@ -90,13 +94,6 @@
                                                          '--enable-targets=all','--with-as=/home/baldrick/bin32/as'])},
         ]
 
-# Offline, no free x86_64 resources.
-{'name' : "llvm-x86_64-linux-checks",
- 'slavenames':["osu2"],
- 'builddir':"llvm-x86_64-linux-checks",
- 'factory':LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", jobs=10, expensive_checks=True)}
-
-
 clang_i386_linux_xfails = [
     'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4',
     'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4',



From grosbach at apple.com  Wed Sep 22 11:45:14 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 16:45:14 -0000
Subject: [llvm-commits] [llvm] r114550 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100922164514.0FAE22A6C12E@llvm.org>

Author: grosbach
Date: Wed Sep 22 11:45:13 2010
New Revision: 114550

URL: http://llvm.org/viewvc/llvm-project?rev=114550&view=rev
Log:
Clean up comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114550&r1=114549&r2=114550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 22 11:45:13 2010
@@ -1335,10 +1335,10 @@
         else
           // Internal to current translation unit.
           //
-          // When we place the LSDA into the TEXT section, the type info pointers
-          // need to be indirect and pc-rel. We accomplish this by using NLPs.
-          // However, sometimes the types are local to the file. So we need to
-          // fill in the value for the NLP in those cases.
+          // When we place the LSDA into the TEXT section, the type info
+          // pointers need to be indirect and pc-rel. We accomplish this by
+          // using NLPs; however, sometimes the types are local to the file.
+          // We need to fill in the value for the NLP in those cases.
           OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
                                                         OutContext),
                                 4/*size*/, 0/*addrspace*/);



From wdietz2 at illinois.edu  Wed Sep 22 12:05:47 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 22 Sep 2010 17:05:47 -0000
Subject: [llvm-commits] [poolalloc] r114552 - in
 /poolalloc/trunk/test/dsa/local: extern.ll extern2.ll extern3.ll
Message-ID: <20100922170547.D28712A6C12F@llvm.org>

Author: wdietz2
Date: Wed Sep 22 12:05:47 2010
New Revision: 114552

URL: http://llvm.org/viewvc/llvm-project?rev=114552&view=rev
Log:
Added various tests regarding incompleteness due to exposure to external code.

Added:
    poolalloc/trunk/test/dsa/local/extern.ll
    poolalloc/trunk/test/dsa/local/extern2.ll
    poolalloc/trunk/test/dsa/local/extern3.ll

Added: poolalloc/trunk/test/dsa/local/extern.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern.ll?rev=114552&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern.ll (added)
+++ poolalloc/trunk/test/dsa/local/extern.ll Wed Sep 22 12:05:47 2010
@@ -0,0 +1,63 @@
+;Test that pointers from external functions are marked incomplete properly
+;Tests on all the DSA passes for three simple cases:
+;--calling an allocator wrapper (shouldn't be incomplete in interprocedural)
+;--calling a undefined (external) function.  Should be incomplete at least
+;  once the interprocedural passes run.
+;--calling a function that calls an undefined (external) function.
+;  Should be incomplete, tests very basic tracking.
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrExtern+I"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrViaExtern+I"
+
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrExtern+I"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr-I"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrViaExtern+I"
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrExtern+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrViaExtern+I"
+
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrExtern+I"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr-I"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrViaExtern+I"
+
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrExtern+I"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr-I"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrViaExtern+I"
+
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrExtern+I"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr-I"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrViaExtern+I"
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32* @getPointerViaExtern() nounwind {
+entry:
+  %0 = tail call i32* (...)* @getPointerExtern() nounwind ; <i32*> [#uses=1]
+  ret i32* %0
+}
+
+declare i32* @getPointerExtern(...)
+
+define noalias i32* @getPointer() nounwind {
+entry:
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
+  %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  ret i32* %1
+}
+
+declare noalias i8* @malloc(i64) nounwind
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+  %ptr = tail call i32* ()* @getPointer() nounwind
+  %ptrExtern = tail call i32* (...)* @getPointerExtern() nounwind
+  %ptrViaExtern = tail call i32* ()* @getPointerViaExtern() nounwind
+  %val1 = load i32* %ptr, align 4
+  %val2 = load i32* %ptrExtern, align 4
+  %val3 = load i32* %ptrViaExtern, align 4
+  %sum_partial = add i32 %val1, %val2
+  %sum = add i32 %sum_partial, %val3
+  ret i32 %sum
+}

Added: poolalloc/trunk/test/dsa/local/extern2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern2.ll?rev=114552&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern2.ll (added)
+++ poolalloc/trunk/test/dsa/local/extern2.ll Wed Sep 22 12:05:47 2010
@@ -0,0 +1,38 @@
+;Here we get a pointer from an external function and pass it to a callee.
+;We then test that the flags on that pointer are set appropriately.
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "takesPointer:ptr+I"
+
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "takesPointer:ptr+I"
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+I"
+
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "takesPointer:ptr+I"
+
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "takesPointer:ptr+I"
+
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr+I"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "takesPointer:ptr+I"
+
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @takesPointer(i32* nocapture %ptr) nounwind readonly {
+entry:
+  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
+  ret i32 %0
+}
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+  %ptr = tail call i32* (...)* @getPointerExtern() nounwind
+  %0 = tail call i32 @takesPointer(i32* %ptr) nounwind
+  ret i32 %0
+}
+
+declare i32* @getPointerExtern(...)

Added: poolalloc/trunk/test/dsa/local/extern3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern3.ll?rev=114552&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern3.ll (added)
+++ poolalloc/trunk/test/dsa/local/extern3.ll Wed Sep 22 12:05:47 2010
@@ -0,0 +1,88 @@
+; ModuleID = 'extern.c'
+;This tests the various cases that could involve incompleteness due
+;to external code, and additionally verifies these flags are NOT set
+;on internal functions.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare i32* @getPointerExtern()
+declare void @takesPointerExtern(i32*)
+declare noalias i8* @malloc(i64) nounwind
+declare void @free(i8*) nounwind
+
+;This should be marked incomplete and external due to the
+;unification-based nature of DSA.
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointer:ptr+I"
+define i32* @getPointer() nounwind {
+entry:
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
+  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  ret i32* %ptr
+}
+
+;This should be marked incomplete and external due to the
+;unification-based nature of DSA.
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+I"
+define i32 @takesPointer(i32* %ptr) nounwind {
+entry:
+  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
+  ret i32 %0
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointerInternal:ptr-I"
+define internal i32* @getPointerInternal() nounwind {
+entry:
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
+  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  ret i32* %ptr
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointerInternal:ptr-I"
+define internal i32 @takesPointerInternal(i32* %ptr) nounwind {
+entry:
+  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
+  ret i32 %0
+}
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+  call void @checkExterns() nounwind
+  call void @checkExternals() nounwind
+  call void @checkInternals() nounwind
+  ret i32 0
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:get+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:take+I"
+define void @checkExterns() nounwind {
+  %get = tail call i32* ()* @getPointerExtern() nounwind ; <i32*> [#uses=0]
+  %1 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
+  %take = bitcast i8* %1 to i32*                     ; <i32*> [#uses=1]
+  tail call void @takesPointerExtern(i32* %take) nounwind
+  tail call void @free(i8* %1) nounwind
+  ret void
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take+I"
+define void @checkExternals() nounwind {
+entry:
+  %get = tail call i32* ()* @getPointer() nounwind ; <i32*> [#uses=0]
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
+  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  tail call i32 @takesPointer(i32* %take) nounwind
+  tail call void @free(i8* %0) nounwind
+  ret void
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take-I"
+define void @checkInternals() nounwind {
+entry:
+  %get = tail call i32* ()* @getPointerInternal() nounwind ; <i32*> [#uses=0]
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
+  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  tail call i32 @takesPointerInternal(i32* %take) nounwind
+  tail call void @free(i8* %0) nounwind
+  ret void
+}



From grosbach at apple.com  Wed Sep 22 12:15:35 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 17:15:35 -0000
Subject: [llvm-commits] [llvm] r114553 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100922171535.B6FDF2A6C12D@llvm.org>

Author: grosbach
Date: Wed Sep 22 12:15:35 2010
New Revision: 114553

URL: http://llvm.org/viewvc/llvm-project?rev=114553&view=rev
Log:
Add MC instruction printer support for TB[BH] style thumb2 jump tables.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114553&r1=114552&r2=114553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 22 12:15:35 2010
@@ -1400,42 +1400,46 @@
   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
-  bool ByteOffset = false, HalfWordOffset = false;
+  unsigned OffsetWidth = 4;
   if (MI->getOpcode() == ARM::t2TBB)
-    ByteOffset = true;
+    OffsetWidth = 1;
   else if (MI->getOpcode() == ARM::t2TBH)
-    HalfWordOffset = true;
+    OffsetWidth = 2;
 
   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
     MachineBasicBlock *MBB = JTBBs[i];
+    const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
+                                                      OutContext);
     // If this isn't a TBB or TBH, the entries are direct branch instructions.
-    if (!ByteOffset && !HalfWordOffset) {
+    if (OffsetWidth == 4) {
       MCInst BrInst;
       BrInst.setOpcode(ARM::t2B);
-      BrInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
-            MBB->getSymbol(), OutContext)));
+      BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
       OutStreamer.EmitInstruction(BrInst);
       continue;
     }
     // Otherwise it's an offset from the dispatch instruction. Construct an
-    // MCExpr for the entry.
-    assert(0 && "FIXME: TB[BH] jump table!!");
-
-#if 0
-    if (ByteOffset)
-      O << MAI->getData8bitsDirective();
-    else if (HalfWordOffset)
-      O << MAI->getData16bitsDirective();
-
-    if (ByteOffset || HalfWordOffset)
-      O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
-    else
-      O << "\tb.w " << *MBB->getSymbol();
-
-    if (i != e-1)
-      O << '\n';
-#endif
+    // MCExpr for the entry. We want a value of the form:
+    // (BasicBlockAddr - TableBeginAddr) / 2
+    //
+    // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
+    // would look like:
+    // LJTI_0_0:
+    //    .byte (LBB0 - LJTI_0_0) / 2
+    //    .byte (LBB1 - LJTI_0_0) / 2
+    const MCExpr *Expr =
+      MCBinaryExpr::CreateSub(MBBSymbolExpr,
+                              MCSymbolRefExpr::Create(JTISymbol, OutContext),
+                              OutContext);
+    Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
+                                   OutContext);
+    OutStreamer.EmitValue(Expr, OffsetWidth);
   }
+
+  // Make sure the instruction that follows TBB is 2-byte aligned.
+  // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
+  if (MI->getOpcode() == ARM::t2TBB)
+    EmitAlignment(1);
 }
 
 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
@@ -1654,7 +1658,6 @@
     MCInst TmpInst;
     MCInstLowering.Lower(MI, TmpInst);
     OutStreamer.EmitInstruction(TmpInst);
-
     EmitJump2Table(MI);
     return;
   }



From bob.wilson at apple.com  Wed Sep 22 12:35:14 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 22 Sep 2010 17:35:14 -0000
Subject: [llvm-commits] [llvm] r114554 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100922173514.4837C2A6C12C@llvm.org>

Author: bwilson
Date: Wed Sep 22 12:35:14 2010
New Revision: 114554

URL: http://llvm.org/viewvc/llvm-project?rev=114554&view=rev
Log:
Attempt to fix llvm-gcc build.  It was crashing when building gcov.o for an
ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114554&r1=114553&r2=114554&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 22 12:35:14 2010
@@ -6384,7 +6384,8 @@
     // shouldn't be necessary except that RFP cannot be live across
     // multiple blocks. When stackifier is fixed, they can be uncoupled.
     MachineFunction &MF = DAG.getMachineFunction();
-    int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
+    unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
+    int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
     SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
     Tys = DAG.getVTList(MVT::Other);
     SDValue Ops[] = {
@@ -6393,7 +6394,7 @@
     MachineMemOperand *MMO =
       DAG.getMachineFunction()
       .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
-                            MachineMemOperand::MOStore, 8, 8);
+                            MachineMemOperand::MOStore, SSFISize, SSFISize);
     
     Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
                                     Ops, array_lengthof(Ops),



From grosbach at apple.com  Wed Sep 22 12:39:48 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 17:39:48 -0000
Subject: [llvm-commits] [llvm] r114555 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100922173948.4E4F72A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 12:39:48 2010
New Revision: 114555

URL: http://llvm.org/viewvc/llvm-project?rev=114555&view=rev
Log:
Add MC instruction printer support for ARM and Thumb1 jump tables.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114555&r1=114554&r2=114555&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 22 12:39:48 2010
@@ -1385,6 +1385,47 @@
   return Label;
 }
 
+void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
+  unsigned Opcode = MI->getOpcode();
+  int OpNum = 1;
+  if (Opcode == ARM::BR_JTadd)
+    OpNum = 2;
+  else if (Opcode == ARM::BR_JTm)
+    OpNum = 3;
+
+  const MachineOperand &MO1 = MI->getOperand(OpNum);
+  const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
+  unsigned JTI = MO1.getIndex();
+
+  // Emit a label for the jump table.
+  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
+  OutStreamer.EmitLabel(JTISymbol);
+
+  // Emit each entry of the table.
+  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
+  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
+  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
+
+  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
+    MachineBasicBlock *MBB = JTBBs[i];
+    // Construct an MCExpr for the entry. We want a value of the form:
+    // (BasicBlockAddr - TableBeginAddr)
+    //
+    // For example, a table with entries jumping to basic blocks BB0 and BB1
+    // would look like:
+    // LJTI_0_0:
+    //    .word (LBB0 - LJTI_0_0)
+    //    .word (LBB1 - LJTI_0_0)
+    const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
+
+    if (TM.getRelocationModel() == Reloc::PIC_)
+      Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
+                                                                   OutContext),
+                                     OutContext);
+    OutStreamer.EmitValue(Expr, 4);
+  }
+}
+
 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
   unsigned Opcode = MI->getOpcode();
   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
@@ -1664,9 +1705,14 @@
   case ARM::tBR_JTr:
   case ARM::BR_JTr:
   case ARM::BR_JTm:
-  case ARM::BR_JTadd:
-    abort();
-    break;
+  case ARM::BR_JTadd: {
+    // Lower and emit the instruction itself, then the jump table following it.
+    MCInst TmpInst;
+    MCInstLowering.Lower(MI, TmpInst);
+    OutStreamer.EmitInstruction(TmpInst);
+    EmitJumpTable(MI);
+    return;
+  }
   }
 
   MCInst TmpInst;



From rafael.espindola at gmail.com  Wed Sep 22 12:43:05 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 22 Sep 2010 17:43:05 -0000
Subject: [llvm-commits] [llvm] r114556 - in /llvm/trunk:
 lib/MC/MCELFStreamer.cpp test/MC/ELF/align-bss.s
Message-ID: <20100922174305.19DA42A6C12C@llvm.org>

Author: rafael
Date: Wed Sep 22 12:43:04 2010
New Revision: 114556

URL: http://llvm.org/viewvc/llvm-project?rev=114556&view=rev
Log:
Correctly align bss.

Added:
    llvm/trunk/test/MC/ELF/align-bss.s
Modified:
    llvm/trunk/lib/MC/MCELFStreamer.cpp

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=114556&r1=114555&r2=114556&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Wed Sep 22 12:43:04 2010
@@ -322,9 +322,15 @@
                                                                     SectionKind::getBSS());
 
     MCSectionData &SectData = getAssembler().getOrCreateSectionData(*Section);
+    new MCAlignFragment(ByteAlignment, 0, 1, ByteAlignment, &SectData);
+
     MCFragment *F = new MCFillFragment(0, 0, Size, &SectData);
     SD.setFragment(F);
     Symbol->setSection(*Section);
+
+    // Update the maximum alignment of the section if necessary.
+    if (ByteAlignment > SectData.getAlignment())
+      SectData.setAlignment(ByteAlignment);
   } else {
     SD.setCommon(Size, ByteAlignment);
   }

Added: llvm/trunk/test/MC/ELF/align-bss.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/align-bss.s?rev=114556&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/align-bss.s (added)
+++ llvm/trunk/test/MC/ELF/align-bss.s Wed Sep 22 12:43:04 2010
@@ -0,0 +1,17 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  | FileCheck %s
+
+// Test that the bss section is correctly aligned
+
+	.local	foo
+	.comm	foo,2048,16
+
+// CHECK:        ('sh_name', 13) # '.bss'
+// CHECK-NEXT:   ('sh_type', 8)
+// CHECK-NEXT:   ('sh_flags', 3)
+// CHECK-NEXT:   ('sh_addr', 0)
+// CHECK-NEXT:   ('sh_offset', 64)
+// CHECK-NEXT:   ('sh_size', 2048)
+// CHECK-NEXT:   ('sh_link', 0)
+// CHECK-NEXT:   ('sh_info', 0)
+// CHECK-NEXT:   ('sh_addralign', 16)
+// CHECK-NEXT:   ('sh_entsize', 0)



From daniel at zuster.org  Wed Sep 22 12:46:10 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 17:46:10 -0000
Subject: [llvm-commits] [llvm] r114558 -
	/llvm/trunk/lib/System/Unix/Signals.inc
Message-ID: <20100922174611.007892A6C12D@llvm.org>

Author: ddunbar
Date: Wed Sep 22 12:46:10 2010
New Revision: 114558

URL: http://llvm.org/viewvc/llvm-project?rev=114558&view=rev
Log:
CrashRecovery/Darwin: Override raise() as well so that crash recovery doesn't
end up altering the thread on which crashes are done because of its use of
Darwin's broken raise() implementation.

Modified:
    llvm/trunk/lib/System/Unix/Signals.inc

Modified: llvm/trunk/lib/System/Unix/Signals.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Signals.inc?rev=114558&r1=114557&r2=114558&view=diff
==============================================================================
--- llvm/trunk/lib/System/Unix/Signals.inc (original)
+++ llvm/trunk/lib/System/Unix/Signals.inc Wed Sep 22 12:46:10 2010
@@ -274,6 +274,10 @@
 
 #ifdef __APPLE__
 
+int raise(int sig) {
+  return pthread_kill(pthread_self(), SIGABRT);
+}
+
 void __assert_rtn(const char *func,
                   const char *file,
                   int line,
@@ -291,7 +295,7 @@
 #include <pthread.h>
 
 void abort() {
-  pthread_kill(pthread_self(), SIGABRT);
+  raise(SIGABRT);
   usleep(1000);
   __builtin_trap();
 }



From grosbach at apple.com  Wed Sep 22 13:16:55 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 18:16:55 -0000
Subject: [llvm-commits] [llvm] r114560 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp
Message-ID: <20100922181655.613E82A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 13:16:55 2010
New Revision: 114560

URL: http://llvm.org/viewvc/llvm-project?rev=114560&view=rev
Log:
remove trailing whitespace

Modified:
    llvm/trunk/lib/MC/MCAsmStreamer.cpp

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=114560&r1=114559&r2=114560&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Sep 22 13:16:55 2010
@@ -32,7 +32,7 @@
   const MCAsmInfo &MAI;
   OwningPtr<MCInstPrinter> InstPrinter;
   OwningPtr<MCCodeEmitter> Emitter;
-  
+
   SmallString<128> CommentToEmit;
   raw_svector_ostream CommentStream;
 
@@ -68,7 +68,7 @@
   /// isVerboseAsm - Return true if this streamer supports verbose assembly at
   /// all.
   virtual bool isVerboseAsm() const { return IsVerboseAsm; }
-  
+
   /// hasRawTextSupport - We support EmitRawText.
   virtual bool hasRawTextSupport() const { return true; }
 
@@ -130,19 +130,19 @@
   /// @param Symbol - The common symbol to emit.
   /// @param Size - The size of the common symbol.
   virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size);
-  
+
   virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
                             unsigned Size = 0, unsigned ByteAlignment = 0);
 
   virtual void EmitTBSSSymbol (const MCSection *Section, MCSymbol *Symbol,
                                uint64_t Size, unsigned ByteAlignment = 0);
-                               
+
   virtual void EmitBytes(StringRef Data, unsigned AddrSpace);
 
   virtual void EmitValue(const MCExpr *Value, unsigned Size,unsigned AddrSpace);
   virtual void EmitIntValue(uint64_t Value, unsigned Size, unsigned AddrSpace);
   virtual void EmitGPRel32Value(const MCExpr *Value);
-  
+
 
   virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,
                         unsigned AddrSpace);
@@ -161,14 +161,14 @@
   virtual void EmitDwarfFileDirective(unsigned FileNo, StringRef Filename);
 
   virtual void EmitInstruction(const MCInst &Inst);
-  
+
   /// EmitRawText - If this file is backed by a assembly streamer, this dumps
   /// the specified string in the output .s file.  This capability is
   /// indicated by the hasRawTextSupport() predicate.
   virtual void EmitRawText(StringRef String);
-  
+
   virtual void Finish();
-  
+
   /// @}
 };
 
@@ -180,14 +180,14 @@
 /// verbose assembly output is enabled.
 void MCAsmStreamer::AddComment(const Twine &T) {
   if (!IsVerboseAsm) return;
-  
+
   // Make sure that CommentStream is flushed.
   CommentStream.flush();
-  
+
   T.toVector(CommentToEmit);
   // Each comment goes on its own line.
   CommentToEmit.push_back('\n');
-  
+
   // Tell the comment stream that the vector changed underneath it.
   CommentStream.resync();
 }
@@ -197,10 +197,10 @@
     OS << '\n';
     return;
   }
-  
+
   CommentStream.flush();
   StringRef Comments = CommentToEmit.str();
-  
+
   assert(Comments.back() == '\n' &&
          "Comment array not newline terminated");
   do {
@@ -208,10 +208,10 @@
     OS.PadToColumn(MAI.getCommentColumn());
     size_t Position = Comments.find('\n');
     OS << MAI.getCommentString() << ' ' << Comments.substr(0, Position) << '\n';
-    
+
     Comments = Comments.substr(Position+1);
   } while (!Comments.empty());
-  
+
   CommentToEmit.clear();
   // Tell the comment stream that the vector changed underneath it.
   CommentStream.resync();
@@ -360,11 +360,11 @@
                                  unsigned Size, unsigned ByteAlignment) {
   // Note: a .zerofill directive does not switch sections.
   OS << ".zerofill ";
-  
+
   // This is a mach-o specific directive.
   const MCSectionMachO *MOSection = ((const MCSectionMachO*)Section);
   OS << MOSection->getSegmentName() << "," << MOSection->getSectionName();
-  
+
   if (Symbol != NULL) {
     OS << ',' << *Symbol << ',' << Size;
     if (ByteAlignment != 0)
@@ -382,11 +382,11 @@
   // Instead of using the Section we'll just use the shortcut.
   // This is a mach-o specific directive and section.
   OS << ".tbss " << *Symbol << ", " << Size;
-  
+
   // Output align if we have it.  We default to 1 so don't bother printing
   // that.
   if (ByteAlignment > 1) OS << ", " << Log2_32(ByteAlignment);
-  
+
   EmitEOL();
 }
 
@@ -394,19 +394,19 @@
 
 static void PrintQuotedString(StringRef Data, raw_ostream &OS) {
   OS << '"';
-  
+
   for (unsigned i = 0, e = Data.size(); i != e; ++i) {
     unsigned char C = Data[i];
     if (C == '"' || C == '\\') {
       OS << '\\' << (char)C;
       continue;
     }
-    
+
     if (isprint((unsigned char)C)) {
       OS << (char)C;
       continue;
     }
-    
+
     switch (C) {
       case '\b': OS << "\\b"; break;
       case '\f': OS << "\\f"; break;
@@ -421,7 +421,7 @@
         break;
     }
   }
-  
+
   OS << '"';
 }
 
@@ -429,7 +429,7 @@
 void MCAsmStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {
   assert(CurSection && "Cannot emit contents before setting section!");
   if (Data.empty()) return;
-  
+
   if (Data.size() == 1) {
     OS << MAI.getData8bitsDirective(AddrSpace);
     OS << (unsigned)(unsigned char)Data[0];
@@ -475,7 +475,7 @@
     }
     return;
   }
-  
+
   assert(Directive && "Invalid size for machine code value!");
   OS << Directive << truncateToSize(Value, Size);
   EmitEOL();
@@ -492,7 +492,7 @@
   case 4: Directive = MAI.getData32bitsDirective(AddrSpace); break;
   case 8: Directive = MAI.getData64bitsDirective(AddrSpace); break;
   }
-  
+
   assert(Directive && "Invalid size for machine code value!");
   OS << Directive << *Value;
   EmitEOL();
@@ -510,7 +510,7 @@
 void MCAsmStreamer::EmitFill(uint64_t NumBytes, uint8_t FillValue,
                              unsigned AddrSpace) {
   if (NumBytes == 0) return;
-  
+
   if (AddrSpace == 0)
     if (const char *ZeroDirective = MAI.getZeroDirective()) {
       OS << ZeroDirective << NumBytes;
@@ -538,7 +538,7 @@
     case 4: OS << ".p2alignl "; break;
     case 8: llvm_unreachable("Unsupported alignment size!");
     }
-    
+
     if (MAI.getAlignmentIsInBytes())
       OS << ByteAlignment;
     else
@@ -548,13 +548,13 @@
       OS << ", 0x";
       OS.write_hex(truncateToSize(Value, ValueSize));
 
-      if (MaxBytesToEmit) 
+      if (MaxBytesToEmit)
         OS << ", " << MaxBytesToEmit;
     }
     EmitEOL();
     return;
   }
-  
+
   // Non-power of two alignment.  This is not widely supported by assemblers.
   // FIXME: Parameterize this based on MAI.
   switch (ValueSize) {
@@ -567,7 +567,7 @@
 
   OS << ' ' << ByteAlignment;
   OS << ", " << truncateToSize(Value, ValueSize);
-  if (MaxBytesToEmit) 
+  if (MaxBytesToEmit)
     OS << ", " << MaxBytesToEmit;
   EmitEOL();
 }



From grosbach at apple.com  Wed Sep 22 13:18:31 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 18:18:31 -0000
Subject: [llvm-commits] [llvm] r114561 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp
Message-ID: <20100922181831.1A2CC2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 13:18:30 2010
New Revision: 114561

URL: http://llvm.org/viewvc/llvm-project?rev=114561&view=rev
Log:
grammar tweakage

Modified:
    llvm/trunk/lib/MC/MCAsmStreamer.cpp

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=114561&r1=114560&r2=114561&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Sep 22 13:18:30 2010
@@ -162,7 +162,7 @@
 
   virtual void EmitInstruction(const MCInst &Inst);
 
-  /// EmitRawText - If this file is backed by a assembly streamer, this dumps
+  /// EmitRawText - If this file is backed by an assembly streamer, this dumps
   /// the specified string in the output .s file.  This capability is
   /// indicated by the hasRawTextSupport() predicate.
   virtual void EmitRawText(StringRef String);
@@ -692,7 +692,7 @@
   EmitEOL();
 }
 
-/// EmitRawText - If this file is backed by a assembly streamer, this dumps
+/// EmitRawText - If this file is backed by an assembly streamer, this dumps
 /// the specified string in the output .s file.  This capability is
 /// indicated by the hasRawTextSupport() predicate.
 void MCAsmStreamer::EmitRawText(StringRef String) {



From grosbach at apple.com  Wed Sep 22 13:37:14 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 18:37:14 -0000
Subject: [llvm-commits] [llvm] r114563 - in
 /llvm/trunk/lib/Target/ARM/AsmPrinter: ARMInstPrinter.cpp ARMInstPrinter.h
Message-ID: <20100922183715.0379D2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 13:37:14 2010
New Revision: 114563

URL: http://llvm.org/viewvc/llvm-project?rev=114563&view=rev
Log:
Add PrintSpecial() handling for  in ARM MC instruction printer.

Modified:
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114563&r1=114562&r2=114563&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 22 13:37:14 2010
@@ -736,3 +736,11 @@
   uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
   O << "#0x" << utohexstr(Val);
 }
+
+void ARMInstPrinter::PrintSpecial(const MCInst *MI, raw_ostream &O,
+                                  const char *Kind) {
+  if (strcmp(Kind, "comment") == 0)
+    O << "@";
+  else
+    abort();
+}

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=114563&r1=114562&r2=114563&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Wed Sep 22 13:37:14 2010
@@ -110,8 +110,7 @@
   void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 
   void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  // FIXME: Implement.
-  void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind) {}
+  void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind);
 };
 
 }



From bob.wilson at apple.com  Wed Sep 22 13:44:56 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 22 Sep 2010 18:44:56 -0000
Subject: [llvm-commits] [llvm] r114568 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20100922184456.6177D2A6C12C@llvm.org>

Author: bwilson
Date: Wed Sep 22 13:44:56 2010
New Revision: 114568

URL: http://llvm.org/viewvc/llvm-project?rev=114568&view=rev
Log:
When moving zext/sext to be folded with a load, ignore the issue of whether
truncates are free only in the case where the extended type is legal but the
load type is not.  If both types are illegal, such as when they are too big,
the load may not be legalized into an extended load.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=114568&r1=114567&r2=114568&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Wed Sep 22 13:44:56 2010
@@ -772,7 +772,8 @@
   // If the load has other users and the truncate is not free, this probably
   // isn't worthwhile.
   if (!LI->hasOneUse() &&
-      TLI && TLI->isTypeLegal(TLI->getValueType(LI->getType())) &&
+      TLI && (TLI->isTypeLegal(TLI->getValueType(LI->getType())) ||
+              !TLI->isTypeLegal(TLI->getValueType(I->getType()))) &&
       !TLI->isTruncateFree(I->getType(), LI->getType()))
     return false;
 



From bob.wilson at apple.com  Wed Sep 22 13:49:02 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 22 Sep 2010 11:49:02 -0700
Subject: [llvm-commits] [llvm] r114488	-
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
In-Reply-To: <4C99A5C4.5030505@free.fr>
References: <20100921215427.BFE152A6C12C@llvm.org> <4C99A5C4.5030505@free.fr>
Message-ID: <9A6CC8F9-803A-4BC0-8FEC-B666A3BDE712@apple.com>


On Sep 21, 2010, at 11:44 PM, Duncan Sands wrote:

> Hi Bob,
> 
>> Move a sign-extend or a zero-extend of a load to the same basic block as the
>> load when the type of the load is not legal, even if truncates are not free.
>> The load is going to be legalized to an extending load anyway.
> 
> an extending load is not used for illegal integer types that are too large
> (eg: i512).  Instead a pair of half-sized loads is used.

I committed a fix in svn 114568.  It now applies when the extended type is legal but the load is not.

From wdietz2 at illinois.edu  Wed Sep 22 13:59:53 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 22 Sep 2010 18:59:53 -0000
Subject: [llvm-commits] [poolalloc] r114569 - in
 /poolalloc/trunk/test/dsa/local: extern.ll extern3.ll
Message-ID: <20100922185953.AAA1B2A6C12C@llvm.org>

Author: wdietz2
Date: Wed Sep 22 13:59:53 2010
New Revision: 114569

URL: http://llvm.org/viewvc/llvm-project?rev=114569&view=rev
Log:
Fix up extern test cases to be accurate.
Typos (sigh) and forgot to mark one of the methods 'internal'.

Modified:
    poolalloc/trunk/test/dsa/local/extern.ll
    poolalloc/trunk/test/dsa/local/extern3.ll

Modified: poolalloc/trunk/test/dsa/local/extern.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern.ll?rev=114569&r1=114568&r2=114569&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern.ll (original)
+++ poolalloc/trunk/test/dsa/local/extern.ll Wed Sep 22 13:59:53 2010
@@ -40,7 +40,7 @@
 
 declare i32* @getPointerExtern(...)
 
-define noalias i32* @getPointer() nounwind {
+define internal noalias i32* @getPointer() nounwind {
 entry:
   %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
   %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]

Modified: poolalloc/trunk/test/dsa/local/extern3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern3.ll?rev=114569&r1=114568&r2=114569&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern3.ll (original)
+++ poolalloc/trunk/test/dsa/local/extern3.ll Wed Sep 22 13:59:53 2010
@@ -75,8 +75,8 @@
   ret void
 }
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get-I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:get-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:take-I"
 define void @checkInternals() nounwind {
 entry:
   %get = tail call i32* ()* @getPointerInternal() nounwind ; <i32*> [#uses=0]



From rafael.espindola at gmail.com  Wed Sep 22 14:04:41 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 22 Sep 2010 19:04:41 -0000
Subject: [llvm-commits] [llvm] r114570 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20100922190441.5DBA92A6C12C@llvm.org>

Author: rafael
Date: Wed Sep 22 14:04:41 2010
New Revision: 114570

URL: http://llvm.org/viewvc/llvm-project?rev=114570&view=rev
Log:
Fix typo and add a FIXME.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114570&r1=114569&r2=114570&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Sep 22 14:04:41 2010
@@ -812,7 +812,7 @@
 
   unsigned NumRegularSections = Asm.size();
 
-  // We construct .shstrtab, .symtab and .strtab is this order to match gnu as.
+  // We construct .shstrtab, .symtab and .strtab in this order to match gnu as.
   const MCSection *ShstrtabSection;
   ShstrtabSection = Ctx.getELFSection(".shstrtab", ELF::SHT_STRTAB, 0,
                                       SectionKind::getReadOnly(), false);
@@ -856,6 +856,7 @@
          ie = Asm.end(); it != ie; ++it) {
     const MCSectionELF &Section =
       static_cast<const MCSectionELF&>(it->getSection());
+    // FIXME: We could merge prefixes like in .text and .text.rela.
 
     // Remember the index into the string table so we can write it
     // into the sh_name field of the section header table.



From wdietz2 at illinois.edu  Wed Sep 22 14:12:10 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 22 Sep 2010 19:12:10 -0000
Subject: [llvm-commits] [poolalloc] r114571 - in
 /poolalloc/trunk/test/dsa/td: call.c call.ll testcase.c testcase.ll
Message-ID: <20100922191211.052222A6C12C@llvm.org>

Author: wdietz2
Date: Wed Sep 22 14:12:10 2010
New Revision: 114571

URL: http://llvm.org/viewvc/llvm-project?rev=114571&view=rev
Log:
Update testcases that expected internal functions to actually be internal.

Modified:
    poolalloc/trunk/test/dsa/td/call.c
    poolalloc/trunk/test/dsa/td/call.ll
    poolalloc/trunk/test/dsa/td/testcase.c
    poolalloc/trunk/test/dsa/td/testcase.ll

Modified: poolalloc/trunk/test/dsa/td/call.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call.c?rev=114571&r1=114570&r2=114571&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/call.c (original)
+++ poolalloc/trunk/test/dsa/td/call.c Wed Sep 22 14:12:10 2010
@@ -6,7 +6,7 @@
 #include <stdlib.h>
 
 
-int* test() {
+static int* test() {
   int* a2 = (int*)malloc(sizeof(int));
   *a2 = 10;
   

Modified: poolalloc/trunk/test/dsa/td/call.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call.ll?rev=114571&r1=114570&r2=114571&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/call.ll (original)
+++ poolalloc/trunk/test/dsa/td/call.ll Wed Sep 22 14:12:10 2010
@@ -8,7 +8,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
 
-define i32* @test() nounwind {
+define internal i32* @test() nounwind {
 entry:
   %retval = alloca i32*                           ; <i32**> [#uses=2]
   %0 = alloca i32*                                ; <i32**> [#uses=3]

Modified: poolalloc/trunk/test/dsa/td/testcase.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/testcase.c?rev=114571&r1=114570&r2=114571&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/testcase.c (original)
+++ poolalloc/trunk/test/dsa/td/testcase.c Wed Sep 22 14:12:10 2010
@@ -6,7 +6,7 @@
 #include <stdlib.h>
 
 
-int* test() {
+static int* test() {
   int* a2 = (int*)malloc(sizeof(int));
   return a2; 
     

Modified: poolalloc/trunk/test/dsa/td/testcase.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/testcase.ll?rev=114571&r1=114570&r2=114571&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/testcase.ll (original)
+++ poolalloc/trunk/test/dsa/td/testcase.ll Wed Sep 22 14:12:10 2010
@@ -5,7 +5,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
 
-define i32* @test() nounwind {
+define internal i32* @test() nounwind {
 entry:
   %retval = alloca i32*                           ; <i32**> [#uses=2]
   %0 = alloca i32*                                ; <i32**> [#uses=2]



From aggarwa4 at illinois.edu  Wed Sep 22 14:22:16 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Sep 2010 19:22:16 -0000
Subject: [llvm-commits] [poolalloc] r114572 - in
 /poolalloc/trunk/test/dsa/local: arrays1.c arrays1.ll
Message-ID: <20100922192216.74DB82A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Sep 22 14:22:16 2010
New Revision: 114572

URL: http://llvm.org/viewvc/llvm-project?rev=114572&view=rev
Log:
Added comments

Modified:
    poolalloc/trunk/test/dsa/local/arrays1.c
    poolalloc/trunk/test/dsa/local/arrays1.ll

Modified: poolalloc/trunk/test/dsa/local/arrays1.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrays1.c?rev=114572&r1=114571&r2=114572&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrays1.c (original)
+++ poolalloc/trunk/test/dsa/local/arrays1.c Wed Sep 22 14:22:16 2010
@@ -1,3 +1,6 @@
+// Checks that structure field offsets are calculated correctly
+// Checks that structure is folded
+
 //--Make sure we can run DSA on it! 
 //RUN: llvm-gcc %s -c --emit-llvm -o - |  \
 //RUN: dsaopt -dsa-bu -dsa-td -disable-output

Modified: poolalloc/trunk/test/dsa/local/arrays1.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrays1.ll?rev=114572&r1=114571&r2=114572&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrays1.ll (original)
+++ poolalloc/trunk/test/dsa/local/arrays1.ll Wed Sep 22 14:22:16 2010
@@ -1,5 +1,9 @@
+;Checks that structure field offsets are calculated correctly
+;Checks that structure is folded
+
 ;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:tmp:0:0,func:tmp:0
 ;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:c:0,func:tmp:0,func:s2:8
+;RUN: dsaopt %s -dsa-local -analyze -check-type=func:tmp:0,FoldedVOIDArray
 
 ; ModuleID = 'arrays1.bc'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"



From baldrick at free.fr  Wed Sep 22 15:02:46 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 22 Sep 2010 20:02:46 -0000
Subject: [llvm-commits] [zorg] r114573 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100922200246.5982E2A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep 22 15:02:46 2010
New Revision: 114573

URL: http://llvm.org/viewvc/llvm-project?rev=114573&view=rev
Log:
Add forgotten comma.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114573&r1=114572&r2=114573&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Sep 22 15:02:46 2010
@@ -85,7 +85,7 @@
         {'name' : "llvm-x86_64-linux-checks",
         'slavenames':["gcc10"],
         'builddir':"llvm-x86_64-linux-checks",
-        'factory':LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", expensive_checks=True)}
+        'factory':LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", expensive_checks=True)},
         {'name' : "llvm-gcc-i386-linux-selfhost",
          'slavenames':["gcc11"],
          'builddir':"llvm-gcc-i386-linux-selfhost",



From gohman at apple.com  Wed Sep 22 15:11:43 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 22 Sep 2010 20:11:43 -0000
Subject: [llvm-commits] [llvm] r114574 -
	/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
Message-ID: <20100922201143.DE0A42A6C12C@llvm.org>

Author: djg
Date: Wed Sep 22 15:11:43 2010
New Revision: 114574

URL: http://llvm.org/viewvc/llvm-project?rev=114574&view=rev
Log:
Constify.

Modified:
    llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h

Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=114574&r1=114573&r2=114574&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Wed Sep 22 15:11:43 2010
@@ -212,7 +212,7 @@
   private:
     /// ValueIsLoadPair - This is a pair<Value*, bool> where the bool is true if
     /// the dependence is a read only dependence, false if read/write.
-    typedef PointerIntPair<Value*, 1, bool> ValueIsLoadPair;
+    typedef PointerIntPair<const Value*, 1, bool> ValueIsLoadPair;
 
     /// BBSkipFirstBlockPair - This pair is used when caching information for a
     /// block.  If the pointer is null, the cache value is not a full query that



From grosbach at apple.com  Wed Sep 22 15:32:34 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 20:32:34 -0000
Subject: [llvm-commits] [llvm] r114576 -
	/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
Message-ID: <20100922203234.3BD9B2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 15:32:34 2010
New Revision: 114576

URL: http://llvm.org/viewvc/llvm-project?rev=114576&view=rev
Log:
Remove a few commented out bits

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=114576&r1=114575&r2=114576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Sep 22 15:32:34 2010
@@ -14,7 +14,6 @@
 
 #include "ARM.h"
 #include "ARMMCInstLower.h"
-//#include "llvm/CodeGen/MachineModuleInfoImpls.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/Constants.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -22,24 +21,11 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
-//#include "llvm/MC/MCStreamer.h"
 #include "llvm/Target/Mangler.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/SmallString.h"
 using namespace llvm;
 
-
-#if 0
-const ARMSubtarget &ARMMCInstLower::getSubtarget() const {
-  return AsmPrinter.getSubtarget();
-}
-
-MachineModuleInfoMachO &ARMMCInstLower::getMachOMMI() const {
-  assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin");
-  return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
-}
-#endif
-
 MCSymbol *ARMMCInstLower::GetGlobalAddressSymbol(const GlobalValue *GV) const {
   return Printer.Mang->getSymbol(GV);
 }



From echristo at apple.com  Wed Sep 22 15:42:09 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 22 Sep 2010 20:42:09 -0000
Subject: [llvm-commits] [llvm] r114577 -
	/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Message-ID: <20100922204209.27DF92A6C12C@llvm.org>

Author: echristo
Date: Wed Sep 22 15:42:08 2010
New Revision: 114577

URL: http://llvm.org/viewvc/llvm-project?rev=114577&view=rev
Log:
Temporarily work around new address lowering while I figure out what
needs to happen for darwin.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114577&r1=114576&r2=114577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Sep 22 15:42:08 2010
@@ -1149,7 +1149,8 @@
       // that are not a MemSDNode, and thus don't have proper addrspace info.
       Parent->getOpcode() != ISD::PREFETCH &&
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
-      Parent->getOpcode() != ISD::INTRINSIC_VOID) { // nontemporal stores.
+      Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
+      Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
     unsigned AddrSpace =
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
     // AddrSpace 256 -> GS, 257 -> FS.



From grosbach at apple.com  Wed Sep 22 15:55:15 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 20:55:15 -0000
Subject: [llvm-commits] [llvm] r114578 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100922205515.40CD62A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 15:55:15 2010
New Revision: 114578

URL: http://llvm.org/viewvc/llvm-project?rev=114578&view=rev
Log:
add FIXME

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114578&r1=114577&r2=114578&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 22 15:55:15 2010
@@ -1659,6 +1659,7 @@
       V1 = MCOperand::CreateExpr(SymRef1);
       V2 = MCOperand::CreateExpr(SymRef2);
     } else {
+      // FIXME: External symbol?
       MI->dump();
       llvm_unreachable("cannot handle this operand");
     }



From daniel at zuster.org  Wed Sep 22 16:07:08 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 21:07:08 -0000
Subject: [llvm-commits] [test-suite] r114579 - in
 /test-suite/trunk/SingleSource/UnitTests: conditional-gnu-ext-cxx.cpp
 conditional-gnu-ext-cxx.reference_output conditional-gnu-ext.cpp
Message-ID: <20100922210709.00A4B2A6C12C@llvm.org>

Author: ddunbar
Date: Wed Sep 22 16:07:08 2010
New Revision: 114579

URL: http://llvm.org/viewvc/llvm-project?rev=114579&view=rev
Log:
Rename conditional-gnu-ext.cpp, horrible implementation implies two tests can have same basename(1).

Added:
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.cpp
      - copied, changed from r114458, test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.reference_output
Removed:
    test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp

Copied: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.cpp (from r114458, test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp)
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.cpp?p2=test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.cpp&p1=test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp&r1=114458&r2=114579&rev=114579&view=diff
==============================================================================
    (empty)

Added: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.reference_output?rev=114579&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.reference_output (added)
+++ test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext-cxx.reference_output Wed Sep 22 16:07:08 2010
@@ -0,0 +1 @@
+exit 0

Removed: test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp?rev=114578&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp (original)
+++ test-suite/trunk/SingleSource/UnitTests/conditional-gnu-ext.cpp (removed)
@@ -1,36 +0,0 @@
-// rdar://8453812
-extern "C" void abort();
-
-_Complex int getComplex(_Complex int val) {
-  static int count;
-  if (count++)
-    abort();
-  return val;
-}
-
-_Complex int cmplx_test() {
-    _Complex int cond;
-    _Complex int rhs;
-
-    return getComplex(1+2i) ? : rhs;
-}
-
-// lvalue test
-int global = 1;
-void foo (int& lv) {
-  ++lv;
-}
-
-int &cond() {
-  static int count;
-  if (count++)
-    abort();
-  return global;
-}
-
-int  main() {
-    cmplx_test();
-    int rhs = 10;
-    foo (cond()? : rhs);
-    return  global-2;
-}



From daniel at zuster.org  Wed Sep 22 16:07:11 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 21:07:11 -0000
Subject: [llvm-commits] [test-suite] r114580 - in /test-suite/trunk:
 MultiSource/Makefile.multisrc SingleSource/Makefile.singlesrc
Message-ID: <20100922210711.52E7E2A6C12D@llvm.org>

Author: ddunbar
Date: Wed Sep 22 16:07:11 2010
New Revision: 114580

URL: http://llvm.org/viewvc/llvm-project?rev=114580&view=rev
Log:
TEST=simple: Add support for a new make variable, LD_ENV_OVERRIDES, which can be
used to set additional environment variables before calling link steps.

Modified:
    test-suite/trunk/MultiSource/Makefile.multisrc
    test-suite/trunk/SingleSource/Makefile.singlesrc

Modified: test-suite/trunk/MultiSource/Makefile.multisrc
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Makefile.multisrc?rev=114580&r1=114579&r2=114580&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Makefile.multisrc (original)
+++ test-suite/trunk/MultiSource/Makefile.multisrc Wed Sep 22 16:07:11 2010
@@ -90,7 +90,7 @@
 /^program/   { sum += $$2; }\
 !/^program/  { print; }\
 END       { printf("program %f\n", sum); }' > $@.compile.time
-	-$(LCXX) -o $@ $^ $(LDFLAGS) $(CFLAGS) $(TARGET_FLAGS)
+	-$(LD_ENV_OVERRIDES) $(LCXX) -o $@ $^ $(LDFLAGS) $(CFLAGS) $(TARGET_FLAGS)
 
 Output/%.native: $(NObjects)
 	-$(CXX) -o $@ $(NObjects) $(LDFLAGS) $(CFLAGS) $(TARGET_FLAGS)

Modified: test-suite/trunk/SingleSource/Makefile.singlesrc
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Makefile.singlesrc?rev=114580&r1=114579&r2=114580&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Makefile.singlesrc (original)
+++ test-suite/trunk/SingleSource/Makefile.singlesrc Wed Sep 22 16:07:11 2010
@@ -70,7 +70,7 @@
 
 Output/%.simple: Output/%.llvm.o Output/.dir
 	-$(CP) $<.compile.time $@.compile.time
-	-$(LCXX) -o $@ $< $(LDFLAGS) $(CFLAGS) $(TARGET_FLAGS)
+	-$(LD_ENV_OVERRIDES) $(LCXX) -o $@ $< $(LDFLAGS) $(CFLAGS) $(TARGET_FLAGS)
 
 # FIXME: LIBS should be specified, not hardcoded to -lm
 Output/%.native: $(SourceDir)/%.c Output/.dir



From daniel at zuster.org  Wed Sep 22 16:10:17 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 21:10:17 -0000
Subject: [llvm-commits] [zorg] r114582 - in /zorg/trunk/lnt/lnt:
 testing/util/compilers.py tests/nt.py
Message-ID: <20100922211017.5E19A2A6C12C@llvm.org>

Author: ddunbar
Date: Wed Sep 22 16:10:17 2010
New Revision: 114582

URL: http://llvm.org/viewvc/llvm-project?rev=114582&view=rev
Log:
LNT/nt: Change get_cc_info to pickup the 'as' and 'ld' versions as the compiler
would find them (using the flags under test). This makes sure we capture the
appropriate version and information even with things like sysroot flags, etc.

Modified:
    zorg/trunk/lnt/lnt/testing/util/compilers.py
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/testing/util/compilers.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/testing/util/compilers.py?rev=114582&r1=114581&r2=114582&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/testing/util/compilers.py (original)
+++ zorg/trunk/lnt/lnt/testing/util/compilers.py Wed Sep 22 16:10:17 2010
@@ -1,8 +1,10 @@
 import hashlib
 import re
+import tempfile
 
-from commands import error
 from commands import capture
+from commands import error
+from commands import rm_f
 
 def get_cc_info(path, cc_flags=[]):
     """get_cc_info(path) -> { ... }
@@ -107,6 +109,19 @@
             error("unable to determine LLVM compiler target: %r: %r" %
                   (cc, target_cc_ll))
 
+    # Determine the binary tool versions for the assembler and the linker, as
+    # found by the compiler.
+    cc_as_version = capture([cc, "-c", '-Wa,-v'] + cc_flags +
+                            ['-x', 'assembler', '/dev/null'],
+                            include_stderr=True).strip()
+
+    tf = tempfile.NamedTemporaryFile(suffix='.c', delete=False)
+    print >>tf, "int main() { return 0; }"
+    tf.close()
+    cc_ld_version = capture([cc, "-Wl,-v"] + cc_flags + [tf.name],
+                            include_stderr=True).strip()
+    rm_f(tf.name)
+
     cc_exec_hash = hashlib.sha1()
     cc_exec_hash.update(open(cc,'rb').read())
 
@@ -120,6 +135,8 @@
              'cc_version' :cc_version,
              'cc_exec_hash' : cc_exec_hash.hexdigest(),
              'cc1_exec_hash' : cc1_exec_hash.hexdigest(),
+             'cc_as_version' : cc_as_version,
+             'cc_ld_version' : cc_ld_version,
              }
     if cc_src_tag is not None:
         info['cc_src_tag'] = cc_src_tag

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=114582&r1=114581&r2=114582&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Wed Sep 22 16:10:17 2010
@@ -443,11 +443,6 @@
     # Create the machine entry.
     machine = lnt.testing.Machine(nick, machine_info)
 
-    # Capture binary tool versions.
-    run_info['as_version'] = capture(["gcc", "-c", "-xassembler", "/dev/null",
-                                      "-Wa,-v"], include_stderr=True).strip()
-    run_info['ld_version'] = capture(["ld", "-v"], include_stderr=True).strip()
-
     # FIXME: Hack, use better method of getting versions. Ideally, from binaries
     # so we are more likely to be accurate.
     run_info['llvm_revision'] = llvm_source_version



From daniel at zuster.org  Wed Sep 22 16:10:19 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 21:10:19 -0000
Subject: [llvm-commits] [zorg] r114583 - /zorg/trunk/lnt/lnt/tests/nt.py
Message-ID: <20100922211019.9C4142A6C12D@llvm.org>

Author: ddunbar
Date: Wed Sep 22 16:10:19 2010
New Revision: 114583

URL: http://llvm.org/viewvc/llvm-project?rev=114583&view=rev
Log:
LNT/nt: Add --liblto-path command line option, which does the extra setup necessary to test libLTO (currently by overriding DYLD_LIBRARY_PATH under the covers).

Modified:
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=114583&r1=114582&r2=114583&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Wed Sep 22 16:10:19 2010
@@ -114,6 +114,10 @@
         make_variables['SMALL_PROBLEM_SIZE'] = '1'
     if opts.test_integrated_as:
         make_variables['TEST_INTEGRATED_AS'] = '1'
+    if opts.liblto_path:
+        make_variables['LD_ENV_OVERRIDES'] = (
+            'env DYLD_LIBRARY_PATH=%s' % os.path.dirname(
+                opts.liblto_path))
 
     if opts.threads > 1:
         make_variables['ENABLE_PARALLEL_REPORT'] = '1'
@@ -593,6 +597,11 @@
         group.add_option("", "--isysroot", dest="isysroot", metavar="PATH",
                          help="Set -isysroot in TARGET_FLAGS [%default]",
                          type=str, default=None)
+        group.add_option("", "--liblto-path", dest="liblto_path",
+                         metavar="PATH",
+                         help=("Specify the path to the libLTO library "
+                               "[%default]"),
+                         type=str, default=None)
 
         group.add_option("", "--mcpu", dest="mcpu",
                          help="Set -mcpu in TARGET_LLCFLAGS [%default]",
@@ -751,6 +760,12 @@
             if opts.remote_user is None:
                 parser.error('--remote-user is required with --remote')
 
+        # libLTO should exist, if given.
+        if opts.liblto_path:
+            if not os.path.exists(opts.liblto_path):
+                parser.error('invalid --liblto-path argument %r' % (
+                        opts.liblto_path,))
+
         # FIXME: We need to validate that there is no configured output in the
         # test-suite directory, that borks things. <rdar://problem/7876418>
 



From daniel at zuster.org  Wed Sep 22 16:10:21 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 21:10:21 -0000
Subject: [llvm-commits] [zorg] r114584 - /zorg/trunk/lnt/lnt/tests/nt.py
Message-ID: <20100922211021.D9D9E2A6C12E@llvm.org>

Author: ddunbar
Date: Wed Sep 22 16:10:21 2010
New Revision: 114584

URL: http://llvm.org/viewvc/llvm-project?rev=114584&view=rev
Log:
LNT/nt: Set additional Makefile variables for use in conditionalizing nightly test runs.
 - Set CC_UNDER_TEST_IS_LLVM_GCC and CC_UNDER_TEST_IS_GCC, a la CC_UNDER_TEST_IS_CLANG.

 - Set CC_UNDER_TEST_TARGET_IS_FOO where FOO is derived from the target triple. Useful for determining ARMv7, for example, given that we mangle it into the triple in a most horrible fashion. And now I am introducing a dependency on that horribleness, have I no shame?!?

Modified:
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=114584&r1=114583&r2=114584&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Wed Sep 22 16:10:21 2010
@@ -143,6 +143,16 @@
     # Set CC_UNDER_TEST_IS_CLANG when appropriate.
     if cc_info.get('cc_name') in ('apple_clang', 'clang'):
         make_variables['CC_UNDER_TEST_IS_CLANG'] = '1'
+    elif cc_info.get('cc_name') in ('llvm-gcc',):
+        make_variables['CC_UNDER_TEST_IS_LLVM_GCC'] = '1'
+    elif cc_info.get('cc_name') in ('gcc',):
+        make_variables['CC_UNDER_TEST_IS_GCC'] = '1'
+
+    # Convert the target arch into a make variable, to allow more target based
+    # specialization (e.g., CC_UNDER_TEST_TARGET_IS_ARMV7).
+    if '-' in cc_info.get('cc_target', ''):
+        arch_name = cc_info.get('cc_target').split('-',1)[0]
+        make_variables['CC_UNDER_TEST_TARGET_IS_' + arch_name.upper()] = '1'
 
     # Set LLVM_RELEASE_IS_PLUS_ASSERTS when appropriate, to allow testing older
     # LLVM source trees.



From dpatel at apple.com  Wed Sep 22 16:10:38 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 22 Sep 2010 21:10:38 -0000
Subject: [llvm-commits] [llvm] r114585 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20100922211039.014472A6C12C@llvm.org>

Author: dpatel
Date: Wed Sep 22 16:10:38 2010
New Revision: 114585

URL: http://llvm.org/viewvc/llvm-project?rev=114585&view=rev
Log:
Use DW_OP_fbreg when offset is based on frame register.


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=114585&r1=114584&r2=114585&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Sep 22 16:10:38 2010
@@ -811,6 +811,16 @@
   const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
   unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false);
   DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
+  const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
+
+  if (TRI->getFrameRegister(*Asm->MF) == Location.getReg()
+      && Location.getOffset()) {
+    // If variable offset is based in frame register then use fbreg.
+    addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_fbreg);
+    addSInt(Block, 0, dwarf::DW_FORM_sdata, Location.getOffset());
+    addBlock(Die, Attribute, 0, Block);
+    return;
+  }
 
   if (Location.isReg()) {
     if (Reg < 32) {



From clattner at apple.com  Wed Sep 22 16:37:14 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 22 Sep 2010 14:37:14 -0700
Subject: [llvm-commits] [llvm] r114563 - in
	/llvm/trunk/lib/Target/ARM/AsmPrinter: ARMInstPrinter.cpp
	ARMInstPrinter.h
In-Reply-To: <20100922183715.0379D2A6C12C@llvm.org>
References: <20100922183715.0379D2A6C12C@llvm.org>
Message-ID: <E28949E6-9B65-4EDB-82E0-A599D1C7E317@apple.com>


On Sep 22, 2010, at 11:37 AM, Jim Grosbach wrote:

> Author: grosbach
> Date: Wed Sep 22 13:37:14 2010
> New Revision: 114563
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114563&view=rev
> Log:
> Add PrintSpecial() handling for  in ARM MC instruction printer.

Hi Jim,

What instructions are using ${:comment}?  Are they pseudo instructions that should be handled at mcinst lowering time?  Would a disassembler ever create them?

-Chris

> 
> Modified:
>    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
>    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
> 
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=114563&r1=114562&r2=114563&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Sep 22 13:37:14 2010
> @@ -736,3 +736,11 @@
>   uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
>   O << "#0x" << utohexstr(Val);
> }
> +
> +void ARMInstPrinter::PrintSpecial(const MCInst *MI, raw_ostream &O,
> +                                  const char *Kind) {
> +  if (strcmp(Kind, "comment") == 0)
> +    O << "@";
> +  else
> +    abort();
> +}
> 
> Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=114563&r1=114562&r2=114563&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original)
> +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Wed Sep 22 13:37:14 2010
> @@ -110,8 +110,7 @@
>   void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
> 
>   void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
> -  // FIXME: Implement.
> -  void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind) {}
> +  void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind);
> };
> 
> }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From gohman at apple.com  Wed Sep 22 16:41:02 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 22 Sep 2010 21:41:02 -0000
Subject: [llvm-commits] [llvm] r114588 - in /llvm/trunk:
 include/llvm/Analysis/MemoryDependenceAnalysis.h
 lib/Analysis/MemoryDependenceAnalysis.cpp
Message-ID: <20100922214102.CED042A6C12C@llvm.org>

Author: djg
Date: Wed Sep 22 16:41:02 2010
New Revision: 114588

URL: http://llvm.org/viewvc/llvm-project?rev=114588&view=rev
Log:
Teach memdep about TBAA tags.

Modified:
    llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp

Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=114588&r1=114587&r2=114588&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Wed Sep 22 16:41:02 2010
@@ -17,6 +17,7 @@
 #include "llvm/BasicBlock.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/ValueHandle.h"
+#include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/OwningPtr.h"
@@ -220,11 +221,23 @@
     /// or not the contents of the block was skipped.
     typedef PointerIntPair<BasicBlock*, 1, bool> BBSkipFirstBlockPair;
 
+    /// NonLocalPointerInfo - This record is the information kept for each
+    /// (value, is load) pair.
+    struct NonLocalPointerInfo {
+      /// Pair - The pair of the block and the skip-first-block flag.
+      BBSkipFirstBlockPair Pair;
+      /// NonLocalDeps - The results of the query for each relevant block.
+      NonLocalDepInfo NonLocalDeps;
+      /// TBAATag - The TBAA tag associated with dereferences of the
+      /// pointer. May be null if there are no tags or conflicting tags.
+      MDNode *TBAATag;
+    };
+
     /// CachedNonLocalPointerInfo - This map stores the cached results of doing
     /// a pointer lookup at the bottom of a block.  The key of this map is the
     /// pointer+isload bit, the value is a list of <bb->result> mappings.
-    typedef DenseMap<ValueIsLoadPair, std::pair<BBSkipFirstBlockPair, 
-                  NonLocalDepInfo> > CachedNonLocalPointerInfo;
+    typedef DenseMap<ValueIsLoadPair,
+                     NonLocalPointerInfo> CachedNonLocalPointerInfo;
     CachedNonLocalPointerInfo NonLocalPointerDeps;
 
     // A map from instructions to their non-local pointer dependencies.
@@ -297,9 +310,17 @@
     /// set of instructions that either define or clobber the value.
     ///
     /// This method assumes the pointer has a "NonLocal" dependency within BB.
+    void getNonLocalPointerDependency(const AliasAnalysis::Location &Loc,
+                                      bool isLoad, BasicBlock *BB,
+                                    SmallVectorImpl<NonLocalDepResult> &Result);
+
+    /// getNonLocalPointerDependence - A convenience wrapper.
     void getNonLocalPointerDependency(Value *Pointer, bool isLoad,
                                       BasicBlock *BB,
-                                    SmallVectorImpl<NonLocalDepResult> &Result);
+                                    SmallVectorImpl<NonLocalDepResult> &Result){
+      return getNonLocalPointerDependency(AliasAnalysis::Location(Pointer),
+                                          isLoad, BB, Result);
+    }
     
     /// removeInstruction - Remove an instruction from the dependence analysis,
     /// updating the dependence of instructions that previously depended on it.
@@ -319,19 +340,20 @@
     void invalidateCachedPredecessors();
     
   private:
-    MemDepResult getPointerDependencyFrom(Value *Pointer, uint64_t MemSize,
+    MemDepResult getPointerDependencyFrom(const AliasAnalysis::Location &Loc,
                                           bool isLoad, 
                                           BasicBlock::iterator ScanIt,
                                           BasicBlock *BB);
     MemDepResult getCallSiteDependencyFrom(CallSite C, bool isReadOnlyCall,
                                            BasicBlock::iterator ScanIt,
                                            BasicBlock *BB);
-    bool getNonLocalPointerDepFromBB(const PHITransAddr &Pointer, uint64_t Size,
+    bool getNonLocalPointerDepFromBB(const PHITransAddr &Pointer,
+                                     const AliasAnalysis::Location &Loc,
                                      bool isLoad, BasicBlock *BB,
                                      SmallVectorImpl<NonLocalDepResult> &Result,
                                      DenseMap<BasicBlock*, Value*> &Visited,
                                      bool SkipFirstBlock = false);
-    MemDepResult GetNonLocalInfoForBlock(Value *Pointer, uint64_t PointeeSize,
+    MemDepResult GetNonLocalInfoForBlock(const AliasAnalysis::Location &Loc,
                                          bool isLoad, BasicBlock *BB,
                                          NonLocalDepInfo *Cache,
                                          unsigned NumSortedEntries);

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=114588&r1=114587&r2=114588&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Sep 22 16:41:02 2010
@@ -19,6 +19,7 @@
 #include "llvm/Instructions.h"
 #include "llvm/IntrinsicInst.h"
 #include "llvm/Function.h"
+#include "llvm/LLVMContext.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/Dominators.h"
 #include "llvm/Analysis/InstructionSimplify.h"
@@ -108,18 +109,19 @@
     Instruction *Inst = --ScanIt;
     
     // If this inst is a memory op, get the pointer it accessed
-    Value *Pointer = 0;
-    uint64_t PointerSize = 0;
+    AliasAnalysis::Location Loc;
     if (StoreInst *S = dyn_cast<StoreInst>(Inst)) {
-      Pointer = S->getPointerOperand();
-      PointerSize = AA->getTypeStoreSize(S->getOperand(0)->getType());
+      Loc = AliasAnalysis::Location(S->getPointerOperand(),
+                                    AA->getTypeStoreSize(S->getValueOperand()
+                                                           ->getType()),
+                                    S->getMetadata(LLVMContext::MD_tbaa));
     } else if (VAArgInst *V = dyn_cast<VAArgInst>(Inst)) {
-      Pointer = V->getOperand(0);
-      PointerSize = AA->getTypeStoreSize(V->getType());
+      Loc = AliasAnalysis::Location(V->getPointerOperand(),
+                                    AA->getTypeStoreSize(V->getType()),
+                                    V->getMetadata(LLVMContext::MD_tbaa));
     } else if (const CallInst *CI = isFreeCall(Inst)) {
-      Pointer = CI->getArgOperand(0);
       // calls to free() erase the entire structure
-      PointerSize = ~0ULL;
+      Loc = AliasAnalysis::Location(CI->getArgOperand(0));
     } else if (CallSite InstCS = cast<Value>(Inst)) {
       // Debug intrinsics don't cause dependences.
       if (isa<DbgInfoIntrinsic>(Inst)) continue;
@@ -143,7 +145,7 @@
       continue;
     }
     
-    if (AA->getModRefInfo(CS, Pointer, PointerSize) != AliasAnalysis::NoModRef)
+    if (AA->getModRefInfo(CS, Loc) != AliasAnalysis::NoModRef)
       return MemDepResult::getClobber(Inst);
   }
   
@@ -158,7 +160,7 @@
 /// location depends.  If isLoad is true, this routine ignore may-aliases with
 /// read-only operations.
 MemDepResult MemoryDependenceAnalysis::
-getPointerDependencyFrom(Value *MemPtr, uint64_t MemSize, bool isLoad, 
+getPointerDependencyFrom(const AliasAnalysis::Location &MemLoc, bool isLoad, 
                          BasicBlock::iterator ScanIt, BasicBlock *BB) {
 
   Value *InvariantTag = 0;
@@ -184,7 +186,8 @@
         // FIXME: This only considers queries directly on the invariant-tagged
         // pointer, not on query pointers that are indexed off of them.  It'd
         // be nice to handle that at some point.
-        AliasAnalysis::AliasResult R = AA->alias(II->getArgOperand(2), MemPtr);
+        AliasAnalysis::AliasResult R =
+          AA->alias(AliasAnalysis::Location(II->getArgOperand(2)), MemLoc);
         if (R == AliasAnalysis::MustAlias)
           InvariantTag = II->getArgOperand(0);
 
@@ -197,7 +200,8 @@
         // FIXME: This only considers queries directly on the invariant-tagged
         // pointer, not on query pointers that are indexed off of them.  It'd
         // be nice to handle that at some point.
-        AliasAnalysis::AliasResult R = AA->alias(II->getArgOperand(1), MemPtr);
+        AliasAnalysis::AliasResult R =
+          AA->alias(AliasAnalysis::Location(II->getArgOperand(1)), MemLoc);
         if (R == AliasAnalysis::MustAlias)
           return MemDepResult::getDef(II);
         continue;
@@ -216,10 +220,12 @@
     if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
       Value *Pointer = LI->getPointerOperand();
       uint64_t PointerSize = AA->getTypeStoreSize(LI->getType());
+      MDNode *TBAATag = LI->getMetadata(LLVMContext::MD_tbaa);
       
       // If we found a pointer, check if it could be the same as our pointer.
       AliasAnalysis::AliasResult R =
-        AA->alias(Pointer, PointerSize, MemPtr, MemSize);
+        AA->alias(AliasAnalysis::Location(Pointer, PointerSize, TBAATag),
+                  MemLoc);
       if (R == AliasAnalysis::NoAlias)
         continue;
       
@@ -239,17 +245,19 @@
       // If alias analysis can tell that this store is guaranteed to not modify
       // the query pointer, ignore it.  Use getModRefInfo to handle cases where
       // the query pointer points to constant memory etc.
-      if (AA->getModRefInfo(SI, MemPtr, MemSize) == AliasAnalysis::NoModRef)
+      if (AA->getModRefInfo(SI, MemLoc) == AliasAnalysis::NoModRef)
         continue;
 
       // Ok, this store might clobber the query pointer.  Check to see if it is
       // a must alias: in this case, we want to return this as a def.
       Value *Pointer = SI->getPointerOperand();
       uint64_t PointerSize = AA->getTypeStoreSize(SI->getOperand(0)->getType());
+      MDNode *TBAATag = SI->getMetadata(LLVMContext::MD_tbaa);
       
       // If we found a pointer, check if it could be the same as our pointer.
       AliasAnalysis::AliasResult R =
-        AA->alias(Pointer, PointerSize, MemPtr, MemSize);
+        AA->alias(AliasAnalysis::Location(Pointer, PointerSize, TBAATag),
+                  MemLoc);
       
       if (R == AliasAnalysis::NoAlias)
         continue;
@@ -268,7 +276,7 @@
     // need to continue scanning until the malloc call.
     if (isa<AllocaInst>(Inst) ||
         (isa<CallInst>(Inst) && extractMallocCall(Inst))) {
-      Value *AccessPtr = MemPtr->getUnderlyingObject();
+      const Value *AccessPtr = MemLoc.Ptr->getUnderlyingObject();
       
       if (AccessPtr == Inst ||
           AA->alias(Inst, 1, AccessPtr, 1) == AliasAnalysis::MustAlias)
@@ -277,7 +285,7 @@
     }
 
     // See if this instruction (e.g. a call or vaarg) mod/ref's the pointer.
-    switch (AA->getModRefInfo(Inst, MemPtr, MemSize)) {
+    switch (AA->getModRefInfo(Inst, MemLoc)) {
     case AliasAnalysis::NoModRef:
       // If the call has no effect on the queried pointer, just ignore it.
       continue;
@@ -327,8 +335,7 @@
   
   BasicBlock *QueryParent = QueryInst->getParent();
   
-  Value *MemPtr = 0;
-  uint64_t MemSize = 0;
+  AliasAnalysis::Location MemLoc;
   
   // Do the scan.
   if (BasicBlock::iterator(QueryInst) == QueryParent->begin()) {
@@ -343,23 +350,23 @@
     // previous instruction as a clobber.
     if (SI->isVolatile())
       LocalCache = MemDepResult::getClobber(--BasicBlock::iterator(ScanPos));
-    else {
-      MemPtr = SI->getPointerOperand();
-      MemSize = AA->getTypeStoreSize(SI->getOperand(0)->getType());
-    }
+    else
+      MemLoc = AliasAnalysis::Location(SI->getPointerOperand(),
+                                       AA->getTypeStoreSize(SI->getOperand(0)
+                                                              ->getType()),
+                                       SI->getMetadata(LLVMContext::MD_tbaa));
   } else if (LoadInst *LI = dyn_cast<LoadInst>(QueryInst)) {
     // If this is a volatile load, don't mess around with it.  Just return the
     // previous instruction as a clobber.
     if (LI->isVolatile())
       LocalCache = MemDepResult::getClobber(--BasicBlock::iterator(ScanPos));
-    else {
-      MemPtr = LI->getPointerOperand();
-      MemSize = AA->getTypeStoreSize(LI->getType());
-    }
+    else
+      MemLoc = AliasAnalysis::Location(LI->getPointerOperand(),
+                                       AA->getTypeStoreSize(LI->getType()),
+                                       LI->getMetadata(LLVMContext::MD_tbaa));
   } else if (const CallInst *CI = isFreeCall(QueryInst)) {
-    MemPtr = CI->getArgOperand(0);
     // calls to free() erase the entire structure, not just a field.
-    MemSize = ~0UL;
+    MemLoc = AliasAnalysis::Location(CI->getArgOperand(0));
   } else if (isa<CallInst>(QueryInst) || isa<InvokeInst>(QueryInst)) {
     int IntrinsicID = 0;  // Intrinsic IDs start at 1.
     IntrinsicInst *II = dyn_cast<IntrinsicInst>(QueryInst);
@@ -370,12 +377,16 @@
     case Intrinsic::lifetime_start:
     case Intrinsic::lifetime_end:
     case Intrinsic::invariant_start:
-      MemPtr = II->getArgOperand(1);
-      MemSize = cast<ConstantInt>(II->getArgOperand(0))->getZExtValue();
+      MemLoc = AliasAnalysis::Location(II->getArgOperand(1),
+                                       cast<ConstantInt>(II->getArgOperand(0))
+                                         ->getZExtValue(),
+                                       II->getMetadata(LLVMContext::MD_tbaa));
       break;
     case Intrinsic::invariant_end:
-      MemPtr = II->getArgOperand(2);
-      MemSize = cast<ConstantInt>(II->getArgOperand(1))->getZExtValue();
+      MemLoc = AliasAnalysis::Location(II->getArgOperand(2),
+                                       cast<ConstantInt>(II->getArgOperand(1))
+                                         ->getZExtValue(),
+                                       II->getMetadata(LLVMContext::MD_tbaa));
       break;
     default:
       CallSite QueryCS(QueryInst);
@@ -390,12 +401,12 @@
   }
   
   // If we need to do a pointer scan, make it happen.
-  if (MemPtr) {
+  if (MemLoc.Ptr) {
     bool isLoad = !QueryInst->mayWriteToMemory();
     if (IntrinsicInst *II = dyn_cast<MemoryUseIntrinsic>(QueryInst)) {
       isLoad |= II->getIntrinsicID() == Intrinsic::lifetime_end;
     }
-    LocalCache = getPointerDependencyFrom(MemPtr, MemSize, isLoad, ScanPos,
+    LocalCache = getPointerDependencyFrom(MemLoc, isLoad, ScanPos,
                                           QueryParent);
   }
   
@@ -570,31 +581,27 @@
 /// own block.
 ///
 void MemoryDependenceAnalysis::
-getNonLocalPointerDependency(Value *Pointer, bool isLoad, BasicBlock *FromBB,
+getNonLocalPointerDependency(const AliasAnalysis::Location &Loc, bool isLoad,
+                             BasicBlock *FromBB,
                              SmallVectorImpl<NonLocalDepResult> &Result) {
-  assert(Pointer->getType()->isPointerTy() &&
+  assert(Loc.Ptr->getType()->isPointerTy() &&
          "Can't get pointer deps of a non-pointer!");
   Result.clear();
   
-  // We know that the pointer value is live into FromBB find the def/clobbers
-  // from presecessors.
-  const Type *EltTy = cast<PointerType>(Pointer->getType())->getElementType();
-  uint64_t PointeeSize = AA->getTypeStoreSize(EltTy);
-  
-  PHITransAddr Address(Pointer, TD);
+  PHITransAddr Address(const_cast<Value *>(Loc.Ptr), TD);
   
   // This is the set of blocks we've inspected, and the pointer we consider in
   // each block.  Because of critical edges, we currently bail out if querying
   // a block with multiple different pointers.  This can happen during PHI
   // translation.
   DenseMap<BasicBlock*, Value*> Visited;
-  if (!getNonLocalPointerDepFromBB(Address, PointeeSize, isLoad, FromBB,
+  if (!getNonLocalPointerDepFromBB(Address, Loc, isLoad, FromBB,
                                    Result, Visited, true))
     return;
   Result.clear();
   Result.push_back(NonLocalDepResult(FromBB,
                                      MemDepResult::getClobber(FromBB->begin()),
-                                     Pointer));
+                                     const_cast<Value *>(Loc.Ptr)));
 }
 
 /// GetNonLocalInfoForBlock - Compute the memdep value for BB with
@@ -602,7 +609,7 @@
 /// lookup (which may use dirty cache info if available).  If we do a lookup,
 /// add the result to the cache.
 MemDepResult MemoryDependenceAnalysis::
-GetNonLocalInfoForBlock(Value *Pointer, uint64_t PointeeSize,
+GetNonLocalInfoForBlock(const AliasAnalysis::Location &Loc,
                         bool isLoad, BasicBlock *BB,
                         NonLocalDepInfo *Cache, unsigned NumSortedEntries) {
   
@@ -636,15 +643,14 @@
     ScanPos = ExistingResult->getResult().getInst();
     
     // Eliminating the dirty entry from 'Cache', so update the reverse info.
-    ValueIsLoadPair CacheKey(Pointer, isLoad);
+    ValueIsLoadPair CacheKey(Loc.Ptr, isLoad);
     RemoveFromReverseMap(ReverseNonLocalPtrDeps, ScanPos, CacheKey);
   } else {
     ++NumUncacheNonLocalPtr;
   }
   
   // Scan the block for the dependency.
-  MemDepResult Dep = getPointerDependencyFrom(Pointer, PointeeSize, isLoad, 
-                                              ScanPos, BB);
+  MemDepResult Dep = getPointerDependencyFrom(Loc, isLoad, ScanPos, BB);
   
   // If we had a dirty entry for the block, update it.  Otherwise, just add
   // a new entry.
@@ -663,7 +669,7 @@
   // update MemDep when we remove instructions.
   Instruction *Inst = Dep.getInst();
   assert(Inst && "Didn't depend on anything?");
-  ValueIsLoadPair CacheKey(Pointer, isLoad);
+  ValueIsLoadPair CacheKey(Loc.Ptr, isLoad);
   ReverseNonLocalPtrDeps[Inst].insert(CacheKey);
   return Dep;
 }
@@ -717,7 +723,8 @@
 /// not compute dependence information for some reason.  This should be treated
 /// as a clobber dependence on the first instruction in the predecessor block.
 bool MemoryDependenceAnalysis::
-getNonLocalPointerDepFromBB(const PHITransAddr &Pointer, uint64_t PointeeSize,
+getNonLocalPointerDepFromBB(const PHITransAddr &Pointer,
+                            const AliasAnalysis::Location &Loc,
                             bool isLoad, BasicBlock *StartBB,
                             SmallVectorImpl<NonLocalDepResult> &Result,
                             DenseMap<BasicBlock*, Value*> &Visited,
@@ -725,14 +732,23 @@
   
   // Look up the cached info for Pointer.
   ValueIsLoadPair CacheKey(Pointer.getAddr(), isLoad);
-  
-  std::pair<BBSkipFirstBlockPair, NonLocalDepInfo> *CacheInfo =
-    &NonLocalPointerDeps[CacheKey];
-  NonLocalDepInfo *Cache = &CacheInfo->second;
+  NonLocalPointerInfo *CacheInfo = &NonLocalPointerDeps[CacheKey];
+
+  // If this query's TBAATag is inconsistent with the cached one, discard the
+  // tag and restart the query.
+  if (CacheInfo->TBAATag != Loc.TBAATag) {
+    CacheInfo->TBAATag = 0;
+    NonLocalPointerDeps.erase(CacheKey);
+    return getNonLocalPointerDepFromBB(Pointer, Loc.getWithoutTBAATag(),
+                                       isLoad, StartBB, Result, Visited,
+                                       SkipFirstBlock);
+  }
+
+  NonLocalDepInfo *Cache = &CacheInfo->NonLocalDeps;
 
   // If we have valid cached information for exactly the block we are
   // investigating, just return it with no recomputation.
-  if (CacheInfo->first == BBSkipFirstBlockPair(StartBB, SkipFirstBlock)) {
+  if (CacheInfo->Pair == BBSkipFirstBlockPair(StartBB, SkipFirstBlock)) {
     // We have a fully cached result for this query then we can just return the
     // cached results and populate the visited set.  However, we have to verify
     // that we don't already have conflicting results for these blocks.  Check
@@ -768,9 +784,11 @@
   // than its valid cache info.  If empty, the result will be valid cache info,
   // otherwise it isn't.
   if (Cache->empty())
-    CacheInfo->first = BBSkipFirstBlockPair(StartBB, SkipFirstBlock);
-  else
-    CacheInfo->first = BBSkipFirstBlockPair();
+    CacheInfo->Pair = BBSkipFirstBlockPair(StartBB, SkipFirstBlock);
+  else {
+    CacheInfo->Pair = BBSkipFirstBlockPair();
+    CacheInfo->TBAATag = 0;
+  }
   
   SmallVector<BasicBlock*, 32> Worklist;
   Worklist.push_back(StartBB);
@@ -795,8 +813,7 @@
       // Get the dependency info for Pointer in BB.  If we have cached
       // information, we will use it, otherwise we compute it.
       DEBUG(AssertSorted(*Cache, NumSortedEntries));
-      MemDepResult Dep = GetNonLocalInfoForBlock(Pointer.getAddr(), PointeeSize,
-                                                 isLoad, BB, Cache,
+      MemDepResult Dep = GetNonLocalInfoForBlock(Loc, isLoad, BB, Cache,
                                                  NumSortedEntries);
       
       // If we got a Def or Clobber, add this to the list of results.
@@ -893,7 +910,9 @@
         // queries.  Mark this in NonLocalPointerDeps by setting the
         // BBSkipFirstBlockPair pointer to null.  This requires reuse of the
         // cached value to do more work but not miss the phi trans failure.
-        NonLocalPointerDeps[CacheKey].first = BBSkipFirstBlockPair();
+        NonLocalPointerInfo &NLPI = NonLocalPointerDeps[CacheKey];
+        NLPI.Pair = BBSkipFirstBlockPair();
+        NLPI.TBAATag = 0;
         continue;
       }
 
@@ -904,21 +923,24 @@
       
       // If we have a problem phi translating, fall through to the code below
       // to handle the failure condition.
-      if (getNonLocalPointerDepFromBB(PredPointer, PointeeSize, isLoad, Pred,
+      if (getNonLocalPointerDepFromBB(PredPointer,
+                                      Loc.getWithNewPtr(PredPointer.getAddr()),
+                                      isLoad, Pred,
                                       Result, Visited))
         goto PredTranslationFailure;
     }
     
     // Refresh the CacheInfo/Cache pointer so that it isn't invalidated.
     CacheInfo = &NonLocalPointerDeps[CacheKey];
-    Cache = &CacheInfo->second;
+    Cache = &CacheInfo->NonLocalDeps;
     NumSortedEntries = Cache->size();
     
     // Since we did phi translation, the "Cache" set won't contain all of the
     // results for the query.  This is ok (we can still use it to accelerate
     // specific block queries) but we can't do the fastpath "return all
     // results from the set"  Clear out the indicator for this.
-    CacheInfo->first = BBSkipFirstBlockPair();
+    CacheInfo->Pair = BBSkipFirstBlockPair();
+    CacheInfo->TBAATag = 0;
     SkipFirstBlock = false;
     continue;
 
@@ -927,7 +949,7 @@
     if (Cache == 0) {
       // Refresh the CacheInfo/Cache pointer if it got invalidated.
       CacheInfo = &NonLocalPointerDeps[CacheKey];
-      Cache = &CacheInfo->second;
+      Cache = &CacheInfo->NonLocalDeps;
       NumSortedEntries = Cache->size();
     }
     
@@ -935,7 +957,8 @@
     // results for the query.  This is ok (we can still use it to accelerate
     // specific block queries) but we can't do the fastpath "return all
     // results from the set".  Clear out the indicator for this.
-    CacheInfo->first = BBSkipFirstBlockPair();
+    CacheInfo->Pair = BBSkipFirstBlockPair();
+    CacheInfo->TBAATag = 0;
     
     // If *nothing* works, mark the pointer as being clobbered by the first
     // instruction in this block.
@@ -977,7 +1000,7 @@
   
   // Remove all of the entries in the BB->val map.  This involves removing
   // instructions from the reverse map.
-  NonLocalDepInfo &PInfo = It->second.second;
+  NonLocalDepInfo &PInfo = It->second.NonLocalDeps;
   
   for (unsigned i = 0, e = PInfo.size(); i != e; ++i) {
     Instruction *Target = PInfo[i].getResult().getInst();
@@ -1148,10 +1171,11 @@
       assert(P.getPointer() != RemInst &&
              "Already removed NonLocalPointerDeps info for RemInst");
       
-      NonLocalDepInfo &NLPDI = NonLocalPointerDeps[P].second;
+      NonLocalDepInfo &NLPDI = NonLocalPointerDeps[P].NonLocalDeps;
       
       // The cache is not valid for any specific block anymore.
-      NonLocalPointerDeps[P].first = BBSkipFirstBlockPair();
+      NonLocalPointerDeps[P].Pair = BBSkipFirstBlockPair();
+      NonLocalPointerDeps[P].TBAATag = 0;
       
       // Update any entries for RemInst to use the instruction after it.
       for (NonLocalDepInfo::iterator DI = NLPDI.begin(), DE = NLPDI.end();
@@ -1197,7 +1221,7 @@
   for (CachedNonLocalPointerInfo::const_iterator I =NonLocalPointerDeps.begin(),
        E = NonLocalPointerDeps.end(); I != E; ++I) {
     assert(I->first.getPointer() != D && "Inst occurs in NLPD map key");
-    const NonLocalDepInfo &Val = I->second.second;
+    const NonLocalDepInfo &Val = I->second.NonLocalDeps;
     for (NonLocalDepInfo::const_iterator II = Val.begin(), E = Val.end();
          II != E; ++II)
       assert(II->getResult().getInst() != D && "Inst occurs as NLPD value");



From clattner at apple.com  Wed Sep 22 16:50:45 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 22 Sep 2010 14:50:45 -0700
Subject: [llvm-commits] [llvm] r114577 -
	/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
In-Reply-To: <20100922204209.27DF92A6C12C@llvm.org>
References: <20100922204209.27DF92A6C12C@llvm.org>
Message-ID: <EB6E8638-5CE1-4150-9573-CD752CE570FB@apple.com>


On Sep 22, 2010, at 1:42 PM, Eric Christopher wrote:

> Author: echristo
> Date: Wed Sep 22 15:42:08 2010
> New Revision: 114577
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114577&view=rev
> Log:
> Temporarily work around new address lowering while I figure out what
> needs to happen for darwin.

This happens when an instruction is matched with a pattern that uses "addr:$ptr" to represent a memory location.  The assert fires when it doesn't derive from MemSDNode, so it doesn't have memory location.  Is "TLSCALL" doing a memory access? If so, what kind?

-Chris

> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=114577&r1=114576&r2=114577&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Sep 22 15:42:08 2010
> @@ -1149,7 +1149,8 @@
>       // that are not a MemSDNode, and thus don't have proper addrspace info.
>       Parent->getOpcode() != ISD::PREFETCH &&
>       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
> -      Parent->getOpcode() != ISD::INTRINSIC_VOID) { // nontemporal stores.
> +      Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
> +      Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
>     unsigned AddrSpace =
>       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
>     // AddrSpace 256 -> GS, 257 -> FS.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From grosbach at apple.com  Wed Sep 22 16:52:26 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 14:52:26 -0700
Subject: [llvm-commits] [llvm] r114563 - in
	/llvm/trunk/lib/Target/ARM/AsmPrinter: ARMInstPrinter.cpp
	ARMInstPrinter.h
In-Reply-To: <E28949E6-9B65-4EDB-82E0-A599D1C7E317@apple.com>
References: <20100922183715.0379D2A6C12C@llvm.org>
	<E28949E6-9B65-4EDB-82E0-A599D1C7E317@apple.com>
Message-ID: <6B2D4439-71E8-44BA-88A2-10FE7B27877C@apple.com>


On Sep 22, 2010, at 2:37 PM, Chris Lattner wrote:

> 
> On Sep 22, 2010, at 11:37 AM, Jim Grosbach wrote:
> 
>> Author: grosbach
>> Date: Wed Sep 22 13:37:14 2010
>> New Revision: 114563
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=114563&view=rev
>> Log:
>> Add PrintSpecial() handling for  in ARM MC instruction printer.
> 
> Hi Jim,
> 
> What instructions are using ${:comment}?  Are they pseudo instructions that should be handled at mcinst lowering time?  Would a disassembler ever create them?
> 

It's mostly the pseudo instructions that are using it, yes. Most of those are expanded by the back end before MC lowering time, but not all.

For those that aren't (the sjlj.setjmp horrible blob stands out here), yes, they should be handled explicitly at lowering time, and finishing that up is on the agenda right after I get PLT implemented.

The one exception (and the one instance that a disassembler may create) is the trap instructions (one ARM mode, one Thumb mode), which use .long/.short directives with a comment about what they're actually doing.

-Jim



From clattner at apple.com  Wed Sep 22 16:57:11 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 22 Sep 2010 14:57:11 -0700
Subject: [llvm-commits] [llvm] r114563 - in
	/llvm/trunk/lib/Target/ARM/AsmPrinter: ARMInstPrinter.cpp
	ARMInstPrinter.h
In-Reply-To: <6B2D4439-71E8-44BA-88A2-10FE7B27877C@apple.com>
References: <20100922183715.0379D2A6C12C@llvm.org>
	<E28949E6-9B65-4EDB-82E0-A599D1C7E317@apple.com>
	<6B2D4439-71E8-44BA-88A2-10FE7B27877C@apple.com>
Message-ID: <FD5EDCBF-8FEC-425B-B845-F494E476504D@apple.com>


On Sep 22, 2010, at 2:52 PM, Jim Grosbach wrote:

> 
> On Sep 22, 2010, at 2:37 PM, Chris Lattner wrote:
> 
>> 
>> On Sep 22, 2010, at 11:37 AM, Jim Grosbach wrote:
>> 
>>> Author: grosbach
>>> Date: Wed Sep 22 13:37:14 2010
>>> New Revision: 114563
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=114563&view=rev
>>> Log:
>>> Add PrintSpecial() handling for  in ARM MC instruction printer.
>> 
>> Hi Jim,
>> 
>> What instructions are using ${:comment}?  Are they pseudo instructions that should be handled at mcinst lowering time?  Would a disassembler ever create them?
>> 
> 
> It's mostly the pseudo instructions that are using it, yes. Most of those are expanded by the back end before MC lowering time, but not all.
> 
> For those that aren't (the sjlj.setjmp horrible blob stands out here), yes, they should be handled explicitly at lowering time, and finishing that up is on the agenda right after I get PLT implemented.

Ok, when you get to it, please come back to this and remove PrintSpecial.  I agree it's good to get it out of the way in the intermediate term though!

> The one exception (and the one instance that a disassembler may create) is the trap instructions (one ARM mode, one Thumb mode), which use .long/.short directives with a comment about what they're actually doing.

I think that trap should be lowered at mcinstlowering time too.  It can emit a .word and use emitcomment.  The asm string for the instruction should be empty.

Thanks Jim,

-Chris

From grosbach at apple.com  Wed Sep 22 17:04:54 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 15:04:54 -0700
Subject: [llvm-commits] [llvm] r114563 - in
	/llvm/trunk/lib/Target/ARM/AsmPrinter: ARMInstPrinter.cpp
	ARMInstPrinter.h
In-Reply-To: <FD5EDCBF-8FEC-425B-B845-F494E476504D@apple.com>
References: <20100922183715.0379D2A6C12C@llvm.org>
	<E28949E6-9B65-4EDB-82E0-A599D1C7E317@apple.com>
	<6B2D4439-71E8-44BA-88A2-10FE7B27877C@apple.com>
	<FD5EDCBF-8FEC-425B-B845-F494E476504D@apple.com>
Message-ID: <8A7777A5-1323-4F76-B0B9-4E2EB2B4C199@apple.com>


On Sep 22, 2010, at 2:57 PM, Chris Lattner wrote:

> 
> On Sep 22, 2010, at 2:52 PM, Jim Grosbach wrote:
> 
>> 
>> On Sep 22, 2010, at 2:37 PM, Chris Lattner wrote:
>> 
>>> 
>>> On Sep 22, 2010, at 11:37 AM, Jim Grosbach wrote:
>>> 
>>>> Author: grosbach
>>>> Date: Wed Sep 22 13:37:14 2010
>>>> New Revision: 114563
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=114563&view=rev
>>>> Log:
>>>> Add PrintSpecial() handling for  in ARM MC instruction printer.
>>> 
>>> Hi Jim,
>>> 
>>> What instructions are using ${:comment}?  Are they pseudo instructions that should be handled at mcinst lowering time?  Would a disassembler ever create them?
>>> 
>> 
>> It's mostly the pseudo instructions that are using it, yes. Most of those are expanded by the back end before MC lowering time, but not all.
>> 
>> For those that aren't (the sjlj.setjmp horrible blob stands out here), yes, they should be handled explicitly at lowering time, and finishing that up is on the agenda right after I get PLT implemented.
> 
> Ok, when you get to it, please come back to this and remove PrintSpecial.  I agree it's good to get it out of the way in the intermediate term though!
>> The one exception (and the one instance that a disassembler may create) is the trap instructions (one ARM mode, one Thumb mode), which use .long/.short directives with a comment about what they're actually doing.
> 
> I think that trap should be lowered at mcinstlowering time too.  It can emit a .word and use emitcomment.  The asm string for the instruction should be empty.

That all makes good sense. Will do. (8466273)

-Jim

From bob.wilson at apple.com  Wed Sep 22 17:09:21 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 22 Sep 2010 22:09:21 -0000
Subject: [llvm-commits] [llvm] r114589 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20100922220921.C44AD2A6C12C@llvm.org>

Author: bwilson
Date: Wed Sep 22 17:09:21 2010
New Revision: 114589

URL: http://llvm.org/viewvc/llvm-project?rev=114589&view=rev
Log:
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
of those.  Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114589&r1=114588&r2=114589&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 22 17:09:21 2010
@@ -620,8 +620,8 @@
   case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
   case ARMISD::RRX:           return "ARMISD::RRX";
 
-  case ARMISD::VMOVRRD:         return "ARMISD::VMOVRRD";
-  case ARMISD::VMOVDRR:         return "ARMISD::VMOVDRR";
+  case ARMISD::VMOVRRD:       return "ARMISD::VMOVRRD";
+  case ARMISD::VMOVDRR:       return "ARMISD::VMOVDRR";
 
   case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
   case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
@@ -4337,6 +4337,35 @@
   return SDValue();
 }
 
+/// PerformVMOVRRDCombine - Target-specific dag combine xforms for
+/// ARMISD::VMOVRRD.
+static SDValue PerformVMOVRRDCombine(SDNode *N,
+                                     TargetLowering::DAGCombinerInfo &DCI) {
+  // vmovrrd(vmovdrr x, y) -> x,y
+  SDValue InDouble = N->getOperand(0);
+  if (InDouble.getOpcode() == ARMISD::VMOVDRR)
+    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
+  return SDValue();
+}
+
+/// PerformVMOVDRRCombine - Target-specific dag combine xforms for
+/// ARMISD::VMOVDRR.  This is also used for BUILD_VECTORs with 2 operands.
+static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
+  // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  if (Op0.getOpcode() == ISD::BIT_CONVERT)
+    Op0 = Op0.getOperand(0);
+  if (Op1.getOpcode() == ISD::BIT_CONVERT)
+    Op1 = Op1.getOperand(0);
+  if (Op0.getOpcode() == ARMISD::VMOVRRD &&
+      Op0.getNode() == Op1.getNode() &&
+      Op0.getResNo() == 0 && Op1.getResNo() == 1)
+    return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
+                       N->getValueType(0), Op0.getOperand(0));
+  return SDValue();
+}
+
 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
 /// ISD::BUILD_VECTOR.
 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
@@ -4344,32 +4373,9 @@
   // VMOVRRD is introduced when legalizing i64 types.  It forces the i64 value
   // into a pair of GPRs, which is fine when the value is used as a scalar,
   // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
-  if (N->getNumOperands() == 2) {
-    SDValue Op0 = N->getOperand(0);
-    SDValue Op1 = N->getOperand(1);
-    if (Op0.getOpcode() == ISD::BIT_CONVERT)
-      Op0 = Op0.getOperand(0);
-    if (Op1.getOpcode() == ISD::BIT_CONVERT)
-      Op1 = Op1.getOperand(0);
-    if (Op0.getOpcode() == ARMISD::VMOVRRD &&
-        Op0.getNode() == Op1.getNode() &&
-        Op0.getResNo() == 0 && Op1.getResNo() == 1) {
-      return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
-                         N->getValueType(0), Op0.getOperand(0));
-    }
-  }
-
-  return SDValue();
-}
+  if (N->getNumOperands() == 2)
+    return PerformVMOVDRRCombine(N, DAG);
 
-/// PerformVMOVRRDCombine - Target-specific dag combine xforms for
-/// ARMISD::VMOVRRD.
-static SDValue PerformVMOVRRDCombine(SDNode *N,
-                                   TargetLowering::DAGCombinerInfo &DCI) {
-  // fmrrd(fmdrr x, y) -> x,y
-  SDValue InDouble = N->getOperand(0);
-  if (InDouble.getOpcode() == ARMISD::VMOVDRR)
-    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
   return SDValue();
 }
 
@@ -4780,8 +4786,9 @@
   case ISD::SUB:        return PerformSUBCombine(N, DCI);
   case ISD::MUL:        return PerformMULCombine(N, DCI, Subtarget);
   case ISD::OR:         return PerformORCombine(N, DCI, Subtarget);
-  case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
   case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
+  case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
+  case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
   case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
   case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
   case ISD::SHL:



From gohman at apple.com  Wed Sep 22 17:18:07 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 22 Sep 2010 22:18:07 -0000
Subject: [llvm-commits] [llvm] r114591 -
	/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
Message-ID: <20100922221807.634552A6C12C@llvm.org>

Author: djg
Date: Wed Sep 22 17:18:07 2010
New Revision: 114591

URL: http://llvm.org/viewvc/llvm-project?rev=114591&view=rev
Log:
Fix uninitialized TBAAFlag field values.

Modified:
    llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h

Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=114591&r1=114590&r2=114591&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Wed Sep 22 17:18:07 2010
@@ -231,6 +231,8 @@
       /// TBAATag - The TBAA tag associated with dereferences of the
       /// pointer. May be null if there are no tags or conflicting tags.
       MDNode *TBAATag;
+
+      NonLocalPointerInfo() : TBAATag(0) {}
     };
 
     /// CachedNonLocalPointerInfo - This map stores the cached results of doing



From sabre at nondot.org  Wed Sep 22 17:19:53 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 22 Sep 2010 22:19:53 -0000
Subject: [llvm-commits] [llvm] r114592 - in /llvm/trunk:
 include/llvm/MC/MCAsmInfo.h lib/MC/MCAsmInfo.cpp lib/MC/MCAsmStreamer.cpp
Message-ID: <20100922221953.4DE102A6C12C@llvm.org>

Author: lattner
Date: Wed Sep 22 17:19:53 2010
New Revision: 114592

URL: http://llvm.org/viewvc/llvm-project?rev=114592&view=rev
Log:
allow target-specific label suffixes, patch by Yuri Gribov!

Modified:
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/lib/MC/MCAsmInfo.cpp
    llvm/trunk/lib/MC/MCAsmStreamer.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=114592&r1=114591&r2=114592&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Wed Sep 22 17:19:53 2010
@@ -72,6 +72,9 @@
     /// assembler.
     const char *CommentString;               // Defaults to "#"
 
+    /// LabelSuffix - This is appended to emitted labels.
+    const char *LabelSuffix;                 // Defaults to ":"
+
     /// GlobalPrefix - If this is set to a non-empty string, it is prepended
     /// onto all global symbols.  This is often used for "_" or ".".
     const char *GlobalPrefix;                // Defaults to ""
@@ -334,6 +337,9 @@
     const char *getCommentString() const {
       return CommentString;
     }
+    const char *getLabelSuffix() const {
+      return LabelSuffix;
+    }
     const char *getGlobalPrefix() const {
       return GlobalPrefix;
     }

Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=114592&r1=114591&r2=114592&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfo.cpp Wed Sep 22 17:19:53 2010
@@ -28,6 +28,7 @@
   SeparatorChar = ';';
   CommentColumn = 40;
   CommentString = "#";
+  LabelSuffix = ":";
   GlobalPrefix = "";
   PrivateGlobalPrefix = ".";
   LinkerPrivateGlobalPrefix = "";

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=114592&r1=114591&r2=114592&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Sep 22 17:19:53 2010
@@ -236,7 +236,7 @@
   assert(!Symbol->isVariable() && "Cannot emit a variable symbol!");
   assert(CurSection && "Cannot emit before setting section!");
 
-  OS << *Symbol << ":";
+  OS << *Symbol << MAI.getLabelSuffix();
   EmitEOL();
   Symbol->setSection(*CurSection);
 }



From nicholas at mxc.ca  Wed Sep 22 17:22:50 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 22 Sep 2010 22:22:50 -0000
Subject: [llvm-commits] [test-suite] r114593 -
 /test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile
Message-ID: <20100922222250.A10702A6C12C@llvm.org>

Author: nicholas
Date: Wed Sep 22 17:22:50 2010
New Revision: 114593

URL: http://llvm.org/viewvc/llvm-project?rev=114593&view=rev
Log:
Add -fpermissive to help newer GCC's cope with crufty C++ code.

Modified:
    test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile

Modified: test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile?rev=114593&r1=114592&r2=114593&view=diff
==============================================================================
--- test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile (original)
+++ test-suite/trunk/External/SPEC/CINT2000/252.eon/Makefile Wed Sep 22 17:22:50 2010
@@ -57,7 +57,7 @@
             mrXYRectangle.cc mrXZRectangle.cc mrYZRectangle.cc myrand.cc)
 
 # Yes, we know this is an old crufty C++ benchmark.  Don't tell us about it GCC!
-CXXFLAGS += -fno-exceptions -Wno-deprecated -Wno-non-template-friend 
+CXXFLAGS += -fno-exceptions -Wno-deprecated -Wno-non-template-friend -fpermissive
 
 LDFLAGS = -lstdc++ -lm
 LIBS    = -lm



From rafael.espindola at gmail.com  Wed Sep 22 17:27:05 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 22 Sep 2010 22:27:05 -0000
Subject: [llvm-commits] [llvm] r114594 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h include/llvm/MC/MCObjectStreamer.h
 lib/MC/MCAssembler.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCMachOStreamer.cpp
 lib/MC/MCObjectStreamer.cpp lib/MC/WinCOFFStreamer.cpp test/MC/ELF/align.s
Message-ID: <20100922222705.6C9A02A6C12C@llvm.org>

Author: rafael
Date: Wed Sep 22 17:27:05 2010
New Revision: 114594

URL: http://llvm.org/viewvc/llvm-project?rev=114594&view=rev
Log:
Avoid some Mach-O specific alignment being done on ELF.

Added:
    llvm/trunk/test/MC/ELF/align.s
Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/include/llvm/MC/MCObjectStreamer.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCELFStreamer.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp
    llvm/trunk/lib/MC/MCObjectStreamer.cpp
    llvm/trunk/lib/MC/WinCOFFStreamer.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Wed Sep 22 17:27:05 2010
@@ -605,6 +605,7 @@
 
   unsigned RelaxAll : 1;
   unsigned SubsectionsViaSymbols : 1;
+  unsigned PadSectionToAlignment : 1;
 
 private:
   /// Evaluate a fixup to a relocatable expression and the value which should be
@@ -676,7 +677,8 @@
   // option is to make this abstract, and have targets provide concrete
   // implementations as we do with AsmParser.
   MCAssembler(MCContext &_Context, TargetAsmBackend &_Backend,
-              MCCodeEmitter &_Emitter, raw_ostream &OS);
+              MCCodeEmitter &_Emitter, bool _PadSectionToAlignment,
+              raw_ostream &OS);
   ~MCAssembler();
 
   MCContext &getContext() const { return Context; }

Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Wed Sep 22 17:27:05 2010
@@ -35,7 +35,8 @@
 
 protected:
   MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
-                   raw_ostream &_OS, MCCodeEmitter *_Emitter);
+                   raw_ostream &_OS, MCCodeEmitter *_Emitter,
+                   bool _PadSectionToAlignment);
   ~MCObjectStreamer();
 
   MCSectionData *getCurrentSectionData() const {

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Sep 22 17:27:05 2010
@@ -221,9 +221,11 @@
 /* *** */
 
 MCAssembler::MCAssembler(MCContext &_Context, TargetAsmBackend &_Backend,
-                         MCCodeEmitter &_Emitter, raw_ostream &_OS)
+                         MCCodeEmitter &_Emitter, bool _PadSectionToAlignment,
+                         raw_ostream &_OS)
   : Context(_Context), Backend(_Backend), Emitter(_Emitter),
-    OS(_OS), RelaxAll(false), SubsectionsViaSymbols(false)
+    OS(_OS), RelaxAll(false), SubsectionsViaSymbols(false),
+    PadSectionToAlignment(_PadSectionToAlignment)
 {
 }
 
@@ -712,25 +714,25 @@
   // Insert additional align fragments for concrete sections to explicitly pad
   // the previous section to match their alignment requirements. This is for
   // 'gas' compatibility, it shouldn't strictly be necessary.
-  //
-  // FIXME: This may be Mach-O specific.
-  for (unsigned i = 1, e = Layout.getSectionOrder().size(); i < e; ++i) {
-    MCSectionData *SD = Layout.getSectionOrder()[i];
+  if (PadSectionToAlignment) {
+    for (unsigned i = 1, e = Layout.getSectionOrder().size(); i < e; ++i) {
+      MCSectionData *SD = Layout.getSectionOrder()[i];
+
+      // Ignore sections without alignment requirements.
+      unsigned Align = SD->getAlignment();
+      if (Align <= 1)
+        continue;
 
-    // Ignore sections without alignment requirements.
-    unsigned Align = SD->getAlignment();
-    if (Align <= 1)
-      continue;
-
-    // Ignore virtual sections, they don't cause file size modifications.
-    if (getBackend().isVirtualSection(SD->getSection()))
-      continue;
-
-    // Otherwise, create a new align fragment at the end of the previous
-    // section.
-    MCAlignFragment *AF = new MCAlignFragment(Align, 0, 1, Align,
-                                              Layout.getSectionOrder()[i - 1]);
-    AF->setOnlyAlignAddress(true);
+      // Ignore virtual sections, they don't cause file size modifications.
+      if (getBackend().isVirtualSection(SD->getSection()))
+        continue;
+
+      // Otherwise, create a new align fragment at the end of the previous
+      // section.
+      MCAlignFragment *AF = new MCAlignFragment(Align, 0, 1, Align,
+                                                Layout.getSectionOrder()[i - 1]);
+      AF->setOnlyAlignAddress(true);
+    }
   }
 
   // Create dummy fragments and assign section ordinals.

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Wed Sep 22 17:27:05 2010
@@ -40,7 +40,7 @@
 public:
   MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB,
                   raw_ostream &OS, MCCodeEmitter *Emitter)
-    : MCObjectStreamer(Context, TAB, OS, Emitter) {}
+    : MCObjectStreamer(Context, TAB, OS, Emitter, false) {}
 
   ~MCELFStreamer() {}
 

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Wed Sep 22 17:27:05 2010
@@ -41,7 +41,7 @@
 public:
   MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB,
                   raw_ostream &OS, MCCodeEmitter *Emitter)
-    : MCObjectStreamer(Context, TAB, OS, Emitter) {}
+    : MCObjectStreamer(Context, TAB, OS, Emitter, true) {}
 
   /// @name MCStreamer Interface
   /// @{

Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Wed Sep 22 17:27:05 2010
@@ -17,9 +17,12 @@
 using namespace llvm;
 
 MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
-                                   raw_ostream &_OS, MCCodeEmitter *_Emitter)
+                                   raw_ostream &_OS, MCCodeEmitter *_Emitter,
+                                   bool _PadSectionToAlignment)
   : MCStreamer(Context), Assembler(new MCAssembler(Context, TAB,
-                                                   *_Emitter, _OS)),
+                                                   *_Emitter,
+                                                   _PadSectionToAlignment,
+                                                   _OS)),
     CurSectionData(0)
 {
 }

Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=114594&r1=114593&r2=114594&view=diff
==============================================================================
--- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Wed Sep 22 17:27:05 2010
@@ -86,7 +86,7 @@
                                  TargetAsmBackend &TAB,
                                  MCCodeEmitter &CE,
                                  raw_ostream &OS)
-    : MCObjectStreamer(Context, TAB, OS, &CE)
+    : MCObjectStreamer(Context, TAB, OS, &CE, true)
     , CurSymbol(NULL) {
 }
 

Added: llvm/trunk/test/MC/ELF/align.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/align.s?rev=114594&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/align.s (added)
+++ llvm/trunk/test/MC/ELF/align.s Wed Sep 22 17:27:05 2010
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  | FileCheck %s
+
+// Test that the alignment of rodata doesn't force a alignment of the
+// previous section (.bss)
+
+	nop
+	.section	.rodata,"a", at progbits
+	.align	8
+
+// CHECK: # Section 3
+// CHECK-NEXT:  (('sh_name', 13) # '.bss'
+// CHECK-NEXT:   ('sh_type', 8)
+// CHECK-NEXT:   ('sh_flags', 3)
+// CHECK-NEXT:   ('sh_addr', 0)
+// CHECK-NEXT:   ('sh_offset', 68)
+// CHECK-NEXT:   ('sh_size', 0)
+// CHECK-NEXT:   ('sh_link', 0)
+// CHECK-NEXT:   ('sh_info', 0)
+// CHECK-NEXT:   ('sh_addralign', 4)
+// CHECK-NEXT:   ('sh_entsize', 0)
+// CHECK-NEXT:  ),
+// CHECK-NEXT:  # Section 4
+// CHECK-NEXT:  (('sh_name', 18) # '.rodata'
+// CHECK-NEXT:   ('sh_type', 1)
+// CHECK-NEXT:   ('sh_flags', 2)
+// CHECK-NEXT:   ('sh_addr', 0)
+// CHECK-NEXT:   ('sh_offset', 72)
+// CHECK-NEXT:   ('sh_size', 0)
+// CHECK-NEXT:   ('sh_link', 0)
+// CHECK-NEXT:   ('sh_info', 0)
+// CHECK-NEXT:   ('sh_addralign', 8)
+// CHECK-NEXT:   ('sh_entsize', 0)



From bob.wilson at apple.com  Wed Sep 22 17:27:31 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 22 Sep 2010 22:27:31 -0000
Subject: [llvm-commits] [llvm] r114595 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20100922222731.1A09A2A6C12C@llvm.org>

Author: bwilson
Date: Wed Sep 22 17:27:30 2010
New Revision: 114595

URL: http://llvm.org/viewvc/llvm-project?rev=114595&view=rev
Log:
Change VDUPLANE DAG combiner to just return the result instead of calling
CombineTo to avoid putting the result on the worklist.  I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114595&r1=114594&r2=114595&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 22 17:27:30 2010
@@ -4381,8 +4381,7 @@
 
 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
 /// ARMISD::VDUPLANE.
-static SDValue PerformVDUPLANECombine(SDNode *N,
-                                      TargetLowering::DAGCombinerInfo &DCI) {
+static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
   // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
   // redundant.
   SDValue Op = N->getOperand(0);
@@ -4404,8 +4403,7 @@
   if (EltSize > VT.getVectorElementType().getSizeInBits())
     return SDValue();
 
-  SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
-  return DCI.CombineTo(N, Res, false);
+  return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
 }
 
 /// getVShiftImm - Check if this is a valid build_vector for the immediate
@@ -4789,7 +4787,7 @@
   case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
   case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
   case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
-  case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
+  case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
   case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
   case ISD::SHL:
   case ISD::SRA:



From natebegeman at mac.com  Wed Sep 22 17:28:43 2010
From: natebegeman at mac.com (Nate Begeman)
Date: Wed, 22 Sep 2010 22:28:43 -0000
Subject: [llvm-commits] [llvm] r114596 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20100922222843.12CBB2A6C12C@llvm.org>

Author: sampo
Date: Wed Sep 22 17:28:42 2010
New Revision: 114596

URL: http://llvm.org/viewvc/llvm-project?rev=114596&view=rev
Log:
<rdar://problem/8228022> Wvector-conversions warnings in arm_neon.h

Explicitly cast arguments to the type the builtin expects, which is <vN x i8>


Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=114596&r1=114595&r2=114596&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Wed Sep 22 17:28:42 2010
@@ -89,7 +89,7 @@
       return 'i';
     case 'f':
       return 'h';
-    default: throw "unhandled type in widen!";
+    default: throw "unhandled type in narrow!";
   }
   return '\0';
 }
@@ -155,6 +155,10 @@
     case 'n':
       type = Widen(type);
       break;
+    case 'i':
+      type = 'i';
+      scal = true;
+      break;
     case 'l':
       type = 'l';
       scal = true;
@@ -807,14 +811,27 @@
   
   for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) {
     std::string args = std::string(&arg, 1);
+    bool argquad = quad;
+    bool scal = false;
+
+    (void) ModType(proto[i], type, argquad, dummy, dummy, scal, dummy, dummy);
+    bool explicitcast = define && !scal;
+
     if (define)
       args = "(" + args + ")";
+    if (explicitcast) {
+      unsigned builtinelts = quad ? 16 : 8;
+      args = "(__neon_int8x" + utostr(builtinelts) + "_t)(" + args;
+    }
     
     // Handle multiple-vector values specially, emitting each subvector as an
     // argument to the __builtin.
-    if (structTypes && (proto[i] == '2' || proto[i] == '3' || proto[i] == '4')){
+    if (structTypes && (proto[i] >= '2') && (proto[i] <= '4')) {
       for (unsigned vi = 0, ve = proto[i] - '0'; vi != ve; ++vi) {
         s += args + ".val[" + utostr(vi) + "].val";
+        if (explicitcast)
+          s += ")";
+        
         if ((vi + 1) < ve)
           s += ", ";
       }
@@ -829,10 +846,10 @@
     else
       s += args;
     
-    if (structTypes && proto[i] != 's' && proto[i] != 'i' && proto[i] != 'l' &&
-        proto[i] != 'p' && proto[i] != 'c' && proto[i] != 'a') {
+    if (structTypes && !scal)
       s += ".val";
-    }
+    if (explicitcast)
+      s += ")";
     if ((i + 1) < e)
       s += ", ";
   }



From clattner at apple.com  Wed Sep 22 17:35:30 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 22 Sep 2010 15:35:30 -0700
Subject: [llvm-commits] [PATCH] Add ret instruction to PTX backend
In-Reply-To: <AANLkTikOi+Gwcf6ApheMm9dvU-zDAmEVQi9=tUN1On9h@mail.gmail.com>
References: <AANLkTikOi+Gwcf6ApheMm9dvU-zDAmEVQi9=tUN1On9h@mail.gmail.com>
Message-ID: <4FA60469-24D8-4817-9D2C-DBBD315C39B5@apple.com>


On Sep 22, 2010, at 3:37 AM, Che-Liang Chiou wrote:

> Hi,
> 
> This patch adds 'ret' instruction to PTX backend.

looks fine to me, please commit.

-Chris

> 
> SVN revisioin: r114539.
> 
> TEST:
> $ llvm-lit test/CodeGen/PTX
> -- Testing: 2 tests, 8 threads --
> PASS: LLVM :: CodeGen/PTX/exit.ll (1 of 2)
> PASS: LLVM :: CodeGen/PTX/ret.ll (2 of 2)
> Testing Time: 0.02s
>  Expected Passes    : 2
> 
> Regards,
> Che-Liang
> <r114539-add-ret.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dirty at apple.com  Wed Sep 22 17:35:21 2010
From: dirty at apple.com (Cameron Esfahani)
Date: Wed, 22 Sep 2010 22:35:21 -0000
Subject: [llvm-commits] [llvm] r114597 - in /llvm/trunk:
 lib/Target/X86/X86RegisterInfo.cpp test/CodeGen/X86/win_chkstk.ll
Message-ID: <20100922223521.CB5792A6C12C@llvm.org>

Author: dirty
Date: Wed Sep 22 17:35:21 2010
New Revision: 114597

URL: http://llvm.org/viewvc/llvm-project?rev=114597&view=rev
Log:
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/test/CodeGen/X86/win_chkstk.ll

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=114597&r1=114596&r2=114597&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Sep 22 17:35:21 2010
@@ -1086,10 +1086,11 @@
 
     const char *StackProbeSymbol =
       Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
+    unsigned CallOp = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
     if (!isEAXAlive) {
       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
         .addImm(NumBytes);
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
+      BuildMI(MBB, MBBI, DL, TII.get(CallOp))
         .addExternalSymbol(StackProbeSymbol)
         .addReg(StackPtr,    RegState::Define | RegState::Implicit)
         .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
@@ -1102,7 +1103,7 @@
       // allocated bytes for EAX.
       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
         .addImm(NumBytes - 4);
-      BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
+      BuildMI(MBB, MBBI, DL, TII.get(CallOp))
         .addExternalSymbol(StackProbeSymbol)
         .addReg(StackPtr,    RegState::Define | RegState::Implicit)
         .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);

Modified: llvm/trunk/test/CodeGen/X86/win_chkstk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win_chkstk.ll?rev=114597&r1=114596&r2=114597&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/win_chkstk.ll (original)
+++ llvm/trunk/test/CodeGen/X86/win_chkstk.ll Wed Sep 22 17:35:21 2010
@@ -15,7 +15,7 @@
 ; WIN_X32:    calll __chkstk
 ; WIN_X64:    call __chkstk
 ; MINGW_X32:  calll __alloca
-; MINGW_X64:  calll _alloca
+; MINGW_X64:  callq _alloca
 ; LINUX-NOT:  call __chkstk
   %array4096 = alloca [4096 x i8], align 16       ; <[4096 x i8]*> [#uses=0]
   ret i32 0
@@ -34,7 +34,7 @@
 ; WIN_X64:       ret
 
 ; MINGW_X64:     # BB#0:
-; MINGW_X64-NOT: call _alloca
+; MINGW_X64-NOT: callq _alloca
 ; MINGW_X64:     ret
 
 ; LINUX:         # BB#0:



From resistor at mac.com  Wed Sep 22 17:58:22 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 22 Sep 2010 22:58:22 -0000
Subject: [llvm-commits] [llvm] r114599 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/bit-test-shift.ll
Message-ID: <20100922225822.3B7E22A6C12C@llvm.org>

Author: resistor
Date: Wed Sep 22 17:58:22 2010
New Revision: 114599

URL: http://llvm.org/viewvc/llvm-project?rev=114599&view=rev
Log:
A select between a constant and zero, when fed by a bit test, can be efficiently
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.

Added:
    llvm/trunk/test/CodeGen/X86/bit-test-shift.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=114599&r1=114598&r2=114599&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Sep 22 17:58:22 2010
@@ -6808,6 +6808,35 @@
     }
   }
 
+  // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
+  // where y is has a single bit set.
+  // A plaintext description would be, we can turn the SELECT_CC into an AND
+  // when the condition can be materialized as an all-ones register.  Any
+  // single bit-test can be materialized as an all-ones register with
+  // shift-left and shift-right-arith.
+  if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
+      N0->getValueType(0) == VT &&
+      N1C && N1C->isNullValue() && 
+      N2C && N2C->isNullValue()) {
+    SDValue AndLHS = N0->getOperand(0);
+    ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
+    if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
+      // Shift the tested bit over the sign bit.
+      APInt AndMask = ConstAndRHS->getAPIntValue();
+      SDValue ShlAmt =
+        DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy());
+      SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
+      
+      // Now arithmetic right shift it all the way over, so the result is either
+      // all-ones, or zero.
+      SDValue ShrAmt =
+        DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy());
+      SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
+      
+      return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
+    }
+  }
+
   // fold select C, 16, 0 -> shl C, 4
   if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
       TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {

Added: llvm/trunk/test/CodeGen/X86/bit-test-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bit-test-shift.ll?rev=114599&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bit-test-shift.ll (added)
+++ llvm/trunk/test/CodeGen/X86/bit-test-shift.ll Wed Sep 22 17:58:22 2010
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+; <rdar://problem/8285015>
+
+define i32 @x(i32 %t) nounwind readnone ssp {
+entry:
+; CHECK: shll	$23, %eax
+; CHECK: sarl	$31, %eax
+; CHECK: andl	$-26, %eax
+  %and = and i32 %t, 256
+  %tobool = icmp eq i32 %and, 0
+  %retval.0 = select i1 %tobool, i32 0, i32 -26
+  ret i32 %retval.0
+}



From grosbach at apple.com  Wed Sep 22 18:01:29 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 23:01:29 -0000
Subject: [llvm-commits] [llvm] r114601 -
	/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
Message-ID: <20100922230129.27B752A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 18:01:28 2010
New Revision: 114601

URL: http://llvm.org/viewvc/llvm-project?rev=114601&view=rev
Log:
Enable a few additional asserts in MC instruction lowering.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=114601&r1=114600&r2=114601&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Sep 22 18:01:28 2010
@@ -75,11 +75,10 @@
   raw_svector_ostream(Name) << Printer.MAI->getPrivateGlobalPrefix() << "JTI"
     << Printer.getFunctionNumber() << '_' << MO.getIndex();
 
-#if 0
   switch (MO.getTargetFlags()) {
-    default: llvm_unreachable("Unknown target flag on GV operand");
+  default: assert(0 && "Unknown target flag on jump table operand");
+  case 0: break;
   }
-#endif
 
   // Create a symbol for the name.
   return Ctx.GetOrCreateSymbol(Name.str());
@@ -91,11 +90,10 @@
   raw_svector_ostream(Name) << Printer.MAI->getPrivateGlobalPrefix() << "CPI"
     << Printer.getFunctionNumber() << '_' << MO.getIndex();
 
-#if 0
   switch (MO.getTargetFlags()) {
-  default: llvm_unreachable("Unknown target flag on GV operand");
+  default: assert(0 && "Unknown target flag on CPI operand");
+  case 0: break;
   }
-#endif
 
   // Create a symbol for the name.
   return Ctx.GetOrCreateSymbol(Name.str());
@@ -107,11 +105,10 @@
   // lot of extra uniquing.
   const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx);
 
-#if 0
   switch (MO.getTargetFlags()) {
-  default: llvm_unreachable("Unknown target flag on GV operand");
+  default: assert(0 && "Unknown target flag on Symbol operand");
+  case 0: break;
   }
-#endif
 
   if (!MO.isJTI() && MO.getOffset())
     Expr = MCBinaryExpr::CreateAdd(Expr,



From daniel at zuster.org  Wed Sep 22 18:03:28 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 23:03:28 -0000
Subject: [llvm-commits] [test-suite] r114605 -
 /test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output
Message-ID: <20100922230329.03B162A6C12C@llvm.org>

Author: ddunbar
Date: Wed Sep 22 18:03:28 2010
New Revision: 114605

URL: http://llvm.org/viewvc/llvm-project?rev=114605&view=rev
Log:
Add reference output.

Added:
    test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output

Added: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output?rev=114605&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output (added)
+++ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output Wed Sep 22 18:03:28 2010
@@ -0,0 +1,24 @@
+test_basic
+a0_0: (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)
+a0_1: (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
+a0_2: (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
+a1_0: (1, 1, 1, 1, 1, 1, 1, 1)
+a1_1: (0, 1, 2, 3, 4, 5, 6, 7)
+a1_2: (1, 2, 3, 4, 5, 6, 7, 8)
+a2_0: (1, 1, 1, 1)
+a2_1: (0, 1, 2, 3)
+a2_2: (1, 2, 3, 4)
+test_zip
+a0_2.val[0]: (0, 15, 1, 14, 2, 13, 3, 12, 4, 11, 5, 10, 6, 9, 7, 8)
+a0_2.val[1]: (0, 15, 1, 14, 2, 13, 3, 12, 4, 11, 5, 10, 6, 9, 7, 8)
+a0_3.val[0]: (0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)
+a0_3.val[1]: (15, 14, 13, 12, 11, 10, 9, 8, 15, 14, 13, 12, 11, 10, 9, 8)
+a1_2.val[0]: (0, 7, 1, 6, 2, 5, 3, 4)
+a1_2.val[1]: (0, 7, 1, 6, 2, 5, 3, 4)
+a1_3.val[0]: (0, 1, 2, 3, 0, 1, 2, 3)
+a1_3.val[1]: (7, 6, 5, 4, 7, 6, 5, 4)
+a2_2.val[0]: (0, 3, 1, 2)
+a2_2.val[1]: (0, 3, 1, 2)
+a2_3.val[0]: (0, 1, 0, 1)
+a2_3.val[1]: (3, 2, 3, 2)
+exit 0



From daniel at zuster.org  Wed Sep 22 18:03:32 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Sep 2010 23:03:32 -0000
Subject: [llvm-commits] [test-suite] r114606 -
 /test-suite/trunk/SingleSource/UnitTests/Vector/Makefile
Message-ID: <20100922230332.3EAD82A6C12D@llvm.org>

Author: ddunbar
Date: Wed Sep 22 18:03:32 2010
New Revision: 114606

URL: http://llvm.org/viewvc/llvm-project?rev=114606&view=rev
Log:
Enable NEON vector tests on ARMv7 or "Thumbv7".

Modified:
    test-suite/trunk/SingleSource/UnitTests/Vector/Makefile

Modified: test-suite/trunk/SingleSource/UnitTests/Vector/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/Makefile?rev=114606&r1=114605&r2=114606&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Vector/Makefile (original)
+++ test-suite/trunk/SingleSource/UnitTests/Vector/Makefile Wed Sep 22 18:03:32 2010
@@ -16,6 +16,11 @@
 DIRS += SSE
 endif
 
+# Assume ARMv7 implies NEON.
+ifneq ($(CC_UNDER_TEST_TARGET_IS_ARMV7)$(CC_UNDER_TEST_TARGET_IS_THUMBV7),)
+DIRS += NEON
+endif
+
 include $(LEVEL)/SingleSource/Makefile.singlesrc
 
 



From gohman at apple.com  Wed Sep 22 18:20:04 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 22 Sep 2010 23:20:04 -0000
Subject: [llvm-commits] [llvm] r114612 -
	/llvm/trunk/include/llvm/ADT/SetVector.h
Message-ID: <20100922232004.984712A6C12C@llvm.org>

Author: djg
Date: Wed Sep 22 18:20:04 2010
New Revision: 114612

URL: http://llvm.org/viewvc/llvm-project?rev=114612&view=rev
Log:
Make SetVector's remove indicate whether it actually removed something.

Modified:
    llvm/trunk/include/llvm/ADT/SetVector.h

Modified: llvm/trunk/include/llvm/ADT/SetVector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SetVector.h?rev=114612&r1=114611&r2=114612&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SetVector.h (original)
+++ llvm/trunk/include/llvm/ADT/SetVector.h Wed Sep 22 18:20:04 2010
@@ -114,13 +114,15 @@
   }
 
   /// @brief Remove an item from the set vector.
-  void remove(const value_type& X) {
+  bool remove(const value_type& X) {
     if (set_.erase(X)) {
       typename vector_type::iterator I =
         std::find(vector_.begin(), vector_.end(), X);
       assert(I != vector_.end() && "Corrupted SetVector instances!");
       vector_.erase(I);
+      return true;
     }
+    return false;
   }
 
 



From grosbach at apple.com  Wed Sep 22 18:27:36 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 23:27:36 -0000
Subject: [llvm-commits] [llvm] r114613 - in /llvm/trunk:
 include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp lib/Target/ARM/ARMBaseInfo.h
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMMCInstLower.cpp
 lib/Target/ARM/ARMMCInstLower.h
Message-ID: <20100922232737.0FBCB2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep 22 18:27:36 2010
New Revision: 114613

URL: http://llvm.org/viewvc/llvm-project?rev=114613&view=rev
Log:
Add support for ELF PLT references for ARM MC asm printing. Adding a
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).


Modified:
    llvm/trunk/include/llvm/MC/MCExpr.h
    llvm/trunk/lib/MC/MCExpr.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
    llvm/trunk/lib/Target/ARM/ARMMCInstLower.h

Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=114613&r1=114612&r2=114613&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Wed Sep 22 18:27:36 2010
@@ -137,6 +137,7 @@
     VK_TPOFF,
     VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the asm file)
     VK_ARM_LO16, // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the asm file)
+    VK_ARM_PLT,  // ARM-style PLT symbol references. i.e., (PLT) instead of @PLT
     VK_TLVP // Mach-O thread local variable relocation
   };
 

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=114613&r1=114612&r2=114613&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Wed Sep 22 18:27:36 2010
@@ -50,9 +50,11 @@
     else
       OS << Sym;
 
-    if (SRE.getKind() != MCSymbolRefExpr::VK_None &&
-        SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 &&
-        SRE.getKind() != MCSymbolRefExpr::VK_ARM_LO16)
+    if (SRE.getKind() == MCSymbolRefExpr::VK_ARM_PLT)
+      OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind());
+    else if (SRE.getKind() != MCSymbolRefExpr::VK_None &&
+             SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 &&
+             SRE.getKind() != MCSymbolRefExpr::VK_ARM_LO16)
       OS << '@' << MCSymbolRefExpr::getVariantKindName(SRE.getKind());
 
     return;
@@ -177,6 +179,7 @@
   case VK_TPOFF: return "TPOFF";
   case VK_ARM_HI16: return ":upper16:";
   case VK_ARM_LO16: return ":lower16:";
+  case VK_ARM_PLT: return "(PLT)";
   case VK_TLVP: return "TLVP";
   }
 }

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=114613&r1=114612&r2=114613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Wed Sep 22 18:27:36 2010
@@ -181,7 +181,11 @@
 
     /// MO_HI16 - On a symbol operand, this represents a relocation containing
     /// higher 16 bit of the address. Used only via movt instruction.
-    MO_HI16
+    MO_HI16,
+
+    /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
+    /// call operand.
+    MO_PLT
   };
 } // end namespace ARMII
 

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114613&r1=114612&r2=114613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 22 18:27:36 2010
@@ -1195,8 +1195,14 @@
       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
       Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
                            getPointerTy(), Callee, PICLabel);
-    } else
-      Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
+    } else {
+      // On ELF targets for PIC code, direct calls should go through the PLT
+      unsigned OpFlags = 0;
+      if (Subtarget->isTargetELF() &&
+                  getTargetMachine().getRelocationModel() == Reloc::PIC_)
+        OpFlags = ARMII::MO_PLT;
+      Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
+    }
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
     isDirect = true;
     bool isStub = Subtarget->isTargetDarwin() &&
@@ -1217,8 +1223,14 @@
       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
       Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
                            getPointerTy(), Callee, PICLabel);
-    } else
-      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
+    } else {
+      unsigned OpFlags = 0;
+      // On ELF targets for PIC code, direct calls should go through the PLT
+      if (Subtarget->isTargetELF() &&
+                  getTargetMachine().getRelocationModel() == Reloc::PIC_)
+        OpFlags = ARMII::MO_PLT;
+      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
+    }
   }
 
   // FIXME: handle tail calls differently.

Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=114613&r1=114612&r2=114613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed Sep 22 18:27:36 2010
@@ -33,7 +33,6 @@
 const MCSymbolRefExpr *ARMMCInstLower::
 GetSymbolRef(const MachineOperand &MO) const {
   assert(MO.isGlobal() && "Isn't a global address reference?");
-  // FIXME: HANDLE PLT references how??
 
   const MCSymbolRefExpr *SymRef;
   const MCSymbol *Symbol = GetGlobalAddressSymbol(MO.getGlobal());
@@ -49,22 +48,36 @@
   case ARMII::MO_HI16:
     SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_HI16, Ctx);
     break;
+  case ARMII::MO_PLT:
+    SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx);
+    break;
   }
 
   return SymRef;
 }
 
-MCSymbol *ARMMCInstLower::
+const MCSymbolRefExpr *ARMMCInstLower::
 GetExternalSymbolSymbol(const MachineOperand &MO) const {
-  // FIXME: HANDLE PLT references how??
-  // FIXME: This probably needs to be merged with the above SymbolRef stuff
-  // to handle :lower16: and :upper16: (?)
+  const MCSymbolRefExpr *SymRef;
+  const MCSymbol *Symbol = Printer.GetExternalSymbolSymbol(MO.getSymbolName());
+
   switch (MO.getTargetFlags()) {
-  default: assert(0 && "Unknown target flag on GV operand");
-  case 0: break;
+  default: assert(0 && "Unknown target flag on external symbol operand");
+  case 0:
+    SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
+    break;
+  case ARMII::MO_LO16:
+    SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_LO16, Ctx);
+    break;
+  case ARMII::MO_HI16:
+    SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_HI16, Ctx);
+    break;
+  case ARMII::MO_PLT:
+    SymRef = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx);
+    break;
   }
 
-  return Printer.GetExternalSymbolSymbol(MO.getSymbolName());
+  return SymRef;
 }
 
 
@@ -157,7 +170,7 @@
       MCOp = LowerSymbolRefOperand(MO, GetSymbolRef(MO));
       break;
     case MachineOperand::MO_ExternalSymbol:
-      MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO));
+      MCOp = LowerSymbolRefOperand(MO, GetExternalSymbolSymbol(MO));
       break;
     case MachineOperand::MO_JumpTableIndex:
       MCOp = LowerSymbolOperand(MO, GetJumpTableSymbol(MO));

Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.h?rev=114613&r1=114612&r2=114613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.h Wed Sep 22 18:27:36 2010
@@ -43,7 +43,8 @@
   //MCSymbol *GetPICBaseSymbol() const;
   MCSymbol *GetGlobalAddressSymbol(const GlobalValue *GV) const;
   const MCSymbolRefExpr *GetSymbolRef(const MachineOperand &MO) const;
-  MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
+  const MCSymbolRefExpr *GetExternalSymbolSymbol(const MachineOperand &MO)
+    const;
   MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const;
   MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const;
   MCOperand LowerSymbolRefOperand(const MachineOperand &MO,



From gohman at apple.com  Wed Sep 22 19:33:13 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 23 Sep 2010 00:33:13 -0000
Subject: [llvm-commits] [llvm] r114614 - in /llvm/trunk:
 test/Other/extract.ll tools/llvm-extract/llvm-extract.cpp
Message-ID: <20100923003313.72ECF2A6C12C@llvm.org>

Author: djg
Date: Wed Sep 22 19:33:13 2010
New Revision: 114614

URL: http://llvm.org/viewvc/llvm-project?rev=114614&view=rev
Log:
Fix llvm-extract -delete's lazy loading to materialize the functions that
will not be deleted, rather than the ones that will.

Added:
    llvm/trunk/test/Other/extract.ll
Modified:
    llvm/trunk/tools/llvm-extract/llvm-extract.cpp

Added: llvm/trunk/test/Other/extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Other/extract.ll?rev=114614&view=auto
==============================================================================
--- llvm/trunk/test/Other/extract.ll (added)
+++ llvm/trunk/test/Other/extract.ll Wed Sep 22 19:33:13 2010
@@ -0,0 +1,22 @@
+; RUN: llvm-extract -func foo -S < %s | FileCheck %s
+; RUN: llvm-extract -delete -func foo -S < %s | FileCheck --check-prefix=DELETE %s
+; RUN: llvm-as < %s > %t
+; RUN: llvm-extract -func foo -S %t | FileCheck %s
+; RUN: llvm-extract -delete -func foo -S %t | FileCheck --check-prefix=DELETE %s
+
+; llvm-extract uses lazy bitcode loading, so make sure it correctly reads
+; from bitcode files in addition to assembly files.
+
+; CHECK: define void @foo() {
+; CHECK:   ret void
+; CHECK: }
+; DELETE: define void @bar() {
+; DELETE:   ret void
+; DELETE: }
+
+define void @foo() {
+  ret void
+}
+define void @bar() {
+  ret void
+}

Modified: llvm/trunk/tools/llvm-extract/llvm-extract.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-extract/llvm-extract.cpp?rev=114614&r1=114613&r2=114614&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-extract/llvm-extract.cpp (original)
+++ llvm/trunk/tools/llvm-extract/llvm-extract.cpp Wed Sep 22 19:33:13 2010
@@ -26,6 +26,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/SystemUtils.h"
 #include "llvm/System/Signals.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include <memory>
 using namespace llvm;
 
@@ -102,13 +103,39 @@
   }
 
   // Materialize requisite global values.
-  for (size_t i = 0, e = GVs.size(); i != e; ++i) {
-    GlobalValue *GV = GVs[i];
-    if (GV->isMaterializable()) {
-      std::string ErrInfo;
-      if (GV->Materialize(&ErrInfo)) {
-        errs() << argv[0] << ": error reading input: " << ErrInfo << "\n";
-        return 1;
+  if (!DeleteFn)
+    for (size_t i = 0, e = GVs.size(); i != e; ++i) {
+      GlobalValue *GV = GVs[i];
+      if (GV->isMaterializable()) {
+        std::string ErrInfo;
+        if (GV->Materialize(&ErrInfo)) {
+          errs() << argv[0] << ": error reading input: " << ErrInfo << "\n";
+          return 1;
+        }
+      }
+    }
+  else {
+    // Deleting. Materialize every GV that's *not* in GVs.
+    SmallPtrSet<GlobalValue *, 8> GVSet(GVs.begin(), GVs.end());
+    for (Module::global_iterator I = M->global_begin(), E = M->global_end();
+         I != E; ++I) {
+      GlobalVariable *G = I;
+      if (!GVSet.count(G) && G->isMaterializable()) {
+        std::string ErrInfo;
+        if (G->Materialize(&ErrInfo)) {
+          errs() << argv[0] << ": error reading input: " << ErrInfo << "\n";
+          return 1;
+        }
+      }
+    }
+    for (Module::iterator I = M->begin(), E = M->end(); I != E; ++I) {
+      Function *F = I;
+      if (!GVSet.count(F) && F->isMaterializable()) {
+        std::string ErrInfo;
+        if (F->Materialize(&ErrInfo)) {
+          errs() << argv[0] << ": error reading input: " << ErrInfo << "\n";
+          return 1;
+        }
       }
     }
   }



From wdietz2 at illinois.edu  Wed Sep 22 20:35:29 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 23 Sep 2010 01:35:29 -0000
Subject: [llvm-commits] [poolalloc] r114617 - in /poolalloc/trunk:
 include/dsa/DSGraph.h lib/DSA/DSGraph.cpp
Message-ID: <20100923013529.DDE702A6C12C@llvm.org>

Author: wdietz2
Date: Wed Sep 22 20:35:29 2010
New Revision: 114617

URL: http://llvm.org/viewvc/llvm-project?rev=114617&view=rev
Log:
Better handling of incompleteness due to potential influence of external code.
Fixes extern.ll, extern2.ll, and extern3.ll (PR8206).

Modified:
    poolalloc/trunk/include/dsa/DSGraph.h
    poolalloc/trunk/lib/DSA/DSGraph.cpp

Modified: poolalloc/trunk/include/dsa/DSGraph.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=114617&r1=114616&r2=114617&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSGraph.h (original)
+++ poolalloc/trunk/include/dsa/DSGraph.h Wed Sep 22 20:35:29 2010
@@ -499,6 +499,12 @@
   };
   void markIncompleteNodes(unsigned Flags);
 
+  // markExternalNodes - Traverse the graph, identifying nodes that may be
+  // exposed to external code.  The sources of this happening are:
+  // --Arguments and return values for external functions
+  // --Arguments and return values for externally visible functions
+  void markExternalNodes(void);
+
   // removeDeadNodes - Use a reachability analysis to eliminate subgraphs that
   // are unreachable.  This often occurs because the data structure doesn't
   // "escape" into it's caller, and thus should be eliminated from the caller's

Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=114617&r1=114616&r2=114617&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSGraph.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSGraph.cpp Wed Sep 22 20:35:29 2010
@@ -648,15 +648,17 @@
            E = AuxFunctionCalls.end(); I != E; ++I)
       markIncomplete(*I);
 
-#if 0
   // Mark stuff passed into external functions as being incomplete.
   // External functions may not appear in Aux during td, so process
   // them specially
+#if 0
   for (std::list<DSCallSite>::iterator I = FunctionCalls.begin(),
          E = FunctionCalls.end(); I != E; ++I)
     if(I->isDirectCall() && I->getCalleeFunc()->isDeclaration())
       markIncomplete(*I);
 #endif
+  // Handle all sources of external
+  markExternalNodes();
 
   // Mark all global nodes as incomplete.
   for (DSScalarMap::global_iterator I = ScalarMap.global_begin(),
@@ -675,6 +677,85 @@
   }
 }
 
+static void markExternalNode(DSNode *N) {
+  // FIXME: For now, we say that external is the same as incomplete as little to nothing
+  // checks or uses the External flag, and if we're to do the External flag it's as part of something
+  // else and needs more thought.  For now we simply are ensuring things that should be incomplete due to
+  // external influence are, in fact, marked incomplete.
+  markIncompleteNode(N);
+}
+
+static void markExternal(DSCallSite &Call) {
+  markExternalNode(Call.getRetVal().getNode());
+
+  markExternalNode(Call.getVAVal().getNode());
+
+  // All objects pointed to by function arguments are incomplete!
+  for (unsigned i = 0, e = Call.getNumPtrArgs(); i != e; ++i)
+    markExternalNode(Call.getPtrArg(i).getNode());
+}
+
+// markExternalNodes - Traverse the graph, identifying nodes that may be
+// exposed to external code.  The sources of this happening are:
+// --Arguments and return values for external functions
+// --Arguments and return values for externally visible functions
+//
+// FIXME: Unlike 'Incomplete' flag, the 'External' flag is never reset
+// and if done right should propagate throughout the various passes.
+// That is to say we can probably get away by not re-marking everything,
+// but instead placing just the right flag updates in just the right places.
+// However this is simpler and more likely to be correct--that kind of 
+// optimization can wait until everything works correctly.
+void DSGraph::markExternalNodes() {
+  // Process all CallSites that call functions influenced by external code
+  for (std::list<DSCallSite>::iterator I = FunctionCalls.begin(),
+         E = FunctionCalls.end(); I != E; ++I) {
+    bool shouldBeMarkedExternal = false;
+
+    // Figure out what this callsite calls...
+    std::vector<const Function *> Functions;
+    if (I->isDirectCall())
+      Functions.push_back(I->getCalleeFunc());
+    else
+      I->getCalleeNode()->addFullFunctionList(Functions);
+
+    // ...And examine each callee:
+    for (std::vector<const Function *>::iterator II = Functions.begin(),
+                                            EE = Functions.end();
+          (II != EE) && !shouldBeMarkedExternal; ++II) {
+
+      // Calls to external functions should be marked external
+      shouldBeMarkedExternal |= (*II)->isDeclaration();
+      // Calls to code that is externally visible should be marked
+      // external.  This might be overkill due to unification and the
+      // various passes propagating this information,
+      // but for now we /ensure/ the flags are set correctly.
+      shouldBeMarkedExternal |= !(*II)->hasInternalLinkage();
+    }
+
+    if (shouldBeMarkedExternal) {
+      markExternal(*I);
+    }
+  }
+
+  // Additionally, look at each *function* that is external-related
+  // and set the External flag for its arguments and return value.
+  for (ReturnNodesTy::iterator FI = ReturnNodes.begin(), E =ReturnNodes.end();
+      FI != E; ++FI) {
+    const Function &F = *FI->first;
+    // If this function is potentially influenced by external code...
+    if (!F.hasInternalLinkage() || F.isDeclaration()) {
+      // Mark its arguments, return value (and vanode) as external.
+      for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
+          I != E; ++I)
+        if (isa<PointerType>(I->getType()))
+          markExternalNode(getNodeForValue(I).getNode());
+      markExternalNode(FI->second.getNode());
+      markExternalNode(getVANodeFor(F).getNode());
+    }
+  }
+}
+
 static inline void killIfUselessEdge(DSNodeHandle &Edge) {
   if (DSNode * N = Edge.getNode()) // Is there an edge?
     if (N->getNumReferrers() == 1)  // Does it point to a lonely node?



From grosbach at apple.com  Wed Sep 22 20:48:11 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Sep 2010 18:48:11 -0700
Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
Message-ID: <1B431CFE-CD10-4DC9-8387-560EFADCAC67@apple.com>


On Sep 19, 2010, at 10:36 PM, Jason Kim wrote:

> Double oops.
> I somehow missed a compile breaking typo.
> Apologies for the noise.
> Tested against clean build dir.
> <arm-mc-elf-s01.patch4>


> Index: lib/Target/X86/X86TargetMachine.cpp
> ===================================================================
> --- lib/Target/X86/X86TargetMachine.cpp	(revision 114214)
> +++ lib/Target/X86/X86TargetMachine.cpp	(working copy)
> @@ -39,11 +39,11 @@
>    }
>  }
> 
> -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
> -                                    MCContext &Ctx, TargetAsmBackend &TAB,
> -                                    raw_ostream &_OS,
> -                                    MCCodeEmitter *_Emitter,
> -                                    bool RelaxAll) {
> +static MCStreamer *createX86MCStreamer(const Target &T, const std::string &TT,
> +                                       MCContext &Ctx, TargetAsmBackend &TAB,
> +                                       raw_ostream &_OS,
> +                                       MCCodeEmitter *_Emitter,
> +                                       bool RelaxAll) {

Why is this rename necessary? It's a static function, so there's no namespace collision with anything in another target.

>    Triple TheTriple(TT);
>    switch (TheTriple.getOS()) {
>    case Triple::Darwin:
> @@ -58,7 +58,7 @@
>    }
>  }
> 
> -extern "C" void LLVMInitializeX86Target() {
> +extern "C" void LLVMInitializeX86Target() {
>    // Register the target.
>    RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
>    RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
> @@ -81,9 +81,9 @@
> 
>    // Register the object streamer.
>    TargetRegistry::RegisterObjectStreamer(TheX86_32Target,
> -                                         createMCStreamer);
> +                                         createX86MCStreamer);
>    TargetRegistry::RegisterObjectStreamer(TheX86_64Target,
> -                                         createMCStreamer);
> +                                         createX86MCStreamer);
>  }
> 
> 
> @@ -100,9 +100,9 @@
> 
>  /// X86TargetMachine ctor - Create an X86 target.
>  ///
> -X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
> +X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
>                                     const std::string &FS, bool is64Bit)
> -  : LLVMTargetMachine(T, TT),
> +  : LLVMTargetMachine(T, TT),
>      Subtarget(TT, FS, is64Bit),
>      DataLayout(Subtarget.getDataLayout()),
>      FrameInfo(TargetFrameInfo::StackGrowsDown,
> @@ -217,13 +217,13 @@
>                                        JITCodeEmitter &JCE) {
>    // FIXME: Move this to TargetJITInfo!
>    // On Darwin, do not override 64-bit setting made in X86TargetMachine().
> -  if (DefRelocModel == Reloc::Default &&
> +  if (DefRelocModel == Reloc::Default &&
>        (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
>      setRelocationModel(Reloc::Static);
>      Subtarget.setPICStyle(PICStyles::None);
>    }
> -
> 
> +

Looks like a few whitespace only changes slipped into the patch. It's best if cosmetic changes and functional changes are done in separate patches to make it easier to track which revisions are making "real" changes to the code.

>    PM.add(createX86JITCodeEmitterPass(*this, JCE));
> 
>    return false;
> Index: lib/Target/ARM/ARMTargetMachine.cpp
> ===================================================================
> --- lib/Target/ARM/ARMTargetMachine.cpp	(revision 114214)
> +++ lib/Target/ARM/ARMTargetMachine.cpp	(working copy)
> @@ -31,6 +31,27 @@
>    }
>  }
> 
> +// TODO(jasonwkim): [2010/09/19 10:31:16 PDT (Sunday)]
> +// This is duplicated code. Refactor this.
> +static MCStreamer *createARMMCStreamer(const Target &T, const std::string &TT,

It's static, so it doesn't technically need the "ARM" bit in the name. Not really a big deal, but I'd prefer changing things here to be consistent with X86 for now, then adjusting both later if it's more appropriate to include the prefix. That is, add new bits in a manner consistent with what's already there, then do the cleanup, or vice versa, but not both in the same patch. Same basic idea as above in that it keeps the patches small and single purpose, which makes them easier to test and review.


> +                                       MCContext &Ctx, TargetAsmBackend &TAB,
> +                                       raw_ostream &_OS,
> +                                       MCCodeEmitter *_Emitter,
> +                                       bool RelaxAll) {
> +  Triple TheTriple(TT);
> +  switch (TheTriple.getOS()) {
> +  case Triple::Darwin:
> +    return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
> +  case Triple::MinGW32:
> +  case Triple::MinGW64:
> +  case Triple::Cygwin:
> +  case Triple::Win32:
> +    return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);

ARM doesn't currently have any intention of supporting any of the Windows targets, so these should be omitted here, or possibly trigger an assert.

> +  default:
> +    return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
> +  }
> +}
> +
>  extern "C" void LLVMInitializeARMTarget() {
>    // Register the target.
>    RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
> @@ -39,6 +60,19 @@
>    // Register the target asm info.
>    RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
>    RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
> +
> +  // Register the MC Code Emitter
> +  TargetRegistry::RegisterCodeEmitter(TheARMTarget,
> +                                      createARMMCCodeEmitter);
> +  TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
> +                                      createARMMCCodeEmitter);
> +
> +  // Register the object streamer.
> +  TargetRegistry::RegisterObjectStreamer(TheARMTarget,
> +                                         createARMMCStreamer);
> +  TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
> +                                         createARMMCStreamer);
> +
>  }
> 
>  /// TargetMachine ctor - Create an ARM architecture model.
> @@ -46,23 +80,28 @@
>  ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
>                                             const std::string &TT,
>                                             const std::string &FS,
> +                                           StringRef TargetDescription,
>                                             bool isThumb)
>    : LLVMTargetMachine(T, TT),
>      Subtarget(TT, FS, isThumb),
>      FrameInfo(Subtarget),
>      JITInfo(),
> -    InstrItins(Subtarget.getInstrItineraryData()) {
> +    InstrItins(Subtarget.getInstrItineraryData()),
> +    DataLayout(TargetDescription),

 The TargetData is accessible from the TargetMachine instance via the getTargetData() accessor function. Is that not sufficient for what you're looking to accomplish?

> +    ELFWriterInfo(*this)

This creates an ELFWriter() even when the target doesn't need or want one. That doesn't seem right. I see X86 does the same thing, though. Doesn't seem right there, either, but perhaps I'm missing something and someone familiar with that area can comment.

> <snip>

> Index: lib/Target/ARM/ARMELFWriterInfo.h
> ===================================================================
> --- lib/Target/ARM/ARMELFWriterInfo.h	(revision 0)
> +++ lib/Target/ARM/ARMELFWriterInfo.h	(revision 0)
> @@ -0,0 +1,66 @@
> +//===-- ARMELFWriterInfo.h - ELF Writer Info for ARM ------------*- C++ -*-===//
> +//
> +//                     The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file implements ELF writer information for the ARM backend.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef ARM_ELF_WRITER_INFO_H
> +#define ARM_ELF_WRITER_INFO_H
> +
> +#include "llvm/Target/TargetELFWriterInfo.h"
> +
> +namespace llvm {
> +
> +  class ARMELFWriterInfo : public TargetELFWriterInfo {
> +
> +    // ELF Relocation types for ARM
> +    // FIXME: TODO(jasonwkim): [2010/09/17 14:52:25 PDT (Friday)]

FIXME's don't need name/date info. "svn annotate" does the trick for that information.

> +    // Come up with a better way to orgnize the 100+ ARM reloc types.
> +
> +    enum ARMRelocationType {
> +    };
> +
> +  public:
> +    ARMELFWriterInfo(TargetMachine &TM);
> +    virtual ~ARMELFWriterInfo();
> +
> +    /// getRelocationType - Returns the target specific ELF Relocation type.
> +    /// 'MachineRelTy' contains the object code independent relocation type
> +    virtual unsigned getRelocationType(unsigned MachineRelTy) const;
> +
> +    /// hasRelocationAddend - True if the target uses an addend in the
> +    /// ELF relocation entry.
> +    virtual bool hasRelocationAddend() const { return is64Bit ? true : false; }

There's no 64-bit here. Should this always return 'false' for ARM? Probably shouldn't reference 64Bit in any case, I'd think.

> +
> +    /// getDefaultAddendForRelTy - Gets the default addend value for a
> +    /// relocation entry based on the target ELF relocation type.
> +    virtual long int getDefaultAddendForRelTy(unsigned RelTy,
> +                                              long int Modifier = 0) const;

> +
> +    /// isPCRelativeRel - True if the relocation type is pc relative
> +    virtual bool isPCRelativeRel(unsigned RelTy) const;
> +
> +    /// getJumpTableRelocationTy - Returns the machine relocation type used
> +    /// to reference a jumptable.
> +    virtual unsigned getAbsoluteLabelMachineRelTy() const;

Advance warning: ARM does jump tables with custom handling. This may be an "interesting" bit.


> +
> +    /// computeRelocation - Some relocatable fields could be relocated
> +    /// directly, avoiding the relocation symbol emission, compute the
> +    /// final relocation value for this symbol.
> +    virtual long int computeRelocation(unsigned SymOffset, unsigned RelOffset,
> +                                       unsigned RelTy) const;
> +  };
> +
> +} // end llvm namespace
> +
> +#endif // ARM_ELF_WRITER_INFO_H
> Index: lib/Target/ARM/ARMELFWriterInfo.cpp
> ===================================================================
> --- lib/Target/ARM/ARMELFWriterInfo.cpp	(revision 0)
> +++ lib/Target/ARM/ARMELFWriterInfo.cpp	(revision 0)
> @@ -0,0 +1,65 @@
> +//===-- ARMELFWriterInfo.cpp - ELF Writer Info for the ARM backend --------===//
> +//
> +//                     The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file implements ELF writer information for the ARM backend.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#include "ARMELFWriterInfo.h"
> +#include "ARMRelocations.h"
> +#include "llvm/Function.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Target/TargetData.h"
> +#include "llvm/Target/TargetMachine.h"
> +
> +using namespace llvm;
> +
> +//===----------------------------------------------------------------------===//
> +//  Implementation of the ARMELFWriterInfo class
> +//===----------------------------------------------------------------------===//
> +
> +ARMELFWriterInfo::ARMELFWriterInfo(TargetMachine &TM)
> +  : TargetELFWriterInfo(TM) {
> +  // silently OK construction
> +}
> +
> +ARMELFWriterInfo::~ARMELFWriterInfo() {}
> +
> +unsigned ARMELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
> +  assert(0 && "ARMELFWriterInfo::getRelocationType() not implemented");
> +  return 0;
> +}
> +
> +long int ARMELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
> +                                                    long int Modifier) const {
> +  assert(0 && "ARMELFWriterInfo::getDefaultAddendForRelTy() not implemented");
> +  return 0;
> +}
> +
> +unsigned ARMELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
> +  assert(0 && "ARMELFWriterInfo::getRelocationTySize() not implemented");
> +  return 0;
> +}
> +
> +bool ARMELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
> +  assert(0 && "ARMELFWriterInfo::isPCRelativeRel() not implemented");
> +  return 1;
> +}
> +
> +unsigned ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
> +  assert(0 && "ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not implemented");
> +  return 0;
> +}
> +
> +long int ARMELFWriterInfo::computeRelocation(unsigned SymOffset,
> +                                             unsigned RelOffset,
> +                                             unsigned RelTy) const {
> +  assert(0 && "ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not implemented");
> +  return 0;
> +}
> Index: lib/Target/ARM/CMakeLists.txt
> ===================================================================
> --- lib/Target/ARM/CMakeLists.txt	(revision 114214)
> +++ lib/Target/ARM/CMakeLists.txt	(working copy)
> @@ -21,6 +21,7 @@
>    ARMCodeEmitter.cpp
>    ARMConstantIslandPass.cpp
>    ARMConstantPoolValue.cpp
> +  ARMELFWriterInfo.cpp
>    ARMExpandPseudoInsts.cpp
>    ARMFastISel.cpp
>    ARMGlobalMerge.cpp
> Index: lib/Target/ARM/ARMTargetMachine.h
> ===================================================================
> --- lib/Target/ARM/ARMTargetMachine.h	(revision 114214)
> +++ lib/Target/ARM/ARMTargetMachine.h	(working copy)
> @@ -16,7 +16,9 @@
> 
>  #include "llvm/Target/TargetMachine.h"
>  #include "llvm/Target/TargetData.h"
> +#include "llvm/MC/MCStreamer.h"
>  #include "ARMInstrInfo.h"
> +#include "ARMELFWriterInfo.h"
>  #include "ARMFrameInfo.h"
>  #include "ARMJITInfo.h"
>  #include "ARMSubtarget.h"
> @@ -38,10 +40,21 @@
>    InstrItineraryData  InstrItins;
>    Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
> 
> +protected:
> +  const TargetData    DataLayout;       // Calculates type size & alignment
> +  ARMELFWriterInfo    ELFWriterInfo;
> +
>  public:
>    ARMBaseTargetMachine(const Target &T, const std::string &TT,
> -                       const std::string &FS, bool isThumb);
> +                       const std::string &FS,
> +                       StringRef Target,
> +                       bool isThumb);
> 
> +  virtual const TargetData       *getTargetData() const { return &DataLayout; }
> +  virtual const ARMELFWriterInfo *getELFWriterInfo() const {
> +    return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
> +  };
> +
>    virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
>    virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
>    virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
> @@ -63,7 +76,6 @@
>  ///
>  class ARMTargetMachine : public ARMBaseTargetMachine {
>    ARMInstrInfo        InstrInfo;
> -  const TargetData    DataLayout;       // Calculates type size & alignment
>    ARMTargetLowering   TLInfo;
>    ARMSelectionDAGInfo TSInfo;
>  public:
> @@ -93,7 +105,6 @@
>  class ThumbTargetMachine : public ARMBaseTargetMachine {
>    // Either Thumb1InstrInfo or Thumb2InstrInfo.
>    OwningPtr<ARMBaseInstrInfo> InstrInfo;
> -  const TargetData    DataLayout;   // Calculates type size & alignment
>    ARMTargetLowering   TLInfo;
>    ARMSelectionDAGInfo TSInfo;
>  public:
> Index: lib/Target/TargetELFWriterInfo.cpp
> ===================================================================
> --- lib/Target/TargetELFWriterInfo.cpp	(revision 114214)
> +++ lib/Target/TargetELFWriterInfo.cpp	(working copy)
> @@ -18,6 +18,8 @@
>  using namespace llvm;
> 
>  TargetELFWriterInfo::TargetELFWriterInfo(TargetMachine &tm) : TM(tm) {
> +  // TODO(jasonwkim): [2010/09/18 09:57:44 PDT (Saturday)]
> +  // Fixme: NaCl 64bit has 32bit pointers. Need a better test.
>    is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64;
>    isLittleEndian = TM.getTargetData()->isLittleEndian();
>  }


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From scallanan at apple.com  Wed Sep 22 21:14:12 2010
From: scallanan at apple.com (Sean Callanan)
Date: Thu, 23 Sep 2010 02:14:12 -0000
Subject: [llvm-commits] [llvm] r114621 -
	/llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp
Message-ID: <20100923021412.888182A6C12C@llvm.org>

Author: spyffe
Date: Wed Sep 22 21:14:12 2010
New Revision: 114621

URL: http://llvm.org/viewvc/llvm-project?rev=114621&view=rev
Log:
Fixed a crash in the enhanced disassembler where
because of the lack of a newline, AsmToken::Eof
was being found instead of AsmToken::EndOfStatement.

Modified:
    llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp

Modified: llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp?rev=114621&r1=114620&r2=114621&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp Wed Sep 22 21:14:12 2010
@@ -62,6 +62,8 @@
   
   if (Disassembler.printInst(String, *Inst))
     return StringifyResult.setResult(-1);
+
+  String.push_back('\n');
   
   return StringifyResult.setResult(0);
 }



From jasonwkim at google.com  Wed Sep 22 22:51:41 2010
From: jasonwkim at google.com (Jason Kim)
Date: Wed, 22 Sep 2010 20:51:41 -0700
Subject: [llvm-commits] [Patch] seqence for ARM/MC object emission
	(arm-mc-elf-s01-r114621.patch)
Message-ID: <AANLkTi=brdw3hXM6ctjJNP0O3EO6_bM8oyMopMegM96V@mail.gmail.com>

This patch replaces the buggy arm-mc-elf-s01.patch5 I sent to this
list earlier this week.

Patch applies cleanly to r114621, and make check-lit passes (yes
PR8199 is not triggered :-).

Thank you.

-Jason

---

Its still mostly stub work so far.
Some cleanup in ARM Target Machine initialization - including
1. The ARM DataLayout member has been lifted upwards and initialized
directly via new method in ARMSubTarget
2. createMCStreamer() -> createX86MCStreamer()/createARMMCStreamer()
3. new ARMSubtarget::getDataLayout() method being called in ARMBaseTargetMachine
4. Quashed some random extra blank lines in X86, and added new
comments for future expansion

M       lib/Target/X86/X86TargetMachine.cpp
M       lib/Target/ARM/ARMTargetMachine.cpp
A       lib/Target/ARM/ARMELFWriterInfo.h
M       lib/Target/ARM/ARMSubtarget.h
A       lib/Target/ARM/ARMELFWriterInfo.cpp
M       lib/Target/ARM/CMakeLists.txt
M       lib/Target/ARM/ARMTargetMachine.h
M       lib/Target/TargetELFWriterInfo.cpp
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From jasonwkim at google.com  Wed Sep 22 22:55:24 2010
From: jasonwkim at google.com (Jason Kim)
Date: Wed, 22 Sep 2010 20:55:24 -0700
Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <1B431CFE-CD10-4DC9-8387-560EFADCAC67@apple.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
	<1B431CFE-CD10-4DC9-8387-560EFADCAC67@apple.com>
Message-ID: <AANLkTi=ryShkRXrTW7xk6vZb0XH++nq5DhhFej5PJLNs@mail.gmail.com>

Hi Jim,

Just makes debugging a little easier at times, is all (explicit
names), makes it easier to realize what function I am in.
Do you want me to revert the name change?

BTW, I *just* sent an update to this patch, it fixes a bug I introduced in it .

(sorry!) and Thanks

-jason


On Wed, Sep 22, 2010 at 6:48 PM, Jim Grosbach <grosbach at apple.com> wrote:
>
> On Sep 19, 2010, at 10:36 PM, Jason Kim wrote:
>
> Double oops.
> I somehow missed a compile breaking typo.
> Apologies for the noise.
> Tested against clean build dir.
> <arm-mc-elf-s01.patch4>
>
> Index: lib/Target/X86/X86TargetMachine.cpp
> ===================================================================
> --- lib/Target/X86/X86TargetMachine.cpp (revision 114214)
> +++ lib/Target/X86/X86TargetMachine.cpp (working copy)
> @@ -39,11 +39,11 @@
> ?? }
> ?}
> -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCContext &Ctx, TargetAsmBackend &TAB,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &_OS,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCCodeEmitter *_Emitter,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool RelaxAll) {
> +static MCStreamer *createX86MCStreamer(const Target &T, const std::string
> &TT,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx, TargetAsmBackend
> &TAB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &_OS,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCCodeEmitter *_Emitter,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool RelaxAll) {
>
> Why is this rename necessary? It's a static function, so there's no
> namespace collision with anything in another target.
>
> ?? Triple TheTriple(TT);
> ?? switch (TheTriple.getOS()) {
> ?? case Triple::Darwin:
> @@ -58,7 +58,7 @@
> ?? }
> ?}
> -extern "C" void LLVMInitializeX86Target() {
> +extern "C" void LLVMInitializeX86Target() {
> ?? // Register the target.
> ?? RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
> ?? RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
> @@ -81,9 +81,9 @@
> ?? // Register the object streamer.
> ?? TargetRegistry::RegisterObjectStreamer(TheX86_32Target,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createMCStreamer);
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createX86MCStreamer);
> ?? TargetRegistry::RegisterObjectStreamer(TheX86_64Target,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createMCStreamer);
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createX86MCStreamer);
> ?}
>
> @@ -100,9 +100,9 @@
> ?/// X86TargetMachine ctor - Create an X86 target.
> ?///
> -X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
> +X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
> ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &FS, bool is64Bit)
> - ?: LLVMTargetMachine(T, TT),
> + ?: LLVMTargetMachine(T, TT),
> ?? ? Subtarget(TT, FS, is64Bit),
> ?? ? DataLayout(Subtarget.getDataLayout()),
> ?? ? FrameInfo(TargetFrameInfo::StackGrowsDown,
> @@ -217,13 +217,13 @@
> ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JITCodeEmitter &JCE) {
> ?? // FIXME: Move this to TargetJITInfo!
> ?? // On Darwin, do not override 64-bit setting made in X86TargetMachine().
> - ?if (DefRelocModel == Reloc::Default &&
> + ?if (DefRelocModel == Reloc::Default &&
> ?? ? ? (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
> ?? ? setRelocationModel(Reloc::Static);
> ?? ? Subtarget.setPICStyle(PICStyles::None);
> ?? }
> -
> +
>
> Looks like a few whitespace only changes slipped into the patch. It's best
> if cosmetic changes and functional changes are done in separate patches to
> make it easier to track which revisions are making "real" changes to the
> code.
>
> ?? PM.add(createX86JITCodeEmitterPass(*this, JCE));
> ?? return false;
> Index: lib/Target/ARM/ARMTargetMachine.cpp
> ===================================================================
> --- lib/Target/ARM/ARMTargetMachine.cpp (revision 114214)
> +++ lib/Target/ARM/ARMTargetMachine.cpp (working copy)
> @@ -31,6 +31,27 @@
> ?? }
> ?}
> +// TODO(jasonwkim): [2010/09/19 10:31:16 PDT (Sunday)]
> +// This is duplicated code. Refactor this.
> +static MCStreamer *createARMMCStreamer(const Target &T, const std::string
> &TT,
>
> It's static, so it doesn't technically need the "ARM" bit in the name. Not
> really a big deal, but I'd prefer changing things here to be consistent with
> X86 for now, then adjusting both later if it's more appropriate to include
> the prefix. That is, add new bits in a manner consistent with what's already
> there, then do the cleanup, or vice versa, but not both in the same patch.
> Same basic idea as above in that it keeps the patches small and single
> purpose, which makes them easier to test and review.
>
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx, TargetAsmBackend
> &TAB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &_OS,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCCodeEmitter *_Emitter,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool RelaxAll) {
> + ?Triple TheTriple(TT);
> + ?switch (TheTriple.getOS()) {
> + ?case Triple::Darwin:
> + ? ?return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
> + ?case Triple::MinGW32:
> + ?case Triple::MinGW64:
> + ?case Triple::Cygwin:
> + ?case Triple::Win32:
> + ? ?return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
>
> ARM doesn't currently have any intention of supporting any of the Windows
> targets, so these should be omitted here, or possibly trigger an assert.
>
> + ?default:
> + ? ?return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
> + ?}
> +}
> +
> ?extern "C" void LLVMInitializeARMTarget() {
> ?? // Register the target.
> ?? RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
> @@ -39,6 +60,19 @@
> ?? // Register the target asm info.
> ?? RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
> ?? RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
> +
> + ?// Register the MC Code Emitter
> + ?TargetRegistry::RegisterCodeEmitter(TheARMTarget,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?createARMMCCodeEmitter);
> + ?TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?createARMMCCodeEmitter);
> +
> + ?// Register the object streamer.
> + ?TargetRegistry::RegisterObjectStreamer(TheARMTarget,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createARMMCStreamer);
> + ?TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? createARMMCStreamer);
> +
> ?}
> ?/// TargetMachine ctor - Create an ARM architecture model.
> @@ -46,23 +80,28 @@
> ?ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
> ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &TT,
> ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &FS,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StringRef TargetDescription,
> ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isThumb)
> ?? : LLVMTargetMachine(T, TT),
> ?? ? Subtarget(TT, FS, isThumb),
> ?? ? FrameInfo(Subtarget),
> ?? ? JITInfo(),
> - ? ?InstrItins(Subtarget.getInstrItineraryData()) {
> + ? ?InstrItins(Subtarget.getInstrItineraryData()),
> + ? ?DataLayout(TargetDescription),
>
> ?The TargetData is accessible from the TargetMachine instance via the
> getTargetData() accessor function. Is that not sufficient for what you're
> looking to accomplish?
>
> + ? ?ELFWriterInfo(*this)
>
> This creates an ELFWriter() even when the target doesn't need or want one.
> That doesn't seem right. I see X86 does the same thing, though. Doesn't seem
> right there, either, but perhaps I'm missing something and someone familiar
> with that area can comment.
>
> <snip>
>
> Index: lib/Target/ARM/ARMELFWriterInfo.h
> ===================================================================
> --- lib/Target/ARM/ARMELFWriterInfo.h (revision 0)
> +++ lib/Target/ARM/ARMELFWriterInfo.h (revision 0)
> @@ -0,0 +1,66 @@
> +//===-- ARMELFWriterInfo.h - ELF Writer Info for ARM ------------*- C++
> -*-===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file implements ELF writer information for the ARM backend.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef ARM_ELF_WRITER_INFO_H
> +#define ARM_ELF_WRITER_INFO_H
> +
> +#include "llvm/Target/TargetELFWriterInfo.h"
> +
> +namespace llvm {
> +
> + ?class ARMELFWriterInfo : public TargetELFWriterInfo {
> +
> + ? ?// ELF Relocation types for ARM
> + ? ?// FIXME: TODO(jasonwkim): [2010/09/17 14:52:25 PDT (Friday)]
>
> FIXME's don't need name/date info. "svn annotate" does the trick for that
> information.
>
> + ? ?// Come up with a better way to orgnize the 100+ ARM reloc types.
> +
> + ? ?enum ARMRelocationType {
> + ? ?};
> +
> + ?public:
> + ? ?ARMELFWriterInfo(TargetMachine &TM);
> + ? ?virtual ~ARMELFWriterInfo();
> +
> + ? ?/// getRelocationType - Returns the target specific ELF Relocation
> type.
> + ? ?/// 'MachineRelTy' contains the object code independent relocation type
> + ? ?virtual unsigned getRelocationType(unsigned MachineRelTy) const;
> +
> + ? ?/// hasRelocationAddend - True if the target uses an addend in the
> + ? ?/// ELF relocation entry.
> + ? ?virtual bool hasRelocationAddend() const { return is64Bit ? true :
> false; }
>
> There's no 64-bit here. Should this always return 'false' for ARM? Probably
> shouldn't reference 64Bit in any case, I'd think.
>
> +
> + ? ?/// getDefaultAddendForRelTy - Gets the default addend value for a
> + ? ?/// relocation entry based on the target ELF relocation type.
> + ? ?virtual long int getDefaultAddendForRelTy(unsigned RelTy,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?long int Modifier = 0) const;
>
> +
> + ? ?/// isPCRelativeRel - True if the relocation type is pc relative
> + ? ?virtual bool isPCRelativeRel(unsigned RelTy) const;
> +
> + ? ?/// getJumpTableRelocationTy - Returns the machine relocation type used
> + ? ?/// to reference a jumptable.
> + ? ?virtual unsigned getAbsoluteLabelMachineRelTy() const;
>
> Advance warning: ARM does jump tables with custom handling. This may be an
> "interesting" bit.
>
> +
> + ? ?/// computeRelocation - Some relocatable fields could be relocated
> + ? ?/// directly, avoiding the relocation symbol emission, compute the
> + ? ?/// final relocation value for this symbol.
> + ? ?virtual long int computeRelocation(unsigned SymOffset, unsigned
> RelOffset,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned RelTy) const;
> + ?};
> +
> +} // end llvm namespace
> +
> +#endif // ARM_ELF_WRITER_INFO_H
> Index: lib/Target/ARM/ARMELFWriterInfo.cpp
> ===================================================================
> --- lib/Target/ARM/ARMELFWriterInfo.cpp (revision 0)
> +++ lib/Target/ARM/ARMELFWriterInfo.cpp (revision 0)
> @@ -0,0 +1,65 @@
> +//===-- ARMELFWriterInfo.cpp - ELF Writer Info for the ARM backend
> --------===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file implements ELF writer information for the ARM backend.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#include "ARMELFWriterInfo.h"
> +#include "ARMRelocations.h"
> +#include "llvm/Function.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Target/TargetData.h"
> +#include "llvm/Target/TargetMachine.h"
> +
> +using namespace llvm;
> +
> +//===----------------------------------------------------------------------===//
> +// ?Implementation of the ARMELFWriterInfo class
> +//===----------------------------------------------------------------------===//
> +
> +ARMELFWriterInfo::ARMELFWriterInfo(TargetMachine &TM)
> + ?: TargetELFWriterInfo(TM) {
> + ?// silently OK construction
> +}
> +
> +ARMELFWriterInfo::~ARMELFWriterInfo() {}
> +
> +unsigned ARMELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
> + ?assert(0 && "ARMELFWriterInfo::getRelocationType() not implemented");
> + ?return 0;
> +}
> +
> +long int ARMELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?long int Modifier)
> const {
> + ?assert(0 && "ARMELFWriterInfo::getDefaultAddendForRelTy() not
> implemented");
> + ?return 0;
> +}
> +
> +unsigned ARMELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
> + ?assert(0 && "ARMELFWriterInfo::getRelocationTySize() not implemented");
> + ?return 0;
> +}
> +
> +bool ARMELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
> + ?assert(0 && "ARMELFWriterInfo::isPCRelativeRel() not implemented");
> + ?return 1;
> +}
> +
> +unsigned ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
> + ?assert(0 && "ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not
> implemented");
> + ?return 0;
> +}
> +
> +long int ARMELFWriterInfo::computeRelocation(unsigned SymOffset,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned RelOffset,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned RelTy) const {
> + ?assert(0 && "ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not
> implemented");
> + ?return 0;
> +}
> Index: lib/Target/ARM/CMakeLists.txt
> ===================================================================
> --- lib/Target/ARM/CMakeLists.txt (revision 114214)
> +++ lib/Target/ARM/CMakeLists.txt (working copy)
> @@ -21,6 +21,7 @@
> ?? ARMCodeEmitter.cpp
> ?? ARMConstantIslandPass.cpp
> ?? ARMConstantPoolValue.cpp
> + ?ARMELFWriterInfo.cpp
> ?? ARMExpandPseudoInsts.cpp
> ?? ARMFastISel.cpp
> ?? ARMGlobalMerge.cpp
> Index: lib/Target/ARM/ARMTargetMachine.h
> ===================================================================
> --- lib/Target/ARM/ARMTargetMachine.h (revision 114214)
> +++ lib/Target/ARM/ARMTargetMachine.h (working copy)
> @@ -16,7 +16,9 @@
> ?#include "llvm/Target/TargetMachine.h"
> ?#include "llvm/Target/TargetData.h"
> +#include "llvm/MC/MCStreamer.h"
> ?#include "ARMInstrInfo.h"
> +#include "ARMELFWriterInfo.h"
> ?#include "ARMFrameInfo.h"
> ?#include "ARMJITInfo.h"
> ?#include "ARMSubtarget.h"
> @@ -38,10 +40,21 @@
> ?? InstrItineraryData ?InstrItins;
> ?? Reloc::Model ? ? ? ?DefRelocModel; ? ?// Reloc model before it's
> overridden.
> +protected:
> + ?const TargetData ? ?DataLayout; ? ? ? // Calculates type size & alignment
> + ?ARMELFWriterInfo ? ?ELFWriterInfo;
> +
> ?public:
> ?? ARMBaseTargetMachine(const Target &T, const std::string &TT,
> - ? ? ? ? ? ? ? ? ? ? ? const std::string &FS, bool isThumb);
> + ? ? ? ? ? ? ? ? ? ? ? const std::string &FS,
> + ? ? ? ? ? ? ? ? ? ? ? StringRef Target,
> + ? ? ? ? ? ? ? ? ? ? ? bool isThumb);
> + ?virtual const TargetData ? ? ? *getTargetData() const { return
> &DataLayout; }
> + ?virtual const ARMELFWriterInfo *getELFWriterInfo() const {
> + ? ?return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
> + ?};
> +
> ?? virtual const ARMFrameInfo ? ? *getFrameInfo() const { return &FrameInfo;
> }
> ?? virtual ? ? ? ARMJITInfo ? ? ? *getJITInfo() ? ? ? ? { return &JITInfo; }
> ?? virtual const ARMSubtarget ?*getSubtargetImpl() const { return
> &Subtarget; }
> @@ -63,7 +76,6 @@
> ?///
> ?class ARMTargetMachine : public ARMBaseTargetMachine {
> ?? ARMInstrInfo ? ? ? ?InstrInfo;
> - ?const TargetData ? ?DataLayout; ? ? ? // Calculates type size & alignment
> ?? ARMTargetLowering ? TLInfo;
> ?? ARMSelectionDAGInfo TSInfo;
> ?public:
> @@ -93,7 +105,6 @@
> ?class ThumbTargetMachine : public ARMBaseTargetMachine {
> ?? // Either Thumb1InstrInfo or Thumb2InstrInfo.
> ?? OwningPtr<ARMBaseInstrInfo> InstrInfo;
> - ?const TargetData ? ?DataLayout; ? // Calculates type size & alignment
> ?? ARMTargetLowering ? TLInfo;
> ?? ARMSelectionDAGInfo TSInfo;
> ?public:
> Index: lib/Target/TargetELFWriterInfo.cpp
> ===================================================================
> --- lib/Target/TargetELFWriterInfo.cpp (revision 114214)
> +++ lib/Target/TargetELFWriterInfo.cpp (working copy)
> @@ -18,6 +18,8 @@
> ?using namespace llvm;
> ?TargetELFWriterInfo::TargetELFWriterInfo(TargetMachine &tm) : TM(tm) {
> + ?// TODO(jasonwkim): [2010/09/18 09:57:44 PDT (Saturday)]
> + ?// Fixme: NaCl 64bit has 32bit pointers. Need a better test.
> ?? is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64;
> ?? isLittleEndian = TM.getTargetData()->isLittleEndian();
> ?}
>


From aggarwa4 at illinois.edu  Wed Sep 22 23:11:27 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 04:11:27 -0000
Subject: [llvm-commits] [poolalloc] r114623 -
	/poolalloc/trunk/lib/DSA/DSTest.cpp
Message-ID: <20100923041127.57E722A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Sep 22 23:11:27 2010
New Revision: 114623

URL: http://llvm.org/viewvc/llvm-project?rev=114623&view=rev
Log:
Better error messages

Modified:
    poolalloc/trunk/lib/DSA/DSTest.cpp

Modified: poolalloc/trunk/lib/DSA/DSTest.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=114623&r1=114622&r2=114623&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSTest.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSTest.cpp Wed Sep 22 23:11:27 2010
@@ -461,7 +461,13 @@
       
       printTypesForNode(*test, NV);
       
-      assert(test->str()==typeRef && "Types don't match!");
+      if(test->str()!=typeRef) {
+              errs() << "ERROR: Type test for type :     \t" <<
+                typeRef  << " Failed \n";
+              errs() << "       But found this type:\t" <<
+                test->str() << "\n";
+              assert(0 && "Type verification failed!");
+      }
     }
     return true;
   }



From aggarwa4 at illinois.edu  Wed Sep 22 23:13:03 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 04:13:03 -0000
Subject: [llvm-commits] [poolalloc] r114624 - in
 /poolalloc/trunk/test/dsa/local: bitfields1.bc bitfields1.c bitfields1.ll
 bitfields2.c bitfields2.ll
Message-ID: <20100923041303.83E902A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Sep 22 23:13:03 2010
New Revision: 114624

URL: http://llvm.org/viewvc/llvm-project?rev=114624&view=rev
Log:
 Some tests for offsets/types for bitfields

Added:
    poolalloc/trunk/test/dsa/local/bitfields1.bc   (with props)
    poolalloc/trunk/test/dsa/local/bitfields1.c
    poolalloc/trunk/test/dsa/local/bitfields1.ll
    poolalloc/trunk/test/dsa/local/bitfields2.c
    poolalloc/trunk/test/dsa/local/bitfields2.ll

Added: poolalloc/trunk/test/dsa/local/bitfields1.bc
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields1.bc?rev=114624&view=auto
==============================================================================
Binary file - no diff available.

Propchange: poolalloc/trunk/test/dsa/local/bitfields1.bc
------------------------------------------------------------------------------
    svn:mime-type = application/octet-stream

Added: poolalloc/trunk/test/dsa/local/bitfields1.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields1.c?rev=114624&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields1.c (added)
+++ poolalloc/trunk/test/dsa/local/bitfields1.c Wed Sep 22 23:13:03 2010
@@ -0,0 +1,24 @@
+#include <stdio.h>
+
+typedef union {
+        struct {
+                signed int immed:16;
+                unsigned int rt:5;
+                unsigned int rs:5;
+                unsigned int rf:5;
+                unsigned int opcode:6;
+        };
+        unsigned int w;
+} I_format_t;
+
+ 
+int main()
+{
+        I_format_t *ia = (I_format_t *)malloc(sizeof(I_format_t));
+        ia->w = 0xAFBE0010;
+        printf("\ninstruction: %X\n",ia->w);
+        printf("opcode: %X\n",ia->opcode);
+        printf("rs: %d rt: %d rj: %d \n", ia->rs, ia->rt, ia->rf);
+        printf("immed: %d\n",ia->immed);
+        return 0;
+}

Added: poolalloc/trunk/test/dsa/local/bitfields1.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields1.ll?rev=114624&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields1.ll (added)
+++ poolalloc/trunk/test/dsa/local/bitfields1.ll Wed Sep 22 23:13:03 2010
@@ -0,0 +1,92 @@
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:ia:0,0:i16|i32::4:i8
+
+; ModuleID = 'bitfields1.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.anon = type <{ i16, i16, i8, [3 x i8] }>
+%union.I_format_t = type { i32, [1 x i32] }
+
+ at .str = private constant [18 x i8] c"\0Ainstruction: %X\0A\00", align 1 ; <[18 x i8]*> [#uses=1]
+ at .str1 = private constant [12 x i8] c"opcode: %X\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
+ at .str2 = private constant [23 x i8] c"rs: %d rt: %d rj: %d \0A\00", align 1 ; <[23 x i8]*> [#uses=1]
+ at .str3 = private constant [11 x i8] c"immed: %d\0A\00", align 1 ; <[11 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32                            ; <i32*> [#uses=2]
+  %0 = alloca i32                                 ; <i32*> [#uses=2]
+  %ia = alloca %union.I_format_t*                 ; <%union.I_format_t**> [#uses=8]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  %1 = call noalias i8* @malloc(i64 8) nounwind   ; <i8*> [#uses=1]
+  %2 = bitcast i8* %1 to %union.I_format_t*       ; <%union.I_format_t*> [#uses=1]
+  store %union.I_format_t* %2, %union.I_format_t** %ia, align 8
+  %3 = load %union.I_format_t** %ia, align 8      ; <%union.I_format_t*> [#uses=1]
+  %4 = getelementptr inbounds %union.I_format_t* %3, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32 -1346502640, i32* %4, align 4
+  %5 = load %union.I_format_t** %ia, align 8      ; <%union.I_format_t*> [#uses=1]
+  %6 = getelementptr inbounds %union.I_format_t* %5, i32 0, i32 0 ; <i32*> [#uses=1]
+  %7 = load i32* %6, align 4                      ; <i32> [#uses=1]
+  %8 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([18 x i8]* @.str, i64 0, i64 0), i32 %7) nounwind ; <i32> [#uses=0]
+  %9 = load %union.I_format_t** %ia, align 8      ; <%union.I_format_t*> [#uses=1]
+  %10 = getelementptr inbounds %union.I_format_t* %9, i32 0, i32 0 ; <i32*> [#uses=1]
+  %11 = bitcast i32* %10 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %12 = getelementptr inbounds %struct.anon* %11, i32 0, i32 2 ; <i8*> [#uses=1]
+  %13 = load i8* %12, align 1                     ; <i8> [#uses=1]
+  %14 = shl i8 %13, 2                             ; <i8> [#uses=1]
+  %15 = lshr i8 %14, 2                            ; <i8> [#uses=1]
+  %16 = trunc i8 %15 to i6                        ; <i6> [#uses=1]
+  %17 = zext i6 %16 to i32                        ; <i32> [#uses=1]
+  %18 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([12 x i8]* @.str1, i64 0, i64 0), i32 %17) nounwind ; <i32> [#uses=0]
+  %19 = load %union.I_format_t** %ia, align 8     ; <%union.I_format_t*> [#uses=1]
+  %20 = getelementptr inbounds %union.I_format_t* %19, i32 0, i32 0 ; <i32*> [#uses=1]
+  %21 = bitcast i32* %20 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %22 = getelementptr inbounds %struct.anon* %21, i32 0, i32 0 ; <i16*> [#uses=1]
+  %23 = bitcast i16* %22 to i32*                  ; <i32*> [#uses=1]
+  %24 = load i32* %23, align 1                    ; <i32> [#uses=1]
+  %25 = shl i32 %24, 1                            ; <i32> [#uses=1]
+  %26 = lshr i32 %25, 27                          ; <i32> [#uses=1]
+  %27 = trunc i32 %26 to i5                       ; <i5> [#uses=1]
+  %28 = zext i5 %27 to i32                        ; <i32> [#uses=1]
+  %29 = load %union.I_format_t** %ia, align 8     ; <%union.I_format_t*> [#uses=1]
+  %30 = getelementptr inbounds %union.I_format_t* %29, i32 0, i32 0 ; <i32*> [#uses=1]
+  %31 = bitcast i32* %30 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %32 = getelementptr inbounds %struct.anon* %31, i32 0, i32 0 ; <i16*> [#uses=1]
+  %33 = bitcast i16* %32 to i32*                  ; <i32*> [#uses=1]
+  %34 = load i32* %33, align 1                    ; <i32> [#uses=1]
+  %35 = shl i32 %34, 11                           ; <i32> [#uses=1]
+  %36 = lshr i32 %35, 27                          ; <i32> [#uses=1]
+  %37 = trunc i32 %36 to i5                       ; <i5> [#uses=1]
+  %38 = zext i5 %37 to i32                        ; <i32> [#uses=1]
+  %39 = load %union.I_format_t** %ia, align 8     ; <%union.I_format_t*> [#uses=1]
+  %40 = getelementptr inbounds %union.I_format_t* %39, i32 0, i32 0 ; <i32*> [#uses=1]
+  %41 = bitcast i32* %40 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %42 = getelementptr inbounds %struct.anon* %41, i32 0, i32 0 ; <i16*> [#uses=1]
+  %43 = bitcast i16* %42 to i32*                  ; <i32*> [#uses=1]
+  %44 = load i32* %43, align 1                    ; <i32> [#uses=1]
+  %45 = shl i32 %44, 6                            ; <i32> [#uses=1]
+  %46 = lshr i32 %45, 27                          ; <i32> [#uses=1]
+  %47 = trunc i32 %46 to i5                       ; <i5> [#uses=1]
+  %48 = zext i5 %47 to i32                        ; <i32> [#uses=1]
+  %49 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([23 x i8]* @.str2, i64 0, i64 0), i32 %48, i32 %38, i32 %28) nounwind ; <i32> [#uses=0]
+  %50 = load %union.I_format_t** %ia, align 8     ; <%union.I_format_t*> [#uses=1]
+  %51 = getelementptr inbounds %union.I_format_t* %50, i32 0, i32 0 ; <i32*> [#uses=1]
+  %52 = bitcast i32* %51 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %53 = getelementptr inbounds %struct.anon* %52, i32 0, i32 0 ; <i16*> [#uses=1]
+  %54 = load i16* %53, align 1                    ; <i16> [#uses=1]
+  %55 = sext i16 %54 to i32                       ; <i32> [#uses=1]
+  %56 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([11 x i8]* @.str3, i64 0, i64 0), i32 %55) nounwind ; <i32> [#uses=0]
+  store i32 0, i32* %0, align 4
+  %57 = load i32* %0, align 4                     ; <i32> [#uses=1]
+  store i32 %57, i32* %retval, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32* %retval                    ; <i32> [#uses=1]
+  ret i32 %retval1
+}
+
+declare noalias i8* @malloc(i64) nounwind
+
+declare i32 @printf(i8* noalias, ...) nounwind

Added: poolalloc/trunk/test/dsa/local/bitfields2.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields2.c?rev=114624&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields2.c (added)
+++ poolalloc/trunk/test/dsa/local/bitfields2.c Wed Sep 22 23:13:03 2010
@@ -0,0 +1,39 @@
+#include <stdio.h>
+
+typedef union {
+	struct {
+		unsigned int fn:6;
+		unsigned int sh:5;
+		unsigned int rd:5;
+	};
+	struct {
+		signed int immed:16;
+		unsigned int rt:5;
+		unsigned int rs:5;
+		unsigned int opcode:6;
+	};
+	unsigned int w;
+} mips_format_t;
+
+
+int main()
+{
+	int i;
+	mips_format_t ia;
+	unsigned int codes[] = {0x27bdffe8, 0xAFBE0010, 0x03A0F021, 0x2402000E};
+	int n = sizeof(codes)/sizeof(int);
+	for (i=0; i<n; i++) {
+		ia.w = codes[i];
+		printf("\ninstruction: %X\n",ia.w);
+		printf("opcode: %X\n",ia.opcode);
+		printf("rs: %d rt: %d\n", ia.rs, ia.rt);
+		if (ia.opcode==0) {
+			printf("rd: %d  sh: %d  fn: %X\n",ia.rd,ia.sh,ia.fn);
+		}
+		else {
+			printf("immed: %d\n",ia.immed);
+		}
+	}
+	return 0;
+}
+

Added: poolalloc/trunk/test/dsa/local/bitfields2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields2.ll?rev=114624&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields2.ll (added)
+++ poolalloc/trunk/test/dsa/local/bitfields2.ll Wed Sep 22 23:13:03 2010
@@ -0,0 +1,152 @@
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:codes,0:i32Array
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:ia,0:i16|i32
+
+; ModuleID = 'bitfields2.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%0 = type <{ i16, i16 }>
+%struct.anon = type <{ i16, [2 x i8] }>
+%union.mips_format_t = type { i32 }
+
+ at C.0.1960 = private constant [4 x i32] [i32 666763240, i32 -1346502640, i32 60878881, i32 604110862] ; <[4 x i32]*> [#uses=4]
+ at .str = private constant [18 x i8] c"\0Ainstruction: %X\0A\00", align 1 ; <[18 x i8]*> [#uses=1]
+ at .str1 = private constant [12 x i8] c"opcode: %X\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
+ at .str2 = private constant [15 x i8] c"rs: %d rt: %d\0A\00", align 1 ; <[15 x i8]*> [#uses=1]
+ at .str3 = private constant [24 x i8] c"rd: %d  sh: %d  fn: %X\0A\00", align 1 ; <[24 x i8]*> [#uses=1]
+ at .str4 = private constant [11 x i8] c"immed: %d\0A\00", align 1 ; <[11 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32                            ; <i32*> [#uses=2]
+  %0 = alloca i32                                 ; <i32*> [#uses=2]
+  %i = alloca i32                                 ; <i32*> [#uses=5]
+  %ia = alloca %union.mips_format_t               ; <%union.mips_format_t*> [#uses=10]
+  %codes = alloca [4 x i32]                       ; <[4 x i32]*> [#uses=5]
+  %n = alloca i32                                 ; <i32*> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  %1 = getelementptr inbounds [4 x i32]* %codes, i32 0, i32 0 ; <i32*> [#uses=1]
+  %2 = load i32* getelementptr inbounds ([4 x i32]* @C.0.1960, i64 0, i64 0), align 4 ; <i32> [#uses=1]
+  store i32 %2, i32* %1, align 4
+  %3 = getelementptr inbounds [4 x i32]* %codes, i32 0, i32 1 ; <i32*> [#uses=1]
+  %4 = load i32* getelementptr inbounds ([4 x i32]* @C.0.1960, i64 0, i64 1), align 4 ; <i32> [#uses=1]
+  store i32 %4, i32* %3, align 4
+  %5 = getelementptr inbounds [4 x i32]* %codes, i32 0, i32 2 ; <i32*> [#uses=1]
+  %6 = load i32* getelementptr inbounds ([4 x i32]* @C.0.1960, i64 0, i64 2), align 4 ; <i32> [#uses=1]
+  store i32 %6, i32* %5, align 4
+  %7 = getelementptr inbounds [4 x i32]* %codes, i32 0, i32 3 ; <i32*> [#uses=1]
+  %8 = load i32* getelementptr inbounds ([4 x i32]* @C.0.1960, i64 0, i64 3), align 4 ; <i32> [#uses=1]
+  store i32 %8, i32* %7, align 4
+  store i32 4, i32* %n, align 4
+  store i32 0, i32* %i, align 4
+  br label %bb4
+
+bb:                                               ; preds = %bb4
+  %9 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %10 = sext i32 %9 to i64                        ; <i64> [#uses=1]
+  %11 = getelementptr inbounds [4 x i32]* %codes, i64 0, i64 %10 ; <i32*> [#uses=1]
+  %12 = load i32* %11, align 4                    ; <i32> [#uses=1]
+  %13 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32 %12, i32* %13, align 4
+  %14 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %15 = load i32* %14, align 4                    ; <i32> [#uses=1]
+  %16 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([18 x i8]* @.str, i64 0, i64 0), i32 %15) nounwind ; <i32> [#uses=0]
+  %17 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %18 = bitcast i32* %17 to %0*                   ; <%0*> [#uses=1]
+  %19 = getelementptr inbounds %0* %18, i32 0, i32 0 ; <i16*> [#uses=1]
+  %20 = bitcast i16* %19 to i32*                  ; <i32*> [#uses=1]
+  %21 = load i32* %20, align 1                    ; <i32> [#uses=1]
+  %22 = lshr i32 %21, 26                          ; <i32> [#uses=1]
+  %23 = trunc i32 %22 to i6                       ; <i6> [#uses=1]
+  %24 = zext i6 %23 to i32                        ; <i32> [#uses=1]
+  %25 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([12 x i8]* @.str1, i64 0, i64 0), i32 %24) nounwind ; <i32> [#uses=0]
+  %26 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %27 = bitcast i32* %26 to %0*                   ; <%0*> [#uses=1]
+  %28 = getelementptr inbounds %0* %27, i32 0, i32 0 ; <i16*> [#uses=1]
+  %29 = bitcast i16* %28 to i32*                  ; <i32*> [#uses=1]
+  %30 = load i32* %29, align 1                    ; <i32> [#uses=1]
+  %31 = shl i32 %30, 11                           ; <i32> [#uses=1]
+  %32 = lshr i32 %31, 27                          ; <i32> [#uses=1]
+  %33 = trunc i32 %32 to i5                       ; <i5> [#uses=1]
+  %34 = zext i5 %33 to i32                        ; <i32> [#uses=1]
+  %35 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %36 = bitcast i32* %35 to %0*                   ; <%0*> [#uses=1]
+  %37 = getelementptr inbounds %0* %36, i32 0, i32 0 ; <i16*> [#uses=1]
+  %38 = bitcast i16* %37 to i32*                  ; <i32*> [#uses=1]
+  %39 = load i32* %38, align 1                    ; <i32> [#uses=1]
+  %40 = shl i32 %39, 6                            ; <i32> [#uses=1]
+  %41 = lshr i32 %40, 27                          ; <i32> [#uses=1]
+  %42 = trunc i32 %41 to i5                       ; <i5> [#uses=1]
+  %43 = zext i5 %42 to i32                        ; <i32> [#uses=1]
+  %44 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([15 x i8]* @.str2, i64 0, i64 0), i32 %43, i32 %34) nounwind ; <i32> [#uses=0]
+  %45 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %46 = bitcast i32* %45 to %0*                   ; <%0*> [#uses=1]
+  %47 = getelementptr inbounds %0* %46, i32 0, i32 0 ; <i16*> [#uses=1]
+  %48 = bitcast i16* %47 to i32*                  ; <i32*> [#uses=1]
+  %49 = load i32* %48, align 1                    ; <i32> [#uses=1]
+  %50 = lshr i32 %49, 26                          ; <i32> [#uses=1]
+  %51 = trunc i32 %50 to i6                       ; <i6> [#uses=1]
+  %52 = icmp eq i6 %51, 0                         ; <i1> [#uses=1]
+  br i1 %52, label %bb1, label %bb2
+
+bb1:                                              ; preds = %bb
+  %53 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %54 = bitcast i32* %53 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %55 = getelementptr inbounds %struct.anon* %54, i32 0, i32 0 ; <i16*> [#uses=1]
+  %56 = load i16* %55, align 1                    ; <i16> [#uses=1]
+  %57 = shl i16 %56, 10                           ; <i16> [#uses=1]
+  %58 = lshr i16 %57, 10                          ; <i16> [#uses=1]
+  %59 = trunc i16 %58 to i6                       ; <i6> [#uses=1]
+  %60 = zext i6 %59 to i32                        ; <i32> [#uses=1]
+  %61 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %62 = bitcast i32* %61 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %63 = getelementptr inbounds %struct.anon* %62, i32 0, i32 0 ; <i16*> [#uses=1]
+  %64 = load i16* %63, align 1                    ; <i16> [#uses=1]
+  %65 = shl i16 %64, 5                            ; <i16> [#uses=1]
+  %66 = lshr i16 %65, 11                          ; <i16> [#uses=1]
+  %67 = trunc i16 %66 to i5                       ; <i5> [#uses=1]
+  %68 = zext i5 %67 to i32                        ; <i32> [#uses=1]
+  %69 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %70 = bitcast i32* %69 to %struct.anon*         ; <%struct.anon*> [#uses=1]
+  %71 = getelementptr inbounds %struct.anon* %70, i32 0, i32 0 ; <i16*> [#uses=1]
+  %72 = load i16* %71, align 1                    ; <i16> [#uses=1]
+  %73 = lshr i16 %72, 11                          ; <i16> [#uses=1]
+  %74 = trunc i16 %73 to i5                       ; <i5> [#uses=1]
+  %75 = zext i5 %74 to i32                        ; <i32> [#uses=1]
+  %76 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i32 %75, i32 %68, i32 %60) nounwind ; <i32> [#uses=0]
+  br label %bb3
+
+bb2:                                              ; preds = %bb
+  %77 = getelementptr inbounds %union.mips_format_t* %ia, i32 0, i32 0 ; <i32*> [#uses=1]
+  %78 = bitcast i32* %77 to %0*                   ; <%0*> [#uses=1]
+  %79 = getelementptr inbounds %0* %78, i32 0, i32 0 ; <i16*> [#uses=1]
+  %80 = load i16* %79, align 1                    ; <i16> [#uses=1]
+  %81 = sext i16 %80 to i32                       ; <i32> [#uses=1]
+  %82 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([11 x i8]* @.str4, i64 0, i64 0), i32 %81) nounwind ; <i32> [#uses=0]
+  br label %bb3
+
+bb3:                                              ; preds = %bb2, %bb1
+  %83 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %84 = add nsw i32 %83, 1                        ; <i32> [#uses=1]
+  store i32 %84, i32* %i, align 4
+  br label %bb4
+
+bb4:                                              ; preds = %bb3, %entry
+  %85 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %86 = load i32* %n, align 4                     ; <i32> [#uses=1]
+  %87 = icmp slt i32 %85, %86                     ; <i1> [#uses=1]
+  br i1 %87, label %bb, label %bb5
+
+bb5:                                              ; preds = %bb4
+  store i32 0, i32* %0, align 4
+  %88 = load i32* %0, align 4                     ; <i32> [#uses=1]
+  store i32 %88, i32* %retval, align 4
+  br label %return
+
+return:                                           ; preds = %bb5
+  %retval6 = load i32* %retval                    ; <i32> [#uses=1]
+  ret i32 %retval6
+}
+
+declare i32 @printf(i8* noalias, ...) nounwind



From wdietz2 at illinois.edu  Wed Sep 22 23:25:07 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 23 Sep 2010 04:25:07 -0000
Subject: [llvm-commits] [poolalloc] r114625 -
	/poolalloc/trunk/lib/DSA/DSTest.cpp
Message-ID: <20100923042507.8F9CF2A6C12C@llvm.org>

Author: wdietz2
Date: Wed Sep 22 23:25:07 2010
New Revision: 114625

URL: http://llvm.org/viewvc/llvm-project?rev=114625&view=rev
Log:
Touchup some formatting issues.
No functionality changes.

Modified:
    poolalloc/trunk/lib/DSA/DSTest.cpp

Modified: poolalloc/trunk/lib/DSA/DSTest.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=114625&r1=114624&r2=114625&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSTest.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSTest.cpp Wed Sep 22 23:25:07 2010
@@ -462,11 +462,11 @@
       printTypesForNode(*test, NV);
       
       if(test->str()!=typeRef) {
-              errs() << "ERROR: Type test for type :     \t" <<
-                typeRef  << " Failed \n";
-              errs() << "       But found this type:\t" <<
-                test->str() << "\n";
-              assert(0 && "Type verification failed!");
+        errs() << "ERROR: Testing for type :   \t" <<
+          typeRef  << "\n";
+        errs() << "       But found this type :\t" <<
+          test->str() << "\n";
+        assert(0 && "Type verification failed!");
       }
     }
     return true;
@@ -519,11 +519,11 @@
             I != E; ++I ) {
           if (shouldHaveFlag == (ActualFlags.find(*I) == std::string::npos))
           {
-              errs() << "ERROR: Verify flags for:     \t" <<
-                NodeFlagOption  << "\n";
-              errs() << "       But found these flags:\t" <<
-                ActualFlags << "\n";
-              assert(0 && "Flag verification failed!");
+            errs() << "ERROR: Verify flags for:      \t" <<
+              NodeFlagOption  << "\n";
+            errs() << "       But found these flags: \t" <<
+              ActualFlags << "\n";
+            assert(0 && "Flag verification failed!");
           }
         }
 



From lhames at gmail.com  Wed Sep 22 23:28:55 2010
From: lhames at gmail.com (Lang Hames)
Date: Thu, 23 Sep 2010 04:28:55 -0000
Subject: [llvm-commits] [llvm] r114626 - in /llvm/trunk:
 include/llvm/CodeGen/LinkAllCodegenComponents.h
 include/llvm/CodeGen/Passes.h include/llvm/CodeGen/RegAllocPBQP.h
 lib/CodeGen/RegAllocPBQP.cpp
Message-ID: <20100923042855.1C2702A6C12C@llvm.org>

Author: lhames
Date: Wed Sep 22 23:28:54 2010
New Revision: 114626

URL: http://llvm.org/viewvc/llvm-project?rev=114626&view=rev
Log:
Moved the PBQP allocator class out of the header and back in to the cpp file to hide the gory details.
Allocator instances can now be created by calling createPBQPRegisterAllocator.

Tidied up use of CoalescerPair as per Jakob's suggestions.

Made the new PBQPBuilder based construction process the default. The internal construction process
remains in-place and available via -pbqp-builder=false for now. It will be removed shortly if the new
process doesn't cause any regressions.


Modified:
    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
    llvm/trunk/include/llvm/CodeGen/Passes.h
    llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h
    llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=114626&r1=114625&r2=114626&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Wed Sep 22 23:28:54 2010
@@ -35,7 +35,7 @@
 
       (void) llvm::createFastRegisterAllocator();
       (void) llvm::createLinearScanRegisterAllocator();
-      (void) llvm::createPBQPRegisterAllocator();
+      (void) llvm::createDefaultPBQPRegisterAllocator();
 
       (void) llvm::createSimpleRegisterCoalescer();
       

Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=114626&r1=114625&r2=114626&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Wed Sep 22 23:28:54 2010
@@ -103,7 +103,7 @@
   /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
   /// Quadratic Prograaming (PBQP) based register allocator.
   ///
-  FunctionPass *createPBQPRegisterAllocator();
+  FunctionPass *createDefaultPBQPRegisterAllocator();
 
   /// SimpleRegisterCoalescing Pass - Coalesce all copies possible.  Can run
   /// independently of the register allocator.

Modified: llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h?rev=114626&r1=114625&r2=114626&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegAllocPBQP.h Wed Sep 22 23:28:54 2010
@@ -160,125 +160,7 @@
                             PBQP::PBQPNum benefit);
   };
 
-  ///
-  /// PBQP based allocators solve the register allocation problem by mapping
-  /// register allocation problems to Partitioned Boolean Quadratic
-  /// Programming problems.
-  class RegAllocPBQP : public MachineFunctionPass {
-  public:
-
-    static char ID;
-
-    /// Construct a PBQP register allocator.
-    RegAllocPBQP(std::auto_ptr<PBQPBuilder> b) : MachineFunctionPass(ID), builder(b) {}
-
-    /// Return the pass name.
-    virtual const char* getPassName() const {
-      return "PBQP Register Allocator";
-    }
-
-    /// PBQP analysis usage.
-    virtual void getAnalysisUsage(AnalysisUsage &au) const;
-
-    /// Perform register allocation
-    virtual bool runOnMachineFunction(MachineFunction &MF);
-
-  private:
-
-    typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
-    typedef std::vector<const LiveInterval*> Node2LIMap;
-    typedef std::vector<unsigned> AllowedSet;
-    typedef std::vector<AllowedSet> AllowedSetMap;
-    typedef std::pair<unsigned, unsigned> RegPair;
-    typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
-    typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
-    typedef std::set<unsigned> RegSet;
-
-
-    std::auto_ptr<PBQPBuilder> builder;
-
-    MachineFunction *mf;
-    const TargetMachine *tm;
-    const TargetRegisterInfo *tri;
-    const TargetInstrInfo *tii;
-    const MachineLoopInfo *loopInfo;
-    MachineRegisterInfo *mri;
-    RenderMachineFunction *rmf;
-
-    LiveIntervals *lis;
-    LiveStacks *lss;
-    VirtRegMap *vrm;
-
-    LI2NodeMap li2Node;
-    Node2LIMap node2LI;
-    AllowedSetMap allowedSets;
-    RegSet vregsToAlloc, emptyIntervalVRegs;
-    NodeVector problemNodes;
-
-
-    /// Builds a PBQP cost vector.
-    template <typename RegContainer>
-    PBQP::Vector buildCostVector(unsigned vReg,
-                                 const RegContainer &allowed,
-                                 const CoalesceMap &cealesces,
-                                 PBQP::PBQPNum spillCost) const;
-
-    /// \brief Builds a PBQP interference matrix.
-    ///
-    /// @return Either a pointer to a non-zero PBQP matrix representing the
-    ///         allocation option costs, or a null pointer for a zero matrix.
-    ///
-    /// Expects allowed sets for two interfering LiveIntervals. These allowed
-    /// sets should contain only allocable registers from the LiveInterval's
-    /// register class, with any interfering pre-colored registers removed.
-    template <typename RegContainer>
-    PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1,
-                                          const RegContainer &allowed2) const;
-
-    ///
-    /// Expects allowed sets for two potentially coalescable LiveIntervals,
-    /// and an estimated benefit due to coalescing. The allowed sets should
-    /// contain only allocable registers from the LiveInterval's register
-    /// classes, with any interfering pre-colored registers removed.
-    template <typename RegContainer>
-    PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1,
-                                        const RegContainer &allowed2,
-                                        PBQP::PBQPNum cBenefit) const;
-
-    /// \brief Finds coalescing opportunities and returns them as a map.
-    ///
-    /// Any entries in the map are guaranteed coalescable, even if their
-    /// corresponding live intervals overlap.
-    CoalesceMap findCoalesces();
-
-    /// \brief Finds the initial set of vreg intervals to allocate.
-    void findVRegIntervalsToAlloc();
-
-    /// \brief Constructs a PBQP problem representation of the register
-    /// allocation problem for this function.
-    ///
-    /// @return a PBQP solver object for the register allocation problem.
-    PBQP::Graph constructPBQPProblem();
-
-    /// \brief Adds a stack interval if the given live interval has been
-    /// spilled. Used to support stack slot coloring.
-    void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
-
-    /// \brief Given a solved PBQP problem maps this solution back to a register
-    /// assignment.
-    bool mapPBQPToRegAlloc(const PBQP::Solution &solution);
-
-    /// \brief Given a solved PBQP problem maps this solution back to a register
-    /// assignment.
-    bool mapPBQPToRegAlloc2(const PBQPRAProblem &problem,
-                            const PBQP::Solution &solution);
-
-    /// \brief Postprocessing before final spilling. Sets basic block "live in"
-    /// variables.
-    void finalizeAlloc() const;
-
-  };
-
+  FunctionPass* createPBQPRegisterAllocator(std::auto_ptr<PBQPBuilder> builder);
 }
 
 #endif /* LLVM_CODEGEN_REGALLOCPBQP_H */

Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114626&r1=114625&r2=114626&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Wed Sep 22 23:28:54 2010
@@ -56,11 +56,11 @@
 #include <set>
 #include <vector>
 
-namespace llvm {
+using namespace llvm;
 
 static RegisterRegAlloc
 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
-                       llvm::createPBQPRegisterAllocator);
+                       createDefaultPBQPRegisterAllocator);
 
 static cl::opt<bool>
 pbqpCoalescing("pbqp-coalescing",
@@ -69,17 +69,149 @@
 
 static cl::opt<bool>
 pbqpBuilder("pbqp-builder",
-                cl::desc("Use new builder system."),
-                cl::init(false), cl::Hidden);
+             cl::desc("Use new builder system."),
+             cl::init(true), cl::Hidden);
 
 
 static cl::opt<bool>
 pbqpPreSplitting("pbqp-pre-splitting",
-                 cl::desc("Pre-splite before PBQP register allocation."),
+                 cl::desc("Pre-split before PBQP register allocation."),
                  cl::init(false), cl::Hidden);
 
+namespace {
+
+///
+/// PBQP based allocators solve the register allocation problem by mapping
+/// register allocation problems to Partitioned Boolean Quadratic
+/// Programming problems.
+class RegAllocPBQP : public MachineFunctionPass {
+public:
+
+  static char ID;
+
+  /// Construct a PBQP register allocator.
+  RegAllocPBQP(std::auto_ptr<PBQPBuilder> b) : MachineFunctionPass(ID), builder(b) {}
+
+  /// Return the pass name.
+  virtual const char* getPassName() const {
+    return "PBQP Register Allocator";
+  }
+
+  /// PBQP analysis usage.
+  virtual void getAnalysisUsage(AnalysisUsage &au) const;
+
+  /// Perform register allocation
+  virtual bool runOnMachineFunction(MachineFunction &MF);
+
+private:
+
+  typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
+  typedef std::vector<const LiveInterval*> Node2LIMap;
+  typedef std::vector<unsigned> AllowedSet;
+  typedef std::vector<AllowedSet> AllowedSetMap;
+  typedef std::pair<unsigned, unsigned> RegPair;
+  typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
+  typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
+  typedef std::set<unsigned> RegSet;
+
+
+  std::auto_ptr<PBQPBuilder> builder;
+
+  MachineFunction *mf;
+  const TargetMachine *tm;
+  const TargetRegisterInfo *tri;
+  const TargetInstrInfo *tii;
+  const MachineLoopInfo *loopInfo;
+  MachineRegisterInfo *mri;
+  RenderMachineFunction *rmf;
+
+  LiveIntervals *lis;
+  LiveStacks *lss;
+  VirtRegMap *vrm;
+
+  LI2NodeMap li2Node;
+  Node2LIMap node2LI;
+  AllowedSetMap allowedSets;
+  RegSet vregsToAlloc, emptyIntervalVRegs;
+  NodeVector problemNodes;
+
+
+  /// Builds a PBQP cost vector.
+  template <typename RegContainer>
+  PBQP::Vector buildCostVector(unsigned vReg,
+                               const RegContainer &allowed,
+                               const CoalesceMap &cealesces,
+                               PBQP::PBQPNum spillCost) const;
+
+  /// \brief Builds a PBQP interference matrix.
+  ///
+  /// @return Either a pointer to a non-zero PBQP matrix representing the
+  ///         allocation option costs, or a null pointer for a zero matrix.
+  ///
+  /// Expects allowed sets for two interfering LiveIntervals. These allowed
+  /// sets should contain only allocable registers from the LiveInterval's
+  /// register class, with any interfering pre-colored registers removed.
+  template <typename RegContainer>
+  PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1,
+                                        const RegContainer &allowed2) const;
+
+  ///
+  /// Expects allowed sets for two potentially coalescable LiveIntervals,
+  /// and an estimated benefit due to coalescing. The allowed sets should
+  /// contain only allocable registers from the LiveInterval's register
+  /// classes, with any interfering pre-colored registers removed.
+  template <typename RegContainer>
+  PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1,
+                                      const RegContainer &allowed2,
+                                      PBQP::PBQPNum cBenefit) const;
+
+  /// \brief Finds coalescing opportunities and returns them as a map.
+  ///
+  /// Any entries in the map are guaranteed coalescable, even if their
+  /// corresponding live intervals overlap.
+  CoalesceMap findCoalesces();
+
+  /// \brief Finds the initial set of vreg intervals to allocate.
+  void findVRegIntervalsToAlloc();
+
+  /// \brief Constructs a PBQP problem representation of the register
+  /// allocation problem for this function.
+  ///
+  /// Old Construction Process - this functionality has been subsumed
+  /// by PBQPBuilder. This function will only be hanging around for a little
+  /// while until the new system has been fully tested.
+  /// 
+  /// @return a PBQP solver object for the register allocation problem.
+  PBQP::Graph constructPBQPProblemOld();
+
+  /// \brief Adds a stack interval if the given live interval has been
+  /// spilled. Used to support stack slot coloring.
+  void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
+
+  /// \brief Given a solved PBQP problem maps this solution back to a register
+  /// assignment.
+  ///
+  /// Old Construction Process - this functionality has been subsumed
+  /// by PBQPBuilder. This function will only be hanging around for a little
+  /// while until the new system has been fully tested.
+  /// 
+  bool mapPBQPToRegAllocOld(const PBQP::Solution &solution);
+
+  /// \brief Given a solved PBQP problem maps this solution back to a register
+  /// assignment.
+  bool mapPBQPToRegAlloc(const PBQPRAProblem &problem,
+                         const PBQP::Solution &solution);
+
+  /// \brief Postprocessing before final spilling. Sets basic block "live in"
+  /// variables.
+  void finalizeAlloc() const;
+
+};
+
 char RegAllocPBQP::ID = 0;
 
+} // End anonymous namespace.
+
 unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
   Node2VReg::const_iterator vregItr = node2VReg.find(node);
   assert(vregItr != node2VReg.end() && "No vreg for node.");
@@ -277,58 +409,54 @@
          miItr != miEnd; ++miItr) {
       const MachineInstr *mi = &*miItr;
 
-      if (!mi->isCopy() && !mi->isSubregToReg())
-        continue; // Not coalescable.
-
       if (!cp.setRegisters(mi))
         continue; // Not coalescable.
 
       if (cp.getSrcReg() == cp.getDstReg())
         continue; // Already coalesced.
 
-      if (cp.isCoalescable(mi)) {
-
-        unsigned dst = cp.getDstReg(),
-                 src = cp.getSrcReg();
-
+      unsigned dst = cp.getDstReg(),
+               src = cp.getSrcReg();
 
+      const float copyFactor = 0.5; // Cost of copy relative to load. Current
+      // value plucked randomly out of the air.
+                                      
+      PBQP::PBQPNum cBenefit =
+        copyFactor * LiveIntervals::getSpillWeight(false, true,
+                                                   loopInfo->getLoopDepth(mbb));
 
-        PBQP::PBQPNum cBenefit =
-          std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb));
-
-        if (cp.isPhys()) {
-          if (!lis->isAllocatable(dst))
-            continue;
+      if (cp.isPhys()) {
+        if (!lis->isAllocatable(dst))
+          continue;
 
-          const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
-          unsigned pregOpt = 0;  
-          while (pregOpt < allowed.size() && allowed[pregOpt] != dst)
-            ++pregOpt;
-          if (pregOpt < allowed.size()) {
-            ++pregOpt; // +1 to account for spill option.
-            PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
-            addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
-          }
+        const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
+        unsigned pregOpt = 0;  
+        while (pregOpt < allowed.size() && allowed[pregOpt] != dst)
+          ++pregOpt;
+        if (pregOpt < allowed.size()) {
+          ++pregOpt; // +1 to account for spill option.
+          PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
+          addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
+        }
+      } else {
+        const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
+        const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
+        PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
+        PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
+        PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
+        if (edge == g.edgesEnd()) {
+          edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
+                                                      allowed2->size() + 1,
+                                                      0));
         } else {
-          const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
-          const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
-          PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
-          PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
-          PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
-          if (edge == g.edgesEnd()) {
-            edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
-                                                        allowed2->size() + 1,
-                                                        0));
-          } else {
-            if (g.getEdgeNode1(edge) == node2) {
-              std::swap(node1, node2);
-              std::swap(allowed1, allowed2);
-            }
+          if (g.getEdgeNode1(edge) == node2) {
+            std::swap(node1, node2);
+            std::swap(allowed1, allowed2);
           }
-            
-          addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
-                             cBenefit);
         }
+            
+        addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
+                           cBenefit);
       }
     }
   }
@@ -336,7 +464,6 @@
   return p;
 }
 
-
 void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
                                                    unsigned pregOption,
                                                    PBQP::PBQPNum benefit) {
@@ -707,7 +834,7 @@
   }
 }
 
-PBQP::Graph RegAllocPBQP::constructPBQPProblem() {
+PBQP::Graph RegAllocPBQP::constructPBQPProblemOld() {
 
   typedef std::vector<const LiveInterval*> LIVector;
   typedef std::vector<unsigned> RegVector;
@@ -893,7 +1020,7 @@
   stackInterval.MergeRangesInAsValue(rhsInterval, vni);
 }
 
-bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
+bool RegAllocPBQP::mapPBQPToRegAllocOld(const PBQP::Solution &solution) {
 
   // Set to true if we have any spills
   bool anotherRoundNeeded = false;
@@ -964,8 +1091,8 @@
   return !anotherRoundNeeded;
 }
 
-bool RegAllocPBQP::mapPBQPToRegAlloc2(const PBQPRAProblem &problem,
-                                      const PBQP::Solution &solution) {
+bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
+                                     const PBQP::Solution &solution) {
   // Set to true if we have any spills
   bool anotherRoundNeeded = false;
 
@@ -1132,11 +1259,11 @@
       while (!pbqpAllocComplete) {
         DEBUG(dbgs() << "  PBQP Regalloc round " << round << ":\n");
 
-        PBQP::Graph problem = constructPBQPProblem();
+        PBQP::Graph problem = constructPBQPProblemOld();
         PBQP::Solution solution =
           PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
 
-        pbqpAllocComplete = mapPBQPToRegAlloc(solution);
+        pbqpAllocComplete = mapPBQPToRegAllocOld(solution);
 
         ++round;
       }
@@ -1150,7 +1277,7 @@
           PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
             problem->getGraph());
 
-        pbqpAllocComplete = mapPBQPToRegAlloc2(*problem, solution);
+        pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution);
 
         ++round;
       }
@@ -1179,15 +1306,18 @@
   return true;
 }
 
-FunctionPass* createPBQPRegisterAllocator() {
-  if (pbqpCoalescing) {
-    return new RegAllocPBQP(
-                 std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
-  } // else
-  return new RegAllocPBQP(
-                 std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));
+FunctionPass* llvm::createPBQPRegisterAllocator(
+                                           std::auto_ptr<PBQPBuilder> builder) {
+  return new RegAllocPBQP(builder);
 }
 
+FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
+  if (pbqpCoalescing) {
+    return createPBQPRegisterAllocator(
+             std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
+  } // else
+  return createPBQPRegisterAllocator(
+           std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));
 }
 
 #undef DEBUG_TYPE



From lhames at gmail.com  Wed Sep 22 23:35:37 2010
From: lhames at gmail.com (Lang Hames)
Date: Thu, 23 Sep 2010 14:35:37 +1000
Subject: [llvm-commits] [llvm] r114429 - in /llvm/trunk:
 include/llvm/CodeGen/PBQP/Heuristics/Briggs.h
 include/llvm/CodeGen/RegAllocPBQP.h lib/CodeGen/RegAllocPBQP.cpp
In-Reply-To: <F11F3360-CC6D-4C9F-AADA-BD2C98535E86@2pi.dk>
References: <20100921131936.528C02A6C12C@llvm.org>
	<F11F3360-CC6D-4C9F-AADA-BD2C98535E86@2pi.dk>
Message-ID: <AANLkTinsuDeR--swb7z1WJJTDK57AXJ9LUrf-EwWqgSc@mail.gmail.com>

>
> Yay!
>

Yep - CoalescerPair makes life much easier.

The redundant lines have been removed in r114626 (and the coalescing benefit
calculation has been replaced with a call to LiveIntervals::getSpillWeight).
Thanks for the suggestions!

- Lang.
-------------- next part --------------
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From baldrick at free.fr  Thu Sep 23 01:10:32 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 23 Sep 2010 06:10:32 -0000
Subject: [llvm-commits] [zorg] r114629 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100923061032.F2D792A6C12C@llvm.org>

Author: baldrick
Date: Thu Sep 23 01:10:32 2010
New Revision: 114629

URL: http://llvm.org/viewvc/llvm-project?rev=114629&view=rev
Log:
Turn this into an expensive checks llvm-gcc self-host build.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114629&r1=114628&r2=114629&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Sep 23 01:10:32 2010
@@ -85,7 +85,10 @@
         {'name' : "llvm-x86_64-linux-checks",
         'slavenames':["gcc10"],
         'builddir':"llvm-x86_64-linux-checks",
-        'factory':LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", expensive_checks=True)},
+        'factory':LLVMBuilder.getLLVMGCCBuildFactory("x86_64-pc-linux-gnu",
+                                                     stage1_config='Release+Asserts+Checks',
+                                                     stage2_config='Release+Asserts+Checks',
+                                                     extra_configure_args=['--disable-multilib'])},
         {'name' : "llvm-gcc-i386-linux-selfhost",
          'slavenames':["gcc11"],
          'builddir':"llvm-gcc-i386-linux-selfhost",



From baldrick at free.fr  Thu Sep 23 01:29:13 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 23 Sep 2010 08:29:13 +0200
Subject: [llvm-commits] [llvm] r114599 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/bit-test-shift.ll
In-Reply-To: <20100922225822.3B7E22A6C12C@llvm.org>
References: <20100922225822.3B7E22A6C12C@llvm.org>
Message-ID: <4C9AF3B9.1010808@free.fr>

Hi Owen,

> A select between a constant and zero, when fed by a bit test, can be efficiently
> lowered using a series of shifts.
> Fixes<rdar://problem/8285015>.

can't you do this at the IR level?  At the IR level, you can change

   %s = select i1 %cond, i32 %a, i32 0

into

   %cond.1 = sext i1 %cond to i32
   %s = and i32 %a, %cond.1

which could be a win depending on where %cond comes from.

Ciao,

Duncan.

From nicholas at mxc.ca  Thu Sep 23 01:35:17 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 22 Sep 2010 23:35:17 -0700
Subject: [llvm-commits] [llvm] r114599 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/bit-test-shift.ll
In-Reply-To: <4C9AF3B9.1010808@free.fr>
References: <20100922225822.3B7E22A6C12C@llvm.org> <4C9AF3B9.1010808@free.fr>
Message-ID: <4C9AF525.9070506@mxc.ca>

Duncan Sands wrote:
> Hi Owen,
>
>> A select between a constant and zero, when fed by a bit test, can be efficiently
>> lowered using a series of shifts.
>> Fixes<rdar://problem/8285015>.
>
> can't you do this at the IR level?  At the IR level, you can change
>
>     %s = select i1 %cond, i32 %a, i32 0
>
> into
>
>     %cond.1 = sext i1 %cond to i32
>     %s = and i32 %a, %cond.1
>
> which could be a win depending on where %cond comes from.

I would much rather we turned chains of expressions on i1 into a single 
statement, then taught the backend how to do efficient construction of 
the right values out of the select statement.

Nick

From jasonwkim at google.com  Thu Sep 23 01:48:51 2010
From: jasonwkim at google.com (Jason Kim)
Date: Wed, 22 Sep 2010 23:48:51 -0700
Subject: [llvm-commits] Initial cut of ARM MC ELF emitter (PATCH)
In-Reply-To: <1B431CFE-CD10-4DC9-8387-560EFADCAC67@apple.com>
References: <AANLkTimo35LOkR1DiFDv+QxUQp6GRCng-gq0GTV3L3ct@mail.gmail.com>
	<461E2CD0-5905-48E9-8730-AFF37C693B2A@apple.com>
	<AANLkTinCz5BrD7FhWXBMZ8k41qtruTNqK8ufGZPFKAe1@mail.gmail.com>
	<B5C095B7-001E-44EC-94DB-3CB68CE878A4@apple.com>
	<AANLkTinhymcEWgYPc1jhPCgTv2E+OpxzcivNVg9_ycQ-@mail.gmail.com>
	<AANLkTimR3GPR=MbGzxKqcyP4ZOdtqAW3ErXTpxTQY8+N@mail.gmail.com>
	<AANLkTimR+imcXYcD6FhB44Txe26OFFoxH4h3LYJ8B_89@mail.gmail.com>
	<1B431CFE-CD10-4DC9-8387-560EFADCAC67@apple.com>
Message-ID: <AANLkTikociYFnf6tgdp5ZH7bucgbsjO=7bY6Bjjj3hXU@mail.gmail.com>

Jim,

Thanks very much for the helpful comments.

Quick recap for Jim G:

All simple white space diffs have been quashed.
All non apropos comments made by me have been removed.
create(X86|ARM)MCStreamer have been "reverted" back to the clashing
static names.
Itemwise responses below:

Everyone:

This patch replaces the controversial arm-mc-elf-s01-r114621.patch I
sent to this
list earlier TODAY. It incorporates most of Jim G's suggestions (which
were originally for the
obsoleted arm-mc-elf-s01.patch4 sent earlier this week)

Patch applies cleanly to r114626, and make check-lit passes (yes
PR8199 is STILL not triggered :-).

Thank you.

-Jason

Notes-------------------

Towards eventual ARM/MC ELF emission
Its still mostly stub work so far.
Some cleanup in ARM Target Machine initialization - including
1. The ARM DataLayout member has been lifted upwards and initialized
directly via new method in ARMSubTarget
2. new ARMSubtarget::getDataLayout() method being called in ARMBaseTargetMachine


On Wed, Sep 22, 2010 at 6:48 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Index: lib/Target/X86/X86TargetMachine.cpp
> ===================================================================
> --- lib/Target/X86/X86TargetMachine.cpp (revision 114214)
> +++ lib/Target/X86/X86TargetMachine.cpp (working copy)
> @@ -39,11 +39,11 @@
> ?? }
> ?}
> -static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCContext &Ctx, TargetAsmBackend &TAB,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?raw_ostream &_OS,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCCodeEmitter *_Emitter,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool RelaxAll) {
> +static MCStreamer *createX86MCStreamer(const Target &T, const std::string
> &TT,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCContext &Ctx, TargetAsmBackend
> &TAB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? raw_ostream &_OS,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MCCodeEmitter *_Emitter,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool RelaxAll) {
>
> Why is this rename necessary? It's a static function, so there's no
> namespace collision with anything in another target.

When examining assembly (as I had to do for sanity checking), its
helpful to have matching names.


<snip>
> + ?case Triple::Win32:
> + ? ?return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
>
> ARM doesn't currently have any intention of supporting any of the Windows
> targets, so these should be omitted here, or possibly trigger an assert.

Done.  asserting.

<snip>
> ?? ? Subtarget(TT, FS, isThumb),
> ?? ? FrameInfo(Subtarget),
> ?? ? JITInfo(),
> - ? ?InstrItins(Subtarget.getInstrItineraryData()) {
> + ? ?InstrItins(Subtarget.getInstrItineraryData()),
> + ? ?DataLayout(TargetDescription),
>
> ?The TargetData is accessible from the TargetMachine instance via the
> getTargetData() accessor function. Is that not sufficient for what you're
> looking to accomplish?

I updated this portion of the code to better track what the how the
X86 initializes the DataLayout variable.


<snip>
>
> + ? ?ELFWriterInfo(*this)
>
> This creates an ELFWriter() even when the target doesn't need or want one.
> That doesn't seem right. I see X86 does the same thing, though. Doesn't seem
> right there, either, but perhaps I'm missing something and someone familiar
> with that area can comment.

Uhm, I claim this is beyond the scope of this one patch. How about we
let this one slide for now, for the sake of consistency? :-)

>
> <snip>
>
> Index: lib/Target/ARM/ARMELFWriterInfo.h
> ===================================================================
> --- lib/Target/ARM/ARMELFWriterInfo.h (revision 0)
> +++ lib/Target/ARM/ARMELFWriterInfo.h (revision 0)
> @@ -0,0 +1,66 @@
> +//===-- ARMELFWriterInfo.h - ELF Writer Info for ARM ------------*- C++
> -*-===//
> +//
> +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file implements ELF writer information for the ARM backend.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef ARM_ELF_WRITER_INFO_H
> +#define ARM_ELF_WRITER_INFO_H
> +
> +#include "llvm/Target/TargetELFWriterInfo.h"
> +
> +namespace llvm {
> +
> + ?class ARMELFWriterInfo : public TargetELFWriterInfo {
> +
> + ? ?// ELF Relocation types for ARM
> + ? ?// FIXME: TODO(jasonwkim): [2010/09/17 14:52:25 PDT (Friday)]
>
> FIXME's don't need name/date info. "svn annotate" does the trick for that
> information.

comment reverted for more apropos patch.

>
> + ? ?// Come up with a better way to orgnize the 100+ ARM reloc types.
> +
> + ? ?enum ARMRelocationType {
> + ? ?};
> +
> + ?public:
> + ? ?ARMELFWriterInfo(TargetMachine &TM);
> + ? ?virtual ~ARMELFWriterInfo();
> +
> + ? ?/// getRelocationType - Returns the target specific ELF Relocation
> type.
> + ? ?/// 'MachineRelTy' contains the object code independent relocation type
> + ? ?virtual unsigned getRelocationType(unsigned MachineRelTy) const;
> +
> + ? ?/// hasRelocationAddend - True if the target uses an addend in the
> + ? ?/// ELF relocation entry.
> + ? ?virtual bool hasRelocationAddend() const { return is64Bit ? true :
> false; }
>
> There's no 64-bit here. Should this always return 'false' for ARM? Probably
> shouldn't reference 64Bit in any case, I'd think.

Uhh, I am not sure yet about the addend. ARM arch manual does mention
it being allowed.
You are right about the is64bit. returns false for now.

>
> +
> + ? ?/// getDefaultAddendForRelTy - Gets the default addend value for a
> + ? ?/// relocation entry based on the target ELF relocation type.
> + ? ?virtual long int getDefaultAddendForRelTy(unsigned RelTy,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?long int Modifier = 0) const;
>
> +
> + ? ?/// isPCRelativeRel - True if the relocation type is pc relative
> + ? ?virtual bool isPCRelativeRel(unsigned RelTy) const;
> +
> + ? ?/// getJumpTableRelocationTy - Returns the machine relocation type used
> + ? ?/// to reference a jumptable.
> + ? ?virtual unsigned getAbsoluteLabelMachineRelTy() const;
>
> Advance warning: ARM does jump tables with custom handling. This may be an
> "interesting" bit.

Consider me warned :-)

-Jason
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From evan.cheng at apple.com  Thu Sep 23 01:51:55 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 06:51:55 -0000
Subject: [llvm-commits] [llvm] r114630 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100923065155.C6B682A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 01:51:55 2010
New Revision: 114630

URL: http://llvm.org/viewvc/llvm-project?rev=114630&view=rev
Log:
SDISel should not optimize a unconditional branch following a conditional branch
when the unconditional branch destination is the fallthrough block. The
canonicalization makes it easier to allow optimizations on DAGs to invert
conditional branches. The branch folding pass (and AnalyzeBranch) will clean up
the unnecessary unconditional branches later.

This is one of the patches leading up to disabling codegen prepare critical edge
splitting.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114630&r1=114629&r2=114630&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep 23 01:51:55 2010
@@ -1503,10 +1503,11 @@
                                MVT::Other, getControlRoot(), Cond,
                                DAG.getBasicBlock(CB.TrueBB));
 
-  // Insert the false branch.
-  if (CB.FalseBB != NextBlock)
-    BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
-                         DAG.getBasicBlock(CB.FalseBB));
+  // Insert the false branch. Do this even if it's a fall through branch,
+  // this makes it easier to do DAG optimizations which require inverting
+  // the branch condition.
+  BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
+                       DAG.getBasicBlock(CB.FalseBB));
 
   DAG.setRoot(BrCond);
 }



From evan.cheng at apple.com  Thu Sep 23 01:53:00 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 06:53:00 -0000
Subject: [llvm-commits] [llvm] r114631 -
	/llvm/trunk/lib/CodeGen/MachineSink.cpp
Message-ID: <20100923065300.DE5282A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 01:53:00 2010
New Revision: 114631

URL: http://llvm.org/viewvc/llvm-project?rev=114631&view=rev
Log:
Don't sink insert_subreg, subreg_to_reg, reg_sequence. They are meant to be
close to their sources to facilitate coalescing.

Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=114631&r1=114630&r2=114631&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Thu Sep 23 01:53:00 2010
@@ -281,7 +281,7 @@
   if (!CEBCandidates.insert(std::make_pair(From, To)))
     return true;
 
-  if (!(MI->isCopyLike() || MI->getDesc().isAsCheapAsAMove()))
+  if (!MI->isCopy() && !MI->getDesc().isAsCheapAsAMove())
     return true;
 
   // MI is cheap, we probably don't want to break the critical edge for it.
@@ -368,9 +368,18 @@
   return FromBB->SplitCriticalEdge(ToBB, this);
 }
 
+static bool AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) {
+  return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence();
+}
+
 /// SinkInstruction - Determine whether it is safe to sink the specified machine
 /// instruction out of its current block into a successor.
 bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
+  // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
+  // be close to the source to make it easier to coalesce.
+  if (AvoidsSinking(MI, MRI))
+    return false;
+
   // Check if it's safe to move the instruction.
   if (!MI->isSafeToMove(TII, AA, SawStore))
     return false;



From evan.cheng at apple.com  Thu Sep 23 01:54:40 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 06:54:40 -0000
Subject: [llvm-commits] [llvm] r114632 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20100923065440.DDACB2A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 01:54:40 2010
New Revision: 114632

URL: http://llvm.org/viewvc/llvm-project?rev=114632&view=rev
Log:
If there are multiple unconditional branches terminating a block, eliminate all
but the first one. Those will never be executed. There was logic to do this
but it was faulty.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114632&r1=114631&r2=114632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Sep 23 01:54:40 2010
@@ -275,13 +275,29 @@
 
   // Get the instruction before it if it is a terminator.
   MachineInstr *SecondLastInst = I;
+  unsigned SecondLastOpc = SecondLastInst->getOpcode();
+
+  // If AllowModify is true and the block ends with two or more unconditional
+  // branches, delete all but the first unconditional branch.
+  if (AllowModify && isUncondBranchOpcode(LastOpc)) {
+    while (isUncondBranchOpcode(SecondLastOpc)) {
+      LastInst->eraseFromParent();
+      LastInst = SecondLastInst;
+      LastOpc = LastInst->getOpcode();
+      if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
+        break;
+      else {
+        SecondLastInst = I;
+        SecondLastOpc = SecondLastInst->getOpcode();
+      }
+    }
+  }
 
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
     return true;
 
   // If the block ends with a B and a Bcc, handle it.
-  unsigned SecondLastOpc = SecondLastInst->getOpcode();
   if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
     TBB =  SecondLastInst->getOperand(0).getMBB();
     Cond.push_back(SecondLastInst->getOperand(1));



From evan.cheng at apple.com  Thu Sep 23 01:55:34 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 06:55:34 -0000
Subject: [llvm-commits] [llvm] r114633 - in /llvm/trunk:
 lib/Transforms/Scalar/CodeGenPrepare.cpp
 test/CodeGen/ARM/lsr-on-unrolled-loops.ll
 test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
 test/CodeGen/X86/2008-02-18-TailMergingBug.ll test/CodeGen/X86/lsr-reuse.ll
 test/CodeGen/X86/phi-immediate-factoring.ll
 test/CodeGen/X86/phys_subreg_coalesce-2.ll test/CodeGen/X86/postra-licm.ll
 test/CodeGen/X86/pr2659.ll test/CodeGen/X86/tail-opts.ll
 test/CodeGen/X86/tailcallfp2.ll
Message-ID: <20100923065534.C86FF2A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 01:55:34 2010
New Revision: 114633

URL: http://llvm.org/viewvc/llvm-project?rev=114633&view=rev
Log:
Disable codegen prepare critical edge splitting. Machine instruction passes now
break critical edges on demand.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
    llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
    llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
    llvm/trunk/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
    llvm/trunk/test/CodeGen/X86/lsr-reuse.ll
    llvm/trunk/test/CodeGen/X86/phi-immediate-factoring.ll
    llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll
    llvm/trunk/test/CodeGen/X86/postra-licm.ll
    llvm/trunk/test/CodeGen/X86/pr2659.ll
    llvm/trunk/test/CodeGen/X86/tail-opts.ll
    llvm/trunk/test/CodeGen/X86/tailcallfp2.ll

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Thu Sep 23 01:55:34 2010
@@ -31,6 +31,7 @@
 #include "llvm/Transforms/Utils/BuildLibCalls.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/Statistic.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/Support/CallSite.h"
 #include "llvm/Support/CommandLine.h"
@@ -42,10 +43,12 @@
 using namespace llvm;
 using namespace llvm::PatternMatch;
 
+STATISTIC(NumElim,  "Number of blocks eliminated");
+
 static cl::opt<bool>
 CriticalEdgeSplit("cgp-critical-edge-splitting",
                   cl::desc("Split critical edges during codegen prepare"),
-                  cl::init(true), cl::Hidden);
+                  cl::init(false), cl::Hidden);
 
 namespace {
   class CodeGenPrepare : public FunctionPass {
@@ -302,6 +305,7 @@
     PFI->removeEdge(ProfileInfo::getEdge(BB, DestBB));
   }
   BB->eraseFromParent();
+  ++NumElim;
 
   DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n");
 }

Modified: llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Thu Sep 23 01:55:34 2010
@@ -624,12 +624,12 @@
 bb24:                                             ; preds = %bb23
 
 ; LSR should use count-down iteration to avoid requiring the trip count
-; in a register, and it shouldn't require any reloads here.
+; in a register.
 
 ;      CHECK: @ %bb24
 ; CHECK-NEXT: @   in Loop: Header=BB1_1 Depth=1
-; CHECK-NEXT: sub{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1
-; CHECK-NEXT: bne.w
+; CHECK: subs [[REGISTER:(r[0-9]+)|(lr)]], #1
+; CHECK: bne.w
 
   %92 = icmp eq i32 %tmp81, %indvar78             ; <i1> [#uses=1]
   %indvar.next79 = add i32 %indvar78, 1           ; <i32> [#uses=1]

Modified: llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Thu Sep 23 01:55:34 2010
@@ -10,7 +10,7 @@
 define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind {
 ; CHECK: blx ___muldf3
 ; CHECK: blx ___muldf3
-; CHECK: beq LBB0_8
+; CHECK: beq LBB0_7
 ; CHECK: blx ___muldf3
 ; <label>:3
   switch i32 %1, label %4 [

Modified: llvm/trunk/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-18-TailMergingBug.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-02-18-TailMergingBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-02-18-TailMergingBug.ll Thu Sep 23 01:55:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 9
+; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 16
 ; PR1909
 
 @.str = internal constant [48 x i8] c"transformed bounds: (%.2f, %.2f), (%.2f, %.2f)\0A\00"		; <[48 x i8]*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lsr-reuse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lsr-reuse.ll Thu Sep 23 01:55:34 2010
@@ -389,7 +389,7 @@
 ; rdar://7657764
 
 ; CHECK: asd:
-; CHECK: BB9_5:
+; CHECK: BB9_4:
 ; CHECK-NEXT: addl  (%r{{[^,]*}},%rdi,4), %e
 ; CHECK-NEXT: incq  %rdi
 ; CHECK-NEXT: cmpq  %rdi, %r{{[^,]*}}
@@ -464,7 +464,7 @@
 
 ; And the one at %bb68, where we want to be sure to use superhero mode:
 
-; CHECK:      BB10_9:
+; CHECK:      BB10_7:
 ; CHECK-NEXT:   movaps  48(%r{{[^,]*}}), %xmm{{.*}}
 ; CHECK-NEXT:   mulps   %xmm{{.*}}, %xmm{{.*}}
 ; CHECK-NEXT:   movaps  32(%r{{[^,]*}}), %xmm{{.*}}
@@ -484,7 +484,6 @@
 ; CHECK-NEXT:   addq    $64, %r{{.*}}
 ; CHECK-NEXT:   addq    $64, %r{{.*}}
 ; CHECK-NEXT:   addq    $-16, %r{{.*}}
-; CHECK-NEXT: BB10_10:
 ; CHECK-NEXT:   cmpq    $15, %r{{.*}}
 ; CHECK-NEXT:   jg
 

Modified: llvm/trunk/test/CodeGen/X86/phi-immediate-factoring.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phi-immediate-factoring.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/phi-immediate-factoring.ll (original)
+++ llvm/trunk/test/CodeGen/X86/phi-immediate-factoring.ll Thu Sep 23 01:55:34 2010
@@ -1,5 +1,5 @@
+; RUN: llc < %s -march=x86 -stats |& grep {Number of blocks eliminated} | grep 6
 ; PR1296
-; RUN: llc < %s -march=x86 | grep {movl	\$1} | count 1
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "i686-apple-darwin8"

Modified: llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/phys_subreg_coalesce-2.ll Thu Sep 23 01:55:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep mov | count 5
+; RUN: llc < %s -march=x86 | grep mov | count 4
 ; PR2659
 
 define i32 @binomial(i32 %n, i32 %k) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/postra-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/postra-licm.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/postra-licm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/postra-licm.ll Thu Sep 23 01:55:34 2010
@@ -68,7 +68,7 @@
 
 bb23:                                             ; preds = %imix_test.exit
   unreachable
-; X86-32: %bb26.preheader.bb28_crit_edge
+; X86-32: %bb26.preheader
 ; X86-32: movl -16(%ebp),
 ; X86-32-NEXT: .align 4
 ; X86-32-NEXT: %bb28

Modified: llvm/trunk/test/CodeGen/X86/pr2659.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr2659.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr2659.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr2659.ll Thu Sep 23 01:55:34 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 4
 ; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s
 ; PR2659
 
@@ -14,10 +14,11 @@
   %cmp44 = icmp eq i32 %k, 0            ; <i1> [#uses=1]
   br i1 %cmp44, label %afterfor, label %forbody
 
-; CHECK: %forcond.preheader.forbody_crit_edge
+; CHECK: %forcond.preheader
 ; CHECK: movl $1
 ; CHECK-NOT: xorl
-; CHECK-NEXT: movl
+; CHECK-NOT: movl
+; CHECK-NEXT: je
 
 ifthen:         ; preds = %entry
   ret i32 0

Modified: llvm/trunk/test/CodeGen/X86/tail-opts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-opts.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-opts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-opts.ll Thu Sep 23 01:55:34 2010
@@ -153,19 +153,16 @@
 ; an unconditional jump to complete a two-way conditional branch.
 
 ; CHECK: c_expand_expr_stmt:
-; CHECK:        jmp .LBB3_7
-; CHECK-NEXT: .LBB3_12:
+; CHECK:        jmp .LBB3_11
+; CHECK-NEXT: .LBB3_9:
 ; CHECK-NEXT:   movq 8(%rax), %rax
+; CHECK-NEXT:   xorb %dl, %dl
 ; CHECK-NEXT:   movb 16(%rax), %al
 ; CHECK-NEXT:   cmpb $16, %al
-; CHECK-NEXT:   je .LBB3_6
+; CHECK-NEXT:   je .LBB3_11
 ; CHECK-NEXT:   cmpb $23, %al
-; CHECK-NEXT:   je .LBB3_6
-; CHECK-NEXT:   jmp .LBB3_15
-; CHECK-NEXT: .LBB3_14:
-; CHECK-NEXT:   cmpb $23, %bl
-; CHECK-NEXT:   jne .LBB3_15
-; CHECK-NEXT: .LBB3_15:
+; CHECK-NEXT:   jne .LBB3_14
+; CHECK-NEXT: .LBB3_11:
 
 %0 = type { %struct.rtx_def* }
 %struct.lang_decl = type opaque

Modified: llvm/trunk/test/CodeGen/X86/tailcallfp2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcallfp2.ll?rev=114633&r1=114632&r2=114633&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tailcallfp2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tailcallfp2.ll Thu Sep 23 01:55:34 2010
@@ -1,8 +1,9 @@
-; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%edx}
+; RUN: llc < %s -march=x86 -tailcallopt | FileCheck %s
 
 declare i32 @putchar(i32)
 
 define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind {
+; CHECK: checktail:
         %tmp1 = icmp sgt i32 %x, 0
         br i1 %tmp1, label %if-then, label %if-else
 
@@ -10,6 +11,7 @@
         %fun_ptr = bitcast i32* %f to i32(i32, i32*, i32)* 
         %arg1    = add i32 %x, -1
         call i32 @putchar(i32 90)       
+; CHECK: jmpl *%e{{.*}}
         %res = tail call fastcc i32 %fun_ptr( i32 %arg1, i32 * %f, i32 %g)
         ret i32 %res
 



From clattner at apple.com  Thu Sep 23 02:12:33 2010
From: clattner at apple.com (Chris Lattner)
Date: Thu, 23 Sep 2010 00:12:33 -0700
Subject: [llvm-commits] [llvm] r114599 - in /llvm/trunk:
	lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	test/CodeGen/X86/bit-test-shift.ll
In-Reply-To: <4C9AF525.9070506@mxc.ca>
References: <20100922225822.3B7E22A6C12C@llvm.org> <4C9AF3B9.1010808@free.fr>
	<4C9AF525.9070506@mxc.ca>
Message-ID: <20B17572-5F3C-4040-BF1D-593E8C43A634@apple.com>


On Sep 22, 2010, at 11:35 PM, Nick Lewycky wrote:

> Duncan Sands wrote:
>> Hi Owen,
>> 
>>> A select between a constant and zero, when fed by a bit test, can be efficiently
>>> lowered using a series of shifts.
>>> Fixes<rdar://problem/8285015>.
>> 
>> can't you do this at the IR level?  At the IR level, you can change
>> 
>>    %s = select i1 %cond, i32 %a, i32 0
>> 
>> into
>> 
>>    %cond.1 = sext i1 %cond to i32
>>    %s = and i32 %a, %cond.1
>> 
>> which could be a win depending on where %cond comes from.
> 
> I would much rather we turned chains of expressions on i1 into a single 
> statement, then taught the backend how to do efficient construction of 
> the right values out of the select statement.

Yes, I agree.  The canonical form at the IR level should be a select.

-Chris

From evan.cheng at apple.com  Thu Sep 23 02:18:35 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 07:18:35 -0000
Subject: [llvm-commits] [llvm] r114634 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100923071835.6980E2A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 02:18:35 2010
New Revision: 114634

URL: http://llvm.org/viewvc/llvm-project?rev=114634&view=rev
Log:
Follow up to r114630. Do not optimize away unconditional branch following a conditional one.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114634&r1=114633&r2=114634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep 23 02:18:35 2010
@@ -1617,9 +1617,8 @@
                                 MVT::Other, CopyTo, RangeCmp,
                                 DAG.getBasicBlock(B.Default));
 
-  if (MBB != NextBlock)
-    BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
-                          DAG.getBasicBlock(MBB));
+  BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
+                        DAG.getBasicBlock(MBB));
 
   DAG.setRoot(BrRange);
 }
@@ -1672,9 +1671,8 @@
   if (++BBI != FuncInfo.MF->end())
     NextBlock = BBI;
 
-  if (NextMBB != NextBlock)
-    BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
-                        DAG.getBasicBlock(NextMBB));
+  BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
+                      DAG.getBasicBlock(NextMBB));
 
   DAG.setRoot(BrAnd);
 }



From wdietz2 at illinois.edu  Thu Sep 23 03:32:14 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 23 Sep 2010 08:32:14 -0000
Subject: [llvm-commits] [poolalloc] r114635 - in /poolalloc/trunk/test/dsa:
 local/extern.ll local/extern2.ll local/extern3.ll td/extern.ll
 td/extern2.ll td/extern3.ll td/extern_global.ll
Message-ID: <20100923083214.D330E2A6C12C@llvm.org>

Author: wdietz2
Date: Thu Sep 23 03:32:14 2010
New Revision: 114635

URL: http://llvm.org/viewvc/llvm-project?rev=114635&view=rev
Log:
Added test case for external (and non-external) globals and their completeness.
Also moved extern*.ll tests to test/dsa/td since they're not 'local' tests.

Added:
    poolalloc/trunk/test/dsa/td/extern.ll
      - copied unchanged from r114626, poolalloc/trunk/test/dsa/local/extern.ll
    poolalloc/trunk/test/dsa/td/extern2.ll
      - copied unchanged from r114626, poolalloc/trunk/test/dsa/local/extern2.ll
    poolalloc/trunk/test/dsa/td/extern3.ll
      - copied unchanged from r114626, poolalloc/trunk/test/dsa/local/extern3.ll
    poolalloc/trunk/test/dsa/td/extern_global.ll
Removed:
    poolalloc/trunk/test/dsa/local/extern.ll
    poolalloc/trunk/test/dsa/local/extern2.ll
    poolalloc/trunk/test/dsa/local/extern3.ll

Removed: poolalloc/trunk/test/dsa/local/extern.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern.ll?rev=114634&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern.ll (original)
+++ poolalloc/trunk/test/dsa/local/extern.ll (removed)
@@ -1,63 +0,0 @@
-;Test that pointers from external functions are marked incomplete properly
-;Tests on all the DSA passes for three simple cases:
-;--calling an allocator wrapper (shouldn't be incomplete in interprocedural)
-;--calling a undefined (external) function.  Should be incomplete at least
-;  once the interprocedural passes run.
-;--calling a function that calls an undefined (external) function.
-;  Should be incomplete, tests very basic tracking.
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrViaExtern+I"
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-define i32* @getPointerViaExtern() nounwind {
-entry:
-  %0 = tail call i32* (...)* @getPointerExtern() nounwind ; <i32*> [#uses=1]
-  ret i32* %0
-}
-
-declare i32* @getPointerExtern(...)
-
-define internal noalias i32* @getPointer() nounwind {
-entry:
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
-  %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  ret i32* %1
-}
-
-declare noalias i8* @malloc(i64) nounwind
-
-define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-entry:
-  %ptr = tail call i32* ()* @getPointer() nounwind
-  %ptrExtern = tail call i32* (...)* @getPointerExtern() nounwind
-  %ptrViaExtern = tail call i32* ()* @getPointerViaExtern() nounwind
-  %val1 = load i32* %ptr, align 4
-  %val2 = load i32* %ptrExtern, align 4
-  %val3 = load i32* %ptrViaExtern, align 4
-  %sum_partial = add i32 %val1, %val2
-  %sum = add i32 %sum_partial, %val3
-  ret i32 %sum
-}

Removed: poolalloc/trunk/test/dsa/local/extern2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern2.ll?rev=114634&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern2.ll (original)
+++ poolalloc/trunk/test/dsa/local/extern2.ll (removed)
@@ -1,38 +0,0 @@
-;Here we get a pointer from an external function and pass it to a callee.
-;We then test that the flags on that pointer are set appropriately.
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "takesPointer:ptr+I"
-
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "takesPointer:ptr+I"
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+I"
-
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "takesPointer:ptr+I"
-
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "takesPointer:ptr+I"
-
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "takesPointer:ptr+I"
-
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-define i32 @takesPointer(i32* nocapture %ptr) nounwind readonly {
-entry:
-  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
-  ret i32 %0
-}
-
-define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-entry:
-  %ptr = tail call i32* (...)* @getPointerExtern() nounwind
-  %0 = tail call i32 @takesPointer(i32* %ptr) nounwind
-  ret i32 %0
-}
-
-declare i32* @getPointerExtern(...)

Removed: poolalloc/trunk/test/dsa/local/extern3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/extern3.ll?rev=114634&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/extern3.ll (original)
+++ poolalloc/trunk/test/dsa/local/extern3.ll (removed)
@@ -1,88 +0,0 @@
-; ModuleID = 'extern.c'
-;This tests the various cases that could involve incompleteness due
-;to external code, and additionally verifies these flags are NOT set
-;on internal functions.
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-declare i32* @getPointerExtern()
-declare void @takesPointerExtern(i32*)
-declare noalias i8* @malloc(i64) nounwind
-declare void @free(i8*) nounwind
-
-;This should be marked incomplete and external due to the
-;unification-based nature of DSA.
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointer:ptr+I"
-define i32* @getPointer() nounwind {
-entry:
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
-  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  ret i32* %ptr
-}
-
-;This should be marked incomplete and external due to the
-;unification-based nature of DSA.
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+I"
-define i32 @takesPointer(i32* %ptr) nounwind {
-entry:
-  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
-  ret i32 %0
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointerInternal:ptr-I"
-define internal i32* @getPointerInternal() nounwind {
-entry:
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
-  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  ret i32* %ptr
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointerInternal:ptr-I"
-define internal i32 @takesPointerInternal(i32* %ptr) nounwind {
-entry:
-  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
-  ret i32 %0
-}
-
-define i32 @main(i32 %argc, i8** %argv) nounwind {
-entry:
-  call void @checkExterns() nounwind
-  call void @checkExternals() nounwind
-  call void @checkInternals() nounwind
-  ret i32 0
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:get+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:take+I"
-define void @checkExterns() nounwind {
-  %get = tail call i32* ()* @getPointerExtern() nounwind ; <i32*> [#uses=0]
-  %1 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
-  %take = bitcast i8* %1 to i32*                     ; <i32*> [#uses=1]
-  tail call void @takesPointerExtern(i32* %take) nounwind
-  tail call void @free(i8* %1) nounwind
-  ret void
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take+I"
-define void @checkExternals() nounwind {
-entry:
-  %get = tail call i32* ()* @getPointer() nounwind ; <i32*> [#uses=0]
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
-  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  tail call i32 @takesPointer(i32* %take) nounwind
-  tail call void @free(i8* %0) nounwind
-  ret void
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:get-I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:take-I"
-define void @checkInternals() nounwind {
-entry:
-  %get = tail call i32* ()* @getPointerInternal() nounwind ; <i32*> [#uses=0]
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
-  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  tail call i32 @takesPointerInternal(i32* %take) nounwind
-  tail call void @free(i8* %0) nounwind
-  ret void
-}

Added: poolalloc/trunk/test/dsa/td/extern_global.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern_global.ll?rev=114635&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern_global.ll (added)
+++ poolalloc/trunk/test/dsa/td/extern_global.ll Thu Sep 23 03:32:14 2010
@@ -0,0 +1,48 @@
+; ModuleID = 'extern_global.c'
+;This tests how DSA handles external globals and their completeness in TD.
+
+; Externally visible globals should be incomplete
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalInt+I
+; Externally visible global and what it points to should be incomplete
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr+I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr:0+I
+; Externally visible global and what it points to should be incomplete,
+; this time with a struct and point to some stack memory...
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers+I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8+I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8:8+I
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=globalStructWithPointers:8,globalStructWithPointers:8:8
+; Globals that aren't marked 'external' shouldn't be incomplete
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal-I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags internalGlobal-I
+; Check some edges of the graph
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=normalGlobal:0,globalIntPtr
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=internalGlobal:0,normalGlobal
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.myStruct = type { i32, %struct.myStruct* }
+
+ at globalStructWithPointers = external global %struct.myStruct
+ at globalIntPtr = external global i32*
+ at globalInt = external global i32
+ at normalGlobal = global i32** null
+ at internalGlobal = internal global i32*** null
+
+define i32 @main() nounwind {
+entry:
+;Create the struct and initialize it
+  %s = alloca %struct.myStruct, align 8           ; <%struct.myStruct*> [#uses=1]
+  %0 = getelementptr inbounds %struct.myStruct* %s, i32 0, i32 1 ; <%struct.myStruct**> [#uses=1]
+  store %struct.myStruct* %s, %struct.myStruct** %0, align 8
+  %1 = getelementptr inbounds %struct.myStruct* %s, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32 100, i32* %1, align 8
+;Store the struct into the global
+  store %struct.myStruct* %s, %struct.myStruct** getelementptr inbounds (%struct.myStruct* @globalStructWithPointers, i64 0, i32 1), align 8
+;Play around with the rest of the globals
+  store i32* @globalInt, i32** @globalIntPtr, align 8
+  store i32** @globalIntPtr, i32*** @normalGlobal, align 8
+  store i32*** @normalGlobal, i32**** @internalGlobal, align 8
+  ret i32 undef
+}



From rdivacky at freebsd.org  Thu Sep 23 09:10:34 2010
From: rdivacky at freebsd.org (Roman Divacky)
Date: Thu, 23 Sep 2010 16:10:34 +0200
Subject: [llvm-commits] [patch][RFC] Correctly produce R_X86_64_32 or
	R_X86_64_32S
In-Reply-To: <AANLkTi=qf+oWGf4tpGR14r9XYKMsQ7Wb0Jd5gZnwBo8p@mail.gmail.com>
References: <AANLkTikmXne4afVBc_zohprP=1UWZEgJufrvCw-=n1-k@mail.gmail.com>
	<AANLkTi=ABAVxcn7mdkQfiLLVHEveH237gtO_db2ArYdd@mail.gmail.com>
	<AANLkTi=qf+oWGf4tpGR14r9XYKMsQ7Wb0Jd5gZnwBo8p@mail.gmail.com>
Message-ID: <20100923141034.GA80287@freebsd.org>

On Wed, Sep 22, 2010 at 11:33:38AM -0400, Rafael Espindola wrote:
> On 21 September 2010 20:29, Rafael Espindola <espindola at google.com> wrote:
> > The attached patch survived a bit more testing :-)
> 
> The patch just survived a opt bootstrap on Darwin and a debug
> bootstrap is on stage3.

fwiw - I havent observed any ill effects with this patch + it fixes
all signed/unsigned reloc mismatches I was having when linking
FreeBSD kenrel.

roman

From rafael.espindola at gmail.com  Thu Sep 23 09:14:56 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Sep 2010 14:14:56 -0000
Subject: [llvm-commits] [llvm] r114639 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20100923141456.5B3C62A6C12C@llvm.org>

Author: rafael
Date: Thu Sep 23 09:14:56 2010
New Revision: 114639

URL: http://llvm.org/viewvc/llvm-project?rev=114639&view=rev
Log:
Fix the FIXME.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114639&r1=114638&r2=114639&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 23 09:14:56 2010
@@ -856,7 +856,7 @@
          ie = Asm.end(); it != ie; ++it) {
     const MCSectionELF &Section =
       static_cast<const MCSectionELF&>(it->getSection());
-    // FIXME: We could merge prefixes like in .text and .text.rela.
+    // FIXME: We could merge suffixes like in .text and .rela.text.
 
     // Remember the index into the string table so we can write it
     // into the sh_name field of the section header table.



From dgregor at apple.com  Thu Sep 23 09:19:21 2010
From: dgregor at apple.com (Douglas Gregor)
Date: Thu, 23 Sep 2010 14:19:21 -0000
Subject: [llvm-commits] [llvm] r114640 - /llvm/trunk/CMakeLists.txt
Message-ID: <20100923141921.C1F622A6C12C@llvm.org>

Author: dgregor
Date: Thu Sep 23 09:19:21 2010
New Revision: 114640

URL: http://llvm.org/viewvc/llvm-project?rev=114640&view=rev
Log:
Bump LLVM in CMake makefiles to 2.9

Modified:
    llvm/trunk/CMakeLists.txt

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=114640&r1=114639&r2=114640&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Thu Sep 23 09:19:21 2010
@@ -10,7 +10,7 @@
   "${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules"
   )
 
-set(PACKAGE_VERSION "2.8")
+set(PACKAGE_VERSION "2.9")
 include(VersionFromVCS)
 add_version_info_from_vcs(PACKAGE_VERSION)
 



From daniel at zuster.org  Thu Sep 23 09:57:17 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 23 Sep 2010 14:57:17 -0000
Subject: [llvm-commits] [zorg] r114642 -
	/zorg/trunk/buildbot/osuosl/master/config/slaves.py
Message-ID: <20100923145717.C46852A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 09:57:17 2010
New Revision: 114642

URL: http://llvm.org/viewvc/llvm-project?rev=114642&view=rev
Log:
Add a new build slave

Modified:
    zorg/trunk/buildbot/osuosl/master/config/slaves.py

Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=114642&r1=114641&r2=114642&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Thu Sep 23 09:57:17 2010
@@ -123,6 +123,9 @@
         # Debian, P4 2.8GHz, 1GB mem
         create_slave("balint1", properties={'jobs' : 1}, max_builds=1),
 
+        # Pentium Dual CPU T3400 @ 2.1GHz
+        create_slave("dumitrescu1", properties={'jobs' : 2}, max_builds=1),
+
         # Defunct.
         #create_slave("osu2", properties={'jobs' : 4}, max_builds=2),
         #create_slave("andrew1"),



From daniel at zuster.org  Thu Sep 23 09:57:45 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 23 Sep 2010 14:57:45 -0000
Subject: [llvm-commits] [zorg] r114643 -
	/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
Message-ID: <20100923145745.467D82A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 09:57:45 2010
New Revision: 114643

URL: http://llvm.org/viewvc/llvm-project?rev=114643&view=rev
Log:
Tweak default cmake path.

Modified:
    zorg/trunk/zorg/buildbot/builders/ClangBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=114643&r1=114642&r2=114643&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Thu Sep 23 09:57:45 2010
@@ -249,8 +249,7 @@
 
     return f
 
-def getClangMSVCBuildFactory(update=True, clean=True, vcDrive='c', jobs=1,
-                             cmake=r"c:\Program Files\CMake 2.6\bin\cmake"):
+def getClangMSVCBuildFactory(update=True, clean=True, vcDrive='c', jobs=1, cmake=r"cmake"):
     f = buildbot.process.factory.BuildFactory()
 
     if update:



From daniel at zuster.org  Thu Sep 23 09:58:16 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 23 Sep 2010 14:58:16 -0000
Subject: [llvm-commits] [zorg] r114644 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100923145816.97E0B2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 09:58:16 2010
New Revision: 114644

URL: http://llvm.org/viewvc/llvm-project?rev=114644&view=rev
Log:
Fix import and a build dir name.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114644&r1=114643&r2=114644&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Sep 23 09:58:16 2010
@@ -85,10 +85,10 @@
         {'name' : "llvm-x86_64-linux-checks",
         'slavenames':["gcc10"],
         'builddir':"llvm-x86_64-linux-checks",
-        'factory':LLVMBuilder.getLLVMGCCBuildFactory("x86_64-pc-linux-gnu",
-                                                     stage1_config='Release+Asserts+Checks',
-                                                     stage2_config='Release+Asserts+Checks',
-                                                     extra_configure_args=['--disable-multilib'])},
+        'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory("x86_64-pc-linux-gnu",
+                                                        stage1_config='Release+Asserts+Checks',
+                                                        stage2_config='Release+Asserts+Checks',
+                                                        extra_configure_args=['--disable-multilib'])},
         {'name' : "llvm-gcc-i386-linux-selfhost",
          'slavenames':["gcc11"],
          'builddir':"llvm-gcc-i386-linux-selfhost",
@@ -476,7 +476,7 @@
 
         {'name'      : "llvm-gcc-native-mingw32-win7",
          'slavenames': [ "kistanova3" ],
-         'builddir'  : "llvm-gcc-native-mingw32",
+         'builddir'  : "llvm-gcc-native-mingw32-win7",
          'factory'   : ScriptedBuilder.getScriptedBuildFactory(
                        source_code  = [SVN(name='svn-llvm',
                                            mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/',



From aggarwa4 at illinois.edu  Thu Sep 23 10:06:32 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 15:06:32 -0000
Subject: [llvm-commits] [poolalloc] r114645 - in
 /poolalloc/trunk/test/dsa/local: bitfields1.c bitfields2.c
Message-ID: <20100923150632.E41302A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 10:06:32 2010
New Revision: 114645

URL: http://llvm.org/viewvc/llvm-project?rev=114645&view=rev
Log:
Added run lines

Modified:
    poolalloc/trunk/test/dsa/local/bitfields1.c
    poolalloc/trunk/test/dsa/local/bitfields2.c

Modified: poolalloc/trunk/test/dsa/local/bitfields1.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields1.c?rev=114645&r1=114644&r2=114645&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields1.c (original)
+++ poolalloc/trunk/test/dsa/local/bitfields1.c Thu Sep 23 10:06:32 2010
@@ -1,4 +1,9 @@
+//--Make sure we can run DSA on it! 
+//RUN: llvm-gcc %s -c --emit-llvm -o - |  \
+//RUN: dsaopt -dsa-bu -dsa-td -disable-output
+
 #include <stdio.h>
+#include <stdlib.h>
 
 typedef union {
         struct {

Modified: poolalloc/trunk/test/dsa/local/bitfields2.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields2.c?rev=114645&r1=114644&r2=114645&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields2.c (original)
+++ poolalloc/trunk/test/dsa/local/bitfields2.c Thu Sep 23 10:06:32 2010
@@ -1,4 +1,9 @@
+//--Make sure we can run DSA on it! 
+//RUN: llvm-gcc %s -c --emit-llvm -o - |  \
+//RUN: dsaopt -dsa-bu -dsa-td -disable-output
+
 #include <stdio.h>
+#include <stdlib.h>
 
 typedef union {
 	struct {



From aggarwa4 at illinois.edu  Thu Sep 23 10:06:52 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 15:06:52 -0000
Subject: [llvm-commits] [poolalloc] r114646 - in
 /poolalloc/trunk/test/dsa/local: bitfields3.c bitfields3.ll
Message-ID: <20100923150652.9CF302A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 10:06:52 2010
New Revision: 114646

URL: http://llvm.org/viewvc/llvm-project?rev=114646&view=rev
Log:
Last test for bit fields

Added:
    poolalloc/trunk/test/dsa/local/bitfields3.c
    poolalloc/trunk/test/dsa/local/bitfields3.ll

Added: poolalloc/trunk/test/dsa/local/bitfields3.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields3.c?rev=114646&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields3.c (added)
+++ poolalloc/trunk/test/dsa/local/bitfields3.c Thu Sep 23 10:06:52 2010
@@ -0,0 +1,26 @@
+//--Make sure we can run DSA on it! 
+//RUN: llvm-gcc %s -c --emit-llvm -o - |  \
+//RUN: dsaopt -dsa-bu -dsa-td -disable-output
+
+#include <stdio.h>
+
+struct taxonomy {
+	unsigned kingdom: 2;
+	unsigned phylum: 4;
+	unsigned genus: 12;
+};
+
+int main()
+{
+	struct taxonomy t = {0, 0, 21};
+	t.kingdom = 1;
+	t.phylum = 7;
+	printf("sizeof(struct taxonomy): %d bytes\n",sizeof(struct taxonomy));
+	printf("taxonomy: 0x%x\n",t);
+	printf("kingdom: %d\n",t.kingdom);
+	printf("phylum: %d\n",t.phylum);
+	printf("genus: %d\n",t.genus);
+	
+	return 0;
+}
+

Added: poolalloc/trunk/test/dsa/local/bitfields3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/bitfields3.ll?rev=114646&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/bitfields3.ll (added)
+++ poolalloc/trunk/test/dsa/local/bitfields3.ll Thu Sep 23 10:06:52 2010
@@ -0,0 +1,76 @@
+; example with a packed struct
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:t,0:i32
+
+; ModuleID = 'bitfields3.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%0 = type { i8, i8, i8, i8 }
+%1 = type { i64 }
+%struct.taxonomy = type <{ i32 }>
+
+ at C.0.1944 = private constant %0 { i8 64, i8 5, i8 0, i8 0 }, align 4 ; <%0*> [#uses=1]
+ at .str = private constant [35 x i8] c"sizeof(struct taxonomy): %d bytes\0A\00", align 8 ; <[35 x i8]*> [#uses=1]
+ at .str1 = private constant [16 x i8] c"taxonomy: 0x%x\0A\00", align 1 ; <[16 x i8]*> [#uses=1]
+ at .str2 = private constant [13 x i8] c"kingdom: %d\0A\00", align 1 ; <[13 x i8]*> [#uses=1]
+ at .str3 = private constant [12 x i8] c"phylum: %d\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
+ at .str4 = private constant [11 x i8] c"genus: %d\0A\00", align 1 ; <[11 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32                            ; <i32*> [#uses=2]
+  %0 = alloca i32                                 ; <i32*> [#uses=2]
+  %t = alloca %struct.taxonomy, align 4           ; <%struct.taxonomy*> [#uses=7]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  %1 = getelementptr inbounds %struct.taxonomy* %t, i32 0, i32 0 ; <i32*> [#uses=1]
+  %2 = load i32* bitcast (%0* @C.0.1944 to i32*), align 4 ; <i32> [#uses=1]
+  store i32 %2, i32* %1, align 4
+  %3 = getelementptr inbounds %struct.taxonomy* %t, i32 0, i32 0 ; <i32*> [#uses=2]
+  %4 = load i32* %3, align 1                      ; <i32> [#uses=1]
+  %5 = and i32 %4, -4                             ; <i32> [#uses=1]
+  %6 = or i32 %5, 1                               ; <i32> [#uses=1]
+  store i32 %6, i32* %3, align 1
+  %7 = getelementptr inbounds %struct.taxonomy* %t, i32 0, i32 0 ; <i32*> [#uses=2]
+  %8 = load i32* %7, align 1                      ; <i32> [#uses=1]
+  %9 = and i32 %8, -61                            ; <i32> [#uses=1]
+  %10 = or i32 %9, 28                             ; <i32> [#uses=1]
+  store i32 %10, i32* %7, align 1
+  %11 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([35 x i8]* @.str, i64 0, i64 0), i64 4) nounwind ; <i32> [#uses=0]
+  %12 = bitcast %struct.taxonomy* %t to %1*       ; <%1*> [#uses=1]
+  %elt = getelementptr inbounds %1* %12, i32 0, i32 0 ; <i64*> [#uses=1]
+  %13 = bitcast i64* %elt to i32*                 ; <i32*> [#uses=1]
+  %14 = load i32* %13                             ; <i32> [#uses=1]
+  %15 = zext i32 %14 to i64                       ; <i64> [#uses=1]
+  %16 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([16 x i8]* @.str1, i64 0, i64 0), i64 %15) nounwind ; <i32> [#uses=0]
+  %17 = getelementptr inbounds %struct.taxonomy* %t, i32 0, i32 0 ; <i32*> [#uses=1]
+  %18 = load i32* %17, align 1                    ; <i32> [#uses=1]
+  %19 = shl i32 %18, 30                           ; <i32> [#uses=1]
+  %20 = lshr i32 %19, 30                          ; <i32> [#uses=1]
+  %21 = trunc i32 %20 to i2                       ; <i2> [#uses=1]
+  %22 = zext i2 %21 to i32                        ; <i32> [#uses=1]
+  %23 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([13 x i8]* @.str2, i64 0, i64 0), i32 %22) nounwind ; <i32> [#uses=0]
+  %24 = getelementptr inbounds %struct.taxonomy* %t, i32 0, i32 0 ; <i32*> [#uses=1]
+  %25 = load i32* %24, align 1                    ; <i32> [#uses=1]
+  %26 = shl i32 %25, 26                           ; <i32> [#uses=1]
+  %27 = lshr i32 %26, 28                          ; <i32> [#uses=1]
+  %28 = trunc i32 %27 to i4                       ; <i4> [#uses=1]
+  %29 = zext i4 %28 to i32                        ; <i32> [#uses=1]
+  %30 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([12 x i8]* @.str3, i64 0, i64 0), i32 %29) nounwind ; <i32> [#uses=0]
+  %31 = getelementptr inbounds %struct.taxonomy* %t, i32 0, i32 0 ; <i32*> [#uses=1]
+  %32 = load i32* %31, align 1                    ; <i32> [#uses=1]
+  %33 = shl i32 %32, 14                           ; <i32> [#uses=1]
+  %34 = lshr i32 %33, 20                          ; <i32> [#uses=1]
+  %35 = trunc i32 %34 to i12                      ; <i12> [#uses=1]
+  %36 = zext i12 %35 to i32                       ; <i32> [#uses=1]
+  %37 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([11 x i8]* @.str4, i64 0, i64 0), i32 %36) nounwind ; <i32> [#uses=0]
+  store i32 0, i32* %0, align 4
+  %38 = load i32* %0, align 4                     ; <i32> [#uses=1]
+  store i32 %38, i32* %retval, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32* %retval                    ; <i32> [#uses=1]
+  ret i32 %retval1
+}
+
+declare i32 @printf(i8* noalias, ...) nounwind



From aggarwa4 at illinois.edu  Thu Sep 23 10:20:59 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 15:20:59 -0000
Subject: [llvm-commits] [poolalloc] r114648 - in
 /poolalloc/trunk/test/dsa/local: array_in_struct.ll array_of_struct.ll
Message-ID: <20100923152059.B79852A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 10:20:59 2010
New Revision: 114648

URL: http://llvm.org/viewvc/llvm-project?rev=114648&view=rev
Log:
Test cases for arrays/struct combinations

Added:
    poolalloc/trunk/test/dsa/local/array_in_struct.ll
    poolalloc/trunk/test/dsa/local/array_of_struct.ll

Added: poolalloc/trunk/test/dsa/local/array_in_struct.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/array_in_struct.ll?rev=114648&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/array_in_struct.ll (added)
+++ poolalloc/trunk/test/dsa/local/array_in_struct.ll Thu Sep 23 10:20:59 2010
@@ -0,0 +1,47 @@
+; An example with a struct with an array. The node for the struct must be folded
+; if we access the array. 
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=test1:arr,FoldedVOIDArray
+
+; ModuleID = 'test1.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.sType = type { i32, [10 x i32], i32 }
+
+ at .str = private constant [4 x i8] c"%d\0A\00", align 1 ; <[4 x i8]*> [#uses=1]
+
+define void @test1() nounwind {
+entry:
+  %arr = alloca %struct.sType                     ; <%struct.sType*> [#uses=4]
+  %z = alloca i32                                 ; <i32*> [#uses=2]
+  %t = alloca i32                                 ; <i32*> [#uses=1]
+  %r = alloca i32                                 ; <i32*> [#uses=1]
+  %r1 = alloca i32                                ; <i32*> [#uses=1]
+  %r2 = alloca float                              ; <float*> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  %0 = call i32 (i8*, ...)* @scanf(i8* noalias getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %z) nounwind ; <i32> [#uses=0]
+  %1 = load i32* %z, align 4                      ; <i32> [#uses=1]
+  %2 = getelementptr inbounds %struct.sType* %arr, i32 0, i32 1 ; <[10 x i32]*> [#uses=1]
+  %3 = sext i32 %1 to i64                         ; <i64> [#uses=1]
+  %4 = getelementptr inbounds [10 x i32]* %2, i64 0, i64 %3 ; <i32*> [#uses=1]
+  %5 = load i32* %4, align 4                      ; <i32> [#uses=1]
+  store i32 %5, i32* %t, align 4
+  %6 = getelementptr inbounds %struct.sType* %arr, i32 0, i32 2 ; <i32*> [#uses=1]
+  %7 = load i32* %6, align 4                      ; <i32> [#uses=1]
+  store i32 %7, i32* %r, align 4
+  %8 = getelementptr inbounds %struct.sType* %arr, i32 0, i32 1 ; <[10 x i32]*> [#uses=1]
+  %9 = getelementptr inbounds [10 x i32]* %8, i64 0, i64 5 ; <i32*> [#uses=1]
+  %10 = load i32* %9, align 4                     ; <i32> [#uses=1]
+  store i32 %10, i32* %r1, align 4
+  %11 = getelementptr inbounds %struct.sType* %arr, i32 0, i32 0 ; <i32*> [#uses=1]
+  %12 = load i32* %11, align 4                    ; <i32> [#uses=1]
+  %13 = sitofp i32 %12 to float                   ; <float> [#uses=1]
+  store float %13, float* %r2, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+declare i32 @scanf(i8* noalias, ...) nounwind

Added: poolalloc/trunk/test/dsa/local/array_of_struct.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/array_of_struct.ll?rev=114648&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/array_of_struct.ll (added)
+++ poolalloc/trunk/test/dsa/local/array_of_struct.ll Thu Sep 23 10:20:59 2010
@@ -0,0 +1,35 @@
+; An example with an array of structs. The node for the array must 
+; be folded modulo the size of the struct element
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=test2:arr,0:i32::4:i32Array
+
+; ModuleID = 'test2.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.sType = type { i32, i32 }
+
+define void @test2() nounwind {
+entry:
+  %arr = alloca [10 x %struct.sType]              ; <[10 x %struct.sType]*> [#uses=2]
+  %z = alloca i32                                 ; <i32*> [#uses=2]
+  %t = alloca i32                                 ; <i32*> [#uses=1]
+  %t1 = alloca i32                                ; <i32*> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  %0 = load i32* %z, align 4                      ; <i32> [#uses=1]
+  %1 = sext i32 %0 to i64                         ; <i64> [#uses=1]
+  %2 = getelementptr inbounds [10 x %struct.sType]* %arr, i64 0, i64 %1 ; <%struct.sType*> [#uses=1]
+  %3 = getelementptr inbounds %struct.sType* %2, i32 0, i32 1 ; <i32*> [#uses=1]
+  %4 = load i32* %3, align 4                      ; <i32> [#uses=1]
+  store i32 %4, i32* %t, align 4
+  %5 = load i32* %z, align 4                      ; <i32> [#uses=1]
+  %6 = sext i32 %5 to i64                         ; <i64> [#uses=1]
+  %7 = getelementptr inbounds [10 x %struct.sType]* %arr, i64 0, i64 %6 ; <%struct.sType*> [#uses=1]
+  %8 = getelementptr inbounds %struct.sType* %7, i32 0, i32 0 ; <i32*> [#uses=1]
+  %9 = load i32* %8, align 4                      ; <i32> [#uses=1]
+  store i32 %9, i32* %t1, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}



From daniel at zuster.org  Thu Sep 23 11:01:54 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 23 Sep 2010 16:01:54 -0000
Subject: [llvm-commits] [test-suite] r114650 -
 /test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output
Message-ID: <20100923160154.1E7112A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 11:01:53 2010
New Revision: 114650

URL: http://llvm.org/viewvc/llvm-project?rev=114650&view=rev
Log:
NEON/simple: Adding the right reference output seems like a reasonable idea.

Modified:
    test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output

Modified: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output?rev=114650&r1=114649&r2=114650&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output (original)
+++ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.reference_output Thu Sep 23 11:01:53 2010
@@ -10,15 +10,15 @@
 a2_2: (1, 2, 3, 4)
 test_zip
 a0_2.val[0]: (0, 15, 1, 14, 2, 13, 3, 12, 4, 11, 5, 10, 6, 9, 7, 8)
-a0_2.val[1]: (0, 15, 1, 14, 2, 13, 3, 12, 4, 11, 5, 10, 6, 9, 7, 8)
-a0_3.val[0]: (0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)
-a0_3.val[1]: (15, 14, 13, 12, 11, 10, 9, 8, 15, 14, 13, 12, 11, 10, 9, 8)
+a0_2.val[1]: (8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15, 0)
+a0_3.val[0]: (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
+a0_3.val[1]: (15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
 a1_2.val[0]: (0, 7, 1, 6, 2, 5, 3, 4)
-a1_2.val[1]: (0, 7, 1, 6, 2, 5, 3, 4)
-a1_3.val[0]: (0, 1, 2, 3, 0, 1, 2, 3)
-a1_3.val[1]: (7, 6, 5, 4, 7, 6, 5, 4)
+a1_2.val[1]: (4, 3, 5, 2, 6, 1, 7, 0)
+a1_3.val[0]: (0, 1, 2, 3, 4, 5, 6, 7)
+a1_3.val[1]: (7, 6, 5, 4, 3, 2, 1, 0)
 a2_2.val[0]: (0, 3, 1, 2)
-a2_2.val[1]: (0, 3, 1, 2)
-a2_3.val[0]: (0, 1, 0, 1)
-a2_3.val[1]: (3, 2, 3, 2)
+a2_2.val[1]: (2, 1, 3, 0)
+a2_3.val[0]: (0, 1, 2, 3)
+a2_3.val[1]: (3, 2, 1, 0)
 exit 0



From daniel at zuster.org  Thu Sep 23 11:03:44 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 23 Sep 2010 16:03:44 -0000
Subject: [llvm-commits] [test-suite] r114651 -
 /test-suite/trunk/SingleSource/Regression/C++/EH/Makefile
Message-ID: <20100923160344.86B192A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 11:03:44 2010
New Revision: 114651

URL: http://llvm.org/viewvc/llvm-project?rev=114651&view=rev
Log:
Un "XFAIL" ConditionalExpr for Clang.

Modified:
    test-suite/trunk/SingleSource/Regression/C++/EH/Makefile

Modified: test-suite/trunk/SingleSource/Regression/C++/EH/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Regression/C%2B%2B/EH/Makefile?rev=114651&r1=114650&r2=114651&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Regression/C++/EH/Makefile (original)
+++ test-suite/trunk/SingleSource/Regression/C++/EH/Makefile Thu Sep 23 11:03:44 2010
@@ -1,10 +1,6 @@
 LEVEL = ../../../..
 REQUIRES_EH_SUPPORT = 1
 
-ifdef CC_UNDER_TEST_IS_CLANG
-EXEC_XFAILS = ConditionalExpr
-endif
-
 CFLAGS += -std=c99
 LDFLAGS += -lstdc++
 include $(LEVEL)/SingleSource/Makefile.singlesrc



From baldrick at free.fr  Thu Sep 23 11:06:45 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 23 Sep 2010 16:06:45 -0000
Subject: [llvm-commits] [zorg] r114653 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100923160645.189AC2A6C12C@llvm.org>

Author: baldrick
Date: Thu Sep 23 11:06:44 2010
New Revision: 114653

URL: http://llvm.org/viewvc/llvm-project?rev=114653&view=rev
Log:
For some reason 'make' doesn't accept the -jx86_64-pc-linux-gnu option!

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114653&r1=114652&r2=114653&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Sep 23 11:06:44 2010
@@ -85,7 +85,7 @@
         {'name' : "llvm-x86_64-linux-checks",
         'slavenames':["gcc10"],
         'builddir':"llvm-x86_64-linux-checks",
-        'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory("x86_64-pc-linux-gnu",
+        'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='x86_64-pc-linux-gnu',
                                                         stage1_config='Release+Asserts+Checks',
                                                         stage2_config='Release+Asserts+Checks',
                                                         extra_configure_args=['--disable-multilib'])},



From aggarwa4 at illinois.edu  Thu Sep 23 11:13:37 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 16:13:37 -0000
Subject: [llvm-commits] [poolalloc] r114657 -
	/poolalloc/trunk/test/dsa/local/multidimarray.ll
Message-ID: <20100923161337.2381A2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 11:13:36 2010
New Revision: 114657

URL: http://llvm.org/viewvc/llvm-project?rev=114657&view=rev
Log:
Example with a flattened multidimensional array. To check folding 

Added:
    poolalloc/trunk/test/dsa/local/multidimarray.ll

Added: poolalloc/trunk/test/dsa/local/multidimarray.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/multidimarray.ll?rev=114657&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/multidimarray.ll (added)
+++ poolalloc/trunk/test/dsa/local/multidimarray.ll Thu Sep 23 11:13:36 2010
@@ -0,0 +1,76 @@
+; An example with multidimensional array. It is a flattened array
+; Gets the same array tag.
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=func:arr,0:i32::8:%\struct.StructType*Array
+
+; ModuleID = 'multidimarray.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.StructType = type { i32, %struct.StructType* }
+
+define void @func() nounwind {
+entry:
+  %arr = alloca [10 x [20 x %struct.StructType]]  ; <[10 x [20 x %struct.StructType]]*> [#uses=4]
+  %i = alloca i32                                 ; <i32*> [#uses=11]
+  %s2 = alloca %struct.StructType                 ; <%struct.StructType*> [#uses=3]
+  %c = alloca %struct.StructType*                 ; <%struct.StructType**> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 0, i32* %i, align 4
+  br label %bb1
+
+bb:                                               ; preds = %bb1
+  %0 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %1 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %2 = sext i32 %0 to i64                         ; <i64> [#uses=1]
+  %3 = getelementptr inbounds [10 x [20 x %struct.StructType]]* %arr, i64 0, i64 %2 ; <[20 x %struct.StructType]*> [#uses=1]
+  %4 = sext i32 %1 to i64                         ; <i64> [#uses=1]
+  %5 = getelementptr inbounds [20 x %struct.StructType]* %3, i64 0, i64 %4 ; <%struct.StructType*> [#uses=1]
+  %6 = getelementptr inbounds %struct.StructType* %5, i32 0, i32 0 ; <i32*> [#uses=1]
+  %7 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  store i32 %7, i32* %6, align 8
+  %8 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %9 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %10 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %11 = sub nsw i32 %10, 1                        ; <i32> [#uses=1]
+  %12 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %13 = sub nsw i32 %12, 1                        ; <i32> [#uses=1]
+  %14 = sext i32 %11 to i64                       ; <i64> [#uses=1]
+  %15 = getelementptr inbounds [10 x [20 x %struct.StructType]]* %arr, i64 0, i64 %14 ; <[20 x %struct.StructType]*> [#uses=1]
+  %16 = sext i32 %13 to i64                       ; <i64> [#uses=1]
+  %17 = getelementptr inbounds [20 x %struct.StructType]* %15, i64 0, i64 %16 ; <%struct.StructType*> [#uses=1]
+  %18 = sext i32 %8 to i64                        ; <i64> [#uses=1]
+  %19 = getelementptr inbounds [10 x [20 x %struct.StructType]]* %arr, i64 0, i64 %18 ; <[20 x %struct.StructType]*> [#uses=1]
+  %20 = sext i32 %9 to i64                        ; <i64> [#uses=1]
+  %21 = getelementptr inbounds [20 x %struct.StructType]* %19, i64 0, i64 %20 ; <%struct.StructType*> [#uses=1]
+  %22 = getelementptr inbounds %struct.StructType* %21, i32 0, i32 1 ; <%struct.StructType**> [#uses=1]
+  store %struct.StructType* %17, %struct.StructType** %22, align 8
+  %23 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %24 = add nsw i32 %23, 1                        ; <i32> [#uses=1]
+  store i32 %24, i32* %i, align 4
+  br label %bb1
+
+bb1:                                              ; preds = %bb, %entry
+  %25 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %26 = icmp sle i32 %25, 9                       ; <i1> [#uses=1]
+  br i1 %26, label %bb, label %bb2
+
+bb2:                                              ; preds = %bb1
+  %27 = getelementptr inbounds [10 x [20 x %struct.StructType]]* %arr, i64 0, i64 1 ; <[20 x %struct.StructType]*> [#uses=1]
+  %28 = getelementptr inbounds [20 x %struct.StructType]* %27, i64 0, i64 1 ; <%struct.StructType*> [#uses=2]
+  %29 = getelementptr inbounds %struct.StructType* %s2, i32 0, i32 0 ; <i32*> [#uses=1]
+  %30 = getelementptr inbounds %struct.StructType* %28, i32 0, i32 0 ; <i32*> [#uses=1]
+  %31 = load i32* %30, align 8                    ; <i32> [#uses=1]
+  store i32 %31, i32* %29, align 8
+  %32 = getelementptr inbounds %struct.StructType* %s2, i32 0, i32 1 ; <%struct.StructType**> [#uses=1]
+  %33 = getelementptr inbounds %struct.StructType* %28, i32 0, i32 1 ; <%struct.StructType**> [#uses=1]
+  %34 = load %struct.StructType** %33, align 8    ; <%struct.StructType*> [#uses=1]
+  store %struct.StructType* %34, %struct.StructType** %32, align 8
+  %35 = getelementptr inbounds %struct.StructType* %s2, i32 0, i32 1 ; <%struct.StructType**> [#uses=1]
+  %36 = load %struct.StructType** %35, align 8    ; <%struct.StructType*> [#uses=1]
+  store %struct.StructType* %36, %struct.StructType** %c, align 8
+  br label %return
+
+return:                                           ; preds = %bb2
+  ret void
+}



From natebegeman at mac.com  Thu Sep 23 11:49:18 2010
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 23 Sep 2010 16:49:18 -0000
Subject: [llvm-commits] [llvm] r114659 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20100923164918.10AB12A6C12C@llvm.org>

Author: sampo
Date: Thu Sep 23 11:49:17 2010
New Revision: 114659

URL: http://llvm.org/viewvc/llvm-project?rev=114659&view=rev
Log:
Revert r114596, it's breaking a few tests.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=114659&r1=114658&r2=114659&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Thu Sep 23 11:49:17 2010
@@ -89,7 +89,7 @@
       return 'i';
     case 'f':
       return 'h';
-    default: throw "unhandled type in narrow!";
+    default: throw "unhandled type in widen!";
   }
   return '\0';
 }
@@ -155,10 +155,6 @@
     case 'n':
       type = Widen(type);
       break;
-    case 'i':
-      type = 'i';
-      scal = true;
-      break;
     case 'l':
       type = 'l';
       scal = true;
@@ -811,27 +807,14 @@
   
   for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) {
     std::string args = std::string(&arg, 1);
-    bool argquad = quad;
-    bool scal = false;
-
-    (void) ModType(proto[i], type, argquad, dummy, dummy, scal, dummy, dummy);
-    bool explicitcast = define && !scal;
-
     if (define)
       args = "(" + args + ")";
-    if (explicitcast) {
-      unsigned builtinelts = quad ? 16 : 8;
-      args = "(__neon_int8x" + utostr(builtinelts) + "_t)(" + args;
-    }
     
     // Handle multiple-vector values specially, emitting each subvector as an
     // argument to the __builtin.
-    if (structTypes && (proto[i] >= '2') && (proto[i] <= '4')) {
+    if (structTypes && (proto[i] == '2' || proto[i] == '3' || proto[i] == '4')){
       for (unsigned vi = 0, ve = proto[i] - '0'; vi != ve; ++vi) {
         s += args + ".val[" + utostr(vi) + "].val";
-        if (explicitcast)
-          s += ")";
-        
         if ((vi + 1) < ve)
           s += ", ";
       }
@@ -846,10 +829,10 @@
     else
       s += args;
     
-    if (structTypes && !scal)
+    if (structTypes && proto[i] != 's' && proto[i] != 'i' && proto[i] != 'l' &&
+        proto[i] != 'p' && proto[i] != 'c' && proto[i] != 'a') {
       s += ".val";
-    if (explicitcast)
-      s += ")";
+    }
     if ((i + 1) < e)
       s += ", ";
   }



From ofv at wanadoo.es  Thu Sep 23 11:59:36 2010
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Thu, 23 Sep 2010 16:59:36 -0000
Subject: [llvm-commits] [llvm] r114661 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20100923165936.9FCD42A6C12C@llvm.org>

Author: ofv
Date: Thu Sep 23 11:59:36 2010
New Revision: 114661

URL: http://llvm.org/viewvc/llvm-project?rev=114661&view=rev
Log:
Fix VS 2010 build.

Patch by Nathan Jeffords!

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=114661&r1=114660&r2=114661&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Sep 23 11:59:36 2010
@@ -2247,7 +2247,7 @@
       if (Val & 128)
         Val = GetVBR(Val, MatcherTable, MatcherIndex);
       RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
-                                      CurDAG->getTargetConstant(Val, VT), 0));
+                              CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
       continue;
     }
     case OPC_EmitRegister: {
@@ -2255,7 +2255,7 @@
         (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
       unsigned RegNo = MatcherTable[MatcherIndex++];
       RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
-                                      CurDAG->getRegister(RegNo, VT), 0));
+                              CurDAG->getRegister(RegNo, VT), (SDNode*)0));
       continue;
     }
         
@@ -2370,7 +2370,7 @@
       unsigned RecNo = MatcherTable[MatcherIndex++];
       assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
       SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
-      RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, 0));
+      RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
       continue;
     }
         
@@ -2451,7 +2451,7 @@
         for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
           if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
           RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
-                                                             0));
+                                                             (SDNode*) 0));
         }
         
       } else {



From ofv at wanadoo.es  Thu Sep 23 11:59:44 2010
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Thu, 23 Sep 2010 16:59:44 -0000
Subject: [llvm-commits] [llvm] r114662 - in /llvm/trunk/include/llvm:
	Attributes.h Operator.h
Message-ID: <20100923165945.009B62A6C12C@llvm.org>

Author: ofv
Date: Thu Sep 23 11:59:44 2010
New Revision: 114662

URL: http://llvm.org/viewvc/llvm-project?rev=114662&view=rev
Log:
Avoid warnings about conversions to `bool' in MS compilers.

Patch by Nathan Jeffords!

Modified:
    llvm/trunk/include/llvm/Attributes.h
    llvm/trunk/include/llvm/Operator.h

Modified: llvm/trunk/include/llvm/Attributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=114662&r1=114661&r2=114662&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Attributes.h (original)
+++ llvm/trunk/include/llvm/Attributes.h Thu Sep 23 11:59:44 2010
@@ -223,7 +223,7 @@
   /// paramHasAttr - Return true if the specified parameter index has the
   /// specified attribute set.
   bool paramHasAttr(unsigned Idx, Attributes Attr) const {
-    return getAttributes(Idx) & Attr;
+    return static_cast<bool>(getAttributes(Idx) & Attr);
   }
 
   /// getParamAlignment - Return the alignment for the specified function

Modified: llvm/trunk/include/llvm/Operator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Operator.h?rev=114662&r1=114661&r2=114662&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Operator.h (original)
+++ llvm/trunk/include/llvm/Operator.h Thu Sep 23 11:59:44 2010
@@ -99,7 +99,7 @@
   /// hasNoSignedWrap - Test whether this operation is known to never
   /// undergo signed overflow, aka the nsw property.
   bool hasNoSignedWrap() const {
-    return SubclassOptionalData & NoSignedWrap;
+    return static_cast<bool>(SubclassOptionalData & NoSignedWrap);
   }
 
   static inline bool classof(const OverflowingBinaryOperator *) { return true; }



From criswell at uiuc.edu  Thu Sep 23 12:14:45 2010
From: criswell at uiuc.edu (John Criswell)
Date: Thu, 23 Sep 2010 17:14:45 -0000
Subject: [llvm-commits] [poolalloc] r114663 - in
 /poolalloc/trunk/lib/PoolAllocate: Heuristic.cpp Heuristic.h
 PointerCompress.cpp PoolAllocate.cpp
Message-ID: <20100923171445.462562A6C12C@llvm.org>

Author: criswell
Date: Thu Sep 23 12:14:45 2010
New Revision: 114663

URL: http://llvm.org/viewvc/llvm-project?rev=114663&view=rev
Log:
Moved the Heuristic.h file into the publicly accessible header file area.

Removed:
    poolalloc/trunk/lib/PoolAllocate/Heuristic.h
Modified:
    poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp
    poolalloc/trunk/lib/PoolAllocate/PointerCompress.cpp
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp?rev=114663&r1=114662&r2=114663&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp Thu Sep 23 12:14:45 2010
@@ -16,9 +16,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "Heuristic.h"
-
 #include "dsa/DSGraphTraits.h"
+#include "poolalloc/Heuristic.h"
 #include "poolalloc/PoolAllocate.h"
 #include "llvm/Instructions.h"
 #include "llvm/Module.h"

Removed: poolalloc/trunk/lib/PoolAllocate/Heuristic.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Heuristic.h?rev=114662&view=auto
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/Heuristic.h (original)
+++ poolalloc/trunk/lib/PoolAllocate/Heuristic.h (removed)
@@ -1,107 +0,0 @@
-//===-- Heuristic.h - Interface to PA heuristics ----------------*- C++ -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This header is the abstract interface used by the pool allocator to access
-// the various heuristics supported.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef POOLALLOCATION_HEURISTIC_H
-#define POOLALLOCATION_HEURISTIC_H
-
-#include <vector>
-#include <map>
-
-namespace llvm {
-  class Value;
-  class Function;
-  class Module;
-  class DSGraph;
-  class DSNode;
-  class PoolAllocate;
-  class TargetData;
-  class Type;
-
-namespace PA {
-  class Heuristic {
-  protected:
-    Module *M;
-    DSGraph *GG;
-    PoolAllocate *PA;
-
-    Heuristic() {}
-  public:
-    void Initialize(Module &m, DSGraph* gg, PoolAllocate &pa) {
-      M = &m; GG = gg; PA = &pa;
-    }
-    virtual ~Heuristic();
-
-    /// IsRealHeuristic - Return true if this is not a real pool allocation
-    /// heuristic.
-    virtual bool IsRealHeuristic() { return true; }
-
-    /// OnePool - This represents some number of nodes which are coallesced into
-    /// a pool.
-    struct OnePool {
-      // NodesInPool - The DS nodes to be allocated to this pool.  There may be
-      // multiple here if they are being coallesced into the same pool.
-      std::vector<const DSNode*> NodesInPool;
-
-      // PoolDesc - If the heuristic wants the nodes allocated to a specific
-      // pool descriptor, it can specify it here, otherwise a new pool is
-      // created.
-      Value *PoolDesc;
-
-      // PoolSize - If the pool is to be created, indicate the "recommended
-      // size" for the pool here.  This gets passed into poolinit.
-      unsigned PoolSize;
-      unsigned PoolAlignment;
-
-      OnePool() : PoolDesc(0), PoolSize(0), PoolAlignment(0) {}
-
-      OnePool(const DSNode *N) : PoolDesc(0), PoolSize(getRecommendedSize(N)), 
-                                 PoolAlignment(getRecommendedAlignment(N)) {
-        NodesInPool.push_back(N);
-      }
-      OnePool(const DSNode *N, Value *PD) : PoolDesc(PD), PoolSize(0),
-                                            PoolAlignment(0) {
-        NodesInPool.push_back(N);
-      }
-    };
-
-    /// AssignToPools - Partition NodesToPA into a set of disjoint pools,
-    /// returning the result in ResultPools.  If this is a function being pool
-    /// allocated, F will not be null.
-    virtual void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
-                               Function *F, DSGraph* G,
-                               std::vector<OnePool> &ResultPools) = 0;
-
-    // Hacks for the OnlyOverhead heuristic.
-    virtual void HackFunctionBody(Function &F,
-                                  std::map<const DSNode*, Value*> &PDs) {}
-
-    /// getRecommendedSize - Return the recommended pool size for this DSNode.
-    ///
-    static unsigned getRecommendedSize(const DSNode *N);
-
-    /// getRecommendedAlignment - Return the recommended object alignment for
-    /// this DSNode.
-    ///
-    static unsigned getRecommendedAlignment(const DSNode *N);
-    static unsigned getRecommendedAlignment(const Type *Ty,
-                                            const TargetData &TD);
-    
-    /// create - This static ctor creates the heuristic, based on the command
-    /// line argument to choose the heuristic.
-    static Heuristic *create();
-  };
-}
-}
-
-#endif

Modified: poolalloc/trunk/lib/PoolAllocate/PointerCompress.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PointerCompress.cpp?rev=114663&r1=114662&r2=114663&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PointerCompress.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PointerCompress.cpp Thu Sep 23 12:14:45 2010
@@ -15,8 +15,8 @@
 
 #include "dsa/DataStructure.h"
 #include "dsa/DSGraph.h"
+#include "poolalloc/Heuristic.h"
 #include "poolalloc/PoolAllocate.h"
-#include "Heuristic.h"
 #include "llvm/Constants.h"
 #include "llvm/Instructions.h"
 #include "llvm/Module.h"

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=114663&r1=114662&r2=114663&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Thu Sep 23 12:14:45 2010
@@ -18,8 +18,8 @@
 
 #include "dsa/DataStructure.h"
 #include "dsa/DSGraph.h"
+#include "poolalloc/Heuristic.h"
 #include "poolalloc/PoolAllocate.h"
-#include "Heuristic.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Instructions.h"



From criswell at uiuc.edu  Thu Sep 23 12:19:58 2010
From: criswell at uiuc.edu (John Criswell)
Date: Thu, 23 Sep 2010 17:19:58 -0000
Subject: [llvm-commits] [poolalloc] r114664 -
	/poolalloc/trunk/include/poolalloc/Heuristic.h
Message-ID: <20100923171959.013462A6C12D@llvm.org>

Author: criswell
Date: Thu Sep 23 12:19:58 2010
New Revision: 114664

URL: http://llvm.org/viewvc/llvm-project?rev=114664&view=rev
Log:
Moved the Heuristic.h file to include/poolalloc.

Added:
    poolalloc/trunk/include/poolalloc/Heuristic.h
      - copied unchanged from r114662, poolalloc/trunk/lib/PoolAllocate/Heuristic.h


From tonic at nondot.org  Thu Sep 23 12:23:04 2010
From: tonic at nondot.org (Tanya Lattner)
Date: Thu, 23 Sep 2010 17:23:04 -0000
Subject: [llvm-commits] [www] r114665 - /www/trunk/devmtg/talk.php
Message-ID: <20100923172304.F1D612A6C12C@llvm.org>

Author: tbrethou
Date: Thu Sep 23 12:23:04 2010
New Revision: 114665

URL: http://llvm.org/viewvc/llvm-project?rev=114665&view=rev
Log:
Close talk proposal form.

Modified:
    www/trunk/devmtg/talk.php

Modified: www/trunk/devmtg/talk.php
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/talk.php?rev=114665&r1=114664&r2=114665&view=diff
==============================================================================
--- www/trunk/devmtg/talk.php (original)
+++ www/trunk/devmtg/talk.php Thu Sep 23 12:23:04 2010
@@ -200,8 +200,10 @@
 ?>
 
 <div class="www_sectiontitle">LLVM Developers' Meeting - Talk Proposal</div>
-
+<p>
+The deadline to submit a talk proposal has passed. We hope you can make the meeting.</p>
 <?
+exit();
 
 if (isset($_POST['verify'])) {
   $formErrors = validateForm($_POST);



From bob.wilson at apple.com  Thu Sep 23 12:25:06 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 23 Sep 2010 17:25:06 -0000
Subject: [llvm-commits] [llvm] r114666 - in /llvm/trunk:
 lib/Transforms/IPO/ExtractGV.cpp test/Other/extract.ll
Message-ID: <20100923172506.B153E2A6C12C@llvm.org>

Author: bwilson
Date: Thu Sep 23 12:25:06 2010
New Revision: 114666

URL: http://llvm.org/viewvc/llvm-project?rev=114666&view=rev
Log:
Fix llvm-extract so that it changes the linkage of all GlobalValues to
"external" even when doing lazy bitcode loading.  This was broken because
a function that is not materialized fails the !isDeclaration() test.

Modified:
    llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp
    llvm/trunk/test/Other/extract.ll

Modified: llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp?rev=114666&r1=114665&r2=114666&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Thu Sep 23 12:25:06 2010
@@ -50,24 +50,22 @@
 
       // Visit the GlobalVariables.
       for (Module::global_iterator I = M.global_begin(), E = M.global_end();
-           I != E; ++I)
-        if (!I->isDeclaration()) {
-          if (I->hasLocalLinkage())
-            I->setVisibility(GlobalValue::HiddenVisibility);
-          I->setLinkage(GlobalValue::ExternalLinkage);
-          if (deleteStuff == (bool)Named.count(I))
-            I->setInitializer(0);
-        }
+           I != E; ++I) {
+        if (I->hasLocalLinkage())
+          I->setVisibility(GlobalValue::HiddenVisibility);
+        I->setLinkage(GlobalValue::ExternalLinkage);
+        if (deleteStuff == (bool)Named.count(I) && !I->isDeclaration())
+          I->setInitializer(0);
+      }
 
       // Visit the Functions.
-      for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-        if (!I->isDeclaration()) {
-          if (I->hasLocalLinkage())
-            I->setVisibility(GlobalValue::HiddenVisibility);
-          I->setLinkage(GlobalValue::ExternalLinkage);
-          if (deleteStuff == (bool)Named.count(I))
-            I->deleteBody();
-        }
+      for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
+        if (I->hasLocalLinkage())
+          I->setVisibility(GlobalValue::HiddenVisibility);
+        I->setLinkage(GlobalValue::ExternalLinkage);
+        if (deleteStuff == (bool)Named.count(I) && !I->isDeclaration())
+          I->deleteBody();
+      }
 
       return true;
     }

Modified: llvm/trunk/test/Other/extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Other/extract.ll?rev=114666&r1=114665&r2=114666&view=diff
==============================================================================
--- llvm/trunk/test/Other/extract.ll (original)
+++ llvm/trunk/test/Other/extract.ll Thu Sep 23 12:25:06 2010
@@ -10,13 +10,18 @@
 ; CHECK: define void @foo() {
 ; CHECK:   ret void
 ; CHECK: }
+
+; The linkonce_odr linkage for foo() should be changed to external linkage.
+; DELETE: declare void @foo()
 ; DELETE: define void @bar() {
+; DELETE:   call void @foo()
 ; DELETE:   ret void
 ; DELETE: }
 
-define void @foo() {
+define linkonce_odr void @foo() {
   ret void
 }
 define void @bar() {
+  call void @foo()
   ret void
 }



From rafael.espindola at gmail.com  Thu Sep 23 12:25:18 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Sep 2010 17:25:18 -0000
Subject: [llvm-commits] [llvm] r114667 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/local-reloc.s
Message-ID: <20100923172518.647A32A6C12C@llvm.org>

Author: rafael
Date: Thu Sep 23 12:25:18 2010
New Revision: 114667

URL: http://llvm.org/viewvc/llvm-project?rev=114667&view=rev
Log:
Represent relocations against local symbols as relocations against the section
they are in. Both ways should be equivalent, but gas produces relocations
against the section.

Roman wrote the patch, I added the test.

Added:
    llvm/trunk/test/MC/ELF/local-reloc.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114667&r1=114666&r2=114667&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 23 12:25:18 2010
@@ -502,7 +502,7 @@
     }
 
     if (Base) {
-      if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) {
+      if (F && !SD.isExternal()) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
         Value += Layout.getSymbolAddress(&SD);
       } else

Added: llvm/trunk/test/MC/ELF/local-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/local-reloc.s?rev=114667&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/local-reloc.s (added)
+++ llvm/trunk/test/MC/ELF/local-reloc.s Thu Sep 23 12:25:18 2010
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
+
+// Test that relocations with local symbols are represented as relocations
+// with the section. They should be equivalent, but gas behaves like this.
+
+	movl	foo, %r14d
+foo:
+
+// Section number 1 is .text
+// CHECK:        # Section 1
+// CHECK-next:  (('sh_name', 1) # '.text'
+
+
+// Relocation refers to symbol number 2
+// CHECK:      ('_relocations', [
+// CHECK-NEXT:  # Relocation 0
+// CHECK-NEXT:   (('r_offset',
+// CHECK-NEXT:    ('r_sym', 2)
+// CHECK-NEXT:    ('r_type',
+// CHECK-NEXT:    ('r_addend',
+// CHECK-NEXT:   ),
+// CHECK-NEXT:  ])
+
+// Symbol number 2 is section number 1
+// CHECK:    # Symbol 2
+// CHECK-NEXT:    (('st_name', 0) # ''
+// CHECK-NEXT:     ('st_bind', 0)
+// CHECK-NEXT:     ('st_type', 3)
+// CHECK-NEXT:     ('st_other', 0)
+// CHECK-NEXT:     ('st_shndx', 1)
+// CHECK-NEXT:     ('st_value', 0)
+// CHECK-NEXT:     ('st_size', 0)



From tonic at nondot.org  Thu Sep 23 12:25:31 2010
From: tonic at nondot.org (Tanya Lattner)
Date: Thu, 23 Sep 2010 17:25:31 -0000
Subject: [llvm-commits] [www] r114668 - /www/trunk/devmtg/2010-11/index.html
Message-ID: <20100923172531.361952A6C12C@llvm.org>

Author: tbrethou
Date: Thu Sep 23 12:25:31 2010
New Revision: 114668

URL: http://llvm.org/viewvc/llvm-project?rev=114668&view=rev
Log:
Extend deadline for funding requests.

Modified:
    www/trunk/devmtg/2010-11/index.html

Modified: www/trunk/devmtg/2010-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=114668&r1=114667&r2=114668&view=diff
==============================================================================
--- www/trunk/devmtg/2010-11/index.html (original)
+++ www/trunk/devmtg/2010-11/index.html Thu Sep 23 12:25:31 2010
@@ -43,12 +43,7 @@
 
 <div class="www_sectiontitle" id="speakers">Call for Speakers</div>
 
-<p>We are looking for speakers for this year's developers meeting! Specifically
-we'd love talks on the LLVM, Clang, LLDB, core infrastructure, new uses and 
-applications of LLVM components, etc.</p>
-<p>If you are interested in presenting at this year's LLVM Developers'  
-Meeting, please submit your talk proposal to us by <b>September 22, 2010</b> via  
-the <a href="http://llvm.org/devmtg/talk.php">website</a>.</p>
+<p>The deadline to submit a talk proposal has passed.</p>
 
 <div class="www_sectiontitle" id="sponsors">Sponsors Needed</div>
 	
@@ -56,9 +51,9 @@
 
 <div class="www_sectiontitle" id="funding">Funding for Active Contributors/Students</div>
 
-<p>At this time, we are not sure if there will be funding for active contributors or students to attend the event. However, we are hopeful that we will have company sponsorship to make this happen. Those who are funded are required to present at the meeting and may have other requirements from their sponsor (ie. writing a blog post, etc).</p>
+<p>There will be some funding for active contributors or students to attend the event. hose who are funded are required to present at the meeting and may have other requirements from their sponsor (ie. writing a blog post, etc).</p>
 
-<p>If you need funding to attend the meeting, please submit your request to us by <b>September 22, 2010</b> via  the <a href="http://llvm.org/devmtg/students.php">website</a>.</p>
+<p>If you need funding to attend the meeting, please submit your request to us by <b>September 29, 2010</b> via  the <a href="http://llvm.org/devmtg/students.php">website</a>.</p>
 
 <!-- *********************************************************************** -->
 <hr>



From sabre at nondot.org  Thu Sep 23 12:27:54 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 23 Sep 2010 17:27:54 -0000
Subject: [llvm-commits] [llvm] r114669 -
	/llvm/trunk/docs/DeveloperPolicy.html
Message-ID: <20100923172754.528072A6C12C@llvm.org>

Author: lattner
Date: Thu Sep 23 12:27:54 2010
New Revision: 114669

URL: http://llvm.org/viewvc/llvm-project?rev=114669&view=rev
Log:
add lldb and libc++ code owners.

Modified:
    llvm/trunk/docs/DeveloperPolicy.html

Modified: llvm/trunk/docs/DeveloperPolicy.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/DeveloperPolicy.html?rev=114669&r1=114668&r2=114669&view=diff
==============================================================================
--- llvm/trunk/docs/DeveloperPolicy.html (original)
+++ llvm/trunk/docs/DeveloperPolicy.html Thu Sep 23 12:27:54 2010
@@ -196,7 +196,11 @@
 <ol>
   <li><b>Evan Cheng</b>: Code generator and all targets.</li>
 
-  <li><b>Doug Gregor</b>: Clang Basic, Lex, Parse, and Sema Libraries.</li>
+  <li><b>Greg Clayton</b>: LLDB.</li>
+
+  <li><b>Doug Gregor</b>: Clang Frontend Libraries.</li>
+
+  <li><b>Howard Hinnant</b>: libc++.</li>
 
   <li><b>Anton Korobeynikov</b>: Exception handling, debug information, and
       Windows codegen.</li>



From criswell at uiuc.edu  Thu Sep 23 12:29:44 2010
From: criswell at uiuc.edu (John Criswell)
Date: Thu, 23 Sep 2010 17:29:44 -0000
Subject: [llvm-commits] [poolalloc] r114670 - in
 /poolalloc/trunk/lib/PoolAllocate: PoolAllocate.cpp
 TransformFunctionBody.cpp
Message-ID: <20100923172944.2B7CC2A6C12C@llvm.org>

Author: criswell
Date: Thu Sep 23 12:29:43 2010
New Revision: 114670

URL: http://llvm.org/viewvc/llvm-project?rev=114670&view=rev
Log:
Added code to get automatic pool allocation to start playing nice with the new
SAFECode.
Have the poolalloc pass create a poolalloc_init() function because SAFECode
expects there to be one.
Have the poolalloc transform also correctly fill in pool handles into SAFECode
run-time checks.
Added a FIXME of something that needs to be fixed in order to work with
SAFECode correctly.

Modified:
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
    poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=114670&r1=114669&r2=114670&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Thu Sep 23 12:29:43 2010
@@ -82,6 +82,29 @@
 
 }
 
+static void
+createPoolAllocInit (Module & M) {
+  //
+  // Create the __poolalloc_init() function.
+  //
+  const Type * VoidType = Type::getVoidTy(M.getContext());
+  FunctionType * FTy = FunctionType::get(VoidType,
+                                         std::vector<const Type*>(),
+                                         false);
+  Function *InitFunc = Function::Create (FTy,
+                                         GlobalValue::ExternalLinkage,
+                                         "__poolalloc_init",
+                                         &M);
+
+  //
+  // Add an entry basic block that just returns.
+  //
+  BasicBlock * BB = BasicBlock::Create (M.getContext(), "entry", InitFunc);
+  ReturnInst::Create(M.getContext(), BB);
+
+  return;
+}
+
 void PoolAllocate::getAnalysisUsage(AnalysisUsage &AU) const {
   if (dsa_pass_to_use == PASS_EQTD) {
     AU.addRequiredTransitive<EQTDDataStructures>();
@@ -285,6 +308,12 @@
   }
 
   //
+  // Add an empty __poolalloc_init() function.  SAFECode will call this to
+  // intialize things; we don't make use of it with real pool allocation.
+  //
+  createPoolAllocInit (M);
+
+  //
   // FIXME: Make name more descriptive and explain, in a comment here, what this
   //        code is trying to do (namely, avoid optimizations for performance
   //        overhead measurements?).
@@ -1316,6 +1345,10 @@
       }
     }
 #else
+    //
+    // FIXME: This is not correct for SAFECode; all DSNodes will need to be
+    //        poolallocated.
+    //
     if ((N->isHeapNode()) || (BoundsChecksEnabled && (N->isArrayNode())) ||
     	(GlobalsGraphNodeMapping.count(N) &&
        GlobalsGraphNodeMapping[N].getNode()->isHeapNode())) {
@@ -1392,8 +1425,26 @@
 void PoolAllocate::CalculateLivePoolFreeBlocks(std::set<BasicBlock*>&LiveBlocks,
                                                Value *PD) {
   for (Value::use_iterator I = PD->use_begin(), E = PD->use_end(); I != E; ++I){
-    // The only users of the pool should be call & invoke instructions.
-    CallSite U = CallSite::get(*I);
+    //
+    // The only users of the pool should be call, invoke, and cast
+    // instructions.  We know that poolfree() and pooldestroy() do not need to
+    // cast pool handles, so if we see a non-call instruction, we know it's not
+    // used in a poolfree() or pooldestroy() call.
+    //
+    if (Instruction * Inst = dyn_cast<Instruction>(I)) {
+      if (!isa<CallInst>(*I)) {
+        // This block and every block that can reach this block must keep pool
+        // frees.
+        for (idf_ext_iterator<BasicBlock*, std::set<BasicBlock*> >
+               DI = idf_ext_begin(Inst->getParent(), LiveBlocks),
+               DE = idf_ext_end(Inst->getParent(), LiveBlocks);
+             DI != DE; ++DI)
+          /* empty */;
+        continue;
+      }
+    }
+
+    CallSite U = CallSite::get(I->stripPointerCasts());
     if (U.getCalledValue() != PoolFree && U.getCalledValue() != PoolDestroy) {
       // This block and every block that can reach this block must keep pool
       // frees.

Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=114670&r1=114669&r2=114670&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Thu Sep 23 12:29:43 2010
@@ -72,6 +72,7 @@
     void visitReallocCall(CallSite CS);
     void visitMemAlignCall(CallSite CS);
     void visitStrdupCall(CallSite CS);
+    void visitRuntimeCheck(CallSite CS);
     //void visitFreeInst(FreeInst &FI);
     void visitFreeCall(CallSite &CS);
     void visitCallSite(CallSite &CS);
@@ -137,6 +138,28 @@
   };
 }
 
+static inline Value *
+castTo (Value * V, const Type * Ty, std::string Name, Instruction * InsertPt) {
+  //
+  // Don't bother creating a cast if it's already the correct type.
+  //
+  if (V->getType() == Ty)
+    return V;
+
+  //
+  // If it's a constant, just create a constant expression.
+  //
+  if (Constant * C = dyn_cast<Constant>(V)) {
+    Constant * CE = ConstantExpr::getZExtOrBitCast (C, Ty);
+    return CE;
+  }
+
+  //
+  // Otherwise, insert a cast instruction.
+  //
+  return CastInst::CreateZExtOrBitCast (V, Ty, Name, InsertPt);
+}
+
 void
 PoolAllocate::TransformBody (DSGraph* g, PA::FuncInfo &fi,
                              std::multimap<AllocaInst*,Instruction*> &poolUses,
@@ -709,6 +732,40 @@
 }
 
 //
+// Method: visitRuntimeCheck()
+//
+// Description:
+//  Visit a call to a run-time check (or related function) and insert pool
+//  arguments where needed.
+//
+void
+FuncTransform::visitRuntimeCheck (CallSite CS) {
+  // A run-time check should have at least one argument for a pool
+  assert ((CS.arg_size() > 1) && "strdup takes one argument!");
+
+  //
+  // Get the pool handle for the pointer argument.
+  //
+  Value *PH = getPoolHandle(CS.getArgument(1)->stripPointerCasts());
+  //assert (PH && "Pool Handle for run-time checks is null!\n");
+
+  //
+  // Insert the pool handle into the run-time check.
+  //
+  if (PH) {
+    const Type * Int8Type  = Type::getInt8Ty(CS.getInstruction()->getContext());
+    const Type * VoidPtrTy = PointerType::getUnqual(Int8Type);
+    PH = castTo (PH, VoidPtrTy, PH->getName(), CS.getInstruction());
+    CS.setArgument (0, PH);
+
+    //
+    // Record that we've used the pool here.
+    //
+    AddPoolUse (*(CS.getInstruction()), PH, PoolUses);
+  }
+}
+
+//
 // Method: visitCallSite()
 //
 // Description:
@@ -780,6 +837,20 @@
     } else if (CF->getName() == "valloc") {
       errs() << "VALLOC USED BUT NOT HANDLED!\n";
       abort();
+    } else if ((CF->getName() == "sc.lscheck") ||
+               (CF->getName() == "sc.lscheckui") ||
+               (CF->getName() == "sc.lscheckalign") ||
+               (CF->getName() == "sc.lscheckalignui") ||
+               (CF->getName() == "sc.boundscheck") ||
+               (CF->getName() == "sc.boundscheckui") ||
+               (CF->getName() == "sc.pool_register_stack") ||
+               (CF->getName() == "sc.pool_unregister_stack") ||
+               (CF->getName() == "sc.pool_register_global") ||
+               (CF->getName() == "sc.pool_unregister_global") ||
+               (CF->getName() == "sc.pool_register") ||
+               (CF->getName() == "sc.pool_unregister") ||
+               (CF->getName() == "sc.get_actual_val")) {
+      visitRuntimeCheck (CS);
     } else if (CF->getName() == "pthread_create") {
       thread_creation_point = true;
 



From sabre at nondot.org  Thu Sep 23 12:37:11 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 23 Sep 2010 17:37:11 -0000
Subject: [llvm-commits] [llvm] r114673 -
	/llvm/trunk/docs/DeveloperPolicy.html
Message-ID: <20100923173711.3C3B12A6C12C@llvm.org>

Author: lattner
Date: Thu Sep 23 12:37:11 2010
New Revision: 114673

URL: http://llvm.org/viewvc/llvm-project?rev=114673&view=rev
Log:
rewrite the copyright section to match reality: llvm does't have a
copyright assignment process.

Modified:
    llvm/trunk/docs/DeveloperPolicy.html

Modified: llvm/trunk/docs/DeveloperPolicy.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/DeveloperPolicy.html?rev=114673&r1=114672&r2=114673&view=diff
==============================================================================
--- llvm/trunk/docs/DeveloperPolicy.html (original)
+++ llvm/trunk/docs/DeveloperPolicy.html Thu Sep 23 12:37:11 2010
@@ -510,20 +510,24 @@
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsection"><a name="copyright">Copyright</a></div>
 <div class="doc_text">
-<p>For consistency and ease of management, the project requires the copyright
-   for all LLVM software to be held by a single copyright holder: the University
-   of Illinois (UIUC).</p>
-  
-<p>Although UIUC may eventually reassign the copyright of the software to
-   another entity (e.g. a dedicated non-profit "LLVM Organization") the intent
-   for the project is to always have a single entity hold the copyrights to LLVM
-   at any given time.</p>
-
-<p>We believe that having a single copyright holder is in the best interests of
-   all developers and users as it greatly reduces the managerial burden for any
-   kind of administrative or technical decisions about LLVM.  The goal of the
-   LLVM project is to always keep the code open and <a href="#license">licensed
-   under a very liberal license</a>.</p>
+
+<p>The LLVM project does not require copyright assignments, which means that the
+   copyright for the code in the project is held by its respective contributors
+   who have each agreed to release their contributed code under the terms of the
+   <a href="#license">LLVM License</a>.</p>
+   
+<p>An implication of this is that the LLVM license is unlikely to ever change:
+   changing it would require tracking down all the contributors to LLVM and
+   getting them to agree that a license change is acceptable for their
+   contribution.  Since there are no plans to change the license, this is not a
+   cause for concern.</p>
+   
+<p>As a contributor to the project, this means that you (or your company) retain
+   ownership of the code you contribute, that it cannot be used in a way that
+   contradicts the license (which is a liberal BSD-style license), and that the
+   license for your contributions won't change without your approval in the
+   future.</p>
+   
 </div>
 
 <!-- _______________________________________________________________________ -->



From espindola at google.com  Thu Sep 23 12:43:10 2010
From: espindola at google.com (Rafael Espindola)
Date: Thu, 23 Sep 2010 13:43:10 -0400
Subject: [llvm-commits] [patch][RFC] Correctly produce R_X86_64_32 or
	R_X86_64_32S
In-Reply-To: <20100923141034.GA80287@freebsd.org>
References: <AANLkTikmXne4afVBc_zohprP=1UWZEgJufrvCw-=n1-k@mail.gmail.com>
	<AANLkTi=ABAVxcn7mdkQfiLLVHEveH237gtO_db2ArYdd@mail.gmail.com>
	<AANLkTi=qf+oWGf4tpGR14r9XYKMsQ7Wb0Jd5gZnwBo8p@mail.gmail.com>
	<20100923141034.GA80287@freebsd.org>
Message-ID: <AANLkTi=tUk0zJLUQLyLbD892jOk4QNzHpV-3o7Q1mMa1@mail.gmail.com>

> fwiw - I havent observed any ill effects with this patch + it fixes
> all signed/unsigned reloc mismatches I was having when linking
> FreeBSD kenrel.

Nice!

An update patch against current trunk is attached. I also expanded the
included test.

> roman
>

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From grosbach at apple.com  Thu Sep 23 12:58:00 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 17:58:00 -0000
Subject: [llvm-commits] [llvm] r114676 -
	/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
Message-ID: <20100923175800.39DFB2A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 12:58:00 2010
New Revision: 114676

URL: http://llvm.org/viewvc/llvm-project?rev=114676&view=rev
Log:
nuke unused var

Modified:
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h?rev=114676&r1=114675&r2=114676&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h Thu Sep 23 12:58:00 2010
@@ -20,7 +20,6 @@
   class MCOperand;
 
 class ARMInstPrinter : public MCInstPrinter {
-  bool VerboseAsm;
 public:
   ARMInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {}
 



From rafael.espindola at gmail.com  Thu Sep 23 13:01:31 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Sep 2010 18:01:31 -0000
Subject: [llvm-commits] [llvm] r114678 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20100923180131.AC1422A6C12C@llvm.org>

Author: rafael
Date: Thu Sep 23 13:01:31 2010
New Revision: 114678

URL: http://llvm.org/viewvc/llvm-project?rev=114678&view=rev
Log:
Correctly compute the offset of the symbol. Forgot these bits from the
last commit.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114678&r1=114677&r2=114678&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 23 13:01:31 2010
@@ -504,7 +504,10 @@
     if (Base) {
       if (F && !SD.isExternal()) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
-        Value += Layout.getSymbolAddress(&SD);
+
+        MCSectionData *FSD = F->getParent();
+        // Offset of the symbol in the section
+        Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
       } else
         Index = getSymbolIndexInSymbolTable(Asm, Symbol);
       if (Base != &SD)



From grosbach at apple.com  Thu Sep 23 13:05:37 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 18:05:37 -0000
Subject: [llvm-commits] [llvm] r114679 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMInstrInfo.td ARMInstrThumb.td
Message-ID: <20100923180537.BA9082A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 13:05:37 2010
New Revision: 114679

URL: http://llvm.org/viewvc/llvm-project?rev=114679&view=rev
Log:
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114679&r1=114678&r2=114679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 13:05:37 2010
@@ -1210,6 +1210,16 @@
     OS << '\t';
     printRegisterList(MI, 5, OS);
   } else
+  // TRAP and tTRAP need special handling for non-Darwin. The GNU binutils
+  // don't (yet) support the 'trap' mnemonic. (Use decimal, not hex, to
+  // be consistent with the MC instruction printer.)
+  // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
+  //        Need a way to ask "isTargetDarwin()" there, first, though.
+  if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
+    OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
+  } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
+    OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
+  } else
     printInstruction(MI, OS);
 
   // Output the instruction to the stream
@@ -1714,6 +1724,30 @@
     EmitJumpTable(MI);
     return;
   }
+  case ARM::TRAP: {
+    // Non-Darwin binutils don't yet support the "trap" mnemonic.
+    // FIXME: Remove this special case when they do.
+    if (!Subtarget->isTargetDarwin()) {
+      //.long 0xe7ffdefe ${:comment} trap
+      uint32_t Val = 0xe7ffdefee;
+      OutStreamer.AddComment("trap");
+      OutStreamer.EmitIntValue(Val, 4);
+      return;
+    }
+    break;
+  }
+  case ARM::tTRAP: {
+    // Non-Darwin binutils don't yet support the "trap" mnemonic.
+    // FIXME: Remove this special case when they do.
+    if (!Subtarget->isTargetDarwin()) {
+      //.long 0xe7ffdefe ${:comment} trap
+      uint32_t Val = 0xdefe;
+      OutStreamer.AddComment("trap");
+      OutStreamer.EmitIntValue(Val, 2);
+      return;
+    }
+    break;
+  }
   }
 
   MCInst TmpInst;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114679&r1=114678&r2=114679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 23 13:05:37 2010
@@ -815,11 +815,9 @@
 }
 
 // A5.4 Permanently UNDEFINED instructions.
-// FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
-// binutils
 let isBarrier = 1, isTerminator = 1 in
 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 
-               ".long 0xe7ffdefe ${:comment} trap", [(trap)]>,
+               "trap", [(trap)]>,
            Requires<[IsARM]> {
   let Inst{27-25} = 0b011;
   let Inst{24-20} = 0b11111;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=114679&r1=114678&r2=114679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Sep 23 13:05:37 2010
@@ -411,11 +411,9 @@
 
 // A8.6.16 B: Encoding T1
 // If Inst{11-8} == 0b1110 then UNDEFINED
-// FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
-// binutils
 let isBarrier = 1, isTerminator = 1 in
 def tTRAP : TI<(outs), (ins), IIC_Br, 
-               ".short 0xdefe ${:comment} trap", [(trap)]>, Encoding16 {
+               "trap", [(trap)]>, Encoding16 {
   let Inst{15-12} = 0b1101;
   let Inst{11-8} = 0b1110;
 }



From grosbach at apple.com  Thu Sep 23 13:07:04 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 18:07:04 -0000
Subject: [llvm-commits] [llvm] r114680 -
	/llvm/trunk/include/llvm/MC/MCAsmInfo.h
Message-ID: <20100923180704.EFF472A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 13:07:04 2010
New Revision: 114680

URL: http://llvm.org/viewvc/llvm-project?rev=114680&view=rev
Log:
trailing whitespace

Modified:
    llvm/trunk/include/llvm/MC/MCAsmInfo.h

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=114680&r1=114679&r2=114680&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Sep 23 13:07:04 2010
@@ -22,7 +22,7 @@
 namespace llvm {
   class MCSection;
   class MCContext;
-  
+
   /// MCAsmInfo - This class is intended to be used as a base class for asm
   /// properties and features specific to the target.
   namespace ExceptionHandling { enum ExceptionsType { None, Dwarf, SjLj }; }
@@ -36,25 +36,25 @@
     /// HasSubsectionsViaSymbols - True if this target has the MachO
     /// .subsections_via_symbols directive.
     bool HasSubsectionsViaSymbols;           // Default is false.
-    
+
     /// HasMachoZeroFillDirective - True if this is a MachO target that supports
     /// the macho-specific .zerofill directive for emitting BSS Symbols.
     bool HasMachoZeroFillDirective;               // Default is false.
-    
+
     /// HasMachoTBSSDirective - True if this is a MachO target that supports
     /// the macho-specific .tbss directive for emitting thread local BSS Symbols
     bool HasMachoTBSSDirective;                 // Default is false.
-    
+
     /// HasStaticCtorDtorReferenceInStaticMode - True if the compiler should
     /// emit a ".reference .constructors_used" or ".reference .destructors_used"
     /// directive after the a static ctor/dtor list.  This directive is only
     /// emitted in Static relocation model.
     bool HasStaticCtorDtorReferenceInStaticMode;  // Default is false.
-    
+
     /// MaxInstLength - This is the maximum possible length of an instruction,
     /// which is needed to compute the size of an inline asm.
     unsigned MaxInstLength;                  // Defaults to 4.
-    
+
     /// PCSymbol - The symbol used to represent the current PC.  Used in PC
     /// relative expressions.
     const char *PCSymbol;                    // Defaults to "$".
@@ -83,12 +83,12 @@
     /// pool entries that are completely private to the .s file and should not
     /// have names in the .o file.  This is often "." or "L".
     const char *PrivateGlobalPrefix;         // Defaults to "."
-    
+
     /// LinkerPrivateGlobalPrefix - This prefix is used for symbols that should
     /// be passed through the assembler but be removed by the linker.  This
     /// is "l" on Darwin, currently used for some ObjC metadata.
     const char *LinkerPrivateGlobalPrefix;   // Defaults to ""
-    
+
     /// InlineAsmStart/End - If these are nonempty, they contain a directive to
     /// emit before and after an inline assembly statement.
     const char *InlineAsmStart;              // Defaults to "#APP\n"
@@ -120,7 +120,7 @@
     /// AsciiDirective - This directive allows emission of an ascii string with
     /// the standard C escape characters embedded into it.
     const char *AsciiDirective;              // Defaults to "\t.ascii\t"
-    
+
     /// AscizDirective - If not null, this allows for special handling of
     /// zero terminated strings on this target.  This is commonly supported as
     /// ".asciz".  If a target doesn't support this, it can be set to null.
@@ -138,7 +138,7 @@
     /// which should be relocated as a 32-bit GP-relative offset, e.g. .gpword
     /// on Mips or .gprel32 on Alpha.
     const char *GPRel32Directive;            // Defaults to NULL.
-    
+
     /// getDataASDirective - Return the directive that should be used to emit
     /// data of the specified size to the specified numeric address space.
     virtual const char *getDataASDirective(unsigned Size, unsigned AS) const {
@@ -152,15 +152,15 @@
     bool SunStyleELFSectionSwitchSyntax;     // Defaults to false.
 
     /// UsesELFSectionDirectiveForBSS - This is true if this target uses ELF
-    /// '.section' directive before the '.bss' one. It's used for PPC/Linux 
+    /// '.section' directive before the '.bss' one. It's used for PPC/Linux
     /// which doesn't support the '.bss' directive only.
     bool UsesELFSectionDirectiveForBSS;      // Defaults to false.
-    
+
     /// HasMicrosoftFastStdCallMangling - True if this target uses microsoft
     /// style mangling for functions with X86_StdCall/X86_FastCall calling
     /// convention.
     bool HasMicrosoftFastStdCallMangling;    // Defaults to false.
-    
+
     //===--- Alignment Information ----------------------------------------===//
 
     /// AlignDirective - The directive used to emit round up to an alignment
@@ -179,27 +179,27 @@
     unsigned TextAlignFillValue;             // Defaults to 0
 
     //===--- Global Variable Emission Directives --------------------------===//
-    
+
     /// GlobalDirective - This is the directive used to declare a global entity.
     ///
     const char *GlobalDirective;             // Defaults to NULL.
 
-    /// ExternDirective - This is the directive used to declare external 
+    /// ExternDirective - This is the directive used to declare external
     /// globals.
     ///
     const char *ExternDirective;             // Defaults to NULL.
-    
+
     /// HasSetDirective - True if the assembler supports the .set directive.
     bool HasSetDirective;                    // Defaults to true.
-    
+
     /// HasLCOMMDirective - This is true if the target supports the .lcomm
     /// directive.
     bool HasLCOMMDirective;                  // Defaults to false.
-    
+
     /// COMMDirectiveAlignmentIsInBytes - True is COMMDirective's optional
     /// alignment is to be specified in bytes instead of log2(n).
     bool COMMDirectiveAlignmentIsInBytes;    // Defaults to true;
-    
+
     /// HasDotTypeDotSizeDirective - True if the target has .type and .size
     /// directives, this is true for most ELF targets.
     bool HasDotTypeDotSizeDirective;         // Defaults to true.
@@ -215,7 +215,7 @@
     /// WeakRefDirective - This directive, if non-null, is used to declare a
     /// global as being a weak undefined symbol.
     const char *WeakRefDirective;            // Defaults to NULL.
-    
+
     /// WeakDefDirective - This directive, if non-null, is used to declare a
     /// global as being a weak defined symbol.
     const char *WeakDefDirective;            // Defaults to NULL.
@@ -223,7 +223,7 @@
     /// LinkOnceDirective - This directive, if non-null is used to declare a
     /// global as being a weak defined symbol.  This is used on cygwin/mingw.
     const char *LinkOnceDirective;           // Defaults to NULL.
-    
+
     /// HiddenVisibilityAttr - This attribute, if not MCSA_Invalid, is used to
     /// declare a symbol as having hidden visibility.
     MCSymbolAttr HiddenVisibilityAttr;       // Defaults to MCSA_Hidden.
@@ -257,8 +257,8 @@
 
     /// DwarfSectionOffsetDirective - Special section offset directive.
     const char* DwarfSectionOffsetDirective; // Defaults to NULL
-    
-    /// DwarfUsesAbsoluteLabelForStmtList - True if DW_AT_stmt_list needs 
+
+    /// DwarfUsesAbsoluteLabelForStmtList - True if DW_AT_stmt_list needs
     /// absolute label instead of offset.
     bool DwarfUsesAbsoluteLabelForStmtList;  // Defaults to true;
 
@@ -279,7 +279,7 @@
     static unsigned getULEB128Size(unsigned Value);
 
     bool hasSubsectionsViaSymbols() const { return HasSubsectionsViaSymbols; }
-    
+
     // Data directive accessors.
     //
     const char *getData8bitsDirective(unsigned AS = 0) const {
@@ -302,11 +302,11 @@
     virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) const{
       return 0;
     }
-    
+
     bool usesSunStyleELFSectionSwitchSyntax() const {
       return SunStyleELFSectionSwitchSyntax;
     }
-    
+
     bool usesELFSectionDirectiveForBSS() const {
       return UsesELFSectionDirectiveForBSS;
     }
@@ -314,7 +314,7 @@
     bool hasMicrosoftFastStdCallMangling() const {
       return HasMicrosoftFastStdCallMangling;
     }
-    
+
     // Accessors.
     //
     bool hasMachoZeroFillDirective() const { return HasMachoZeroFillDirective; }
@@ -402,7 +402,7 @@
     const char *getWeakRefDirective() const { return WeakRefDirective; }
     const char *getWeakDefDirective() const { return WeakDefDirective; }
     const char *getLinkOnceDirective() const { return LinkOnceDirective; }
-    
+
     MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityAttr;}
     MCSymbolAttr getProtectedVisibilityAttr() const {
       return ProtectedVisibilityAttr;



From clattner at apple.com  Thu Sep 23 13:25:37 2010
From: clattner at apple.com (Chris Lattner)
Date: Thu, 23 Sep 2010 11:25:37 -0700
Subject: [llvm-commits] [llvm] r114679 - in /llvm/trunk/lib/Target/ARM:
	ARMAsmPrinter.cpp ARMInstrInfo.td ARMInstrThumb.td
In-Reply-To: <20100923180537.BA9082A6C12C@llvm.org>
References: <20100923180537.BA9082A6C12C@llvm.org>
Message-ID: <ECD056F0-3E3E-4BCD-AEC2-5E007207436F@apple.com>

On Sep 23, 2010, at 11:05 AM, Jim Grosbach wrote:
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114679&view=rev
> Log:
> Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
> (yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
> opcode directly. On Darwin, however, we do want the mnemonic for more
> readable assembly code and better disassembly.

Nice!

> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 13:05:37 2010
> @@ -1210,6 +1210,16 @@
>     OS << '\t';
>     printRegisterList(MI, 5, OS);
>   } else
> +  // TRAP and tTRAP need special handling for non-Darwin. The GNU binutils
> +  // don't (yet) support the 'trap' mnemonic. (Use decimal, not hex, to
> +  // be consistent with the MC instruction printer.)
> +  // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
> +  //        Need a way to ask "isTargetDarwin()" there, first, though.
> +  if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
> +    OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
> +  } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
> +    OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";

I'm fine with this staying in ARMAsmPrinter.cpp (in mcinst lowering), it's the right place to go.  This specific hunk will disappear when the old instprinter gets vaporized.

-Chris




From evan.cheng at apple.com  Thu Sep 23 13:32:19 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 18:32:19 -0000
Subject: [llvm-commits] [llvm] r114681 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100923183219.35D1D2A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 13:32:19 2010
New Revision: 114681

URL: http://llvm.org/viewvc/llvm-project?rev=114681&view=rev
Log:
Revert 114634 for now since buildbot claim it broke Clang self-hosting. I doubt it but it's possible it's exposing another bug somewhere.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114681&r1=114680&r2=114681&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep 23 13:32:19 2010
@@ -1617,8 +1617,9 @@
                                 MVT::Other, CopyTo, RangeCmp,
                                 DAG.getBasicBlock(B.Default));
 
-  BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
-                        DAG.getBasicBlock(MBB));
+  if (MBB != NextBlock)
+    BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
+                          DAG.getBasicBlock(MBB));
 
   DAG.setRoot(BrRange);
 }
@@ -1671,8 +1672,9 @@
   if (++BBI != FuncInfo.MF->end())
     NextBlock = BBI;
 
-  BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
-                      DAG.getBasicBlock(NextMBB));
+  if (NextMBB != NextBlock)
+    BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
+                        DAG.getBasicBlock(NextMBB));
 
   DAG.setRoot(BrAnd);
 }



From nlewycky at google.com  Thu Sep 23 13:35:29 2010
From: nlewycky at google.com (Nick Lewycky)
Date: Thu, 23 Sep 2010 11:35:29 -0700
Subject: [llvm-commits] [llvm] r114673 -
	/llvm/trunk/docs/DeveloperPolicy.html
In-Reply-To: <20100923173711.3C3B12A6C12C@llvm.org>
References: <20100923173711.3C3B12A6C12C@llvm.org>
Message-ID: <AANLkTinSL-AZL9zzmeXSkPF-Ne19KFyMUt-L9rXBdn2A@mail.gmail.com>

On 23 September 2010 10:37, Chris Lattner <sabre at nondot.org> wrote:

> Author: lattner
> Date: Thu Sep 23 12:37:11 2010
> New Revision: 114673
>
> URL: http://llvm.org/viewvc/llvm-project?rev=114673&view=rev
> Log:
> rewrite the copyright section to match reality: llvm does't have a
> copyright assignment process.
>

Chris, thank you for this fix!

Nick

Modified:
>    llvm/trunk/docs/DeveloperPolicy.html
>
> Modified: llvm/trunk/docs/DeveloperPolicy.html
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/DeveloperPolicy.html?rev=114673&r1=114672&r2=114673&view=diff
>
> ==============================================================================
> --- llvm/trunk/docs/DeveloperPolicy.html (original)
> +++ llvm/trunk/docs/DeveloperPolicy.html Thu Sep 23 12:37:11 2010
> @@ -510,20 +510,24 @@
>  <!--
> _______________________________________________________________________ -->
>  <div class="doc_subsection"><a name="copyright">Copyright</a></div>
>  <div class="doc_text">
> -<p>For consistency and ease of management, the project requires the
> copyright
> -   for all LLVM software to be held by a single copyright holder: the
> University
> -   of Illinois (UIUC).</p>
> -
> -<p>Although UIUC may eventually reassign the copyright of the software to
> -   another entity (e.g. a dedicated non-profit "LLVM Organization") the
> intent
> -   for the project is to always have a single entity hold the copyrights
> to LLVM
> -   at any given time.</p>
> -
> -<p>We believe that having a single copyright holder is in the best
> interests of
> -   all developers and users as it greatly reduces the managerial burden
> for any
> -   kind of administrative or technical decisions about LLVM.  The goal of
> the
> -   LLVM project is to always keep the code open and <a
> href="#license">licensed
> -   under a very liberal license</a>.</p>
> +
> +<p>The LLVM project does not require copyright assignments, which means
> that the
> +   copyright for the code in the project is held by its respective
> contributors
> +   who have each agreed to release their contributed code under the terms
> of the
> +   <a href="#license">LLVM License</a>.</p>
> +
> +<p>An implication of this is that the LLVM license is unlikely to ever
> change:
> +   changing it would require tracking down all the contributors to LLVM
> and
> +   getting them to agree that a license change is acceptable for their
> +   contribution.  Since there are no plans to change the license, this is
> not a
> +   cause for concern.</p>
> +
> +<p>As a contributor to the project, this means that you (or your company)
> retain
> +   ownership of the code you contribute, that it cannot be used in a way
> that
> +   contradicts the license (which is a liberal BSD-style license), and
> that the
> +   license for your contributions won't change without your approval in
> the
> +   future.</p>
> +
>  </div>
>
>  <!--
> _______________________________________________________________________ -->
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From aggarwa4 at illinois.edu  Thu Sep 23 13:50:50 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 18:50:50 -0000
Subject: [llvm-commits] [poolalloc] r114683 -
	/poolalloc/trunk/test/dsa/local/arrayPointers3.ll
Message-ID: <20100923185050.E919C2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 13:50:50 2010
New Revision: 114683

URL: http://llvm.org/viewvc/llvm-project?rev=114683&view=rev
Log:
Array flag test case

Added:
    poolalloc/trunk/test/dsa/local/arrayPointers3.ll

Added: poolalloc/trunk/test/dsa/local/arrayPointers3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrayPointers3.ll?rev=114683&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrayPointers3.ll (added)
+++ poolalloc/trunk/test/dsa/local/arrayPointers3.ll Thu Sep 23 13:50:50 2010
@@ -0,0 +1,104 @@
+; array of pointers to arrays of structs. The inner array gets folded.
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array,0:%\struct.structType*Array
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array:0,main:row1,main:row2,FoldedVOIDArray
+;RUN: dsaopt %s -dsa-local -analyze -check-same-node=main:row1,main:row2,main:array:0
+
+; ModuleID = 'arrayPointers3.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.structType = type { i32, i32, float }
+
+define void @main() nounwind {
+entry:
+  %nrows = alloca i32                             ; <i32*> [#uses=2]
+  %ncolumns = alloca i32                          ; <i32*> [#uses=2]
+  %i = alloca i32                                 ; <i32*> [#uses=9]
+  %array = alloca [10 x %struct.structType*]      ; <[10 x %struct.structType*]*> [#uses=5]
+  %row1 = alloca [10 x %struct.structType]        ; <[10 x %struct.structType]*> [#uses=1]
+  %row2 = alloca [10 x %struct.structType]        ; <[10 x %struct.structType]*> [#uses=1]
+  %j = alloca i32                                 ; <i32*> [#uses=9]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 2, i32* %nrows, align 4
+  store i32 10, i32* %ncolumns, align 4
+  %0 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 0 ; <%struct.structType**> [#uses=1]
+  %row11 = bitcast [10 x %struct.structType]* %row1 to %struct.structType* ; <%struct.structType*> [#uses=1]
+  store %struct.structType* %row11, %struct.structType** %0, align 8
+  %1 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 1 ; <%struct.structType**> [#uses=1]
+  %row22 = bitcast [10 x %struct.structType]* %row2 to %struct.structType* ; <%struct.structType*> [#uses=1]
+  store %struct.structType* %row22, %struct.structType** %1, align 8
+  store i32 0, i32* %i, align 4
+  br label %bb6
+
+bb:                                               ; preds = %bb6
+  store i32 0, i32* %j, align 4
+  br label %bb4
+
+bb3:                                              ; preds = %bb4
+  %2 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %3 = sext i32 %2 to i64                         ; <i64> [#uses=1]
+  %4 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %3 ; <%struct.structType**> [#uses=1]
+  %5 = load %struct.structType** %4, align 8      ; <%struct.structType*> [#uses=1]
+  %6 = load i32* %j, align 4                      ; <i32> [#uses=1]
+  %7 = sext i32 %6 to i64                         ; <i64> [#uses=1]
+  %8 = getelementptr inbounds %struct.structType* %5, i64 %7 ; <%struct.structType*> [#uses=1]
+  %9 = getelementptr inbounds %struct.structType* %8, i32 0, i32 0 ; <i32*> [#uses=1]
+  %10 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  store i32 %10, i32* %9, align 4
+  %11 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %12 = add nsw i32 %11, 1                        ; <i32> [#uses=1]
+  store i32 %12, i32* %j, align 4
+  br label %bb4
+
+bb4:                                              ; preds = %bb3, %bb
+  %13 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %14 = load i32* %ncolumns, align 4              ; <i32> [#uses=1]
+  %15 = icmp slt i32 %13, %14                     ; <i1> [#uses=1]
+  br i1 %15, label %bb3, label %bb5
+
+bb5:                                              ; preds = %bb4
+  %16 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %17 = sext i32 %16 to i64                       ; <i64> [#uses=1]
+  %18 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %17 ; <%struct.structType**> [#uses=1]
+  %19 = load %struct.structType** %18, align 8    ; <%struct.structType*> [#uses=1]
+  %20 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %21 = sext i32 %20 to i64                       ; <i64> [#uses=1]
+  %22 = getelementptr inbounds %struct.structType* %19, i64 %21 ; <%struct.structType*> [#uses=1]
+  %23 = getelementptr inbounds %struct.structType* %22, i32 0, i32 1 ; <i32*> [#uses=1]
+  %24 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  store i32 %24, i32* %23, align 4
+  %25 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %26 = sext i32 %25 to i64                       ; <i64> [#uses=1]
+  %27 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %26 ; <%struct.structType**> [#uses=1]
+  %28 = load %struct.structType** %27, align 8    ; <%struct.structType*> [#uses=1]
+  %29 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %30 = sext i32 %29 to i64                       ; <i64> [#uses=1]
+  %31 = getelementptr inbounds %struct.structType* %28, i64 %30 ; <%struct.structType*> [#uses=1]
+  %32 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %33 = sitofp i32 %32 to double                  ; <double> [#uses=1]
+  %34 = fdiv double %33, 2.000000e+00             ; <double> [#uses=1]
+  %35 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %36 = sitofp i32 %35 to double                  ; <double> [#uses=1]
+  %37 = fdiv double %36, 2.000000e+00             ; <double> [#uses=1]
+  %38 = fadd double %34, %37                      ; <double> [#uses=1]
+  %39 = fptrunc double %38 to float               ; <float> [#uses=1]
+  %40 = getelementptr inbounds %struct.structType* %31, i32 0, i32 2 ; <float*> [#uses=1]
+  store float %39, float* %40, align 4
+  %41 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %42 = add nsw i32 %41, 1                        ; <i32> [#uses=1]
+  store i32 %42, i32* %i, align 4
+  br label %bb6
+
+bb6:                                              ; preds = %bb5, %entry
+  %43 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %44 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %45 = icmp slt i32 %43, %44                     ; <i1> [#uses=1]
+  br i1 %45, label %bb, label %bb7
+
+bb7:                                              ; preds = %bb6
+  br label %return
+
+return:                                           ; preds = %bb7
+  ret void
+}



From benny.kra at googlemail.com  Thu Sep 23 13:57:26 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 23 Sep 2010 18:57:26 -0000
Subject: [llvm-commits] [llvm] r114684 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100923185726.7CBA62A6C12C@llvm.org>

Author: d0k
Date: Thu Sep 23 13:57:26 2010
New Revision: 114684

URL: http://llvm.org/viewvc/llvm-project?rev=114684&view=rev
Log:
Unbreak build. Jim, please review.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114684&r1=114683&r2=114684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 13:57:26 2010
@@ -1216,7 +1216,7 @@
   // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
   //        Need a way to ask "isTargetDarwin()" there, first, though.
   if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
-    OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
+    OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
   } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
     OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
   } else
@@ -1729,7 +1729,7 @@
     // FIXME: Remove this special case when they do.
     if (!Subtarget->isTargetDarwin()) {
       //.long 0xe7ffdefe ${:comment} trap
-      uint32_t Val = 0xe7ffdefee;
+      uint32_t Val = 0xe7ffdefe;
       OutStreamer.AddComment("trap");
       OutStreamer.EmitIntValue(Val, 4);
       return;
@@ -1740,8 +1740,8 @@
     // Non-Darwin binutils don't yet support the "trap" mnemonic.
     // FIXME: Remove this special case when they do.
     if (!Subtarget->isTargetDarwin()) {
-      //.long 0xe7ffdefe ${:comment} trap
-      uint32_t Val = 0xdefe;
+      //.short 57086 ${:comment} trap
+      uint16_t Val = 0xdefe;
       OutStreamer.AddComment("trap");
       OutStreamer.EmitIntValue(Val, 2);
       return;



From ismail at namtrac.org  Thu Sep 23 14:01:12 2010
From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=)
Date: Thu, 23 Sep 2010 22:01:12 +0300
Subject: [llvm-commits] [llvm] r114681 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <20100923183219.35D1D2A6C12C@llvm.org>
References: <20100923183219.35D1D2A6C12C@llvm.org>
Message-ID: <AANLkTi=JVKo7kfh-Qmz95xH1mCzav1u6N7Y2dHKqLkw1@mail.gmail.com>

This possibly fixed http://llvm.org/bugs/show_bug.cgi?id=8212 too .

On Thu, Sep 23, 2010 at 9:32 PM, Evan Cheng <evan.cheng at apple.com> wrote:

> Author: evancheng
> Date: Thu Sep 23 13:32:19 2010
> New Revision: 114681
>
> URL: http://llvm.org/viewvc/llvm-project?rev=114681&view=rev
> Log:
> Revert 114634 for now since buildbot claim it broke Clang self-hosting. I
> doubt it but it's possible it's exposing another bug somewhere.
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114681&r1=114680&r2=114681&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep 23
> 13:32:19 2010
> @@ -1617,8 +1617,9 @@
>                                 MVT::Other, CopyTo, RangeCmp,
>                                 DAG.getBasicBlock(B.Default));
>
> -  BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
> -                        DAG.getBasicBlock(MBB));
> +  if (MBB != NextBlock)
> +    BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
> +                          DAG.getBasicBlock(MBB));
>
>   DAG.setRoot(BrRange);
>  }
> @@ -1671,8 +1672,9 @@
>   if (++BBI != FuncInfo.MF->end())
>     NextBlock = BBI;
>
> -  BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
> -                      DAG.getBasicBlock(NextMBB));
> +  if (NextMBB != NextBlock)
> +    BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
> +                        DAG.getBasicBlock(NextMBB));
>
>   DAG.setRoot(BrAnd);
>  }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From grosbach at apple.com  Thu Sep 23 14:08:04 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 19:08:04 -0000
Subject: [llvm-commits] [llvm] r114686 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100923190804.8592D2A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 14:08:04 2010
New Revision: 114686

URL: http://llvm.org/viewvc/llvm-project?rev=114686&view=rev
Log:
explicit 'unsigned long' on constant value. Hopefully make bots happier.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114686&r1=114685&r2=114686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 14:08:04 2010
@@ -1729,7 +1729,7 @@
     // FIXME: Remove this special case when they do.
     if (!Subtarget->isTargetDarwin()) {
       //.long 0xe7ffdefe ${:comment} trap
-      uint32_t Val = 0xe7ffdefe;
+      uint32_t Val = 0xe7ffdefeUL;
       OutStreamer.AddComment("trap");
       OutStreamer.EmitIntValue(Val, 4);
       return;



From grosbach at apple.com  Thu Sep 23 14:32:40 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 19:32:40 -0000
Subject: [llvm-commits] [llvm] r114687 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100923193240.AACBD2A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 14:32:40 2010
New Revision: 114687

URL: http://llvm.org/viewvc/llvm-project?rev=114687&view=rev
Log:
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
constant. Hopefully the non-Darwin bots will like it...

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114687&r1=114686&r2=114687&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 14:32:40 2010
@@ -1729,7 +1729,7 @@
     // FIXME: Remove this special case when they do.
     if (!Subtarget->isTargetDarwin()) {
       //.long 0xe7ffdefe ${:comment} trap
-      uint32_t Val = 0xe7ffdefeUL;
+      uint32_t Val = 0xe7ffdefeeUL;
       OutStreamer.AddComment("trap");
       OutStreamer.EmitIntValue(Val, 4);
       return;



From grosbach at apple.com  Thu Sep 23 14:34:23 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 12:34:23 -0700
Subject: [llvm-commits] [llvm] r114684 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
In-Reply-To: <20100923185726.7CBA62A6C12C@llvm.org>
References: <20100923185726.7CBA62A6C12C@llvm.org>
Message-ID: <8ECEB833-F8BE-49FF-88CD-128F3FB0B154@apple.com>


On Sep 23, 2010, at 11:57 AM, Benjamin Kramer wrote:

> Author: d0k
> Date: Thu Sep 23 13:57:26 2010
> New Revision: 114684
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114684&view=rev
> Log:
> Unbreak build. Jim, please review.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114684&r1=114683&r2=114684&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 13:57:26 2010
> @@ -1216,7 +1216,7 @@
>   // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
>   //        Need a way to ask "isTargetDarwin()" there, first, though.
>   if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
> -    OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
> +    OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
>   } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
>     OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
>   } else
> @@ -1729,7 +1729,7 @@
>     // FIXME: Remove this special case when they do.
>     if (!Subtarget->isTargetDarwin()) {
>       //.long 0xe7ffdefe ${:comment} trap
> -      uint32_t Val = 0xe7ffdefee;
> +      uint32_t Val = 0xe7ffdefe;
 
The value was correct before. Clang is just being picky about the constant type. Not sure why I can't reproduce locally; I am building with clang. Odd. From the bot emails, looks like it only issues that diagnostic for this line on non-Darwin hosts?

Fixed the value in r114687, with an explicit "UL" suffix on the constant this time. Hopefully the bots will like that...

>       OutStreamer.AddComment("trap");
>       OutStreamer.EmitIntValue(Val, 4);
>       return;
> @@ -1740,8 +1740,8 @@
>     // Non-Darwin binutils don't yet support the "trap" mnemonic.
>     // FIXME: Remove this special case when they do.
>     if (!Subtarget->isTargetDarwin()) {
> -      //.long 0xe7ffdefe ${:comment} trap
> -      uint32_t Val = 0xdefe;
> +      //.short 57086 ${:comment} trap
> +      uint16_t Val = 0xdefe;
>       OutStreamer.AddComment("trap");
>       OutStreamer.EmitIntValue(Val, 2);
>       return;
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From evan.cheng at apple.com  Thu Sep 23 14:42:03 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Sep 2010 19:42:03 -0000
Subject: [llvm-commits] [llvm] r114688 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20100923194204.03BE82A6C12C@llvm.org>

Author: evancheng
Date: Thu Sep 23 14:42:03 2010
New Revision: 114688

URL: http://llvm.org/viewvc/llvm-project?rev=114688&view=rev
Log:
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114688&r1=114687&r2=114688&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Sep 23 14:42:03 2010
@@ -284,9 +284,11 @@
       LastInst->eraseFromParent();
       LastInst = SecondLastInst;
       LastOpc = LastInst->getOpcode();
-      if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
-        break;
-      else {
+      if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
+        // Return now the only terminator is an unconditional branch.
+        TBB = LastInst->getOperand(0).getMBB();
+        return false;
+      } else {
         SecondLastInst = I;
         SecondLastOpc = SecondLastInst->getOpcode();
       }



From grosbach at apple.com  Thu Sep 23 14:42:17 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 19:42:17 -0000
Subject: [llvm-commits] [llvm] r114689 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100923194217.A5C642A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 14:42:17 2010
New Revision: 114689

URL: http://llvm.org/viewvc/llvm-project?rev=114689&view=rev
Log:
never mind. I can't read, apparently

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114689&r1=114688&r2=114689&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 14:42:17 2010
@@ -1729,7 +1729,7 @@
     // FIXME: Remove this special case when they do.
     if (!Subtarget->isTargetDarwin()) {
       //.long 0xe7ffdefe ${:comment} trap
-      uint32_t Val = 0xe7ffdefeeUL;
+      uint32_t Val = 0xe7ffdefeUL;
       OutStreamer.AddComment("trap");
       OutStreamer.EmitIntValue(Val, 4);
       return;



From grosbach at apple.com  Thu Sep 23 14:43:52 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 12:43:52 -0700
Subject: [llvm-commits] [llvm] r114684 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
In-Reply-To: <8ECEB833-F8BE-49FF-88CD-128F3FB0B154@apple.com>
References: <20100923185726.7CBA62A6C12C@llvm.org>
	<8ECEB833-F8BE-49FF-88CD-128F3FB0B154@apple.com>
Message-ID: <E383EAC9-EDEF-4D31-AF59-883387673922@apple.com>


On Sep 23, 2010, at 12:34 PM, Jim Grosbach wrote:

> 
> On Sep 23, 2010, at 11:57 AM, Benjamin Kramer wrote:
> 
>> Author: d0k
>> Date: Thu Sep 23 13:57:26 2010
>> New Revision: 114684
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=114684&view=rev
>> Log:
>> Unbreak build. Jim, please review.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114684&r1=114683&r2=114684&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 13:57:26 2010
>> @@ -1216,7 +1216,7 @@
>>  // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
>>  //        Need a way to ask "isTargetDarwin()" there, first, though.
>>  if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
>> -    OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
>> +    OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
>>  } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
>>    OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
>>  } else
>> @@ -1729,7 +1729,7 @@
>>    // FIXME: Remove this special case when they do.
>>    if (!Subtarget->isTargetDarwin()) {
>>      //.long 0xe7ffdefe ${:comment} trap
>> -      uint32_t Val = 0xe7ffdefee;
>> +      uint32_t Val = 0xe7ffdefe;
> 
> The value was correct before. Clang is just being picky about the constant type. Not sure why I can't reproduce locally; I am building with clang. Odd. From the bot emails, looks like it only issues that diagnostic for this line on non-Darwin hosts?

Never mind me. I can't count. You were right.

> 
> Fixed the value in r114687, with an explicit "UL" suffix on the constant this time. Hopefully the bots will like that...
> 
>>      OutStreamer.AddComment("trap");
>>      OutStreamer.EmitIntValue(Val, 4);
>>      return;
>> @@ -1740,8 +1740,8 @@
>>    // Non-Darwin binutils don't yet support the "trap" mnemonic.
>>    // FIXME: Remove this special case when they do.
>>    if (!Subtarget->isTargetDarwin()) {
>> -      //.long 0xe7ffdefe ${:comment} trap
>> -      uint32_t Val = 0xdefe;
>> +      //.short 57086 ${:comment} trap
>> +      uint16_t Val = 0xdefe;
>>      OutStreamer.AddComment("trap");
>>      OutStreamer.EmitIntValue(Val, 2);
>>      return;
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From benny.kra at googlemail.com  Thu Sep 23 14:46:12 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 23 Sep 2010 21:46:12 +0200
Subject: [llvm-commits] [llvm] r114684 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
In-Reply-To: <8ECEB833-F8BE-49FF-88CD-128F3FB0B154@apple.com>
References: <20100923185726.7CBA62A6C12C@llvm.org>
	<8ECEB833-F8BE-49FF-88CD-128F3FB0B154@apple.com>
Message-ID: <246E5EAF-1AA8-4F52-864E-88014BDCC53C@gmail.com>


On 23.09.2010, at 21:34, Jim Grosbach wrote:

> 
> On Sep 23, 2010, at 11:57 AM, Benjamin Kramer wrote:
> 
>> Author: d0k
>> Date: Thu Sep 23 13:57:26 2010
>> New Revision: 114684
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=114684&view=rev
>> Log:
>> Unbreak build. Jim, please review.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114684&r1=114683&r2=114684&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 13:57:26 2010
>> @@ -1216,7 +1216,7 @@
>>  // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
>>  //        Need a way to ask "isTargetDarwin()" there, first, though.
>>  if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
>> -    OS << "\t.long\t2147348462\t\t" << MAI->getCommentString() << "trap";
>> +    OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
>>  } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
>>    OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
>>  } else
>> @@ -1729,7 +1729,7 @@
>>    // FIXME: Remove this special case when they do.
>>    if (!Subtarget->isTargetDarwin()) {
>>      //.long 0xe7ffdefe ${:comment} trap
>> -      uint32_t Val = 0xe7ffdefee;
>> +      uint32_t Val = 0xe7ffdefe;
> 
> The value was correct before. Clang is just being picky about the constant type. Not sure why I can't reproduce locally; I am building with clang. Odd. From the bot emails, looks like it only issues that diagnostic for this line on non-Darwin hosts?
> 
> Fixed the value in r114687, with an explicit "UL" suffix on the constant this time. Hopefully the bots will like that...

You had 3 different values in your code.

1. 0x7ffdefee (.long\t2147348462)
2. 0xe7ffdefe (in the comment, which I believe is the correct one)
3. 0xe7ffdefee (the buildbots complained about this one, doesn't even fit in 32 bits)

You reintroduced #3 in r114687. I don't think that's right, it will truncate to #1.

From baldrick at free.fr  Thu Sep 23 14:50:47 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 23 Sep 2010 21:50:47 +0200
Subject: [llvm-commits] [www] r114668 -
	/www/trunk/devmtg/2010-11/index.html
In-Reply-To: <20100923172531.361952A6C12C@llvm.org>
References: <20100923172531.361952A6C12C@llvm.org>
Message-ID: <4C9BAF97.4020207@free.fr>

Hi Tanya,

> +<p>There will be some funding for active contributors or students to attend the event. hose who are funded are required to present at the meeting and may have other requirements from their sponsor (ie. writing a blog post, etc).</p>

hose who are funded -> Those who are funded

Ciao,

Duncan.

From rafael.espindola at gmail.com  Thu Sep 23 14:55:14 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Sep 2010 19:55:14 -0000
Subject: [llvm-commits] [llvm] r114690 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/weak.s
Message-ID: <20100923195514.5C4C62A6C12C@llvm.org>

Author: rafael
Date: Thu Sep 23 14:55:14 2010
New Revision: 114690

URL: http://llvm.org/viewvc/llvm-project?rev=114690&view=rev
Log:
Correctly handle weak undefined symbols. Before we would get a invalid binding
(2 == STB_WEAK | STB_GLOBAL).

Added:
    llvm/trunk/test/MC/ELF/weak.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114690&r1=114689&r2=114690&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 23 14:55:14 2010
@@ -43,6 +43,20 @@
   return Type;
 }
 
+static unsigned GetBinding(const MCSymbolData &SD) {
+  uint32_t Binding = (SD.getFlags() & (0xf << ELF_STB_Shift)) >> ELF_STB_Shift;
+  assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL ||
+         Binding == ELF::STB_WEAK);
+  return Binding;
+}
+
+static void SetBinding(MCSymbolData &SD, unsigned Binding) {
+  assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL ||
+         Binding == ELF::STB_WEAK);
+  uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STB_Shift);
+  SD.setFlags(OtherFlags | (Binding << ELF_STB_Shift));
+}
+
 namespace {
 
   class ELFObjectWriterImpl {
@@ -460,16 +474,15 @@
     assert((Data.getFlags() & ELF_STB_Global) &&
            "External symbol requires STB_GLOBAL flag");
     WriteSymbol(F, MSD, Layout);
-    if ((Data.getFlags() & (0xf << ELF_STB_Shift)) == ELF_STB_Local)
+    if (GetBinding(Data) == ELF::STB_LOCAL)
       LastLocalSymbolIndex++;
   }
 
   for (unsigned i = 0, e = UndefinedSymbolData.size(); i != e; ++i) {
     ELFSymbolData &MSD = UndefinedSymbolData[i];
     MCSymbolData &Data = *MSD.SymbolData;
-    Data.setFlags(Data.getFlags() | ELF_STB_Global);
     WriteSymbol(F, MSD, Layout);
-    if ((Data.getFlags() & (0xf << ELF_STB_Shift)) == ELF_STB_Local)
+    if (GetBinding(Data) == ELF::STB_LOCAL)
       LastLocalSymbolIndex++;
   }
 }
@@ -682,8 +695,10 @@
       ExternalSymbolData.push_back(MSD);
     } else if (Symbol.isUndefined()) {
       MSD.SectionIndex = ELF::SHN_UNDEF;
-      // XXX: for some reason we dont Emit* this
-      it->setFlags(it->getFlags() | ELF_STB_Global);
+      // FIXME: Undefined symbols are global, but this is the first place we
+      // are able to set it.
+      if (GetBinding(*it) == ELF::STB_LOCAL)
+        SetBinding(*it, ELF::STB_GLOBAL);
       UndefinedSymbolData.push_back(MSD);
     } else if (Symbol.isAbsolute()) {
       MSD.SectionIndex = ELF::SHN_ABS;

Added: llvm/trunk/test/MC/ELF/weak.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/weak.s?rev=114690&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/weak.s (added)
+++ llvm/trunk/test/MC/ELF/weak.s Thu Sep 23 14:55:14 2010
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  | FileCheck %s
+
+// Test that this produces a weak undefined symbol.
+
+	.weak	foo
+        .long   foo
+
+//CHECK:       (('st_name', 1) # 'foo'
+//CHECK-NEXT:   ('st_bind', 2)
+//CHECK-NEXT:   ('st_type', 0)
+//CHECK-NEXT:   ('st_other', 0)
+//CHECK-NEXT:   ('st_shndx', 0)
+//CHECK-NEXT:   ('st_value', 0)
+//CHECK-NEXT:   ('st_size', 0)



From wdietz2 at illinois.edu  Thu Sep 23 15:41:18 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 23 Sep 2010 20:41:18 -0000
Subject: [llvm-commits] [poolalloc] r114692 - in
 /poolalloc/trunk/test/dsa/td: extern.ll extern2.ll extern3.ll
 extern_global.ll
Message-ID: <20100923204118.2F9272A6C12C@llvm.org>

Author: wdietz2
Date: Thu Sep 23 15:41:17 2010
New Revision: 114692

URL: http://llvm.org/viewvc/llvm-project?rev=114692&view=rev
Log:
Update tests to also verify the 'External' flag is set correctly.

Modified:
    poolalloc/trunk/test/dsa/td/extern.ll
    poolalloc/trunk/test/dsa/td/extern2.ll
    poolalloc/trunk/test/dsa/td/extern3.ll
    poolalloc/trunk/test/dsa/td/extern_global.ll

Modified: poolalloc/trunk/test/dsa/td/extern.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern.ll?rev=114692&r1=114691&r2=114692&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern.ll Thu Sep 23 15:41:17 2010
@@ -5,29 +5,29 @@
 ;  once the interprocedural passes run.
 ;--calling a function that calls an undefined (external) function.
 ;  Should be incomplete, tests very basic tracking.
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrViaExtern+I"
-
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrExtern+I"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr-I"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrViaExtern+I"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I-E"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrViaExtern+IE"
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"

Modified: poolalloc/trunk/test/dsa/td/extern2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern2.ll?rev=114692&r1=114691&r2=114692&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern2.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern2.ll Thu Sep 23 15:41:17 2010
@@ -1,22 +1,22 @@
 ;Here we get a pointer from an external function and pass it to a callee.
 ;We then test that the flags on that pointer are set appropriately.
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "takesPointer:ptr+IE"
 
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "takesPointer:ptr+IE"
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+IE"
 
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "takesPointer:ptr+IE"
 
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "takesPointer:ptr+IE"
 
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr+I"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "takesPointer:ptr+IE"
 
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"

Modified: poolalloc/trunk/test/dsa/td/extern3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern3.ll?rev=114692&r1=114691&r2=114692&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern3.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern3.ll Thu Sep 23 15:41:17 2010
@@ -12,7 +12,7 @@
 
 ;This should be marked incomplete and external due to the
 ;unification-based nature of DSA.
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointer:ptr+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointer:ptr+IE"
 define i32* @getPointer() nounwind {
 entry:
   %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
@@ -22,14 +22,14 @@
 
 ;This should be marked incomplete and external due to the
 ;unification-based nature of DSA.
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+IE"
 define i32 @takesPointer(i32* %ptr) nounwind {
 entry:
   %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
   ret i32 %0
 }
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointerInternal:ptr-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointerInternal:ptr-IE"
 define internal i32* @getPointerInternal() nounwind {
 entry:
   %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
@@ -37,7 +37,7 @@
   ret i32* %ptr
 }
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointerInternal:ptr-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointerInternal:ptr-IE"
 define internal i32 @takesPointerInternal(i32* %ptr) nounwind {
 entry:
   %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
@@ -52,8 +52,8 @@
   ret i32 0
 }
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:get+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:take+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:get+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:take+IE"
 define void @checkExterns() nounwind {
   %get = tail call i32* ()* @getPointerExtern() nounwind ; <i32*> [#uses=0]
   %1 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
@@ -63,8 +63,8 @@
   ret void
 }
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get+I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take+I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take+IE"
 define void @checkExternals() nounwind {
 entry:
   %get = tail call i32* ()* @getPointer() nounwind ; <i32*> [#uses=0]
@@ -75,8 +75,8 @@
   ret void
 }
 
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:get-I"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:take-I"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:get-IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:take-IE"
 define void @checkInternals() nounwind {
 entry:
   %get = tail call i32* ()* @getPointerInternal() nounwind ; <i32*> [#uses=0]

Modified: poolalloc/trunk/test/dsa/td/extern_global.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern_global.ll?rev=114692&r1=114691&r2=114692&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern_global.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern_global.ll Thu Sep 23 15:41:17 2010
@@ -2,22 +2,23 @@
 ;This tests how DSA handles external globals and their completeness in TD.
 
 ; Externally visible globals should be incomplete
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalInt+I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalInt+GIE
 ; Externally visible global and what it points to should be incomplete
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr+I
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr:0+I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr+GIE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr:0+GIE
 ; Externally visible global and what it points to should be incomplete,
 ; this time with a struct and point to some stack memory...
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers+I
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8+I
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8:8+I
-;RUN: dsaopt %s -dsa-td -analyze -check-same-node=globalStructWithPointers:8,globalStructWithPointers:8:8
-; Globals that aren't marked 'external' shouldn't be incomplete
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal-I
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags internalGlobal-I
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers+GIE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8+IE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8:8+IE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags main:s+IES
+; Globals that aren't marked 'external' shouldn't be incomplete (or external)
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal+G-IE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags internalGlobal+G-IE
 ; Check some edges of the graph
 ;RUN: dsaopt %s -dsa-td -analyze -check-same-node=normalGlobal:0,globalIntPtr
 ;RUN: dsaopt %s -dsa-td -analyze -check-same-node=internalGlobal:0,normalGlobal
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=globalStructWithPointers:8,globalStructWithPointers:8:8
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"



From atrick at apple.com  Thu Sep 23 15:26:45 2010
From: atrick at apple.com (Andrew Trick)
Date: Thu, 23 Sep 2010 20:26:45 -0000
Subject: [llvm-commits] [llvm] r114691 - in /llvm/trunk/docs:
	GettingStarted.html TestingGuide.html
Message-ID: <20100923202645.4999C2A6C12C@llvm.org>

Author: atrick
Date: Thu Sep 23 15:26:44 2010
New Revision: 114691

URL: http://llvm.org/viewvc/llvm-project?rev=114691&view=rev
Log:
Fix Getting Started docs.
configure expects LLVM Test Suite to be in projects/test-suite.
Made the "getting started" and "testing infrastructure" docs internally consistent.
Avoid confusion between llvm-test and llvm/test.

Modified:
    llvm/trunk/docs/GettingStarted.html
    llvm/trunk/docs/TestingGuide.html

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=114691&r1=114690&r2=114691&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Thu Sep 23 15:26:44 2010
@@ -44,7 +44,7 @@
       <li><a href="#projects"><tt>llvm/projects</tt></a></li>
       <li><a href="#runtime"><tt>llvm/runtime</tt></a></li>
       <li><a href="#test"><tt>llvm/test</tt></a></li>
-      <li><a href="#llvmtest"><tt>llvm-test</tt></a></li>
+      <li><a href="#test-suite"><tt>test-suite</tt></a></li>
       <li><a href="#tools"><tt>llvm/tools</tt></a></li>
       <li><a href="#utils"><tt>llvm/utils</tt></a></li>
       <li><a href="#win32"><tt>llvm/win32</tt></a></li>
@@ -80,11 +80,12 @@
 <p>Welcome to LLVM! In order to get started, you first need to know some
 basic information.</p>
 
-<p>First, LLVM comes in two pieces. The first piece is the LLVM suite. This
-contains all of the tools, libraries, and header files needed to use the low
-level virtual machine.  It contains an assembler, disassembler, bitcode
-analyzer and bitcode optimizer.  It also contains a test suite that can be
-used to test the LLVM tools and the GCC front end.</p>
+<p>First, LLVM comes in three pieces. The first piece is the LLVM
+suite. This contains all of the tools, libraries, and header files
+needed to use the low level virtual machine.  It contains an
+assembler, disassembler, bitcode analyzer and bitcode optimizer.  It
+also contains basic regression tests that can be used to test the LLVM
+tools and the GCC front end.</p>
 
 <p>The second piece is the GCC front end.  This component provides a version of
 GCC that compiles C and C++ code into LLVM bitcode.  Currently, the GCC front
@@ -93,7 +94,7 @@
 from the LLVM suite.</p>
 
 <p>
-There is a third, optional piece called llvm-test.  It is a suite of programs
+There is a third, optional piece called Test Suite.  It is a suite of programs
 with a testing harness that can be used to further test LLVM's functionality
 and performance.
 </p>
@@ -142,6 +143,7 @@
       <li><tt>cd <i>where-you-want-llvm-to-live</i></tt>
       <li><tt>cd llvm/projects</tt>
       <li><tt>gunzip --stdout llvm-test-<i>version</i>.tar.gz | tar -xvf -</tt>
+      <li><tt>mv llvm-test-<i>version</i> test-suite</tt>
     </ol></li>
 
   </ul></li>
@@ -162,7 +164,7 @@
         <p>Optionally, specify for <i>directory</i> the full pathname of the 
         C/C++ front end installation to use with this LLVM configuration. If
         not specified, the PATH will be searched.  This is only needed if you
-        want to run the testsuite or do some special kinds of LLVM builds.</p></li>
+        want to run test-suite or do some special kinds of LLVM builds.</p></li>
         <li><tt>--enable-spec2000=<i>directory</i></tt>
             <p>Enable the SPEC2000 benchmarks for testing.  The SPEC2000
             benchmarks should be available in
@@ -684,7 +686,7 @@
   <dd>Source release for the LLVM libraries and tools.<br></dd>
 
   <dt><tt>llvm-test-x.y.tar.gz</tt></dt>
-  <dd>Source release for the LLVM test suite.</dd>
+  <dd>Source release for the LLVM test-suite.</dd>
 
   <dt><tt>llvm-gcc-4.2-x.y.source.tar.gz</tt></dt>
   <dd>Source release of the llvm-gcc-4.2 front end.  See README.LLVM in the root
@@ -751,7 +753,7 @@
 <div class="doc_code">
 <pre>
 % cd llvm/projects
-% svn co http://llvm.org/svn/llvm-project/test-suite/trunk llvm-test
+% svn co http://llvm.org/svn/llvm-project/test-suite/trunk test-suite
 </pre>
 </div>
 
@@ -774,7 +776,7 @@
 
 <p>Before configuring and compiling the LLVM suite (or if you want to use just the LLVM
 GCC front end) you can optionally extract the front end from the binary distribution.
-It is used for running the llvm-test testsuite and for compiling C/C++ programs.  Note that
+It is used for running the LLVM test-suite and for compiling C/C++ programs.  Note that
 you can optionally <a href="GCCFEBuildInstrs.html">build llvm-gcc yourself</a> after building the
 main LLVM repository.</p>
 
@@ -795,9 +797,9 @@
 
 <p>If you now want to build LLVM from source, when you configure LLVM, it will 
 automatically detect <tt>llvm-gcc</tt>'s presence (if it is in your path) enabling its
-use in llvm-test.  Note that you can always build or install <tt>llvm-gcc</tt> at any
+use in test-suite.  Note that you can always build or install <tt>llvm-gcc</tt> at any
 point after building the main LLVM repository: just reconfigure llvm and 
-llvm-test will pick it up.
+test-suite will pick it up.
 </p>
 
 <p>As a convenience for Windows users, the front end binaries for MinGW/x86 include
@@ -1348,7 +1350,7 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection"><a name="llvmtest"><tt>test-suite</tt></a></div>
+<div class="doc_subsection"><a name="test-suite"><tt>test-suite</tt></a></div>
 <div class="doc_text">
   <p>This is not a directory in the normal llvm module; it is a separate
   Subversion
@@ -1408,7 +1410,7 @@
 
   <dt><tt><b>llvm-ld</b></tt></dt>
   <dd><tt>llvm-ld</tt> is a general purpose and extensible linker for LLVM. 
-  This is the linker invoked by <tt>llvmc</tt>. It performsn standard link time
+  This is the linker invoked by <tt>llvmc</tt>. It performs standard link time
   optimizations and allows optimization modules to be loaded and run so that 
   language specific optimizations can be applied at link time.</dd>
 

Modified: llvm/trunk/docs/TestingGuide.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TestingGuide.html?rev=114691&r1=114690&r2=114691&view=diff
==============================================================================
--- llvm/trunk/docs/TestingGuide.html (original)
+++ llvm/trunk/docs/TestingGuide.html Thu Sep 23 15:26:44 2010
@@ -40,7 +40,7 @@
       <li><a href="#testsuiteexternal">Configuring External Tests</a></li>
       <li><a href="#testsuitetests">Running different tests</a></li>
       <li><a href="#testsuiteoutput">Generating test output</a></li>
-      <li><a href="#testsuitecustom">Writing custom tests for llvm-test</a></li>
+      <li><a href="#testsuitecustom">Writing custom tests for test-suite</a></li>
    </ul>
   </li>
 </ol>
@@ -870,34 +870,34 @@
 test using the <tt>TEST</tt> variable to change what tests or run on the
 selected programs (see below for more info).</p>
 
-<p>In addition for testing correctness, the <tt>llvm-test</tt> directory also
+<p>In addition for testing correctness, the <tt>test-suite</tt> directory also
 performs timing tests of various LLVM optimizations.  It also records
 compilation times for the compilers and the JIT.  This information can be
 used to compare the effectiveness of LLVM's optimizations and code
 generation.</p>
 
-<p><tt>llvm-test</tt> tests are divided into three types of tests: MultiSource,
+<p><tt>test-suite</tt> tests are divided into three types of tests: MultiSource,
 SingleSource, and External.</p> 
 
 <ul>
-<li><tt>llvm-test/SingleSource</tt>
+<li><tt>test-suite/SingleSource</tt>
 <p>The SingleSource directory contains test programs that are only a single 
 source file in size.  These are usually small benchmark programs or small 
 programs that calculate a particular value.  Several such programs are grouped 
 together in each directory.</p></li>
 
-<li><tt>llvm-test/MultiSource</tt>
+<li><tt>test-suite/MultiSource</tt>
 <p>The MultiSource directory contains subdirectories which contain entire 
 programs with multiple source files.  Large benchmarks and whole applications 
 go here.</p></li>
 
-<li><tt>llvm-test/External</tt>
+<li><tt>test-suite/External</tt>
 <p>The External directory contains Makefiles for building code that is external
 to (i.e., not distributed with) LLVM.  The most prominent members of this
 directory are the SPEC 95 and SPEC 2000 benchmark suites. The <tt>External</tt>
 directory does not contain these actual tests, but only the Makefiles that know
 how to properly compile these programs from somewhere else. The presence and
-location of these external programs is configured by the llvm-test
+location of these external programs is configured by the test-suite
 <tt>configure</tt> script.</p></li>
 </ul>
 
@@ -1084,9 +1084,9 @@
 will tally counts of things you care about.</p>
 
 <p>Following this, you can set up a test and a report that collects these and
-formats them for easy viewing.  This consists of two files, an
+formats them for easy viewing.  This consists of two files, a
 "<tt>test-suite/TEST.XXX.Makefile</tt>" fragment (where XXX is the name of your
-test) and an "<tt>llvm-test/TEST.XXX.report</tt>" file that indicates how to
+test) and a "<tt>test-suite/TEST.XXX.report</tt>" file that indicates how to
 format the output into a table.  There are many example reports of various
 levels of sophistication included with the test suite, and the framework is very
 general.</p>



From bob.wilson at apple.com  Thu Sep 23 16:43:54 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 23 Sep 2010 21:43:54 -0000
Subject: [llvm-commits] [llvm] r114696 - in /llvm/trunk:
 lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/vld1.ll
 test/CodeGen/ARM/vld2.ll test/CodeGen/ARM/vld3.ll test/CodeGen/ARM/vld4.ll
Message-ID: <20100923214354.C07342A6C12C@llvm.org>

Author: bwilson
Date: Thu Sep 23 16:43:54 2010
New Revision: 114696

URL: http://llvm.org/viewvc/llvm-project?rev=114696&view=rev
Log:
Set alignment operand for NEON VLD instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/ARM/vld1.ll
    llvm/trunk/test/CodeGen/ARM/vld2.ll
    llvm/trunk/test/CodeGen/ARM/vld3.ll
    llvm/trunk/test/CodeGen/ARM/vld4.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Sep 23 16:43:54 2010
@@ -1016,6 +1016,22 @@
   EVT VT = N->getValueType(0);
   bool is64BitVector = VT.is64BitVector();
 
+  // Set the alignment.  The supported values depend on the number of
+  // registers being loaded.
+  unsigned NumRegs = NumVecs;
+  if (!is64BitVector && NumVecs < 3)
+    NumRegs *= 2;
+  unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
+  if (Alignment >= 32 && NumRegs == 4)
+    Alignment = 32;
+  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
+    Alignment = 16;
+  else if (Alignment >= 8)
+    Alignment = 8;
+  else
+    Alignment = 0;
+  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
+
   unsigned OpcodeIndex;
   switch (VT.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("unhandled vld type");

Modified: llvm/trunk/test/CodeGen/ARM/vld1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld1.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld1.ll Thu Sep 23 16:43:54 2010
@@ -2,8 +2,9 @@
 
 define <8 x i8> @vld1i8(i8* %A) nounwind {
 ;CHECK: vld1i8:
-;CHECK: vld1.8
-	%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 64 bits:
+;CHECK: vld1.8 {d0}, [r0, :64]
+	%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
 	ret <8 x i8> %tmp1
 }
 
@@ -41,8 +42,9 @@
 
 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
 ;CHECK: vld1Qi8:
-;CHECK: vld1.8
-	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vld1.8 {d0, d1}, [r0, :128]
+	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 32)
 	ret <16 x i8> %tmp1
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/vld2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld2.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld2.ll Thu Sep 23 16:43:54 2010
@@ -13,8 +13,9 @@
 
 define <8 x i8> @vld2i8(i8* %A) nounwind {
 ;CHECK: vld2i8:
-;CHECK: vld2.8
-	%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vld2.8 {d0, d1}, [r0, :64]
+	%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
         %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
         %tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -23,9 +24,10 @@
 
 define <4 x i16> @vld2i16(i16* %A) nounwind {
 ;CHECK: vld2i16:
-;CHECK: vld2.16
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vld2.16 {d0, d1}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32)
         %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
         %tmp4 = add <4 x i16> %tmp2, %tmp3
@@ -56,9 +58,10 @@
 
 define <1 x i64> @vld2i64(i64* %A) nounwind {
 ;CHECK: vld2i64:
-;CHECK: vld1.64
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vld1.64 {d0, d1}, [r0, :128]
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32)
         %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
         %tmp4 = add <1 x i64> %tmp2, %tmp3
@@ -67,8 +70,9 @@
 
 define <16 x i8> @vld2Qi8(i8* %A) nounwind {
 ;CHECK: vld2Qi8:
-;CHECK: vld2.8
-	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld2.8 {d0, d1, d2, d3}, [r0, :64]
+	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
         %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
         %tmp4 = add <16 x i8> %tmp2, %tmp3
@@ -77,9 +81,10 @@
 
 define <8 x i16> @vld2Qi16(i16* %A) nounwind {
 ;CHECK: vld2Qi16:
-;CHECK: vld2.16
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld2.16 {d0, d1, d2, d3}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16)
         %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
         %tmp4 = add <8 x i16> %tmp2, %tmp3
@@ -88,9 +93,10 @@
 
 define <4 x i32> @vld2Qi32(i32* %A) nounwind {
 ;CHECK: vld2Qi32:
-;CHECK: vld2.32
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld2.32 {d0, d1, d2, d3}, [r0, :256]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64)
         %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
         %tmp4 = add <4 x i32> %tmp2, %tmp3

Modified: llvm/trunk/test/CodeGen/ARM/vld3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld3.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld3.ll Thu Sep 23 16:43:54 2010
@@ -13,8 +13,9 @@
 
 define <8 x i8> @vld3i8(i8* %A) nounwind {
 ;CHECK: vld3i8:
-;CHECK: vld3.8
-	%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 64 bits:
+;CHECK: vld3.8 {d0, d1, d2}, [r0, :64]
+	%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
         %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
         %tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -56,9 +57,10 @@
 
 define <1 x i64> @vld3i64(i64* %A) nounwind {
 ;CHECK: vld3i64:
-;CHECK: vld1.64
+;Check the alignment value.  Max for this instruction is 64 bits:
+;CHECK: vld1.64 {d0, d1, d2}, [r0, :64]
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16)
         %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
         %tmp4 = add <1 x i64> %tmp2, %tmp3
@@ -67,9 +69,10 @@
 
 define <16 x i8> @vld3Qi8(i8* %A) nounwind {
 ;CHECK: vld3Qi8:
-;CHECK: vld3.8
-;CHECK: vld3.8
-	%tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 64 bits:
+;CHECK: vld3.8 {d0, d2, d4}, [r0, :64]!
+;CHECK: vld3.8 {d1, d3, d5}, [r0, :64]
+	%tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32)
         %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
         %tmp4 = add <16 x i8> %tmp2, %tmp3

Modified: llvm/trunk/test/CodeGen/ARM/vld4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld4.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld4.ll Thu Sep 23 16:43:54 2010
@@ -13,8 +13,9 @@
 
 define <8 x i8> @vld4i8(i8* %A) nounwind {
 ;CHECK: vld4i8:
-;CHECK: vld4.8
-	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld4.8 {d0, d1, d2, d3}, [r0, :64]
+	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
         %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
         %tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -23,9 +24,10 @@
 
 define <4 x i16> @vld4i16(i16* %A) nounwind {
 ;CHECK: vld4i16:
-;CHECK: vld4.16
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld4.16 {d0, d1, d2, d3}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16)
         %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
         %tmp4 = add <4 x i16> %tmp2, %tmp3
@@ -34,9 +36,10 @@
 
 define <2 x i32> @vld4i32(i32* %A) nounwind {
 ;CHECK: vld4i32:
-;CHECK: vld4.32
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld4.32 {d0, d1, d2, d3}, [r0, :256]
 	%tmp0 = bitcast i32* %A to i8*
-	%tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32)
         %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
         %tmp4 = add <2 x i32> %tmp2, %tmp3
@@ -56,9 +59,10 @@
 
 define <1 x i64> @vld4i64(i64* %A) nounwind {
 ;CHECK: vld4i64:
-;CHECK: vld1.64
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld1.64 {d0, d1, d2, d3}, [r0, :256]
 	%tmp0 = bitcast i64* %A to i8*
-	%tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 1)
+	%tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
         %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
         %tmp4 = add <1 x i64> %tmp2, %tmp3
@@ -67,9 +71,10 @@
 
 define <16 x i8> @vld4Qi8(i8* %A) nounwind {
 ;CHECK: vld4Qi8:
-;CHECK: vld4.8
-;CHECK: vld4.8
-	%tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 1)
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vld4.8 {d0, d2, d4, d6}, [r0, :256]!
+;CHECK: vld4.8 {d1, d3, d5, d7}, [r0, :256]
+	%tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64)
         %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
         %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
         %tmp4 = add <16 x i8> %tmp2, %tmp3
@@ -78,8 +83,9 @@
 
 define <8 x i16> @vld4Qi16(i16* %A) nounwind {
 ;CHECK: vld4Qi16:
-;CHECK: vld4.16
-;CHECK: vld4.16
+;Check for no alignment specifier.
+;CHECK: vld4.16 {d0, d2, d4, d6}, [r0]!
+;CHECK: vld4.16 {d1, d3, d5, d7}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 1)
         %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0



From aggarwa4 at illinois.edu  Thu Sep 23 16:58:23 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 21:58:23 -0000
Subject: [llvm-commits] [poolalloc] r114698 -
	/poolalloc/trunk/lib/DSA/Local.cpp
Message-ID: <20100923215823.E7A352A6C12D@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 16:58:23 2010
New Revision: 114698

URL: http://llvm.org/viewvc/llvm-project?rev=114698&view=rev
Log:
Change to correctly fold arrays of structs, modulo the size of the struct that they contain, and correcty set the array flag

Modified:
    poolalloc/trunk/lib/DSA/Local.cpp

Modified: poolalloc/trunk/lib/DSA/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=114698&r1=114697&r2=114698&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Local.cpp (original)
+++ poolalloc/trunk/lib/DSA/Local.cpp Thu Sep 23 16:58:23 2010
@@ -426,6 +426,7 @@
 
 
 void GraphBuilder::visitBitCastInst(BitCastInst &I) {
+  
   if (!isa<PointerType>(I.getType())) return; // Only pointers
   DSNodeHandle Ptr = getValueDest(I.getOperand(0));
   if (Ptr.isNull()) return;
@@ -559,9 +560,25 @@
   for (gep_type_iterator I = gep_type_begin(GEP), E = gep_type_end(GEP);
        I != E; ++I)
     if (const StructType *STy = dyn_cast<StructType>(*I)) {
+      // indexing into a structure
+      // next index must be a constant
       const ConstantInt* CUI = cast<ConstantInt>(I.getOperand());
       int FieldNo = CUI->getSExtValue();
+      // increment the offset by the actual byte offset being accessed
       Offset += (unsigned)TD.getStructLayout(STy)->getElementOffset(FieldNo);
+      
+    } else if(isa<ArrayType>(*I)) {
+      // indexing into an array.
+      Value.getNode()->setArrayMarker();
+      
+      // Find if the DSNode belongs to the array
+      // If not fold.
+      if(Value.getOffset() || Offset != 0) {
+        Value.getNode()->foldNodeCompletely();
+        Value.getNode();
+        Offset = 0;
+        break;
+      } 
     } else if (isa<PointerType>(*I)) {
       //
       // Unless we're advancing the pointer by zero bytes via array indexing,
@@ -571,6 +588,7 @@
       // Note that we break out of the loop if we fold the node.  Once
       // something is folded, all values within it are considered to alias.
       //
+      
       if (!isa<Constant>(I.getOperand()) ||
           !cast<Constant>(I.getOperand())->isNullValue()) {
         Value.getNode()->setArrayMarker();



From aggarwa4 at illinois.edu  Thu Sep 23 17:01:41 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Sep 2010 22:01:41 -0000
Subject: [llvm-commits] [poolalloc] r114699 - in
 /poolalloc/trunk/test/dsa/local: arrayPointers.ll arrayPointers1.ll
 arrayPointers2.ll
Message-ID: <20100923220141.716FD2A6C12D@llvm.org>

Author: aggarwa4
Date: Thu Sep 23 17:01:41 2010
New Revision: 114699

URL: http://llvm.org/viewvc/llvm-project?rev=114699&view=rev
Log:
Tests for arrays of structs

Added:
    poolalloc/trunk/test/dsa/local/arrayPointers.ll
    poolalloc/trunk/test/dsa/local/arrayPointers1.ll
    poolalloc/trunk/test/dsa/local/arrayPointers2.ll

Added: poolalloc/trunk/test/dsa/local/arrayPointers.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrayPointers.ll?rev=114699&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrayPointers.ll (added)
+++ poolalloc/trunk/test/dsa/local/arrayPointers.ll Thu Sep 23 17:01:41 2010
@@ -0,0 +1,103 @@
+;2D array using pointers. Should be folded
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array:0,FoldedVOIDArray
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array:0:0,FoldedVOIDArray
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array,0:i32**
+
+; ModuleID = 'arrayPointers.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @main() nounwind {
+entry:
+  %nrows = alloca i32                             ; <i32*> [#uses=4]
+  %ncolumns = alloca i32                          ; <i32*> [#uses=3]
+  %i = alloca i32                                 ; <i32*> [#uses=11]
+  %array = alloca i32**                           ; <i32***> [#uses=3]
+  %j = alloca i32                                 ; <i32*> [#uses=6]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 10, i32* %nrows, align 4
+  store i32 10, i32* %ncolumns, align 4
+  %0 = load i32* %nrows, align 4                  ; <i32> [#uses=1]
+  %1 = sext i32 %0 to i64                         ; <i64> [#uses=1]
+  %2 = mul i64 %1, 8                              ; <i64> [#uses=1]
+  %3 = call noalias i8* @malloc(i64 %2) nounwind  ; <i8*> [#uses=1]
+  %4 = bitcast i8* %3 to i32**                    ; <i32**> [#uses=1]
+  store i32** %4, i32*** %array, align 8
+  store i32 0, i32* %i, align 4
+  br label %bb1
+
+bb:                                               ; preds = %bb1
+  %5 = load i32* %ncolumns, align 4               ; <i32> [#uses=1]
+  %6 = sext i32 %5 to i64                         ; <i64> [#uses=1]
+  %7 = mul i64 %6, 4                              ; <i64> [#uses=1]
+  %8 = call noalias i8* @malloc(i64 %7) nounwind  ; <i8*> [#uses=1]
+  %9 = bitcast i8* %8 to i32*                     ; <i32*> [#uses=1]
+  %10 = load i32*** %array, align 8               ; <i32**> [#uses=1]
+  %11 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %12 = sext i32 %11 to i64                       ; <i64> [#uses=1]
+  %13 = getelementptr inbounds i32** %10, i64 %12 ; <i32**> [#uses=1]
+  store i32* %9, i32** %13, align 1
+  %14 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %15 = add nsw i32 %14, 1                        ; <i32> [#uses=1]
+  store i32 %15, i32* %i, align 4
+  br label %bb1
+
+bb1:                                              ; preds = %bb, %entry
+  %16 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %17 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %18 = icmp slt i32 %16, %17                     ; <i1> [#uses=1]
+  br i1 %18, label %bb, label %bb2
+
+bb2:                                              ; preds = %bb1
+  store i32 0, i32* %i, align 4
+  br label %bb7
+
+bb3:                                              ; preds = %bb7
+  store i32 0, i32* %j, align 4
+  br label %bb5
+
+bb4:                                              ; preds = %bb5
+  %19 = load i32*** %array, align 8               ; <i32**> [#uses=1]
+  %20 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %21 = sext i32 %20 to i64                       ; <i64> [#uses=1]
+  %22 = getelementptr inbounds i32** %19, i64 %21 ; <i32**> [#uses=1]
+  %23 = load i32** %22, align 1                   ; <i32*> [#uses=1]
+  %24 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %25 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %26 = add nsw i32 %24, %25                      ; <i32> [#uses=1]
+  %27 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %28 = sext i32 %27 to i64                       ; <i64> [#uses=1]
+  %29 = getelementptr inbounds i32* %23, i64 %28  ; <i32*> [#uses=1]
+  store i32 %26, i32* %29, align 1
+  %30 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %31 = add nsw i32 %30, 1                        ; <i32> [#uses=1]
+  store i32 %31, i32* %j, align 4
+  br label %bb5
+
+bb5:                                              ; preds = %bb4, %bb3
+  %32 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %33 = load i32* %ncolumns, align 4              ; <i32> [#uses=1]
+  %34 = icmp slt i32 %32, %33                     ; <i1> [#uses=1]
+  br i1 %34, label %bb4, label %bb6
+
+bb6:                                              ; preds = %bb5
+  %35 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %36 = add nsw i32 %35, 1                        ; <i32> [#uses=1]
+  store i32 %36, i32* %i, align 4
+  br label %bb7
+
+bb7:                                              ; preds = %bb6, %bb2
+  %37 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %38 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %39 = icmp slt i32 %37, %38                     ; <i1> [#uses=1]
+  br i1 %39, label %bb3, label %bb8
+
+bb8:                                              ; preds = %bb7
+  br label %return
+
+return:                                           ; preds = %bb8
+  ret void
+}
+
+declare noalias i8* @malloc(i64) nounwind

Added: poolalloc/trunk/test/dsa/local/arrayPointers1.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrayPointers1.ll?rev=114699&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrayPointers1.ll (added)
+++ poolalloc/trunk/test/dsa/local/arrayPointers1.ll Thu Sep 23 17:01:41 2010
@@ -0,0 +1,94 @@
+; 2D array as array of pointers. Array should not be folded.
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array,0:i32*Array
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array:0,FoldedVOIDArray
+
+; ModuleID = 'arrayPointers1.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @main() nounwind {
+entry:
+  %nrows = alloca i32                             ; <i32*> [#uses=3]
+  %ncolumns = alloca i32                          ; <i32*> [#uses=3]
+  %i = alloca i32                                 ; <i32*> [#uses=11]
+  %array = alloca [10 x i32*]                     ; <[10 x i32*]*> [#uses=2]
+  %j = alloca i32                                 ; <i32*> [#uses=6]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 10, i32* %nrows, align 4
+  store i32 10, i32* %ncolumns, align 4
+  store i32 0, i32* %i, align 4
+  br label %bb1
+
+bb:                                               ; preds = %bb1
+  %0 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %1 = load i32* %ncolumns, align 4               ; <i32> [#uses=1]
+  %2 = sext i32 %1 to i64                         ; <i64> [#uses=1]
+  %3 = mul i64 %2, 4                              ; <i64> [#uses=1]
+  %4 = call noalias i8* @malloc(i64 %3) nounwind  ; <i8*> [#uses=1]
+  %5 = bitcast i8* %4 to i32*                     ; <i32*> [#uses=1]
+  %6 = sext i32 %0 to i64                         ; <i64> [#uses=1]
+  %7 = getelementptr inbounds [10 x i32*]* %array, i64 0, i64 %6 ; <i32**> [#uses=1]
+  store i32* %5, i32** %7, align 8
+  %8 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %9 = add nsw i32 %8, 1                          ; <i32> [#uses=1]
+  store i32 %9, i32* %i, align 4
+  br label %bb1
+
+bb1:                                              ; preds = %bb, %entry
+  %10 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %11 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %12 = icmp slt i32 %10, %11                     ; <i1> [#uses=1]
+  br i1 %12, label %bb, label %bb2
+
+bb2:                                              ; preds = %bb1
+  store i32 0, i32* %i, align 4
+  br label %bb7
+
+bb3:                                              ; preds = %bb7
+  store i32 0, i32* %j, align 4
+  br label %bb5
+
+bb4:                                              ; preds = %bb5
+  %13 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %14 = sext i32 %13 to i64                       ; <i64> [#uses=1]
+  %15 = getelementptr inbounds [10 x i32*]* %array, i64 0, i64 %14 ; <i32**> [#uses=1]
+  %16 = load i32** %15, align 8                   ; <i32*> [#uses=1]
+  %17 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %18 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %19 = add nsw i32 %17, %18                      ; <i32> [#uses=1]
+  %20 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %21 = sext i32 %20 to i64                       ; <i64> [#uses=1]
+  %22 = getelementptr inbounds i32* %16, i64 %21  ; <i32*> [#uses=1]
+  store i32 %19, i32* %22, align 1
+  %23 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %24 = add nsw i32 %23, 1                        ; <i32> [#uses=1]
+  store i32 %24, i32* %j, align 4
+  br label %bb5
+
+bb5:                                              ; preds = %bb4, %bb3
+  %25 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %26 = load i32* %ncolumns, align 4              ; <i32> [#uses=1]
+  %27 = icmp slt i32 %25, %26                     ; <i1> [#uses=1]
+  br i1 %27, label %bb4, label %bb6
+
+bb6:                                              ; preds = %bb5
+  %28 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %29 = add nsw i32 %28, 1                        ; <i32> [#uses=1]
+  store i32 %29, i32* %i, align 4
+  br label %bb7
+
+bb7:                                              ; preds = %bb6, %bb2
+  %30 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %31 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %32 = icmp slt i32 %30, %31                     ; <i1> [#uses=1]
+  br i1 %32, label %bb3, label %bb8
+
+bb8:                                              ; preds = %bb7
+  br label %return
+
+return:                                           ; preds = %bb8
+  ret void
+}
+
+declare noalias i8* @malloc(i64) nounwind

Added: poolalloc/trunk/test/dsa/local/arrayPointers2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/arrayPointers2.ll?rev=114699&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/local/arrayPointers2.ll (added)
+++ poolalloc/trunk/test/dsa/local/arrayPointers2.ll Thu Sep 23 17:01:41 2010
@@ -0,0 +1,123 @@
+; 2D array as array of pointers. Array should not be folded.
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array:0,FoldedVOIDArray
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:array,0:%\struct.structType*Array
+
+
+; ModuleID = 'arrayPointers2.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.structType = type { i32, i32, float }
+
+define void @main() nounwind {
+entry:
+  %nrows = alloca i32                             ; <i32*> [#uses=3]
+  %ncolumns = alloca i32                          ; <i32*> [#uses=3]
+  %i = alloca i32                                 ; <i32*> [#uses=14]
+  %array = alloca [10 x %struct.structType*]      ; <[10 x %struct.structType*]*> [#uses=4]
+  %j = alloca i32                                 ; <i32*> [#uses=9]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 10, i32* %nrows, align 4
+  store i32 10, i32* %ncolumns, align 4
+  store i32 0, i32* %i, align 4
+  br label %bb1
+
+bb:                                               ; preds = %bb1
+  %0 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %1 = load i32* %ncolumns, align 4               ; <i32> [#uses=1]
+  %2 = sext i32 %1 to i64                         ; <i64> [#uses=1]
+  %3 = mul i64 %2, 12                             ; <i64> [#uses=1]
+  %4 = call noalias i8* @malloc(i64 %3) nounwind  ; <i8*> [#uses=1]
+  %5 = bitcast i8* %4 to %struct.structType*      ; <%struct.structType*> [#uses=1]
+  %6 = sext i32 %0 to i64                         ; <i64> [#uses=1]
+  %7 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %6 ; <%struct.structType**> [#uses=1]
+  store %struct.structType* %5, %struct.structType** %7, align 8
+  %8 = load i32* %i, align 4                      ; <i32> [#uses=1]
+  %9 = add nsw i32 %8, 1                          ; <i32> [#uses=1]
+  store i32 %9, i32* %i, align 4
+  br label %bb1
+
+bb1:                                              ; preds = %bb, %entry
+  %10 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %11 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %12 = icmp slt i32 %10, %11                     ; <i1> [#uses=1]
+  br i1 %12, label %bb, label %bb2
+
+bb2:                                              ; preds = %bb1
+  store i32 0, i32* %i, align 4
+  br label %bb7
+
+bb3:                                              ; preds = %bb7
+  store i32 0, i32* %j, align 4
+  br label %bb5
+
+bb4:                                              ; preds = %bb5
+  %13 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %14 = sext i32 %13 to i64                       ; <i64> [#uses=1]
+  %15 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %14 ; <%struct.structType**> [#uses=1]
+  %16 = load %struct.structType** %15, align 8    ; <%struct.structType*> [#uses=1]
+  %17 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %18 = sext i32 %17 to i64                       ; <i64> [#uses=1]
+  %19 = getelementptr inbounds %struct.structType* %16, i64 %18 ; <%struct.structType*> [#uses=1]
+  %20 = getelementptr inbounds %struct.structType* %19, i32 0, i32 0 ; <i32*> [#uses=1]
+  %21 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  store i32 %21, i32* %20, align 4
+  %22 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %23 = add nsw i32 %22, 1                        ; <i32> [#uses=1]
+  store i32 %23, i32* %j, align 4
+  br label %bb5
+
+bb5:                                              ; preds = %bb4, %bb3
+  %24 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %25 = load i32* %ncolumns, align 4              ; <i32> [#uses=1]
+  %26 = icmp slt i32 %24, %25                     ; <i1> [#uses=1]
+  br i1 %26, label %bb4, label %bb6
+
+bb6:                                              ; preds = %bb5
+  %27 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %28 = sext i32 %27 to i64                       ; <i64> [#uses=1]
+  %29 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %28 ; <%struct.structType**> [#uses=1]
+  %30 = load %struct.structType** %29, align 8    ; <%struct.structType*> [#uses=1]
+  %31 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %32 = sext i32 %31 to i64                       ; <i64> [#uses=1]
+  %33 = getelementptr inbounds %struct.structType* %30, i64 %32 ; <%struct.structType*> [#uses=1]
+  %34 = getelementptr inbounds %struct.structType* %33, i32 0, i32 1 ; <i32*> [#uses=1]
+  %35 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  store i32 %35, i32* %34, align 4
+  %36 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %37 = sext i32 %36 to i64                       ; <i64> [#uses=1]
+  %38 = getelementptr inbounds [10 x %struct.structType*]* %array, i64 0, i64 %37 ; <%struct.structType**> [#uses=1]
+  %39 = load %struct.structType** %38, align 8    ; <%struct.structType*> [#uses=1]
+  %40 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %41 = sext i32 %40 to i64                       ; <i64> [#uses=1]
+  %42 = getelementptr inbounds %struct.structType* %39, i64 %41 ; <%struct.structType*> [#uses=1]
+  %43 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %44 = sitofp i32 %43 to double                  ; <double> [#uses=1]
+  %45 = fdiv double %44, 2.000000e+00             ; <double> [#uses=1]
+  %46 = load i32* %j, align 4                     ; <i32> [#uses=1]
+  %47 = sitofp i32 %46 to double                  ; <double> [#uses=1]
+  %48 = fdiv double %47, 2.000000e+00             ; <double> [#uses=1]
+  %49 = fadd double %45, %48                      ; <double> [#uses=1]
+  %50 = fptrunc double %49 to float               ; <float> [#uses=1]
+  %51 = getelementptr inbounds %struct.structType* %42, i32 0, i32 2 ; <float*> [#uses=1]
+  store float %50, float* %51, align 4
+  %52 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %53 = add nsw i32 %52, 1                        ; <i32> [#uses=1]
+  store i32 %53, i32* %i, align 4
+  br label %bb7
+
+bb7:                                              ; preds = %bb6, %bb2
+  %54 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %55 = load i32* %nrows, align 4                 ; <i32> [#uses=1]
+  %56 = icmp slt i32 %54, %55                     ; <i1> [#uses=1]
+  br i1 %56, label %bb3, label %bb8
+
+bb8:                                              ; preds = %bb7
+  br label %return
+
+return:                                           ; preds = %bb8
+  ret void
+}
+
+declare noalias i8* @malloc(i64) nounwind



From wdietz2 at illinois.edu  Thu Sep 23 17:10:30 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 23 Sep 2010 22:10:30 -0000
Subject: [llvm-commits] [poolalloc] r114700 - in /poolalloc/trunk:
 include/dsa/DSGraph.h lib/DSA/DSGraph.cpp
Message-ID: <20100923221030.7FE9C2A6C12D@llvm.org>

Author: wdietz2
Date: Thu Sep 23 17:10:30 2010
New Revision: 114700

URL: http://llvm.org/viewvc/llvm-project?rev=114700&view=rev
Log:
Calculate the 'External' flag when processing sources of external influence.

Modified:
    poolalloc/trunk/include/dsa/DSGraph.h
    poolalloc/trunk/lib/DSA/DSGraph.cpp

Modified: poolalloc/trunk/include/dsa/DSGraph.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=114700&r1=114699&r2=114700&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSGraph.h (original)
+++ poolalloc/trunk/include/dsa/DSGraph.h Thu Sep 23 17:10:30 2010
@@ -499,11 +499,13 @@
   };
   void markIncompleteNodes(unsigned Flags);
 
-  // markExternalNodes - Traverse the graph, identifying nodes that may be
+  // recalculateExternalNodes - Clear the external flag on all nodes,
+  // then traverse the graph, identifying nodes that may be
   // exposed to external code.  The sources of this happening are:
   // --Arguments and return values for external functions
   // --Arguments and return values for externally visible functions
-  void markExternalNodes(void);
+  // --Externally visible globals
+  void recalculateExternalNodes(void);
 
   // removeDeadNodes - Use a reachability analysis to eliminate subgraphs that
   // are unreachable.  This often occurs because the data structure doesn't

Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=114700&r1=114699&r2=114700&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSGraph.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSGraph.cpp Thu Sep 23 17:10:30 2010
@@ -658,14 +658,13 @@
       markIncomplete(*I);
 #endif
   // Handle all sources of external
-  markExternalNodes();
+  recalculateExternalNodes();
 
   // Mark all global nodes as incomplete.
   for (DSScalarMap::global_iterator I = ScalarMap.global_begin(),
          E = ScalarMap.global_end(); I != E; ++I)
     if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(*I))
-      if (!GV->hasInitializer() ||    // Always mark external globals incomp.
-          (!GV->isConstant() && (Flags & DSGraph::IgnoreGlobals) == 0))
+      if (!GV->isConstant() && (Flags & DSGraph::IgnoreGlobals) == 0)
         markIncompleteNode(ScalarMap[GV].getNode());
 
   // Mark any node with the VAStart flag as incomplete.
@@ -678,11 +677,21 @@
 }
 
 static void markExternalNode(DSNode *N) {
-  // FIXME: For now, we say that external is the same as incomplete as little to nothing
-  // checks or uses the External flag, and if we're to do the External flag it's as part of something
-  // else and needs more thought.  For now we simply are ensuring things that should be incomplete due to
-  // external influence are, in fact, marked incomplete.
-  markIncompleteNode(N);
+  // Stop recursion if no node, or if node already marked...
+  if (N == 0 || N->isExternalNode()) return;
+
+  // Actually mark the node
+  N->setExternalMarker();
+
+  // External also means incomplete
+  N->setIncompleteMarker();
+  
+  // FIXME: Should we 'collapse' the node as well?
+
+  // Recursively process children...
+  for (DSNode::edge_iterator ii = N->edge_begin(), ee = N->edge_end();
+       ii != ee; ++ii)
+    markExternalNode(ii->second.getNode());
 }
 
 static void markExternal(DSCallSite &Call) {
@@ -695,18 +704,17 @@
     markExternalNode(Call.getPtrArg(i).getNode());
 }
 
-// markExternalNodes - Traverse the graph, identifying nodes that may be
+// recalculateExternalNodes - Clear the external flag on all nodes,
+// then traverse the graph, identifying nodes that may be
 // exposed to external code.  The sources of this happening are:
 // --Arguments and return values for external functions
 // --Arguments and return values for externally visible functions
-//
-// FIXME: Unlike 'Incomplete' flag, the 'External' flag is never reset
-// and if done right should propagate throughout the various passes.
-// That is to say we can probably get away by not re-marking everything,
-// but instead placing just the right flag updates in just the right places.
-// However this is simpler and more likely to be correct--that kind of 
-// optimization can wait until everything works correctly.
-void DSGraph::markExternalNodes() {
+// --Externally visible globals
+void DSGraph::recalculateExternalNodes() {
+
+  // Clear the external flag (we use it as marker for recursion)
+  maskNodeTypes(~DSNode::ExternalNode);
+
   // Process all CallSites that call functions influenced by external code
   for (std::list<DSCallSite>::iterator I = FunctionCalls.begin(),
          E = FunctionCalls.end(); I != E; ++I) {
@@ -754,6 +762,18 @@
       markExternalNode(getVANodeFor(F).getNode());
     }
   }
+
+  // Now handle all external globals...
+  for (DSScalarMap::global_iterator I = ScalarMap.global_begin(),
+         E = ScalarMap.global_end(); I != E; ++I)
+    if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(*I)) {
+      // If the global is external... mark it as such!
+      // FIXME: It's unclear to me that a global we initialize
+      // can't be externally visible.  For now preserving original
+      // behavior (and additionally marking external as well as incomplete).
+      if (!GV->hasInitializer())
+        markExternalNode(ScalarMap[GV].getNode());
+    }
 }
 
 static inline void killIfUselessEdge(DSNodeHandle &Edge) {



From sabre at nondot.org  Thu Sep 23 17:34:49 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 23 Sep 2010 22:34:49 -0000
Subject: [llvm-commits] [llvm] r114701 -
	/llvm/trunk/docs/DeveloperPolicy.html
Message-ID: <20100923223449.49BA92A6C12C@llvm.org>

Author: lattner
Date: Thu Sep 23 17:34:49 2010
New Revision: 114701

URL: http://llvm.org/viewvc/llvm-project?rev=114701&view=rev
Log:
remove an obsolete section

Modified:
    llvm/trunk/docs/DeveloperPolicy.html

Modified: llvm/trunk/docs/DeveloperPolicy.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/DeveloperPolicy.html?rev=114701&r1=114700&r2=114701&view=diff
==============================================================================
--- llvm/trunk/docs/DeveloperPolicy.html (original)
+++ llvm/trunk/docs/DeveloperPolicy.html Thu Sep 23 17:34:49 2010
@@ -29,7 +29,6 @@
     <li><a href="#copyright">Copyright</a></li>
     <li><a href="#license">License</a></li>
     <li><a href="#patents">Patents</a></li>
-    <li><a href="#devagree">Developer Agreements</a></li>
   </ol></li>
 </ol>
 <div class="doc_author">Written by the LLVM Oversight Team</div>
@@ -592,21 +591,6 @@
    details.</p>
 </div>
 
-<!-- _______________________________________________________________________ -->
-<div class="doc_subsection"><a name="devagree">Developer Agreements</a></div>
-<div class="doc_text">
-<p>With regards to the LLVM copyright and licensing, developers agree to assign
-   their copyrights to UIUC for any contribution made so that the entire
-   software base can be managed by a single copyright holder.  This implies that
-   any contributions can be licensed under the license that the project
-   uses.</p>
-
-<p>When contributing code, you also affirm that you are legally entitled to
-   grant this copyright, personally or on behalf of your employer.  If the code
-   belongs to some other entity, please raise this issue with the oversight
-   group before the code is committed.</p>
-</div>
-
 <!-- *********************************************************************** -->
 <hr>
 <address>



From resistor at mac.com  Thu Sep 23 17:44:10 2010
From: resistor at mac.com (Owen Anderson)
Date: Thu, 23 Sep 2010 22:44:10 -0000
Subject: [llvm-commits] [llvm] r114702 - in /llvm/trunk:
 include/llvm/Target/Target.td include/llvm/Target/TargetInstrDesc.h
 utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h
 utils/TableGen/InstrInfoEmitter.cpp
Message-ID: <20100923224410.70EBE2A6C12C@llvm.org>

Author: resistor
Date: Thu Sep 23 17:44:10 2010
New Revision: 114702

URL: http://llvm.org/viewvc/llvm-project?rev=114702&view=rev
Log:
Add an TargetInstrDesc bit to indicate that a given instruction is a conditional move.
Not intended functionality change, as nothing uses this yet.

Modified:
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/include/llvm/Target/TargetInstrDesc.h
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.h
    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=114702&r1=114701&r2=114702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Thu Sep 23 17:44:10 2010
@@ -201,6 +201,7 @@
   bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
+  bit isConditionalMove = 0; // Is this instruction a conditional move instr?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = 0;     // Is it possible for this inst to read memory?
   bit mayStore     = 0;     // Is it possible for this inst to write memory?

Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=114702&r1=114701&r2=114702&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Thu Sep 23 17:44:10 2010
@@ -99,6 +99,7 @@
     HasOptionalDef,
     Return,
     Call,
+    ConditionalMove,
     Barrier,
     Terminator,
     Branch,
@@ -352,6 +353,12 @@
     return Flags & (1 << TID::Compare);
   }
   
+  /// isConditionalMove - Return true if this instruction can be considered a
+  /// conditional move, like CMOV on X86 or MOVCC on ARM.
+  bool isConditionalMove() const {
+    return Flags & (1 << TID::ConditionalMove);
+  }
+  
   /// isNotDuplicable - Return true if this instruction cannot be safely
   /// duplicated.  For example, if the instruction has a unique labels attached
   /// to it, duplicating it would cause multiple definition errors.

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=114702&r1=114701&r2=114702&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Thu Sep 23 17:44:10 2010
@@ -103,6 +103,7 @@
   isBranch     = R->getValueAsBit("isBranch");
   isIndirectBranch = R->getValueAsBit("isIndirectBranch");
   isCompare    = R->getValueAsBit("isCompare");
+  isConditionalMove = R->getValueAsBit("isConditionalMove");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=114702&r1=114701&r2=114702&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Thu Sep 23 17:44:10 2010
@@ -124,6 +124,7 @@
     bool isBranch;
     bool isIndirectBranch;
     bool isCompare;
+    bool isConditionalMove;
     bool isBarrier;
     bool isCall;
     bool canFoldAsLoad;

Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=114702&r1=114701&r2=114702&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Thu Sep 23 17:44:10 2010
@@ -274,6 +274,7 @@
   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1<<TID::Call)";
+  if (Inst.isConditionalMove)  OS << "|(1<<TID::ConditionalMove)";
   if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";



From resistor at mac.com  Thu Sep 23 17:57:01 2010
From: resistor at mac.com (Owen Anderson)
Date: Thu, 23 Sep 2010 22:57:01 -0000
Subject: [llvm-commits] [llvm] r114703 - in /llvm/trunk/lib/Target:
 ARM/ARMInstrInfo.td ARM/ARMInstrThumb.td ARM/ARMInstrThumb2.td
 X86/X86Instr64bit.td X86/X86InstrInfo.td
Message-ID: <20100923225701.A4AA72A6C12C@llvm.org>

Author: resistor
Date: Thu Sep 23 17:57:01 2010
New Revision: 114703

URL: http://llvm.org/viewvc/llvm-project?rev=114703&view=rev
Log:
Add isConditionalMove bits to X86 and ARM instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114703&r1=114702&r2=114703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 23 17:57:01 2010
@@ -2391,7 +2391,7 @@
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1 in {
+let neverHasSideEffects = 1, isConditionalMove = 1 in {
 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
                 IIC_iCMOVr, "mov", "\t$dst, $true",
       [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2415,7 +2415,7 @@
                 RegConstraint<"$false = $dst">, UnaryDP {
   let Inst{25} = 1;
 }
-} // neverHasSideEffects
+} // neverHasSideEffects, isConditionalMove
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=114703&r1=114702&r2=114703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Sep 23 17:57:01 2010
@@ -866,7 +866,7 @@
 
 
 // 16-bit movcc in IT blocks for Thumb2.
-let neverHasSideEffects = 1 in {
+let neverHasSideEffects = 1, isConditionalMove = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
               T1Special<{1,0,?,?}>;
@@ -874,7 +874,7 @@
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
               T1General<{1,0,0,?,?}>;
-} // neverHasSideEffects
+} // neverHasSideEffects, isConditionalMove
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114703&r1=114702&r2=114703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Sep 23 17:57:01 2010
@@ -2169,7 +2169,7 @@
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1 in {
+let neverHasSideEffects = 1, isConditionalMove = 1 in {
 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
                    "mov", ".w\t$dst, $true",
    [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2221,7 +2221,7 @@
                              (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
                              IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
                  RegConstraint<"$false = $dst">;
-} // neverHasSideEffects
+} // neverHasSideEffects, isConditionalMove
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=114703&r1=114702&r2=114703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Sep 23 17:57:01 2010
@@ -1366,7 +1366,7 @@
 } // Defs = [EFLAGS]
 
 // Conditional moves
-let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
+let isConditionalMove = 1, Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
 let isCommutable = 1 in {
 def CMOVB64rr : RI<0x42, MRMSrcReg,       // if <u, GR64 = GR64
                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@@ -1530,7 +1530,7 @@
                    "cmovno{q}\t{$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
                                      X86_COND_NO, EFLAGS))]>, TB;
-} // Constraints = "$src1 = $dst"
+} // isConditionalMove, Constraints = "$src1 = $dst"
 
 // Use sbb to materialize carry flag into a GPR.
 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114703&r1=114702&r2=114703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Sep 23 17:57:01 2010
@@ -1269,7 +1269,7 @@
 // Conditional moves
 let Uses = [EFLAGS] in {
 
-let Predicates = [HasCMov] in {
+let isConditionalMove = 1, Predicates = [HasCMov] in {
 let isCommutable = 1 in {
 def CMOVB16rr : I<0x42, MRMSrcReg,       // if <u, GR16 = GR16
                   (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
@@ -1657,7 +1657,7 @@
                    [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
                                     X86_COND_NO, EFLAGS))]>,
                   TB;
-} // Predicates = [HasCMov]
+} // isConditionalMove, Predicates = [HasCMov]
 
 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,



From grosbach at apple.com  Thu Sep 23 18:03:27 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 23:03:27 -0000
Subject: [llvm-commits] [llvm] r114705 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20100923230327.17FCB2A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 18:03:26 2010
New Revision: 114705

URL: http://llvm.org/viewvc/llvm-project?rev=114705&view=rev
Log:
Fix formatting of output .s code

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114705&r1=114704&r2=114705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 23 18:03:26 2010
@@ -2699,7 +2699,7 @@
   def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
                                    AddrModeNone, SizeSpecial, IndexModeNone,
                                    Pseudo, NoItinerary,
-                           "add\t$val, pc, #8\n ${:comment} eh_setjmp begin\n\t"
+                           "add\t$val, pc, #8\t${:comment} eh_setjmp begin\n\t"
                            "str\t$val, [$src, #+4]\n\t"
                            "mov\tr0, #0\n\t"
                            "add\tpc, pc, #0\n\t"



From grosbach at apple.com  Thu Sep 23 18:32:38 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 23:32:38 -0000
Subject: [llvm-commits] [llvm] r114706 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20100923233238.DABBA2A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 18:32:38 2010
New Revision: 114706

URL: http://llvm.org/viewvc/llvm-project?rev=114706&view=rev
Log:
#+4 --> #4 for consistency with other asm output

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114706&r1=114705&r2=114706&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 23 18:32:38 2010
@@ -2685,7 +2685,7 @@
                                AddrModeNone, SizeSpecial, IndexModeNone,
                                Pseudo, NoItinerary,
                            "add\t$val, pc, #8\t${:comment} eh_setjmp begin\n\t"
-                           "str\t$val, [$src, #+4]\n\t"
+                           "str\t$val, [$src, #4]\n\t"
                            "mov\tr0, #0\n\t"
                            "add\tpc, pc, #0\n\t"
                            "mov\tr0, #1 ${:comment} eh_setjmp end", "",
@@ -2700,7 +2700,7 @@
                                    AddrModeNone, SizeSpecial, IndexModeNone,
                                    Pseudo, NoItinerary,
                            "add\t$val, pc, #8\t${:comment} eh_setjmp begin\n\t"
-                           "str\t$val, [$src, #+4]\n\t"
+                           "str\t$val, [$src, #4]\n\t"
                            "mov\tr0, #0\n\t"
                            "add\tpc, pc, #0\n\t"
                            "mov\tr0, #1 ${:comment} eh_setjmp end", "",



From grosbach at apple.com  Thu Sep 23 18:33:57 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Sep 2010 23:33:57 -0000
Subject: [llvm-commits] [llvm] r114707 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100923233357.1CB552A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep 23 18:33:56 2010
New Revision: 114707

URL: http://llvm.org/viewvc/llvm-project?rev=114707&view=rev
Log:
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114707&r1=114706&r2=114707&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Sep 23 18:33:56 2010
@@ -1748,6 +1748,83 @@
     }
     break;
   }
+  case ARM::Int_eh_sjlj_setjmp_nofp:
+  case ARM::Int_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
+    // Two incoming args: GPR:$src, GPR:$val
+    // add $val, pc, #8
+    // str $val, [$src, #+4]
+    // mov r0, #0
+    // add pc, pc, #0
+    // mov r0, #1
+    unsigned SrcReg = MI->getOperand(0).getReg();
+    unsigned ValReg = MI->getOperand(1).getReg();
+
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::ADDri);
+      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
+      TmpInst.addOperand(MCOperand::CreateImm(8));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      // 's' bit operand (always reg0 for this).
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.AddComment("eh_setjmp begin");
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::STR);
+      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
+      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      TmpInst.addOperand(MCOperand::CreateImm(4));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::MOVi);
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
+      TmpInst.addOperand(MCOperand::CreateImm(0));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      // 's' bit operand (always reg0 for this).
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::ADDri);
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
+      TmpInst.addOperand(MCOperand::CreateImm(0));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      // 's' bit operand (always reg0 for this).
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::MOVi);
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
+      TmpInst.addOperand(MCOperand::CreateImm(1));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      // 's' bit operand (always reg0 for this).
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.AddComment("eh_setjmp end");
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    return;
+  }
   }
 
   MCInst TmpInst;



From bob.wilson at apple.com  Thu Sep 23 18:42:37 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 23 Sep 2010 23:42:37 -0000
Subject: [llvm-commits] [llvm] r114709 - in /llvm/trunk:
 lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/vld1.ll
 test/CodeGen/ARM/vst1.ll test/CodeGen/ARM/vst2.ll test/CodeGen/ARM/vst3.ll
 test/CodeGen/ARM/vst4.ll
Message-ID: <20100923234238.013962A6C12C@llvm.org>

Author: bwilson
Date: Thu Sep 23 18:42:37 2010
New Revision: 114709

URL: http://llvm.org/viewvc/llvm-project?rev=114709&view=rev
Log:
Set alignment operand for NEON VST instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/ARM/vld1.ll
    llvm/trunk/test/CodeGen/ARM/vst1.ll
    llvm/trunk/test/CodeGen/ARM/vst2.ll
    llvm/trunk/test/CodeGen/ARM/vst3.ll
    llvm/trunk/test/CodeGen/ARM/vst4.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=114709&r1=114708&r2=114709&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Sep 23 18:42:37 2010
@@ -1002,6 +1002,24 @@
   return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
 }
 
+/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
+/// of a NEON VLD or VST instruction.  The supported values depend on the
+/// number of registers being loaded.
+static unsigned GetVLDSTAlign(SDNode *N, unsigned NumVecs, bool is64BitVector) {
+  unsigned NumRegs = NumVecs;
+  if (!is64BitVector && NumVecs < 3)
+    NumRegs *= 2;
+
+  unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
+  if (Alignment >= 32 && NumRegs == 4)
+    return 32;
+  if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
+    return 16;
+  if (Alignment >= 8)
+    return 8;
+  return 0;
+}
+
 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
                                    unsigned *DOpcodes, unsigned *QOpcodes0,
                                    unsigned *QOpcodes1) {
@@ -1016,20 +1034,7 @@
   EVT VT = N->getValueType(0);
   bool is64BitVector = VT.is64BitVector();
 
-  // Set the alignment.  The supported values depend on the number of
-  // registers being loaded.
-  unsigned NumRegs = NumVecs;
-  if (!is64BitVector && NumVecs < 3)
-    NumRegs *= 2;
-  unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
-  if (Alignment >= 32 && NumRegs == 4)
-    Alignment = 32;
-  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
-    Alignment = 16;
-  else if (Alignment >= 8)
-    Alignment = 8;
-  else
-    Alignment = 0;
+  unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
   Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
 
   unsigned OpcodeIndex;
@@ -1143,6 +1148,9 @@
   EVT VT = N->getOperand(3).getValueType();
   bool is64BitVector = VT.is64BitVector();
 
+  unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
+  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
+
   unsigned OpcodeIndex;
   switch (VT.getSimpleVT().SimpleTy) {
   default: llvm_unreachable("unhandled vst type");

Modified: llvm/trunk/test/CodeGen/ARM/vld1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld1.ll?rev=114709&r1=114708&r2=114709&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld1.ll Thu Sep 23 18:42:37 2010
@@ -43,16 +43,17 @@
 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
 ;CHECK: vld1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
-;CHECK: vld1.8 {d0, d1}, [r0, :128]
-	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 32)
+;CHECK: vld1.8 {d0, d1}, [r0, :64]
+	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
 	ret <16 x i8> %tmp1
 }
 
 define <8 x i16> @vld1Qi16(i16* %A) nounwind {
 ;CHECK: vld1Qi16:
-;CHECK: vld1.16
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vld1.16 {d0, d1}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
-	%tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 1)
+	%tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32)
 	ret <8 x i16> %tmp1
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/vst1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst1.ll?rev=114709&r1=114708&r2=114709&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst1.ll Thu Sep 23 18:42:37 2010
@@ -2,9 +2,10 @@
 
 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vst1i8:
-;CHECK: vst1.8
+;Check the alignment value.  Max for this instruction is 64 bits:
+;CHECK: vst1.8 {d0}, [r0, :64]
 	%tmp1 = load <8 x i8>* %B
-	call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
 	ret void
 }
 
@@ -46,18 +47,20 @@
 
 define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vst1Qi8:
-;CHECK: vst1.8
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vst1.8 {d0, d1}, [r0, :64]
 	%tmp1 = load <16 x i8>* %B
-	call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
 	ret void
 }
 
 define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vst1Qi16:
-;CHECK: vst1.16
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vst1.16 {d0, d1}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <8 x i16>* %B
-	call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
 	ret void
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/vst2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst2.ll?rev=114709&r1=114708&r2=114709&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst2.ll Thu Sep 23 18:42:37 2010
@@ -2,18 +2,20 @@
 
 define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vst2i8:
-;CHECK: vst2.8
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vst2.8 {d0, d1}, [r0, :64]
 	%tmp1 = load <8 x i8>* %B
-	call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
 	ret void
 }
 
 define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vst2i16:
-;CHECK: vst2.16
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vst2.16 {d0, d1}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
-	call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
 	ret void
 }
 
@@ -37,36 +39,40 @@
 
 define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
 ;CHECK: vst2i64:
-;CHECK: vst1.64
+;Check the alignment value.  Max for this instruction is 128 bits:
+;CHECK: vst1.64 {d0, d1}, [r0, :128]
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <1 x i64>* %B
-	call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
 	ret void
 }
 
 define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vst2Qi8:
-;CHECK: vst2.8
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst2.8 {d0, d1, d2, d3}, [r0, :64]
 	%tmp1 = load <16 x i8>* %B
-	call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
 	ret void
 }
 
 define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vst2Qi16:
-;CHECK: vst2.16
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst2.16 {d0, d1, d2, d3}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <8 x i16>* %B
-	call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16)
 	ret void
 }
 
 define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
 ;CHECK: vst2Qi32:
-;CHECK: vst2.32
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst2.32 {d0, d1, d2, d3}, [r0, :256]
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
-	call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64)
 	ret void
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/vst3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst3.ll?rev=114709&r1=114708&r2=114709&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst3.ll Thu Sep 23 18:42:37 2010
@@ -2,9 +2,11 @@
 
 define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vst3i8:
-;CHECK: vst3.8
+;Check the alignment value.  Max for this instruction is 64 bits:
+;This test runs at -O0 so do not check for specific register numbers.
+;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]
 	%tmp1 = load <8 x i8>* %B
-	call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
 	ret void
 }
 
@@ -37,19 +39,23 @@
 
 define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
 ;CHECK: vst3i64:
-;CHECK: vst1.64
+;Check the alignment value.  Max for this instruction is 64 bits:
+;This test runs at -O0 so do not check for specific register numbers.
+;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <1 x i64>* %B
-	call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
 	ret void
 }
 
 define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vst3Qi8:
-;CHECK: vst3.8
-;CHECK: vst3.8
+;Check the alignment value.  Max for this instruction is 64 bits:
+;This test runs at -O0 so do not check for specific register numbers.
+;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]!
+;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]
 	%tmp1 = load <16 x i8>* %B
-	call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
 	ret void
 }
 

Modified: llvm/trunk/test/CodeGen/ARM/vst4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst4.ll?rev=114709&r1=114708&r2=114709&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vst4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vst4.ll Thu Sep 23 18:42:37 2010
@@ -2,27 +2,30 @@
 
 define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vst4i8:
-;CHECK: vst4.8
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst4.8 {d0, d1, d2, d3}, [r0, :64]
 	%tmp1 = load <8 x i8>* %B
-	call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
 	ret void
 }
 
 define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vst4i16:
-;CHECK: vst4.16
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst4.16 {d0, d1, d2, d3}, [r0, :128]
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
-	call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16)
 	ret void
 }
 
 define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vst4i32:
-;CHECK: vst4.32
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst4.32 {d0, d1, d2, d3}, [r0, :256]
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
-	call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32)
 	ret void
 }
 
@@ -37,26 +40,29 @@
 
 define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
 ;CHECK: vst4i64:
-;CHECK: vst1.64
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst1.64 {d0, d1, d2, d3}, [r0, :256]
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <1 x i64>* %B
-	call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64)
 	ret void
 }
 
 define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vst4Qi8:
-;CHECK: vst4.8
-;CHECK: vst4.8
+;Check the alignment value.  Max for this instruction is 256 bits:
+;CHECK: vst4.8 {d0, d2, d4, d6}, [r0, :256]!
+;CHECK: vst4.8 {d1, d3, d5, d7}, [r0, :256]
 	%tmp1 = load <16 x i8>* %B
-	call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 1)
+	call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64)
 	ret void
 }
 
 define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vst4Qi16:
-;CHECK: vst4.16
-;CHECK: vst4.16
+;Check for no alignment specifier.
+;CHECK: vst4.16 {d0, d2, d4, d6}, [r0]!
+;CHECK: vst4.16 {d1, d3, d5, d7}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <8 x i16>* %B
 	call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)



From resistor at mac.com  Thu Sep 23 18:45:25 2010
From: resistor at mac.com (Owen Anderson)
Date: Thu, 23 Sep 2010 23:45:25 -0000
Subject: [llvm-commits] [llvm] r114710 - in /llvm/trunk:
 include/llvm/Target/Target.td include/llvm/Target/TargetInstrDesc.h
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb.td
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/X86/X86Instr64bit.td
 lib/Target/X86/X86InstrInfo.td utils/TableGen/CodeGenInstruction.cpp
 utils/TableGen/CodeGenInstruction.h utils/TableGen/InstrInfoEmitter.cpp
Message-ID: <20100923234525.86FE22A6C12C@llvm.org>

Author: resistor
Date: Thu Sep 23 18:45:25 2010
New Revision: 114710

URL: http://llvm.org/viewvc/llvm-project?rev=114710&view=rev
Log:
Revert r114703 and r114702, removing the isConditionalMove flag from instructions.  After further
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

Modified:
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/include/llvm/Target/TargetInstrDesc.h
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/X86/X86Instr64bit.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.h
    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Thu Sep 23 18:45:25 2010
@@ -201,7 +201,6 @@
   bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
-  bit isConditionalMove = 0; // Is this instruction a conditional move instr?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = 0;     // Is it possible for this inst to read memory?
   bit mayStore     = 0;     // Is it possible for this inst to write memory?

Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Thu Sep 23 18:45:25 2010
@@ -99,7 +99,6 @@
     HasOptionalDef,
     Return,
     Call,
-    ConditionalMove,
     Barrier,
     Terminator,
     Branch,
@@ -353,12 +352,6 @@
     return Flags & (1 << TID::Compare);
   }
   
-  /// isConditionalMove - Return true if this instruction can be considered a
-  /// conditional move, like CMOV on X86 or MOVCC on ARM.
-  bool isConditionalMove() const {
-    return Flags & (1 << TID::ConditionalMove);
-  }
-  
   /// isNotDuplicable - Return true if this instruction cannot be safely
   /// duplicated.  For example, if the instruction has a unique labels attached
   /// to it, duplicating it would cause multiple definition errors.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 23 18:45:25 2010
@@ -2391,7 +2391,7 @@
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
                 IIC_iCMOVr, "mov", "\t$dst, $true",
       [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2415,7 +2415,7 @@
                 RegConstraint<"$false = $dst">, UnaryDP {
   let Inst{25} = 1;
 }
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Sep 23 18:45:25 2010
@@ -866,7 +866,7 @@
 
 
 // 16-bit movcc in IT blocks for Thumb2.
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
               T1Special<{1,0,?,?}>;
@@ -874,7 +874,7 @@
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
               T1General<{1,0,0,?,?}>;
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Sep 23 18:45:25 2010
@@ -2169,7 +2169,7 @@
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
                    "mov", ".w\t$dst, $true",
    [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2221,7 +2221,7 @@
                              (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
                              IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
                  RegConstraint<"$false = $dst">;
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Sep 23 18:45:25 2010
@@ -1366,7 +1366,7 @@
 } // Defs = [EFLAGS]
 
 // Conditional moves
-let isConditionalMove = 1, Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
+let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
 let isCommutable = 1 in {
 def CMOVB64rr : RI<0x42, MRMSrcReg,       // if <u, GR64 = GR64
                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@@ -1530,7 +1530,7 @@
                    "cmovno{q}\t{$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
                                      X86_COND_NO, EFLAGS))]>, TB;
-} // isConditionalMove, Constraints = "$src1 = $dst"
+} // Constraints = "$src1 = $dst"
 
 // Use sbb to materialize carry flag into a GPR.
 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Sep 23 18:45:25 2010
@@ -1269,7 +1269,7 @@
 // Conditional moves
 let Uses = [EFLAGS] in {
 
-let isConditionalMove = 1, Predicates = [HasCMov] in {
+let Predicates = [HasCMov] in {
 let isCommutable = 1 in {
 def CMOVB16rr : I<0x42, MRMSrcReg,       // if <u, GR16 = GR16
                   (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
@@ -1657,7 +1657,7 @@
                    [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
                                     X86_COND_NO, EFLAGS))]>,
                   TB;
-} // isConditionalMove, Predicates = [HasCMov]
+} // Predicates = [HasCMov]
 
 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Thu Sep 23 18:45:25 2010
@@ -103,7 +103,6 @@
   isBranch     = R->getValueAsBit("isBranch");
   isIndirectBranch = R->getValueAsBit("isIndirectBranch");
   isCompare    = R->getValueAsBit("isCompare");
-  isConditionalMove = R->getValueAsBit("isConditionalMove");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Thu Sep 23 18:45:25 2010
@@ -124,7 +124,6 @@
     bool isBranch;
     bool isIndirectBranch;
     bool isCompare;
-    bool isConditionalMove;
     bool isBarrier;
     bool isCall;
     bool canFoldAsLoad;

Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Thu Sep 23 18:45:25 2010
@@ -274,7 +274,6 @@
   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1<<TID::Call)";
-  if (Inst.isConditionalMove)  OS << "|(1<<TID::ConditionalMove)";
   if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";



From daniel at zuster.org  Thu Sep 23 20:58:57 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 01:58:57 -0000
Subject: [llvm-commits] [llvm] r114717 - /llvm/trunk/lib/MC/MCAssembler.cpp
Message-ID: <20100924015857.20F552A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 20:58:56 2010
New Revision: 114717

URL: http://llvm.org/viewvc/llvm-project?rev=114717&view=rev
Log:
MC: Add missing ')' in diagnostic.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=114717&r1=114716&r2=114717&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Sep 23 20:58:56 2010
@@ -451,7 +451,7 @@
     int64_t Offset = TargetLocation - FragmentOffset;
     if (Offset < 0 || Offset >= 0x40000000)
       report_fatal_error("invalid .org offset '" + Twine(TargetLocation) +
-                         "' (at offset '" + Twine(FragmentOffset) + "'");
+                         "' (at offset '" + Twine(FragmentOffset) + "')");
 
     return Offset;
   }



From daniel at zuster.org  Thu Sep 23 20:59:31 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 01:59:31 -0000
Subject: [llvm-commits] [llvm] r114718 - in /llvm/trunk:
 include/llvm/MC/MCParser/MCAsmLexer.h lib/MC/MCParser/AsmLexer.cpp
 tools/llvm-mc/llvm-mc.cpp
Message-ID: <20100924015931.312B72A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 20:59:31 2010
New Revision: 114718

URL: http://llvm.org/viewvc/llvm-project?rev=114718&view=rev
Log:
MC/Lexer: Add 'Real' token type for floating point literals.

Modified:
    llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h
    llvm/trunk/lib/MC/MCParser/AsmLexer.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp

Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=114718&r1=114717&r2=114718&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Thu Sep 23 20:59:31 2010
@@ -33,6 +33,9 @@
     // Integer values.
     Integer,
     
+    // Real values.
+    Real,
+    
     // Register values (stored in IntVal).  Only used by TargetAsmLexer.
     Register,
     

Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=114718&r1=114717&r2=114718&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Thu Sep 23 20:59:31 2010
@@ -65,9 +65,21 @@
 }
 
 /// LexIdentifier: [a-zA-Z_.][a-zA-Z0-9_$.@]*
+static bool IsIdentifierChar(char c) {
+  return isalnum(c) || c == '_' || c == '$' || c == '.' || c == '@';
+}
 AsmToken AsmLexer::LexIdentifier() {
-  while (isalnum(*CurPtr) || *CurPtr == '_' || *CurPtr == '$' ||
-         *CurPtr == '.' || *CurPtr == '@')
+  // Check for floating point literals.
+  if (CurPtr[-1] == '.' && isdigit(*CurPtr)) {
+    while (isdigit(*CurPtr))
+      ++CurPtr;
+    if (!IsIdentifierChar(*CurPtr)) {
+      return AsmToken(AsmToken::Real,
+                      StringRef(TokStart, CurPtr - TokStart));
+    }
+  }
+
+  while (IsIdentifierChar(*CurPtr))
     ++CurPtr;
   
   // Handle . as a special case.
@@ -124,7 +136,6 @@
     CurPtr += 3;
 }
 
-
 /// LexDigit: First character is [0-9].
 ///   Local Label: [0-9][:]
 ///   Forward/Backward Label: [0-9][fb]
@@ -132,13 +143,21 @@
 ///   Octal integer: 0[0-7]+
 ///   Hex integer: 0x[0-9a-fA-F]+
 ///   Decimal integer: [1-9][0-9]*
-/// TODO: FP literal.
 AsmToken AsmLexer::LexDigit() {
   // Decimal integer: [1-9][0-9]*
   if (CurPtr[-1] != '0') {
     while (isdigit(*CurPtr))
       ++CurPtr;
-    
+
+    // Check for floating point literals.
+    if (*CurPtr == '.') {
+      ++CurPtr;
+      while (isdigit(*CurPtr))
+        ++CurPtr;
+
+      return AsmToken(AsmToken::Real, StringRef(TokStart, CurPtr - TokStart));
+    }
+
     StringRef Result(TokStart, CurPtr - TokStart);
 
     long long Value;

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=114718&r1=114717&r2=114718&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Sep 23 20:59:31 2010
@@ -208,6 +208,9 @@
     case AsmToken::Integer:
       Out->os() << "int: " << Lexer.getTok().getString() << '\n';
       break;
+    case AsmToken::Real:
+      Out->os() << "real: " << Lexer.getTok().getString() << '\n';
+      break;
     case AsmToken::Register:
       Out->os() << "register: " << Lexer.getTok().getRegVal() << '\n';
       break;



From daniel at zuster.org  Thu Sep 23 20:59:56 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 01:59:56 -0000
Subject: [llvm-commits] [llvm] r114719 - in /llvm/trunk:
 lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/floating-literals.s
Message-ID: <20100924015956.BA15F2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Sep 23 20:59:56 2010
New Revision: 114719

URL: http://llvm.org/viewvc/llvm-project?rev=114719&view=rev
Log:
MC/AsmParser: Support .single and .double for embedding floating point literals.
 - I believe more modern 'gas' supports a more enhanced set of arithmetic on
   them, but for now the only thing we can do is emit them as data.

Added:
    llvm/trunk/test/MC/AsmParser/floating-literals.s
Modified:
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=114719&r1=114718&r2=114719&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Sep 23 20:59:56 2010
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSwitch.h"
@@ -178,6 +179,7 @@
   // Directive Parsing.
   bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz"
   bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ...
+  bool ParseDirectiveRealValue(const fltSemantics &); // ".single", ...
   bool ParseDirectiveFill(); // ".fill"
   bool ParseDirectiveSpace(); // ".space"
   bool ParseDirectiveZero(); // ".zero"
@@ -926,6 +928,10 @@
       return ParseDirectiveValue(4);
     if (IDVal == ".quad")
       return ParseDirectiveValue(8);
+    if (IDVal == ".single")
+      return ParseDirectiveRealValue(APFloat::IEEEsingle);
+    if (IDVal == ".double")
+      return ParseDirectiveRealValue(APFloat::IEEEdouble);
 
     if (IDVal == ".align") {
       bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
@@ -1409,6 +1415,56 @@
   return false;
 }
 
+/// ParseDirectiveRealValue
+///  ::= (.single | .double) [ expression (, expression)* ]
+bool AsmParser::ParseDirectiveRealValue(const fltSemantics &Semantics) {
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    CheckForValidSection();
+
+    for (;;) {
+      // We don't truly support arithmetic on floating point expressions, so we
+      // have to manually parse unary prefixes.
+      bool IsNeg = false;
+      if (getLexer().is(AsmToken::Minus)) {
+        Lex();
+        IsNeg = true;
+      } else if (getLexer().is(AsmToken::Plus))
+        Lex();
+
+      if (getLexer().isNot(AsmToken::Integer) && 
+          getLexer().isNot(AsmToken::Real))
+        return TokError("unexpected token in directive");
+
+      // Convert to an APFloat.
+      APFloat Value(Semantics);
+      if (Value.convertFromString(getTok().getString(),
+                                  APFloat::rmNearestTiesToEven) ==
+          APFloat::opInvalidOp)
+        return TokError("invalid floating point literal");
+      if (IsNeg)
+        Value.changeSign();
+
+      // Consume the numeric token.
+      Lex();
+
+      // Emit the value as an integer.
+      APInt AsInt = Value.bitcastToAPInt();
+      getStreamer().EmitIntValue(AsInt.getLimitedValue(),
+                                 AsInt.getBitWidth() / 8, DEFAULT_ADDRSPACE);
+
+      if (getLexer().is(AsmToken::EndOfStatement))
+        break;
+      
+      if (getLexer().isNot(AsmToken::Comma))
+        return TokError("unexpected token in directive");
+      Lex();
+    }
+  }
+
+  Lex();
+  return false;
+}
+
 /// ParseDirectiveSpace
 ///  ::= .space expression [ , expression ]
 bool AsmParser::ParseDirectiveSpace() {

Added: llvm/trunk/test/MC/AsmParser/floating-literals.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/floating-literals.s?rev=114719&view=auto
==============================================================================
--- llvm/trunk/test/MC/AsmParser/floating-literals.s (added)
+++ llvm/trunk/test/MC/AsmParser/floating-literals.s Thu Sep 23 20:59:56 2010
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
+
+# CHECK: .long	1067412619
+# CHECK: .long	1075000115
+# CHECK: .long	1077936128
+# CHECK: .long	1082549862
+.single 1.2455, +2.3, 3, + 4.2
+        
+# CHECK: .quad	4617315517961601024
+# CHECK: .quad	4597526701198935065
+# CHECK: .quad	-4600933674317040845
+.double 5, .232, -11.1



From evan.cheng at apple.com  Fri Sep 24 00:18:35 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 05:18:35 -0000
Subject: [llvm-commits] [llvm] r114723 -
	/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp
Message-ID: <20100924051835.7B1682A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 00:18:35 2010
New Revision: 114723

URL: http://llvm.org/viewvc/llvm-project?rev=114723&view=rev
Log:
Fix a potential null dereference bug.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp?rev=114723&r1=114722&r2=114723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp Fri Sep 24 00:18:35 2010
@@ -53,6 +53,14 @@
   return dyn_cast_or_null<BlockAddress>(CVal);
 }
 
+static bool CPV_streq(const char *S1, const char *S2) {
+  if (S1 == S2)
+    return true;
+  if (S1 && S2 && strcmp(S1, S2) == 0)
+    return true;
+  return false;
+}
+
 int ARMConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
                                                     unsigned Alignment) {
   unsigned AlignMask = Alignment - 1;
@@ -65,8 +73,8 @@
       if (CPV->CVal == CVal &&
           CPV->LabelId == LabelId &&
           CPV->PCAdjust == PCAdjust &&
-          (CPV->S == S || strcmp(CPV->S, S) == 0) &&
-          (CPV->Modifier == Modifier || strcmp(CPV->Modifier, Modifier) == 0))
+          CPV_streq(CPV->S, S) &&
+          CPV_streq(CPV->Modifier, Modifier))
         return i;
     }
   }
@@ -91,8 +99,8 @@
   if (ACPV->Kind == Kind &&
       ACPV->CVal == CVal &&
       ACPV->PCAdjust == PCAdjust &&
-      (ACPV->S == S || strcmp(ACPV->S, S) == 0) &&
-      (ACPV->Modifier == Modifier || strcmp(ACPV->Modifier, Modifier) == 0)) {
+      CPV_streq(ACPV->S, S) &&
+      CPV_streq(ACPV->Modifier, Modifier)) {
     if (ACPV->LabelId == LabelId)
       return true;
     // Two PC relative constpool entries containing the same GV address or



From baldrick at free.fr  Fri Sep 24 02:27:20 2010
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 24 Sep 2010 09:27:20 +0200
Subject: [llvm-commits] [llvm] r114681
	-	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <20100923183219.35D1D2A6C12C@llvm.org>
References: <20100923183219.35D1D2A6C12C@llvm.org>
Message-ID: <4C9C52D8.3090708@free.fr>

> Revert 114634 for now since buildbot claim it broke Clang self-hosting. I doubt it but it's possible it's exposing another bug somewhere.

Thanks Evan.  Reverting this also fixed the dragonegg self-host.

Ciao,

Duncan.

From bigcheesegs at gmail.com  Fri Sep 24 04:00:56 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 09:00:56 -0000
Subject: [llvm-commits] [llvm] r114724 - in /llvm/trunk:
 cmake/config-ix.cmake test/CMakeLists.txt utils/lit/lit/TestFormats.py
Message-ID: <20100924090056.B11152A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 04:00:56 2010
New Revision: 114724

URL: http://llvm.org/viewvc/llvm-project?rev=114724&view=rev
Log:
Fix whitespace.

Modified:
    llvm/trunk/cmake/config-ix.cmake
    llvm/trunk/test/CMakeLists.txt
    llvm/trunk/utils/lit/lit/TestFormats.py

Modified: llvm/trunk/cmake/config-ix.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=114724&r1=114723&r2=114724&view=diff
==============================================================================
--- llvm/trunk/cmake/config-ix.cmake (original)
+++ llvm/trunk/cmake/config-ix.cmake Fri Sep 24 04:00:56 2010
@@ -202,15 +202,15 @@
 elseif (LLVM_NATIVE_ARCH MATCHES "msp430")
   set(LLVM_NATIVE_ARCH MSP430)
 else ()
-  message(STATUS 
+  message(STATUS
     "Unknown architecture ${LLVM_NATIVE_ARCH}; lli will not JIT code")
   set(LLVM_NATIVE_ARCH)
 endif ()
-  
+
 if (LLVM_NATIVE_ARCH)
   list(FIND LLVM_TARGETS_TO_BUILD ${LLVM_NATIVE_ARCH} NATIVE_ARCH_IDX)
   if (NATIVE_ARCH_IDX EQUAL -1)
-    message(STATUS 
+    message(STATUS
       "Native target ${LLVM_NATIVE_ARCH} is not selected; lli will not JIT code")
     set(LLVM_NATIVE_ARCH)
   else ()

Modified: llvm/trunk/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=114724&r1=114723&r2=114724&view=diff
==============================================================================
--- llvm/trunk/test/CMakeLists.txt (original)
+++ llvm/trunk/test/CMakeLists.txt Fri Sep 24 04:00:56 2010
@@ -18,7 +18,7 @@
 else() # Default for all other unix like systems.
   # CMake hardcodes the library locaction using rpath.
   # Therefore LD_LIBRARY_PATH is not required to run binaries in the
-  # build dir. We pass it anyways. 
+  # build dir. We pass it anyways.
   set(SHLIBPATH_VAR "LD_LIBRARY_PATH")
 endif()
 

Modified: llvm/trunk/utils/lit/lit/TestFormats.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestFormats.py?rev=114724&r1=114723&r2=114724&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/TestFormats.py (original)
+++ llvm/trunk/utils/lit/lit/TestFormats.py Fri Sep 24 04:00:56 2010
@@ -44,7 +44,7 @@
                 index += 1
             while len(nested_tests) > index:
                 nested_tests.pop()
-            
+
             ln = ln[index*2:]
             if ln.endswith('.'):
                 nested_tests.append(ln)
@@ -84,7 +84,7 @@
 
         out, err, exitCode = TestRunner.executeCommand(
             cmd, env=test.config.environment)
-            
+
         if not exitCode:
             return Test.PASS,''
 



From bigcheesegs at gmail.com  Fri Sep 24 04:01:13 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 09:01:13 -0000
Subject: [llvm-commits] [llvm] r114725 - in /llvm/trunk: CMakeLists.txt
 test/CMakeLists.txt unittests/CMakeLists.txt utils/unittest/CMakeLists.txt
 utils/unittest/googletest/include/gtest/internal/gtest-port.h
Message-ID: <20100924090113.735D22A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 04:01:13 2010
New Revision: 114725

URL: http://llvm.org/viewvc/llvm-project?rev=114725&view=rev
Log:
CMake: Build unittests.

Added:
    llvm/trunk/unittests/CMakeLists.txt
    llvm/trunk/utils/unittest/CMakeLists.txt
Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/test/CMakeLists.txt
    llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=114725&r1=114724&r2=114725&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Fri Sep 24 04:01:13 2010
@@ -305,7 +305,6 @@
 add_subdirectory(lib/MC)
 add_subdirectory(lib/MC/MCParser)
 add_subdirectory(lib/MC/MCDisassembler)
-add_subdirectory(test)
 
 add_subdirectory(utils/FileCheck)
 add_subdirectory(utils/count)
@@ -370,6 +369,12 @@
 option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF)
 add_subdirectory(examples)
 
+option(LLVM_BUILD_TESTS "Build LLVM unit tests." OFF)
+add_subdirectory(test)
+add_subdirectory(utils/unittest)
+add_subdirectory(unittests)
+
+
 add_subdirectory(cmake/modules)
 
 install(DIRECTORY include/

Modified: llvm/trunk/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=114725&r1=114724&r2=114725&view=diff
==============================================================================
--- llvm/trunk/test/CMakeLists.txt (original)
+++ llvm/trunk/test/CMakeLists.txt Fri Sep 24 04:01:13 2010
@@ -52,7 +52,15 @@
   set(LLVM_TOOLS_DIR "${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}")
   set(LLVMGCCDIR "")
   set(PYTHON_EXECUTABLE ${PYTHON_EXECUTABLE})
-  set(LLVM_BUILD_MODE ${CMAKE_CFG_INTDIR})
+  if (CMAKE_CONFIGURATION_TYPES)
+    # FIXME: We have no idea. It could be any of them... So just output all of
+    # them.
+    set(LLVM_BUILD_MODE "${CMAKE_CONFIGURATION_TYPES}")
+  elseif (CMAKE_BUILD_TYPE)
+    set(LLVM_BUILD_MODE "${CMAKE_BUILD_TYPE}")
+  else()
+    set(LLVM_BUILD_MODE "None")
+  endif()
   set(ENABLE_SHARED ${LLVM_SHARED_LIBS_ENABLED})
   set(SHLIBPATH_VAR ${SHLIBPATH_VAR})
 

Added: llvm/trunk/unittests/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=114725&view=auto
==============================================================================
--- llvm/trunk/unittests/CMakeLists.txt (added)
+++ llvm/trunk/unittests/CMakeLists.txt Fri Sep 24 04:01:13 2010
@@ -0,0 +1,95 @@
+function(add_llvm_unittest test_name)
+  if (CMAKE_BUILD_TYPE)
+    set(CMAKE_RUNTIME_OUTPUT_DIRECTORY
+      ${LLVM_BINARY_DIR}/unittests/${test_name}/${CMAKE_BUILD_TYPE})
+  else()
+    set(CMAKE_RUNTIME_OUTPUT_DIRECTORY
+      ${LLVM_BINARY_DIR}/unittests/${test_name})
+  endif()
+  if( NOT LLVM_BUILD_TESTS )
+    set(EXCLUDE_FROM_ALL ON)
+  endif()
+  add_llvm_executable(${test_name}Tests ${ARGN})
+endfunction()
+
+include_directories(${LLVM_MAIN_SRC_DIR}/utils/unittest/googletest/include)
+
+set(LLVM_LINK_COMPONENTS
+  jit
+  interpreter
+  nativecodegen
+  BitWriter
+  BitReader
+  AsmParser
+  Core
+  System
+  Support
+  )
+
+set(LLVM_USED_LIBS
+  gtest
+  gtest_main
+  )
+
+add_llvm_unittest(ADT
+  ADT/APFloatTest.cpp
+  ADT/APIntTest.cpp
+  ADT/BitVectorTest.cpp
+  ADT/DAGDeltaAlgorithmTest.cpp
+  ADT/DeltaAlgorithmTest.cpp
+  ADT/DenseMapTest.cpp
+  ADT/DenseSetTest.cpp
+  ADT/ilistTest.cpp
+  ADT/ImmutableSetTest.cpp
+  ADT/SmallBitVectorTest.cpp
+  ADT/SmallStringTest.cpp
+  ADT/SmallVectorTest.cpp
+  ADT/SparseBitVectorTest.cpp
+  ADT/StringMapTest.cpp
+  ADT/StringRefTest.cpp
+  ADT/TripleTest.cpp
+  ADT/TwineTest.cpp
+  ADT/ValueMapTest.cpp
+  )
+
+add_llvm_unittest(Analysis
+  Analysis/ScalarEvolutionTest.cpp
+  )
+
+add_llvm_unittest(ExecutionEngine
+  ExecutionEngine/ExecutionEngineTest.cpp
+  )
+
+add_llvm_unittest(JIT
+  ExecutionEngine/JIT/JITEventListenerTest.cpp
+  ExecutionEngine/JIT/JITMemoryManagerTest.cpp
+  ExecutionEngine/JIT/JITTest.cpp
+  ExecutionEngine/JIT/MultiJITTest.cpp
+  )
+
+add_llvm_unittest(Support
+  Support/AllocatorTest.cpp
+  Support/Casting.cpp
+  Support/CommandLineTest.cpp
+  Support/ConstantRangeTest.cpp
+  Support/LeakDetectorTest.cpp
+  Support/MathExtrasTest.cpp
+  Support/raw_ostream_test.cpp
+  Support/RegexTest.cpp
+  Support/System.cpp
+  Support/TypeBuilderTest.cpp
+  Support/ValueHandleTest.cpp
+  )
+
+add_llvm_unittest(Transforms
+  Transforms/Utils/Cloning.cpp
+  )
+
+add_llvm_unittest(VMCore
+  VMCore/ConstantsTest.cpp
+  VMCore/DerivedTypesTest.cpp
+  VMCore/InstructionsTest.cpp
+  VMCore/MetadataTest.cpp
+  VMCore/PassManagerTest.cpp
+  VMCore/VerifierTest.cpp
+  )

Added: llvm/trunk/utils/unittest/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/CMakeLists.txt?rev=114725&view=auto
==============================================================================
--- llvm/trunk/utils/unittest/CMakeLists.txt (added)
+++ llvm/trunk/utils/unittest/CMakeLists.txt Fri Sep 24 04:01:13 2010
@@ -0,0 +1,34 @@
+########################################################################
+# Experimental CMake build script for Google Test.
+#
+# Consider this a prototype.  It will change drastically.  For now,
+# this is only for people on the cutting edge.
+#
+# To run the tests for Google Test itself on Linux, use 'make test' or
+# ctest.  You can select which tests to run using 'ctest -R regex'.
+# For more options, run 'ctest --help'.
+########################################################################
+#
+# Project-wide settings
+
+# Where gtest's .h files can be found.
+include_directories(
+  googletest/include
+  )
+
+if(WIN32)
+  add_definitions(-DGTEST_OS_WINDOWS=1)
+endif()
+
+add_llvm_library(gtest
+  googletest/gtest.cc
+  googletest/gtest-death-test.cc
+  googletest/gtest-filepath.cc
+  googletest/gtest-port.cc
+  googletest/gtest-test-part.cc
+  googletest/gtest-typed-test.cc
+  )
+
+add_llvm_library(gtest_main
+  UnitTestMain/TestMain.cpp
+  )

Modified: llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h?rev=114725&r1=114724&r2=114725&view=diff
==============================================================================
--- llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h (original)
+++ llvm/trunk/utils/unittest/googletest/include/gtest/internal/gtest-port.h Fri Sep 24 04:01:13 2010
@@ -403,7 +403,8 @@
 // defining __GNUC__ and friends, but cannot compile GCC's tuple
 // implementation.  MSVC 2008 (9.0) provides TR1 tuple in a 323 MB
 // Feature Pack download, which we cannot assume the user has.
-#if (defined(__GNUC__) && !defined(__CUDACC__) && (GTEST_GCC_VER_ >= 40000)) \
+#if (defined(__GNUC__) && !(defined(__CUDACC__) || defined(__clang__)) \
+                       && (GTEST_GCC_VER_ >= 40000)) \
     || _MSC_VER >= 1600
 #define GTEST_USE_OWN_TR1_TUPLE 0
 #else



From bigcheesegs at gmail.com  Fri Sep 24 04:01:22 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 09:01:22 -0000
Subject: [llvm-commits] [llvm] r114726 -
	/llvm/trunk/utils/lit/lit/TestFormats.py
Message-ID: <20100924090122.CE4F82A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 04:01:22 2010
New Revision: 114726

URL: http://llvm.org/viewvc/llvm-project?rev=114726&view=rev
Log:
Test unittests built with CMake.

Modified:
    llvm/trunk/utils/lit/lit/TestFormats.py

Modified: llvm/trunk/utils/lit/lit/TestFormats.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestFormats.py?rev=114726&r1=114725&r2=114726&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/TestFormats.py (original)
+++ llvm/trunk/utils/lit/lit/TestFormats.py Fri Sep 24 04:01:22 2010
@@ -9,7 +9,7 @@
 
 class GoogleTest(object):
     def __init__(self, test_sub_dir, test_suffix):
-        self.test_sub_dir = str(test_sub_dir)
+        self.test_sub_dir = str(test_sub_dir).split(';')
         self.test_suffix = str(test_suffix)
 
         # On Windows, assume tests will also end in '.exe'.
@@ -28,7 +28,10 @@
 
         try:
             lines = Util.capture([path, '--gtest_list_tests'],
-                                 env=localConfig.environment).split('\n')
+                                 env=localConfig.environment)
+            if kIsWindows:
+              lines = lines.replace('\r', '')
+            lines = lines.split('\n')
         except:
             litConfig.error("unable to discover google-tests in %r" % path)
             raise StopIteration
@@ -56,10 +59,13 @@
         source_path = testSuite.getSourcePath(path_in_suite)
         for filename in os.listdir(source_path):
             # Check for the one subdirectory (build directory) tests will be in.
-            if filename != self.test_sub_dir:
+            if not filename in self.test_sub_dir:
                 continue
 
             filepath = os.path.join(source_path, filename)
+            if not os.path.isdir(filepath):
+                continue
+
             for subfilename in os.listdir(filepath):
                 if subfilename.endswith(self.test_suffix):
                     execpath = os.path.join(filepath, subfilename)



From bigcheesegs at gmail.com  Fri Sep 24 04:01:34 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 09:01:34 -0000
Subject: [llvm-commits] [llvm] r114727 - in /llvm/trunk:
 unittests/Support/System.cpp utils/unittest/UnitTestMain/TestMain.cpp
Message-ID: <20100924090134.A03002A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 04:01:34 2010
New Revision: 114727

URL: http://llvm.org/viewvc/llvm-project?rev=114727&view=rev
Log:
unittests: Support Windows.

Modified:
    llvm/trunk/unittests/Support/System.cpp
    llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp

Modified: llvm/trunk/unittests/Support/System.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/System.cpp?rev=114727&r1=114726&r2=114727&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/System.cpp (original)
+++ llvm/trunk/unittests/Support/System.cpp Fri Sep 24 04:01:34 2010
@@ -11,6 +11,6 @@
 TEST_F(SystemTest, TimeValue) {
   sys::TimeValue now = sys::TimeValue::now();
   time_t now_t = time(NULL);
-  EXPECT_TRUE(abs(now_t - now.toEpochTime()) < 2);
+  EXPECT_TRUE(abs(static_cast<time_t>(now_t - now.toEpochTime())) < 2);
 }
 }

Modified: llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp?rev=114727&r1=114726&r2=114727&view=diff
==============================================================================
--- llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp (original)
+++ llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp Fri Sep 24 04:01:34 2010
@@ -7,9 +7,36 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/Config/config.h"
+#include "llvm/System/Signals.h"
 #include "gtest/gtest.h"
 
+
+#if defined(LLVM_ON_WIN32)
+# include <Windows.h>
+# if defined(_MSC_VER)
+#   include <crtdbg.h>
+# endif
+#endif
+
 int main(int argc, char **argv) {
+  llvm::sys::PrintStackTraceOnErrorSignal();
   testing::InitGoogleTest(&argc, argv);
+
+# if defined(LLVM_ON_WIN32)
+  // Disable all of the possible ways Windows conspires to make automated
+  // testing impossible.
+  ::SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOGPFAULTERRORBOX);
+#   if defined(_MSC_VER)
+    ::_set_error_mode(_OUT_TO_STDERR);
+    ::_CrtSetReportMode(_CRT_WARN, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
+    ::_CrtSetReportFile(_CRT_WARN, _CRTDBG_FILE_STDERR);
+    ::_CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
+    ::_CrtSetReportFile(_CRT_ERROR, _CRTDBG_FILE_STDERR);
+    ::_CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
+    ::_CrtSetReportFile(_CRT_ASSERT, _CRTDBG_FILE_STDERR);
+#   endif
+# endif
+
   return RUN_ALL_TESTS();
 }



From bigcheesegs at gmail.com  Fri Sep 24 04:10:21 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 09:10:21 -0000
Subject: [llvm-commits] [llvm] r114728 -
	/llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp
Message-ID: <20100924091021.901E12A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 04:10:21 2010
New Revision: 114728

URL: http://llvm.org/viewvc/llvm-project?rev=114728&view=rev
Log:
Fix line endings from my last commit.

Modified:
    llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp

Modified: llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp?rev=114728&r1=114727&r2=114728&view=diff
==============================================================================
--- llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp (original)
+++ llvm/trunk/utils/unittest/UnitTestMain/TestMain.cpp Fri Sep 24 04:10:21 2010
@@ -29,11 +29,11 @@
   ::SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOGPFAULTERRORBOX);
 #   if defined(_MSC_VER)
     ::_set_error_mode(_OUT_TO_STDERR);
-    ::_CrtSetReportMode(_CRT_WARN, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
+    ::_CrtSetReportMode(_CRT_WARN, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
     ::_CrtSetReportFile(_CRT_WARN, _CRTDBG_FILE_STDERR);
-    ::_CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
+    ::_CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
     ::_CrtSetReportFile(_CRT_ERROR, _CRTDBG_FILE_STDERR);
-    ::_CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
+    ::_CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);
     ::_CrtSetReportFile(_CRT_ASSERT, _CRTDBG_FILE_STDERR);
 #   endif
 # endif



From geek4civic at gmail.com  Fri Sep 24 05:19:49 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 24 Sep 2010 19:19:49 +0900
Subject: [llvm-commits] [llvm] r113766 - in /llvm/trunk:
 include/llvm/InlineAsm.h include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Targ
Message-ID: <AANLkTikrCdYssmicNN1zJ7FWYDvEGec13BfobgpKJbYG@mail.gmail.com>

Good evening, John.

With this commit, test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crashes
when --enable-assertions=no.
(Un)luckily, this test is marked as "XFAIL: *" and catches crash, too.

I have confirmed on x86_64-linux(CentOS5) with optimization.
Please see below, thank you;

* r113765
$ bisect/bin/llc < ~/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
        .machine ppc
        .section        __TEXT,__textcoal_nt,coalesced,pure_instructions
        .section        __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
        .section        __TEXT,__text,regular,pure_instructions
LLVM ERROR: Unsupported asm: input constraint with a matching output
constraint of incompatible type!

* r113766 (and ToT)
$ bisect/bin/llc < ~/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
        .machine ppc
        .section        __TEXT,__textcoal_nt,coalesced,pure_instructions
        .section        __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
        .section        __TEXT,__text,regular,pure_instructions
0  llc             0x00000000009d295f
1  llc             0x00000000009d46fa
2  libpthread.so.0 0x00000039de00eb10
3  llc             0x00000000005f64af
llvm::SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<llvm::SDValue,
std::allocator<llvm::SDValue> >&) + 431
4  llc             0x00000000005f678f
llvm::SelectionDAGISel::Select_INLINEASM(llvm::SDNode*) + 239
5  llc             0x00000000005f7725
llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char
const*, unsigned int) + 1269
6  llc             0x000000000050ebe7
7  llc             0x00000000005f1c20
llvm::SelectionDAGISel::DoInstructionSelection() + 368
8  llc             0x00000000005f2e8b
llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 715
9  llc             0x00000000005f44de
llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction
const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 158
10 llc             0x00000000005f499d
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) +
1133
11 llc             0x00000000005f53e9
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) +
361
12 llc             0x000000000050e226
13 llc             0x00000000009695c9
llvm::FPPassManager::runOnFunction(llvm::Function&) + 521
14 llc             0x000000000096967b
llvm::FPPassManager::runOnModule(llvm::Module&) + 75
15 llc             0x0000000000969221
llvm::MPPassManager::runOnModule(llvm::Module&) + 465
16 llc             0x000000000096933d
llvm::PassManagerImpl::run(llvm::Module&) + 125
17 llc             0x00000000004cdc45 main + 3397
18 libc.so.6       0x00000039dd41d994 __libc_start_main + 244
19 llc             0x00000000004cbc89 __gxx_personality_v0 + 633
Stack dump:
0.      Program arguments: bisect/bin/llc
1.      Running pass 'Function Pass Manager' on module '<stdin>'.
2.      Running pass 'PowerPC DAG->DAG Pattern Instruction Selection'
on function '@test'


2010/9/14 John Thompson <John.Thompson.JTSoftware at gmail.com>:
> Author: jtsoftware
> Date: Mon Sep 13 13:15:37 2010
> New Revision: 113766
>
> URL: http://llvm.org/viewvc/llvm-project?rev=113766&view=rev
> Log:
> Added skeleton for inline asm multiple alternative constraint support.
>
> Modified:
> ? ?llvm/trunk/include/llvm/InlineAsm.h
> ? ?llvm/trunk/include/llvm/Target/TargetLowering.h
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.h
> ? ?llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
> ? ?llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
> ? ?llvm/trunk/lib/VMCore/InlineAsm.cpp


From geek4civic at gmail.com  Fri Sep 24 05:19:49 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 24 Sep 2010 19:19:49 +0900
Subject: [llvm-commits] [llvm] r113766 - in /llvm/trunk:
 include/llvm/InlineAsm.h include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Targ
Message-ID: <AANLkTikrCdYssmicNN1zJ7FWYDvEGec13BfobgpKJbYG@mail.gmail.com>

Good evening, John.

With this commit, test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crashes
when --enable-assertions=no.
(Un)luckily, this test is marked as "XFAIL: *" and catches crash, too.

I have confirmed on x86_64-linux(CentOS5) with optimization.
Please see below, thank you;

* r113765
$ bisect/bin/llc < ~/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
        .machine ppc
        .section        __TEXT,__textcoal_nt,coalesced,pure_instructions
        .section        __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
        .section        __TEXT,__text,regular,pure_instructions
LLVM ERROR: Unsupported asm: input constraint with a matching output
constraint of incompatible type!

* r113766 (and ToT)
$ bisect/bin/llc < ~/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
        .machine ppc
        .section        __TEXT,__textcoal_nt,coalesced,pure_instructions
        .section        __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
        .section        __TEXT,__text,regular,pure_instructions
0  llc             0x00000000009d295f
1  llc             0x00000000009d46fa
2  libpthread.so.0 0x00000039de00eb10
3  llc             0x00000000005f64af
llvm::SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<llvm::SDValue,
std::allocator<llvm::SDValue> >&) + 431
4  llc             0x00000000005f678f
llvm::SelectionDAGISel::Select_INLINEASM(llvm::SDNode*) + 239
5  llc             0x00000000005f7725
llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char
const*, unsigned int) + 1269
6  llc             0x000000000050ebe7
7  llc             0x00000000005f1c20
llvm::SelectionDAGISel::DoInstructionSelection() + 368
8  llc             0x00000000005f2e8b
llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 715
9  llc             0x00000000005f44de
llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction
const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 158
10 llc             0x00000000005f499d
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) +
1133
11 llc             0x00000000005f53e9
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) +
361
12 llc             0x000000000050e226
13 llc             0x00000000009695c9
llvm::FPPassManager::runOnFunction(llvm::Function&) + 521
14 llc             0x000000000096967b
llvm::FPPassManager::runOnModule(llvm::Module&) + 75
15 llc             0x0000000000969221
llvm::MPPassManager::runOnModule(llvm::Module&) + 465
16 llc             0x000000000096933d
llvm::PassManagerImpl::run(llvm::Module&) + 125
17 llc             0x00000000004cdc45 main + 3397
18 libc.so.6       0x00000039dd41d994 __libc_start_main + 244
19 llc             0x00000000004cbc89 __gxx_personality_v0 + 633
Stack dump:
0.      Program arguments: bisect/bin/llc
1.      Running pass 'Function Pass Manager' on module '<stdin>'.
2.      Running pass 'PowerPC DAG->DAG Pattern Instruction Selection'
on function '@test'


2010/9/14 John Thompson <John.Thompson.JTSoftware at gmail.com>:
> Author: jtsoftware
> Date: Mon Sep 13 13:15:37 2010
> New Revision: 113766
>
> URL: http://llvm.org/viewvc/llvm-project?rev=113766&view=rev
> Log:
> Added skeleton for inline asm multiple alternative constraint support.
>
> Modified:
> ? ?llvm/trunk/include/llvm/InlineAsm.h
> ? ?llvm/trunk/include/llvm/Target/TargetLowering.h
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.h
> ? ?llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
> ? ?llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
> ? ?llvm/trunk/lib/VMCore/InlineAsm.cpp


From Edmund.Grimley-Evans at arm.com  Fri Sep 24 09:09:25 2010
From: Edmund.Grimley-Evans at arm.com (Edmund Grimley-Evans)
Date: Fri, 24 Sep 2010 15:09:25 +0100
Subject: [llvm-commits] [PATCH] Possible bug fix in LegalizeDAG.cpp
Message-ID: <680044E4997F5343A2C58032DDD099160705D9@ZIPPY.Emea.Arm.com>

I don't have a test case, but the original code looks suspicious and none of the regression tests fails for me when I make this change.

On the other hand, see the comment a few lines above the altered line ...






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From criswell at uiuc.edu  Fri Sep 24 10:15:21 2010
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 24 Sep 2010 15:15:21 -0000
Subject: [llvm-commits] [poolalloc] r114729 - in /poolalloc/trunk:
 include/poolalloc/Heuristic.h include/poolalloc/PoolAllocate.h
 lib/PoolAllocate/Heuristic.cpp lib/PoolAllocate/PoolAllocate.cpp
 test/TEST.poolalloc.Makefile
Message-ID: <20100924151521.67BD92A6C12C@llvm.org>

Author: criswell
Date: Fri Sep 24 10:15:21 2010
New Revision: 114729

URL: http://llvm.org/viewvc/llvm-project?rev=114729&view=rev
Log:
Refactored the code to make the Heuristic classes an LLVM analysis group.  
This will eventually allow clients (such as SAFECode) to more easily tailor
Automatic Pool Allocation's behavior.

Modified:
    poolalloc/trunk/include/poolalloc/Heuristic.h
    poolalloc/trunk/include/poolalloc/PoolAllocate.h
    poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
    poolalloc/trunk/test/TEST.poolalloc.Makefile

Modified: poolalloc/trunk/include/poolalloc/Heuristic.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/Heuristic.h?rev=114729&r1=114728&r2=114729&view=diff
==============================================================================
--- poolalloc/trunk/include/poolalloc/Heuristic.h (original)
+++ poolalloc/trunk/include/poolalloc/Heuristic.h Fri Sep 24 10:15:21 2010
@@ -12,8 +12,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef POOLALLOCATION_HEURISTIC_H
-#define POOLALLOCATION_HEURISTIC_H
+#ifndef POOLALLOC_HEURISTIC_H
+#define POOLALLOC_HEURISTIC_H
+
+#include "dsa/DataStructure.h"
+#include "dsa/DSGraph.h"
+
+#include "llvm/Pass.h"
 
 #include <vector>
 #include <map>
@@ -29,18 +34,34 @@
   class Type;
 
 namespace PA {
-  class Heuristic {
+  class Heuristic : public ImmutablePass {
   protected:
     Module *M;
-    DSGraph *GG;
     PoolAllocate *PA;
 
-    Heuristic() {}
   public:
-    void Initialize(Module &m, DSGraph* gg, PoolAllocate &pa) {
-      M = &m; GG = gg; PA = &pa;
+    //
+    // Pass methods and members.
+    //
+    static char ID;
+    Heuristic (intptr_t IDp = (intptr_t) (&ID)) : ImmutablePass (IDp) { }
+    virtual ~Heuristic () {return;}
+    virtual bool runOnModule (Module & M);
+
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      // We require DSA while this pass is still responding to queries
+      AU.addRequiredTransitive<EQTDDataStructures>();
+
+      // This pass does not modify anything when it runs
+      AU.setPreservesAll();
+    }
+
+    //
+    // Other methods.
+    //
+    void Initialize (PoolAllocate &pa) {
+      PA = &pa;
     }
-    virtual ~Heuristic();
 
     /// IsRealHeuristic - Return true if this is not a real pool allocation
     /// heuristic.
@@ -96,10 +117,6 @@
     static unsigned getRecommendedAlignment(const DSNode *N);
     static unsigned getRecommendedAlignment(const Type *Ty,
                                             const TargetData &TD);
-    
-    /// create - This static ctor creates the heuristic, based on the command
-    /// line argument to choose the heuristic.
-    static Heuristic *create();
   };
 }
 }

Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=114729&r1=114728&r2=114729&view=diff
==============================================================================
--- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original)
+++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Fri Sep 24 10:15:21 2010
@@ -32,6 +32,7 @@
 #include "dsa/DataStructure.h"
 #include "dsa/DSGraph.h"
 #include "poolalloc/Config/config.h"
+#include "poolalloc/Heuristic.h"
 
 #include <utility>
 
@@ -46,8 +47,6 @@
 
   extern cl::opt<bool>  PA_SAFECODE;
 
-  class Heuristic;
-
   /// FuncInfo - Represent the pool allocation information for one function in
   /// the program.  Note that many functions must actually be cloned in order
   /// for pool allocation to add arguments to the function signature.  In this

Modified: poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp?rev=114729&r1=114728&r2=114729&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp Fri Sep 24 10:15:21 2010
@@ -26,39 +26,16 @@
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetData.h"
 #include <iostream>
+
 using namespace llvm;
 using namespace PA;
 
 namespace {
-  enum PoolAllocHeuristic {
-    NoNodes,
-    OnlyOverhead,
-    AllInOneGlobalPool,
-    SmartCoallesceNodes,
-    CyclicNodes,
-    AllButUnreachableFromMemory,
-    AllNodes
-  };
-  cl::opt<PoolAllocHeuristic>
-  TheHeuristic("poolalloc-heuristic",
-    cl::desc("Heuristic to choose which nodes to pool allocate"),
-    cl::values(clEnumVal(AllNodes, "  Pool allocate all nodes"),
-               clEnumVal(AllButUnreachableFromMemory, "  Pool allocate all reachable from memory objects"),
-               clEnumVal(CyclicNodes, "  Pool allocate nodes with cycles"),
-               clEnumVal(SmartCoallesceNodes, "  Use the smart node merging heuristic"),
-               clEnumVal(AllInOneGlobalPool, "  Use pool library as replacement for malloc/free"),
-               clEnumVal(OnlyOverhead, "  Do not pool allocate anything, but induce all overhead from it"),
-               clEnumVal(NoNodes, "  Do not pool allocate anything"),
-               clEnumValEnd),
-    cl::init(AllButUnreachableFromMemory)); 
-
   cl::opt<bool>
   DisableAlignOpt("poolalloc-disable-alignopt",
                   cl::desc("Force all pool alignment to 8 bytes"));
 }
 
-Heuristic::~Heuristic() {}
-
 //
 // Function: getRecommendedSize()
 //
@@ -229,12 +206,35 @@
   return 4;
 }
  
+//
+// Method: runOnModule()
+//
+// Description:
+//  This is the entry point for this pass.
+//
+bool
+Heuristic::runOnModule (Module & Module) {
+  //
+  // Remember which module we are analyzing.
+  //
+  M = &Module;
+
+  // We never modify anything in this pass
+  return false;
+}
 
 //===-- AllNodes Heuristic ------------------------------------------------===//
 //
 // This heuristic pool allocates everything possible into separate pools.
 //
-struct AllNodesHeuristic : public Heuristic {
+class AllNodesHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
 
   void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
                      Function *F, DSGraph* G,
@@ -252,7 +252,15 @@
 // that are not cyclic and are only pointed to by scalars: these tend to be
 // singular memory allocations that are not worth creating a whole pool for.
 //
-struct AllButUnreachableFromMemoryHeuristic : public Heuristic {
+class AllButUnreachableFromMemoryHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
+
 
   void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
                      Function *F, DSGraph* G,
@@ -304,7 +312,15 @@
 //
 // This heuristic only pool allocates nodes in an SCC in the DSGraph.
 //
-struct CyclicNodesHeuristic : public Heuristic {
+class CyclicNodesHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
+
 
   void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
                      Function *F, DSGraph* G,
@@ -333,7 +349,15 @@
 // This heuristic attempts to be smart and coallesce nodes at times.  In
 // practice, it doesn't work very well.
 //
-struct SmartCoallesceNodesHeuristic : public Heuristic {
+class SmartCoallesceNodesHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
+
 
   void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
                     Function *F, DSGraph* G,
@@ -510,7 +534,15 @@
 // pool.  This is not safe, and is not good for performance, but can be used to
 // evaluate how good the pool allocator runtime works as a "malloc replacement".
 //
-struct AllInOneGlobalPoolHeuristic : public Heuristic {
+class AllInOneGlobalPoolHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
+
   // TheGlobalPD - This global pool is the one and only one used when running
   // with Heuristic=AllInOneGlobalPool.
   GlobalVariable *TheGlobalPD;
@@ -541,7 +573,15 @@
 // the program, but dynamically only passes null into the pool alloc/free
 // functions, causing them to allocate from the heap.
 //
-struct OnlyOverheadHeuristic : public Heuristic {
+class OnlyOverheadHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
+
   virtual bool IsRealHeuristic() { return false; }
 
   void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
@@ -608,7 +648,15 @@
 //
 // This dummy heuristic chooses to not pool allocate anything.
 //
-struct NoNodesHeuristic : public Heuristic {
+class NoNodesHeuristic : public Heuristic {
+  public:
+  static char ID;
+  virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+    if (PI->isPassID(&Heuristic::ID))
+      return (Heuristic*)this;
+    return this;
+  }
+
   virtual bool IsRealHeuristic() { return false; }
 
   void AssignToPools(const std::vector<const DSNode*> &NodesToPA,
@@ -618,20 +666,51 @@
   }
 };
 
-//===----------------------------------------------------------------------===//
-// Heuristic dispatch support
 //
+// Register all of the heuristic passes.
+//
+static RegisterPass<AllNodesHeuristic>
+A ("paheur-AllNodes", "Pool allocate all nodes");
+
+static RegisterPass<AllButUnreachableFromMemoryHeuristic>
+B ("paheur-AllButUnreachableFromMemory", "Pool allocate all reachable from memory objects");
+
+static RegisterPass<CyclicNodesHeuristic>
+C ("paheur-CyclicNodes", "Pool allocate nodes with cycles");
+
+static RegisterPass<SmartCoallesceNodesHeuristic>
+D ("paheur-SmartCoallesceNodes", "Pool allocate using the smart node merging heuristic ");
+
+static RegisterPass<AllInOneGlobalPoolHeuristic>
+E ("paheur-AllInOneGlobalPool", "Pool allocate using the pool library to replace malloc/free");
+
+static RegisterPass<OnlyOverheadHeuristic>
+F ("paheur-OnlyOverhead", "Do not pool allocate anything, but induce all overhead from it");
+
+static RegisterPass<NoNodesHeuristic>
+G ("paheur-NoNodes", "Pool allocate nothing");
+
+//
+// Create the heuristic analysis group.
+//
+static RegisterAnalysisGroup<Heuristic>
+HeuristicGroup ("Pool Allocation Heuristic");
+
+RegisterAnalysisGroup<Heuristic> Heuristic1(A);
+RegisterAnalysisGroup<Heuristic, true> Heuristic2(B);
+RegisterAnalysisGroup<Heuristic> Heuristic3(C);
+RegisterAnalysisGroup<Heuristic> Heuristic4(D);
+RegisterAnalysisGroup<Heuristic> Heuristic5(E);
+RegisterAnalysisGroup<Heuristic> Heuristic6(F);
+RegisterAnalysisGroup<Heuristic> Heuristic7(G);
+
+char Heuristic::ID = 0;
+char AllNodesHeuristic::ID = 0;
+char AllButUnreachableFromMemoryHeuristic::ID = 0;
+char CyclicNodesHeuristic::ID = 0;
+char SmartCoallesceNodesHeuristic::ID = 0;
+char AllInOneGlobalPoolHeuristic::ID = 0;
+char OnlyOverheadHeuristic::ID = 0;
+char NoNodesHeuristic::ID = 0;
+
 
-PA::Heuristic *Heuristic::create() {
-  switch (TheHeuristic) {
-  default: assert(0 && "Unknown heuristic!");
-  case AllNodes: return new AllNodesHeuristic();
-  case AllButUnreachableFromMemory:
-    return new AllButUnreachableFromMemoryHeuristic();
-  case CyclicNodes: return new CyclicNodesHeuristic();
-  case SmartCoallesceNodes: return new SmartCoallesceNodesHeuristic();
-  case AllInOneGlobalPool: return new AllInOneGlobalPoolHeuristic();
-  case OnlyOverhead: return new OnlyOverheadHeuristic();
-  case NoNodes: return new NoNodesHeuristic();
-  }
-}

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=114729&r1=114728&r2=114729&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Fri Sep 24 10:15:21 2010
@@ -106,6 +106,8 @@
 }
 
 void PoolAllocate::getAnalysisUsage(AnalysisUsage &AU) const {
+  // We will need the heuristic pass to tell us what to do and how to do it
+  AU.addRequiredTransitive<Heuristic>();
   if (dsa_pass_to_use == PASS_EQTD) {
     AU.addRequiredTransitive<EQTDDataStructures>();
     if(lie_preserve_passes != LIE_NONE)
@@ -146,8 +148,11 @@
   else
     Graphs = &getAnalysis<EquivBUDataStructures>();
 
-  CurHeuristic = Heuristic::create();
-  CurHeuristic->Initialize(M, Graphs->getGlobalsGraph(), *this);
+  //
+  // Get the heuristic pass and then tell it who we are.
+  //
+  CurHeuristic = &getAnalysis<Heuristic>();
+  CurHeuristic->Initialize (*this);
 
   // Add the pool* prototypes to the module
   AddPoolPrototypes(&M);
@@ -325,7 +330,6 @@
     MicroOptimizePoolCalls();
   #endif
  
-  delete CurHeuristic;
   return true;
 }
 

Modified: poolalloc/trunk/test/TEST.poolalloc.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.poolalloc.Makefile?rev=114729&r1=114728&r2=114729&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.poolalloc.Makefile (original)
+++ poolalloc/trunk/test/TEST.poolalloc.Makefile Fri Sep 24 10:15:21 2010
@@ -67,18 +67,18 @@
 $(PROGRAMS_TO_TEST:%=Output/%.basepa.bc): \
 Output/%.basepa.bc: Output/%.base.bc $(PA_SO) $(LOPT)
 	- at rm -f $(CURDIR)/$@.info
-	-$(OPT_PA_STATS) -poolalloc -poolalloc-disable-alignopt -poolalloc-force-all-poolfrees -poolalloc-heuristic=AllNodes $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out
+	-$(OPT_PA_STATS) -paheur-AllNodes -poolalloc -poolalloc-disable-alignopt -poolalloc-force-all-poolfrees $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out
 
 
 $(PROGRAMS_TO_TEST:%=Output/%.mallocrepl.bc): \
 Output/%.mallocrepl.bc: Output/%.base.bc $(PA_SO) $(LOPT)
 	- at rm -f $(CURDIR)/$@.info
-	-$(OPT_PA_STATS) -poolalloc -poolalloc-heuristic=AllInOneGlobalPool $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out
+	-$(OPT_PA_STATS) -paheur-AllInOneGlobalPool -poolalloc $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out
 
 $(PROGRAMS_TO_TEST:%=Output/%.onlyoverhead.bc): \
 Output/%.onlyoverhead.bc: Output/%.base.bc $(PA_SO) $(LOPT)
 	- at rm -f $(CURDIR)/$@.info
-	-$(OPT_PA_STATS) -poolalloc -poolalloc-heuristic=OnlyOverhead $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out
+	-$(OPT_PA_STATS) -paheur-OnlyOverhead -poolalloc $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out
 
 $(PROGRAMS_TO_TEST:%=Output/%.nonpa.bc): \
 Output/%.nonpa.bc: Output/%.base.bc $(LOPT)



From daniel at zuster.org  Fri Sep 24 12:10:26 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 17:10:26 -0000
Subject: [llvm-commits] [llvm] r114733 - in /llvm/trunk:
 lib/MC/MCParser/AsmLexer.cpp test/MC/AsmParser/floating-literals.s
Message-ID: <20100924171026.52CA02A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 12:10:26 2010
New Revision: 114733

URL: http://llvm.org/viewvc/llvm-project?rev=114733&view=rev
Log:
MC/AsmParser: Handle a missed case of floating literals in the lexer.

Modified:
    llvm/trunk/lib/MC/MCParser/AsmLexer.cpp
    llvm/trunk/test/MC/AsmParser/floating-literals.s

Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=114733&r1=114732&r2=114733&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Fri Sep 24 12:10:26 2010
@@ -145,7 +145,7 @@
 ///   Decimal integer: [1-9][0-9]*
 AsmToken AsmLexer::LexDigit() {
   // Decimal integer: [1-9][0-9]*
-  if (CurPtr[-1] != '0') {
+  if (CurPtr[-1] != '0' || CurPtr[0] == '.') {
     while (isdigit(*CurPtr))
       ++CurPtr;
 

Modified: llvm/trunk/test/MC/AsmParser/floating-literals.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/floating-literals.s?rev=114733&r1=114732&r2=114733&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/floating-literals.s (original)
+++ llvm/trunk/test/MC/AsmParser/floating-literals.s Fri Sep 24 12:10:26 2010
@@ -10,3 +10,6 @@
 # CHECK: .quad	4597526701198935065
 # CHECK: .quad	-4600933674317040845
 .double 5, .232, -11.1
+
+# CHECK: .quad  0
+.double 0.0



From nicolas.geoffray at lip6.fr  Fri Sep 24 12:27:50 2010
From: nicolas.geoffray at lip6.fr (Nicolas Geoffray)
Date: Fri, 24 Sep 2010 17:27:50 -0000
Subject: [llvm-commits] [llvm] r114736 - in /llvm/trunk:
 include/llvm/CodeGen/GCMetadata.h lib/CodeGen/GCStrategy.cpp
Message-ID: <20100924172750.3080F2A6C12C@llvm.org>

Author: geoffray
Date: Fri Sep 24 12:27:50 2010
New Revision: 114736

URL: http://llvm.org/viewvc/llvm-project?rev=114736&view=rev
Log:
Attach a DebugLoc to a GC point in order to get precise information in the JIT of a GC point.


Modified:
    llvm/trunk/include/llvm/CodeGen/GCMetadata.h
    llvm/trunk/lib/CodeGen/GCStrategy.cpp

Modified: llvm/trunk/include/llvm/CodeGen/GCMetadata.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GCMetadata.h?rev=114736&r1=114735&r2=114736&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GCMetadata.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GCMetadata.h Fri Sep 24 12:27:50 2010
@@ -36,6 +36,7 @@
 #include "llvm/Pass.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/StringMap.h"
+#include "llvm/Support/DebugLoc.h"
 
 namespace llvm {
   class AsmPrinter;
@@ -59,8 +60,10 @@
   struct GCPoint {
     GC::PointKind Kind; //< The kind of the safe point.
     MCSymbol *Label;    //< A label.
+    DebugLoc Loc;
 
-    GCPoint(GC::PointKind K, MCSymbol *L) : Kind(K), Label(L) {}
+    GCPoint(GC::PointKind K, MCSymbol *L, DebugLoc DL)
+        : Kind(K), Label(L), Loc(DL) {}
   };
 
   /// GCRoot - Metadata for a pointer to an object managed by the garbage
@@ -121,8 +124,8 @@
     /// addSafePoint - Notes the existence of a safe point. Num is the ID of the
     /// label just prior to the safe point (if the code generator is using
     /// MachineModuleInfo).
-    void addSafePoint(GC::PointKind Kind, MCSymbol *Label) {
-      SafePoints.push_back(GCPoint(Kind, Label));
+    void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) {
+      SafePoints.push_back(GCPoint(Kind, Label, DL));
     }
 
     /// getFrameSize/setFrameSize - Records the function's frame size.

Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCStrategy.cpp?rev=114736&r1=114735&r2=114736&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GCStrategy.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCStrategy.cpp Fri Sep 24 12:27:50 2010
@@ -345,13 +345,15 @@
   MachineBasicBlock::iterator RAI = CI; 
   ++RAI;                                
   
-  if (FI->getStrategy().needsSafePoint(GC::PreCall))
-    FI->addSafePoint(GC::PreCall, InsertLabel(*CI->getParent(), CI,
-                                              CI->getDebugLoc()));
-  
-  if (FI->getStrategy().needsSafePoint(GC::PostCall))
-    FI->addSafePoint(GC::PostCall, InsertLabel(*CI->getParent(), RAI,
-                                               CI->getDebugLoc()));
+  if (FI->getStrategy().needsSafePoint(GC::PreCall)) {
+    MCSymbol* Label = InsertLabel(*CI->getParent(), CI, CI->getDebugLoc());
+    FI->addSafePoint(GC::PreCall, Label, CI->getDebugLoc());
+  }
+  
+  if (FI->getStrategy().needsSafePoint(GC::PostCall)) {
+    MCSymbol* Label = InsertLabel(*CI->getParent(), RAI, CI->getDebugLoc());
+    FI->addSafePoint(GC::PostCall, Label, CI->getDebugLoc());
+  }
 }
 
 void MachineCodeAnalysis::FindSafePoints(MachineFunction &MF) {



From fjahanian at apple.com  Fri Sep 24 12:32:09 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Fri, 24 Sep 2010 17:32:09 -0000
Subject: [llvm-commits] [test-suite] r114738 -
	/test-suite/trunk/SingleSource/UnitTests/vla.c
Message-ID: <20100924173209.B2B722A6C12C@llvm.org>

Author: fjahanian
Date: Fri Sep 24 12:32:09 2010
New Revision: 114738

URL: http://llvm.org/viewvc/llvm-project?rev=114738&view=rev
Log:
Test for pr7827 (clang).

Added:
    test-suite/trunk/SingleSource/UnitTests/vla.c

Added: test-suite/trunk/SingleSource/UnitTests/vla.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/vla.c?rev=114738&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/vla.c (added)
+++ test-suite/trunk/SingleSource/UnitTests/vla.c Fri Sep 24 12:32:09 2010
@@ -0,0 +1,36 @@
+#include <stdio.h>
+extern void abort();
+
+int bork[4][3] = { 1,2,3,4,5,6,7,8,9,10,11,12};
+void function(short width, int data[][width]) {
+  int i,j;
+  for (i = 0; i < 4; i++)
+    for (j = 0; j < width; j++)
+      if (bork[i][j] != data[i][j])
+	abort();
+}
+
+
+void test() {
+     function(3, bork);
+}
+
+int bork2[2][3][4] = { 1,2,3,4,5,6,7,8,9,10,11,12, 13,14,15,16,17,18,19,20,21,22,23,24};
+void function2(short width, short width2, int data[][width][width2]) {
+  int i,j,k;
+  for (i = 0; i < 2; i++)
+    for (j = 0; j < width; j++)
+      for (k = 0; k < width2; k++)
+        if (bork2[i][j][k] != data[i][j][k])
+          abort();
+}
+
+
+void test2() {
+     function2(3, 4, bork2);
+}
+int main() {
+  test();
+  test2();
+  return 0;
+}



From stoklund at 2pi.dk  Fri Sep 24 12:43:32 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 10:43:32 -0700
Subject: [llvm-commits] [zorg] r114546 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
In-Reply-To: <20100922154020.DF2A12A6C12C@llvm.org>
References: <20100922154020.DF2A12A6C12C@llvm.org>
Message-ID: <D4AC81E6-D9A0-4146-BE70-52E3F04A87E8@2pi.dk>


On Sep 22, 2010, at 8:40 AM, Duncan Sands wrote:

> +        {'name' : "llvm-x86_64-linux-checks",
> +        'slavenames':["gcc10"],
> +        'builddir':"llvm-x86_64-linux-checks",
> +        'factory':LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", expensive_checks=True)}

nice -n 10 make -jx86_64-pc-linux-gnu
make: the `-j' option requires a positive integral argument

It looks like 'jobs=N' isn't so optional...




From evan.cheng at apple.com  Fri Sep 24 12:48:16 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 10:48:16 -0700
Subject: [llvm-commits] [llvm] r114681	-
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <4C9C52D8.3090708@free.fr>
References: <20100923183219.35D1D2A6C12C@llvm.org> <4C9C52D8.3090708@free.fr>
Message-ID: <707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>

There is definitely a codegen bug downstream. A unconditional branch to a fallthrough block is correct the last time I checked. If someone has some time to look into this, I would appreciate a test case.

Evan

On Sep 24, 2010, at 12:27 AM, Duncan Sands wrote:

>> Revert 114634 for now since buildbot claim it broke Clang self-hosting. I doubt it but it's possible it's exposing another bug somewhere.
> 
> Thanks Evan.  Reverting this also fixed the dragonegg self-host.
> 
> Ciao,
> 
> Duncan.
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From stoklund at 2pi.dk  Fri Sep 24 13:49:05 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 11:49:05 -0700
Subject: [llvm-commits] [llvm] r114681	-
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>
References: <20100923183219.35D1D2A6C12C@llvm.org> <4C9C52D8.3090708@free.fr>
	<707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>
Message-ID: <37BE4EFC-83BD-4696-8472-F85A74D6F3AF@2pi.dk>


On Sep 24, 2010, at 10:48 AM, Evan Cheng wrote:

> There is definitely a codegen bug downstream. A unconditional branch to a fallthrough block is correct the last time I checked. If someone has some time to look into this, I would appreciate a test case.

It looks like MachineBasicBlock::canFallThrough affects codegen which could trigger this bug, and MachineBasicBlock::updateTerminator looks like it is going to undo it anyway by removing the unconditional branch.

Is any code assuming the presence of an unconditional branch?

/jakob



From rafael.espindola at gmail.com  Fri Sep 24 13:48:09 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Sep 2010 18:48:09 -0000
Subject: [llvm-commits] [llvm] r114742 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/local-reloc.s
Message-ID: <20100924184809.212B72A6C12C@llvm.org>

Author: rafael
Date: Fri Sep 24 13:48:08 2010
New Revision: 114742

URL: http://llvm.org/viewvc/llvm-project?rev=114742&view=rev
Log:
Revert 114678 and 114667 to see if

http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost

gets happy.

Removed:
    llvm/trunk/test/MC/ELF/local-reloc.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114742&r1=114741&r2=114742&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Fri Sep 24 13:48:08 2010
@@ -515,12 +515,9 @@
     }
 
     if (Base) {
-      if (F && !SD.isExternal()) {
+      if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
-
-        MCSectionData *FSD = F->getParent();
-        // Offset of the symbol in the section
-        Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
+        Value += Layout.getSymbolAddress(&SD);
       } else
         Index = getSymbolIndexInSymbolTable(Asm, Symbol);
       if (Base != &SD)

Removed: llvm/trunk/test/MC/ELF/local-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/local-reloc.s?rev=114741&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/local-reloc.s (original)
+++ llvm/trunk/test/MC/ELF/local-reloc.s (removed)
@@ -1,32 +0,0 @@
-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
-
-// Test that relocations with local symbols are represented as relocations
-// with the section. They should be equivalent, but gas behaves like this.
-
-	movl	foo, %r14d
-foo:
-
-// Section number 1 is .text
-// CHECK:        # Section 1
-// CHECK-next:  (('sh_name', 1) # '.text'
-
-
-// Relocation refers to symbol number 2
-// CHECK:      ('_relocations', [
-// CHECK-NEXT:  # Relocation 0
-// CHECK-NEXT:   (('r_offset',
-// CHECK-NEXT:    ('r_sym', 2)
-// CHECK-NEXT:    ('r_type',
-// CHECK-NEXT:    ('r_addend',
-// CHECK-NEXT:   ),
-// CHECK-NEXT:  ])
-
-// Symbol number 2 is section number 1
-// CHECK:    # Symbol 2
-// CHECK-NEXT:    (('st_name', 0) # ''
-// CHECK-NEXT:     ('st_bind', 0)
-// CHECK-NEXT:     ('st_type', 3)
-// CHECK-NEXT:     ('st_other', 0)
-// CHECK-NEXT:     ('st_shndx', 1)
-// CHECK-NEXT:     ('st_value', 0)
-// CHECK-NEXT:     ('st_size', 0)



From daniel at zuster.org  Fri Sep 24 13:52:28 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 18:52:28 -0000
Subject: [llvm-commits] [zorg] r114743 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100924185228.191122A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 13:52:27 2010
New Revision: 114743

URL: http://llvm.org/viewvc/llvm-project?rev=114743&view=rev
Log:
buildbot: Disable some offline builders.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114743&r1=114742&r2=114743&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Sep 24 13:52:27 2010
@@ -32,10 +32,10 @@
          'slavenames': ["dunbar1"],
          'builddir': "llvm-i686", 
          'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", jobs=2, enable_shared=True)},
-        {'name': "llvm-x86_64-linux",
-         'slavenames': ["osu1"],
-         'builddir': "llvm-x86_64",
-         'factory': LLVMBuilder.getLLVMBuildFactory(triple="x86_64-pc-linux-gnu")},
+#        {'name': "llvm-x86_64-linux",
+#         'slavenames': ["osu1"],
+#         'builddir': "llvm-x86_64",
+#         'factory': LLVMBuilder.getLLVMBuildFactory(triple="x86_64-pc-linux-gnu")},
         {'name': "llvm-arm-linux",
          'slavenames':["ranby1"],
          'builddir':"llvm-arm-linux",
@@ -126,10 +126,10 @@
 # Clang builders.
 def _get_clang_builders():
     return [
-        {'name': "clang-x86_64-linux",
-         'slavenames':["osu1"],
-         'builddir':"clang-x86_64-linux",
-         'factory': ClangBuilder.getClangBuildFactory(examples=True)},
+#        {'name': "clang-x86_64-linux",
+#         'slavenames':["osu1"],
+#         'builddir':"clang-x86_64-linux",
+#         'factory': ClangBuilder.getClangBuildFactory(examples=True)},
         {'name': "clang-i686-linux",
          'slavenames':["dunbar1"],
          'builddir':"clang-i686-linux",
@@ -521,11 +521,11 @@
                                                        stage2_config='Release+Asserts'),
          'category' : 'clang.exp' },
 
-        {'name' : "clang-i686-xp-msvc9_alt",
-         'slavenames' :['adobe1'],
-         'builddir' :"clang-i686-xp-msvc9_alt",
-         'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2),
-         'category' : 'clang.exp' },
+#        {'name' : "clang-i686-xp-msvc9_alt",
+#         'slavenames' :['adobe1'],
+#         'builddir' :"clang-i686-xp-msvc9_alt",
+#         'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2),
+#         'category' : 'clang.exp' },
 
         {'name': "clang-i686-freebsd-selfhost-rel",
          'slavenames':["freebsd1"],



From criswell at uiuc.edu  Fri Sep 24 14:05:43 2010
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 24 Sep 2010 19:05:43 -0000
Subject: [llvm-commits] [poolalloc] r114744 -
	/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
Message-ID: <20100924190543.1287F2A6C12C@llvm.org>

Author: criswell
Date: Fri Sep 24 14:05:42 2010
New Revision: 114744

URL: http://llvm.org/viewvc/llvm-project?rev=114744&view=rev
Log:
Removed dead code (the MarkNodesWhichMustBePassedIn() functions).
No functionality changes.

Modified:
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=114744&r1=114743&r2=114744&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Fri Sep 24 14:05:42 2010
@@ -550,186 +550,6 @@
 }
 
 //
-// Function: MarkNodesWhichMustBePassedIn()
-//
-// Description:
-//  Given a function and its DSGraph, determine which values will need to have
-//  their pools passed in from the caller.
-//
-// Inputs:
-//  F                - A reference to the function to analyze.
-//  G                - The DSGraph of the function F.
-//  PassAllArguments - Flags whether all arguments should have their pool
-//                     handles passed into the function.
-//
-// Outputs:
-//  MarkedNodes      - A set of DSNodes whose associated pools should be
-//                     passed into the function when it is called.
-//
-static inline void
-MarkNodesWhichMustBePassedIn (DenseSet<const DSNode*> &MarkedNodes,
-                              Function &F, DSGraph* G,
-                              bool PassAllArguments) {
-  // Mark globals and incomplete nodes as live... (this handles arguments)
-
-  //
-  // Scan through all of the function's arguments.  If they have an associated
-  // DSNode, then we need to pass the argument's pool handle into the function.
-  // The only exception is for byval arguments.  These may have a DSNode, but
-  // they are allocated magically by the code generator; the caller has no
-  // pool for them.
-  //
-  // We also need to pass in pools for any value that is reachable via a
-  // function argument.
-  //
-  // Of course, skip this if this function is the main() function.  We can't
-  // really add pools to main().  :)
-  //
-  // FIXME: This needs to handle varargs properly.
-  //
-  if (F.getName() != "main") {
-    //
-    // Scan through all of the argument of this function.
-    //
-    for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
-         I != E; ++I) {
-      //
-      // All DSNodes reachable from arguments must be passed in.
-      //
-      DSGraph::ScalarMapTy::iterator AI = G->getScalarMap().find(I);
-
-      //
-      // Assert that we either have a non-pointer parameter or that we have a
-      // an entry in the Scalar Map for this item.
-      //
-      if (AI != G->getScalarMap().end()) {
-        if (DSNode *N = AI->second.getNode()) {
-          //
-          // Find all nodes reachable from this node.  Include this node, even
-          // if it is a byval argument.
-          //
-          // Now, I hear what you're thinking: "Why pass pools for byval
-          // arguments?"  Well, we want to pass pools for byval arguments
-          // because the function may be the target of an indirect function
-          // call, and the byval parameter could therefore alias with a
-          // non-byval argument from another function that is a target of the
-          // indirect function call.  Passing pools for byval arguments helps
-          // ensure that all targets of an indirect function call get
-          // transformed identically.
-          //
-
-          //
-          // Add all nodes reachable from this parameter into our set of
-          // nodes needing pools.
-          //
-          N->markReachableNodes(MarkedNodes);
-        }
-      }
-    }
-
-    //
-    // Mark the returned node as needing to be passed in.
-    //
-    if (DSNode *RetNode = G->getReturnNodeFor(F).getNode())
-      RetNode->markReachableNodes(MarkedNodes);
-  }
-
-  //
-  // Calculate which DSNodes are reachable from globals.  If a node is reachable
-  // from a global, we will create a global pool for it, so no argument passage
-  // is required.
-  //
-  DenseSet<const DSNode*> NodesFromGlobals;
-  GetNodesReachableFromGlobals(G, NodesFromGlobals);
-
-  //
-  // Remove any nodes reachable from a global.  These nodes will be put into
-  // global pools, which do not require arguments to be passed in.  Also, erase
-  // any marked node that is not a heap node.  Since no allocations or frees
-  // will be done with it, it needs no argument.
-  //
-  // FIXME:
-  //  1) PassAllArguments seems to be ignored here.  Why is that?
-  //  2) Should the heap node check be part of the PassAllArguments check?
-  //  3) SAFECode probably needs to pass the pool even if it's not a heap node.
-  //     We should probably just do what the heuristic tells us to do.
-  //
-  for (DenseSet<const DSNode*>::iterator I = MarkedNodes.begin(),
-         E = MarkedNodes.end(); I != E; ) {
-    const DSNode *N = *I; ++I;
-    if ((!(1 || N->isHeapNode()) && !PassAllArguments) || NodesFromGlobals.count(N))
-      MarkedNodes.erase(N);
-  }
-}
-
-//
-// Function: RemoveGlobalNodes()
-//
-// Description:
-//  Given a function and its DSGraph, determine which values will need to have
-//  their pools passed in from the caller.
-//
-// Inputs:
-//  RootNodes        - The root DSNodes for which pools may need to be passed
-//                     in.  These include the DSNodes of any arguments, the
-//                     DSNode of the return value, and the VarArgs DSNode.
-//  G                - The DSGraph of the function F.
-//  PassAllArguments - Flags whether all arguments should have their pool
-//                     handles passed into the function.
-//
-// Outputs:
-//  MarkedNodes      - A set of DSNodes whose associated pools should be
-//                     passed into the function when it is called.
-//
-static inline void
-MarkNodesWhichMustBePassedIn (DenseSet<const DSNode*> &MarkedNodes,
-                              const std::vector<DSNodeHandle> & RootNodes,
-                              DSGraph* G,
-                              bool PassAllArguments) {
-  //
-  // Loop through all of the root DSNodes.  Insert them and any DSNode
-  // reachable from them into the set of DSNodes for which a pool descriptor
-  // must be passed.
-  //
-  for (unsigned index = 0; index < RootNodes.size(); ++index) {
-    if (DSNode * N = RootNodes[index].getNode()) {
-      MarkedNodes.insert (N);
-      N->markReachableNodes(MarkedNodes);
-    }
-  }
-
-  //
-  // Determine which DSNodes are reachable from globals.  If a node is
-  // reachable from a global, we will create a global pool for it, so no
-  // argument passage is required.
-  //
-  DenseSet<const DSNode*> NodesFromGlobals;
-  GetNodesReachableFromGlobals (G, NodesFromGlobals);
-
-  //
-  // Remove any nodes reachable from a global.  These nodes will be put into
-  // global pools, which do not require arguments to be passed in.  Also, erase
-  // any marked node that is not a heap node.  Since no allocations or frees
-  // will be done with it, it needs no argument.
-  //
-  // FIXME:
-  //  1) PassAllArguments seems to be ignored here.  Why is that?
-  //  2) Should the heap node check be part of the PassAllArguments check?
-  //  3) SAFECode probably needs to pass the pool even if it's not a heap node.
-  //     We should probably just do what the heuristic tells us to do.
-  //
-  for (DenseSet<const DSNode*>::iterator I = MarkedNodes.begin(),
-         E = MarkedNodes.end(); I != E; ) {
-    const DSNode *N = *I; ++I;
-    if ((!(1 || N->isHeapNode()) && !PassAllArguments) || NodesFromGlobals.count(N))
-      MarkedNodes.erase(N);
-  }
-
-  return;
-}
-
-
-//
 // Method: FindPoolArgs()
 //
 // Description:



From dalej at apple.com  Fri Sep 24 14:05:48 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 24 Sep 2010 19:05:48 -0000
Subject: [llvm-commits] [llvm] r114745 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100924190548.AAF7E2A6C12D@llvm.org>

Author: johannes
Date: Fri Sep 24 14:05:48 2010
New Revision: 114745

URL: http://llvm.org/viewvc/llvm-project?rev=114745&view=rev
Log:
We can't return SSE/MMX vectors if SSE is disabled.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=114745&r1=114744&r2=114745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 24 14:05:48 2010
@@ -1315,9 +1315,11 @@
     SDValue ValToCopy = OutVals[i];
     EVT ValVT = ValToCopy.getValueType();
 
-    // If this is x86-64, and we disabled SSE, we can't return FP values
-    if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
-        (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
+    // If this is x86-64, and we disabled SSE, we can't return FP values,
+    // or SSE or MMX vectors.
+    if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
+         VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
+          (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
       report_fatal_error("SSE register return with SSE disabled");
     }
     // Likewise we can't return F64 values with SSE1 only.  gcc does so, but



From evan.cheng at apple.com  Fri Sep 24 14:07:51 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 12:07:51 -0700
Subject: [llvm-commits] [llvm] r114681	-
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <37BE4EFC-83BD-4696-8472-F85A74D6F3AF@2pi.dk>
References: <20100923183219.35D1D2A6C12C@llvm.org> <4C9C52D8.3090708@free.fr>
	<707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>
	<37BE4EFC-83BD-4696-8472-F85A74D6F3AF@2pi.dk>
Message-ID: <6426039E-DD38-44D5-B30B-84A7EE32AF20@apple.com>


On Sep 24, 2010, at 11:49 AM, Jakob Stoklund Olesen wrote:

> 
> On Sep 24, 2010, at 10:48 AM, Evan Cheng wrote:
> 
>> There is definitely a codegen bug downstream. A unconditional branch to a fallthrough block is correct the last time I checked. If someone has some time to look into this, I would appreciate a test case.
> 
> It looks like MachineBasicBlock::canFallThrough affects codegen which could trigger this bug, and MachineBasicBlock::updateTerminator looks like it is going to undo it anyway by removing the unconditional branch.
> 
> Is any code assuming the presence of an unconditional branch?

I sure hope not. The reason for this change some DAG transformations require the presence of the unconditional branch following a conditional one so it can flip them. With this case, a lot of fcmp_oeq can be optimized to a pair of conditional branches, rather than two setcc and an and.

I've verified machine instruction passes will eliminate the branch to fallthrough. I wonder if we could disable branch folding and see if more miscompilations show up.

Evan

> 
> /jakob
> 



From evan.cheng at apple.com  Fri Sep 24 14:07:23 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 19:07:23 -0000
Subject: [llvm-commits] [llvm] r114746 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll
 test/CodeGen/ARM/code-placement.ll
Message-ID: <20100924190723.D94142A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 14:07:23 2010
New Revision: 114746

URL: http://llvm.org/viewvc/llvm-project?rev=114746&view=rev
Log:
Enable code placement optimization pass for ARM.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
    llvm/trunk/test/CodeGen/ARM/code-placement.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=114746&r1=114745&r2=114746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep 24 14:07:23 2010
@@ -76,11 +76,6 @@
   cl::desc("Enable / disable ARM interworking (for debugging only)"),
   cl::init(true));
 
-static cl::opt<bool>
-EnableARMCodePlacement("arm-code-placement", cl::Hidden,
-  cl::desc("Enable code placement pass for ARM"),
-  cl::init(false));
-
 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
                                        EVT PromotedBitwiseVT) {
   if (VT != PromotedLdStVT) {
@@ -550,8 +545,7 @@
   // are at least 4 bytes aligned.
   setMinStackArgumentAlignment(4);
 
-  if (EnableARMCodePlacement)
-    benefitFromCodePlacementOpt = true;
+  benefitFromCodePlacementOpt = true;
 }
 
 std::pair<const TargetRegisterClass*, uint8_t>

Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=114746&r1=114745&r2=114746&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Fri Sep 24 14:07:23 2010
@@ -18,13 +18,13 @@
   %0 = ptrtoint i8* %tmp2 to i32
 
 ; CHECK:      ands r12, r12, #3
-; CHECK-NEXT: beq LBB0_4
+; CHECK-NEXT: beq LBB0_2
 
 ; T2:      movs r5, #3
 ; T2-NEXT: mov r6, r4
 ; T2-NEXT: ands r6, r5
 ; T2-NEXT: tst r4, r5
-; T2-NEXT: beq LBB0_5
+; T2-NEXT: beq LBB0_3
 
   %and = and i32 %0, 3
   %tst = icmp eq i32 %and, 0

Modified: llvm/trunk/test/CodeGen/ARM/code-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/code-placement.ll?rev=114746&r1=114745&r2=114746&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/code-placement.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/code-placement.ll Fri Sep 24 14:07:23 2010
@@ -5,8 +5,9 @@
 %struct.list_data_s = type { i16, i16 }
 %struct.list_head = type { %struct.list_head*, %struct.list_data_s* }
 
-define arm_apcscc %struct.list_head* @t(%struct.list_head* %list) nounwind {
+define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
 entry:
+; CHECK: t1:
   %0 = icmp eq %struct.list_head* %list, null
   br i1 %0, label %bb2, label %bb
 
@@ -27,3 +28,51 @@
   %next.0.lcssa = phi %struct.list_head* [ null, %entry ], [ %list_addr.05, %bb ]
   ret %struct.list_head* %next.0.lcssa
 }
+
+; Optimize loop entry, eliminate intra loop branches
+; rdar://8117827
+define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
+entry:
+; CHECK: t2:
+; CHECK: beq LBB1_5
+  %0 = icmp eq i32 %passes, 0                     ; <i1> [#uses=1]
+  br i1 %0, label %bb5, label %bb.nph15
+
+; CHECK: LBB1_2
+bb1:                                              ; preds = %bb2.preheader, %bb1
+; CHECK: LBB1_3:
+; CHECK: bne LBB1_3
+  %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]
+  %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]
+  %tmp17 = sub i32 %i.07, %indvar                 ; <i32> [#uses=1]
+  %scevgep = getelementptr i32* %src, i32 %tmp17  ; <i32*> [#uses=1]
+  %1 = load i32* %scevgep, align 4                ; <i32> [#uses=1]
+  %2 = add nsw i32 %1, %sum.08                    ; <i32> [#uses=2]
+  %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=2]
+  %exitcond = icmp eq i32 %indvar.next, %size     ; <i1> [#uses=1]
+  br i1 %exitcond, label %bb3, label %bb1
+
+bb3:                                              ; preds = %bb1, %bb2.preheader
+; CHECK: LBB1_4
+; CHECK: bne LBB1_2
+; CHECK-NOT: b LBB1_
+; CHECK: ldmia sp!
+  %sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; <i32> [#uses=2]
+  %3 = add i32 %pass.011, 1                       ; <i32> [#uses=2]
+  %exitcond18 = icmp eq i32 %3, %passes           ; <i1> [#uses=1]
+  br i1 %exitcond18, label %bb5, label %bb2.preheader
+
+bb.nph15:                                         ; preds = %entry
+  %i.07 = add i32 %size, -1                       ; <i32> [#uses=2]
+  %4 = icmp sgt i32 %i.07, -1                     ; <i1> [#uses=1]
+  br label %bb2.preheader
+
+bb2.preheader:                                    ; preds = %bb3, %bb.nph15
+  %pass.011 = phi i32 [ 0, %bb.nph15 ], [ %3, %bb3 ] ; <i32> [#uses=1]
+  %sum.110 = phi i32 [ 0, %bb.nph15 ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=2]
+  br i1 %4, label %bb1, label %bb3
+
+bb5:                                              ; preds = %bb3, %entry
+  %sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=1]
+  ret i32 %sum.1.lcssa
+}



From bigcheesegs at gmail.com  Fri Sep 24 14:10:51 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 19:10:51 -0000
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
Message-ID: <20100924191051.A24F42A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 14:10:51 2010
New Revision: 114747

URL: http://llvm.org/viewvc/llvm-project?rev=114747&view=rev
Log:
CMake: Don't include tools, unittets, or examples as available targets
unless LLVM_INCLUDE_X is ON. LLVM_BUILD_X implies LLVM_INCLUDE_X

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/cmake/modules/AddLLVM.cmake
    llvm/trunk/unittests/CMakeLists.txt
    llvm/trunk/utils/unittest/CMakeLists.txt

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=114747&r1=114746&r2=114747&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Fri Sep 24 14:10:51 2010
@@ -364,12 +364,18 @@
 add_subdirectory(projects)
 
 option(LLVM_BUILD_TOOLS "Build LLVM tool programs." ON)
+option(LLVM_INCLUDE_TOOLS
+  "Include LLVM tool programs as an available target." ON)
 add_subdirectory(tools)
 
 option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF)
+option(LLVM_INCLUDE_EXAMPLES
+  "Include LLVM example programs as an available target." OFF)
 add_subdirectory(examples)
 
 option(LLVM_BUILD_TESTS "Build LLVM unit tests." OFF)
+option(LLVM_INCLUDE_TESTS
+  "Include LLVM unit tests as an available target." OFF)
 add_subdirectory(test)
 add_subdirectory(utils/unittest)
 add_subdirectory(unittests)

Modified: llvm/trunk/cmake/modules/AddLLVM.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=114747&r1=114746&r2=114747&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/AddLLVM.cmake (original)
+++ llvm/trunk/cmake/modules/AddLLVM.cmake Fri Sep 24 14:10:51 2010
@@ -77,7 +77,9 @@
   if( NOT LLVM_BUILD_TOOLS )
     set(EXCLUDE_FROM_ALL ON)
   endif()
-  add_llvm_executable(${name} ${ARGN})
+  if( LLVM_INCLUDE_TOOLS OR LLVM_BUILD_TOOLS )
+    add_llvm_executable(${name} ${ARGN})
+  endif()
   if( LLVM_BUILD_TOOLS )
     install(TARGETS ${name} RUNTIME DESTINATION bin)
   endif()
@@ -89,7 +91,9 @@
   if( NOT LLVM_BUILD_EXAMPLES )
     set(EXCLUDE_FROM_ALL ON)
   endif()
-  add_llvm_executable(${name} ${ARGN})
+  if( LLVM_INCLUDE_EXAMPLES OR LLVM_BUILD_EXAMPLES )
+    add_llvm_executable(${name} ${ARGN})
+  endif()
   if( LLVM_BUILD_EXAMPLES )
     install(TARGETS ${name} RUNTIME DESTINATION examples)
   endif()

Modified: llvm/trunk/unittests/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=114747&r1=114746&r2=114747&view=diff
==============================================================================
--- llvm/trunk/unittests/CMakeLists.txt (original)
+++ llvm/trunk/unittests/CMakeLists.txt Fri Sep 24 14:10:51 2010
@@ -9,7 +9,9 @@
   if( NOT LLVM_BUILD_TESTS )
     set(EXCLUDE_FROM_ALL ON)
   endif()
-  add_llvm_executable(${test_name}Tests ${ARGN})
+  if (LLVM_INCLUDE_TESTS OR LLVM_BUILD_TESTS)
+    add_llvm_executable(${test_name}Tests ${ARGN})
+  endif()
 endfunction()
 
 include_directories(${LLVM_MAIN_SRC_DIR}/utils/unittest/googletest/include)

Modified: llvm/trunk/utils/unittest/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/CMakeLists.txt?rev=114747&r1=114746&r2=114747&view=diff
==============================================================================
--- llvm/trunk/utils/unittest/CMakeLists.txt (original)
+++ llvm/trunk/utils/unittest/CMakeLists.txt Fri Sep 24 14:10:51 2010
@@ -20,15 +20,17 @@
   add_definitions(-DGTEST_OS_WINDOWS=1)
 endif()
 
-add_llvm_library(gtest
-  googletest/gtest.cc
-  googletest/gtest-death-test.cc
-  googletest/gtest-filepath.cc
-  googletest/gtest-port.cc
-  googletest/gtest-test-part.cc
-  googletest/gtest-typed-test.cc
-  )
+if (LLVM_INCLUDE_TESTS OR LLVM_BUILD_TESTS)
+  add_llvm_library(gtest
+    googletest/gtest.cc
+    googletest/gtest-death-test.cc
+    googletest/gtest-filepath.cc
+    googletest/gtest-port.cc
+    googletest/gtest-test-part.cc
+    googletest/gtest-typed-test.cc
+    )
 
-add_llvm_library(gtest_main
-  UnitTestMain/TestMain.cpp
-  )
+  add_llvm_library(gtest_main
+    UnitTestMain/TestMain.cpp
+    )
+endif()



From tonic at nondot.org  Fri Sep 24 14:20:48 2010
From: tonic at nondot.org (Tanya Lattner)
Date: Fri, 24 Sep 2010 19:20:48 -0000
Subject: [llvm-commits] [www] r114748 - /www/trunk/devmtg/2010-11/index.html
Message-ID: <20100924192048.C4AC62A6C12C@llvm.org>

Author: tbrethou
Date: Fri Sep 24 14:20:48 2010
New Revision: 114748

URL: http://llvm.org/viewvc/llvm-project?rev=114748&view=rev
Log:
Fix typo.

Modified:
    www/trunk/devmtg/2010-11/index.html

Modified: www/trunk/devmtg/2010-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=114748&r1=114747&r2=114748&view=diff
==============================================================================
--- www/trunk/devmtg/2010-11/index.html (original)
+++ www/trunk/devmtg/2010-11/index.html Fri Sep 24 14:20:48 2010
@@ -51,7 +51,7 @@
 
 <div class="www_sectiontitle" id="funding">Funding for Active Contributors/Students</div>
 
-<p>There will be some funding for active contributors or students to attend the event. hose who are funded are required to present at the meeting and may have other requirements from their sponsor (ie. writing a blog post, etc).</p>
+<p>There will be some funding for active contributors or students to attend the event. Those who are funded are required to present at the meeting and may have other requirements from their sponsor (ie. writing a blog post, etc).</p>
 
 <p>If you need funding to attend the meeting, please submit your request to us by <b>September 29, 2010</b> via  the <a href="http://llvm.org/devmtg/students.php">website</a>.</p>
 



From bigcheesegs at gmail.com  Fri Sep 24 14:26:39 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Fri, 24 Sep 2010 15:26:39 -0400
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
In-Reply-To: <20100924191051.A24F42A6C12C@llvm.org>
References: <20100924191051.A24F42A6C12C@llvm.org>
Message-ID: <AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>

This was requested for the msvc build bot as building ALL_BUILD from
VSBuild doesn't build anything and we needed to disable building
unittests and examples.

I don't really like the implementation because it may be confusing to
the user because LLVM_INCLUDE_X is ignored if LLVM_BUILD_X is on. I
tried getting CMake to update the cache so ccmake and cmake-gui would
show the change, but it didn't work :(. I would appreciate any help in
making this implementation more robust.

- Michael Spencer



On Fri, Sep 24, 2010 at 3:10 PM, Michael J. Spencer
<bigcheesegs at gmail.com> wrote:
> Author: mspencer
> Date: Fri Sep 24 14:10:51 2010
> New Revision: 114747
>
> URL: http://llvm.org/viewvc/llvm-project?rev=114747&view=rev
> Log:
> CMake: Don't include tools, unittets, or examples as available targets
> unless LLVM_INCLUDE_X is ON. LLVM_BUILD_X implies LLVM_INCLUDE_X
>
> Modified:
> ? ?llvm/trunk/CMakeLists.txt
> ? ?llvm/trunk/cmake/modules/AddLLVM.cmake
> ? ?llvm/trunk/unittests/CMakeLists.txt
> ? ?llvm/trunk/utils/unittest/CMakeLists.txt
>
> Modified: llvm/trunk/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=114747&r1=114746&r2=114747&view=diff
> ==============================================================================
> --- llvm/trunk/CMakeLists.txt (original)
> +++ llvm/trunk/CMakeLists.txt Fri Sep 24 14:10:51 2010
> @@ -364,12 +364,18 @@
> ?add_subdirectory(projects)
>
> ?option(LLVM_BUILD_TOOLS "Build LLVM tool programs." ON)
> +option(LLVM_INCLUDE_TOOLS
> + ?"Include LLVM tool programs as an available target." ON)
> ?add_subdirectory(tools)
>
> ?option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF)
> +option(LLVM_INCLUDE_EXAMPLES
> + ?"Include LLVM example programs as an available target." OFF)
> ?add_subdirectory(examples)
>
> ?option(LLVM_BUILD_TESTS "Build LLVM unit tests." OFF)
> +option(LLVM_INCLUDE_TESTS
> + ?"Include LLVM unit tests as an available target." OFF)
> ?add_subdirectory(test)
> ?add_subdirectory(utils/unittest)
> ?add_subdirectory(unittests)
>
> Modified: llvm/trunk/cmake/modules/AddLLVM.cmake
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=114747&r1=114746&r2=114747&view=diff
> ==============================================================================
> --- llvm/trunk/cmake/modules/AddLLVM.cmake (original)
> +++ llvm/trunk/cmake/modules/AddLLVM.cmake Fri Sep 24 14:10:51 2010
> @@ -77,7 +77,9 @@
> ? if( NOT LLVM_BUILD_TOOLS )
> ? ? set(EXCLUDE_FROM_ALL ON)
> ? endif()
> - ?add_llvm_executable(${name} ${ARGN})
> + ?if( LLVM_INCLUDE_TOOLS OR LLVM_BUILD_TOOLS )
> + ? ?add_llvm_executable(${name} ${ARGN})
> + ?endif()
> ? if( LLVM_BUILD_TOOLS )
> ? ? install(TARGETS ${name} RUNTIME DESTINATION bin)
> ? endif()
> @@ -89,7 +91,9 @@
> ? if( NOT LLVM_BUILD_EXAMPLES )
> ? ? set(EXCLUDE_FROM_ALL ON)
> ? endif()
> - ?add_llvm_executable(${name} ${ARGN})
> + ?if( LLVM_INCLUDE_EXAMPLES OR LLVM_BUILD_EXAMPLES )
> + ? ?add_llvm_executable(${name} ${ARGN})
> + ?endif()
> ? if( LLVM_BUILD_EXAMPLES )
> ? ? install(TARGETS ${name} RUNTIME DESTINATION examples)
> ? endif()
>
> Modified: llvm/trunk/unittests/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=114747&r1=114746&r2=114747&view=diff
> ==============================================================================
> --- llvm/trunk/unittests/CMakeLists.txt (original)
> +++ llvm/trunk/unittests/CMakeLists.txt Fri Sep 24 14:10:51 2010
> @@ -9,7 +9,9 @@
> ? if( NOT LLVM_BUILD_TESTS )
> ? ? set(EXCLUDE_FROM_ALL ON)
> ? endif()
> - ?add_llvm_executable(${test_name}Tests ${ARGN})
> + ?if (LLVM_INCLUDE_TESTS OR LLVM_BUILD_TESTS)
> + ? ?add_llvm_executable(${test_name}Tests ${ARGN})
> + ?endif()
> ?endfunction()
>
> ?include_directories(${LLVM_MAIN_SRC_DIR}/utils/unittest/googletest/include)
>
> Modified: llvm/trunk/utils/unittest/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/CMakeLists.txt?rev=114747&r1=114746&r2=114747&view=diff
> ==============================================================================
> --- llvm/trunk/utils/unittest/CMakeLists.txt (original)
> +++ llvm/trunk/utils/unittest/CMakeLists.txt Fri Sep 24 14:10:51 2010
> @@ -20,15 +20,17 @@
> ? add_definitions(-DGTEST_OS_WINDOWS=1)
> ?endif()
>
> -add_llvm_library(gtest
> - ?googletest/gtest.cc
> - ?googletest/gtest-death-test.cc
> - ?googletest/gtest-filepath.cc
> - ?googletest/gtest-port.cc
> - ?googletest/gtest-test-part.cc
> - ?googletest/gtest-typed-test.cc
> - ?)
> +if (LLVM_INCLUDE_TESTS OR LLVM_BUILD_TESTS)
> + ?add_llvm_library(gtest
> + ? ?googletest/gtest.cc
> + ? ?googletest/gtest-death-test.cc
> + ? ?googletest/gtest-filepath.cc
> + ? ?googletest/gtest-port.cc
> + ? ?googletest/gtest-test-part.cc
> + ? ?googletest/gtest-typed-test.cc
> + ? ?)
>
> -add_llvm_library(gtest_main
> - ?UnitTestMain/TestMain.cpp
> - ?)
> + ?add_llvm_library(gtest_main
> + ? ?UnitTestMain/TestMain.cpp
> + ? ?)
> +endif()
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From bigcheesegs at gmail.com  Fri Sep 24 14:48:47 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Fri, 24 Sep 2010 19:48:47 -0000
Subject: [llvm-commits] [llvm] r114750 - in /llvm/trunk:
 lib/CodeGen/IntrinsicLowering.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/Transforms/Utils/LowerInvoke.cpp utils/TableGen/IntrinsicEmitter.cpp
Message-ID: <20100924194847.C23D02A6C12C@llvm.org>

Author: mspencer
Date: Fri Sep 24 14:48:47 2010
New Revision: 114750

URL: http://llvm.org/viewvc/llvm-project?rev=114750&view=rev
Log:
Get rid of pop_macro warnings on MSVC.

Modified:
    llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
    llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp

Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=114750&r1=114749&r2=114750&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Fri Sep 24 14:48:47 2010
@@ -85,9 +85,11 @@
 }
 
 // VisualStudio defines setjmp as _setjmp
-#if defined(_MSC_VER) && defined(setjmp)
-#define setjmp_undefined_for_visual_studio
-#undef setjmp
+#if defined(_MSC_VER) && defined(setjmp) && \
+                         !defined(setjmp_undefined_for_msvc)
+#  pragma push_macro("setjmp")
+#  undef setjmp
+#  define setjmp_undefined_for_msvc
 #endif
 
 void IntrinsicLowering::AddPrototypes(Module &M) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114750&r1=114749&r2=114750&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Sep 24 14:48:47 2010
@@ -3970,9 +3970,11 @@
 }
 
 // VisualStudio defines setjmp as _setjmp
-#if defined(_MSC_VER) && defined(setjmp)
-#define setjmp_undefined_for_visual_studio
-#undef setjmp
+#if defined(_MSC_VER) && defined(setjmp) && \
+                         !defined(setjmp_undefined_for_msvc)
+#  pragma push_macro("setjmp")
+#  undef setjmp
+#  define setjmp_undefined_for_msvc
 #endif
 
 /// visitIntrinsicCall - Lower the call to the specified intrinsic function.  If

Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=114750&r1=114749&r2=114750&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Fri Sep 24 14:48:47 2010
@@ -148,19 +148,20 @@
                                       "llvm.sjljeh.jblist");
     }
 
-// VisualStudio defines setjmp as _setjmp via #include <csetjmp> / <setjmp.h>,
-// so it looks like Intrinsic::_setjmp
-#if defined(_MSC_VER) && defined(setjmp)
-#define setjmp_undefined_for_visual_studio
-#undef setjmp
+// VisualStudio defines setjmp as _setjmp
+#if defined(_MSC_VER) && defined(setjmp) && \
+                         !defined(setjmp_undefined_for_msvc)
+#  pragma push_macro("setjmp")
+#  undef setjmp
+#  define setjmp_undefined_for_msvc
 #endif
 
     SetJmpFn = Intrinsic::getDeclaration(&M, Intrinsic::setjmp);
 
-#if defined(_MSC_VER) && defined(setjmp_undefined_for_visual_studio)
-// let's return it to _setjmp state in case anyone ever needs it after this
-// point under VisualStudio
-#define setjmp _setjmp
+#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)
+   // let's return it to _setjmp state
+#  pragma pop_macro("setjmp")
+#  undef setjmp_undefined_for_msvc
 #endif
 
     LongJmpFn = Intrinsic::getDeclaration(&M, Intrinsic::longjmp);

Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=114750&r1=114749&r2=114750&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Fri Sep 24 14:48:47 2010
@@ -68,16 +68,19 @@
 
 void IntrinsicEmitter::EmitPrefix(raw_ostream &OS) {
   OS << "// VisualStudio defines setjmp as _setjmp\n"
-        "#if defined(_MSC_VER) && defined(setjmp)\n"
+        "#if defined(_MSC_VER) && defined(setjmp) && \\\n"
+        "                         !defined(setjmp_undefined_for_msvc)\n"
         "#  pragma push_macro(\"setjmp\")\n"
         "#  undef setjmp\n"
+        "#  define setjmp_undefined_for_msvc\n"
         "#endif\n\n";
 }
 
 void IntrinsicEmitter::EmitSuffix(raw_ostream &OS) {
-  OS << "#if defined(_MSC_VER)\n"
+  OS << "#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)\n"
         "// let's return it to _setjmp state\n"
         "#  pragma pop_macro(\"setjmp\")\n"
+        "#  undef setjmp_undefined_for_msvc\n"
         "#endif\n\n";
 }
 



From daniel at zuster.org  Fri Sep 24 14:57:34 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 19:57:34 -0000
Subject: [llvm-commits] [zorg] r114751 -
	/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
Message-ID: <20100924195734.54AD82A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 14:57:34 2010
New Revision: 114751

URL: http://llvm.org/viewvc/llvm-project?rev=114751&view=rev
Log:
buildbot: Don't build examples or unittests during MSVC build.

Modified:
    zorg/trunk/zorg/buildbot/builders/ClangBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=114751&r1=114750&r2=114751&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Fri Sep 24 14:57:34 2010
@@ -286,6 +286,9 @@
     f.addStep(BatchFileDownload(name='cmakegen',
                                 command=[cmake,
                                          "-DLLVM_TARGETS_TO_BUILD:=X86",
+                                         "-DLLVM_INCLUDE_EXAMPLES:=OFF",
+                                         "-DLLVM_INCLUDE_TESTS:=OFF",
+                                         "-DLLVM_TARGETS_TO_BUILD:=X86",
                                          "-G",
                                          "Visual Studio 9 2008",
                                          ".."],



From ofv at wanadoo.es  Fri Sep 24 15:01:25 2010
From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=)
Date: Fri, 24 Sep 2010 22:01:25 +0200
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
	cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
	utils/unittest/CMakeLists.txt
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
Message-ID: <87sk0ykj1m.fsf@telefonica.net>

Michael Spencer <bigcheesegs at gmail.com>
writes:

> This was requested for the msvc build bot as building ALL_BUILD from
> VSBuild doesn't build anything and we needed to disable building
> unittests and examples.

I don't understand this. So if the cmake invocation contains
-DLLVM_BUILD_EXAMPLES=OFF this is a problem?

And why you don't want to build examples and unittests on the bot, if
precisely the purpose of the bot is to test the build? (*all* the build,
I guess)

> I don't really like the implementation because it may be confusing to
> the user because LLVM_INCLUDE_X is ignored if LLVM_BUILD_X is on. I
> tried getting CMake to update the cache so ccmake and cmake-gui would
> show the change, but it didn't work :(. I would appreciate any help in
> making this implementation more robust.

I don't like the patch either. The previous implementation supported
ignoring the tools and examples on the default build but allowing
building them later as the user demanded. Now if the user wants to build
a tool or example, he must reconfigure and incorporate *all* the tools
examples to the default build.

Please explain in more detail what the problem is and maybe we can find
a better implementation. The current one removes a convenience from the
user and is unnecessarily complex (why not

if( LLVM_INCLUDE_X )
  add_subdirectory(X)
endif()

instead of changing add_llvm_X)

In any case, removing an option (LLVM_BUILD_TOOLS) and introducing a new
one (LLVM_INCLUDE_TOOLS) requires updating docs/CMake.html.

Oh, and next time it would be a good idea to discuss the patch before
committing it.


From dirty at apple.com  Fri Sep 24 15:13:36 2010
From: dirty at apple.com (Cameron Esfahani)
Date: Fri, 24 Sep 2010 13:13:36 -0700
Subject: [llvm-commits] [PATCH] Updated versions of previous patches
Message-ID: <E34E4552-5349-49E7-9ACD-CE1598F60682@apple.com>

It's been a few weeks, and my previous patches have gotten a little stale compared to TOT.

There is a slight conflict, as two of these patches both modify X86RegisterInfo.cpp, so it might be difficult to apply them both separately.

Enclosed are three separate patches:

- Add support for the Windows 64 version of __chkstk

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- Add support for the Windows 64 versions of the tail call pseudo opcodes

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- Add support for Windows 64 var args

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Cameron Esfahani
dirty at apple.com

"We do what we must because we can."

Aperture Science




From daniel at zuster.org  Fri Sep 24 15:19:28 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 20:19:28 -0000
Subject: [llvm-commits] [zorg] r114753 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20100924201928.5521F2A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 15:19:28 2010
New Revision: 114753

URL: http://llvm.org/viewvc/llvm-project?rev=114753&view=rev
Log:
buildbot: Move llvm-x86_64-linux to gcc14 slave. Thanks Duncan\!

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=114753&r1=114752&r2=114753&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Sep 24 15:19:28 2010
@@ -32,10 +32,10 @@
          'slavenames': ["dunbar1"],
          'builddir': "llvm-i686", 
          'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", jobs=2, enable_shared=True)},
-#        {'name': "llvm-x86_64-linux",
-#         'slavenames': ["osu1"],
-#         'builddir': "llvm-x86_64",
-#         'factory': LLVMBuilder.getLLVMBuildFactory(triple="x86_64-pc-linux-gnu")},
+        {'name': "llvm-x86_64-linux",
+         'slavenames': ["gcc14"],
+         'builddir': "llvm-x86_64",
+         'factory': LLVMBuilder.getLLVMBuildFactory(triple="x86_64-pc-linux-gnu")},
         {'name': "llvm-arm-linux",
          'slavenames':["ranby1"],
          'builddir':"llvm-arm-linux",
@@ -127,7 +127,7 @@
 def _get_clang_builders():
     return [
 #        {'name': "clang-x86_64-linux",
-#         'slavenames':["osu1"],
+#         'slavenames':["gcc14"],
 #         'builddir':"clang-x86_64-linux",
 #         'factory': ClangBuilder.getClangBuildFactory(examples=True)},
         {'name': "clang-i686-linux",



From stoklund at 2pi.dk  Fri Sep 24 15:24:01 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 20:24:01 -0000
Subject: [llvm-commits] [test-suite] r114754 -
	/test-suite/trunk/SingleSource/UnitTests/ObjC/Makefile
Message-ID: <20100924202401.715D32A6C12C@llvm.org>

Author: stoklund
Date: Fri Sep 24 15:24:01 2010
New Revision: 114754

URL: http://llvm.org/viewvc/llvm-project?rev=114754&view=rev
Log:
XFAIL a known llvm-gcc miscompilation.

Modified:
    test-suite/trunk/SingleSource/UnitTests/ObjC/Makefile

Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/Makefile?rev=114754&r1=114753&r2=114754&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/ObjC/Makefile (original)
+++ test-suite/trunk/SingleSource/UnitTests/ObjC/Makefile Fri Sep 24 15:24:01 2010
@@ -15,4 +15,9 @@
 PROGRAMS_TO_SKIP += print-class-info-x86-64
 endif
 
+# This is a known gcc / llvm-gcc miscompilation fixed in clang.
+ifdef CC_UNDER_TEST_IS_LLVM_GCC
+EXEC_XFAILS = dot-syntax-2
+endif
+
 include $(LEVEL)/SingleSource/Makefile.singlesrc



From stoklund at 2pi.dk  Fri Sep 24 15:34:49 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 20:34:49 -0000
Subject: [llvm-commits] [llvm] r114755 -
	/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
Message-ID: <20100924203449.A4C322A6C12C@llvm.org>

Author: stoklund
Date: Fri Sep 24 15:34:49 2010
New Revision: 114755

URL: http://llvm.org/viewvc/llvm-project?rev=114755&view=rev
Log:
Be more precise when trying to XFAIL this tester: http://google1.osuosl.org:8011/builders/llvm-arm-linux

Modified:
    llvm/trunk/test/Transforms/InstCombine/fold-calls.ll

Modified: llvm/trunk/test/Transforms/InstCombine/fold-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/fold-calls.ll?rev=114755&r1=114754&r2=114755&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/fold-calls.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/fold-calls.ll Fri Sep 24 15:34:49 2010
@@ -1,8 +1,9 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
-; This test is inexplicably still failing, which suggests a
-; bug in the host libm.
-; XFAIL: arm-linux
+; This test is inexplicably still failing, which suggests a bug in the host
+; libm. It appears that sin(inf) returns NaN without setting a floating point
+; exception.
+; XFAIL: arm-pc-linux-gnu
 
 ; This shouldn't fold, because sin(inf) is invalid.
 ; CHECK: @foo



From stoklund at 2pi.dk  Fri Sep 24 15:47:02 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 20:47:02 -0000
Subject: [llvm-commits] [test-suite] r114757 -
	/test-suite/trunk/SingleSource/UnitTests/Makefile
Message-ID: <20100924204702.76CE12A6C12C@llvm.org>

Author: stoklund
Date: Fri Sep 24 15:47:02 2010
New Revision: 114757

URL: http://llvm.org/viewvc/llvm-project?rev=114757&view=rev
Log:
Run ObjC and ObjC++ unit tests on all Darwin platforms.

Modified:
    test-suite/trunk/SingleSource/UnitTests/Makefile

Modified: test-suite/trunk/SingleSource/UnitTests/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Makefile?rev=114757&r1=114756&r2=114757&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Makefile (original)
+++ test-suite/trunk/SingleSource/UnitTests/Makefile Fri Sep 24 15:47:02 2010
@@ -11,15 +11,10 @@
 
 DIRS += SignlessTypes Threads
 
-# Only test Obj-C on darwin/x86 for time being.
+# Only test Obj-C on Darwin.
 ifeq ($(TARGET_OS),Darwin)
-ifeq ($(ARCH),x86)
 DIRS += ObjC ObjC++
 endif
-ifeq ($(ARCH),x86_64)
-DIRS += ObjC ObjC++
-endif
-endif
 
 # Darwin doesn't support weak/weak_import in a way that we can test in this
 # framework.



From grosbach at apple.com  Fri Sep 24 15:47:59 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Sep 2010 20:47:59 -0000
Subject: [llvm-commits] [llvm] r114758 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20100924204759.0F22B2A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep 24 15:47:58 2010
New Revision: 114758

URL: http://llvm.org/viewvc/llvm-project?rev=114758&view=rev
Log:
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114758&r1=114757&r2=114758&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep 24 15:47:58 2010
@@ -236,6 +236,8 @@
                                           const MachineBasicBlock *MBB) const;
     MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
 
+    MCSymbol *GetARMSJLJEHLabel(void) const;
+
     /// EmitMachineConstantPoolValue - Print a machine constantpool value to
     /// the .s file.
     virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
@@ -953,6 +955,14 @@
   return OutContext.GetOrCreateSymbol(Name.str());
 }
 
+
+MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
+  SmallString<60> Name;
+  raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
+    << getFunctionNumber();
+  return OutContext.GetOrCreateSymbol(Name.str());
+}
+
 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
                                         raw_ostream &O) {
   assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
@@ -1748,6 +1758,91 @@
     }
     break;
   }
+  case ARM::t2Int_eh_sjlj_setjmp:
+  case ARM::t2Int_eh_sjlj_setjmp_nofp:
+  case ARM::tInt_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
+    // Two incoming args: GPR:$src, GPR:$val
+    // mov $val, pc
+    // adds $val, #7
+    // str $val, [$src, #4]
+    // movs r0, #0
+    // b 1f
+    // movs r0, #1
+    // 1:
+    unsigned SrcReg = MI->getOperand(0).getReg();
+    unsigned ValReg = MI->getOperand(1).getReg();
+    MCSymbol *Label = GetARMSJLJEHLabel();
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
+      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
+      // 's' bit operand
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+      OutStreamer.AddComment("eh_setjmp begin");
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tADDi3);
+      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
+      // 's' bit operand
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
+      TmpInst.addOperand(MCOperand::CreateImm(7));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tSTR);
+      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
+      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
+      // The offset immediate is #4. The operand value is scaled by 4 for the
+      // tSTR instruction.
+      TmpInst.addOperand(MCOperand::CreateImm(1));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tMOVi8);
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+      TmpInst.addOperand(MCOperand::CreateImm(0));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tB);
+      TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tMOVi8);
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
+      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+      TmpInst.addOperand(MCOperand::CreateImm(1));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
+      OutStreamer.AddComment("eh_setjmp end");
+      OutStreamer.EmitInstruction(TmpInst);
+    }
+    OutStreamer.EmitLabel(Label);
+    return;
+  }
+
   case ARM::Int_eh_sjlj_setjmp_nofp:
   case ARM::Int_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
     // Two incoming args: GPR:$src, GPR:$val



From evan.cheng at apple.com  Fri Sep 24 16:05:27 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 14:05:27 -0700
Subject: [llvm-commits] [llvm] r114681	-
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <6426039E-DD38-44D5-B30B-84A7EE32AF20@apple.com>
References: <20100923183219.35D1D2A6C12C@llvm.org> <4C9C52D8.3090708@free.fr>
	<707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>
	<37BE4EFC-83BD-4696-8472-F85A74D6F3AF@2pi.dk>
	<6426039E-DD38-44D5-B30B-84A7EE32AF20@apple.com>
Message-ID: <89F1B266-141E-4020-8C72-805D33D492E3@apple.com>


On Sep 24, 2010, at 12:07 PM, Evan Cheng wrote:

> 
> On Sep 24, 2010, at 11:49 AM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Sep 24, 2010, at 10:48 AM, Evan Cheng wrote:
>> 
>>> There is definitely a codegen bug downstream. A unconditional branch to a fallthrough block is correct the last time I checked. If someone has some time to look into this, I would appreciate a test case.
>> 
>> It looks like MachineBasicBlock::canFallThrough affects codegen which could trigger this bug, and MachineBasicBlock::updateTerminator looks like it is going to undo it anyway by removing the unconditional branch.
>> 
>> Is any code assuming the presence of an unconditional branch?
> 
> I sure hope not. The reason for this change some DAG transformations require the presence of the unconditional branch following a conditional one so it can flip them. With this case, a lot of fcmp_oeq can be optimized to a pair of conditional branches, rather than two setcc and an and.
> 
> I've verified machine instruction passes will eliminate the branch to fallthrough. I wonder if we could disable branch folding and see if more miscompilations show up.

Tried it. No miscompilations on Darwin.

Evan

> 
> Evan
> 
>> 
>> /jakob
>> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From wdietz2 at illinois.edu  Fri Sep 24 16:08:54 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Fri, 24 Sep 2010 21:08:54 -0000
Subject: [llvm-commits] [poolalloc] r114759 - in /poolalloc/trunk/test/dsa:
 extern/ extern/dg.exp extern/extern.ll extern/extern2.ll extern/extern3.ll
 extern/extern_global.ll td/extern.ll td/extern2.ll td/extern3.ll
 td/extern_global.ll
Message-ID: <20100924210854.C44DB2A6C12C@llvm.org>

Author: wdietz2
Date: Fri Sep 24 16:08:54 2010
New Revision: 114759

URL: http://llvm.org/viewvc/llvm-project?rev=114759&view=rev
Log:
Add 'extern' testing directory, move tests over.
No functionality changes.

Added:
    poolalloc/trunk/test/dsa/extern/
    poolalloc/trunk/test/dsa/extern/dg.exp
    poolalloc/trunk/test/dsa/extern/extern.ll
    poolalloc/trunk/test/dsa/extern/extern2.ll
    poolalloc/trunk/test/dsa/extern/extern3.ll
    poolalloc/trunk/test/dsa/extern/extern_global.ll
Removed:
    poolalloc/trunk/test/dsa/td/extern.ll
    poolalloc/trunk/test/dsa/td/extern2.ll
    poolalloc/trunk/test/dsa/td/extern3.ll
    poolalloc/trunk/test/dsa/td/extern_global.ll

Added: poolalloc/trunk/test/dsa/extern/dg.exp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/dg.exp?rev=114759&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/extern/dg.exp (added)
+++ poolalloc/trunk/test/dsa/extern/dg.exp Fri Sep 24 16:08:54 2010
@@ -0,0 +1,3 @@
+load_lib llvm.exp
+
+RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,cpp}]]

Added: poolalloc/trunk/test/dsa/extern/extern.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern.ll?rev=114759&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/extern/extern.ll (added)
+++ poolalloc/trunk/test/dsa/extern/extern.ll Fri Sep 24 16:08:54 2010
@@ -0,0 +1,63 @@
+;Test that pointers from external functions are marked incomplete properly
+;Tests on all the DSA passes for three simple cases:
+;--calling an allocator wrapper (shouldn't be incomplete in interprocedural)
+;--calling a undefined (external) function.  Should be incomplete at least
+;  once the interprocedural passes run.
+;--calling a function that calls an undefined (external) function.
+;  Should be incomplete, tests very basic tracking.
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I-E"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrViaExtern+IE"
+
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrExtern+IE"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr-IE"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrViaExtern+IE"
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32* @getPointerViaExtern() nounwind {
+entry:
+  %0 = tail call i32* (...)* @getPointerExtern() nounwind ; <i32*> [#uses=1]
+  ret i32* %0
+}
+
+declare i32* @getPointerExtern(...)
+
+define internal noalias i32* @getPointer() nounwind {
+entry:
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
+  %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  ret i32* %1
+}
+
+declare noalias i8* @malloc(i64) nounwind
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+  %ptr = tail call i32* ()* @getPointer() nounwind
+  %ptrExtern = tail call i32* (...)* @getPointerExtern() nounwind
+  %ptrViaExtern = tail call i32* ()* @getPointerViaExtern() nounwind
+  %val1 = load i32* %ptr, align 4
+  %val2 = load i32* %ptrExtern, align 4
+  %val3 = load i32* %ptrViaExtern, align 4
+  %sum_partial = add i32 %val1, %val2
+  %sum = add i32 %sum_partial, %val3
+  ret i32 %sum
+}

Added: poolalloc/trunk/test/dsa/extern/extern2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern2.ll?rev=114759&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/extern/extern2.ll (added)
+++ poolalloc/trunk/test/dsa/extern/extern2.ll Fri Sep 24 16:08:54 2010
@@ -0,0 +1,38 @@
+;Here we get a pointer from an external function and pass it to a callee.
+;We then test that the flags on that pointer are set appropriately.
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-local -analyze -verify-flags "takesPointer:ptr+IE"
+
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "takesPointer:ptr+IE"
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+IE"
+
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "takesPointer:ptr+IE"
+
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "takesPointer:ptr+IE"
+
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr+IE"
+;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "takesPointer:ptr+IE"
+
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @takesPointer(i32* nocapture %ptr) nounwind readonly {
+entry:
+  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
+  ret i32 %0
+}
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+  %ptr = tail call i32* (...)* @getPointerExtern() nounwind
+  %0 = tail call i32 @takesPointer(i32* %ptr) nounwind
+  ret i32 %0
+}
+
+declare i32* @getPointerExtern(...)

Added: poolalloc/trunk/test/dsa/extern/extern3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern3.ll?rev=114759&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/extern/extern3.ll (added)
+++ poolalloc/trunk/test/dsa/extern/extern3.ll Fri Sep 24 16:08:54 2010
@@ -0,0 +1,88 @@
+; ModuleID = 'extern.c'
+;This tests the various cases that could involve incompleteness due
+;to external code, and additionally verifies these flags are NOT set
+;on internal functions.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare i32* @getPointerExtern()
+declare void @takesPointerExtern(i32*)
+declare noalias i8* @malloc(i64) nounwind
+declare void @free(i8*) nounwind
+
+;This should be marked incomplete and external due to the
+;unification-based nature of DSA.
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointer:ptr+IE"
+define i32* @getPointer() nounwind {
+entry:
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
+  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  ret i32* %ptr
+}
+
+;This should be marked incomplete and external due to the
+;unification-based nature of DSA.
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+IE"
+define i32 @takesPointer(i32* %ptr) nounwind {
+entry:
+  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
+  ret i32 %0
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointerInternal:ptr-IE"
+define internal i32* @getPointerInternal() nounwind {
+entry:
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
+  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  ret i32* %ptr
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointerInternal:ptr-IE"
+define internal i32 @takesPointerInternal(i32* %ptr) nounwind {
+entry:
+  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
+  ret i32 %0
+}
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+  call void @checkExterns() nounwind
+  call void @checkExternals() nounwind
+  call void @checkInternals() nounwind
+  ret i32 0
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:get+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:take+IE"
+define void @checkExterns() nounwind {
+  %get = tail call i32* ()* @getPointerExtern() nounwind ; <i32*> [#uses=0]
+  %1 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
+  %take = bitcast i8* %1 to i32*                     ; <i32*> [#uses=1]
+  tail call void @takesPointerExtern(i32* %take) nounwind
+  tail call void @free(i8* %1) nounwind
+  ret void
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get+IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take+IE"
+define void @checkExternals() nounwind {
+entry:
+  %get = tail call i32* ()* @getPointer() nounwind ; <i32*> [#uses=0]
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
+  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  tail call i32 @takesPointer(i32* %take) nounwind
+  tail call void @free(i8* %0) nounwind
+  ret void
+}
+
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:get-IE"
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:take-IE"
+define void @checkInternals() nounwind {
+entry:
+  %get = tail call i32* ()* @getPointerInternal() nounwind ; <i32*> [#uses=0]
+  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
+  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  tail call i32 @takesPointerInternal(i32* %take) nounwind
+  tail call void @free(i8* %0) nounwind
+  ret void
+}

Added: poolalloc/trunk/test/dsa/extern/extern_global.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern_global.ll?rev=114759&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/extern/extern_global.ll (added)
+++ poolalloc/trunk/test/dsa/extern/extern_global.ll Fri Sep 24 16:08:54 2010
@@ -0,0 +1,49 @@
+; ModuleID = 'extern_global.c'
+;This tests how DSA handles external globals and their completeness in TD.
+
+; Externally visible globals should be incomplete
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalInt+GIE
+; Externally visible global and what it points to should be incomplete
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr+GIE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr:0+GIE
+; Externally visible global and what it points to should be incomplete,
+; this time with a struct and point to some stack memory...
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers+GIE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8+IE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8:8+IE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags main:s+IES
+; Globals that aren't marked 'external' shouldn't be incomplete (or external)
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal+G-IE
+;RUN: dsaopt %s -dsa-td -analyze -verify-flags internalGlobal+G-IE
+; Check some edges of the graph
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=normalGlobal:0,globalIntPtr
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=internalGlobal:0,normalGlobal
+;RUN: dsaopt %s -dsa-td -analyze -check-same-node=globalStructWithPointers:8,globalStructWithPointers:8:8
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.myStruct = type { i32, %struct.myStruct* }
+
+ at globalStructWithPointers = external global %struct.myStruct
+ at globalIntPtr = external global i32*
+ at globalInt = external global i32
+ at normalGlobal = global i32** null
+ at internalGlobal = internal global i32*** null
+
+define i32 @main() nounwind {
+entry:
+;Create the struct and initialize it
+  %s = alloca %struct.myStruct, align 8           ; <%struct.myStruct*> [#uses=1]
+  %0 = getelementptr inbounds %struct.myStruct* %s, i32 0, i32 1 ; <%struct.myStruct**> [#uses=1]
+  store %struct.myStruct* %s, %struct.myStruct** %0, align 8
+  %1 = getelementptr inbounds %struct.myStruct* %s, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32 100, i32* %1, align 8
+;Store the struct into the global
+  store %struct.myStruct* %s, %struct.myStruct** getelementptr inbounds (%struct.myStruct* @globalStructWithPointers, i64 0, i32 1), align 8
+;Play around with the rest of the globals
+  store i32* @globalInt, i32** @globalIntPtr, align 8
+  store i32** @globalIntPtr, i32*** @normalGlobal, align 8
+  store i32*** @normalGlobal, i32**** @internalGlobal, align 8
+  ret i32 undef
+}

Removed: poolalloc/trunk/test/dsa/td/extern.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern.ll?rev=114758&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern.ll (removed)
@@ -1,63 +0,0 @@
-;Test that pointers from external functions are marked incomplete properly
-;Tests on all the DSA passes for three simple cases:
-;--calling an allocator wrapper (shouldn't be incomplete in interprocedural)
-;--calling a undefined (external) function.  Should be incomplete at least
-;  once the interprocedural passes run.
-;--calling a function that calls an undefined (external) function.
-;  Should be incomplete, tests very basic tracking.
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrExtern+IE"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+I-E"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptrViaExtern+IE"
-
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrExtern+IE"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr-IE"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptrViaExtern+IE"
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrExtern+IE"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr-IE"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptrViaExtern+IE"
-
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrExtern+IE"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr-IE"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptrViaExtern+IE"
-
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrExtern+IE"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr-IE"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptrViaExtern+IE"
-
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrExtern+IE"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr-IE"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptrViaExtern+IE"
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-define i32* @getPointerViaExtern() nounwind {
-entry:
-  %0 = tail call i32* (...)* @getPointerExtern() nounwind ; <i32*> [#uses=1]
-  ret i32* %0
-}
-
-declare i32* @getPointerExtern(...)
-
-define internal noalias i32* @getPointer() nounwind {
-entry:
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
-  %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  ret i32* %1
-}
-
-declare noalias i8* @malloc(i64) nounwind
-
-define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-entry:
-  %ptr = tail call i32* ()* @getPointer() nounwind
-  %ptrExtern = tail call i32* (...)* @getPointerExtern() nounwind
-  %ptrViaExtern = tail call i32* ()* @getPointerViaExtern() nounwind
-  %val1 = load i32* %ptr, align 4
-  %val2 = load i32* %ptrExtern, align 4
-  %val3 = load i32* %ptrViaExtern, align 4
-  %sum_partial = add i32 %val1, %val2
-  %sum = add i32 %sum_partial, %val3
-  ret i32 %sum
-}

Removed: poolalloc/trunk/test/dsa/td/extern2.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern2.ll?rev=114758&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern2.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern2.ll (removed)
@@ -1,38 +0,0 @@
-;Here we get a pointer from an external function and pass it to a callee.
-;We then test that the flags on that pointer are set appropriately.
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr+IE"
-;RUN: dsaopt %s -dsa-local -analyze -verify-flags "takesPointer:ptr+IE"
-
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:ptr+IE"
-;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "takesPointer:ptr+IE"
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:ptr+IE"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+IE"
-
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "main:ptr+IE"
-;RUN: dsaopt %s -dsa-cbu -analyze -verify-flags "takesPointer:ptr+IE"
-
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "main:ptr+IE"
-;RUN: dsaopt %s -dsa-eq -analyze -verify-flags "takesPointer:ptr+IE"
-
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "main:ptr+IE"
-;RUN: dsaopt %s -dsa-eqtd -analyze -verify-flags "takesPointer:ptr+IE"
-
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-define i32 @takesPointer(i32* nocapture %ptr) nounwind readonly {
-entry:
-  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
-  ret i32 %0
-}
-
-define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-entry:
-  %ptr = tail call i32* (...)* @getPointerExtern() nounwind
-  %0 = tail call i32 @takesPointer(i32* %ptr) nounwind
-  ret i32 %0
-}
-
-declare i32* @getPointerExtern(...)

Removed: poolalloc/trunk/test/dsa/td/extern3.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern3.ll?rev=114758&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern3.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern3.ll (removed)
@@ -1,88 +0,0 @@
-; ModuleID = 'extern.c'
-;This tests the various cases that could involve incompleteness due
-;to external code, and additionally verifies these flags are NOT set
-;on internal functions.
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-declare i32* @getPointerExtern()
-declare void @takesPointerExtern(i32*)
-declare noalias i8* @malloc(i64) nounwind
-declare void @free(i8*) nounwind
-
-;This should be marked incomplete and external due to the
-;unification-based nature of DSA.
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointer:ptr+IE"
-define i32* @getPointer() nounwind {
-entry:
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
-  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  ret i32* %ptr
-}
-
-;This should be marked incomplete and external due to the
-;unification-based nature of DSA.
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointer:ptr+IE"
-define i32 @takesPointer(i32* %ptr) nounwind {
-entry:
-  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
-  ret i32 %0
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "getPointerInternal:ptr-IE"
-define internal i32* @getPointerInternal() nounwind {
-entry:
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=1]
-  %ptr = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  ret i32* %ptr
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "takesPointerInternal:ptr-IE"
-define internal i32 @takesPointerInternal(i32* %ptr) nounwind {
-entry:
-  %0 = load i32* %ptr, align 4                    ; <i32> [#uses=1]
-  ret i32 %0
-}
-
-define i32 @main(i32 %argc, i8** %argv) nounwind {
-entry:
-  call void @checkExterns() nounwind
-  call void @checkExternals() nounwind
-  call void @checkInternals() nounwind
-  ret i32 0
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:get+IE"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExterns:take+IE"
-define void @checkExterns() nounwind {
-  %get = tail call i32* ()* @getPointerExtern() nounwind ; <i32*> [#uses=0]
-  %1 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
-  %take = bitcast i8* %1 to i32*                     ; <i32*> [#uses=1]
-  tail call void @takesPointerExtern(i32* %take) nounwind
-  tail call void @free(i8* %1) nounwind
-  ret void
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:get+IE"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkExternals:take+IE"
-define void @checkExternals() nounwind {
-entry:
-  %get = tail call i32* ()* @getPointer() nounwind ; <i32*> [#uses=0]
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
-  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  tail call i32 @takesPointer(i32* %take) nounwind
-  tail call void @free(i8* %0) nounwind
-  ret void
-}
-
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:get-IE"
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags "checkInternals:take-IE"
-define void @checkInternals() nounwind {
-entry:
-  %get = tail call i32* ()* @getPointerInternal() nounwind ; <i32*> [#uses=0]
-  %0 = tail call noalias i8* @malloc(i64 4) nounwind ; <i8*> [#uses=2]
-  %take = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
-  tail call i32 @takesPointerInternal(i32* %take) nounwind
-  tail call void @free(i8* %0) nounwind
-  ret void
-}

Removed: poolalloc/trunk/test/dsa/td/extern_global.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/extern_global.ll?rev=114758&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/td/extern_global.ll (original)
+++ poolalloc/trunk/test/dsa/td/extern_global.ll (removed)
@@ -1,49 +0,0 @@
-; ModuleID = 'extern_global.c'
-;This tests how DSA handles external globals and their completeness in TD.
-
-; Externally visible globals should be incomplete
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalInt+GIE
-; Externally visible global and what it points to should be incomplete
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr+GIE
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr:0+GIE
-; Externally visible global and what it points to should be incomplete,
-; this time with a struct and point to some stack memory...
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers+GIE
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8+IE
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8:8+IE
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags main:s+IES
-; Globals that aren't marked 'external' shouldn't be incomplete (or external)
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal+G-IE
-;RUN: dsaopt %s -dsa-td -analyze -verify-flags internalGlobal+G-IE
-; Check some edges of the graph
-;RUN: dsaopt %s -dsa-td -analyze -check-same-node=normalGlobal:0,globalIntPtr
-;RUN: dsaopt %s -dsa-td -analyze -check-same-node=internalGlobal:0,normalGlobal
-;RUN: dsaopt %s -dsa-td -analyze -check-same-node=globalStructWithPointers:8,globalStructWithPointers:8:8
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-unknown-linux-gnu"
-
-%struct.myStruct = type { i32, %struct.myStruct* }
-
- at globalStructWithPointers = external global %struct.myStruct
- at globalIntPtr = external global i32*
- at globalInt = external global i32
- at normalGlobal = global i32** null
- at internalGlobal = internal global i32*** null
-
-define i32 @main() nounwind {
-entry:
-;Create the struct and initialize it
-  %s = alloca %struct.myStruct, align 8           ; <%struct.myStruct*> [#uses=1]
-  %0 = getelementptr inbounds %struct.myStruct* %s, i32 0, i32 1 ; <%struct.myStruct**> [#uses=1]
-  store %struct.myStruct* %s, %struct.myStruct** %0, align 8
-  %1 = getelementptr inbounds %struct.myStruct* %s, i32 0, i32 0 ; <i32*> [#uses=1]
-  store i32 100, i32* %1, align 8
-;Store the struct into the global
-  store %struct.myStruct* %s, %struct.myStruct** getelementptr inbounds (%struct.myStruct* @globalStructWithPointers, i64 0, i32 1), align 8
-;Play around with the rest of the globals
-  store i32* @globalInt, i32** @globalIntPtr, align 8
-  store i32** @globalIntPtr, i32*** @normalGlobal, align 8
-  store i32*** @normalGlobal, i32**** @internalGlobal, align 8
-  ret i32 undef
-}



From stoklund at 2pi.dk  Fri Sep 24 16:15:42 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 14:15:42 -0700
Subject: [llvm-commits] [llvm] r114681	-
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <89F1B266-141E-4020-8C72-805D33D492E3@apple.com>
References: <20100923183219.35D1D2A6C12C@llvm.org> <4C9C52D8.3090708@free.fr>
	<707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>
	<37BE4EFC-83BD-4696-8472-F85A74D6F3AF@2pi.dk>
	<6426039E-DD38-44D5-B30B-84A7EE32AF20@apple.com>
	<89F1B266-141E-4020-8C72-805D33D492E3@apple.com>
Message-ID: <83C5B0CC-37B5-4800-9663-14380E7EB91B@2pi.dk>


On Sep 24, 2010, at 2:05 PM, Evan Cheng wrote:

> 
> On Sep 24, 2010, at 12:07 PM, Evan Cheng wrote:
> 
>> 
>> On Sep 24, 2010, at 11:49 AM, Jakob Stoklund Olesen wrote:
>> 
>>> 
>>> On Sep 24, 2010, at 10:48 AM, Evan Cheng wrote:
>>> 
>>>> There is definitely a codegen bug downstream. A unconditional branch to a fallthrough block is correct the last time I checked. If someone has some time to look into this, I would appreciate a test case.
>>> 
>>> It looks like MachineBasicBlock::canFallThrough affects codegen which could trigger this bug, and MachineBasicBlock::updateTerminator looks like it is going to undo it anyway by removing the unconditional branch.
>>> 
>>> Is any code assuming the presence of an unconditional branch?
>> 
>> I sure hope not. The reason for this change some DAG transformations require the presence of the unconditional branch following a conditional one so it can flip them. With this case, a lot of fcmp_oeq can be optimized to a pair of conditional branches, rather than two setcc and an and.
>> 
>> I've verified machine instruction passes will eliminate the branch to fallthrough. I wonder if we could disable branch folding and see if more miscompilations show up.
> 
> Tried it. No miscompilations on Darwin.

Thanks.

Well, if this build succeeds, we get to blame Rafael: http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69 ;-)

I noticed that AnalyzeBranch is doing a whole lot of editing for a function named Analyze*. It will remove the unconditional branch when called with AllowModify=true, as far as I can tell. That means the unconditional branch is probably not going to survive very far downstream.

/jakob



From rafael.espindola at gmail.com  Fri Sep 24 16:19:03 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Sep 2010 21:19:03 -0000
Subject: [llvm-commits] [llvm] r114761 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/local-reloc.s
Message-ID: <20100924211903.82EB42A6C12C@llvm.org>

Author: rafael
Date: Fri Sep 24 16:19:03 2010
New Revision: 114761

URL: http://llvm.org/viewvc/llvm-project?rev=114761&view=rev
Log:
Reapply 114678 and 114667. Reverting them did not fix the bot:

http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69

Added:
    llvm/trunk/test/MC/ELF/local-reloc.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114761&r1=114760&r2=114761&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Fri Sep 24 16:19:03 2010
@@ -515,9 +515,12 @@
     }
 
     if (Base) {
-      if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) {
+      if (F && !SD.isExternal()) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
-        Value += Layout.getSymbolAddress(&SD);
+
+        MCSectionData *FSD = F->getParent();
+        // Offset of the symbol in the section
+        Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
       } else
         Index = getSymbolIndexInSymbolTable(Asm, Symbol);
       if (Base != &SD)

Added: llvm/trunk/test/MC/ELF/local-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/local-reloc.s?rev=114761&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/local-reloc.s (added)
+++ llvm/trunk/test/MC/ELF/local-reloc.s Fri Sep 24 16:19:03 2010
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
+
+// Test that relocations with local symbols are represented as relocations
+// with the section. They should be equivalent, but gas behaves like this.
+
+	movl	foo, %r14d
+foo:
+
+// Section number 1 is .text
+// CHECK:        # Section 1
+// CHECK-next:  (('sh_name', 1) # '.text'
+
+
+// Relocation refers to symbol number 2
+// CHECK:      ('_relocations', [
+// CHECK-NEXT:  # Relocation 0
+// CHECK-NEXT:   (('r_offset',
+// CHECK-NEXT:    ('r_sym', 2)
+// CHECK-NEXT:    ('r_type',
+// CHECK-NEXT:    ('r_addend',
+// CHECK-NEXT:   ),
+// CHECK-NEXT:  ])
+
+// Symbol number 2 is section number 1
+// CHECK:    # Symbol 2
+// CHECK-NEXT:    (('st_name', 0) # ''
+// CHECK-NEXT:     ('st_bind', 0)
+// CHECK-NEXT:     ('st_type', 3)
+// CHECK-NEXT:     ('st_other', 0)
+// CHECK-NEXT:     ('st_shndx', 1)
+// CHECK-NEXT:     ('st_value', 0)
+// CHECK-NEXT:     ('st_size', 0)



From stoklund at 2pi.dk  Fri Sep 24 16:22:07 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 14:22:07 -0700
Subject: [llvm-commits] [llvm] r114761 - in /llvm/trunk:
	lib/MC/ELFObjectWriter.cpp test/MC/ELF/local-reloc.s
In-Reply-To: <20100924211903.82EB42A6C12C@llvm.org>
References: <20100924211903.82EB42A6C12C@llvm.org>
Message-ID: <C9A7F0F8-10B8-41B4-BB10-EE03BEEB6E14@2pi.dk>


On Sep 24, 2010, at 2:19 PM, Rafael Espindola wrote:

> Author: rafael
> Date: Fri Sep 24 16:19:03 2010
> New Revision: 114761
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114761&view=rev
> Log:
> Reapply 114678 and 114667. Reverting them did not fix the bot:
> 
> http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69

Thanks, Rafael!




From bigcheesegs at gmail.com  Fri Sep 24 16:36:56 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Fri, 24 Sep 2010 17:36:56 -0400
Subject: [llvm-commits] [PATCH][System] Add SwapByteOrder and move
 implementation from Support/MathExtras.h.
In-Reply-To: <AANLkTi=geQ-=48bcjWbWugELGwyM9AhRpwrdnN8WJRL7@mail.gmail.com>
References: <AANLkTin+nEOsSZd5Pi-nSXS0OTga2db-T4yG6qOJ3Q_u@mail.gmail.com>
	<AANLkTi=1JphZHJyFUKrxvXLZpRDD0AJTSw4TVQPqKSL7@mail.gmail.com>
	<AANLkTin8L6Xiwvo-PjRq2DNbnTetd=md6t9hsrhJ0cje@mail.gmail.com>
	<AANLkTi=geQ-=48bcjWbWugELGwyM9AhRpwrdnN8WJRL7@mail.gmail.com>
Message-ID: <AANLkTik-mJWKHyE1n+pQBG2-y-FqBphx9pr=UcpnJwuw@mail.gmail.com>

On Fri, Sep 17, 2010 at 11:40 AM, Rafael Espindola <espindola at google.com> wrote:
>> The generic code is actually being used for both COFF and ELF with
>> signed types, but it hasn't been tested because I've only tried out
>> x86{,-64} so far (and thus this function isn't called). If someone
>> could send me a small bigendian ELF file I could add a test for it and
>> make sure everything works.
>
> Is it common to try to byteswap signed integers? If not, it is
> probably a bit safer to just not support it. Things like
>
> int32_t foo;
> int64_t bar = SwapByteOrder(foo);

In this case it depends on what byte order foo is. If it is not host,
then the results will be as expected (byte swapped then sign
extended). If it is already host, then the result will be creepy, and
arguably as expected. It's an operation that doesn't make any sense,
and there's nothing SwapByteOrder can do about it.

> can be a bit surprising. The user might have intended to sign extend
> foo first, but that is not what is going to happen.
>
> I compiled gas with at target of ppc64-linux-gnu and passed it an
> empty .s. The produced .o is attached.
>
>> Thanks for the review!
>>
>> - Michael Spencer
>
> Cheers,
> --
> Rafael ?vila de Esp?ndola
>

I added unittests to verify signed swaps work, and modified the
implementation to error out if any type is used other than
{signed,unsigned} {8,16,32,64}bit integer types.

New patch attached.

- Michael Spencer
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From daniel at zuster.org  Fri Sep 24 16:56:11 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 21:56:11 -0000
Subject: [llvm-commits] [test-suite] r114765 -
 /test-suite/trunk/SingleSource/UnitTests/vla.reference_output
Message-ID: <20100924215611.7BA3C2A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 16:56:11 2010
New Revision: 114765

URL: http://llvm.org/viewvc/llvm-project?rev=114765&view=rev
Log:
Add a reference output.

Added:
    test-suite/trunk/SingleSource/UnitTests/vla.reference_output

Added: test-suite/trunk/SingleSource/UnitTests/vla.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/vla.reference_output?rev=114765&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/vla.reference_output (added)
+++ test-suite/trunk/SingleSource/UnitTests/vla.reference_output Fri Sep 24 16:56:11 2010
@@ -0,0 +1 @@
+exit 0



From evan.cheng at apple.com  Fri Sep 24 17:03:47 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 22:03:47 -0000
Subject: [llvm-commits] [llvm] r114766 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td ARMInstrThumb2.td ARMSchedule.td ARMScheduleA8.td
 ARMScheduleA9.td
Message-ID: <20100924220347.31ED22A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 17:03:46 2010
New Revision: 114766

URL: http://llvm.org/viewvc/llvm-project?rev=114766&view=rev
Log:
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMSchedule.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114766&r1=114765&r2=114766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Sep 24 17:03:46 2010
@@ -2729,9 +2729,11 @@
 // Large immediate handling.
 
 // Two piece so_imms.
+// FIXME: Expand this in ARMExpandPseudoInsts.
+// FIXME: Remove this when we can do generalized remat.
 let isReMaterializable = 1 in
 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
-                         Pseudo, IIC_iMOVi,
+                         Pseudo, IIC_iMOVix2,
                          "mov", "\t$dst, $src",
                          [(set GPR:$dst, so_imm2part:$src)]>,
                   Requires<[IsARM, NoV6T2]>;
@@ -2754,7 +2756,7 @@
 // as a single unit instead of having to handle reg inputs.
 // FIXME: Remove this when we can do generalized remat.
 let isReMaterializable = 1 in
-def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
+def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVix2,
                    "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
                      [(set GPR:$dst, (i32 imm:$src))]>,
                Requires<[IsARM, HasV6T2]>;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114766&r1=114765&r2=114766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep 24 17:03:46 2010
@@ -2689,10 +2689,10 @@
                     (t2_so_neg_imm2part_2 imm:$RHS))>;
 
 // 32-bit immediate using movw + movt.
-// This is a single pseudo instruction to make it re-materializable. Remove
-// when we can do generalized remat.
+// This is a single pseudo instruction to make it re-materializable.
+// FIXME: Remove this when we can do generalized remat.
 let isReMaterializable = 1 in
-def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
+def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
                    "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
                      [(set rGPR:$dst, (i32 imm:$src))]>;
 

Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=114766&r1=114765&r2=114766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Fri Sep 24 17:03:46 2010
@@ -23,6 +23,7 @@
 def IIC_iCMPsi     : InstrItinClass;
 def IIC_iCMPsr     : InstrItinClass;
 def IIC_iMOVi      : InstrItinClass;
+def IIC_iMOVix2    : InstrItinClass;
 def IIC_iMOVr      : InstrItinClass;
 def IIC_iMOVsi     : InstrItinClass;
 def IIC_iMOVsr     : InstrItinClass;

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=114766&r1=114765&r2=114766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Sep 24 17:03:46 2010
@@ -50,6 +50,8 @@
   //
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
+  InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+                             InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=114766&r1=114765&r2=114766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Sep 24 17:03:46 2010
@@ -32,6 +32,8 @@
   //
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
+  InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
+                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,



From John.Thompson.JTSoftware at gmail.com  Fri Sep 24 17:24:05 2010
From: John.Thompson.JTSoftware at gmail.com (John Thompson)
Date: Fri, 24 Sep 2010 22:24:05 -0000
Subject: [llvm-commits] [llvm] r114767 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100924222405.9B02E2A6C12C@llvm.org>

Author: jtsoftware
Date: Fri Sep 24 17:24:05 2010
New Revision: 114767

URL: http://llvm.org/viewvc/llvm-project?rev=114767&view=rev
Log:
Fix for test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crash.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=114767&r1=114766&r2=114767&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Sep 24 17:24:05 2010
@@ -5434,6 +5434,26 @@
   for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
     SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
 
+    // If this is an output operand with a matching input operand, look up the
+    // matching input. If their types mismatch, e.g. one is an integer, the
+    // other is floating point, or their sizes are different, flag it as an
+    // error.
+    if (OpInfo.hasMatchingInput()) {
+      SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
+      
+      if (OpInfo.ConstraintVT != Input.ConstraintVT) {
+        if ((OpInfo.ConstraintVT.isInteger() !=
+             Input.ConstraintVT.isInteger()) ||
+            (OpInfo.ConstraintVT.getSizeInBits() !=
+             Input.ConstraintVT.getSizeInBits())) {
+          report_fatal_error("Unsupported asm: input constraint"
+                             " with a matching output constraint of"
+                             " incompatible type!");
+        }
+        Input.ConstraintVT = OpInfo.ConstraintVT;
+      }
+    }
+
     // Compute the constraint code and ConstraintType to use.
     TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
 



From john.thompson.jtsoftware at gmail.com  Fri Sep 24 17:27:26 2010
From: john.thompson.jtsoftware at gmail.com (John Thompson)
Date: Fri, 24 Sep 2010 15:27:26 -0700
Subject: [llvm-commits] [llvm] r113766 - in /llvm/trunk:
 include/llvm/InlineAsm.h include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Targ
In-Reply-To: <AANLkTikrCdYssmicNN1zJ7FWYDvEGec13BfobgpKJbYG@mail.gmail.com>
References: <AANLkTikrCdYssmicNN1zJ7FWYDvEGec13BfobgpKJbYG@mail.gmail.com>
Message-ID: <AANLkTimFHtBnaqame7k-UhZAMX2xt=ksK9xY4co4Hf9d@mail.gmail.com>

Fixed in r114767.

-John

On Fri, Sep 24, 2010 at 3:19 AM, NAKAMURA Takumi <geek4civic at gmail.com>wrote:

> Good evening, John.
>
> With this commit, test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
> crashes
> when --enable-assertions=no.
> (Un)luckily, this test is marked as "XFAIL: *" and catches crash, too.
>
> I have confirmed on x86_64-linux(CentOS5) with optimization.
> Please see below, thank you;
>
> * r113765
> $ bisect/bin/llc <
> ~/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
>        .machine ppc
>        .section        __TEXT,__textcoal_nt,coalesced,pure_instructions
>        .section
>  __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
>        .section        __TEXT,__text,regular,pure_instructions
> LLVM ERROR: Unsupported asm: input constraint with a matching output
> constraint of incompatible type!
>
> * r113766 (and ToT)
> $ bisect/bin/llc <
> ~/llvm/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
>        .machine ppc
>        .section        __TEXT,__textcoal_nt,coalesced,pure_instructions
>        .section
>  __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
>        .section        __TEXT,__text,regular,pure_instructions
> 0  llc             0x00000000009d295f
> 1  llc             0x00000000009d46fa
> 2  libpthread.so.0 0x00000039de00eb10
> 3  llc             0x00000000005f64af
>
> llvm::SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<llvm::SDValue,
> std::allocator<llvm::SDValue> >&) + 431
> 4  llc             0x00000000005f678f
> llvm::SelectionDAGISel::Select_INLINEASM(llvm::SDNode*) + 239
> 5  llc             0x00000000005f7725
> llvm::SelectionDAGISel::SelectCodeCommon(llvm::SDNode*, unsigned char
> const*, unsigned int) + 1269
> 6  llc             0x000000000050ebe7
> 7  llc             0x00000000005f1c20
> llvm::SelectionDAGISel::DoInstructionSelection() + 368
> 8  llc             0x00000000005f2e8b
> llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 715
> 9  llc             0x00000000005f44de
>
> llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction
> const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 158
> 10 llc             0x00000000005f499d
> llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) +
> 1133
> 11 llc             0x00000000005f53e9
> llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) +
> 361
> 12 llc             0x000000000050e226
> 13 llc             0x00000000009695c9
> llvm::FPPassManager::runOnFunction(llvm::Function&) + 521
> 14 llc             0x000000000096967b
> llvm::FPPassManager::runOnModule(llvm::Module&) + 75
> 15 llc             0x0000000000969221
> llvm::MPPassManager::runOnModule(llvm::Module&) + 465
> 16 llc             0x000000000096933d
> llvm::PassManagerImpl::run(llvm::Module&) + 125
> 17 llc             0x00000000004cdc45 main + 3397
> 18 libc.so.6       0x00000039dd41d994 __libc_start_main + 244
> 19 llc             0x00000000004cbc89 __gxx_personality_v0 + 633
> Stack dump:
> 0.      Program arguments: bisect/bin/llc
> 1.      Running pass 'Function Pass Manager' on module '<stdin>'.
> 2.      Running pass 'PowerPC DAG->DAG Pattern Instruction Selection'
> on function '@test'
>
>
> 2010/9/14 John Thompson <John.Thompson.JTSoftware at gmail.com>:
> > Author: jtsoftware
> > Date: Mon Sep 13 13:15:37 2010
> > New Revision: 113766
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=113766&view=rev
> > Log:
> > Added skeleton for inline asm multiple alternative constraint support.
> >
> > Modified:
> >    llvm/trunk/include/llvm/InlineAsm.h
> >    llvm/trunk/include/llvm/Target/TargetLowering.h
> >    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> >    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> >    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> >    llvm/trunk/lib/Target/X86/X86ISelLowering.h
> >    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
> >    llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
> >    llvm/trunk/lib/VMCore/InlineAsm.cpp
>



-- 
John Thompson
John.Thompson.JTSoftware at gmail.com
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From evan.cheng at apple.com  Fri Sep 24 17:41:41 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 22:41:41 -0000
Subject: [llvm-commits] [llvm] r114768 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrThumb2.td ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td
 ARMScheduleV6.td
Message-ID: <20100924224142.0110B2A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 17:41:41 2010
New Revision: 114768

URL: http://llvm.org/viewvc/llvm-project?rev=114768&view=rev
Log:
More pseudo instruction scheduling itinerary fixes.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMSchedule.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
    llvm/trunk/lib/Target/ARM/ARMScheduleV6.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep 24 17:41:41 2010
@@ -2711,7 +2711,7 @@
 // scheduling.
 let canFoldAsLoad = 1, isReMaterializable = 1 in
 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
-                   NoItinerary,
+                   IIC_iLoadiALU,
                    "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
                [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
                                            imm:$cp))]>,

Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Fri Sep 24 17:41:41 2010
@@ -45,6 +45,7 @@
 def IIC_iLoadsiu   : InstrItinClass;
 def IIC_iLoadm     : InstrItinClass<0>;  // micro-coded
 def IIC_iLoadmBr   : InstrItinClass<0>;  // micro-coded
+def IIC_iLoadiALU  : InstrItinClass;
 def IIC_iStorei    : InstrItinClass;
 def IIC_iStorer    : InstrItinClass;
 def IIC_iStoresi   : InstrItinClass;

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Sep 24 17:41:41 2010
@@ -51,7 +51,7 @@
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
-                             InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
+                             InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
   InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
@@ -133,6 +133,14 @@
                                 InstrStage<1, [A8_LdSt0]>,
                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
+                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+                                InstrStage<1, [A8_LdSt0]>,
+                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
+
+
   // Integer store pipeline
   //
   // use A8_Issue to enforce the 1 load/store per cycle limit

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Sep 24 17:41:41 2010
@@ -33,7 +33,7 @@
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
-                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
+                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
   InstrItinData<IIC_iMOVr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
@@ -115,6 +115,12 @@
                                 InstrStage<1, [A9_LSPipe]>,
                                 InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Pipe1]>,
+                                InstrStage<1, [A9_LSPipe]>,
+                                InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [4, 1]>,
+
   // Integer store pipeline
   ///
   // Immediate offset

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Fri Sep 24 17:41:41 2010
@@ -46,6 +46,8 @@
   InstrItinData<IIC_iMOVr    , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
   InstrItinData<IIC_iMOVsi   , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
   InstrItinData<IIC_iMOVsr   , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
+  InstrItinData<IIC_iMOVix2  , [InstrStage<1, [V6_Pipe]>,
+                                InstrStage<1, [V6_Pipe]>], [2]>,
   //
   // Move instructions, conditional
   InstrItinData<IIC_iCMOVi   , [InstrStage<1, [V6_Pipe]>], [3]>,
@@ -91,6 +93,11 @@
   InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>,
                                 InstrStage<1, [V6_Pipe]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
+                                InstrStage<1, [V6_Pipe]>], [3, 1]>,
+
   // Integer store pipeline
   //
   // Immediate offset



From evan.cheng at apple.com  Fri Sep 24 17:54:57 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 15:54:57 -0700
Subject: [llvm-commits] [llvm] r114681	-
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
In-Reply-To: <83C5B0CC-37B5-4800-9663-14380E7EB91B@2pi.dk>
References: <20100923183219.35D1D2A6C12C@llvm.org> <4C9C52D8.3090708@free.fr>
	<707A7566-7C53-4F36-A6B1-C732B3BE58B2@apple.com>
	<37BE4EFC-83BD-4696-8472-F85A74D6F3AF@2pi.dk>
	<6426039E-DD38-44D5-B30B-84A7EE32AF20@apple.com>
	<89F1B266-141E-4020-8C72-805D33D492E3@apple.com>
	<83C5B0CC-37B5-4800-9663-14380E7EB91B@2pi.dk>
Message-ID: <7A9C1E6E-B26E-4F8F-9A20-1B7AB17B7A4E@apple.com>


On Sep 24, 2010, at 2:15 PM, Jakob Stoklund Olesen wrote:

> 
> On Sep 24, 2010, at 2:05 PM, Evan Cheng wrote:
> 
>> 
>> On Sep 24, 2010, at 12:07 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Sep 24, 2010, at 11:49 AM, Jakob Stoklund Olesen wrote:
>>> 
>>>> 
>>>> On Sep 24, 2010, at 10:48 AM, Evan Cheng wrote:
>>>> 
>>>>> There is definitely a codegen bug downstream. A unconditional branch to a fallthrough block is correct the last time I checked. If someone has some time to look into this, I would appreciate a test case.
>>>> 
>>>> It looks like MachineBasicBlock::canFallThrough affects codegen which could trigger this bug, and MachineBasicBlock::updateTerminator looks like it is going to undo it anyway by removing the unconditional branch.
>>>> 
>>>> Is any code assuming the presence of an unconditional branch?
>>> 
>>> I sure hope not. The reason for this change some DAG transformations require the presence of the unconditional branch following a conditional one so it can flip them. With this case, a lot of fcmp_oeq can be optimized to a pair of conditional branches, rather than two setcc and an and.
>>> 
>>> I've verified machine instruction passes will eliminate the branch to fallthrough. I wonder if we could disable branch folding and see if more miscompilations show up.
>> 
>> Tried it. No miscompilations on Darwin.
> 
> Thanks.
> 
> Well, if this build succeeds, we get to blame Rafael: http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69 ;-)
> 
> I noticed that AnalyzeBranch is doing a whole lot of editing for a function named Analyze*. It will remove the unconditional branch when called with AllowModify=true, as far as I can tell. That means the unconditional branch is probably not going to survive very far downstream.

Yes, AnalyzeBranch is pretty horrible.

Evan

> 
> /jakob
> 



From daniel at zuster.org  Fri Sep 24 18:19:43 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 23:19:43 -0000
Subject: [llvm-commits] [zorg] r114772 - /zorg/trunk/lnt/lnt/tests/nt.py
Message-ID: <20100924231944.039AF2A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 18:19:43 2010
New Revision: 114772

URL: http://llvm.org/viewvc/llvm-project?rev=114772&view=rev
Log:
LNT/nt: When using a remote execution host, capture uname (and optionally sw_vers) from it.

Modified:
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=114772&r1=114771&r2=114772&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Fri Sep 24 18:19:43 2010
@@ -445,6 +445,25 @@
     run_info['tag'] = test_namespace
     run_info.update(cc_info)
 
+    # Capture sw_vers if this looks like Darwin.
+    if 'Darwin' in machine_info['os']:
+        run_info['sw_vers'] = capture(['sw_vers'], include_stderr=True).strip()
+
+    # Query remote properties if in use.
+    if opts.remote:
+        remote_args = [opts.remote_client,
+                       "-l", opts.remote_user,
+                       "-p",  str(opts.remote_port),
+                       opts.remote_host]
+        print remote_args
+        run_info['remote_uname'] = capture(remote_args + ["uname", "-a"],
+                                           include_stderr=True).strip()
+
+        # Capture sw_vers if this looks like Darwin.
+        if 'Darwin' in run_info['remote_uname']:
+            run_info['remote_sw_vers'] = capture(remote_args + ["sw_vers"],
+                                                 include_stderr=True).strip()
+
     # Add machine dependent info.
     if opts.use_machdep_info:
         machdep_info = machine_info



From evan.cheng at apple.com  Fri Sep 24 18:21:13 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Sep 2010 16:21:13 -0700
Subject: [llvm-commits] [llvm] r114506 - in /llvm/trunk:
	lib/Target/ARM/ARMBaseInstrInfo.cpp
	test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
In-Reply-To: <548d15b2-8188-493f-bfcd-3dfa6b028717@m16g2000vbs.googlegroups.com>
References: <20100921234908.2B6822A6C12C@llvm.org>
	<548d15b2-8188-493f-bfcd-3dfa6b028717@m16g2000vbs.googlegroups.com>
Message-ID: <8026F913-CABC-4B41-A7FA-64FB111A9ED4@apple.com>


On Sep 22, 2010, at 3:50 AM, Gabor Greif wrote:

> Hi Evan, All,
> 
> my observations inline below...
> 
> On Sep 22, 1:49 am, Evan Cheng <evan.ch... at apple.com> wrote:
>> Author: evancheng
>> Date: Tue Sep 21 18:49:07 2010
>> New Revision: 114506
>> 
>> URL:http://llvm.org/viewvc/llvm-project?rev=114506&view=rev
>> Log:
>> OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
>> 
>> Added:
>>     llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
>> Modified:
>>     llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBase...
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 21 18:49:07 2010
>> @@ -1455,7 +1455,8 @@
>> 
>>    // Check that CPSR isn't set between the comparison instruction and the one we
>>    // want to change.
>> -  MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
>> +  MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
>> +    B = MI->getParent()->begin();
>>    --I;
>>    for (; I != E; --I) {
>>      const MachineInstr &Instr = *I;
>> @@ -1469,6 +1470,10 @@
>>        if (MO.getReg() == ARM::CPSR)
>>          return false;
>>      }
>> +
>> +    if (I == B)
>> +      // The 'and' is below the comparison instruction.
>> +      return false;
>>    }
>> 
>>    // Set the "zero" bit in CPSR.
>> 
>> Added: llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll
>> URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-...
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll (added)
>> +++ llvm/trunk/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll Tue Sep 21 18:49:07 2010
>> @@ -0,0 +1,84 @@
>> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
>> +
>> +declare noalias i8* @malloc(i32) nounwind
>> +
>> +define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, i8* %pixels) nounwind {
>> +entry:
>> +  br i1 undef, label %bb3.i, label %bb3
>> +
>> +bb3.i:                                            ; preds = %entry
>> +  unreachable
>> +
>> +gl_error.exit:                                    ; preds = %bb22
>> +  ret void
>> +
>> +bb3:                                              ; preds = %entry
>> +  br i1 false, label %bb5, label %bb4
>> +
>> +bb4:                                              ; preds = %bb3
>> +  br label %bb5
>> +
>> +bb5:                                              ; preds = %bb4, %bb3
>> +  br i1 undef, label %bb19, label %bb22
>> +
>> +bb19:                                             ; preds = %bb5
>> +  switch i32 %type, label %bb3.i6.i [
>> +    i32 5120, label %bb1.i13
>> +    i32 5121, label %bb1.i13
>> +    i32 6656, label %bb9.i.i6
>> +  ]
>> +
>> +bb9.i.i6:                                         ; preds = %bb19
>> +  br label %bb1.i13
>> +
>> +bb3.i6.i:                                         ; preds = %bb19
>> +  unreachable
>> +
>> +bb1.i13:                                          ; preds = %bb9.i.i6, %bb19, %bb19
>> +  br i1 undef, label %bb3.i17, label %bb2.i16
>> +
>> +bb2.i16:                                          ; preds = %bb1.i13
>> +  unreachable
>> +
>> +bb3.i17:                                          ; preds = %bb1.i13
>> +  br i1 undef, label %bb4.i18, label %bb23.i
>> +
>> +bb4.i18:                                          ; preds = %bb3.i17
>> +  %0 = mul nsw i32 %height, %width
>> +  %1 = and i32 %0, 7
>> +  %not..i = icmp ne i32 %1, 0
>> +  %2 = zext i1 %not..i to i32
>> +  %storemerge2.i = add i32 0, %2
>> +  %3 = call noalias i8* @malloc(i32 %storemerge2.i) nounwind
>> +  br i1 undef, label %bb3.i9, label %bb9.i
> 
> This seems to instruction select to:
> 
> BB#10: derived from LLVM BB %bb4.i18
>    Predecessors according to CFG: BB#9
>        %reg16402<def> = COPY %reg16385; rGPR:%reg16402 GPR:%reg16385
>        %reg16403<def> = COPY %reg16384; rGPR:%reg16403 GPR:%reg16384
>        %reg16401<def> = t2MUL %reg16402, %reg16403, pred:14, pred:
> %reg0; rGPR:%reg16401,16402,16403
>        %reg16404<def> = t2MOVi 0, pred:14, pred:%reg0, opt:%reg0;
> rGPR:%reg16404
>        t2TSTri %reg16401, 7, pred:14, pred:%reg0, %CPSR<imp-def>;
> rGPR:%reg16401
>        %reg16405<def> = t2MOVCCi %reg16404, 1, pred:1, pred:%CPSR;
> rGPR:%reg16405,16404
>        ADJCALLSTACKDOWN 0, pred:14, pred:%reg0, %SP<imp-def,dead>,
> %SP<imp-use>
>        %R0<def> = COPY %reg16405; rGPR:%reg16405
>        tBLXi_r9 <ga:@malloc>, %R0, %R0<imp-def>, %R1<imp-def,dead>,
> %R3<imp-def,dead>, %CPSR<imp-def,dead>, ...
>        ADJCALLSTACKUP 0, 0, pred:14, pred:%reg0, %SP<imp-def,dead>,
> %SP<imp-use>
>        %reg16407<def> = t2ANDri %reg16401, 7, pred:14, pred:%reg0,
> opt:%reg0; rGPR:%reg16407,16401
>        %reg16387<def> = COPY %reg16407; GPR:%reg16387 rGPR:%reg16407
>        %reg16408<def> = IMPLICIT_DEF; GPR:%reg16408
>        t2CMPzri %reg16408<kill>, 0, pred:14, pred:%reg0, %CPSR<imp-
> def>; GPR:%reg16408
>        t2Bcc <BB#18>, pred:1, pred:%CPSR
>    Successors according to CFG: BB#18 BB#11
> 
> The TST and the AND indeed both consume %reg16401 and the AND is below
> the TST. Your fix is correct to bail out at the start of the BB.
> 
> But I see a missed opportunity here, and I'd like to understand
> whether our arsenal is good enough to recognize it.
> 
> Finally the above ends up to output:
> 
> @ BB#4:                                 @ %bb.i24.i.preheader
>        and     r0, r4, #7
>        movs    r1, #0        ;; why movS? can we change to mov?
>        cmp     r0, #0        ;; equivalent to tst r0, #7, elidable
>        it      ne
>        movne   r1, #1
>        b       LBB0_6
> 
> But I guess the optimal sequence would be:
> 
> @ BB#4:                                 @ %bb.i24.i.preheader
>        andS     r0, r4, #7
>        ite     ne
>        movne   r1, #1
>        moveq   r1, #0  ;; or perhaps equivalently: moveq r1, r0
>        b       LBB0_6

Yes, the schedule is non-optimal. If the optimization is done at isel time, the reuse would have forced a better schedule. That's an issue with doing this optimization after scheduling.

> 
> Please correct me if I missed something :-)
> 
> Anyway, to get here, I must understand a few things:
> 
>        %reg16387<def> = COPY %reg16407; GPR:%reg16387 rGPR:%reg16407
> 
> 1) Why is this copy present at all?

This means the result of t2AND is being used in a successor block.

> 
>        %reg16408<def> = IMPLICIT_DEF; GPR:%reg16408
> 
> 2) What is defined implicitly here?

That's what's being compared to zero. It's likely due to bugpoint reduction.

> 
> 3) Third question: which MachineInst is responsible for the "movs r1,
> #0" above?

t2MOVi will be shortened into a tMOVi which always sets CPSR. Since the optimization is done late it has no effect on the optimization.

Evan


> 
> Hopefully someone can explain this all to me ;-)
> 
> Cheers,
> 
>   Gabor
> 
> 
>> +
>> +bb9.i:                                            ; preds = %bb4.i18
>> +  br i1 undef, label %bb13.i19, label %bb.i24.i
>> +
>> +bb13.i19:                                         ; preds = %bb9.i
>> +  br i1 undef, label %bb14.i20, label %bb15.i
>> +
>> +bb14.i20:                                         ; preds = %bb13.i19
>> +  unreachable
>> +
>> +bb15.i:                                           ; preds = %bb13.i19
>> +  unreachable
>> +
>> +bb.i24.i:                                         ; preds = %bb.i24.i, %bb9.i
>> +  %storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ]
>> +  %4 = add i32 %storemerge1.i21.i, 1
>> +  %exitcond47.i = icmp eq i32 %4, %storemerge2.i
>> +  br i1 %exitcond47.i, label %bb22, label %bb.i24.i
>> +
>> +bb23.i:                                           ; preds = %bb3.i17
>> +  unreachable
>> +
>> +bb3.i9:                                           ; preds = %bb4.i18
>> +  unreachable
>> +
>> +bb22:                                             ; preds = %bb.i24.i, %bb5
>> +  br i1 undef, label %gl_error.exit, label %bb23
>> +
>> +bb23:                                             ; preds = %bb22
>> +  ret void
>> +}
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From daniel at zuster.org  Fri Sep 24 18:25:23 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 24 Sep 2010 23:25:23 -0000
Subject: [llvm-commits] [test-suite] r114773 - in
 /test-suite/trunk/SingleSource/UnitTests/ObjC: for-in.m property.m
 synchronized.m
Message-ID: <20100924232523.E2D4E2A6C12C@llvm.org>

Author: ddunbar
Date: Fri Sep 24 18:25:23 2010
New Revision: 114773

URL: http://llvm.org/viewvc/llvm-project?rev=114773&view=rev
Log:
Use Foundation instead of Cocoa when possible.

Modified:
    test-suite/trunk/SingleSource/UnitTests/ObjC/for-in.m
    test-suite/trunk/SingleSource/UnitTests/ObjC/property.m
    test-suite/trunk/SingleSource/UnitTests/ObjC/synchronized.m

Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/for-in.m
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/for-in.m?rev=114773&r1=114772&r2=114773&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/ObjC/for-in.m (original)
+++ test-suite/trunk/SingleSource/UnitTests/ObjC/for-in.m Fri Sep 24 18:25:23 2010
@@ -1,4 +1,4 @@
-#import <Cocoa/Cocoa.h>
+#import <Foundation/Foundation.h>
 
 #define S(n) @#n
 #define L1(n) S(n+0),S(n+1)

Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/property.m
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/property.m?rev=114773&r1=114772&r2=114773&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/ObjC/property.m (original)
+++ test-suite/trunk/SingleSource/UnitTests/ObjC/property.m Fri Sep 24 18:25:23 2010
@@ -1,4 +1,4 @@
-#include <Cocoa/Cocoa.h>
+#include <Foundation/Foundation.h>
 
 struct S {
   int f0, f1;

Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/synchronized.m
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/synchronized.m?rev=114773&r1=114772&r2=114773&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/ObjC/synchronized.m (original)
+++ test-suite/trunk/SingleSource/UnitTests/ObjC/synchronized.m Fri Sep 24 18:25:23 2010
@@ -1,4 +1,4 @@
-#include <Cocoa/Cocoa.h>
+#include <Foundation/Foundation.h>
 #include <stdio.h>
 
 @interface A : NSThread



From stoklund at 2pi.dk  Fri Sep 24 18:58:56 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Sep 2010 23:58:56 -0000
Subject: [llvm-commits] [llvm] r114776 - in /llvm/trunk:
 include/llvm/CodeGen/LiveIntervalAnalysis.h
 include/llvm/CodeGen/SlotIndexes.h lib/CodeGen/SlotIndexes.cpp
Message-ID: <20100924235857.098462A6C12C@llvm.org>

Author: stoklund
Date: Fri Sep 24 18:58:56 2010
New Revision: 114776

URL: http://llvm.org/viewvc/llvm-project?rev=114776&view=rev
Log:
Terminator gaps were unused. Might as well delete them.

Modified:
    llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
    llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
    llvm/trunk/lib/CodeGen/SlotIndexes.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=114776&r1=114775&r2=114776&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Fri Sep 24 18:58:56 2010
@@ -227,10 +227,6 @@
       return indexes_->getMBBFromIndex(index);
     }
 
-    SlotIndex getMBBTerminatorGap(const MachineBasicBlock *mbb) {
-      return indexes_->getTerminatorGap(mbb);
-    }
-
     SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
       return indexes_->insertMachineInstrInMaps(MI);
     }

Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=114776&r1=114775&r2=114776&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Fri Sep 24 18:58:56 2010
@@ -405,9 +405,6 @@
     /// and MBB id.
     std::vector<IdxMBBPair> idx2MBBMap;
 
-    typedef DenseMap<const MachineBasicBlock*, SlotIndex> TerminatorGapsMap;
-    TerminatorGapsMap terminatorGaps;
-
     // IndexListEntry allocator.
     BumpPtrAllocator ileAllocator;
 
@@ -579,14 +576,6 @@
       return itr->second.second;
     }
 
-    /// Returns the terminator gap for the given index.
-    SlotIndex getTerminatorGap(const MachineBasicBlock *mbb) {
-      TerminatorGapsMap::iterator itr = terminatorGaps.find(mbb);
-      assert(itr != terminatorGaps.end() &&
-             "All MBBs should have terminator gaps in their indexes.");
-      return itr->second;
-    }
-
     /// Returns the basic block which the given index falls in.
     MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
       std::vector<IdxMBBPair>::const_iterator I =
@@ -789,7 +778,6 @@
       MachineFunction::iterator nextMBB =
         llvm::next(MachineFunction::iterator(mbb));
       IndexListEntry *startEntry = createEntry(0, 0);
-      IndexListEntry *terminatorEntry = createEntry(0, 0); 
       IndexListEntry *nextEntry = 0;
 
       if (nextMBB == mbb->getParent()->end()) {
@@ -799,15 +787,10 @@
       }
 
       insert(nextEntry, startEntry);
-      insert(nextEntry, terminatorEntry);
 
       SlotIndex startIdx(startEntry, SlotIndex::LOAD);
-      SlotIndex terminatorIdx(terminatorEntry, SlotIndex::PHI_BIT);
       SlotIndex endIdx(nextEntry, SlotIndex::LOAD);
 
-      terminatorGaps.insert(
-        std::make_pair(mbb, terminatorIdx));
-
       mbb2IdxMap.insert(
         std::make_pair(mbb, std::make_pair(startIdx, endIdx)));
 

Modified: llvm/trunk/lib/CodeGen/SlotIndexes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SlotIndexes.cpp?rev=114776&r1=114775&r2=114776&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SlotIndexes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SlotIndexes.cpp Fri Sep 24 18:58:56 2010
@@ -61,7 +61,6 @@
   mi2iMap.clear();
   mbb2IdxMap.clear();
   idx2MBBMap.clear();
-  terminatorGaps.clear();
   clearList();
 }
 
@@ -112,13 +111,6 @@
       if (mi->isDebugValue())
         continue;
 
-      if (miItr == mbb->getFirstTerminator()) {
-        push_back(createEntry(0, index));
-        terminatorGaps.insert(
-          std::make_pair(mbb, SlotIndex(back(), SlotIndex::PHI_BIT)));
-        index += SlotIndex::NUM;
-      }
-
       // Insert a store index for the instr.
       push_back(createEntry(mi, index));
 
@@ -135,13 +127,6 @@
       index += (Slots + 1) * SlotIndex::NUM;
     }
 
-    if (mbb->getFirstTerminator() == mbb->end()) {
-      push_back(createEntry(0, index));
-      terminatorGaps.insert(
-        std::make_pair(mbb, SlotIndex(back(), SlotIndex::PHI_BIT)));
-      index += SlotIndex::NUM;
-    }
-
     // One blank instruction at the end.
     push_back(createEntry(0, index));    
 
@@ -179,7 +164,7 @@
     curEntry->setIndex(index);
 
     if (curEntry->getInstr() == 0) {
-      // MBB start entry or terminator gap. Just step index by 1.
+      // MBB start entry. Just step index by 1.
       index += SlotIndex::NUM;
     }
     else {



From stoklund at 2pi.dk  Fri Sep 24 19:45:15 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sat, 25 Sep 2010 00:45:15 -0000
Subject: [llvm-commits] [llvm] r114778 - /llvm/trunk/lib/CodeGen/Spiller.cpp
Message-ID: <20100925004515.880452A6C12C@llvm.org>

Author: stoklund
Date: Fri Sep 24 19:45:15 2010
New Revision: 114778

URL: http://llvm.org/viewvc/llvm-project?rev=114778&view=rev
Log:
Remove the only use of SlotIndex::isPHI. This bit is not being set consistently
and it will be removed shortly.

Modified:
    llvm/trunk/lib/CodeGen/Spiller.cpp

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=114778&r1=114777&r2=114778&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Fri Sep 24 19:45:15 2010
@@ -458,7 +458,7 @@
     // Iterate over any PHI kills - we'll need to insert new copies for them.
     for (LiveInterval::iterator LRI = newLI->begin(), LRE = newLI->end();
          LRI != LRE; ++LRI) {
-      if (LRI->valno != newVNI || LRI->end.isPHI())
+      if (LRI->valno != newVNI)
         continue;
       SlotIndex killIdx = LRI->end;
       MachineBasicBlock *killMBB = lis->getMBBFromIndex(killIdx);



From stoklund at 2pi.dk  Fri Sep 24 19:45:18 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sat, 25 Sep 2010 00:45:18 -0000
Subject: [llvm-commits] [llvm] r114779 - in /llvm/trunk:
 include/llvm/CodeGen/SlotIndexes.h lib/CodeGen/LiveIntervalAnalysis.cpp
 lib/CodeGen/SlotIndexes.cpp lib/CodeGen/Splitter.cpp
Message-ID: <20100925004518.DBB822A6C12D@llvm.org>

Author: stoklund
Date: Fri Sep 24 19:45:18 2010
New Revision: 114779

URL: http://llvm.org/viewvc/llvm-project?rev=114779&view=rev
Log:
Remove SlotIndex::PHI_BIT. It is no longer used by anything.

Modified:
    llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/SlotIndexes.cpp
    llvm/trunk/lib/CodeGen/Splitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=114779&r1=114778&r2=114779&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Fri Sep 24 19:45:18 2010
@@ -13,10 +13,7 @@
 //
 // SlotIndex is mostly a proxy for entries of the SlotIndexList, a class which
 // is held is LiveIntervals and provides the real numbering. This allows
-// LiveIntervals to perform largely transparent renumbering. The SlotIndex
-// class does hold a PHI bit, which determines whether the index relates to a
-// PHI use or def point, or an actual instruction. See the SlotIndex class
-// description for futher information.
+// LiveIntervals to perform largely transparent renumbering.
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_SLOTINDEXES_H
@@ -130,12 +127,10 @@
 
     enum Slot { LOAD, USE, DEF, STORE, NUM };
 
-    static const unsigned PHI_BIT = 1 << 2;
+    PointerIntPair<IndexListEntry*, 2, unsigned> lie;
 
-    PointerIntPair<IndexListEntry*, 3, unsigned> lie;
-
-    SlotIndex(IndexListEntry *entry, unsigned phiAndSlot)
-      : lie(entry, phiAndSlot) {
+    SlotIndex(IndexListEntry *entry, unsigned slot)
+      : lie(entry, slot) {
       assert(entry != 0 && "Attempt to construct index with 0 pointer.");
     }
 
@@ -149,7 +144,7 @@
 
     /// Returns the slot for this SlotIndex.
     Slot getSlot() const {
-      return static_cast<Slot>(lie.getInt()  & ~PHI_BIT);
+      return static_cast<Slot>(lie.getInt());
     }
 
     static inline unsigned getHashValue(const SlotIndex &v) {
@@ -166,22 +161,13 @@
     static inline SlotIndex getTombstoneKey() {
       return SlotIndex(IndexListEntry::getTombstoneKeyEntry(), 0);
     }
-    
+
     /// Construct an invalid index.
     SlotIndex() : lie(IndexListEntry::getEmptyKeyEntry(), 0) {}
 
-    // Construct a new slot index from the given one, set the phi flag on the
-    // new index to the value of the phi parameter.
-    SlotIndex(const SlotIndex &li, bool phi)
-      : lie(&li.entry(), phi ? PHI_BIT | li.getSlot() : (unsigned)li.getSlot()){
-      assert(lie.getPointer() != 0 &&
-             "Attempt to construct index with 0 pointer.");
-    }
-
-    // Construct a new slot index from the given one, set the phi flag on the
-    // new index to the value of the phi parameter, and the slot to the new slot.
-    SlotIndex(const SlotIndex &li, bool phi, Slot s)
-      : lie(&li.entry(), phi ? PHI_BIT | s : (unsigned)s) {
+    // Construct a new slot index from the given one, and set the slot.
+    SlotIndex(const SlotIndex &li, Slot s)
+      : lie(&li.entry(), unsigned(s)) {
       assert(lie.getPointer() != 0 &&
              "Attempt to construct index with 0 pointer.");
     }
@@ -236,11 +222,6 @@
       return other.getIndex() - getIndex();
     }
 
-    /// Returns the state of the PHI bit.
-    bool isPHI() const {
-      return lie.getInt() & PHI_BIT;
-    }
-
     /// isLoad - Return true if this is a LOAD slot.
     bool isLoad() const {
       return getSlot() == LOAD;

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=114779&r1=114778&r2=114779&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Sep 24 19:45:18 2010
@@ -393,8 +393,7 @@
       // Create interval with one of a NEW value number.  Note that this value
       // number isn't actually defined by an instruction, weird huh? :)
       if (PHIJoin) {
-        ValNo = interval.getNextValue(SlotIndex(Start, true), 0, false,
-                                      VNInfoAllocator);
+        ValNo = interval.getNextValue(Start, 0, false, VNInfoAllocator);
         ValNo->setIsPHIDef(true);
       }
       LiveRange LR(Start, killIdx, ValNo);
@@ -673,8 +672,7 @@
   }
 
   VNInfo *vni =
-    interval.getNextValue(SlotIndex(getMBBStartIdx(MBB), true),
-                          0, false, VNInfoAllocator);
+    interval.getNextValue(getMBBStartIdx(MBB), 0, false, VNInfoAllocator);
   vni->setIsPHIDef(true);
   LiveRange LR(start, end, vni);
 

Modified: llvm/trunk/lib/CodeGen/SlotIndexes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SlotIndexes.cpp?rev=114779&r1=114778&r2=114779&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SlotIndexes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SlotIndexes.cpp Fri Sep 24 19:45:18 2010
@@ -199,11 +199,7 @@
 
 // Print a SlotIndex to a raw_ostream.
 void SlotIndex::print(raw_ostream &os) const {
-  os << entry().getIndex();
-  if (isPHI())
-    os << "*";
-  else
-    os << "LudS"[getSlot()];
+  os << entry().getIndex() << "LudS"[getSlot()];
 }
 
 // Dump a SlotIndex to stderr.

Modified: llvm/trunk/lib/CodeGen/Splitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.cpp?rev=114779&r1=114778&r2=114779&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Splitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/Splitter.cpp Fri Sep 24 19:45:18 2010
@@ -178,8 +178,7 @@
         li.removeRange(ls.lis->getMBBStartIdx(outBlock), copyDefIdx);
 
         VNInfo *newVal =
-          getNewLI()->getNextValue(SlotIndex(ls.lis->getMBBStartIdx(outBlock),
-                                             true),
+          getNewLI()->getNextValue(ls.lis->getMBBStartIdx(outBlock),
                                    0, false, ls.lis->getVNInfoAllocator());
 
         getNewLI()->addRange(LiveRange(ls.lis->getMBBStartIdx(outBlock),



From evan.cheng at apple.com  Fri Sep 24 19:49:35 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Sat, 25 Sep 2010 00:49:35 -0000
Subject: [llvm-commits] [llvm] r114780 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td
 ARMScheduleV6.td
Message-ID: <20100925004935.C72D92A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 19:49:35 2010
New Revision: 114780

URL: http://llvm.org/viewvc/llvm-project?rev=114780&view=rev
Log:
Fix zero and sign extension instructions scheduling itineraries.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMSchedule.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
    llvm/trunk/lib/Target/ARM/ARMScheduleV6.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114780&r1=114779&r2=114780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Sep 24 19:49:35 2010
@@ -534,69 +534,69 @@
 }
 }
 
-/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
+/// AI_ext_rrot - A unary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
-multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
+multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
   def r     : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
-                 IIC_iUNAr, opc, "\t$dst, $src",
+                 IIC_iEXTr, opc, "\t$dst, $src",
                  [(set GPR:$dst, (opnode GPR:$src))]>,
               Requires<[IsARM, HasV6]> {
     let Inst{11-10} = 0b00;
     let Inst{19-16} = 0b1111;
   }
   def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
-                 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
+                 IIC_iEXTr, opc, "\t$dst, $src, ror $rot",
                  [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
               Requires<[IsARM, HasV6]> {
     let Inst{19-16} = 0b1111;
   }
 }
 
-multiclass AI_unary_rrot_np<bits<8> opcod, string opc> {
+multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
   def r     : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
-                 IIC_iUNAr, opc, "\t$dst, $src",
+                 IIC_iEXTr, opc, "\t$dst, $src",
                  [/* For disassembly only; pattern left blank */]>,
               Requires<[IsARM, HasV6]> {
     let Inst{11-10} = 0b00;
     let Inst{19-16} = 0b1111;
   }
   def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
-                 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
+                 IIC_iEXTr, opc, "\t$dst, $src, ror $rot",
                  [/* For disassembly only; pattern left blank */]>,
               Requires<[IsARM, HasV6]> {
     let Inst{19-16} = 0b1111;
   }
 }
 
-/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
+/// AI_exta_rrot - A binary operation with two forms: one whose operand is a
 /// register and one whose operand is a register rotated by 8/16/24.
-multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
+multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
   def rr     : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
-                  IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
+                  IIC_iEXTAr, opc, "\t$dst, $LHS, $RHS",
                   [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
                Requires<[IsARM, HasV6]> {
     let Inst{11-10} = 0b00;
   }
   def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
                                               i32imm:$rot),
-                  IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
+                  IIC_iEXTAr, opc, "\t$dst, $LHS, $RHS, ror $rot",
                   [(set GPR:$dst, (opnode GPR:$LHS,
                                           (rotr GPR:$RHS, rot_imm:$rot)))]>,
                   Requires<[IsARM, HasV6]>;
 }
 
 // For disassembly only.
-multiclass AI_bin_rrot_np<bits<8> opcod, string opc> {
+multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
   def rr     : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
-                  IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
+                  IIC_iEXTAr, opc, "\t$dst, $LHS, $RHS",
                   [/* For disassembly only; pattern left blank */]>,
                Requires<[IsARM, HasV6]> {
     let Inst{11-10} = 0b00;
   }
   def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
                                               i32imm:$rot),
-                  IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
+                  IIC_iEXTAr, opc, "\t$dst, $LHS, $RHS, ror $rot",
                   [/* For disassembly only; pattern left blank */]>,
                   Requires<[IsARM, HasV6]>;
 }
@@ -1551,31 +1551,31 @@
 
 // Sign extenders
 
-defm SXTB  : AI_unary_rrot<0b01101010,
-                           "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
-defm SXTH  : AI_unary_rrot<0b01101011,
-                           "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
+defm SXTB  : AI_ext_rrot<0b01101010,
+                         "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
+defm SXTH  : AI_ext_rrot<0b01101011,
+                         "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
 
-defm SXTAB : AI_bin_rrot<0b01101010,
+defm SXTAB : AI_exta_rrot<0b01101010,
                "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
-defm SXTAH : AI_bin_rrot<0b01101011,
+defm SXTAH : AI_exta_rrot<0b01101011,
                "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
 
 // For disassembly only
-defm SXTB16  : AI_unary_rrot_np<0b01101000, "sxtb16">;
+defm SXTB16  : AI_ext_rrot_np<0b01101000, "sxtb16">;
 
 // For disassembly only
-defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">;
+defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
 
 // Zero extenders
 
 let AddedComplexity = 16 in {
-defm UXTB   : AI_unary_rrot<0b01101110,
-                            "uxtb"  , UnOpFrag<(and node:$Src, 0x000000FF)>>;
-defm UXTH   : AI_unary_rrot<0b01101111,
-                            "uxth"  , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
-defm UXTB16 : AI_unary_rrot<0b01101100,
-                            "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
+defm UXTB   : AI_ext_rrot<0b01101110,
+                          "uxtb"  , UnOpFrag<(and node:$Src, 0x000000FF)>>;
+defm UXTH   : AI_ext_rrot<0b01101111,
+                          "uxth"  , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
+defm UXTB16 : AI_ext_rrot<0b01101100,
+                          "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
 
 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
 //        The transformation should probably be done as a combiner action
@@ -1586,15 +1586,15 @@
 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
                (UXTB16r_rot GPR:$Src, 8)>;
 
-defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
+defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
                         BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
-defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
+defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
                         BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
 }
 
 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
 // For disassembly only
-defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">;
+defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
 
 
 def SBFX  : I<(outs GPR:$dst),

Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=114780&r1=114779&r2=114780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Fri Sep 24 19:49:35 2010
@@ -18,6 +18,8 @@
 def IIC_iUNAr      : InstrItinClass;
 def IIC_iUNAsi     : InstrItinClass;
 def IIC_iUNAsr     : InstrItinClass;
+def IIC_iEXTr      : InstrItinClass;
+def IIC_iEXTAr     : InstrItinClass;
 def IIC_iCMPi      : InstrItinClass;
 def IIC_iCMPr      : InstrItinClass;
 def IIC_iCMPsi     : InstrItinClass;

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=114780&r1=114779&r2=114780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Sep 24 19:49:35 2010
@@ -42,6 +42,10 @@
   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
   InstrItinData<IIC_iUNAsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
   //
+  // Zero and sign extension instructions
+  InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
+  InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>,
+  //
   // Compare instructions
   InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
   InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=114780&r1=114779&r2=114780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Sep 24 19:49:35 2010
@@ -52,6 +52,10 @@
   InstrItinData<IIC_iUNAsi  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
   InstrItinData<IIC_iUNAsr  , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
   //
+  // Zero and sign extension instructions
+  InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
+  InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [3, 1, 1]>,
+  //
   // Compare instructions
   InstrItinData<IIC_iCMPi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
   InstrItinData<IIC_iCMPr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=114780&r1=114779&r2=114780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Fri Sep 24 19:49:35 2010
@@ -35,6 +35,10 @@
   InstrItinData<IIC_iUNAsi   , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
   InstrItinData<IIC_iUNAsr   , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
   //
+  // Zero and sign extension instructions
+  InstrItinData<IIC_iEXTr    , [InstrStage<1, [V6_Pipe]>], [1, 1]>,
+  InstrItinData<IIC_iEXTAr   , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,
+  //
   // Compare instructions
   InstrItinData<IIC_iCMPi    , [InstrStage<1, [V6_Pipe]>], [2]>,
   InstrItinData<IIC_iCMPr    , [InstrStage<1, [V6_Pipe]>], [2, 2]>,



From echristo at apple.com  Fri Sep 24 19:57:26 2010
From: echristo at apple.com (Eric Christopher)
Date: Sat, 25 Sep 2010 00:57:26 -0000
Subject: [llvm-commits] [llvm] r114781 -
	/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
Message-ID: <20100925005726.CBE142A6C12C@llvm.org>

Author: echristo
Date: Fri Sep 24 19:57:26 2010
New Revision: 114781

URL: http://llvm.org/viewvc/llvm-project?rev=114781&view=rev
Log:
If we're changing the source of a memcpy we need to use the alignment
of the source, not the original alignment since it may no longer
be valid.

Fixes rdar://8400094

Modified:
    llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=114781&r1=114780&r2=114781&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Fri Sep 24 19:57:26 2010
@@ -697,14 +697,16 @@
                                  M->getParent()->getParent()->getParent(),
                                  M->getIntrinsicID(), ArgTys, 3);
     
+  // Make sure to use the alignment of the source since we're changing the
+  // location we're reading from.
+  // TODO: Is this worth it if we're creating a less aligned memcpy? For
+  // example we could be moving from movaps -> movq on x86.
   Value *Args[5] = {
     M->getRawDest(), MDep->getRawSource(), M->getLength(),
-    M->getAlignmentCst(), M->getVolatileCst()
+    MDep->getAlignmentCst(), M->getVolatileCst()
   };
-  
   CallInst *C = CallInst::Create(MemCpyFun, Args, Args+5, "", M);
   
-  
   // If C and M don't interfere, then this is a valid transformation.  If they
   // did, this would mean that the two sources overlap, which would be bad.
   if (MD.getDependency(C) == dep) {



From evan.cheng at apple.com  Fri Sep 24 20:06:02 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Sat, 25 Sep 2010 01:06:02 -0000
Subject: [llvm-commits] [llvm] r114782 - in /llvm/trunk/lib/Target/ARM:
 ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td ARMScheduleV6.td
Message-ID: <20100925010602.3F9D82A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 20:06:02 2010
New Revision: 114782

URL: http://llvm.org/viewvc/llvm-project?rev=114782&view=rev
Log:
Remove a unused instruction itinerary class.

Modified:
    llvm/trunk/lib/Target/ARM/ARMSchedule.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
    llvm/trunk/lib/Target/ARM/ARMScheduleV6.td

Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=114782&r1=114781&r2=114782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Fri Sep 24 20:06:02 2010
@@ -17,7 +17,6 @@
 def IIC_iALUsr     : InstrItinClass;
 def IIC_iUNAr      : InstrItinClass;
 def IIC_iUNAsi     : InstrItinClass;
-def IIC_iUNAsr     : InstrItinClass;
 def IIC_iEXTr      : InstrItinClass;
 def IIC_iEXTAr     : InstrItinClass;
 def IIC_iCMPi      : InstrItinClass;

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=114782&r1=114781&r2=114782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Sep 24 20:06:02 2010
@@ -40,7 +40,6 @@
   // Unary Instructions that produce a result
   InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
   InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>,
-  InstrItinData<IIC_iUNAsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>,
   //
   // Zero and sign extension instructions
   InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=114782&r1=114781&r2=114782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Sep 24 20:06:02 2010
@@ -50,7 +50,6 @@
   // Unary Instructions that produce a result
   InstrItinData<IIC_iUNAr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
   InstrItinData<IIC_iUNAsi  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
-  InstrItinData<IIC_iUNAsr  , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
   //
   // Zero and sign extension instructions
   InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=114782&r1=114781&r2=114782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Fri Sep 24 20:06:02 2010
@@ -33,7 +33,6 @@
   // Unary Instructions that produce a result
   InstrItinData<IIC_iUNAr    , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
   InstrItinData<IIC_iUNAsi   , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
-  InstrItinData<IIC_iUNAsr   , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
   //
   // Zero and sign extension instructions
   InstrItinData<IIC_iEXTr    , [InstrStage<1, [V6_Pipe]>], [1, 1]>,



From bigcheesegs at gmail.com  Fri Sep 24 20:09:37 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Fri, 24 Sep 2010 21:09:37 -0400
Subject: [llvm-commits] [PATCH][Support] Add Endian.h which contains
 generic code to deal with endian specific data.
In-Reply-To: <AANLkTi=0+2WSjKif9965KPc7J_Tx2aO+6xsjZ00Ot9ji@mail.gmail.com>
References: <AANLkTi=0+2WSjKif9965KPc7J_Tx2aO+6xsjZ00Ot9ji@mail.gmail.com>
Message-ID: <AANLkTikU0AFnj7qeeL1ViqpUyz8Vf8XgPGHi3ZV7z2k1@mail.gmail.com>

On Tue, Sep 14, 2010 at 5:53 PM, Michael Spencer <bigcheesegs at gmail.com> wrote:
> The attached patch adds Endian.h to Support. This patch is a
> prerequisite for the object file library I am writing.
>
> Endian.h contains:
>
> * SwapByteOrderIfDifferent
> This is a templated function that takes a value_type, and returns the
> value if host and target are the same, or returns the value with its
> endianness swapped if they are different.
> (host and target are int's because MSVC doesn't support enums used
> like this. see:
> http://stackoverflow.com/questions/2763836/sfinae-failing-with-enum-template-parameter)
>
> * endian
> This is a templated struct for reading endian specific data directly
> from memory. It is typedefed based on the host platform's endianness
> (well, not yet, because there's no LLVM_IS_BIG_ENDIAN or such yet).
>
> * packed_endian_specific_integral
> This is the most important thing included in this patch. This class
> allows the portable creation of packed structs of any integral integer
> value_type and endianness. Any struct that would be POD if it used
> normal integral data types is still POD if it uses these.
>
> This is used extensively in the object file library to directly access
> memory mapped object files. In the case when host and target
> endianness match (and the compiler inlines), using these should
> produce identical code to "*reinterpret_cast<value_type*>(memory)".
>
> - Michael Spencer
>

New version, now with unittests.

- Michael Spencer
-------------- next part --------------
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From evan.cheng at apple.com  Fri Sep 24 20:09:28 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Sat, 25 Sep 2010 01:09:28 -0000
Subject: [llvm-commits] [llvm] r114784 -
	/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
Message-ID: <20100925010928.5374F2A6C12C@llvm.org>

Author: evancheng
Date: Fri Sep 24 20:09:28 2010
New Revision: 114784

URL: http://llvm.org/viewvc/llvm-project?rev=114784&view=rev
Log:
Fix IIC_iEXTAr itinerary class of Cortex-A9.

Modified:
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=114784&r1=114783&r2=114784&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Sep 24 20:09:28 2010
@@ -53,7 +53,7 @@
   //
   // Zero and sign extension instructions
   InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
-  InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [3, 1, 1]>,
+  InstrItinData<IIC_iEXTAr, [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [3, 1, 1]>,
   //
   // Compare instructions
   InstrItinData<IIC_iCMPi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,



From bigcheesegs at gmail.com  Fri Sep 24 20:43:45 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Fri, 24 Sep 2010 21:43:45 -0400
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
In-Reply-To: <87sk0ykj1m.fsf@telefonica.net>
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
Message-ID: <AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>

On Fri, Sep 24, 2010 at 4:01 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
> Michael Spencer <bigcheesegs at gmail.com>
> writes:
>
>> This was requested for the msvc build bot as building ALL_BUILD from
>> VSBuild doesn't build anything and we needed to disable building
>> unittests and examples.
>
> I don't understand this. So if the cmake invocation contains
> -DLLVM_BUILD_EXAMPLES=OFF this is a problem?

The only way to build (that we could find) clang from the command line
using VCBuild is to build the entire solution, which includes the
tools, examples, and tests no matter what. LLVM_BUILD_X only controls
if they are part of the ALL_BUILD target, and building ALL_BUILD
doesn't build anything with VCBuild.

> And why you don't want to build examples and unittests on the bot, if
> precisely the purpose of the bot is to test the build? (*all* the build,
> I guess)

This is a clang tester, it slows it down. And the unittests don't
build on msvc9 (they do in 10).

>> I don't really like the implementation because it may be confusing to
>> the user because LLVM_INCLUDE_X is ignored if LLVM_BUILD_X is on. I
>> tried getting CMake to update the cache so ccmake and cmake-gui would
>> show the change, but it didn't work :(. I would appreciate any help in
>> making this implementation more robust.
>
> I don't like the patch either. The previous implementation supported
> ignoring the tools and examples on the default build but allowing
> building them later as the user demanded. Now if the user wants to build
> a tool or example, he must reconfigure and incorporate *all* the tools
> examples to the default build.

Ugg, the intention was to not change the behavior at all for TOOLS and
EXAMPLES. TOOLS is currently the same, but I accidentally changed
EXAMPLES. LLVM_INCLUDE_EXAMPLES should default to ON.

> Please explain in more detail what the problem is and maybe we can find
> a better implementation.

There are two options per group. LLVM_BUILD_X and LLVM_INCLUDE_X.
LLVM_BUILD_X says that X should be built by ALL_BUILD, and
LLVM_INCLUDE_X says that X should be included as a target that is
available to be built. LLVM_BUILD_X must imply LLVM_INCLUDE_X, as you
cannot build a target that doesn't exist.

The problem is that I could not find a way to change the cache value
of LLVM_INCLUDE_X displayed in ccache and cmake-gui to ON if
LLVM_BUILD_X is ON. This would make it clearer to the user and make
the code simpler.

> The current one removes a convenience from the
> user

It shouldn't. See above.

> and is unnecessarily complex (why not
>
> if( LLVM_INCLUDE_X )
> ?add_subdirectory(X)
> endif()
>
> instead of changing add_llvm_X)

I agree. However, it should be:

if( LLVM_INCLUDE_X OR LLVM_BUILD_X )

Because of the problem above.

> In any case, removing an option (LLVM_BUILD_TOOLS)

No options were removed.

>  and introducing a new
> one (LLVM_INCLUDE_TOOLS) requires updating docs/CMake.html.

I agree.

> Oh, and next time it would be a good idea to discuss the patch before
> committing it.

It didn't (well, wasn't supposed to) have any functionality changes,
it's rather small, and it was needed to fix the build bot. Is this
really too much for review after commit?

- Michael Spencer


From bigcheesegs at gmail.com  Fri Sep 24 21:17:50 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Fri, 24 Sep 2010 22:17:50 -0400
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
In-Reply-To: <AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
	<AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>
Message-ID: <AANLkTi=_n78-JoHN_TOScu_QC9h4o-SFK2nDRVDzgjdh@mail.gmail.com>

On Fri, Sep 24, 2010 at 9:43 PM, Michael Spencer <bigcheesegs at gmail.com> wrote:
> On Fri, Sep 24, 2010 at 4:01 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
>> Michael Spencer <bigcheesegs at gmail.com>
>> writes:
>>
>>> This was requested for the msvc build bot as building ALL_BUILD from
>>> VSBuild doesn't build anything and we needed to disable building
>>> unittests and examples.
>>
>> I don't understand this. So if the cmake invocation contains
>> -DLLVM_BUILD_EXAMPLES=OFF this is a problem?
>
> The only way to build (that we could find) clang from the command line
> using VCBuild is to build the entire solution, which includes the
> tools, examples, and tests no matter what. LLVM_BUILD_X only controls
> if they are part of the ALL_BUILD target, and building ALL_BUILD
> doesn't build anything with VCBuild.
>
>> And why you don't want to build examples and unittests on the bot, if
>> precisely the purpose of the bot is to test the build? (*all* the build,
>> I guess)
>
> This is a clang tester, it slows it down. And the unittests don't
> build on msvc9 (they do in 10).
>
>>> I don't really like the implementation because it may be confusing to
>>> the user because LLVM_INCLUDE_X is ignored if LLVM_BUILD_X is on. I
>>> tried getting CMake to update the cache so ccmake and cmake-gui would
>>> show the change, but it didn't work :(. I would appreciate any help in
>>> making this implementation more robust.
>>
>> I don't like the patch either. The previous implementation supported
>> ignoring the tools and examples on the default build but allowing
>> building them later as the user demanded. Now if the user wants to build
>> a tool or example, he must reconfigure and incorporate *all* the tools
>> examples to the default build.
>
> Ugg, the intention was to not change the behavior at all for TOOLS and
> EXAMPLES. TOOLS is currently the same, but I accidentally changed
> EXAMPLES. LLVM_INCLUDE_EXAMPLES should default to ON.
>
>> Please explain in more detail what the problem is and maybe we can find
>> a better implementation.
>
> There are two options per group. LLVM_BUILD_X and LLVM_INCLUDE_X.
> LLVM_BUILD_X says that X should be built by ALL_BUILD, and
> LLVM_INCLUDE_X says that X should be included as a target that is
> available to be built. LLVM_BUILD_X must imply LLVM_INCLUDE_X, as you
> cannot build a target that doesn't exist.
>
> The problem is that I could not find a way to change the cache value
> of LLVM_INCLUDE_X displayed in ccache and cmake-gui to ON if
> LLVM_BUILD_X is ON. This would make it clearer to the user and make
> the code simpler.
>
>> The current one removes a convenience from the
>> user
>
> It shouldn't. See above.
>
>> and is unnecessarily complex (why not
>>
>> if( LLVM_INCLUDE_X )
>> ?add_subdirectory(X)
>> endif()
>>
>> instead of changing add_llvm_X)
>
> I agree. However, it should be:
>
> if( LLVM_INCLUDE_X OR LLVM_BUILD_X )
>
> Because of the problem above.
>
>> In any case, removing an option (LLVM_BUILD_TOOLS)
>
> No options were removed.
>
>> ?and introducing a new
>> one (LLVM_INCLUDE_TOOLS) requires updating docs/CMake.html.
>
> I agree.
>
>> Oh, and next time it would be a good idea to discuss the patch before
>> committing it.
>
> It didn't (well, wasn't supposed to) have any functionality changes,
> it's rather small, and it was needed to fix the build bot. Is this
> really too much for review after commit?
>
> - Michael Spencer
>

Attached is a patch that fixes the above (except for auto updating
LLVM_INCLUDE_X).

- Michael Spencer
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From bigcheesegs at gmail.com  Fri Sep 24 21:44:32 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Fri, 24 Sep 2010 22:44:32 -0400
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
In-Reply-To: <AANLkTi=_n78-JoHN_TOScu_QC9h4o-SFK2nDRVDzgjdh@mail.gmail.com>
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
	<AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>
	<AANLkTi=_n78-JoHN_TOScu_QC9h4o-SFK2nDRVDzgjdh@mail.gmail.com>
Message-ID: <AANLkTinfXgAw4KmYUTng0oSwQ5jE9n5e__mUzTOEUan7@mail.gmail.com>

On Fri, Sep 24, 2010 at 10:17 PM, Michael Spencer <bigcheesegs at gmail.com> wrote:
> On Fri, Sep 24, 2010 at 9:43 PM, Michael Spencer <bigcheesegs at gmail.com> wrote:
>> On Fri, Sep 24, 2010 at 4:01 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
>>> Michael Spencer <bigcheesegs at gmail.com>
>>> writes:
>>>
>>>> This was requested for the msvc build bot as building ALL_BUILD from
>>>> VSBuild doesn't build anything and we needed to disable building
>>>> unittests and examples.
>>>
>>> I don't understand this. So if the cmake invocation contains
>>> -DLLVM_BUILD_EXAMPLES=OFF this is a problem?
>>
>> The only way to build (that we could find) clang from the command line
>> using VCBuild is to build the entire solution, which includes the
>> tools, examples, and tests no matter what. LLVM_BUILD_X only controls
>> if they are part of the ALL_BUILD target, and building ALL_BUILD
>> doesn't build anything with VCBuild.
>>
>>> And why you don't want to build examples and unittests on the bot, if
>>> precisely the purpose of the bot is to test the build? (*all* the build,
>>> I guess)
>>
>> This is a clang tester, it slows it down. And the unittests don't
>> build on msvc9 (they do in 10).
>>
>>>> I don't really like the implementation because it may be confusing to
>>>> the user because LLVM_INCLUDE_X is ignored if LLVM_BUILD_X is on. I
>>>> tried getting CMake to update the cache so ccmake and cmake-gui would
>>>> show the change, but it didn't work :(. I would appreciate any help in
>>>> making this implementation more robust.
>>>
>>> I don't like the patch either. The previous implementation supported
>>> ignoring the tools and examples on the default build but allowing
>>> building them later as the user demanded. Now if the user wants to build
>>> a tool or example, he must reconfigure and incorporate *all* the tools
>>> examples to the default build.
>>
>> Ugg, the intention was to not change the behavior at all for TOOLS and
>> EXAMPLES. TOOLS is currently the same, but I accidentally changed
>> EXAMPLES. LLVM_INCLUDE_EXAMPLES should default to ON.
>>
>>> Please explain in more detail what the problem is and maybe we can find
>>> a better implementation.
>>
>> There are two options per group. LLVM_BUILD_X and LLVM_INCLUDE_X.
>> LLVM_BUILD_X says that X should be built by ALL_BUILD, and
>> LLVM_INCLUDE_X says that X should be included as a target that is
>> available to be built. LLVM_BUILD_X must imply LLVM_INCLUDE_X, as you
>> cannot build a target that doesn't exist.
>>
>> The problem is that I could not find a way to change the cache value
>> of LLVM_INCLUDE_X displayed in ccache and cmake-gui to ON if
>> LLVM_BUILD_X is ON. This would make it clearer to the user and make
>> the code simpler.
>>
>>> The current one removes a convenience from the
>>> user
>>
>> It shouldn't. See above.
>>
>>> and is unnecessarily complex (why not
>>>
>>> if( LLVM_INCLUDE_X )
>>> ?add_subdirectory(X)
>>> endif()
>>>
>>> instead of changing add_llvm_X)
>>
>> I agree. However, it should be:
>>
>> if( LLVM_INCLUDE_X OR LLVM_BUILD_X )
>>
>> Because of the problem above.
>>
>>> In any case, removing an option (LLVM_BUILD_TOOLS)
>>
>> No options were removed.
>>
>>> ?and introducing a new
>>> one (LLVM_INCLUDE_TOOLS) requires updating docs/CMake.html.
>>
>> I agree.
>>
>>> Oh, and next time it would be a good idea to discuss the patch before
>>> committing it.
>>
>> It didn't (well, wasn't supposed to) have any functionality changes,
>> it's rather small, and it was needed to fix the build bot. Is this
>> really too much for review after commit?
>>
>> - Michael Spencer
>>
>
> Attached is a patch that fixes the above (except for auto updating
> LLVM_INCLUDE_X).
>
> - Michael Spencer
>

There was a bug in that last patch. Correct patch attached.

- Michael Spencer
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From ofv at wanadoo.es  Fri Sep 24 22:41:35 2010
From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=)
Date: Sat, 25 Sep 2010 05:41:35 +0200
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
	cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
	utils/unittest/CMakeLists.txt
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
	<AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>
Message-ID: <87bp7mjxqo.fsf@telefonica.net>

Michael Spencer <bigcheesegs at gmail.com>
writes:

> The only way to build (that we could find) clang from the command line
> using VCBuild is to build the entire solution, which includes the
> tools, examples, and tests no matter what. LLVM_BUILD_X only controls
> if they are part of the ALL_BUILD target, and building ALL_BUILD
> doesn't build anything with VCBuild.

cmake --build .

on the build directory works fine here, omitting the examples as
required by the setting of LLVM_BUILD_EXAMPLES.

And is it really important to build with VCBuild? NMake works fine and
seems faster than VCBuild. And JOM allows parallel builds, in case the
bot is a multicore machine.

But if you want to speed-up the VS build you could investigate why
tblgen is so slow on Windows. The time it takes to process the files
associated to the X86 target is quite larger than the required for
building the examples.

>> And why you don't want to build examples and unittests on the bot, if
>> precisely the purpose of the bot is to test the build? (*all* the build,
>> I guess)
>
> This is a clang tester, it slows it down. And the unittests don't
> build on msvc9 (they do in 10).

This is a pity, having a bot that ignores part of the build. Apart from
that, failed unittests are significant for clang, aren't they?

[snip]

>> Please explain in more detail what the problem is and maybe we can find
>> a better implementation.
>
> There are two options per group. LLVM_BUILD_X and LLVM_INCLUDE_X.
> LLVM_BUILD_X says that X should be built by ALL_BUILD, and
> LLVM_INCLUDE_X says that X should be included as a target that is
> available to be built. LLVM_BUILD_X must imply LLVM_INCLUDE_X, as you
> cannot build a target that doesn't exist.
>
> The problem is that I could not find a way to change the cache value
> of LLVM_INCLUDE_X displayed in ccache and cmake-gui to ON if
> LLVM_BUILD_X is ON. This would make it clearer to the user and make
> the code simpler.

[snip]

>> and is unnecessarily complex (why not
>>
>> if( LLVM_INCLUDE_X )
>> ?add_subdirectory(X)
>> endif()
>>
>> instead of changing add_llvm_X)
>
> I agree. However, it should be:
>
> if( LLVM_INCLUDE_X OR LLVM_BUILD_X )
>
> Because of the problem above.

What we could do is simply

if( LLVM_INCLUDE_TOOLS )
  add_subdirectory(tools)
endif()

and add to the documentation of LLVM_BUILD_TOOLS a note about it being
conditioned by LLVM_INCLUDE_TOOLS (both on the definition of the
variable and on the html file.) Likewise for EXAMPLES.

But all this may be irrelevant if the command "cmake --build ." works
for you as it works for me. In that case simply revert the commit and
you are done.

[snip]

>> Oh, and next time it would be a good idea to discuss the patch before
>> committing it.
>
> It didn't (well, wasn't supposed to) have any functionality changes,
> it's rather small, and it was needed to fix the build bot. Is this
> really too much for review after commit?

Well, you yourself were not satisfied with the change. That is a big
hint that others may share your opinion ;-) so describing the problem
and posting the patch for discussion is a good way of not creating
surprises and even achieving a better solution.


From grosbach at apple.com  Fri Sep 24 23:20:11 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Sep 2010 21:20:11 -0700
Subject: [llvm-commits] [llvm] r114781 -
	/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
In-Reply-To: <20100925005726.CBE142A6C12C@llvm.org>
References: <20100925005726.CBE142A6C12C@llvm.org>
Message-ID: <C4B23BF3-01D5-4AE9-A339-164E7B0CC082@apple.com>

Eesh. That's a nasty one. Nice fix.

re: the TODO, I suspect the answer is "maybe." Not sure off the top of my head how to accurately model the change in cost, though.

On Sep 24, 2010, at 5:57 PM, Eric Christopher wrote:

> Author: echristo
> Date: Fri Sep 24 19:57:26 2010
> New Revision: 114781
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114781&view=rev
> Log:
> If we're changing the source of a memcpy we need to use the alignment
> of the source, not the original alignment since it may no longer
> be valid.
> 
> Fixes rdar://8400094
> 
> Modified:
>    llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
> 
> Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=114781&r1=114780&r2=114781&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
> +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Fri Sep 24 19:57:26 2010
> @@ -697,14 +697,16 @@
>                                  M->getParent()->getParent()->getParent(),
>                                  M->getIntrinsicID(), ArgTys, 3);
> 
> +  // Make sure to use the alignment of the source since we're changing the
> +  // location we're reading from.
> +  // TODO: Is this worth it if we're creating a less aligned memcpy? For
> +  // example we could be moving from movaps -> movq on x86.
>   Value *Args[5] = {
>     M->getRawDest(), MDep->getRawSource(), M->getLength(),
> -    M->getAlignmentCst(), M->getVolatileCst()
> +    MDep->getAlignmentCst(), M->getVolatileCst()
>   };
> -  
>   CallInst *C = CallInst::Create(MemCpyFun, Args, Args+5, "", M);
> 
> -  
>   // If C and M don't interfere, then this is a valid transformation.  If they
>   // did, this would mean that the two sources overlap, which would be bad.
>   if (MD.getDependency(C) == dep) {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From bigcheesegs at gmail.com  Sat Sep 25 00:06:19 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Sat, 25 Sep 2010 01:06:19 -0400
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
In-Reply-To: <87bp7mjxqo.fsf@telefonica.net>
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
	<AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>
	<87bp7mjxqo.fsf@telefonica.net>
Message-ID: <AANLkTinc1=MVQUc=7YsKYipD=nupyYwQNpp6qvG-aguk@mail.gmail.com>

On Fri, Sep 24, 2010 at 11:41 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
> The following message is a courtesy copy of an article
> that has been posted to gmane.comp.compilers.llvm.cvs as well.
>
> Michael Spencer <bigcheesegs-Re5JQEeQqe8AvxtiuMwx3w at public.gmane.org>
> writes:
>
>> The only way to build (that we could find) clang from the command line
>> using VCBuild is to build the entire solution, which includes the
>> tools, examples, and tests no matter what. LLVM_BUILD_X only controls
>> if they are part of the ALL_BUILD target, and building ALL_BUILD
>> doesn't build anything with VCBuild.
>
> cmake --build .

This works for me (VS 2010), but on the build bot (VS 2008) it
attempts to run VCExpress instead of VCBuild, and it fails. I don't
really know much else as Daniel has everything setup.

> on the build directory works fine here, omitting the examples as
> required by the setting of LLVM_BUILD_EXAMPLES.
>
> And is it really important to build with VCBuild? NMake works fine and
> seems faster than VCBuild. And JOM allows parallel builds, in case the
> bot is a multicore machine.

VCBuild allows parallel builds with the -M switch.

> But if you want to speed-up the VS build you could investigate why
> tblgen is so slow on Windows. The time it takes to process the files
> associated to the X86 target is quite larger than the required for
> building the examples.

tblgen seems fast to me. Where exactly are you seeing these slowdowns?

>>> And why you don't want to build examples and unittests on the bot, if
>>> precisely the purpose of the bot is to test the build? (*all* the build,
>>> I guess)
>>
>> This is a clang tester, it slows it down. And the unittests don't
>> build on msvc9 (they do in 10).
>
> This is a pity, having a bot that ignores part of the build. Apart from
> that, failed unittests are significant for clang, aren't they?

The unit tests are the LLVM unit tests that I just added CMake support
for. MSVC 2008 fails to build them for some reason and I don't use
2008 so I can't really fix them.

> [snip]
>
>>> Please explain in more detail what the problem is and maybe we can find
>>> a better implementation.
>>
>> There are two options per group. LLVM_BUILD_X and LLVM_INCLUDE_X.
>> LLVM_BUILD_X says that X should be built by ALL_BUILD, and
>> LLVM_INCLUDE_X says that X should be included as a target that is
>> available to be built. LLVM_BUILD_X must imply LLVM_INCLUDE_X, as you
>> cannot build a target that doesn't exist.
>>
>> The problem is that I could not find a way to change the cache value
>> of LLVM_INCLUDE_X displayed in ccache and cmake-gui to ON if
>> LLVM_BUILD_X is ON. This would make it clearer to the user and make
>> the code simpler.
>
> [snip]
>
>>> and is unnecessarily complex (why not
>>>
>>> if( LLVM_INCLUDE_X )
>>> ?add_subdirectory(X)
>>> endif()
>>>
>>> instead of changing add_llvm_X)
>>
>> I agree. However, it should be:
>>
>> if( LLVM_INCLUDE_X OR LLVM_BUILD_X )
>>
>> Because of the problem above.
>
> What we could do is simply
>
> if( LLVM_INCLUDE_TOOLS )
> ?add_subdirectory(tools)
> endif()
>
> and add to the documentation of LLVM_BUILD_TOOLS a note about it being
> conditioned by LLVM_INCLUDE_TOOLS (both on the definition of the
> variable and on the html file.) Likewise for EXAMPLES.

Did you take a look at my patch? LLVM_INCLUDE_X should be conditioned
by LLVM_BUILD_X.

> But all this may be irrelevant if the command "cmake --build ." works
> for you as it works for me. In that case simply revert the commit and
> you are done.

I really would prefer this, but apparently the build bot doesn't like it :(.

> [snip]
>
>>> Oh, and next time it would be a good idea to discuss the patch before
>>> committing it.
>>
>> It didn't (well, wasn't supposed to) have any functionality changes,
>> it's rather small, and it was needed to fix the build bot. Is this
>> really too much for review after commit?
>
> Well, you yourself were not satisfied with the change. That is a big
> hint that others may share your opinion ;-) so describing the problem
> and posting the patch for discussion is a good way of not creating
> surprises and even achieving a better solution.
>


From resistor at mac.com  Sat Sep 25 00:26:18 2010
From: resistor at mac.com (Owen Anderson)
Date: Sat, 25 Sep 2010 05:26:18 -0000
Subject: [llvm-commits] [llvm] r114785 - in /llvm/trunk:
 lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/pre-single-pred.ll
Message-ID: <20100925052618.AF9562A6C12C@llvm.org>

Author: resistor
Date: Sat Sep 25 00:26:18 2010
New Revision: 114785

URL: http://llvm.org/viewvc/llvm-project?rev=114785&view=rev
Log:
LoadPRE was not properly checking that the load it was PRE'ing post-dominated the block it was being hoisted to.
Splitting critical edges at the merge point only addressed part of the issue; it is also possible for non-post-domination
to occur when the path from the load to the merge has branches in it.  Unfortunately, full anticipation analysis is
time-consuming, so for now approximate it.  This is strictly more conservative than real anticipation, so we will miss
some cases that real PRE would allow, but we also no longer insert loads into paths where they didn't exist before. :-)

This is a very slight net positive on SPEC for me (0.5% on average).  Most of the benchmarks are largely unaffected, but
when it pays off it pays off decently: 181.mcf improves by 4.5% on my machine.

Modified:
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/test/Transforms/GVN/pre-single-pred.ll

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=114785&r1=114784&r2=114785&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Sat Sep 25 00:26:18 2010
@@ -1532,8 +1532,14 @@
       return false;
     if (Blockers.count(TmpBB))
       return false;
+    
+    // If any of these blocks has more than one successor (i.e. if the edge we
+    // just traversed was critical), then there are other paths through this 
+    // block along which the load may not be anticipated.  Hoisting the load 
+    // above this block would be adding the load to execution paths along
+    // which it was not previously executed.
     if (TmpBB->getTerminator()->getNumSuccessors() != 1)
-      allSingleSucc = false;
+      return false;
   }
 
   assert(TmpBB);

Modified: llvm/trunk/test/Transforms/GVN/pre-single-pred.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/pre-single-pred.ll?rev=114785&r1=114784&r2=114785&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/GVN/pre-single-pred.ll (original)
+++ llvm/trunk/test/Transforms/GVN/pre-single-pred.ll Sat Sep 25 00:26:18 2010
@@ -1,4 +1,13 @@
-; RUN: opt < %s -gvn -enable-load-pre -S | not grep {tmp3 = load}
+; RUN: opt < %s -gvn -enable-load-pre -S | FileCheck %s
+; This testcase assumed we'll PRE the load into %for.cond, but we don't actually
+; verify that doing so is safe.  If there didn't _happen_ to be a load in
+; %for.end, we would actually be lengthening the execution on some paths, and
+; we were never actually checking that case.  Now we actually do perform some
+; conservative checking to make sure we don't make paths longer, but we don't
+; currently get this case, which we got lucky on previously.
+;
+; Now that that faulty assumption is corrected, test that we DON'T incorrectly
+; hoist the load.  Doing the right thing for the wrong reasons is still a bug.
 
 @p = external global i32
 define i32 @f(i32 %n) nounwind {
@@ -13,6 +22,8 @@
 for.cond.for.end_crit_edge:		; preds = %for.cond
 	br label %for.end
 
+; CHECK: for.body:
+; CHECK-NEXT: %tmp3 = load i32* @p
 for.body:		; preds = %for.cond
 	%tmp3 = load i32* @p		; <i32> [#uses=1]
 	%dec = add i32 %tmp3, -1		; <i32> [#uses=2]
@@ -20,6 +31,7 @@
 	%cmp6 = icmp slt i32 %dec, 0		; <i1> [#uses=1]
 	br i1 %cmp6, label %for.body.for.end_crit_edge, label %for.inc
 
+; CHECK: for.body.for.end_crit_edge:
 for.body.for.end_crit_edge:		; preds = %for.body
 	br label %for.end
 



From ofv at wanadoo.es  Sat Sep 25 00:33:18 2010
From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes)
Date: Sat, 25 Sep 2010 07:33:18 +0200
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
	cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
	utils/unittest/CMakeLists.txt
In-Reply-To: <AANLkTinc1=MVQUc=7YsKYipD=nupyYwQNpp6qvG-aguk@mail.gmail.com>
	(Michael Spencer's message of "Sat, 25 Sep 2010 01:06:19 -0400")
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
	<AANLkTik4rCZDcogtz7b_wU_mybDMwkEXX83rt2MVLGLL@mail.gmail.com>
	<87bp7mjxqo.fsf@telefonica.net>
	<AANLkTinc1=MVQUc=7YsKYipD=nupyYwQNpp6qvG-aguk@mail.gmail.com>
Message-ID: <8762xujskh.fsf@telefonica.net>

Michael Spencer <bigcheesegs at gmail.com> writes:

[snip]

>> But if you want to speed-up the VS build you could investigate why
>> tblgen is so slow on Windows. The time it takes to process the files
>> associated to the X86 target is quite larger than the required for
>> building the examples.
>
> tblgen seems fast to me. Where exactly are you seeing these slowdowns?

Well, just looking at the build output on the console. It took several
minutes to build the tablegen files for the X86 LLVM target. I'm using
VMWare, so there may be the problem.

[snip]

>> What we could do is simply
>>
>> if( LLVM_INCLUDE_TOOLS )
>> ?add_subdirectory(tools)
>> endif()
>>
>> and add to the documentation of LLVM_BUILD_TOOLS a note about it being
>> conditioned by LLVM_INCLUDE_TOOLS (both on the definition of the
>> variable and on the html file.) Likewise for EXAMPLES.
>
> Did you take a look at my patch? LLVM_INCLUDE_X should be conditioned
> by LLVM_BUILD_X.

LLVM_BUILD_X means "If ON, add the targets under X to the ALL target,
else keep them as standalone targets." Your LLVM_INCLUDE_X means "If ON,
process the CMakeLists.txt files under X, else ignore them." Obviously
it doesn't make sense to decide if X is added to ALL when its
CMakeLists.txt are being ignored. So setting LLVM_INCLUDE_X to OFF makes
the setting of LLVM_BUILD_X irrelevant.

>> But all this may be irrelevant if the command "cmake --build ." works
>> for you as it works for me. In that case simply revert the commit and
>> you are done.
>
> I really would prefer this, but apparently the build bot doesn't like it :(.

So using nmake/jom is not a feasible option?


From rafael.espindola at gmail.com  Sat Sep 25 00:42:19 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Sat, 25 Sep 2010 05:42:19 -0000
Subject: [llvm-commits] [llvm] r114786 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp lib/MC/MCELFStreamer.cpp
 lib/Target/X86/X86AsmBackend.cpp test/MC/ELF/basic-elf.ll
 test/MC/ELF/merge.s
Message-ID: <20100925054219.695ED2A6C12C@llvm.org>

Author: rafael
Date: Sat Sep 25 00:42:19 2010
New Revision: 114786

URL: http://llvm.org/viewvc/llvm-project?rev=114786&view=rev
Log:
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
symbols defined in merge sections in independent atoms.

Added:
    llvm/trunk/test/MC/ELF/merge.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/MCELFStreamer.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
    llvm/trunk/test/MC/ELF/basic-elf.ll

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=114786&r1=114785&r2=114786&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Sat Sep 25 00:42:19 2010
@@ -487,6 +487,13 @@
   }
 }
 
+static const MCSymbolData *getAtom(const MCSymbolData &SD) {
+  if (!SD.getFragment())
+    return 0;
+
+  return SD.getFragment()->getAtom();
+}
+
 // FIXME: this is currently X86/X86_64 only
 void ELFObjectWriterImpl::RecordRelocation(const MCAssembler &Asm,
                                            const MCAsmLayout &Layout,
@@ -502,7 +509,7 @@
   if (!Target.isAbsolute()) {
     const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
     MCSymbolData &SD = Asm.getSymbolData(*Symbol);
-    const MCSymbolData *Base = Asm.getAtom(Layout, &SD);
+    const MCSymbolData *Base = getAtom(SD);
     MCFragment *F = SD.getFragment();
 
     // Avoid relocations for cases like jumps and calls in the same file.
@@ -515,7 +522,7 @@
     }
 
     if (Base) {
-      if (F && !SD.isExternal()) {
+      if (Base != &SD) {
         Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1;
 
         MCSectionData *FSD = F->getParent();
@@ -523,8 +530,6 @@
         Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
       } else
         Index = getSymbolIndexInSymbolTable(Asm, Symbol);
-      if (Base != &SD)
-        Value += Layout.getSymbolAddress(&SD) - Layout.getSymbolAddress(Base);
       Addend = Value;
       // Compensate for the addend on i386.
       if (Is64Bit)
@@ -537,11 +542,14 @@
 
         MCSectionData *FSD = F->getParent();
         // Offset of the symbol in the section
-        Addend = Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
+        Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD);
       } else {
-        FixedValue = Value;
-        return;
+        Index = getSymbolIndexInSymbolTable(Asm, Symbol);
       }
+      Addend = Value;
+      // Compensate for the addend on i386.
+      if (Is64Bit)
+        Value = 0;
     }
   }
 

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=114786&r1=114785&r2=114786&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Sat Sep 25 00:42:19 2010
@@ -149,20 +149,43 @@
   SetSectionText();
 }
 
+static bool isSymbolLinkerVisible(const MCAssembler &Asm,
+                                  const MCSymbolData &Data) {
+  const MCSymbol &Symbol = Data.getSymbol();
+  // Absolute temporary labels are never visible.
+  if (!Symbol.isInSection())
+    return false;
+
+  if (Asm.getBackend().doesSectionRequireSymbols(Symbol.getSection()))
+    return true;
+
+  if (!Data.isExternal())
+    return false;
+
+  return Asm.isSymbolLinkerVisible(Symbol);
+}
+
 void MCELFStreamer::EmitLabel(MCSymbol *Symbol) {
   assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
 
+  Symbol->setSection(*CurSection);
+
+  MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
+
+  // We have to create a new fragment if this is an atom defining symbol,
+  // fragments cannot span atoms.
+  if (isSymbolLinkerVisible(getAssembler(), SD))
+    new MCDataFragment(getCurrentSectionData());
+
   // FIXME: This is wasteful, we don't necessarily need to create a data
   // fragment. Instead, we should mark the symbol as pointing into the data
   // fragment if it exists, otherwise we should just queue the label and set its
   // fragment pointer when we emit the next fragment.
   MCDataFragment *F = getOrCreateDataFragment();
-  MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
+
   assert(!SD.getFragment() && "Unexpected fragment on symbol data!");
   SD.setFragment(F);
   SD.setOffset(F->getContents().size());
-
-  Symbol->setSection(*CurSection);
 }
 
 void MCELFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) {
@@ -476,7 +499,37 @@
 }
 
 void MCELFStreamer::Finish() {
-  getAssembler().Finish();
+  // FIXME: We create more atoms than it is necessary. Some relocations to
+  // merge sections can be implemented with section address + offset,
+  // figure out which ones and why.
+
+  // First, scan the symbol table to build a lookup table from fragments to
+  // defining symbols.
+  DenseMap<const MCFragment*, MCSymbolData*> DefiningSymbolMap;
+  for (MCAssembler::symbol_iterator it = getAssembler().symbol_begin(),
+         ie = getAssembler().symbol_end(); it != ie; ++it) {
+    if (isSymbolLinkerVisible(getAssembler(), *it) &&
+        it->getFragment()) {
+      // An atom defining symbol should never be internal to a fragment.
+      assert(it->getOffset() == 0 && "Invalid offset in atom defining symbol!");
+      DefiningSymbolMap[it->getFragment()] = it;
+    }
+  }
+
+  // Set the fragment atom associations by tracking the last seen atom defining
+  // symbol.
+  for (MCAssembler::iterator it = getAssembler().begin(),
+         ie = getAssembler().end(); it != ie; ++it) {
+    MCSymbolData *CurrentAtom = 0;
+    for (MCSectionData::iterator it2 = it->begin(),
+           ie2 = it->end(); it2 != ie2; ++it2) {
+      if (MCSymbolData *SD = DefiningSymbolMap.lookup(it2))
+        CurrentAtom = SD;
+      it2->setAtom(CurrentAtom);
+    }
+  }
+
+  this->MCObjectStreamer::Finish();
 }
 
 MCStreamer *llvm::createELFStreamer(MCContext &Context, TargetAsmBackend &TAB,

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=114786&r1=114785&r2=114786&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Sat Sep 25 00:42:19 2010
@@ -191,6 +191,12 @@
     : X86AsmBackend(T), OSType(_OSType) {
     HasAbsolutizedSet = true;
     HasScatteredSymbols = true;
+    HasReliableSymbolDifference = true;
+  }
+
+  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
+    const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
+    return ES.getFlags() & MCSectionELF::SHF_MERGE;
   }
 
   bool isVirtualSection(const MCSection &Section) const {

Modified: llvm/trunk/test/MC/ELF/basic-elf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/basic-elf.ll?rev=114786&r1=114785&r2=114786&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/basic-elf.ll (original)
+++ llvm/trunk/test/MC/ELF/basic-elf.ll Sat Sep 25 00:42:19 2010
@@ -83,7 +83,7 @@
 ; 64:     # Relocation 2
 ; 64:     (('r_offset', 15)
 ; 64:      ('r_type', 10)
-; 64:      ('r_addend', 6)
+; 64:      ('r_addend', 0)
 ; 64:     ),
 ; 64:     # Relocation 3
 ; 64:     (('r_offset', 20)

Added: llvm/trunk/test/MC/ELF/merge.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/merge.s?rev=114786&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/merge.s (added)
+++ llvm/trunk/test/MC/ELF/merge.s Sat Sep 25 00:42:19 2010
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
+
+// Test that relocations with local symbols in a mergeable section are done
+// with a reference to the symbol. Not sure if this is a linker limitation,
+// but this matches the behavior of gas.
+
+        .section        .sec1,"aM", at progbits,16
+.Lfoo:
+        .text
+        movsd   .Lfoo(%rip), %xmm1
+
+// Relocation refers to symbol 1
+
+// CHECK:       ('_relocations', [
+// CHECK-NEXT:   # Relocation 0
+// CHECK-NEXT:   (('r_offset',
+// CHECK-NEXT:    ('r_sym', 1)
+// CHECK-NEXT:    ('r_type',
+// CHECK-NEXT:    ('r_addend',
+// CHECK-NEXT:   ),
+// CHECK-NEXT:  ])
+
+// Symbol number 1 is .Lfoo
+
+// CHECK:      # Symbol 1
+// CHECK-NEXT: (('st_name', 1) # '.Lfoo'



From clchiou at gmail.com  Sat Sep 25 02:02:31 2010
From: clchiou at gmail.com (Che-Liang Chiou)
Date: Sat, 25 Sep 2010 07:02:31 -0000
Subject: [llvm-commits] [llvm] r114787 -
	/llvm/trunk/include/llvm/CallingConv.h
Message-ID: <20100925070231.137F02A6C12C@llvm.org>

Author: clchiou
Date: Sat Sep 25 02:02:30 2010
New Revision: 114787

URL: http://llvm.org/viewvc/llvm-project?rev=114787&view=rev
Log:
Remove trailing spaces of CallingConv.h

Modified:
    llvm/trunk/include/llvm/CallingConv.h

Modified: llvm/trunk/include/llvm/CallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallingConv.h?rev=114787&r1=114786&r2=114787&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CallingConv.h (original)
+++ llvm/trunk/include/llvm/CallingConv.h Sat Sep 25 02:02:30 2010
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines LLVM's set of calling conventions. 
+// This file defines LLVM's set of calling conventions.
 //
 //===----------------------------------------------------------------------===//
 
@@ -20,21 +20,21 @@
 /// the well-known calling conventions.
 ///
 namespace CallingConv {
-  /// A set of enums which specify the assigned numeric values for known llvm 
+  /// A set of enums which specify the assigned numeric values for known llvm
   /// calling conventions.
   /// @brief LLVM Calling Convention Representation
   enum ID {
     /// C - The default llvm calling convention, compatible with C.  This
     /// convention is the only calling convention that supports varargs calls.
-    /// As with typical C calling conventions, the callee/caller have to 
+    /// As with typical C calling conventions, the callee/caller have to
     /// tolerate certain amounts of prototype mismatch.
     C = 0,
-    
+
     // Generic LLVM calling conventions.  None of these calling conventions
     // support varargs calls, and all assume that the caller and callee
     // prototype exactly match.
 
-    /// Fast - This calling convention attempts to make calls as fast as 
+    /// Fast - This calling convention attempts to make calls as fast as
     /// possible (e.g. by passing things in registers).
     Fast = 8,
 



From clchiou at gmail.com  Sat Sep 25 02:46:17 2010
From: clchiou at gmail.com (Che-Liang Chiou)
Date: Sat, 25 Sep 2010 07:46:17 -0000
Subject: [llvm-commits] [llvm] r114788 - in /llvm/trunk:
 include/llvm/CallingConv.h lib/AsmParser/LLLexer.cpp
 lib/AsmParser/LLParser.cpp lib/AsmParser/LLToken.h
 lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXISelLowering.h
 lib/Target/PTX/PTXInstrInfo.td lib/VMCore/AsmWriter.cpp
 lib/VMCore/Verifier.cpp test/CodeGen/PTX/exit.ll utils/vim/llvm.vim
Message-ID: <20100925074618.75BB92A6C12C@llvm.org>

Author: clchiou
Date: Sat Sep 25 02:46:17 2010
New Revision: 114788

URL: http://llvm.org/viewvc/llvm-project?rev=114788&view=rev
Log:
Add ret instruction to PTX backend

Modified:
    llvm/trunk/include/llvm/CallingConv.h
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.h
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp
    llvm/trunk/test/CodeGen/PTX/exit.ll
    llvm/trunk/utils/vim/llvm.vim

Modified: llvm/trunk/include/llvm/CallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallingConv.h?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CallingConv.h (original)
+++ llvm/trunk/include/llvm/CallingConv.h Sat Sep 25 02:46:17 2010
@@ -79,7 +79,15 @@
     /// X86_ThisCall - Similar to X86_StdCall. Passes first argument in ECX,
     /// others via stack. Callee is responsible for stack cleaning. MSVC uses
     /// this by default for methods in its ABI.
-    X86_ThisCall = 70
+    X86_ThisCall = 70,
+
+    /// PTX_Kernel - Call to a PTX kernel.
+    /// Passes all arguments in parameter space.
+    PTX_Kernel = 71,
+
+    /// PTX_Device - Call to a PTX device function.
+    /// Passes all arguments in register or parameter space.
+    PTX_Device = 72
   };
 } // End CallingConv namespace
 

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Sat Sep 25 02:46:17 2010
@@ -544,6 +544,8 @@
   KEYWORD(arm_aapcscc);
   KEYWORD(arm_aapcs_vfpcc);
   KEYWORD(msp430_intrcc);
+  KEYWORD(ptx_kernel);
+  KEYWORD(ptx_device);
 
   KEYWORD(cc);
   KEYWORD(c);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Sat Sep 25 02:46:17 2010
@@ -1084,6 +1084,8 @@
 ///   ::= 'arm_aapcscc'
 ///   ::= 'arm_aapcs_vfpcc'
 ///   ::= 'msp430_intrcc'
+///   ::= 'ptx_kernel'
+///   ::= 'ptx_device'
 ///   ::= 'cc' UINT
 ///
 bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
@@ -1099,6 +1101,8 @@
   case lltok::kw_arm_aapcscc:    CC = CallingConv::ARM_AAPCS; break;
   case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
   case lltok::kw_msp430_intrcc:  CC = CallingConv::MSP430_INTR; break;
+  case lltok::kw_ptx_kernel:     CC = CallingConv::PTX_Kernel; break;
+  case lltok::kw_ptx_device:     CC = CallingConv::PTX_Device; break;
   case lltok::kw_cc: {
       unsigned ArbitraryCC;
       Lex.Lex();

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Sat Sep 25 02:46:17 2010
@@ -72,6 +72,7 @@
     kw_x86_stdcallcc, kw_x86_fastcallcc, kw_x86_thiscallcc,
     kw_arm_apcscc, kw_arm_aapcscc, kw_arm_aapcs_vfpcc,
     kw_msp430_intrcc,
+    kw_ptx_kernel, kw_ptx_device,
 
     kw_signext,
     kw_zeroext,

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Sat Sep 25 02:46:17 2010
@@ -32,6 +32,7 @@
   switch (Opcode) {
     default:           llvm_unreachable("Unknown opcode");
     case PTXISD::EXIT: return "PTXISD::EXIT";
+    case PTXISD::RET:  return "PTXISD::RET";
   }
 }
 
@@ -58,5 +59,25 @@
               const SmallVectorImpl<SDValue> &OutVals,
               DebugLoc dl,
               SelectionDAG &DAG) const {
-  return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
+  assert(!isVarArg && "PTX does not support var args.");
+
+  switch (CallConv) {
+    default:
+      llvm_unreachable("Unsupported calling convention.");
+    case CallingConv::PTX_Kernel:
+      assert(Outs.size() == 0 && "Kernel must return void.");
+      return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
+    case CallingConv::PTX_Device:
+      assert(Outs.size() <= 1 && "Can at most return one value.");
+      break;
+  }
+
+  // PTX_Device
+
+  if (Outs.size() == 0)
+    return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
+
+  // TODO: allocate return register
+  SDValue Flag;
+  return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
 }

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.h?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.h Sat Sep 25 02:46:17 2010
@@ -24,7 +24,8 @@
 namespace PTXISD {
   enum NodeType {
     FIRST_NUMBER = ISD::BUILTIN_OP_END,
-    EXIT
+    EXIT,
+    RET
   };
 } // namespace PTXISD
 

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Sat Sep 25 02:46:17 2010
@@ -23,6 +23,8 @@
 
 def PTXexit
   : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
+def PTXret
+  : SDNode<"PTXISD::RET",  SDTNone, [SDNPHasChain]>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -30,4 +32,5 @@
 
 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
   def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
+  def RET  : InstPTX<(outs), (ins), "ret",  [(PTXret)]>;
 }

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Sat Sep 25 02:46:17 2010
@@ -1579,6 +1579,8 @@
   case CallingConv::ARM_AAPCS:    Out << "arm_aapcscc "; break;
   case CallingConv::ARM_AAPCS_VFP:Out << "arm_aapcs_vfpcc "; break;
   case CallingConv::MSP430_INTR:  Out << "msp430_intrcc "; break;
+  case CallingConv::PTX_Kernel:   Out << "ptx_kernel"; break;
+  case CallingConv::PTX_Device:   Out << "ptx_device"; break;
   default: Out << "cc" << F->getCallingConv() << " "; break;
   }
 
@@ -1847,6 +1849,8 @@
     case CallingConv::ARM_AAPCS:    Out << " arm_aapcscc "; break;
     case CallingConv::ARM_AAPCS_VFP:Out << " arm_aapcs_vfpcc "; break;
     case CallingConv::MSP430_INTR:  Out << " msp430_intrcc "; break;
+    case CallingConv::PTX_Kernel:   Out << " ptx_kernel"; break;
+    case CallingConv::PTX_Device:   Out << " ptx_device"; break;
     default: Out << " cc" << CI->getCallingConv(); break;
     }
 
@@ -1901,6 +1905,8 @@
     case CallingConv::ARM_AAPCS:    Out << " arm_aapcscc "; break;
     case CallingConv::ARM_AAPCS_VFP:Out << " arm_aapcs_vfpcc "; break;
     case CallingConv::MSP430_INTR:  Out << " msp430_intrcc "; break;
+    case CallingConv::PTX_Kernel:   Out << " ptx_kernel"; break;
+    case CallingConv::PTX_Device:   Out << " ptx_device"; break;
     default: Out << " cc" << II->getCallingConv(); break;
     }
 

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Sat Sep 25 02:46:17 2010
@@ -685,6 +685,8 @@
   case CallingConv::Cold:
   case CallingConv::X86_FastCall:
   case CallingConv::X86_ThisCall:
+  case CallingConv::PTX_Kernel:
+  case CallingConv::PTX_Device:
     Assert1(!F.isVarArg(),
             "Varargs functions must have C calling conventions!", &F);
     break;

Modified: llvm/trunk/test/CodeGen/PTX/exit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/exit.ll?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/exit.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/exit.ll Sat Sep 25 02:46:17 2010
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=ptx | FileCheck %s
 
-define void @t1() {
+define ptx_kernel void @t1() {
 ;CHECK: exit;
 	ret void
 }

Modified: llvm/trunk/utils/vim/llvm.vim
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/vim/llvm.vim?rev=114788&r1=114787&r2=114788&view=diff
==============================================================================
--- llvm/trunk/utils/vim/llvm.vim (original)
+++ llvm/trunk/utils/vim/llvm.vim Sat Sep 25 02:46:17 2010
@@ -49,6 +49,7 @@
 syn keyword llvmKeyword except deplibs
 syn keyword llvmKeyword volatile fastcc coldcc cc ccc
 syn keyword llvmKeyword x86_stdcallcc x86_fastcallcc
+syn keyword llvmKeyword ptx_kernel ptx_device
 syn keyword llvmKeyword signext zeroext inreg sret nounwind noreturn
 syn keyword llvmKeyword nocapture byval nest readnone readonly noalias
 syn keyword llvmKeyword inlinehint noinline alwaysinline optsize ssp sspreq



From clchiou at gmail.com  Sat Sep 25 02:49:54 2010
From: clchiou at gmail.com (Che-Liang Chiou)
Date: Sat, 25 Sep 2010 07:49:54 -0000
Subject: [llvm-commits] [llvm] r114789 - /llvm/trunk/test/CodeGen/PTX/ret.ll
Message-ID: <20100925074954.3771D2A6C12C@llvm.org>

Author: clchiou
Date: Sat Sep 25 02:49:54 2010
New Revision: 114789

URL: http://llvm.org/viewvc/llvm-project?rev=114789&view=rev
Log:
Add test case for PTX ret instruction

Added:
    llvm/trunk/test/CodeGen/PTX/ret.ll

Added: llvm/trunk/test/CodeGen/PTX/ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ret.ll?rev=114789&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/ret.ll (added)
+++ llvm/trunk/test/CodeGen/PTX/ret.ll Sat Sep 25 02:49:54 2010
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=ptx | FileCheck %s
+
+define ptx_device void @t1() {
+;CHECK: ret;
+	ret void
+}



From pichet2000 at gmail.com  Sat Sep 25 05:09:51 2010
From: pichet2000 at gmail.com (Francois Pichet)
Date: Sat, 25 Sep 2010 06:09:51 -0400
Subject: [llvm-commits] [llvm] r114747 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
In-Reply-To: <87sk0ykj1m.fsf@telefonica.net>
References: <20100924191051.A24F42A6C12C@llvm.org>
	<AANLkTinmar-Yp0DhvSM-1TGxBmcUT8LX9CTcbBmwu6GR@mail.gmail.com>
	<87sk0ykj1m.fsf@telefonica.net>
Message-ID: <AANLkTi=m_H-sBs3BVXTAGC5KjtR4+3hYa5v48Jw3jP-B@mail.gmail.com>

On Fri, Sep 24, 2010 at 4:01 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
> Michael Spencer <bigcheesegs at gmail.com>
> writes:
>
>> This was requested for the msvc build bot as building ALL_BUILD from
>> VSBuild doesn't build anything and we needed to disable building
>> unittests and examples.
>
> I don't understand this. So if the cmake invocation contains
> -DLLVM_BUILD_EXAMPLES=OFF this is a problem?
>
> And why you don't want to build examples and unittests on the bot, if
> precisely the purpose of the bot is to test the build? (*all* the build,
> I guess)

+ for removing the examples from the solution. Even if they are not
build as part of "ALL_BUILD", they still appear in the solution pane
(with 123 projects, any non essential projects is good to remove).They
get in the way. For example, if I want to debug clang, MSVC will tell
me that not all targets are up to date even if clang doesn't need them
to run. I like all my targets to be up to date even if ALL_TARGET do
not depend of them.


From lhames at gmail.com  Sat Sep 25 07:04:16 2010
From: lhames at gmail.com (Lang Hames)
Date: Sat, 25 Sep 2010 12:04:16 -0000
Subject: [llvm-commits] [llvm] r114791 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/InlineSpiller.cpp
 lib/CodeGen/LiveInterval.cpp lib/CodeGen/LiveIntervalAnalysis.cpp
 lib/CodeGen/PreAllocSplitting.cpp lib/CodeGen/RegAllocLinearScan.cpp
 lib/CodeGen/RegAllocPBQP.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp
 lib/CodeGen/Spiller.cpp lib/CodeGen/SplitKit.cpp lib/CodeGen/Splitter.cpp
Message-ID: <20100925120416.D10022A6C12C@llvm.org>

Author: lhames
Date: Sat Sep 25 07:04:16 2010
New Revision: 114791

URL: http://llvm.org/viewvc/llvm-project?rev=114791&view=rev
Log:
Removed VNInfo::isDefAccurate(). Def "accuracy" can be checked by testing whether LiveIntervals::getInstructionFromIndex(def) returns NULL.


Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
    llvm/trunk/lib/CodeGen/LiveInterval.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
    llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/Spiller.cpp
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/Splitter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Sat Sep 25 07:04:16 2010
@@ -39,25 +39,13 @@
   /// This class holds information about a machine level values, including
   /// definition and use points.
   ///
-  /// Care must be taken in interpreting the def index of the value. The
-  /// following rules apply:
-  ///
-  /// If the isDefAccurate() method returns false then def does not contain the
-  /// index of the defining MachineInstr, or even (necessarily) to a
-  /// MachineInstr at all. In general such a def index is not meaningful
-  /// and should not be used. The exception is that, for values originally
-  /// defined by PHI instructions, after PHI elimination def will contain the
-  /// index of the MBB in which the PHI originally existed. This can be used
-  /// to insert code (spills or copies) which deals with the value, which will
-  /// be live in to the block.
   class VNInfo {
   private:
     enum {
       HAS_PHI_KILL    = 1,
       REDEF_BY_EC     = 1 << 1,
       IS_PHI_DEF      = 1 << 2,
-      IS_UNUSED       = 1 << 3,
-      IS_DEF_ACCURATE = 1 << 4
+      IS_UNUSED       = 1 << 3
     };
 
     MachineInstr *copy;
@@ -73,10 +61,8 @@
     SlotIndex def;
 
     /// VNInfo constructor.
-    /// d is presumed to point to the actual defining instr. If it doesn't
-    /// setIsDefAccurate(false) should be called after construction.
     VNInfo(unsigned i, SlotIndex d, MachineInstr *c)
-      : copy(c), flags(IS_DEF_ACCURATE), id(i), def(d)
+      : copy(c), flags(0), id(i), def(d)
     { }
 
     /// VNInfo construtor, copies values from orig, except for the value number.
@@ -145,16 +131,6 @@
       else
         flags &= ~IS_UNUSED;
     }
-
-    /// Returns true if the def is accurate.
-    bool isDefAccurate() const { return flags & IS_DEF_ACCURATE; }
-    /// Set the "is def accurate" flag on this value.
-    void setIsDefAccurate(bool defAccurate) {
-      if (defAccurate)
-        flags |= IS_DEF_ACCURATE;
-      else
-        flags &= ~IS_DEF_ACCURATE;
-    }
   };
 
   /// LiveRange structure - This represents a simple register range in the
@@ -320,10 +296,9 @@
     /// getNextValue - Create a new value number and return it.  MIIdx specifies
     /// the instruction that defines the value number.
     VNInfo *getNextValue(SlotIndex def, MachineInstr *CopyMI,
-                       bool isDefAccurate, VNInfo::Allocator &VNInfoAllocator) {
+                         VNInfo::Allocator &VNInfoAllocator) {
       VNInfo *VNI =
         new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def, CopyMI);
-      VNI->setIsDefAccurate(isDefAccurate);
       valnos.push_back(VNI);
       return VNI;
     }

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Sat Sep 25 07:04:16 2010
@@ -233,8 +233,7 @@
   }
   DEBUG(dbgs() << "\t        " << UseIdx << '\t' << *MI);
 
-  VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
-                                       lis_.getVNInfoAllocator());
+  VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, lis_.getVNInfoAllocator());
   NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
   DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
   return true;
@@ -249,7 +248,7 @@
   for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
        E = li_->vni_end(); I != E; ++I) {
     VNInfo *VNI = *I;
-    if (VNI->isUnused() || !VNI->isDefAccurate())
+    if (VNI->isUnused())
       continue;
     MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
     if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
@@ -283,7 +282,7 @@
     lis_.RemoveMachineInstrFromMaps(DefMI);
     vrm_.RemoveMachineInstrFromMaps(DefMI);
     DefMI->eraseFromParent();
-    VNI->setIsDefAccurate(false);
+    VNI->def = lis_.getZeroIndex();
     anyRemoved = true;
   }
 
@@ -366,7 +365,7 @@
   SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
   vrm_.addSpillSlotUse(stackSlot_, MI);
   DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MI);
-  VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
+  VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
                                        lis_.getVNInfoAllocator());
   NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
 }
@@ -381,8 +380,7 @@
   SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
   vrm_.addSpillSlotUse(stackSlot_, MI);
   DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
-  VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
-                                        lis_.getVNInfoAllocator());
+  VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, lis_.getVNInfoAllocator());
   NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
 }
 

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Sat Sep 25 07:04:16 2010
@@ -678,10 +678,7 @@
       if (vni->isUnused()) {
         OS << "x";
       } else {
-        if (!vni->isDefAccurate() && !vni->isPHIDef())
-          OS << "?";
-        else
-          OS << vni->def;
+        OS << vni->def;
         if (vni->hasPHIKill())
           OS << "-phikill";
         if (vni->hasRedefByEC())

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sat Sep 25 07:04:16 2010
@@ -285,8 +285,8 @@
   SlotIndex RedefIndex = MIIdx.getDefIndex();
   const LiveRange *OldLR =
     interval.getLiveRangeContaining(RedefIndex.getUseIndex());
-  if (OldLR->valno->isDefAccurate()) {
-    MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
+  MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
+  if (DefMI != 0) {
     return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
   }
   return false;
@@ -326,8 +326,7 @@
       CopyMI = mi;
     }
 
-    VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, true,
-                                          VNInfoAllocator);
+    VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
     assert(ValNo->id == 0 && "First value in interval is not 0?");
 
     // Loop over all of the blocks that the vreg is defined in.  There are
@@ -393,7 +392,9 @@
       // Create interval with one of a NEW value number.  Note that this value
       // number isn't actually defined by an instruction, weird huh? :)
       if (PHIJoin) {
-        ValNo = interval.getNextValue(Start, 0, false, VNInfoAllocator);
+        assert(getInstructionFromIndex(Start) == 0 &&
+               "PHI def index points at actual instruction.");
+        ValNo = interval.getNextValue(Start, 0, VNInfoAllocator);
         ValNo->setIsPHIDef(true);
       }
       LiveRange LR(Start, killIdx, ValNo);
@@ -439,10 +440,7 @@
 
       // The new value number (#1) is defined by the instruction we claimed
       // defined value #0.
-      VNInfo *ValNo = interval.getNextValue(OldValNo->def, OldValNo->getCopy(),
-                                            false, // update at *
-                                            VNInfoAllocator);
-      ValNo->setFlags(OldValNo->getFlags()); // * <- updating here
+      VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
 
       // Value#0 is now defined by the 2-addr instruction.
       OldValNo->def  = RedefIndex;
@@ -480,7 +478,7 @@
       MachineInstr *CopyMI = NULL;
       if (mi->isCopyLike())
         CopyMI = mi;
-      ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
+      ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
 
       SlotIndex killIndex = getMBBEndIdx(mbb);
       LiveRange LR(defIndex, killIndex, ValNo);
@@ -575,7 +573,7 @@
   LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
   bool Extend = OldLR != interval.end();
   VNInfo *ValNo = Extend
-    ? OldLR->valno : interval.getNextValue(start, CopyMI, true, VNInfoAllocator);
+    ? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator);
   if (MO.isEarlyClobber() && Extend)
     ValNo->setHasRedefByEC(true);
   LiveRange LR(start, end, ValNo);
@@ -671,8 +669,11 @@
     }
   }
 
+  SlotIndex defIdx = getMBBStartIdx(MBB);
+  assert(getInstructionFromIndex(defIdx) == 0 &&
+         "PHI def index points at actual instruction.");
   VNInfo *vni =
-    interval.getNextValue(getMBBStartIdx(MBB), 0, false, VNInfoAllocator);
+    interval.getNextValue(defIdx, 0, VNInfoAllocator);
   vni->setIsPHIDef(true);
   LiveRange LR(start, end, vni);
 
@@ -863,9 +864,9 @@
     if (VNI->isUnused())
       continue; // Dead val#.
     // Is the def for the val# rematerializable?
-    if (!VNI->isDefAccurate())
-      return false;
     MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
+    if (!ReMatDefMI)
+      return false;
     bool DefIsLoad = false;
     if (!ReMatDefMI ||
         !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
@@ -1188,7 +1189,7 @@
     if (HasUse) {
       if (CreatedNewVReg) {
         LiveRange LR(index.getLoadIndex(), index.getDefIndex(),
-                     nI.getNextValue(SlotIndex(), 0, false, VNInfoAllocator));
+                     nI.getNextValue(SlotIndex(), 0, VNInfoAllocator));
         DEBUG(dbgs() << " +" << LR);
         nI.addRange(LR);
       } else {
@@ -1202,7 +1203,7 @@
     }
     if (HasDef) {
       LiveRange LR(index.getDefIndex(), index.getStoreIndex(),
-                   nI.getNextValue(SlotIndex(), 0, false, VNInfoAllocator));
+                   nI.getNextValue(SlotIndex(), 0, VNInfoAllocator));
       DEBUG(dbgs() << " +" << LR);
       nI.addRange(LR);
     }
@@ -1651,8 +1652,7 @@
     if (VNI->isUnused())
       continue; // Dead val#.
     // Is the def for the val# rematerializable?
-    MachineInstr *ReMatDefMI = VNI->isDefAccurate()
-      ? getInstructionFromIndex(VNI->def) : 0;
+    MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
     bool dummy;
     if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, SpillIs, dummy)) {
       // Remember how to remat the def of this val#.
@@ -1994,7 +1994,7 @@
   LiveInterval& Interval = getOrCreateInterval(reg);
   VNInfo* VN = Interval.getNextValue(
     SlotIndex(getInstructionIndex(startInst).getDefIndex()),
-    startInst, true, getVNInfoAllocator());
+    startInst, getVNInfoAllocator());
   VN->setHasPHIKill(true);
   LiveRange LR(
      SlotIndex(getInstructionIndex(startInst).getDefIndex()),

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Sat Sep 25 07:04:16 2010
@@ -324,7 +324,7 @@
   if (CurrSLI->hasAtLeastOneValue())
     CurrSValNo = CurrSLI->getValNumInfo(0);
   else
-    CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0, false,
+    CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0,
                                        LSs->getVNInfoAllocator());
   return SS;
 }
@@ -585,7 +585,7 @@
 
   SlotIndex StartIndex = LIs->getMBBStartIdx(MBB);
   VNInfo *RetVNI = Phis[MBB] =
-    LI->getNextValue(SlotIndex(), /*FIXME*/ 0, false,
+    LI->getNextValue(SlotIndex(), /*FIXME*/ 0,
                      LIs->getVNInfoAllocator());
 
   if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
@@ -674,7 +674,7 @@
     DefIdx = DefIdx.getDefIndex();
     
     assert(!DI->isPHI() && "PHI instr in code during pre-alloc splitting.");
-    VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
+    VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc);
     
     // If the def is a move, set the copy field.
     if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
@@ -807,7 +807,8 @@
   MachineBasicBlock& MBB = *RestorePt->getParent();
   
   MachineBasicBlock::iterator KillPt = BarrierMBB->end();
-  if (!ValNo->isDefAccurate() || DefMI->getParent() == BarrierMBB)
+  if (LIs->getInstructionFromIndex(ValNo->def) == 0 ||
+      DefMI->getParent() == BarrierMBB)
     KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB);
   else
     KillPt = llvm::next(MachineBasicBlock::iterator(DefMI));
@@ -872,7 +873,7 @@
     if (CurrSLI->hasAtLeastOneValue())
       CurrSValNo = CurrSLI->getValNumInfo(0);
     else
-      CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0, false,
+      CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0,
                                          LSs->getVNInfoAllocator());
   }
   
@@ -967,8 +968,7 @@
 
   assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
 
-  MachineInstr *DefMI = ValNo->isDefAccurate()
-    ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
+  MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
 
   // If this would create a new join point, do not split.
   if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent())) {
@@ -1005,7 +1005,7 @@
   SlotIndex SpillIndex;
   MachineInstr *SpillMI = NULL;
   int SS = -1;
-  if (!ValNo->isDefAccurate()) {
+  if (LIs->getInstructionFromIndex(ValNo->def) == 0) {
     // If we don't know where the def is we must split just before the barrier.
     if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
                             BarrierMBB, SS, RefsInMBB))) {
@@ -1199,12 +1199,12 @@
       
       // We also don't try to handle the results of PHI joins, since there's
       // no defining instruction to analyze.
-      if (!CurrVN->isDefAccurate() || CurrVN->isUnused()) continue;
+      MachineInstr* DefMI = LIs->getInstructionFromIndex(CurrVN->def);
+      if (!DefMI || CurrVN->isUnused()) continue;
     
       // We're only interested in eliminating cruft introduced by the splitter,
       // is of the form load-use or load-use-store.  First, check that the
       // definition is a load, and remember what stack slot we loaded it from.
-      MachineInstr* DefMI = LIs->getInstructionFromIndex(CurrVN->def);
       int FrameIndex;
       if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
       

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Sat Sep 25 07:04:16 2010
@@ -431,8 +431,7 @@
   unsigned CandReg;
   {
     MachineInstr *CopyMI;
-    if (vni->def != SlotIndex() && vni->isDefAccurate() &&
-        (CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
+    if ((CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
       // Defined by a copy, try to extend SrcReg forward
       CandReg = CopyMI->getOperand(1).getReg();
     else if (TrivCoalesceEnds &&
@@ -800,7 +799,7 @@
   if (SI.hasAtLeastOneValue())
     VNI = SI.getValNumInfo(0);
   else
-    VNI = SI.getNextValue(SlotIndex(), 0, false,
+    VNI = SI.getNextValue(SlotIndex(), 0,
                           ls_->getVNInfoAllocator());
 
   LiveInterval &RI = li_->getInterval(cur->reg);
@@ -984,8 +983,7 @@
   // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
   if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
     VNInfo *vni = cur->begin()->valno;
-    if ((vni->def != SlotIndex()) && !vni->isUnused() &&
-         vni->isDefAccurate()) {
+    if (!vni->isUnused()) {
       MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
       if (CopyMI && CopyMI->isCopy()) {
         unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();

Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sat Sep 25 07:04:16 2010
@@ -1014,7 +1014,7 @@
     vni = stackInterval.getValNumInfo(0);
   else
     vni = stackInterval.getNextValue(
-      SlotIndex(), 0, false, lss->getVNInfoAllocator());
+      SlotIndex(), 0, lss->getVNInfoAllocator());
 
   LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
   stackInterval.MergeRangesInAsValue(rhsInterval, vni);

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Sep 25 07:04:16 2010
@@ -218,7 +218,7 @@
         continue;
       LiveInterval &SRLI = li_->getInterval(*SR);
       SRLI.addRange(LiveRange(FillerStart, FillerEnd,
-                              SRLI.getNextValue(FillerStart, 0, true,
+                              SRLI.getNextValue(FillerStart, 0,
                                                 li_->getVNInfoAllocator())));
     }
   }
@@ -267,7 +267,8 @@
       if (BI->valno == BValNo)
         continue;
       // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
-      if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
+      if (!BValNo && li_->getInstructionFromIndex(BI->valno->def) == 0 &&
+          !BI->valno->getCopy())
         continue;
       if (BI->start <= AI->start && BI->end > AI->start)
         return true;
@@ -351,12 +352,11 @@
   assert(ALR != IntA.end() && "Live range not found!");
   VNInfo *AValNo = ALR->valno;
   // If other defs can reach uses of this def, then it's not safe to perform
-  // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
-  // tested?
-  if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
-      AValNo->isUnused() || AValNo->hasPHIKill())
-    return false;
+  // the optimization.
   MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
+  if (AValNo->isPHIDef() || DefMI == 0 || AValNo->isUnused() ||
+      AValNo->hasPHIKill())
+    return false;
   if (!DefMI)
     return false;
   const TargetInstrDesc &TID = DefMI->getDesc();
@@ -652,9 +652,8 @@
   assert(SrcLR != SrcInt.end() && "Live range not found!");
   VNInfo *ValNo = SrcLR->valno;
   // If other defs can reach uses of this def, then it's not safe to perform
-  // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
-  // tested?
-  if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
+  // the optimization.
+  if (ValNo->isPHIDef() || li_->getInstructionFromIndex(ValNo->def)==0 ||
       ValNo->isUnused() || ValNo->hasPHIKill())
     return false;
   MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Sat Sep 25 07:04:16 2010
@@ -144,7 +144,7 @@
         vrm->addSpillSlotUse(ss, loadInstr);
         SlotIndex endIndex = loadIndex.getNextIndex();
         VNInfo *loadVNI =
-          newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
+          newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
         newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
       }
 
@@ -158,7 +158,7 @@
         vrm->addSpillSlotUse(ss, storeInstr);
         SlotIndex beginIndex = storeIndex.getPrevIndex();
         VNInfo *storeVNI =
-          newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
+          newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());
         newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
       }
 
@@ -297,7 +297,8 @@
 
   /// Extract the given value number from the interval.
   LiveInterval* extractVNI(LiveInterval *li, VNInfo *vni) const {
-    assert(vni->isDefAccurate() || vni->isPHIDef());
+    assert((lis->getInstructionFromIndex(vni->def) != 0 || vni->isPHIDef()) &&
+           "Def index not sane?");
 
     // Create a new vreg and live interval, copy VNI ranges over.
     const TargetRegisterClass *trc = mri->getRegClass(li->reg);
@@ -335,8 +336,11 @@
                                      tii->get(TargetOpcode::COPY), newVReg)
                                .addReg(li->reg, RegState::Kill);
       SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
-      VNInfo *phiDefVNI = li->getNextValue(lis->getMBBStartIdx(defMBB),
-                                           0, false, lis->getVNInfoAllocator());
+      SlotIndex phiDefIdx = lis->getMBBStartIdx(defMBB);
+      assert(lis->getInstructionFromIndex(phiDefIdx) == 0 &&
+             "PHI def index points at actual instruction.");
+      VNInfo *phiDefVNI = li->getNextValue(phiDefIdx,
+                                           0, lis->getVNInfoAllocator());
       phiDefVNI->setIsPHIDef(true);
       li->addRange(LiveRange(phiDefVNI->def, copyIdx.getDefIndex(), phiDefVNI));
       LiveRange *oldPHIDefRange =
@@ -358,7 +362,6 @@
       newVNI->def = copyIdx.getDefIndex();
       newVNI->setCopy(copyMI);
       newVNI->setIsPHIDef(false); // not a PHI def anymore.
-      newVNI->setIsDefAccurate(true);
     } else {
       // non-PHI def. Rename the def. If it's two-addr that means renaming the
       // use and inserting a new copy too.
@@ -391,7 +394,7 @@
           li->getLiveRangeContaining(newVNI->def.getUseIndex());
         origUseRange->end = copyIdx.getDefIndex();
         VNInfo *copyVNI = newLI->getNextValue(copyIdx.getDefIndex(), copyMI,
-                                              true, lis->getVNInfoAllocator());
+                                              lis->getVNInfoAllocator());
         LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
         newLI->addRange(copyRange);
       }
@@ -448,7 +451,7 @@
         // Insert a new range & vni for the two-address-to-copy value. This
         // will be attached to the new live interval.
         VNInfo *copyVNI =
-          newLI->getNextValue(useIdx.getDefIndex(), 0, true,
+          newLI->getNextValue(useIdx.getDefIndex(), 0,
                               lis->getVNInfoAllocator());
         LiveRange copyRange(useIdx.getDefIndex(),copyIdx.getDefIndex(),copyVNI);
         newLI->addRange(copyRange);
@@ -481,8 +484,7 @@
       }
 
       VNInfo *newKillVNI = li->getNextValue(copyIdx.getDefIndex(),
-                                            copyMI, true,
-                                            lis->getVNInfoAllocator());
+                                            copyMI, lis->getVNInfoAllocator());
       newKillVNI->setHasPHIKill(true);
       li->addRange(LiveRange(copyIdx.getDefIndex(),
                              lis->getMBBEndIdx(killMBB),

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Sat Sep 25 07:04:16 2010
@@ -365,7 +365,7 @@
   assert(parentli_.getVNInfoAt(Idx) == ParentVNI && "Bad ParentVNI");
 
   // Create a new value.
-  VNInfo *VNI = li_->getNextValue(Idx, 0, true, lis_.getVNInfoAllocator());
+  VNInfo *VNI = li_->getNextValue(Idx, 0, lis_.getVNInfoAllocator());
 
   // Use insert for lookup, so we can add missing values with a second lookup.
   std::pair<ValueMap::iterator,bool> InsP =
@@ -468,7 +468,7 @@
 
       // We have a collision between the old and new VNI at Succ. That means
       // neither dominates and we need a new phi-def.
-      VNI = li_->getNextValue(Start, 0, true, lis_.getVNInfoAllocator());
+      VNI = li_->getNextValue(Start, 0, lis_.getVNInfoAllocator());
       VNI->setIsPHIDef(true);
       InsP.first->second = VNI;
 

Modified: llvm/trunk/lib/CodeGen/Splitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.cpp?rev=114791&r1=114790&r2=114791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Splitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/Splitter.cpp Sat Sep 25 07:04:16 2010
@@ -140,7 +140,6 @@
       VNInfo *newVal = getNewVNI(preHeaderRange->valno);
       newVal->def = copyDefIdx;
       newVal->setCopy(copy);
-      newVal->setIsDefAccurate(true);
       li.removeRange(copyDefIdx, ls.lis->getMBBEndIdx(preHeader), true);
 
       getNewLI()->addRange(LiveRange(copyDefIdx,
@@ -174,12 +173,13 @@
         
         // Blow away output range definition.
         outRange->valno->def = ls.lis->getInvalidIndex();
-        outRange->valno->setIsDefAccurate(false);
         li.removeRange(ls.lis->getMBBStartIdx(outBlock), copyDefIdx);
 
+        SlotIndex newDefIdx = ls.lis->getMBBStartIdx(outBlock);
+        assert(ls.lis->getInstructionFromIndex(newDefIdx) == 0 &&
+               "PHI def index points at actual instruction.");
         VNInfo *newVal =
-          getNewLI()->getNextValue(ls.lis->getMBBStartIdx(outBlock),
-                                   0, false, ls.lis->getVNInfoAllocator());
+          getNewLI()->getNextValue(newDefIdx, 0, ls.lis->getVNInfoAllocator());
 
         getNewLI()->addRange(LiveRange(ls.lis->getMBBStartIdx(outBlock),
                                        copyDefIdx, newVal));
@@ -513,8 +513,10 @@
       if (!insertRange)
         continue;
 
-      VNInfo *newVal = li.getNextValue(lis->getMBBStartIdx(preHeader),
-                                       0, false, lis->getVNInfoAllocator());
+      SlotIndex newDefIdx = lis->getMBBStartIdx(preHeader);
+      assert(lis->getInstructionFromIndex(newDefIdx) == 0 &&
+             "PHI def index points at actual instruction.");
+      VNInfo *newVal = li.getNextValue(newDefIdx, 0, lis->getVNInfoAllocator());
       li.addRange(LiveRange(lis->getMBBStartIdx(preHeader),
                             lis->getMBBEndIdx(preHeader),
                             newVal));
@@ -611,8 +613,11 @@
                          lis->getMBBEndIdx(splitBlock), true);
         }
       } else if (intersects) {
-        VNInfo *newVal = li.getNextValue(lis->getMBBStartIdx(splitBlock),
-                                         0, false, lis->getVNInfoAllocator());
+        SlotIndex newDefIdx = lis->getMBBStartIdx(splitBlock);
+        assert(lis->getInstructionFromIndex(newDefIdx) == 0 &&
+               "PHI def index points at actual instruction.");
+        VNInfo *newVal = li.getNextValue(newDefIdx, 0,
+                                         lis->getVNInfoAllocator());
         li.addRange(LiveRange(lis->getMBBStartIdx(splitBlock),
                               lis->getMBBEndIdx(splitBlock),
                               newVal));



From sabre at nondot.org  Sat Sep 25 10:53:35 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sat, 25 Sep 2010 15:53:35 -0000
Subject: [llvm-commits] [llvm] r114792 -
	/llvm/trunk/docs/DeveloperPolicy.html
Message-ID: <20100925155335.B2BB02A6C12C@llvm.org>

Author: lattner
Date: Sat Sep 25 10:53:35 2010
New Revision: 114792

URL: http://llvm.org/viewvc/llvm-project?rev=114792&view=rev
Log:
temporarily revert developer policy change as a courtesy to vikram.

Modified:
    llvm/trunk/docs/DeveloperPolicy.html

Modified: llvm/trunk/docs/DeveloperPolicy.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/DeveloperPolicy.html?rev=114792&r1=114791&r2=114792&view=diff
==============================================================================
--- llvm/trunk/docs/DeveloperPolicy.html (original)
+++ llvm/trunk/docs/DeveloperPolicy.html Sat Sep 25 10:53:35 2010
@@ -509,24 +509,20 @@
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsection"><a name="copyright">Copyright</a></div>
 <div class="doc_text">
-
-<p>The LLVM project does not require copyright assignments, which means that the
-   copyright for the code in the project is held by its respective contributors
-   who have each agreed to release their contributed code under the terms of the
-   <a href="#license">LLVM License</a>.</p>
-   
-<p>An implication of this is that the LLVM license is unlikely to ever change:
-   changing it would require tracking down all the contributors to LLVM and
-   getting them to agree that a license change is acceptable for their
-   contribution.  Since there are no plans to change the license, this is not a
-   cause for concern.</p>
-   
-<p>As a contributor to the project, this means that you (or your company) retain
-   ownership of the code you contribute, that it cannot be used in a way that
-   contradicts the license (which is a liberal BSD-style license), and that the
-   license for your contributions won't change without your approval in the
-   future.</p>
-   
+<p>For consistency and ease of management, the project requires the copyright
+   for all LLVM software to be held by a single copyright holder: the University
+   of Illinois (UIUC).</p>
+  
+<p>Although UIUC may eventually reassign the copyright of the software to
+   another entity (e.g. a dedicated non-profit "LLVM Organization") the intent
+   for the project is to always have a single entity hold the copyrights to LLVM
+   at any given time.</p>
+
+<p>We believe that having a single copyright holder is in the best interests of
+   all developers and users as it greatly reduces the managerial burden for any
+   kind of administrative or technical decisions about LLVM.  The goal of the
+   LLVM project is to always keep the code open and <a href="#license">licensed
+   under a very liberal license</a>.</p>
 </div>
 
 <!-- _______________________________________________________________________ -->



From stoklund at 2pi.dk  Sat Sep 25 11:09:51 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sat, 25 Sep 2010 09:09:51 -0700
Subject: [llvm-commits] [llvm] r114791 - in /llvm/trunk:
	include/llvm/CodeGen/LiveInterval.h
	lib/CodeGen/InlineSpiller.cpp lib/CodeGen/LiveInterval.cpp
	lib/CodeGen/LiveIntervalAnalysis.cpp
	lib/CodeGen/PreAllocSplitting.cpp lib/CodeGen/RegAllocLinearScan.cpp
	lib/CodeGen/RegAllocPBQP.cpp
	lib/CodeGen/SimpleRegisterCoalescing.cpp
	lib/CodeGen/Spiller.cpp lib/CodeGen/SplitKit.cpp
	lib/CodeGen/Splitter.cpp
In-Reply-To: <20100925120416.D10022A6C12C@llvm.org>
References: <20100925120416.D10022A6C12C@llvm.org>
Message-ID: <84EB0C33-7301-45C3-9DDE-C3B42E74A9D4@2pi.dk>


On Sep 25, 2010, at 5:04 AM, Lang Hames wrote:

> Author: lhames
> Date: Sat Sep 25 07:04:16 2010
> New Revision: 114791
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114791&view=rev
> Log:
> Removed VNInfo::isDefAccurate(). Def "accuracy" can be checked by testing whether LiveIntervals::getInstructionFromIndex(def) returns NULL.

Awesome. Thanks, Lang!

> Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=114791&r1=114790&r2=114791&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
> +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Sat Sep 25 07:04:16 2010
> @@ -283,7 +282,7 @@
>     lis_.RemoveMachineInstrFromMaps(DefMI);
>     vrm_.RemoveMachineInstrFromMaps(DefMI);
>     DefMI->eraseFromParent();
> -    VNI->setIsDefAccurate(false);
> +    VNI->def = lis_.getZeroIndex();

Would it be possible to simply use SlotIndex() here? I am not completely clear on the difference, but it would be nice to have just one exceptional SlotIndex.

> Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=114791&r1=114790&r2=114791&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
> +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Sat Sep 25 07:04:16 2010
> @@ -967,8 +968,7 @@
> 
>   assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
> 
> -  MachineInstr *DefMI = ValNo->isDefAccurate()
> -    ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
> +  MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
> 
>   // If this would create a new join point, do not split.
>   if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent())) {
> @@ -1005,7 +1005,7 @@
>   SlotIndex SpillIndex;
>   MachineInstr *SpillMI = NULL;
>   int SS = -1;
> -  if (!ValNo->isDefAccurate()) {
> +  if (LIs->getInstructionFromIndex(ValNo->def) == 0) {

This lookup is already available as DefMI above.

> Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=114791&r1=114790&r2=114791&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Sep 25 07:04:16 2010
> @@ -218,7 +218,7 @@
>         continue;
>       LiveInterval &SRLI = li_->getInterval(*SR);
>       SRLI.addRange(LiveRange(FillerStart, FillerEnd,
> -                              SRLI.getNextValue(FillerStart, 0, true,
> +                              SRLI.getNextValue(FillerStart, 0,
>                                                 li_->getVNInfoAllocator())));
>     }
>   }
> @@ -267,7 +267,8 @@
>       if (BI->valno == BValNo)
>         continue;
>       // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
> -      if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
> +      if (!BValNo && li_->getInstructionFromIndex(BI->valno->def) == 0 &&
> +          !BI->valno->getCopy())

Yeah, this is my fault. Those dummy clobber values don't exist any more. They used inaccurate defs a lot. This test can just be assumed false always.

>         continue;
>       if (BI->start <= AI->start && BI->end > AI->start)
>         return true;


> @@ -351,12 +352,11 @@
>   assert(ALR != IntA.end() && "Live range not found!");
>   VNInfo *AValNo = ALR->valno;
>   // If other defs can reach uses of this def, then it's not safe to perform
> -  // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
> -  // tested?
> -  if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
> -      AValNo->isUnused() || AValNo->hasPHIKill())
> -    return false;
> +  // the optimization.
>   MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
> +  if (AValNo->isPHIDef() || DefMI == 0 || AValNo->isUnused() ||
> +      AValNo->hasPHIKill())
> +    return false;
>   if (!DefMI)
>     return false;
>   const TargetInstrDesc &TID = DefMI->getDesc();
> @@ -652,9 +652,8 @@
>   assert(SrcLR != SrcInt.end() && "Live range not found!");
>   VNInfo *ValNo = SrcLR->valno;
>   // If other defs can reach uses of this def, then it's not safe to perform
> -  // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
> -  // tested?
> -  if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
> +  // the optimization.
> +  if (ValNo->isPHIDef() || li_->getInstructionFromIndex(ValNo->def)==0 ||
>       ValNo->isUnused() || ValNo->hasPHIKill())
>     return false;
>   MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);

These are both meant to be short-circuit optimizations: if isPHIDef() or isUnused(), don't pay the price of getInstructionFromIndex().

They should read:

if (isPHIDef || isUnused || hasPHIKill) return false;
MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
if (!DefMI) return false;

/jakob

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From stoklund at 2pi.dk  Sat Sep 25 13:10:38 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sat, 25 Sep 2010 18:10:38 -0000
Subject: [llvm-commits] [llvm] r114794 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h
 lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <20100925181038.D498A2A6C12C@llvm.org>

Author: stoklund
Date: Sat Sep 25 13:10:38 2010
New Revision: 114794

URL: http://llvm.org/viewvc/llvm-project?rev=114794&view=rev
Log:
Avoid using VNInfo::getCopy as much as possible. I want to get rid of it.

Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=114794&r1=114793&r2=114794&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Sat Sep 25 13:10:38 2010
@@ -90,6 +90,10 @@
     /// undefined behavior.
     void setCopy(MachineInstr *c) { copy = c; }
 
+    /// isDefByCopy - Return true when this value was defined by a copy-like
+    /// instruction as determined by MachineInstr::isCopyLike.
+    bool isDefByCopy() const { return copy != 0; }
+
     /// Returns true if one or more kills are PHI nodes.
     bool hasPHIKill() const { return flags & HAS_PHI_KILL; }
     /// Set the PHI kill flag on this value.

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=114794&r1=114793&r2=114794&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Sep 25 13:10:38 2010
@@ -124,7 +124,7 @@
   // Get the location that B is defined at.  Two options: either this value has
   // an unknown definition point or it is defined at CopyIdx.  If unknown, we
   // can't process it.
-  if (!BValNo->getCopy()) return false;
+  if (!BValNo->isDefByCopy()) return false;
   assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
 
   // AValNo is the value number in A that defines the copy, A3 in the example.
@@ -266,10 +266,6 @@
     for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
       if (BI->valno == BValNo)
         continue;
-      // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
-      if (!BValNo && li_->getInstructionFromIndex(BI->valno->def) == 0 &&
-          !BI->valno->getCopy())
-        continue;
       if (BI->start <= AI->start && BI->end > AI->start)
         return true;
       if (BI->start > AI->start && BI->start < AI->end)
@@ -342,7 +338,7 @@
   // Get the location that B is defined at.  Two options: either this value has
   // an unknown definition point or it is defined at CopyIdx.  If unknown, we
   // can't process it.
-  if (!BValNo->getCopy()) return false;
+  if (!BValNo->isDefByCopy()) return false;
   assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
 
   // AValNo is the value number in A that defines the copy, A3 in the example.
@@ -873,7 +869,7 @@
   if (li_->hasInterval(DstReg)) {
     LiveInterval &LI = li_->getInterval(DstReg);
     if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
-      if (LR->valno->getCopy() == CopyMI)
+      if (LR->valno->def == DefIdx)
         LR->valno->setCopy(0);
   }
   if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
@@ -883,7 +879,7 @@
       continue;
     LiveInterval &LI = li_->getInterval(*AS);
     if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
-      if (LR->valno->getCopy() == CopyMI)
+      if (LR->valno->def == DefIdx)
         LR->valno->setCopy(0);
   }
 }
@@ -1316,7 +1312,7 @@
   for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
        i != e; ++i) {
     VNInfo *VNI = *i;
-    if (VNI->isUnused() || VNI->getCopy() == 0)  // Src not defined by a copy?
+    if (VNI->isUnused() || !VNI->isDefByCopy())  // Src not defined by a copy?
       continue;
 
     // Never join with a register that has EarlyClobber redefs.
@@ -1340,7 +1336,7 @@
   for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
        i != e; ++i) {
     VNInfo *VNI = *i;
-    if (VNI->isUnused() || VNI->getCopy() == 0)  // Src not defined by a copy?
+    if (VNI->isUnused() || !VNI->isDefByCopy())  // Src not defined by a copy?
       continue;
 
     // Never join with a register that has EarlyClobber redefs.



From ofv at wanadoo.es  Sat Sep 25 15:25:25 2010
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Sat, 25 Sep 2010 20:25:25 -0000
Subject: [llvm-commits] [llvm] r114795 - in /llvm/trunk: CMakeLists.txt
 cmake/modules/AddLLVM.cmake unittests/CMakeLists.txt
 utils/unittest/CMakeLists.txt
Message-ID: <20100925202525.D3D2D2A6C12C@llvm.org>

Author: ofv
Date: Sat Sep 25 15:25:25 2010
New Revision: 114795

URL: http://llvm.org/viewvc/llvm-project?rev=114795&view=rev
Log:
Reverting "CMake: Don't include tools, unittets, or examples as
available targets unless LLVM_INCLUDE_X is ON. LLVM_BUILD_X implies
LLVM_INCLUDE_X"

It breaks the configuration phase when cmake is invoked without
parameters, it is too complex for the purpose and introduces an
incovenience for the user (as both LLVM_BUILD_X and LLVM_INCLUDE_X
must set to OFF for not including X on the build)

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/cmake/modules/AddLLVM.cmake
    llvm/trunk/unittests/CMakeLists.txt
    llvm/trunk/utils/unittest/CMakeLists.txt

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=114795&r1=114794&r2=114795&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Sat Sep 25 15:25:25 2010
@@ -364,18 +364,12 @@
 add_subdirectory(projects)
 
 option(LLVM_BUILD_TOOLS "Build LLVM tool programs." ON)
-option(LLVM_INCLUDE_TOOLS
-  "Include LLVM tool programs as an available target." ON)
 add_subdirectory(tools)
 
 option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF)
-option(LLVM_INCLUDE_EXAMPLES
-  "Include LLVM example programs as an available target." OFF)
 add_subdirectory(examples)
 
 option(LLVM_BUILD_TESTS "Build LLVM unit tests." OFF)
-option(LLVM_INCLUDE_TESTS
-  "Include LLVM unit tests as an available target." OFF)
 add_subdirectory(test)
 add_subdirectory(utils/unittest)
 add_subdirectory(unittests)

Modified: llvm/trunk/cmake/modules/AddLLVM.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=114795&r1=114794&r2=114795&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/AddLLVM.cmake (original)
+++ llvm/trunk/cmake/modules/AddLLVM.cmake Sat Sep 25 15:25:25 2010
@@ -77,9 +77,7 @@
   if( NOT LLVM_BUILD_TOOLS )
     set(EXCLUDE_FROM_ALL ON)
   endif()
-  if( LLVM_INCLUDE_TOOLS OR LLVM_BUILD_TOOLS )
-    add_llvm_executable(${name} ${ARGN})
-  endif()
+  add_llvm_executable(${name} ${ARGN})
   if( LLVM_BUILD_TOOLS )
     install(TARGETS ${name} RUNTIME DESTINATION bin)
   endif()
@@ -91,9 +89,7 @@
   if( NOT LLVM_BUILD_EXAMPLES )
     set(EXCLUDE_FROM_ALL ON)
   endif()
-  if( LLVM_INCLUDE_EXAMPLES OR LLVM_BUILD_EXAMPLES )
-    add_llvm_executable(${name} ${ARGN})
-  endif()
+  add_llvm_executable(${name} ${ARGN})
   if( LLVM_BUILD_EXAMPLES )
     install(TARGETS ${name} RUNTIME DESTINATION examples)
   endif()

Modified: llvm/trunk/unittests/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=114795&r1=114794&r2=114795&view=diff
==============================================================================
--- llvm/trunk/unittests/CMakeLists.txt (original)
+++ llvm/trunk/unittests/CMakeLists.txt Sat Sep 25 15:25:25 2010
@@ -9,9 +9,7 @@
   if( NOT LLVM_BUILD_TESTS )
     set(EXCLUDE_FROM_ALL ON)
   endif()
-  if (LLVM_INCLUDE_TESTS OR LLVM_BUILD_TESTS)
-    add_llvm_executable(${test_name}Tests ${ARGN})
-  endif()
+  add_llvm_executable(${test_name}Tests ${ARGN})
 endfunction()
 
 include_directories(${LLVM_MAIN_SRC_DIR}/utils/unittest/googletest/include)

Modified: llvm/trunk/utils/unittest/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/CMakeLists.txt?rev=114795&r1=114794&r2=114795&view=diff
==============================================================================
--- llvm/trunk/utils/unittest/CMakeLists.txt (original)
+++ llvm/trunk/utils/unittest/CMakeLists.txt Sat Sep 25 15:25:25 2010
@@ -20,17 +20,15 @@
   add_definitions(-DGTEST_OS_WINDOWS=1)
 endif()
 
-if (LLVM_INCLUDE_TESTS OR LLVM_BUILD_TESTS)
-  add_llvm_library(gtest
-    googletest/gtest.cc
-    googletest/gtest-death-test.cc
-    googletest/gtest-filepath.cc
-    googletest/gtest-port.cc
-    googletest/gtest-test-part.cc
-    googletest/gtest-typed-test.cc
-    )
+add_llvm_library(gtest
+  googletest/gtest.cc
+  googletest/gtest-death-test.cc
+  googletest/gtest-filepath.cc
+  googletest/gtest-port.cc
+  googletest/gtest-test-part.cc
+  googletest/gtest-typed-test.cc
+  )
 
-  add_llvm_library(gtest_main
-    UnitTestMain/TestMain.cpp
-    )
-endif()
+add_llvm_library(gtest_main
+  UnitTestMain/TestMain.cpp
+  )



From ofv at wanadoo.es  Sat Sep 25 15:27:36 2010
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Sat, 25 Sep 2010 20:27:36 -0000
Subject: [llvm-commits] [llvm] r114796 - in /llvm/trunk/include/llvm:
 Analysis/DebugInfo.h Attributes.h Operator.h
Message-ID: <20100925202736.391C12A6C12C@llvm.org>

Author: ofv
Date: Sat Sep 25 15:27:36 2010
New Revision: 114796

URL: http://llvm.org/viewvc/llvm-project?rev=114796&view=rev
Log:
Avoid warnings about implicit conversions to `bool' in MSVC. This time
for real.

Patch by Nathan Jeffords!

Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/include/llvm/Attributes.h
    llvm/trunk/include/llvm/Operator.h

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=114796&r1=114795&r2=114796&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Sat Sep 25 15:27:36 2010
@@ -160,8 +160,8 @@
     /// module does not contain any main compile unit then the code generator
     /// will emit multiple compile units in the output object file.
 
-    bool isMain() const                { return getUnsignedField(6); }
-    bool isOptimized() const           { return getUnsignedField(7); }
+    bool isMain() const                { return getUnsignedField(6) != 0; }
+    bool isOptimized() const           { return getUnsignedField(7) != 0; }
     StringRef getFlags() const       { return getStringField(8);   }
     unsigned getRunTimeVersion() const { return getUnsignedField(9); }
 

Modified: llvm/trunk/include/llvm/Attributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=114796&r1=114795&r2=114796&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Attributes.h (original)
+++ llvm/trunk/include/llvm/Attributes.h Sat Sep 25 15:27:36 2010
@@ -223,7 +223,7 @@
   /// paramHasAttr - Return true if the specified parameter index has the
   /// specified attribute set.
   bool paramHasAttr(unsigned Idx, Attributes Attr) const {
-    return static_cast<bool>(getAttributes(Idx) & Attr);
+    return (getAttributes(Idx) & Attr) != 0;
   }
 
   /// getParamAlignment - Return the alignment for the specified function

Modified: llvm/trunk/include/llvm/Operator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Operator.h?rev=114796&r1=114795&r2=114796&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Operator.h (original)
+++ llvm/trunk/include/llvm/Operator.h Sat Sep 25 15:27:36 2010
@@ -99,7 +99,7 @@
   /// hasNoSignedWrap - Test whether this operation is known to never
   /// undergo signed overflow, aka the nsw property.
   bool hasNoSignedWrap() const {
-    return static_cast<bool>(SubclassOptionalData & NoSignedWrap);
+    return (SubclassOptionalData & NoSignedWrap) != 0;
   }
 
   static inline bool classof(const OverflowingBinaryOperator *) { return true; }



From ofv at wanadoo.es  Sat Sep 25 15:43:06 2010
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Sat, 25 Sep 2010 20:43:06 -0000
Subject: [llvm-commits] [llvm] r114797 - in /llvm/trunk: CMakeLists.txt
	docs/CMake.html
Message-ID: <20100925204306.9EA092A6C12C@llvm.org>

Author: ofv
Date: Sat Sep 25 15:43:06 2010
New Revision: 114797

URL: http://llvm.org/viewvc/llvm-project?rev=114797&view=rev
Log:
New cmake options LLVM_INCLUDE_X (X = {TOOLS, EXAMPLES, TESTS}) for
not generating build targets for those parts of the build.

Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/docs/CMake.html

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=114797&r1=114796&r2=114797&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Sat Sep 25 15:43:06 2010
@@ -363,17 +363,28 @@
 
 add_subdirectory(projects)
 
-option(LLVM_BUILD_TOOLS "Build LLVM tool programs." ON)
-add_subdirectory(tools)
-
-option(LLVM_BUILD_EXAMPLES "Build LLVM example programs." OFF)
-add_subdirectory(examples)
-
-option(LLVM_BUILD_TESTS "Build LLVM unit tests." OFF)
-add_subdirectory(test)
-add_subdirectory(utils/unittest)
-add_subdirectory(unittests)
-
+option(LLVM_BUILD_TOOLS
+  "Build the LLVM tools. If OFF, just generate build targets." ON)
+option(LLVM_INCLUDE_TOOLS "Generate build targets for the LLVM tools." ON)
+if( LLVM_INCLUDE_TOOLS )
+  add_subdirectory(tools)
+endif()
+
+option(LLVM_BUILD_EXAMPLES
+  "Build the LLVM example programs. If OFF, just generate build targets." OFF)
+option(LLVM_INCLUDE_EXAMPLES "Generate build targets for the LLVM examples" ON)
+if( LLVM_INCLUDE_EXAMPLES )
+  add_subdirectory(examples)
+endif()
+
+option(LLVM_BUILD_TESTS
+  "Build LLVM unit tests. If OFF, just generate build targes." OFF)
+option(LLVM_INCLUDE_TESTS "Generate build targets for the LLVM unit tests." ON)
+if( LLVM_INCLUDE_TESTS )
+  add_subdirectory(test)
+  add_subdirectory(utils/unittest)
+  add_subdirectory(unittests)
+endif()
 
 add_subdirectory(cmake/modules)
 

Modified: llvm/trunk/docs/CMake.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=114797&r1=114796&r2=114797&view=diff
==============================================================================
--- llvm/trunk/docs/CMake.html (original)
+++ llvm/trunk/docs/CMake.html Sat Sep 25 15:43:06 2010
@@ -257,11 +257,21 @@
     with a makefile-based system executing <i>make llvm-as</i> on the
     root of your build directory.</dd>
 
+  <dt><b>LLVM_INCLUDE_TOOLS</b>:BOOL</dt>
+  <dd>Generate build targets for the LLVM tools. Defaults to
+    ON. You can use that option for disabling the generation of build
+    targets for the LLVM tools.</dd>
+
   <dt><b>LLVM_BUILD_EXAMPLES</b>:BOOL</dt>
   <dd>Build LLVM examples. Defaults to OFF. Targets for building each
     example are generated in any case. See documentation
     for <i>LLVM_BUILD_TOOLS</i> above for more details.</dd>
 
+  <dt><b>LLVM_INCLUDE_EXAMPLES</b>:BOOL</dt>
+  <dd>Generate build targets for the LLVM examples. Defaults to
+    ON. You can use that option for disabling the generation of build
+    targets for the LLVM examples.</dd>
+
   <dt><b>LLVM_ENABLE_THREADS</b>:BOOL</dt>
   <dd>Build with threads support, if available. Defaults to ON.</dd>
 



From lhames at gmail.com  Sat Sep 25 22:37:09 2010
From: lhames at gmail.com (Lang Hames)
Date: Sun, 26 Sep 2010 03:37:09 -0000
Subject: [llvm-commits] [llvm] r114798 - in /llvm/trunk/lib/CodeGen:
 InlineSpiller.cpp PreAllocSplitting.cpp SimpleRegisterCoalescing.cpp
Message-ID: <20100926033709.9D8C82A6C12C@llvm.org>

Author: lhames
Date: Sat Sep 25 22:37:09 2010
New Revision: 114798

URL: http://llvm.org/viewvc/llvm-project?rev=114798&view=rev
Log:
Fixed some tests to avoid LiveIntervals::getInstructionFromIndex(..) overhead where possible. Thanks to Jakob for the suggestions.


Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=114798&r1=114797&r2=114798&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Sat Sep 25 22:37:09 2010
@@ -282,7 +282,7 @@
     lis_.RemoveMachineInstrFromMaps(DefMI);
     vrm_.RemoveMachineInstrFromMaps(DefMI);
     DefMI->eraseFromParent();
-    VNI->def = lis_.getZeroIndex();
+    VNI->def = SlotIndex();
     anyRemoved = true;
   }
 

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=114798&r1=114797&r2=114798&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Sat Sep 25 22:37:09 2010
@@ -807,8 +807,7 @@
   MachineBasicBlock& MBB = *RestorePt->getParent();
   
   MachineBasicBlock::iterator KillPt = BarrierMBB->end();
-  if (LIs->getInstructionFromIndex(ValNo->def) == 0 ||
-      DefMI->getParent() == BarrierMBB)
+  if (!DefMI || DefMI->getParent() == BarrierMBB)
     KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB);
   else
     KillPt = llvm::next(MachineBasicBlock::iterator(DefMI));
@@ -1005,7 +1004,7 @@
   SlotIndex SpillIndex;
   MachineInstr *SpillMI = NULL;
   int SS = -1;
-  if (LIs->getInstructionFromIndex(ValNo->def) == 0) {
+  if (!DefMI) {
     // If we don't know where the def is we must split just before the barrier.
     if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
                             BarrierMBB, SS, RefsInMBB))) {

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=114798&r1=114797&r2=114798&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Sep 25 22:37:09 2010
@@ -349,10 +349,9 @@
   VNInfo *AValNo = ALR->valno;
   // If other defs can reach uses of this def, then it's not safe to perform
   // the optimization.
-  MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
-  if (AValNo->isPHIDef() || DefMI == 0 || AValNo->isUnused() ||
-      AValNo->hasPHIKill())
+  if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
     return false;
+  MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
   if (!DefMI)
     return false;
   const TargetInstrDesc &TID = DefMI->getDesc();
@@ -649,10 +648,11 @@
   VNInfo *ValNo = SrcLR->valno;
   // If other defs can reach uses of this def, then it's not safe to perform
   // the optimization.
-  if (ValNo->isPHIDef() || li_->getInstructionFromIndex(ValNo->def)==0 ||
-      ValNo->isUnused() || ValNo->hasPHIKill())
+  if (ValNo->isPHIDef() || ValNo->isUnused() || ValNo->hasPHIKill())
     return false;
   MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
+  if (!DefMI)
+    return false;
   assert(DefMI && "Defining instruction disappeared");
   const TargetInstrDesc &TID = DefMI->getDesc();
   if (!TID.isAsCheapAsAMove())



From echristo at apple.com  Sat Sep 25 22:48:14 2010
From: echristo at apple.com (Eric Christopher)
Date: Sat, 25 Sep 2010 20:48:14 -0700
Subject: [llvm-commits] [llvm] r114781 -
	/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
In-Reply-To: <C4B23BF3-01D5-4AE9-A339-164E7B0CC082@apple.com>
References: <20100925005726.CBE142A6C12C@llvm.org>
	<C4B23BF3-01D5-4AE9-A339-164E7B0CC082@apple.com>
Message-ID: <28C7298E-D866-444F-AACD-E2F7DE647631@apple.com>


On Sep 24, 2010, at 9:20 PM, Jim Grosbach wrote:

> Eesh. That's a nasty one. Nice fix.
> 
> re: the TODO, I suspect the answer is "maybe." Not sure off the top of my head how to accurately model the change in cost, though.

Yeah, we'd have to model whether or not we think it'll be combined with another memcpy, blah blah blah, etc.

Probably worth just removing the TODO and hoping for the best :)

-eric

From lhames at gmail.com  Sat Sep 25 22:50:37 2010
From: lhames at gmail.com (Lang Hames)
Date: Sun, 26 Sep 2010 13:50:37 +1000
Subject: [llvm-commits] [llvm] r114791 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/InlineSpiller.cpp
 lib/CodeGen/LiveInterval.cpp lib/CodeGen/LiveIntervalAnalysis.cpp
 lib/CodeGen/PreAllocSplitting.cpp lib/CodeGen/RegAllocLinearScan.c
Message-ID: <AANLkTi=HPNgFZL7MjqXUs4RoR93zNvbME3Jfmz9xABbm@mail.gmail.com>

Hi Jakob,

Thanks for the suggestions. They've been applied in r114798.


> Would it be possible to simply use SlotIndex() here? I am not completely
> clear on the difference, but it would be nice to have just one exceptional
> SlotIndex.
>

LiveIntervals::getZeroIndex() returns an index which will compare lower than
any other (and is the valid first index in the function). SlotIndex() values
will compare higher than any other. Whether any code actually relies on this
property I am not sure. SlotIndex() values are _not_ valid slots for any
function, and it's impossible to traverse from them to any valid slot.
They're self contained "weird" values. For that reason I think SlotIndex()
would be better as the exceptional value.

Cheers,
Lang.

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=114791&r1=114790&r2=114791&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
> +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Sat Sep 25 07:04:16 2010
> @@ -967,8 +968,7 @@
>
>   assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
>
> -  MachineInstr *DefMI = ValNo->isDefAccurate()
> -    ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
> +  MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
>
>   // If this would create a new join point, do not split.
>   if (DefMI && createsNewJoin(LR, DefMI->getParent(),
> Barrier->getParent())) {
> @@ -1005,7 +1005,7 @@
>   SlotIndex SpillIndex;
>   MachineInstr *SpillMI = NULL;
>   int SS = -1;
> -  if (!ValNo->isDefAccurate()) {
> +  if (LIs->getInstructionFromIndex(ValNo->def) == 0) {
>
>
> This lookup is already available as DefMI above.
>
> Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=114791&r1=114790&r2=114791&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Sep 25 07:04:16
> 2010
> @@ -218,7 +218,7 @@
>         continue;
>       LiveInterval &SRLI = li_->getInterval(*SR);
>       SRLI.addRange(LiveRange(FillerStart, FillerEnd,
> -                              SRLI.getNextValue(FillerStart, 0, true,
> +                              SRLI.getNextValue(FillerStart, 0,
>
>                                                 li_->getVNInfoAllocator())));
>     }
>   }
> @@ -267,7 +267,8 @@
>       if (BI->valno == BValNo)
>         continue;
>       // When BValNo is null, we're looking for a dummy clobber-value for a
> subreg.
> -      if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
> +      if (!BValNo && li_->getInstructionFromIndex(BI->valno->def) == 0 &&
> +          !BI->valno->getCopy())
>
>
> Yeah, this is my fault. Those dummy clobber values don't exist any more.
> They used inaccurate defs a lot. This test can just be assumed false always.
>
>         continue;
>       if (BI->start <= AI->start && BI->end > AI->start)
>         return true;
>
>
>
> @@ -351,12 +352,11 @@
>   assert(ALR != IntA.end() && "Live range not found!");
>   VNInfo *AValNo = ALR->valno;
>   // If other defs can reach uses of this def, then it's not safe to
> perform
> -  // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to
> be
> -  // tested?
> -  if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
> -      AValNo->isUnused() || AValNo->hasPHIKill())
> -    return false;
> +  // the optimization.
>   MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
> +  if (AValNo->isPHIDef() || DefMI == 0 || AValNo->isUnused() ||
> +      AValNo->hasPHIKill())
> +    return false;
>   if (!DefMI)
>     return false;
>   const TargetInstrDesc &TID = DefMI->getDesc();
> @@ -652,9 +652,8 @@
>   assert(SrcLR != SrcInt.end() && "Live range not found!");
>   VNInfo *ValNo = SrcLR->valno;
>   // If other defs can reach uses of this def, then it's not safe to
> perform
> -  // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to
> be
> -  // tested?
> -  if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
> +  // the optimization.
> +  if (ValNo->isPHIDef() || li_->getInstructionFromIndex(ValNo->def)==0 ||
>       ValNo->isUnused() || ValNo->hasPHIKill())
>     return false;
>   MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
>
>
> These are both meant to be short-circuit optimizations: if isPHIDef() or
> isUnused(), don't pay the price of getInstructionFromIndex().
>
> They should read:
>
> if (isPHIDef || isUnused || hasPHIKill) return false;
> MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
> if (!DefMI) return false;
>
> /jakob
>
>
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From baldrick at free.fr  Sun Sep 26 02:33:09 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 07:33:09 -0000
Subject: [llvm-commits] [dragonegg] r114799 - in /dragonegg/trunk:
 bits_and_bobs.cpp llvm-backend.cpp llvm-convert.cpp x86/llvm-target.cpp
Message-ID: <20100926073309.E90152A6C12D@llvm.org>

Author: baldrick
Date: Sun Sep 26 02:33:09 2010
New Revision: 114799

URL: http://llvm.org/viewvc/llvm-project?rev=114799&view=rev
Log:
Trim header files.

Modified:
    dragonegg/trunk/bits_and_bobs.cpp
    dragonegg/trunk/llvm-backend.cpp
    dragonegg/trunk/llvm-convert.cpp
    dragonegg/trunk/x86/llvm-target.cpp

Modified: dragonegg/trunk/bits_and_bobs.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/bits_and_bobs.cpp?rev=114799&r1=114798&r2=114799&view=diff
==============================================================================
--- dragonegg/trunk/bits_and_bobs.cpp (original)
+++ dragonegg/trunk/bits_and_bobs.cpp Sun Sep 26 02:33:09 2010
@@ -1,5 +1,2 @@
-#include <stdlib.h>
-
 int ix86_regparm;
-
 union tree_node;

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=114799&r1=114798&r2=114799&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Sun Sep 26 02:33:09 2010
@@ -71,11 +71,9 @@
 #include "target.h"
 #include "tree.h"
 
-#include "cgraph.h"
 #include "debug.h"
 #include "diagnostic.h"
 #include "flags.h"
-#include "function.h"
 #include "gcc-plugin.h"
 #include "intl.h"
 #include "langhooks.h"
@@ -83,11 +81,9 @@
 #include "params.h"
 #include "plugin-version.h"
 #include "toplev.h"
-#include "tree-inline.h"
 #include "tree-flow.h"
 #include "tree-pass.h"
 #include "version.h"
-#include "except.h"
 }
 
 #if (GCC_MAJOR != 4)

Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=114799&r1=114798&r2=114799&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Sun Sep 26 02:33:09 2010
@@ -63,21 +63,16 @@
 #include "target.h"
 #include "tree.h"
 
-#include "tm_p.h"
-//TODO#include "c-tree.h"  // FIXME: eliminate.
-#include "tree-iterator.h"
-#include "output.h"
 #include "diagnostic.h"
-#include "real.h"
-#include "function.h"
-#include "toplev.h"
+#include "except.h"
 #include "flags.h"
-#include "hard-reg-set.h"
+#include "langhooks.h"
+#include "output.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "toplev.h"
 #include "tree-flow.h"
 #include "tree-pass.h"
-#include "rtl.h"
-#include "langhooks.h"
-#include "except.h"
 
 extern int get_pointer_alignment (tree exp, unsigned int max_align);
 extern enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];

Modified: dragonegg/trunk/x86/llvm-target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=114799&r1=114798&r2=114799&view=diff
==============================================================================
--- dragonegg/trunk/x86/llvm-target.cpp (original)
+++ dragonegg/trunk/x86/llvm-target.cpp Sun Sep 26 02:33:09 2010
@@ -44,9 +44,10 @@
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"
-#include "toplev.h"
 #include "tree.h"
+
 #include "gimple.h"
+#include "toplev.h"
 }
 
 static LLVMContext &Context = getGlobalContext();



From baldrick at free.fr  Sun Sep 26 02:47:46 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 07:47:46 -0000
Subject: [llvm-commits] [dragonegg] r114800 - in /dragonegg/trunk:
 llvm-abi-default.cpp llvm-backend.cpp llvm-convert.cpp llvm-debug.cpp
 llvm-types.cpp x86/llvm-target.cpp
Message-ID: <20100926074746.741EA2A6C12D@llvm.org>

Author: baldrick
Date: Sun Sep 26 02:47:46 2010
New Revision: 114800

URL: http://llvm.org/viewvc/llvm-project?rev=114800&view=rev
Log:
Some versions of gcc give a compile error when building with -pedantic
because system headers define getopt with 'throw()', while gcc headers
define getopt without the exception specification.  Work around this by
turning off gcc's declaration.  Part of PR8229. 

Modified:
    dragonegg/trunk/llvm-abi-default.cpp
    dragonegg/trunk/llvm-backend.cpp
    dragonegg/trunk/llvm-convert.cpp
    dragonegg/trunk/llvm-debug.cpp
    dragonegg/trunk/llvm-types.cpp
    dragonegg/trunk/x86/llvm-target.cpp

Modified: dragonegg/trunk/llvm-abi-default.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-abi-default.cpp?rev=114800&r1=114799&r2=114800&view=diff
==============================================================================
--- dragonegg/trunk/llvm-abi-default.cpp (original)
+++ dragonegg/trunk/llvm-abi-default.cpp Sun Sep 26 02:47:46 2010
@@ -7,6 +7,8 @@
 // GCC headers
 extern "C" {
 #include "config.h"
+// Stop GCC declaring 'getopt' as it can clash with the system's declaration.
+#undef HAVE_DECL_GETOPT
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=114800&r1=114799&r2=114800&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Sun Sep 26 02:47:46 2010
@@ -66,6 +66,8 @@
 // GCC headers
 extern "C" {
 #include "config.h"
+// Stop GCC declaring 'getopt' as it can clash with the system's declaration.
+#undef HAVE_DECL_GETOPT
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"

Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=114800&r1=114799&r2=114800&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Sun Sep 26 02:47:46 2010
@@ -58,6 +58,8 @@
 // GCC headers
 extern "C" {
 #include "config.h"
+// Stop GCC declaring 'getopt' as it can clash with the system's declaration.
+#undef HAVE_DECL_GETOPT
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"

Modified: dragonegg/trunk/llvm-debug.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-debug.cpp?rev=114800&r1=114799&r2=114800&view=diff
==============================================================================
--- dragonegg/trunk/llvm-debug.cpp (original)
+++ dragonegg/trunk/llvm-debug.cpp Sun Sep 26 02:47:46 2010
@@ -46,6 +46,8 @@
 // GCC headers
 extern "C" {
 #include "config.h"
+// Stop GCC declaring 'getopt' as it can clash with the system's declaration.
+#undef HAVE_DECL_GETOPT
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"

Modified: dragonegg/trunk/llvm-types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-types.cpp?rev=114800&r1=114799&r2=114800&view=diff
==============================================================================
--- dragonegg/trunk/llvm-types.cpp (original)
+++ dragonegg/trunk/llvm-types.cpp Sun Sep 26 02:47:46 2010
@@ -50,6 +50,8 @@
 // GCC headers
 extern "C" {
 #include "config.h"
+// Stop GCC declaring 'getopt' as it can clash with the system's declaration.
+#undef HAVE_DECL_GETOPT
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"

Modified: dragonegg/trunk/x86/llvm-target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=114800&r1=114799&r2=114800&view=diff
==============================================================================
--- dragonegg/trunk/x86/llvm-target.cpp (original)
+++ dragonegg/trunk/x86/llvm-target.cpp Sun Sep 26 02:47:46 2010
@@ -41,6 +41,8 @@
 // GCC headers
 extern "C" {
 #include "config.h"
+// Stop GCC declaring 'getopt' as it can clash with the system's declaration.
+#undef HAVE_DECL_GETOPT
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"



From baldrick at free.fr  Sun Sep 26 02:58:25 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 07:58:25 -0000
Subject: [llvm-commits] [dragonegg] r114801 - in /dragonegg/trunk:
	llvm-cache.c llvm-cache.h
Message-ID: <20100926075825.4EFCD2A6C12D@llvm.org>

Author: baldrick
Date: Sun Sep 26 02:58:25 2010
New Revision: 114801

URL: http://llvm.org/viewvc/llvm-project?rev=114801&view=rev
Log:
Make these files -pedantic clean.

Modified:
    dragonegg/trunk/llvm-cache.c
    dragonegg/trunk/llvm-cache.h

Modified: dragonegg/trunk/llvm-cache.c
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-cache.c?rev=114801&r1=114800&r2=114801&view=diff
==============================================================================
--- dragonegg/trunk/llvm-cache.c (original)
+++ dragonegg/trunk/llvm-cache.c Sun Sep 26 02:58:25 2010
@@ -18,16 +18,16 @@
 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 02111-1307, USA.  */
 
-//===----------------------------------------------------------------------===//
-// This code lets you to associate a void* with a tree, as if it were cached
-// inside the tree: if the tree is garbage collected and reallocated, then the
-// cached value will have been cleared.
-//===----------------------------------------------------------------------===//
+/*===----------------------------------------------------------------------===
+   This code lets you to associate a void* with a tree, as if it were cached
+   inside the tree: if the tree is garbage collected and reallocated, then the
+   cached value will have been cleared.
+  ===----------------------------------------------------------------------===*/
 
-// Plugin headers
+/* Plugin headers.  */
 #include "llvm-cache.h"
 
-// GCC headers
+/* GCC headers.  */
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
@@ -48,10 +48,11 @@
              param_is(struct tree_llvm_map)))
   htab_t llvm_cache;
 
-// Garbage collector header
+/* Garbage collector header.  */
 #include "gt-llvm-cache.h"
 
-/// llvm_has_cached - Returns whether a value has been associated with the tree.
+/* llvm_has_cached - Returns whether a value has been associated with the
+   tree.  */
 int llvm_has_cached(union tree_node *tree) {
   struct tree_map_base in;
 
@@ -62,7 +63,7 @@
   return htab_find(llvm_cache, &in) != NULL;
 }
 
-/// llvm_get_cached - Returns the value associated with the tree, or NULL.
+/* llvm_get_cached - Returns the value associated with the tree, or NULL.  */
 const void *llvm_get_cached(union tree_node *tree) {
   struct tree_llvm_map *h;
   struct tree_map_base in;
@@ -75,15 +76,15 @@
   return h ? h->val : NULL;
 }
 
-/// llvm_set_cached - Associates the given value with the tree (and returns it).
-/// To delete an association, pass a NULL value here.
+/* llvm_set_cached - Associates the given value with the tree (and returns it).
+   To delete an association, pass a NULL value here.  */
 const void *llvm_set_cached(union tree_node *tree, const void *val) {
   struct tree_llvm_map **slot;
   struct tree_map_base in;
 
   in.from = tree;
 
-  // If deleting, remove the slot.
+  /* If deleting, remove the slot.  */
   if (val == NULL) {
     if (llvm_cache)
       htab_remove_elt(llvm_cache, &in);
@@ -111,8 +112,8 @@
   const void *new_val;
 };
 
-/// replace - If the current value for the slot matches old_val, then replace
-/// it with new_val, or delete it if new_val is NULL.
+/* replace - If the current value for the slot matches old_val, then replace
+   it with new_val, or delete it if new_val is NULL.  */
 static int replace(void **slot, void *data) {
   struct tree_llvm_map *entry = *(struct tree_llvm_map **)slot;
   struct update *u = (struct update *)data;
@@ -128,9 +129,11 @@
   return 1;
 }
 
-/// llvm_replace_cached - Replaces all occurrences of old_val with new_val.
+/* llvm_replace_cached - Replaces all occurrences of old_val with new_val.  */
 void llvm_replace_cached(const void *old_val, const void *new_val) {
-  struct update u = { old_val, new_val };
+  struct update u;
+  u.old_val = old_val;
+  u.new_val = new_val;
 
   if (!llvm_cache || old_val == NULL)
     return;

Modified: dragonegg/trunk/llvm-cache.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-cache.h?rev=114801&r1=114800&r2=114801&view=diff
==============================================================================
--- dragonegg/trunk/llvm-cache.h (original)
+++ dragonegg/trunk/llvm-cache.h Sun Sep 26 02:58:25 2010
@@ -19,28 +19,29 @@
 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 02111-1307, USA.  */
 
-//===----------------------------------------------------------------------===//
-// This code lets you to associate a void* with a tree, as if it were cached
-// inside the tree: if the tree is garbage collected and reallocated, then the
-// cached value will have been cleared.
-//===----------------------------------------------------------------------===//
+/*===----------------------------------------------------------------------===
+   This code lets you to associate a void* with a tree, as if it were cached
+   inside the tree: if the tree is garbage collected and reallocated, then the
+   cached value will have been cleared.
+  ===----------------------------------------------------------------------===*/
 
 #ifndef LLVM_CACHE_H
 #define LLVM_CACHE_H
 
 union tree_node;
 
-/// llvm_has_cached - Returns whether a value has been associated with the tree.
+/* llvm_has_cached - Returns whether a value has been associated with the
+   tree.  */
 extern int llvm_has_cached(union tree_node *tree);
 
-/// llvm_get_cached - Returns the value associated with the tree, or NULL.
+/* llvm_get_cached - Returns the value associated with the tree, or NULL.  */
 extern const void *llvm_get_cached(union tree_node *tree);
 
-/// llvm_set_cached - Associates the given value with the tree (and returns it).
-/// To delete an association, pass NULL for the value.
+/* llvm_set_cached - Associates the given value with the tree (and returns it).
+   To delete an association, pass NULL for the value.  */
 extern const void *llvm_set_cached(union tree_node *tree, const void *val);
 
-/// llvm_replace_cached - Replaces all occurrences of old_val with new_val.
+/* llvm_replace_cached - Replaces all occurrences of old_val with new_val.  */
 extern void llvm_replace_cached(const void *old_val, const void *new_val);
 
 #endif /* LLVM_CACHE_H */



From baldrick at free.fr  Sun Sep 26 03:01:21 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 08:01:21 -0000
Subject: [llvm-commits] [dragonegg] r114802 -
	/dragonegg/trunk/llvm-convert.cpp
Message-ID: <20100926080121.4D6632A6C12D@llvm.org>

Author: baldrick
Date: Sun Sep 26 03:01:21 2010
New Revision: 114802

URL: http://llvm.org/viewvc/llvm-project?rev=114802&view=rev
Log:
Make this file -pedantic clean ('use of C99 long long integer constant').

Modified:
    dragonegg/trunk/llvm-convert.cpp

Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=114802&r1=114801&r2=114802&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Sun Sep 26 03:01:21 2010
@@ -7700,7 +7700,8 @@
 
     // Next, if this doesn't touch the top bit, mask out any bits that shouldn't
     // be set in the result.
-    uint64_t MaskVal = ((1ULL << BitsInVal)-1) << FirstBitInVal;
+    uint64_t MaskVal = 1;
+    MaskVal = ((MaskVal << BitsInVal)-1) << FirstBitInVal;
     Constant *Mask = ConstantInt::get(Type::getInt64Ty(Context), MaskVal);
     Mask = Builder.getFolder().CreateTruncOrBitCast(Mask, ValTy);
 



From baldrick at free.fr  Sun Sep 26 07:53:14 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 12:53:14 -0000
Subject: [llvm-commits] [dragonegg] r114803 - /dragonegg/trunk/llvm-types.cpp
Message-ID: <20100926125314.14AED2A6C12C@llvm.org>

Author: baldrick
Date: Sun Sep 26 07:53:13 2010
New Revision: 114803

URL: http://llvm.org/viewvc/llvm-project?rev=114803&view=rev
Log:
Remove uses of "C99 long long integer constant", making this file
clean when building with -pedantic.

Modified:
    dragonegg/trunk/llvm-types.cpp

Modified: dragonegg/trunk/llvm-types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-types.cpp?rev=114803&r1=114802&r2=114803&view=diff
==============================================================================
--- dragonegg/trunk/llvm-types.cpp (original)
+++ dragonegg/trunk/llvm-types.cpp Sun Sep 26 07:53:13 2010
@@ -58,6 +58,10 @@
 #include "tree.h"
 }
 
+// NoLength - Special value used to indicate that an array has variable or
+// unknown length.
+static const uint64_t NoLength = ~(uint64_t)0;
+
 static LLVMContext &Context = getGlobalContext();
 
 //===----------------------------------------------------------------------===//
@@ -204,16 +208,16 @@
 //                       Type Conversion Utilities
 //===----------------------------------------------------------------------===//
 
-/// ArrayLengthOf - Returns the length of the given gcc array type, or ~0ULL if
-/// the array has variable or unknown length.
+/// ArrayLengthOf - Returns the length of the given gcc array type, or NoLength
+//  if the array has variable or unknown length.
 uint64_t ArrayLengthOf(tree type) {
   assert(TREE_CODE(type) == ARRAY_TYPE && "Only for array types!");
   // If the element type has variable size and the array type has variable
   // length, but by some miracle the product gives a constant size, then we
-  // also return ~0ULL here.  I can live with this, and I bet you can too!
+  // also return NoLength here.  I can live with this, and I bet you can too!
   if (!isInt64(TYPE_SIZE(type), true) ||
       !isInt64(TYPE_SIZE(TREE_TYPE(type)), true))
-    return ~0ULL;
+    return NoLength;
   // May return zero for arrays that gcc considers to have non-zero length, but
   // only if the array type has zero size (this can happen if the element type
   // has zero size), in which case the discrepancy doesn't matter.
@@ -640,7 +644,7 @@
 
   case ARRAY_TYPE: {
     uint64_t NumElts = ArrayLengthOf(type);
-    if (NumElts == ~0ULL)
+    if (NumElts == NoLength)
       return true;
     unsigned EltSizeBits = getInt64(TYPE_SIZE(TREE_TYPE(type)), true);
 
@@ -903,7 +907,7 @@
     const Type *ElementTy = ConvertType(TREE_TYPE(type));
     uint64_t NumElements = ArrayLengthOf(type);
 
-    if (NumElements == ~0ULL) // Variable length array?
+    if (NumElements == NoLength) // Variable length array?
       NumElements = 0;
 
     // Create the array type.
@@ -1917,7 +1921,7 @@
   tree GccUnionTy = 0;
   tree UnionField = 0;
   unsigned MinAlign = ~0U;
-  uint64_t BestSize = FindBiggest ? 0ULL : ~0ULL;
+  uint64_t BestSize = FindBiggest ? 0 : ~(uint64_t)0;
   for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) {
     if (TREE_CODE(Field) != FIELD_DECL) continue;
     assert(DECL_FIELD_OFFSET(Field) && integer_zerop(DECL_FIELD_OFFSET(Field))



From baldrick at free.fr  Sun Sep 26 08:47:06 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 13:47:06 -0000
Subject: [llvm-commits] [dragonegg] r114804 - in /dragonegg/trunk/x86:
	llvm-target.cpp x86_builtins
Message-ID: <20100926134706.786D42A6C12C@llvm.org>

Author: baldrick
Date: Sun Sep 26 08:47:06 2010
New Revision: 114804

URL: http://llvm.org/viewvc/llvm-project?rev=114804&view=rev
Log:
Use a switch rather than a computed goto.  With this, dragonegg
is -pedantic clean.

Added:
    dragonegg/trunk/x86/x86_builtins
Modified:
    dragonegg/trunk/x86/llvm-target.cpp

Modified: dragonegg/trunk/x86/llvm-target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=114804&r1=114803&r2=114804&view=diff
==============================================================================
--- dragonegg/trunk/x86/llvm-target.cpp (original)
+++ dragonegg/trunk/x86/llvm-target.cpp Sun Sep 26 08:47:06 2010
@@ -34,6 +34,7 @@
 #include "llvm/Intrinsics.h"
 #include "llvm/LLVMContext.h"
 #include "llvm/Module.h"
+#include "llvm/Support/ErrorHandling.h"
 
 // System headers
 #include <gmp.h>
@@ -64,8 +65,16 @@
                                                    VecTy->getNumElements()));
 }
 
+enum BuiltinCode {
+  SearchForHandler, // Builtin not seen before - search for a handler.
+#define DEFINE_BUILTIN(x) x
+#include "x86_builtins"
+#undef DEFINE_BUILTIN
+  , UnsupportedBuiltin // There is no handler for this builtin.
+};
+
 struct HandlerEntry {
-  const char *Name; void *Handler;
+  const char *Name; BuiltinCode Handler;
 };
 
 static bool LT(const HandlerEntry &E, const HandlerEntry &F) {
@@ -83,658 +92,16 @@
                                       const Type *ResultType,
                                       std::vector<Value*> &Ops) {
   static const HandlerEntry Handlers[] = {
-    // Unsupported builtins are commented out.
-    {"__builtin_ia32_addpd", &&IX86_BUILTIN_ADDPD},
-    {"__builtin_ia32_addpd256", &&IX86_BUILTIN_ADDPD256},
-    {"__builtin_ia32_addps", &&IX86_BUILTIN_ADDPS},
-    {"__builtin_ia32_addps256", &&IX86_BUILTIN_ADDPS256},
-    //{"__builtin_ia32_addsd", &&IX86_BUILTIN_ADDSD},
-    //{"__builtin_ia32_addss", &&IX86_BUILTIN_ADDSS},
-    //{"__builtin_ia32_addsubpd", &&IX86_BUILTIN_ADDSUBPD},
-    //{"__builtin_ia32_addsubpd256", &&IX86_BUILTIN_ADDSUBPD256},
-    //{"__builtin_ia32_addsubps", &&IX86_BUILTIN_ADDSUBPS},
-    //{"__builtin_ia32_addsubps256", &&IX86_BUILTIN_ADDSUBPS256},
-    //{"__builtin_ia32_aesdec128", &&IX86_BUILTIN_AESDEC128},
-    //{"__builtin_ia32_aesdeclast128", &&IX86_BUILTIN_AESDECLAST128},
-    //{"__builtin_ia32_aesenc128", &&IX86_BUILTIN_AESENC128},
-    //{"__builtin_ia32_aesenclast128", &&IX86_BUILTIN_AESENCLAST128},
-    //{"__builtin_ia32_aesimc128", &&IX86_BUILTIN_AESIMC128},
-    //{"__builtin_ia32_aeskeygenassist128", &&IX86_BUILTIN_AESKEYGENASSIST128},
-    {"__builtin_ia32_andnpd", &&IX86_BUILTIN_ANDNPD},
-    {"__builtin_ia32_andnpd256", &&IX86_BUILTIN_ANDNPD256},
-    {"__builtin_ia32_andnps", &&IX86_BUILTIN_ANDNPS},
-    {"__builtin_ia32_andnps256", &&IX86_BUILTIN_ANDNPS256},
-    {"__builtin_ia32_andpd", &&IX86_BUILTIN_ANDPD},
-    {"__builtin_ia32_andpd256", &&IX86_BUILTIN_ANDPD256},
-    {"__builtin_ia32_andps", &&IX86_BUILTIN_ANDPS},
-    {"__builtin_ia32_andps256", &&IX86_BUILTIN_ANDPS256},
-    //{"__builtin_ia32_blendpd", &&IX86_BUILTIN_BLENDPD},
-    //{"__builtin_ia32_blendpd256", &&IX86_BUILTIN_BLENDPD256},
-    //{"__builtin_ia32_blendps", &&IX86_BUILTIN_BLENDPS},
-    //{"__builtin_ia32_blendps256", &&IX86_BUILTIN_BLENDPS256},
-    //{"__builtin_ia32_blendvpd", &&IX86_BUILTIN_BLENDVPD},
-    //{"__builtin_ia32_blendvpd256", &&IX86_BUILTIN_BLENDVPD256},
-    //{"__builtin_ia32_blendvps", &&IX86_BUILTIN_BLENDVPS},
-    //{"__builtin_ia32_blendvps256", &&IX86_BUILTIN_BLENDVPS256},
-    //{"__builtin_ia32_bsrdi", &&IX86_BUILTIN_BSRDI},
-    //{"__builtin_ia32_bsrsi", &&IX86_BUILTIN_BSRSI},
-    //{"__builtin_ia32_clflush", &&IX86_BUILTIN_CLFLUSH},
-    {"__builtin_ia32_cmpeqpd", &&IX86_BUILTIN_CMPEQPD},
-    {"__builtin_ia32_cmpeqps", &&IX86_BUILTIN_CMPEQPS},
-    {"__builtin_ia32_cmpeqsd", &&IX86_BUILTIN_CMPEQSD},
-    {"__builtin_ia32_cmpeqss", &&IX86_BUILTIN_CMPEQSS},
-    {"__builtin_ia32_cmpgepd", &&IX86_BUILTIN_CMPGEPD},
-    {"__builtin_ia32_cmpgeps", &&IX86_BUILTIN_CMPGEPS},
-    {"__builtin_ia32_cmpgtpd", &&IX86_BUILTIN_CMPGTPD},
-    {"__builtin_ia32_cmpgtps", &&IX86_BUILTIN_CMPGTPS},
-    {"__builtin_ia32_cmplepd", &&IX86_BUILTIN_CMPLEPD},
-    {"__builtin_ia32_cmpleps", &&IX86_BUILTIN_CMPLEPS},
-    {"__builtin_ia32_cmplesd", &&IX86_BUILTIN_CMPLESD},
-    {"__builtin_ia32_cmpless", &&IX86_BUILTIN_CMPLESS},
-    {"__builtin_ia32_cmpltpd", &&IX86_BUILTIN_CMPLTPD},
-    {"__builtin_ia32_cmpltps", &&IX86_BUILTIN_CMPLTPS},
-    {"__builtin_ia32_cmpltsd", &&IX86_BUILTIN_CMPLTSD},
-    {"__builtin_ia32_cmpltss", &&IX86_BUILTIN_CMPLTSS},
-    {"__builtin_ia32_cmpneqpd", &&IX86_BUILTIN_CMPNEQPD},
-    {"__builtin_ia32_cmpneqps", &&IX86_BUILTIN_CMPNEQPS},
-    {"__builtin_ia32_cmpneqsd", &&IX86_BUILTIN_CMPNEQSD},
-    {"__builtin_ia32_cmpneqss", &&IX86_BUILTIN_CMPNEQSS},
-    {"__builtin_ia32_cmpngepd", &&IX86_BUILTIN_CMPNGEPD},
-    {"__builtin_ia32_cmpngeps", &&IX86_BUILTIN_CMPNGEPS},
-    //{"__builtin_ia32_cmpngess", &&IX86_BUILTIN_CMPNGESS},
-    {"__builtin_ia32_cmpngtpd", &&IX86_BUILTIN_CMPNGTPD},
-    {"__builtin_ia32_cmpngtps", &&IX86_BUILTIN_CMPNGTPS},
-    //{"__builtin_ia32_cmpngtss", &&IX86_BUILTIN_CMPNGTSS},
-    {"__builtin_ia32_cmpnlepd", &&IX86_BUILTIN_CMPNLEPD},
-    {"__builtin_ia32_cmpnleps", &&IX86_BUILTIN_CMPNLEPS},
-    {"__builtin_ia32_cmpnlesd", &&IX86_BUILTIN_CMPNLESD},
-    {"__builtin_ia32_cmpnless", &&IX86_BUILTIN_CMPNLESS},
-    {"__builtin_ia32_cmpnltpd", &&IX86_BUILTIN_CMPNLTPD},
-    {"__builtin_ia32_cmpnltps", &&IX86_BUILTIN_CMPNLTPS},
-    {"__builtin_ia32_cmpnltsd", &&IX86_BUILTIN_CMPNLTSD},
-    {"__builtin_ia32_cmpnltss", &&IX86_BUILTIN_CMPNLTSS},
-    {"__builtin_ia32_cmpordpd", &&IX86_BUILTIN_CMPORDPD},
-    {"__builtin_ia32_cmpordps", &&IX86_BUILTIN_CMPORDPS},
-    {"__builtin_ia32_cmpordsd", &&IX86_BUILTIN_CMPORDSD},
-    {"__builtin_ia32_cmpordss", &&IX86_BUILTIN_CMPORDSS},
-    //{"__builtin_ia32_cmppd", &&IX86_BUILTIN_CMPPD},
-    //{"__builtin_ia32_cmppd256", &&IX86_BUILTIN_CMPPD256},
-    //{"__builtin_ia32_cmpps", &&IX86_BUILTIN_CMPPS},
-    //{"__builtin_ia32_cmpps256", &&IX86_BUILTIN_CMPPS256},
-    //{"__builtin_ia32_cmpsd", &&IX86_BUILTIN_CMPSD},
-    //{"__builtin_ia32_cmpss", &&IX86_BUILTIN_CMPSS},
-    {"__builtin_ia32_cmpunordpd", &&IX86_BUILTIN_CMPUNORDPD},
-    {"__builtin_ia32_cmpunordps", &&IX86_BUILTIN_CMPUNORDPS},
-    {"__builtin_ia32_cmpunordsd", &&IX86_BUILTIN_CMPUNORDSD},
-    {"__builtin_ia32_cmpunordss", &&IX86_BUILTIN_CMPUNORDSS},
-    //{"__builtin_ia32_comieq", &&IX86_BUILTIN_COMIEQSS},
-    //{"__builtin_ia32_comige", &&IX86_BUILTIN_COMIGESS},
-    //{"__builtin_ia32_comigt", &&IX86_BUILTIN_COMIGTSS},
-    //{"__builtin_ia32_comile", &&IX86_BUILTIN_COMILESS},
-    //{"__builtin_ia32_comilt", &&IX86_BUILTIN_COMILTSS},
-    //{"__builtin_ia32_comineq", &&IX86_BUILTIN_COMINEQSS},
-    //{"__builtin_ia32_comisdeq", &&IX86_BUILTIN_COMIEQSD},
-    //{"__builtin_ia32_comisdge", &&IX86_BUILTIN_COMIGESD},
-    //{"__builtin_ia32_comisdgt", &&IX86_BUILTIN_COMIGTSD},
-    //{"__builtin_ia32_comisdle", &&IX86_BUILTIN_COMILESD},
-    //{"__builtin_ia32_comisdlt", &&IX86_BUILTIN_COMILTSD},
-    //{"__builtin_ia32_comisdneq", &&IX86_BUILTIN_COMINEQSD},
-    //{"__builtin_ia32_copysignpd", &&IX86_BUILTIN_CPYSGNPD},
-    //{"__builtin_ia32_copysignps", &&IX86_BUILTIN_CPYSGNPS},
-    //{"__builtin_ia32_crc32di", &&IX86_BUILTIN_CRC32DI},
-    //{"__builtin_ia32_crc32hi", &&IX86_BUILTIN_CRC32HI},
-    //{"__builtin_ia32_crc32qi", &&IX86_BUILTIN_CRC32QI},
-    //{"__builtin_ia32_crc32si", &&IX86_BUILTIN_CRC32SI},
-    //{"__builtin_ia32_cvtdq2pd", &&IX86_BUILTIN_CVTDQ2PD},
-    //{"__builtin_ia32_cvtdq2pd256", &&IX86_BUILTIN_CVTDQ2PD256},
-    //{"__builtin_ia32_cvtdq2ps", &&IX86_BUILTIN_CVTDQ2PS},
-    //{"__builtin_ia32_cvtdq2ps256", &&IX86_BUILTIN_CVTDQ2PS256},
-    //{"__builtin_ia32_cvtpd2dq", &&IX86_BUILTIN_CVTPD2DQ},
-    //{"__builtin_ia32_cvtpd2dq256", &&IX86_BUILTIN_CVTPD2DQ256},
-    //{"__builtin_ia32_cvtpd2pi", &&IX86_BUILTIN_CVTPD2PI},
-    //{"__builtin_ia32_cvtpd2ps", &&IX86_BUILTIN_CVTPD2PS},
-    //{"__builtin_ia32_cvtpd2ps256", &&IX86_BUILTIN_CVTPD2PS256},
-    //{"__builtin_ia32_cvtpi2pd", &&IX86_BUILTIN_CVTPI2PD},
-    //{"__builtin_ia32_cvtpi2ps", &&IX86_BUILTIN_CVTPI2PS},
-    //{"__builtin_ia32_cvtps2dq", &&IX86_BUILTIN_CVTPS2DQ},
-    //{"__builtin_ia32_cvtps2dq256", &&IX86_BUILTIN_CVTPS2DQ256},
-    //{"__builtin_ia32_cvtps2pd", &&IX86_BUILTIN_CVTPS2PD},
-    //{"__builtin_ia32_cvtps2pd256", &&IX86_BUILTIN_CVTPS2PD256},
-    //{"__builtin_ia32_cvtps2pi", &&IX86_BUILTIN_CVTPS2PI},
-    //{"__builtin_ia32_cvtsd2si", &&IX86_BUILTIN_CVTSD2SI},
-    //{"__builtin_ia32_cvtsd2si64", &&IX86_BUILTIN_CVTSD2SI64},
-    //{"__builtin_ia32_cvtsd2ss", &&IX86_BUILTIN_CVTSD2SS},
-    //{"__builtin_ia32_cvtsi2sd", &&IX86_BUILTIN_CVTSI2SD},
-    //{"__builtin_ia32_cvtsi2ss", &&IX86_BUILTIN_CVTSI2SS},
-    //{"__builtin_ia32_cvtsi642sd", &&IX86_BUILTIN_CVTSI642SD},
-    //{"__builtin_ia32_cvtsi642ss", &&IX86_BUILTIN_CVTSI642SS},
-    //{"__builtin_ia32_cvtss2sd", &&IX86_BUILTIN_CVTSS2SD},
-    //{"__builtin_ia32_cvtss2si", &&IX86_BUILTIN_CVTSS2SI},
-    //{"__builtin_ia32_cvtss2si64", &&IX86_BUILTIN_CVTSS2SI64},
-    //{"__builtin_ia32_cvttpd2dq", &&IX86_BUILTIN_CVTTPD2DQ},
-    //{"__builtin_ia32_cvttpd2dq256", &&IX86_BUILTIN_CVTTPD2DQ256},
-    //{"__builtin_ia32_cvttpd2pi", &&IX86_BUILTIN_CVTTPD2PI},
-    //{"__builtin_ia32_cvttps2dq", &&IX86_BUILTIN_CVTTPS2DQ},
-    //{"__builtin_ia32_cvttps2dq256", &&IX86_BUILTIN_CVTTPS2DQ256},
-    //{"__builtin_ia32_cvttps2pi", &&IX86_BUILTIN_CVTTPS2PI},
-    //{"__builtin_ia32_cvttsd2si", &&IX86_BUILTIN_CVTTSD2SI},
-    //{"__builtin_ia32_cvttsd2si64", &&IX86_BUILTIN_CVTTSD2SI64},
-    //{"__builtin_ia32_cvttss2si", &&IX86_BUILTIN_CVTTSS2SI},
-    //{"__builtin_ia32_cvttss2si64", &&IX86_BUILTIN_CVTTSS2SI64},
-    //{"__builtin_ia32_cvtudq2ps", &&IX86_BUILTIN_CVTUDQ2PS},
-    {"__builtin_ia32_divpd", &&IX86_BUILTIN_DIVPD},
-    {"__builtin_ia32_divpd256", &&IX86_BUILTIN_DIVPD256},
-    {"__builtin_ia32_divps", &&IX86_BUILTIN_DIVPS},
-    {"__builtin_ia32_divps256", &&IX86_BUILTIN_DIVPS256},
-    //{"__builtin_ia32_divsd", &&IX86_BUILTIN_DIVSD},
-    //{"__builtin_ia32_divss", &&IX86_BUILTIN_DIVSS},
-    //{"__builtin_ia32_dppd", &&IX86_BUILTIN_DPPD},
-    //{"__builtin_ia32_dpps", &&IX86_BUILTIN_DPPS},
-    //{"__builtin_ia32_dpps256", &&IX86_BUILTIN_DPPS256},
-    //{"__builtin_ia32_emms", &&IX86_BUILTIN_EMMS},
-    //{"__builtin_ia32_extrq", &&IX86_BUILTIN_EXTRQ},
-    //{"__builtin_ia32_extrqi", &&IX86_BUILTIN_EXTRQI},
-    //{"__builtin_ia32_femms", &&IX86_BUILTIN_FEMMS},
-    //{"__builtin_ia32_haddpd", &&IX86_BUILTIN_HADDPD},
-    //{"__builtin_ia32_haddpd256", &&IX86_BUILTIN_HADDPD256},
-    //{"__builtin_ia32_haddps", &&IX86_BUILTIN_HADDPS},
-    //{"__builtin_ia32_haddps256", &&IX86_BUILTIN_HADDPS256},
-    //{"__builtin_ia32_hsubpd", &&IX86_BUILTIN_HSUBPD},
-    //{"__builtin_ia32_hsubpd256", &&IX86_BUILTIN_HSUBPD256},
-    //{"__builtin_ia32_hsubps", &&IX86_BUILTIN_HSUBPS},
-    //{"__builtin_ia32_hsubps256", &&IX86_BUILTIN_HSUBPS256},
-    //{"__builtin_ia32_insertps128", &&IX86_BUILTIN_INSERTPS128},
-    //{"__builtin_ia32_insertq", &&IX86_BUILTIN_INSERTQ},
-    //{"__builtin_ia32_insertqi", &&IX86_BUILTIN_INSERTQI},
-    //{"__builtin_ia32_lddqu", &&IX86_BUILTIN_LDDQU},
-    //{"__builtin_ia32_lddqu256", &&IX86_BUILTIN_LDDQU256},
-    {"__builtin_ia32_ldmxcsr", &&IX86_BUILTIN_LDMXCSR},
-    //{"__builtin_ia32_lfence", &&IX86_BUILTIN_LFENCE},
-    {"__builtin_ia32_loaddqu", &&IX86_BUILTIN_LOADDQU},
-    //{"__builtin_ia32_loaddqu256", &&IX86_BUILTIN_LOADDQU256},
-    {"__builtin_ia32_loadhpd", &&IX86_BUILTIN_LOADHPD},
-    {"__builtin_ia32_loadhps", &&IX86_BUILTIN_LOADHPS},
-    {"__builtin_ia32_loadlpd", &&IX86_BUILTIN_LOADLPD},
-    {"__builtin_ia32_loadlps", &&IX86_BUILTIN_LOADLPS},
-    {"__builtin_ia32_loadupd", &&IX86_BUILTIN_LOADUPD},
-    //{"__builtin_ia32_loadupd256", &&IX86_BUILTIN_LOADUPD256},
-    {"__builtin_ia32_loadups", &&IX86_BUILTIN_LOADUPS},
-    //{"__builtin_ia32_loadups256", &&IX86_BUILTIN_LOADUPS256},
-    //{"__builtin_ia32_maskloadpd", &&IX86_BUILTIN_MASKLOADPD},
-    //{"__builtin_ia32_maskloadpd256", &&IX86_BUILTIN_MASKLOADPD256},
-    //{"__builtin_ia32_maskloadps", &&IX86_BUILTIN_MASKLOADPS},
-    //{"__builtin_ia32_maskloadps256", &&IX86_BUILTIN_MASKLOADPS256},
-    //{"__builtin_ia32_maskmovdqu", &&IX86_BUILTIN_MASKMOVDQU},
-    //{"__builtin_ia32_maskmovq", &&IX86_BUILTIN_MASKMOVQ},
-    //{"__builtin_ia32_maskstorepd", &&IX86_BUILTIN_MASKSTOREPD},
-    //{"__builtin_ia32_maskstorepd256", &&IX86_BUILTIN_MASKSTOREPD256},
-    //{"__builtin_ia32_maskstoreps", &&IX86_BUILTIN_MASKSTOREPS},
-    //{"__builtin_ia32_maskstoreps256", &&IX86_BUILTIN_MASKSTOREPS256},
-    //{"__builtin_ia32_maxpd", &&IX86_BUILTIN_MAXPD},
-    //{"__builtin_ia32_maxpd256", &&IX86_BUILTIN_MAXPD256},
-    //{"__builtin_ia32_maxps", &&IX86_BUILTIN_MAXPS},
-    //{"__builtin_ia32_maxps256", &&IX86_BUILTIN_MAXPS256},
-    //{"__builtin_ia32_maxsd", &&IX86_BUILTIN_MAXSD},
-    //{"__builtin_ia32_maxss", &&IX86_BUILTIN_MAXSS},
-    //{"__builtin_ia32_mfence", &&IX86_BUILTIN_MFENCE},
-    //{"__builtin_ia32_minpd", &&IX86_BUILTIN_MINPD},
-    //{"__builtin_ia32_minpd256", &&IX86_BUILTIN_MINPD256},
-    //{"__builtin_ia32_minps", &&IX86_BUILTIN_MINPS},
-    //{"__builtin_ia32_minps256", &&IX86_BUILTIN_MINPS256},
-    //{"__builtin_ia32_minsd", &&IX86_BUILTIN_MINSD},
-    //{"__builtin_ia32_minss", &&IX86_BUILTIN_MINSS},
-    //{"__builtin_ia32_monitor", &&IX86_BUILTIN_MONITOR},
-    //{"__builtin_ia32_movddup256", &&IX86_BUILTIN_MOVDDUP256},
-    {"__builtin_ia32_movhlps", &&IX86_BUILTIN_MOVHLPS},
-    {"__builtin_ia32_movlhps", &&IX86_BUILTIN_MOVLHPS},
-    //{"__builtin_ia32_movmskpd", &&IX86_BUILTIN_MOVMSKPD},
-    //{"__builtin_ia32_movmskpd256", &&IX86_BUILTIN_MOVMSKPD256},
-    //{"__builtin_ia32_movmskps", &&IX86_BUILTIN_MOVMSKPS},
-    //{"__builtin_ia32_movmskps256", &&IX86_BUILTIN_MOVMSKPS256},
-    //{"__builtin_ia32_movntdq", &&IX86_BUILTIN_MOVNTDQ},
-    //{"__builtin_ia32_movntdq256", &&IX86_BUILTIN_MOVNTDQ256},
-    //{"__builtin_ia32_movntdqa", &&IX86_BUILTIN_MOVNTDQA},
-    //{"__builtin_ia32_movnti", &&IX86_BUILTIN_MOVNTI},
-    //{"__builtin_ia32_movntpd", &&IX86_BUILTIN_MOVNTPD},
-    //{"__builtin_ia32_movntpd256", &&IX86_BUILTIN_MOVNTPD256},
-    //{"__builtin_ia32_movntps", &&IX86_BUILTIN_MOVNTPS},
-    //{"__builtin_ia32_movntps256", &&IX86_BUILTIN_MOVNTPS256},
-    //{"__builtin_ia32_movntq", &&IX86_BUILTIN_MOVNTQ},
-    //{"__builtin_ia32_movntsd", &&IX86_BUILTIN_MOVNTSD},
-    //{"__builtin_ia32_movntss", &&IX86_BUILTIN_MOVNTSS},
-    {"__builtin_ia32_movq128", &&IX86_BUILTIN_MOVQ128},
-    {"__builtin_ia32_movsd", &&IX86_BUILTIN_MOVSD},
-    {"__builtin_ia32_movshdup", &&IX86_BUILTIN_MOVSHDUP},
-    //{"__builtin_ia32_movshdup256", &&IX86_BUILTIN_MOVSHDUP256},
-    {"__builtin_ia32_movsldup", &&IX86_BUILTIN_MOVSLDUP},
-    //{"__builtin_ia32_movsldup256", &&IX86_BUILTIN_MOVSLDUP256},
-    {"__builtin_ia32_movss", &&IX86_BUILTIN_MOVSS},
-    //{"__builtin_ia32_mpsadbw128", &&IX86_BUILTIN_MPSADBW128},
-    {"__builtin_ia32_mulpd", &&IX86_BUILTIN_MULPD},
-    {"__builtin_ia32_mulpd256", &&IX86_BUILTIN_MULPD256},
-    {"__builtin_ia32_mulps", &&IX86_BUILTIN_MULPS},
-    {"__builtin_ia32_mulps256", &&IX86_BUILTIN_MULPS256},
-    //{"__builtin_ia32_mulsd", &&IX86_BUILTIN_MULSD},
-    //{"__builtin_ia32_mulss", &&IX86_BUILTIN_MULSS},
-    //{"__builtin_ia32_mwait", &&IX86_BUILTIN_MWAIT},
-    {"__builtin_ia32_orpd", &&IX86_BUILTIN_ORPD},
-    {"__builtin_ia32_orpd256", &&IX86_BUILTIN_ORPD256},
-    {"__builtin_ia32_orps", &&IX86_BUILTIN_ORPS},
-    {"__builtin_ia32_orps256", &&IX86_BUILTIN_ORPS256},
-    //{"__builtin_ia32_pabsb", &&IX86_BUILTIN_PABSB},
-    //{"__builtin_ia32_pabsb128", &&IX86_BUILTIN_PABSB128},
-    //{"__builtin_ia32_pabsd", &&IX86_BUILTIN_PABSD},
-    //{"__builtin_ia32_pabsd128", &&IX86_BUILTIN_PABSD128},
-    //{"__builtin_ia32_pabsw", &&IX86_BUILTIN_PABSW},
-    //{"__builtin_ia32_pabsw128", &&IX86_BUILTIN_PABSW128},
-    //{"__builtin_ia32_packssdw", &&IX86_BUILTIN_PACKSSDW},
-    //{"__builtin_ia32_packssdw128", &&IX86_BUILTIN_PACKSSDW128},
-    //{"__builtin_ia32_packsswb", &&IX86_BUILTIN_PACKSSWB},
-    //{"__builtin_ia32_packsswb128", &&IX86_BUILTIN_PACKSSWB128},
-    //{"__builtin_ia32_packusdw128", &&IX86_BUILTIN_PACKUSDW128},
-    //{"__builtin_ia32_packuswb", &&IX86_BUILTIN_PACKUSWB},
-    //{"__builtin_ia32_packuswb128", &&IX86_BUILTIN_PACKUSWB128},
-    {"__builtin_ia32_paddb", &&IX86_BUILTIN_PADDB},
-    {"__builtin_ia32_paddb128", &&IX86_BUILTIN_PADDB128},
-    {"__builtin_ia32_paddd", &&IX86_BUILTIN_PADDD},
-    {"__builtin_ia32_paddd128", &&IX86_BUILTIN_PADDD128},
-    {"__builtin_ia32_paddq", &&IX86_BUILTIN_PADDQ},
-    {"__builtin_ia32_paddq128", &&IX86_BUILTIN_PADDQ128},
-    //{"__builtin_ia32_paddsb", &&IX86_BUILTIN_PADDSB},
-    //{"__builtin_ia32_paddsb128", &&IX86_BUILTIN_PADDSB128},
-    //{"__builtin_ia32_paddsw", &&IX86_BUILTIN_PADDSW},
-    //{"__builtin_ia32_paddsw128", &&IX86_BUILTIN_PADDSW128},
-    //{"__builtin_ia32_paddusb", &&IX86_BUILTIN_PADDUSB},
-    //{"__builtin_ia32_paddusb128", &&IX86_BUILTIN_PADDUSB128},
-    //{"__builtin_ia32_paddusw", &&IX86_BUILTIN_PADDUSW},
-    //{"__builtin_ia32_paddusw128", &&IX86_BUILTIN_PADDUSW128},
-    {"__builtin_ia32_paddw", &&IX86_BUILTIN_PADDW},
-    {"__builtin_ia32_paddw128", &&IX86_BUILTIN_PADDW128},
-    {"__builtin_ia32_palignr", &&IX86_BUILTIN_PALIGNR},
-    {"__builtin_ia32_palignr128", &&IX86_BUILTIN_PALIGNR128},
-    {"__builtin_ia32_pand", &&IX86_BUILTIN_PAND},
-    {"__builtin_ia32_pand128", &&IX86_BUILTIN_PAND128},
-    {"__builtin_ia32_pandn", &&IX86_BUILTIN_PANDN},
-    {"__builtin_ia32_pandn128", &&IX86_BUILTIN_PANDN128},
-    //{"__builtin_ia32_pavgb", &&IX86_BUILTIN_PAVGB},
-    //{"__builtin_ia32_pavgb128", &&IX86_BUILTIN_PAVGB128},
-    //{"__builtin_ia32_pavgusb", &&IX86_BUILTIN_PAVGUSB},
-    //{"__builtin_ia32_pavgw", &&IX86_BUILTIN_PAVGW},
-    //{"__builtin_ia32_pavgw128", &&IX86_BUILTIN_PAVGW128},
-    //{"__builtin_ia32_pblendvb128", &&IX86_BUILTIN_PBLENDVB128},
-    //{"__builtin_ia32_pblendw128", &&IX86_BUILTIN_PBLENDW128},
-    //{"__builtin_ia32_pclmulqdq128", &&IX86_BUILTIN_PCLMULQDQ128},
-    //{"__builtin_ia32_pcmpeqb", &&IX86_BUILTIN_PCMPEQB},
-    //{"__builtin_ia32_pcmpeqb128", &&IX86_BUILTIN_PCMPEQB128},
-    //{"__builtin_ia32_pcmpeqd", &&IX86_BUILTIN_PCMPEQD},
-    //{"__builtin_ia32_pcmpeqd128", &&IX86_BUILTIN_PCMPEQD128},
-    //{"__builtin_ia32_pcmpeqq", &&IX86_BUILTIN_PCMPEQQ},
-    //{"__builtin_ia32_pcmpeqw", &&IX86_BUILTIN_PCMPEQW},
-    //{"__builtin_ia32_pcmpeqw128", &&IX86_BUILTIN_PCMPEQW128},
-    //{"__builtin_ia32_pcmpestri128", &&IX86_BUILTIN_PCMPESTRI128},
-    //{"__builtin_ia32_pcmpestria128", &&IX86_BUILTIN_PCMPESTRA128},
-    //{"__builtin_ia32_pcmpestric128", &&IX86_BUILTIN_PCMPESTRC128},
-    //{"__builtin_ia32_pcmpestrio128", &&IX86_BUILTIN_PCMPESTRO128},
-    //{"__builtin_ia32_pcmpestris128", &&IX86_BUILTIN_PCMPESTRS128},
-    //{"__builtin_ia32_pcmpestriz128", &&IX86_BUILTIN_PCMPESTRZ128},
-    //{"__builtin_ia32_pcmpestrm128", &&IX86_BUILTIN_PCMPESTRM128},
-    //{"__builtin_ia32_pcmpgtb", &&IX86_BUILTIN_PCMPGTB},
-    //{"__builtin_ia32_pcmpgtb128", &&IX86_BUILTIN_PCMPGTB128},
-    //{"__builtin_ia32_pcmpgtd", &&IX86_BUILTIN_PCMPGTD},
-    //{"__builtin_ia32_pcmpgtd128", &&IX86_BUILTIN_PCMPGTD128},
-    //{"__builtin_ia32_pcmpgtq", &&IX86_BUILTIN_PCMPGTQ},
-    //{"__builtin_ia32_pcmpgtw", &&IX86_BUILTIN_PCMPGTW},
-    //{"__builtin_ia32_pcmpgtw128", &&IX86_BUILTIN_PCMPGTW128},
-    //{"__builtin_ia32_pcmpistri128", &&IX86_BUILTIN_PCMPISTRI128},
-    //{"__builtin_ia32_pcmpistria128", &&IX86_BUILTIN_PCMPISTRA128},
-    //{"__builtin_ia32_pcmpistric128", &&IX86_BUILTIN_PCMPISTRC128},
-    //{"__builtin_ia32_pcmpistrio128", &&IX86_BUILTIN_PCMPISTRO128},
-    //{"__builtin_ia32_pcmpistris128", &&IX86_BUILTIN_PCMPISTRS128},
-    //{"__builtin_ia32_pcmpistriz128", &&IX86_BUILTIN_PCMPISTRZ128},
-    //{"__builtin_ia32_pcmpistrm128", &&IX86_BUILTIN_PCMPISTRM128},
-    //{"__builtin_ia32_pd256_pd", &&IX86_BUILTIN_PD256_PD},
-    //{"__builtin_ia32_pd_pd256", &&IX86_BUILTIN_PD_PD256},
-    //{"__builtin_ia32_pf2id", &&IX86_BUILTIN_PF2ID},
-    //{"__builtin_ia32_pf2iw", &&IX86_BUILTIN_PF2IW},
-    //{"__builtin_ia32_pfacc", &&IX86_BUILTIN_PFACC},
-    //{"__builtin_ia32_pfadd", &&IX86_BUILTIN_PFADD},
-    //{"__builtin_ia32_pfcmpeq", &&IX86_BUILTIN_PFCMPEQ},
-    //{"__builtin_ia32_pfcmpge", &&IX86_BUILTIN_PFCMPGE},
-    //{"__builtin_ia32_pfcmpgt", &&IX86_BUILTIN_PFCMPGT},
-    //{"__builtin_ia32_pfmax", &&IX86_BUILTIN_PFMAX},
-    //{"__builtin_ia32_pfmin", &&IX86_BUILTIN_PFMIN},
-    //{"__builtin_ia32_pfmul", &&IX86_BUILTIN_PFMUL},
-    //{"__builtin_ia32_pfnacc", &&IX86_BUILTIN_PFNACC},
-    //{"__builtin_ia32_pfpnacc", &&IX86_BUILTIN_PFPNACC},
-    //{"__builtin_ia32_pfrcp", &&IX86_BUILTIN_PFRCP},
-    //{"__builtin_ia32_pfrcpit1", &&IX86_BUILTIN_PFRCPIT1},
-    //{"__builtin_ia32_pfrcpit2", &&IX86_BUILTIN_PFRCPIT2},
-    //{"__builtin_ia32_pfrsqit1", &&IX86_BUILTIN_PFRSQIT1},
-    //{"__builtin_ia32_pfrsqrt", &&IX86_BUILTIN_PFRSQRT},
-    //{"__builtin_ia32_pfsub", &&IX86_BUILTIN_PFSUB},
-    //{"__builtin_ia32_pfsubr", &&IX86_BUILTIN_PFSUBR},
-    //{"__builtin_ia32_phaddd", &&IX86_BUILTIN_PHADDD},
-    //{"__builtin_ia32_phaddd128", &&IX86_BUILTIN_PHADDD128},
-    //{"__builtin_ia32_phaddsw", &&IX86_BUILTIN_PHADDSW},
-    //{"__builtin_ia32_phaddsw128", &&IX86_BUILTIN_PHADDSW128},
-    //{"__builtin_ia32_phaddw", &&IX86_BUILTIN_PHADDW},
-    //{"__builtin_ia32_phaddw128", &&IX86_BUILTIN_PHADDW128},
-    //{"__builtin_ia32_phminposuw128", &&IX86_BUILTIN_PHMINPOSUW128},
-    //{"__builtin_ia32_phsubd", &&IX86_BUILTIN_PHSUBD},
-    //{"__builtin_ia32_phsubd128", &&IX86_BUILTIN_PHSUBD128},
-    //{"__builtin_ia32_phsubsw", &&IX86_BUILTIN_PHSUBSW},
-    //{"__builtin_ia32_phsubsw128", &&IX86_BUILTIN_PHSUBSW128},
-    //{"__builtin_ia32_phsubw", &&IX86_BUILTIN_PHSUBW},
-    //{"__builtin_ia32_phsubw128", &&IX86_BUILTIN_PHSUBW128},
-    //{"__builtin_ia32_pi2fd", &&IX86_BUILTIN_PI2FD},
-    //{"__builtin_ia32_pi2fw", &&IX86_BUILTIN_PI2FW},
-    //{"__builtin_ia32_pmaddubsw", &&IX86_BUILTIN_PMADDUBSW},
-    //{"__builtin_ia32_pmaddubsw128", &&IX86_BUILTIN_PMADDUBSW128},
-    //{"__builtin_ia32_pmaddwd", &&IX86_BUILTIN_PMADDWD},
-    //{"__builtin_ia32_pmaddwd128", &&IX86_BUILTIN_PMADDWD128},
-    //{"__builtin_ia32_pmaxsb128", &&IX86_BUILTIN_PMAXSB128},
-    //{"__builtin_ia32_pmaxsd128", &&IX86_BUILTIN_PMAXSD128},
-    //{"__builtin_ia32_pmaxsw", &&IX86_BUILTIN_PMAXSW},
-    //{"__builtin_ia32_pmaxsw128", &&IX86_BUILTIN_PMAXSW128},
-    //{"__builtin_ia32_pmaxub", &&IX86_BUILTIN_PMAXUB},
-    //{"__builtin_ia32_pmaxub128", &&IX86_BUILTIN_PMAXUB128},
-    //{"__builtin_ia32_pmaxud128", &&IX86_BUILTIN_PMAXUD128},
-    //{"__builtin_ia32_pmaxuw128", &&IX86_BUILTIN_PMAXUW128},
-    //{"__builtin_ia32_pminsb128", &&IX86_BUILTIN_PMINSB128},
-    //{"__builtin_ia32_pminsd128", &&IX86_BUILTIN_PMINSD128},
-    //{"__builtin_ia32_pminsw", &&IX86_BUILTIN_PMINSW},
-    //{"__builtin_ia32_pminsw128", &&IX86_BUILTIN_PMINSW128},
-    //{"__builtin_ia32_pminub", &&IX86_BUILTIN_PMINUB},
-    //{"__builtin_ia32_pminub128", &&IX86_BUILTIN_PMINUB128},
-    //{"__builtin_ia32_pminud128", &&IX86_BUILTIN_PMINUD128},
-    //{"__builtin_ia32_pminuw128", &&IX86_BUILTIN_PMINUW128},
-    //{"__builtin_ia32_pmovmskb", &&IX86_BUILTIN_PMOVMSKB},
-    //{"__builtin_ia32_pmovmskb128", &&IX86_BUILTIN_PMOVMSKB128},
-    //{"__builtin_ia32_pmovsxbd128", &&IX86_BUILTIN_PMOVSXBD128},
-    //{"__builtin_ia32_pmovsxbq128", &&IX86_BUILTIN_PMOVSXBQ128},
-    //{"__builtin_ia32_pmovsxbw128", &&IX86_BUILTIN_PMOVSXBW128},
-    //{"__builtin_ia32_pmovsxdq128", &&IX86_BUILTIN_PMOVSXDQ128},
-    //{"__builtin_ia32_pmovsxwd128", &&IX86_BUILTIN_PMOVSXWD128},
-    //{"__builtin_ia32_pmovsxwq128", &&IX86_BUILTIN_PMOVSXWQ128},
-    //{"__builtin_ia32_pmovzxbd128", &&IX86_BUILTIN_PMOVZXBD128},
-    //{"__builtin_ia32_pmovzxbq128", &&IX86_BUILTIN_PMOVZXBQ128},
-    //{"__builtin_ia32_pmovzxbw128", &&IX86_BUILTIN_PMOVZXBW128},
-    //{"__builtin_ia32_pmovzxdq128", &&IX86_BUILTIN_PMOVZXDQ128},
-    //{"__builtin_ia32_pmovzxwd128", &&IX86_BUILTIN_PMOVZXWD128},
-    //{"__builtin_ia32_pmovzxwq128", &&IX86_BUILTIN_PMOVZXWQ128},
-    //{"__builtin_ia32_pmuldq128", &&IX86_BUILTIN_PMULDQ128},
-    //{"__builtin_ia32_pmulhrsw", &&IX86_BUILTIN_PMULHRSW},
-    //{"__builtin_ia32_pmulhrsw128", &&IX86_BUILTIN_PMULHRSW128},
-    //{"__builtin_ia32_pmulhrw", &&IX86_BUILTIN_PMULHRW},
-    //{"__builtin_ia32_pmulhuw", &&IX86_BUILTIN_PMULHUW},
-    //{"__builtin_ia32_pmulhuw128", &&IX86_BUILTIN_PMULHUW128},
-    //{"__builtin_ia32_pmulhw", &&IX86_BUILTIN_PMULHW},
-    //{"__builtin_ia32_pmulhw128", &&IX86_BUILTIN_PMULHW128},
-    {"__builtin_ia32_pmulld128", &&IX86_BUILTIN_PMULLD128},
-    {"__builtin_ia32_pmullw", &&IX86_BUILTIN_PMULLW},
-    {"__builtin_ia32_pmullw128", &&IX86_BUILTIN_PMULLW128},
-    //{"__builtin_ia32_pmuludq", &&IX86_BUILTIN_PMULUDQ},
-    //{"__builtin_ia32_pmuludq128", &&IX86_BUILTIN_PMULUDQ128},
-    {"__builtin_ia32_por", &&IX86_BUILTIN_POR},
-    {"__builtin_ia32_por128", &&IX86_BUILTIN_POR128},
-    //{"__builtin_ia32_ps256_ps", &&IX86_BUILTIN_PS256_PS},
-    //{"__builtin_ia32_psadbw", &&IX86_BUILTIN_PSADBW},
-    //{"__builtin_ia32_psadbw128", &&IX86_BUILTIN_PSADBW128},
-    //{"__builtin_ia32_pshufb", &&IX86_BUILTIN_PSHUFB},
-    //{"__builtin_ia32_pshufb128", &&IX86_BUILTIN_PSHUFB128},
-    {"__builtin_ia32_pshufd", &&IX86_BUILTIN_PSHUFD},
-    {"__builtin_ia32_pshufhw", &&IX86_BUILTIN_PSHUFHW},
-    {"__builtin_ia32_pshuflw", &&IX86_BUILTIN_PSHUFLW},
-    {"__builtin_ia32_pshufw", &&IX86_BUILTIN_PSHUFW},
-    //{"__builtin_ia32_psignb", &&IX86_BUILTIN_PSIGNB},
-    //{"__builtin_ia32_psignb128", &&IX86_BUILTIN_PSIGNB128},
-    //{"__builtin_ia32_psignd", &&IX86_BUILTIN_PSIGND},
-    //{"__builtin_ia32_psignd128", &&IX86_BUILTIN_PSIGND128},
-    //{"__builtin_ia32_psignw", &&IX86_BUILTIN_PSIGNW},
-    //{"__builtin_ia32_psignw128", &&IX86_BUILTIN_PSIGNW128},
-    //{"__builtin_ia32_pslld", &&IX86_BUILTIN_PSLLD},
-    //{"__builtin_ia32_pslld128", &&IX86_BUILTIN_PSLLD128},
-    //{"__builtin_ia32_pslldi", &&IX86_BUILTIN_PSLLDI},
-    //{"__builtin_ia32_pslldi128", &&IX86_BUILTIN_PSLLDI128},
-    //{"__builtin_ia32_pslldqi128", &&IX86_BUILTIN_PSLLDQI128},
-    //{"__builtin_ia32_psllq", &&IX86_BUILTIN_PSLLQ},
-    //{"__builtin_ia32_psllq128", &&IX86_BUILTIN_PSLLQ128},
-    //{"__builtin_ia32_psllqi", &&IX86_BUILTIN_PSLLQI},
-    //{"__builtin_ia32_psllqi128", &&IX86_BUILTIN_PSLLQI128},
-    //{"__builtin_ia32_psllw", &&IX86_BUILTIN_PSLLW},
-    //{"__builtin_ia32_psllw128", &&IX86_BUILTIN_PSLLW128},
-    //{"__builtin_ia32_psllwi", &&IX86_BUILTIN_PSLLWI},
-    //{"__builtin_ia32_psllwi128", &&IX86_BUILTIN_PSLLWI128},
-    //{"__builtin_ia32_ps_ps256", &&IX86_BUILTIN_PS_PS256},
-    //{"__builtin_ia32_psrad", &&IX86_BUILTIN_PSRAD},
-    //{"__builtin_ia32_psrad128", &&IX86_BUILTIN_PSRAD128},
-    //{"__builtin_ia32_psradi", &&IX86_BUILTIN_PSRADI},
-    //{"__builtin_ia32_psradi128", &&IX86_BUILTIN_PSRADI128},
-    //{"__builtin_ia32_psraw", &&IX86_BUILTIN_PSRAW},
-    //{"__builtin_ia32_psraw128", &&IX86_BUILTIN_PSRAW128},
-    //{"__builtin_ia32_psrawi", &&IX86_BUILTIN_PSRAWI},
-    //{"__builtin_ia32_psrawi128", &&IX86_BUILTIN_PSRAWI128},
-    //{"__builtin_ia32_psrld", &&IX86_BUILTIN_PSRLD},
-    //{"__builtin_ia32_psrld128", &&IX86_BUILTIN_PSRLD128},
-    //{"__builtin_ia32_psrldi", &&IX86_BUILTIN_PSRLDI},
-    //{"__builtin_ia32_psrldi128", &&IX86_BUILTIN_PSRLDI128},
-    //{"__builtin_ia32_psrldqi128", &&IX86_BUILTIN_PSRLDQI128},
-    //{"__builtin_ia32_psrlq", &&IX86_BUILTIN_PSRLQ},
-    //{"__builtin_ia32_psrlq128", &&IX86_BUILTIN_PSRLQ128},
-    //{"__builtin_ia32_psrlqi", &&IX86_BUILTIN_PSRLQI},
-    //{"__builtin_ia32_psrlqi128", &&IX86_BUILTIN_PSRLQI128},
-    //{"__builtin_ia32_psrlw", &&IX86_BUILTIN_PSRLW},
-    //{"__builtin_ia32_psrlw128", &&IX86_BUILTIN_PSRLW128},
-    //{"__builtin_ia32_psrlwi", &&IX86_BUILTIN_PSRLWI},
-    //{"__builtin_ia32_psrlwi128", &&IX86_BUILTIN_PSRLWI128},
-    {"__builtin_ia32_psubb", &&IX86_BUILTIN_PSUBB},
-    {"__builtin_ia32_psubb128", &&IX86_BUILTIN_PSUBB128},
-    {"__builtin_ia32_psubd", &&IX86_BUILTIN_PSUBD},
-    {"__builtin_ia32_psubd128", &&IX86_BUILTIN_PSUBD128},
-    {"__builtin_ia32_psubq", &&IX86_BUILTIN_PSUBQ},
-    {"__builtin_ia32_psubq128", &&IX86_BUILTIN_PSUBQ128},
-    //{"__builtin_ia32_psubsb", &&IX86_BUILTIN_PSUBSB},
-    //{"__builtin_ia32_psubsb128", &&IX86_BUILTIN_PSUBSB128},
-    //{"__builtin_ia32_psubsw", &&IX86_BUILTIN_PSUBSW},
-    //{"__builtin_ia32_psubsw128", &&IX86_BUILTIN_PSUBSW128},
-    //{"__builtin_ia32_psubusb", &&IX86_BUILTIN_PSUBUSB},
-    //{"__builtin_ia32_psubusb128", &&IX86_BUILTIN_PSUBUSB128},
-    //{"__builtin_ia32_psubusw", &&IX86_BUILTIN_PSUBUSW},
-    //{"__builtin_ia32_psubusw128", &&IX86_BUILTIN_PSUBUSW128},
-    {"__builtin_ia32_psubw", &&IX86_BUILTIN_PSUBW},
-    {"__builtin_ia32_psubw128", &&IX86_BUILTIN_PSUBW128},
-    //{"__builtin_ia32_pswapdsf", &&IX86_BUILTIN_PSWAPDSF},
-    //{"__builtin_ia32_pswapdsi", &&IX86_BUILTIN_PSWAPDSI},
-    //{"__builtin_ia32_ptestc128", &&IX86_BUILTIN_PTESTC},
-    //{"__builtin_ia32_ptestc256", &&IX86_BUILTIN_PTESTC256},
-    //{"__builtin_ia32_ptestnzc128", &&IX86_BUILTIN_PTESTNZC},
-    //{"__builtin_ia32_ptestnzc256", &&IX86_BUILTIN_PTESTNZC256},
-    //{"__builtin_ia32_ptestz128", &&IX86_BUILTIN_PTESTZ},
-    //{"__builtin_ia32_ptestz256", &&IX86_BUILTIN_PTESTZ256},
-    {"__builtin_ia32_punpckhbw", &&IX86_BUILTIN_PUNPCKHBW},
-    {"__builtin_ia32_punpckhbw128", &&IX86_BUILTIN_PUNPCKHBW128},
-    {"__builtin_ia32_punpckhdq", &&IX86_BUILTIN_PUNPCKHDQ},
-    {"__builtin_ia32_punpckhdq128", &&IX86_BUILTIN_PUNPCKHDQ128},
-    {"__builtin_ia32_punpckhqdq128", &&IX86_BUILTIN_PUNPCKHQDQ128},
-    {"__builtin_ia32_punpckhwd", &&IX86_BUILTIN_PUNPCKHWD},
-    {"__builtin_ia32_punpckhwd128", &&IX86_BUILTIN_PUNPCKHWD128},
-    {"__builtin_ia32_punpcklbw", &&IX86_BUILTIN_PUNPCKLBW},
-    {"__builtin_ia32_punpcklbw128", &&IX86_BUILTIN_PUNPCKLBW128},
-    {"__builtin_ia32_punpckldq", &&IX86_BUILTIN_PUNPCKLDQ},
-    {"__builtin_ia32_punpckldq128", &&IX86_BUILTIN_PUNPCKLDQ128},
-    {"__builtin_ia32_punpcklqdq128", &&IX86_BUILTIN_PUNPCKLQDQ128},
-    {"__builtin_ia32_punpcklwd", &&IX86_BUILTIN_PUNPCKLWD},
-    {"__builtin_ia32_punpcklwd128", &&IX86_BUILTIN_PUNPCKLWD128},
-    {"__builtin_ia32_pxor", &&IX86_BUILTIN_PXOR},
-    {"__builtin_ia32_pxor128", &&IX86_BUILTIN_PXOR128},
-    //{"__builtin_ia32_rcpps", &&IX86_BUILTIN_RCPPS},
-    //{"__builtin_ia32_rcpps256", &&IX86_BUILTIN_RCPPS256},
-    //{"__builtin_ia32_rcpss", &&IX86_BUILTIN_RCPSS},
-    //{"__builtin_ia32_rdpmc", &&IX86_BUILTIN_RDPMC},
-    //{"__builtin_ia32_rdtsc", &&IX86_BUILTIN_RDTSC},
-    //{"__builtin_ia32_rdtscp", &&IX86_BUILTIN_RDTSCP},
-    //{"__builtin_ia32_rolhi", &&IX86_BUILTIN_ROLHI},
-    //{"__builtin_ia32_rolqi", &&IX86_BUILTIN_ROLQI},
-    //{"__builtin_ia32_rorhi", &&IX86_BUILTIN_RORHI},
-    //{"__builtin_ia32_rorqi", &&IX86_BUILTIN_RORQI},
-    //{"__builtin_ia32_roundpd", &&IX86_BUILTIN_ROUNDPD},
-    //{"__builtin_ia32_roundpd256", &&IX86_BUILTIN_ROUNDPD256},
-    //{"__builtin_ia32_roundps", &&IX86_BUILTIN_ROUNDPS},
-    //{"__builtin_ia32_roundps256", &&IX86_BUILTIN_ROUNDPS256},
-    //{"__builtin_ia32_roundsd", &&IX86_BUILTIN_ROUNDSD},
-    //{"__builtin_ia32_roundss", &&IX86_BUILTIN_ROUNDSS},
-    //{"__builtin_ia32_rsqrtf", &&IX86_BUILTIN_RSQRTF},
-    //{"__builtin_ia32_rsqrtps", &&IX86_BUILTIN_RSQRTPS},
-    //{"__builtin_ia32_rsqrtps256", &&IX86_BUILTIN_RSQRTPS256},
-    //{"__builtin_ia32_rsqrtps_nr", &&IX86_BUILTIN_RSQRTPS_NR},
-    //{"__builtin_ia32_rsqrtps_nr256", &&IX86_BUILTIN_RSQRTPS_NR256},
-    //{"__builtin_ia32_rsqrtss", &&IX86_BUILTIN_RSQRTSS},
-    //{"__builtin_ia32_sfence", &&IX86_BUILTIN_SFENCE},
-    {"__builtin_ia32_shufpd", &&IX86_BUILTIN_SHUFPD},
-    //{"__builtin_ia32_shufpd256", &&IX86_BUILTIN_SHUFPD256},
-    {"__builtin_ia32_shufps", &&IX86_BUILTIN_SHUFPS},
-    //{"__builtin_ia32_shufps256", &&IX86_BUILTIN_SHUFPS256},
-    //{"__builtin_ia32_si256_si", &&IX86_BUILTIN_SI256_SI},
-    //{"__builtin_ia32_si_si256", &&IX86_BUILTIN_SI_SI256},
-    //{"__builtin_ia32_sqrtpd", &&IX86_BUILTIN_SQRTPD},
-    //{"__builtin_ia32_sqrtpd256", &&IX86_BUILTIN_SQRTPD256},
-    //{"__builtin_ia32_sqrtps", &&IX86_BUILTIN_SQRTPS},
-    //{"__builtin_ia32_sqrtps256", &&IX86_BUILTIN_SQRTPS256},
-    //{"__builtin_ia32_sqrtps_nr", &&IX86_BUILTIN_SQRTPS_NR},
-    //{"__builtin_ia32_sqrtps_nr256", &&IX86_BUILTIN_SQRTPS_NR256},
-    //{"__builtin_ia32_sqrtsd", &&IX86_BUILTIN_SQRTSD},
-    //{"__builtin_ia32_sqrtss", &&IX86_BUILTIN_SQRTSS},
-    {"__builtin_ia32_stmxcsr", &&IX86_BUILTIN_STMXCSR},
-    {"__builtin_ia32_storedqu", &&IX86_BUILTIN_STOREDQU},
-    //{"__builtin_ia32_storedqu256", &&IX86_BUILTIN_STOREDQU256},
-    {"__builtin_ia32_storehps", &&IX86_BUILTIN_STOREHPS},
-    {"__builtin_ia32_storelps", &&IX86_BUILTIN_STORELPS},
-    {"__builtin_ia32_storeupd", &&IX86_BUILTIN_STOREUPD},
-    //{"__builtin_ia32_storeupd256", &&IX86_BUILTIN_STOREUPD256},
-    {"__builtin_ia32_storeups", &&IX86_BUILTIN_STOREUPS},
-    //{"__builtin_ia32_storeups256", &&IX86_BUILTIN_STOREUPS256},
-    {"__builtin_ia32_subpd", &&IX86_BUILTIN_SUBPD},
-    {"__builtin_ia32_subpd256", &&IX86_BUILTIN_SUBPD256},
-    {"__builtin_ia32_subps", &&IX86_BUILTIN_SUBPS},
-    {"__builtin_ia32_subps256", &&IX86_BUILTIN_SUBPS256},
-    //{"__builtin_ia32_subsd", &&IX86_BUILTIN_SUBSD},
-    //{"__builtin_ia32_subss", &&IX86_BUILTIN_SUBSS},
-    //{"__builtin_ia32_ucomieq", &&IX86_BUILTIN_UCOMIEQSS},
-    //{"__builtin_ia32_ucomige", &&IX86_BUILTIN_UCOMIGESS},
-    //{"__builtin_ia32_ucomigt", &&IX86_BUILTIN_UCOMIGTSS},
-    //{"__builtin_ia32_ucomile", &&IX86_BUILTIN_UCOMILESS},
-    //{"__builtin_ia32_ucomilt", &&IX86_BUILTIN_UCOMILTSS},
-    //{"__builtin_ia32_ucomineq", &&IX86_BUILTIN_UCOMINEQSS},
-    //{"__builtin_ia32_ucomisdeq", &&IX86_BUILTIN_UCOMIEQSD},
-    //{"__builtin_ia32_ucomisdge", &&IX86_BUILTIN_UCOMIGESD},
-    //{"__builtin_ia32_ucomisdgt", &&IX86_BUILTIN_UCOMIGTSD},
-    //{"__builtin_ia32_ucomisdle", &&IX86_BUILTIN_UCOMILESD},
-    //{"__builtin_ia32_ucomisdlt", &&IX86_BUILTIN_UCOMILTSD},
-    //{"__builtin_ia32_ucomisdneq", &&IX86_BUILTIN_UCOMINEQSD},
-    {"__builtin_ia32_unpckhpd", &&IX86_BUILTIN_UNPCKHPD},
-    //{"__builtin_ia32_unpckhpd256", &&IX86_BUILTIN_UNPCKHPD256},
-    {"__builtin_ia32_unpckhps", &&IX86_BUILTIN_UNPCKHPS},
-    //{"__builtin_ia32_unpckhps256", &&IX86_BUILTIN_UNPCKHPS256},
-    {"__builtin_ia32_unpcklpd", &&IX86_BUILTIN_UNPCKLPD},
-    //{"__builtin_ia32_unpcklpd256", &&IX86_BUILTIN_UNPCKLPD256},
-    {"__builtin_ia32_unpcklps", &&IX86_BUILTIN_UNPCKLPS},
-    //{"__builtin_ia32_unpcklps256", &&IX86_BUILTIN_UNPCKLPS256},
-    //{"__builtin_ia32_vbroadcastf128_pd256", &&IX86_BUILTIN_VBROADCASTPD256},
-    //{"__builtin_ia32_vbroadcastf128_ps256", &&IX86_BUILTIN_VBROADCASTPS256},
-    //{"__builtin_ia32_vbroadcastsd256", &&IX86_BUILTIN_VBROADCASTSD256},
-    //{"__builtin_ia32_vbroadcastss", &&IX86_BUILTIN_VBROADCASTSS},
-    //{"__builtin_ia32_vbroadcastss256", &&IX86_BUILTIN_VBROADCASTSS256},
-    {"__builtin_ia32_vec_ext_v16qi", &&IX86_BUILTIN_VEC_EXT_V16QI},
-    {"__builtin_ia32_vec_ext_v2df", &&IX86_BUILTIN_VEC_EXT_V2DF},
-    {"__builtin_ia32_vec_ext_v2di", &&IX86_BUILTIN_VEC_EXT_V2DI},
-    {"__builtin_ia32_vec_ext_v2si", &&IX86_BUILTIN_VEC_EXT_V2SI},
-    {"__builtin_ia32_vec_ext_v4hi", &&IX86_BUILTIN_VEC_EXT_V4HI},
-    {"__builtin_ia32_vec_ext_v4sf", &&IX86_BUILTIN_VEC_EXT_V4SF},
-    {"__builtin_ia32_vec_ext_v4si", &&IX86_BUILTIN_VEC_EXT_V4SI},
-    {"__builtin_ia32_vec_ext_v8hi", &&IX86_BUILTIN_VEC_EXT_V8HI},
-    {"__builtin_ia32_vec_init_v2si", &&IX86_BUILTIN_VEC_INIT_V2SI},
-    {"__builtin_ia32_vec_init_v4hi", &&IX86_BUILTIN_VEC_INIT_V4HI},
-    {"__builtin_ia32_vec_init_v8qi", &&IX86_BUILTIN_VEC_INIT_V8QI},
-    //{"__builtin_ia32_vec_pack_sfix", &&IX86_BUILTIN_VEC_PACK_SFIX},
-    {"__builtin_ia32_vec_set_v16qi", &&IX86_BUILTIN_VEC_SET_V16QI},
-    {"__builtin_ia32_vec_set_v2di", &&IX86_BUILTIN_VEC_SET_V2DI},
-    {"__builtin_ia32_vec_set_v4hi", &&IX86_BUILTIN_VEC_SET_V4HI},
-    //{"__builtin_ia32_vec_set_v4sf", &&IX86_BUILTIN_VEC_SET_V4SF},
-    {"__builtin_ia32_vec_set_v4si", &&IX86_BUILTIN_VEC_SET_V4SI},
-    {"__builtin_ia32_vec_set_v8hi", &&IX86_BUILTIN_VEC_SET_V8HI},
-    //{"__builtin_ia32_vextractf128_pd256", &&IX86_BUILTIN_EXTRACTF128PD256},
-    //{"__builtin_ia32_vextractf128_ps256", &&IX86_BUILTIN_EXTRACTF128PS256},
-    //{"__builtin_ia32_vextractf128_si256", &&IX86_BUILTIN_EXTRACTF128SI256},
-    //{"__builtin_ia32_vfmaddpd", &&IX86_BUILTIN_VFMADDPD},
-    //{"__builtin_ia32_vfmaddpd256", &&IX86_BUILTIN_VFMADDPD256},
-    //{"__builtin_ia32_vfmaddps", &&IX86_BUILTIN_VFMADDPS},
-    //{"__builtin_ia32_vfmaddps256", &&IX86_BUILTIN_VFMADDPS256},
-    //{"__builtin_ia32_vfmaddsd", &&IX86_BUILTIN_VFMADDSD},
-    //{"__builtin_ia32_vfmaddss", &&IX86_BUILTIN_VFMADDSS},
-    //{"__builtin_ia32_vfmaddsubpd", &&IX86_BUILTIN_VFMADDSUBPD},
-    //{"__builtin_ia32_vfmaddsubpd256", &&IX86_BUILTIN_VFMADDSUBPD256},
-    //{"__builtin_ia32_vfmaddsubps", &&IX86_BUILTIN_VFMADDSUBPS},
-    //{"__builtin_ia32_vfmaddsubps256", &&IX86_BUILTIN_VFMADDSUBPS256},
-    //{"__builtin_ia32_vfmsubaddpd", &&IX86_BUILTIN_VFMSUBADDPD},
-    //{"__builtin_ia32_vfmsubaddpd256", &&IX86_BUILTIN_VFMSUBADDPD256},
-    //{"__builtin_ia32_vfmsubaddps", &&IX86_BUILTIN_VFMSUBADDPS},
-    //{"__builtin_ia32_vfmsubaddps256", &&IX86_BUILTIN_VFMSUBADDPS256},
-    //{"__builtin_ia32_vfmsubpd", &&IX86_BUILTIN_VFMSUBPD},
-    //{"__builtin_ia32_vfmsubpd256", &&IX86_BUILTIN_VFMSUBPD256},
-    //{"__builtin_ia32_vfmsubps", &&IX86_BUILTIN_VFMSUBPS},
-    //{"__builtin_ia32_vfmsubps256", &&IX86_BUILTIN_VFMSUBPS256},
-    //{"__builtin_ia32_vfmsubsd", &&IX86_BUILTIN_VFMSUBSD},
-    //{"__builtin_ia32_vfmsubss", &&IX86_BUILTIN_VFMSUBSS},
-    //{"__builtin_ia32_vfnmaddpd", &&IX86_BUILTIN_VFNMADDPD},
-    //{"__builtin_ia32_vfnmaddpd256", &&IX86_BUILTIN_VFNMADDPD256},
-    //{"__builtin_ia32_vfnmaddps", &&IX86_BUILTIN_VFNMADDPS},
-    //{"__builtin_ia32_vfnmaddps256", &&IX86_BUILTIN_VFNMADDPS256},
-    //{"__builtin_ia32_vfnmaddsd", &&IX86_BUILTIN_VFNMADDSD},
-    //{"__builtin_ia32_vfnmaddss", &&IX86_BUILTIN_VFNMADDSS},
-    //{"__builtin_ia32_vfnmsubpd", &&IX86_BUILTIN_VFNMSUBPD},
-    //{"__builtin_ia32_vfnmsubpd256", &&IX86_BUILTIN_VFNMSUBPD256},
-    //{"__builtin_ia32_vfnmsubps", &&IX86_BUILTIN_VFNMSUBPS},
-    //{"__builtin_ia32_vfnmsubps256", &&IX86_BUILTIN_VFNMSUBPS256},
-    //{"__builtin_ia32_vfnmsubsd", &&IX86_BUILTIN_VFNMSUBSD},
-    //{"__builtin_ia32_vfnmsubss", &&IX86_BUILTIN_VFNMSUBSS},
-    //{"__builtin_ia32_vinsertf128_pd256", &&IX86_BUILTIN_VINSERTF128PD256},
-    //{"__builtin_ia32_vinsertf128_ps256", &&IX86_BUILTIN_VINSERTF128PS256},
-    //{"__builtin_ia32_vinsertf128_si256", &&IX86_BUILTIN_VINSERTF128SI256},
-    //{"__builtin_ia32_vperm2f128_pd256", &&IX86_BUILTIN_VPERM2F128PD256},
-    //{"__builtin_ia32_vperm2f128_ps256", &&IX86_BUILTIN_VPERM2F128PS256},
-    //{"__builtin_ia32_vperm2f128_si256", &&IX86_BUILTIN_VPERM2F128SI256},
-    //{"__builtin_ia32_vpermilpd", &&IX86_BUILTIN_VPERMILPD},
-    //{"__builtin_ia32_vpermilpd256", &&IX86_BUILTIN_VPERMILPD256},
-    //{"__builtin_ia32_vpermilps", &&IX86_BUILTIN_VPERMILPS},
-    //{"__builtin_ia32_vpermilps256", &&IX86_BUILTIN_VPERMILPS256},
-    //{"__builtin_ia32_vpermilvarpd", &&IX86_BUILTIN_VPERMILVARPD},
-    //{"__builtin_ia32_vpermilvarpd256", &&IX86_BUILTIN_VPERMILVARPD256},
-    //{"__builtin_ia32_vpermilvarps", &&IX86_BUILTIN_VPERMILVARPS},
-    //{"__builtin_ia32_vpermilvarps256", &&IX86_BUILTIN_VPERMILVARPS256},
-    //{"__builtin_ia32_vtestcpd", &&IX86_BUILTIN_VTESTCPD},
-    //{"__builtin_ia32_vtestcpd256", &&IX86_BUILTIN_VTESTCPD256},
-    //{"__builtin_ia32_vtestcps", &&IX86_BUILTIN_VTESTCPS},
-    //{"__builtin_ia32_vtestcps256", &&IX86_BUILTIN_VTESTCPS256},
-    //{"__builtin_ia32_vtestnzcpd", &&IX86_BUILTIN_VTESTNZCPD},
-    //{"__builtin_ia32_vtestnzcpd256", &&IX86_BUILTIN_VTESTNZCPD256},
-    //{"__builtin_ia32_vtestnzcps", &&IX86_BUILTIN_VTESTNZCPS},
-    //{"__builtin_ia32_vtestnzcps256", &&IX86_BUILTIN_VTESTNZCPS256},
-    //{"__builtin_ia32_vtestzpd", &&IX86_BUILTIN_VTESTZPD},
-    //{"__builtin_ia32_vtestzpd256", &&IX86_BUILTIN_VTESTZPD256},
-    //{"__builtin_ia32_vtestzps", &&IX86_BUILTIN_VTESTZPS},
-    //{"__builtin_ia32_vtestzps256", &&IX86_BUILTIN_VTESTZPS256},
-    //{"__builtin_ia32_vzeroall", &&IX86_BUILTIN_VZEROALL},
-    {"__builtin_ia32_xorpd", &&IX86_BUILTIN_XORPD},
-    {"__builtin_ia32_xorpd256", &&IX86_BUILTIN_XORPD256},
-    {"__builtin_ia32_xorps", &&IX86_BUILTIN_XORPS},
-    {"__builtin_ia32_xorps256", &&IX86_BUILTIN_XORPS256},
+#define DEFINE_BUILTIN(x) {#x, x}
+#include "x86_builtins"
+#undef DEFINE_BUILTIN
   };
 
-  static std::vector<void*> FunctionCodeCache;
+  static std::vector<BuiltinCode> FunctionCodeCache;
   if (FunctionCodeCache.size() <= DECL_FUNCTION_CODE(fndecl))
       FunctionCodeCache.resize(DECL_FUNCTION_CODE(fndecl) + 1);
-  void *&Handler = FunctionCodeCache[DECL_FUNCTION_CODE(fndecl)];
-  if (!Handler) {
+  BuiltinCode &Handler = FunctionCodeCache[DECL_FUNCTION_CODE(fndecl)];
+  if (Handler == SearchForHandler) {
     // Find the handler for this intrinsic.
     size_t N = sizeof(Handlers) / sizeof(Handlers[0]);
 #ifndef NDEBUG
@@ -746,121 +113,124 @@
       Checked = true;
     }
 #endif
-    HandlerEntry ToFind = {IDENTIFIER_POINTER(DECL_NAME(fndecl)), NULL};
+    HandlerEntry ToFind
+      = {IDENTIFIER_POINTER(DECL_NAME(fndecl)), SearchForHandler};
     const HandlerEntry *E = std::lower_bound(Handlers, Handlers + N, ToFind, LT);
     Handler = (E == Handlers + N) || strcmp(E->Name, ToFind.Name) ?
-      &&unknown : E->Handler;
+      UnsupportedBuiltin : E->Handler;
   }
 
   bool flip = false;
   unsigned PredCode;
-  goto *Handler;
 
-  unknown: return false;
-  IX86_BUILTIN_ADDPS:
-  IX86_BUILTIN_ADDPS256:
-  IX86_BUILTIN_ADDPD:
-  IX86_BUILTIN_ADDPD256:
+  switch (Handler) {
+  case SearchForHandler:
+    assert(false && "Unexpected builtin code!");
+  case UnsupportedBuiltin: return false;
+  case addps:
+  case addps256:
+  case addpd:
+  case addpd256:
     Result = Builder.CreateFAdd(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_PADDB:
-  IX86_BUILTIN_PADDW:
-  IX86_BUILTIN_PADDD:
-  IX86_BUILTIN_PADDQ:
-  IX86_BUILTIN_PADDB128:
-  IX86_BUILTIN_PADDW128:
-  IX86_BUILTIN_PADDD128:
-  IX86_BUILTIN_PADDQ128:
+  case paddb:
+  case paddw:
+  case paddd:
+  case paddq:
+  case paddb128:
+  case paddw128:
+  case paddd128:
+  case paddq128:
     Result = Builder.CreateAdd(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_SUBPS:
-  IX86_BUILTIN_SUBPS256:
-  IX86_BUILTIN_SUBPD:
-  IX86_BUILTIN_SUBPD256:
+  case subps:
+  case subps256:
+  case subpd:
+  case subpd256:
     Result = Builder.CreateFSub(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_PSUBB:
-  IX86_BUILTIN_PSUBW:
-  IX86_BUILTIN_PSUBD:
-  IX86_BUILTIN_PSUBQ:
-  IX86_BUILTIN_PSUBB128:
-  IX86_BUILTIN_PSUBW128:
-  IX86_BUILTIN_PSUBD128:
-  IX86_BUILTIN_PSUBQ128:
+  case psubb:
+  case psubw:
+  case psubd:
+  case psubq:
+  case psubb128:
+  case psubw128:
+  case psubd128:
+  case psubq128:
     Result = Builder.CreateSub(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_MULPS:
-  IX86_BUILTIN_MULPS256:
-  IX86_BUILTIN_MULPD:
-  IX86_BUILTIN_MULPD256:
+  case mulps:
+  case mulps256:
+  case mulpd:
+  case mulpd256:
     Result = Builder.CreateFMul(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_PMULLW:
-  IX86_BUILTIN_PMULLW128:
-  IX86_BUILTIN_PMULLD128:
+  case pmullw:
+  case pmullw128:
+  case pmulld128:
     Result = Builder.CreateMul(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_DIVPS:
-  IX86_BUILTIN_DIVPS256:
-  IX86_BUILTIN_DIVPD:
-  IX86_BUILTIN_DIVPD256:
+  case divps:
+  case divps256:
+  case divpd:
+  case divpd256:
     Result = Builder.CreateFDiv(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_PAND:
-  IX86_BUILTIN_PAND128:
+  case pand:
+  case pand128:
     Result = Builder.CreateAnd(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_PANDN:
-  IX86_BUILTIN_PANDN128:
+  case pandn:
+  case pandn128:
     Ops[0] = Builder.CreateNot(Ops[0]);
     Result = Builder.CreateAnd(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_POR:
-  IX86_BUILTIN_POR128:
+  case por:
+  case por128:
     Result = Builder.CreateOr(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_PXOR:
-  IX86_BUILTIN_PXOR128:
+  case pxor:
+  case pxor128:
     Result = Builder.CreateXor(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_ANDPS:
-  IX86_BUILTIN_ANDPS256:
-  IX86_BUILTIN_ANDPD:
-  IX86_BUILTIN_ANDPD256:
+  case andps:
+  case andps256:
+  case andpd:
+  case andpd256:
     Ops[0] = BitCastToIntVector(Ops[0], Builder);
     Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType());
     Result = Builder.CreateAnd(Ops[0], Ops[1]);
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
-  IX86_BUILTIN_ORPS:
-  IX86_BUILTIN_ORPS256:
-  IX86_BUILTIN_ORPD:
-  IX86_BUILTIN_ORPD256:
+  case orps:
+  case orps256:
+  case orpd:
+  case orpd256:
     Ops[0] = BitCastToIntVector(Ops[0], Builder);
     Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType());
     Result = Builder.CreateOr(Ops[0], Ops[1]);
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
-  IX86_BUILTIN_XORPS:
-  IX86_BUILTIN_XORPS256:
-  IX86_BUILTIN_XORPD:
-  IX86_BUILTIN_XORPD256:
+  case xorps:
+  case xorps256:
+  case xorpd:
+  case xorpd256:
     Ops[0] = BitCastToIntVector(Ops[0], Builder);
     Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType());
     Result = Builder.CreateXor(Ops[0], Ops[1]);
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
-  IX86_BUILTIN_ANDNPS:
-  IX86_BUILTIN_ANDNPS256:
-  IX86_BUILTIN_ANDNPD:
-  IX86_BUILTIN_ANDNPD256:
+  case andnps:
+  case andnps256:
+  case andnpd:
+  case andnpd256:
     Ops[0] = BitCastToIntVector(Ops[0], Builder);
     Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType());
     Ops[0] = Builder.CreateNot(Ops[0]);
     Result = Builder.CreateAnd(Ops[0], Ops[1]);
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
-  IX86_BUILTIN_SHUFPS:
+  case shufps:
     if (ConstantInt *Elt = dyn_cast<ConstantInt>(Ops[2])) {
       int EV = Elt->getZExtValue();
       Result = BuildVectorShuffle(Ops[0], Ops[1],
@@ -871,7 +241,7 @@
       Result = Ops[0];
     }
     return true;
-  IX86_BUILTIN_SHUFPD:
+  case shufpd:
     if (ConstantInt *Elt = dyn_cast<ConstantInt>(Ops[2])) {
       int EV = Elt->getZExtValue();
       Result = BuildVectorShuffle(Ops[0], Ops[1],
@@ -881,8 +251,8 @@
       Result = Ops[0];
     }
     return true;
-  IX86_BUILTIN_PSHUFW:
-  IX86_BUILTIN_PSHUFD:
+  case pshufw:
+  case pshufd:
     if (ConstantInt *Elt = dyn_cast<ConstantInt>(Ops[1])) {
       int EV = Elt->getZExtValue();
       Result = BuildVectorShuffle(Ops[0], Ops[0],
@@ -893,7 +263,7 @@
       Result = Ops[0];
     }
     return true;
-  IX86_BUILTIN_PSHUFHW:
+  case pshufhw:
     if (ConstantInt *Elt = dyn_cast<ConstantInt>(Ops[1])) {
       int EV = Elt->getZExtValue();
       Result = BuildVectorShuffle(Ops[0], Ops[0],
@@ -903,7 +273,7 @@
       return true;
     }
     return false;
-  IX86_BUILTIN_PSHUFLW:
+  case pshuflw:
     if (ConstantInt *Elt = dyn_cast<ConstantInt>(Ops[1])) {
       int EV = Elt->getZExtValue();
       Result = BuildVectorShuffle(Ops[0], Ops[0],
@@ -916,81 +286,81 @@
     }
 
     return true;
-  IX86_BUILTIN_PUNPCKHBW:
+  case punpckhbw:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 4, 12, 5, 13,
                                                 6, 14, 7, 15);
     return true;
-  IX86_BUILTIN_PUNPCKHWD:
+  case punpckhwd:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 2, 6, 3, 7);
     return true;
-  IX86_BUILTIN_PUNPCKHDQ:
+  case punpckhdq:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 1, 3);
     return true;
-  IX86_BUILTIN_PUNPCKLBW:
+  case punpcklbw:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0,  8, 1,  9,
                                                 2, 10, 3, 11);
     return true;
-  IX86_BUILTIN_PUNPCKLWD:
+  case punpcklwd:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 4, 1, 5);
     return true;
-  IX86_BUILTIN_PUNPCKLDQ:
+  case punpckldq:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 2);
     return true;
-  IX86_BUILTIN_PUNPCKHBW128:
+  case punpckhbw128:
     Result = BuildVectorShuffle(Ops[0], Ops[1],  8, 24,  9, 25,
                                                 10, 26, 11, 27,
                                                 12, 28, 13, 29,
                                                 14, 30, 15, 31);
     return true;
-  IX86_BUILTIN_PUNPCKHWD128:
+  case punpckhwd128:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 4, 12, 5, 13, 6, 14, 7, 15);
     return true;
-  IX86_BUILTIN_PUNPCKHDQ128:
+  case punpckhdq128:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 2, 6, 3, 7);
     return true;
-  IX86_BUILTIN_PUNPCKHQDQ128:
+  case punpckhqdq128:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 1, 3);
     return true;
-  IX86_BUILTIN_PUNPCKLBW128:
+  case punpcklbw128:
     Result = BuildVectorShuffle(Ops[0], Ops[1],  0, 16,  1, 17,
                                                  2, 18,  3, 19,
                                                  4, 20,  5, 21,
                                                  6, 22,  7, 23);
     return true;
-  IX86_BUILTIN_PUNPCKLWD128:
+  case punpcklwd128:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 8, 1, 9, 2, 10, 3, 11);
     return true;
-  IX86_BUILTIN_PUNPCKLDQ128:
+  case punpckldq128:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 4, 1, 5);
     return true;
-  IX86_BUILTIN_PUNPCKLQDQ128:
+  case punpcklqdq128:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 2);
     return true;
-  IX86_BUILTIN_UNPCKHPS:
+  case unpckhps:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 2, 6, 3, 7);
     return true;
-  IX86_BUILTIN_UNPCKHPD:
+  case unpckhpd:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 1, 3);
     return true;
-  IX86_BUILTIN_UNPCKLPS:
+  case unpcklps:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 4, 1, 5);
     return true;
-  IX86_BUILTIN_UNPCKLPD:
+  case unpcklpd:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 2);
     return true;
-  IX86_BUILTIN_MOVHLPS:
+  case movhlps:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 6, 7, 2, 3);
     return true;
-  IX86_BUILTIN_MOVLHPS:
+  case movlhps:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 0, 1, 4, 5);
     return true;
-  IX86_BUILTIN_MOVSS:
+  case movss:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 4, 1, 2, 3);
     return true;
-  IX86_BUILTIN_MOVSD:
+  case movsd:
     Result = BuildVectorShuffle(Ops[0], Ops[1], 2, 1);
     return true;
-  IX86_BUILTIN_MOVQ128: {
+  case movq128: {
     Value *Zero = Constant::getNullValue(Ops[0]->getType());
     Result = BuildVectorShuffle(Zero, Ops[0], 2, 1);
     return true;
@@ -1006,7 +376,7 @@
 //TODO    Result = Builder.CreateBitCast(Result, ResultType);
 //TODO    return true;
 //TODO  }
-  IX86_BUILTIN_LOADUPS: {
+  case loadups: {
     VectorType *v4f32 = VectorType::get(Type::getFloatTy(Context), 4);
     const PointerType *v4f32Ptr = v4f32->getPointerTo();
     Value *BC = Builder.CreateBitCast(Ops[0], v4f32Ptr);
@@ -1015,7 +385,7 @@
     Result = LI;
     return true;
   }
-  IX86_BUILTIN_LOADUPD: {
+  case loadupd: {
     VectorType *v2f64 = VectorType::get(Type::getDoubleTy(Context), 2);
     const PointerType *v2f64Ptr = v2f64->getPointerTo();
     Value *BC = Builder.CreateBitCast(Ops[0], v2f64Ptr);
@@ -1024,7 +394,7 @@
     Result = LI;
     return true;
   }
-  IX86_BUILTIN_LOADDQU: {
+  case loaddqu: {
     VectorType *v16i8 = VectorType::get(Type::getInt8Ty(Context), 16);
     const PointerType *v16i8Ptr = v16i8->getPointerTo();
     Value *BC = Builder.CreateBitCast(Ops[0], v16i8Ptr);
@@ -1033,7 +403,7 @@
     Result = LI;
     return true;
   }
-  IX86_BUILTIN_STOREUPS: {
+  case storeups: {
     VectorType *v4f32 = VectorType::get(Type::getFloatTy(Context), 4);
     const PointerType *v4f32Ptr = v4f32->getPointerTo();
     Value *BC = Builder.CreateBitCast(Ops[0], v4f32Ptr);
@@ -1041,7 +411,7 @@
     SI->setAlignment(1);
     return true;
   }
-  IX86_BUILTIN_STOREUPD: {
+  case storeupd: {
     VectorType *v2f64 = VectorType::get(Type::getDoubleTy(Context), 2);
     const PointerType *v2f64Ptr = v2f64->getPointerTo();
     Value *BC = Builder.CreateBitCast(Ops[0], v2f64Ptr);
@@ -1049,7 +419,7 @@
     SI->setAlignment(1);
     return true;
   }
-  IX86_BUILTIN_STOREDQU: {
+  case storedqu: {
     VectorType *v16i8 = VectorType::get(Type::getInt8Ty(Context), 16);
     const PointerType *v16i8Ptr = v16i8->getPointerTo();
     Value *BC = Builder.CreateBitCast(Ops[0], v16i8Ptr);
@@ -1057,7 +427,7 @@
     SI->setAlignment(1);
     return true;
   }
-  IX86_BUILTIN_LOADHPS: {
+  case loadhps: {
     const PointerType *f64Ptr = Type::getDoublePtrTy(Context);
     Ops[1] = Builder.CreateBitCast(Ops[1], f64Ptr);
     Value *Load = Builder.CreateLoad(Ops[1]);
@@ -1067,7 +437,7 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_LOADLPS: {
+  case loadlps: {
     const PointerType *f64Ptr = Type::getDoublePtrTy(Context);
     Ops[1] = Builder.CreateBitCast(Ops[1], f64Ptr);
     Value *Load = Builder.CreateLoad(Ops[1]);
@@ -1077,7 +447,7 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_LOADHPD: {
+  case loadhpd: {
     Value *Load = Builder.CreateLoad(Ops[1]);
     Ops[1] = BuildVector(Load, UndefValue::get(Type::getDoubleTy(Context)), NULL);
     Ops[1] = Builder.CreateBitCast(Ops[1], ResultType);
@@ -1085,7 +455,7 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_LOADLPD: {
+  case loadlpd: {
     Value *Load = Builder.CreateLoad(Ops[1]);
     Ops[1] = BuildVector(Load, UndefValue::get(Type::getDoubleTy(Context)), NULL);
     Ops[1] = Builder.CreateBitCast(Ops[1], ResultType);
@@ -1093,7 +463,7 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_STOREHPS: {
+  case storehps: {
     VectorType *v2f64 = VectorType::get(Type::getDoubleTy(Context), 2);
     const PointerType *f64Ptr = Type::getDoublePtrTy(Context);
     Ops[0] = Builder.CreateBitCast(Ops[0], f64Ptr);
@@ -1103,7 +473,7 @@
     Builder.CreateStore(Ops[1], Ops[0]);
     return true;
   }
-  IX86_BUILTIN_STORELPS: {
+  case storelps: {
     VectorType *v2f64 = VectorType::get(Type::getDoubleTy(Context), 2);
     const PointerType *f64Ptr = Type::getDoublePtrTy(Context);
     Ops[0] = Builder.CreateBitCast(Ops[0], f64Ptr);
@@ -1113,23 +483,23 @@
     Builder.CreateStore(Ops[1], Ops[0]);
     return true;
   }
-  IX86_BUILTIN_MOVSHDUP:
+  case movshdup:
     Result = BuildVectorShuffle(Ops[0], Ops[0], 1, 1, 3, 3);
     return true;
-  IX86_BUILTIN_MOVSLDUP:
+  case movsldup:
     Result = BuildVectorShuffle(Ops[0], Ops[0], 0, 0, 2, 2);
     return true;
-  IX86_BUILTIN_VEC_INIT_V2SI:
+  case vec_init_v2si:
     Result = BuildVector(Ops[0], Ops[1], NULL);
     return true;
-  IX86_BUILTIN_VEC_INIT_V4HI:
+  case vec_init_v4hi:
     // Sometimes G++ promotes arguments to int.
     for (unsigned i = 0; i != 4; ++i)
       Ops[i] = Builder.CreateIntCast(Ops[i], Type::getInt16Ty(Context),
                                      /*isSigned*/false);
     Result = BuildVector(Ops[0], Ops[1], Ops[2], Ops[3], NULL);
     return true;
-  IX86_BUILTIN_VEC_INIT_V8QI:
+  case vec_init_v8qi:
     // Sometimes G++ promotes arguments to int.
     for (unsigned i = 0; i != 8; ++i)
       Ops[i] = Builder.CreateIntCast(Ops[i], Type::getInt8Ty(Context),
@@ -1137,48 +507,48 @@
     Result = BuildVector(Ops[0], Ops[1], Ops[2], Ops[3],
                          Ops[4], Ops[5], Ops[6], Ops[7], NULL);
     return true;
-  IX86_BUILTIN_VEC_EXT_V2SI:
-  IX86_BUILTIN_VEC_EXT_V4HI:
-  IX86_BUILTIN_VEC_EXT_V2DF:
-  IX86_BUILTIN_VEC_EXT_V2DI:
-  IX86_BUILTIN_VEC_EXT_V4SI:
-  IX86_BUILTIN_VEC_EXT_V4SF:
-  IX86_BUILTIN_VEC_EXT_V8HI:
-  IX86_BUILTIN_VEC_EXT_V16QI:
+  case vec_ext_v2si:
+  case vec_ext_v4hi:
+  case vec_ext_v2df:
+  case vec_ext_v2di:
+  case vec_ext_v4si:
+  case vec_ext_v4sf:
+  case vec_ext_v8hi:
+  case vec_ext_v16qi:
     Result = Builder.CreateExtractElement(Ops[0], Ops[1]);
     return true;
-  IX86_BUILTIN_VEC_SET_V16QI:
+  case vec_set_v16qi:
     // Sometimes G++ promotes arguments to int.
     Ops[1] = Builder.CreateIntCast(Ops[1], Type::getInt8Ty(Context),
                                    /*isSigned*/false);
     Result = Builder.CreateInsertElement(Ops[0], Ops[1], Ops[2]);
     return true;
-  IX86_BUILTIN_VEC_SET_V4HI:
-  IX86_BUILTIN_VEC_SET_V8HI:
+  case vec_set_v4hi:
+  case vec_set_v8hi:
     // GCC sometimes doesn't produce the right element type.
     Ops[1] = Builder.CreateIntCast(Ops[1], Type::getInt16Ty(Context),
                                    /*isSigned*/false);
     Result = Builder.CreateInsertElement(Ops[0], Ops[1], Ops[2]);
     return true;
-  IX86_BUILTIN_VEC_SET_V4SI:
+  case vec_set_v4si:
     Result = Builder.CreateInsertElement(Ops[0], Ops[1], Ops[2]);
     return true;
-  IX86_BUILTIN_VEC_SET_V2DI:
+  case vec_set_v2di:
     Result = Builder.CreateInsertElement(Ops[0], Ops[1], Ops[2]);
     return true;
 
-  IX86_BUILTIN_CMPEQPS: PredCode = 0; goto CMPXXPS;
-  IX86_BUILTIN_CMPLTPS: PredCode = 1; goto CMPXXPS;
-  IX86_BUILTIN_CMPGTPS: PredCode = 1; flip = true; goto CMPXXPS;
-  IX86_BUILTIN_CMPLEPS: PredCode = 2; goto CMPXXPS;
-  IX86_BUILTIN_CMPGEPS: PredCode = 2; flip = true; goto CMPXXPS;
-  IX86_BUILTIN_CMPUNORDPS: PredCode = 3; goto CMPXXPS;
-  IX86_BUILTIN_CMPNEQPS: PredCode = 4; goto CMPXXPS;
-  IX86_BUILTIN_CMPNLTPS: PredCode = 5; goto CMPXXPS;
-  IX86_BUILTIN_CMPNGTPS: PredCode = 5; flip = true; goto CMPXXPS;
-  IX86_BUILTIN_CMPNLEPS: PredCode = 6; goto CMPXXPS;
-  IX86_BUILTIN_CMPNGEPS: PredCode = 6; flip = true; goto CMPXXPS;
-  IX86_BUILTIN_CMPORDPS: PredCode = 7; goto CMPXXPS;
+  case cmpeqps: PredCode = 0; goto CMPXXPS;
+  case cmpltps: PredCode = 1; goto CMPXXPS;
+  case cmpgtps: PredCode = 1; flip = true; goto CMPXXPS;
+  case cmpleps: PredCode = 2; goto CMPXXPS;
+  case cmpgeps: PredCode = 2; flip = true; goto CMPXXPS;
+  case cmpunordps: PredCode = 3; goto CMPXXPS;
+  case cmpneqps: PredCode = 4; goto CMPXXPS;
+  case cmpnltps: PredCode = 5; goto CMPXXPS;
+  case cmpngtps: PredCode = 5; flip = true; goto CMPXXPS;
+  case cmpnleps: PredCode = 6; goto CMPXXPS;
+  case cmpngeps: PredCode = 6; flip = true; goto CMPXXPS;
+  case cmpordps: PredCode = 7; goto CMPXXPS;
   CMPXXPS: {
     Function *cmpps =
       Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse_cmp_ps);
@@ -1191,14 +561,14 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_CMPEQSS:    PredCode = 0; goto CMPXXSS;
-  IX86_BUILTIN_CMPLTSS:    PredCode = 1; goto CMPXXSS;
-  IX86_BUILTIN_CMPLESS:    PredCode = 2; goto CMPXXSS;
-  IX86_BUILTIN_CMPUNORDSS: PredCode = 3; goto CMPXXSS;
-  IX86_BUILTIN_CMPNEQSS:   PredCode = 4; goto CMPXXSS;
-  IX86_BUILTIN_CMPNLTSS:   PredCode = 5; goto CMPXXSS;
-  IX86_BUILTIN_CMPNLESS:   PredCode = 6; goto CMPXXSS;
-  IX86_BUILTIN_CMPORDSS:   PredCode = 7; goto CMPXXSS;
+  case cmpeqss:    PredCode = 0; goto CMPXXSS;
+  case cmpltss:    PredCode = 1; goto CMPXXSS;
+  case cmpless:    PredCode = 2; goto CMPXXSS;
+  case cmpunordss: PredCode = 3; goto CMPXXSS;
+  case cmpneqss:   PredCode = 4; goto CMPXXSS;
+  case cmpnltss:   PredCode = 5; goto CMPXXSS;
+  case cmpnless:   PredCode = 6; goto CMPXXSS;
+  case cmpordss:   PredCode = 7; goto CMPXXSS;
   CMPXXSS: {
     Function *cmpss =
       Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse_cmp_ss);
@@ -1208,18 +578,18 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_CMPEQPD:    PredCode = 0; goto CMPXXPD;
-  IX86_BUILTIN_CMPLTPD:    PredCode = 1; goto CMPXXPD;
-  IX86_BUILTIN_CMPGTPD:    PredCode = 1; flip = true; goto CMPXXPD;
-  IX86_BUILTIN_CMPLEPD:    PredCode = 2; goto CMPXXPD;
-  IX86_BUILTIN_CMPGEPD:    PredCode = 2; flip = true; goto CMPXXPD;
-  IX86_BUILTIN_CMPUNORDPD: PredCode = 3; goto CMPXXPD;
-  IX86_BUILTIN_CMPNEQPD:   PredCode = 4; goto CMPXXPD;
-  IX86_BUILTIN_CMPNLTPD:   PredCode = 5; goto CMPXXPD;
-  IX86_BUILTIN_CMPNGTPD:   PredCode = 5; flip = true; goto CMPXXPD;
-  IX86_BUILTIN_CMPNLEPD:   PredCode = 6; goto CMPXXPD;
-  IX86_BUILTIN_CMPNGEPD:   PredCode = 6; flip = true; goto CMPXXPD;
-  IX86_BUILTIN_CMPORDPD:   PredCode = 7; goto CMPXXPD;
+  case cmpeqpd:    PredCode = 0; goto CMPXXPD;
+  case cmpltpd:    PredCode = 1; goto CMPXXPD;
+  case cmpgtpd:    PredCode = 1; flip = true; goto CMPXXPD;
+  case cmplepd:    PredCode = 2; goto CMPXXPD;
+  case cmpgepd:    PredCode = 2; flip = true; goto CMPXXPD;
+  case cmpunordpd: PredCode = 3; goto CMPXXPD;
+  case cmpneqpd:   PredCode = 4; goto CMPXXPD;
+  case cmpnltpd:   PredCode = 5; goto CMPXXPD;
+  case cmpngtpd:   PredCode = 5; flip = true; goto CMPXXPD;
+  case cmpnlepd:   PredCode = 6; goto CMPXXPD;
+  case cmpngepd:   PredCode = 6; flip = true; goto CMPXXPD;
+  case cmpordpd:   PredCode = 7; goto CMPXXPD;
   CMPXXPD: {
     Function *cmppd =
       Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse2_cmp_pd);
@@ -1233,14 +603,14 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_CMPEQSD:    PredCode = 0; goto CMPXXSD;
-  IX86_BUILTIN_CMPLTSD:    PredCode = 1; goto CMPXXSD;
-  IX86_BUILTIN_CMPLESD:    PredCode = 2; goto CMPXXSD;
-  IX86_BUILTIN_CMPUNORDSD: PredCode = 3; goto CMPXXSD;
-  IX86_BUILTIN_CMPNEQSD:   PredCode = 4; goto CMPXXSD;
-  IX86_BUILTIN_CMPNLTSD:   PredCode = 5; goto CMPXXSD;
-  IX86_BUILTIN_CMPNLESD:   PredCode = 6; goto CMPXXSD;
-  IX86_BUILTIN_CMPORDSD:   PredCode = 7; goto CMPXXSD;
+  case cmpeqsd:    PredCode = 0; goto CMPXXSD;
+  case cmpltsd:    PredCode = 1; goto CMPXXSD;
+  case cmplesd:    PredCode = 2; goto CMPXXSD;
+  case cmpunordsd: PredCode = 3; goto CMPXXSD;
+  case cmpneqsd:   PredCode = 4; goto CMPXXSD;
+  case cmpnltsd:   PredCode = 5; goto CMPXXSD;
+  case cmpnlesd:   PredCode = 6; goto CMPXXSD;
+  case cmpordsd:   PredCode = 7; goto CMPXXSD;
   CMPXXSD: {
     Function *cmpsd =
       Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse2_cmp_sd);
@@ -1250,7 +620,7 @@
     Result = Builder.CreateBitCast(Result, ResultType);
     return true;
   }
-  IX86_BUILTIN_LDMXCSR: {
+  case ldmxcsr: {
     Function *ldmxcsr =
       Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse_ldmxcsr);
     Value *Ptr = CreateTemporary(Type::getInt32Ty(Context));
@@ -1259,7 +629,7 @@
     Builder.CreateCall(ldmxcsr, Ptr);
     return true;
   }
-  IX86_BUILTIN_STMXCSR: {
+  case stmxcsr: {
     Function *stmxcsr =
       Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse_stmxcsr);
     Value *Ptr  = CreateTemporary(Type::getInt32Ty(Context));
@@ -1269,7 +639,7 @@
     Result = Builder.CreateLoad(Ptr);
     return true;
   }
-  IX86_BUILTIN_PALIGNR: {
+  case palignr: {
     if (isa<ConstantInt>(Ops[2])) {
 
       // In the header we multiply by 8, correct that back now.
@@ -1321,7 +691,7 @@
       return true;
     }
   }
-  IX86_BUILTIN_PALIGNR128: {
+  case palignr128: {
     if (isa<ConstantInt>(Ops[2])) {
 
       // In the header we multiply by 8, correct that back now.
@@ -1372,6 +742,8 @@
       return true;
     }
   }
+  }
+  llvm_unreachable("Builtin not implemented!");
 }
 
 /* These are defined in i386.c */

Added: dragonegg/trunk/x86/x86_builtins
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/x86_builtins?rev=114804&view=auto
==============================================================================
--- dragonegg/trunk/x86/x86_builtins (added)
+++ dragonegg/trunk/x86/x86_builtins Sun Sep 26 08:47:06 2010
@@ -0,0 +1,645 @@
+// Unsupported builtins are commented out.
+DEFINE_BUILTIN(addpd),
+DEFINE_BUILTIN(addpd256),
+DEFINE_BUILTIN(addps),
+DEFINE_BUILTIN(addps256),
+//DEFINE_BUILTIN(addsd),
+//DEFINE_BUILTIN(addss),
+//DEFINE_BUILTIN(addsubpd),
+//DEFINE_BUILTIN(addsubpd256),
+//DEFINE_BUILTIN(addsubps),
+//DEFINE_BUILTIN(addsubps256),
+//DEFINE_BUILTIN(aesdec128),
+//DEFINE_BUILTIN(aesdeclast128),
+//DEFINE_BUILTIN(aesenc128),
+//DEFINE_BUILTIN(aesenclast128),
+//DEFINE_BUILTIN(aesimc128),
+//DEFINE_BUILTIN(aeskeygenassist128),
+DEFINE_BUILTIN(andnpd),
+DEFINE_BUILTIN(andnpd256),
+DEFINE_BUILTIN(andnps),
+DEFINE_BUILTIN(andnps256),
+DEFINE_BUILTIN(andpd),
+DEFINE_BUILTIN(andpd256),
+DEFINE_BUILTIN(andps),
+DEFINE_BUILTIN(andps256),
+//DEFINE_BUILTIN(blendpd),
+//DEFINE_BUILTIN(blendpd256),
+//DEFINE_BUILTIN(blendps),
+//DEFINE_BUILTIN(blendps256),
+//DEFINE_BUILTIN(blendvpd),
+//DEFINE_BUILTIN(blendvpd256),
+//DEFINE_BUILTIN(blendvps),
+//DEFINE_BUILTIN(blendvps256),
+//DEFINE_BUILTIN(bsrdi),
+//DEFINE_BUILTIN(bsrsi),
+//DEFINE_BUILTIN(clflush),
+DEFINE_BUILTIN(cmpeqpd),
+DEFINE_BUILTIN(cmpeqps),
+DEFINE_BUILTIN(cmpeqsd),
+DEFINE_BUILTIN(cmpeqss),
+DEFINE_BUILTIN(cmpgepd),
+DEFINE_BUILTIN(cmpgeps),
+DEFINE_BUILTIN(cmpgtpd),
+DEFINE_BUILTIN(cmpgtps),
+DEFINE_BUILTIN(cmplepd),
+DEFINE_BUILTIN(cmpleps),
+DEFINE_BUILTIN(cmplesd),
+DEFINE_BUILTIN(cmpless),
+DEFINE_BUILTIN(cmpltpd),
+DEFINE_BUILTIN(cmpltps),
+DEFINE_BUILTIN(cmpltsd),
+DEFINE_BUILTIN(cmpltss),
+DEFINE_BUILTIN(cmpneqpd),
+DEFINE_BUILTIN(cmpneqps),
+DEFINE_BUILTIN(cmpneqsd),
+DEFINE_BUILTIN(cmpneqss),
+DEFINE_BUILTIN(cmpngepd),
+DEFINE_BUILTIN(cmpngeps),
+//DEFINE_BUILTIN(cmpngess),
+DEFINE_BUILTIN(cmpngtpd),
+DEFINE_BUILTIN(cmpngtps),
+//DEFINE_BUILTIN(cmpngtss),
+DEFINE_BUILTIN(cmpnlepd),
+DEFINE_BUILTIN(cmpnleps),
+DEFINE_BUILTIN(cmpnlesd),
+DEFINE_BUILTIN(cmpnless),
+DEFINE_BUILTIN(cmpnltpd),
+DEFINE_BUILTIN(cmpnltps),
+DEFINE_BUILTIN(cmpnltsd),
+DEFINE_BUILTIN(cmpnltss),
+DEFINE_BUILTIN(cmpordpd),
+DEFINE_BUILTIN(cmpordps),
+DEFINE_BUILTIN(cmpordsd),
+DEFINE_BUILTIN(cmpordss),
+//DEFINE_BUILTIN(cmppd),
+//DEFINE_BUILTIN(cmppd256),
+//DEFINE_BUILTIN(cmpps),
+//DEFINE_BUILTIN(cmpps256),
+//DEFINE_BUILTIN(cmpsd),
+//DEFINE_BUILTIN(cmpss),
+DEFINE_BUILTIN(cmpunordpd),
+DEFINE_BUILTIN(cmpunordps),
+DEFINE_BUILTIN(cmpunordsd),
+DEFINE_BUILTIN(cmpunordss),
+//DEFINE_BUILTIN(comieq),
+//DEFINE_BUILTIN(comige),
+//DEFINE_BUILTIN(comigt),
+//DEFINE_BUILTIN(comile),
+//DEFINE_BUILTIN(comilt),
+//DEFINE_BUILTIN(comineq),
+//DEFINE_BUILTIN(comisdeq),
+//DEFINE_BUILTIN(comisdge),
+//DEFINE_BUILTIN(comisdgt),
+//DEFINE_BUILTIN(comisdle),
+//DEFINE_BUILTIN(comisdlt),
+//DEFINE_BUILTIN(comisdneq),
+//DEFINE_BUILTIN(copysignpd),
+//DEFINE_BUILTIN(copysignps),
+//DEFINE_BUILTIN(crc32di),
+//DEFINE_BUILTIN(crc32hi),
+//DEFINE_BUILTIN(crc32qi),
+//DEFINE_BUILTIN(crc32si),
+//DEFINE_BUILTIN(cvtdq2pd),
+//DEFINE_BUILTIN(cvtdq2pd256),
+//DEFINE_BUILTIN(cvtdq2ps),
+//DEFINE_BUILTIN(cvtdq2ps256),
+//DEFINE_BUILTIN(cvtpd2dq),
+//DEFINE_BUILTIN(cvtpd2dq256),
+//DEFINE_BUILTIN(cvtpd2pi),
+//DEFINE_BUILTIN(cvtpd2ps),
+//DEFINE_BUILTIN(cvtpd2ps256),
+//DEFINE_BUILTIN(cvtpi2pd),
+//DEFINE_BUILTIN(cvtpi2ps),
+//DEFINE_BUILTIN(cvtps2dq),
+//DEFINE_BUILTIN(cvtps2dq256),
+//DEFINE_BUILTIN(cvtps2pd),
+//DEFINE_BUILTIN(cvtps2pd256),
+//DEFINE_BUILTIN(cvtps2pi),
+//DEFINE_BUILTIN(cvtsd2si),
+//DEFINE_BUILTIN(cvtsd2si64),
+//DEFINE_BUILTIN(cvtsd2ss),
+//DEFINE_BUILTIN(cvtsi2sd),
+//DEFINE_BUILTIN(cvtsi2ss),
+//DEFINE_BUILTIN(cvtsi642sd),
+//DEFINE_BUILTIN(cvtsi642ss),
+//DEFINE_BUILTIN(cvtss2sd),
+//DEFINE_BUILTIN(cvtss2si),
+//DEFINE_BUILTIN(cvtss2si64),
+//DEFINE_BUILTIN(cvttpd2dq),
+//DEFINE_BUILTIN(cvttpd2dq256),
+//DEFINE_BUILTIN(cvttpd2pi),
+//DEFINE_BUILTIN(cvttps2dq),
+//DEFINE_BUILTIN(cvttps2dq256),
+//DEFINE_BUILTIN(cvttps2pi),
+//DEFINE_BUILTIN(cvttsd2si),
+//DEFINE_BUILTIN(cvttsd2si64),
+//DEFINE_BUILTIN(cvttss2si),
+//DEFINE_BUILTIN(cvttss2si64),
+//DEFINE_BUILTIN(cvtudq2ps),
+DEFINE_BUILTIN(divpd),
+DEFINE_BUILTIN(divpd256),
+DEFINE_BUILTIN(divps),
+DEFINE_BUILTIN(divps256),
+//DEFINE_BUILTIN(divsd),
+//DEFINE_BUILTIN(divss),
+//DEFINE_BUILTIN(dppd),
+//DEFINE_BUILTIN(dpps),
+//DEFINE_BUILTIN(dpps256),
+//DEFINE_BUILTIN(emms),
+//DEFINE_BUILTIN(extrq),
+//DEFINE_BUILTIN(extrqi),
+//DEFINE_BUILTIN(femms),
+//DEFINE_BUILTIN(haddpd),
+//DEFINE_BUILTIN(haddpd256),
+//DEFINE_BUILTIN(haddps),
+//DEFINE_BUILTIN(haddps256),
+//DEFINE_BUILTIN(hsubpd),
+//DEFINE_BUILTIN(hsubpd256),
+//DEFINE_BUILTIN(hsubps),
+//DEFINE_BUILTIN(hsubps256),
+//DEFINE_BUILTIN(insertps128),
+//DEFINE_BUILTIN(insertq),
+//DEFINE_BUILTIN(insertqi),
+//DEFINE_BUILTIN(lddqu),
+//DEFINE_BUILTIN(lddqu256),
+DEFINE_BUILTIN(ldmxcsr),
+//DEFINE_BUILTIN(lfence),
+DEFINE_BUILTIN(loaddqu),
+//DEFINE_BUILTIN(loaddqu256),
+DEFINE_BUILTIN(loadhpd),
+DEFINE_BUILTIN(loadhps),
+DEFINE_BUILTIN(loadlpd),
+DEFINE_BUILTIN(loadlps),
+DEFINE_BUILTIN(loadupd),
+//DEFINE_BUILTIN(loadupd256),
+DEFINE_BUILTIN(loadups),
+//DEFINE_BUILTIN(loadups256),
+//DEFINE_BUILTIN(maskloadpd),
+//DEFINE_BUILTIN(maskloadpd256),
+//DEFINE_BUILTIN(maskloadps),
+//DEFINE_BUILTIN(maskloadps256),
+//DEFINE_BUILTIN(maskmovdqu),
+//DEFINE_BUILTIN(maskmovq),
+//DEFINE_BUILTIN(maskstorepd),
+//DEFINE_BUILTIN(maskstorepd256),
+//DEFINE_BUILTIN(maskstoreps),
+//DEFINE_BUILTIN(maskstoreps256),
+//DEFINE_BUILTIN(maxpd),
+//DEFINE_BUILTIN(maxpd256),
+//DEFINE_BUILTIN(maxps),
+//DEFINE_BUILTIN(maxps256),
+//DEFINE_BUILTIN(maxsd),
+//DEFINE_BUILTIN(maxss),
+//DEFINE_BUILTIN(mfence),
+//DEFINE_BUILTIN(minpd),
+//DEFINE_BUILTIN(minpd256),
+//DEFINE_BUILTIN(minps),
+//DEFINE_BUILTIN(minps256),
+//DEFINE_BUILTIN(minsd),
+//DEFINE_BUILTIN(minss),
+//DEFINE_BUILTIN(monitor),
+//DEFINE_BUILTIN(movddup256),
+DEFINE_BUILTIN(movhlps),
+DEFINE_BUILTIN(movlhps),
+//DEFINE_BUILTIN(movmskpd),
+//DEFINE_BUILTIN(movmskpd256),
+//DEFINE_BUILTIN(movmskps),
+//DEFINE_BUILTIN(movmskps256),
+//DEFINE_BUILTIN(movntdq),
+//DEFINE_BUILTIN(movntdq256),
+//DEFINE_BUILTIN(movntdqa),
+//DEFINE_BUILTIN(movnti),
+//DEFINE_BUILTIN(movntpd),
+//DEFINE_BUILTIN(movntpd256),
+//DEFINE_BUILTIN(movntps),
+//DEFINE_BUILTIN(movntps256),
+//DEFINE_BUILTIN(movntq),
+//DEFINE_BUILTIN(movntsd),
+//DEFINE_BUILTIN(movntss),
+DEFINE_BUILTIN(movq128),
+DEFINE_BUILTIN(movsd),
+DEFINE_BUILTIN(movshdup),
+//DEFINE_BUILTIN(movshdup256),
+DEFINE_BUILTIN(movsldup),
+//DEFINE_BUILTIN(movsldup256),
+DEFINE_BUILTIN(movss),
+//DEFINE_BUILTIN(mpsadbw128),
+DEFINE_BUILTIN(mulpd),
+DEFINE_BUILTIN(mulpd256),
+DEFINE_BUILTIN(mulps),
+DEFINE_BUILTIN(mulps256),
+//DEFINE_BUILTIN(mulsd),
+//DEFINE_BUILTIN(mulss),
+//DEFINE_BUILTIN(mwait),
+DEFINE_BUILTIN(orpd),
+DEFINE_BUILTIN(orpd256),
+DEFINE_BUILTIN(orps),
+DEFINE_BUILTIN(orps256),
+//DEFINE_BUILTIN(pabsb),
+//DEFINE_BUILTIN(pabsb128),
+//DEFINE_BUILTIN(pabsd),
+//DEFINE_BUILTIN(pabsd128),
+//DEFINE_BUILTIN(pabsw),
+//DEFINE_BUILTIN(pabsw128),
+//DEFINE_BUILTIN(packssdw),
+//DEFINE_BUILTIN(packssdw128),
+//DEFINE_BUILTIN(packsswb),
+//DEFINE_BUILTIN(packsswb128),
+//DEFINE_BUILTIN(packusdw128),
+//DEFINE_BUILTIN(packuswb),
+//DEFINE_BUILTIN(packuswb128),
+DEFINE_BUILTIN(paddb),
+DEFINE_BUILTIN(paddb128),
+DEFINE_BUILTIN(paddd),
+DEFINE_BUILTIN(paddd128),
+DEFINE_BUILTIN(paddq),
+DEFINE_BUILTIN(paddq128),
+//DEFINE_BUILTIN(paddsb),
+//DEFINE_BUILTIN(paddsb128),
+//DEFINE_BUILTIN(paddsw),
+//DEFINE_BUILTIN(paddsw128),
+//DEFINE_BUILTIN(paddusb),
+//DEFINE_BUILTIN(paddusb128),
+//DEFINE_BUILTIN(paddusw),
+//DEFINE_BUILTIN(paddusw128),
+DEFINE_BUILTIN(paddw),
+DEFINE_BUILTIN(paddw128),
+DEFINE_BUILTIN(palignr),
+DEFINE_BUILTIN(palignr128),
+DEFINE_BUILTIN(pand),
+DEFINE_BUILTIN(pand128),
+DEFINE_BUILTIN(pandn),
+DEFINE_BUILTIN(pandn128),
+//DEFINE_BUILTIN(pavgb),
+//DEFINE_BUILTIN(pavgb128),
+//DEFINE_BUILTIN(pavgusb),
+//DEFINE_BUILTIN(pavgw),
+//DEFINE_BUILTIN(pavgw128),
+//DEFINE_BUILTIN(pblendvb128),
+//DEFINE_BUILTIN(pblendw128),
+//DEFINE_BUILTIN(pclmulqdq128),
+//DEFINE_BUILTIN(pcmpeqb),
+//DEFINE_BUILTIN(pcmpeqb128),
+//DEFINE_BUILTIN(pcmpeqd),
+//DEFINE_BUILTIN(pcmpeqd128),
+//DEFINE_BUILTIN(pcmpeqq),
+//DEFINE_BUILTIN(pcmpeqw),
+//DEFINE_BUILTIN(pcmpeqw128),
+//DEFINE_BUILTIN(pcmpestri128),
+//DEFINE_BUILTIN(pcmpestria128),
+//DEFINE_BUILTIN(pcmpestric128),
+//DEFINE_BUILTIN(pcmpestrio128),
+//DEFINE_BUILTIN(pcmpestris128),
+//DEFINE_BUILTIN(pcmpestriz128),
+//DEFINE_BUILTIN(pcmpestrm128),
+//DEFINE_BUILTIN(pcmpgtb),
+//DEFINE_BUILTIN(pcmpgtb128),
+//DEFINE_BUILTIN(pcmpgtd),
+//DEFINE_BUILTIN(pcmpgtd128),
+//DEFINE_BUILTIN(pcmpgtq),
+//DEFINE_BUILTIN(pcmpgtw),
+//DEFINE_BUILTIN(pcmpgtw128),
+//DEFINE_BUILTIN(pcmpistri128),
+//DEFINE_BUILTIN(pcmpistria128),
+//DEFINE_BUILTIN(pcmpistric128),
+//DEFINE_BUILTIN(pcmpistrio128),
+//DEFINE_BUILTIN(pcmpistris128),
+//DEFINE_BUILTIN(pcmpistriz128),
+//DEFINE_BUILTIN(pcmpistrm128),
+//DEFINE_BUILTIN(pd256_pd),
+//DEFINE_BUILTIN(pd_pd256),
+//DEFINE_BUILTIN(pf2id),
+//DEFINE_BUILTIN(pf2iw),
+//DEFINE_BUILTIN(pfacc),
+//DEFINE_BUILTIN(pfadd),
+//DEFINE_BUILTIN(pfcmpeq),
+//DEFINE_BUILTIN(pfcmpge),
+//DEFINE_BUILTIN(pfcmpgt),
+//DEFINE_BUILTIN(pfmax),
+//DEFINE_BUILTIN(pfmin),
+//DEFINE_BUILTIN(pfmul),
+//DEFINE_BUILTIN(pfnacc),
+//DEFINE_BUILTIN(pfpnacc),
+//DEFINE_BUILTIN(pfrcp),
+//DEFINE_BUILTIN(pfrcpit1),
+//DEFINE_BUILTIN(pfrcpit2),
+//DEFINE_BUILTIN(pfrsqit1),
+//DEFINE_BUILTIN(pfrsqrt),
+//DEFINE_BUILTIN(pfsub),
+//DEFINE_BUILTIN(pfsubr),
+//DEFINE_BUILTIN(phaddd),
+//DEFINE_BUILTIN(phaddd128),
+//DEFINE_BUILTIN(phaddsw),
+//DEFINE_BUILTIN(phaddsw128),
+//DEFINE_BUILTIN(phaddw),
+//DEFINE_BUILTIN(phaddw128),
+//DEFINE_BUILTIN(phminposuw128),
+//DEFINE_BUILTIN(phsubd),
+//DEFINE_BUILTIN(phsubd128),
+//DEFINE_BUILTIN(phsubsw),
+//DEFINE_BUILTIN(phsubsw128),
+//DEFINE_BUILTIN(phsubw),
+//DEFINE_BUILTIN(phsubw128),
+//DEFINE_BUILTIN(pi2fd),
+//DEFINE_BUILTIN(pi2fw),
+//DEFINE_BUILTIN(pmaddubsw),
+//DEFINE_BUILTIN(pmaddubsw128),
+//DEFINE_BUILTIN(pmaddwd),
+//DEFINE_BUILTIN(pmaddwd128),
+//DEFINE_BUILTIN(pmaxsb128),
+//DEFINE_BUILTIN(pmaxsd128),
+//DEFINE_BUILTIN(pmaxsw),
+//DEFINE_BUILTIN(pmaxsw128),
+//DEFINE_BUILTIN(pmaxub),
+//DEFINE_BUILTIN(pmaxub128),
+//DEFINE_BUILTIN(pmaxud128),
+//DEFINE_BUILTIN(pmaxuw128),
+//DEFINE_BUILTIN(pminsb128),
+//DEFINE_BUILTIN(pminsd128),
+//DEFINE_BUILTIN(pminsw),
+//DEFINE_BUILTIN(pminsw128),
+//DEFINE_BUILTIN(pminub),
+//DEFINE_BUILTIN(pminub128),
+//DEFINE_BUILTIN(pminud128),
+//DEFINE_BUILTIN(pminuw128),
+//DEFINE_BUILTIN(pmovmskb),
+//DEFINE_BUILTIN(pmovmskb128),
+//DEFINE_BUILTIN(pmovsxbd128),
+//DEFINE_BUILTIN(pmovsxbq128),
+//DEFINE_BUILTIN(pmovsxbw128),
+//DEFINE_BUILTIN(pmovsxdq128),
+//DEFINE_BUILTIN(pmovsxwd128),
+//DEFINE_BUILTIN(pmovsxwq128),
+//DEFINE_BUILTIN(pmovzxbd128),
+//DEFINE_BUILTIN(pmovzxbq128),
+//DEFINE_BUILTIN(pmovzxbw128),
+//DEFINE_BUILTIN(pmovzxdq128),
+//DEFINE_BUILTIN(pmovzxwd128),
+//DEFINE_BUILTIN(pmovzxwq128),
+//DEFINE_BUILTIN(pmuldq128),
+//DEFINE_BUILTIN(pmulhrsw),
+//DEFINE_BUILTIN(pmulhrsw128),
+//DEFINE_BUILTIN(pmulhrw),
+//DEFINE_BUILTIN(pmulhuw),
+//DEFINE_BUILTIN(pmulhuw128),
+//DEFINE_BUILTIN(pmulhw),
+//DEFINE_BUILTIN(pmulhw128),
+DEFINE_BUILTIN(pmulld128),
+DEFINE_BUILTIN(pmullw),
+DEFINE_BUILTIN(pmullw128),
+//DEFINE_BUILTIN(pmuludq),
+//DEFINE_BUILTIN(pmuludq128),
+DEFINE_BUILTIN(por),
+DEFINE_BUILTIN(por128),
+//DEFINE_BUILTIN(ps256_ps),
+//DEFINE_BUILTIN(psadbw),
+//DEFINE_BUILTIN(psadbw128),
+//DEFINE_BUILTIN(pshufb),
+//DEFINE_BUILTIN(pshufb128),
+DEFINE_BUILTIN(pshufd),
+DEFINE_BUILTIN(pshufhw),
+DEFINE_BUILTIN(pshuflw),
+DEFINE_BUILTIN(pshufw),
+//DEFINE_BUILTIN(psignb),
+//DEFINE_BUILTIN(psignb128),
+//DEFINE_BUILTIN(psignd),
+//DEFINE_BUILTIN(psignd128),
+//DEFINE_BUILTIN(psignw),
+//DEFINE_BUILTIN(psignw128),
+//DEFINE_BUILTIN(pslld),
+//DEFINE_BUILTIN(pslld128),
+//DEFINE_BUILTIN(pslldi),
+//DEFINE_BUILTIN(pslldi128),
+//DEFINE_BUILTIN(pslldqi128),
+//DEFINE_BUILTIN(psllq),
+//DEFINE_BUILTIN(psllq128),
+//DEFINE_BUILTIN(psllqi),
+//DEFINE_BUILTIN(psllqi128),
+//DEFINE_BUILTIN(psllw),
+//DEFINE_BUILTIN(psllw128),
+//DEFINE_BUILTIN(psllwi),
+//DEFINE_BUILTIN(psllwi128),
+//DEFINE_BUILTIN(ps_ps256),
+//DEFINE_BUILTIN(psrad),
+//DEFINE_BUILTIN(psrad128),
+//DEFINE_BUILTIN(psradi),
+//DEFINE_BUILTIN(psradi128),
+//DEFINE_BUILTIN(psraw),
+//DEFINE_BUILTIN(psraw128),
+//DEFINE_BUILTIN(psrawi),
+//DEFINE_BUILTIN(psrawi128),
+//DEFINE_BUILTIN(psrld),
+//DEFINE_BUILTIN(psrld128),
+//DEFINE_BUILTIN(psrldi),
+//DEFINE_BUILTIN(psrldi128),
+//DEFINE_BUILTIN(psrldqi128),
+//DEFINE_BUILTIN(psrlq),
+//DEFINE_BUILTIN(psrlq128),
+//DEFINE_BUILTIN(psrlqi),
+//DEFINE_BUILTIN(psrlqi128),
+//DEFINE_BUILTIN(psrlw),
+//DEFINE_BUILTIN(psrlw128),
+//DEFINE_BUILTIN(psrlwi),
+//DEFINE_BUILTIN(psrlwi128),
+DEFINE_BUILTIN(psubb),
+DEFINE_BUILTIN(psubb128),
+DEFINE_BUILTIN(psubd),
+DEFINE_BUILTIN(psubd128),
+DEFINE_BUILTIN(psubq),
+DEFINE_BUILTIN(psubq128),
+//DEFINE_BUILTIN(psubsb),
+//DEFINE_BUILTIN(psubsb128),
+//DEFINE_BUILTIN(psubsw),
+//DEFINE_BUILTIN(psubsw128),
+//DEFINE_BUILTIN(psubusb),
+//DEFINE_BUILTIN(psubusb128),
+//DEFINE_BUILTIN(psubusw),
+//DEFINE_BUILTIN(psubusw128),
+DEFINE_BUILTIN(psubw),
+DEFINE_BUILTIN(psubw128),
+//DEFINE_BUILTIN(pswapdsf),
+//DEFINE_BUILTIN(pswapdsi),
+//DEFINE_BUILTIN(ptestc128),
+//DEFINE_BUILTIN(ptestc256),
+//DEFINE_BUILTIN(ptestnzc128),
+//DEFINE_BUILTIN(ptestnzc256),
+//DEFINE_BUILTIN(ptestz128),
+//DEFINE_BUILTIN(ptestz256),
+DEFINE_BUILTIN(punpckhbw),
+DEFINE_BUILTIN(punpckhbw128),
+DEFINE_BUILTIN(punpckhdq),
+DEFINE_BUILTIN(punpckhdq128),
+DEFINE_BUILTIN(punpckhqdq128),
+DEFINE_BUILTIN(punpckhwd),
+DEFINE_BUILTIN(punpckhwd128),
+DEFINE_BUILTIN(punpcklbw),
+DEFINE_BUILTIN(punpcklbw128),
+DEFINE_BUILTIN(punpckldq),
+DEFINE_BUILTIN(punpckldq128),
+DEFINE_BUILTIN(punpcklqdq128),
+DEFINE_BUILTIN(punpcklwd),
+DEFINE_BUILTIN(punpcklwd128),
+DEFINE_BUILTIN(pxor),
+DEFINE_BUILTIN(pxor128),
+//DEFINE_BUILTIN(rcpps),
+//DEFINE_BUILTIN(rcpps256),
+//DEFINE_BUILTIN(rcpss),
+//DEFINE_BUILTIN(rdpmc),
+//DEFINE_BUILTIN(rdtsc),
+//DEFINE_BUILTIN(rdtscp),
+//DEFINE_BUILTIN(rolhi),
+//DEFINE_BUILTIN(rolqi),
+//DEFINE_BUILTIN(rorhi),
+//DEFINE_BUILTIN(rorqi),
+//DEFINE_BUILTIN(roundpd),
+//DEFINE_BUILTIN(roundpd256),
+//DEFINE_BUILTIN(roundps),
+//DEFINE_BUILTIN(roundps256),
+//DEFINE_BUILTIN(roundsd),
+//DEFINE_BUILTIN(roundss),
+//DEFINE_BUILTIN(rsqrtf),
+//DEFINE_BUILTIN(rsqrtps),
+//DEFINE_BUILTIN(rsqrtps256),
+//DEFINE_BUILTIN(rsqrtps_nr),
+//DEFINE_BUILTIN(rsqrtps_nr256),
+//DEFINE_BUILTIN(rsqrtss),
+//DEFINE_BUILTIN(sfence),
+DEFINE_BUILTIN(shufpd),
+//DEFINE_BUILTIN(shufpd256),
+DEFINE_BUILTIN(shufps),
+//DEFINE_BUILTIN(shufps256),
+//DEFINE_BUILTIN(si256_si),
+//DEFINE_BUILTIN(si_si256),
+//DEFINE_BUILTIN(sqrtpd),
+//DEFINE_BUILTIN(sqrtpd256),
+//DEFINE_BUILTIN(sqrtps),
+//DEFINE_BUILTIN(sqrtps256),
+//DEFINE_BUILTIN(sqrtps_nr),
+//DEFINE_BUILTIN(sqrtps_nr256),
+//DEFINE_BUILTIN(sqrtsd),
+//DEFINE_BUILTIN(sqrtss),
+DEFINE_BUILTIN(stmxcsr),
+DEFINE_BUILTIN(storedqu),
+//DEFINE_BUILTIN(storedqu256),
+DEFINE_BUILTIN(storehps),
+DEFINE_BUILTIN(storelps),
+DEFINE_BUILTIN(storeupd),
+//DEFINE_BUILTIN(storeupd256),
+DEFINE_BUILTIN(storeups),
+//DEFINE_BUILTIN(storeups256),
+DEFINE_BUILTIN(subpd),
+DEFINE_BUILTIN(subpd256),
+DEFINE_BUILTIN(subps),
+DEFINE_BUILTIN(subps256),
+//DEFINE_BUILTIN(subsd),
+//DEFINE_BUILTIN(subss),
+//DEFINE_BUILTIN(ucomieq),
+//DEFINE_BUILTIN(ucomige),
+//DEFINE_BUILTIN(ucomigt),
+//DEFINE_BUILTIN(ucomile),
+//DEFINE_BUILTIN(ucomilt),
+//DEFINE_BUILTIN(ucomineq),
+//DEFINE_BUILTIN(ucomisdeq),
+//DEFINE_BUILTIN(ucomisdge),
+//DEFINE_BUILTIN(ucomisdgt),
+//DEFINE_BUILTIN(ucomisdle),
+//DEFINE_BUILTIN(ucomisdlt),
+//DEFINE_BUILTIN(ucomisdneq),
+DEFINE_BUILTIN(unpckhpd),
+//DEFINE_BUILTIN(unpckhpd256),
+DEFINE_BUILTIN(unpckhps),
+//DEFINE_BUILTIN(unpckhps256),
+DEFINE_BUILTIN(unpcklpd),
+//DEFINE_BUILTIN(unpcklpd256),
+DEFINE_BUILTIN(unpcklps),
+//DEFINE_BUILTIN(unpcklps256),
+//DEFINE_BUILTIN(vbroadcastf128_pd256),
+//DEFINE_BUILTIN(vbroadcastf128_ps256),
+//DEFINE_BUILTIN(vbroadcastsd256),
+//DEFINE_BUILTIN(vbroadcastss),
+//DEFINE_BUILTIN(vbroadcastss256),
+DEFINE_BUILTIN(vec_ext_v16qi),
+DEFINE_BUILTIN(vec_ext_v2df),
+DEFINE_BUILTIN(vec_ext_v2di),
+DEFINE_BUILTIN(vec_ext_v2si),
+DEFINE_BUILTIN(vec_ext_v4hi),
+DEFINE_BUILTIN(vec_ext_v4sf),
+DEFINE_BUILTIN(vec_ext_v4si),
+DEFINE_BUILTIN(vec_ext_v8hi),
+DEFINE_BUILTIN(vec_init_v2si),
+DEFINE_BUILTIN(vec_init_v4hi),
+DEFINE_BUILTIN(vec_init_v8qi),
+//DEFINE_BUILTIN(vec_pack_sfix),
+DEFINE_BUILTIN(vec_set_v16qi),
+DEFINE_BUILTIN(vec_set_v2di),
+DEFINE_BUILTIN(vec_set_v4hi),
+//DEFINE_BUILTIN(vec_set_v4sf),
+DEFINE_BUILTIN(vec_set_v4si),
+DEFINE_BUILTIN(vec_set_v8hi),
+//DEFINE_BUILTIN(vextractf128_pd256),
+//DEFINE_BUILTIN(vextractf128_ps256),
+//DEFINE_BUILTIN(vextractf128_si256),
+//DEFINE_BUILTIN(vfmaddpd),
+//DEFINE_BUILTIN(vfmaddpd256),
+//DEFINE_BUILTIN(vfmaddps),
+//DEFINE_BUILTIN(vfmaddps256),
+//DEFINE_BUILTIN(vfmaddsd),
+//DEFINE_BUILTIN(vfmaddss),
+//DEFINE_BUILTIN(vfmaddsubpd),
+//DEFINE_BUILTIN(vfmaddsubpd256),
+//DEFINE_BUILTIN(vfmaddsubps),
+//DEFINE_BUILTIN(vfmaddsubps256),
+//DEFINE_BUILTIN(vfmsubaddpd),
+//DEFINE_BUILTIN(vfmsubaddpd256),
+//DEFINE_BUILTIN(vfmsubaddps),
+//DEFINE_BUILTIN(vfmsubaddps256),
+//DEFINE_BUILTIN(vfmsubpd),
+//DEFINE_BUILTIN(vfmsubpd256),
+//DEFINE_BUILTIN(vfmsubps),
+//DEFINE_BUILTIN(vfmsubps256),
+//DEFINE_BUILTIN(vfmsubsd),
+//DEFINE_BUILTIN(vfmsubss),
+//DEFINE_BUILTIN(vfnmaddpd),
+//DEFINE_BUILTIN(vfnmaddpd256),
+//DEFINE_BUILTIN(vfnmaddps),
+//DEFINE_BUILTIN(vfnmaddps256),
+//DEFINE_BUILTIN(vfnmaddsd),
+//DEFINE_BUILTIN(vfnmaddss),
+//DEFINE_BUILTIN(vfnmsubpd),
+//DEFINE_BUILTIN(vfnmsubpd256),
+//DEFINE_BUILTIN(vfnmsubps),
+//DEFINE_BUILTIN(vfnmsubps256),
+//DEFINE_BUILTIN(vfnmsubsd),
+//DEFINE_BUILTIN(vfnmsubss),
+//DEFINE_BUILTIN(vinsertf128_pd256),
+//DEFINE_BUILTIN(vinsertf128_ps256),
+//DEFINE_BUILTIN(vinsertf128_si256),
+//DEFINE_BUILTIN(vperm2f128_pd256),
+//DEFINE_BUILTIN(vperm2f128_ps256),
+//DEFINE_BUILTIN(vperm2f128_si256),
+//DEFINE_BUILTIN(vpermilpd),
+//DEFINE_BUILTIN(vpermilpd256),
+//DEFINE_BUILTIN(vpermilps),
+//DEFINE_BUILTIN(vpermilps256),
+//DEFINE_BUILTIN(vpermilvarpd),
+//DEFINE_BUILTIN(vpermilvarpd256),
+//DEFINE_BUILTIN(vpermilvarps),
+//DEFINE_BUILTIN(vpermilvarps256),
+//DEFINE_BUILTIN(vtestcpd),
+//DEFINE_BUILTIN(vtestcpd256),
+//DEFINE_BUILTIN(vtestcps),
+//DEFINE_BUILTIN(vtestcps256),
+//DEFINE_BUILTIN(vtestnzcpd),
+//DEFINE_BUILTIN(vtestnzcpd256),
+//DEFINE_BUILTIN(vtestnzcps),
+//DEFINE_BUILTIN(vtestnzcps256),
+//DEFINE_BUILTIN(vtestzpd),
+//DEFINE_BUILTIN(vtestzpd256),
+//DEFINE_BUILTIN(vtestzps),
+//DEFINE_BUILTIN(vtestzps256),
+//DEFINE_BUILTIN(vzeroall),
+DEFINE_BUILTIN(xorpd),
+DEFINE_BUILTIN(xorpd256),
+DEFINE_BUILTIN(xorps),
+DEFINE_BUILTIN(xorps256)



From baldrick at free.fr  Sun Sep 26 09:00:14 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 14:00:14 -0000
Subject: [llvm-commits] [dragonegg] r114805 -
	/dragonegg/trunk/x86/llvm-target.cpp
Message-ID: <20100926140014.765182A6C12C@llvm.org>

Author: baldrick
Date: Sun Sep 26 09:00:14 2010
New Revision: 114805

URL: http://llvm.org/viewvc/llvm-project?rev=114805&view=rev
Log:
Fix builtin matching after the previous commit: adjust for dropping the
__builtin_ia32_ prefix from builtin names.

Modified:
    dragonegg/trunk/x86/llvm-target.cpp

Modified: dragonegg/trunk/x86/llvm-target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=114805&r1=114804&r2=114805&view=diff
==============================================================================
--- dragonegg/trunk/x86/llvm-target.cpp (original)
+++ dragonegg/trunk/x86/llvm-target.cpp Sun Sep 26 09:00:14 2010
@@ -113,8 +113,9 @@
       Checked = true;
     }
 #endif
-    HandlerEntry ToFind
-      = {IDENTIFIER_POINTER(DECL_NAME(fndecl)), SearchForHandler};
+    const char *Identifier = IDENTIFIER_POINTER(DECL_NAME(fndecl));
+    assert(!strncmp(Identifier, "__builtin_ia32_", 15) && "Unexpected prefix!");
+    HandlerEntry ToFind = {Identifier + 15, SearchForHandler};
     const HandlerEntry *E = std::lower_bound(Handlers, Handlers + N, ToFind, LT);
     Handler = (E == Handlers + N) || strcmp(E->Name, ToFind.Name) ?
       UnsupportedBuiltin : E->Handler;



From baldrick at free.fr  Sun Sep 26 11:03:03 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Sep 2010 16:03:03 -0000
Subject: [llvm-commits] [dragonegg] r114806 -
	/dragonegg/trunk/x86/llvm-target.cpp
Message-ID: <20100926160303.7EC2C2A6C12C@llvm.org>

Author: baldrick
Date: Sun Sep 26 11:03:03 2010
New Revision: 114806

URL: http://llvm.org/viewvc/llvm-project?rev=114806&view=rev
Log:
If a builtin is seen with a name that does not start with
__builtin_ia32_, then consider it unsupported rather than
asserting.  Add a some explanatory comments while there.

Modified:
    dragonegg/trunk/x86/llvm-target.cpp

Modified: dragonegg/trunk/x86/llvm-target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=114806&r1=114805&r2=114806&view=diff
==============================================================================
--- dragonegg/trunk/x86/llvm-target.cpp (original)
+++ dragonegg/trunk/x86/llvm-target.cpp Sun Sep 26 11:03:03 2010
@@ -65,6 +65,7 @@
                                                    VecTy->getNumElements()));
 }
 
+/// BuiltinCode - A enumerated type with one value for each supported builtin.
 enum BuiltinCode {
   SearchForHandler, // Builtin not seen before - search for a handler.
 #define DEFINE_BUILTIN(x) x
@@ -91,18 +92,31 @@
                                       Value *&Result,
                                       const Type *ResultType,
                                       std::vector<Value*> &Ops) {
-  static const HandlerEntry Handlers[] = {
+  // DECL_FUNCTION_CODE contains a value of the enumerated type ix86_builtins,
+  // declared in i386.c.  If this type was visible to us then we could simply
+  // use a switch statement on DECL_FUNCTION_CODE to jump to the right code for
+  // handling the builtin.  But the type isn't visible, so instead we generate
+  // at run-time a map from the values of DECL_FUNCTION_CODE to values of the
+  // enumerated type BuiltinCode (defined above), the analog of ix86_builtins,
+  // and do the switch on the BuiltinCode value instead.
+
+  // The map from DECL_FUNCTION_CODE values to BuiltinCode.
+  static std::vector<BuiltinCode> FunctionCodeMap;
+  if (FunctionCodeMap.size() <= DECL_FUNCTION_CODE(fndecl))
+      FunctionCodeMap.resize(DECL_FUNCTION_CODE(fndecl) + 1);
+
+  // See if we already associated a BuiltinCode with this DECL_FUNCTION_CODE.
+  BuiltinCode &Handler = FunctionCodeMap[DECL_FUNCTION_CODE(fndecl)];
+  if (Handler == SearchForHandler) {
+    // No associated BuiltinCode.  Work out what value to use based on the
+    // builtin's name.
+
+    // List of builtin names (w/o '__builtin_ia32_') and associated BuiltinCode.
+    static const HandlerEntry Handlers[] = {
 #define DEFINE_BUILTIN(x) {#x, x}
 #include "x86_builtins"
 #undef DEFINE_BUILTIN
-  };
-
-  static std::vector<BuiltinCode> FunctionCodeCache;
-  if (FunctionCodeCache.size() <= DECL_FUNCTION_CODE(fndecl))
-      FunctionCodeCache.resize(DECL_FUNCTION_CODE(fndecl) + 1);
-  BuiltinCode &Handler = FunctionCodeCache[DECL_FUNCTION_CODE(fndecl)];
-  if (Handler == SearchForHandler) {
-    // Find the handler for this intrinsic.
+    };
     size_t N = sizeof(Handlers) / sizeof(Handlers[0]);
 #ifndef NDEBUG
     // Check that the list of handlers is sorted by name.
@@ -113,12 +127,16 @@
       Checked = true;
     }
 #endif
+
+    Handler = UnsupportedBuiltin;
     const char *Identifier = IDENTIFIER_POINTER(DECL_NAME(fndecl));
-    assert(!strncmp(Identifier, "__builtin_ia32_", 15) && "Unexpected prefix!");
-    HandlerEntry ToFind = {Identifier + 15, SearchForHandler};
-    const HandlerEntry *E = std::lower_bound(Handlers, Handlers + N, ToFind, LT);
-    Handler = (E == Handlers + N) || strcmp(E->Name, ToFind.Name) ?
-      UnsupportedBuiltin : E->Handler;
+    // All builtins handled here have a name starting with __builtin_ia32_.
+    if (!strncmp(Identifier, "__builtin_ia32_", 15)) {
+      HandlerEntry ToFind = { Identifier + 15, SearchForHandler };
+      const HandlerEntry *E = std::lower_bound(Handlers, Handlers + N, ToFind, LT);
+      if ((E < Handlers + N) && !strcmp(E->Name, ToFind.Name))
+        Handler = E->Handler;
+    }
   }
 
   bool flip = false;



From aggarwa4 at illinois.edu  Sun Sep 26 11:27:09 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Sun, 26 Sep 2010 16:27:09 -0000
Subject: [llvm-commits] [poolalloc] r114807 -
	/poolalloc/trunk/include/dsa/DSNode.h
Message-ID: <20100926162709.434A52A6C12C@llvm.org>

Author: aggarwa4
Date: Sun Sep 26 11:27:09 2010
New Revision: 114807

URL: http://llvm.org/viewvc/llvm-project?rev=114807&view=rev
Log:
growSize, should not shrink the node. Keeping the size same should be fine.

Modified:
    poolalloc/trunk/include/dsa/DSNode.h

Modified: poolalloc/trunk/include/dsa/DSNode.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSNode.h?rev=114807&r1=114806&r2=114807&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSNode.h (original)
+++ poolalloc/trunk/include/dsa/DSNode.h Sun Sep 26 11:27:09 2010
@@ -200,8 +200,8 @@
   }
 
   void growSize(unsigned NSize) {
-    assert(NSize > Size && "Cannot shrink");
-    assert(!isCollapsedNode() && "growing a collapsed node");
+    assert(NSize >= Size && "Cannot shrink");
+    assert(!isCollapsedNode() && "Growing a collapsed node");
     Size = NSize;
   }
 



From bigcheesegs at gmail.com  Sun Sep 26 15:59:04 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Sun, 26 Sep 2010 16:59:04 -0400
Subject: [llvm-commits] lit configuration for test-suite and some minor test
	changes for MSVC.
Message-ID: <AANLkTi=Hze5iejv_jGYmUvZavz+tiGqMHz0CSk_qTZVh@mail.gmail.com>

Attached is a lit configuration for running the single source tests in
the test suite. It has been tested on Linux and Windows with MSVC,
clang, and gcc.

Usage:
To use this simply call lit.py (llvm-lit does not currently know how
to run these tests) and pass it a directory under
test-suite/SingleSource. The config looks for available compilers in
PATH and runs each one it finds on each source file that also has a
.reference_output.

Options:
The following --param's are supported.
* no-default-flags={True,False} - Defaults to False. If True no
default flags are used on any compiler. This only includes flags set
in the lit.cfg, not those set in lit.local.cfg.
* <compiler>_[<lang>_]flags - Defaults to "". A space separated quoted
string of arguments. The exact semantics are explained below.

Flags are formatted as [<compiler>_][<lang>_]flags.
They are loaded first from lit.cfg, then lit.site.cfg, then the
lit.local.cfg's, and finally from the command line using --param. Flags
specified in lit config files follow Python list rules for replacement,
appending, and removing. Flags specified in --param are replaced if the first
char is '=', appended if it is '+=', and removed if it is '-='.

The available flags are:
* <compiler>_flags are used for all languages on <compiler>.
* <compiler>_<lang>_flags are used for <lang> in {c, cxx, objc, objcxx} on
  <compiler>.
* gcccompatible_[<lang>_]flags are used for all gcc compatible compilers. The
  lang option is the same as above.

flags are added/removed in the following order AFTER each has been loaded and
merged:
* gcccompatible_flags - if the compiler supports them
* <compiler>_flags
* gcccompatible_<lang>_flags - if the compiler supports them
* <compiler>_<lang>_flags

Currently supported compilers are:
* MSVC - Microsoft Visual C/C++. Which ever version is on the PATH is used.
  This can be changed by running the vcvars.bat script of the on you want to
  use and then run lit from that environment.
* clang - The LLVM C Language Family Compiler.
* gcc - The GNU Compiler Collection.

lit.local.cfg:
The compilation of each source file is configurable with the following
variables in each directory's lit.local.cfg (they default to whatever
value the parent config had).

* config.(all the flags above) - These follow the Python list rules. -
ex. config.gcccombatible_flags -= ['-fomit-frame-pointer'] # Removes
-fomit-frame-pointer from flags.
* config.unsupported['<compiler>']. - This is either a list of strings
of unsupported files (without extension), or the value True if none
are supported.
* config.compilers - A dictionary mapping compiler names to compilers.
This may be used to add a compiler for a specific directory.
* config.hashed - If this is True, the output of the program is hashed
using md5 before it is compared to the reference output.

TODO:
There are a few issues with this config, many of which stem from lit
infrastructure problems that Daniel and I have been discussing.
However, there are others unrelated to that:
* There is currently no way to specify exactly which executables to
use to compile, link, JIT, and such. This needs to be set in a
lit.site.cfg and have an associated param.
* With the current setup there are two different "compilers" for
native executables (which actually generates two executables. One with
integrated as and one without) and bitcode to be run with lli. What I
would like is to separate compilers from what is being generated. A
major use of this would be to directly compare the same compiler with
a different set of flags.
* There's currently no way to generate statistics other than
PASS/FAIL. I would like to be able to be able to get the time
measurement granularity down to {compile, [JIT,] run}.

I'm sure there are other issues, but I think it's far enough along for
others to test out.

I have also attached another patch that contains (for some tests) the
minimal changes required to get them to compile with MSVC and clang on
Windows. Most of them are header file issues, but some are due to
MSVC's ignorance of any recent C standard. The rest are differences in
extensions.

I thought about just adding headers with the same name as the ones
Windows doesn't have have including them on Windows, but I decided
against because then the tests would no longer be stand alone. Running
them without lit would require explicitly adding some crazy include
path on the command line that is not stable across systems.

- Michael Spencer
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From sabre at nondot.org  Sun Sep 26 23:23:03 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 27 Sep 2010 04:23:03 -0000
Subject: [llvm-commits] [llvm] r114809 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp
 test/MC/AsmParser/X86/x86_instructions.s
Message-ID: <20100927042303.390BF2A6C12C@llvm.org>

Author: lattner
Date: Sun Sep 26 23:23:03 2010
New Revision: 114809

URL: http://llvm.org/viewvc/llvm-project?rev=114809&view=rev
Log:
implement support for 'clr' alias.  This is part of rdar://8416805,
but balrog was wanting it on irc.

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=114809&r1=114808&r2=114809&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sun Sep 26 23:23:03 2010
@@ -1052,6 +1052,17 @@
     Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
   }
   
+  
+  // "clr <reg>" -> "xor <reg>, <reg>".
+  if ((Name == "clrb" || Name == "clrw" || Name == "clrl" || Name == "clrq" ||
+       Name == "clr") && Operands.size() == 2 &&
+      static_cast<X86Operand*>(Operands[1])->isReg()) {
+    unsigned RegNo = static_cast<X86Operand*>(Operands[1])->getReg();
+    Operands.push_back(X86Operand::CreateReg(RegNo, NameLoc, NameLoc));
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken("xor", NameLoc);
+  }
+  
   return false;
 }
 

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=114809&r1=114808&r2=114809&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Sun Sep 26 23:23:03 2010
@@ -360,4 +360,18 @@
 faddp %st, %st(1)
 fmulp %st, %st(2)
 
+// rdar://8416805
+// CHECK: xorb	%al, %al
+// CHECK: encoding: [0x30,0xc0]
+// CHECK: xorw	%di, %di
+// CHECK: encoding: [0x66,0x31,0xff]
+// CHECK: xorl	%esi, %esi
+// CHECK: encoding: [0x31,0xf6]
+// CHECK: xorq	%rsi, %rsi
+// CHECK: encoding: [0x48,0x31,0xf6]
+clrb    %al
+clr    %di
+clr    %esi
+clr    %rsi
+