From bigcheesegs at gmail.com  Mon Oct 25 01:16:48 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Mon, 25 Oct 2010 02:16:48 -0400
Subject: [llvm-commits] [PATCH] Start of support for
	__attribute__((ms_hook_prologue))
In-Reply-To: <4CC4E0BF.50107@mymail.mines.edu>
References: <4CC4E0BF.50107@mymail.mines.edu>
Message-ID: <AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>

On Sun, Oct 24, 2010 at 9:43 PM, Charles Davis <cdavis at mymail.mines.edu> wrote:
> Hi,
>
> I thought that, while I wait for a response to my latest clang "patch"
> on cfe-dev, I'd work on something else Wine-related.
>
> Microsoft's compiler has a switch, '/hotpatch', that inserts a magic
> sequence in the beginning of every compiled function. This sequence lets
> other DLLs hook these functions (assuming they were exported from a DLL)
> to do interesting things when they're called. In response, GCC added an
> attribute, 'ms_hook_prologue', that does the same in GCC (partially at
> the behest of the Wine developers). And now I intend to do the same for
> Clang.
>
> Of course, this needs backend support. So, as with my
> 'force_align_arg_pointer' patches, I'm starting with the basics. This
> patch adds support for the attribute in LLVM IR. OK to commit?
>
> Chip

I'm not convinced that a new attribute is needed. We already have
dllexport linkage, so why not just add an option that makes all
dllexport functions hot patchable? It doesn't change the calling
convention at all.

Also, this doesn't seem to include the lexing or parsing code for the keyword.

- Michael Spencer

From pichet2000 at gmail.com  Mon Oct 25 01:38:07 2010
From: pichet2000 at gmail.com (Francois Pichet)
Date: Mon, 25 Oct 2010 02:38:07 -0400
Subject: [llvm-commits] [PATCH] Teach CMake to only touch
 tablegen-generated files if anything actually changed.
In-Reply-To: <874occmvzv.fsf@telefonica.net>
References: <AANLkTinGnB19yKYCyN9MtcAbZFO6Yv1ZiHqWs3QgNFLZ@mail.gmail.com>
	<87eibimbym.fsf@telefonica.net>
	<AANLkTim3gsZ83W9xgwEFQC+L-QFdzz6VS+MT0NZvRrUA@mail.gmail.com>
	<AANLkTik_3iUoqZtenN+T9YViEACd6uuB5Tpmdfb2ZaV3@mail.gmail.com>
	<878w1qm8bf.fsf@telefonica.net>
	<AANLkTi=mV5NzOro5Q5998qMfHSJd43hwLywfBLbm55Ak@mail.gmail.com>
	<874occmvzv.fsf@telefonica.net>
Message-ID: <AANLkTi=XPmkkUYChOb7OyyLUo0gnFf1bRPGScTnLfs0w@mail.gmail.com>

On Sat, Oct 23, 2010 at 5:37 PM, ?scar Fuentes <ofv at wanadoo.es> wrote:
> Francois Pichet <pichet2000 at gmail.com> writes:
>
>> I don't know if this patch is the problem but there is problem with
>> CMake dependency on VS2008 since 2-3 ago. When I select the the
>> "clang-test" project and build (to run the test). The project
>> LLVMX86CodeGen always get recompiled even if nothing has changed. This
>> is annoying as I run the test very very often. Now i have to revert
>> back to using the command line to run the clang lit test.
>
> Please open a bug report on Bugzilla an attach the full contents of the
> Output window after building the `clang-test' target.

Nevermind, I did a clean checkout rebuilded and the issue is gone.


From baldrick at free.fr  Mon Oct 25 02:42:56 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 07:42:56 -0000
Subject: [llvm-commits] [dragonegg] r117253 -
	/dragonegg/trunk/llvm-backend.cpp
Message-ID: <20101025074256.993152A6C12D@llvm.org>

Author: baldrick
Date: Mon Oct 25 02:42:56 2010
New Revision: 117253

URL: http://llvm.org/viewvc/llvm-project?rev=117253&view=rev
Log:
Turn on the ODR for C++ - see if this still breaks the x86-32
self-host.

Modified:
    dragonegg/trunk/llvm-backend.cpp

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=117253&r1=117252&r2=117253&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Mon Oct 25 02:42:56 2010
@@ -537,7 +537,7 @@
   } else if (LanguageName == "GNU C") {
     flag_vararg_requires_arguments = true; // "T foo() {}" -> "T foo(void) {}"
   } else if (LanguageName == "GNU C++") {
-//    flag_odr = true; // C++ obeys the one-definition-rule
+    flag_odr = true; // C++ obeys the one-definition-rule
   } else if (LanguageName == "GNU Fortran") {
   } else if (LanguageName == "GNU GIMPLE") { // LTO gold plugin
   } else if (LanguageName == "GNU Java") {



From ggreif at gmail.com  Mon Oct 25 03:28:28 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 25 Oct 2010 10:28:28 +0200
Subject: [llvm-commits] [PATCH,
 PING] Peephole Infrastructure improvements and (ARM, T,
 T2) TSTrr optimizations
In-Reply-To: <AANLkTi=Zh7SLJAHG_Uf2TBweKQvZ9_8UFbEbeWPkwrTz@mail.gmail.com>
References: <AANLkTi=Zh7SLJAHG_Uf2TBweKQvZ9_8UFbEbeWPkwrTz@mail.gmail.com>
Message-ID: <AANLkTimndokWkx-UW+EeVkNwPPKpyTxyEJa-+wGu1wJS@mail.gmail.com>

Ping!

Attached the diff against recent trunk.

Cheers,

    Gabor

On 10/21/10, Gabor Greif <ggreif at gmail.com> wrote:
> Hi all,
>
> the last weeks I've been working on a flexible infrastructure for
> peephole optimizations, which is potentially target independent and
> extensible without needing interface changes.
>
> The result of my work is attached. It moves all current ARM peepholes
> over to the new architecture and adds TSTrr-related optimizations too.
>
> The ordering and forward referencing of functions is still suboptimal,
> but this is only done to keep the patch size manageable. I plan to
> reorder in a cleanup commit after this patch has landed. Also some
> currently freestanding functions will become methods.
>
> You can also see the code in its entirety here:
> <http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/>
>
> Feedback is welcome.
>
> Cheers,
>
>     Gabor
>
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From kalle.raiskila at nokia.com  Mon Oct 25 03:57:30 2010
From: kalle.raiskila at nokia.com (Kalle Raiskila)
Date: Mon, 25 Oct 2010 08:57:30 -0000
Subject: [llvm-commits] [llvm] r117255 - /llvm/trunk/docs/CodeGenerator.html
Message-ID: <20101025085730.73F002A6C12C@llvm.org>

Author: kraiskil
Date: Mon Oct 25 03:57:30 2010
New Revision: 117255

URL: http://llvm.org/viewvc/llvm-project?rev=117255&view=rev
Log:
Update target feature matrix for CellSPU

Modified:
    llvm/trunk/docs/CodeGenerator.html

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=117255&r1=117254&r2=117255&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Mon Oct 25 03:57:30 2010
@@ -1976,7 +1976,7 @@
   <td class="yes"></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
-  <td class="unknown"></td> <!-- CellSPU -->
+  <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
   <td class="unknown"></td> <!-- Mips -->
@@ -2027,7 +2027,7 @@
   <td class="yes"></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
   <td class="yes"></td> <!-- Blackfin -->
-  <td class="unknown"></td> <!-- CellSPU -->
+  <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
   <td class="unknown"></td> <!-- Mips -->
@@ -2044,7 +2044,7 @@
   <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
-  <td class="unknown"></td> <!-- CellSPU -->
+  <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
   <td class="unknown"></td> <!-- Mips -->
@@ -2078,7 +2078,7 @@
   <td class="yes"></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- Blackfin -->
-  <td class="unknown"></td> <!-- CellSPU -->
+  <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
   <td class="unknown"></td> <!-- Mips -->



From cdavis at mymail.mines.edu  Mon Oct 25 05:42:00 2010
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 04:42:00 -0600
Subject: [llvm-commits] [PATCH] Start of support for
	__attribute__((ms_hook_prologue))
In-Reply-To: <AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>
References: <4CC4E0BF.50107@mymail.mines.edu>
	<AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>
Message-ID: <4CC55EF8.4020100@mymail.mines.edu>

On 10/25/10 12:16 AM, Michael Spencer wrote:
> On Sun, Oct 24, 2010 at 9:43 PM, Charles Davis <cdavis at mymail.mines.edu> wrote:
>> Hi,
>>
>> I thought that, while I wait for a response to my latest clang "patch"
>> on cfe-dev, I'd work on something else Wine-related.
>>
>> Microsoft's compiler has a switch, '/hotpatch', that inserts a magic
>> sequence in the beginning of every compiled function. This sequence lets
>> other DLLs hook these functions (assuming they were exported from a DLL)
>> to do interesting things when they're called. In response, GCC added an
>> attribute, 'ms_hook_prologue', that does the same in GCC (partially at
>> the behest of the Wine developers). And now I intend to do the same for
>> Clang.
>>
>> Of course, this needs backend support. So, as with my
>> 'force_align_arg_pointer' patches, I'm starting with the basics. This
>> patch adds support for the attribute in LLVM IR. OK to commit?
>>
>> Chip
> 
> I'm not convinced that a new attribute is needed.
All right then, let me convince you.
> We already have
> dllexport linkage, so why not just add an option that makes all
> dllexport functions hot patchable? It doesn't change the calling
> convention at all.
Several reasons:
- This adds some noop instruction(s) to the beginning of the function.
(On x86, it adds a 'mov %edi,%edi'.) This could potentially affect
performance if the function is called over and over again. Are you sure
you want all dllexport functions to be hotpatchable?
- Not everyone uses dllexport. Some people still use .def files. Wine is
one notable example (though the .def files are autogenerated). They
declare some of their functions with this attribute.
- GCC already has this attribute. It's too late.
> 
> Also, this doesn't seem to include the lexing or parsing code for the keyword.
It was only missing the lexing code. Patch reattached.
> 
> - Michael Spencer

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From bigcheesegs at gmail.com  Mon Oct 25 06:03:25 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Mon, 25 Oct 2010 07:03:25 -0400
Subject: [llvm-commits] [PATCH] Start of support for
	__attribute__((ms_hook_prologue))
In-Reply-To: <4CC55EF8.4020100@mymail.mines.edu>
References: <4CC4E0BF.50107@mymail.mines.edu>
	<AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>
	<4CC55EF8.4020100@mymail.mines.edu>
Message-ID: <AANLkTi=kQKyZ1uV2Mx=t6ssj6vsrjhSCUUviTDcMLrV+@mail.gmail.com>

On Mon, Oct 25, 2010 at 6:42 AM, Charles Davis <cdavis at mymail.mines.edu> wrote:
> On 10/25/10 12:16 AM, Michael Spencer wrote:
>> On Sun, Oct 24, 2010 at 9:43 PM, Charles Davis <cdavis at mymail.mines.edu> wrote:
>>> Hi,
>>>
>>> I thought that, while I wait for a response to my latest clang "patch"
>>> on cfe-dev, I'd work on something else Wine-related.
>>>
>>> Microsoft's compiler has a switch, '/hotpatch', that inserts a magic
>>> sequence in the beginning of every compiled function. This sequence lets
>>> other DLLs hook these functions (assuming they were exported from a DLL)
>>> to do interesting things when they're called. In response, GCC added an
>>> attribute, 'ms_hook_prologue', that does the same in GCC (partially at
>>> the behest of the Wine developers). And now I intend to do the same for
>>> Clang.
>>>
>>> Of course, this needs backend support. So, as with my
>>> 'force_align_arg_pointer' patches, I'm starting with the basics. This
>>> patch adds support for the attribute in LLVM IR. OK to commit?
>>>
>>> Chip
>>
>> I'm not convinced that a new attribute is needed.
> All right then, let me convince you.
>> We already have
>> dllexport linkage, so why not just add an option that makes all
>> dllexport functions hot patchable? It doesn't change the calling
>> convention at all.
> Several reasons:
> - This adds some noop instruction(s) to the beginning of the function.
> (On x86, it adds a 'mov %edi,%edi'.) This could potentially affect
> performance if the function is called over and over again. Are you sure
> you want all dllexport functions to be hotpatchable?

It actually only requires that the first instruction be two bytes.

> - Not everyone uses dllexport. Some people still use .def files. Wine is
> one notable example (though the .def files are autogenerated). They
> declare some of their functions with this attribute.

OK.

> - GCC already has this attribute. It's too late.

We don't have to implement all gcc features.

>>
>> Also, this doesn't seem to include the lexing or parsing code for the keyword.
> It was only missing the lexing code. Patch reattached.
>>
>> - Michael Spencer

Individually choosing functions to apply this to independent of
dllexport is a good enough reason for me. I have no objections.

From anton at korobeynikov.info  Mon Oct 25 06:08:56 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Mon, 25 Oct 2010 15:08:56 +0400
Subject: [llvm-commits] [PATCH] Start of support for
	__attribute__((ms_hook_prologue))
In-Reply-To: <AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>
References: <4CC4E0BF.50107@mymail.mines.edu>
	<AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>
Message-ID: <AANLkTime5N9WwG6+TBNmQggJKqXM+Hd=ji+=8=2wy1pp@mail.gmail.com>

Michael,

> I'm not convinced that a new attribute is needed. We already have
> dllexport linkage, so why not just add an option that makes all
> dllexport functions hot patchable? It doesn't change the calling
> convention at all.
I don't see why this should be connected to dllexport stuff at all.
One definitely might want to make a non-dllexported function
hot-patchable.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From baldrick at free.fr  Mon Oct 25 06:24:02 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 11:24:02 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r117257 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-abi.h llvm-convert.cpp
Message-ID: <20101025112403.0878D2A6C12C@llvm.org>

Author: baldrick
Date: Mon Oct 25 06:24:02 2010
New Revision: 117257

URL: http://llvm.org/viewvc/llvm-project?rev=117257&view=rev
Log:
Use the cast-to-void idiom rather than ATTRIBUTE_UNUSED to avoid
warnings about deliberately unused variables.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-abi.h
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=117257&r1=117256&r2=117257&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Mon Oct 25 06:24:02 2010
@@ -37,7 +37,6 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/LLVMContext.h"
 #include "llvm/Target/TargetData.h"
-#include "llvm/Support/Compiler.h"
 
 namespace llvm {
   class BasicBlock;
@@ -103,8 +102,9 @@
 
   /// HandleFCAArgument - This callback is invoked if the aggregate function
   /// argument is passed by value as a first class aggregate.
-  virtual void HandleFCAArgument(const llvm::Type *LLVMTy,
-                         tree type ATTRIBUTE_UNUSED) {}
+  virtual void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
+    (void)LLVMTy; (void)type; // Unused.
+  }
 
   /// EnterField - Called when we're about the enter the field of a struct
   /// or union.  FieldNo is the number of the element we are entering in the

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=117257&r1=117256&r2=117257&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Oct 25 06:24:02 2010
@@ -402,8 +402,8 @@
       ++AI;
     }
 
-    void HandleFCAArgument(const llvm::Type *LLVMTy,
-                           tree type ATTRIBUTE_UNUSED) {
+    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
+      (void)type; // Unused.
       // Store the FCA argument into alloca.
       assert(!LocStack.empty());
       Value *Loc = LocStack.back();
@@ -2940,8 +2940,8 @@
 
     /// HandleFCAArgument - This callback is invoked if the aggregate function
     /// argument is passed as a first class aggregate.
-    void HandleFCAArgument(const llvm::Type *LLVMTy,
-                           tree type ATTRIBUTE_UNUSED) {
+    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
+      (void)type; // Unused.
       Value *Loc = getAddress();
       assert(LLVMTy->getPointerTo() == Loc->getType());
       CallOperands.push_back(Builder.CreateLoad(Loc));
@@ -6413,8 +6413,8 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinBZero(tree exp,
-                                  Value *&Result ATTRIBUTE_UNUSED) {
+bool TreeToLLVM::EmitBuiltinBZero(tree exp, Value *&Result) {
+  (void)Result; // Unused.
   tree arglist = TREE_OPERAND(exp, 1);
   if (!validate_arglist(arglist, POINTER_TYPE, INTEGER_TYPE, VOID_TYPE))
     return false;
@@ -6656,8 +6656,8 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(tree exp,
-                                              Value *&Result ATTRIBUTE_UNUSED) {
+bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(tree exp, Value *&Result) {
+  (void)Result; // Unused.
 #ifdef DWARF2_UNWIND_INFO
   unsigned int i;
   bool wrote_return_column = false;



From baldrick at free.fr  Mon Oct 25 06:50:18 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 11:50:18 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r117258 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-abi.h llvm-convert.cpp
Message-ID: <20101025115018.1AFF02A6C12C@llvm.org>

Author: baldrick
Date: Mon Oct 25 06:50:17 2010
New Revision: 117258

URL: http://llvm.org/viewvc/llvm-project?rev=117258&view=rev
Log:
In which I learn from Chandler the trick of simply omitting names
for unused parameters.  What a language!

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-abi.h
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=117258&r1=117257&r2=117258&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Mon Oct 25 06:50:17 2010
@@ -102,9 +102,7 @@
 
   /// HandleFCAArgument - This callback is invoked if the aggregate function
   /// argument is passed by value as a first class aggregate.
-  virtual void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
-    (void)LLVMTy; (void)type; // Unused.
-  }
+  virtual void HandleFCAArgument(const llvm::Type * /*LLVMTy*/, tree /*type*/){}
 
   /// EnterField - Called when we're about the enter the field of a struct
   /// or union.  FieldNo is the number of the element we are entering in the

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=117258&r1=117257&r2=117258&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Oct 25 06:50:17 2010
@@ -402,8 +402,7 @@
       ++AI;
     }
 
-    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)type; // Unused.
+    void HandleFCAArgument(const llvm::Type *LLVMTy, tree /*type*/) {
       // Store the FCA argument into alloca.
       assert(!LocStack.empty());
       Value *Loc = LocStack.back();
@@ -2940,8 +2939,7 @@
 
     /// HandleFCAArgument - This callback is invoked if the aggregate function
     /// argument is passed as a first class aggregate.
-    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)type; // Unused.
+    void HandleFCAArgument(const llvm::Type *LLVMTy, tree /*type*/) {
       Value *Loc = getAddress();
       assert(LLVMTy->getPointerTo() == Loc->getType());
       CallOperands.push_back(Builder.CreateLoad(Loc));
@@ -6413,8 +6411,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinBZero(tree exp, Value *&Result) {
-  (void)Result; // Unused.
+bool TreeToLLVM::EmitBuiltinBZero(tree exp, Value *&/*Result*/) {
   tree arglist = TREE_OPERAND(exp, 1);
   if (!validate_arglist(arglist, POINTER_TYPE, INTEGER_TYPE, VOID_TYPE))
     return false;
@@ -6656,8 +6653,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(tree exp, Value *&Result) {
-  (void)Result; // Unused.
+bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(tree exp, Value *&/*Result*/) {
 #ifdef DWARF2_UNWIND_INFO
   unsigned int i;
   bool wrote_return_column = false;



From bigcheesegs at gmail.com  Mon Oct 25 07:41:36 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Mon, 25 Oct 2010 08:41:36 -0400
Subject: [llvm-commits] [PATCH] Start of support for
	__attribute__((ms_hook_prologue))
In-Reply-To: <AANLkTime5N9WwG6+TBNmQggJKqXM+Hd=ji+=8=2wy1pp@mail.gmail.com>
References: <4CC4E0BF.50107@mymail.mines.edu>
	<AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>
	<AANLkTime5N9WwG6+TBNmQggJKqXM+Hd=ji+=8=2wy1pp@mail.gmail.com>
Message-ID: <AANLkTi=+LUdduYzSdaRCVQ2yzP5HmwejGjtKaEQBvMii@mail.gmail.com>

On Mon, Oct 25, 2010 at 7:08 AM, Anton Korobeynikov
<anton at korobeynikov.info> wrote:
> Michael,
>
>> I'm not convinced that a new attribute is needed. We already have
>> dllexport linkage, so why not just add an option that makes all
>> dllexport functions hot patchable? It doesn't change the calling
>> convention at all.
> I don't see why this should be connected to dllexport stuff at all.
> One definitely might want to make a non-dllexported function
> hot-patchable.
>
> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>

One may want to, but Windows only supports hotpatching dllexported functions.

- Michael Spencer

From baldrick at free.fr  Mon Oct 25 07:43:15 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 12:43:15 -0000
Subject: [llvm-commits] [dragonegg] r117259 - in /dragonegg/trunk:
 llvm-abi-default.cpp llvm-abi.h llvm-backend.cpp llvm-convert.cpp
 llvm-types.cpp x86/llvm-target.cpp
Message-ID: <20101025124315.DA78D2A6C12C@llvm.org>

Author: baldrick
Date: Mon Oct 25 07:43:15 2010
New Revision: 117259

URL: http://llvm.org/viewvc/llvm-project?rev=117259&view=rev
Log:
Avoid compiler warnings about unused parameters by not naming the
parameter rather than using the cast-to-void idiom.

Modified:
    dragonegg/trunk/llvm-abi-default.cpp
    dragonegg/trunk/llvm-abi.h
    dragonegg/trunk/llvm-backend.cpp
    dragonegg/trunk/llvm-convert.cpp
    dragonegg/trunk/llvm-types.cpp
    dragonegg/trunk/x86/llvm-target.cpp

Modified: dragonegg/trunk/llvm-abi-default.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-abi-default.cpp?rev=117259&r1=117258&r2=117259&view=diff
==============================================================================
--- dragonegg/trunk/llvm-abi-default.cpp (original)
+++ dragonegg/trunk/llvm-abi-default.cpp Mon Oct 25 07:43:15 2010
@@ -17,8 +17,7 @@
 
 // doNotUseShadowReturn - Return true if the specified GCC type
 // should not be returned using a pointer to struct parameter.
-bool doNotUseShadowReturn(tree type, tree fndecl, CallingConv::ID CC) {
-  (void)CC; // Otherwise unused - avoid compiler warning.
+bool doNotUseShadowReturn(tree type, tree fndecl, CallingConv::ID /*CC*/) {
   if (!TYPE_SIZE(type))
     return false;
   if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST)

Modified: dragonegg/trunk/llvm-abi.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-abi.h?rev=117259&r1=117258&r2=117259&view=diff
==============================================================================
--- dragonegg/trunk/llvm-abi.h (original)
+++ dragonegg/trunk/llvm-abi.h Mon Oct 25 07:43:15 2010
@@ -54,84 +54,65 @@
 
   /// HandleScalarResult - This callback is invoked if the function returns a
   /// simple scalar result value, which is of type RetTy.
-  virtual void HandleScalarResult(const Type *RetTy) {
-    (void)RetTy; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleScalarResult(const Type * /*RetTy*/) {}
 
   /// HandleAggregateResultAsScalar - This callback is invoked if the function
   /// returns an aggregate value by bit converting it to the specified scalar
   /// type and returning that.  The bit conversion should start at byte Offset
   /// within the struct, and ScalarTy is not necessarily big enough to cover
   /// the entire struct.
-  virtual void HandleAggregateResultAsScalar(const Type *ScalarTy,
-                                             unsigned Offset = 0) {
-    (void)ScalarTy; (void)Offset; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleAggregateResultAsScalar(const Type * /*ScalarTy*/,
+                                             unsigned /*Offset*/ = 0) {}
 
   /// HandleAggregateResultAsAggregate - This callback is invoked if the function
   /// returns an aggregate value using multiple return values.
-  virtual void HandleAggregateResultAsAggregate(const Type *AggrTy) {
-    (void)AggrTy; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleAggregateResultAsAggregate(const Type * /*AggrTy*/) {}
 
   /// HandleAggregateShadowResult - This callback is invoked if the function
   /// returns an aggregate value by using a "shadow" first parameter, which is
   /// a pointer to the aggregate, of type PtrArgTy.  If RetPtr is set to true,
   /// the pointer argument itself is returned from the function.
-  virtual void HandleAggregateShadowResult(const PointerType *PtrArgTy,
-                                           bool RetPtr) {
-    (void)PtrArgTy; (void)RetPtr; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleAggregateShadowResult(const PointerType * /*PtrArgTy*/,
+                                           bool /*RetPtr*/) {}
 
   /// HandleScalarShadowResult - This callback is invoked if the function
   /// returns a scalar value by using a "shadow" first parameter, which is a
   /// pointer to the scalar, of type PtrArgTy.  If RetPtr is set to true,
   /// the pointer argument itself is returned from the function.
-  virtual void HandleScalarShadowResult(const PointerType *PtrArgTy,
-                                        bool RetPtr) {
-    (void)PtrArgTy; (void)RetPtr; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleScalarShadowResult(const PointerType * /*PtrArgTy*/,
+                                        bool /*RetPtr*/) {}
 
 
   /// HandleScalarArgument - This is the primary callback that specifies an
   /// LLVM argument to pass.  It is only used for first class types.
   /// If RealSize is non Zero then it specifies number of bytes to access
   /// from LLVMTy.
-  virtual void HandleScalarArgument(const llvm::Type *LLVMTy, tree_node *type,
-                                    unsigned RealSize = 0) {
-    (void)LLVMTy; (void)type;
-    (void)RealSize; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleScalarArgument(const llvm::Type * /*LLVMTy*/,
+                                    tree_node * /*type*/,
+                                    unsigned /*RealSize*/ = 0) {}
 
   /// HandleByInvisibleReferenceArgument - This callback is invoked if a pointer
   /// (of type PtrTy) to the argument is passed rather than the argument itself.
-  virtual void HandleByInvisibleReferenceArgument(const llvm::Type *PtrTy,
-                                                  tree_node *type) {
-    (void)PtrTy; (void)type; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleByInvisibleReferenceArgument(const llvm::Type * /*PtrTy*/,
+                                                  tree_node * /*type*/) {}
 
   /// HandleByValArgument - This callback is invoked if the aggregate function
   /// argument is passed by value.
-  virtual void HandleByValArgument(const llvm::Type *LLVMTy, tree_node *type) {
-    (void)LLVMTy; (void)type; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleByValArgument(const llvm::Type * /*LLVMTy*/,
+                                   tree_node * /*type*/) {}
 
   /// HandleFCAArgument - This callback is invoked if the aggregate function
   /// argument is passed by value as a first class aggregate.
-  virtual void HandleFCAArgument(const llvm::Type *LLVMTy, tree_node *type) {
-    (void)LLVMTy; (void)type; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandleFCAArgument(const llvm::Type * /*LLVMTy*/,
+                                 tree_node * /*type*/) {}
 
   /// EnterField - Called when we're about the enter the field of a struct
   /// or union.  FieldNo is the number of the element we are entering in the
   /// LLVM Struct, StructTy is the LLVM type of the struct we are entering.
-  virtual void EnterField(unsigned FieldNo, const llvm::Type *StructTy) {
-    (void)FieldNo; (void)StructTy; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void EnterField(unsigned /*FieldNo*/,
+                          const llvm::Type * /*StructTy*/) {}
   virtual void ExitField() {}
-  virtual void HandlePad(const llvm::Type *LLVMTy) {
-    (void)LLVMTy; // Otherwise unused - avoid compiler warning.
-  }
+  virtual void HandlePad(const llvm::Type * /*LLVMTy*/) {}
 };
 
 // LLVM_SHOULD_NOT_RETURN_COMPLEX_IN_MEMORY - A hook to allow
@@ -197,8 +178,8 @@
 // getLLVMAggregateTypeForStructReturn - Return LLVM type if TY can be
 // returns as multiple values, otherwise return NULL. This is the default
 // target independent implementation.
-static inline const Type* getLLVMAggregateTypeForStructReturn(tree_node *type) {
-  (void)type; // Otherwise unused - avoid compiler warning.
+static inline
+const Type* getLLVMAggregateTypeForStructReturn(tree_node * /*type*/) {
   return NULL;
 }
 
@@ -324,11 +305,9 @@
   llvm_default_extract_multiple_return_value((Src),(Dest),(V),(B))
 #endif
 static inline
-void llvm_default_extract_multiple_return_value(Value *Src, Value *Dest,
-                                                bool isVolatile,
-                                                LLVMBuilder &Builder) {
-  (void)Src; (void)Dest;
-  (void)isVolatile; (void)Builder; // Otherwise unused - avoid compiler warning.
+void llvm_default_extract_multiple_return_value(Value * /*Src*/, Value * /*Dest*/,
+                                                bool /*isVolatile*/,
+                                                LLVMBuilder &/*Builder*/) {
   assert (0 && "LLVM_EXTRACT_MULTIPLE_RETURN_VALUE is not implemented!");
 }
 

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=117259&r1=117258&r2=117259&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Mon Oct 25 07:43:15 2010
@@ -1556,9 +1556,7 @@
 /// before processing the compilation unit.
 /// NOTE: called even when only doing syntax checking, so do not initialize the
 /// module etc here.
-static void llvm_start_unit(void *gcc_data, void *user_data) {
-  (void)gcc_data; (void)user_data; // Otherwise unused - avoid compiler warning.
-
+static void llvm_start_unit(void * /*gcc_data*/, void * /*user_data*/) {
   if (!quiet_flag)
     errs() << "Starting compilation unit\n";
 
@@ -1872,9 +1870,7 @@
 
 /// emit_same_body_alias - Turn a same-body alias into LLVM IR.
 static void emit_same_body_alias(struct cgraph_node *alias,
-                                 struct cgraph_node *target) {
-  (void)target; // Otherwise unused - avoid compiler warning.
-
+                                 struct cgraph_node * /*target*/) {
   if (errorcount || sorrycount)
     return; // Do not process broken code.
 
@@ -1895,7 +1891,7 @@
 /// emit_functions - Turn all functions in the compilation unit into LLVM IR.
 static void emit_functions(cgraph_node_set set
 #if (GCC_MINOR > 5)
-                           , varpool_node_set vset LLVM_ATTRIBUTE_UNUSED
+                           , varpool_node_set /*vset*/
 #endif
                            ) {
   if (errorcount || sorrycount)
@@ -1968,13 +1964,11 @@
 };
 
 /// emit_variables - Output GCC global variables to the LLVM IR.
-static void emit_variables(cgraph_node_set set
+static void emit_variables(cgraph_node_set /*set*/
 #if (GCC_MINOR > 5)
-                           , varpool_node_set vset LLVM_ATTRIBUTE_UNUSED
+                           , varpool_node_set /*vset*/
 #endif
                            ) {
-  (void)set; // Otherwise unused - avoid compiler warning.
-
   if (errorcount || sorrycount)
     return; // Do not process broken code.
 
@@ -2104,16 +2098,13 @@
 
 
 /// llvm_finish - Run shutdown code when GCC exits.
-static void llvm_finish(void *gcc_data, void *user_data) {
-  (void)gcc_data; (void)user_data; // Otherwise unused - avoid compiler warning.
+static void llvm_finish(void * /*gcc_data*/, void * /*user_data*/) {
   FinalizePlugin();
 }
 
 /// llvm_finish_unit - Finish the .s file.  This is called by GCC once the
 /// compilation unit has been completely processed.
-static void llvm_finish_unit(void *gcc_data, void *user_data) {
-  (void)gcc_data; (void)user_data; // Otherwise unused - avoid compiler warning.
-
+static void llvm_finish_unit(void * /*gcc_data*/, void * /*user_data*/) {
   if (errorcount || sorrycount)
     return; // Do not process broken code.
 

Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=117259&r1=117258&r2=117259&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Mon Oct 25 07:43:15 2010
@@ -381,8 +381,7 @@
     /// getCallingConv - This provides the desired CallingConv for the function.
     CallingConv::ID& getCallingConv(void) { return CallingConv; }
 
-    void HandlePad(const llvm::Type *LLVMTy) {
-      (void)LLVMTy; // Otherwise unused - avoid compiler warning.
+    void HandlePad(const llvm::Type * /*LLVMTy*/) {
       ++AI;
     }
 
@@ -401,8 +400,8 @@
       LocStack.clear();
     }
 
-    void HandleAggregateShadowResult(const PointerType *PtrArgTy, bool RetPtr) {
-      (void)PtrArgTy; (void)RetPtr; // Otherwise unused - avoid compiler warning
+    void HandleAggregateShadowResult(const PointerType * /*PtrArgTy*/,
+                                     bool /*RetPtr*/) {
       // If the function returns a structure by value, we transform the function
       // to take a pointer to the result as the first argument of the function
       // instead.
@@ -436,8 +435,8 @@
       ++AI;
     }
 
-    void HandleScalarShadowResult(const PointerType *PtrArgTy, bool RetPtr) {
-      (void)PtrArgTy; (void)RetPtr; // Otherwise unused - avoid compiler warning
+    void HandleScalarShadowResult(const PointerType * /*PtrArgTy*/,
+                                  bool /*RetPtr*/) {
       assert(AI != Builder.GetInsertBlock()->getParent()->arg_end() &&
              "No explicit return value?");
       AI->setName("scalar.result");
@@ -446,9 +445,8 @@
       ++AI;
     }
 
-    void HandleScalarArgument(const llvm::Type *LLVMTy, tree type,
+    void HandleScalarArgument(const llvm::Type *LLVMTy, tree /*type*/,
                               unsigned RealSize = 0) {
-      (void)type; // Otherwise unused - avoid compiler warning.
       Value *ArgVal = AI;
       if (ArgVal->getType() != LLVMTy) {
         if (ArgVal->getType()->isPointerTy() && LLVMTy->isPointerTy()) {
@@ -476,8 +474,7 @@
       ++AI;
     }
 
-    void HandleByValArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)LLVMTy; (void)type; // Otherwise unused - avoid compiler warning.
+    void HandleByValArgument(const llvm::Type * /*LLVMTy*/, tree type) {
       if (LLVM_BYVAL_ALIGNMENT_TOO_SMALL(type)) {
         // Incoming object on stack is insufficiently aligned for the type.
         // Make a correctly aligned copy.
@@ -508,8 +505,7 @@
       ++AI;
     }
 
-    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)LLVMTy; (void)type; // Otherwise unused - avoid compiler warning.
+    void HandleFCAArgument(const llvm::Type * /*LLVMTy*/, tree /*type*/) {
       // Store the FCA argument into alloca.
       assert(!LocStack.empty());
       Value *Loc = LocStack.back();
@@ -518,9 +514,8 @@
       ++AI;
     }
 
-    void HandleAggregateResultAsScalar(const Type *ScalarTy,
+    void HandleAggregateResultAsScalar(const Type * /*ScalarTy*/,
                                        unsigned Offset = 0) {
-      (void)ScalarTy; // Otherwise unused - avoid compiler warning.
       this->Offset = Offset;
     }
 
@@ -545,8 +540,7 @@
 // passed in memory byval.
 static bool isPassedByVal(tree type, const Type *Ty,
                           std::vector<const Type*> &ScalarArgs,
-                          bool isShadowRet, CallingConv::ID &CC) {
-  (void)CC; // Otherwise unused - avoid compiler warning.
+                          bool isShadowRet, CallingConv::ID &/*CC*/) {
   if (LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(type, Ty))
     return true;
 
@@ -2602,8 +2596,7 @@
 
     /// HandleScalarResult - This callback is invoked if the function returns a
     /// simple scalar result value.
-    void HandleScalarResult(const Type *RetTy) {
-      (void)RetTy; // Otherwise unused - avoid compiler warning.
+    void HandleScalarResult(const Type * /*RetTy*/) {
       // There is nothing to do here if we return a scalar or void.
       assert(DestLoc == 0 &&
              "Call returns a scalar but caller expects aggregate!");
@@ -2612,16 +2605,14 @@
     /// HandleAggregateResultAsScalar - This callback is invoked if the function
     /// returns an aggregate value by bit converting it to the specified scalar
     /// type and returning that.
-    void HandleAggregateResultAsScalar(const Type *ScalarTy,
+    void HandleAggregateResultAsScalar(const Type * /*ScalarTy*/,
                                        unsigned Offset = 0) {
-      (void)ScalarTy; // Otherwise unused - avoid compiler warning.
       this->Offset = Offset;
     }
 
     /// HandleAggregateResultAsAggregate - This callback is invoked if the
     /// function returns an aggregate value using multiple return values.
-    void HandleAggregateResultAsAggregate(const Type *AggrTy) {
-      (void)AggrTy; // Otherwise unused - avoid compiler warning.
+    void HandleAggregateResultAsAggregate(const Type * /*AggrTy*/) {
       // There is nothing to do here.
       isAggrRet = true;
     }
@@ -2630,8 +2621,7 @@
     /// returns an aggregate value by using a "shadow" first parameter.  If
     /// RetPtr is set to true, the pointer argument itself is returned from the
     /// function.
-    void HandleAggregateShadowResult(const PointerType *PtrArgTy, bool RetPtr) {
-      (void)RetPtr; // Otherwise unused - avoid compiler warning.
+    void HandleAggregateShadowResult(const PointerType *PtrArgTy, bool /*RetPtr*/) {
       // We need to pass memory to write the return value into.
       // FIXME: alignment and volatility are being ignored!
       assert(!DestLoc || PtrArgTy == DestLoc->Ptr->getType());
@@ -2664,8 +2654,8 @@
     /// returns a scalar value by using a "shadow" first parameter, which is a
     /// pointer to the scalar, of type PtrArgTy.  If RetPtr is set to true,
     /// the pointer argument itself is returned from the function.
-    void HandleScalarShadowResult(const PointerType *PtrArgTy, bool RetPtr) {
-      (void)RetPtr; // Otherwise unused - avoid compiler warning.
+    void HandleScalarShadowResult(const PointerType *PtrArgTy,
+                                  bool /*RetPtr*/) {
       assert(DestLoc == 0 &&
              "Call returns a scalar but caller expects aggregate!");
       // Create a buffer to hold the result.  The result will be loaded out of
@@ -2705,8 +2695,7 @@
     /// pointer (of type PtrTy) to the argument is passed rather than the
     /// argument itself.
     void HandleByInvisibleReferenceArgument(const llvm::Type *PtrTy,
-                                            tree type) {
-      (void)type; // Otherwise unused - avoid compiler warning.
+                                            tree /*type*/) {
       Value *Loc = getAddress();
       Loc = Builder.CreateBitCast(Loc, PtrTy);
       CallOperands.push_back(Loc);
@@ -2715,8 +2704,7 @@
     /// HandleByValArgument - This callback is invoked if the aggregate function
     /// argument is passed by value. It is lowered to a parameter passed by
     /// reference with an additional parameter attribute "ByVal".
-    void HandleByValArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)type; // Otherwise unused - avoid compiler warning.
+    void HandleByValArgument(const llvm::Type *LLVMTy, tree /*type*/) {
       Value *Loc = getAddress();
       assert(LLVMTy->getPointerTo() == Loc->getType());
       (void)LLVMTy; // Otherwise unused if asserts off - avoid compiler warning.
@@ -2725,8 +2713,7 @@
 
     /// HandleFCAArgument - This callback is invoked if the aggregate function
     /// argument is passed as a first class aggregate.
-    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)type; // Otherwise unused - avoid compiler warning.
+    void HandleFCAArgument(const llvm::Type *LLVMTy, tree /*type*/) {
       Value *Loc = getAddress();
       assert(LLVMTy->getPointerTo() == Loc->getType());
       (void)LLVMTy; // Otherwise unused if asserts off - avoid compiler warning.
@@ -4646,8 +4633,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinBZero(gimple stmt, Value *&Result) {
-  (void)Result; // Otherwise unused - avoid compiler warning.
+bool TreeToLLVM::EmitBuiltinBZero(gimple stmt, Value *&/*Result*/) {
   if (!validate_gimple_arglist(stmt, POINTER_TYPE, INTEGER_TYPE, VOID_TYPE))
     return false;
 
@@ -4871,8 +4857,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinEHReturn(gimple stmt, Value *&Result) {
-  (void)Result; // Otherwise unused - avoid compiler warning.
+bool TreeToLLVM::EmitBuiltinEHReturn(gimple stmt, Value *&/*Result*/) {
   if (!validate_gimple_arglist(stmt, INTEGER_TYPE, POINTER_TYPE, VOID_TYPE))
     return false;
 
@@ -4894,8 +4879,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(gimple stmt, Value *&Result) {
-  (void)Result; // Otherwise unused - avoid compiler warning.
+bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(gimple stmt, Value *&/*Result*/) {
 #ifdef DWARF2_UNWIND_INFO
   unsigned int i;
   bool wrote_return_column = false;
@@ -4961,8 +4945,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinUnwindInit(gimple stmt, Value *&Result) {
-  (void)Result; // Otherwise unused - avoid compiler warning.
+bool TreeToLLVM::EmitBuiltinUnwindInit(gimple stmt, Value *&/*Result*/) {
   if (!validate_gimple_arglist(stmt, VOID_TYPE))
     return false;
 
@@ -5083,8 +5066,7 @@
   return true;
 }
 
-bool TreeToLLVM::EmitBuiltinInitTrampoline(gimple stmt, Value *&Result) {
-  (void)Result; // Otherwise unused - avoid compiler warning.
+bool TreeToLLVM::EmitBuiltinInitTrampoline(gimple stmt, Value *&/*Result*/) {
   if (!validate_gimple_arglist(stmt, POINTER_TYPE, POINTER_TYPE, POINTER_TYPE,
                          VOID_TYPE))
     return false;

Modified: dragonegg/trunk/llvm-types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-types.cpp?rev=117259&r1=117258&r2=117259&view=diff
==============================================================================
--- dragonegg/trunk/llvm-types.cpp (original)
+++ dragonegg/trunk/llvm-types.cpp Mon Oct 25 07:43:15 2010
@@ -1027,8 +1027,7 @@
     }
 
     void HandleScalarArgument(const llvm::Type *LLVMTy, tree type,
-                              unsigned RealSize = 0) {
-      (void)RealSize; // Otherwise unused - avoid compiler warning.
+                              unsigned /*RealSize*/ = 0) {
       if (KNRPromotion) {
         if (type == float_type_node)
           LLVMTy = ConvertType(double_type_node);
@@ -1041,8 +1040,8 @@
 
     /// HandleByInvisibleReferenceArgument - This callback is invoked if a pointer
     /// (of type PtrTy) to the argument is passed rather than the argument itself.
-    void HandleByInvisibleReferenceArgument(const llvm::Type *PtrTy, tree type) {
-      (void)type; // Otherwise unused - avoid compiler warning.
+    void HandleByInvisibleReferenceArgument(const llvm::Type *PtrTy,
+                                            tree /*type*/) {
       ArgTypes.push_back(PtrTy);
     }
 
@@ -1055,8 +1054,7 @@
 
     /// HandleFCAArgument - This callback is invoked if the aggregate function
     /// argument is a first class aggregate passed by value.
-    void HandleFCAArgument(const llvm::Type *LLVMTy, tree type) {
-      (void)type; // Otherwise unused - avoid compiler warning.
+    void HandleFCAArgument(const llvm::Type *LLVMTy, tree /*type*/) {
       ArgTypes.push_back(LLVMTy);
     }
   };
@@ -1462,9 +1460,8 @@
   /// includes the specified byte, remove it. Return true struct
   /// layout is sized properly. Return false if unable to handle ByteOffset.
   /// In this case caller should redo this struct as a packed structure.
-  bool ResizeLastElementIfOverlapsWith(uint64_t ByteOffset, tree Field,
+  bool ResizeLastElementIfOverlapsWith(uint64_t ByteOffset, tree /*Field*/,
                                        const Type *Ty) {
-    (void)Field; // Otherwise unused - avoid compiler warning.
     const Type *SavedTy = NULL;
 
     if (!Elements.empty()) {

Modified: dragonegg/trunk/x86/llvm-target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/x86/llvm-target.cpp?rev=117259&r1=117258&r2=117259&view=diff
==============================================================================
--- dragonegg/trunk/x86/llvm-target.cpp (original)
+++ dragonegg/trunk/x86/llvm-target.cpp Mon Oct 25 07:43:15 2010
@@ -88,11 +88,10 @@
  */
 bool TreeToLLVM::TargetIntrinsicLower(gimple stmt,
                                       tree fndecl,
-                                      const MemRef *DestLoc,
+                                      const MemRef * /*DestLoc*/,
                                       Value *&Result,
                                       const Type *ResultType,
                                       std::vector<Value*> &Ops) {
-  (void)DestLoc; // Otherwise unused - avoid compiler warning.
   // DECL_FUNCTION_CODE contains a value of the enumerated type ix86_builtins,
   // declared in i386.c.  If this type was visible to us then we could simply
   // use a switch statement on DECL_FUNCTION_CODE to jump to the right code for
@@ -1326,9 +1325,8 @@
 /// The original implementation of this routine is based on
 /// llvm_x86_64_should_pass_aggregate_in_mixed_regs code.
 void
-llvm_x86_64_get_multiple_return_reg_classes(tree TreeType, const Type *Ty,
+llvm_x86_64_get_multiple_return_reg_classes(tree TreeType, const Type * /*Ty*/,
                                             std::vector<const Type*> &Elts) {
-  (void)Ty; // Otherwise unused - avoid compiler warning.
   enum x86_64_reg_class Class[MAX_CLASSES];
   enum machine_mode Mode = type_natural_mode(TreeType, NULL);
   HOST_WIDE_INT Bytes =



From baldrick at free.fr  Mon Oct 25 07:47:22 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 12:47:22 -0000
Subject: [llvm-commits] [llvm] r117260 -
	/llvm/trunk/include/llvm/Support/Compiler.h
Message-ID: <20101025124722.B5C662A6C12C@llvm.org>

Author: baldrick
Date: Mon Oct 25 07:47:22 2010
New Revision: 117260

URL: http://llvm.org/viewvc/llvm-project?rev=117260&view=rev
Log:
Remove deprecated macro names.  Hopefully this will unbreak the
smooshlab build.  The breakage seems to be due to a collision
between LLVM's ATTRIBUTE_UNUSED and gcc's which was previously
hidden due to header files being included in a lucky order.

Modified:
    llvm/trunk/include/llvm/Support/Compiler.h

Modified: llvm/trunk/include/llvm/Support/Compiler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=117260&r1=117259&r2=117260&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Compiler.h (original)
+++ llvm/trunk/include/llvm/Support/Compiler.h Mon Oct 25 07:47:22 2010
@@ -107,15 +107,4 @@
 #define LLVM_ATTRIBUTE_NORETURN
 #endif
 
-// We provide definitions without the LLVM_ prefix briefly while transitioning
-// to always-prefixed names. These will go away as soon as the migration is
-// complete.
-#define ATTRIBUTE_USED LLVM_ATTRIBUTE_USED
-#define ATTRIBUTE_UNUSED LLVM_ATTRIBUTE_UNUSED
-#define ATTRIBUTE_READNONE LLVM_ATTRIBUTE_READNONE
-#define ATTRIBUTE_READONLY LLVM_ATTRIBUTE_READONLY
-#define NORETURN LLVM_ATTRIBUTE_NORETURN
-#define DISABLE_INLINE LLVM_ATTRIBUTE_NOINLINE
-#define ALWAYS_INLINE LLVM_ATTRIBUTE_ALWAYS_INLINE
-
 #endif



From baldrick at free.fr  Mon Oct 25 08:04:43 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 13:04:43 -0000
Subject: [llvm-commits] [dragonegg] r117261 - /dragonegg/trunk/Makefile
Message-ID: <20101025130443.198F12A6C12C@llvm.org>

Author: baldrick
Date: Mon Oct 25 08:04:42 2010
New Revision: 117261

URL: http://llvm.org/viewvc/llvm-project?rev=117261&view=rev
Log:
There are now no warnings with -Wextra even when doing a release
build.

Modified:
    dragonegg/trunk/Makefile

Modified: dragonegg/trunk/Makefile
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/Makefile?rev=117261&r1=117260&r2=117261&view=diff
==============================================================================
--- dragonegg/trunk/Makefile (original)
+++ dragonegg/trunk/Makefile Mon Oct 25 08:04:42 2010
@@ -17,7 +17,7 @@
 	QUIET:=@
 endif
 
-COMMON_FLAGS=-Wall -fvisibility=hidden
+COMMON_FLAGS=-Wall -Wextra -fvisibility=hidden
 CFLAGS+=$(COMMON_FLAGS) $(shell $(LLVM_CONFIG) --cflags)
 CXXFLAGS+=$(COMMON_FLAGS) $(shell $(LLVM_CONFIG) --cxxflags)
 



From baldrick at free.fr  Mon Oct 25 08:10:04 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 13:10:04 -0000
Subject: [llvm-commits] [llvm] r117262 -
	/llvm/trunk/lib/System/Win32/ThreadLocal.inc
Message-ID: <20101025131004.270E82A6C12C@llvm.org>

Author: baldrick
Date: Mon Oct 25 08:10:03 2010
New Revision: 117262

URL: http://llvm.org/viewvc/llvm-project?rev=117262&view=rev
Log:
ATTRIBUTE_UNUSED has been renamed to LLVM_ATTRIBUTE_UNUSED.
Rather than rename this instance, use the cast-to-void idiom
instead.  This will hopefully fix the windows buildbots.

Modified:
    llvm/trunk/lib/System/Win32/ThreadLocal.inc

Modified: llvm/trunk/lib/System/Win32/ThreadLocal.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/ThreadLocal.inc?rev=117262&r1=117261&r2=117262&view=diff
==============================================================================
--- llvm/trunk/lib/System/Win32/ThreadLocal.inc (original)
+++ llvm/trunk/lib/System/Win32/ThreadLocal.inc Mon Oct 25 08:10:03 2010
@@ -17,7 +17,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "Win32.h"
-#include "llvm/Support/Compiler.h"
 #include "llvm/System/ThreadLocal.h"
 
 namespace llvm {
@@ -43,8 +42,9 @@
 
 void ThreadLocalImpl::setInstance(const void* d){
   DWORD* tls = static_cast<DWORD*>(data);
-  int ATTRIBUTE_UNUSED errorcode = TlsSetValue(*tls, const_cast<void*>(d));
+  int errorcode = TlsSetValue(*tls, const_cast<void*>(d));
   assert(errorcode != 0);
+  (void)errorcode;
 }
 
 void ThreadLocalImpl::removeInstance() {



From kennethuil at gmail.com  Mon Oct 25 08:14:16 2010
From: kennethuil at gmail.com (Kenneth Uildriks)
Date: Mon, 25 Oct 2010 08:14:16 -0500
Subject: [llvm-commits] [PATCH] Promote all possible memory to registers
In-Reply-To: <4B724AA3-FE6B-478A-9575-DDD4522E5BFD@apple.com>
References: <AANLkTi=5e3_Fs9ehrVGOYpBnd=-HifuSCufADMPa8YYD@mail.gmail.com>
	<AANLkTikXCisSf6aEjXvxmvx9fuZ9rT6-XWj8-GWBt9tk@mail.gmail.com>
	<AANLkTim5g3uLBxzVcszi2SJPwGcKWwj5eJB+sPnwkBHz@mail.gmail.com>
	<590A0EB1-A1DF-46E7-B6D1-AE55C044D0CD@apple.com>
	<4CC42974.4000402@free.fr>
	<4B724AA3-FE6B-478A-9575-DDD4522E5BFD@apple.com>
Message-ID: <AANLkTinu+isYcanLCmAna4WwpoJAG_3FQ7CwGTVujmpP@mail.gmail.com>

On Sun, Oct 24, 2010 at 9:51 AM, Chris Lattner <clattner at apple.com> wrote:
>?Splitting scalar and memory GVN apart from each other isn't practical: each unblocks important cse's in the other.
>
> -Chris
>

I'm thinking that if multiple conceptually different optimizations are
living in one pass so that they can be repeated until neither helps
the other, PassManager really ought to handle that sort of thing
instead somehow.  Maybe have a pass request to be repeated after some
other pass (if it is turned on) changes the code.  Then each can point
to another that way and be alternated until they stop finding
improvements.  We'd have to make sure that they actually stop at some
point, but the same is true for the present GVN's loop inside of
runOnFunction.


From grosser at fim.uni-passau.de  Mon Oct 25 10:36:50 2010
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Mon, 25 Oct 2010 15:36:50 -0000
Subject: [llvm-commits] [llvm] r117263 -
	/llvm/trunk/include/llvm/LinkAllPasses.h
Message-ID: <20101025153650.F3CD02A6C12C@llvm.org>

Author: grosser
Date: Mon Oct 25 10:36:50 2010
New Revision: 117263

URL: http://llvm.org/viewvc/llvm-project?rev=117263&view=rev
Log:
Reference RegionPass to stop it being eliminated.

Contributed by: ether

Modified:
    llvm/trunk/include/llvm/LinkAllPasses.h

Modified: llvm/trunk/include/llvm/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=117263&r1=117262&r2=117263&view=diff
==============================================================================
--- llvm/trunk/include/llvm/LinkAllPasses.h (original)
+++ llvm/trunk/include/llvm/LinkAllPasses.h Mon Oct 25 10:36:50 2010
@@ -21,6 +21,7 @@
 #include "llvm/Analysis/IntervalPartition.h"
 #include "llvm/Analysis/Passes.h"
 #include "llvm/Analysis/PostDominators.h"
+#include "llvm/Analysis/RegionPass.h"
 #include "llvm/Analysis/RegionPrinter.h"
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/Lint.h"
@@ -151,6 +152,8 @@
       (void)new llvm::FindUsedTypes();
       (void)new llvm::ScalarEvolution();
       ((llvm::Function*)0)->viewCFGOnly();
+      llvm::RGPassManager RGM(0);
+      ((llvm::RegionPass*)0)->runOnRegion((llvm::Region*)0, RGM);
       llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0);
       X.add((llvm::Value*)0, 0, 0);  // for -print-alias-sets
     }



From cdavis at mines.edu  Mon Oct 25 10:37:09 2010
From: cdavis at mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 15:37:09 -0000
Subject: [llvm-commits] [llvm] r117264 - in /llvm/trunk: docs/LangRef.html
 include/llvm/Attributes.h lib/AsmParser/LLLexer.cpp
 lib/AsmParser/LLParser.cpp lib/AsmParser/LLToken.h
 lib/VMCore/Attributes.cpp
Message-ID: <20101025153710.2AAF52A6C12C@llvm.org>

Author: cdavis
Date: Mon Oct 25 10:37:09 2010
New Revision: 117264

URL: http://llvm.org/viewvc/llvm-project?rev=117264&view=rev
Log:
Add a new 'hotpatch' attribute. This attribute will insert a two-byte no-op
instruction at the beginning of each function that has the attribute, allowing
the function to be easily hooked and/or patched.

Modified:
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm/Attributes.h
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/VMCore/Attributes.cpp

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=117264&r1=117263&r2=117264&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Oct 25 10:37:09 2010
@@ -1131,6 +1131,11 @@
       function into callers whenever possible, ignoring any active inlining size
       threshold for this caller.</dd>
 
+  <dt><tt><b>hotpatch</b></tt></dt>
+  <dd>This attribute indicates that the prologue should contain a 'hotpatch'
+      sequence at the beginning. This is the same sequence used in the
+      system DLLs in Microsoft Windows XP Service Pack 2 and higher.</dd>
+
   <dt><tt><b>inlinehint</b></tt></dt>
   <dd>This attribute indicates that the source code contained a hint that inlining
       this function is desirable (such as the "inline" keyword in C/C++).  It

Modified: llvm/trunk/include/llvm/Attributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=117264&r1=117263&r2=117264&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Attributes.h (original)
+++ llvm/trunk/include/llvm/Attributes.h Mon Oct 25 10:37:09 2010
@@ -65,6 +65,8 @@
                                           ///of alignment with +1 bias
                                           ///0 means unaligned (different from
                                           ///alignstack(1))
+const Attributes Hotpatch    = 1<<29;     ///< Function should have special
+                                          ///'hotpatch' sequence in prologue
 
 /// @brief Attributes that only apply to function parameters.
 const Attributes ParameterOnly = ByVal | Nest | StructRet | NoCapture;
@@ -73,7 +75,8 @@
 /// be used on return values or function parameters.
 const Attributes FunctionOnly = NoReturn | NoUnwind | ReadNone | ReadOnly |
   NoInline | AlwaysInline | OptimizeForSize | StackProtect | StackProtectReq |
-  NoRedZone | NoImplicitFloat | Naked | InlineHint | StackAlignment;
+  NoRedZone | NoImplicitFloat | Naked | InlineHint | StackAlignment |
+  Hotpatch;
 
 /// @brief Parameter attributes that do not apply to vararg call arguments.
 const Attributes VarArgsIncompatible = StructRet;

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=117264&r1=117263&r2=117264&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Oct 25 10:37:09 2010
@@ -573,6 +573,7 @@
   KEYWORD(noredzone);
   KEYWORD(noimplicitfloat);
   KEYWORD(naked);
+  KEYWORD(hotpatch);
 
   KEYWORD(type);
   KEYWORD(opaque);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=117264&r1=117263&r2=117264&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Oct 25 10:37:09 2010
@@ -982,6 +982,7 @@
     case lltok::kw_noredzone:       Attrs |= Attribute::NoRedZone; break;
     case lltok::kw_noimplicitfloat: Attrs |= Attribute::NoImplicitFloat; break;
     case lltok::kw_naked:           Attrs |= Attribute::Naked; break;
+    case lltok::kw_hotpatch:        Attrs |= Attribute::Hotpatch; break;
 
     case lltok::kw_alignstack: {
       unsigned Alignment;

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=117264&r1=117263&r2=117264&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Mon Oct 25 10:37:09 2010
@@ -96,6 +96,7 @@
     kw_noredzone,
     kw_noimplicitfloat,
     kw_naked,
+    kw_hotpatch,
 
     kw_type,
     kw_opaque,

Modified: llvm/trunk/lib/VMCore/Attributes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=117264&r1=117263&r2=117264&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Attributes.cpp (original)
+++ llvm/trunk/lib/VMCore/Attributes.cpp Mon Oct 25 10:37:09 2010
@@ -70,6 +70,8 @@
     Result += "noimplicitfloat ";
   if (Attrs & Attribute::Naked)
     Result += "naked ";
+  if (Attrs & Attribute::Hotpatch)
+    Result += "hotpatch ";
   if (Attrs & Attribute::StackAlignment) {
     Result += "alignstack(";
     Result += utostr(Attribute::getStackAlignmentFromAttrs(Attrs));



From cdavis at mymail.mines.edu  Mon Oct 25 10:39:24 2010
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 09:39:24 -0600
Subject: [llvm-commits] [PATCH] Start of support for
	__attribute__((ms_hook_prologue))
In-Reply-To: <AANLkTi=kQKyZ1uV2Mx=t6ssj6vsrjhSCUUviTDcMLrV+@mail.gmail.com>
References: <4CC4E0BF.50107@mymail.mines.edu>	<AANLkTikmVAR8eUrv1DUArdF+aOWfhs4_q=e+PNmndx=L@mail.gmail.com>	<4CC55EF8.4020100@mymail.mines.edu>
	<AANLkTi=kQKyZ1uV2Mx=t6ssj6vsrjhSCUUviTDcMLrV+@mail.gmail.com>
Message-ID: <4CC5A4AC.9020804@mymail.mines.edu>

Committed in r117264.

Chip

On 10/25/10 5:03 AM, Michael Spencer wrote:
> On Mon, Oct 25, 2010 at 6:42 AM, Charles Davis <cdavis at mymail.mines.edu> wrote:
>> On 10/25/10 12:16 AM, Michael Spencer wrote:
>>> On Sun, Oct 24, 2010 at 9:43 PM, Charles Davis <cdavis at mymail.mines.edu> wrote:
>>>> Hi,
>>>>
>>>> I thought that, while I wait for a response to my latest clang "patch"
>>>> on cfe-dev, I'd work on something else Wine-related.
>>>>
>>>> Microsoft's compiler has a switch, '/hotpatch', that inserts a magic
>>>> sequence in the beginning of every compiled function. This sequence lets
>>>> other DLLs hook these functions (assuming they were exported from a DLL)
>>>> to do interesting things when they're called. In response, GCC added an
>>>> attribute, 'ms_hook_prologue', that does the same in GCC (partially at
>>>> the behest of the Wine developers). And now I intend to do the same for
>>>> Clang.
>>>>
>>>> Of course, this needs backend support. So, as with my
>>>> 'force_align_arg_pointer' patches, I'm starting with the basics. This
>>>> patch adds support for the attribute in LLVM IR. OK to commit?
>>>>
>>>> Chip
>>>
>>> I'm not convinced that a new attribute is needed.
>> All right then, let me convince you.
>>> We already have
>>> dllexport linkage, so why not just add an option that makes all
>>> dllexport functions hot patchable? It doesn't change the calling
>>> convention at all.
>> Several reasons:
>> - This adds some noop instruction(s) to the beginning of the function.
>> (On x86, it adds a 'mov %edi,%edi'.) This could potentially affect
>> performance if the function is called over and over again. Are you sure
>> you want all dllexport functions to be hotpatchable?
> 
> It actually only requires that the first instruction be two bytes.
> 
>> - Not everyone uses dllexport. Some people still use .def files. Wine is
>> one notable example (though the .def files are autogenerated). They
>> declare some of their functions with this attribute.
> 
> OK.
> 
>> - GCC already has this attribute. It's too late.
> 
> We don't have to implement all gcc features.
> 
>>>
>>> Also, this doesn't seem to include the lexing or parsing code for the keyword.
>> It was only missing the lexing code. Patch reattached.
>>>
>>> - Michael Spencer
> 
> Individually choosing functions to apply this to independent of
> dllexport is a good enough reason for me. I have no objections.


From baldrick at free.fr  Mon Oct 25 10:54:33 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 25 Oct 2010 17:54:33 +0200
Subject: [llvm-commits] [llvm] r117264 - in /llvm/trunk:
 docs/LangRef.html include/llvm/Attributes.h lib/AsmParser/LLLexer.cpp
 lib/AsmParser/LLParser.cpp lib/AsmParser/LLToken.h
 lib/VMCore/Attributes.cpp
In-Reply-To: <20101025153710.2AAF52A6C12C@llvm.org>
References: <20101025153710.2AAF52A6C12C@llvm.org>
Message-ID: <4CC5A839.90702@free.fr>

Hi Charles,

> +<dt><tt><b>hotpatch</b></tt></dt>
> +<dd>This attribute indicates that the prologue should contain a 'hotpatch'
> +      sequence at the beginning. This is the same sequence used in the
> +      system DLLs in Microsoft Windows XP Service Pack 2 and higher.</dd>

I think this is too target specific, and describes the implementation of the
feature rather than the functionality the feature provides.  I think you should
describe the functionality without saying how it is done, and mention that on
windows it is compatible with the Microsoft thing.

Ciao,

Duncan.

From gohman at apple.com  Mon Oct 25 11:16:27 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 16:16:27 -0000
Subject: [llvm-commits] [llvm] r117265 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
 test/Transforms/InstCombine/bitcast-store.ll
Message-ID: <20101025161627.D62372A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 11:16:27 2010
New Revision: 117265

URL: http://llvm.org/viewvc/llvm-project?rev=117265&view=rev
Log:
Fix a case where instcombine was stripping metadata (and alignment)
from stores when folding in bitcasts.

Added:
    llvm/trunk/test/Transforms/InstCombine/bitcast-store.ll
Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=117265&r1=117264&r2=117265&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Oct 25 11:16:27 2010
@@ -330,7 +330,9 @@
   
   NewCast = IC.Builder->CreateCast(opcode, SIOp0, CastDstTy,
                                    SIOp0->getName()+".c");
-  return new StoreInst(NewCast, CastOp);
+  SI.setOperand(0, NewCast);
+  SI.setOperand(1, CastOp);
+  return &SI;
 }
 
 /// equivalentAddressValues - Test if A and B will obviously have the same

Added: llvm/trunk/test/Transforms/InstCombine/bitcast-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bitcast-store.ll?rev=117265&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/bitcast-store.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/bitcast-store.ll Mon Oct 25 11:16:27 2010
@@ -0,0 +1,21 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; Instcombine should preserve metadata and alignment while
+; folding a bitcast into a store.
+
+; CHECK: store i32 (...)** bitcast (i8** getelementptr inbounds ([5 x i8*]* @G, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 16, !tag !0
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
+%struct.A = type { i32 (...)** }
+
+ at G = external constant [5 x i8*]
+
+define void @foo(%struct.A* %a) nounwind {
+entry:
+  %0 = bitcast %struct.A* %a to i8***
+  store i8** getelementptr inbounds ([5 x i8*]* @G, i64 0, i64 2), i8*** %0, align 16, !tag !0
+  ret void
+}
+
+!0 = metadata !{metadata !"hello"}



From gohman at apple.com  Mon Oct 25 11:28:57 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 16:28:57 -0000
Subject: [llvm-commits] [llvm] r117266 -
	/llvm/trunk/lib/Analysis/AliasAnalysis.cpp
Message-ID: <20101025162857.791912A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 11:28:57 2010
New Revision: 117266

URL: http://llvm.org/viewvc/llvm-project?rev=117266&view=rev
Log:
Reintroduce these asserts, now that BasicAA is a normal AliasAnalysis pass.

Modified:
    llvm/trunk/lib/Analysis/AliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=117266&r1=117265&r2=117266&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Oct 25 11:28:57 2010
@@ -67,8 +67,7 @@
 AliasAnalysis::ModRefResult
 AliasAnalysis::getModRefInfo(ImmutableCallSite CS,
                              const Location &Loc) {
-  // Don't assert AA because BasicAA calls us in order to make use of the
-  // logic here.
+  assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!");
 
   ModRefBehavior MRB = getModRefBehavior(CS);
   if (MRB == DoesNotAccessMemory)
@@ -105,8 +104,7 @@
 
 AliasAnalysis::ModRefResult
 AliasAnalysis::getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2) {
-  // Don't assert AA because BasicAA calls us in order to make use of the
-  // logic here.
+  assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!");
 
   // If CS1 or CS2 are readnone, they don't interact.
   ModRefBehavior CS1B = getModRefBehavior(CS1);
@@ -164,8 +162,7 @@
 
 AliasAnalysis::ModRefBehavior
 AliasAnalysis::getModRefBehavior(ImmutableCallSite CS) {
-  // Don't assert AA because BasicAA calls us in order to make use of the
-  // logic here.
+  assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!");
 
   ModRefBehavior Min = UnknownModRefBehavior;
 



From cdavis at mines.edu  Mon Oct 25 11:29:03 2010
From: cdavis at mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 16:29:03 -0000
Subject: [llvm-commits] [llvm] r117267 - /llvm/trunk/docs/LangRef.html
Message-ID: <20101025162904.0D58D2A6C12D@llvm.org>

Author: cdavis
Date: Mon Oct 25 11:29:03 2010
New Revision: 117267

URL: http://llvm.org/viewvc/llvm-project?rev=117267&view=rev
Log:
Make hotpatch attribute description a little less Wintel-specific.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=117267&r1=117266&r2=117267&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Oct 25 11:29:03 2010
@@ -1132,9 +1132,11 @@
       threshold for this caller.</dd>
 
   <dt><tt><b>hotpatch</b></tt></dt>
-  <dd>This attribute indicates that the prologue should contain a 'hotpatch'
-      sequence at the beginning. This is the same sequence used in the
-      system DLLs in Microsoft Windows XP Service Pack 2 and higher.</dd>
+  <dd>This attribute indicates that the function should be 'hotpatchable',
+      meaning the function can be patched even while it is loaded into memory.
+      On x86, the function prologue will contain a two-byte no-op sequence;
+      this is the same sequence used in the system DLLs in Microsoft Windows
+      XP Service Pack 2 and higher.</dd>
 
   <dt><tt><b>inlinehint</b></tt></dt>
   <dd>This attribute indicates that the source code contained a hint that inlining



From cdavis at mymail.mines.edu  Mon Oct 25 11:31:16 2010
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 10:31:16 -0600
Subject: [llvm-commits] [llvm] r117264 - in /llvm/trunk:
 docs/LangRef.html include/llvm/Attributes.h lib/AsmParser/LLLexer.cpp
 lib/AsmParser/LLParser.cpp lib/AsmParser/LLToken.h
 lib/VMCore/Attributes.cpp
In-Reply-To: <4CC5A839.90702@free.fr>
References: <20101025153710.2AAF52A6C12C@llvm.org> <4CC5A839.90702@free.fr>
Message-ID: <4CC5B0D4.5030902@mymail.mines.edu>

On 10/25/10 9:54 AM, Duncan Sands wrote:
> Hi Charles,
> 
>> +<dt><tt><b>hotpatch</b></tt></dt>
>> +<dd>This attribute indicates that the prologue should contain a 'hotpatch'
>> +      sequence at the beginning. This is the same sequence used in the
>> +      system DLLs in Microsoft Windows XP Service Pack 2 and higher.</dd>
> 
> I think this is too target specific, and describes the implementation of the
> feature rather than the functionality the feature provides.  I think you should
> describe the functionality without saying how it is done, and mention that on
> windows it is compatible with the Microsoft thing.
Done. r117267.

Chip

From gohman at apple.com  Mon Oct 25 11:29:52 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 16:29:52 -0000
Subject: [llvm-commits] [llvm] r117268 -
	/llvm/trunk/lib/Analysis/AliasAnalysis.cpp
Message-ID: <20101025162952.3D9A72A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 11:29:52 2010
New Revision: 117268

URL: http://llvm.org/viewvc/llvm-project?rev=117268&view=rev
Log:
Update comments; BasicAA is no longer necessarily the end of the chain.

Modified:
    llvm/trunk/lib/Analysis/AliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=117268&r1=117267&r2=117268&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Oct 25 11:29:52 2010
@@ -94,7 +94,7 @@
   if ((Mask & Mod) && pointsToConstantMemory(Loc))
     Mask = ModRefResult(Mask & ~Mod);
 
-  // If this is BasicAA, don't forward.
+  // If this is the end of the chain, don't forward.
   if (!AA) return Mask;
 
   // Otherwise, fall back to the next AA in the chain. But we can merge
@@ -152,7 +152,7 @@
       return R;
   }
 
-  // If this is BasicAA, don't forward.
+  // If this is the end of the chain, don't forward.
   if (!AA) return Mask;
 
   // Otherwise, fall back to the next AA in the chain. But we can merge
@@ -171,7 +171,7 @@
   if (const Function *F = CS.getCalledFunction())
     Min = getModRefBehavior(F);
 
-  // If this is BasicAA, don't forward.
+  // If this is the end of the chain, don't forward.
   if (!AA) return Min;
 
   // Otherwise, fall back to the next AA in the chain. But we can merge



From resistor at mac.com  Mon Oct 25 12:12:46 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 17:12:46 -0000
Subject: [llvm-commits] [llvm] r117269 -
	/llvm/trunk/test/MC/ARM/neon-sub-encoding.ll
Message-ID: <20101025171246.AB9652A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 12:12:46 2010
New Revision: 117269

URL: http://llvm.org/viewvc/llvm-project?rev=117269&view=rev
Log:
Add tests for NEON encoding of vsubhn and vrsubhn.

Modified:
    llvm/trunk/test/MC/ARM/neon-sub-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-sub-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-sub-encoding.ll?rev=117269&r1=117268&r2=117269&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-sub-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-sub-encoding.ll Mon Oct 25 12:12:46 2010
@@ -472,3 +472,65 @@
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
 	ret <2 x i64> %tmp3
 }
+
+declare <8 x i8>  @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vsubhn_8xi16
+define <8 x i8> @vsubhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vsubhn.i16	d16, q8, q9     @ encoding: [0xa2,0x06,0xc0,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vsubhn_4xi32
+define <4 x i16> @vsubhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vsubhn.i32	d16, q8, q9     @ encoding: [0xa2,0x06,0xd0,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vsubhn_2xi64
+define <2 x i32> @vsubhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vsubhn.i64	d16, q8, q9     @ encoding: [0xa2,0x06,0xe0,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vrsubhn_8xi16
+define <8 x i8> @vrsubhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vrsubhn.i16	d16, q8, q9     @ encoding: [0xa2,0x06,0xc0,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vrsubhn_4xi32
+define <4 x i16> @vrsubhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vrsubhn.i32	d16, q8, q9     @ encoding: [0xa2,0x06,0xd0,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vrsubhn_2xi64
+define <2 x i32> @vrsubhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vrsubhn.i64	d16, q8, q9     @ encoding: [0xa2,0x06,0xe0,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i32> %tmp3
+}



From resistor at mac.com  Mon Oct 25 12:20:26 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 17:20:26 -0000
Subject: [llvm-commits] [llvm] r117270 -
	/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
Message-ID: <20101025172026.8EF8A2A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 12:20:26 2010
New Revision: 117270

URL: http://llvm.org/viewvc/llvm-project?rev=117270&view=rev
Log:
Add tests for NEON encoding of vceq.

Added:
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll?rev=117270&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll Mon Oct 25 12:20:26 2010
@@ -0,0 +1,81 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+; CHECK: vceq_8xi8
+define <8 x i8> @vceq_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vceq.i8	d16, d16, d17           @ encoding: [0xb1,0x08,0x40,0xf3]
+	%tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vceq_4xi16
+define <4 x i16> @vceq_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vceq.i16	d16, d16, d17   @ encoding: [0xb1,0x08,0x50,0xf3]
+	%tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+; CHECK: vceq_2xi32
+define <2 x i32> @vceq_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vceq.i32	d16, d16, d17   @ encoding: [0xb1,0x08,0x60,0xf3]
+	%tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vceq_2xfloat
+define <2 x i32> @vceq_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vceq.f32	d16, d16, d17   @ encoding: [0xa1,0x0e,0x40,0xf2]
+	%tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vceq_16xi8
+define <16 x i8> @vceq_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vceq.i8	q8, q8, q9              @ encoding: [0xf2,0x08,0x40,0xf3]
+	%tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
+  %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vceq_8xi16
+define <8 x i16> @vceq_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vceq.i16	q8, q8, q9      @ encoding: [0xf2,0x08,0x50,0xf3]
+	%tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vceq_4xi32
+define <4 x i32> @vceq_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vceq.i32	q8, q8, q9      @ encoding: [0xf2,0x08,0x60,0xf3]
+	%tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vceq_4xfloat
+define <4 x i32> @vceq_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vceq.f32	q8, q8, q9      @ encoding: [0xe2,0x0e,0x40,0xf2]
+	%tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}



From stoklund at 2pi.dk  Mon Oct 25 12:27:30 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 25 Oct 2010 17:27:30 -0000
Subject: [llvm-commits] [llvm] r117272 - /llvm/trunk/lib/CodeGen/Spiller.h
Message-ID: <20101025172730.ADA972A6C12C@llvm.org>

Author: stoklund
Date: Mon Oct 25 12:27:30 2010
New Revision: 117272

URL: http://llvm.org/viewvc/llvm-project?rev=117272&view=rev
Log:
In which I learn how to forward declare template classes.

Modified:
    llvm/trunk/lib/CodeGen/Spiller.h

Modified: llvm/trunk/lib/CodeGen/Spiller.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=117272&r1=117271&r2=117272&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.h (original)
+++ llvm/trunk/lib/CodeGen/Spiller.h Mon Oct 25 12:27:30 2010
@@ -10,14 +10,13 @@
 #ifndef LLVM_CODEGEN_SPILLER_H
 #define LLVM_CODEGEN_SPILLER_H
 
-#include "llvm/ADT/SmallVector.h"
-
 namespace llvm {
 
   class LiveInterval;
   class MachineFunction;
   class MachineFunctionPass;
   class SlotIndex;
+  template <typename T> class SmallVectorImpl;
   class VirtRegMap;
 
   /// Spiller interface.



From jasonwkim at google.com  Mon Oct 25 12:30:16 2010
From: jasonwkim at google.com (Jason Kim)
Date: Mon, 25 Oct 2010 10:30:16 -0700
Subject: [llvm-commits] Fwd: [LLVMdev] Fwd: Fwd: Proof of concept patch for
 unifying the .s/ELF emission of .ARM.attributes
In-Reply-To: <AANLkTi=_A15998qNoMLpSBTe8uHn4x99_nzUq+O4Y9bj@mail.gmail.com>
References: <AANLkTikSjtvxSNc0oxKEoG2LdGriz10OXOTAtC4caR_+@mail.gmail.com>
	<AANLkTikaS4qjUi+5q3YWt_GF5EdWKVNwxq7=-LyWRRpv@mail.gmail.com>
	<AANLkTinH7mZtZSQKDYMOE9C8-0baHwm31crmp30roWKy@mail.gmail.com>
	<AANLkTimhWm3dCbO003ipXkaDS3f0o948b9b2NquVSe29@mail.gmail.com>
	<AANLkTi=2B7Pk9HkkxYvQBvm-AfJsYCHW8uYxURq5iEcd@mail.gmail.com>
	<AANLkTi=iVAmVx08ww0EOu9DvJ82oxWD+02Es3btVSqK2@mail.gmail.com>
	<AANLkTin5KdNX6g+ZRYJS0nNy6=bu4o4gwa6v5-XNwkW9@mail.gmail.com>
	<AANLkTikAPuZKYLf4iisi=C4v2onfz5qCXQ-mo2s62UNq@mail.gmail.com>
	<6D9C9A6C-872A-494D-A5F6-2523DD4CA5B6@apple.com>
	<AANLkTi=4=8T0ww0csECny4t0RMSrJV=nUT77h+759-Ab@mail.gmail.com>
	<8FD08C3F-E6E1-448B-A384-7E5CF0763EC1@apple.com>
	<AANLkTikH8sEANQrDGVHg1uOtfCs2UzygkUPpm91E9kZc@mail.gmail.com>
	<AANLkTimoHYSw=viMcpZLirRqd789_xjWmT4+foao_T6f@mail.gmail.com>
	<8E5A9C6C-BA61-41F8-B445-336D9F96D774@apple.com>
	<AANLkTiksC9MbzDhYrzLs9Kt5YRGuHu2nv3Jri=-xRKb9@mail.gmail.com>
	<AANLkTi=73V-VRH_HGiPwcQjBNcFZMiU+jazHMH3YdJ-V@mail.gmail.com>
	<AANLkTikGWx7GH5VZUByposdJWhhvc+qR6X-1Ve_gNmKG@mail.gmail.com>
	<AANLkTik7AYHB1_Crv6Vcf4uMyx4U_x5mJaYK+-S3=ucU@mail.gmail.com>
	<AANLkTi=e_fCXZo_H1=_47tv5BABbpHkf8qJiyrMfRFj_@mail.gmail.com>
	<AANLkTi=MArF+PJK1iwc66wZNobOTjC6pi127Kt=A64bp@mail.gmail.com>
	<AANLkTimHKpEKfy2mr_UKco+Uscg_YBDtCmvXhT4AhAnp@mail.gmail.com>
	<AANLkTimt3NyHcqEh38hn+FnUNL_O5Qv81OYjzE7d0Qf1@mail.gmail.com>
	<AANLkTin8ykW=j=arKX3wC-CX2adx0sTtUmYMJr7qYqJY@mail.gmail.com>
	<AANLkTikXC0jb1VQ--c7iAgX6=DvpTHD_prwSF9F2Tjm4@mail.gmail.com>
	<AANLkTi=SBh85q-m-SvA4nNj9DfdUDXgYmxs6u9Zc4w7s@mail.gmail.com>
	<AANLkTinVf83nF2RUWsmRzT1tL=5MMVJdoGHm8h1D6mG6@mail.gmail.com>
	<AANLkTikHY6Sej-knz3b5+EUjMWVuoPOkWrmFHKHBWtam@mail.gmail.com>
	<AANLkTinFCYO-f67sKptJ0fb6FK=c_zAbX6CMi55W1v+X@mail.gmail.com>
	<AANLkTimxqNQwKoVTEd6J8LrD4mm8_8=ZVeafrHLUsZjb@mail.gmail.com>
	<AANLkTinxWGCVcq1=0rVa-bbMSC2dqKUy5z4m5q_nkQOJ@mail.gmail.com>
	<AANLkTimtZPqq6=0=3E3VKWBqQCjVAP=oij2vUE7=Np_9@mail.gmail.com>
	<AANLkTi=qXYf--J5kgwvm1=7byfM6gRad09d0MEsR3NVi@mail.gmail.com>
	<AANLkTi=FzG7nCvqA0a=GKcXxwMhbU_0=ZWUCerKicvnh@mail.gmail.com>
	<AANLkTikXXEvKcu4KKFMT7eZaWuh-cSd2SpSvu31hJhJk@mail.gmail.com>
	<AANLkTikHnjO-ToOJfFuQvBr3MJaeQjY4Rv7AxLxZq9Kz@mail.gmail.com>
	<AANLkTik3b4iZzDeXh2fcz_vYLYR=sepfWiMsxJZv6k8C@mail.gmail.com>
	<AANLkTi=2yhU-At91xJRHCUfAGmQYnpZuisRpwTF_inTj@mail.gmail.com>
	<AANLkTi=_A15998qNoMLpSBTe8uHn4x99_nzUq+O4Y9bj@mail.gmail.com>
Message-ID: <AANLkTimPhqG=HXSmVSiikfjuQK6=VaqBW+b10o6NGzp8@mail.gmail.com>

Forwarding to commits.


---------- Forwarded message ----------
From: Jason Kim <jasonwkim at google.com>
Date: Mon, Oct 25, 2010 at 10:21 AM
Subject: Re: [LLVMdev] Fwd: [llvm-commits] Fwd: Proof of concept patch
for unifying the .s/ELF emission of .ARM.attributes
To: Rafael Esp?ndola <rafael.espindola at gmail.com>
Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu>, Jim Grosbach
<grosbach at apple.com>, Rafael Espindola <espindola at google.com>


All well and good, Rafael, 3 new classes and 4 new slots.
In any case, I am done arguing this - outside of any additional input
on this might as well as commit your rework. Any objections?

On Sun, Oct 24, 2010 at 7:01 PM, Rafael Esp?ndola
<rafael.espindola at gmail.com> wrote:
> I also noticed that we were trying to optimize the output of 41 bytes
> of data :-)

Err, Yes. 2+ weeks on this. I am without words at the moment.

> The attached patch is similar to the previous one but drops the API
> changes by just accumulating the attributes locally before outputting
> them.

-jason


From resistor at mac.com  Mon Oct 25 12:33:02 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 17:33:02 -0000
Subject: [llvm-commits] [llvm] r117273 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-cmp-encoding.ll
Message-ID: <20101025173302.D10182A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 12:33:02 2010
New Revision: 117273

URL: http://llvm.org/viewvc/llvm-project?rev=117273&view=rev
Log:
Add a warning about our inability to test the encoding of vceq with immediate zero.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117273&r1=117272&r2=117273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 12:33:02 2010
@@ -2809,6 +2809,7 @@
 defm VCGEz    : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
                             "$dst, $src, #0">;
 // For disassembly only.
+// FIXME: This instruction's encoding MAY NOT BE correct.
 defm VCLEz    : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
                             "$dst, $src, #0">;
 

Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll?rev=117273&r1=117272&r2=117273&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll Mon Oct 25 12:33:02 2010
@@ -79,3 +79,7 @@
   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
 	ret <4 x i32> %tmp4
 }
+
+; FIXME: We cannot currently test the vceq with immediate zero, because we do
+; not code generate it at this time.
+



From resistor at mac.com  Mon Oct 25 12:49:32 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 17:49:32 -0000
Subject: [llvm-commits] [llvm] r117274 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-cmp-encoding.ll
Message-ID: <20101025174932.7EFD82A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 12:49:32 2010
New Revision: 117274

URL: http://llvm.org/viewvc/llvm-project?rev=117274&view=rev
Log:
Add tests for NEON encodings of vcge and vacge.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117274&r1=117273&r2=117274&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 12:49:32 2010
@@ -2806,6 +2806,7 @@
 def  VCGEfq   : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
                      NEONvcge, 0>;
 // For disassembly only.
+// FIXME: This instruction's encoding MAY NOT BE correct.
 defm VCGEz    : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
                             "$dst, $src, #0">;
 // For disassembly only.

Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll?rev=117274&r1=117273&r2=117274&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll Mon Oct 25 12:49:32 2010
@@ -1,5 +1,10 @@
 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
 
+; FIXME: We cannot currently test the following instructions, which are 
+; currently marked as for-disassembly only in the .td files:
+;  - VCEQz
+;  - VCGEz, VCLEz
+
 ; CHECK: vceq_8xi8
 define <8 x i8> @vceq_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 	%tmp1 = load <8 x i8>* %A
@@ -80,6 +85,163 @@
 	ret <4 x i32> %tmp4
 }
 
-; FIXME: We cannot currently test the vceq with immediate zero, because we do
-; not code generate it at this time.
+; CHECK: vcges_8xi8
+define <8 x i8> @vcges_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vcge.s8	d16, d16, d17           @ encoding: [0xb1,0x03,0x40,0xf2]
+	%tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vcges_4xi16
+define <4 x i16> @vcges_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
+; CHECK: vcge.s16	d16, d16, d17   @ encoding: [0xb1,0x03,0x50,0xf2]
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+; CHECK: vcges_2xi32
+define <2 x i32> @vcges_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vcge.s32	d16, d16, d17   @ encoding: [0xb1,0x03,0x60,0xf2]
+	%tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vcgeu_8xi8
+define <8 x i8> @vcgeu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vcge.u8	d16, d16, d17           @ encoding: [0xb1,0x03,0x40,0xf3]
+	%tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vcgeu_4xi16
+define <4 x i16> @vcgeu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vcge.u16	d16, d16, d17   @ encoding: [0xb1,0x03,0x50,0xf3]
+	%tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+; CHECK: vcgeu_2xi32
+define <2 x i32> @vcgeu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
+; CHECK: vcge.u32	d16, d16, d17   @ encoding: [0xb1,0x03,0x60,0xf3]
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vcge_2xfloat
+define <2 x i32> @vcge_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vcge.f32	d16, d16, d17   @ encoding: [0xa1,0x0e,0x40,0xf3]
+	%tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vcges_16xi8
+define <16 x i8> @vcges_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vcge.s8	q8, q8, q9              @ encoding: [0xf2,0x03,0x40,0xf2]
+	%tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
+  %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vcges_8xi16
+define <8 x i16> @vcges_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vcge.s16	q8, q8, q9      @ encoding: [0xf2,0x03,0x50,0xf2]
+	%tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vcges_4xi32
+define <4 x i32> @vcges_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vcge.s32	q8, q8, q9      @ encoding: [0xf2,0x03,0x60,0xf2]
+	%tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vcgeu_16xi8
+define <16 x i8> @vcgeu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vcge.u8	q8, q8, q9              @ encoding: [0xf2,0x03,0x40,0xf3]
+	%tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
+  %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vcgeu_8xi16
+define <8 x i16> @vcgeu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vcge.u16	q8, q8, q9      @ encoding: [0xf2,0x03,0x50,0xf3]
+	%tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vcgeu_4xi32
+define <4 x i32> @vcgeu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vcge.u32	q8, q8, q9      @ encoding: [0xf2,0x03,0x60,0xf3]
+	%tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vcge_4xfloat
+define <4 x i32> @vcge_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vcge.f32	q8, q8, q9      @ encoding: [0xe2,0x0e,0x40,0xf3]
+	%tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
 
+declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vacge_2xfloat
+define <2 x i32> @vacge_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; vacge.f32	d16, d16, d17   @ encoding: [0xb1,0x0e,0x40,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vacge_4xfloat
+define <4 x i32> @vacge_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vacge.f32	q8, q8, q9      @ encoding: [0xf2,0x0e,0x40,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x i32> %tmp3
+}



From espindola at google.com  Mon Oct 25 12:51:51 2010
From: espindola at google.com (Rafael Espindola)
Date: Mon, 25 Oct 2010 13:51:51 -0400
Subject: [llvm-commits] [LLVMdev] Fwd: Fwd: Proof of concept patch for
 unifying the .s/ELF emission of .ARM.attributes
In-Reply-To: <AANLkTi=_A15998qNoMLpSBTe8uHn4x99_nzUq+O4Y9bj@mail.gmail.com>
References: <AANLkTikSjtvxSNc0oxKEoG2LdGriz10OXOTAtC4caR_+@mail.gmail.com>
	<AANLkTikaS4qjUi+5q3YWt_GF5EdWKVNwxq7=-LyWRRpv@mail.gmail.com>
	<AANLkTinH7mZtZSQKDYMOE9C8-0baHwm31crmp30roWKy@mail.gmail.com>
	<AANLkTimhWm3dCbO003ipXkaDS3f0o948b9b2NquVSe29@mail.gmail.com>
	<AANLkTi=2B7Pk9HkkxYvQBvm-AfJsYCHW8uYxURq5iEcd@mail.gmail.com>
	<AANLkTi=iVAmVx08ww0EOu9DvJ82oxWD+02Es3btVSqK2@mail.gmail.com>
	<AANLkTin5KdNX6g+ZRYJS0nNy6=bu4o4gwa6v5-XNwkW9@mail.gmail.com>
	<AANLkTikAPuZKYLf4iisi=C4v2onfz5qCXQ-mo2s62UNq@mail.gmail.com>
	<6D9C9A6C-872A-494D-A5F6-2523DD4CA5B6@apple.com>
	<AANLkTi=4=8T0ww0csECny4t0RMSrJV=nUT77h+759-Ab@mail.gmail.com>
	<8FD08C3F-E6E1-448B-A384-7E5CF0763EC1@apple.com>
	<AANLkTikH8sEANQrDGVHg1uOtfCs2UzygkUPpm91E9kZc@mail.gmail.com>
	<AANLkTimoHYSw=viMcpZLirRqd789_xjWmT4+foao_T6f@mail.gmail.com>
	<8E5A9C6C-BA61-41F8-B445-336D9F96D774@apple.com>
	<AANLkTiksC9MbzDhYrzLs9Kt5YRGuHu2nv3Jri=-xRKb9@mail.gmail.com>
	<AANLkTi=73V-VRH_HGiPwcQjBNcFZMiU+jazHMH3YdJ-V@mail.gmail.com>
	<AANLkTikGWx7GH5VZUByposdJWhhvc+qR6X-1Ve_gNmKG@mail.gmail.com>
	<AANLkTik7AYHB1_Crv6Vcf4uMyx4U_x5mJaYK+-S3=ucU@mail.gmail.com>
	<AANLkTi=e_fCXZo_H1=_47tv5BABbpHkf8qJiyrMfRFj_@mail.gmail.com>
	<AANLkTi=MArF+PJK1iwc66wZNobOTjC6pi127Kt=A64bp@mail.gmail.com>
	<AANLkTimHKpEKfy2mr_UKco+Uscg_YBDtCmvXhT4AhAnp@mail.gmail.com>
	<AANLkTimt3NyHcqEh38hn+FnUNL_O5Qv81OYjzE7d0Qf1@mail.gmail.com>
	<AANLkTin8ykW=j=arKX3wC-CX2adx0sTtUmYMJr7qYqJY@mail.gmail.com>
	<AANLkTikXC0jb1VQ--c7iAgX6=DvpTHD_prwSF9F2Tjm4@mail.gmail.com>
	<AANLkTi=SBh85q-m-SvA4nNj9DfdUDXgYmxs6u9Zc4w7s@mail.gmail.com>
	<AANLkTinVf83nF2RUWsmRzT1tL=5MMVJdoGHm8h1D6mG6@mail.gmail.com>
	<AANLkTikHY6Sej-knz3b5+EUjMWVuoPOkWrmFHKHBWtam@mail.gmail.com>
	<AANLkTinFCYO-f67sKptJ0fb6FK=c_zAbX6CMi55W1v+X@mail.gmail.com>
	<AANLkTimxqNQwKoVTEd6J8LrD4mm8_8=ZVeafrHLUsZjb@mail.gmail.com>
	<AANLkTinxWGCVcq1=0rVa-bbMSC2dqKUy5z4m5q_nkQOJ@mail.gmail.com>
	<AANLkTimtZPqq6=0=3E3VKWBqQCjVAP=oij2vUE7=Np_9@mail.gmail.com>
	<AANLkTi=qXYf--J5kgwvm1=7byfM6gRad09d0MEsR3NVi@mail.gmail.com>
	<AANLkTi=FzG7nCvqA0a=GKcXxwMhbU_0=ZWUCerKicvnh@mail.gmail.com>
	<AANLkTikXXEvKcu4KKFMT7eZaWuh-cSd2SpSvu31hJhJk@mail.gmail.com>
	<AANLkTikHnjO-ToOJfFuQvBr3MJaeQjY4Rv7AxLxZq9Kz@mail.gmail.com>
	<AANLkTik3b4iZzDeXh2fcz_vYLYR=sepfWiMsxJZv6k8C@mail.gmail.com>
	<AANLkTi=2yhU-At91xJRHCUfAGmQYnpZuisRpwTF_inTj@mail.gmail.com>
	<AANLkTi=_A15998qNoMLpSBTe8uHn4x99_nzUq+O4Y9bj@mail.gmail.com>
Message-ID: <AANLkTi=0qAudS1SG3HV+8JpG+9_cUSfEWo1sL1b_DkdK@mail.gmail.com>

On 25 October 2010 13:21, Jason Kim <jasonwkim at google.com> wrote:
> All well and good, Rafael, 3 new classes and 4 new slots.
> In any case, I am done arguing this - outside of any additional input
> on this might as well as commit your rework. Any objections?

All of them used ;-). The member variable are also in a class that is
only alive inside emitAttributes.

I will commit your patch with the modifications I made.

> On Sun, Oct 24, 2010 at 7:01 PM, Rafael Esp?ndola
> <rafael.espindola at gmail.com> wrote:
>> I also noticed that we were trying to optimize the output of 41 bytes
>> of data :-)
>
> Err, Yes. 2+ weeks on this. I am without words at the moment.
>
>> The attached patch is similar to the previous one but drops the API
>> changes by just accumulating the attributes locally before outputting
>> them.
>
> -jason
>

Cheers,
-- 
Rafael ?vila de Esp?ndola


From rafael.espindola at gmail.com  Mon Oct 25 12:50:35 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 25 Oct 2010 17:50:35 -0000
Subject: [llvm-commits] [llvm] r117275 - in /llvm/trunk:
 include/llvm/Support/ELF.h lib/MC/ELFObjectWriter.cpp
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp
 lib/Target/ARM/ARMBuildAttrs.h
 test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
Message-ID: <20101025175035.F23132A6C12C@llvm.org>

Author: rafael
Date: Mon Oct 25 12:50:35 2010
New Revision: 117275

URL: http://llvm.org/viewvc/llvm-project?rev=117275&view=rev
Log:
Add support for emitting ARM file attributes.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
Modified:
    llvm/trunk/include/llvm/Support/ELF.h
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h

Modified: llvm/trunk/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=117275&r1=117274&r2=117275&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ELF.h (original)
+++ llvm/trunk/include/llvm/Support/ELF.h Mon Oct 25 12:50:35 2010
@@ -299,6 +299,16 @@
   SHT_LOOS          = 0x60000000, // Lowest operating system-specific type.
   SHT_HIOS          = 0x6fffffff, // Highest operating system-specific type.
   SHT_LOPROC        = 0x70000000, // Lowest processor architecture-specific type.
+  // Fixme: All this is duplicated in MCSectionELF. Why??
+  // Exception Index table
+  SHT_ARM_EXIDX           = 0x70000001U,
+  // BPABI DLL dynamic linking pre-emption map
+  SHT_ARM_PREEMPTMAP      = 0x70000002U,
+  //  Object file compatibility attributes
+  SHT_ARM_ATTRIBUTES      = 0x70000003U,
+  SHT_ARM_DEBUGOVERLAY    = 0x70000004U,
+  SHT_ARM_OVERLAYSECTION  = 0x70000005U,
+
   SHT_HIPROC        = 0x7fffffff, // Highest processor architecture-specific type.
   SHT_LOUSER        = 0x80000000, // Lowest type reserved for applications.
   SHT_HIUSER        = 0xffffffff  // Highest type reserved for applications.

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117275&r1=117274&r2=117275&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Oct 25 12:50:35 2010
@@ -1200,12 +1200,10 @@
     case ELF::SHT_STRTAB:
     case ELF::SHT_NOBITS:
     case ELF::SHT_NULL:
+    case ELF::SHT_ARM_ATTRIBUTES:
       // Nothing to do.
       break;
 
-    case ELF::SHT_HASH:
-    case ELF::SHT_GROUP:
-    case ELF::SHT_SYMTAB_SHNDX:
     default:
       assert(0 && "FIXME: sh_type value not supported!");
       break;

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=117275&r1=117274&r2=117275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Oct 25 12:50:35 2010
@@ -55,12 +55,11 @@
 }
 
 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
-  assert(0 && "ARMAsmBackend::WriteNopData() unimplemented");
   if ((Count % 4) != 0) {
     // Fixme: % 2 for Thumb?
     return false;
   }
-  return false;
+  return true;
 }
 } // end anonymous namespace
 

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117275&r1=117274&r2=117275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Oct 25 12:50:35 2010
@@ -32,10 +32,12 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Target/Mangler.h"
@@ -63,6 +65,91 @@
 }
 
 namespace {
+
+  // Per section and per symbol attributes are not supported.
+  // To implement them we would need the ability to delay this emission
+  // until the assembly file is fully parsed/generated as only then do we
+  // know the symbol and section numbers.
+  class AttributeEmitter {
+  public:
+    virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
+    virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
+    virtual void Finish() = 0;
+  };
+
+  class AsmAttributeEmitter : public AttributeEmitter {
+    MCStreamer &Streamer;
+
+  public:
+    AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
+    void MaybeSwitchVendor(StringRef Vendor) { }
+
+    void EmitAttribute(unsigned Attribute, unsigned Value) {
+      Streamer.EmitRawText("\t.eabi_attribute " +
+                           Twine(Attribute) + ", " + Twine(Value));
+    }
+
+    void Finish() { }
+  };
+
+  class ObjectAttributeEmitter : public AttributeEmitter {
+    MCObjectStreamer &Streamer;
+    size_t SectionStart;
+    size_t TagStart;
+    StringRef CurrentVendor;
+    SmallString<64> Contents;
+
+  public:
+    ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
+      Streamer(Streamer_), CurrentVendor("") { }
+
+    void MaybeSwitchVendor(StringRef Vendor) {
+      assert(!Vendor.empty() && "Vendor cannot be empty.");
+
+      if (CurrentVendor.empty())
+        CurrentVendor = Vendor;
+      else if (CurrentVendor == Vendor)
+        return;
+      else
+        Finish();
+
+      CurrentVendor = Vendor;
+
+      SectionStart = Contents.size();
+
+      // Length of the data for this vendor.
+      Contents.append(4, (char)0);
+
+      Contents.append(Vendor.begin(), Vendor.end());
+      Contents += 0;
+
+      Contents += ARMBuildAttrs::File;
+
+      TagStart = Contents.size();
+
+      // Length of the data for this tag.
+      Contents.append(4, (char)0);
+    }
+
+    void EmitAttribute(unsigned Attribute, unsigned Value) {
+      // FIXME: should be ULEB
+      Contents += Attribute;
+      Contents += Value;
+    }
+
+    void Finish() {
+      size_t EndPos = Contents.size();
+
+      // FIXME: endian.
+      *((uint32_t*)&Contents[SectionStart]) = EndPos - SectionStart;
+
+      // +1 since it includes the tag that came before it.
+      *((uint32_t*)&Contents[TagStart]) = EndPos - TagStart + 1;
+
+      Streamer.EmitBytes(Contents, 0);
+    }
+  };
+
   class ARMAsmPrinter : public AsmPrinter {
 
     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
@@ -110,8 +197,6 @@
   private:
     // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
     void emitAttributes();
-    void emitTextAttribute(ARMBuildAttrs::SpecialAttr attr, StringRef v);
-    void emitAttribute(ARMBuildAttrs::AttrType attr, int v);
 
     // Helper for ELF .o only
     void emitARMAttributeSection();
@@ -502,34 +587,58 @@
 
   emitARMAttributeSection();
 
+  AttributeEmitter *AttrEmitter;
+  if (OutStreamer.hasRawTextSupport())
+    AttrEmitter = new AsmAttributeEmitter(OutStreamer);
+  else {
+    MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
+    AttrEmitter = new ObjectAttributeEmitter(O);
+  }
+
+  AttrEmitter->MaybeSwitchVendor("aeabi");
+
   std::string CPUString = Subtarget->getCPUString();
-  emitTextAttribute(ARMBuildAttrs::SEL_CPU, CPUString);
+  if (OutStreamer.hasRawTextSupport()) {
+    if (CPUString != "generic")
+      OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
+  } else {
+    assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
+    // FIXME: Why these defaults?
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
+  }
 
   // FIXME: Emit FPU type
   if (Subtarget->hasVFP2())
-    emitAttribute(ARMBuildAttrs::VFP_arch, 2);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
 
   // Signal various FP modes.
   if (!UnsafeFPMath) {
-    emitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
-    emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
   }
 
   if (NoInfsFPMath && NoNaNsFPMath)
-    emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
   else
-    emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
 
   // 8-bytes alignment stuff.
-  emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
-  emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
+  AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
+  AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
 
   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
   if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
-    emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
-    emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
   }
   // FIXME: Should we signal R9 usage?
+
+  AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
+
+  AttrEmitter->Finish();
+  delete AttrEmitter;
 }
 
 void ARMAsmPrinter::emitARMAttributeSection() {
@@ -549,32 +658,9 @@
     (getObjFileLowering());
 
   OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
-  // Fixme: Still more to do here.
-}
 
-void ARMAsmPrinter::emitAttribute(ARMBuildAttrs::AttrType attr, int v) {
-  if (OutStreamer.hasRawTextSupport()) {
-    OutStreamer.EmitRawText("\t.eabi_attribute " +
-                            Twine(attr) + ", " + Twine(v));
-
-  } else {
-    assert(0 && "ELF .ARM.attributes unimplemented");
-  }
-}
-
-void ARMAsmPrinter::emitTextAttribute(ARMBuildAttrs::SpecialAttr attr,
-                                      StringRef val) {
-  switch (attr) {
-  default: assert(0 && "Unimplemented ARMBuildAttrs::SpecialAttr"); break;
-  case ARMBuildAttrs::SEL_CPU:
-    if (OutStreamer.hasRawTextSupport()) {
-      if (val != "generic") {
-        OutStreamer.EmitRawText("\t.cpu " + val);
-      }
-    } else {
-      // FIXME: ELF
-    }
-  }
+  // Format version
+  OutStreamer.EmitIntValue(0x41, 1);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=117275&r1=117274&r2=117275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Mon Oct 25 12:50:35 2010
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file contains enumerations and support routines for ARM build attributes
-// as defined in ARM ABI addenda document (ABI release 2.07).
+// as defined in ARM ABI addenda document (ABI release 2.08).
 //
 //===----------------------------------------------------------------------===//
 
@@ -59,18 +59,39 @@
     CPU_unaligned_access      = 34,
     VFP_HP_extension          = 36,
     ABI_FP_16bit_format       = 38,
+    MPextension_use           = 42, // was 70, 2.08 ABI
+    DIV_use                   = 44,
     nodefaults                = 64,
     also_compatible_with      = 65,
     T2EE_use                  = 66,
     conformance               = 67,
     Virtualization_use        = 68,
-    MPextension_use           = 70
+    MPextension_use_old       = 70
   };
 
   // Magic numbers for .ARM.attributes
   enum AttrMagic {
     Format_Version  = 0x41
   };
+
+  // Legal Values for CPU_arch, (=6), uleb128
+  enum CPUArch {
+    Pre_v4       = 0,
+    v4       = 1,   // e.g. SA110
+    v4T      = 2,   // e.g. ARM7TDMI
+    v5T      = 3,   // e.g. ARM9TDMI
+    v5TE     = 4,   // e.g. ARM946E_S
+    v5TEJ    = 5,   // e.g. ARM926EJ_S
+    v6       = 6,   // e.g. ARM1136J_S
+    v6KZ     = 7,   // e.g. ARM1176JZ_S
+    v6T2     = 8,   // e.g. ARM1156T2F_S
+    v6K      = 9,   // e.g. ARM1136J_S
+    v7       = 10,  // e.g. Cortex A8, Cortex M3
+    v6_M     = 11,  // e.g. Cortex M1
+    v6S_M    = 12,  // v6_M with the System extensions
+    v7E_M    = 13   // v7_M with DSP extensions
+  };
+
 }
 
 #endif // __TARGET_ARMBUILDATTRS_H__

Added: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=117275&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Mon Oct 25 12:50:35 2010
@@ -0,0 +1,19 @@
+; RUN: llc  %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \
+; RUN:    elf-dump --dump-section-data | FileCheck %s
+; This tests that the extpected ARM attributes are emitted.
+;
+; CHECK:        .ARM.attributes
+; CHECK-NEXT:         0x70000003
+; CHECK-NEXT:         0x00000000
+; CHECK-NEXT:         0x00000000
+; CHECK-NEXT:         0x0000003c
+; CHECK-NEXT:         0x00000022
+; CHECK-NEXT:         0x00000000
+; CHECK-NEXT:         0x00000000
+; CHECK-NEXT:         0x00000001
+; CHECK-NEXT:         0x00000000
+; CHECK-NEXT:         '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01'
+
+define i32 @f(i64 %z) {
+       ret i32 0
+}



From rafael.espindola at gmail.com  Mon Oct 25 12:58:14 2010
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Mon, 25 Oct 2010 13:58:14 -0400
Subject: [llvm-commits] [llvm] r117275 - in /llvm/trunk:
 include/llvm/Support/ELF.h lib/MC/ELFObjectWriter.cpp
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp
 lib/Target/ARM/ARMBuildAttrs.h
 test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
In-Reply-To: <20101025175035.F23132A6C12C@llvm.org>
References: <20101025175035.F23132A6C12C@llvm.org>
Message-ID: <AANLkTim5vaUS7RuufOnBFCYaYHmjQDeaqTzZz+PxVBLk@mail.gmail.com>

Patch by Jason, refactoring into a class by me.

On 25 October 2010 13:50, Rafael Espindola <rafael.espindola at gmail.com> wrote:
> Author: rafael
> Date: Mon Oct 25 12:50:35 2010
> New Revision: 117275
>
> URL: http://llvm.org/viewvc/llvm-project?rev=117275&view=rev
> Log:
> Add support for emitting ARM file attributes.
>
> Added:
> ? ?llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
> Modified:
> ? ?llvm/trunk/include/llvm/Support/ELF.h
> ? ?llvm/trunk/lib/MC/ELFObjectWriter.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h
>
> Modified: llvm/trunk/include/llvm/Support/ELF.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=117275&r1=117274&r2=117275&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/ELF.h (original)
> +++ llvm/trunk/include/llvm/Support/ELF.h Mon Oct 25 12:50:35 2010
> @@ -299,6 +299,16 @@
> ? SHT_LOOS ? ? ? ? ?= 0x60000000, // Lowest operating system-specific type.
> ? SHT_HIOS ? ? ? ? ?= 0x6fffffff, // Highest operating system-specific type.
> ? SHT_LOPROC ? ? ? ?= 0x70000000, // Lowest processor architecture-specific type.
> + ?// Fixme: All this is duplicated in MCSectionELF. Why??
> + ?// Exception Index table
> + ?SHT_ARM_EXIDX ? ? ? ? ? = 0x70000001U,
> + ?// BPABI DLL dynamic linking pre-emption map
> + ?SHT_ARM_PREEMPTMAP ? ? ?= 0x70000002U,
> + ?// ?Object file compatibility attributes
> + ?SHT_ARM_ATTRIBUTES ? ? ?= 0x70000003U,
> + ?SHT_ARM_DEBUGOVERLAY ? ?= 0x70000004U,
> + ?SHT_ARM_OVERLAYSECTION ?= 0x70000005U,
> +
> ? SHT_HIPROC ? ? ? ?= 0x7fffffff, // Highest processor architecture-specific type.
> ? SHT_LOUSER ? ? ? ?= 0x80000000, // Lowest type reserved for applications.
> ? SHT_HIUSER ? ? ? ?= 0xffffffff ?// Highest type reserved for applications.
>
> Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117275&r1=117274&r2=117275&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
> +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Oct 25 12:50:35 2010
> @@ -1200,12 +1200,10 @@
> ? ? case ELF::SHT_STRTAB:
> ? ? case ELF::SHT_NOBITS:
> ? ? case ELF::SHT_NULL:
> + ? ?case ELF::SHT_ARM_ATTRIBUTES:
> ? ? ? // Nothing to do.
> ? ? ? break;
>
> - ? ?case ELF::SHT_HASH:
> - ? ?case ELF::SHT_GROUP:
> - ? ?case ELF::SHT_SYMTAB_SHNDX:
> ? ? default:
> ? ? ? assert(0 && "FIXME: sh_type value not supported!");
> ? ? ? break;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=117275&r1=117274&r2=117275&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Oct 25 12:50:35 2010
> @@ -55,12 +55,11 @@
> ?}
>
> ?bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
> - ?assert(0 && "ARMAsmBackend::WriteNopData() unimplemented");
> ? if ((Count % 4) != 0) {
> ? ? // Fixme: % 2 for Thumb?
> ? ? return false;
> ? }
> - ?return false;
> + ?return true;
> ?}
> ?} // end anonymous namespace
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117275&r1=117274&r2=117275&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Oct 25 12:50:35 2010
> @@ -32,10 +32,12 @@
> ?#include "llvm/CodeGen/MachineFunctionPass.h"
> ?#include "llvm/CodeGen/MachineJumpTableInfo.h"
> ?#include "llvm/MC/MCAsmInfo.h"
> +#include "llvm/MC/MCAssembler.h"
> ?#include "llvm/MC/MCContext.h"
> ?#include "llvm/MC/MCExpr.h"
> ?#include "llvm/MC/MCInst.h"
> ?#include "llvm/MC/MCSectionMachO.h"
> +#include "llvm/MC/MCObjectStreamer.h"
> ?#include "llvm/MC/MCStreamer.h"
> ?#include "llvm/MC/MCSymbol.h"
> ?#include "llvm/Target/Mangler.h"
> @@ -63,6 +65,91 @@
> ?}
>
> ?namespace {
> +
> + ?// Per section and per symbol attributes are not supported.
> + ?// To implement them we would need the ability to delay this emission
> + ?// until the assembly file is fully parsed/generated as only then do we
> + ?// know the symbol and section numbers.
> + ?class AttributeEmitter {
> + ?public:
> + ? ?virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
> + ? ?virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
> + ? ?virtual void Finish() = 0;
> + ?};
> +
> + ?class AsmAttributeEmitter : public AttributeEmitter {
> + ? ?MCStreamer &Streamer;
> +
> + ?public:
> + ? ?AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
> + ? ?void MaybeSwitchVendor(StringRef Vendor) { }
> +
> + ? ?void EmitAttribute(unsigned Attribute, unsigned Value) {
> + ? ? ?Streamer.EmitRawText("\t.eabi_attribute " +
> + ? ? ? ? ? ? ? ? ? ? ? ? ? Twine(Attribute) + ", " + Twine(Value));
> + ? ?}
> +
> + ? ?void Finish() { }
> + ?};
> +
> + ?class ObjectAttributeEmitter : public AttributeEmitter {
> + ? ?MCObjectStreamer &Streamer;
> + ? ?size_t SectionStart;
> + ? ?size_t TagStart;
> + ? ?StringRef CurrentVendor;
> + ? ?SmallString<64> Contents;
> +
> + ?public:
> + ? ?ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
> + ? ? ?Streamer(Streamer_), CurrentVendor("") { }
> +
> + ? ?void MaybeSwitchVendor(StringRef Vendor) {
> + ? ? ?assert(!Vendor.empty() && "Vendor cannot be empty.");
> +
> + ? ? ?if (CurrentVendor.empty())
> + ? ? ? ?CurrentVendor = Vendor;
> + ? ? ?else if (CurrentVendor == Vendor)
> + ? ? ? ?return;
> + ? ? ?else
> + ? ? ? ?Finish();
> +
> + ? ? ?CurrentVendor = Vendor;
> +
> + ? ? ?SectionStart = Contents.size();
> +
> + ? ? ?// Length of the data for this vendor.
> + ? ? ?Contents.append(4, (char)0);
> +
> + ? ? ?Contents.append(Vendor.begin(), Vendor.end());
> + ? ? ?Contents += 0;
> +
> + ? ? ?Contents += ARMBuildAttrs::File;
> +
> + ? ? ?TagStart = Contents.size();
> +
> + ? ? ?// Length of the data for this tag.
> + ? ? ?Contents.append(4, (char)0);
> + ? ?}
> +
> + ? ?void EmitAttribute(unsigned Attribute, unsigned Value) {
> + ? ? ?// FIXME: should be ULEB
> + ? ? ?Contents += Attribute;
> + ? ? ?Contents += Value;
> + ? ?}
> +
> + ? ?void Finish() {
> + ? ? ?size_t EndPos = Contents.size();
> +
> + ? ? ?// FIXME: endian.
> + ? ? ?*((uint32_t*)&Contents[SectionStart]) = EndPos - SectionStart;
> +
> + ? ? ?// +1 since it includes the tag that came before it.
> + ? ? ?*((uint32_t*)&Contents[TagStart]) = EndPos - TagStart + 1;
> +
> + ? ? ?Streamer.EmitBytes(Contents, 0);
> + ? ?}
> + ?};
> +
> ? class ARMAsmPrinter : public AsmPrinter {
>
> ? ? /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
> @@ -110,8 +197,6 @@
> ? private:
> ? ? // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
> ? ? void emitAttributes();
> - ? ?void emitTextAttribute(ARMBuildAttrs::SpecialAttr attr, StringRef v);
> - ? ?void emitAttribute(ARMBuildAttrs::AttrType attr, int v);
>
> ? ? // Helper for ELF .o only
> ? ? void emitARMAttributeSection();
> @@ -502,34 +587,58 @@
>
> ? emitARMAttributeSection();
>
> + ?AttributeEmitter *AttrEmitter;
> + ?if (OutStreamer.hasRawTextSupport())
> + ? ?AttrEmitter = new AsmAttributeEmitter(OutStreamer);
> + ?else {
> + ? ?MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
> + ? ?AttrEmitter = new ObjectAttributeEmitter(O);
> + ?}
> +
> + ?AttrEmitter->MaybeSwitchVendor("aeabi");
> +
> ? std::string CPUString = Subtarget->getCPUString();
> - ?emitTextAttribute(ARMBuildAttrs::SEL_CPU, CPUString);
> + ?if (OutStreamer.hasRawTextSupport()) {
> + ? ?if (CPUString != "generic")
> + ? ? ?OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
> + ?} else {
> + ? ?assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
> + ? ?// FIXME: Why these defaults?
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
> + ?}
>
> ? // FIXME: Emit FPU type
> ? if (Subtarget->hasVFP2())
> - ? ?emitAttribute(ARMBuildAttrs::VFP_arch, 2);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
>
> ? // Signal various FP modes.
> ? if (!UnsafeFPMath) {
> - ? ?emitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
> - ? ?emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
> ? }
>
> ? if (NoInfsFPMath && NoNaNsFPMath)
> - ? ?emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
> ? else
> - ? ?emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
>
> ? // 8-bytes alignment stuff.
> - ?emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
> - ?emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
> + ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
> + ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
>
> ? // Hard float. ?Use both S and D registers and conform to AAPCS-VFP.
> ? if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
> - ? ?emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
> - ? ?emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
> + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
> ? }
> ? // FIXME: Should we signal R9 usage?
> +
> + ?AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
> +
> + ?AttrEmitter->Finish();
> + ?delete AttrEmitter;
> ?}
>
> ?void ARMAsmPrinter::emitARMAttributeSection() {
> @@ -549,32 +658,9 @@
> ? ? (getObjFileLowering());
>
> ? OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
> - ?// Fixme: Still more to do here.
> -}
>
> -void ARMAsmPrinter::emitAttribute(ARMBuildAttrs::AttrType attr, int v) {
> - ?if (OutStreamer.hasRawTextSupport()) {
> - ? ?OutStreamer.EmitRawText("\t.eabi_attribute " +
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?Twine(attr) + ", " + Twine(v));
> -
> - ?} else {
> - ? ?assert(0 && "ELF .ARM.attributes unimplemented");
> - ?}
> -}
> -
> -void ARMAsmPrinter::emitTextAttribute(ARMBuildAttrs::SpecialAttr attr,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StringRef val) {
> - ?switch (attr) {
> - ?default: assert(0 && "Unimplemented ARMBuildAttrs::SpecialAttr"); break;
> - ?case ARMBuildAttrs::SEL_CPU:
> - ? ?if (OutStreamer.hasRawTextSupport()) {
> - ? ? ?if (val != "generic") {
> - ? ? ? ?OutStreamer.EmitRawText("\t.cpu " + val);
> - ? ? ?}
> - ? ?} else {
> - ? ? ?// FIXME: ELF
> - ? ?}
> - ?}
> + ?// Format version
> + ?OutStreamer.EmitIntValue(0x41, 1);
> ?}
>
> ?//===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=117275&r1=117274&r2=117275&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Mon Oct 25 12:50:35 2010
> @@ -8,7 +8,7 @@
> ?//===----------------------------------------------------------------------===//
> ?//
> ?// This file contains enumerations and support routines for ARM build attributes
> -// as defined in ARM ABI addenda document (ABI release 2.07).
> +// as defined in ARM ABI addenda document (ABI release 2.08).
> ?//
> ?//===----------------------------------------------------------------------===//
>
> @@ -59,18 +59,39 @@
> ? ? CPU_unaligned_access ? ? ?= 34,
> ? ? VFP_HP_extension ? ? ? ? ?= 36,
> ? ? ABI_FP_16bit_format ? ? ? = 38,
> + ? ?MPextension_use ? ? ? ? ? = 42, // was 70, 2.08 ABI
> + ? ?DIV_use ? ? ? ? ? ? ? ? ? = 44,
> ? ? nodefaults ? ? ? ? ? ? ? ?= 64,
> ? ? also_compatible_with ? ? ?= 65,
> ? ? T2EE_use ? ? ? ? ? ? ? ? ?= 66,
> ? ? conformance ? ? ? ? ? ? ? = 67,
> ? ? Virtualization_use ? ? ? ?= 68,
> - ? ?MPextension_use ? ? ? ? ? = 70
> + ? ?MPextension_use_old ? ? ? = 70
> ? };
>
> ? // Magic numbers for .ARM.attributes
> ? enum AttrMagic {
> ? ? Format_Version ?= 0x41
> ? };
> +
> + ?// Legal Values for CPU_arch, (=6), uleb128
> + ?enum CPUArch {
> + ? ?Pre_v4 ? ? ? = 0,
> + ? ?v4 ? ? ? = 1, ? // e.g. SA110
> + ? ?v4T ? ? ?= 2, ? // e.g. ARM7TDMI
> + ? ?v5T ? ? ?= 3, ? // e.g. ARM9TDMI
> + ? ?v5TE ? ? = 4, ? // e.g. ARM946E_S
> + ? ?v5TEJ ? ?= 5, ? // e.g. ARM926EJ_S
> + ? ?v6 ? ? ? = 6, ? // e.g. ARM1136J_S
> + ? ?v6KZ ? ? = 7, ? // e.g. ARM1176JZ_S
> + ? ?v6T2 ? ? = 8, ? // e.g. ARM1156T2F_S
> + ? ?v6K ? ? ?= 9, ? // e.g. ARM1136J_S
> + ? ?v7 ? ? ? = 10, ?// e.g. Cortex A8, Cortex M3
> + ? ?v6_M ? ? = 11, ?// e.g. Cortex M1
> + ? ?v6S_M ? ?= 12, ?// v6_M with the System extensions
> + ? ?v7E_M ? ?= 13 ? // v7_M with DSP extensions
> + ?};
> +
> ?}
>
> ?#endif // __TARGET_ARMBUILDATTRS_H__
>
> Added: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=117275&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Mon Oct 25 12:50:35 2010
> @@ -0,0 +1,19 @@
> +; RUN: llc ?%s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \
> +; RUN: ? ?elf-dump --dump-section-data | FileCheck %s
> +; This tests that the extpected ARM attributes are emitted.
> +;
> +; CHECK: ? ? ? ?.ARM.attributes
> +; CHECK-NEXT: ? ? ? ? 0x70000003
> +; CHECK-NEXT: ? ? ? ? 0x00000000
> +; CHECK-NEXT: ? ? ? ? 0x00000000
> +; CHECK-NEXT: ? ? ? ? 0x0000003c
> +; CHECK-NEXT: ? ? ? ? 0x00000022
> +; CHECK-NEXT: ? ? ? ? 0x00000000
> +; CHECK-NEXT: ? ? ? ? 0x00000000
> +; CHECK-NEXT: ? ? ? ? 0x00000001
> +; CHECK-NEXT: ? ? ? ? 0x00000000
> +; CHECK-NEXT: ? ? ? ? '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01'
> +
> +define i32 @f(i64 %z) {
> + ? ? ? ret i32 0
> +}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From resistor at mac.com  Mon Oct 25 13:03:59 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 18:03:59 -0000
Subject: [llvm-commits] [llvm] r117276 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-cmp-encoding.ll
Message-ID: <20101025180359.D0E0D2A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 13:03:59 2010
New Revision: 117276

URL: http://llvm.org/viewvc/llvm-project?rev=117276&view=rev
Log:
Add NEON encoding tests for vcgt and vacgt.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117276&r1=117275&r2=117276&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 13:03:59 2010
@@ -2824,9 +2824,11 @@
 def  VCGTfq   : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
                      NEONvcgt, 0>;
 // For disassembly only.
+// FIXME: This instruction's encoding MAY NOT BE correct.
 defm VCGTz    : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
                             "$dst, $src, #0">;
 // For disassembly only.
+// FIXME: This instruction's encoding MAY NOT BE correct.
 defm VCLTz    : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
                             "$dst, $src, #0">;
 

Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll?rev=117276&r1=117275&r2=117276&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll Mon Oct 25 13:03:59 2010
@@ -4,6 +4,7 @@
 ; currently marked as for-disassembly only in the .td files:
 ;  - VCEQz
 ;  - VCGEz, VCLEz
+;  - VCGTz, VCLTz
 
 ; CHECK: vceq_8xi8
 define <8 x i8> @vceq_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -245,3 +246,165 @@
 	%tmp3 = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x i32> %tmp3
 }
+
+; CHECK: vcgts_8xi8
+define <8 x i8> @vcgts_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vcgt.s8	d16, d16, d17           @ encoding: [0xa1,0x03,0x40,0xf2]
+	%tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vcgts_4xi16
+define <4 x i16> @vcgts_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vcgt.s16	d16, d16, d17   @ encoding: [0xa1,0x03,0x50,0xf2]
+	%tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+; CHECK: vcgts_2xi32
+define <2 x i32> @vcgts_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vcgt.s32	d16, d16, d17   @ encoding: [0xa1,0x03,0x60,0xf2]
+	%tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vcgtu_8xi8
+define <8 x i8> @vcgtu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vcgt.u8	d16, d16, d17           @ encoding: [0xa1,0x03,0x40,0xf3]
+	%tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vcgtu_4xi16
+define <4 x i16> @vcgtu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vcgt.u16	d16, d16, d17   @ encoding: [0xa1,0x03,0x50,0xf3]
+	%tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+; CHECK: vcgtu_2xi32
+define <2 x i32> @vcgtu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vcgt.u32	d16, d16, d17   @ encoding: [0xa1,0x03,0x60,0xf3]
+	%tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vcgt_2xfloat
+define <2 x i32> @vcgt_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vcgt.f32	d16, d16, d17   @ encoding: [0xa1,0x0e,0x60,0xf3]
+	%tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
+  %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+; CHECK: vcgts_16xi8
+define <16 x i8> @vcgts_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vcgt.s8	q8, q8, q9              @ encoding: [0xe2,0x03,0x40,0xf2]
+	%tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
+  %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vcgts_8xi16
+define <8 x i16> @vcgts_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vcgt.s16	q8, q8, q9      @ encoding: [0xe2,0x03,0x50,0xf2]
+	%tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vcgts_4xi32
+define <4 x i32> @vcgts_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vcgt.s32	q8, q8, q9      @ encoding: [0xe2,0x03,0x60,0xf2]
+	%tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vcgtu_16xi8
+define <16 x i8> @vcgtu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vcgt.u8	q8, q8, q9              @ encoding: [0xe2,0x03,0x40,0xf3]
+	%tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
+  %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vcgtu_8xi16
+define <8 x i16> @vcgtu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vcgt.u16	q8, q8, q9      @ encoding: [0xe2,0x03,0x50,0xf3]
+	%tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
+  %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vcgtu_4xi32
+define <4 x i32> @vcgtu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vcgt.u32	q8, q8, q9      @ encoding: [0xe2,0x03,0x60,0xf3]
+	%tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vcgt_4xfloat
+define <4 x i32> @vcgt_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vcgt.f32	q8, q8, q9      @ encoding: [0xe2,0x0e,0x60,0xf3]
+	%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
+  %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vacgt_2xfloat
+define <2 x i32> @vacgt_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vacgt.f32	d16, d16, d17   @ encoding: [0xb1,0x0e,0x60,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vacgt_4xfloat
+define <4 x i32> @vacgt_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vacgt.f32	q8, q8, q9      @ encoding: [0xf2,0x0e,0x60,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x i32> %tmp3
+}
+



From resistor at mac.com  Mon Oct 25 13:10:34 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 18:10:34 -0000
Subject: [llvm-commits] [llvm] r117277 -
	/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
Message-ID: <20101025181034.7E1EE2A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 13:10:34 2010
New Revision: 117277

URL: http://llvm.org/viewvc/llvm-project?rev=117277&view=rev
Log:
Add tests for NEON encoding of vtst.

Modified:
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll?rev=117277&r1=117276&r2=117277&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.ll Mon Oct 25 13:10:34 2010
@@ -408,3 +408,68 @@
 	ret <4 x i32> %tmp3
 }
 
+; CHECK: vtst_8xi8
+define <8 x i8> @vtst_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vtst.8	d16, d16, d17           @ encoding: [0xb1,0x08,0x40,0xf2]
+	%tmp3 = and <8 x i8> %tmp1, %tmp2
+	%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
+  %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
+	ret <8 x i8> %tmp5
+}
+
+; CHECK: vtst_4xi16
+define <4 x i16> @vtst_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vtst.16	d16, d16, d17           @ encoding: [0xb1,0x08,0x50,0xf2]
+	%tmp3 = and <4 x i16> %tmp1, %tmp2
+	%tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
+  %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
+	ret <4 x i16> %tmp5
+}
+
+; CHECK: vtst_2xi32
+define <2 x i32> @vtst_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vtst.32	d16, d16, d17           @ encoding: [0xb1,0x08,0x60,0xf2]
+	%tmp3 = and <2 x i32> %tmp1, %tmp2
+	%tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
+  %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
+	ret <2 x i32> %tmp5
+}
+
+; CHECK: vtst_16xi8
+define <16 x i8> @vtst_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vtst.8	q8, q8, q9              @ encoding: [0xf2,0x08,0x40,0xf2]
+	%tmp3 = and <16 x i8> %tmp1, %tmp2
+	%tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
+  %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
+	ret <16 x i8> %tmp5
+}
+
+; CHECK: vtst_8xi16
+define <8 x i16> @vtst_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vtst.16	q8, q8, q9              @ encoding: [0xf2,0x08,0x50,0xf2]
+	%tmp3 = and <8 x i16> %tmp1, %tmp2
+	%tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
+  %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
+	ret <8 x i16> %tmp5
+}
+
+; CHECK: vtst_4xi32
+define <4 x i32> @vtst_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vtst.32	q8, q8, q9              @ encoding: [0xf2,0x08,0x60,0xf2]
+	%tmp3 = and <4 x i32> %tmp1, %tmp2
+	%tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
+  %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
+	ret <4 x i32> %tmp5
+}



From resistor at mac.com  Mon Oct 25 13:28:30 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 18:28:30 -0000
Subject: [llvm-commits] [llvm] r117279 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td test/MC/ARM/neon-bitwise-encoding.ll
Message-ID: <20101025182830.6B9792A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 13:28:30 2010
New Revision: 117279

URL: http://llvm.org/viewvc/llvm-project?rev=117279&view=rev
Log:
Provide correct NEON encodings for vand, veor, and vorr.

Added:
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117279&r1=117278&r2=117279&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Oct 25 13:28:30 2010
@@ -1765,6 +1765,18 @@
   let Inst{11-8}  = op11_8;
   let Inst{6}     = op6;
   let Inst{4}     = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<5> Vn;
+  bits<5> Vm;
+
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{19-16} = Vn{3-0};
+  let Inst{7}     = Vn{4};
+  let Inst{3-0}   = Vm{3-0};
+  let Inst{5}     = Vm{4};
 }
 
 // NEON VMOVs between scalar and core registers.

Added: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117279&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Mon Oct 25 13:28:30 2010
@@ -0,0 +1,58 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+; FIXME: The following instructions still require testing:
+;  - vand with immediate
+
+; CHECK: vand_8xi8
+define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vand	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf2]
+	%tmp3 = and <8 x i8> %tmp1, %tmp2
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vand_16xi8
+define <16 x i8> @vand_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vand	q8, q8, q9              @ encoding: [0xf2,0x01,0x40,0xf2]
+	%tmp3 = and <16 x i8> %tmp1, %tmp2
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: veor_8xi8
+define <8 x i8> @veor_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: veor	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf3]
+	%tmp3 = xor <8 x i8> %tmp1, %tmp2
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: veor_16xi8
+define <16 x i8> @veor_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: veor	q8, q8, q9              @ encoding: [0xf2,0x01,0x40,0xf3]
+	%tmp3 = xor <16 x i8> %tmp1, %tmp2
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vorr_8xi8
+define <8 x i8> @vorr_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vorr	d16, d17, d16           @ encoding: [0xb0,0x01,0x61,0xf2]
+	%tmp3 = or <8 x i8> %tmp1, %tmp2
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vorr_16xi8
+define <16 x i8> @vorr_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vorr	q8, q8, q9              @ encoding: [0xf2,0x01,0x60,0xf2]
+	%tmp3 = or <16 x i8> %tmp1, %tmp2
+	ret <16 x i8> %tmp3
+}
\ No newline at end of file



From rafael.espindola at gmail.com  Mon Oct 25 13:38:32 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 25 Oct 2010 18:38:32 -0000
Subject: [llvm-commits] [llvm] r117280 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20101025183832.3E5192A6C12C@llvm.org>

Author: rafael
Date: Mon Oct 25 13:38:32 2010
New Revision: 117280

URL: http://llvm.org/viewvc/llvm-project?rev=117280&view=rev
Log:
Add a virtual destructor.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117280&r1=117279&r2=117280&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Oct 25 13:38:32 2010
@@ -75,6 +75,7 @@
     virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
     virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
     virtual void Finish() = 0;
+    virtual ~AttributeEmitter() {}
   };
 
   class AsmAttributeEmitter : public AttributeEmitter {



From resistor at mac.com  Mon Oct 25 13:43:52 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 18:43:52 -0000
Subject: [llvm-commits] [llvm] r117282 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
 test/MC/ARM/neon-bitwise-encoding.ll
Message-ID: <20101025184352.EF9472A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 13:43:52 2010
New Revision: 117282

URL: http://llvm.org/viewvc/llvm-project?rev=117282&view=rev
Log:
Add correct instruction encodings for vbic, vorn, and vmvn.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117282&r1=117281&r2=117282&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Oct 25 13:43:52 2010
@@ -1698,6 +1698,15 @@
   let Inst{11-7}  = op11_7;
   let Inst{6}     = op6;
   let Inst{4}     = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<5> Vm;
+
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{3-0}   = Vm{3-0};
+  let Inst{5}     = Vm{4};
 }
 
 // Same as N2V except it doesn't have a datatype suffix.
@@ -1713,6 +1722,15 @@
   let Inst{11-7}  = op11_7;
   let Inst{6}     = op6;
   let Inst{4}     = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<5> Vm;
+
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{3-0}   = Vm{3-0};
+  let Inst{5}     = Vm{4};
 }
 
 // NEON 2 vector register with immediate.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117282&r1=117281&r2=117282&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 13:43:52 2010
@@ -2899,19 +2899,22 @@
 //   VMVN     : Vector Bitwise NOT (Immediate)
 
 let isReMaterializable = 1 in {
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$dst, $SIMM", "",
                          [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$dst, $SIMM", "",
                          [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
-
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i32", "$dst, $SIMM", "",
                          [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i32", "$dst, $SIMM", "",

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117282&r1=117281&r2=117282&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Mon Oct 25 13:43:52 2010
@@ -2,6 +2,7 @@
 
 ; FIXME: The following instructions still require testing:
 ;  - vand with immediate
+;  - vmvn of an immediate
 
 ; CHECK: vand_8xi8
 define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -55,4 +56,60 @@
 ; CHECK: vorr	q8, q8, q9              @ encoding: [0xf2,0x01,0x60,0xf2]
 	%tmp3 = or <16 x i8> %tmp1, %tmp2
 	ret <16 x i8> %tmp3
-}
\ No newline at end of file
+}
+
+; CHECK: vbic_8xi8
+define <8 x i8> @vbic_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vbic	d16, d17, d16           @ encoding: [0xb0,0x01,0x51,0xf2]
+	%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp4 = and <8 x i8> %tmp1, %tmp3
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vbic_16xi8
+define <16 x i8> @vbic_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vbic	q8, q8, q9              @ encoding: [0xf2,0x01,0x50,0xf2]
+	%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp4 = and <16 x i8> %tmp1, %tmp3
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vorn_8xi8
+define <8 x i8> @vorn_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vorn	d16, d17, d16           @ encoding: [0xb0,0x01,0x71,0xf2]
+	%tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp4 = or <8 x i8> %tmp1, %tmp3
+	ret <8 x i8> %tmp4
+}
+
+; CHECK: vorn_16xi8
+define <16 x i8> @vorn_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vorn	q8, q8, q9              @ encoding: [0xf2,0x01,0x70,0xf2]
+	%tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp4 = or <16 x i8> %tmp1, %tmp3
+	ret <16 x i8> %tmp4
+}
+
+; CHECK: vmvn_8xi8
+define <8 x i8> @vmvn_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vmvn	d16, d16                @ encoding: [0xa0,0x05,0xf0,0xf3]
+	%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vmvn_16xi8
+define <16 x i8> @vmvn_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vmvn	q8, q8                  @ encoding: [0xe0,0x05,0xf0,0xf3]
+	%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	ret <16 x i8> %tmp2
+}



From john.thompson.jtsoftware at gmail.com  Mon Oct 25 13:59:14 2010
From: john.thompson.jtsoftware at gmail.com (John Thompson)
Date: Mon, 25 Oct 2010 11:59:14 -0700
Subject: [llvm-commits] [PATCH] Inline asm mult-alt constraints done for
	now
In-Reply-To: <9A1D67C5-A2E4-482E-A7AC-2523D412AE9B@apple.com>
References: <AANLkTimqDbOn8PJTH7UtRFuX7BKpbonoJiJ3w3Ly9Aqt@mail.gmail.com>
	<FDD00E40-6648-4E4B-B43C-139DCE499F37@apple.com>
	<AANLkTim_Z3UFnHf3u2LS83Phu-UMk-jmZthLgo0thmDe@mail.gmail.com>
	<9A1D67C5-A2E4-482E-A7AC-2523D412AE9B@apple.com>
Message-ID: <AANLkTi=e+3ObdE8fMBzNuS5TMNjByUNXr-8r5VL=GHU1@mail.gmail.com>

Thanks, Dale.  Though I'm still rebuilding my system after a crash, here a
revised patch which addresses some of the issues, with the following notes.
This is from an updated tree from Friday, with the 3 sets of llvm tests
re-run.

>There is too much duplication in the different versions of
getSingleConstraintMatchWeight.  Generic constraints like 'r' should be
handled only in the generic version.  I think several of the overloaded
versions can go away entirely.  The approach of substituting
ConstraintWeight for numbers is generally OK with this modification.

Yes, I noticed that, but I put it in anyway to be consistent with the
getConstraintType function already there, which I used as a guide.  I've
removed these in the new patch.  The platform implementer can probably
figure out when he needs to add one, using another platform as a guide.

> Should be followed by 'break' (several places).  It's disturbing that
testing didn't catch this.

Yes.  Sorry, I haven't tested all the platforms yet, only Linux x86.  Rather
than do this whole thing all at once, I've been trying to do it
incrementally.  My reasoning is that since multi-alt wouldn't work in Clang
anyway, as long as I don't regress on the existing tests, I should be okay,
now that I know how to run all three sets of tests.  I have a couple of test
files I'm working on locally, which I plan to convert to clang and LLVM test
files after I get the current patch in.

Having said that, it just occured to me that perhaps I should be running the
gcc tests for multiple platforms, rather than just the default one in the
makefile.  Do you guys do that?  If so, could you give me a list of the
triples that I should test?

To give it a shot, I ran the gcc tests with powerpc-apple-darwin for the
build and target in the top-level makefile.  Perhaps running the gcc
tests targeting platforms other than x86 would have caught this.  Here's my
results:

Modified summary:
# of expected passes        16082
# of unexpected failures    17933
# of unexpected successes    29
# of expected failures        28
# of unresolved testcases    8666
# of untested testcases        273
# of unsupported tests        671
/home/john/llvm/Release+Asserts/bin/clang  version 2.9 (trunk 117191)

Original summary:
# of expected passes        16082
# of unexpected failures    17933
# of unexpected successes    29
# of expected failures        28
# of unresolved testcases    8666
# of untested testcases        273
# of unsupported tests        671
/home/john/llvm_org/Release+Asserts/bin/clang  version 2.9 (trunk 117191)
Quite a lot fewer passes than in x86, but the results for the
modified/original trees are the same.

 > I need to look at the ParseConstraints bits more, I don't really
understand what you're doing there yet.

There are two main parts of it.  One part (the beginning and ending chunks
of code) was to take some of what was in
SelectionDAGBuilder::visitInlineAsm, and some other stuff in
SelectionDAGBuilder.cpp such as getCallOperandValEVT, and duplicate it here,
to the extent possible without having a DAG.  This was necessary because of
that one place where parsing the constraints was needed outside of the DAG
pass.

The second part (the code chunk in the middle) does the selection of the
constraint alternatives, if there are multiple, using the
getMultipleConstraintMatchWeight function to compute the best constraint
weight for one alternative, which might have multiple constraint letters.
The getSingleConstraintMatchWeight function computes the weight for one
constraint character, and is the part to be overidden for different
platforms.

The main idea was that I could inject the support for multiple-alternative
constraints without affecting the current logic.

There are a couple of architectural problems with this in that the parsing
could be done multiple times in some circumstances, as opposed to doing it
once and saving the results, and there is some duplication of functionality,
but changing this would be a much more significant change, and I thought it
best to just get it to work reasonably as-is, since the whole inline asm
lowering is a pretty complicated set of logic.

>The bits covered above can go in.

I think it would be dangerous to try to separate the parts now, so can I
just wait until you are comfortable with the whole patch?  I'm assuming it
won't take much more time.  I'm available if you would like me to come over
and look at it with you (I'm in Santa Clara).

Thanks again!

-John


On Thu, Oct 21, 2010 at 11:54 AM, Dale Johannesen <dalej at apple.com> wrote:

> OK, I've gotten to this now.  Thanks for your patience.
>
> The various changes of std::vector to SmallVector and uses of typedefs are
> OK.
>
> There is too much duplication in the different versions of
> getSingleConstraintMatchWeight.  Generic constraints like 'r' should be
> handled only in the generic version.  I think several of the overloaded
> versions can go away entirely.  The approach of substituting
> ConstraintWeight for numbers is generally OK with this modification.
>
>   +  default:
> +    weight = TargetLowering::getSingleConstraintMatchWeight(info,
> constraint);
>
>
> Should be followed by 'break' (several places).  It's disturbing that
> testing didn't catch this.
>
>  +    CW_Okay     = 0,      // Acceptible.
>
>
> Spelling.
>
> I need to look at the ParseConstraints bits more, I don't really understand
> what you're doing there yet.   The bits covered above can go in.
>
>  On Oct 15, 2010, at 10:42 AMPDT, John Thompson wrote:
>
>  Thanks for the heads up, Evan.
>
> I forgot to point out a couple of other changes I made.  One was to change
> some usages of std::vector to SmallVector typedefs on the stuff related to
> the constraints.  The other was that I changed some hard tabs in one file
> (not from me this time) to spaces, based on the report from a checking
> program I wrote and am now running on the files I touch.
> -John
> On Fri, Oct 15, 2010 at 10:02 AM, Evan Cheng <evan.cheng at apple.com> wrote:
>
>> Dale should review this once he gets back on Monday.
>>
>> Evan
>>
>>   On Oct 14, 2010, at 6:41 PM, John Thompson wrote:
>>
>>   I made a pass through all the platforms, and added support for the
>> weighting of the platform-specific constraints that seemed to have any kind
>> of support, which was not much, based on what was in the existing
>> getConstraintType functions.  There probably isn't much point
>> adding weighting for constraints not yet supported, but at least the now
>> framework is there for if and when they are added.  Therefore, I'm
>> considering Clang/LLVM mult-alt constraint support done for now, except for
>> some tests I'm getting in shape to check in for both the Clang and LLVM
>> sides.  I've run the regression tests, test-suite, and gcc tests on both
>> modified and unmodified trees from this morning on Linux with no
>> differences.
>>
>> May I check this in?
>>
>> Thanks.
>>
>> -John
>>
>> --
>> John Thompson
>> John.Thompson.JTSoftware at gmail.com
>>
>> <llvmmultalt15.patch>_______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>>
>
>
> --
> John Thompson
> John.Thompson.JTSoftware at gmail.com
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>


-- 
John Thompson
John.Thompson.JTSoftware at gmail.com
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Index: include/llvm/Target/TargetLowering.h
===================================================================
--- include/llvm/Target/TargetLowering.h	(revision 117191)
+++ include/llvm/Target/TargetLowering.h	(working copy)
@@ -1320,6 +1320,22 @@
     C_Unknown              // Unsupported constraint.
   };
 
+  enum ConstraintWeight {
+    // Generic weights.
+    CW_Invalid  = -1,     // No match.
+    CW_Okay     = 0,      // Acceptable.
+    CW_Good     = 1,      // Good weight.
+    CW_Better   = 2,      // Better weight.
+    CW_Best     = 3,      // Best weight.
+    
+    // Well-known weights.
+    CW_SpecificReg  = CW_Okay,    // Specific register operands.
+    CW_Register     = CW_Good,    // Register operands.
+    CW_Memory       = CW_Better,  // Memory operands.
+    CW_Constant     = CW_Best,    // Constant operand.
+    CW_Default      = CW_Okay     // Default or don't know type.
+  };
+
   /// AsmOperandInfo - This contains information for each constraint that we are
   /// lowering.
   struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
@@ -1365,24 +1381,23 @@
     }
   };
   
+  typedef SmallVector<AsmOperandInfo,16> AsmOperandInfoVector;
+  
   /// ParseConstraints - Split up the constraint string from the inline
   /// assembly value into the specific constraints and their prefixes,
   /// and also tie in the associated operand values.
   /// If this returns an empty vector, and if the constraint string itself
   /// isn't empty, there was an error parsing.
-  virtual std::vector<AsmOperandInfo> ParseConstraints(
-    ImmutableCallSite CS) const;
+  virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
   
-  /// Examine constraint type and operand type and determine a weight value,
-  /// where: -1 = invalid match, and 0 = so-so match to 5 = good match.
+  /// Examine constraint type and operand type and determine a weight value.
   /// The operand object must already have been set up with the operand type.
-  virtual int getMultipleConstraintMatchWeight(
+  virtual ConstraintWeight getMultipleConstraintMatchWeight(
       AsmOperandInfo &info, int maIndex) const;
   
-  /// Examine constraint string and operand type and determine a weight value,
-  /// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
+  /// Examine constraint string and operand type and determine a weight value.
   /// The operand object must already have been set up with the operand type.
-  virtual int getSingleConstraintMatchWeight(
+  virtual ConstraintWeight getSingleConstraintMatchWeight(
       AsmOperandInfo &info, const char *constraint) const;
 
   /// ComputeConstraintToUse - Determines the constraint code and constraint
Index: include/llvm/InlineAsm.h
===================================================================
--- include/llvm/InlineAsm.h	(revision 117191)
+++ include/llvm/InlineAsm.h	(working copy)
@@ -16,8 +16,8 @@
 #ifndef LLVM_INLINEASM_H
 #define LLVM_INLINEASM_H
 
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/Value.h"
-#include <vector>
 
 namespace llvm {
 
@@ -87,6 +87,8 @@
     isClobber           // '~x'
   };
   
+  typedef SmallVector<std::string,8> ConstraintCodeVector;
+  
   struct SubConstraintInfo {
     /// MatchingInput - If this is not -1, this is an output constraint where an
     /// input constraint is required to match it (e.g. "0").  The value is the
@@ -95,10 +97,14 @@
     signed char MatchingInput;
     /// Code - The constraint code, either the register name (in braces) or the
     /// constraint letter/number.
-    std::vector<std::string> Codes;
+    ConstraintCodeVector Codes;
     /// Default constructor.
     SubConstraintInfo() : MatchingInput(-1) {}
   };
+
+  typedef SmallVector<SubConstraintInfo,4> SubConstraintInfoVector;
+  struct ConstraintInfo;
+  typedef SmallVector<ConstraintInfo,16> ConstraintInfoVector;
   
   struct ConstraintInfo {
     /// Type - The basic type of the constraint: input/output/clobber
@@ -131,14 +137,14 @@
     
     /// Code - The constraint code, either the register name (in braces) or the
     /// constraint letter/number.
-    std::vector<std::string> Codes;
+    ConstraintCodeVector Codes;
     
     /// isMultipleAlternative - '|': has multiple-alternative constraints.
     bool isMultipleAlternative;
     
     /// multipleAlternatives - If there are multiple alternative constraints,
     /// this array will contain them.  Otherwise it will be empty.
-    std::vector<SubConstraintInfo> multipleAlternatives;
+    SubConstraintInfoVector multipleAlternatives;
     
     /// The currently selected alternative constraint index.
     unsigned currentAlternativeIndex;
@@ -152,8 +158,7 @@
     /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
     /// fields in this structure.  If the constraint string is not understood,
     /// return true, otherwise return false.
-    bool Parse(StringRef Str, 
-               std::vector<InlineAsm::ConstraintInfo> &ConstraintsSoFar);
+    bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
                
     /// selectAlternative - Point this constraint to the alternative constraint
     /// indicated by the index.
@@ -163,13 +168,11 @@
   /// ParseConstraints - Split up the constraint string into the specific
   /// constraints and their prefixes.  If this returns an empty vector, and if
   /// the constraint string itself isn't empty, there was an error parsing.
-  static std::vector<ConstraintInfo> 
-    ParseConstraints(StringRef ConstraintString);
+  static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
   
   /// ParseConstraints - Parse the constraints of this inlineasm object, 
   /// returning them the same way that ParseConstraints(str) does.
-  std::vector<ConstraintInfo> 
-  ParseConstraints() const {
+  ConstraintInfoVector ParseConstraints() const {
     return ParseConstraints(Constraints);
   }
   
Index: include/llvm/CodeGen/Analysis.h
===================================================================
--- include/llvm/CodeGen/Analysis.h	(revision 117191)
+++ include/llvm/CodeGen/Analysis.h	(working copy)
@@ -52,7 +52,7 @@
 
 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
 /// processed uses a memory 'm' constraint.
-bool hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
+bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
                                const TargetLowering &TLI);
 
 /// getFCmpCondCode - Return the ISD condition code corresponding to
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp	(revision 117191)
+++ lib/Target/X86/X86ISelLowering.cpp	(working copy)
@@ -11423,7 +11423,7 @@
 
 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
   InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
-  std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
+  InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
 
   std::string AsmStr = IA->getAsmString();
 
@@ -11503,18 +11503,32 @@
 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
-    case 'A':
-      return C_Register;
-    case 'f':
-    case 'r':
     case 'R':
-    case 'l':
     case 'q':
     case 'Q':
+    case 'f':
+    case 't':
+    case 'u':
+    case 'y':
     case 'x':
-    case 'y':
     case 'Y':
       return C_RegisterClass;
+    case 'a':
+    case 'b':
+    case 'c':
+    case 'd':
+    case 'S':
+    case 'D':
+    case 'A':
+      return C_Register;
+    case 'I':
+    case 'J':
+    case 'K':
+    case 'L':
+    case 'M':
+    case 'N':
+    case 'G':
+    case 'C':
     case 'e':
     case 'Z':
       return C_Other;
@@ -11525,30 +11539,106 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
-/// Examine constraint type and operand type and determine a weight value,
-/// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
+/// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
 /// and the current alternative constraint selected.
-int X86TargetLowering::getSingleConstraintMatchWeight(
+TargetLowering::ConstraintWeight
+  X86TargetLowering::getSingleConstraintMatchWeight(
     AsmOperandInfo &info, const char *constraint) const {
-  int weight = -1;
+  ConstraintWeight weight = CW_Invalid;
   Value *CallOperandVal = info.CallOperandVal;
     // If we don't have a value, we can't do a match,
     // but allow it at the lowest weight.
   if (CallOperandVal == NULL)
-    return 0;
+    return CW_Default;
+  const Type *type = CallOperandVal->getType();
   // Look at the constraint type.
   switch (*constraint) {
   default:
-    return TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+  case 'R':
+  case 'q':
+  case 'Q':
+  case 'a':
+  case 'b':
+  case 'c':
+  case 'd':
+  case 'S':
+  case 'D':
+  case 'A':
+    if (CallOperandVal->getType()->isIntegerTy())
+      weight = CW_SpecificReg;
     break;
+  case 'f':
+  case 't':
+  case 'u':
+      if (type->isX86_FP80Ty())
+        weight = CW_SpecificReg;
+      break;
+  case 'y':
+      if (type->isX86_MMXTy())
+        weight = CW_SpecificReg;
+      break;
+  case 'x':
+  case 'Y':
+    if (type->isVectorTy() && type->isFloatingPointTy())
+      weight = CW_Register;
+    break;
   case 'I':
     if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
       if (C->getZExtValue() <= 31)
-        weight = 3;
+        weight = CW_Constant;
     }
     break;
-  // etc.
+  case 'J':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if (C->getZExtValue() <= 63)
+        weight = CW_Constant;
+    }
+    break;
+  case 'K':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
+        weight = CW_Constant;
+    }
+    break;
+  case 'L':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
+        weight = CW_Constant;
+    }
+    break;
+  case 'M':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if (C->getZExtValue() <= 3)
+        weight = CW_Constant;
+    }
+    break;
+  case 'N':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if (C->getZExtValue() <= 0xff)
+        weight = CW_Constant;
+    }
+    break;
+  case 'G':
+  case 'C':
+    if (dyn_cast<ConstantFP>(CallOperandVal)) {
+      weight = CW_Constant;
+    }
+    break;
+  case 'e':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if ((C->getSExtValue() >= -0x80000000LL) &&
+          (C->getSExtValue() <= 0x7fffffffLL))
+        weight = CW_Constant;
+    }
+    break;
+  case 'Z':
+    if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
+      if (C->getZExtValue() <= 0xffffffff)
+        weight = CW_Constant;
+    }
+    break;
   }
   return weight;
 }
Index: lib/Target/X86/X86ISelLowering.h
===================================================================
--- lib/Target/X86/X86ISelLowering.h	(revision 117191)
+++ lib/Target/X86/X86ISelLowering.h	(working copy)
@@ -542,10 +542,9 @@
 
     ConstraintType getConstraintType(const std::string &Constraint) const;
 
-    /// Examine constraint string and operand type and determine a weight value,
-    /// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
+    /// Examine constraint string and operand type and determine a weight value.
     /// The operand object must already have been set up with the operand type.
-    virtual int getSingleConstraintMatchWeight(
+    virtual ConstraintWeight getSingleConstraintMatchWeight(
       AsmOperandInfo &info, const char *constraint) const;
 
     std::vector<unsigned>
Index: lib/Target/CBackend/CBackend.cpp
===================================================================
--- lib/Target/CBackend/CBackend.cpp	(revision 117191)
+++ lib/Target/CBackend/CBackend.cpp	(working copy)
@@ -3193,7 +3193,7 @@
 //      handle communitivity
 void CWriter::visitInlineAsm(CallInst &CI) {
   InlineAsm* as = cast<InlineAsm>(CI.getCalledValue());
-  std::vector<InlineAsm::ConstraintInfo> Constraints = as->ParseConstraints();
+  InlineAsm::ConstraintInfoVector Constraints = as->ParseConstraints();
 
   std::vector<std::pair<Value*, int> > ResultVals;
   if (CI.getType() == Type::getVoidTy(CI.getContext()))
@@ -3213,7 +3213,7 @@
   bool IsFirst = true;
 
   // Convert over all the output constraints.
-  for (std::vector<InlineAsm::ConstraintInfo>::iterator I = Constraints.begin(),
+  for (InlineAsm::ConstraintInfoVector::iterator I = Constraints.begin(),
        E = Constraints.end(); I != E; ++I) {
 
     if (I->Type != InlineAsm::isOutput) {
@@ -3255,7 +3255,7 @@
   Out << "\n        :";
   IsFirst = true;
   ValueCount = 0;
-  for (std::vector<InlineAsm::ConstraintInfo>::iterator I = Constraints.begin(),
+  for (InlineAsm::ConstraintInfoVector::iterator I = Constraints.begin(),
        E = Constraints.end(); I != E; ++I) {
     if (I->Type != InlineAsm::isInput) {
       ++ValueCount;
@@ -3284,7 +3284,7 @@
 
   // Convert over the clobber constraints.
   IsFirst = true;
-  for (std::vector<InlineAsm::ConstraintInfo>::iterator I = Constraints.begin(),
+  for (InlineAsm::ConstraintInfoVector::iterator I = Constraints.begin(),
        E = Constraints.end(); I != E; ++I) {
     if (I->Type != InlineAsm::isClobber)
       continue;  // Ignore non-input constraints.
Index: lib/Target/CellSPU/SPUISelLowering.h
===================================================================
--- lib/Target/CellSPU/SPUISelLowering.h	(revision 117191)
+++ lib/Target/CellSPU/SPUISelLowering.h	(working copy)
@@ -129,6 +129,11 @@
 
     ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
 
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::pair<unsigned, const TargetRegisterClass*>
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    EVT VT) const;
Index: lib/Target/CellSPU/SPUISelLowering.cpp
===================================================================
--- lib/Target/CellSPU/SPUISelLowering.cpp	(revision 117191)
+++ lib/Target/CellSPU/SPUISelLowering.cpp	(working copy)
@@ -20,6 +20,7 @@
 #include "llvm/Function.h"
 #include "llvm/Intrinsics.h"
 #include "llvm/CallingConv.h"
+#include "llvm/Type.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -2989,6 +2990,38 @@
   return TargetLowering::getConstraintType(ConstraintLetter);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+SPUTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+    //FIXME: Seems like the supported constraint letters were just copied
+    // from PPC, as the following doesn't correspond to the GCC docs.
+    // I'm leaving it so until someone adds the corresponding lowering support.
+  case 'b':
+  case 'r':
+  case 'f':
+  case 'd':
+  case 'v':
+  case 'y':
+    weight = CW_Register;
+    break;
+  }
+  return weight;
+}
+
 std::pair<unsigned, const TargetRegisterClass*>
 SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 EVT VT) const
Index: lib/Target/MBlaze/MBlazeISelLowering.h
===================================================================
--- lib/Target/MBlaze/MBlazeISelLowering.h	(revision 117191)
+++ lib/Target/MBlaze/MBlazeISelLowering.h	(working copy)
@@ -153,6 +153,11 @@
     // Inline asm support
     ConstraintType getConstraintType(const std::string &Constraint) const;
 
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::pair<unsigned, const TargetRegisterClass*>
               getRegForInlineAsmConstraint(const std::string &Constraint,
               EVT VT) const;
Index: lib/Target/MBlaze/MBlazeISelLowering.cpp
===================================================================
--- lib/Target/MBlaze/MBlazeISelLowering.cpp	(revision 117191)
+++ lib/Target/MBlaze/MBlazeISelLowering.cpp	(working copy)
@@ -908,6 +908,37 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+MBlazeTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  const Type *type = CallOperandVal->getType();
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+  case 'd':     
+  case 'y': 
+    if (type->isIntegerTy())
+      weight = CW_Register;
+    break;
+  case 'f':
+    if (type->isFloatTy())
+      weight = CW_Register;
+    break;
+  }
+  return weight;
+}
+
 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
 /// return a list of registers that can be used to satisfy the constraint.
 /// This should only be used for C_RegisterClass constraints.
Index: lib/Target/ARM/ARMISelLowering.h
===================================================================
--- lib/Target/ARM/ARMISelLowering.h	(revision 117191)
+++ lib/Target/ARM/ARMISelLowering.h	(working copy)
@@ -241,6 +241,12 @@
 
 
     ConstraintType getConstraintType(const std::string &Constraint) const;
+
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::pair<unsigned, const TargetRegisterClass*>
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    EVT VT) const;
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp	(revision 117191)
+++ lib/Target/ARM/ARMISelLowering.cpp	(working copy)
@@ -5390,6 +5390,40 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+ARMTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  const Type *type = CallOperandVal->getType();
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+  case 'l':
+    if (type->isIntegerTy()) {
+      if (Subtarget->isThumb())
+        weight = CW_SpecificReg;
+      else
+        weight = CW_Register;
+    }
+    break;
+  case 'w':
+    if (type->isFloatingPointTy())
+      weight = CW_Register;
+    break;
+  }
+  return weight;
+}
+
 std::pair<unsigned, const TargetRegisterClass*>
 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 EVT VT) const {
Index: lib/Target/PowerPC/PPCISelLowering.h
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.h	(revision 117191)
+++ lib/Target/PowerPC/PPCISelLowering.h	(working copy)
@@ -308,6 +308,12 @@
                                             bool is8bit, unsigned Opcode) const;
     
     ConstraintType getConstraintType(const std::string &Constraint) const;
+
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::pair<unsigned, const TargetRegisterClass*> 
       getRegForInlineAsmConstraint(const std::string &Constraint,
                                    EVT VT) const;
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp	(revision 117191)
+++ lib/Target/PowerPC/PPCISelLowering.cpp	(working copy)
@@ -2473,13 +2473,13 @@
     // node so that legalize doesn't hack it.
     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
-					  Callee.getValueType());
+            Callee.getValueType());
       needIndirectCall = false;
     }
   }
   if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
       Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
-					   Callee.getValueType());
+             Callee.getValueType());
       needIndirectCall = false;
   }
   if (needIndirectCall) {
@@ -5374,6 +5374,51 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+PPCTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  const Type *type = CallOperandVal->getType();
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+  case 'b':
+    if (type->isIntegerTy())
+      weight = CW_Register;
+    break;
+  case 'r':
+    if (type->isIntegerTy())
+      weight = CW_Register;
+    break;
+  case 'f':
+    if (type->isFloatTy())
+      weight = CW_Register;
+    break;
+  case 'd':
+    if (type->isDoubleTy())
+      weight = CW_Register;
+    break;
+  case 'v':
+    if (type->isVectorTy())
+      weight = CW_Register;
+    break;
+  case 'y':
+    weight = CW_Register;
+    break;
+  }
+  return weight;
+}
+
 std::pair<unsigned, const TargetRegisterClass*>
 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 EVT VT) const {
Index: lib/Target/Alpha/AlphaISelLowering.h
===================================================================
--- lib/Target/Alpha/AlphaISelLowering.h	(revision 117191)
+++ lib/Target/Alpha/AlphaISelLowering.h	(working copy)
@@ -87,6 +87,11 @@
 
     ConstraintType getConstraintType(const std::string &Constraint) const;
 
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         EVT VT) const;
Index: lib/Target/Alpha/AlphaISelLowering.cpp
===================================================================
--- lib/Target/Alpha/AlphaISelLowering.cpp	(revision 117191)
+++ lib/Target/Alpha/AlphaISelLowering.cpp	(working copy)
@@ -27,6 +27,7 @@
 #include "llvm/Function.h"
 #include "llvm/Module.h"
 #include "llvm/Intrinsics.h"
+#include "llvm/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
@@ -803,6 +804,30 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+AlphaTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+  case 'f':
+    weight = CW_Register;
+    break;
+  }
+  return weight;
+}
+
 std::vector<unsigned> AlphaTargetLowering::
 getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                   EVT VT) const {
Index: lib/Target/Mips/MipsISelLowering.h
===================================================================
--- lib/Target/Mips/MipsISelLowering.h	(revision 117191)
+++ lib/Target/Mips/MipsISelLowering.h	(working copy)
@@ -139,6 +139,11 @@
     // Inline asm support
     ConstraintType getConstraintType(const std::string &Constraint) const;
 
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::pair<unsigned, const TargetRegisterClass*> 
               getRegForInlineAsmConstraint(const std::string &Constraint,
               EVT VT) const;
Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp	(revision 117191)
+++ lib/Target/Mips/MipsISelLowering.cpp	(working copy)
@@ -1269,6 +1269,37 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+MipsTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  const Type *type = CallOperandVal->getType();
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+  case 'd':     
+  case 'y': 
+    if (type->isIntegerTy())
+      weight = CW_Register;
+    break;
+  case 'f':
+    if (type->isFloatTy())
+      weight = CW_Register;
+    break;
+  }
+  return weight;
+}
+
 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
 /// return a list of registers that can be used to satisfy the constraint.
 /// This should only be used for C_RegisterClass constraints.
Index: lib/Target/Blackfin/BlackfinISelLowering.h
===================================================================
--- lib/Target/Blackfin/BlackfinISelLowering.h	(revision 117191)
+++ lib/Target/Blackfin/BlackfinISelLowering.h	(working copy)
@@ -39,6 +39,12 @@
                                     SelectionDAG &DAG) const;
 
     ConstraintType getConstraintType(const std::string &Constraint) const;
+
+    /// Examine constraint string and operand type and determine a weight value.
+    /// The operand object must already have been set up with the operand type.
+    ConstraintWeight getSingleConstraintMatchWeight(
+      AsmOperandInfo &info, const char *constraint) const;
+
     std::pair<unsigned, const TargetRegisterClass*>
     getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
     std::vector<unsigned>
Index: lib/Target/Blackfin/BlackfinISelLowering.cpp
===================================================================
--- lib/Target/Blackfin/BlackfinISelLowering.cpp	(revision 117191)
+++ lib/Target/Blackfin/BlackfinISelLowering.cpp	(working copy)
@@ -15,6 +15,7 @@
 #include "BlackfinISelLowering.h"
 #include "BlackfinTargetMachine.h"
 #include "llvm/Function.h"
+#include "llvm/Type.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -549,6 +550,52 @@
   return TargetLowering::getConstraintType(Constraint);
 }
 
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+BlackfinTargetLowering::getSingleConstraintMatchWeight(
+    AsmOperandInfo &info, const char *constraint) const {
+  ConstraintWeight weight = CW_Invalid;
+  Value *CallOperandVal = info.CallOperandVal;
+    // If we don't have a value, we can't do a match,
+    // but allow it at the lowest weight.
+  if (CallOperandVal == NULL)
+    return CW_Default;
+  // Look at the constraint type.
+  switch (*constraint) {
+  default:
+    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+    break;
+
+    // Blackfin-specific constraints
+  case 'a':
+  case 'd':
+  case 'z':
+  case 'D':
+  case 'W':
+  case 'e':
+  case 'b':
+  case 'v':
+  case 'f':
+  case 'c':
+  case 't':
+  case 'u':
+  case 'k':
+  case 'x':
+  case 'y':
+  case 'w':
+    return CW_Register;
+  case 'A':
+  case 'B':
+  case 'C':
+  case 'Z':
+  case 'Y':
+    return CW_SpecificReg;
+  }
+  return weight;
+}
+
 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
 /// constraint.
 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
Index: lib/VMCore/InlineAsm.cpp
===================================================================
--- lib/VMCore/InlineAsm.cpp	(revision 117191)
+++ lib/VMCore/InlineAsm.cpp	(working copy)
@@ -76,11 +76,11 @@
 /// fields in this structure.  If the constraint string is not understood,
 /// return true, otherwise return false.
 bool InlineAsm::ConstraintInfo::Parse(StringRef Str,
-                     std::vector<InlineAsm::ConstraintInfo> &ConstraintsSoFar) {
+                     InlineAsm::ConstraintInfoVector &ConstraintsSoFar) {
   StringRef::iterator I = Str.begin(), E = Str.end();
   unsigned multipleAlternativeCount = Str.count('|') + 1;
   unsigned multipleAlternativeIndex = 0;
-  std::vector<std::string> *pCodes = &Codes;
+  ConstraintCodeVector *pCodes = &Codes;
   
   // Initialize
   isMultipleAlternative = (multipleAlternativeCount > 1 ? true : false);
@@ -202,9 +202,9 @@
   }
 }
 
-std::vector<InlineAsm::ConstraintInfo>
+InlineAsm::ConstraintInfoVector
 InlineAsm::ParseConstraints(StringRef Constraints) {
-  std::vector<ConstraintInfo> Result;
+  ConstraintInfoVector Result;
   
   // Scan the constraints string.
   for (StringRef::iterator I = Constraints.begin(),
@@ -239,7 +239,7 @@
 bool InlineAsm::Verify(const FunctionType *Ty, StringRef ConstStr) {
   if (Ty->isVarArg()) return false;
   
-  std::vector<ConstraintInfo> Constraints = ParseConstraints(ConstStr);
+  ConstraintInfoVector Constraints = ParseConstraints(ConstStr);
   
   // Error parsing constraints.
   if (Constraints.empty() && !ConstStr.empty()) return false;
Index: lib/Transforms/Utils/AddrModeMatcher.cpp
===================================================================
--- lib/Transforms/Utils/AddrModeMatcher.cpp	(revision 117191)
+++ lib/Transforms/Utils/AddrModeMatcher.cpp	(working copy)
@@ -380,7 +380,7 @@
 /// return false.
 static bool IsOperandAMemoryOperand(CallInst *CI, InlineAsm *IA, Value *OpVal,
                                     const TargetLowering &TLI) {
-  std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI.ParseConstraints(ImmutableCallSite(CI));
+  TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(ImmutableCallSite(CI));
   for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
     TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
     
Index: lib/Transforms/Scalar/CodeGenPrepare.cpp
===================================================================
--- lib/Transforms/Scalar/CodeGenPrepare.cpp	(revision 117191)
+++ lib/Transforms/Scalar/CodeGenPrepare.cpp	(working copy)
@@ -743,7 +743,7 @@
                                            DenseMap<Value*,Value*> &SunkAddrs) {
   bool MadeChange = false;
 
-  std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI->ParseConstraints(CS);
+  TargetLowering::AsmOperandInfoVector TargetConstraints = TLI->ParseConstraints(CS);
   unsigned ArgNo = 0;
   for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
     TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	(revision 117191)
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	(working copy)
@@ -5210,6 +5210,8 @@
   }
 };
 
+typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
+
 } // end llvm namespace.
 
 /// isAllocatableRegister - If the specified register is safe to allocate,
@@ -5447,11 +5449,11 @@
   const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
 
   /// ConstraintOperands - Information about all of the constraints.
-  std::vector<SDISelAsmOperandInfo> ConstraintOperands;
+  SDISelAsmOperandInfoVector ConstraintOperands;
 
   std::set<unsigned> OutputRegs, InputRegs;
 
-  std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI.ParseConstraints(CS);
+  TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
   bool hasMemory = false;
 
   unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp	(revision 117191)
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp	(working copy)
@@ -2664,16 +2664,16 @@
 /// and also tie in the associated operand values.
 /// If this returns an empty vector, and if the constraint string itself
 /// isn't empty, there was an error parsing.
-std::vector<TargetLowering::AsmOperandInfo> TargetLowering::ParseConstraints(
+TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
     ImmutableCallSite CS) const {
   /// ConstraintOperands - Information about all of the constraints.
-  std::vector<AsmOperandInfo> ConstraintOperands;
+  AsmOperandInfoVector ConstraintOperands;
   const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
   unsigned maCount = 0; // Largest number of multiple alternative constraints.
 
   // Do a prepass over the constraints, canonicalizing them, and building up the
   // ConstraintOperands list.
-  std::vector<InlineAsm::ConstraintInfo>
+  InlineAsm::ConstraintInfoVector
     ConstraintInfos = IA->ParseConstraints();
     
   unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
@@ -2687,7 +2687,7 @@
     if (OpInfo.multipleAlternatives.size() > maCount)
       maCount = OpInfo.multipleAlternatives.size();
 
-    EVT OpVT = MVT::Other;
+    OpInfo.ConstraintVT = MVT::Other;
 
     // Compute the value type for each operand.
     switch (OpInfo.Type) {
@@ -2703,10 +2703,10 @@
       assert(!CS.getType()->isVoidTy() &&
              "Bad inline asm!");
       if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
-        OpVT = getValueType(STy->getElementType(ResNo));
+        OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
       } else {
         assert(ResNo == 0 && "Asm only has one result!");
-        OpVT = getValueType(CS.getType());
+        OpInfo.ConstraintVT = getValueType(CS.getType());
       }
       ++ResNo;
       break;
@@ -2717,6 +2717,36 @@
       // Nothing to do.
       break;
     }
+    
+    if (OpInfo.CallOperandVal) {
+      const llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
+      if (OpInfo.isIndirect) {
+        const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
+        if (!PtrTy)
+          report_fatal_error("Indirect operand for inline asm not a pointer!");
+        OpTy = PtrTy->getElementType();
+      }
+      // If OpTy is not a single value, it may be a struct/union that we
+      // can tile with integers.
+      if (!OpTy->isSingleValueType() && OpTy->isSized()) {
+        unsigned BitSize = TD->getTypeSizeInBits(OpTy);
+        switch (BitSize) {
+        default: break;
+        case 1:
+        case 8:
+        case 16:
+        case 32:
+        case 64:
+        case 128:
+          OpTy = IntegerType::get(OpTy->getContext(), BitSize);
+          break;
+        }
+      } else if (dyn_cast<PointerType>(OpTy)) {
+        OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
+      } else {
+        OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
+      }
+    }
   }
 
   // If we have multiple alternative constraints, select the best alternative.
@@ -2737,13 +2767,12 @@
           if (OpInfo.Type == InlineAsm::isClobber)
             continue;
 
-          // If this is an output operand with a matching input operand, look up the
-          // matching input. If their types mismatch, e.g. one is an integer, the
-          // other is floating point, or their sizes are different, flag it as an
-          // maCantMatch.
+          // If this is an output operand with a matching input operand,
+          // look up the matching input. If their types mismatch, e.g. one
+          // is an integer, the other is floating point, or their sizes are
+          // different, flag it as an maCantMatch.
           if (OpInfo.hasMatchingInput()) {
             AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
-            
             if (OpInfo.ConstraintVT != Input.ConstraintVT) {
               if ((OpInfo.ConstraintVT.isInteger() !=
                    Input.ConstraintVT.isInteger()) ||
@@ -2752,10 +2781,8 @@
                 weightSum = -1;  // Can't match.
                 break;
               }
-              Input.ConstraintVT = OpInfo.ConstraintVT;
             }
           }
-          
           weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
           if (weight == -1) {
             weightSum = -1;
@@ -2792,7 +2819,7 @@
     // error.
     if (OpInfo.hasMatchingInput()) {
       AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
-      
+
       if (OpInfo.ConstraintVT != Input.ConstraintVT) {
         if ((OpInfo.ConstraintVT.isInteger() !=
              Input.ConstraintVT.isInteger()) ||
@@ -2802,8 +2829,8 @@
                              " with a matching output constraint of"
                              " incompatible type!");
         }
-        Input.ConstraintVT = OpInfo.ConstraintVT;
       }
+
     }
   }
 
@@ -2828,22 +2855,23 @@
   }
 }
 
-/// Examine constraint type and operand type and determine a weight value,
-/// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
+/// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
 /// and the current alternative constraint selected.
-int TargetLowering::getMultipleConstraintMatchWeight(
+TargetLowering::ConstraintWeight
+  TargetLowering::getMultipleConstraintMatchWeight(
     AsmOperandInfo &info, int maIndex) const {
-  std::vector<std::string> *rCodes;
+  InlineAsm::ConstraintCodeVector *rCodes;
   if (maIndex >= (int)info.multipleAlternatives.size())
     rCodes = &info.Codes;
   else
     rCodes = &info.multipleAlternatives[maIndex].Codes;
-  int BestWeight = -1;
+  ConstraintWeight BestWeight = CW_Invalid;
 
   // Loop over the options, keeping track of the most general one.
   for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
-    int weight = getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
+    ConstraintWeight weight =
+      getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
     if (weight > BestWeight)
       BestWeight = weight;
   }
@@ -2851,50 +2879,50 @@
   return BestWeight;
 }
 
-/// Examine constraint type and operand type and determine a weight value,
-/// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
+/// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
 /// and the current alternative constraint selected.
-int TargetLowering::getSingleConstraintMatchWeight(
+TargetLowering::ConstraintWeight
+  TargetLowering::getSingleConstraintMatchWeight(
     AsmOperandInfo &info, const char *constraint) const {
-  int weight = -1;
+  ConstraintWeight weight = CW_Invalid;
   Value *CallOperandVal = info.CallOperandVal;
     // If we don't have a value, we can't do a match,
     // but allow it at the lowest weight.
   if (CallOperandVal == NULL)
-    return 0;
+    return CW_Default;
   // Look at the constraint type.
   switch (*constraint) {
     case 'i': // immediate integer.
     case 'n': // immediate integer with a known value.
-      weight = 0;
-      if (info.CallOperandVal) {
-        if (isa<ConstantInt>(info.CallOperandVal))
-          weight = 3;
-        else
-          weight = -1;
-      }
+      if (isa<ConstantInt>(CallOperandVal))
+        weight = CW_Constant;
       break;
     case 's': // non-explicit intregal immediate.
-      weight = 0;
-      if (info.CallOperandVal) {
-        if (isa<GlobalValue>(info.CallOperandVal))
-          weight = 3;
-        else
-          weight = -1;
-      }
+      if (isa<GlobalValue>(CallOperandVal))
+        weight = CW_Constant;
       break;
+    case 'E': // immediate float if host format.
+    case 'F': // immediate float.
+      if (isa<ConstantFP>(CallOperandVal))
+        weight = CW_Constant;
+      break;
+    case '<': // memory operand with autodecrement.
+    case '>': // memory operand with autoincrement.
     case 'm': // memory operand.
     case 'o': // offsettable memory operand
     case 'V': // non-offsettable memory operand
-      weight = 2;
+      weight = CW_Memory;
       break;
+    case 'r': // general register.
     case 'g': // general register, memory operand or immediate integer.
+              // note: Clang converts "g" to "imr".
+      if (CallOperandVal->getType()->isIntegerTy())
+        weight = CW_Register;
+      break;
     case 'X': // any operand.
-      weight = 1;
-      break;
     default:
-      weight = 0;
+      weight = CW_Default;
       break;
   }
   return weight;
Index: lib/CodeGen/Analysis.cpp
===================================================================
--- lib/CodeGen/Analysis.cpp	(revision 117191)
+++ lib/CodeGen/Analysis.cpp	(working copy)
@@ -125,7 +125,7 @@
 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
 /// processed uses a memory 'm' constraint.
 bool
-llvm::hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
+llvm::hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
                                 const TargetLowering &TLI) {
   for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
     InlineAsm::ConstraintInfo &CI = CInfos[i];

From bigcheesegs at gmail.com  Mon Oct 25 14:02:18 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Mon, 25 Oct 2010 15:02:18 -0400
Subject: [llvm-commits] [llvm] r117267 - /llvm/trunk/docs/LangRef.html
In-Reply-To: <20101025162904.0D58D2A6C12D@llvm.org>
References: <20101025162904.0D58D2A6C12D@llvm.org>
Message-ID: <AANLkTimwMUa6Z6qXgbZXgo8LAM0A5e_tMu8aUwzKpkTe@mail.gmail.com>

On Mon, Oct 25, 2010 at 12:29 PM, Charles Davis <cdavis at mines.edu> wrote:
> Author: cdavis
> Date: Mon Oct 25 11:29:03 2010
> New Revision: 117267
>
> URL: http://llvm.org/viewvc/llvm-project?rev=117267&view=rev
> Log:
> Make hotpatch attribute description a little less Wintel-specific.
>
> Modified:
> ? ?llvm/trunk/docs/LangRef.html
>
> Modified: llvm/trunk/docs/LangRef.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=117267&r1=117266&r2=117267&view=diff
> ==============================================================================
> --- llvm/trunk/docs/LangRef.html (original)
> +++ llvm/trunk/docs/LangRef.html Mon Oct 25 11:29:03 2010
> @@ -1132,9 +1132,11 @@
> ? ? ? threshold for this caller.</dd>
>
> ? <dt><tt><b>hotpatch</b></tt></dt>
> - ?<dd>This attribute indicates that the prologue should contain a 'hotpatch'
> - ? ? ?sequence at the beginning. This is the same sequence used in the
> - ? ? ?system DLLs in Microsoft Windows XP Service Pack 2 and higher.</dd>
> + ?<dd>This attribute indicates that the function should be 'hotpatchable',
> + ? ? ?meaning the function can be patched even while it is loaded into memory.
> + ? ? ?On x86, the function prologue will contain a two-byte no-op sequence;
> + ? ? ?this is the same sequence used in the system DLLs in Microsoft Windows
> + ? ? ?XP Service Pack 2 and higher.</dd>
>
> ? <dt><tt><b>inlinehint</b></tt></dt>
> ? <dd>This attribute indicates that the source code contained a hint that inlining

The constraint is not a two byte no-op. The constraint is actually
that there be an instruction that is 2 bytes or larger. See
http://blogs.msdn.com/b/freik/archive/2006/03/07/x64-hotpatchability.aspx

- Michael Spencer


From cdavis at mines.edu  Mon Oct 25 14:07:39 2010
From: cdavis at mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 19:07:39 -0000
Subject: [llvm-commits] [llvm] r117286 - /llvm/trunk/docs/LangRef.html
Message-ID: <20101025190739.AEA442A6C12D@llvm.org>

Author: cdavis
Date: Mon Oct 25 14:07:39 2010
New Revision: 117286

URL: http://llvm.org/viewvc/llvm-project?rev=117286&view=rev
Log:
Make the description of the hotpatch attribute even more generic. Spotted by
Michael Spencer.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=117286&r1=117285&r2=117286&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Oct 25 14:07:39 2010
@@ -1133,10 +1133,11 @@
 
   <dt><tt><b>hotpatch</b></tt></dt>
   <dd>This attribute indicates that the function should be 'hotpatchable',
-      meaning the function can be patched even while it is loaded into memory.
-      On x86, the function prologue will contain a two-byte no-op sequence;
-      this is the same sequence used in the system DLLs in Microsoft Windows
-      XP Service Pack 2 and higher.</dd>
+      meaning the function can be patched and/or hooked even while it is
+      loaded into memory. On x86, the function prologue will be preceded
+      by six bytes of padding and will begin with a two-byte instruction.
+      Most of the functions in the Windows system DLLs in Windows XP SP2 or
+      higher were compiled in this fashion.</dd>
 
   <dt><tt><b>inlinehint</b></tt></dt>
   <dd>This attribute indicates that the source code contained a hint that inlining



From cdavis at mymail.mines.edu  Mon Oct 25 14:09:48 2010
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 25 Oct 2010 13:09:48 -0600
Subject: [llvm-commits] [llvm] r117267 - /llvm/trunk/docs/LangRef.html
In-Reply-To: <AANLkTimwMUa6Z6qXgbZXgo8LAM0A5e_tMu8aUwzKpkTe@mail.gmail.com>
References: <20101025162904.0D58D2A6C12D@llvm.org>
	<AANLkTimwMUa6Z6qXgbZXgo8LAM0A5e_tMu8aUwzKpkTe@mail.gmail.com>
Message-ID: <4CC5D5FC.5030001@mymail.mines.edu>

On 10/25/10 1:02 PM, Michael Spencer wrote:
> On Mon, Oct 25, 2010 at 12:29 PM, Charles Davis <cdavis at mines.edu> wrote:
>> Author: cdavis
>> Date: Mon Oct 25 11:29:03 2010
>> New Revision: 117267
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=117267&view=rev
>> Log:
>> Make hotpatch attribute description a little less Wintel-specific.
>>
>> Modified:
>>    llvm/trunk/docs/LangRef.html
>>
>> Modified: llvm/trunk/docs/LangRef.html
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=117267&r1=117266&r2=117267&view=diff
>> ==============================================================================
>> --- llvm/trunk/docs/LangRef.html (original)
>> +++ llvm/trunk/docs/LangRef.html Mon Oct 25 11:29:03 2010
>> @@ -1132,9 +1132,11 @@
>>       threshold for this caller.</dd>
>>
>>   <dt><tt><b>hotpatch</b></tt></dt>
>> -  <dd>This attribute indicates that the prologue should contain a 'hotpatch'
>> -      sequence at the beginning. This is the same sequence used in the
>> -      system DLLs in Microsoft Windows XP Service Pack 2 and higher.</dd>
>> +  <dd>This attribute indicates that the function should be 'hotpatchable',
>> +      meaning the function can be patched even while it is loaded into memory.
>> +      On x86, the function prologue will contain a two-byte no-op sequence;
>> +      this is the same sequence used in the system DLLs in Microsoft Windows
>> +      XP Service Pack 2 and higher.</dd>
>>
>>   <dt><tt><b>inlinehint</b></tt></dt>
>>   <dd>This attribute indicates that the source code contained a hint that inlining
> 
> The constraint is not a two byte no-op. The constraint is actually
> that there be an instruction that is 2 bytes or larger. See
> http://blogs.msdn.com/b/freik/archive/2006/03/07/x64-hotpatchability.aspx
Fixed in r117286.

Chip

From gohman at apple.com  Mon Oct 25 14:47:25 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 19:47:25 -0000
Subject: [llvm-commits] [llvm] r117288 -
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
Message-ID: <20101025194725.7B8C92A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 14:47:25 2010
New Revision: 117288

URL: http://llvm.org/viewvc/llvm-project?rev=117288&view=rev
Log:
Add a comment.

Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=117288&r1=117287&r2=117288&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Mon Oct 25 14:47:25 2010
@@ -31,7 +31,9 @@
 //
 // The second field identifies the type's parent node in the tree, or
 // is null or omitted for a root node. A type is considered to alias
-// all of its decendents and all of its ancestors in the tree.
+// all of its decendents and all of its ancestors in the tree. Also,
+// a type is considered to alias all types in other trees, so that
+// bitcode produced from multiple front-ends is handled conservatively.
 //
 // If the third field is present, it's an integer which if equal to 1
 // indicates that the type is "constant" (meaning pointsToConstantMemory



From rafael.espindola at gmail.com  Mon Oct 25 14:53:20 2010
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Mon, 25 Oct 2010 15:53:20 -0400
Subject: [llvm-commits] [patch] Add relaxations for arithmetic
	instructions
In-Reply-To: <AANLkTi=096=q1Vq9TMQxpWnRSrwpcZfScxAKcDe3oWoV@mail.gmail.com>
References: <AANLkTi=096=q1Vq9TMQxpWnRSrwpcZfScxAKcDe3oWoV@mail.gmail.com>
Message-ID: <AANLkTikuCBTNZWNO3CB7uC7_VBWu=03oWGTzAJX_Z94p@mail.gmail.com>

Updated patch with a test is attached.

Cheers,
Rafael
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From grosbach at apple.com  Mon Oct 25 15:00:01 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 25 Oct 2010 20:00:01 -0000
Subject: [llvm-commits] [llvm] r117291 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrThumb2.td InstPrinter/ARMInstPrinter.cpp
 InstPrinter/ARMInstPrinter.h
Message-ID: <20101025200001.BEB8A2A6C12C@llvm.org>

Author: grosbach
Date: Mon Oct 25 15:00:01 2010
New Revision: 117291

URL: http://llvm.org/viewvc/llvm-project?rev=117291&view=rev
Log:
imm12 operands aren't Thumb2 only, so rename the printer helper function.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=117291&r1=117290&r2=117291&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 25 15:00:01 2010
@@ -128,7 +128,7 @@
 // t2addrmode_imm12  := reg + imm12
 def t2addrmode_imm12 : Operand<i32>,
                        ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
-  let PrintMethod = "printT2AddrModeImm12Operand";
+  let PrintMethod = "printAddrModeImm12Operand";
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=117291&r1=117290&r2=117291&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Oct 25 15:00:01 2010
@@ -600,9 +600,8 @@
     O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
 }
 
-void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
-                                                 unsigned OpNum,
-                                                 raw_ostream &O) {
+void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
+                                               raw_ostream &O) {
   const MCOperand &MO1 = MI->getOperand(OpNum);
   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=117291&r1=117290&r2=117291&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Oct 25 15:00:01 2010
@@ -74,8 +74,8 @@
                                    raw_ostream &O);
 
   void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
-                                   raw_ostream &O);
+  void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
+                                 raw_ostream &O);
   void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum,
                                   raw_ostream &O);
   void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum,



From resistor at mac.com  Mon Oct 25 15:13:13 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 20:13:13 -0000
Subject: [llvm-commits] [llvm] r117293 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-bitwise-encoding.ll
Message-ID: <20101025201313.C2EF72A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 15:13:13 2010
New Revision: 117293

URL: http://llvm.org/viewvc/llvm-project?rev=117293&view=rev
Log:
Provide correct NEON encodings for vbsl.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117293&r1=117292&r2=117293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 15:13:13 2010
@@ -2934,20 +2934,20 @@
 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
 
 //   VBSL     : Vector Bitwise Select
-def  VBSLd    : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
-                     (ins DPR:$src1, DPR:$src2, DPR:$src3),
+def  VBSLd    : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
+                     (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
                      N3RegFrm, IIC_VCNTiD,
-                     "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
-                     [(set DPR:$dst,
-                       (v2i32 (or (and DPR:$src2, DPR:$src1),
-                                  (and DPR:$src3, (vnotd DPR:$src1)))))]>;
-def  VBSLq    : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
-                     (ins QPR:$src1, QPR:$src2, QPR:$src3),
+                     "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
+                     [(set DPR:$Vd,
+                       (v2i32 (or (and DPR:$Vn, DPR:$src1),
+                                  (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
+def  VBSLq    : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
+                     (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
                      N3RegFrm, IIC_VCNTiQ,
-                     "vbsl", "$dst, $src2, $src3", "$src1 = $dst",
-                     [(set QPR:$dst,
-                       (v4i32 (or (and QPR:$src2, QPR:$src1),
-                                  (and QPR:$src3, (vnotq QPR:$src1)))))]>;
+                     "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
+                     [(set QPR:$Vd,
+                       (v4i32 (or (and QPR:$Vn, QPR:$src1),
+                                  (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
 
 //   VBIF     : Vector Bitwise Insert if False
 //              like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117293&r1=117292&r2=117293&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Mon Oct 25 15:13:13 2010
@@ -113,3 +113,29 @@
 	%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
 	ret <16 x i8> %tmp2
 }
+
+; CHECK: vbsl_8xi8
+define <8 x i8> @vbsl_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+; CHECK: vbsl	d18, d17, d16           @ encoding: [0xb0,0x21,0x51,0xf3]
+	%tmp4 = and <8 x i8> %tmp1, %tmp2
+	%tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp6 = and <8 x i8> %tmp5, %tmp3
+	%tmp7 = or <8 x i8> %tmp4, %tmp6
+	ret <8 x i8> %tmp7
+}
+
+; CHECK: vbsl_16xi8
+define <16 x i8> @vbsl_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+	%tmp3 = load <16 x i8>* %C
+; CHECK: vbsl	q8, q10, q9             @ encoding: [0xf2,0x01,0x54,0xf3]
+	%tmp4 = and <16 x i8> %tmp1, %tmp2
+	%tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp6 = and <16 x i8> %tmp5, %tmp3
+	%tmp7 = or <16 x i8> %tmp4, %tmp6
+	ret <16 x i8> %tmp7
+}
\ No newline at end of file



From resistor at mac.com  Mon Oct 25 15:17:22 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 20:17:22 -0000
Subject: [llvm-commits] [llvm] r117294 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-bitwise-encoding.ll
Message-ID: <20101025201722.66D832A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 15:17:22 2010
New Revision: 117294

URL: http://llvm.org/viewvc/llvm-project?rev=117294&view=rev
Log:
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117294&r1=117293&r2=117294&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 15:17:22 2010
@@ -2951,28 +2951,30 @@
 
 //   VBIF     : Vector Bitwise Insert if False
 //              like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def  VBIFd    : N3VX<1, 0, 0b11, 0b0001, 0, 1,
-                     (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
+                     (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
                      N3RegFrm, IIC_VBINiD,
-                     "vbif", "$dst, $src2, $src3", "$src1 = $dst",
+                     "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      [/* For disassembly only; pattern left blank */]>;
 def  VBIFq    : N3VX<1, 0, 0b11, 0b0001, 1, 1,
-                     (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
+                     (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
                      N3RegFrm, IIC_VBINiQ,
-                     "vbif", "$dst, $src2, $src3", "$src1 = $dst",
+                     "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      [/* For disassembly only; pattern left blank */]>;
 
 //   VBIT     : Vector Bitwise Insert if True
 //              like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def  VBITd    : N3VX<1, 0, 0b10, 0b0001, 0, 1,
-                     (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
+                     (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
                      N3RegFrm, IIC_VBINiD,
-                     "vbit", "$dst, $src2, $src3", "$src1 = $dst",
+                     "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      [/* For disassembly only; pattern left blank */]>;
 def  VBITq    : N3VX<1, 0, 0b10, 0b0001, 1, 1,
-                     (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
+                     (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
                      N3RegFrm, IIC_VBINiQ,
-                     "vbit", "$dst, $src2, $src3", "$src1 = $dst",
+                     "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
                      [/* For disassembly only; pattern left blank */]>;
 
 // VBIT/VBIF are not yet implemented.  The TwoAddress pass will not go looking

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117294&r1=117293&r2=117294&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Mon Oct 25 15:17:22 2010
@@ -3,6 +3,7 @@
 ; FIXME: The following instructions still require testing:
 ;  - vand with immediate
 ;  - vmvn of an immediate
+;  - both vbit and vbif
 
 ; CHECK: vand_8xi8
 define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -138,4 +139,4 @@
 	%tmp6 = and <16 x i8> %tmp5, %tmp3
 	%tmp7 = or <16 x i8> %tmp4, %tmp6
 	ret <16 x i8> %tmp7
-}
\ No newline at end of file
+}



From daniel at zuster.org  Mon Oct 25 15:18:41 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 25 Oct 2010 20:18:41 -0000
Subject: [llvm-commits] [llvm] r117295 -
	/llvm/trunk/test/MC/AsmParser/exprs.s
Message-ID: <20101025201841.7AFBE2A6C12C@llvm.org>

Author: ddunbar
Date: Mon Oct 25 15:18:41 2010
New Revision: 117295

URL: http://llvm.org/viewvc/llvm-project?rev=117295&view=rev
Log:
MC/AsmParser: Rewrite test to actually check some parts of expression parsing,
now that we have macros and friends. Uncovered a bug in macro expansion...

Modified:
    llvm/trunk/test/MC/AsmParser/exprs.s

Modified: llvm/trunk/test/MC/AsmParser/exprs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/exprs.s?rev=117295&r1=117294&r2=117295&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/exprs.s (original)
+++ llvm/trunk/test/MC/AsmParser/exprs.s Mon Oct 25 15:18:41 2010
@@ -1,47 +1,52 @@
-// FIXME: For now this test just checks that llvm-mc -triple i386-unknown-unknown works. Once we have .macro,
-// .if, and .abort we can write a better test (without resorting to miles of
-// greps).
-        
 // RUN: llvm-mc -triple i386-unknown-unknown %s > %t
 
+.macro check_expr
+  .if ($0) != ($1)
+        .abort Unexpected $0 != $1.
+  .endif
+.endmacro
+        
         .text
 g:
 h:
 j:
 k:      
         .data
-        .byte !1 + 2
-        .byte !0
-        .byte ~0
-        .byte -1
-        .byte +1
-        .byte 1 + 2
-        .byte 1 & 3
+        check_expr !1 + 2, 2
+        check_expr !0, 1
+        check_expr ~0 & 0xFF, 0xFF
+        check_expr -1 & 0xFF, 0xFF
+        check_expr +1, 1
+        check_expr 1 + 2, 3
+        check_expr 1 & 3, 1
+        // FIXME: There is a bug here in macro expansion.
         .byte 4 / 2
         .byte 4 / -2
-        .byte 1 == 1
-        .byte 1 == 0
-        .byte 1 > 0
-        .byte 1 >= 1
-        .byte 1 < 2
-        .byte 1 <= 1
-        .byte 4 % 3
-        .byte 2 * 2
-        .byte 2 != 2
-        .byte 2 <> 2
-        .byte 1 | 2
-        .byte 1 << 1
-        .byte 2 >> 1
-        .byte ~0 >> 1
-        .byte 3 - 2
-        .byte 1 ^ 3
-        .byte 1 && 2
-        .byte 3 && 0
-        .byte 1 || 2
-        .byte 0 || 0
+        check_expr 1 == 1, 1
+        check_expr 1 == 0, 0
+        check_expr 1 > 0, 1
+        check_expr 1 >= 1, 1
+        check_expr 1 < 2, 1
+        check_expr 1 <= 1, 1
+        check_expr 4 % 3, 1
+        check_expr 2 * 2, 4
+        check_expr 2 != 2, 0
+        check_expr 2 <> 2, 0
+        check_expr 1 | 2, 3
+        check_expr 1 << 1, 2
+        check_expr 2 >> 1, 1
+        check_expr (~0 >> 1) & 0xFF, 0xFF
+        check_expr 3 - 2, 1
+        check_expr 1 ^ 3, 2
+        check_expr 1 && 2, 1
+        check_expr 3 && 0, 0
+        check_expr 0 && 1, 0
+        check_expr 1 || 2, 1
+        check_expr 0 || 1, 1
+        check_expr 0 || 0, 0
 
         .set c, 10
-        .byte c + 1
+        check_expr c + 1, 11
 
         d = e + 10
         .long d



From daniel at zuster.org  Mon Oct 25 15:18:47 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 25 Oct 2010 20:18:47 -0000
Subject: [llvm-commits] [llvm] r117296 -
	/llvm/trunk/tools/llvm-mc/llvm-mc.cpp
Message-ID: <20101025201847.1B58D2A6C12D@llvm.org>

Author: ddunbar
Date: Mon Oct 25 15:18:46 2010
New Revision: 117296

URL: http://llvm.org/viewvc/llvm-project?rev=117296&view=rev
Log:
llvm-mc: Teach -as-lex to print the raw token string as well.

Modified:
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=117296&r1=117295&r2=117296&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Oct 25 15:18:46 2010
@@ -194,7 +194,9 @@
 
   bool Error = false;
   while (Lexer.Lex().isNot(AsmToken::Eof)) {
-    switch (Lexer.getKind()) {
+    AsmToken Tok = Lexer.getTok();
+
+    switch (Tok.getKind()) {
     default:
       SrcMgr.PrintMessage(Lexer.getLoc(), "unknown token", "warning");
       Error = true;
@@ -203,58 +205,63 @@
       Error = true; // error already printed.
       break;
     case AsmToken::Identifier:
-      Out->os() << "identifier: " << Lexer.getTok().getString() << '\n';
+      Out->os() << "identifier: " << Lexer.getTok().getString();
       break;
     case AsmToken::Integer:
-      Out->os() << "int: " << Lexer.getTok().getString() << '\n';
+      Out->os() << "int: " << Lexer.getTok().getString();
       break;
     case AsmToken::Real:
-      Out->os() << "real: " << Lexer.getTok().getString() << '\n';
+      Out->os() << "real: " << Lexer.getTok().getString();
       break;
     case AsmToken::Register:
-      Out->os() << "register: " << Lexer.getTok().getRegVal() << '\n';
+      Out->os() << "register: " << Lexer.getTok().getRegVal();
       break;
     case AsmToken::String:
-      Out->os() << "string: " << Lexer.getTok().getString() << '\n';
+      Out->os() << "string: " << Lexer.getTok().getString();
       break;
 
-    case AsmToken::Amp:            Out->os() << "Amp\n"; break;
-    case AsmToken::AmpAmp:         Out->os() << "AmpAmp\n"; break;
-    case AsmToken::At:             Out->os() << "At\n"; break;
-    case AsmToken::Caret:          Out->os() << "Caret\n"; break;
-    case AsmToken::Colon:          Out->os() << "Colon\n"; break;
-    case AsmToken::Comma:          Out->os() << "Comma\n"; break;
-    case AsmToken::Dollar:         Out->os() << "Dollar\n"; break;
-    case AsmToken::Dot:            Out->os() << "Dot\n"; break;
-    case AsmToken::EndOfStatement: Out->os() << "EndOfStatement\n"; break;
-    case AsmToken::Eof:            Out->os() << "Eof\n"; break;
-    case AsmToken::Equal:          Out->os() << "Equal\n"; break;
-    case AsmToken::EqualEqual:     Out->os() << "EqualEqual\n"; break;
-    case AsmToken::Exclaim:        Out->os() << "Exclaim\n"; break;
-    case AsmToken::ExclaimEqual:   Out->os() << "ExclaimEqual\n"; break;
-    case AsmToken::Greater:        Out->os() << "Greater\n"; break;
-    case AsmToken::GreaterEqual:   Out->os() << "GreaterEqual\n"; break;
-    case AsmToken::GreaterGreater: Out->os() << "GreaterGreater\n"; break;
-    case AsmToken::Hash:           Out->os() << "Hash\n"; break;
-    case AsmToken::LBrac:          Out->os() << "LBrac\n"; break;
-    case AsmToken::LCurly:         Out->os() << "LCurly\n"; break;
-    case AsmToken::LParen:         Out->os() << "LParen\n"; break;
-    case AsmToken::Less:           Out->os() << "Less\n"; break;
-    case AsmToken::LessEqual:      Out->os() << "LessEqual\n"; break;
-    case AsmToken::LessGreater:    Out->os() << "LessGreater\n"; break;
-    case AsmToken::LessLess:       Out->os() << "LessLess\n"; break;
-    case AsmToken::Minus:          Out->os() << "Minus\n"; break;
-    case AsmToken::Percent:        Out->os() << "Percent\n"; break;
-    case AsmToken::Pipe:           Out->os() << "Pipe\n"; break;
-    case AsmToken::PipePipe:       Out->os() << "PipePipe\n"; break;
-    case AsmToken::Plus:           Out->os() << "Plus\n"; break;
-    case AsmToken::RBrac:          Out->os() << "RBrac\n"; break;
-    case AsmToken::RCurly:         Out->os() << "RCurly\n"; break;
-    case AsmToken::RParen:         Out->os() << "RParen\n"; break;
-    case AsmToken::Slash:          Out->os() << "Slash\n"; break;
-    case AsmToken::Star:           Out->os() << "Star\n"; break;
-    case AsmToken::Tilde:          Out->os() << "Tilde\n"; break;
+    case AsmToken::Amp:            Out->os() << "Amp"; break;
+    case AsmToken::AmpAmp:         Out->os() << "AmpAmp"; break;
+    case AsmToken::At:             Out->os() << "At"; break;
+    case AsmToken::Caret:          Out->os() << "Caret"; break;
+    case AsmToken::Colon:          Out->os() << "Colon"; break;
+    case AsmToken::Comma:          Out->os() << "Comma"; break;
+    case AsmToken::Dollar:         Out->os() << "Dollar"; break;
+    case AsmToken::Dot:            Out->os() << "Dot"; break;
+    case AsmToken::EndOfStatement: Out->os() << "EndOfStatement"; break;
+    case AsmToken::Eof:            Out->os() << "Eof"; break;
+    case AsmToken::Equal:          Out->os() << "Equal"; break;
+    case AsmToken::EqualEqual:     Out->os() << "EqualEqual"; break;
+    case AsmToken::Exclaim:        Out->os() << "Exclaim"; break;
+    case AsmToken::ExclaimEqual:   Out->os() << "ExclaimEqual"; break;
+    case AsmToken::Greater:        Out->os() << "Greater"; break;
+    case AsmToken::GreaterEqual:   Out->os() << "GreaterEqual"; break;
+    case AsmToken::GreaterGreater: Out->os() << "GreaterGreater"; break;
+    case AsmToken::Hash:           Out->os() << "Hash"; break;
+    case AsmToken::LBrac:          Out->os() << "LBrac"; break;
+    case AsmToken::LCurly:         Out->os() << "LCurly"; break;
+    case AsmToken::LParen:         Out->os() << "LParen"; break;
+    case AsmToken::Less:           Out->os() << "Less"; break;
+    case AsmToken::LessEqual:      Out->os() << "LessEqual"; break;
+    case AsmToken::LessGreater:    Out->os() << "LessGreater"; break;
+    case AsmToken::LessLess:       Out->os() << "LessLess"; break;
+    case AsmToken::Minus:          Out->os() << "Minus"; break;
+    case AsmToken::Percent:        Out->os() << "Percent"; break;
+    case AsmToken::Pipe:           Out->os() << "Pipe"; break;
+    case AsmToken::PipePipe:       Out->os() << "PipePipe"; break;
+    case AsmToken::Plus:           Out->os() << "Plus"; break;
+    case AsmToken::RBrac:          Out->os() << "RBrac"; break;
+    case AsmToken::RCurly:         Out->os() << "RCurly"; break;
+    case AsmToken::RParen:         Out->os() << "RParen"; break;
+    case AsmToken::Slash:          Out->os() << "Slash"; break;
+    case AsmToken::Star:           Out->os() << "Star"; break;
+    case AsmToken::Tilde:          Out->os() << "Tilde"; break;
     }
+
+    // Print the token string.
+    Out->os() << " (\"";
+    Out->os().write_escaped(Tok.getString());
+    Out->os() << "\")\n";
   }
 
   // Keep output if no errors.



From daniel at zuster.org  Mon Oct 25 15:18:49 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 25 Oct 2010 20:18:49 -0000
Subject: [llvm-commits] [llvm] r117297 -
	/llvm/trunk/test/MC/AsmParser/exprs.s
Message-ID: <20101025201849.C13892A6C12C@llvm.org>

Author: ddunbar
Date: Mon Oct 25 15:18:49 2010
New Revision: 117297

URL: http://llvm.org/viewvc/llvm-project?rev=117297&view=rev
Log:
tweak test.

Modified:
    llvm/trunk/test/MC/AsmParser/exprs.s

Modified: llvm/trunk/test/MC/AsmParser/exprs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/exprs.s?rev=117297&r1=117296&r2=117297&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/exprs.s (original)
+++ llvm/trunk/test/MC/AsmParser/exprs.s Mon Oct 25 15:18:49 2010
@@ -14,8 +14,8 @@
         .data
         check_expr !1 + 2, 2
         check_expr !0, 1
-        check_expr ~0 & 0xFF, 0xFF
-        check_expr -1 & 0xFF, 0xFF
+        check_expr ~0, -1
+        check_expr -1, ~0
         check_expr +1, 1
         check_expr 1 + 2, 3
         check_expr 1 & 3, 1
@@ -35,7 +35,7 @@
         check_expr 1 | 2, 3
         check_expr 1 << 1, 2
         check_expr 2 >> 1, 1
-        check_expr (~0 >> 1) & 0xFF, 0xFF
+        check_expr (~0 >> 1), -1
         check_expr 3 - 2, 1
         check_expr 1 ^ 3, 2
         check_expr 1 && 2, 1



From daniel at zuster.org  Mon Oct 25 15:18:57 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 25 Oct 2010 20:18:57 -0000
Subject: [llvm-commits] [llvm] r117299 - in /llvm/trunk:
 lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/exprs.s
Message-ID: <20101025201857.2A7B92A6C12C@llvm.org>

Author: ddunbar
Date: Mon Oct 25 15:18:56 2010
New Revision: 117299

URL: http://llvm.org/viewvc/llvm-project?rev=117299&view=rev
Log:
MC/AsmParser: Fix relative precedence of {+,-} and comparison ops.

Modified:
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp
    llvm/trunk/test/MC/AsmParser/exprs.s

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=117299&r1=117298&r2=117299&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Oct 25 15:18:56 2010
@@ -717,13 +717,7 @@
     Kind = MCBinaryExpr::And;
     return 2;
 
-    // Intermediate Precedence: +, -, ==, !=, <>, <, <=, >, >=
-  case AsmToken::Plus:
-    Kind = MCBinaryExpr::Add;
-    return 3;
-  case AsmToken::Minus:
-    Kind = MCBinaryExpr::Sub;
-    return 3;
+    // Low Intermediate Precedence: ==, !=, <>, <, <=, >, >=
   case AsmToken::EqualEqual:
     Kind = MCBinaryExpr::EQ;
     return 3;
@@ -744,22 +738,30 @@
     Kind = MCBinaryExpr::GTE;
     return 3;
 
+    // High Intermediate Precedence: +, -
+  case AsmToken::Plus:
+    Kind = MCBinaryExpr::Add;
+    return 4;
+  case AsmToken::Minus:
+    Kind = MCBinaryExpr::Sub;
+    return 4;
+
     // Highest Precedence: *, /, %, <<, >>
   case AsmToken::Star:
     Kind = MCBinaryExpr::Mul;
-    return 4;
+    return 5;
   case AsmToken::Slash:
     Kind = MCBinaryExpr::Div;
-    return 4;
+    return 5;
   case AsmToken::Percent:
     Kind = MCBinaryExpr::Mod;
-    return 4;
+    return 5;
   case AsmToken::LessLess:
     Kind = MCBinaryExpr::Shl;
-    return 4;
+    return 5;
   case AsmToken::GreaterGreater:
     Kind = MCBinaryExpr::Shr;
-    return 4;
+    return 5;
   }
 }
 

Modified: llvm/trunk/test/MC/AsmParser/exprs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/exprs.s?rev=117299&r1=117298&r2=117299&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/exprs.s (original)
+++ llvm/trunk/test/MC/AsmParser/exprs.s Mon Oct 25 15:18:56 2010
@@ -43,7 +43,8 @@
         check_expr 1 || 2, 1
         check_expr 0 || 1, 1
         check_expr 0 || 0, 0
-
+        check_expr 1 + 2 < 3 + 4, 1
+        
         .set c, 10
         check_expr c + 1, 11
 



From daniel at zuster.org  Mon Oct 25 15:18:53 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 25 Oct 2010 20:18:53 -0000
Subject: [llvm-commits] [llvm] r117298 - in /llvm/trunk:
 lib/MC/MCParser/AsmLexer.cpp test/MC/AsmParser/exprs.s
Message-ID: <20101025201853.70B432A6C12E@llvm.org>

Author: ddunbar
Date: Mon Oct 25 15:18:53 2010
New Revision: 117298

URL: http://llvm.org/viewvc/llvm-project?rev=117298&view=rev
Log:
MC/AsmLexer: Fix bug in source location for Slash token.

Modified:
    llvm/trunk/lib/MC/MCParser/AsmLexer.cpp
    llvm/trunk/test/MC/AsmParser/exprs.s

Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=117298&r1=117297&r2=117298&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Mon Oct 25 15:18:53 2010
@@ -119,7 +119,7 @@
   switch (*CurPtr) {
   case '*': break; // C style comment.
   case '/': return ++CurPtr, LexLineComment();
-  default:  return AsmToken(AsmToken::Slash, StringRef(CurPtr, 1));
+  default:  return AsmToken(AsmToken::Slash, StringRef(CurPtr-1, 1));
   }
 
   // C Style comment.

Modified: llvm/trunk/test/MC/AsmParser/exprs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/exprs.s?rev=117298&r1=117297&r2=117298&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/exprs.s (original)
+++ llvm/trunk/test/MC/AsmParser/exprs.s Mon Oct 25 15:18:53 2010
@@ -19,9 +19,8 @@
         check_expr +1, 1
         check_expr 1 + 2, 3
         check_expr 1 & 3, 1
-        // FIXME: There is a bug here in macro expansion.
-        .byte 4 / 2
-        .byte 4 / -2
+        check_expr 4 / 2, 2
+        check_expr 4 / -2, -2
         check_expr 1 == 1, 1
         check_expr 1 == 0, 0
         check_expr 1 > 0, 1



From gohman at apple.com  Mon Oct 25 15:22:29 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 20:22:29 -0000
Subject: [llvm-commits] [llvm] r117301 -
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
Message-ID: <20101025202229.297EA2A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 15:22:29 2010
New Revision: 117301

URL: http://llvm.org/viewvc/llvm-project?rev=117301&view=rev
Log:
Only read one bit for testing for a readonly type, leaving the other
bits open for future uses.

Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=117301&r1=117300&r2=117301&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Mon Oct 25 15:22:29 2010
@@ -102,8 +102,7 @@
       ConstantInt *CI = dyn_cast<ConstantInt>(Node->getOperand(2));
       if (!CI)
         return false;
-      // TODO: Think about the encoding.
-      return CI->isOne();
+      return CI->getValue()[0];
     }
   };
 }



From resistor at mac.com  Mon Oct 25 15:29:27 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 20:29:27 -0000
Subject: [llvm-commits] [llvm] r117302 -
	/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
Message-ID: <20101025202927.AE1762A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 15:29:27 2010
New Revision: 117302

URL: http://llvm.org/viewvc/llvm-project?rev=117302&view=rev
Log:
Add tests for NEON encoding of vabd.

Added:
    llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll?rev=117302&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll Mon Oct 25 15:29:27 2010
@@ -0,0 +1,147 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8>  @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vabds_8xi8
+define <8 x i8> @vabds_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vabd.s8	d16, d16, d17           @ encoding: [0xa1,0x07,0x40,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vabds_4xi16
+define <4 x i16> @vabds_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vabd.s16	d16, d16, d17   @ encoding: [0xa1,0x07,0x50,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vabds_2xi32
+define <2 x i32> @vabds_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vabd.s32	d16, d16, d17   @ encoding: [0xa1,0x07,0x60,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vabdu_8xi8
+define <8 x i8> @vabdu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vabd.u8	d16, d16, d17           @ encoding: [0xa1,0x07,0x40,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vabdu_4xi16
+define <4 x i16> @vabdu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vabd.u16	d16, d16, d17   @ encoding: [0xa1,0x07,0x50,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vabdu_2xi32
+define <2 x i32> @vabdu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vabd.u32	d16, d16, d17   @ encoding: [0xa1,0x07,0x60,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+; CHECK: vabd_2xfloat
+define <2 x float> @vabd_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vabd.f32	d16, d16, d17   @ encoding: [0xa1,0x0d,0x60,0xf3]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; CHECK: vabds_16xi8
+define <16 x i8> @vabds_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vabd.s8	q8, q8, q9              @ encoding: [0xe2,0x07,0x40,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vabds_8xi16
+define <8 x i16> @vabds_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vabd.s16	q8, q8, q9      @ encoding: [0xe2,0x07,0x50,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vabds_4xi32
+define <4 x i32> @vabds_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vabd.s32	q8, q8, q9      @ encoding: [0xe2,0x07,0x60,0xf2]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; CHECK: vabdu_16xi8
+define <16 x i8> @vabdu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vabd.u8	q8, q8, q9              @ encoding: [0xe2,0x07,0x40,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vabdu_8xi16
+define <8 x i16> @vabdu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vabd.u16	q8, q8, q9      @ encoding: [0xe2,0x07,0x50,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vabdu_4xi32
+define <4 x i32> @vabdu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vabd.u32	q8, q8, q9      @ encoding: [0xe2,0x07,0x60,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vabd_4xfloat
+define <4 x float> @vabd_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vabd.f32	q8, q8, q9      @ encoding: [0xe2,0x0d,0x60,0xf3]
+	%tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x float> %tmp3
+}



From resistor at mac.com  Mon Oct 25 15:36:28 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 20:36:28 -0000
Subject: [llvm-commits] [llvm] r117303 -
	/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
Message-ID: <20101025203628.85B6E2A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 15:36:28 2010
New Revision: 117303

URL: http://llvm.org/viewvc/llvm-project?rev=117303&view=rev
Log:
Tests for NEON encoding of vabdl.

Modified:
    llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll?rev=117303&r1=117302&r2=117303&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll Mon Oct 25 15:36:28 2010
@@ -145,3 +145,62 @@
 	%tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
+
+; CHECK: vabdls_8xi8
+define <8 x i16> @vabdls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vabdl.s8	q8, d16, d17    @ encoding: [0xa1,0x07,0xc0,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vabdls_4xi16
+define <4 x i32> @vabdls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vabdl.s16	q8, d16, d17    @ encoding: [0xa1,0x07,0xd0,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vabdls_2xi32
+define <2 x i64> @vabdls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vabdl.s32	q8, d16, d17    @ encoding: [0xa1,0x07,0xe0,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+; CHECK: vabdlu_8xi8
+define <8 x i16> @vabdlu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vabdl.u8	q8, d16, d17    @ encoding: [0xa1,0x07,0xc0,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	%tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+; CHECK: vabdlu_4xi16
+define <4 x i32> @vabdlu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vabdl.u16	q8, d16, d17    @ encoding: [0xa1,0x07,0xd0,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	%tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+; CHECK: vabdlu_2xi3
+define <2 x i64> @vabdlu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}



From dpatel at apple.com  Mon Oct 25 15:41:19 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 25 Oct 2010 20:41:19 -0000
Subject: [llvm-commits] [test-suite] r117306 -
	/test-suite/trunk/Makefile.rules
Message-ID: <20101025204119.E8ED02A6C12C@llvm.org>

Author: dpatel
Date: Mon Oct 25 15:41:19 2010
New Revision: 117306

URL: http://llvm.org/viewvc/llvm-project?rev=117306&view=rev
Log:
Do not hardcode -O3 as the optimization level for llc and friends. 

Modified:
    test-suite/trunk/Makefile.rules

Modified: test-suite/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.rules?rev=117306&r1=117305&r2=117306&view=diff
==============================================================================
--- test-suite/trunk/Makefile.rules (original)
+++ test-suite/trunk/Makefile.rules Mon Oct 25 15:41:19 2010
@@ -386,9 +386,9 @@
 CFLAGS += -mieee
 endif
 
-# Set llc / lli optimization level to -O3 to match gcc.
-LLC_OPTFLAGS := -O3
-LLI_OPTFLAGS := -O3
+# Set llc / lli optimization level
+LLC_OPTFLAGS := $(OPTFLAGS)
+LLI_OPTFLAGS := $(OPTFLAGS)
 
 # gcc / llvm-gcc default is -fPIC -fno-omit-frame-pointer
 # llc / lli default is equal to -mdynamic-no-pic -fomit-frame-pointer
@@ -446,8 +446,8 @@
 
 # link both projlib and llvmlib libraries
 LinkG    := $(Link) -g -L$(PROJLIBDEBUGSOURCE)  -L$(LLVMLIBDEBUGSOURCE) $(STRIP)
-LinkO    := $(Link) -O3 -L$(PROJLIBRELEASESOURCE) -L$(LLVMLIBRELEASESOURCE)
-LinkP    := $(Link) -O3 -L$(PROJLIBPROFILESOURCE) -L$(LLVMLIBPROFILESOURCE) $(PROFILE)
+LinkO    := $(Link) $(OPTFLAGS) -L$(PROJLIBRELEASESOURCE) -L$(LLVMLIBRELEASESOURCE)
+LinkP    := $(Link) $(OPTFLAGS) -L$(PROJLIBPROFILESOURCE) -L$(LLVMLIBPROFILESOURCE) $(PROFILE)
 
 # TOOLLINKOPTSB to pass options to the linker like library search path etc
 # Note that this is different from TOOLLINKOPTS, these options



From dpatel at apple.com  Mon Oct 25 15:45:32 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 25 Oct 2010 20:45:32 -0000
Subject: [llvm-commits] [llvm] r117307 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20101025204533.0433C2A6C12C@llvm.org>

Author: dpatel
Date: Mon Oct 25 15:45:32 2010
New Revision: 117307

URL: http://llvm.org/viewvc/llvm-project?rev=117307&view=rev
Log:
Add simple counter to count no. of basic blocks without any line number information. At -O0, these basic block coule cause less than optimial debugging experience.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=117307&r1=117306&r2=117307&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 25 15:45:32 2010
@@ -30,6 +30,7 @@
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Analysis/DebugInfo.h"
+#include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/CommandLine.h"
@@ -52,6 +53,8 @@
      cl::desc("Make an absense of debug location information explicit."),
      cl::init(false));
 
+STATISTIC(BlocksWithoutLineNo, "Number of blocks without any line number");
+
 namespace {
   const char *DWARFGroupName = "DWARF Emission";
   const char *DbgTimerName = "DWARF Debug Writer";
@@ -2770,12 +2773,37 @@
   return DebugLoc();
 }
 
+#ifndef NDEBUG
+/// CheckLineNumbers - Count basicblocks whose instructions do not have any
+/// line number information.
+static void CheckLineNumbers(const MachineFunction *MF) {
+  for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
+       I != E; ++I) {
+    bool FoundLineNo = false;
+    for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
+         II != IE; ++II) {
+      const MachineInstr *MI = II;
+      if (!MI->getDebugLoc().isUnknown()) {
+        FoundLineNo = true;
+        break;
+      }
+    }
+    if (!FoundLineNo)
+      ++BlocksWithoutLineNo;      
+  }
+}
+#endif
+
 /// beginFunction - Gather pre-function debug information.  Assumes being
 /// emitted immediately after the function entry point.
 void DwarfDebug::beginFunction(const MachineFunction *MF) {
   if (!MMI->hasDebugInfo()) return;
   if (!extractScopeInformation()) return;
 
+#ifndef NDEBUG
+  CheckLineNumbers(MF);
+#endif
+
   FunctionBeginSym = Asm->GetTempSymbol("func_begin",
                                         Asm->getFunctionNumber());
   // Assumes in correct section after the entry point.



From resistor at mac.com  Mon Oct 25 15:52:57 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 20:52:57 -0000
Subject: [llvm-commits] [llvm] r117309 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-absdiff-encoding.ll
 test/MC/ARM/neon-bitwise-encoding.ll
Message-ID: <20101025205258.161442A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 15:52:57 2010
New Revision: 117309

URL: http://llvm.org/viewvc/llvm-project?rev=117309&view=rev
Log:
Add correct NEON encodings for vaba.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117309&r1=117308&r2=117309&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 15:52:57 2010
@@ -1410,18 +1410,18 @@
                 InstrItinClass itin, string OpcodeStr, string Dt,
                 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
   : N3V<op24, op23, op21_20, op11_8, 0, op4,
-        (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
-        [(set DPR:$dst, (Ty (OpNode DPR:$src1,
-                             (Ty (IntOp (Ty DPR:$src2), (Ty DPR:$src3))))))]>;
+        (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
+        OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+        [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
+                             (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
                 InstrItinClass itin, string OpcodeStr, string Dt,
                 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
   : N3V<op24, op23, op21_20, op11_8, 1, op4,
-        (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
-        [(set QPR:$dst, (Ty (OpNode QPR:$src1,
-                             (Ty (IntOp (Ty QPR:$src2), (Ty QPR:$src3))))))]>;
+        (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
+        OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+        [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
+                             (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
 
 // Neon 3-argument intrinsics, both double- and quad-register.
 // The destination register is also used as the first source operand register.

Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll?rev=117309&r1=117308&r2=117309&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll Mon Oct 25 15:52:57 2010
@@ -204,3 +204,135 @@
 	%tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
 	ret <2 x i64> %tmp4
 }
+
+; CHECK: vabas_8xi8
+define <8 x i8> @vabas_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+; CHECK: vaba.s8	d16, d18, d17           @ encoding: [0xb1,0x07,0x42,0xf2]
+	%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
+	%tmp5 = add <8 x i8> %tmp1, %tmp4
+	ret <8 x i8> %tmp5
+}
+
+; CHECK: vabas_4xi16
+define <4 x i16> @vabas_4xi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+; CHECK: vaba.s16	d16, d18, d17   @ encoding: [0xb1,0x07,0x52,0xf2]
+	%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
+	%tmp5 = add <4 x i16> %tmp1, %tmp4
+	ret <4 x i16> %tmp5
+}
+
+; CHECK: vabas_2xi32
+define <2 x i32> @vabas_2xi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+; CHECK: vaba.s32	d16, d18, d17   @ encoding: [0xb1,0x07,0x62,0xf2]
+	%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
+	%tmp5 = add <2 x i32> %tmp1, %tmp4
+	ret <2 x i32> %tmp5
+}
+
+; CHECK: vabau_8xi8
+define <8 x i8> @vabau_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+; CHECK: vaba.u8	d16, d18, d17           @ encoding: [0xb1,0x07,0x42,0xf3]
+	%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
+	%tmp5 = add <8 x i8> %tmp1, %tmp4
+	ret <8 x i8> %tmp5
+}
+
+; CHECK: vabau_4xi16
+define <4 x i16> @vabau_4xi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+; CHECK: vaba.u16	d16, d18, d17   @ encoding: [0xb1,0x07,0x52,0xf3]
+	%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
+	%tmp5 = add <4 x i16> %tmp1, %tmp4
+	ret <4 x i16> %tmp5
+}
+
+; CHECK: vabau_2xi32
+define <2 x i32> @vabau_2xi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+; CHECK: vaba.u32	d16, d18, d17   @ encoding: [0xb1,0x07,0x62,0xf3]
+	%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
+	%tmp5 = add <2 x i32> %tmp1, %tmp4
+	ret <2 x i32> %tmp5
+}
+
+; CHECK: vabas_16xi8
+define <16 x i8> @vabas_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+	%tmp3 = load <16 x i8>* %C
+; CHECK: vaba.s8	q9, q8, q10             @ encoding: [0xf4,0x27,0x40,0xf2]
+	%tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
+	%tmp5 = add <16 x i8> %tmp1, %tmp4
+	ret <16 x i8> %tmp5
+}
+
+; CHECK: vabas_8xi16
+define <8 x i16> @vabas_8xi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+	%tmp3 = load <8 x i16>* %C
+; CHECK: vaba.s16	q9, q8, q10     @ encoding: [0xf4,0x27,0x50,0xf2]
+	%tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
+	%tmp5 = add <8 x i16> %tmp1, %tmp4
+	ret <8 x i16> %tmp5
+}
+
+; CHECK: vabas_4xi32
+define <4 x i32> @vabas_4xi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+	%tmp3 = load <4 x i32>* %C
+; CHECK: vaba.s32	q9, q8, q10     @ encoding: [0xf4,0x27,0x60,0xf2]
+	%tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
+	%tmp5 = add <4 x i32> %tmp1, %tmp4
+	ret <4 x i32> %tmp5
+}
+
+; CHECK: vabau_16xi8
+define <16 x i8> @vabau_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+	%tmp3 = load <16 x i8>* %C
+; CHECK: vaba.u8	q9, q8, q10             @ encoding: [0xf4,0x27,0x40,0xf3]
+	%tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3)
+	%tmp5 = add <16 x i8> %tmp1, %tmp4
+	ret <16 x i8> %tmp5
+}
+
+; CHECK: vabau_8xi16
+define <8 x i16> @vabau_8xi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+	%tmp3 = load <8 x i16>* %C
+; CHECK: vaba.u16	q9, q8, q10     @ encoding: [0xf4,0x27,0x50,0xf3]
+	%tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3)
+	%tmp5 = add <8 x i16> %tmp1, %tmp4
+	ret <8 x i16> %tmp5
+}
+
+; CHECK: vabau_4xi32
+define <4 x i32> @vabau_4xi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+	%tmp3 = load <4 x i32>* %C
+; CHECK: vaba.u32	q9, q8, q10     @ encoding: [0xf4,0x27,0x60,0xf3]
+	%tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3)
+	%tmp5 = add <4 x i32> %tmp1, %tmp4
+	ret <4 x i32> %tmp5
+}

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117309&r1=117308&r2=117309&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Mon Oct 25 15:52:57 2010
@@ -1,7 +1,7 @@
 ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
 
 ; FIXME: The following instructions still require testing:
-;  - vand with immediate
+;  - vand with immediate, vorr with immediate
 ;  - vmvn of an immediate
 ;  - both vbit and vbif
 



From dpatel at apple.com  Mon Oct 25 15:55:43 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 25 Oct 2010 20:55:43 -0000
Subject: [llvm-commits] [llvm] r117310 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20101025205543.2CE752A6C12C@llvm.org>

Author: dpatel
Date: Mon Oct 25 15:55:43 2010
New Revision: 117310

URL: http://llvm.org/viewvc/llvm-project?rev=117310&view=rev
Log:
Add counters to count basic blocks and machine basic blocks with out of order line number info.
Add counters to count how many basic blocks are entirely selected by fastisel.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=117310&r1=117309&r2=117310&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 25 15:55:43 2010
@@ -53,7 +53,13 @@
 using namespace llvm;
 
 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
+STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
+STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
+STATISTIC(NumBBWithOutOfOrderLineInfo, 
+          "Number of blocks with out of order line number info");
+STATISTIC(NumMBBWithOutOfOrderLineInfo, 
+          "Number of machine blocks with out of order line number info");
 
 static cl::opt<bool>
 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
@@ -370,7 +376,7 @@
   return true;
 }
 
-void
+bool
 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
                                    BasicBlock::const_iterator End,
                                    bool &HadTailCall) {
@@ -387,6 +393,7 @@
 
   // Final step, emit the lowered DAG as machine code.
   CodeGenAndEmitDAG();
+  return Begin != End;
 }
 
 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
@@ -726,8 +733,47 @@
   return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
 }
 
-  
+#ifndef NDEBUG
+/// CheckLineNumbers - Check if basic block instructions follow source order
+/// or not.
+static void CheckLineNumbers(const BasicBlock *BB) {
+  unsigned Line = 0;
+  unsigned Col = 0;
+  for (BasicBlock::const_iterator BI = BB->begin(),
+         BE = BB->end(); BI != BE; ++BI) {
+    const DebugLoc DL = BI->getDebugLoc();
+    if (DL.isUnknown()) continue;
+    unsigned L = DL.getLine();
+    unsigned C = DL.getCol();
+    if (L < Line || (L == Line && C < Col)) {
+      ++NumBBWithOutOfOrderLineInfo;
+      return;
+    }
+    Line = L;
+    Col = C;
+  }
+}  
 
+/// CheckLineNumbers - Check if machine basic block instructions follow source 
+/// order or not.
+static void CheckLineNumbers(const MachineBasicBlock *MBB) {
+  unsigned Line = 0;
+  unsigned Col = 0;
+  for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
+         MBE = MBB->end(); MBI != MBE; ++MBI) {
+    const DebugLoc DL = MBI->getDebugLoc();
+    if (DL.isUnknown()) continue;
+    unsigned L = DL.getLine();
+    unsigned C = DL.getCol();
+    if (L < Line || (L == Line && C < Col)) {
+      ++NumMBBWithOutOfOrderLineInfo;
+      return;
+    }
+    Line = L;
+    Col = C;
+  }
+}  
+#endif
 
 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
   // Initialize the Fast-ISel state, if needed.
@@ -737,7 +783,11 @@
 
   // Iterate over all basic blocks in the function.
   for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
+    bool BBSelectedUsingDAG = false;
     const BasicBlock *LLVMBB = &*I;
+#ifndef NDEBUG
+    CheckLineNumbers(LLVMBB);
+#endif
     FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
     FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
 
@@ -822,7 +872,7 @@
           }
 
           bool HadTailCall = false;
-          SelectBasicBlock(Inst, BI, HadTailCall);
+          BBSelectedUsingDAG |= SelectBasicBlock(Inst, BI, HadTailCall);
 
           // If the call was emitted as a tail call, we're done with the block.
           if (HadTailCall) {
@@ -856,13 +906,22 @@
     // not handled by FastISel. If FastISel is not run, this is the entire
     // block.
     bool HadTailCall;
-    SelectBasicBlock(Begin, BI, HadTailCall);
+    BBSelectedUsingDAG |= SelectBasicBlock(Begin, BI, HadTailCall);
 
     FinishBasicBlock();
     FuncInfo->PHINodesToUpdate.clear();
+    if (BBSelectedUsingDAG)
+      ++NumDAGBlocks;
+    else
+      ++NumFastIselBlocks;
   }
 
   delete FastIS;
+#ifndef NDEBUG
+  for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
+       MBI != MBE; ++MBI)
+    CheckLineNumbers(MBI);
+#endif
 }
 
 void



From gohman at apple.com  Mon Oct 25 15:58:57 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 13:58:57 -0700
Subject: [llvm-commits] [llvm] r117070	-
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
In-Reply-To: <4CC2D027.4040701@free.fr>
References: <20101021215535.56EB92A6C12C@llvm.org> <4CC19A46.8080409@free.fr>
	<1840ECD2-B3DB-4AEA-9F5B-5132FD66BB3E@apple.com>
	<BD8846FB-1675-4D7C-8540-4356445C8552@apple.com>
	<4CC2D027.4040701@free.fr>
Message-ID: <047F46EA-629E-4D69-9B44-9515B91114C2@apple.com>


On Oct 23, 2010, at 5:08 AM, Duncan Sands wrote:

> Hi Dan,
> 
>>> Both C and C++ say that modifying an object defined with a const qualifier
>>> has undefined results, so while you can't use this for pointer-to-const, you
>>> could use it for const variables after they've been initialized.
>> 
>> 
>> For pointsToConstantMemory, it has to be really constant, so in C, the only
>> thing that could use it is statically initialized const variables.
>> 
>> LLVM already has constant GlobalVariables, so probably the only new
>> theoretical functionality here for C and C++ would be for statically initialized
>> objects which are mostly const but have mutable fields.
>> 
>> For other languages, this feature could be used for runtime library calls
>> which allocate objects and initialize some thereafter-constant fields in
>> the objects, as long as the calls are never inlined.
> 
> this sounds a lot like what you can do with llvm.invariant (initialize a
> variable, then mark it as constant afterwards using llvm.invariant).

It may be theoretically redundant at some level, but there are
some practical differences. llvm.invariant is only visible to passes
using memdep or do some other scanning of multiple instructions. The
TBAA const flag is attached to loads directly, so clients like LICM
and CodeGen which don't do that can easily find them.

Dan



From dpatel at apple.com  Mon Oct 25 16:04:12 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 25 Oct 2010 21:04:12 -0000
Subject: [llvm-commits] [llvm] r117312 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
Message-ID: <20101025210412.7BA622A6C12C@llvm.org>

Author: dpatel
Date: Mon Oct 25 16:04:12 2010
New Revision: 117312

URL: http://llvm.org/viewvc/llvm-project?rev=117312&view=rev
Log:
Update SelectBasicBlock signature. This should have been committed with r117310.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=117312&r1=117311&r2=117312&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Oct 25 16:04:12 2010
@@ -287,7 +287,7 @@
   bool TryToFoldFastISelLoad(const LoadInst *LI, FastISel *FastIS);
   void FinishBasicBlock();
 
-  void SelectBasicBlock(BasicBlock::const_iterator Begin,
+  bool SelectBasicBlock(BasicBlock::const_iterator Begin,
                         BasicBlock::const_iterator End,
                         bool &HadTailCall);
   void CodeGenAndEmitDAG();



From gohman at apple.com  Mon Oct 25 16:24:56 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 21:24:56 -0000
Subject: [llvm-commits] [llvm] r117314 -
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
Message-ID: <20101025212456.10AFD2A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 16:24:55 2010
New Revision: 117314

URL: http://llvm.org/viewvc/llvm-project?rev=117314&view=rev
Log:
Fix chaining in TBAA's pointsToConstantMemory.

Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=117314&r1=117313&r2=117314&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Mon Oct 25 16:24:55 2010
@@ -225,7 +225,7 @@
     return AliasAnalysis::pointsToConstantMemory(Loc);
 
   const MDNode *M = Loc.TBAATag;
-  if (!M) return false;
+  if (!M) return AliasAnalysis::pointsToConstantMemory(Loc);
 
   // If this is an "immutable" type, we can assume the pointer is pointing
   // to constant memory.



From resistor at mac.com  Mon Oct 25 16:29:04 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 21:29:04 -0000
Subject: [llvm-commits] [llvm] r117315 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-absdiff-encoding.ll
Message-ID: <20101025212904.DA0892A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 16:29:04 2010
New Revision: 117315

URL: http://llvm.org/viewvc/llvm-project?rev=117315&view=rev
Log:
Add correct encodings for NEON vabal.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117315&r1=117314&r2=117315&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 25 16:29:04 2010
@@ -1483,11 +1483,11 @@
                    ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
                    SDNode OpNode>
   : N3V<op24, op23, op21_20, op11_8, 0, op4,
-        (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin,
-        OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst",
-        [(set QPR:$dst, (OpNode (TyQ QPR:$src1),
-                                (TyQ (ExtOp (TyD (IntOp (TyD DPR:$src2),
-                                                        (TyD DPR:$src3)))))))]>;
+        (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
+        OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
+        [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
+                                (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
+                                                        (TyD DPR:$Vm)))))))]>;
 
 // Neon Long 3-argument intrinsic.  The destination register is
 // a quad-register and is also used as the first source operand register.

Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll?rev=117315&r1=117314&r2=117315&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.ll Mon Oct 25 16:29:04 2010
@@ -336,3 +336,75 @@
 	%tmp5 = add <4 x i32> %tmp1, %tmp4
 	ret <4 x i32> %tmp5
 }
+
+; CHECK: vabals_8xi8
+define <8 x i16> @vabals_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+; CHECK: vabal.s8	q8, d19, d18    @ encoding: [0xa2,0x05,0xc3,0xf2]
+	%tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
+	%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
+	%tmp6 = add <8 x i16> %tmp1, %tmp5
+	ret <8 x i16> %tmp6
+}
+
+; CHECK: vabals_4xi16
+define <4 x i32> @vabals_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+; CHECK: vabal.s16	q8, d19, d18    @ encoding: [0xa2,0x05,0xd3,0xf2]
+	%tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
+	%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
+	%tmp6 = add <4 x i32> %tmp1, %tmp5
+	ret <4 x i32> %tmp6
+}
+
+; CHECK: vabals_2xi32
+define <2 x i64> @vabals_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+; CHECK: vabal.s32	q8, d19, d18    @ encoding: [0xa2,0x05,0xe3,0xf2]
+	%tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
+	%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
+	%tmp6 = add <2 x i64> %tmp1, %tmp5
+	ret <2 x i64> %tmp6
+}
+
+; CHECK: vabalu_8xi8
+define <8 x i16> @vabalu_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+; CHECK: vabal.u8	q8, d19, d18    @ encoding: [0xa2,0x05,0xc3,0xf3]
+	%tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3)
+	%tmp5 = zext <8 x i8> %tmp4 to <8 x i16>
+	%tmp6 = add <8 x i16> %tmp1, %tmp5
+	ret <8 x i16> %tmp6
+}
+
+; CHECK: vabalu_4xi16
+define <4 x i32> @vabalu_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+; CHECK: 	vabal.u16	q8, d19, d18    @ encoding: [0xa2,0x05,0xd3,0xf3]
+	%tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3)
+	%tmp5 = zext <4 x i16> %tmp4 to <4 x i32>
+	%tmp6 = add <4 x i32> %tmp1, %tmp5
+	ret <4 x i32> %tmp6
+}
+
+; CHECK: vabalu_2xi32
+define <2 x i64> @vabalu_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+; CHECK: vabal.u32	q8, d19, d18    @ encoding: [0xa2,0x05,0xe3,0xf3]
+	%tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3)
+	%tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
+	%tmp6 = add <2 x i64> %tmp1, %tmp5
+	ret <2 x i64> %tmp6
+}



From dpatel at apple.com  Mon Oct 25 16:31:47 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 25 Oct 2010 21:31:47 -0000
Subject: [llvm-commits] [llvm] r117316 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGISel.h
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20101025213147.0F9FF2A6C12C@llvm.org>

Author: dpatel
Date: Mon Oct 25 16:31:46 2010
New Revision: 117316

URL: http://llvm.org/viewvc/llvm-project?rev=117316&view=rev
Log:
Simplify.
Do not count use of sdisel for single call instruction.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=117316&r1=117315&r2=117316&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Oct 25 16:31:46 2010
@@ -287,7 +287,7 @@
   bool TryToFoldFastISelLoad(const LoadInst *LI, FastISel *FastIS);
   void FinishBasicBlock();
 
-  bool SelectBasicBlock(BasicBlock::const_iterator Begin,
+  void SelectBasicBlock(BasicBlock::const_iterator Begin,
                         BasicBlock::const_iterator End,
                         bool &HadTailCall);
   void CodeGenAndEmitDAG();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=117316&r1=117315&r2=117316&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 25 16:31:46 2010
@@ -376,7 +376,7 @@
   return true;
 }
 
-bool
+void
 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
                                    BasicBlock::const_iterator End,
                                    bool &HadTailCall) {
@@ -393,7 +393,7 @@
 
   // Final step, emit the lowered DAG as machine code.
   CodeGenAndEmitDAG();
-  return Begin != End;
+  return;
 }
 
 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
@@ -783,7 +783,6 @@
 
   // Iterate over all basic blocks in the function.
   for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
-    bool BBSelectedUsingDAG = false;
     const BasicBlock *LLVMBB = &*I;
 #ifndef NDEBUG
     CheckLineNumbers(LLVMBB);
@@ -872,7 +871,7 @@
           }
 
           bool HadTailCall = false;
-          BBSelectedUsingDAG |= SelectBasicBlock(Inst, BI, HadTailCall);
+          SelectBasicBlock(Inst, BI, HadTailCall);
 
           // If the call was emitted as a tail call, we're done with the block.
           if (HadTailCall) {
@@ -902,18 +901,19 @@
       FastIS->recomputeInsertPt();
     }
 
+    if (Begin != BI)
+      ++NumDAGBlocks;
+    else
+      ++NumFastIselBlocks;
+
     // Run SelectionDAG instruction selection on the remainder of the block
     // not handled by FastISel. If FastISel is not run, this is the entire
     // block.
     bool HadTailCall;
-    BBSelectedUsingDAG |= SelectBasicBlock(Begin, BI, HadTailCall);
+    SelectBasicBlock(Begin, BI, HadTailCall);
 
     FinishBasicBlock();
     FuncInfo->PHINodesToUpdate.clear();
-    if (BBSelectedUsingDAG)
-      ++NumDAGBlocks;
-    else
-      ++NumFastIselBlocks;
   }
 
   delete FastIS;



From gohman at apple.com  Mon Oct 25 16:38:20 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 25 Oct 2010 21:38:20 -0000
Subject: [llvm-commits] [llvm] r117317 -
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
Message-ID: <20101025213820.C18D62A6C12C@llvm.org>

Author: djg
Date: Mon Oct 25 16:38:20 2010
New Revision: 117317

URL: http://llvm.org/viewvc/llvm-project?rev=117317&view=rev
Log:
Support TBAA attachments on calls. This is somewhat experimental.

Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=117317&r1=117316&r2=117317&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Mon Oct 25 16:38:20 2010
@@ -59,6 +59,7 @@
 
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/Passes.h"
+#include "llvm/LLVMContext.h"
 #include "llvm/Module.h"
 #include "llvm/Metadata.h"
 #include "llvm/Pass.h"
@@ -138,6 +139,10 @@
     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
     virtual AliasResult alias(const Location &LocA, const Location &LocB);
     virtual bool pointsToConstantMemory(const Location &Loc);
+    virtual ModRefResult getModRefInfo(ImmutableCallSite CS,
+                                       const Location &Loc);
+    virtual ModRefResult getModRefInfo(ImmutableCallSite CS1,
+                                       ImmutableCallSite CS2);
   };
 }  // End of anonymous namespace
 
@@ -234,3 +239,34 @@
 
   return AliasAnalysis::pointsToConstantMemory(Loc);
 }
+
+AliasAnalysis::ModRefResult
+TypeBasedAliasAnalysis::getModRefInfo(ImmutableCallSite CS,
+                                      const Location &Loc) {
+  if (!EnableTBAA)
+    return AliasAnalysis::getModRefInfo(CS, Loc);
+
+  if (const MDNode *L = Loc.TBAATag)
+    if (const MDNode *M =
+          CS.getInstruction()->getMetadata(LLVMContext::MD_tbaa))
+      if (!Aliases(L, M))
+        return NoModRef;
+
+  return AliasAnalysis::getModRefInfo(CS, Loc);
+}
+
+AliasAnalysis::ModRefResult
+TypeBasedAliasAnalysis::getModRefInfo(ImmutableCallSite CS1,
+                                      ImmutableCallSite CS2) {
+  if (!EnableTBAA)
+    return AliasAnalysis::getModRefInfo(CS1, CS2);
+
+  if (const MDNode *M1 =
+        CS1.getInstruction()->getMetadata(LLVMContext::MD_tbaa))
+    if (const MDNode *M2 =
+          CS2.getInstruction()->getMetadata(LLVMContext::MD_tbaa))
+      if (!Aliases(M1, M2))
+        return NoModRef;
+
+  return AliasAnalysis::getModRefInfo(CS1, CS2);
+}



From atrick at apple.com  Mon Oct 25 16:47:18 2010
From: atrick at apple.com (Andy Trick)
Date: Mon, 25 Oct 2010 14:47:18 -0700
Subject: [llvm-commits] [llvm] r117199 -
	/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
In-Reply-To: <20101023074614.DBDC72A6C12D@llvm.org>
References: <20101023074614.DBDC72A6C12D@llvm.org>
Message-ID: <6DA63D70-7074-47E8-A896-8A98BA20936A@apple.com>

This is the second time someone reported a warning that my build doesn't report. Of course, I want to keep the build warning-clean, but I'm not sure how to do better since the makefiles already set -Wall -pedantic (and several other -W's). Is this because I'm running a newer gcc (4.2.1) than linux developers? (gcc really should be smart enough to know this isn't a bug.)

-Andy

On Oct 23, 2010, at 12:46 AM, Chandler Carruth wrote:

> Author: chandlerc
> Date: Sat Oct 23 02:46:14 2010
> New Revision: 117199
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=117199&view=rev
> Log:
> Fix a likely bug in an assertion by adding parentheses around '||'. This bug
> was found by a GCC warning. ;]
> 
> Modified:
>    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117199&r1=117198&r2=117199&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Sat Oct 23 02:46:14 2010
> @@ -25,7 +25,7 @@
>   // Add this live virtual register to the union
>   LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
>                                                 &lvr, less_ptr<LiveInterval>());
> -  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR insertion");
> +  assert((pos == lvrs_.end() || *pos != &lvr) && "duplicate LVR insertion");
>   lvrs_.insert(pos, &lvr);
>   // Insert each of the virtual register's live segments into the map
>   SegmentIter segPos = segments_.begin();
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From stoklund at 2pi.dk  Mon Oct 25 16:58:26 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 25 Oct 2010 14:58:26 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h
	include/llvm/CodeGen/Passes.h lib/CodeGen/CMakeLists.txt
	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <20101022230915.AB8EF2A6C12C@llvm.org>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
Message-ID: <99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>


On Oct 22, 2010, at 4:09 PM, Andrew Trick wrote:

> Author: atrick
> Date: Fri Oct 22 18:09:15 2010
> New Revision: 117174
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=117174&view=rev
> Log:
> This is a prototype of an experimental register allocation
> framework. It's purpose is not to improve register allocation per se,
> but to make it easier to develop powerful live range splitting. I call
> it the basic allocator because it is as simple as a global allocator
> can be but provides the building blocks for sophisticated register
> allocation with live range splitting. 
> 
> A minimal implementation is provided that trivially spills whenever it
> runs out of registers. I'm checking in now to get high-level design
> and style feedback. I've only done minimal testing. The next step is
> implementing a "greedy" allocation algorithm that does some register
> reassignment and makes better splitting decisions.

Thanks, Andy! This is very promising.

Some comments below.

> Added: llvm/trunk/lib/CodeGen/RegAllocBase.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=117174&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocBase.h (added)
> +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Fri Oct 22 18:09:15 2010
> @@ -0,0 +1,179 @@
> +#ifndef LLVM_CODEGEN_REGALLOCBASE
> +#define LLVM_CODEGEN_REGALLOCBASE
> +
> +#include "LiveIntervalUnion.h"
> +#include "VirtRegMap.h"
> +#include "llvm/CodeGen/LiveIntervalAnalysis.h"
> +#include "llvm/Target/TargetRegisterInfo.h"
> +#include "llvm/ADT/OwningPtr.h"
> +#include <vector>
> +#include <queue>

Please try to limit the header file dependencies.

- When passing a SmallVector by reference, use SmallVectorImpl, see Spiller.h:

virtual unsigned selectOrSplit(LiveInterval &lvr,
                               SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;

- The rest of the unnecessary headers are pulled in by the premature abstraction of making allocatePhysRegs templated on the comparator.

Please drop the template, it will clean up the code significantly when you move the implementation into the .cpp file.

When/if we need the abstraction, we can use virtual functions instead:

  struct PriQueue {
    virtual void seed(LiveIntervals&) =0;
    virtual LiveInterval *get() =0;
  };

Since we will be doing significant work on each register, avoiding a virtual call is not worth the template ick.


> Added: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=117174&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (added)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Fri Oct 22 18:09:15 2010
> @@ -0,0 +1,193 @@

> +#include "llvm/CodeGen/LiveInterval.h"

Do you need this header? It looks like SlotIndexes.h is enough.

> +struct LiveSegment {
> +  bool operator<(const LiveSegment &ls) const {
> +    return start < ls.start || (start == ls.start && end < ls.end);
> +  }

I know that struct LiveRange does it too, but why the lexicographical compare? We are only dealing with disjoint segments, right?

This operator will be quite performance sensitive.

> +/// Compare a live virtual register segment to a LiveIntervalUnion segment.
> +inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
> +  return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
> +}

Please add a note that LiveSegment represents a half-open interval. I am actually planning on switching to closed intervals - it is more natural for callers since the low bits of SlotIndex are symbolic.

> +class LiveIntervalUnion {
> +public:
> +  // default ctor avoids placement new
> +  LiveIntervalUnion() : repReg_(0) {}
> +  
> +  void init(unsigned repReg) { repReg_ = repReg; }
> +
> +  SegmentIter begin() { return segments_.begin(); }
> +  SegmentIter end() { return segments_.end(); }
> +
> +  /// FIXME: !!!!!!!!!!! Keeps a non-const ref
> +  void unify(LiveInterval &lvr);
> +
> +  // FIXME: needed by RegAllocGreedy
> +  //void extract(const LiveInterval &li);

Please add comments to public functions.

I feel your pain on storing non-const references, but just add a comment promising not to change anything.


> Added: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117174&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (added)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Fri Oct 22 18:09:15 2010
> @@ -0,0 +1,167 @@
> +// Merge a LiveInterval's segments. Guarantee no overlaps.
> +void LiveIntervalUnion::unify(LiveInterval &lvr) {
> +  // Add this live virtual register to the union
> +  LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
> +                                                &lvr, less_ptr<LiveInterval>());
> +  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR insertion");

You should be even stricter here, and assert no overlaps.

> +  lvrs_.insert(pos, &lvr);
> +  // Insert each of the virtual register's live segments into the map
> +  SegmentIter segPos = segments_.begin();
> +  for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end();
> +       lvrI != lvrEnd; ++lvrI ) {
> +    LiveSegment segment(lvrI->start, lvrI->end, lvr);
> +    segPos = segments_.insert(segPos, segment);
> +    assert(*segPos == segment && "need equal val for equal key");
> +  }

You could save some space by coalescing touching segments here, but that can wait until we get a 'real' data structure.

> +typedef LiveIntervalUnion::SegmentIter SegmentIter;
> +SegmentIter upperBound(SegmentIter segBegin,
> +                       SegmentIter segEnd,
> +                       const LiveRange &lvrSeg)

Please use anonymous namespaces only for types. Functions should just be declared static.


> Added: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=117174&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (added)
> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Oct 22 18:09:15 2010
> @@ -0,0 +1,259 @@

> +class RABasic : public MachineFunctionPass, public RegAllocBase

Instead of using multiple inheritance, would it make sense for RegAllocBase to be a MachineFunctionPass? It seems that any register allocator using RegAllocBase would need the same pass initialization code and so on.

> +void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
> +  au.setPreservesCFG();
> +  au.addRequired<LiveIntervals>();
> +  au.addPreserved<SlotIndexes>();
> +  if (StrongPHIElim)
> +    au.addRequiredID(StrongPHIEliminationID);
> +  au.addRequiredTransitive<RegisterCoalescer>();
> +  au.addRequired<CalculateSpillWeights>();
> +  au.addRequired<LiveStacks>();
> +  au.addPreserved<LiveStacks>();
> +  au.addRequired<MachineLoopInfo>();
> +  au.addPreserved<MachineLoopInfo>();
> +  au.addRequired<VirtRegMap>();
> +  au.addPreserved<VirtRegMap>();
> +  DEBUG(au.addRequired<RenderMachineFunction>());
> +  MachineFunctionPass::getAnalysisUsage(au);
> +}

This would probably be the same for all register allocators using RegAllocBase.

> +void RABasic::releaseMemory() {
> +  spiller_.reset(0);
> +  RegAllocBase::releaseMemory();
> +}

Since register allocation is not an analysis used by other passes, you might as well release all memory at the bottom of runOnMachineFunction().

/jakob



From chandlerc at gmail.com  Mon Oct 25 17:12:20 2010
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 25 Oct 2010 15:12:20 -0700
Subject: [llvm-commits] [llvm] r117199 -
	/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
In-Reply-To: <6DA63D70-7074-47E8-A896-8A98BA20936A@apple.com>
References: <20101023074614.DBDC72A6C12D@llvm.org>
	<6DA63D70-7074-47E8-A896-8A98BA20936A@apple.com>
Message-ID: <AANLkTikGM3h_fzooaFK65AyRP2vUzV=qwBybZ-Zy3Rfe@mail.gmail.com>

On Mon, Oct 25, 2010 at 2:47 PM, Andy Trick <atrick at apple.com> wrote:

> This is the second time someone reported a warning that my build doesn't
> report. Of course, I want to keep the build warning-clean, but I'm not sure
> how to do better since the makefiles already set -Wall -pedantic (and
> several other -W's). Is this because I'm running a newer gcc (4.2.1) than
> linux developers?


Quite the opposite, 4.2.1 is much older than most Linux GCCs. GCC is on 4.4
now, and 4.5 isn't that far away.


> (gcc really should be smart enough to know this isn't a bug.)
>

The flow control may have been the same here, but in general it looked like
a bug. The only reason this wasn't a bug is because the string constant is
always true...


>
> -Andy
>
> On Oct 23, 2010, at 12:46 AM, Chandler Carruth wrote:
>
> > Author: chandlerc
> > Date: Sat Oct 23 02:46:14 2010
> > New Revision: 117199
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=117199&view=rev
> > Log:
> > Fix a likely bug in an assertion by adding parentheses around '||'. This
> bug
> > was found by a GCC warning. ;]
> >
> > Modified:
> >    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
> >
> > Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117199&r1=117198&r2=117199&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
> > +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Sat Oct 23 02:46:14 2010
> > @@ -25,7 +25,7 @@
> >   // Add this live virtual register to the union
> >   LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(),
> lvrs_.end(),
> >                                                 &lvr,
> less_ptr<LiveInterval>());
> > -  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR
> insertion");
> > +  assert((pos == lvrs_.end() || *pos != &lvr) && "duplicate LVR
> insertion");
> >   lvrs_.insert(pos, &lvr);
> >   // Insert each of the virtual register's live segments into the map
> >   SegmentIter segPos = segments_.begin();
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From dalej at apple.com  Mon Oct 25 17:17:05 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 25 Oct 2010 22:17:05 -0000
Subject: [llvm-commits] [llvm] r117322 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/stdcall-notailcall.ll
Message-ID: <20101025221705.C4B602A6C12C@llvm.org>

Author: johannes
Date: Mon Oct 25 17:17:05 2010
New Revision: 117322

URL: http://llvm.org/viewvc/llvm-project?rev=117322&view=rev
Log:
An stdcall function calling a non-stdcall function
cannot use tailcall.  PR 8461.


Added:
    llvm/trunk/test/CodeGen/X86/stdcall-notailcall.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=117322&r1=117321&r2=117322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 25 17:17:05 2010
@@ -2532,6 +2532,11 @@
     }
   }
 
+  // An stdcall caller is expected to clean up its arguments; the callee
+  // isn't going to do that.   PR 8461.
+  if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
+    return false;
+
   return true;
 }
 

Added: llvm/trunk/test/CodeGen/X86/stdcall-notailcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stdcall-notailcall.ll?rev=117322&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stdcall-notailcall.ll (added)
+++ llvm/trunk/test/CodeGen/X86/stdcall-notailcall.ll Mon Oct 25 17:17:05 2010
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=i386-apple-darwin11 -O2 < %s | FileCheck %s
+
+%struct.I = type { i32 (...)** }
+define x86_stdcallcc void @bar(%struct.I* nocapture %this) ssp align 2 {
+; CHECK: bar:
+; CHECK-NOT: jmp
+; CHECK: ret $4
+entry:
+  tail call void @foo()
+  ret void
+}
+
+declare void @foo()



From rafael.espindola at gmail.com  Mon Oct 25 17:26:55 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 25 Oct 2010 22:26:55 -0000
Subject: [llvm-commits] [llvm] r117323 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20101025222655.D62C72A6C12C@llvm.org>

Author: rafael
Date: Mon Oct 25 17:26:55 2010
New Revision: 117323

URL: http://llvm.org/viewvc/llvm-project?rev=117323&view=rev
Log:
Produce the headers directly in the Finish method. This allows us to use
the existing streamer methods that are endian safe.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117323&r1=117322&r2=117323&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Oct 25 17:26:55 2010
@@ -95,8 +95,6 @@
 
   class ObjectAttributeEmitter : public AttributeEmitter {
     MCObjectStreamer &Streamer;
-    size_t SectionStart;
-    size_t TagStart;
     StringRef CurrentVendor;
     SmallString<64> Contents;
 
@@ -116,20 +114,7 @@
 
       CurrentVendor = Vendor;
 
-      SectionStart = Contents.size();
-
-      // Length of the data for this vendor.
-      Contents.append(4, (char)0);
-
-      Contents.append(Vendor.begin(), Vendor.end());
-      Contents += 0;
-
-      Contents += ARMBuildAttrs::File;
-
-      TagStart = Contents.size();
-
-      // Length of the data for this tag.
-      Contents.append(4, (char)0);
+      assert(Contents.size() == 0);
     }
 
     void EmitAttribute(unsigned Attribute, unsigned Value) {
@@ -139,15 +124,24 @@
     }
 
     void Finish() {
-      size_t EndPos = Contents.size();
+      const size_t ContentsSize = Contents.size();
+
+      // Vendor size + Vendor name + '\0'
+      const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
 
-      // FIXME: endian.
-      *((uint32_t*)&Contents[SectionStart]) = EndPos - SectionStart;
+      // Tag + Tag Size
+      const size_t TagHeaderSize = 1 + 4;
 
-      // +1 since it includes the tag that came before it.
-      *((uint32_t*)&Contents[TagStart]) = EndPos - TagStart + 1;
+      Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
+      Streamer.EmitBytes(CurrentVendor, 0);
+      Streamer.EmitIntValue(0, 1); // '\0'
+
+      Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
+      Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
 
       Streamer.EmitBytes(Contents, 0);
+
+      Contents.clear();
     }
   };
 



From fjahanian at apple.com  Mon Oct 25 18:30:25 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Mon, 25 Oct 2010 23:30:25 -0000
Subject: [llvm-commits] [test-suite] r117325 -
	/test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp
Message-ID: <20101025233025.706DB2A6C12C@llvm.org>

Author: fjahanian
Date: Mon Oct 25 18:30:25 2010
New Revision: 117325

URL: http://llvm.org/viewvc/llvm-project?rev=117325&view=rev
Log:
Test for statement expressions with non-trivial
copy constructors. //rdar: //8540501.

Added:
    test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp

Added: test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp?rev=117325&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp (added)
+++ test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp Mon Oct 25 18:30:25 2010
@@ -0,0 +1,64 @@
+// rdar: //8540501
+extern "C" int printf(...);
+extern "C" void abort();
+
+struct A
+{
+  int i;
+  A (int j) : i(j) {printf("this = %p A(%d)\n", this, j);}
+  A (const A &j) : i(j.i) {printf("this = %p const A&(%d)\n", this, i);}
+  A& operator= (const A &j) { i = j.i; abort(); return *this; }
+  ~A() { printf("this = %p ~A(%d)\n", this, i); }
+};
+
+struct B
+{
+  int i;
+  B (const A& a) { i = a.i; }
+  B() {printf("this = %p B()\n", this);}
+  B (const B &j) : i(j.i) {printf("this = %p const B&(%d)\n", this, i);}
+  ~B() { printf("this = %p ~B(%d)\n", this, i); }
+};
+
+A foo(int j)
+{
+  return ({ j ? A(1) : A(0); });
+}
+
+
+void foo2()
+{
+  A b = ({ A a(1); A a1(2); A a2(3); a1; a2; a; });
+  if (b.i != 1)
+    abort(); 
+  A c = ({ A a(1); A a1(2); A a2(3); a1; a2; a; A a3(4); a2; a3; });
+  if (c.i != 4)
+    abort(); 
+}
+
+void foo3()
+{
+  const A &b = ({ A a(1); a; });
+  if (b.i != 1)
+    abort();
+}
+
+void foo4()
+{
+// CHECK: call void @_ZN1AC1Ei
+// CHECK: call void @_ZN1AC1ERKS_
+// CHECK: call void @_ZN1AD1Ev
+// CHECK: call void @_ZN1BC1ERK1A
+// CHECK: call void @_ZN1AD1Ev
+  const B &b = ({ A a(1); a; });
+  if (b.i != 1)
+    abort();
+}
+
+int main()
+{
+  foo2();
+  foo3();
+  foo4();
+  return foo(1).i-1;
+}



From resistor at mac.com  Mon Oct 25 18:35:36 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 23:35:36 -0000
Subject: [llvm-commits] [llvm] r117326 -
	/llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll
Message-ID: <20101025233536.A084A2A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 18:35:36 2010
New Revision: 117326

URL: http://llvm.org/viewvc/llvm-project?rev=117326&view=rev
Log:
Tests for NEON encoding of vmin.

Added:
    llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll?rev=117326&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll Mon Oct 25 18:35:36 2010
@@ -0,0 +1,147 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8>  @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vmins_8xi8
+define <8 x i8> @vmins_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vmin.s8	d16, d16, d17           @ encoding: [0xb1,0x06,0x40,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vmins_4xi16
+define <4 x i16> @vmins_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vmin.s16	d16, d16, d17   @ encoding: [0xb1,0x06,0x50,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vmins_2xi32
+define <2 x i32> @vmins_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vmin.s32	d16, d16, d17   @ encoding: [0xb1,0x06,0x60,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vminu_8xi8
+define <8 x i8> @vminu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vmin.u8	d16, d16, d17           @ encoding: [0xb1,0x06,0x40,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vminu_4xi16
+define <4 x i16> @vminu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vmin.u16	d16, d16, d17   @ encoding: [0xb1,0x06,0x50,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vminu_2xi32
+define <2 x i32> @vminu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vmin.u32	d16, d16, d17   @ encoding: [0xb1,0x06,0x60,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+; CHECK: vmin_2xfloat
+define <2 x float> @vmin_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vmin.f32	d16, d16, d17   @ encoding: [0xa1,0x0f,0x60,0xf2]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; CHECK: vmins_16xi8
+define <16 x i8> @vmins_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vmin.s8	q8, q8, q9              @ encoding: [0xf2,0x06,0x40,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vmins_8xi16
+define <8 x i16> @vmins_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vmin.s16	q8, q8, q9      @ encoding: [0xf2,0x06,0x50,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vmins_4xi32
+define <4 x i32> @vmins_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vmin.s32	q8, q8, q9      @ encoding: [0xf2,0x06,0x60,0xf2]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; CHECK: vminu_16xi8
+define <16 x i8> @vminu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vmin.u8	q8, q8, q9              @ encoding: [0xf2,0x06,0x40,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vminu_8xi16
+define <8 x i16> @vminu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vmin.u16	q8, q8, q9      @ encoding: [0xf2,0x06,0x50,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vminu_4xi32
+define <4 x i32> @vminu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vmin.u32	q8, q8, q9      @ encoding: [0xf2,0x06,0x60,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vmin_4xfloat
+define <4 x float> @vmin_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vmin.f32	q8, q8, q9      @ encoding: [0xe2,0x0f,0x60,0xf2]
+	%tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x float> %tmp3
+}



From matthewbg at google.com  Mon Oct 25 18:44:15 2010
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Mon, 25 Oct 2010 16:44:15 -0700
Subject: [llvm-commits] [PATCH] Guard new STATISTICs with #ifndef NDEBUG
Message-ID: <AANLkTin6q+yJ237_cx5Ht3W0b8N0dit4K6=+Rtvf9=TX@mail.gmail.com>

With -Wall -Werror -DNDEBUG, gcc complains:
lib/CodeGen/AsmPrinter/DwarfDebug.cpp:56: error: 'BlocksWithoutLineNo'
defined but not used [-Wunused-variable]
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:59: error:
'NumBBWithOutOfOrderLineInfo' defined but not used [-Wunused-variable]
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:61: error:
'NumMBBWithOutOfOrderLineInfo' defined but not used
[-Wunused-variable]

-Matt
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From resistor at mac.com  Mon Oct 25 18:45:34 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 25 Oct 2010 23:45:34 -0000
Subject: [llvm-commits] [llvm] r117327 -
	/llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll
Message-ID: <20101025234534.CBDB12A6C12C@llvm.org>

Author: resistor
Date: Mon Oct 25 18:45:34 2010
New Revision: 117327

URL: http://llvm.org/viewvc/llvm-project?rev=117327&view=rev
Log:
Tests for NEON encoding of vmax.

Modified:
    llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll?rev=117327&r1=117326&r2=117327&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-minmax-encoding.ll Mon Oct 25 18:45:34 2010
@@ -145,3 +145,149 @@
 	%tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
 	ret <4 x float> %tmp3
 }
+
+declare <8 x i8>  @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vmaxs_8xi8
+define <8 x i8> @vmaxs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vmax.s8	d16, d16, d17           @ encoding: [0xa1,0x06,0x40,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vmaxs_4xi16
+define <4 x i16> @vmaxs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vmax.s16	d16, d16, d17   @ encoding: [0xa1,0x06,0x50,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vmaxs_2xi32
+define <2 x i32> @vmaxs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vmax.s32	d16, d16, d17   @ encoding: [0xa1,0x06,0x60,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vmaxu_8xi8
+define <8 x i8> @vmaxu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vmax.u8	d16, d16, d17           @ encoding: [0xa1,0x06,0x40,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vmaxu_4xi16
+define <4 x i16> @vmaxu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vmax.u16	d16, d16, d17   @ encoding: [0xa1,0x06,0x50,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vmaxu_2xi32
+define <2 x i32> @vmaxu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vmax.u32	d16, d16, d17   @ encoding: [0xa1,0x06,0x60,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+; CHECK: vmax_2xfloat
+define <2 x float> @vmax_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vmax.f32	d16, d16, d17   @ encoding: [0xa1,0x0f,0x40,0xf2]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; CHECK: vmaxs_16xi8
+define <16 x i8> @vmaxs_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vmax.s8	q8, q8, q9              @ encoding: [0xe2,0x06,0x40,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vmaxs_8xi16
+define <8 x i16> @vmaxs_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vmax.s16	q8, q8, q9      @ encoding: [0xe2,0x06,0x50,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vmaxs_4xi32
+define <4 x i32> @vmaxs_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vmax.s32	q8, q8, q9      @ encoding: [0xe2,0x06,0x60,0xf2]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; CHECK: vmaxu_16xi8
+define <16 x i8> @vmaxu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vmax.u8	q8, q8, q9              @ encoding: [0xe2,0x06,0x40,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vmaxu_8xi16
+define <8 x i16> @vmaxu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vmax.u16	q8, q8, q9      @ encoding: [0xe2,0x06,0x50,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vmaxu_4xi32
+define <4 x i32> @vmaxu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vmax.u32	q8, q8, q9      @ encoding: [0xe2,0x06,0x60,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vmax_4xfloat
+define <4 x float> @vmax_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vmax.f32	q8, q8, q9      @ encoding: [0xe2,0x0f,0x40,0xf2]
+	%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x float> %tmp3
+}



From evan.cheng at apple.com  Mon Oct 25 18:56:21 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 25 Oct 2010 23:56:21 -0000
Subject: [llvm-commits] [llvm] r117329 -
	/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
Message-ID: <20101025235621.764F82A6C12C@llvm.org>

Author: evancheng
Date: Mon Oct 25 18:56:21 2010
New Revision: 117329

URL: http://llvm.org/viewvc/llvm-project?rev=117329&view=rev
Log:
Neuter r117193 as it causes significant post-ra scheduler compile time regression.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=117329&r1=117328&r2=117329&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Mon Oct 25 18:56:21 2010
@@ -169,8 +169,8 @@
   } else {
     // For others, e.g. fallthrough, conditional branch, assume the exit
     // uses all the registers.
-    for (int i = 0, e = TRI->getNumRegs(); i != e; ++i)
-      Uses[i].push_back(&ExitSU);
+    // FIXME: This causes too much compile time regression. We need to compute
+    // liveout instead.
   }
 }
 



From bob.wilson at apple.com  Mon Oct 25 19:02:19 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 26 Oct 2010 00:02:19 -0000
Subject: [llvm-commits] [llvm] r117331 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
Message-ID: <20101026000219.4ED242A6C12C@llvm.org>

Author: bwilson
Date: Mon Oct 25 19:02:19 2010
New Revision: 117331

URL: http://llvm.org/viewvc/llvm-project?rev=117331&view=rev
Log:
Tidy up redundant check.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=117331&r1=117330&r2=117331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Mon Oct 25 19:02:19 2010
@@ -328,7 +328,7 @@
                                          unsigned NumInstrs,
                                          float Probability,
                                          float Confidence) const {
-    return NumInstrs && NumInstrs == 1;
+    return NumInstrs == 1;
   }
 
   /// AnalyzeCompare - For a comparison instruction, return the source register



From bob.wilson at apple.com  Mon Oct 25 19:02:21 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 26 Oct 2010 00:02:21 -0000
Subject: [llvm-commits] [llvm] r117332 -
	/llvm/trunk/lib/CodeGen/IfConversion.cpp
Message-ID: <20101026000221.7D6E32A6C12D@llvm.org>

Author: bwilson
Date: Mon Oct 25 19:02:21 2010
New Revision: 117332

URL: http://llvm.org/viewvc/llvm-project?rev=117332&view=rev
Log:
Change if-conversion to keep track of the extra cost due to microcoded
instructions separately from the count of non-predicated instructions.  The
instruction count is used in places to determine how many instructions to
copy, predicate, etc. and things get confused if that count includes the
extra cost for microcoded ops.

Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=117332&r1=117331&r2=117332&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Oct 25 19:02:21 2010
@@ -93,6 +93,7 @@
     /// ClobbersPred    - True if BB could modify predicates (e.g. has
     ///                   cmp, call, etc.)
     /// NonPredSize     - Number of non-predicated instructions.
+    /// ExtraCost       - Extra cost for microcoded instructions.
     /// BB              - Corresponding MachineBasicBlock.
     /// TrueBB / FalseBB- See AnalyzeBranch().
     /// BrCond          - Conditions for end of block conditional branches.
@@ -108,6 +109,7 @@
       bool CannotBeCopied  : 1;
       bool ClobbersPred    : 1;
       unsigned NonPredSize;
+      unsigned ExtraCost;
       MachineBasicBlock *BB;
       MachineBasicBlock *TrueBB;
       MachineBasicBlock *FalseBB;
@@ -117,7 +119,7 @@
                  IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false),
                  HasFallThrough(false), IsUnpredicable(false),
                  CannotBeCopied(false), ClobbersPred(false), NonPredSize(0),
-                 BB(0), TrueBB(0), FalseBB(0) {}
+                 ExtraCost(0), BB(0), TrueBB(0), FalseBB(0) {}
     };
 
     /// IfcvtToken - Record information about pending if-conversions to attempt:
@@ -652,6 +654,7 @@
 
   // Then scan all the instructions.
   BBI.NonPredSize = 0;
+  BBI.ExtraCost = 0;
   BBI.ClobbersPred = false;
   for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
        I != E; ++I) {
@@ -667,8 +670,10 @@
 
     if (!isCondBr) {
       if (!isPredicated) {
+        BBI.NonPredSize++;
         unsigned NumOps = TII->getNumMicroOps(&*I, InstrItins);
-        BBI.NonPredSize += NumOps;
+        if (NumOps > 1)
+          BBI.ExtraCost += NumOps-1;
       } else if (!AlreadyPredicated) {
         // FIXME: This instruction is already predicated before the
         // if-conversion pass. It's probably something like a conditional move.
@@ -815,8 +820,10 @@
   }
   
   if (CanRevCond && ValidDiamond(TrueBBI, FalseBBI, Dups, Dups2) &&
-      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize - (Dups + Dups2),
-                         *FalseBBI.BB, FalseBBI.NonPredSize - (Dups + Dups2),
+      MeetIfcvtSizeLimit(*TrueBBI.BB, (TrueBBI.NonPredSize - (Dups + Dups2) +
+                                       TrueBBI.ExtraCost),
+                         *FalseBBI.BB, (FalseBBI.NonPredSize - (Dups + Dups2) +
+                                        FalseBBI.ExtraCost),
                          Prediction, Confidence) &&
       FeasibilityAnalysis(TrueBBI, BBI.BrCond) &&
       FeasibilityAnalysis(FalseBBI, RevCond)) {
@@ -834,7 +841,7 @@
   }
 
   if (ValidTriangle(TrueBBI, FalseBBI, false, Dups, Prediction, Confidence) &&
-      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize,
+      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
                          Prediction, Confidence) &&
       FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
     // Triangle:
@@ -849,7 +856,7 @@
   }
 
   if (ValidTriangle(TrueBBI, FalseBBI, true, Dups, Prediction, Confidence) &&
-      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize,
+      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
                          Prediction, Confidence) &&
       FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
     Tokens.push_back(new IfcvtToken(BBI, ICTriangleRev, TNeedSub, Dups));
@@ -857,7 +864,7 @@
   }
 
   if (ValidSimple(TrueBBI, Dups, Prediction, Confidence) &&
-      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize,
+      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
                          Prediction, Confidence) &&
       FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
     // Simple (split, no rejoin):
@@ -875,7 +882,8 @@
     // Try the other path...
     if (ValidTriangle(FalseBBI, TrueBBI, false, Dups,
                       1.0-Prediction, Confidence) &&
-        MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize,
+        MeetIfcvtSizeLimit(*FalseBBI.BB,
+                           FalseBBI.NonPredSize + FalseBBI.ExtraCost,
                            1.0-Prediction, Confidence) &&
         FeasibilityAnalysis(FalseBBI, RevCond, true)) {
       Tokens.push_back(new IfcvtToken(BBI, ICTriangleFalse, FNeedSub, Dups));
@@ -884,7 +892,8 @@
 
     if (ValidTriangle(FalseBBI, TrueBBI, true, Dups,
                       1.0-Prediction, Confidence) &&
-        MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize,
+        MeetIfcvtSizeLimit(*FalseBBI.BB,
+                           FalseBBI.NonPredSize + FalseBBI.ExtraCost,
                            1.0-Prediction, Confidence) &&
         FeasibilityAnalysis(FalseBBI, RevCond, true, true)) {
       Tokens.push_back(new IfcvtToken(BBI, ICTriangleFRev, FNeedSub, Dups));
@@ -892,7 +901,8 @@
     }
 
     if (ValidSimple(FalseBBI, Dups, 1.0-Prediction, Confidence) &&
-        MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize,
+        MeetIfcvtSizeLimit(*FalseBBI.BB,
+                           FalseBBI.NonPredSize + FalseBBI.ExtraCost,
                            1.0-Prediction, Confidence) &&
         FeasibilityAnalysis(FalseBBI, RevCond)) {
       Tokens.push_back(new IfcvtToken(BBI, ICSimpleFalse, FNeedSub, Dups));
@@ -1422,8 +1432,10 @@
 
     MachineInstr *MI = MF.CloneMachineInstr(I);
     ToBBI.BB->insert(ToBBI.BB->end(), MI);
+    ToBBI.NonPredSize++;
     unsigned NumOps = TII->getNumMicroOps(MI, InstrItins);
-    ToBBI.NonPredSize += NumOps;
+    if (NumOps > 1)
+      ToBBI.ExtraCost += NumOps-1;
 
     if (!TII->isPredicated(I) && !MI->isDebugValue()) {
       if (!TII->PredicateInstruction(MI, Cond)) {
@@ -1497,7 +1509,9 @@
   FromBBI.Predicate.clear();
 
   ToBBI.NonPredSize += FromBBI.NonPredSize;
+  ToBBI.ExtraCost += FromBBI.ExtraCost;
   FromBBI.NonPredSize = 0;
+  FromBBI.ExtraCost = 0;
 
   ToBBI.ClobbersPred |= FromBBI.ClobbersPred;
   ToBBI.HasFallThrough = FromBBI.HasFallThrough;



From bob.wilson at apple.com  Mon Oct 25 19:02:24 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 26 Oct 2010 00:02:24 -0000
Subject: [llvm-commits] [llvm] r117333 - in /llvm/trunk:
 lib/CodeGen/IfConversion.cpp test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
 test/MC/ARM/simple-fp-encoding.ll
Message-ID: <20101026000224.D4ADD2A6C12E@llvm.org>

Author: bwilson
Date: Mon Oct 25 19:02:24 2010
New Revision: 117333

URL: http://llvm.org/viewvc/llvm-project?rev=117333&view=rev
Log:
When the "true" and "false" blocks of a diamond if-conversion are the same,
do not double-count the duplicate instructions by counting once from the
beginning and again from the end.  Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end.  Radar 8589805.

This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction.  That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp
    llvm/trunk/test/MC/ARM/simple-fp-encoding.ll

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=117333&r1=117332&r2=117333&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Oct 25 19:02:24 2010
@@ -520,18 +520,6 @@
   return TExit && TExit == FalseBBI.BB;
 }
 
-static
-MachineBasicBlock::iterator firstNonBranchInst(MachineBasicBlock *BB,
-                                               const TargetInstrInfo *TII) {
-  MachineBasicBlock::iterator I = BB->end();
-  while (I != BB->begin()) {
-    --I;
-    if (!I->getDesc().isBranch())
-      break;
-  }
-  return I;
-}
-
 /// ValidDiamond - Returns true if the 'true' and 'false' blocks (along
 /// with their common predecessor) forms a valid diamond shape for ifcvt.
 bool IfConverter::ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
@@ -560,64 +548,70 @@
       (TrueBBI.ClobbersPred && FalseBBI.ClobbersPred))
     return false;
 
-  MachineBasicBlock::iterator TI = TrueBBI.BB->begin();
-  MachineBasicBlock::iterator FI = FalseBBI.BB->begin();
+  // Count duplicate instructions at the beginning of the true and false blocks.
+  MachineBasicBlock::iterator TIB = TrueBBI.BB->begin();
+  MachineBasicBlock::iterator FIB = FalseBBI.BB->begin();
   MachineBasicBlock::iterator TIE = TrueBBI.BB->end();
   MachineBasicBlock::iterator FIE = FalseBBI.BB->end();
-  // Skip dbg_value instructions
-  while (TI != TIE && TI->isDebugValue())
-    ++TI;
-  while (FI != FIE && FI->isDebugValue())
-    ++FI;
-  while (TI != TIE && FI != FIE) {
+  while (TIB != TIE && FIB != FIE) {
     // Skip dbg_value instructions. These do not count.
-    if (TI->isDebugValue()) {
-      while (TI != TIE && TI->isDebugValue())
-        ++TI;
-      if (TI == TIE)
+    if (TIB->isDebugValue()) {
+      while (TIB != TIE && TIB->isDebugValue())
+        ++TIB;
+      if (TIB == TIE)
         break;
     }
-    if (FI->isDebugValue()) {
-      while (FI != FIE && FI->isDebugValue())
-        ++FI;
-      if (FI == FIE)
+    if (FIB->isDebugValue()) {
+      while (FIB != FIE && FIB->isDebugValue())
+        ++FIB;
+      if (FIB == FIE)
         break;
     }
-    if (!TI->isIdenticalTo(FI))
+    if (!TIB->isIdenticalTo(FIB))
       break;
     ++Dups1;
-    ++TI;
-    ++FI;
+    ++TIB;
+    ++FIB;
   }
 
-  TI = firstNonBranchInst(TrueBBI.BB, TII);
-  FI = firstNonBranchInst(FalseBBI.BB, TII);
-  MachineBasicBlock::iterator TIB = TrueBBI.BB->begin();
-  MachineBasicBlock::iterator FIB = FalseBBI.BB->begin();
-  // Skip dbg_value instructions at end of the bb's.
-  while (TI != TIB && TI->isDebugValue())
-    --TI;
-  while (FI != FIB && FI->isDebugValue())
-    --FI;
-  while (TI != TIB && FI != FIB) {
+  // Now, in preparation for counting duplicate instructions at the ends of the
+  // blocks, move the end iterators up past any branch instructions.
+  while (TIE != TIB) {
+    --TIE;
+    if (!TIE->getDesc().isBranch())
+      break;
+  }
+  while (FIE != FIB) {
+    --FIE;
+    if (!FIE->getDesc().isBranch())
+      break;
+  }
+
+  // If Dups1 includes all of a block, then don't count duplicate
+  // instructions at the end of the blocks.
+  if (TIB == TIE || FIB == FIE)
+    return true;
+
+  // Count duplicate instructions at the ends of the blocks.
+  while (TIE != TIB && FIE != FIB) {
     // Skip dbg_value instructions. These do not count.
-    if (TI->isDebugValue()) {
-      while (TI != TIB && TI->isDebugValue())
-        --TI;
-      if (TI == TIB)
+    if (TIE->isDebugValue()) {
+      while (TIE != TIB && TIE->isDebugValue())
+        --TIE;
+      if (TIE == TIB)
         break;
     }
-    if (FI->isDebugValue()) {
-      while (FI != FIB && FI->isDebugValue())
-        --FI;
-      if (FI == FIB)
+    if (FIE->isDebugValue()) {
+      while (FIE != FIB && FIE->isDebugValue())
+        --FIE;
+      if (FIE == FIB)
         break;
     }
-    if (!TI->isIdenticalTo(FI))
+    if (!TIE->isIdenticalTo(FIE))
       break;
     ++Dups2;
-    --TI;
-    --FI;
+    --TIE;
+    --FIE;
   }
 
   return true;

Added: llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll?rev=117333&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll Mon Oct 25 19:02:24 2010
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=arm1136jf-s | FileCheck %s
+; Radar 8589805: Counting the number of microcoded operations, such as for an
+; LDM instruction, was causing an assertion failure because the microop count
+; was being treated as an instruction count.
+
+; CHECK: ldmia
+; CHECK: ldmia
+; CHECK: ldmia
+; CHECK: ldmia
+
+define i32 @test(i32 %x) {
+entry:
+  %0 = tail call signext i16 undef(i32* undef)
+  switch i32 undef, label %bb3 [
+    i32 0, label %bb4
+    i32 1, label %bb1
+    i32 2, label %bb2
+  ]
+
+bb1:
+  ret i32 1
+
+bb2:
+  ret i32 2
+
+bb3:
+  ret i32 1
+
+bb4:
+  ret i32 3
+}

Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=117333&r1=117332&r2=117333&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.ll Mon Oct 25 19:02:24 2010
@@ -349,16 +349,16 @@
   ret double %a
 }
 
-define float @f99(float %a, i32 %i) nounwind readnone {
+define float @f99(float %a, float %b, i32 %i) nounwind readnone {
 entry:
   %cmp = icmp eq i32 %i, 3
   br i1 %cmp, label %if.end, label %return
 
 if.end:                                           ; preds = %entry
 ; CHECK: f99
-; CHECK: vmovne r0, s0               @ encoding: [0x10,0x0a,0x10,0x1e]
-  %sub = fsub float -0.000000e+00, %a
-  ret float %sub
+; CHECK: vmovne s0, r0               @ encoding: [0x10,0x0a,0x00,0x1e]
+; CHECK: vmoveq s0, r1               @ encoding: [0x10,0x1a,0x00,0x0e]
+  ret float %b
 
 return:                                           ; preds = %entry
   ret float %a



From stoklund at 2pi.dk  Mon Oct 25 19:11:33 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 00:11:33 -0000
Subject: [llvm-commits] [llvm] r117337 - in /llvm/trunk:
 include/llvm/CodeGen/Passes.h lib/CodeGen/LiveStackAnalysis.cpp
 lib/CodeGen/RegAllocLinearScan.cpp lib/CodeGen/Spiller.cpp
Message-ID: <20101026001133.E75332A6C12C@llvm.org>

Author: stoklund
Date: Mon Oct 25 19:11:33 2010
New Revision: 117337

URL: http://llvm.org/viewvc/llvm-project?rev=117337&view=rev
Log:
Make the spiller responsible for updating the LiveStacks analysis.

Modified:
    llvm/trunk/include/llvm/CodeGen/Passes.h
    llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
    llvm/trunk/lib/CodeGen/Spiller.cpp

Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=117337&r1=117336&r2=117337&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Mon Oct 25 19:11:33 2010
@@ -66,6 +66,9 @@
 
   extern char &PreAllocSplittingID;
 
+  /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
+  extern char &LiveStacksID;
+
   /// SimpleRegisterCoalescing pass.  Aggressively coalesces every register
   /// copy it can.
   ///

Modified: llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp?rev=117337&r1=117336&r2=117337&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp Mon Oct 25 19:11:33 2010
@@ -28,6 +28,8 @@
 INITIALIZE_PASS(LiveStacks, "livestacks",
                 "Live Stack Slot Analysis", false, false)
 
+char &llvm::LiveStacksID = LiveStacks::ID;
+
 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesAll();
   AU.addPreserved<SlotIndexes>();

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=117337&r1=117336&r2=117337&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Mon Oct 25 19:11:33 2010
@@ -18,7 +18,6 @@
 #include "llvm/Function.h"
 #include "llvm/CodeGen/CalcSpillWeights.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/LiveStackAnalysis.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
@@ -138,7 +137,6 @@
     BitVector allocatableRegs_;
     BitVector reservedRegs_;
     LiveIntervals* li_;
-    LiveStacks* ls_;
     MachineLoopInfo *loopInfo;
 
     /// handled_ - Intervals are added to the handled_ set in the order of their
@@ -204,8 +202,8 @@
       AU.addRequired<CalculateSpillWeights>();
       if (PreSplitIntervals)
         AU.addRequiredID(PreAllocSplittingID);
-      AU.addRequired<LiveStacks>();
-      AU.addPreserved<LiveStacks>();
+      AU.addRequiredID(LiveStacksID);
+      AU.addPreservedID(LiveStacksID);
       AU.addRequired<MachineLoopInfo>();
       AU.addPreserved<MachineLoopInfo>();
       AU.addRequired<VirtRegMap>();
@@ -498,7 +496,6 @@
   allocatableRegs_ = tri_->getAllocatableSet(fn);
   reservedRegs_ = tri_->getReservedRegs(fn);
   li_ = &getAnalysis<LiveIntervals>();
-  ls_ = &getAnalysis<LiveStacks>();
   loopInfo = &getAnalysis<MachineLoopInfo>();
 
   // We don't run the coalescer here because we have no reason to
@@ -658,8 +655,6 @@
 
   // Look for physical registers that end up not being allocated even though
   // register allocator had to spill other registers in its register class.
-  if (ls_->getNumIntervals() == 0)
-    return;
   if (!vrm_->FindUnusedRegisters(li_))
     return;
 }
@@ -804,30 +799,6 @@
   }
 }
 
-/// addStackInterval - Create a LiveInterval for stack if the specified live
-/// interval has been spilled.
-static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
-                             LiveIntervals *li_,
-                             MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
-  int SS = vrm_.getStackSlot(cur->reg);
-  if (SS == VirtRegMap::NO_STACK_SLOT)
-    return;
-
-  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
-  LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
-
-  VNInfo *VNI;
-  if (SI.hasAtLeastOneValue())
-    VNI = SI.getValNumInfo(0);
-  else
-    VNI = SI.getNextValue(SlotIndex(), 0,
-                          ls_->getVNInfoAllocator());
-
-  LiveInterval &RI = li_->getInterval(cur->reg);
-  // FIXME: This may be overly conservative.
-  SI.MergeRangesInAsValue(RI, VNI);
-}
-
 /// getConflictWeight - Return the number of conflicts between cur
 /// live interval and defs and uses of Reg weighted by loop depthes.
 static
@@ -1244,7 +1215,6 @@
     spiller_->spill(cur, added, spillIs);
 
     std::sort(added.begin(), added.end(), LISorter());
-    addStackInterval(cur, ls_, li_, mri_, *vrm_);
     if (added.empty())
       return;  // Early exit if all spills were folded.
 
@@ -1319,7 +1289,6 @@
     if (sli->beginIndex() < earliestStart)
       earliestStart = sli->beginIndex();
     spiller_->spill(sli, added, spillIs);
-    addStackInterval(sli, ls_, li_, mri_, *vrm_);
     spilled.insert(sli->reg);
   }
 

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=117337&r1=117336&r2=117337&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Mon Oct 25 19:11:33 2010
@@ -12,6 +12,7 @@
 #include "Spiller.h"
 #include "VirtRegMap.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveStackAnalysis.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -195,13 +196,17 @@
 /// Falls back on LiveIntervals::addIntervalsForSpills.
 class StandardSpiller : public Spiller {
 protected:
+  MachineFunction *mf;
   LiveIntervals *lis;
+  LiveStacks *lss;
   MachineLoopInfo *loopInfo;
   VirtRegMap *vrm;
 public:
   StandardSpiller(MachineFunctionPass &pass, MachineFunction &mf,
                   VirtRegMap &vrm)
-    : lis(&pass.getAnalysis<LiveIntervals>()),
+    : mf(&mf),
+      lis(&pass.getAnalysis<LiveIntervals>()),
+      lss(&pass.getAnalysis<LiveStacks>()),
       loopInfo(pass.getAnalysisIfAvailable<MachineLoopInfo>()),
       vrm(&vrm) {}
 
@@ -212,6 +217,16 @@
     std::vector<LiveInterval*> added =
       lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
     newIntervals.insert(newIntervals.end(), added.begin(), added.end());
+
+    // Update LiveStacks.
+    int SS = vrm->getStackSlot(li->reg);
+    if (SS == VirtRegMap::NO_STACK_SLOT)
+      return;
+    const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(li->reg);
+    LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
+    if (!SI.hasAtLeastOneValue())
+      SI.getNextValue(SlotIndex(), 0, lss->getVNInfoAllocator());
+    SI.MergeRangesInAsValue(*li, SI.getValNumInfo(0));
   }
 };
 



From stoklund at 2pi.dk  Mon Oct 25 19:11:36 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 00:11:36 -0000
Subject: [llvm-commits] [llvm] r117338 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20101026001136.149692A6C12D@llvm.org>

Author: stoklund
Date: Mon Oct 25 19:11:35 2010
New Revision: 117338

URL: http://llvm.org/viewvc/llvm-project?rev=117338&view=rev
Log:
InlineSpiller can also update LiveStacks.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=117338&r1=117337&r2=117338&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Mon Oct 25 19:11:35 2010
@@ -18,6 +18,7 @@
 #include "SplitKit.h"
 #include "VirtRegMap.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveStackAnalysis.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
@@ -34,6 +35,7 @@
   MachineFunctionPass &pass_;
   MachineFunction &mf_;
   LiveIntervals &lis_;
+  LiveStacks &lss_;
   MachineLoopInfo &loops_;
   VirtRegMap &vrm_;
   MachineFrameInfo &mfi_;
@@ -61,6 +63,7 @@
     : pass_(pass),
       mf_(mf),
       lis_(pass.getAnalysis<LiveIntervals>()),
+      lss_(pass.getAnalysis<LiveStacks>()),
       loops_(pass.getAnalysis<MachineLoopInfo>()),
       vrm_(vrm),
       mfi_(*mf.getFrameInfo()),
@@ -355,6 +358,12 @@
   rc_ = mri_.getRegClass(edit.getReg());
   stackSlot_ = edit.assignStackSlot(vrm_);
 
+  // Update LiveStacks now that we are committed to spilling.
+  LiveInterval &stacklvr = lss_.getOrCreateInterval(stackSlot_, rc_);
+  if (!stacklvr.hasAtLeastOneValue())
+    stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator());
+  stacklvr.MergeRangesInAsValue(edit_->getParent(), stacklvr.getValNumInfo(0));
+
   // Iterate over instructions using register.
   for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(edit.getReg());
        MachineInstr *MI = RI.skipInstruction();) {



From nicholas at mxc.ca  Mon Oct 25 19:51:57 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 26 Oct 2010 00:51:57 -0000
Subject: [llvm-commits] [llvm] r117345 - in /llvm/trunk/lib/CodeGen:
 AsmPrinter/DwarfDebug.cpp SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20101026005157.7CC492A6C12C@llvm.org>

Author: nicholas
Date: Mon Oct 25 19:51:57 2010
New Revision: 117345

URL: http://llvm.org/viewvc/llvm-project?rev=117345&view=rev
Log:
For statistics that are only used in functions declared in !NDEBUG, wrap the
declarations in !NDEBUG to avoid -Wunused-variable warnings. Patch by
Matt Beaumont-Gay!

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=117345&r1=117344&r2=117345&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 25 19:51:57 2010
@@ -53,7 +53,9 @@
      cl::desc("Make an absense of debug location information explicit."),
      cl::init(false));
 
+#ifndef NDEBUG
 STATISTIC(BlocksWithoutLineNo, "Number of blocks without any line number");
+#endif
 
 namespace {
   const char *DWARFGroupName = "DWARF Emission";

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=117345&r1=117344&r2=117345&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 25 19:51:57 2010
@@ -56,10 +56,13 @@
 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
+
+#ifndef NDEBUG
 STATISTIC(NumBBWithOutOfOrderLineInfo, 
           "Number of blocks with out of order line number info");
 STATISTIC(NumMBBWithOutOfOrderLineInfo, 
           "Number of machine blocks with out of order line number info");
+#endif
 
 static cl::opt<bool>
 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,



From nlewycky at google.com  Mon Oct 25 19:55:08 2010
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 25 Oct 2010 17:55:08 -0700
Subject: [llvm-commits] [PATCH] Guard new STATISTICs with #ifndef NDEBUG
In-Reply-To: <AANLkTin6q+yJ237_cx5Ht3W0b8N0dit4K6=+Rtvf9=TX@mail.gmail.com>
References: <AANLkTin6q+yJ237_cx5Ht3W0b8N0dit4K6=+Rtvf9=TX@mail.gmail.com>
Message-ID: <AANLkTi==B0FhWbNFwmPAYpXeWHYdF6RxjtQ_iS+LzXDT@mail.gmail.com>

Committed in revision 117345. Thanks for the patch!

Nick

On 25 October 2010 16:44, Matt Beaumont-Gay <matthewbg at google.com> wrote:

> With -Wall -Werror -DNDEBUG, gcc complains:
> lib/CodeGen/AsmPrinter/DwarfDebug.cpp:56: error: 'BlocksWithoutLineNo'
> defined but not used [-Wunused-variable]
> lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:59: error:
> 'NumBBWithOutOfOrderLineInfo' defined but not used [-Wunused-variable]
> lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:61: error:
> 'NumMBBWithOutOfOrderLineInfo' defined but not used
> [-Wunused-variable]
>
> -Matt
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
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From evan.cheng at apple.com  Mon Oct 25 21:03:05 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Oct 2010 02:03:05 -0000
Subject: [llvm-commits] [llvm] r117347 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20101026020305.8A09D2A6C12C@llvm.org>

Author: evancheng
Date: Mon Oct 25 21:03:05 2010
New Revision: 117347

URL: http://llvm.org/viewvc/llvm-project?rev=117347&view=rev
Log:
NEON vmov's are in Neon domain.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117347&r1=117346&r2=117347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Oct 25 21:03:05 2010
@@ -1801,7 +1801,7 @@
 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
                dag oops, dag iops, Format f, InstrItinClass itin,
                string opc, string dt, string asm, list<dag> pattern>
-  : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
+  : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
             "", itin> {
   let Inst{27-20} = opcod1;
   let Inst{11-8}  = opcod2;



From evan.cheng at apple.com  Mon Oct 25 21:08:51 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Oct 2010 02:08:51 -0000
Subject: [llvm-commits] [llvm] r117348 - in /llvm/trunk:
 include/llvm/Target/TargetInstrInfo.h lib/CodeGen/MachineLICM.cpp
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
 lib/Target/TargetInstrInfo.cpp
Message-ID: <20101026020851.320652A6C12C@llvm.org>

Author: evancheng
Date: Mon Oct 25 21:08:50 2010
New Revision: 117348

URL: http://llvm.org/viewvc/llvm-project?rev=117348&view=rev
Log:
Use instruction itinerary to determine what instructions are 'cheap'.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/CodeGen/MachineLICM.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
    llvm/trunk/lib/Target/TargetInstrInfo.cpp

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=117348&r1=117347&r2=117348&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Oct 25 21:08:50 2010
@@ -639,6 +639,12 @@
                              const MachineInstr *UseMI, unsigned UseIdx) const {
     return false;
   }
+
+  /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true
+  /// if the target considered it 'low'.
+  virtual
+  bool hasLowDefLatency(const InstrItineraryData *ItinData,
+                        const MachineInstr *DefMI, unsigned DefIdx) const;
 };
 
 /// TargetInstrInfoImpl - This is the default implementation of

Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=117348&r1=117347&r2=117348&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Mon Oct 25 21:08:50 2010
@@ -173,7 +173,10 @@
     /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
     /// and an use in the current loop, return true if the target considered
     /// it 'high'.
-    bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg);
+    bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
+                               unsigned Reg) const;
+
+    bool IsCheapInstruction(MachineInstr &MI) const;
 
     /// CanCauseHighRegPressure - Visit BBs from header to current BB,
     /// check if hoisting an instruction of the given cost matrix can cause high
@@ -795,13 +798,15 @@
 /// and an use in the current loop, return true if the target considered
 /// it 'high'.
 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
-                                        unsigned DefIdx, unsigned Reg) {
-  if (MRI->use_nodbg_empty(Reg))
+                                        unsigned DefIdx, unsigned Reg) const {
+  if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
     return false;
 
   for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
          E = MRI->use_nodbg_end(); I != E; ++I) {
     MachineInstr *UseMI = &*I;
+    if (UseMI->isCopyLike())
+      continue;
     if (!CurLoop->contains(UseMI->getParent()))
       continue;
     for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
@@ -823,6 +828,33 @@
   return false;
 }
 
+/// IsCheapInstruction - Return true if the instruction is marked "cheap" or
+/// the operand latency between its def and a use is one or less.
+bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
+  if (MI.getDesc().isAsCheapAsAMove() || MI.isCopyLike())
+    return true;
+  if (!InstrItins || InstrItins->isEmpty())
+    return false;
+
+  bool isCheap = false;
+  unsigned NumDefs = MI.getDesc().getNumDefs();
+  for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
+    MachineOperand &DefMO = MI.getOperand(i);
+    if (!DefMO.isReg() || !DefMO.isDef())
+      continue;
+    --NumDefs;
+    unsigned Reg = DefMO.getReg();
+    if (TargetRegisterInfo::isPhysicalRegister(Reg))
+      continue;
+
+    if (!TII->hasLowDefLatency(InstrItins, &MI, i))
+      return false;
+    isCheap = true;
+  }
+
+  return isCheap;
+}
+
 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
 /// if hoisting an instruction of the given cost matrix can cause high
 /// register pressure.
@@ -905,7 +937,7 @@
   // trade off is it may cause spill in high pressure situation. It will end up
   // adding a store in the loop preheader. But the reload is no more expensive.
   // The side benefit is these loads are frequently CSE'ed.
-  if (MI.getDesc().isAsCheapAsAMove()) {
+  if (IsCheapInstruction(MI)) {
     if (!TII->isTriviallyReMaterializable(&MI, AA))
       return false;
   } else {

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117348&r1=117347&r2=117348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Oct 25 21:08:50 2010
@@ -1951,3 +1951,18 @@
   return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
          UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
 }
+
+bool ARMBaseInstrInfo::
+hasLowDefLatency(const InstrItineraryData *ItinData,
+                 const MachineInstr *DefMI, unsigned DefIdx) const {
+  if (!ItinData || ItinData->isEmpty())
+    return false;
+
+  unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
+  if (DDomain == ARMII::DomainGeneral) {
+    unsigned DefClass = DefMI->getDesc().getSchedClass();
+    int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
+    return (DefCycle != -1 && DefCycle <= 2);
+  }
+  return false;
+}

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=117348&r1=117347&r2=117348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Mon Oct 25 21:08:50 2010
@@ -382,6 +382,8 @@
                              const MachineRegisterInfo *MRI,
                              const MachineInstr *DefMI, unsigned DefIdx,
                              const MachineInstr *UseMI, unsigned UseIdx) const;
+  bool hasLowDefLatency(const InstrItineraryData *ItinData,
+                        const MachineInstr *DefMI, unsigned DefIdx) const;
 };
 
 static inline

Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=117348&r1=117347&r2=117348&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Mon Oct 25 21:08:50 2010
@@ -94,6 +94,16 @@
   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
 }
 
+bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
+                                       const MachineInstr *DefMI,
+                                       unsigned DefIdx) const {
+  if (!ItinData || ItinData->isEmpty())
+    return false;
+
+  unsigned DefClass = DefMI->getDesc().getSchedClass();
+  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
+  return (DefCycle != -1 && DefCycle <= 1);
+}
 
 /// insertNoop - Insert a noop into the instruction stream at the specified
 /// point.



From geek4civic at gmail.com  Tue Oct 26 00:08:27 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 26 Oct 2010 05:08:27 -0000
Subject: [llvm-commits] [llvm] r117352 - /llvm/trunk/CMakeLists.txt
Message-ID: <20101026050827.850C82A6C12C@llvm.org>

Author: chapuni
Date: Tue Oct 26 00:08:27 2010
New Revision: 117352

URL: http://llvm.org/viewvc/llvm-project?rev=117352&view=rev
Log:
CMake: Build utils/KillTheDoctor only on MSVC for now.

Mingw does not have the header <dbghelp.h>.
Thanks to Daniel Newton, testing it on mingw.

Modified:
    llvm/trunk/CMakeLists.txt

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=117352&r1=117351&r2=117352&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Tue Oct 26 00:08:27 2010
@@ -392,7 +392,7 @@
   add_subdirectory(test)
   add_subdirectory(utils/unittest)
   add_subdirectory(unittests)
-  if (WIN32)
+  if (MSVC)
     # This utility is used to prevent chrashing tests from calling Dr. Watson on
     # Windows.
     add_subdirectory(utils/KillTheDoctor)



From baldrick at free.fr  Tue Oct 26 02:47:05 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 26 Oct 2010 09:47:05 +0200
Subject: [llvm-commits] [llvm] r117307
	-	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
In-Reply-To: <20101025204533.0433C2A6C12C@llvm.org>
References: <20101025204533.0433C2A6C12C@llvm.org>
Message-ID: <4CC68779.1080403@free.fr>

Hi Devang,

> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 25 15:45:32 2010
> @@ -30,6 +30,7 @@
>   #include "llvm/Target/TargetRegisterInfo.h"
>   #include "llvm/Target/TargetOptions.h"
>   #include "llvm/Analysis/DebugInfo.h"
> +#include "llvm/ADT/Statistic.h"
>   #include "llvm/ADT/STLExtras.h"
>   #include "llvm/ADT/StringExtras.h"
>   #include "llvm/Support/CommandLine.h"
> @@ -52,6 +53,8 @@
>        cl::desc("Make an absense of debug location information explicit."),
>        cl::init(false));
>
> +STATISTIC(BlocksWithoutLineNo, "Number of blocks without any line number");
> +

maybe the statistic should be surrounded by "#ifndef NDEBUG" too, otherwise when
printing statistics from a release build you will always get BlocksWithoutLineNo
equal to zero, which might be confusing.  That said, maybe the statistic should
be always available - is it really costly to compute?

Ciao,

Duncan.


From baldrick at free.fr  Tue Oct 26 03:09:38 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 26 Oct 2010 10:09:38 +0200
Subject: [llvm-commits] [llvm] r117322 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/stdcall-notailcall.ll
In-Reply-To: <20101025221705.C4B602A6C12C@llvm.org>
References: <20101025221705.C4B602A6C12C@llvm.org>
Message-ID: <4CC68CC2.5030402@free.fr>

Hi Dale,

> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 25 17:17:05 2010
> @@ -2532,6 +2532,11 @@
>       }
>     }
>
> +  // An stdcall caller is expected to clean up its arguments; the callee
> +  // isn't going to do that.   PR 8461.

I think there's some rule saying that PR numbers should not be mentioned in
code comments (not sure why, but I recall Chris saying this once).

Ciao,

Duncan.

From baldrick at free.fr  Tue Oct 26 03:29:43 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 26 Oct 2010 08:29:43 -0000
Subject: [llvm-commits] [dragonegg] r117358 - /dragonegg/trunk/llvm-abi.h
Message-ID: <20101026082943.0CA4B2A6C12F@llvm.org>

Author: baldrick
Date: Tue Oct 26 03:29:42 2010
New Revision: 117358

URL: http://llvm.org/viewvc/llvm-project?rev=117358&view=rev
Log:
Remove unused header file.

Modified:
    dragonegg/trunk/llvm-abi.h

Modified: dragonegg/trunk/llvm-abi.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-abi.h?rev=117358&r1=117357&r2=117358&view=diff
==============================================================================
--- dragonegg/trunk/llvm-abi.h (original)
+++ dragonegg/trunk/llvm-abi.h Tue Oct 26 03:29:42 2010
@@ -38,7 +38,6 @@
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/LLVMContext.h"
-#include "llvm/Support/Compiler.h"
 #include "llvm/Target/TargetData.h"
 
 namespace llvm {



From kalle.raiskila at nokia.com  Tue Oct 26 05:45:47 2010
From: kalle.raiskila at nokia.com (Kalle Raiskila)
Date: Tue, 26 Oct 2010 10:45:47 -0000
Subject: [llvm-commits] [llvm] r117360 - in /llvm/trunk:
 lib/Target/CellSPU/SPUSubtarget.h test/CodeGen/CellSPU/v2f32.ll
 test/CodeGen/CellSPU/v2i32.ll
Message-ID: <20101026104547.E6D432A6C12C@llvm.org>

Author: kraiskil
Date: Tue Oct 26 05:45:47 2010
New Revision: 117360

URL: http://llvm.org/viewvc/llvm-project?rev=117360&view=rev
Log:
Change v64 datalayout in SPU.
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
    llvm/trunk/test/CodeGen/CellSPU/v2f32.ll
    llvm/trunk/test/CodeGen/CellSPU/v2i32.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=117360&r1=117359&r2=117360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Tue Oct 26 05:45:47 2010
@@ -81,7 +81,7 @@
     /// properties of this subtarget.
     const char *getTargetDataString() const {
       return "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128"
-             "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:128:128-v128:128:128"
+             "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128"
              "-s:128:128-n32:64";
     }
   };

Modified: llvm/trunk/test/CodeGen/CellSPU/v2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/v2f32.ll?rev=117360&r1=117359&r2=117360&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/v2f32.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/v2f32.ll Tue Oct 26 05:45:47 2010
@@ -62,8 +62,7 @@
 }
 
 define void @test_unaligned_store()  {
-;CHECK:	cdd	$3, 8($3)
-;CHECK: 	lqd	
+;CHECK:	cdd
 ;CHECK:	shufb
 ;CHECK:	stqd
   %data = alloca [4 x float], align 16         ; <[4 x float]*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/CellSPU/v2i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/v2i32.ll?rev=117360&r1=117359&r2=117360&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/v2i32.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/v2i32.ll Tue Oct 26 05:45:47 2010
@@ -61,3 +61,17 @@
   store %vec %val, %vec* %ptr
   ret void
 }
+
+;Alignment of <2 x i32> is not *directly* defined in the ABI
+;It probably is safe to interpret it as an array, thus having 8 byte
+;alignment (according to ABI). This tests that the size of
+;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the
+;two arrays
+define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr)
+{
+; CHECK-NOT:	ai	$3, $3, 16
+; CHECK:	ai	$3, $3, 8
+; CHECK:	bi	$lr
+   %rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1
+   ret <2 x i32>* %rv
+}



From baldrick at free.fr  Tue Oct 26 07:43:36 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 26 Oct 2010 12:43:36 -0000
Subject: [llvm-commits] [llvm] r117362 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20101026124336.AE9892A6C12C@llvm.org>

Author: baldrick
Date: Tue Oct 26 07:43:36 2010
New Revision: 117362

URL: http://llvm.org/viewvc/llvm-project?rev=117362&view=rev
Log:
Yet another thing that was forgotten to be added to the release notes...

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=117362&r1=117361&r2=117362&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 26 07:43:36 2010
@@ -1017,6 +1017,11 @@
   were dropped.  GC plugins which compute stack maps must be updated to avoid
   having the old definition overload the new signature.
 </li>
+<li>
+  The signature of <tt>MemoryBuffer::getMemBuffer</tt> changed.  Unfortunately
+  calls intended for the old version still compile, but will not work correctly,
+  leading to a confusing error about an invalid header in the bitcode.
+</li>
   
 <li>
   Some APIs were renamed:



From rafael.espindola at gmail.com  Tue Oct 26 09:09:12 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 26 Oct 2010 14:09:12 -0000
Subject: [llvm-commits] [llvm] r117364 - in /llvm/trunk:
 lib/Target/X86/X86AsmBackend.cpp test/MC/ELF/relax-arith.s
Message-ID: <20101026140912.EE8482A6C12C@llvm.org>

Author: rafael
Date: Tue Oct 26 09:09:12 2010
New Revision: 117364

URL: http://llvm.org/viewvc/llvm-project?rev=117364&view=rev
Log:
Implement some relaxations for arithmetic instructions. The limitation
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

Added:
    llvm/trunk/test/MC/ELF/relax-arith.s
Modified:
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=117364&r1=117363&r2=117364&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Tue Oct 26 09:09:12 2010
@@ -69,16 +69,11 @@
 };
 } // end anonymous namespace
 
-static unsigned getRelaxedOpcode(unsigned Op) {
+static unsigned getRelaxedOpcodeBranch(unsigned Op) {
   switch (Op) {
   default:
     return Op;
 
-  // This is used on i386 with things like addl $foo, %ebx
-  // FIXME: Should the other *i8 instructions be here too? If not, it might
-  // be better to just select X86::ADD32ri instead of X86::ADD32ri8.
-  case X86::ADD32ri8: return X86::ADD32ri;
-
   case X86::JAE_1: return X86::JAE_4;
   case X86::JA_1:  return X86::JA_4;
   case X86::JBE_1: return X86::JBE_4;
@@ -99,16 +94,101 @@
   }
 }
 
+static unsigned getRelaxedOpcodeArith(unsigned Op) {
+  switch (Op) {
+  default:
+    return Op;
+
+    // IMUL
+  case X86::IMUL16rri8: return X86::IMUL16rri;
+  case X86::IMUL16rmi8: return X86::IMUL16rmi;
+  case X86::IMUL32rri8: return X86::IMUL32rri;
+  case X86::IMUL32rmi8: return X86::IMUL32rmi;
+  case X86::IMUL64rri8: return X86::IMUL64rri32;
+  case X86::IMUL64rmi8: return X86::IMUL64rmi32;
+
+    // AND
+  case X86::AND16ri8: return X86::AND16ri;
+  case X86::AND16mi8: return X86::AND16mi;
+  case X86::AND32ri8: return X86::AND32ri;
+  case X86::AND32mi8: return X86::AND32mi;
+  case X86::AND64ri8: return X86::AND64ri32;
+  case X86::AND64mi8: return X86::AND64mi32;
+
+    // OR
+  case X86::OR16ri8: return X86::OR16ri;
+  case X86::OR16mi8: return X86::OR16mi;
+  case X86::OR32ri8: return X86::OR32ri;
+  case X86::OR32mi8: return X86::OR32mi;
+  case X86::OR64ri8: return X86::OR64ri32;
+  case X86::OR64mi8: return X86::OR64mi32;
+
+    // XOR
+  case X86::XOR16ri8: return X86::XOR16ri;
+  case X86::XOR16mi8: return X86::XOR16mi;
+  case X86::XOR32ri8: return X86::XOR32ri;
+  case X86::XOR32mi8: return X86::XOR32mi;
+  case X86::XOR64ri8: return X86::XOR64ri32;
+  case X86::XOR64mi8: return X86::XOR64mi32;
+
+    // ADD
+  case X86::ADD16ri8: return X86::ADD16ri;
+  case X86::ADD16mi8: return X86::ADD16mi;
+  case X86::ADD32ri8: return X86::ADD32ri;
+  case X86::ADD32mi8: return X86::ADD32mi;
+  case X86::ADD64ri8: return X86::ADD64ri32;
+  case X86::ADD64mi8: return X86::ADD64mi32;
+
+    // SUB
+  case X86::SUB16ri8: return X86::SUB16ri;
+  case X86::SUB16mi8: return X86::SUB16mi;
+  case X86::SUB32ri8: return X86::SUB32ri;
+  case X86::SUB32mi8: return X86::SUB32mi;
+  case X86::SUB64ri8: return X86::SUB64ri32;
+  case X86::SUB64mi8: return X86::SUB64mi32;
+
+    // CMP
+  case X86::CMP16ri8: return X86::CMP16ri;
+  case X86::CMP16mi8: return X86::CMP16mi;
+  case X86::CMP32ri8: return X86::CMP32ri;
+  case X86::CMP32mi8: return X86::CMP32mi;
+  case X86::CMP64ri8: return X86::CMP64ri32;
+  case X86::CMP64mi8: return X86::CMP64mi32;
+  }
+}
+
+static unsigned getRelaxedOpcode(unsigned Op) {
+  unsigned R = getRelaxedOpcodeArith(Op);
+  if (R != Op)
+    return R;
+  return getRelaxedOpcodeBranch(Op);
+}
+
 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
+  // Branches can always be relaxed.
+  if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
+    return true;
+
   // Check if this instruction is ever relaxable.
-  if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
+  if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
     return false;
 
-  // If so, just assume it can be relaxed. Once we support relaxing more complex
-  // instructions we should check that the instruction actually has symbolic
-  // operands before doing this, but we need to be careful about things like
-  // PCrel.
-  return true;
+
+  // Check if it has an expression and is not RIP relative.
+  bool hasExp = false;
+  bool hasRIP = false;
+  for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
+    const MCOperand &Op = Inst.getOperand(i);
+    if (Op.isExpr())
+      hasExp = true;
+
+    if (Op.isReg() && Op.getReg() == X86::RIP)
+      hasRIP = true;
+  }
+
+  // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
+  // how we do relaxations?
+  return hasExp && !hasRIP;
 }
 
 // FIXME: Can tblgen help at all here to verify there aren't other instructions

Added: llvm/trunk/test/MC/ELF/relax-arith.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith.s?rev=117364&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/relax-arith.s (added)
+++ llvm/trunk/test/MC/ELF/relax-arith.s Tue Oct 26 09:09:12 2010
@@ -0,0 +1,75 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
+
+// Test that we correctly relax these instructions into versions that use
+// 16 or 32 bit immediate values.
+
+bar:
+// CHECK: 'imul'
+// CHECK: ('_section_data', '6669db00 0066691c 25000000 00000069 db000000 00691c25 00000000 00000000 4869db00 00000048 691c2500 00000000 000000')
+        .section imul
+        imul $foo, %bx,  %bx
+        imul $foo, bar,  %bx
+        imul $foo, %ebx, %ebx
+        imul $foo, bar,  %ebx
+        imul $foo, %rbx, %rbx
+        imul $foo, bar,  %rbx
+
+// CHECK: and'
+// CHECK:('_section_data', '6681e300 00668124 25000000 00000081 e3000000 00812425 00000000 00000000 4881e300 00000048 81242500 00000000 000000')
+        .section and
+        and  $foo, %bx
+        andw $foo, bar
+        and  $foo, %ebx
+        andl $foo, bar
+        and  $foo, %rbx
+        andq $foo, bar
+
+// CHECK: 'or'
+// CHECK: ('_section_data', '6681cb00 0066810c 25000000 00000081 cb000000 00810c25 00000000 00000000 4881cb00 00000048 810c2500 00000000 000000')
+        .section or
+        or  $foo, %bx
+        orw $foo, bar
+        or  $foo, %ebx
+        orl $foo, bar
+        or  $foo, %rbx
+        orq $foo, bar
+
+// CHECK: 'xor'
+// CHECK: ('_section_data', '6681f300 00668134 25000000 00000081 f3000000 00813425 00000000 00000000 4881f300 00000048 81342500 00000000 000000')
+        .section xor
+        xor  $foo, %bx
+        xorw $foo, bar
+        xor  $foo, %ebx
+        xorl $foo, bar
+        xor  $foo, %rbx
+        xorq $foo, bar
+
+// CHECK: 'add'
+// CHECK: ('_section_data', '6681c300 00668104 25000000 00000081 c3000000 00810425 00000000 00000000 4881c300 00000048 81042500 00000000 000000')
+        .section add
+        add  $foo, %bx
+        addw $foo, bar
+        add  $foo, %ebx
+        addl $foo, bar
+        add  $foo, %rbx
+        addq $foo, bar
+
+// CHECK: 'sub'
+// CHECK: ('_section_data', '6681eb00 0066812c 25000000 00000081 eb000000 00812c25 00000000 00000000 4881eb00 00000048 812c2500 00000000 000000')
+        .section sub
+        sub  $foo, %bx
+        subw $foo, bar
+        sub  $foo, %ebx
+        subl $foo, bar
+        sub  $foo, %rbx
+        subq $foo, bar
+
+// CHECK: 'cmp'
+// CHECK: ('_section_data', '6681fb00 0066813c 25000000 00000081 fb000000 00813c25 00000000 00000000 4881fb00 00000048 813c2500 00000000 000000')
+        .section cmp
+        cmp  $foo, %bx
+        cmpw $foo, bar
+        cmp  $foo, %ebx
+        cmpl $foo, bar
+        cmp  $foo, %rbx
+        cmpq $foo, bar



From fjahanian at apple.com  Tue Oct 26 11:15:59 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Tue, 26 Oct 2010 16:15:59 -0000
Subject: [llvm-commits] [test-suite] r117368 -
	/test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp
Message-ID: <20101026161559.8C41C2A6C12C@llvm.org>

Author: fjahanian
Date: Tue Oct 26 11:15:59 2010
New Revision: 117368

URL: http://llvm.org/viewvc/llvm-project?rev=117368&view=rev
Log:
Fixes test.

Modified:
    test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp

Modified: test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp?rev=117368&r1=117367&r2=117368&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp (original)
+++ test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp Tue Oct 26 11:15:59 2010
@@ -1,23 +1,22 @@
 // rdar: //8540501
-extern "C" int printf(...);
 extern "C" void abort();
 
 struct A
 {
   int i;
-  A (int j) : i(j) {printf("this = %p A(%d)\n", this, j);}
-  A (const A &j) : i(j.i) {printf("this = %p const A&(%d)\n", this, i);}
+  A (int j) : i(j) {}
+  A (const A &j) : i(j.i) {}
   A& operator= (const A &j) { i = j.i; abort(); return *this; }
-  ~A() { printf("this = %p ~A(%d)\n", this, i); }
+  ~A() { }
 };
 
 struct B
 {
   int i;
   B (const A& a) { i = a.i; }
-  B() {printf("this = %p B()\n", this);}
-  B (const B &j) : i(j.i) {printf("this = %p const B&(%d)\n", this, i);}
-  ~B() { printf("this = %p ~B(%d)\n", this, i); }
+  B() {}
+  B (const B &j) : i(j.i) {}
+  ~B() { }
 };
 
 A foo(int j)



From fjahanian at apple.com  Tue Oct 26 11:28:24 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Tue, 26 Oct 2010 16:28:24 -0000
Subject: [llvm-commits] [test-suite] r117369 -
	/test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp
Message-ID: <20101026162824.AF2E42A6C12C@llvm.org>

Author: fjahanian
Date: Tue Oct 26 11:28:24 2010
New Revision: 117369

URL: http://llvm.org/viewvc/llvm-project?rev=117369&view=rev
Log:
Removed some random comments.

Modified:
    test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp

Modified: test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp?rev=117369&r1=117368&r2=117369&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp (original)
+++ test-suite/trunk/SingleSource/UnitTests/stmtexpr.cpp Tue Oct 26 11:28:24 2010
@@ -44,11 +44,6 @@
 
 void foo4()
 {
-// CHECK: call void @_ZN1AC1Ei
-// CHECK: call void @_ZN1AC1ERKS_
-// CHECK: call void @_ZN1AD1Ev
-// CHECK: call void @_ZN1BC1ERK1A
-// CHECK: call void @_ZN1AD1Ev
   const B &b = ({ A a(1); a; });
   if (b.i != 1)
     abort();



From stoklund at 2pi.dk  Tue Oct 26 11:49:23 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 16:49:23 -0000
Subject: [llvm-commits] [llvm] r117370 -
	/llvm/trunk/lib/CodeGen/MachineVerifier.cpp
Message-ID: <20101026164923.36ED52A6C12C@llvm.org>

Author: stoklund
Date: Tue Oct 26 11:49:23 2010
New Revision: 117370

URL: http://llvm.org/viewvc/llvm-project?rev=117370&view=rev
Log:
Don't verify physical registers going into landing pads.
Magic is happening that we don't understand.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117370&r1=117369&r2=117370&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Oct 26 11:49:23 2010
@@ -1024,6 +1024,14 @@
       }
       for (;;) {
         assert(LiveInts->isLiveInToMBB(LI, MFI));
+        // We don't know how to track physregs into a landing pad.
+        if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
+            MFI->isLandingPad()) {
+          if (&*MFI == EndMBB)
+            break;
+          ++MFI;
+          continue;
+        }
         // Check that VNI is live-out of all predecessors.
         for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
              PE = MFI->pred_end(); PI != PE; ++PI) {



From aggarwa4 at illinois.edu  Tue Oct 26 11:52:24 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 26 Oct 2010 16:52:24 -0000
Subject: [llvm-commits] [poolalloc] r117371 - in
 /poolalloc/trunk/test/dsa/callgraph: testIncomplete.ll varargs.ll
Message-ID: <20101026165224.9FD4D2A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Oct 26 11:52:24 2010
New Revision: 117371

URL: http://llvm.org/viewvc/llvm-project?rev=117371&view=rev
Log:
More test cases, to check call graph construction

Added:
    poolalloc/trunk/test/dsa/callgraph/testIncomplete.ll
    poolalloc/trunk/test/dsa/callgraph/varargs.ll

Added: poolalloc/trunk/test/dsa/callgraph/testIncomplete.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/callgraph/testIncomplete.ll?rev=117371&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/callgraph/testIncomplete.ll (added)
+++ poolalloc/trunk/test/dsa/callgraph/testIncomplete.ll Tue Oct 26 11:52:24 2010
@@ -0,0 +1,87 @@
+; another cause of incompleteness
+; fptr, and arg both point to same node
+; and hence incomplete
+
+;RUN: dsaopt %s -dsa-cbu -analyze -check-callees=A,B,C,D
+;RUN: dsaopt %s -dsa-cbu -analyze -check-callees=B,B,C,D
+
+; ModuleID = 'testIncomplete.o'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32* @B(i8* %fp) nounwind {
+entry:
+  %fp_addr = alloca i8*                           ; <i8**> [#uses=2]
+  %retval = alloca i32*                           ; <i32**> [#uses=1]
+  %x = alloca i32*                                ; <i32**> [#uses=2]
+  %fp1 = alloca i32* (i8*)**                      ; <i32* (i8*)***> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i8* %fp, i8** %fp_addr
+  %0 = call noalias i8* @malloc(i64 4) nounwind   ; <i8*> [#uses=1]
+  %1 = bitcast i8* %0 to i32*                     ; <i32*> [#uses=1]
+  store i32* %1, i32** %x, align 8
+  %2 = load i8** %fp_addr, align 8                ; <i8*> [#uses=1]
+  %3 = bitcast i8* %2 to i32* (i8*)**             ; <i32* (i8*)**> [#uses=1]
+  store i32* (i8*)** %3, i32* (i8*)*** %fp1, align 8
+  %4 = load i32* (i8*)*** %fp1, align 8           ; <i32* (i8*)**> [#uses=1]
+  %5 = load i32* (i8*)** %4, align 8              ; <i32* (i8*)*> [#uses=1]
+  %6 = load i32** %x, align 8                     ; <i32*> [#uses=1]
+  %7 = bitcast i32* %6 to i8*                     ; <i8*> [#uses=1]
+  %8 = call i32* %5(i8* %7) nounwind              ; <i32*> [#uses=0]
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  ret i32* %retval1
+}
+
+declare noalias i8* @malloc(i64) nounwind
+
+define i32* @C(i8* %fp1) nounwind {
+entry:
+  %fp1_addr = alloca i8*                          ; <i8**> [#uses=1]
+  %retval = alloca i32*                           ; <i32**> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i8* %fp1, i8** %fp1_addr
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  ret i32* %retval1
+}
+
+define i32* @D(i8* %fp1) nounwind {
+entry:
+  %fp1_addr = alloca i8*                          ; <i8**> [#uses=1]
+  %retval = alloca i32*                           ; <i32**> [#uses=1]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i8* %fp1, i8** %fp1_addr
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  ret i32* %retval1
+}
+
+define i32* @A() nounwind {
+entry:
+  %retval = alloca i32*                           ; <i32**> [#uses=1]
+  %fp = alloca i32* (i8*)*                        ; <i32* (i8*)**> [#uses=4]
+  %fp1 = alloca i32* (i8*)*                       ; <i32* (i8*)**> [#uses=4]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32* (i8*)* @B, i32* (i8*)** %fp, align 8
+  store i32* (i8*)* @C, i32* (i8*)** %fp, align 8
+  store i32* (i8*)* @D, i32* (i8*)** %fp, align 8
+  store i32* (i8*)* @B, i32* (i8*)** %fp1, align 8
+  store i32* (i8*)* @C, i32* (i8*)** %fp1, align 8
+  store i32* (i8*)* @D, i32* (i8*)** %fp1, align 8
+  %0 = load i32* (i8*)** %fp, align 8             ; <i32* (i8*)*> [#uses=1]
+  %1 = load i32* (i8*)** %fp1, align 8            ; <i32* (i8*)*> [#uses=1]
+  %2 = bitcast i32* (i8*)* %1 to i8*              ; <i8*> [#uses=1]
+  %3 = call i32* %0(i8* %2) nounwind              ; <i32*> [#uses=0]
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32** %retval                   ; <i32*> [#uses=1]
+  ret i32* %retval1
+}

Added: poolalloc/trunk/test/dsa/callgraph/varargs.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/callgraph/varargs.ll?rev=117371&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/callgraph/varargs.ll (added)
+++ poolalloc/trunk/test/dsa/callgraph/varargs.ll Tue Oct 26 11:52:24 2010
@@ -0,0 +1,183 @@
+;RUN: dsaopt %s -dsa-cbu -analyze -check-callees=assign,A,B
+;RUN: dsaopt %s -dsa-bu -analyze -check-callees=assign,A,B
+
+;Go through a list of functions passed as varargs, and call each one.
+
+; ModuleID = 'multiple_callee.o'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.__va_list_tag = type { i32, i32, i8*, i8* }
+
+define internal void @A() nounwind {
+entry:
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+define internal void @B() nounwind {
+entry:
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+define internal void @C() nounwind {
+entry:
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+define internal void @assign(i32 %count, ...) nounwind {
+entry:
+  %count_addr = alloca i32                        ; <i32*> [#uses=2]
+  %addr.2 = alloca i8*                            ; <i8**> [#uses=3]
+  %addr.0 = alloca i8*                            ; <i8**> [#uses=3]
+  %ap = alloca [1 x %struct.__va_list_tag]        ; <[1 x %struct.__va_list_tag]*> [#uses=16]
+  %old = alloca void ()*                          ; <void ()**> [#uses=3]
+  %i = alloca i32                                 ; <i32*> [#uses=4]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  store i32 %count, i32* %count_addr
+  %ap1 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1]
+  %ap12 = bitcast %struct.__va_list_tag* %ap1 to i8* ; <i8*> [#uses=1]
+  call void @llvm.va_start(i8* %ap12)
+  %0 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %1 = getelementptr inbounds %struct.__va_list_tag* %0, i32 0, i32 0 ; <i32*> [#uses=1]
+  %2 = load i32* %1, align 8                      ; <i32> [#uses=1]
+  %3 = icmp uge i32 %2, 48                        ; <i1> [#uses=1]
+  br i1 %3, label %bb3, label %bb
+
+bb:                                               ; preds = %entry
+  %4 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %5 = getelementptr inbounds %struct.__va_list_tag* %4, i32 0, i32 3 ; <i8**> [#uses=1]
+  %6 = load i8** %5, align 8                      ; <i8*> [#uses=1]
+  %7 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %8 = getelementptr inbounds %struct.__va_list_tag* %7, i32 0, i32 0 ; <i32*> [#uses=1]
+  %9 = load i32* %8, align 8                      ; <i32> [#uses=1]
+  %10 = inttoptr i32 %9 to i8*                    ; <i8*> [#uses=1]
+  %11 = ptrtoint i8* %6 to i64                    ; <i64> [#uses=1]
+  %12 = ptrtoint i8* %10 to i64                   ; <i64> [#uses=1]
+  %13 = add i64 %11, %12                          ; <i64> [#uses=1]
+  %14 = inttoptr i64 %13 to i8*                   ; <i8*> [#uses=1]
+  store i8* %14, i8** %addr.0, align 8
+  %15 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %16 = getelementptr inbounds %struct.__va_list_tag* %15, i32 0, i32 0 ; <i32*> [#uses=1]
+  %17 = load i32* %16, align 8                    ; <i32> [#uses=1]
+  %18 = add i32 %17, 8                            ; <i32> [#uses=1]
+  %19 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %20 = getelementptr inbounds %struct.__va_list_tag* %19, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32 %18, i32* %20, align 8
+  br label %bb4
+
+bb3:                                              ; preds = %entry
+  %21 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %22 = getelementptr inbounds %struct.__va_list_tag* %21, i32 0, i32 2 ; <i8**> [#uses=1]
+  %23 = load i8** %22, align 8                    ; <i8*> [#uses=2]
+  store i8* %23, i8** %addr.0, align 8
+  %24 = getelementptr inbounds i8* %23, i64 8     ; <i8*> [#uses=1]
+  %25 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %26 = getelementptr inbounds %struct.__va_list_tag* %25, i32 0, i32 2 ; <i8**> [#uses=1]
+  store i8* %24, i8** %26, align 8
+  br label %bb4
+
+bb4:                                              ; preds = %bb3, %bb
+  %27 = load i8** %addr.0, align 8                ; <i8*> [#uses=1]
+  %28 = bitcast i8* %27 to void ()**              ; <void ()**> [#uses=1]
+  %29 = load void ()** %28, align 8               ; <void ()*> [#uses=1]
+  store void ()* %29, void ()** %old, align 8
+  store i32 0, i32* %i, align 4
+  br label %bb9
+
+bb5:                                              ; preds = %bb9
+  %30 = load void ()** %old, align 8              ; <void ()*> [#uses=1]
+  call void %30() nounwind
+  %31 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %32 = getelementptr inbounds %struct.__va_list_tag* %31, i32 0, i32 0 ; <i32*> [#uses=1]
+  %33 = load i32* %32, align 8                    ; <i32> [#uses=1]
+  %34 = icmp uge i32 %33, 48                      ; <i1> [#uses=1]
+  br i1 %34, label %bb7, label %bb6
+
+bb6:                                              ; preds = %bb5
+  %35 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %36 = getelementptr inbounds %struct.__va_list_tag* %35, i32 0, i32 3 ; <i8**> [#uses=1]
+  %37 = load i8** %36, align 8                    ; <i8*> [#uses=1]
+  %38 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %39 = getelementptr inbounds %struct.__va_list_tag* %38, i32 0, i32 0 ; <i32*> [#uses=1]
+  %40 = load i32* %39, align 8                    ; <i32> [#uses=1]
+  %41 = inttoptr i32 %40 to i8*                   ; <i8*> [#uses=1]
+  %42 = ptrtoint i8* %37 to i64                   ; <i64> [#uses=1]
+  %43 = ptrtoint i8* %41 to i64                   ; <i64> [#uses=1]
+  %44 = add i64 %42, %43                          ; <i64> [#uses=1]
+  %45 = inttoptr i64 %44 to i8*                   ; <i8*> [#uses=1]
+  store i8* %45, i8** %addr.2, align 8
+  %46 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %47 = getelementptr inbounds %struct.__va_list_tag* %46, i32 0, i32 0 ; <i32*> [#uses=1]
+  %48 = load i32* %47, align 8                    ; <i32> [#uses=1]
+  %49 = add i32 %48, 8                            ; <i32> [#uses=1]
+  %50 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %51 = getelementptr inbounds %struct.__va_list_tag* %50, i32 0, i32 0 ; <i32*> [#uses=1]
+  store i32 %49, i32* %51, align 8
+  br label %bb8
+
+bb7:                                              ; preds = %bb5
+  %52 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %53 = getelementptr inbounds %struct.__va_list_tag* %52, i32 0, i32 2 ; <i8**> [#uses=1]
+  %54 = load i8** %53, align 8                    ; <i8*> [#uses=2]
+  store i8* %54, i8** %addr.2, align 8
+  %55 = getelementptr inbounds i8* %54, i64 8     ; <i8*> [#uses=1]
+  %56 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+  %57 = getelementptr inbounds %struct.__va_list_tag* %56, i32 0, i32 2 ; <i8**> [#uses=1]
+  store i8* %55, i8** %57, align 8
+  br label %bb8
+
+bb8:                                              ; preds = %bb7, %bb6
+  %58 = load i8** %addr.2, align 8                ; <i8*> [#uses=1]
+  %59 = bitcast i8* %58 to i8**                   ; <i8**> [#uses=1]
+  %60 = load i8** %59, align 8                    ; <i8*> [#uses=1]
+  %61 = bitcast i8* %60 to void ()*               ; <void ()*> [#uses=1]
+  store void ()* %61, void ()** %old, align 8
+  %62 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %63 = add nsw i32 %62, 1                        ; <i32> [#uses=1]
+  store i32 %63, i32* %i, align 4
+  br label %bb9
+
+bb9:                                              ; preds = %bb8, %bb4
+  %64 = load i32* %i, align 4                     ; <i32> [#uses=1]
+  %65 = load i32* %count_addr, align 4            ; <i32> [#uses=1]
+  %66 = icmp slt i32 %64, %65                     ; <i1> [#uses=1]
+  br i1 %66, label %bb5, label %bb10
+
+bb10:                                             ; preds = %bb9
+  %ap11 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1]
+  %ap1112 = bitcast %struct.__va_list_tag* %ap11 to i8* ; <i8*> [#uses=1]
+  call void @llvm.va_end(i8* %ap1112)
+  br label %return
+
+return:                                           ; preds = %bb10
+  ret void
+}
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @llvm.va_end(i8*) nounwind
+
+define i32 @main() nounwind {
+entry:
+  %retval = alloca i32                            ; <i32*> [#uses=2]
+  %0 = alloca i32                                 ; <i32*> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
+  call void (i32, ...)* @assign(i32 2, void ()* @A, void ()* @B) nounwind
+  store i32 1, i32* %0, align 4
+  %1 = load i32* %0, align 4                      ; <i32> [#uses=1]
+  store i32 %1, i32* %retval, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  %retval1 = load i32* %retval                    ; <i32> [#uses=1]
+  ret i32 %retval1
+}



From rafael.espindola at gmail.com  Tue Oct 26 12:33:39 2010
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Tue, 26 Oct 2010 13:33:39 -0400
Subject: [llvm-commits] [llvm-mc][patch] Rename local symbols if needed
Message-ID: <AANLkTimC-aYNbSwqx=eJk_DS8PnBEVgoEUuK7S0w8Y98@mail.gmail.com>

A ping on a patch posted two weeks ago:

Currently llvm-mc will fail to assemble

----------------------------------------------------
       .size bar, . - bar
.Ltmp0:
      .size foo, .Ltmp0 - foo
--------------------------------------------------

With the interesting error message

../test.s:4:1: error: invalid symbol redefinition
.Ltmp0:

The problem is the the dot in the first size statement causes llvm-mc
to create a temporary symbol named ".Ltmp0".

The attached patch renames new local symbols to avoid the conflict.
This particular case can be solved by just printing "." for the
artificial symbol, but that is not always valid (debug generation
creates temporary symbols too).

Unfortunately we cannot delay the name generation as we print assembly
as it is produced/parsed.

Cheers,
Rafael
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From dpatel at apple.com  Tue Oct 26 12:37:27 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 26 Oct 2010 10:37:27 -0700
Subject: [llvm-commits] [PATCH] Guard new STATISTICs with #ifndef NDEBUG
In-Reply-To: <AANLkTi==B0FhWbNFwmPAYpXeWHYdF6RxjtQ_iS+LzXDT@mail.gmail.com>
References: <AANLkTin6q+yJ237_cx5Ht3W0b8N0dit4K6=+Rtvf9=TX@mail.gmail.com>
	<AANLkTi==B0FhWbNFwmPAYpXeWHYdF6RxjtQ_iS+LzXDT@mail.gmail.com>
Message-ID: <2542E2AE-8B39-4D91-BCDC-59CBBB93CDFB@apple.com>

Thanks!
On Oct 25, 2010, at 5:55 PM, Nick Lewycky wrote:

> Committed in revision 117345. Thanks for the patch!
> 
> Nick
> 
> On 25 October 2010 16:44, Matt Beaumont-Gay <matthewbg at google.com> wrote:
> With -Wall -Werror -DNDEBUG, gcc complains:
> lib/CodeGen/AsmPrinter/DwarfDebug.cpp:56: error: 'BlocksWithoutLineNo'
> defined but not used [-Wunused-variable]
> lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:59: error:
> 'NumBBWithOutOfOrderLineInfo' defined but not used [-Wunused-variable]
> lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:61: error:
> 'NumMBBWithOutOfOrderLineInfo' defined but not used
> [-Wunused-variable]
> 
> -Matt
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From dpatel at apple.com  Tue Oct 26 12:41:32 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 26 Oct 2010 10:41:32 -0700
Subject: [llvm-commits] [llvm] r117307	-
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
In-Reply-To: <4CC68779.1080403@free.fr>
References: <20101025204533.0433C2A6C12C@llvm.org> <4CC68779.1080403@free.fr>
Message-ID: <9ABABF24-3196-4270-B5BF-89B9FF5B5F8A@apple.com>


On Oct 26, 2010, at 12:47 AM, Duncan Sands wrote:

> Hi Devang,
> 
>> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 25 15:45:32 2010
>> @@ -30,6 +30,7 @@
>>  #include "llvm/Target/TargetRegisterInfo.h"
>>  #include "llvm/Target/TargetOptions.h"
>>  #include "llvm/Analysis/DebugInfo.h"
>> +#include "llvm/ADT/Statistic.h"
>>  #include "llvm/ADT/STLExtras.h"
>>  #include "llvm/ADT/StringExtras.h"
>>  #include "llvm/Support/CommandLine.h"
>> @@ -52,6 +53,8 @@
>>       cl::desc("Make an absense of debug location information explicit."),
>>       cl::init(false));
>> 
>> +STATISTIC(BlocksWithoutLineNo, "Number of blocks without any line number");
>> +
> 
> maybe the statistic should be surrounded by "#ifndef NDEBUG" too, otherwise when
> printing statistics from a release build you will always get BlocksWithoutLineNo
> equal to zero, which might be confusing.

Statistics are not printed if value is zero.

>  That said, maybe the statistic should
> be always available - is it really costly to compute?

The cost is likely not significant, it involves couple of rounds of extra iterations to walk all instructions.
-
Devang



From resistor at mac.com  Tue Oct 26 12:40:54 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 17:40:54 -0000
Subject: [llvm-commits] [llvm] r117374 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
 test/MC/ARM/neon-bitwise-encoding.ll test/MC/ARM/neon-mov-encoding.ll
Message-ID: <20101026174054.7DB512A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 12:40:54 2010
New Revision: 117374

URL: http://llvm.org/viewvc/llvm-project?rev=117374&view=rev
Log:
Add NEON encodings for vmov and vmvn of immediates.

Added:
    llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117374&r1=117373&r2=117374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Oct 26 12:40:54 2010
@@ -1683,6 +1683,16 @@
   let Inst{6}     = op6;
   let Inst{5}     = op5;
   let Inst{4}     = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<13> SIMM;
+  
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{24}    = SIMM{7};
+  let Inst{18-16} = SIMM{6-4};
+  let Inst{3-0}   = SIMM{3-0};
 }
 
 // NEON 2 vector register format.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117374&r1=117373&r2=117374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 12:40:54 2010
@@ -2899,26 +2899,34 @@
 //   VMVN     : Vector Bitwise NOT (Immediate)
 
 let isReMaterializable = 1 in {
-// FIXME: This instruction's encoding MAY NOT BE correct.
+
 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$dst, $SIMM", "",
-                         [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
-// FIXME: This instruction's encoding MAY NOT BE correct.
+                         [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
+  let Inst{9} = SIMM{9};
+}
+
 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$dst, $SIMM", "",
-                         [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
-// FIXME: This instruction's encoding MAY NOT BE correct.
+                         [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
+  let Inst{9} = SIMM{9};
+}
+
 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i32", "$dst, $SIMM", "",
-                         [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
-// FIXME: This instruction's encoding MAY NOT BE correct.
+                         [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
+  let Inst{11-8} = SIMM{11-8};
+}
+
 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i32", "$dst, $SIMM", "",
-                         [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
+                         [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
+  let Inst{11-8} = SIMM{11-8};
+}
 }
 
 //   VMVN     : Vector Bitwise NOT
@@ -3387,20 +3395,30 @@
 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmov", "i16", "$dst, $SIMM", "",
-                         [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
+                         [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
+  let Inst{9} = SIMM{9};                         
+}
+
 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmov", "i16", "$dst, $SIMM", "",
-                         [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
+                         [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
+ let Inst{9} = SIMM{9};
+}
 
 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmov", "i32", "$dst, $SIMM", "",
-                         [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
+                         [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
+  let Inst{11-8} = SIMM{11-8};
+}
+
 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmov", "i32", "$dst, $SIMM", "",
-                         [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
+                         [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
+  let Inst{11-8} = SIMM{11-8};
+}
 
 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117374&r1=117373&r2=117374&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Tue Oct 26 12:40:54 2010
@@ -2,7 +2,6 @@
 
 ; FIXME: The following instructions still require testing:
 ;  - vand with immediate, vorr with immediate
-;  - vmvn of an immediate
 ;  - both vbit and vbif
 
 ; CHECK: vand_8xi8

Added: llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.ll?rev=117374&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mov-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-mov-encoding.ll Tue Oct 26 12:40:54 2010
@@ -0,0 +1,169 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+; CHECK: vmov_8xi8
+define <8 x i8> @vmov_8xi8() nounwind {
+; CHECK: vmov.i8	d16, #0x8               @ encoding: [0x18,0x0e,0xc0,0xf2]
+	ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+}
+
+; CHECK: vmov_4xi16a
+define <4 x i16> @vmov_4xi16a() nounwind {
+; CHECK: vmov.i16	d16, #0x10      @ encoding: [0x10,0x08,0xc1,0xf2]
+	ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
+}
+
+; CHECK: vmov_4xi16b
+define <4 x i16> @vmov_4xi16b() nounwind {
+; CHECK: vmov.i16	d16, #0x1000    @ encoding: [0x10,0x0a,0xc1,0xf2]
+	ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
+}
+
+; CHECK: vmov_2xi32a
+define <2 x i32> @vmov_2xi32a() nounwind {
+; CHECK: vmov.i32	d16, #0x20      @ encoding: [0x10,0x00,0xc2,0xf2]
+	ret <2 x i32> < i32 32, i32 32 >
+}
+
+; CHECK: vmov_2xi32b
+define <2 x i32> @vmov_2xi32b() nounwind {
+; CHECK: vmov.i32	d16, #0x2000    @ encoding: [0x10,0x02,0xc2,0xf2]
+	ret <2 x i32> < i32 8192, i32 8192 >
+}
+
+; CHECK: vmov_2xi32c
+define <2 x i32> @vmov_2xi32c() nounwind {
+; CHECK: vmov.i32	d16, #0x200000  @ encoding: [0x10,0x04,0xc2,0xf2]
+	ret <2 x i32> < i32 2097152, i32 2097152 >
+}
+
+; CHECK: vmov_2xi32d
+define <2 x i32> @vmov_2xi32d() nounwind {
+; CHECK: vmov.i32	d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
+	ret <2 x i32> < i32 536870912, i32 536870912 >
+}
+
+; CHECK: vmov_2xi32e
+define <2 x i32> @vmov_2xi32e() nounwind {
+; CHECK: vmov.i32	d16, #0x20FF    @ encoding: [0x10,0x0c,0xc2,0xf2]
+	ret <2 x i32> < i32 8447, i32 8447 >
+}
+
+; CHECK: vmov_2xi32f
+define <2 x i32> @vmov_2xi32f() nounwind {
+; CHECK: vmov.i32	d16, #0x20FFFF  @ encoding: [0x10,0x0d,0xc2,0xf2]
+	ret <2 x i32> < i32 2162687, i32 2162687 >
+}
+
+; CHECK: vmov_1xi64
+define <1 x i64> @vmov_1xi64() nounwind {
+; CHECK: vmov.i64	d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
+	ret <1 x i64> < i64 18374687574888349695 >
+}
+
+; CHECK: vmov_16xi8
+define <16 x i8> @vmov_16xi8() nounwind {
+; CHECK: vmov.i8	q8, #0x8                @ encoding: [0x58,0x0e,0xc0,0xf2]
+	ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+}
+
+; CHECK: vmov_8xi16a
+define <8 x i16> @vmov_8xi16a() nounwind {
+; CHECK: vmov.i16	q8, #0x10       @ encoding: [0x50,0x08,0xc1,0xf2]
+	ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+}
+
+; CHECK: vmov_8xi16b
+define <8 x i16> @vmov_8xi16b() nounwind {
+; CHECK: vmov.i16	q8, #0x1000     @ encoding: [0x50,0x0a,0xc1,0xf2]
+	ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
+}
+
+; CHECK: vmov_4xi32a
+define <4 x i32> @vmov_4xi32a() nounwind {
+; CHECK: vmov.i32	q8, #0x20       @ encoding: [0x50,0x00,0xc2,0xf2]
+	ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
+}
+
+; CHECK: vmov_4xi32b
+define <4 x i32> @vmov_4xi32b() nounwind {
+; CHECK: vmov.i32	q8, #0x2000     @ encoding: [0x50,0x02,0xc2,0xf2]
+	ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
+}
+
+; CHECK: vmov_4xi32c
+define <4 x i32> @vmov_4xi32c() nounwind {
+; CHECK: vmov.i32	q8, #0x200000   @ encoding: [0x50,0x04,0xc2,0xf2]
+	ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
+}
+
+; CHECK: vmov_4xi32d
+define <4 x i32> @vmov_4xi32d() nounwind {
+; CHECK: vmov.i32	q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
+	ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
+}
+
+; CHECK: vmov_4xi32e
+define <4 x i32> @vmov_4xi32e() nounwind {
+; CHECK: vmov.i32	q8, #0x20FF     @ encoding: [0x50,0x0c,0xc2,0xf2]
+	ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
+}
+
+; CHECK: vmov_4xi32f
+define <4 x i32> @vmov_4xi32f() nounwind {
+; CHECK: vmov.i32	q8, #0x20FFFF   @ encoding: [0x50,0x0d,0xc2,0xf2]
+	ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
+}
+
+; CHECK: vmov_2xi64
+define <2 x i64> @vmov_2xi64() nounwind {
+; CHECK: vmov.i64	q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
+	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+}
+
+; CHECK: vmvn_4xi16a
+define <4 x i16> @vmvn_4xi16a() nounwind {
+; CHECK: vmvn.i16	d16, #0x10      @ encoding: [0x30,0x08,0xc1,0xf2]
+	ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
+}
+
+; CHECK: vmvn_4xi16b
+define <4 x i16> @vmvn_4xi16b() nounwind {
+; CHECK: vmvn.i16	d16, #0x1000    @ encoding: [0x30,0x0a,0xc1,0xf2]
+	ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
+}
+
+; CHECK: vmvn_2xi32a
+define <2 x i32> @vmvn_2xi32a() nounwind {
+; CHECK: vmvn.i32	d16, #0x20      @ encoding: [0x30,0x00,0xc2,0xf2]
+	ret <2 x i32> < i32 4294967263, i32 4294967263 >
+}
+
+; CHECK: vmvn_2xi32b
+define <2 x i32> @vmvn_2xi32b() nounwind {
+; CHECK: vmvn.i32	d16, #0x2000    @ encoding: [0x30,0x02,0xc2,0xf2]
+	ret <2 x i32> < i32 4294959103, i32 4294959103 >
+}
+
+; CHECK: vmvn_2xi32c
+define <2 x i32> @vmvn_2xi32c() nounwind {
+; CHECK: vmvn.i32	d16, #0x200000  @ encoding: [0x30,0x04,0xc2,0xf2]
+	ret <2 x i32> < i32 4292870143, i32 4292870143 >
+}
+
+; CHECK: vmvn_2xi32d
+define <2 x i32> @vmvn_2xi32d() nounwind {
+; CHECK: vmvn.i32	d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
+	ret <2 x i32> < i32 3758096383, i32 3758096383 >
+}
+
+; CHECK: vmvn_2xi32e
+define <2 x i32> @vmvn_2xi32e() nounwind {
+; CHECK: vmvn.i32	d16, #0x20FF    @ encoding: [0x30,0x0c,0xc2,0xf2]
+	ret <2 x i32> < i32 4294958848, i32 4294958848 >
+}
+
+; CHECK: vmvn_2xi32f
+define <2 x i32> @vmvn_2xi32f() nounwind {
+; CHECK: vmvn.i32	d16, #0x20FFFF  @ encoding: [0x30,0x0d,0xc2,0xf2]
+	ret <2 x i32> < i32 4292804608, i32 4292804608 >
+}



From wdietz2 at illinois.edu  Tue Oct 26 12:41:40 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Tue, 26 Oct 2010 17:41:40 -0000
Subject: [llvm-commits] [poolalloc] r117375 -
	/poolalloc/trunk/lib/DSA/TopDownClosure.cpp
Message-ID: <20101026174140.848E22A6C12C@llvm.org>

Author: wdietz2
Date: Tue Oct 26 12:41:40 2010
New Revision: 117375

URL: http://llvm.org/viewvc/llvm-project?rev=117375&view=rev
Log:
Remove invalid assertion regarding Incomplete and External.

Modified:
    poolalloc/trunk/lib/DSA/TopDownClosure.cpp

Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=117375&r1=117374&r2=117375&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original)
+++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Tue Oct 26 12:41:40 2010
@@ -89,7 +89,6 @@
   for (DSScalarMap::global_iterator I=GGSM.global_begin(), E=GGSM.global_end();
        I != E; ++I) {
     DSNode *N = GGSM.find(*I)->second.getNode();
-    if (N->isIncompleteNode()) assert(N->isExternalNode());
     if (N->isIncompleteNode() || N->isExternalNode())
       markReachableFunctionsExternallyAccessible(N, Visited);
   }



From dpatel at apple.com  Tue Oct 26 12:49:02 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 26 Oct 2010 17:49:02 -0000
Subject: [llvm-commits] [llvm] r117376 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: AsmPrinter.cpp DwarfDebug.cpp
 DwarfDebug.h
Message-ID: <20101026174902.5D9D22A6C12C@llvm.org>

Author: dpatel
Date: Tue Oct 26 12:49:02 2010
New Revision: 117376

URL: http://llvm.org/viewvc/llvm-project?rev=117376&view=rev
Log:
s/beginScope/beginInstruction/g
s/endScope/endInstruction/g


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=117376&r1=117375&r2=117376&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Oct 26 12:49:02 2010
@@ -638,7 +638,7 @@
 
       if (ShouldPrintDebugScopes) {
         NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled);
-        DD->beginScope(II);
+        DD->beginInstruction(II);
       }
       
       if (isVerbose())
@@ -672,7 +672,7 @@
       
       if (ShouldPrintDebugScopes) {
         NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled);
-        DD->endScope(II);
+        DD->endInstruction(II);
       }
     }
   }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=117376&r1=117375&r2=117376&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Oct 26 12:49:02 2010
@@ -2457,8 +2457,8 @@
   return I->second;
 }
 
-/// beginScope - Process beginning of a scope.
-void DwarfDebug::beginScope(const MachineInstr *MI) {
+/// beginInstruction - Process beginning of an instruction.
+void DwarfDebug::beginInstruction(const MachineInstr *MI) {
   if (InsnNeedsLabel.count(MI) == 0) {
     LabelsBeforeInsn[MI] = PrevLabel;
     return;
@@ -2492,8 +2492,8 @@
   assert (0 && "Instruction is not processed!");
 }
 
-/// endScope - Process end of a scope.
-void DwarfDebug::endScope(const MachineInstr *MI) {
+/// endInstruction - Process end of an instruction.
+void DwarfDebug::endInstruction(const MachineInstr *MI) {
   if (InsnsEndScopeSet.count(MI) != 0) {
     // Emit a label if this instruction ends a scope.
     MCSymbol *Label = MMI->getContext().CreateTempSymbol();

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=117376&r1=117375&r2=117376&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Oct 26 12:49:02 2010
@@ -631,11 +631,11 @@
   /// getLabelAfterInsn - Return Label immediately following the instruction.
   const MCSymbol *getLabelAfterInsn(const MachineInstr *MI);
 
-  /// beginScope - Process beginning of a scope.
-  void beginScope(const MachineInstr *MI);
+  /// beginInstruction - Process beginning of an instruction.
+  void beginInstruction(const MachineInstr *MI);
 
-  /// endScope - Prcess end of a scope.
-  void endScope(const MachineInstr *MI);
+  /// endInstruction - Prcess end of an instruction.
+  void endInstruction(const MachineInstr *MI);
 };
 } // End of namespace llvm
 



From grosbach at apple.com  Tue Oct 26 12:54:32 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 26 Oct 2010 10:54:32 -0700
Subject: [llvm-commits] [llvm] r117374 - in /llvm/trunk:
	lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
	test/MC/ARM/neon-bitwise-encoding.ll
	test/MC/ARM/neon-mov-encoding.ll
In-Reply-To: <20101026174054.7DB512A6C12C@llvm.org>
References: <20101026174054.7DB512A6C12C@llvm.org>
Message-ID: <64C844C0-3279-417D-BD65-5C35BAB42227@apple.com>

The lowering for the intrinsics already handles getting the constant into the right format? I'm curious how that works and the asm printing also gets the right value. That's great if it does, it's just rather curious.

-Jim


On Oct 26, 2010, at 10:40 AM, Owen Anderson wrote:

> Author: resistor
> Date: Tue Oct 26 12:40:54 2010
> New Revision: 117374
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=117374&view=rev
> Log:
> Add NEON encodings for vmov and vmvn of immediates.
> 
> Added:
>    llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117374&r1=117373&r2=117374&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Oct 26 12:40:54 2010
> @@ -1683,6 +1683,16 @@
>   let Inst{6}     = op6;
>   let Inst{5}     = op5;
>   let Inst{4}     = op4;
> +  
> +  // Instruction operands.
> +  bits<5> Vd;
> +  bits<13> SIMM;
> +  
> +  let Inst{15-12} = Vd{3-0};
> +  let Inst{22}    = Vd{4};
> +  let Inst{24}    = SIMM{7};
> +  let Inst{18-16} = SIMM{6-4};
> +  let Inst{3-0}   = SIMM{3-0};
> }
> 
> // NEON 2 vector register format.
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117374&r1=117373&r2=117374&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 12:40:54 2010
> @@ -2899,26 +2899,34 @@
> //   VMVN     : Vector Bitwise NOT (Immediate)
> 
> let isReMaterializable = 1 in {
> -// FIXME: This instruction's encoding MAY NOT BE correct.
> +
> def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmvn", "i16", "$dst, $SIMM", "",
> -                         [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
> -// FIXME: This instruction's encoding MAY NOT BE correct.
> +                         [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
> +  let Inst{9} = SIMM{9};
> +}
> +
> def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmvn", "i16", "$dst, $SIMM", "",
> -                         [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
> -// FIXME: This instruction's encoding MAY NOT BE correct.
> +                         [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
> +  let Inst{9} = SIMM{9};
> +}
> +
> def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmvn", "i32", "$dst, $SIMM", "",
> -                         [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
> -// FIXME: This instruction's encoding MAY NOT BE correct.
> +                         [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
> +  let Inst{11-8} = SIMM{11-8};
> +}
> +
> def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmvn", "i32", "$dst, $SIMM", "",
> -                         [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
> +                         [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
> +  let Inst{11-8} = SIMM{11-8};
> +}
> }
> 
> //   VMVN     : Vector Bitwise NOT
> @@ -3387,20 +3395,30 @@
> def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmov", "i16", "$dst, $SIMM", "",
> -                         [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
> +                         [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
> +  let Inst{9} = SIMM{9};                         
> +}
> +
> def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmov", "i16", "$dst, $SIMM", "",
> -                         [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
> +                         [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
> + let Inst{9} = SIMM{9};
> +}
> 
> def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmov", "i32", "$dst, $SIMM", "",
> -                         [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
> +                         [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
> +  let Inst{11-8} = SIMM{11-8};
> +}
> +
> def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
>                          "vmov", "i32", "$dst, $SIMM", "",
> -                         [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
> +                         [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
> +  let Inst{11-8} = SIMM{11-8};
> +}
> 
> def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
>                          (ins nModImm:$SIMM), IIC_VMOVImm,
> 
> Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117374&r1=117373&r2=117374&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
> +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Tue Oct 26 12:40:54 2010
> @@ -2,7 +2,6 @@
> 
> ; FIXME: The following instructions still require testing:
> ;  - vand with immediate, vorr with immediate
> -;  - vmvn of an immediate
> ;  - both vbit and vbif
> 
> ; CHECK: vand_8xi8
> 
> Added: llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.ll?rev=117374&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/neon-mov-encoding.ll (added)
> +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.ll Tue Oct 26 12:40:54 2010
> @@ -0,0 +1,169 @@
> +; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
> +
> +; CHECK: vmov_8xi8
> +define <8 x i8> @vmov_8xi8() nounwind {
> +; CHECK: vmov.i8	d16, #0x8               @ encoding: [0x18,0x0e,0xc0,0xf2]
> +	ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
> +}
> +
> +; CHECK: vmov_4xi16a
> +define <4 x i16> @vmov_4xi16a() nounwind {
> +; CHECK: vmov.i16	d16, #0x10      @ encoding: [0x10,0x08,0xc1,0xf2]
> +	ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
> +}
> +
> +; CHECK: vmov_4xi16b
> +define <4 x i16> @vmov_4xi16b() nounwind {
> +; CHECK: vmov.i16	d16, #0x1000    @ encoding: [0x10,0x0a,0xc1,0xf2]
> +	ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
> +}
> +
> +; CHECK: vmov_2xi32a
> +define <2 x i32> @vmov_2xi32a() nounwind {
> +; CHECK: vmov.i32	d16, #0x20      @ encoding: [0x10,0x00,0xc2,0xf2]
> +	ret <2 x i32> < i32 32, i32 32 >
> +}
> +
> +; CHECK: vmov_2xi32b
> +define <2 x i32> @vmov_2xi32b() nounwind {
> +; CHECK: vmov.i32	d16, #0x2000    @ encoding: [0x10,0x02,0xc2,0xf2]
> +	ret <2 x i32> < i32 8192, i32 8192 >
> +}
> +
> +; CHECK: vmov_2xi32c
> +define <2 x i32> @vmov_2xi32c() nounwind {
> +; CHECK: vmov.i32	d16, #0x200000  @ encoding: [0x10,0x04,0xc2,0xf2]
> +	ret <2 x i32> < i32 2097152, i32 2097152 >
> +}
> +
> +; CHECK: vmov_2xi32d
> +define <2 x i32> @vmov_2xi32d() nounwind {
> +; CHECK: vmov.i32	d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
> +	ret <2 x i32> < i32 536870912, i32 536870912 >
> +}
> +
> +; CHECK: vmov_2xi32e
> +define <2 x i32> @vmov_2xi32e() nounwind {
> +; CHECK: vmov.i32	d16, #0x20FF    @ encoding: [0x10,0x0c,0xc2,0xf2]
> +	ret <2 x i32> < i32 8447, i32 8447 >
> +}
> +
> +; CHECK: vmov_2xi32f
> +define <2 x i32> @vmov_2xi32f() nounwind {
> +; CHECK: vmov.i32	d16, #0x20FFFF  @ encoding: [0x10,0x0d,0xc2,0xf2]
> +	ret <2 x i32> < i32 2162687, i32 2162687 >
> +}
> +
> +; CHECK: vmov_1xi64
> +define <1 x i64> @vmov_1xi64() nounwind {
> +; CHECK: vmov.i64	d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
> +	ret <1 x i64> < i64 18374687574888349695 >
> +}
> +
> +; CHECK: vmov_16xi8
> +define <16 x i8> @vmov_16xi8() nounwind {
> +; CHECK: vmov.i8	q8, #0x8                @ encoding: [0x58,0x0e,0xc0,0xf2]
> +	ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
> +}
> +
> +; CHECK: vmov_8xi16a
> +define <8 x i16> @vmov_8xi16a() nounwind {
> +; CHECK: vmov.i16	q8, #0x10       @ encoding: [0x50,0x08,0xc1,0xf2]
> +	ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
> +}
> +
> +; CHECK: vmov_8xi16b
> +define <8 x i16> @vmov_8xi16b() nounwind {
> +; CHECK: vmov.i16	q8, #0x1000     @ encoding: [0x50,0x0a,0xc1,0xf2]
> +	ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
> +}
> +
> +; CHECK: vmov_4xi32a
> +define <4 x i32> @vmov_4xi32a() nounwind {
> +; CHECK: vmov.i32	q8, #0x20       @ encoding: [0x50,0x00,0xc2,0xf2]
> +	ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
> +}
> +
> +; CHECK: vmov_4xi32b
> +define <4 x i32> @vmov_4xi32b() nounwind {
> +; CHECK: vmov.i32	q8, #0x2000     @ encoding: [0x50,0x02,0xc2,0xf2]
> +	ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
> +}
> +
> +; CHECK: vmov_4xi32c
> +define <4 x i32> @vmov_4xi32c() nounwind {
> +; CHECK: vmov.i32	q8, #0x200000   @ encoding: [0x50,0x04,0xc2,0xf2]
> +	ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
> +}
> +
> +; CHECK: vmov_4xi32d
> +define <4 x i32> @vmov_4xi32d() nounwind {
> +; CHECK: vmov.i32	q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
> +	ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
> +}
> +
> +; CHECK: vmov_4xi32e
> +define <4 x i32> @vmov_4xi32e() nounwind {
> +; CHECK: vmov.i32	q8, #0x20FF     @ encoding: [0x50,0x0c,0xc2,0xf2]
> +	ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
> +}
> +
> +; CHECK: vmov_4xi32f
> +define <4 x i32> @vmov_4xi32f() nounwind {
> +; CHECK: vmov.i32	q8, #0x20FFFF   @ encoding: [0x50,0x0d,0xc2,0xf2]
> +	ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
> +}
> +
> +; CHECK: vmov_2xi64
> +define <2 x i64> @vmov_2xi64() nounwind {
> +; CHECK: vmov.i64	q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
> +	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
> +}
> +
> +; CHECK: vmvn_4xi16a
> +define <4 x i16> @vmvn_4xi16a() nounwind {
> +; CHECK: vmvn.i16	d16, #0x10      @ encoding: [0x30,0x08,0xc1,0xf2]
> +	ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
> +}
> +
> +; CHECK: vmvn_4xi16b
> +define <4 x i16> @vmvn_4xi16b() nounwind {
> +; CHECK: vmvn.i16	d16, #0x1000    @ encoding: [0x30,0x0a,0xc1,0xf2]
> +	ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
> +}
> +
> +; CHECK: vmvn_2xi32a
> +define <2 x i32> @vmvn_2xi32a() nounwind {
> +; CHECK: vmvn.i32	d16, #0x20      @ encoding: [0x30,0x00,0xc2,0xf2]
> +	ret <2 x i32> < i32 4294967263, i32 4294967263 >
> +}
> +
> +; CHECK: vmvn_2xi32b
> +define <2 x i32> @vmvn_2xi32b() nounwind {
> +; CHECK: vmvn.i32	d16, #0x2000    @ encoding: [0x30,0x02,0xc2,0xf2]
> +	ret <2 x i32> < i32 4294959103, i32 4294959103 >
> +}
> +
> +; CHECK: vmvn_2xi32c
> +define <2 x i32> @vmvn_2xi32c() nounwind {
> +; CHECK: vmvn.i32	d16, #0x200000  @ encoding: [0x30,0x04,0xc2,0xf2]
> +	ret <2 x i32> < i32 4292870143, i32 4292870143 >
> +}
> +
> +; CHECK: vmvn_2xi32d
> +define <2 x i32> @vmvn_2xi32d() nounwind {
> +; CHECK: vmvn.i32	d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
> +	ret <2 x i32> < i32 3758096383, i32 3758096383 >
> +}
> +
> +; CHECK: vmvn_2xi32e
> +define <2 x i32> @vmvn_2xi32e() nounwind {
> +; CHECK: vmvn.i32	d16, #0x20FF    @ encoding: [0x30,0x0c,0xc2,0xf2]
> +	ret <2 x i32> < i32 4294958848, i32 4294958848 >
> +}
> +
> +; CHECK: vmvn_2xi32f
> +define <2 x i32> @vmvn_2xi32f() nounwind {
> +; CHECK: vmvn.i32	d16, #0x20FFFF  @ encoding: [0x30,0x0d,0xc2,0xf2]
> +	ret <2 x i32> < i32 4292804608, i32 4292804608 >
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From resistor at mac.com  Tue Oct 26 13:04:51 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 18:04:51 -0000
Subject: [llvm-commits] [llvm] r117377 -
	/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll
Message-ID: <20101026180451.C52682A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 13:04:51 2010
New Revision: 117377

URL: http://llvm.org/viewvc/llvm-project?rev=117377&view=rev
Log:
Tests for NEON encoding of vpadd and vpaddl.

Added:
    llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll?rev=117377&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll Tue Oct 26 13:04:51 2010
@@ -0,0 +1,155 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8>  @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vpadd_8xi8
+define <8 x i8> @vpadd_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpadd.i8	d16, d17, d16   @ encoding: [0xb0,0x0b,0x41,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vpadd_4xi16
+define <4 x i16> @vpadd_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpadd.i16	d16, d17, d16   @ encoding: [0xb0,0x0b,0x51,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpadd_2xi32
+define <2 x i32> @vpadd_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpadd.i32	d16, d17, d16   @ encoding: [0xb0,0x0b,0x61,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+; CHECK: vpadd_2xfloat
+define <2 x float> @vpadd_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vpadd.f32	d16, d16, d17   @ encoding: [0xa1,0x0d,0x40,0xf3]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
+
+; CHECK: vpaddls_8xi8
+define <4 x i16> @vpaddls_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vpaddl.s8	d16, d16        @ encoding: [0x20,0x02,0xf0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vpaddls_4xi16
+define <2 x i32> @vpaddls_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vpaddl.s16	d16, d16        @ encoding: [0x20,0x02,0xf4,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vpaddls_2xi32
+define <1 x i64> @vpaddls_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vpaddl.s32	d16, d16        @ encoding: [0x20,0x02,0xf8,0xf3]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
+	ret <1 x i64> %tmp2
+}
+
+declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone
+
+; CHECK: vpaddlu_8xi8
+define <4 x i16> @vpaddlu_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vpaddl.u8	d16, d16        @ encoding: [0xa0,0x02,0xf0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vpaddlu_4xi16
+define <2 x i32> @vpaddlu_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vpaddl.u16	d16, d16        @ encoding: [0xa0,0x02,0xf4,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vpaddlu_2xi32
+define <1 x i64> @vpaddlu_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vpaddl.u32	d16, d16        @ encoding: [0xa0,0x02,0xf8,0xf3]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
+	ret <1 x i64> %tmp2
+}
+
+declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone
+
+; CHECK: vpaddls_16xi8
+define <8 x i16> @vpaddls_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vpaddl.s8	q8, q8          @ encoding: [0x60,0x02,0xf0,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vpaddls_8xi16
+define <4 x i32> @vpaddls_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vpaddl.s16	q8, q8          @ encoding: [0x60,0x02,0xf4,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vpaddls_4xi32
+define <2 x i64> @vpaddls_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vpaddl.s32	q8, q8          @ encoding: [0x60,0x02,0xf8,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
+	ret <2 x i64> %tmp2
+}
+
+declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
+
+; CHECK: vpaddlu_16xi8
+define <8 x i16> @vpaddlu_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vpaddl.u8	q8, q8          @ encoding: [0xe0,0x02,0xf0,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vpaddlu_8xi16
+define <4 x i32> @vpaddlu_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vpaddl.u16	q8, q8          @ encoding: [0xe0,0x02,0xf4,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vpaddlu_4xi32
+define <2 x i64> @vpaddlu_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vpaddl.u32	q8, q8          @ encoding: [0xe0,0x02,0xf8,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
+	ret <2 x i64> %tmp2
+}



From rafael.espindola at gmail.com  Tue Oct 26 13:09:55 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 26 Oct 2010 18:09:55 -0000
Subject: [llvm-commits] [llvm] r117378 -
	/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
Message-ID: <20101026180955.8542B2A6C12C@llvm.org>

Author: rafael
Date: Tue Oct 26 13:09:55 2010
New Revision: 117378

URL: http://llvm.org/viewvc/llvm-project?rev=117378&view=rev
Log:
handle X86::EH_RETURN64 and X86::EH_RETURN.

Modified:
    llvm/trunk/lib/Target/X86/X86MCInstLower.cpp

Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=117378&r1=117377&r2=117378&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Tue Oct 26 13:09:55 2010
@@ -12,6 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "InstPrinter/X86ATTInstPrinter.h"
 #include "X86MCInstLower.h"
 #include "X86AsmPrinter.h"
 #include "X86COFFMachineModuleInfo.h"
@@ -415,6 +416,13 @@
     break;
   }
 
+  case X86::EH_RETURN:
+  case X86::EH_RETURN64: {
+    OutMI = MCInst();
+    OutMI.setOpcode(X86::RET);
+    break;
+  }
+
   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
   case X86::TAILJMPr:
   case X86::TAILJMPd:
@@ -543,6 +551,15 @@
       OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
     return;
         
+
+  case X86::EH_RETURN:
+  case X86::EH_RETURN64: {
+    // Lower these as normal, but add some comments.
+    unsigned Reg = MI->getOperand(0).getReg();
+    OutStreamer.AddComment(StringRef("eh_return, addr: %") +
+                           X86ATTInstPrinter::getRegisterName(Reg));
+    break;
+  }
   case X86::TAILJMPr:
   case X86::TAILJMPd:
   case X86::TAILJMPd64:



From bob.wilson at apple.com  Tue Oct 26 13:12:33 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 26 Oct 2010 11:12:33 -0700
Subject: [llvm-commits] [llvm] r117374 - in /llvm/trunk:
	lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
	test/MC/ARM/neon-bitwise-encoding.ll	test/MC/ARM/neon-mov-encoding.ll
In-Reply-To: <64C844C0-3279-417D-BD65-5C35BAB42227@apple.com>
References: <20101026174054.7DB512A6C12C@llvm.org>
	<64C844C0-3279-417D-BD65-5C35BAB42227@apple.com>
Message-ID: <AA1B90A4-1DD8-49F8-8EC9-839294662B55@apple.com>

The NEON modified immediate values are curious!  I admit it is a little strange to have the encoding done when lowering, but it was easier that way.  Search for "NEONModImm" in ARMAddressingModes.h for details.

On Oct 26, 2010, at 10:54 AM, Jim Grosbach wrote:

> The lowering for the intrinsics already handles getting the constant into the right format? I'm curious how that works and the asm printing also gets the right value. That's great if it does, it's just rather curious.
> 
> -Jim
> 
> 
> On Oct 26, 2010, at 10:40 AM, Owen Anderson wrote:
> 
>> Author: resistor
>> Date: Tue Oct 26 12:40:54 2010
>> New Revision: 117374
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=117374&view=rev
>> Log:
>> Add NEON encodings for vmov and vmvn of immediates.
>> 
>> Added:
>>   llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>>   llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>   llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117374&r1=117373&r2=117374&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Oct 26 12:40:54 2010
>> @@ -1683,6 +1683,16 @@
>>  let Inst{6}     = op6;
>>  let Inst{5}     = op5;
>>  let Inst{4}     = op4;
>> +  
>> +  // Instruction operands.
>> +  bits<5> Vd;
>> +  bits<13> SIMM;
>> +  
>> +  let Inst{15-12} = Vd{3-0};
>> +  let Inst{22}    = Vd{4};
>> +  let Inst{24}    = SIMM{7};
>> +  let Inst{18-16} = SIMM{6-4};
>> +  let Inst{3-0}   = SIMM{3-0};
>> }
>> 
>> // NEON 2 vector register format.
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117374&r1=117373&r2=117374&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 12:40:54 2010
>> @@ -2899,26 +2899,34 @@
>> //   VMVN     : Vector Bitwise NOT (Immediate)
>> 
>> let isReMaterializable = 1 in {
>> -// FIXME: This instruction's encoding MAY NOT BE correct.
>> +
>> def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmvn", "i16", "$dst, $SIMM", "",
>> -                         [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
>> -// FIXME: This instruction's encoding MAY NOT BE correct.
>> +                         [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
>> +  let Inst{9} = SIMM{9};
>> +}
>> +
>> def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmvn", "i16", "$dst, $SIMM", "",
>> -                         [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
>> -// FIXME: This instruction's encoding MAY NOT BE correct.
>> +                         [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
>> +  let Inst{9} = SIMM{9};
>> +}
>> +
>> def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmvn", "i32", "$dst, $SIMM", "",
>> -                         [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
>> -// FIXME: This instruction's encoding MAY NOT BE correct.
>> +                         [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
>> +  let Inst{11-8} = SIMM{11-8};
>> +}
>> +
>> def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmvn", "i32", "$dst, $SIMM", "",
>> -                         [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
>> +                         [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
>> +  let Inst{11-8} = SIMM{11-8};
>> +}
>> }
>> 
>> //   VMVN     : Vector Bitwise NOT
>> @@ -3387,20 +3395,30 @@
>> def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmov", "i16", "$dst, $SIMM", "",
>> -                         [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>;
>> +                         [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
>> +  let Inst{9} = SIMM{9};                         
>> +}
>> +
>> def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmov", "i16", "$dst, $SIMM", "",
>> -                         [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>;
>> +                         [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
>> + let Inst{9} = SIMM{9};
>> +}
>> 
>> def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmov", "i32", "$dst, $SIMM", "",
>> -                         [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>;
>> +                         [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
>> +  let Inst{11-8} = SIMM{11-8};
>> +}
>> +
>> def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>>                         "vmov", "i32", "$dst, $SIMM", "",
>> -                         [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>;
>> +                         [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
>> +  let Inst{11-8} = SIMM{11-8};
>> +}
>> 
>> def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
>>                         (ins nModImm:$SIMM), IIC_VMOVImm,
>> 
>> Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll?rev=117374&r1=117373&r2=117374&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll (original)
>> +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.ll Tue Oct 26 12:40:54 2010
>> @@ -2,7 +2,6 @@
>> 
>> ; FIXME: The following instructions still require testing:
>> ;  - vand with immediate, vorr with immediate
>> -;  - vmvn of an immediate
>> ;  - both vbit and vbif
>> 
>> ; CHECK: vand_8xi8
>> 
>> Added: llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.ll?rev=117374&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/neon-mov-encoding.ll (added)
>> +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.ll Tue Oct 26 12:40:54 2010
>> @@ -0,0 +1,169 @@
>> +; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
>> +
>> +; CHECK: vmov_8xi8
>> +define <8 x i8> @vmov_8xi8() nounwind {
>> +; CHECK: vmov.i8	d16, #0x8               @ encoding: [0x18,0x0e,0xc0,0xf2]
>> +	ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
>> +}
>> +
>> +; CHECK: vmov_4xi16a
>> +define <4 x i16> @vmov_4xi16a() nounwind {
>> +; CHECK: vmov.i16	d16, #0x10      @ encoding: [0x10,0x08,0xc1,0xf2]
>> +	ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
>> +}
>> +
>> +; CHECK: vmov_4xi16b
>> +define <4 x i16> @vmov_4xi16b() nounwind {
>> +; CHECK: vmov.i16	d16, #0x1000    @ encoding: [0x10,0x0a,0xc1,0xf2]
>> +	ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
>> +}
>> +
>> +; CHECK: vmov_2xi32a
>> +define <2 x i32> @vmov_2xi32a() nounwind {
>> +; CHECK: vmov.i32	d16, #0x20      @ encoding: [0x10,0x00,0xc2,0xf2]
>> +	ret <2 x i32> < i32 32, i32 32 >
>> +}
>> +
>> +; CHECK: vmov_2xi32b
>> +define <2 x i32> @vmov_2xi32b() nounwind {
>> +; CHECK: vmov.i32	d16, #0x2000    @ encoding: [0x10,0x02,0xc2,0xf2]
>> +	ret <2 x i32> < i32 8192, i32 8192 >
>> +}
>> +
>> +; CHECK: vmov_2xi32c
>> +define <2 x i32> @vmov_2xi32c() nounwind {
>> +; CHECK: vmov.i32	d16, #0x200000  @ encoding: [0x10,0x04,0xc2,0xf2]
>> +	ret <2 x i32> < i32 2097152, i32 2097152 >
>> +}
>> +
>> +; CHECK: vmov_2xi32d
>> +define <2 x i32> @vmov_2xi32d() nounwind {
>> +; CHECK: vmov.i32	d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
>> +	ret <2 x i32> < i32 536870912, i32 536870912 >
>> +}
>> +
>> +; CHECK: vmov_2xi32e
>> +define <2 x i32> @vmov_2xi32e() nounwind {
>> +; CHECK: vmov.i32	d16, #0x20FF    @ encoding: [0x10,0x0c,0xc2,0xf2]
>> +	ret <2 x i32> < i32 8447, i32 8447 >
>> +}
>> +
>> +; CHECK: vmov_2xi32f
>> +define <2 x i32> @vmov_2xi32f() nounwind {
>> +; CHECK: vmov.i32	d16, #0x20FFFF  @ encoding: [0x10,0x0d,0xc2,0xf2]
>> +	ret <2 x i32> < i32 2162687, i32 2162687 >
>> +}
>> +
>> +; CHECK: vmov_1xi64
>> +define <1 x i64> @vmov_1xi64() nounwind {
>> +; CHECK: vmov.i64	d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
>> +	ret <1 x i64> < i64 18374687574888349695 >
>> +}
>> +
>> +; CHECK: vmov_16xi8
>> +define <16 x i8> @vmov_16xi8() nounwind {
>> +; CHECK: vmov.i8	q8, #0x8                @ encoding: [0x58,0x0e,0xc0,0xf2]
>> +	ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
>> +}
>> +
>> +; CHECK: vmov_8xi16a
>> +define <8 x i16> @vmov_8xi16a() nounwind {
>> +; CHECK: vmov.i16	q8, #0x10       @ encoding: [0x50,0x08,0xc1,0xf2]
>> +	ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
>> +}
>> +
>> +; CHECK: vmov_8xi16b
>> +define <8 x i16> @vmov_8xi16b() nounwind {
>> +; CHECK: vmov.i16	q8, #0x1000     @ encoding: [0x50,0x0a,0xc1,0xf2]
>> +	ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
>> +}
>> +
>> +; CHECK: vmov_4xi32a
>> +define <4 x i32> @vmov_4xi32a() nounwind {
>> +; CHECK: vmov.i32	q8, #0x20       @ encoding: [0x50,0x00,0xc2,0xf2]
>> +	ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
>> +}
>> +
>> +; CHECK: vmov_4xi32b
>> +define <4 x i32> @vmov_4xi32b() nounwind {
>> +; CHECK: vmov.i32	q8, #0x2000     @ encoding: [0x50,0x02,0xc2,0xf2]
>> +	ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
>> +}
>> +
>> +; CHECK: vmov_4xi32c
>> +define <4 x i32> @vmov_4xi32c() nounwind {
>> +; CHECK: vmov.i32	q8, #0x200000   @ encoding: [0x50,0x04,0xc2,0xf2]
>> +	ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
>> +}
>> +
>> +; CHECK: vmov_4xi32d
>> +define <4 x i32> @vmov_4xi32d() nounwind {
>> +; CHECK: vmov.i32	q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
>> +	ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
>> +}
>> +
>> +; CHECK: vmov_4xi32e
>> +define <4 x i32> @vmov_4xi32e() nounwind {
>> +; CHECK: vmov.i32	q8, #0x20FF     @ encoding: [0x50,0x0c,0xc2,0xf2]
>> +	ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
>> +}
>> +
>> +; CHECK: vmov_4xi32f
>> +define <4 x i32> @vmov_4xi32f() nounwind {
>> +; CHECK: vmov.i32	q8, #0x20FFFF   @ encoding: [0x50,0x0d,0xc2,0xf2]
>> +	ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
>> +}
>> +
>> +; CHECK: vmov_2xi64
>> +define <2 x i64> @vmov_2xi64() nounwind {
>> +; CHECK: vmov.i64	q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
>> +	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
>> +}
>> +
>> +; CHECK: vmvn_4xi16a
>> +define <4 x i16> @vmvn_4xi16a() nounwind {
>> +; CHECK: vmvn.i16	d16, #0x10      @ encoding: [0x30,0x08,0xc1,0xf2]
>> +	ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
>> +}
>> +
>> +; CHECK: vmvn_4xi16b
>> +define <4 x i16> @vmvn_4xi16b() nounwind {
>> +; CHECK: vmvn.i16	d16, #0x1000    @ encoding: [0x30,0x0a,0xc1,0xf2]
>> +	ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
>> +}
>> +
>> +; CHECK: vmvn_2xi32a
>> +define <2 x i32> @vmvn_2xi32a() nounwind {
>> +; CHECK: vmvn.i32	d16, #0x20      @ encoding: [0x30,0x00,0xc2,0xf2]
>> +	ret <2 x i32> < i32 4294967263, i32 4294967263 >
>> +}
>> +
>> +; CHECK: vmvn_2xi32b
>> +define <2 x i32> @vmvn_2xi32b() nounwind {
>> +; CHECK: vmvn.i32	d16, #0x2000    @ encoding: [0x30,0x02,0xc2,0xf2]
>> +	ret <2 x i32> < i32 4294959103, i32 4294959103 >
>> +}
>> +
>> +; CHECK: vmvn_2xi32c
>> +define <2 x i32> @vmvn_2xi32c() nounwind {
>> +; CHECK: vmvn.i32	d16, #0x200000  @ encoding: [0x30,0x04,0xc2,0xf2]
>> +	ret <2 x i32> < i32 4292870143, i32 4292870143 >
>> +}
>> +
>> +; CHECK: vmvn_2xi32d
>> +define <2 x i32> @vmvn_2xi32d() nounwind {
>> +; CHECK: vmvn.i32	d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
>> +	ret <2 x i32> < i32 3758096383, i32 3758096383 >
>> +}
>> +
>> +; CHECK: vmvn_2xi32e
>> +define <2 x i32> @vmvn_2xi32e() nounwind {
>> +; CHECK: vmvn.i32	d16, #0x20FF    @ encoding: [0x30,0x0c,0xc2,0xf2]
>> +	ret <2 x i32> < i32 4294958848, i32 4294958848 >
>> +}
>> +
>> +; CHECK: vmvn_2xi32f
>> +define <2 x i32> @vmvn_2xi32f() nounwind {
>> +; CHECK: vmvn.i32	d16, #0x20FFFF  @ encoding: [0x30,0x0d,0xc2,0xf2]
>> +	ret <2 x i32> < i32 4292804608, i32 4292804608 >
>> +}
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From daniel at zuster.org  Tue Oct 26 13:11:46 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 26 Oct 2010 18:11:46 -0000
Subject: [llvm-commits] [test-suite] r117379 -
 /test-suite/trunk/SingleSource/UnitTests/stmtexpr.reference_output
Message-ID: <20101026181146.C76852A6C12C@llvm.org>

Author: ddunbar
Date: Tue Oct 26 13:11:46 2010
New Revision: 117379

URL: http://llvm.org/viewvc/llvm-project?rev=117379&view=rev
Log:
Add a reference output.

Added:
    test-suite/trunk/SingleSource/UnitTests/stmtexpr.reference_output

Added: test-suite/trunk/SingleSource/UnitTests/stmtexpr.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/stmtexpr.reference_output?rev=117379&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/stmtexpr.reference_output (added)
+++ test-suite/trunk/SingleSource/UnitTests/stmtexpr.reference_output Tue Oct 26 13:11:46 2010
@@ -0,0 +1 @@
+exit 0



From resistor at mac.com  Tue Oct 26 13:18:04 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 18:18:04 -0000
Subject: [llvm-commits] [llvm] r117380 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-pairwise-encoding.ll
Message-ID: <20101026181804.176792A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 13:18:03 2010
New Revision: 117380

URL: http://llvm.org/viewvc/llvm-project?rev=117380&view=rev
Log:
Add correct NEON encoding for vpadal.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117380&r1=117379&r2=117380&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 13:18:03 2010
@@ -1659,17 +1659,17 @@
                  string OpcodeStr, string Dt,
                  ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
   : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
-        (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), IIC_VPALiD,
-        OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
-        [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
+        (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
+        OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
+        [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
                  bits<2> op17_16, bits<5> op11_7, bit op4,
                  string OpcodeStr, string Dt,
                  ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
   : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
-        (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), IIC_VPALiQ,
-        OpcodeStr, Dt, "$dst, $src2", "$src1 = $dst",
-        [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
+        (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
+        OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
+        [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
 
 // Shift by immediate,
 // both double- and quad-register.

Modified: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll?rev=117380&r1=117379&r2=117380&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll Tue Oct 26 13:18:03 2010
@@ -153,3 +153,127 @@
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
 	ret <2 x i64> %tmp2
 }
+
+declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
+
+; CHECK: vpadals_8xi8
+define <4 x i16> @vpadals_8xi8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpadal.s8	d16, d17        @ encoding: [0x21,0x06,0xf0,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpadals_4xi16
+define <2 x i32> @vpadals_4xi16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpadal.s16	d16, d17        @ encoding: [0x21,0x06,0xf4,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vpadals_2xi32
+define <1 x i64> @vpadals_2xi32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpadal.s32	d16, d17        @ encoding: [0x21,0x06,0xf8,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
+
+; CHECK: vpadalu_8xi8
+define <4 x i16> @vpadalu_8xi8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpadal.u8	d16, d17        @ encoding: [0xa1,0x06,0xf0,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpadalu_4xi16
+define <2 x i32> @vpadalu_4xi16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpadal.u16	d16, d17        @ encoding: [0xa1,0x06,0xf4,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vpadalu_2xi32
+define <1 x i64> @vpadalu_2xi32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpadal.u32	d16, d17        @ encoding: [0xa1,0x06,0xf8,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
+
+; CHECK: vpadals_16xi8
+define <8 x i16> @vpadals_16xi8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vpadal.s8	q9, q8          @ encoding: [0x60,0x26,0xf0,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vpadals_8xi16
+define <4 x i32> @vpadals_8xi16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vpadal.s16	q9, q8          @ encoding: [0x60,0x26,0xf4,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+; CHECK: vpadals_4xi32
+define <2 x i64> @vpadals_4xi32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vpadal.s32	q9, q8          @ encoding: [0x60,0x26,0xf8,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
+
+; CHECK: vpadalu_16xi8
+define <8 x i16> @vpadalu_16xi8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vpadal.u8	q9, q8          @ encoding: [0xe0,0x26,0xf0,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vpadalu_8xi16
+define <4 x i32> @vpadalu_8xi16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vpadal.u16	q9, q8          @ encoding: [0xe0,0x26,0xf4,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+; CHECK: vpadalu_4xi32
+define <2 x i64> @vpadalu_4xi32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vpadal.u32	q9, q8          @ encoding: [0xe0,0x26,0xf8,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
+	ret <2 x i64> %tmp3
+}



From resistor at mac.com  Tue Oct 26 13:31:48 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 18:31:48 -0000
Subject: [llvm-commits] [llvm] r117382 -
	/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll
Message-ID: <20101026183148.276B92A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 13:31:47 2010
New Revision: 117382

URL: http://llvm.org/viewvc/llvm-project?rev=117382&view=rev
Log:
Tests for NEON encodings of vpmin and vpmax.

Modified:
    llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll?rev=117382&r1=117381&r2=117382&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.ll Tue Oct 26 13:31:47 2010
@@ -277,3 +277,149 @@
 	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
 	ret <2 x i64> %tmp3
 }
+
+declare <8 x i8>  @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vpmins_8xi8
+define <8 x i8> @vpmins_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpmin.s8	d16, d16, d17   @ encoding: [0xb1,0x0a,0x40,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vpmins_4xi16
+define <4 x i16> @vpmins_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpmin.s16	d16, d16, d17   @ encoding: [0xb1,0x0a,0x50,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpmins_2xi32
+define <2 x i32> @vpmins_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpmin.s32	d16, d16, d17   @ encoding: [0xb1,0x0a,0x60,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vpminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vpminu_8xi8
+define <8 x i8> @vpminu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpmin.u8	d16, d16, d17   @ encoding: [0xb1,0x0a,0x40,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vpminu_4xi16
+define <4 x i16> @vpminu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpmin.u16	d16, d16, d17   @ encoding: [0xb1,0x0a,0x50,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpminu_2xi32
+define <2 x i32> @vpminu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpmin.u32	d16, d16, d17   @ encoding: [0xb1,0x0a,0x60,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+; CHECK: vpmin_2xfloat
+define <2 x float> @vpmin_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vpmin.f32	d16, d16, d17   @ encoding: [0xa1,0x0f,0x60,0xf3]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vpmaxs_8xi8
+define <8 x i8> @vpmaxs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpmax.s8	d16, d16, d17   @ encoding: [0xa1,0x0a,0x40,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vpmaxs_4xi16
+define <4 x i16> @vpmaxs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpmax.s16	d16, d16, d17   @ encoding: [0xa1,0x0a,0x50,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpmaxs_2xi32
+define <2 x i32> @vpmaxs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpmax.s32	d16, d16, d17   @ encoding: [0xa1,0x0a,0x60,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vpmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vpmaxu_8xi8
+define <8 x i8> @vpmaxu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vpmax.u8	d16, d16, d17   @ encoding: [0xa1,0x0a,0x40,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vpmaxu_4xi16
+define <4 x i16> @vpmaxu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vpmax.u16	d16, d16, d17   @ encoding: [0xa1,0x0a,0x50,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vpmaxu_2xi32
+define <2 x i32> @vpmaxu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vpmax.u32	d16, d16, d17   @ encoding: [0xa1,0x0a,0x60,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+; CHECK: vpmax_2xfloat
+define <2 x float> @vpmax_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vpmax.f32	d16, d16, d17   @ encoding: [0xa1,0x0f,0x40,0xf3]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}



From atrick at apple.com  Tue Oct 26 13:34:01 2010
From: atrick at apple.com (Andrew Trick)
Date: Tue, 26 Oct 2010 18:34:01 -0000
Subject: [llvm-commits] [llvm] r117384 - in /llvm/trunk/lib/CodeGen:
 LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp
Message-ID: <20101026183401.E2D6D2A6C12D@llvm.org>

Author: atrick
Date: Tue Oct 26 13:34:01 2010
New Revision: 117384

URL: http://llvm.org/viewvc/llvm-project?rev=117384&view=rev
Log:
Jakob's review of the basic register allocator.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
    llvm/trunk/lib/CodeGen/RegAllocBase.h
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117384&r1=117383&r2=117384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Oct 26 13:34:01 2010
@@ -21,6 +21,9 @@
 using namespace llvm;
 
 // Merge a LiveInterval's segments. Guarantee no overlaps.
+//
+// Consider coalescing adjacent segments to save space, even though it makes
+// extraction more complicated.
 void LiveIntervalUnion::unify(LiveInterval &lvr) {
   // Add this live virtual register to the union
   LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
@@ -34,19 +37,21 @@
     LiveSegment segment(lvrI->start, lvrI->end, lvr);
     segPos = segments_.insert(segPos, segment);
     assert(*segPos == segment && "need equal val for equal key");
+#ifndef NDEBUG
+    // check for overlap (inductively)
+    if (segPos != segments_.begin()) {
+      SegmentIter prevPos = segPos;
+      --prevPos;
+      assert(prevPos->end <= segment.start && "overlapping segments" );
+    }
+    SegmentIter nextPos = segPos;
+    ++nextPos;
+    if (nextPos != segments_.end())
+      assert(segment.end <= nextPos->start && "overlapping segments" );
+#endif // NDEBUG
   }
 }
 
-namespace {
-
-// Keep LVRs sorted for fast membership test and extraction.
-struct LessReg
-  : public std::binary_function<LiveInterval*, LiveInterval*, bool> {
-  bool operator()(const LiveInterval *left, const LiveInterval *right) const {
-    return left->reg < right->reg;
-  }
-};
-                    
 // Low-level helper to find the first segment in the range [segI,segEnd) that
 // intersects with a live virtual register segment, or segI.start >= lvr.end
 //
@@ -67,10 +72,8 @@
 // Assuming intervals are disjoint, if an intersection exists, it must be the
 // segment found or immediately behind it. We continue reverse iterating to
 // return the first overlap.
-//
-// FIXME: support extract(), handle tombstones of extracted lvrs.
 typedef LiveIntervalUnion::SegmentIter SegmentIter;
-SegmentIter upperBound(SegmentIter segBegin,
+static SegmentIter upperBound(SegmentIter segBegin,
                        SegmentIter segEnd,
                        const LiveRange &lvrSeg) {
   assert(lvrSeg.end > segBegin->start && "segment iterator precondition");
@@ -84,7 +87,6 @@
   }
   return segI;
 }
-} // end anonymous namespace
 
 // Private interface accessed by Query.
 //

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=117384&r1=117383&r2=117384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Oct 26 13:34:01 2010
@@ -23,13 +23,16 @@
 
 namespace llvm {
 
-// A LiveSegment is a copy of a LiveRange object used within
-// LiveIntervalUnion. LiveSegment additionally contains a pointer to its
-// original live virtual register (LiveInterval). This allows quick lookup of
-// the live virtual register as we iterate over live segments in a union. Note
-// that LiveRange is misnamed and actually represents only a single contiguous
-// interval within a virtual register's liveness. To limit confusion, in this
-// file we refer it as a live segment.
+/// A LiveSegment is a copy of a LiveRange object used within
+/// LiveIntervalUnion. LiveSegment additionally contains a pointer to its
+/// original live virtual register (LiveInterval). This allows quick lookup of
+/// the live virtual register as we iterate over live segments in a union. Note
+/// that LiveRange is misnamed and actually represents only a single contiguous
+/// interval within a virtual register's liveness. To limit confusion, in this
+/// file we refer it as a live segment.
+///
+/// Note: This currently represents a half-open interval [start,end).
+/// If LiveRange is modified to represent a closed interval, so should this.
 struct LiveSegment {
   SlotIndex start;
   SlotIndex end;
@@ -46,16 +49,10 @@
     return !operator==(ls);
   }
 
-  bool operator<(const LiveSegment &ls) const {
-    return start < ls.start || (start == ls.start && end < ls.end);
-  }
+  // Order segments by starting point only--we expect them to be disjoint.
+  bool operator<(const LiveSegment &ls) const { return start < ls.start; }
 };
 
-/// Compare a live virtual register segment to a LiveIntervalUnion segment.
-inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
-  return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
-}
-
 inline bool operator<(SlotIndex V, const LiveSegment &ls) {
   return V < ls.start;
 }
@@ -64,6 +61,11 @@
   return ls.start < V;
 }
 
+/// Compare a live virtual register segment to a LiveIntervalUnion segment.
+inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
+  return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
+}
+
 /// Union of live intervals that are strong candidates for coalescing into a
 /// single register (either physical or virtual depending on the context).  We
 /// expect the constituent live intervals to be disjoint, although we may
@@ -100,13 +102,18 @@
 public:
   // default ctor avoids placement new
   LiveIntervalUnion() : repReg_(0) {}
-  
+
+  // Initialize the union by associating it with a representative register
+  // number.
   void init(unsigned repReg) { repReg_ = repReg; }
 
+  // Iterate over all segments in the union of live virtual registers ordered
+  // by their starting position.
   SegmentIter begin() { return segments_.begin(); }
   SegmentIter end() { return segments_.end(); }
 
-  /// FIXME: !!!!!!!!!!! Keeps a non-const ref
+  // Add a live virtual register to this union and merge its segments.
+  // Holds a nonconst reference to the LVR for later maniplution.
   void unify(LiveInterval &lvr);
 
   // FIXME: needed by RegAllocGreedy

Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=117384&r1=117383&r2=117384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBase.h (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBase.h Tue Oct 26 13:34:01 2010
@@ -37,17 +37,29 @@
 #ifndef LLVM_CODEGEN_REGALLOCBASE
 #define LLVM_CODEGEN_REGALLOCBASE
 
-#include "LiveIntervalUnion.h"
-#include "VirtRegMap.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/ADT/OwningPtr.h"
-#include <vector>
-#include <queue>
 
 namespace llvm {
 
+template<typename T> class SmallVectorImpl;
+class TargetRegisterInfo;
 class VirtRegMap;
+class LiveIntervals;
+
+// Heuristic that determines the priority of assigning virtual to physical
+// registers. The main impact of the heuristic is expected to be compile time.
+// The default is to simply compare spill weights.
+struct LessSpillWeightPriority
+  : public std::binary_function<LiveInterval,LiveInterval, bool> {
+  bool operator()(const LiveInterval *left, const LiveInterval *right) const {
+    return left->weight < right->weight;
+  }
+};
+
+// Forward declare a priority queue of live virtual registers. If an
+// implementation needs to prioritize by anything other than spill weight, then
+// this will become an abstract base class with virtual calls to push/get.
+class LiveVirtRegQueue;
 
 /// RegAllocBase provides the register allocation driver and interface that can
 /// be extended to add interesting heuristics.
@@ -58,9 +70,6 @@
 /// standard comparator.
 class RegAllocBase {
 protected:
-  typedef SmallVector<LiveInterval*, 4> LiveVirtRegs;
-  typedef LiveVirtRegs::iterator LVRIter;
-  
   // Array of LiveIntervalUnions indexed by physical register.
   class LIUArray {
     unsigned nRegs_;
@@ -92,18 +101,20 @@
   // A RegAlloc pass should call this before allocatePhysRegs.
   void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
 
-  // The top-level driver. Specialize with the comparator that determines the
-  // priority of assigning live virtual registers. The output is a VirtRegMap
-  // that us updated with physical register assignments.
-  template<typename LICompare>
-  void allocatePhysRegs(LICompare liCompare);
+  // The top-level driver. The output is a VirtRegMap that us updated with
+  // physical register assignments.
+  //
+  // If an implementation wants to override the LiveInterval comparator, we
+  // should modify this interface to allow passing in an instance derived from
+  // LiveVirtRegQueue.
+  void allocatePhysRegs();
 
   // A RegAlloc pass should override this to provide the allocation heuristics.
-  // Each call must guarantee forward progess by returning an available
-  // PhysReg or new set of split LiveVirtRegs. It is up to the splitter to
+  // Each call must guarantee forward progess by returning an available PhysReg
+  // or new set of split live virtual registers. It is up to the splitter to
   // converge quickly toward fully spilled live ranges.
   virtual unsigned selectOrSplit(LiveInterval &lvr,
-                                 LiveVirtRegs &splitLVRs) = 0;
+                                 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
 
   // A RegAlloc pass should call this when PassManager releases its memory.
   virtual void releaseMemory();
@@ -113,69 +124,9 @@
   bool checkPhysRegInterference(LiveIntervalUnion::Query &query, unsigned preg);
   
 private:
-  template<typename PQ>
-  void seedLiveVirtRegs(PQ &lvrQ);
-};
-
-// Heuristic that determines the priority of assigning virtual to physical
-// registers. The main impact of the heuristic is expected to be compile time.
-// The default is to simply compare spill weights.
-struct LessSpillWeightPriority
-  : public std::binary_function<LiveInterval,LiveInterval, bool> {
-  bool operator()(const LiveInterval *left, const LiveInterval *right) const {
-    return left->weight < right->weight;
-  }
+  void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ);
 };
 
-// Visit all the live virtual registers. If they are already assigned to a
-// physical register, unify them with the corresponding LiveIntervalUnion,
-// otherwise push them on the priority queue for later assignment.
-template<typename PQ>
-void RegAllocBase::seedLiveVirtRegs(PQ &lvrQ) {
-  for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
-       liItr != liEnd; ++liItr) {
-    unsigned reg = liItr->first;
-    LiveInterval &li = *liItr->second;
-    if (TargetRegisterInfo::isPhysicalRegister(reg)) {
-      physReg2liu_[reg].unify(li);
-    }
-    else {
-      lvrQ.push(&li);
-    }
-  }
-}
-
-// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
-// selectOrSplit implementation.
-template<typename LICompare>
-void RegAllocBase::allocatePhysRegs(LICompare liCompare) {
-  typedef std::priority_queue
-    <LiveInterval*, std::vector<LiveInterval*>, LICompare> LiveVirtRegQueue;
-
-  LiveVirtRegQueue lvrQ(liCompare);
-  seedLiveVirtRegs(lvrQ);
-  while (!lvrQ.empty()) {
-    LiveInterval *lvr = lvrQ.top();
-    lvrQ.pop();
-    LiveVirtRegs splitLVRs;
-    unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
-    if (availablePhysReg) {
-      assert(splitLVRs.empty() && "inconsistent splitting");
-      assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
-      vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
-      physReg2liu_[availablePhysReg].unify(*lvr);
-    }
-    else {
-      for (LVRIter lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
-           lvrI != lvrEnd; ++lvrI ) {
-        assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
-               "expect split value in virtual register");
-        lvrQ.push(*lvrI);
-      }
-    }
-  }
-}
-
 } // end namespace llvm
 
 #endif // !defined(LLVM_CODEGEN_REGALLOCBASE)

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=117384&r1=117383&r2=117384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Oct 26 13:34:01 2010
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "regalloc"
+#include "LiveIntervalUnion.h"
 #include "RegAllocBase.h"
 #include "RenderMachineFunction.h"
 #include "Spiller.h"
@@ -33,6 +34,14 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
+#include "VirtRegMap.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
+
+#include <vector>
+#include <queue>
+
 using namespace llvm;
 
 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
@@ -72,7 +81,8 @@
 
   virtual void releaseMemory();
 
-  virtual unsigned selectOrSplit(LiveInterval &lvr, LiveVirtRegs &splitLVRs);
+  virtual unsigned selectOrSplit(LiveInterval &lvr,
+                                 SmallVectorImpl<LiveInterval*> &splitLVRs);
 
   /// Perform register allocation.
   virtual bool runOnMachineFunction(MachineFunction &mf);
@@ -101,7 +111,7 @@
 #endif
 INITIALIZE_PASS_END(RABasic, "basic-regalloc",
                     "Basic Register Allocator", false, false)
-#endif // INITIALIZE_PASS
+#endif // disable INITIALIZE_PASS
 
 RABasic::RABasic(): MachineFunctionPass(ID) {
   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
@@ -168,6 +178,79 @@
   physReg2liu_.clear();
 }
 
+namespace llvm {
+/// This class defines a queue of live virtual registers prioritized by spill
+/// weight. The heaviest vreg is popped first.
+///
+/// Currently, this is trivial wrapper that gives us an opaque type in the
+/// header, but we may later give it a virtual interface for register allocators
+/// to override the priority queue comparator.
+class LiveVirtRegQueue {
+  typedef std::priority_queue
+    <LiveInterval*, std::vector<LiveInterval*>, LessSpillWeightPriority> PQ;
+  PQ pq_;
+  
+public:
+  // Is the queue empty?
+  bool empty() { return pq_.empty(); }
+  
+  // Get the highest priority lvr (top + pop)
+  LiveInterval *get() {
+    LiveInterval *lvr = pq_.top();
+    pq_.pop();
+    return lvr;
+  }
+  // Add this lvr to the queue
+  void push(LiveInterval *lvr) {
+    pq_.push(lvr);
+  }
+};
+} // end namespace llvm
+
+// Visit all the live virtual registers. If they are already assigned to a
+// physical register, unify them with the corresponding LiveIntervalUnion,
+// otherwise push them on the priority queue for later assignment.
+void RegAllocBase::seedLiveVirtRegs(LiveVirtRegQueue &lvrQ) {
+  for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
+       liItr != liEnd; ++liItr) {
+    unsigned reg = liItr->first;
+    LiveInterval &li = *liItr->second;
+    if (TargetRegisterInfo::isPhysicalRegister(reg)) {
+      physReg2liu_[reg].unify(li);
+    }
+    else {
+      lvrQ.push(&li);
+    }
+  }
+}
+
+// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
+// selectOrSplit implementation.
+void RegAllocBase::allocatePhysRegs() {
+  LiveVirtRegQueue lvrQ;
+  seedLiveVirtRegs(lvrQ);
+  while (!lvrQ.empty()) {
+    LiveInterval *lvr = lvrQ.get();
+    typedef SmallVector<LiveInterval*, 4> LVRVec;
+    LVRVec splitLVRs;
+    unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
+    if (availablePhysReg) {
+      assert(splitLVRs.empty() && "inconsistent splitting");
+      assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
+      vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
+      physReg2liu_[availablePhysReg].unify(*lvr);
+    }
+    else {
+      for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
+           lvrI != lvrEnd; ++lvrI) {
+        assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
+               "expect split value in virtual register");
+        lvrQ.push(*lvrI);
+      }
+    }
+  }
+}
+
 // Check if this live virtual reg interferes with a physical register. If not,
 // then check for interference on each register that aliases with the physical
 // register.
@@ -201,7 +284,8 @@
 // available register. So, the number of interference tests in the worst case is
 // |vregs| * |machineregs|. And since the number of interference tests is
 // minimal, there is no value in caching them.
-unsigned RABasic::selectOrSplit(LiveInterval &lvr, LiveVirtRegs &splitLVRs) {
+unsigned RABasic::selectOrSplit(LiveInterval &lvr,
+                                SmallVectorImpl<LiveInterval*> &splitLVRs) {
   // Check for an available reg in this class. 
   const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg);
   for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_),
@@ -238,7 +322,7 @@
 
   spiller_.reset(createSpiller(*this, *mf_, *vrm_));
   
-  allocatePhysRegs(LessSpillWeightPriority());
+  allocatePhysRegs();
 
   // Diagnostic output before rewriting
   DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm_ << "\n");
@@ -249,6 +333,9 @@
   // Run rewriter
   std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
   rewriter->runOnMachineFunction(*mf_, *vrm_, lis_);
+
+  // The pass output is in VirtRegMap. Release all the transient data.
+  releaseMemory();
   
   return true;
 }



From atrick at apple.com  Tue Oct 26 13:37:21 2010
From: atrick at apple.com (Andrew Trick)
Date: Tue, 26 Oct 2010 11:37:21 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h
	include/llvm/CodeGen/Passes.h lib/CodeGen/CMakeLists.txt
	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
Message-ID: <9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>

On Oct 25, 2010, at 2:58 PM, Jakob Stoklund Olesen wrote:
> Please try to limit the header file dependencies.
> 
> - When passing a SmallVector by reference, use SmallVectorImpl, see Spiller.h:
> 
> virtual unsigned selectOrSplit(LiveInterval &lvr,
>                               SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
> 
> - The rest of the unnecessary headers are pulled in by the premature abstraction of making allocatePhysRegs templated on the comparator.
> 
> Please drop the template, it will clean up the code significantly when you move the implementation into the .cpp file.
> 
> When/if we need the abstraction, we can use virtual functions instead:
> 
>  struct PriQueue {
>    virtual void seed(LiveIntervals&) =0;
>    virtual LiveInterval *get() =0;
>  };
> 
> Since we will be doing significant work on each register, avoiding a virtual call is not worth the template ick.

Agreed, and done.

>> +#include "llvm/CodeGen/LiveInterval.h"
> 
> Do you need this header? It looks like SlotIndexes.h is enough.

We could do that by moving certain inline functions, like overlap() into LiveIntervalUnion.cpp. But it only ever makes sense for LiveIntervalUnion users to include LiveInterval, so is it worth scattering the methods?

>> +struct LiveSegment {
>> +  bool operator<(const LiveSegment &ls) const {
>> +    return start < ls.start || (start == ls.start && end < ls.end);
>> +  }
> 
> I know that struct LiveRange does it too, but why the lexicographical compare? We are only dealing with disjoint segments, right?
> 
> This operator will be quite performance sensitive.

I originally implemented without making the disjoint assumption unless we needed to. But in hindsight I totally agree.

>> +/// Compare a live virtual register segment to a LiveIntervalUnion segment.
>> +inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
>> +  return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
>> +}
> 
> Please add a note that LiveSegment represents a half-open interval. I am actually planning on switching to closed intervals - it is more natural for callers since the low bits of SlotIndex are symbolic.

OK

>> +class LiveIntervalUnion {
>> +public:
>> +  // default ctor avoids placement new
>> +  LiveIntervalUnion() : repReg_(0) {}
>> +  
>> +  void init(unsigned repReg) { repReg_ = repReg; }
>> +
>> +  SegmentIter begin() { return segments_.begin(); }
>> +  SegmentIter end() { return segments_.end(); }
>> +
>> +  /// FIXME: !!!!!!!!!!! Keeps a non-const ref
>> +  void unify(LiveInterval &lvr);
>> +
>> +  // FIXME: needed by RegAllocGreedy
>> +  //void extract(const LiveInterval &li);
> 
> Please add comments to public functions.
> 
> I feel your pain on storing non-const references, but just add a comment promising not to change anything.

Oops. Meant to do that.

>> Added: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117174&view=auto
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (added)
>> +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Fri Oct 22 18:09:15 2010
>> @@ -0,0 +1,167 @@
>> +// Merge a LiveInterval's segments. Guarantee no overlaps.
>> +void LiveIntervalUnion::unify(LiveInterval &lvr) {
>> +  // Add this live virtual register to the union
>> +  LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
>> +                                                &lvr, less_ptr<LiveInterval>());
>> +  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR insertion");
> 
> You should be even stricter here, and assert no overlaps.

Yes, meant to do it. Please rereview that code now.

>> +  lvrs_.insert(pos, &lvr);
>> +  // Insert each of the virtual register's live segments into the map
>> +  SegmentIter segPos = segments_.begin();
>> +  for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end();
>> +       lvrI != lvrEnd; ++lvrI ) {
>> +    LiveSegment segment(lvrI->start, lvrI->end, lvr);
>> +    segPos = segments_.insert(segPos, segment);
>> +    assert(*segPos == segment && "need equal val for equal key");
>> +  }
> 
> You could save some space by coalescing touching segments here, but that can wait until we get a 'real' data structure.

Comment added. Of course, LVR extraction has to handle it too then.

>> +typedef LiveIntervalUnion::SegmentIter SegmentIter;
>> +SegmentIter upperBound(SegmentIter segBegin,
>> +                       SegmentIter segEnd,
>> +                       const LiveRange &lvrSeg)
> 
> Please use anonymous namespaces only for types. Functions should just be declared static.

Yes. Forgot that rule.

>> Added: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=117174&view=auto
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (added)
>> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Oct 22 18:09:15 2010
>> @@ -0,0 +1,259 @@
> 
>> +class RABasic : public MachineFunctionPass, public RegAllocBase
> 
> Instead of using multiple inheritance, would it make sense for RegAllocBase to be a MachineFunctionPass? It seems that any register allocator using RegAllocBase would need the same pass initialization code and so on.

I was also tempted to make RegAlloc an abstract MachineFunctionPass. In fact I originally did that, and it was a bit easier write the code. But I want to give you some time to reconsider, because I don't think that design follows what you originally asked for: an implementation of the basic allocation pass that would never change and serve as a clean reference point and boilerplate code for extensions. It will be easier for others to understand the design and how to extend it if we keep RegAllocBase pure so that it only handles logic fundamental to the register allocation data structures and algorithms. Each regalloc subclass is a different type of pass, so it is responsible for all pass-related implementation. If RegAllocBase is derived from MachineFunctionPass then it will implement some of the pass setup and dependencies and the subclasses will each have to figure out what's left over and add any new dependencies--I think that's bad design and leads to scattered implementation.

I would not violate good design principles just to avoid multiple inheritance. I think that's a separate issue. Multiple inheritance was just an easy shortcut to avoid defining another class (e.g. RegAllocBasicImpl + RegAllocBasicPass), but I would be happy to do that if you think it's worthwhile.

>> +void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
>> +  au.setPreservesCFG();
>> +  au.addRequired<LiveIntervals>();
>> +  au.addPreserved<SlotIndexes>();
>> +  if (StrongPHIElim)
>> +    au.addRequiredID(StrongPHIEliminationID);
>> +  au.addRequiredTransitive<RegisterCoalescer>();
>> +  au.addRequired<CalculateSpillWeights>();
>> +  au.addRequired<LiveStacks>();
>> +  au.addPreserved<LiveStacks>();
>> +  au.addRequired<MachineLoopInfo>();
>> +  au.addPreserved<MachineLoopInfo>();
>> +  au.addRequired<VirtRegMap>();
>> +  au.addPreserved<VirtRegMap>();
>> +  DEBUG(au.addRequired<RenderMachineFunction>());
>> +  MachineFunctionPass::getAnalysisUsage(au);
>> +}
> 
> This would probably be the same for all register allocators using RegAllocBase.

I think the highest priority is to list all dependencies for a pass in one place for readability. I'm assuming that the common dependencies will hardly change, and if they do it's trivial to correct all passes, but that each pass (subclass) will add dependencies. This may be a rare case in which it's actually desirable to copy the common code, rather than scatter the implementation. If it's really important to factor pass setup, then the same reasoning should apply to all register allocators.

>> +void RABasic::releaseMemory() {
>> +  spiller_.reset(0);
>> +  RegAllocBase::releaseMemory();
>> +}
> 
> Since register allocation is not an analysis used by other passes, you might as well release all memory at the bottom of runOnMachineFunction().

Yes.

-Andy

From resistor at mac.com  Tue Oct 26 13:43:13 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 18:43:13 -0000
Subject: [llvm-commits] [llvm] r117385 -
	/llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.ll
Message-ID: <20101026184313.A010D2A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 13:43:13 2010
New Revision: 117385

URL: http://llvm.org/viewvc/llvm-project?rev=117385&view=rev
Log:
Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts.

Added:
    llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.ll?rev=117385&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.ll Tue Oct 26 13:43:13 2010
@@ -0,0 +1,119 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
+
+; CHECK: vrecpe_2xi32
+define <2 x i32> @vrecpe_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vrecpe.u32	d16, d16        @ encoding: [0x20,0x04,0xfb,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vrecpe_4xi32
+define <4 x i32> @vrecpe_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vrecpe.u32	q8, q8          @ encoding: [0x60,0x04,0xfb,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
+
+; CHECK: vrecpe_2xfloat
+define <2 x float> @vrecpe_2xfloat(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vrecpe.f32	d16, d16        @ encoding: [0x20,0x05,0xfb,0xf3]
+	%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
+	ret <2 x float> %tmp2
+}
+
+; CHECK: vrecpe_4xfloat
+define <4 x float> @vrecpe_4xfloat(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vrecpe.f32	q8, q8          @ encoding: [0x60,0x05,0xfb,0xf3]
+	%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
+	ret <4 x float> %tmp2
+}
+
+declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vrecps_2xfloat
+define <2 x float> @vrecps_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vrecps.f32	d16, d16, d17   @ encoding: [0xb1,0x0f,0x40,0xf2]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+; CHECK: vrecps_4xfloat
+define <4 x float> @vrecps_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vrecps.f32	q8, q8, q9      @ encoding: [0xf2,0x0f,0x40,0xf2]
+	%tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x float> %tmp3
+}
+
+declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
+
+; CHECK: vrsqrte_2xi32
+define <2 x i32> @vrsqrte_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vrsqrte.u32	d16, d16        @ encoding: [0xa0,0x04,0xfb,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vrsqrte_4xi32
+define <4 x i32> @vrsqrte_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vrsqrte.u32	q8, q8          @ encoding: [0xe0,0x04,0xfb,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
+
+; CHECK: vrsqrte_2xfloat
+define <2 x float> @vrsqrte_2xfloat(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vrsqrte.f32	d16, d16        @ encoding: [0xa0,0x05,0xfb,0xf3]
+	%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
+	ret <2 x float> %tmp2
+}
+
+; CHECK: vrsqrte_4xfloat
+define <4 x float> @vrsqrte_4xfloat(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vrsqrte.f32	q8, q8          @ encoding: [0xe0,0x05,0xfb,0xf3]
+	%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
+	ret <4 x float> %tmp2
+}
+
+declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+; CHECK: vrsqrts_2xfloat
+define <2 x float> @vrsqrts_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+	%tmp1 = load <2 x float>* %A
+	%tmp2 = load <2 x float>* %B
+; CHECK: vrsqrts.f32	d16, d16, d17   @ encoding: [0xb1,0x0f,0x60,0xf2]
+	%tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+	ret <2 x float> %tmp3
+}
+
+; CHECK: vrsqrts_4xfloat
+define <4 x float> @vrsqrts_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = load <4 x float>* %B
+; CHECK: vrsqrts.f32	q8, q8, q9      @ encoding: [0xf2,0x0f,0x60,0xf2]
+	%tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+	ret <4 x float> %tmp3
+}



From grosbach at apple.com  Tue Oct 26 14:22:23 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 26 Oct 2010 19:22:23 -0000
Subject: [llvm-commits] [llvm] r117387 -
	/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
Message-ID: <20101026192223.C03E92A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 14:22:23 2010
New Revision: 117387

URL: http://llvm.org/viewvc/llvm-project?rev=117387&view=rev
Log:
Nuke extraneous comment. It's applicable elsewhere, but not in this func.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=117387&r1=117386&r2=117387&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Oct 26 14:22:23 2010
@@ -1314,8 +1314,6 @@
   switch (AddrMode) {
   case ARMII::AddrModeT2_i8:
   case ARMII::AddrModeT2_i12:
-    // i8 supports only negative, and i12 supports only positive, so
-    // based on Offset sign, consider the appropriate instruction
     InstrOffs = MI->getOperand(Idx+1).getImm();
     Scale = 1;
     break;



From grosbach at apple.com  Tue Oct 26 14:34:41 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 26 Oct 2010 19:34:41 -0000
Subject: [llvm-commits] [llvm] r117388 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Message-ID: <20101026193441.97ACA2A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 14:34:41 2010
New Revision: 117388

URL: http://llvm.org/viewvc/llvm-project?rev=117388&view=rev
Log:
Grammar.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=117388&r1=117387&r2=117388&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Oct 26 14:34:41 2010
@@ -1362,7 +1362,7 @@
       (Op0->getOperand(2).getReg() != Op1->getOperand(2).getReg()))
       return false;
 
-  // Must sure the base address satisfies i64 ld / st alignment requirement.
+  // Make sure the base address satisfies i64 ld / st alignment requirement.
   if (!Op0->hasOneMemOperand() ||
       !(*Op0->memoperands_begin())->getValue() ||
       (*Op0->memoperands_begin())->isVolatile())



From rafael.espindola at gmail.com  Tue Oct 26 14:35:47 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 26 Oct 2010 19:35:47 -0000
Subject: [llvm-commits] [llvm] r117389 - in /llvm/trunk:
 lib/MC/MCParser/ELFAsmParser.cpp test/MC/ELF/ident.s
Message-ID: <20101026193547.7B6E42A6C12C@llvm.org>

Author: rafael
Date: Tue Oct 26 14:35:47 2010
New Revision: 117389

URL: http://llvm.org/viewvc/llvm-project?rev=117389&view=rev
Log:
Add support for .ident.

Added:
    llvm/trunk/test/MC/ELF/ident.s
Modified:
    llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp

Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=117389&r1=117388&r2=117389&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Tue Oct 26 14:35:47 2010
@@ -50,6 +50,7 @@
     AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size");
     AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous");
     AddDirectiveHandler<&ELFAsmParser::ParseDirectiveType>(".type");
+    AddDirectiveHandler<&ELFAsmParser::ParseDirectiveIdent>(".ident");
   }
 
   // FIXME: Part of this logic is duplicated in the MCELFStreamer. What is
@@ -114,6 +115,7 @@
   bool ParseDirectiveSize(StringRef, SMLoc);
   bool ParseDirectivePrevious(StringRef, SMLoc);
   bool ParseDirectiveType(StringRef, SMLoc);
+  bool ParseDirectiveIdent(StringRef, SMLoc);
 
 private:
   bool ParseSectionName(StringRef &SectionName);
@@ -345,6 +347,36 @@
   return false;
 }
 
+/// ParseDirectiveIdent
+///  ::= .ident string
+bool ELFAsmParser::ParseDirectiveIdent(StringRef, SMLoc) {
+  if (getLexer().isNot(AsmToken::String))
+    return TokError("unexpected token in '.ident' directive");
+
+  StringRef Data = getTok().getIdentifier();
+
+  Lex();
+
+  const MCSection *OldSection = getStreamer().getCurrentSection();
+  const MCSection *Comment =
+    getContext().getELFSection(".comment", MCSectionELF::SHT_PROGBITS,
+                               MCSectionELF::SHF_MERGE |
+                               MCSectionELF::SHF_STRINGS,
+                               SectionKind::getReadOnly(),
+                               false, 1);
+
+  static bool First = true;
+
+  getStreamer().SwitchSection(Comment);
+  if (First)
+    getStreamer().EmitIntValue(0, 1);
+  First = false;
+  getStreamer().EmitBytes(Data, 0);
+  getStreamer().EmitIntValue(0, 1);
+  getStreamer().SwitchSection(OldSection);
+  return false;
+}
+
 namespace llvm {
 
 MCAsmParserExtension *createELFAsmParser() {

Added: llvm/trunk/test/MC/ELF/ident.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/ident.s?rev=117389&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/ident.s (added)
+++ llvm/trunk/test/MC/ELF/ident.s Tue Oct 26 14:35:47 2010
@@ -0,0 +1,17 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck %s
+
+// CHECK:       (('sh_name', 0x00000012) # '.comment'
+// CHECK-NEXT:   ('sh_type', 0x00000001)
+// CHECK-NEXT:   ('sh_flags', 0x00000030)
+// CHECK-NEXT:   ('sh_addr', 0x00000000)
+// CHECK-NEXT:   ('sh_offset', 0x00000040)
+// CHECK-NEXT:   ('sh_size', 0x0000000d)
+// CHECK-NEXT:   ('sh_link', 0x00000000)
+// CHECK-NEXT:   ('sh_info', 0x00000000)
+// CHECK-NEXT:   ('sh_addralign', 0x00000001)
+// CHECK-NEXT:   ('sh_entsize', 0x00000001)
+// CHECK-NEXT:   ('_section_data', '00666f6f 00626172 007a6564 00')
+
+        .ident "foo"
+        .ident "bar"
+        .ident "zed"



From evan.cheng at apple.com  Tue Oct 26 15:03:08 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Oct 2010 13:03:08 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
Message-ID: <403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>

Thanks Andy. It looks like a great step. Some questions and comments below:

1. How to write a new allocator based on RegAllocBase? Is it as simple as providing a allocation queue priority function and selectOrSplit? How about routines to undo an allocation?
2. Does a allocator need to provide its own allocatePhysRegs? Should RegAllocBase provide a base implementation?
3. It would be nice if the new allocators do not have to update LiveStacks but instead compute it after the allocation is done. Do you think it's possible?
4. What's your plan for more efficient LiveSegments implementation?
5. What's next? :-)

Evan

On Oct 26, 2010, at 11:37 AM, Andrew Trick wrote:

> On Oct 25, 2010, at 2:58 PM, Jakob Stoklund Olesen wrote:
>> Please try to limit the header file dependencies.
>> 
>> - When passing a SmallVector by reference, use SmallVectorImpl, see Spiller.h:
>> 
>> virtual unsigned selectOrSplit(LiveInterval &lvr,
>>                              SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
>> 
>> - The rest of the unnecessary headers are pulled in by the premature abstraction of making allocatePhysRegs templated on the comparator.
>> 
>> Please drop the template, it will clean up the code significantly when you move the implementation into the .cpp file.
>> 
>> When/if we need the abstraction, we can use virtual functions instead:
>> 
>> struct PriQueue {
>>   virtual void seed(LiveIntervals&) =0;
>>   virtual LiveInterval *get() =0;
>> };
>> 
>> Since we will be doing significant work on each register, avoiding a virtual call is not worth the template ick.
> 
> Agreed, and done.
> 
>>> +#include "llvm/CodeGen/LiveInterval.h"
>> 
>> Do you need this header? It looks like SlotIndexes.h is enough.
> 
> We could do that by moving certain inline functions, like overlap() into LiveIntervalUnion.cpp. But it only ever makes sense for LiveIntervalUnion users to include LiveInterval, so is it worth scattering the methods?
> 
>>> +struct LiveSegment {
>>> +  bool operator<(const LiveSegment &ls) const {
>>> +    return start < ls.start || (start == ls.start && end < ls.end);
>>> +  }
>> 
>> I know that struct LiveRange does it too, but why the lexicographical compare? We are only dealing with disjoint segments, right?
>> 
>> This operator will be quite performance sensitive.
> 
> I originally implemented without making the disjoint assumption unless we needed to. But in hindsight I totally agree.
> 
>>> +/// Compare a live virtual register segment to a LiveIntervalUnion segment.
>>> +inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
>>> +  return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
>>> +}
>> 
>> Please add a note that LiveSegment represents a half-open interval. I am actually planning on switching to closed intervals - it is more natural for callers since the low bits of SlotIndex are symbolic.
> 
> OK
> 
>>> +class LiveIntervalUnion {
>>> +public:
>>> +  // default ctor avoids placement new
>>> +  LiveIntervalUnion() : repReg_(0) {}
>>> +  
>>> +  void init(unsigned repReg) { repReg_ = repReg; }
>>> +
>>> +  SegmentIter begin() { return segments_.begin(); }
>>> +  SegmentIter end() { return segments_.end(); }
>>> +
>>> +  /// FIXME: !!!!!!!!!!! Keeps a non-const ref
>>> +  void unify(LiveInterval &lvr);
>>> +
>>> +  // FIXME: needed by RegAllocGreedy
>>> +  //void extract(const LiveInterval &li);
>> 
>> Please add comments to public functions.
>> 
>> I feel your pain on storing non-const references, but just add a comment promising not to change anything.
> 
> Oops. Meant to do that.
> 
>>> Added: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117174&view=auto
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (added)
>>> +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Fri Oct 22 18:09:15 2010
>>> @@ -0,0 +1,167 @@
>>> +// Merge a LiveInterval's segments. Guarantee no overlaps.
>>> +void LiveIntervalUnion::unify(LiveInterval &lvr) {
>>> +  // Add this live virtual register to the union
>>> +  LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
>>> +                                                &lvr, less_ptr<LiveInterval>());
>>> +  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR insertion");
>> 
>> You should be even stricter here, and assert no overlaps.
> 
> Yes, meant to do it. Please rereview that code now.
> 
>>> +  lvrs_.insert(pos, &lvr);
>>> +  // Insert each of the virtual register's live segments into the map
>>> +  SegmentIter segPos = segments_.begin();
>>> +  for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end();
>>> +       lvrI != lvrEnd; ++lvrI ) {
>>> +    LiveSegment segment(lvrI->start, lvrI->end, lvr);
>>> +    segPos = segments_.insert(segPos, segment);
>>> +    assert(*segPos == segment && "need equal val for equal key");
>>> +  }
>> 
>> You could save some space by coalescing touching segments here, but that can wait until we get a 'real' data structure.
> 
> Comment added. Of course, LVR extraction has to handle it too then.
> 
>>> +typedef LiveIntervalUnion::SegmentIter SegmentIter;
>>> +SegmentIter upperBound(SegmentIter segBegin,
>>> +                       SegmentIter segEnd,
>>> +                       const LiveRange &lvrSeg)
>> 
>> Please use anonymous namespaces only for types. Functions should just be declared static.
> 
> Yes. Forgot that rule.
> 
>>> Added: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=117174&view=auto
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (added)
>>> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Oct 22 18:09:15 2010
>>> @@ -0,0 +1,259 @@
>> 
>>> +class RABasic : public MachineFunctionPass, public RegAllocBase
>> 
>> Instead of using multiple inheritance, would it make sense for RegAllocBase to be a MachineFunctionPass? It seems that any register allocator using RegAllocBase would need the same pass initialization code and so on.
> 
> I was also tempted to make RegAlloc an abstract MachineFunctionPass. In fact I originally did that, and it was a bit easier write the code. But I want to give you some time to reconsider, because I don't think that design follows what you originally asked for: an implementation of the basic allocation pass that would never change and serve as a clean reference point and boilerplate code for extensions. It will be easier for others to understand the design and how to extend it if we keep RegAllocBase pure so that it only handles logic fundamental to the register allocation data structures and algorithms. Each regalloc subclass is a different type of pass, so it is responsible for all pass-related implementation. If RegAllocBase is derived from MachineFunctionPass then it will implement some of the pass setup and dependencies and the subclasses will each have to figure out what's left over and add any new dependencies--I think that's bad design and leads to scattered implement!
> ation.
> 
> I would not violate good design principles just to avoid multiple inheritance. I think that's a separate issue. Multiple inheritance was just an easy shortcut to avoid defining another class (e.g. RegAllocBasicImpl + RegAllocBasicPass), but I would be happy to do that if you think it's worthwhile.
> 
>>> +void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
>>> +  au.setPreservesCFG();
>>> +  au.addRequired<LiveIntervals>();
>>> +  au.addPreserved<SlotIndexes>();
>>> +  if (StrongPHIElim)
>>> +    au.addRequiredID(StrongPHIEliminationID);
>>> +  au.addRequiredTransitive<RegisterCoalescer>();
>>> +  au.addRequired<CalculateSpillWeights>();
>>> +  au.addRequired<LiveStacks>();
>>> +  au.addPreserved<LiveStacks>();
>>> +  au.addRequired<MachineLoopInfo>();
>>> +  au.addPreserved<MachineLoopInfo>();
>>> +  au.addRequired<VirtRegMap>();
>>> +  au.addPreserved<VirtRegMap>();
>>> +  DEBUG(au.addRequired<RenderMachineFunction>());
>>> +  MachineFunctionPass::getAnalysisUsage(au);
>>> +}
>> 
>> This would probably be the same for all register allocators using RegAllocBase.
> 
> I think the highest priority is to list all dependencies for a pass in one place for readability. I'm assuming that the common dependencies will hardly change, and if they do it's trivial to correct all passes, but that each pass (subclass) will add dependencies. This may be a rare case in which it's actually desirable to copy the common code, rather than scatter the implementation. If it's really important to factor pass setup, then the same reasoning should apply to all register allocators.
> 
>>> +void RABasic::releaseMemory() {
>>> +  spiller_.reset(0);
>>> +  RegAllocBase::releaseMemory();
>>> +}
>> 
>> Since register allocation is not an analysis used by other passes, you might as well release all memory at the bottom of runOnMachineFunction().
> 
> Yes.
> 
> -Andy
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From stoklund at 2pi.dk  Tue Oct 26 15:19:29 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 13:19:29 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
Message-ID: <DAB3F4F4-42CB-4978-AE22-6DD29AC8F65B@2pi.dk>


On Oct 26, 2010, at 1:03 PM, Evan Cheng wrote:

> 3. It would be nice if the new allocators do not have to update LiveStacks but instead compute it after the allocation is done. Do you think it's possible?

I just moved the responsibility for updating LiveStacks into the spillers.

The implementation in the standard spiller is a bit too conservative since nobody knows when it spills and when it splits.

The implementation in InlineSpiller only updates LiveStacks after splitting and rematerialization is complete, so it should provide near minimal LiveStacks.

If the LiveStacks are minimal, it is fine to calculate them on the fly, right? Or du you have a reason for wanting to compute them after allocation?

/jakob



From stoklund at 2pi.dk  Tue Oct 26 15:21:46 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 20:21:46 -0000
Subject: [llvm-commits] [llvm] r117392 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBasicBlock.h
 include/llvm/CodeGen/MachineFunction.h lib/CodeGen/LiveIntervalAnalysis.cpp
 lib/CodeGen/MachineBasicBlock.cpp lib/CodeGen/MachineFunction.cpp
 lib/CodeGen/MachineVerifier.cpp
Message-ID: <20101026202146.9C9B42A6C12D@llvm.org>

Author: stoklund
Date: Tue Oct 26 15:21:46 2010
New Revision: 117392

URL: http://llvm.org/viewvc/llvm-project?rev=117392&view=rev
Log:
Teach MachineBasicBlock::print() to annotate instructions and blocks with
SlotIndexes when available.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=117392&r1=117391&r2=117392&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Oct 26 15:21:46 2010
@@ -23,6 +23,7 @@
 class BasicBlock;
 class MachineFunction;
 class MCSymbol;
+class SlotIndexes;
 class StringRef;
 class raw_ostream;
 
@@ -361,7 +362,7 @@
 
   // Debugging methods.
   void dump() const;
-  void print(raw_ostream &OS) const;
+  void print(raw_ostream &OS, SlotIndexes* = 0) const;
 
   /// getNumber - MachineBasicBlocks are uniquely numbered at the function
   /// level, unless they're not in a MachineFunction yet, in which case this

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=117392&r1=117391&r2=117392&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Oct 26 15:21:46 2010
@@ -244,7 +244,7 @@
   /// print - Print out the MachineFunction in a format suitable for debugging
   /// to the specified stream.
   ///
-  void print(raw_ostream &OS) const;
+  void print(raw_ostream &OS, SlotIndexes* = 0) const;
 
   /// viewCFG - This function is meant for use from the debugger.  You can just
   /// say 'call F->viewCFG()' and a ghostview window should pop up from the

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=117392&r1=117391&r2=117392&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Oct 26 15:21:46 2010
@@ -141,19 +141,7 @@
 
 void LiveIntervals::printInstrs(raw_ostream &OS) const {
   OS << "********** MACHINEINSTRS **********\n";
-
-  for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
-       mbbi != mbbe; ++mbbi) {
-    OS << "BB#" << mbbi->getNumber()
-       << ":\t\t# derived from " << mbbi->getName() << "\n";
-    for (MachineBasicBlock::iterator mii = mbbi->begin(),
-           mie = mbbi->end(); mii != mie; ++mii) {
-      if (mii->isDebugValue())
-        OS << "    \t" << *mii;
-      else
-        OS << getInstructionIndex(mii) << '\t' << *mii;
-    }
-  }
+  mf_->print(OS, indexes_);
 }
 
 void LiveIntervals::dumpInstrs() const {

Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=117392&r1=117391&r2=117392&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Oct 26 15:21:46 2010
@@ -17,6 +17,7 @@
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Target/TargetRegisterInfo.h"
@@ -176,7 +177,7 @@
     return "(null)";
 }
 
-void MachineBasicBlock::print(raw_ostream &OS) const {
+void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
   const MachineFunction *MF = getParent();
   if (!MF) {
     OS << "Can't print out MachineBasicBlock because parent MachineFunction"
@@ -186,6 +187,9 @@
 
   if (Alignment) { OS << "Alignment " << Alignment << "\n"; }
 
+  if (Indexes)
+    OS << Indexes->getMBBStartIdx(this) << '\t';
+
   OS << "BB#" << getNumber() << ": ";
 
   const char *Comma = "";
@@ -198,8 +202,9 @@
   if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
   OS << '\n';
 
-  const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();  
+  const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
   if (!livein_empty()) {
+    if (Indexes) OS << '\t';
     OS << "    Live Ins:";
     for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
       OutputReg(OS, *I, TRI);
@@ -207,19 +212,26 @@
   }
   // Print the preds of this block according to the CFG.
   if (!pred_empty()) {
+    if (Indexes) OS << '\t';
     OS << "    Predecessors according to CFG:";
     for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
       OS << " BB#" << (*PI)->getNumber();
     OS << '\n';
   }
-  
+
   for (const_iterator I = begin(); I != end(); ++I) {
+    if (Indexes) {
+      if (Indexes->hasIndex(I))
+        OS << Indexes->getInstructionIndex(I);
+      OS << '\t';
+    }
     OS << '\t';
     I->print(OS, &getParent()->getTarget());
   }
 
   // Print the successors of this block according to the CFG.
   if (!succ_empty()) {
+    if (Indexes) OS << '\t';
     OS << "    Successors according to CFG:";
     for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI)
       OS << " BB#" << (*SI)->getNumber();

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=117392&r1=117391&r2=117392&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Oct 26 15:21:46 2010
@@ -280,7 +280,7 @@
   print(dbgs());
 }
 
-void MachineFunction::print(raw_ostream &OS) const {
+void MachineFunction::print(raw_ostream &OS, SlotIndexes *Indexes) const {
   OS << "# Machine code for function " << Fn->getName() << ":\n";
 
   // Print Frame Information
@@ -329,7 +329,7 @@
   
   for (const_iterator BB = begin(), E = end(); BB != E; ++BB) {
     OS << '\n';
-    BB->print(OS);
+    BB->print(OS, Indexes);
   }
 
   OS << "\n# End machine code for function " << Fn->getName() << ".\n\n";

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117392&r1=117391&r2=117392&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Oct 26 15:21:46 2010
@@ -168,6 +168,7 @@
     // Analysis information if available
     LiveVariables *LiveVars;
     const LiveIntervals *LiveInts;
+    SlotIndexes *Indexes;
 
     void visitMachineFunctionBefore();
     void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
@@ -249,11 +250,13 @@
 
   LiveVars = NULL;
   LiveInts = NULL;
+  Indexes = NULL;
   if (PASS) {
     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
     // We don't want to verify LiveVariables if LiveIntervals is available.
     if (!LiveInts)
       LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
+    Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
   }
 
   visitMachineFunctionBefore();
@@ -291,7 +294,7 @@
   assert(MF);
   *OS << '\n';
   if (!foundErrors++)
-    MF->print(*OS);
+    MF->print(*OS, Indexes);
   *OS << "*** Bad machine code: " << msg << " ***\n"
       << "- function:    " << MF->getFunction()->getNameStr() << "\n";
 }
@@ -301,13 +304,19 @@
   report(msg, MBB->getParent());
   *OS << "- basic block: " << MBB->getName()
       << " " << (void*)MBB
-      << " (BB#" << MBB->getNumber() << ")\n";
+      << " (BB#" << MBB->getNumber() << ")";
+  if (Indexes)
+    *OS << " [" << Indexes->getMBBStartIdx(MBB)
+        << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
+  *OS << '\n';
 }
 
 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
   assert(MI);
   report(msg, MI->getParent());
   *OS << "- instruction: ";
+  if (Indexes && Indexes->hasIndex(MI))
+    *OS << Indexes->getInstructionIndex(MI) << '\t';
   MI->print(*OS, TM);
 }
 



From stoklund at 2pi.dk  Tue Oct 26 15:21:43 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 20:21:43 -0000
Subject: [llvm-commits] [llvm] r117391 -
	/llvm/trunk/lib/CodeGen/MachineVerifier.cpp
Message-ID: <20101026202143.4F8842A6C12C@llvm.org>

Author: stoklund
Date: Tue Oct 26 15:21:43 2010
New Revision: 117391

URL: http://llvm.org/viewvc/llvm-project?rev=117391&view=rev
Log:
Remmeber to print full live interval on verification error.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117391&r1=117390&r2=117391&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Oct 26 15:21:43 2010
@@ -920,14 +920,15 @@
       if (DefVNI != VNI) {
         report("Live range at def has different valno", MF);
         *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
-            << " where valno #" << DefVNI->id << " is live.\n";
+            << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
         continue;
       }
 
       const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
       if (!MBB) {
         report("Invalid definition index", MF);
-        *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+        *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+            << " in " << LI << '\n';
         continue;
       }
 
@@ -935,13 +936,15 @@
         if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
           report("PHIDef value is not defined at MBB start", MF);
           *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
-              << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
+              << ", not at the beginning of BB#" << MBB->getNumber()
+              << " in " << LI << '\n';
         }
       } else {
         // Non-PHI def.
         if (!VNI->def.isDef()) {
           report("Non-PHI def must be at a DEF slot", MF);
-          *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+          *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+              << " in " << LI << '\n';
         }
         const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
         if (!MI) {



From atrick at apple.com  Tue Oct 26 15:44:19 2010
From: atrick at apple.com (Andrew Trick)
Date: Tue, 26 Oct 2010 13:44:19 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
Message-ID: <842AE55D-93C8-49B7-AB00-A9888C9CA1DB@apple.com>

On Oct 26, 2010, at 1:03 PM, Evan Cheng wrote:

> Thanks Andy. It looks like a great step. Some questions and comments below:
> 
> 1. How to write a new allocator based on RegAllocBase? Is it as simple as providing a allocation queue priority function and selectOrSplit? How about routines to undo an allocation?

RegAllocBasic is a minimal implementation of RegAllocBase. Maybe it should be called RegAllocMinimal? I could split the .cpp file to make this more clear.

The only thing a new allocator must do is override selectOrSplit(). You can see from RABasic::selectOrSplit, that not much needs to be implemented to have a working allocator.

We do need a way to undo an allocation for functional completeness. (RABasic currently passes most but not all benchmarks.) My next step will be to implement LiveIntervalUnion::extract and call it in the uncommon case that we can't find a register for spills.

> 2. Does a allocator need to provide its own allocatePhysRegs? Should RegAllocBase provide a base implementation?

No. allocatePhysRegs never changes. Any allocator can be plugged in as along it it can solve the global allocation by adhering to two constraints:

1. It must be incremental vs. iterative (Think linear scan vs. graph coloring.) 

The underlying assumption is that we allocate or split one virtual register at a time until the problem is solved. We do not partially solve the problem, mutate the IR, throw away the solution and retry.

2. It must be able to express the desired order of allocation as a static priority.

Currently we assume spill weight can capture the priority. A new allocator can override priority by changing spill weight calculation without otherwise notifying RegAllocBase.

I imagine linear scan could be reimplemented with this framework. However silly and pointless that would be.

> 3. It would be nice if the new allocators do not have to update LiveStacks but instead compute it after the allocation is done. Do you think it's possible?

I'm not planning to update LiveStacks in regalloc because Jakob plans to add it to the spiller.

In general, an allocator implementation will have the choice of updating or recomputing it. Beyond that, I haven't thought much about the tradeoffs.

> 4. What's your plan for more efficient LiveSegments implementation?

I'll let Jakob answer that. I haven't thought of anything better than a B-btree. 

> 5. What's next? :-)

- RABasic handling trivial register reassignment
- RAGreedy implementation (adding simple reassignment and splitting heuristics)
- Evaluation of compile-time vs. code quality tradeoffs (what knobs should we give the user?)

-Andy

> On Oct 26, 2010, at 11:37 AM, Andrew Trick wrote:
> 
>> On Oct 25, 2010, at 2:58 PM, Jakob Stoklund Olesen wrote:
>>> Please try to limit the header file dependencies.
>>> 
>>> - When passing a SmallVector by reference, use SmallVectorImpl, see Spiller.h:
>>> 
>>> virtual unsigned selectOrSplit(LiveInterval &lvr,
>>>                              SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
>>> 
>>> - The rest of the unnecessary headers are pulled in by the premature abstraction of making allocatePhysRegs templated on the comparator.
>>> 
>>> Please drop the template, it will clean up the code significantly when you move the implementation into the .cpp file.
>>> 
>>> When/if we need the abstraction, we can use virtual functions instead:
>>> 
>>> struct PriQueue {
>>>   virtual void seed(LiveIntervals&) =0;
>>>   virtual LiveInterval *get() =0;
>>> };
>>> 
>>> Since we will be doing significant work on each register, avoiding a virtual call is not worth the template ick.
>> 
>> Agreed, and done.
>> 
>>>> +#include "llvm/CodeGen/LiveInterval.h"
>>> 
>>> Do you need this header? It looks like SlotIndexes.h is enough.
>> 
>> We could do that by moving certain inline functions, like overlap() into LiveIntervalUnion.cpp. But it only ever makes sense for LiveIntervalUnion users to include LiveInterval, so is it worth scattering the methods?
>> 
>>>> +struct LiveSegment {
>>>> +  bool operator<(const LiveSegment &ls) const {
>>>> +    return start < ls.start || (start == ls.start && end < ls.end);
>>>> +  }
>>> 
>>> I know that struct LiveRange does it too, but why the lexicographical compare? We are only dealing with disjoint segments, right?
>>> 
>>> This operator will be quite performance sensitive.
>> 
>> I originally implemented without making the disjoint assumption unless we needed to. But in hindsight I totally agree.
>> 
>>>> +/// Compare a live virtual register segment to a LiveIntervalUnion segment.
>>>> +inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
>>>> +  return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
>>>> +}
>>> 
>>> Please add a note that LiveSegment represents a half-open interval. I am actually planning on switching to closed intervals - it is more natural for callers since the low bits of SlotIndex are symbolic.
>> 
>> OK
>> 
>>>> +class LiveIntervalUnion {
>>>> +public:
>>>> +  // default ctor avoids placement new
>>>> +  LiveIntervalUnion() : repReg_(0) {}
>>>> +  
>>>> +  void init(unsigned repReg) { repReg_ = repReg; }
>>>> +
>>>> +  SegmentIter begin() { return segments_.begin(); }
>>>> +  SegmentIter end() { return segments_.end(); }
>>>> +
>>>> +  /// FIXME: !!!!!!!!!!! Keeps a non-const ref
>>>> +  void unify(LiveInterval &lvr);
>>>> +
>>>> +  // FIXME: needed by RegAllocGreedy
>>>> +  //void extract(const LiveInterval &li);
>>> 
>>> Please add comments to public functions.
>>> 
>>> I feel your pain on storing non-const references, but just add a comment promising not to change anything.
>> 
>> Oops. Meant to do that.
>> 
>>>> Added: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117174&view=auto
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (added)
>>>> +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Fri Oct 22 18:09:15 2010
>>>> @@ -0,0 +1,167 @@
>>>> +// Merge a LiveInterval's segments. Guarantee no overlaps.
>>>> +void LiveIntervalUnion::unify(LiveInterval &lvr) {
>>>> +  // Add this live virtual register to the union
>>>> +  LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
>>>> +                                                &lvr, less_ptr<LiveInterval>());
>>>> +  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR insertion");
>>> 
>>> You should be even stricter here, and assert no overlaps.
>> 
>> Yes, meant to do it. Please rereview that code now.
>> 
>>>> +  lvrs_.insert(pos, &lvr);
>>>> +  // Insert each of the virtual register's live segments into the map
>>>> +  SegmentIter segPos = segments_.begin();
>>>> +  for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end();
>>>> +       lvrI != lvrEnd; ++lvrI ) {
>>>> +    LiveSegment segment(lvrI->start, lvrI->end, lvr);
>>>> +    segPos = segments_.insert(segPos, segment);
>>>> +    assert(*segPos == segment && "need equal val for equal key");
>>>> +  }
>>> 
>>> You could save some space by coalescing touching segments here, but that can wait until we get a 'real' data structure.
>> 
>> Comment added. Of course, LVR extraction has to handle it too then.
>> 
>>>> +typedef LiveIntervalUnion::SegmentIter SegmentIter;
>>>> +SegmentIter upperBound(SegmentIter segBegin,
>>>> +                       SegmentIter segEnd,
>>>> +                       const LiveRange &lvrSeg)
>>> 
>>> Please use anonymous namespaces only for types. Functions should just be declared static.
>> 
>> Yes. Forgot that rule.
>> 
>>>> Added: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=117174&view=auto
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (added)
>>>> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Oct 22 18:09:15 2010
>>>> @@ -0,0 +1,259 @@
>>> 
>>>> +class RABasic : public MachineFunctionPass, public RegAllocBase
>>> 
>>> Instead of using multiple inheritance, would it make sense for RegAllocBase to be a MachineFunctionPass? It seems that any register allocator using RegAllocBase would need the same pass initialization code and so on.
>> 
>> I was also tempted to make RegAlloc an abstract MachineFunctionPass. In fact I originally did that, and it was a bit easier write the code. But I want to give you some time to reconsider, because I don't think that design follows what you originally asked for: an implementation of the basic allocation pass that would never change and serve as a clean reference point and boilerplate code for extensions. It will be easier for others to understand the design and how to extend it if we keep RegAllocBase pure so that it only handles logic fundamental to the register allocation data structures and algorithms. Each regalloc subclass is a different type of pass, so it is responsible for all pass-related implementation. If RegAllocBase is derived from MachineFunctionPass then it will implement some of the pass setup and dependencies and the subclasses will each have to figure out what's left over and add any new dependencies--I think that's bad design and leads to scattered implement!
>> ation.
>> 
>> I would not violate good design principles just to avoid multiple inheritance. I think that's a separate issue. Multiple inheritance was just an easy shortcut to avoid defining another class (e.g. RegAllocBasicImpl + RegAllocBasicPass), but I would be happy to do that if you think it's worthwhile.
>> 
>>>> +void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
>>>> +  au.setPreservesCFG();
>>>> +  au.addRequired<LiveIntervals>();
>>>> +  au.addPreserved<SlotIndexes>();
>>>> +  if (StrongPHIElim)
>>>> +    au.addRequiredID(StrongPHIEliminationID);
>>>> +  au.addRequiredTransitive<RegisterCoalescer>();
>>>> +  au.addRequired<CalculateSpillWeights>();
>>>> +  au.addRequired<LiveStacks>();
>>>> +  au.addPreserved<LiveStacks>();
>>>> +  au.addRequired<MachineLoopInfo>();
>>>> +  au.addPreserved<MachineLoopInfo>();
>>>> +  au.addRequired<VirtRegMap>();
>>>> +  au.addPreserved<VirtRegMap>();
>>>> +  DEBUG(au.addRequired<RenderMachineFunction>());
>>>> +  MachineFunctionPass::getAnalysisUsage(au);
>>>> +}
>>> 
>>> This would probably be the same for all register allocators using RegAllocBase.
>> 
>> I think the highest priority is to list all dependencies for a pass in one place for readability. I'm assuming that the common dependencies will hardly change, and if they do it's trivial to correct all passes, but that each pass (subclass) will add dependencies. This may be a rare case in which it's actually desirable to copy the common code, rather than scatter the implementation. If it's really important to factor pass setup, then the same reasoning should apply to all register allocators.
>> 
>>>> +void RABasic::releaseMemory() {
>>>> +  spiller_.reset(0);
>>>> +  RegAllocBase::releaseMemory();
>>>> +}
>>> 
>>> Since register allocation is not an analysis used by other passes, you might as well release all memory at the bottom of runOnMachineFunction().
>> 
>> Yes.
>> 
>> -Andy
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

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From resistor at mac.com  Tue Oct 26 15:56:58 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 20:56:58 -0000
Subject: [llvm-commits] [llvm] r117394 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
 test/MC/ARM/neon-shift-encoding.ll
Message-ID: <20101026205658.393102A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 15:56:57 2010
New Revision: 117394

URL: http://llvm.org/viewvc/llvm-project?rev=117394&view=rev
Log:
Provide correct NEON encodings for vshl, register and immediate forms.

Added:
    llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117394&r1=117393&r2=117394&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Oct 26 15:56:57 2010
@@ -1754,6 +1754,17 @@
   let Inst{7}    = op7;
   let Inst{6}    = op6;
   let Inst{4}    = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<5> Vm;
+  bits<6> SIMM;
+
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{3-0}   = Vm{3-0};
+  let Inst{5}     = Vm{4};
+  let Inst{21-16} = SIMM{5-0};
 }
 
 // NEON 3 vector register format.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117394&r1=117393&r2=117394&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 15:56:57 2010
@@ -1289,6 +1289,15 @@
                          (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
   let isCommutable = 0;
 }
+class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
+              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
+              ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
+  : N3V<op24, op23, op21_20, op11_8, 0, op4,
+        (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
+        OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
+        [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
+  let isCommutable = Commutable;
+}
 
 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
               Format f, InstrItinClass itin, string OpcodeStr, string Dt,
@@ -1323,6 +1332,15 @@
                                                  imm:$lane)))))]> {
   let isCommutable = 0;
 }
+class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
+              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
+              ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
+  : N3V<op24, op23, op21_20, op11_8, 1, op4,
+        (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
+        OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
+        [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
+  let isCommutable = Commutable;
+}
 
 // Multiply-Add/Sub operations: single-, double- and quad-register.
 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
@@ -1936,6 +1954,27 @@
                       OpcodeStr, !strconcat(Dt, "32"),
                       v4i32, v4i32, IntOp, Commutable>;
 }
+multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
+                     InstrItinClass itinD16, InstrItinClass itinD32,
+                     InstrItinClass itinQ16, InstrItinClass itinQ32,
+                     string OpcodeStr, string Dt,
+                     Intrinsic IntOp, bit Commutable = 0> {
+  // 64-bit vector types.
+  def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
+                      OpcodeStr, !strconcat(Dt, "16"),
+                      v4i16, v4i16, IntOp, Commutable>;
+  def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
+                      OpcodeStr, !strconcat(Dt, "32"),
+                      v2i32, v2i32, IntOp, Commutable>;
+
+  // 128-bit vector types.
+  def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
+                      OpcodeStr, !strconcat(Dt, "16"),
+                      v8i16, v8i16, IntOp, Commutable>;
+  def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
+                      OpcodeStr, !strconcat(Dt, "32"),
+                      v4i32, v4i32, IntOp, Commutable>;
+}
 
 multiclass N3VIntSL_HS<bits<4> op11_8, 
                        InstrItinClass itinD16, InstrItinClass itinD32,
@@ -1966,6 +2005,21 @@
                       OpcodeStr, !strconcat(Dt, "8"),
                       v16i8, v16i8, IntOp, Commutable>;
 }
+multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
+                      InstrItinClass itinD16, InstrItinClass itinD32,
+                      InstrItinClass itinQ16, InstrItinClass itinQ32,
+                      string OpcodeStr, string Dt,
+                      Intrinsic IntOp, bit Commutable = 0>
+  : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
+              OpcodeStr, Dt, IntOp, Commutable> {
+  def v8i8  : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
+                      OpcodeStr, !strconcat(Dt, "8"),
+                      v8i8, v8i8, IntOp, Commutable>;
+  def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
+                      OpcodeStr, !strconcat(Dt, "8"),
+                      v16i8, v16i8, IntOp, Commutable>;
+}
+
 
 // ....then also with element size of 64 bits:
 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
@@ -1982,6 +2036,20 @@
                       OpcodeStr, !strconcat(Dt, "64"),
                       v2i64, v2i64, IntOp, Commutable>;
 }
+multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
+                       InstrItinClass itinD16, InstrItinClass itinD32,
+                       InstrItinClass itinQ16, InstrItinClass itinQ32,
+                       string OpcodeStr, string Dt,
+                       Intrinsic IntOp, bit Commutable = 0>
+  : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
+               OpcodeStr, Dt, IntOp, Commutable> {
+  def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
+                      OpcodeStr, !strconcat(Dt, "64"),
+                      v1i64, v1i64, IntOp, Commutable>;
+  def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
+                      OpcodeStr, !strconcat(Dt, "64"),
+                      v2i64, v2i64, IntOp, Commutable>;
+}
 
 // Neon Narrowing 3-register vector intrinsics,
 //   source operand element sizes of 16, 32 and 64 bits:
@@ -3160,10 +3228,10 @@
 // Vector Shifts.
 
 //   VSHL     : Vector Shift
-defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
+defm VSHLs    : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
                             IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
                             "vshl", "s", int_arm_neon_vshifts, 0>;
-defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
+defm VSHLu    : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
                             IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
                             "vshl", "u", int_arm_neon_vshiftu, 0>;
 //   VSHL     : Vector Shift Left (Immediate)

Added: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117394&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Tue Oct 26 15:56:57 2010
@@ -0,0 +1,136 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+; CHECK: vshls_8xi8
+define <8 x i8> @vshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vshl.u8	d16, d17, d16           @ encoding: [0xa1,0x04,0x40,0xf3]
+	%tmp3 = shl <8 x i8> %tmp1, %tmp2
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vshls_4xi16
+define <4 x i16> @vshls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vshl.u16	d16, d17, d16   @ encoding: [0xa1,0x04,0x50,0xf3]
+	%tmp3 = shl <4 x i16> %tmp1, %tmp2
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vshls_2xi32
+define <2 x i32> @vshls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vshl.u32	d16, d17, d16   @ encoding: [0xa1,0x04,0x60,0xf3]
+	%tmp3 = shl <2 x i32> %tmp1, %tmp2
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vshls_1xi64
+define <1 x i64> @vshls_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vshl.u64	d16, d17, d16   @ encoding: [0xa1,0x04,0x70,0xf3]
+	%tmp3 = shl <1 x i64> %tmp1, %tmp2
+	ret <1 x i64> %tmp3
+}
+
+; CHECK: vshli_8xi8
+define <8 x i8> @vshli_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshl.i8	d16, d16, #7            @ encoding: [0x30,0x05,0xcf,0xf2]
+	%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vshli_4xi16
+define <4 x i16> @vshli_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshl.i16	d16, d16, #15   @ encoding: [0x30,0x05,0xdf,0xf2
+	%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vshli_2xi32
+define <2 x i32> @vshli_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshl.i32	d16, d16, #31   @ encoding: [0x30,0x05,0xff,0xf2]
+	%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vshli_1xi64
+define <1 x i64> @vshli_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vshl.i64	d16, d16, #63   @ encoding: [0xb0,0x05,0xff,0xf2]
+	%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vshls_16xi8
+define <16 x i8> @vshls_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vshl.u8	q8, q8, q9              @ encoding: [0xe0,0x04,0x42,0xf3]
+	%tmp3 = shl <16 x i8> %tmp1, %tmp2
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vshls_8xi16
+define <8 x i16> @vshls_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+	%tmp3 = shl <8 x i16> %tmp1, %tmp2
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vshls_4xi32
+define <4 x i32> @vshls_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vshl.u32	q8, q8, q9      @ encoding: [0xe0,0x04,0x62,0xf3]
+	%tmp3 = shl <4 x i32> %tmp1, %tmp2
+	ret <4 x i32> %tmp3
+}
+
+; CHECK: vshls_2xi64
+define <2 x i64> @vshls_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vshl.u64	q8, q8, q9      @ encoding: [0xe0,0x04,0x72,0xf3]
+	%tmp3 = shl <2 x i64> %tmp1, %tmp2
+	ret <2 x i64> %tmp3
+}
+
+; CHECK: vshli_16xi8
+define <16 x i8> @vshli_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vshl.i8	q8, q8, #7              @ encoding: [0x70,0x05,0xcf,0xf2]
+	%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vshli_8xi16
+define <8 x i16> @vshli_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vshl.i16	q8, q8, #15     @ encoding: [0x70,0x05,0xdf,0xf2]
+	%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshli_4xi32
+define <4 x i32> @vshli_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vshl.i32	q8, q8, #31     @ encoding: [0x70,0x05,0xff,0xf2]
+	%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshli_2xi64
+define <2 x i64> @vshli_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vshl.i64	q8, q8, #63     @ encoding: [0xf0,0x05,0xff,0xf2]
+	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
+	ret <2 x i64> %tmp2
+}



From stoklund at 2pi.dk  Tue Oct 26 16:03:56 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 14:03:56 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <842AE55D-93C8-49B7-AB00-A9888C9CA1DB@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
	<842AE55D-93C8-49B7-AB00-A9888C9CA1DB@apple.com>
Message-ID: <79B8235D-A8FA-4AF4-B291-6B2A2BEC0054@2pi.dk>


On Oct 26, 2010, at 1:44 PM, Andrew Trick wrote:

>> 4. What's your plan for more efficient LiveSegments implementation?
> 
> I'll let Jakob answer that. I haven't thought of anything better than a B-btree. 

There is a lot of fancy data structures for storing overlapping intervals, but for disjoint intervals, I don't think anything beats a B+tree for the operations we need.

So far, I am looking at using a node size of 3 cache lines which can store 8 entries in the leaf nodes and 12 branches in the inner nodes with minimal waste.

B+tree iterators support a biased lower_bound() that is very fast when only moving a little bit forward while still being logarithmic for longer searches. That is very handy for calculating overlaps as well as inserting sorted lists of intervals (LiveIntervals).

/jakob



From bob.wilson at apple.com  Tue Oct 26 16:03:58 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 26 Oct 2010 14:03:58 -0700
Subject: [llvm-commits] [llvm] r117394 - in /llvm/trunk:
	lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
	test/MC/ARM/neon-shift-encoding.ll
In-Reply-To: <20101026205658.393102A6C12C@llvm.org>
References: <20101026205658.393102A6C12C@llvm.org>
Message-ID: <A92BD927-DC42-433D-BFD2-94623C03E079@apple.com>

You can simplify this a little by removing all the Commutative parameters -- shifts are never commutative.

On Oct 26, 2010, at 1:56 PM, Owen Anderson wrote:

> Author: resistor
> Date: Tue Oct 26 15:56:57 2010
> New Revision: 117394
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=117394&view=rev
> Log:
> Provide correct NEON encodings for vshl, register and immediate forms.
> 
> Added:
>    llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117394&r1=117393&r2=117394&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Oct 26 15:56:57 2010
> @@ -1754,6 +1754,17 @@
>   let Inst{7}    = op7;
>   let Inst{6}    = op6;
>   let Inst{4}    = op4;
> +  
> +  // Instruction operands.
> +  bits<5> Vd;
> +  bits<5> Vm;
> +  bits<6> SIMM;
> +
> +  let Inst{15-12} = Vd{3-0};
> +  let Inst{22}    = Vd{4};
> +  let Inst{3-0}   = Vm{3-0};
> +  let Inst{5}     = Vm{4};
> +  let Inst{21-16} = SIMM{5-0};
> }
> 
> // NEON 3 vector register format.
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117394&r1=117393&r2=117394&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 15:56:57 2010
> @@ -1289,6 +1289,15 @@
>                          (Ty (NEONvduplane (Ty DPR_8:$src2), imm:$lane)))))]> {
>   let isCommutable = 0;
> }
> +class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> +              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
> +              ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> +  : N3V<op24, op23, op21_20, op11_8, 0, op4,
> +        (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
> +        OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
> +        [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
> +  let isCommutable = Commutable;
> +}
> 
> class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
>               Format f, InstrItinClass itin, string OpcodeStr, string Dt,
> @@ -1323,6 +1332,15 @@
>                                                  imm:$lane)))))]> {
>   let isCommutable = 0;
> }
> +class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> +              Format f, InstrItinClass itin, string OpcodeStr, string Dt,
> +              ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
> +  : N3V<op24, op23, op21_20, op11_8, 1, op4,
> +        (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
> +        OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
> +        [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
> +  let isCommutable = Commutable;
> +}
> 
> // Multiply-Add/Sub operations: single-, double- and quad-register.
> class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
> @@ -1936,6 +1954,27 @@
>                       OpcodeStr, !strconcat(Dt, "32"),
>                       v4i32, v4i32, IntOp, Commutable>;
> }
> +multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
> +                     InstrItinClass itinD16, InstrItinClass itinD32,
> +                     InstrItinClass itinQ16, InstrItinClass itinQ32,
> +                     string OpcodeStr, string Dt,
> +                     Intrinsic IntOp, bit Commutable = 0> {
> +  // 64-bit vector types.
> +  def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
> +                      OpcodeStr, !strconcat(Dt, "16"),
> +                      v4i16, v4i16, IntOp, Commutable>;
> +  def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
> +                      OpcodeStr, !strconcat(Dt, "32"),
> +                      v2i32, v2i32, IntOp, Commutable>;
> +
> +  // 128-bit vector types.
> +  def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
> +                      OpcodeStr, !strconcat(Dt, "16"),
> +                      v8i16, v8i16, IntOp, Commutable>;
> +  def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
> +                      OpcodeStr, !strconcat(Dt, "32"),
> +                      v4i32, v4i32, IntOp, Commutable>;
> +}
> 
> multiclass N3VIntSL_HS<bits<4> op11_8, 
>                        InstrItinClass itinD16, InstrItinClass itinD32,
> @@ -1966,6 +2005,21 @@
>                       OpcodeStr, !strconcat(Dt, "8"),
>                       v16i8, v16i8, IntOp, Commutable>;
> }
> +multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
> +                      InstrItinClass itinD16, InstrItinClass itinD32,
> +                      InstrItinClass itinQ16, InstrItinClass itinQ32,
> +                      string OpcodeStr, string Dt,
> +                      Intrinsic IntOp, bit Commutable = 0>
> +  : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
> +              OpcodeStr, Dt, IntOp, Commutable> {
> +  def v8i8  : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
> +                      OpcodeStr, !strconcat(Dt, "8"),
> +                      v8i8, v8i8, IntOp, Commutable>;
> +  def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
> +                      OpcodeStr, !strconcat(Dt, "8"),
> +                      v16i8, v16i8, IntOp, Commutable>;
> +}
> +
> 
> // ....then also with element size of 64 bits:
> multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
> @@ -1982,6 +2036,20 @@
>                       OpcodeStr, !strconcat(Dt, "64"),
>                       v2i64, v2i64, IntOp, Commutable>;
> }
> +multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
> +                       InstrItinClass itinD16, InstrItinClass itinD32,
> +                       InstrItinClass itinQ16, InstrItinClass itinQ32,
> +                       string OpcodeStr, string Dt,
> +                       Intrinsic IntOp, bit Commutable = 0>
> +  : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
> +               OpcodeStr, Dt, IntOp, Commutable> {
> +  def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
> +                      OpcodeStr, !strconcat(Dt, "64"),
> +                      v1i64, v1i64, IntOp, Commutable>;
> +  def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
> +                      OpcodeStr, !strconcat(Dt, "64"),
> +                      v2i64, v2i64, IntOp, Commutable>;
> +}
> 
> // Neon Narrowing 3-register vector intrinsics,
> //   source operand element sizes of 16, 32 and 64 bits:
> @@ -3160,10 +3228,10 @@
> // Vector Shifts.
> 
> //   VSHL     : Vector Shift
> -defm VSHLs    : N3VInt_QHSD<0, 0, 0b0100, 0, N3RegVShFrm,
> +defm VSHLs    : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
>                             IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
>                             "vshl", "s", int_arm_neon_vshifts, 0>;
> -defm VSHLu    : N3VInt_QHSD<1, 0, 0b0100, 0, N3RegVShFrm,
> +defm VSHLu    : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
>                             IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
>                             "vshl", "u", int_arm_neon_vshiftu, 0>;
> //   VSHL     : Vector Shift Left (Immediate)
> 
> Added: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117394&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (added)
> +++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Tue Oct 26 15:56:57 2010
> @@ -0,0 +1,136 @@
> +; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
> +
> +; CHECK: vshls_8xi8
> +define <8 x i8> @vshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
> +	%tmp1 = load <8 x i8>* %A
> +	%tmp2 = load <8 x i8>* %B
> +; CHECK: vshl.u8	d16, d17, d16           @ encoding: [0xa1,0x04,0x40,0xf3]
> +	%tmp3 = shl <8 x i8> %tmp1, %tmp2
> +	ret <8 x i8> %tmp3
> +}
> +
> +; CHECK: vshls_4xi16
> +define <4 x i16> @vshls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
> +	%tmp1 = load <4 x i16>* %A
> +	%tmp2 = load <4 x i16>* %B
> +; CHECK: vshl.u16	d16, d17, d16   @ encoding: [0xa1,0x04,0x50,0xf3]
> +	%tmp3 = shl <4 x i16> %tmp1, %tmp2
> +	ret <4 x i16> %tmp3
> +}
> +
> +; CHECK: vshls_2xi32
> +define <2 x i32> @vshls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
> +	%tmp1 = load <2 x i32>* %A
> +	%tmp2 = load <2 x i32>* %B
> +; CHECK: vshl.u32	d16, d17, d16   @ encoding: [0xa1,0x04,0x60,0xf3]
> +	%tmp3 = shl <2 x i32> %tmp1, %tmp2
> +	ret <2 x i32> %tmp3
> +}
> +
> +; CHECK: vshls_1xi64
> +define <1 x i64> @vshls_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
> +	%tmp1 = load <1 x i64>* %A
> +	%tmp2 = load <1 x i64>* %B
> +; CHECK: vshl.u64	d16, d17, d16   @ encoding: [0xa1,0x04,0x70,0xf3]
> +	%tmp3 = shl <1 x i64> %tmp1, %tmp2
> +	ret <1 x i64> %tmp3
> +}
> +
> +; CHECK: vshli_8xi8
> +define <8 x i8> @vshli_8xi8(<8 x i8>* %A) nounwind {
> +	%tmp1 = load <8 x i8>* %A
> +; CHECK: vshl.i8	d16, d16, #7            @ encoding: [0x30,0x05,0xcf,0xf2]
> +	%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
> +	ret <8 x i8> %tmp2
> +}
> +
> +; CHECK: vshli_4xi16
> +define <4 x i16> @vshli_4xi16(<4 x i16>* %A) nounwind {
> +	%tmp1 = load <4 x i16>* %A
> +; CHECK: vshl.i16	d16, d16, #15   @ encoding: [0x30,0x05,0xdf,0xf2
> +	%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
> +	ret <4 x i16> %tmp2
> +}
> +
> +; CHECK: vshli_2xi32
> +define <2 x i32> @vshli_2xi32(<2 x i32>* %A) nounwind {
> +	%tmp1 = load <2 x i32>* %A
> +; CHECK: vshl.i32	d16, d16, #31   @ encoding: [0x30,0x05,0xff,0xf2]
> +	%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
> +	ret <2 x i32> %tmp2
> +}
> +
> +; CHECK: vshli_1xi64
> +define <1 x i64> @vshli_1xi64(<1 x i64>* %A) nounwind {
> +	%tmp1 = load <1 x i64>* %A
> +; CHECK: vshl.i64	d16, d16, #63   @ encoding: [0xb0,0x05,0xff,0xf2]
> +	%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
> +	ret <1 x i64> %tmp2
> +}
> +
> +; CHECK: vshls_16xi8
> +define <16 x i8> @vshls_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
> +	%tmp1 = load <16 x i8>* %A
> +	%tmp2 = load <16 x i8>* %B
> +; CHECK: vshl.u8	q8, q8, q9              @ encoding: [0xe0,0x04,0x42,0xf3]
> +	%tmp3 = shl <16 x i8> %tmp1, %tmp2
> +	ret <16 x i8> %tmp3
> +}
> +
> +; CHECK: vshls_8xi16
> +define <8 x i16> @vshls_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
> +	%tmp1 = load <8 x i16>* %A
> +	%tmp2 = load <8 x i16>* %B
> +	%tmp3 = shl <8 x i16> %tmp1, %tmp2
> +	ret <8 x i16> %tmp3
> +}
> +
> +; CHECK: vshls_4xi32
> +define <4 x i32> @vshls_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
> +	%tmp1 = load <4 x i32>* %A
> +	%tmp2 = load <4 x i32>* %B
> +; CHECK: vshl.u32	q8, q8, q9      @ encoding: [0xe0,0x04,0x62,0xf3]
> +	%tmp3 = shl <4 x i32> %tmp1, %tmp2
> +	ret <4 x i32> %tmp3
> +}
> +
> +; CHECK: vshls_2xi64
> +define <2 x i64> @vshls_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
> +	%tmp1 = load <2 x i64>* %A
> +	%tmp2 = load <2 x i64>* %B
> +; CHECK: vshl.u64	q8, q8, q9      @ encoding: [0xe0,0x04,0x72,0xf3]
> +	%tmp3 = shl <2 x i64> %tmp1, %tmp2
> +	ret <2 x i64> %tmp3
> +}
> +
> +; CHECK: vshli_16xi8
> +define <16 x i8> @vshli_16xi8(<16 x i8>* %A) nounwind {
> +	%tmp1 = load <16 x i8>* %A
> +; CHECK: vshl.i8	q8, q8, #7              @ encoding: [0x70,0x05,0xcf,0xf2]
> +	%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
> +	ret <16 x i8> %tmp2
> +}
> +
> +; CHECK: vshli_8xi16
> +define <8 x i16> @vshli_8xi16(<8 x i16>* %A) nounwind {
> +	%tmp1 = load <8 x i16>* %A
> +; CHECK: vshl.i16	q8, q8, #15     @ encoding: [0x70,0x05,0xdf,0xf2]
> +	%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
> +	ret <8 x i16> %tmp2
> +}
> +
> +; CHECK: vshli_4xi32
> +define <4 x i32> @vshli_4xi32(<4 x i32>* %A) nounwind {
> +	%tmp1 = load <4 x i32>* %A
> +; CHECK: vshl.i32	q8, q8, #31     @ encoding: [0x70,0x05,0xff,0xf2]
> +	%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
> +	ret <4 x i32> %tmp2
> +}
> +
> +; CHECK: vshli_2xi64
> +define <2 x i64> @vshli_2xi64(<2 x i64>* %A) nounwind {
> +	%tmp1 = load <2 x i64>* %A
> +; CHECK: vshl.i64	q8, q8, #63     @ encoding: [0xf0,0x05,0xff,0xf2]
> +	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
> +	ret <2 x i64> %tmp2
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From stoklund at 2pi.dk  Tue Oct 26 16:07:01 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 14:07:01 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h
	include/llvm/CodeGen/Passes.h lib/CodeGen/CMakeLists.txt
	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <20101022230915.AB8EF2A6C12C@llvm.org>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
Message-ID: <6E81CB57-7922-4E4B-8FAD-822459F3FF18@2pi.dk>


On Oct 22, 2010, at 4:09 PM, Andrew Trick wrote:

> +void LiveIntervalUnion::unify(LiveInterval &lvr) {
> +  // Add this live virtual register to the union
> +  LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
> +                                                &lvr, less_ptr<LiveInterval>());
> +  assert(pos == lvrs_.end() || *pos != &lvr && "duplicate LVR insertion");
> +  lvrs_.insert(pos, &lvr);

Is it just me, or is this the only place lvrs_ is used?

Can it go away?




From resistor at mac.com  Tue Oct 26 16:08:42 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 21:08:42 -0000
Subject: [llvm-commits] [llvm] r117396 -
	/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
Message-ID: <20101026210842.D36382A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 16:08:42 2010
New Revision: 117396

URL: http://llvm.org/viewvc/llvm-project?rev=117396&view=rev
Log:
Tests for NEON encoding of vshr.

Modified:
    llvm/trunk/test/MC/ARM/neon-shift-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117396&r1=117395&r2=117396&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Tue Oct 26 16:08:42 2010
@@ -134,3 +134,131 @@
 	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
 	ret <2 x i64> %tmp2
 }
+
+; CHECK: vshru_8xi8
+define <8 x i8> @vshru_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshr.u8	d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf3]
+	%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vshru_4xi16
+define <4 x i16> @vshru_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshr.u16	d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf3]
+	%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vshru_2xi32
+define <2 x i32> @vshru_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshr.u32	d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf3]
+	%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vshru_1xi64
+define <1 x i64> @vshru_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vshr.u64	d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf3]
+	%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vshru_16xi8
+define <16 x i8> @vshru_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vshr.u8	q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf3]
+	%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vshru_8xi16
+define <8 x i16> @vshru_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vshr.u16	q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf3]
+	%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshru_4xi32
+define <4 x i32> @vshru_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vshr.u32	q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf3]
+	%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshru_2xi64
+define <2 x i64> @vshru_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vshr.u64	q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf3]
+	%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
+	ret <2 x i64> %tmp2
+}
+
+; CHECK: vshrs_8xi8
+define <8 x i8> @vshrs_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshr.s8	d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf2
+	%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vshrs_4xi16
+define <4 x i16> @vshrs_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshr.s16	d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf2]
+	%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vshrs_2xi32
+define <2 x i32> @vshrs_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshr.s32	d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf2]
+	%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vshrs_1xi64
+define <1 x i64> @vshrs_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vshr.s64	d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf2]
+	%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vshrs_16xi8
+define <16 x i8> @vshrs_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vshr.s8	q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf2]
+	%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vshrs_8xi16
+define <8 x i16> @vshrs_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vshr.s16	q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf2]
+	%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshrs_4xi32
+define <4 x i32> @vshrs_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vshr.s32	q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf2]
+	%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshrs_2xi64
+define <2 x i64> @vshrs_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vshr.s64	q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf2]
+	%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
+	ret <2 x i64> %tmp2
+}



From resistor at mac.com  Tue Oct 26 16:13:59 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 21:13:59 -0000
Subject: [llvm-commits] [llvm] r117398 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20101026211359.C5F862A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 16:13:59 2010
New Revision: 117398

URL: http://llvm.org/viewvc/llvm-project?rev=117398&view=rev
Log:
Simplify classes for shift instructions, which are never commutable.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117398&r1=117397&r2=117398&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 16:13:59 2010
@@ -1291,12 +1291,12 @@
 }
 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
               Format f, InstrItinClass itin, string OpcodeStr, string Dt,
-              ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
+              ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
   : N3V<op24, op23, op21_20, op11_8, 0, op4,
         (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
         OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
         [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
-  let isCommutable = Commutable;
+  let isCommutable = 0;
 }
 
 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
@@ -1334,12 +1334,12 @@
 }
 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
               Format f, InstrItinClass itin, string OpcodeStr, string Dt,
-              ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
+              ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
   : N3V<op24, op23, op21_20, op11_8, 1, op4,
         (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
         OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
         [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
-  let isCommutable = Commutable;
+  let isCommutable = 0;
 }
 
 // Multiply-Add/Sub operations: single-, double- and quad-register.
@@ -1958,22 +1958,22 @@
                      InstrItinClass itinD16, InstrItinClass itinD32,
                      InstrItinClass itinQ16, InstrItinClass itinQ32,
                      string OpcodeStr, string Dt,
-                     Intrinsic IntOp, bit Commutable = 0> {
+                     Intrinsic IntOp> {
   // 64-bit vector types.
   def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
                       OpcodeStr, !strconcat(Dt, "16"),
-                      v4i16, v4i16, IntOp, Commutable>;
+                      v4i16, v4i16, IntOp>;
   def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
                       OpcodeStr, !strconcat(Dt, "32"),
-                      v2i32, v2i32, IntOp, Commutable>;
+                      v2i32, v2i32, IntOp>;
 
   // 128-bit vector types.
   def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
                       OpcodeStr, !strconcat(Dt, "16"),
-                      v8i16, v8i16, IntOp, Commutable>;
+                      v8i16, v8i16, IntOp>;
   def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
                       OpcodeStr, !strconcat(Dt, "32"),
-                      v4i32, v4i32, IntOp, Commutable>;
+                      v4i32, v4i32, IntOp>;
 }
 
 multiclass N3VIntSL_HS<bits<4> op11_8, 
@@ -2009,15 +2009,15 @@
                       InstrItinClass itinD16, InstrItinClass itinD32,
                       InstrItinClass itinQ16, InstrItinClass itinQ32,
                       string OpcodeStr, string Dt,
-                      Intrinsic IntOp, bit Commutable = 0>
+                      Intrinsic IntOp>
   : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
-              OpcodeStr, Dt, IntOp, Commutable> {
+              OpcodeStr, Dt, IntOp> {
   def v8i8  : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
                       OpcodeStr, !strconcat(Dt, "8"),
-                      v8i8, v8i8, IntOp, Commutable>;
+                      v8i8, v8i8, IntOp>;
   def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
                       OpcodeStr, !strconcat(Dt, "8"),
-                      v16i8, v16i8, IntOp, Commutable>;
+                      v16i8, v16i8, IntOp>;
 }
 
 
@@ -2040,15 +2040,15 @@
                        InstrItinClass itinD16, InstrItinClass itinD32,
                        InstrItinClass itinQ16, InstrItinClass itinQ32,
                        string OpcodeStr, string Dt,
-                       Intrinsic IntOp, bit Commutable = 0>
+                       Intrinsic IntOp>
   : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
-               OpcodeStr, Dt, IntOp, Commutable> {
+               OpcodeStr, Dt, IntOp> {
   def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
                       OpcodeStr, !strconcat(Dt, "64"),
-                      v1i64, v1i64, IntOp, Commutable>;
+                      v1i64, v1i64, IntOp>;
   def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
                       OpcodeStr, !strconcat(Dt, "64"),
-                      v2i64, v2i64, IntOp, Commutable>;
+                      v2i64, v2i64, IntOp>;
 }
 
 // Neon Narrowing 3-register vector intrinsics,
@@ -3230,10 +3230,10 @@
 //   VSHL     : Vector Shift
 defm VSHLs    : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
                             IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
-                            "vshl", "s", int_arm_neon_vshifts, 0>;
+                            "vshl", "s", int_arm_neon_vshifts>;
 defm VSHLu    : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
                             IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
-                            "vshl", "u", int_arm_neon_vshiftu, 0>;
+                            "vshl", "u", int_arm_neon_vshiftu>;
 //   VSHL     : Vector Shift Left (Immediate)
 defm VSHLi    : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
                            N2RegVShLFrm>;



From resistor at mac.com  Tue Oct 26 16:21:47 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 21:21:47 -0000
Subject: [llvm-commits] [llvm] r117399 -
	/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
Message-ID: <20101026212147.5C17F2A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 16:21:47 2010
New Revision: 117399

URL: http://llvm.org/viewvc/llvm-project?rev=117399&view=rev
Log:
Add tests for NEON encoding of vshll.

Modified:
    llvm/trunk/test/MC/ARM/neon-shift-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117399&r1=117398&r2=117399&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Tue Oct 26 16:21:47 2010
@@ -262,3 +262,86 @@
 	%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
 	ret <2 x i64> %tmp2
 }
+
+declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vshlls_8xi8
+define <8 x i16> @vshlls_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshll.s8	q8, d16, #7     @ encoding: [0x30,0x0a,0xcf,0xf2]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshlls_4xi16
+define <4 x i32> @vshlls_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshll.s16	q8, d16, #15    @ encoding: [0x30,0x0a,0xdf,0xf2]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshlls_2xi32
+define <2 x i64> @vshlls_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshll.s32	q8, d16, #31    @ encoding: [0x30,0x0a,0xff,0xf2]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+	ret <2 x i64> %tmp2
+}
+
+declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+; CHECK: vshllu_8xi8
+define <8 x i16> @vshllu_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshll.u8	q8, d16, #7     @ encoding: [0x30,0x0a,0xcf,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshllu_4xi16
+define <4 x i32> @vshllu_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshll.u16	q8, d16, #15    @ encoding: [0x30,0x0a,0xdf,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshllu_2xi32
+define <2 x i64> @vshllu_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshll.u32	q8, d16, #31    @ encoding: [0x30,0x0a,0xff,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+	ret <2 x i64> %tmp2
+}
+
+; The following tests use the maximum shift count, so the signedness is
+; irrelevant.  Test both signed and unsigned versions.
+
+; CHECK: vshlli_8xi8
+define <8 x i16> @vshlli_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshll.i8	q8, d16, #8     @ encoding: [0x20,0x03,0xf2,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshlli_4xi16
+define <4 x i32> @vshlli_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshll.i16	q8, d16, #16    @ encoding: [0x20,0x03,0xf6,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshlli_2xi32
+define <2 x i64> @vshlli_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshll.i32	q8, d16, #32    @ encoding: [0x20,0x03,0xfa,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
+	ret <2 x i64> %tmp2
+}



From grosbach at apple.com  Tue Oct 26 16:26:47 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 26 Oct 2010 21:26:47 -0000
Subject: [llvm-commits] [llvm] r117401 -
	/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll
Message-ID: <20101026212647.8E6C92A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 16:26:47 2010
New Revision: 117401

URL: http://llvm.org/viewvc/llvm-project?rev=117401&view=rev
Log:
FileCheck'ize

Modified:
    llvm/trunk/test/CodeGen/ARM/str_pre-2.ll

Modified: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll?rev=117401&r1=117400&r2=117401&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/str_pre-2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Tue Oct 26 16:26:47 2010
@@ -1,10 +1,11 @@
-; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!}
-; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #4}
+; RUN: llc < %s -mtriple=arm-linux-gnu | FileCheck %s
 
 @b = external global i64*
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
+; CHECK: str lr, [sp, #-4]!
+; CHECK: ldr lr, [sp], #4
 	%0 = load i64** @b, align 4
 	%1 = load i64* %0, align 4
 	%2 = mul i64 %1, %a



From resistor at mac.com  Tue Oct 26 16:58:41 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 21:58:41 -0000
Subject: [llvm-commits] [llvm] r117402 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shift-encoding.ll
Message-ID: <20101026215841.C1F5F2A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 16:58:41 2010
New Revision: 117402

URL: http://llvm.org/viewvc/llvm-project?rev=117402&view=rev
Log:
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-shift-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117402&r1=117401&r2=117402&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 16:58:41 2010
@@ -3267,12 +3267,12 @@
                            NEONvshrn>;
 
 //   VRSHL    : Vector Rounding Shift
-defm VRSHLs   : N3VInt_QHSD<0, 0, 0b0101, 0, N3RegVShFrm,
+defm VRSHLs   : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
                             IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
-                            "vrshl", "s", int_arm_neon_vrshifts, 0>;
-defm VRSHLu   : N3VInt_QHSD<1, 0, 0b0101, 0, N3RegVShFrm,
+                            "vrshl", "s", int_arm_neon_vrshifts>;
+defm VRSHLu   : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
                             IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
-                            "vrshl", "u", int_arm_neon_vrshiftu, 0>;
+                            "vrshl", "u", int_arm_neon_vrshiftu>;
 //   VRSHR    : Vector Rounding Shift Right
 defm VRSHRs   : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
                            N2RegVShRFrm>;

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117402&r1=117401&r2=117402&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Tue Oct 26 16:58:41 2010
@@ -345,3 +345,351 @@
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
 	ret <2 x i64> %tmp2
 }
+
+declare <8 x i8>  @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vshrns_8xi16
+define <8 x i8> @vshrns_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vshrn.i16	d16, q8, #8     @ encoding: [0x30,0x08,0xc8,0xf2]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vshrns_4xi32
+define <4 x i16> @vshrns_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vshrn.i32	d16, q8, #16    @ encoding: [0x30,0x08,0xd0,0xf2]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vshrns_2xi64
+define <2 x i32> @vshrns_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vshrn.i64	d16, q8, #32    @ encoding: [0x30,0x08,0xe0,0xf2]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+; CHECK: vrshls_8xi8
+define <8 x i8> @vrshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vrshl.s8	d16, d16, d17   @ encoding: [0xa0,0x05,0x41,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vrshls_4xi16
+define <4 x i16> @vrshls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vrshl.s16	d16, d16, d17   @ encoding: [0xa0,0x05,0x51,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vrshls_2xi32
+define <2 x i32> @vrshls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vrshl.s32	d16, d16, d17   @ encoding: [0xa0,0x05,0x61,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vrshls_1xi64
+define <1 x i64> @vrshls_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vrshl.s64	d16, d16, d17   @ encoding: [0xa0,0x05,0x71,0xf2]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+; CHECK: vrshlu_8xi8
+define <8 x i8> @vrshlu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vrshl.u8	d16, d16, d17   @ encoding: [0xa0,0x05,0x41,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+; CHECK: vrshlu_4xi16
+define <4 x i16> @vrshlu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vrshl.u16	d16, d16, d17   @ encoding: [0xa0,0x05,0x51,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+; CHECK: vrshlu_2xi32
+define <2 x i32> @vrshlu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vrshl.u32	d16, d16, d17   @ encoding: [0xa0,0x05,0x61,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+; CHECK: vrshlu_1xi64
+define <1 x i64> @vrshlu_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vrshl.u64	d16, d16, d17   @ encoding: [0xa0,0x05,0x71,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vrshls_16xi8
+define <16 x i8> @vrshls_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vrshl.s8	q8, q8, q9      @ encoding: [0xe0,0x05,0x42,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vrshls_8xi16
+define <8 x i16> @vrshls_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vrshl.s16	q8, q8, q9      @ encoding: [0xe0,0x05,0x52,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vrshls_4xi32
+define <4 x i32> @vrshls_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vrshl.s32	q8, q8, q9      @ encoding: [0xe0,0x05,0x62,0xf2]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+; CHECK: vrshls_2xi64
+define <2 x i64> @vrshls_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vrshl.s64	q8, q8, q9      @ encoding: [0xe0,0x05,0x72,0xf2]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vrshlu_16xi8
+define <16 x i8> @vrshlu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vrshl.u8	q8, q8, q9      @ encoding: [0xe0,0x05,0x42,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+; CHECK: vrshlu_8xi16
+define <8 x i16> @vrshlu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vrshl.u16	q8, q8, q9      @ encoding: [0xe0,0x05,0x52,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+; CHECK: vrshlu_4xi32
+define <4 x i32> @vrshlu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vrshl.u32	q8, q8, q9      @ encoding: [0xe0,0x05,0x62,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+; CHECK: vrshlu_2xi64
+define <2 x i64> @vrshlu_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vrshl.u64	q8, q8, q9      @ encoding: [0xe0,0x05,0x72,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+; CHECK: vrshrs_8xi8
+define <8 x i8> @vrshrs_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vrshr.s8	d16, d16, #8    @ encoding: [0x30,0x02,0xc8,0xf2]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vrshrs_4xi16
+define <4 x i16> @vrshrs_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vrshr.s16	d16, d16, #16   @ encoding: [0x30,0x02,0xd0,0xf2]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vrshrs_2xi32
+define <2 x i32> @vrshrs_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vrshr.s32	d16, d16, #32   @ encoding: [0x30,0x02,0xe0,0xf2]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vrshrs_1xi64
+define <1 x i64> @vrshrs_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vrshr.s64	d16, d16, #64   @ encoding: [0xb0,0x02,0xc0,0xf2]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vrshru_8xi8
+define <8 x i8> @vrshru_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vrshr.u8	d16, d16, #8    @ encoding: [0x30,0x02,0xc8,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vrshru_4xi16
+define <4 x i16> @vrshru_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vrshr.u16	d16, d16, #16   @ encoding: [0x30,0x02,0xd0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vrshru_2xi32
+define <2 x i32> @vrshru_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vrshr.u32	d16, d16, #32   @ encoding: [0x30,0x02,0xe0,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vrshru_1xi64
+define <1 x i64> @vrshru_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vrshr.u64	d16, d16, #64   @ encoding: [0xb0,0x02,0xc0,0xf3]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vrshrs_16xi8
+define <16 x i8> @vrshrs_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vrshr.s8	q8, q8, #8      @ encoding: [0x70,0x02,0xc8,0xf2]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vrshrs_8xi16
+define <8 x i16> @vrshrs_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vrshr.s16	q8, q8, #16     @ encoding: [0x70,0x02,0xd0,0xf2]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vrshrs_4xi32
+define <4 x i32> @vrshrs_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vrshr.s32	q8, q8, #32     @ encoding: [0x70,0x02,0xe0,0xf2]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vrshrs_2xi64
+define <2 x i64> @vrshrs_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vrshr.s64	q8, q8, #64     @ encoding: [0xf0,0x02,0xc0,0xf2]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
+	ret <2 x i64> %tmp2
+}
+
+; CHECK: vrshru_16xi8
+define <16 x i8> @vrshru_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vrshr.u8	q8, q8, #8      @ encoding: [0x70,0x02,0xc8,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vrshru_8xi16
+define <8 x i16> @vrshru_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vrshr.u16	q8, q8, #16     @ encoding: [0x70,0x02,0xd0,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vrshru_4xi32
+define <4 x i32> @vrshru_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vrshr.u32	q8, q8, #32     @ encoding: [0x70,0x02,0xe0,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vrshru_2xi64
+define <2 x i64> @vrshru_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vrshr.u64	q8, q8, #64     @ encoding: [0xf0,0x02,0xc0,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
+	ret <2 x i64> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vrshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+; CHECK: vrshrns_8xi16
+define <8 x i8> @vrshrns_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vrshrn.i16	d16, q8, #8     @ encoding: [0x70,0x08,0xc8,0xf2]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vrshrns_4xi32
+define <4 x i16> @vrshrns_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vrshrn.i32	d16, q8, #16    @ encoding: [0x70,0x08,0xd0,0xf2]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vrshrns_2xi64
+define <2 x i32> @vrshrns_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vrshrn.i64	d16, q8, #32    @ encoding: [0x70,0x08,0xe0,0xf2]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}



From dpatel at apple.com  Tue Oct 26 17:14:52 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 26 Oct 2010 22:14:52 -0000
Subject: [llvm-commits] [llvm] r117404 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20101026221452.7B7BE2A6C12C@llvm.org>

Author: dpatel
Date: Tue Oct 26 17:14:52 2010
New Revision: 117404

URL: http://llvm.org/viewvc/llvm-project?rev=117404&view=rev
Log:
Assign source ordering to nodes created for StoreInst.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=117404&r1=117403&r2=117404&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Oct 26 17:14:52 2010
@@ -3021,8 +3021,11 @@
                              isVolatile, isNonTemporal, Alignment, TBAAInfo);
   }
 
-  DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
-                          MVT::Other, &Chains[0], NumValues));
+  SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
+                                  MVT::Other, &Chains[0], NumValues);
+  ++SDNodeOrder;
+  AssignOrderingToNode(StoreNode.getNode());
+  DAG.setRoot(StoreNode);
 }
 
 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC



From stoklund at 2pi.dk  Tue Oct 26 17:36:03 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 22:36:03 -0000
Subject: [llvm-commits] [llvm] r117405 - /llvm/trunk/lib/CodeGen/SplitKit.cpp
Message-ID: <20101026223603.225CA2A6C12C@llvm.org>

Author: stoklund
Date: Tue Oct 26 17:36:02 2010
New Revision: 117405

URL: http://llvm.org/viewvc/llvm-project?rev=117405&view=rev
Log:
Preserve PHIDef bits in cloned values during splitting.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117405&r1=117404&r2=117405&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Oct 26 17:36:02 2010
@@ -321,6 +321,10 @@
   // Create a new value.
   VNInfo *VNI = li_->getNextValue(Idx, 0, lis_.getVNInfoAllocator());
 
+  // Preserve the PHIDef bit.
+  if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
+    VNI->setIsPHIDef(true);
+
   // Use insert for lookup, so we can add missing values with a second lookup.
   std::pair<ValueMap::iterator,bool> InsP =
     valueMap_.insert(makeVV(ParentVNI, Idx == ParentVNI->def ? VNI : 0));



From stoklund at 2pi.dk  Tue Oct 26 17:36:05 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 22:36:05 -0000
Subject: [llvm-commits] [llvm] r117406 - /llvm/trunk/lib/CodeGen/SplitKit.cpp
Message-ID: <20101026223605.3661E2A6C12D@llvm.org>

Author: stoklund
Date: Tue Oct 26 17:36:05 2010
New Revision: 117406

URL: http://llvm.org/viewvc/llvm-project?rev=117406&view=rev
Log:
Call RenumberValues for all new registers created during splitting. This is
necessary to get correct hasPHIKill flags.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117406&r1=117405&r2=117406&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Oct 26 17:36:05 2010
@@ -839,7 +839,8 @@
   computeRemainder();
 
   // Get rid of unused values and set phi-kill flags.
-  dupli_.getLI()->RenumberValues(lis_);
+  for (LiveRangeEdit::iterator I = edit_.begin(), E = edit_.end(); I != E; ++I)
+    (*I)->RenumberValues(lis_);
 
   // Now check if dupli was separated into multiple connected components.
   ConnectedVNInfoEqClasses ConEQ(lis_);



From stoklund at 2pi.dk  Tue Oct 26 17:36:07 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 22:36:07 -0000
Subject: [llvm-commits] [llvm] r117407 -
	/llvm/trunk/lib/CodeGen/MachineVerifier.cpp
Message-ID: <20101026223607.50E6C2A6C12E@llvm.org>

Author: stoklund
Date: Tue Oct 26 17:36:07 2010
New Revision: 117407

URL: http://llvm.org/viewvc/llvm-project?rev=117407&view=rev
Log:
Verify that live intervals are connected. If there are multiple connected
components, each should get its own virtual register.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117407&r1=117406&r2=117407&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Oct 26 17:36:07 2010
@@ -167,7 +167,7 @@
 
     // Analysis information if available
     LiveVariables *LiveVars;
-    const LiveIntervals *LiveInts;
+    LiveIntervals *LiveInts;
     SlotIndexes *Indexes;
 
     void visitMachineFunctionBefore();
@@ -1067,6 +1067,14 @@
         ++MFI;
       }
     }
+
+    // Check the LI only has one connected component.
+    ConnectedVNInfoEqClasses ConEQ(*LiveInts);
+    unsigned NumComp = ConEQ.Classify(&LI);
+    if (NumComp > 1) {
+      report("Multiple connected components in live interval", MF);
+      *OS << NumComp << " components in " << LI << '\n';
+    }
   }
 }
 



From stoklund at 2pi.dk  Tue Oct 26 17:36:09 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 22:36:09 -0000
Subject: [llvm-commits] [llvm] r117408 - in /llvm/trunk/lib/CodeGen:
	LiveRangeEdit.h SplitKit.cpp
Message-ID: <20101026223609.6E0062A6C12F@llvm.org>

Author: stoklund
Date: Tue Oct 26 17:36:09 2010
New Revision: 117408

URL: http://llvm.org/viewvc/llvm-project?rev=117408&view=rev
Log:
After splitting, compute connected components of all new registers, not just for
the remainder register.

Example:

bb0:
  x = 1
bb1:
  use(x)
  ...
  x = 2
  jump bb1

When x is isolated in bb1, the inner part breaks into two components, x1 and x2:

bb0:
  x0 = 1
bb1:
  x1 = x0
  use(x1)
  ...
  x2 = 2
  x0 = x2
  jump bb1

Modified:
    llvm/trunk/lib/CodeGen/LiveRangeEdit.h
    llvm/trunk/lib/CodeGen/SplitKit.cpp

Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.h?rev=117408&r1=117407&r2=117408&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.h (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.h Tue Oct 26 17:36:09 2010
@@ -77,6 +77,8 @@
   typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
   iterator begin() const { return newRegs_.begin()+firstNew_; }
   iterator end() const { return newRegs_.end(); }
+  unsigned size() const { return newRegs_.size()-firstNew_; }
+  LiveInterval *get(unsigned idx) const { return newRegs_[idx-firstNew_]; }
 
   /// assignStackSlot - Ensure a stack slot is assigned to parent.
   /// @return the assigned stack slot number.

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117408&r1=117407&r2=117408&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Oct 26 17:36:09 2010
@@ -842,26 +842,27 @@
   for (LiveRangeEdit::iterator I = edit_.begin(), E = edit_.end(); I != E; ++I)
     (*I)->RenumberValues(lis_);
 
-  // Now check if dupli was separated into multiple connected components.
-  ConnectedVNInfoEqClasses ConEQ(lis_);
-  if (unsigned NumComp = ConEQ.Classify(dupli_.getLI())) {
-    DEBUG(dbgs() << "  Remainder has " << NumComp << " connected components: "
-                 << *dupli_.getLI() << '\n');
-    // Did the remainder break up? Create intervals for all the components.
-    if (NumComp > 1) {
-      SmallVector<LiveInterval*, 8> dups;
-      dups.push_back(dupli_.getLI());
-      for (unsigned i = 1; i != NumComp; ++i)
-        dups.push_back(&edit_.create(mri_, lis_, vrm_));
-      ConEQ.Distribute(&dups[0]);
-      // Rewrite uses to the new regs.
-      rewrite(dupli_.getLI()->reg);
-    }
-  }
-
   // Rewrite instructions.
   rewrite(edit_.getReg());
 
+  // Now check if any registers were separated into multiple components.
+  ConnectedVNInfoEqClasses ConEQ(lis_);
+  for (unsigned i = 0, e = edit_.size(); i != e; ++i) {
+    // Don't use iterators, they are invalidated by create() below.
+    LiveInterval *li = edit_.get(i);
+    unsigned NumComp = ConEQ.Classify(li);
+    if (NumComp <= 1)
+      continue;
+    DEBUG(dbgs() << "  " << NumComp << " components: " << *li << '\n');
+    SmallVector<LiveInterval*, 8> dups;
+    dups.push_back(li);
+    for (unsigned i = 1; i != NumComp; ++i)
+      dups.push_back(&edit_.create(mri_, lis_, vrm_));
+    ConEQ.Distribute(&dups[0]);
+    // Rewrite uses to the new regs.
+    rewrite(li->reg);
+  }
+
   // Calculate spill weight and allocation hints for new intervals.
   VirtRegAuxInfo vrai(vrm_.getMachineFunction(), lis_, sa_.loops_);
   for (LiveRangeEdit::iterator I = edit_.begin(), E = edit_.end(); I != E; ++I){



From grosbach at apple.com  Tue Oct 26 17:37:02 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 26 Oct 2010 22:37:02 -0000
Subject: [llvm-commits] [llvm] r117409 - in /llvm/trunk: lib/Target/ARM/
 lib/Target/ARM/InstPrinter/ utils/TableGen/
Message-ID: <20101026223702.C35492A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 17:37:02 2010
New Revision: 117409

URL: http://llvm.org/viewvc/llvm-project?rev=117409&view=rev
Log:
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Oct 26 17:37:02 2010
@@ -873,7 +873,7 @@
     case ARM::PICSTR:   Opcode = ARM::STR; break;
     case ARM::PICSTRB:  Opcode = ARM::STRB; break;
     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
-    case ARM::PICLDR:   Opcode = ARM::LDR; break;
+    case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
     case ARM::PICLDRB:  Opcode = ARM::LDRB; break;
     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
@@ -1220,10 +1220,9 @@
     unsigned ScratchReg = MI->getOperand(1).getReg();
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::LDR);
+      TmpInst.setOpcode(ARM::LDRi12);
       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       TmpInst.addOperand(MCOperand::CreateImm(8));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
@@ -1232,10 +1231,9 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::LDR);
+      TmpInst.setOpcode(ARM::LDRi12);
       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       TmpInst.addOperand(MCOperand::CreateImm(4));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
@@ -1244,10 +1242,9 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::LDR);
+      TmpInst.setOpcode(ARM::LDRi12);
       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       TmpInst.addOperand(MCOperand::CreateImm(0));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Oct 26 17:37:02 2010
@@ -144,7 +144,7 @@
     if (isLoad)
       MemMI = BuildMI(MF, MI->getDebugLoc(),
                       get(MemOpc), MI->getOperand(0).getReg())
-        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
+        .addReg(WBReg).addImm(0).addImm(Pred);
     else
       MemMI = BuildMI(MF, MI->getDebugLoc(),
                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
@@ -155,7 +155,7 @@
     if (isLoad)
       MemMI = BuildMI(MF, MI->getDebugLoc(),
                       get(MemOpc), MI->getOperand(0).getReg())
-        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
+        .addReg(BaseReg).addImm(0).addImm(Pred);
     else
       MemMI = BuildMI(MF, MI->getDebugLoc(),
                       get(MemOpc)).addReg(MI->getOperand(1).getReg())
@@ -823,8 +823,8 @@
 
   switch (RC->getID()) {
   case ARM::GPRRegClassID:
-    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
-                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
+                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
     break;
   case ARM::SPRRegClassID:
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
@@ -894,7 +894,7 @@
                                       int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
-  case ARM::LDR:
+  case ARM::LDRrs:
   case ARM::t2LDRs:  // FIXME: don't use t2LDRs to access frame.
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isReg() &&
@@ -905,6 +905,7 @@
       return MI->getOperand(0).getReg();
     }
     break;
+  case ARM::LDRi12:
   case ARM::t2LDRi12:
   case ARM::tRestore:
   case ARM::VLDRD:
@@ -1078,7 +1079,7 @@
   switch (Load1->getMachineOpcode()) {
   default:
     return false;
-  case ARM::LDR:
+  case ARM::LDRi12:
   case ARM::LDRB:
   case ARM::LDRD:
   case ARM::LDRH:
@@ -1097,7 +1098,7 @@
   switch (Load2->getMachineOpcode()) {
   default:
     return false;
-  case ARM::LDR:
+  case ARM::LDRi12:
   case ARM::LDRB:
   case ARM::LDRD:
   case ARM::LDRH:
@@ -1362,6 +1363,12 @@
     unsigned NumBits = 0;
     unsigned Scale = 1;
     switch (AddrMode) {
+    case ARMII::AddrMode_i12: {
+      ImmIdx = FrameRegIdx + 1;
+      InstrOffs = MI.getOperand(ImmIdx).getImm();
+      NumBits = 12;
+      break;
+    }
     case ARMII::AddrMode2: {
       ImmIdx = FrameRegIdx+2;
       InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Oct 26 17:37:02 2010
@@ -50,6 +50,7 @@
     AddrModeT2_so   = 13,
     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
     AddrModeT2_i8s4 = 15, // i8 * 4
+    AddrMode_i12    = 16,
 
     // Size* - Flags to keep track of the size of an instruction.
     SizeShift     = 5,

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Oct 26 17:37:02 2010
@@ -1201,7 +1201,7 @@
   BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
     .addReg(DestReg, getDefRegState(true), SubIdx)
     .addConstantPoolIndex(Idx)
-    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
+    .addImm(0).addImm(Pred).addReg(PredReg);
 }
 
 bool ARMBaseRegisterInfo::
@@ -1314,6 +1314,7 @@
   switch (AddrMode) {
   case ARMII::AddrModeT2_i8:
   case ARMII::AddrModeT2_i12:
+  case ARMII::AddrMode_i12:
     InstrOffs = MI->getOperand(Idx+1).getImm();
     Scale = 1;
     break;
@@ -1375,7 +1376,7 @@
   // return false for everything else.
   unsigned Opc = MI->getOpcode();
   switch (Opc) {
-  case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
+  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRB:
   case ARM::STR: case ARM::STRH: case ARM::STRB:
   case ARM::t2LDRi12: case ARM::t2LDRi8:
   case ARM::t2STRi12: case ARM::t2STRi8:
@@ -1519,6 +1520,7 @@
     NumBits = 8;
     Scale = 4;
     break;
+  case ARMII::AddrMode_i12:
   case ARMII::AddrMode2:
     NumBits = 12;
     break;
@@ -1813,7 +1815,7 @@
                         const ARMBaseInstrInfo &TII,
                         const unsigned *CSRegs) {
   return ((MI->getOpcode() == (int)ARM::VLDRD ||
-           MI->getOpcode() == (int)ARM::LDR ||
+           MI->getOpcode() == (int)ARM::LDRi12 ||
            MI->getOpcode() == (int)ARM::t2LDRi12) &&
           MI->getOperand(1).isFI() &&
           isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
@@ -1881,7 +1883,7 @@
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
 
     // Move SP to SP upon entry to the function.
-    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
+    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize());
   }
 

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Oct 26 17:37:02 2010
@@ -174,6 +174,8 @@
       const { return 0; }
     unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
                                             unsigned Op) const { return 0; }
+    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
 
     /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
     /// machine operand requires relocation, record the relocation and return

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Oct 26 17:37:02 2010
@@ -603,7 +603,7 @@
             Scale = 4;
             break;
 
-          case ARM::LDR:
+          case ARM::LDRi12:
           case ARM::LDRcp:
           case ARM::t2LDRpci:
             Bits = 12;  // +-offset_12

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Oct 26 17:37:02 2010
@@ -449,7 +449,7 @@
     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                             TII.get(ARM::LDRcp), DestReg)
                     .addConstantPoolIndex(Idx)
-                    .addReg(0).addImm(0));
+                    .addImm(0));
 
   return DestReg;
 }
@@ -750,7 +750,7 @@
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::i32:
-      Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR;
+      Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::f32:
@@ -776,14 +776,9 @@
   
   // The thumb and floating point instructions both take 2 operands, ARM takes
   // another register.
-  if (isFloat || isThumb)
-    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                            TII.get(Opc), ResultReg)
-                    .addReg(Base).addImm(Offset));
-  else
-    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                            TII.get(Opc), ResultReg)
-                    .addReg(Base).addReg(0).addImm(Offset));
+  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                          TII.get(Opc), ResultReg)
+                  .addReg(Base).addImm(Offset));
   return true;
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Oct 26 17:37:02 2010
@@ -80,6 +80,9 @@
 
   bool SelectShifterOperandReg(SDValue N, SDValue &A,
                                SDValue &B, SDValue &C);
+  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
+  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
+
   AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
                                       SDValue &Offset, SDValue &Opc);
   bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
@@ -95,6 +98,7 @@
   bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
                        SDValue &Opc) {
     SelectAddrMode2Worker(N, Base, Offset, Opc);
+//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
     // This always matches one way or another.
     return true;
   }
@@ -268,6 +272,138 @@
   return true;
 }
 
+bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
+                                          SDValue &Base,
+                                          SDValue &OffImm) {
+  // Match simple R + imm12 operands.
+
+  // Base only.
+  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
+    if (N.getOpcode() == ISD::FrameIndex) {
+      // Match frame index...
+      int FI = cast<FrameIndexSDNode>(N)->getIndex();
+      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
+      return true;
+    } else if (N.getOpcode() == ARMISD::Wrapper &&
+               !(Subtarget->useMovt() &&
+                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
+      Base = N.getOperand(0);
+    } else
+      Base = N;
+    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
+    return true;
+  }
+
+  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    int RHSC = (int)RHS->getZExtValue();
+    if (N.getOpcode() == ISD::SUB)
+      RHSC = -RHSC;
+
+    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
+      Base   = N.getOperand(0);
+      if (Base.getOpcode() == ISD::FrameIndex) {
+        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
+        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+      }
+      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
+      return true;
+    }
+  }
+
+  // Base only.
+  Base = N;
+  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
+  return true;
+}
+
+
+
+bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
+                                      SDValue &Opc) {
+  if (N.getOpcode() == ISD::MUL) {
+    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+      // X * [3,5,9] -> X + X * [2,4,8] etc.
+      int RHSC = (int)RHS->getZExtValue();
+      if (RHSC & 1) {
+        RHSC = RHSC & ~1;
+        ARM_AM::AddrOpc AddSub = ARM_AM::add;
+        if (RHSC < 0) {
+          AddSub = ARM_AM::sub;
+          RHSC = - RHSC;
+        }
+        if (isPowerOf2_32(RHSC)) {
+          unsigned ShAmt = Log2_32(RHSC);
+          Base = Offset = N.getOperand(0);
+          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
+                                                            ARM_AM::lsl),
+                                          MVT::i32);
+          return true;
+        }
+      }
+    }
+  }
+
+  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
+    return false;
+
+  // Leave simple R +/- imm12 operands for LDRi12
+  if (N.getOpcode() == ISD::ADD) {
+    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+      int RHSC = (int)RHS->getZExtValue();
+      if ((RHSC >= 0 && RHSC < 0x1000) ||
+          (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
+        return false;
+    }
+  }
+
+  // Otherwise this is R +/- [possibly shifted] R.
+  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
+  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
+  unsigned ShAmt = 0;
+
+  Base   = N.getOperand(0);
+  Offset = N.getOperand(1);
+
+  if (ShOpcVal != ARM_AM::no_shift) {
+    // Check to see if the RHS of the shift is a constant, if not, we can't fold
+    // it.
+    if (ConstantSDNode *Sh =
+           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
+      ShAmt = Sh->getZExtValue();
+      Offset = N.getOperand(1).getOperand(0);
+    } else {
+      ShOpcVal = ARM_AM::no_shift;
+    }
+  }
+
+  // Try matching (R shl C) + (R).
+  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
+    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
+    if (ShOpcVal != ARM_AM::no_shift) {
+      // Check to see if the RHS of the shift is a constant, if not, we can't
+      // fold it.
+      if (ConstantSDNode *Sh =
+          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
+        ShAmt = Sh->getZExtValue();
+        Offset = N.getOperand(0).getOperand(0);
+        Base = N.getOperand(1);
+      } else {
+        ShOpcVal = ARM_AM::no_shift;
+      }
+    }
+  }
+
+  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
+                                  MVT::i32);
+  return true;
+}
+
+
+
+
+//-----
+
 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
                                                      SDValue &Base,
                                                      SDValue &Offset,
@@ -1701,14 +1837,13 @@
       } else {
         SDValue Ops[] = {
           CPIdx,
-          CurDAG->getRegister(0, MVT::i32),
           CurDAG->getTargetConstant(0, MVT::i32),
           getAL(CurDAG),
           CurDAG->getRegister(0, MVT::i32),
           CurDAG->getEntryNode()
         };
         ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
-                                       Ops, 6);
+                                       Ops, 5);
       }
       ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
       return NULL;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Oct 26 17:37:02 2010
@@ -104,6 +104,7 @@
 def AddrModeT2_so   : AddrMode<13>;
 def AddrModeT2_pc   : AddrMode<14>;
 def AddrModeT2_i8s4 : AddrMode<15>;
+def AddrMode_i12    : AddrMode<16>;
 
 // Instruction size.
 class SizeFlagVal<bits<3> val> {
@@ -399,6 +400,38 @@
 }
 
 // loads
+
+// LDR/LDRB
+class AIldr1<bits<3> op, bit opc22, dag oops, dag iops, AddrMode am, Format f,
+             InstrItinClass itin, string opc, string asm, list<dag> pattern>
+  : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
+      "", pattern> {
+  let Inst{27-25} = op;
+  let Inst{24} = 1;  // 24 == P
+  // 23 == U
+  let Inst{22} = opc22;
+  let Inst{21} = 0;  // 21 == W
+  let Inst{20} = 1;
+}
+// LDRH/LDRSB/LDRSH/LDRD
+class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
+             Format f, InstrItinClass itin, string opc, string asm,
+             list<dag> pattern>
+  : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
+      "", pattern> {
+  let Inst{27-25} = 0b000;
+  let Inst{24} = 1;  // 24 == P
+  // 23 == U
+  let Inst{22} = opc22;
+  let Inst{21} = 0;  // 21 == W
+  let Inst{20} = opc20;
+
+  let Inst{7-4} = op;
+}
+
+
+
+
 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
              string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Oct 26 17:37:02 2010
@@ -33,7 +33,7 @@
   default: break;
   case ARM::LDR_PRE:
   case ARM::LDR_POST:
-    return ARM::LDR;
+    return ARM::LDRi12;
   case ARM::LDRH_PRE:
   case ARM::LDRH_POST:
     return ARM::LDRH;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 26 17:37:02 2010
@@ -382,22 +382,27 @@
 
 // Define ARM specific addressing modes.
 
-// addrmode2base := reg +/- imm12
+
+// addrmode_imm12 := reg +/- imm12
 //
-def addrmode2base : Operand<i32>,
-                ComplexPattern<i32, 3, "SelectAddrMode2Base", []> {
-  let PrintMethod = "printAddrMode2Operand";
-  let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
+def addrmode_imm12 : Operand<i32>,
+                     ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
+
+  string EncoderMethod = "getAddrModeImm12OpValue";
+  let PrintMethod = "printAddrModeImm12Operand";
+  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
-// addrmode2shop := reg +/- reg shop imm
+// ldst_so_reg := reg +/- reg shop imm
 //
-def addrmode2shop : Operand<i32>,
-                ComplexPattern<i32, 3, "SelectAddrMode2ShOp", []> {
+def ldst_so_reg : Operand<i32>,
+                  ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
+  // FIXME: Simplify the printer
   let PrintMethod = "printAddrMode2Operand";
   let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
 }
 
-// addrmode2 := (addrmode2base || addrmode2shop)
+// addrmode2 := reg +/- imm12
+//           := reg +/- reg shop imm
 //
 def addrmode2 : Operand<i32>,
                 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
@@ -797,6 +802,34 @@
 }
 }
 
+let canFoldAsLoad = 1, isReMaterializable = 1 in {
+multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
+           InstrItinClass iir, PatFrag opnode> {
+  // Note: We use the complex addrmode_imm12 rather than just an input
+  // GPR and a constrained immediate so that we can use this to match
+  // frame index references and avoid matching constant pool references.
+  def i12 : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
+                   AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
+                  [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
+    bits<4> Rt;
+    bits<17> addr;
+    let Inst{23}    = addr{12};     // U (add = ('U' == 1))
+    let Inst{19-16} = addr{16-13};  // Rn
+    let Inst{15-12} = Rt;
+    let Inst{11-0}  = addr{11-0};   // imm12
+  }
+  def rs : AIldr1<0b011, 0, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
+                  AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
+                 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
+    bits<4> Rt;
+    bits<17> shift;
+    let Inst{23}    = shift{12};    // U (add = ('U' == 1))
+    let Inst{19-16} = shift{16-13}; // Rn
+    let Inst{11-0}  = shift{11-0};
+  }
+}
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -1365,16 +1398,23 @@
 //
 
 // Load
-let canFoldAsLoad = 1, isReMaterializable = 1 in
-def LDR  : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad_r,
-               "ldr", "\t$dst, $addr",
-               [(set GPR:$dst, (load addrmode2:$addr))]>;
+
+
+defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
+                   UnOpFrag<(load node:$Src)>>;
 
 // Special LDR for loads from non-pc-relative constpools.
 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
     isReMaterializable = 1 in
-def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad_r,
-                 "ldr", "\t$dst, $addr", []>;
+def LDRcp : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
+                 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
+  bits<4> Rt;
+  bits<17> addr;
+  let Inst{23}    = addr{12};     // U (add = ('U' == 1))
+  let Inst{19-16} = 0b1111;
+  let Inst{15-12} = Rt;
+  let Inst{11-0}  = addr{11-0};   // imm12
+}
 
 // Loads with zero extension
 def LDRH  : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Oct 26 17:37:02 2010
@@ -130,7 +130,7 @@
 
 static int getLoadStoreMultipleOpcode(int Opcode) {
   switch (Opcode) {
-  case ARM::LDR:
+  case ARM::LDRi12:
     ++NumLDMGened;
     return ARM::LDM;
   case ARM::STR:
@@ -166,7 +166,7 @@
 }
 
 static bool isi32Load(unsigned Opc) {
-  return Opc == ARM::LDR || isT2i32Load(Opc);
+  return Opc == ARM::LDRi12 || isT2i32Load(Opc);
 }
 
 static bool isT2i32Store(unsigned Opc) {
@@ -440,7 +440,7 @@
 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default: return 0;
-  case ARM::LDR:
+  case ARM::LDRi12:
   case ARM::STR:
   case ARM::t2LDRi8:
   case ARM::t2LDRi12:
@@ -578,7 +578,7 @@
 
 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
   switch (Opc) {
-  case ARM::LDR: return ARM::LDR_PRE;
+  case ARM::LDRi12: return ARM::LDR_PRE;
   case ARM::STR: return ARM::STR_PRE;
   case ARM::VLDRS: return ARM::VLDMS_UPD;
   case ARM::VLDRD: return ARM::VLDMD_UPD;
@@ -597,7 +597,7 @@
 
 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
   switch (Opc) {
-  case ARM::LDR: return ARM::LDR_POST;
+  case ARM::LDRi12: return ARM::LDR_POST;
   case ARM::STR: return ARM::STR_POST;
   case ARM::VLDRS: return ARM::VLDMS_UPD;
   case ARM::VLDRD: return ARM::VLDMD_UPD;
@@ -629,14 +629,18 @@
   DebugLoc dl = MI->getDebugLoc();
   bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
                 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
-  bool isAM2 = (Opcode == ARM::LDR || Opcode == ARM::STR);
-  if (isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0)
+  bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STR);
+  // FIXME: This special handling of LDRi12 is hackery until all of the ARM
+  // LDR/STR insns are moved away from the addrmode2 mega-instruction to
+  // the split (LDRi12/LDRrs) style instructions.
+  if (Opcode == ARM::LDRi12 || isT2i32Load(Opcode) || isT2i32Store(Opcode))
+    if (MI->getOperand(2).getImm() != 0)
+      return false;
+  if (isAM2 && Opcode != ARM::LDRi12
+      && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0)
     return false;
   if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
     return false;
-  if (isT2i32Load(Opcode) || isT2i32Store(Opcode))
-    if (MI->getOperand(2).getImm() != 0)
-      return false;
 
   bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
   // Can't do the merge if the destination register is the same as the would-be
@@ -782,7 +786,6 @@
   int Opcode = MI->getOpcode();
   switch (Opcode) {
   default: break;
-  case ARM::LDR:
   case ARM::STR:
     return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
   case ARM::VLDRS:
@@ -791,6 +794,7 @@
   case ARM::VLDRD:
   case ARM::VSTRD:
     return MI->getOperand(1).isReg();
+  case ARM::LDRi12:
   case ARM::t2LDRi8:
   case ARM::t2LDRi12:
   case ARM::t2STRi8:
@@ -818,14 +822,15 @@
 
 static int getMemoryOpOffset(const MachineInstr *MI) {
   int Opcode = MI->getOpcode();
-  bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
+  bool isAM2 = Opcode == ARM::STR;
   bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
   unsigned NumOperands = MI->getDesc().getNumOperands();
   unsigned OffField = MI->getOperand(NumOperands-3).getImm();
 
   if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
       Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
-      Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8)
+      Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
+      Opcode == ARM::LDRi12)
     return OffField;
 
   int Offset = isAM2
@@ -944,7 +949,7 @@
       assert((!isT2 || !OffReg) &&
              "Thumb2 ldrd / strd does not encode offset register!");
       unsigned NewOpc = (isLd)
-        ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDR)
+        ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
         : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STR);
       DebugLoc dl = MBBI->getDebugLoc();
       // If this is a load and base register is killed, it may have been
@@ -1342,7 +1347,7 @@
   // FIXME: VLDRS / VSTRS -> VLDRD / VSTRD
   unsigned Scale = 1;
   unsigned Opcode = Op0->getOpcode();
-  if (Opcode == ARM::LDR)
+  if (Opcode == ARM::LDRi12)
     NewOpc = ARM::LDRD;
   else if (Opcode == ARM::STR)
     NewOpc = ARM::STRD;
@@ -1358,7 +1363,7 @@
     return false;
 
   // Make sure the offset registers match.
-  if (!isT2 &&
+  if (!isT2 && Opcode != ARM::LDRi12 &&
       (Op0->getOperand(2).getReg() != Op1->getOperand(2).getReg()))
       return false;
 
@@ -1405,7 +1410,7 @@
   if (EvenReg == OddReg)
     return false;
   BaseReg = Op0->getOperand(1).getReg();
-  if (!isT2)
+  if (!isT2 && Opcode != ARM::LDRi12)
     OffReg = Op0->getOperand(2).getReg();
   Pred = llvm::getInstrPredicate(Op0, PredReg);
   dl = Op0->getDebugLoc();
@@ -1513,8 +1518,12 @@
               .addReg(EvenReg, RegState::Define)
               .addReg(OddReg, RegState::Define)
               .addReg(BaseReg);
+            // For now, we're converting from LDRi12 to an insn that still
+            // uses addrmode2, so we need an explicit offset reg. It should
+            // always by reg0 since we're transforming LDRi12s. The old
+            // was just being paranoid in allowing for anything else.
             if (!isT2)
-              MIB.addReg(OffReg);
+              MIB.addReg(0);
             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
             ++NumLDRDFormed;
           } else {

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Oct 26 17:37:02 2010
@@ -49,6 +49,10 @@
   /// operand requires relocation, record the relocation and return zero.
   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
 
+  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
+  /// operand.
+  unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const;
+
   /// getCCOutOpValue - Return encoding of the 's' bit.
   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
     // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
@@ -171,6 +175,25 @@
   return 0;
 }
 
+/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
+/// operand.
+unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI,
+                                                   unsigned OpIdx) const {
+  // {17-13} = reg
+  // {12}    = (U)nsigned (add == '1', sub == '0')
+  // {11-0}  = imm12
+  const MCOperand &MO  = MI.getOperand(OpIdx);
+  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
+  unsigned Reg = getARMRegisterNumbering(MO.getReg());
+  int32_t Imm12 = MO1.getImm();
+  uint32_t Binary;
+  Binary = Imm12 & 0xfff;
+  if (Imm12 >= 0)
+    Binary |= (1 << 12);
+  Binary |= (Reg << 13);
+  return Binary;
+}
+
 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
                                            unsigned OpIdx) const {
   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Oct 26 17:37:02 2010
@@ -605,6 +605,11 @@
   const MCOperand &MO1 = MI->getOperand(OpNum);
   const MCOperand &MO2 = MI->getOperand(OpNum+1);
 
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
+    printOperand(MI, OpNum, O);
+    return;
+  }
+
   O << "[" << getRegisterName(MO1.getReg());
 
   unsigned OffImm = MO2.getImm();

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=117409&r1=117408&r2=117409&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Oct 26 17:37:02 2010
@@ -592,6 +592,8 @@
   MISC("so_imm2part", "kOperandTypeARMSoImm2Part");               // I
   MISC("pred", "kOperandTypeARMPredicate");                       // I, R
   MISC("it_pred", "kOperandTypeARMPredicate");                    // I
+  MISC("addrmode_imm12", "kOperandTypeAddrModeImm12");            // R, I
+  MISC("ldst_so_reg", "kOperandTypeLdStSOReg");                   // R, R, I
   MISC("addrmode2", "kOperandTypeARMAddrMode2");                  // R, R, I
   MISC("am2offset", "kOperandTypeARMAddrMode2Offset");            // R, I
   MISC("addrmode3", "kOperandTypeARMAddrMode3");                  // R, R, I
@@ -807,6 +809,8 @@
   operandTypes.addEntry("kOperandTypeARMRotImm");
   operandTypes.addEntry("kOperandTypeARMSoImm2Part");
   operandTypes.addEntry("kOperandTypeARMPredicate");
+  operandTypes.addEntry("kOperandTypeAddrModeImm12");
+  operandTypes.addEntry("kOperandTypeLdStSOReg");
   operandTypes.addEntry("kOperandTypeARMAddrMode2");
   operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
   operandTypes.addEntry("kOperandTypeARMAddrMode3");



From evan.cheng at apple.com  Tue Oct 26 17:46:32 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Oct 2010 15:46:32 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <DAB3F4F4-42CB-4978-AE22-6DD29AC8F65B@2pi.dk>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
	<DAB3F4F4-42CB-4978-AE22-6DD29AC8F65B@2pi.dk>
Message-ID: <F79E0D5E-2C2D-47E9-8F42-9C47CF6330E3@apple.com>


On Oct 26, 2010, at 1:19 PM, Jakob Stoklund Olesen wrote:

> 
> On Oct 26, 2010, at 1:03 PM, Evan Cheng wrote:
> 
>> 3. It would be nice if the new allocators do not have to update LiveStacks but instead compute it after the allocation is done. Do you think it's possible?
> 
> I just moved the responsibility for updating LiveStacks into the spillers.
> 
> The implementation in the standard spiller is a bit too conservative since nobody knows when it spills and when it splits.
> 
> The implementation in InlineSpiller only updates LiveStacks after splitting and rematerialization is complete, so it should provide near minimal LiveStacks.
> 
> If the LiveStacks are minimal, it is fine to calculate them on the fly, right? Or du you have a reason for wanting to compute them after allocation?

No particular reason. LiveStacks is a bit of a hack, I just think we should work towards removing the hack. Not having the allocator updating it is a good start.

Evan

> 
> /jakob
> 

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From resistor at mac.com  Tue Oct 26 17:50:47 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 26 Oct 2010 22:50:47 -0000
Subject: [llvm-commits] [llvm] r117411 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-satshift-encoding.ll
Message-ID: <20101026225047.206732A6C12C@llvm.org>

Author: resistor
Date: Tue Oct 26 17:50:46 2010
New Revision: 117411

URL: http://llvm.org/viewvc/llvm-project?rev=117411&view=rev
Log:
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.

Added:
    llvm/trunk/test/MC/ARM/neon-satshift-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117411&r1=117410&r2=117411&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 26 17:50:46 2010
@@ -3284,12 +3284,12 @@
                            NEONvrshrn>;
 
 //   VQSHL    : Vector Saturating Shift
-defm VQSHLs   : N3VInt_QHSD<0, 0, 0b0100, 1, N3RegVShFrm,
+defm VQSHLs   : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
                             IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
-                            "vqshl", "s", int_arm_neon_vqshifts, 0>;
-defm VQSHLu   : N3VInt_QHSD<1, 0, 0b0100, 1, N3RegVShFrm,
+                            "vqshl", "s", int_arm_neon_vqshifts>;
+defm VQSHLu   : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
                             IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
-                            "vqshl", "u", int_arm_neon_vqshiftu, 0>;
+                            "vqshl", "u", int_arm_neon_vqshiftu>;
 //   VQSHL    : Vector Saturating Shift Left (Immediate)
 defm VQSHLsi  : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
                            N2RegVShLFrm>;
@@ -3310,12 +3310,12 @@
                            NEONvqshrnsu>;
 
 //   VQRSHL   : Vector Saturating Rounding Shift
-defm VQRSHLs  : N3VInt_QHSD<0, 0, 0b0101, 1, N3RegVShFrm,
+defm VQRSHLs  : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
                             IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
-                            "vqrshl", "s", int_arm_neon_vqrshifts, 0>;
-defm VQRSHLu  : N3VInt_QHSD<1, 0, 0b0101, 1, N3RegVShFrm,
+                            "vqrshl", "s", int_arm_neon_vqrshifts>;
+defm VQRSHLu  : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
                             IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
-                            "vqrshl", "u", int_arm_neon_vqrshiftu, 0>;
+                            "vqrshl", "u", int_arm_neon_vqrshiftu>;
 
 //   VQRSHRN  : Vector Saturating Rounding Shift Right and Narrow
 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",

Added: llvm/trunk/test/MC/ARM/neon-satshift-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-satshift-encoding.ll?rev=117411&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-satshift-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-satshift-encoding.ll Tue Oct 26 17:50:46 2010
@@ -0,0 +1,623 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vqshl.s8	d16, d16, d17   @ encoding: [0xb0,0x04,0x41,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vqshl.s16	d16, d16, d17   @ encoding: [0xb0,0x04,0x51,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vqshl.s32	d16, d16, d17   @ encoding: [0xb0,0x04,0x61,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vqshl.s64	d16, d16, d17   @ encoding: [0xb0,0x04,0x71,0xf2]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vqshl.u8	d16, d16, d17   @ encoding: [0xb0,0x04,0x41,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vqshl.u32	d16, d16, d17   @ encoding: [0xb0,0x04,0x61,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vqshl.u64	d16, d16, d17   @ encoding: [0xb0,0x04,0x71,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vqshl.s8	q8, q8, q9      @ encoding: [0xf0,0x04,0x42,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vqshl.s16	q8, q8, q9      @ encoding: [0xf0,0x04,0x52,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vqshl.s32	q8, q8, q9      @ encoding: [0xf0,0x04,0x62,0xf2]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vqshl.u8	q8, q8, q9      @ encoding: [0xf0,0x04,0x42,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vqshl.u16	q8, q8, q9      @ encoding: [0xf0,0x04,0x52,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vqshl.u32	q8, q8, q9      @ encoding: [0xf0,0x04,0x62,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vqshl.u64	q8, q8, q9      @ encoding: [0xf0,0x04,0x72,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vqshl.s8	d16, d16, #7    @ encoding: [0x30,0x07,0xcf,0xf2]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vqshl.s16	d16, d16, #15   @ encoding: [0x30,0x07,0xdf,0xf2]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vqshl.s32	d16, d16, #31   @ encoding: [0x30,0x07,0xff,0xf2]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+	ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vqshl.s64	d16, d16, #63   @ encoding: [0xb0,0x07,0xff,0xf2]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+	ret <1 x i64> %tmp2
+}
+
+define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vqshl.u8	d16, d16, #7    @ encoding: [0x30,0x07,0xcf,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vqshl.u16	d16, d16, #15   @ encoding: [0x30,0x07,0xdf,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vqshl.u32	d16, d16, #31   @ encoding: [0x30,0x07,0xff,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+	ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vqshl.u64	d16, d16, #63   @ encoding: [0xb0,0x07,0xff,0xf3]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+	ret <1 x i64> %tmp2
+}
+
+define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vqshlu.s8	d16, d16, #7    @ encoding: [0x30,0x06,0xcf,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vqshlu.s16	d16, d16, #15   @ encoding: [0x30,0x06,0xdf,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vqshlu.s32	d16, d16, #31   @ encoding: [0x30,0x06,0xff,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+	ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vqshlu.s64	d16, d16, #63   @ encoding: [0xb0,0x06,0xff,0xf3]
+	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+	ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vqshl.s8	q8, q8, #7      @ encoding: [0x70,0x07,0xcf,0xf2]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqshl.s16	q8, q8, #15     @ encoding: [0x70,0x07,0xdf,0xf2]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqshl.s32	q8, q8, #31     @ encoding: [0x70,0x07,0xff,0xf2]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+	ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqshl.s64	q8, q8, #63     @ encoding: [0xf0,0x07,0xff,0xf2]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+	ret <2 x i64> %tmp2
+}
+
+define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vqshl.u8	q8, q8, #7      @ encoding: [0x70,0x07,0xcf,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqshl.u16	q8, q8, #15     @ encoding: [0x70,0x07,0xdf,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqshl.u32	q8, q8, #31     @ encoding: [0x70,0x07,0xff,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+	ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqshl.u64	q8, q8, #63     @ encoding: [0xf0,0x07,0xff,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+	ret <2 x i64> %tmp2
+}
+
+define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vqshlu.s8	q8, q8, #7      @ encoding: [0x70,0x06,0xcf,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqshlu.s16	q8, q8, #15     @ encoding: [0x70,0x06,0xdf,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqshlu.s32	q8, q8, #31     @ encoding: [0x70,0x06,0xff,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+	ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqshlu.s64	q8, q8, #63     @ encoding: [0xf0,0x06,0xff,0xf3]
+	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+	ret <2 x i64> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK:   vqrshl.s8	d16, d16, d17   @ encoding: [0xb0,0x05,0x41,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vqrshl.s16	d16, d16, d17   @ encoding: [0xb0,0x05,0x51,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vqrshl.s32	d16, d16, d17   @ encoding: [0xb0,0x05,0x61,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vqrshl.s64	d16, d16, d17   @ encoding: [0xb0,0x05,0x71,0xf2]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vqrshl.u8	d16, d16, d17   @ encoding: [0xb0,0x05,0x41,0xf3
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+	ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vqrshl.u16	d16, d16, d17   @ encoding: [0xb0,0x05,0x51,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+	ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vqrshl.u32	d16, d16, d17   @ encoding: [0xb0,0x05,0x61,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+	ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vqrshl.u64	d16, d16, d17   @ encoding: [0xb0,0x05,0x71,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+	ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vqrshl.s8	q8, q8, q9      @ encoding: [0xf0,0x05,0x42,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vqrshl.s16	q8, q8, q9      @ encoding: [0xf0,0x05,0x52,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vqrshl.s32	q8, q8, q9      @ encoding: [0xf0,0x05,0x62,0xf2]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vqrshl.s64	q8, q8, q9      @ encoding: [0xf0,0x05,0x72,0xf2]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vqrshl.u8	q8, q8, q9      @ encoding: [0xf0,0x05,0x42,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vqrshl.u16	q8, q8, q9      @ encoding: [0xf0,0x05,0x52,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+	ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vqrshl.u32	q8, q8, q9      @ encoding: [0xf0,0x05,0x62,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vqrshl.u64	q8, q8, q9      @ encoding: [0xf0,0x05,0x72,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+	ret <2 x i64> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqshrn.s16	d16, q8, #8     @ encoding: [0x30,0x09,0xc8,0xf2]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqshrn.s32	d16, q8, #16    @ encoding: [0x30,0x09,0xd0,0xf2]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqshrn.s64	d16, q8, #32    @ encoding: [0x30,0x09,0xe0,0xf2]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqshrn.u16	d16, q8, #8     @ encoding: [0x30,0x09,0xc8,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqshrn.u32	d16, q8, #16    @ encoding: [0x30,0x09,0xd0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqshrn.u64	d16, q8, #32    @ encoding: [0x30,0x09,0xe0,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqshrun.s16	d16, q8, #8     @ encoding: [0x30,0x08,0xc8,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqshrun.s32	d16, q8, #16    @ encoding: [0x30,0x08,0xd0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqshrun.s64	d16, q8, #32    @ encoding: [0x30,0x08,0xe0,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqrshrn.s16	d16, q8, #8     @ encoding: [0x70,0x09,0xc8,0xf2]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqrshrn.s32	d16, q8, #16    @ encoding: [0x70,0x09,0xd0,0xf2]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqrshrn.s64	d16, q8, #32    @ encoding: [0x70,0x09,0xe0,0xf2]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqrshrn.u16	d16, q8, #8     @ encoding: [0x70,0x09,0xc8,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqrshrn.u32	d16, q8, #16    @ encoding: [0x70,0x09,0xd0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqrshrn.u64	d16, q8, #32    @ encoding: [0x70,0x09,0xe0,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqrshrun.s16	d16, q8, #8     @ encoding: [0x70,0x08,0xc8,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqrshrun.s32	d16, q8, #16    @ encoding: [0x70,0x08,0xd0,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqrshrun.s64	d16, q8, #32    @ encoding: [0x70,0x08,0xe0,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+	ret <2 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone



From stoklund at 2pi.dk  Tue Oct 26 17:59:40 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 15:59:40 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <F79E0D5E-2C2D-47E9-8F42-9C47CF6330E3@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
	<DAB3F4F4-42CB-4978-AE22-6DD29AC8F65B@2pi.dk>
	<F79E0D5E-2C2D-47E9-8F42-9C47CF6330E3@apple.com>
Message-ID: <3A50637E-8C3D-47AD-AD5B-41128CFA01DD@2pi.dk>


On Oct 26, 2010, at 3:46 PM, Evan Cheng wrote:

> 
> On Oct 26, 2010, at 1:19 PM, Jakob Stoklund Olesen wrote:

>> If the LiveStacks are minimal, it is fine to calculate them on the fly, right? Or du you have a reason for wanting to compute them after allocation?
> 
> No particular reason. LiveStacks is a bit of a hack, I just think we should work towards removing the hack. Not having the allocator updating it is a good start.

What do you have in mind? It seems like an OK design to me.

Obviously, StackSlotColoring needs to stop doing register allocation (!!), and it could probably share more code with the register allocator.

/jakob



From atrick at apple.com  Tue Oct 26 17:58:24 2010
From: atrick at apple.com (Andrew Trick)
Date: Tue, 26 Oct 2010 22:58:24 -0000
Subject: [llvm-commits] [llvm] r117412 - in /llvm/trunk/lib/CodeGen:
 LiveIntervalUnion.cpp LiveIntervalUnion.h
Message-ID: <20101026225824.E035B2A6C12C@llvm.org>

Author: atrick
Date: Tue Oct 26 17:58:24 2010
New Revision: 117412

URL: http://llvm.org/viewvc/llvm-project?rev=117412&view=rev
Log:
Remove the vector of live vregs. I thought we would need to track
them, but hopefully we won't. And this is not the right data structure
to do it anyway.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.h

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=117412&r1=117411&r2=117412&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Oct 26 17:58:24 2010
@@ -25,11 +25,6 @@
 // Consider coalescing adjacent segments to save space, even though it makes
 // extraction more complicated.
 void LiveIntervalUnion::unify(LiveInterval &lvr) {
-  // Add this live virtual register to the union
-  LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
-                                                &lvr, less_ptr<LiveInterval>());
-  assert((pos == lvrs_.end() || *pos != &lvr) && "duplicate LVR insertion");
-  lvrs_.insert(pos, &lvr);
   // Insert each of the virtual register's live segments into the map
   SegmentIter segPos = segments_.begin();
   for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end();

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=117412&r1=117411&r2=117412&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Oct 26 17:58:24 2010
@@ -97,7 +97,6 @@
 private:
   unsigned repReg_;        // representative register number
   LiveSegments segments_;  // union of virtual reg segements
-  LiveVirtRegs lvrs_;      // set of live virtual regs in the union
 
 public:
   // default ctor avoids placement new



From dalej at apple.com  Tue Oct 26 18:11:10 2010
From: dalej at apple.com (Dale Johannesen)
Date: Tue, 26 Oct 2010 23:11:10 -0000
Subject: [llvm-commits] [llvm] r117413 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/Target/X86/X86ISelDAGToDAG.cpp
Message-ID: <20101026231110.8E6152A6C12C@llvm.org>

Author: johannes
Date: Tue Oct 26 18:11:10 2010
New Revision: 117413

URL: http://llvm.org/viewvc/llvm-project?rev=117413&view=rev
Log:
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=117413&r1=117412&r2=117413&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Oct 26 18:11:10 2010
@@ -936,6 +936,7 @@
     // with either an intrinsic or a target opcode.
     return N->getOpcode() == ISD::LOAD                ||
            N->getOpcode() == ISD::STORE               ||
+           N->getOpcode() == ISD::PREFETCH            ||
            N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
            N->getOpcode() == ISD::ATOMIC_SWAP         ||
            N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
@@ -1011,8 +1012,8 @@
 
 /// MemIntrinsicSDNode - This SDNode is used for target intrinsics that touch
 /// memory and need an associated MachineMemOperand. Its opcode may be
-/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific opcode with a
-/// value not less than FIRST_TARGET_MEMORY_OPCODE.
+/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
+/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
 class MemIntrinsicSDNode : public MemSDNode {
 public:
   MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
@@ -1028,6 +1029,7 @@
     // early a node with a target opcode can be of this class
     return N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
            N->getOpcode() == ISD::INTRINSIC_VOID ||
+           N->getOpcode() == ISD::PREFETCH ||
            N->isTargetMemoryOpcode();
   }
 };

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=117413&r1=117412&r2=117413&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Oct 26 18:11:10 2010
@@ -3829,6 +3829,7 @@
                                   EVT MemVT, MachineMemOperand *MMO) {
   assert((Opcode == ISD::INTRINSIC_VOID ||
           Opcode == ISD::INTRINSIC_W_CHAIN ||
+          Opcode == ISD::PREFETCH ||
           (Opcode <= INT_MAX &&
            (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
          "Opcode is not a memory-accessing opcode!");

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=117413&r1=117412&r2=117413&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Oct 26 18:11:10 2010
@@ -4617,14 +4617,22 @@
 
   case Intrinsic::prefetch: {
     SDValue Ops[4];
+    unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
     Ops[0] = getRoot();
     Ops[1] = getValue(I.getArgOperand(0));
     Ops[2] = getValue(I.getArgOperand(1));
     Ops[3] = getValue(I.getArgOperand(2));
-    DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
+    DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
+                                        DAG.getVTList(MVT::Other),
+                                        &Ops[0], 4, 
+                                        EVT::getIntegerVT(*Context, 8),
+                                        MachinePointerInfo(I.getArgOperand(0)),
+                                        0, /* align */
+                                        false, /* volatile */
+                                        rw==0, /* read */
+                                        rw==1)); /* write */
     return 0;
   }
-
   case Intrinsic::memory_barrier: {
     SDValue Ops[6];
     Ops[0] = getRoot();

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=117413&r1=117412&r2=117413&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Oct 26 18:11:10 2010
@@ -1147,7 +1147,6 @@
   if (Parent &&
       // This list of opcodes are all the nodes that have an "addr:$ptr" operand
       // that are not a MemSDNode, and thus don't have proper addrspace info.
-      Parent->getOpcode() != ISD::PREFETCH &&
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
       Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme



From gohman at apple.com  Tue Oct 26 18:24:54 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 26 Oct 2010 23:24:54 -0000
Subject: [llvm-commits] [llvm] r117415 - /llvm/trunk/utils/vim/vimrc
Message-ID: <20101026232454.70E582A6C12C@llvm.org>

Author: djg
Date: Tue Oct 26 18:24:54 2010
New Revision: 117415

URL: http://llvm.org/viewvc/llvm-project?rev=117415&view=rev
Log:
Enable clang autocompletion by default.

Modified:
    llvm/trunk/utils/vim/vimrc

Modified: llvm/trunk/utils/vim/vimrc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/vim/vimrc?rev=117415&r1=117414&r2=117415&view=diff
==============================================================================
--- llvm/trunk/utils/vim/vimrc (original)
+++ llvm/trunk/utils/vim/vimrc Tue Oct 26 18:24:54 2010
@@ -92,7 +92,7 @@
 "set incsearch
 "set ruler
 
-" Clang code-completion support. This is highly experimental!
+" Clang code-completion support. This is somewhat experimental!
 
 " A path to a clang executable.
 let g:clang_path = "clang++"
@@ -216,5 +216,6 @@
    return []
 endfunction ClangComplete
 
-" Uncomment this to enable the highly-broken autocompletion support.
-"set omnifunc=ClangComplete
+" This to enables the somewhat-experimental clang-based
+" autocompletion support.
+set omnifunc=ClangComplete



From grosbach at apple.com  Tue Oct 26 18:58:04 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 26 Oct 2010 23:58:04 -0000
Subject: [llvm-commits] [llvm] r117418 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20101026235804.991EC2A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 18:58:04 2010
New Revision: 117418

URL: http://llvm.org/viewvc/llvm-project?rev=117418&view=rev
Log:
Since I parameterized this bit, I should probably actually use said parameter.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117418&r1=117417&r2=117418&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 26 18:58:04 2010
@@ -808,7 +808,7 @@
   // Note: We use the complex addrmode_imm12 rather than just an input
   // GPR and a constrained immediate so that we can use this to match
   // frame index references and avoid matching constant pool references.
-  def i12 : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
+  def i12 : AIldr1<0b010, opc22, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
                    AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
                   [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
     bits<4> Rt;
@@ -818,7 +818,7 @@
     let Inst{15-12} = Rt;
     let Inst{11-0}  = addr{11-0};   // imm12
   }
-  def rs : AIldr1<0b011, 0, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
+  def rs : AIldr1<0b011, opc22, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
                   AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
                  [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
     bits<4> Rt;



From grosbach at apple.com  Tue Oct 26 19:19:44 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 00:19:44 -0000
Subject: [llvm-commits] [llvm] r117419 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMBaseInstrInfo.cpp ARMBaseRegisterInfo.cpp
 ARMFastISel.cpp ARMInstrInfo.cpp ARMInstrInfo.td
Message-ID: <20101027001944.EBEAB2A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 19:19:44 2010
New Revision: 117419

URL: http://llvm.org/viewvc/llvm-project?rev=117419&view=rev
Log:
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117419&r1=117418&r2=117419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Oct 26 19:19:44 2010
@@ -874,7 +874,7 @@
     case ARM::PICSTRB:  Opcode = ARM::STRB; break;
     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
-    case ARM::PICLDRB:  Opcode = ARM::LDRB; break;
+    case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117419&r1=117418&r2=117419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Oct 26 19:19:44 2010
@@ -1080,7 +1080,7 @@
   default:
     return false;
   case ARM::LDRi12:
-  case ARM::LDRB:
+  case ARM::LDRBi12:
   case ARM::LDRD:
   case ARM::LDRH:
   case ARM::LDRSB:
@@ -1099,7 +1099,7 @@
   default:
     return false;
   case ARM::LDRi12:
-  case ARM::LDRB:
+  case ARM::LDRBi12:
   case ARM::LDRD:
   case ARM::LDRH:
   case ARM::LDRSB:

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=117419&r1=117418&r2=117419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Oct 26 19:19:44 2010
@@ -1376,7 +1376,7 @@
   // return false for everything else.
   unsigned Opc = MI->getOpcode();
   switch (Opc) {
-  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRB:
+  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
   case ARM::STR: case ARM::STRH: case ARM::STRB:
   case ARM::t2LDRi12: case ARM::t2LDRi8:
   case ARM::t2STRi12: case ARM::t2STRi8:

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=117419&r1=117418&r2=117419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Oct 26 19:19:44 2010
@@ -746,7 +746,7 @@
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::i8:
-      Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB;
+      Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::i32:
@@ -774,8 +774,6 @@
   if (isFloat)
     Offset /= 4;
   
-  // The thumb and floating point instructions both take 2 operands, ARM takes
-  // another register.
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                           TII.get(Opc), ResultReg)
                   .addReg(Base).addImm(Offset));

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=117419&r1=117418&r2=117419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Oct 26 19:19:44 2010
@@ -39,7 +39,7 @@
     return ARM::LDRH;
   case ARM::LDRB_PRE:
   case ARM::LDRB_POST:
-    return ARM::LDRB;
+    return ARM::LDRBi12;
   case ARM::LDRSH_PRE:
   case ARM::LDRSH_POST:
     return ARM::LDRSH;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117419&r1=117418&r2=117419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 26 19:19:44 2010
@@ -1400,8 +1400,10 @@
 // Load
 
 
-defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
-                   UnOpFrag<(load node:$Src)>>;
+defm LDR  : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
+                    UnOpFrag<(load node:$Src)>>;
+defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
+                    UnOpFrag<(zextloadi8 node:$Src)>>;
 
 // Special LDR for loads from non-pc-relative constpools.
 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
@@ -1421,10 +1423,6 @@
                   IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
                   [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
 
-def LDRB  : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
-                  IIC_iLoad_bh_r, "ldrb", "\t$dst, $addr",
-                  [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
-
 // Loads with sign extension
 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
                    IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
@@ -3165,11 +3163,16 @@
       Requires<[IsARM, IsDarwin]>;
 
 // zextload i1 -> zextload i8
-def : ARMPat<(zextloadi1 addrmode2:$addr),  (LDRB addrmode2:$addr)>;
+//def : ARMPat<(zextloadi1 addrmode2:$addr),  (LDRB addrmode2:$addr)>;
+def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
+def : ARMPat<(zextloadi1 ldst_so_reg:$addr),    (LDRBrs ldst_so_reg:$addr)>;
 
 // extload -> zextload
-def : ARMPat<(extloadi1  addrmode2:$addr),  (LDRB addrmode2:$addr)>;
-def : ARMPat<(extloadi8  addrmode2:$addr),  (LDRB addrmode2:$addr)>;
+def : ARMPat<(extloadi1 addrmode_imm12:$addr),  (LDRBi12 addrmode_imm12:$addr)>;
+def : ARMPat<(extloadi1 ldst_so_reg:$addr),     (LDRBrs ldst_so_reg:$addr)>;
+def : ARMPat<(extloadi8 addrmode_imm12:$addr),  (LDRBi12 addrmode_imm12:$addr)>;
+def : ARMPat<(extloadi8 ldst_so_reg:$addr),     (LDRBrs ldst_so_reg:$addr)>;
+
 def : ARMPat<(extloadi16 addrmode3:$addr),  (LDRH addrmode3:$addr)>;
 
 def : ARMPat<(extloadi8  addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;



From evan.cheng at apple.com  Tue Oct 26 19:22:13 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 26 Oct 2010 17:22:13 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <3A50637E-8C3D-47AD-AD5B-41128CFA01DD@2pi.dk>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
	<DAB3F4F4-42CB-4978-AE22-6DD29AC8F65B@2pi.dk>
	<F79E0D5E-2C2D-47E9-8F42-9C47CF6330E3@apple.com>
	<3A50637E-8C3D-47AD-AD5B-41128CFA01DD@2pi.dk>
Message-ID: <EDB55FD0-3D52-42E8-ABC9-C454B12A2B03@apple.com>


On Oct 26, 2010, at 3:59 PM, Jakob Stoklund Olesen wrote:

> 
> On Oct 26, 2010, at 3:46 PM, Evan Cheng wrote:
> 
>> 
>> On Oct 26, 2010, at 1:19 PM, Jakob Stoklund Olesen wrote:
> 
>>> If the LiveStacks are minimal, it is fine to calculate them on the fly, right? Or du you have a reason for wanting to compute them after allocation?
>> 
>> No particular reason. LiveStacks is a bit of a hack, I just think we should work towards removing the hack. Not having the allocator updating it is a good start.
> 
> What do you have in mind? It seems like an OK design to me.

1) LiveStacks is only used to track live time of spill slots. We would want to track non-spill ones as well.
2) It's using LiveIntervals. Doesn't it seem a bit heavy weight?

> 
> Obviously, StackSlotColoring needs to stop doing register allocation (!!), and it could probably share more code with the register allocator.

Like I said, a bit of a hack. :-)

Evan

> 
> /jakob
> 

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From peckw at wesleypeck.com  Tue Oct 26 19:23:02 2010
From: peckw at wesleypeck.com (Wesley Peck)
Date: Wed, 27 Oct 2010 00:23:02 -0000
Subject: [llvm-commits] [llvm] r117420 - in /llvm/trunk: cmake/modules/
 lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/
 lib/Target/MBlaze/Disassembler/
Message-ID: <20101027002302.2AE5F2A6C12C@llvm.org>

Author: peckw
Date: Tue Oct 26 19:23:01 2010
New Revision: 117420

URL: http://llvm.org/viewvc/llvm-project?rev=117420&view=rev
Log:
Adding disassembler to the MicroBlaze backend.

Added:
    llvm/trunk/lib/Target/MBlaze/Disassembler/
    llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt
    llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
    llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
    llvm/trunk/lib/Target/MBlaze/Disassembler/Makefile
Modified:
    llvm/trunk/cmake/modules/LLVMLibDeps.cmake
    llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
    llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
    llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrFSL.td
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td
    llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h
    llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp
    llvm/trunk/lib/Target/MBlaze/Makefile
    llvm/trunk/lib/Target/MBlaze/TODO

Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Tue Oct 26 19:23:01 2010
@@ -33,9 +33,10 @@
 set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
 set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport LLVMSystem)
 set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport)
 set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMSupport)
 set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem)
-set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPTXAsmPrinter LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo)
+set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPTXAsmPrinter LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo)
 set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport LLVMSystem)
 set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport LLVMSystem)
 set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)

Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Tue Oct 26 19:23:01 2010
@@ -72,10 +72,6 @@
 
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
 
-  bool ParseDirectiveThumb(SMLoc L);
-
-  bool ParseDirectiveThumbFunc(SMLoc L);
-
   bool ParseDirectiveCode(SMLoc L);
 
   bool ParseDirectiveSyntax(SMLoc L);
@@ -750,10 +746,6 @@
   StringRef IDVal = DirectiveID.getIdentifier();
   if (IDVal == ".word")
     return ParseDirectiveWord(4, DirectiveID.getLoc());
-  else if (IDVal == ".thumb")
-    return ParseDirectiveThumb(DirectiveID.getLoc());
-  else if (IDVal == ".thumb_func")
-    return ParseDirectiveThumbFunc(DirectiveID.getLoc());
   else if (IDVal == ".code")
     return ParseDirectiveCode(DirectiveID.getLoc());
   else if (IDVal == ".syntax")
@@ -786,36 +778,6 @@
   return false;
 }
 
-/// ParseDirectiveThumb
-///  ::= .thumb
-bool MBlazeAsmParser::ParseDirectiveThumb(SMLoc L) {
-  if (getLexer().isNot(AsmToken::EndOfStatement))
-    return Error(L, "unexpected token in directive");
-  Parser.Lex();
-
-  // TODO: set thumb mode
-  // TODO: tell the MC streamer the mode
-  // getParser().getStreamer().Emit???();
-  return false;
-}
-
-/// ParseDirectiveThumbFunc
-///  ::= .thumbfunc symbol_name
-bool MBlazeAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
-  const AsmToken &Tok = Parser.getTok();
-  if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
-    return Error(L, "unexpected token in .syntax directive");
-  Parser.Lex(); // Consume the identifier token.
-
-  if (getLexer().isNot(AsmToken::EndOfStatement))
-    return Error(L, "unexpected token in directive");
-  Parser.Lex();
-
-  // TODO: mark symbol as a thumb symbol
-  // getParser().getStreamer().Emit???();
-  return false;
-}
-
 /// ParseDirectiveSyntax
 ///  ::= .syntax unified | divided
 bool MBlazeAsmParser::ParseDirectiveSyntax(SMLoc L) {

Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Tue Oct 26 19:23:01 2010
@@ -12,6 +12,7 @@
 tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
 tablegen(MBlazeGenSubtarget.inc -gen-subtarget)
 tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
+tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
 
 add_llvm_target(MBlazeCodeGen
   MBlazeDelaySlotFiller.cpp

Added: llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt?rev=117420&view=auto
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt (added)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt Tue Oct 26 19:23:01 2010
@@ -0,0 +1,16 @@
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. 
+                     ${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_library(LLVMMBlazeDisassembler
+  MBlazeDisassembler.cpp
+  )
+
+# workaround for hanging compilation on MSVC9 and 10
+if( MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 )
+set_property(
+  SOURCE MBlazeDisassembler.cpp
+  PROPERTY COMPILE_FLAGS "/Od"
+  )
+endif()
+
+add_dependencies(LLVMMBlazeDisassembler MBlazeCodeGenTable_gen)

Added: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=117420&view=auto
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (added)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Tue Oct 26 19:23:01 2010
@@ -0,0 +1,578 @@
+//===- MBlazeDisassembler.cpp - Disassembler for MicroBlaze  ----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the MBlaze Disassembler. It contains code to translate
+// the data produced by the decoder into MCInsts.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MBlaze.h"
+#include "MBlazeInstrInfo.h"
+#include "MBlazeDisassembler.h"
+
+#include "llvm/MC/EDInstInfo.h"
+#include "llvm/MC/MCDisassembler.h"
+#include "llvm/MC/MCDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/Target/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/MemoryObject.h"
+#include "llvm/Support/raw_ostream.h"
+
+// #include "MBlazeGenDecoderTables.inc"
+// #include "MBlazeGenRegisterNames.inc"
+#include "MBlazeGenInstrInfo.inc"
+#include "MBlazeGenEDInfo.inc"
+
+using namespace llvm;
+
+const unsigned UNSUPPORTED = -1;
+
+static unsigned mblazeBinary2Opcode[] = {
+  MBlaze::ADD,   MBlaze::RSUB,   MBlaze::ADDC,   MBlaze::RSUBC,   //00,01,02,03
+  MBlaze::ADDK,  MBlaze::RSUBK,  MBlaze::ADDKC,  MBlaze::RSUBKC,  //04,05,06,07
+  MBlaze::ADDI,  MBlaze::RSUBI,  MBlaze::ADDIC,  MBlaze::RSUBIC,  //08,09,0A,0B
+  MBlaze::ADDIK, MBlaze::RSUBIK, MBlaze::ADDIKC, MBlaze::RSUBIKC, //0C,0D,0E,0F
+
+  MBlaze::MUL,   MBlaze::BSRL,   MBlaze::IDIV,   MBlaze::GETD,    //10,11,12,13
+  UNSUPPORTED,   UNSUPPORTED,    MBlaze::FADD,   UNSUPPORTED,     //14,15,16,17
+  MBlaze::MULI,  MBlaze::BSRLI,  UNSUPPORTED,    MBlaze::GET,     //18,19,1A,1B
+  UNSUPPORTED,   UNSUPPORTED,    UNSUPPORTED,    UNSUPPORTED,     //1C,1D,1E,1F
+
+  MBlaze::OR,    MBlaze::AND,    MBlaze::XOR,    MBlaze::ANDN,    //20,21,22,23
+  MBlaze::SEXT8, MBlaze::MFS,    MBlaze::BR,     MBlaze::BEQ,     //24,25,26,27
+  MBlaze::ORI,   MBlaze::ANDI,   MBlaze::XORI,   MBlaze::ANDNI,   //28,29,2A,2B
+  MBlaze::IMM,   MBlaze::RTSD,   MBlaze::BRI,    MBlaze::BEQI,    //2C,2D,2E,2F
+
+  MBlaze::LBU,   MBlaze::LHU,    MBlaze::LW,     UNSUPPORTED,     //30,31,32,33
+  MBlaze::SB,    MBlaze::SH,     MBlaze::SW,     UNSUPPORTED,     //34,35,36,37
+  MBlaze::LBUI,  MBlaze::LHUI,   MBlaze::LWI,    UNSUPPORTED,     //38,39,3A,3B
+  MBlaze::SBI,   MBlaze::SHI,    MBlaze::SWI,    UNSUPPORTED,     //3C,3D,3E,3F
+};
+
+static unsigned getRD( uint32_t insn ) {
+  return MBlazeRegisterInfo::getRegisterFromNumbering( (insn>>21)&0x1F );
+}
+
+static unsigned getRA( uint32_t insn ) {
+  return MBlazeRegisterInfo::getRegisterFromNumbering( (insn>>16)&0x1F );
+}
+
+static unsigned getRB( uint32_t insn ) {
+  return MBlazeRegisterInfo::getRegisterFromNumbering( (insn>>11)&0x1F );
+}
+
+static int64_t getRS( uint32_t insn ) {
+    int16_t val = (insn & 0x3FFF);
+    return val;
+}
+
+static int64_t getIMM( uint32_t insn ) {
+    int16_t val = (insn & 0xFFFF);
+    return val;
+}
+
+static int64_t getSHT( uint32_t insn ) {
+    int16_t val = (insn & 0x1F);
+    return val;
+}
+
+static unsigned getFLAGS( int32_t insn ) {
+    return (insn & 0x7FF);
+}
+
+static int64_t getFSL( uint32_t insn ) {
+    int16_t val = (insn & 0xF);
+    return val;
+}
+
+static unsigned decodeMUL(uint32_t insn) {
+    switch (getFLAGS(insn)) {
+    default: return UNSUPPORTED;
+    case 0:  return MBlaze::MUL;
+    case 1:  return MBlaze::MULH;
+    case 2:  return MBlaze::MULHSU;
+    case 3:  return MBlaze::MULHU;
+    }
+}
+
+static unsigned decodeSEXT(uint32_t insn) {
+    switch (getIMM(insn)) {
+    default:   return UNSUPPORTED;
+    case 0x60: return MBlaze::SEXT8;
+    case 0x68: return MBlaze::WIC;
+    case 0x64: return MBlaze::WDC;
+    case 0x66: return MBlaze::WDCC;
+    case 0x74: return MBlaze::WDCF;
+    case 0x61: return MBlaze::SEXT16;
+    case 0x41: return MBlaze::SRL;
+    case 0x21: return MBlaze::SRC;
+    case 0x01: return MBlaze::SRA;
+    }
+}
+
+static unsigned decodeBEQ(uint32_t insn) {
+    switch (getRD(insn)) {
+    default:    return UNSUPPORTED;
+    case 0x00:  return MBlaze::BEQ;
+    case 0x10:  return MBlaze::BEQD;
+    case 0x05:  return MBlaze::BGE;
+    case 0x15:  return MBlaze::BGED;
+    case 0x04:  return MBlaze::BGT;
+    case 0x14:  return MBlaze::BGTD;
+    case 0x03:  return MBlaze::BLE;
+    case 0x13:  return MBlaze::BLED;
+    case 0x02:  return MBlaze::BLT;
+    case 0x12:  return MBlaze::BLTD;
+    case 0x01:  return MBlaze::BNE;
+    case 0x11:  return MBlaze::BNED;
+    }
+}
+
+static unsigned decodeBEQI(uint32_t insn) {
+    switch (getRD(insn)) {
+    default:    return UNSUPPORTED;
+    case 0x00:  return MBlaze::BEQI;
+    case 0x10:  return MBlaze::BEQID;
+    case 0x05:  return MBlaze::BGEI;
+    case 0x15:  return MBlaze::BGEID;
+    case 0x04:  return MBlaze::BGTI;
+    case 0x14:  return MBlaze::BGTID;
+    case 0x03:  return MBlaze::BLEI;
+    case 0x13:  return MBlaze::BLEID;
+    case 0x02:  return MBlaze::BLTI;
+    case 0x12:  return MBlaze::BLTID;
+    case 0x01:  return MBlaze::BNEI;
+    case 0x11:  return MBlaze::BNEID;
+    }
+}
+
+static unsigned decodeBR(uint32_t insn) {
+    switch ((insn>>16)&0x1F) {
+    default:   return UNSUPPORTED;
+    case 0x00: return MBlaze::BR;
+    case 0x08: return MBlaze::BRA;
+    case 0x0C: return MBlaze::BRK;
+    case 0x10: return MBlaze::BRD;
+    case 0x14: return MBlaze::BRLD;
+    case 0x18: return MBlaze::BRAD;
+    case 0x1C: return MBlaze::BRALD;
+    }
+}
+
+static unsigned decodeBRI(uint32_t insn) {
+    switch ((insn>>16)&0x1F) {
+    default:   return UNSUPPORTED;
+    case 0x00: return MBlaze::BRI;
+    case 0x08: return MBlaze::BRAI;
+    case 0x0C: return MBlaze::BRKI;
+    case 0x10: return MBlaze::BRID;
+    case 0x14: return MBlaze::BRLID;
+    case 0x18: return MBlaze::BRAID;
+    case 0x1C: return MBlaze::BRALID;
+    }
+}
+
+static unsigned decodeBSRL(uint32_t insn) {
+    switch ((insn>>9)&0x3) {
+    default:  return UNSUPPORTED;
+    case 0x2: return MBlaze::BSLL;
+    case 0x1: return MBlaze::BSRA;
+    case 0x0: return MBlaze::BSRL;
+    }
+}
+
+static unsigned decodeBSRLI(uint32_t insn) {
+    switch ((insn>>9)&0x3) {
+    default:  return UNSUPPORTED;
+    case 0x2: return MBlaze::BSLLI;
+    case 0x1: return MBlaze::BSRAI;
+    case 0x0: return MBlaze::BSRLI;
+    }
+}
+
+static unsigned decodeRSUBK(uint32_t insn) {
+    switch (getFLAGS(insn)) {
+    default:  return UNSUPPORTED;
+    case 0x0: return MBlaze::RSUBK;
+    case 0x1: return MBlaze::CMP;
+    case 0x3: return MBlaze::CMPU;
+    }
+}
+
+static unsigned decodeFADD(uint32_t insn) {
+    switch (getFLAGS(insn)) {
+    default:    return UNSUPPORTED;
+    case 0x000: return MBlaze::FADD;
+    case 0x080: return MBlaze::FRSUB;
+    case 0x100: return MBlaze::FMUL;
+    case 0x180: return MBlaze::FDIV;
+    case 0x200: return MBlaze::FCMP_UN;
+    case 0x210: return MBlaze::FCMP_LT;
+    case 0x220: return MBlaze::FCMP_EQ;
+    case 0x230: return MBlaze::FCMP_LE;
+    case 0x240: return MBlaze::FCMP_GT;
+    case 0x250: return MBlaze::FCMP_NE;
+    case 0x260: return MBlaze::FCMP_GE;
+    case 0x280: return MBlaze::FLT;
+    case 0x300: return MBlaze::FINT;
+    case 0x380: return MBlaze::FSQRT;
+    }
+}
+
+static unsigned decodeGET(uint32_t insn) {
+    switch ((insn>>10)&0x3F) {
+    default:   return UNSUPPORTED;
+    case 0x00: return MBlaze::GET;
+    case 0x01: return MBlaze::EGET;
+    case 0x02: return MBlaze::AGET;
+    case 0x03: return MBlaze::EAGET;
+    case 0x04: return MBlaze::TGET;
+    case 0x05: return MBlaze::TEGET;
+    case 0x06: return MBlaze::TAGET;
+    case 0x07: return MBlaze::TEAGET;
+    case 0x08: return MBlaze::CGET;
+    case 0x09: return MBlaze::ECGET;
+    case 0x0A: return MBlaze::CAGET;
+    case 0x0B: return MBlaze::ECAGET;
+    case 0x0C: return MBlaze::TCGET;
+    case 0x0D: return MBlaze::TECGET;
+    case 0x0E: return MBlaze::TCAGET;
+    case 0x0F: return MBlaze::TECAGET;
+    case 0x10: return MBlaze::NGET;
+    case 0x11: return MBlaze::NEGET;
+    case 0x12: return MBlaze::NAGET;
+    case 0x13: return MBlaze::NEAGET;
+    case 0x14: return MBlaze::TNGET;
+    case 0x15: return MBlaze::TNEGET;
+    case 0x16: return MBlaze::TNAGET;
+    case 0x17: return MBlaze::TNEAGET;
+    case 0x18: return MBlaze::NCGET;
+    case 0x19: return MBlaze::NECGET;
+    case 0x1A: return MBlaze::NCAGET;
+    case 0x1B: return MBlaze::NECAGET;
+    case 0x1C: return MBlaze::TNCGET;
+    case 0x1D: return MBlaze::TNECGET;
+    case 0x1E: return MBlaze::TNCAGET;
+    case 0x1F: return MBlaze::TNECAGET;
+    case 0x20: return MBlaze::PUT;
+    case 0x22: return MBlaze::APUT;
+    case 0x24: return MBlaze::TPUT;
+    case 0x26: return MBlaze::TAPUT;
+    case 0x28: return MBlaze::CPUT;
+    case 0x2A: return MBlaze::CAPUT;
+    case 0x2C: return MBlaze::TCPUT;
+    case 0x2E: return MBlaze::TCAPUT;
+    case 0x30: return MBlaze::NPUT;
+    case 0x32: return MBlaze::NAPUT;
+    case 0x34: return MBlaze::TNPUT;
+    case 0x36: return MBlaze::TNAPUT;
+    case 0x38: return MBlaze::NCPUT;
+    case 0x3A: return MBlaze::NCAPUT;
+    case 0x3C: return MBlaze::TNCPUT;
+    case 0x3E: return MBlaze::TNCAPUT;
+    }
+}
+
+static unsigned decodeGETD(uint32_t insn) {
+    switch ((insn>>5)&0x3F) {
+    default:   return UNSUPPORTED;
+    case 0x00: return MBlaze::GETD;
+    case 0x01: return MBlaze::EGETD;
+    case 0x02: return MBlaze::AGETD;
+    case 0x03: return MBlaze::EAGETD;
+    case 0x04: return MBlaze::TGETD;
+    case 0x05: return MBlaze::TEGETD;
+    case 0x06: return MBlaze::TAGETD;
+    case 0x07: return MBlaze::TEAGETD;
+    case 0x08: return MBlaze::CGETD;
+    case 0x09: return MBlaze::ECGETD;
+    case 0x0A: return MBlaze::CAGETD;
+    case 0x0B: return MBlaze::ECAGETD;
+    case 0x0C: return MBlaze::TCGETD;
+    case 0x0D: return MBlaze::TECGETD;
+    case 0x0E: return MBlaze::TCAGETD;
+    case 0x0F: return MBlaze::TECAGETD;
+    case 0x10: return MBlaze::NGETD;
+    case 0x11: return MBlaze::NEGETD;
+    case 0x12: return MBlaze::NAGETD;
+    case 0x13: return MBlaze::NEAGETD;
+    case 0x14: return MBlaze::TNGETD;
+    case 0x15: return MBlaze::TNEGETD;
+    case 0x16: return MBlaze::TNAGETD;
+    case 0x17: return MBlaze::TNEAGETD;
+    case 0x18: return MBlaze::NCGETD;
+    case 0x19: return MBlaze::NECGETD;
+    case 0x1A: return MBlaze::NCAGETD;
+    case 0x1B: return MBlaze::NECAGETD;
+    case 0x1C: return MBlaze::TNCGETD;
+    case 0x1D: return MBlaze::TNECGETD;
+    case 0x1E: return MBlaze::TNCAGETD;
+    case 0x1F: return MBlaze::TNECAGETD;
+    case 0x20: return MBlaze::PUTD;
+    case 0x22: return MBlaze::APUTD;
+    case 0x24: return MBlaze::TPUTD;
+    case 0x26: return MBlaze::TAPUTD;
+    case 0x28: return MBlaze::CPUTD;
+    case 0x2A: return MBlaze::CAPUTD;
+    case 0x2C: return MBlaze::TCPUTD;
+    case 0x2E: return MBlaze::TCAPUTD;
+    case 0x30: return MBlaze::NPUTD;
+    case 0x32: return MBlaze::NAPUTD;
+    case 0x34: return MBlaze::TNPUTD;
+    case 0x36: return MBlaze::TNAPUTD;
+    case 0x38: return MBlaze::NCPUTD;
+    case 0x3A: return MBlaze::NCAPUTD;
+    case 0x3C: return MBlaze::TNCPUTD;
+    case 0x3E: return MBlaze::TNCAPUTD;
+    }
+}
+
+static unsigned decodeIDIV(uint32_t insn) {
+    switch (insn&0x3) {
+    default:  return UNSUPPORTED;
+    case 0x0: return MBlaze::IDIV;
+    case 0x2: return MBlaze::IDIVU;
+    }
+}
+
+static unsigned decodeLW(uint32_t insn) {
+    switch ((insn>>9)&0x3) {
+    default:  return UNSUPPORTED;
+    case 0x0: return MBlaze::LW;
+    case 0x1: return MBlaze::LWR;
+    case 0x2: return MBlaze::LWX;
+    }
+}
+
+static unsigned decodeSW(uint32_t insn) {
+    switch ((insn>>9)&0x3) {
+    default:  return UNSUPPORTED;
+    case 0x0: return MBlaze::SW;
+    case 0x1: return MBlaze::SWR;
+    case 0x2: return MBlaze::SWX;
+    }
+}
+
+static unsigned decodeMFS(uint32_t insn) {
+    switch ((insn>>15)&0x1) {
+    default:   return UNSUPPORTED;
+    case 0x0:
+      switch ((insn>>16)&0x1F) {
+      default:   return UNSUPPORTED;
+      case 0x22: return MBlaze::MSRCLR;
+      case 0x20: return MBlaze::MSRSET;
+      }
+    case 0x1:
+      switch ((insn>>14)&0x1) {
+      default:   return UNSUPPORTED;
+      case 0x0: return MBlaze::MFS;
+      case 0x1: return MBlaze::MTS;
+      }
+    }
+}
+
+static unsigned decodeOR(uint32_t insn) {
+    switch (getFLAGS(insn)) {
+    default:    return UNSUPPORTED;
+    case 0x000: return MBlaze::OR;
+    case 0x400: return MBlaze::PCMPBF;
+    }
+}
+
+static unsigned decodeXOR(uint32_t insn) {
+    switch (getFLAGS(insn)) {
+    default:    return UNSUPPORTED;
+    case 0x000: return MBlaze::OR;
+    case 0x400: return MBlaze::PCMPEQ;
+    }
+}
+
+static unsigned decodeANDN(uint32_t insn) {
+    switch (getFLAGS(insn)) {
+    default:    return UNSUPPORTED;
+    case 0x000: return MBlaze::OR;
+    case 0x400: return MBlaze::PCMPNE;
+    }
+}
+
+static unsigned decodeRTSD(uint32_t insn) {
+    switch ((insn>>21)&0x1F) {
+    default:   return UNSUPPORTED;
+    case 0x10: return MBlaze::RTSD;
+    case 0x11: return MBlaze::RTID;
+    case 0x12: return MBlaze::RTBD;
+    case 0x14: return MBlaze::RTED;
+    }
+}
+
+static unsigned getOPCODE( uint32_t insn ) {
+  unsigned opcode = mblazeBinary2Opcode[ (insn>>26)&0x3F ];
+  switch (opcode) {
+  case MBlaze::MUL:     return decodeMUL(insn);
+  case MBlaze::SEXT8:   return decodeSEXT(insn);
+  case MBlaze::BEQ:     return decodeBEQ(insn);
+  case MBlaze::BEQI:    return decodeBEQI(insn);
+  case MBlaze::BR:      return decodeBR(insn);
+  case MBlaze::BRI:     return decodeBRI(insn);
+  case MBlaze::BSRL:    return decodeBSRL(insn);
+  case MBlaze::BSRLI:   return decodeBSRLI(insn);
+  case MBlaze::RSUBK:   return decodeRSUBK(insn);
+  case MBlaze::FADD:    return decodeFADD(insn);
+  case MBlaze::GET:     return decodeGET(insn);
+  case MBlaze::GETD:    return decodeGETD(insn);
+  case MBlaze::IDIV:    return decodeIDIV(insn);
+  case MBlaze::LW:      return decodeLW(insn);
+  case MBlaze::SW:      return decodeSW(insn);
+  case MBlaze::MFS:     return decodeMFS(insn);
+  case MBlaze::OR:      return decodeOR(insn);
+  case MBlaze::XOR:     return decodeXOR(insn);
+  case MBlaze::ANDN:    return decodeANDN(insn);
+  case MBlaze::RTSD:    return decodeRTSD(insn);
+  default:              return opcode;
+  }
+}
+
+EDInstInfo *MBlazeDisassembler::getEDInfo() const {
+  return instInfoMBlaze;
+}
+
+//
+// Public interface for the disassembler
+//
+
+bool MBlazeDisassembler::getInstruction(MCInst &instr,
+                                        uint64_t &size,
+                                        const MemoryObject &region,
+                                        uint64_t address,
+                                        raw_ostream &vStream) const {
+  // The machine instruction.
+  uint32_t insn;
+  uint8_t bytes[4];
+  
+  // We want to read exactly 4 bytes of data.
+  if (region.readBytes(address, 4, (uint8_t*)bytes, NULL) == -1)
+    return false;
+
+  // Encoded as a big-endian 32-bit word in the stream.
+  insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0);
+
+  // Get the MCInst opcode from the binary instruction and make sure
+  // that it is a valid instruction.
+  unsigned opcode = getOPCODE( insn );
+  if( opcode == UNSUPPORTED )
+    return false;
+
+  instr.setOpcode(opcode);
+
+  uint64_t tsFlags = MBlazeInsts[opcode].TSFlags;
+  switch( (tsFlags & MBlazeII::FormMask) ) {
+  default: 
+    errs() << "Opcode:      " << MBlazeInsts[opcode].Name << "\n";
+    errs() << "Flags:       "; errs().write_hex( tsFlags ); errs() << "\n";
+    return false;
+
+  case MBlazeII::FRRR:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRB(insn) ) );
+    break;
+
+  case MBlazeII::FRRI:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) );
+    break;
+
+  case MBlazeII::FCRR:
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRB(insn) ) );
+    break;
+
+  case MBlazeII::FCRI:
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) );
+    break;
+
+  case MBlazeII::FRCR:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRB(insn) ) );
+    break;
+
+  case MBlazeII::FRCI:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) );
+    break;
+
+  case MBlazeII::FCCR:
+    instr.addOperand( MCOperand::CreateReg( getRB(insn) ) );
+    break;
+
+  case MBlazeII::FCCI:
+    instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) );
+    break;
+
+  case MBlazeII::FRRCI:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getSHT(insn) ) );
+    break;
+
+  case MBlazeII::FRRC:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    break;
+
+  case MBlazeII::FRCX:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getFSL(insn) ) );
+    break;
+
+  case MBlazeII::FRCS:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getRS(insn) ) );
+    break;
+
+  case MBlazeII::FCRCS:
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getRS(insn) ) );
+    break;
+
+  case MBlazeII::FCRCX:
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getFSL(insn) ) );
+    break;
+
+  case MBlazeII::FCX:
+    instr.addOperand( MCOperand::CreateImm( getFSL(insn) ) );
+    break;
+
+  case MBlazeII::FCR:
+    instr.addOperand( MCOperand::CreateReg( getRB(insn) ) );
+    break;
+
+  case MBlazeII::FRIR:
+    instr.addOperand( MCOperand::CreateReg( getRD(insn) ) );
+    instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) );
+    instr.addOperand( MCOperand::CreateReg( getRA(insn) ) );
+    break;
+  }
+
+  return true;
+}
+
+static MCDisassembler *createMBlazeDisassembler(const Target &T) {
+  return new MBlazeDisassembler;
+}
+
+extern "C" void LLVMInitializeMBlazeDisassembler() { 
+  // Register the disassembler.
+  TargetRegistry::RegisterMCDisassembler(TheMBlazeTarget, 
+                                         createMBlazeDisassembler);
+}

Added: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=117420&view=auto
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (added)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Tue Oct 26 19:23:01 2010
@@ -0,0 +1,55 @@
+//===- MBlazeDisassembler.h - Disassembler for MicroBlaze  ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the MBlaze Disassembler. It it the header for
+// MBlazeDisassembler, a subclass of MCDisassembler.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MBLAZEDISASSEMBLER_H
+#define MBLAZEDISASSEMBLER_H
+
+#include "llvm/MC/MCDisassembler.h"
+
+struct InternalInstruction;
+
+namespace llvm {
+  
+class MCInst;
+class MemoryObject;
+class raw_ostream;
+
+struct EDInstInfo;
+  
+/// MBlazeDisassembler - Disassembler for all MBlaze platforms.
+class MBlazeDisassembler : public MCDisassembler {
+public:
+  /// Constructor     - Initializes the disassembler.
+  ///
+  MBlazeDisassembler() :
+    MCDisassembler() {
+  }
+
+  ~MBlazeDisassembler() {
+  }
+
+  /// getInstruction - See MCDisassembler.
+  bool getInstruction(MCInst &instr,
+                      uint64_t &size,
+                      const MemoryObject &region,
+                      uint64_t address,
+                      raw_ostream &vStream) const;
+
+  /// getEDInfo - See MCDisassembler.
+  EDInstInfo *getEDInfo() const;
+};
+
+} // namespace llvm
+  
+#endif

Added: llvm/trunk/lib/Target/MBlaze/Disassembler/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/Makefile?rev=117420&view=auto
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/Makefile (added)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/Makefile Tue Oct 26 19:23:01 2010
@@ -0,0 +1,16 @@
+##===- lib/Target/MBlaze/Disassembler/Makefile -------------*- Makefile -*-===##
+#
+#                     The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../../..
+LIBRARYNAME = LLVMMBlazeDisassembler
+
+# Hack: we need to include 'main' MBlaze target directory to grab headers
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp Tue Oct 26 19:23:01 2010
@@ -7,7 +7,8 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Simple pass to fills delay slots with NOPs.
+// A pass that attempts to fill instructions with delay slots. If no
+// instructions can be moved into the delay slot then a NOP is placed there.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFSL.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFSL.td?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFSL.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFSL.td Tue Oct 26 19:23:01 2010
@@ -11,7 +11,7 @@
 // FSL Instruction Formats
 //===----------------------------------------------------------------------===//
 class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
-             MBlazeInst<op, FFSL, (outs GPR:$dst), (ins fslimm:$b),
+             MBlazeInst<op, FRCX, (outs GPR:$dst), (ins fslimm:$b),
                         !strconcat(instr_asm, " $dst, $b"),
                         [(set GPR:$dst, (OpNode immZExt4:$b))],IIAlu>
 {
@@ -27,7 +27,7 @@
 }
 
 class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
-              MBlazeInst<op, FFSLD, (outs GPR:$dst), (ins GPR:$b),
+              MBlazeInst<op, FRCR, (outs GPR:$dst), (ins GPR:$b),
                          !strconcat(instr_asm, " $dst, $b"),
                          [(set GPR:$dst, (OpNode GPR:$b))], IIAlu>
 {
@@ -43,7 +43,7 @@
 }
 
 class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
-             MBlazeInst<op, FFSL, (outs), (ins GPR:$v, fslimm:$b),
+             MBlazeInst<op, FCRCX, (outs), (ins GPR:$v, fslimm:$b),
                         !strconcat(instr_asm, " $v, $b"),
                         [(OpNode GPR:$v, immZExt4:$b)], IIAlu>
 {
@@ -59,7 +59,7 @@
 }
 
 class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
-              MBlazeInst<op, FFSLD, (outs), (ins GPR:$v, GPR:$b),
+              MBlazeInst<op, FCRR, (outs), (ins GPR:$v, GPR:$b),
                          !strconcat(instr_asm, " $v, $b"),
                          [(OpNode GPR:$v, GPR:$b)], IIAlu>
 {
@@ -75,7 +75,7 @@
 }
 
 class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
-              MBlazeInst<op, FFSLT, (outs), (ins fslimm:$b),
+              MBlazeInst<op, FCX, (outs), (ins fslimm:$b),
                          !strconcat(instr_asm, " $b"),
                          [(OpNode immZExt4:$b)], IIAlu>
 {
@@ -90,7 +90,7 @@
 }
 
 class FSLPutTD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
-               MBlazeInst<op, FFSLTD, (outs), (ins GPR:$b),
+               MBlazeInst<op, FCR, (outs), (ins GPR:$b),
                           !strconcat(instr_asm, " $b"),
                           [(OpNode GPR:$b)], IIAlu>
 {

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td Tue Oct 26 19:23:01 2010
@@ -15,17 +15,24 @@
 }
 
 def FPseudo : Format<0>;
-def FRRR    : Format<1>;
-def FRRI    : Format<2>;
-def FRIR    : Format<3>;
-def FFSL    : Format<4>;
-def FFSLD   : Format<5>;
-def FFSLT   : Format<6>;
-def FFSLTD  : Format<7>;
-def FR      : Format<8>;
-def FI      : Format<9>;
-def FRR     : Format<10>;
-def FRI     : Format<11>;
+def FRRR    : Format<1>;  // ADD, RSUB, OR, etc.
+def FRRI    : Format<2>;  // ADDI, RSUBI, ORI, etc.
+def FCRR    : Format<3>;  // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
+def FCRI    : Format<4>;  // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc.
+def FRCR    : Format<5>;  // BRLD, BRALD, GETD
+def FRCI    : Format<6>;  // BRLID, BRALID, MSRCLR, MSRSET
+def FCCR    : Format<7>;  // BR, BRA, BRD, etc.
+def FCCI    : Format<8>;  // IMM, BRI, BRAI, BRID, etc.
+def FRRCI   : Format<9>;  // BSRLI, BSRAI, BSLLI
+def FRRC    : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
+def FRCX    : Format<11>; // GET
+def FRCS    : Format<12>; // MFS
+def FCRCS   : Format<13>; // MTS
+def FCRCX   : Format<14>; // PUT
+def FCX     : Format<15>; // TPUT
+def FCR     : Format<16>; // TPUTD
+def FRIR    : Format<17>; // RSUBI
+def FC      : Format<18>; // NOP
 
 //===----------------------------------------------------------------------===//
 //  Describe MBlaze instructions format

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Tue Oct 26 19:23:01 2010
@@ -138,21 +138,26 @@
     // PseudoFrm - This represents an instruction that is a pseudo instruction
     // or one that has not been implemented yet.  It is illegal to code generate
     // it, but tolerated for intermediate implementation stages.
-    Pseudo         = 0,
-
-    RegRegReg      = 1,
-    RegRegImm      = 2,
-    RegImmReg      = 3,
-    FSL            = 4,
-    FSLD           = 5,
-    FSLT           = 6,
-    FSLTD          = 7,
-    Reg            = 8,
-    Imm            = 9,
-    RegReg         = 10,
-    RegImm         = 11,
-
-    FormMask       = 63
+    FPseudo = 0,
+    FRRR,
+    FRRI,
+    FCRR,
+    FCRI,
+    FRCR,
+    FRCI,
+    FCCR,
+    FCCI,
+    FRRCI,
+    FRRC,
+    FRCX,
+    FRCS,
+    FCRCS,
+    FCRCX,
+    FCX,
+    FCR,
+    FRIR,
+    FC,
+    FormMask = 63
 
     //===------------------------------------------------------------------===//
     // MBlaze Specific MachineOperand flags.

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Tue Oct 26 19:23:01 2010
@@ -203,6 +203,11 @@
                 [(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))],
                 IIAlu>;
 
+class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
+             TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
+                !strconcat(instr_asm, "   $dst, $b, $c"),
+                 [], IIAlu>;
+
 //===----------------------------------------------------------------------===//
 // Memory Access Instructions
 //===----------------------------------------------------------------------===//
@@ -211,6 +216,11 @@
                !strconcat(instr_asm, "   $dst, $addr"),
                [(set (i32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
 
+class LoadW<bits<6> op, bits<11> flags, string instr_asm> :
+            TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
+               !strconcat(instr_asm, "   $dst, $addr"),
+               [], IILoad>;
+
 class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
              TBR<op, (outs GPR:$dst), (ins memri:$addr),
                  !strconcat(instr_asm, "   $dst, $addr"),
@@ -221,6 +231,11 @@
                 !strconcat(instr_asm, "   $dst, $addr"),
                 [(OpNode (i32 GPR:$dst), xaddr:$addr)], IIStore>;
 
+class StoreW<bits<6> op, bits<11> flags, string instr_asm> :
+             TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
+                !strconcat(instr_asm, "   $dst, $addr"),
+                [], IIStore>;
+
 class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
               TBR<op, (outs), (ins GPR:$dst, memri:$addr),
                   !strconcat(instr_asm, "   $dst, $addr"),
@@ -231,10 +246,11 @@
 //===----------------------------------------------------------------------===//
 class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
              TA<op, flags, (outs), (ins GPR:$target),
-                 !strconcat(instr_asm, "   $target"),
-                 [], IIBranch> {
+                !strconcat(instr_asm, "   $target"),
+                [], IIBranch> {
   let rd = 0x0;
   let ra = br;
+  let Form = FCCR;
 }
 
 class BranchI<bits<6> op, bits<5> br, string instr_asm> :
@@ -243,25 +259,26 @@
                  [], IIBranch> {
   let rd = 0;
   let ra = br;
+  let Form = FCCI;
 }
 
 //===----------------------------------------------------------------------===//
 // Branch and Link Instructions
 //===----------------------------------------------------------------------===//
 class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
-              TA<op, flags, (outs), (ins GPR:$target),
-                 !strconcat(instr_asm, "   r15, $target"),
+              TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
+                 !strconcat(instr_asm, "   $link, $target"),
                  [], IIBranch> {
-  let rd = 15;
   let ra = br;
+  let Form = FRCR;
 }
 
 class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
-               TB<op, (outs), (ins calltarget:$target),
-                  !strconcat(instr_asm, "   r15, $target"),
+               TB<op, (outs), (ins GPR:$link, calltarget:$target),
+                  !strconcat(instr_asm, "   $link, $target"),
                   [], IIBranch> {
-  let rd = 15;
   let ra = br;
+  let Form = FRCI;
 }
 
 //===----------------------------------------------------------------------===//
@@ -274,6 +291,7 @@
                  !strconcat(instr_asm, "   $a, $b, $offset"),
                  [], IIBranch> {
   let rd = br;
+  let Form = FCRR;
 }
 
 class BranchCI<bits<6> op, bits<5> br, string instr_asm, PatFrag cond_op> :
@@ -281,6 +299,7 @@
                   !strconcat(instr_asm, "   $a, $offset"),
                   [], IIBranch> {
   let rd = br;
+  let Form = FCRI;
 }
 
 //===----------------------------------------------------------------------===//
@@ -295,6 +314,9 @@
   def AND    :  Logic<0x21, 0x000, "and    ", and>;
   def OR     :  Logic<0x20, 0x000, "or     ", or>;
   def XOR    :  Logic<0x22, 0x000, "xor    ", xor>;
+  def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
+  def PCMPEQ : PatCmp<0x23, 0x400, "pcmpeq ">;
+  def PCMPNE : PatCmp<0x22, 0x400, "pcmpne ">;
 }
 
 let isAsCheapAsAMove = 1 in {
@@ -364,7 +386,10 @@
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
   def LBU  :  LoadM<0x30, "lbu    ", zextloadi8>;
   def LHU  :  LoadM<0x31, "lhu    ", zextloadi16>;
-  def LW   :  LoadM<0x32, "lw     ", load>;
+
+  def LW   :  LoadW<0x32, 0x0, "lw     ">;
+  def LWR  :  LoadW<0x32, 0x2, "lwr    ">;
+  def LWX  :  LoadW<0x32, 0x4, "lwx    ">;
 
   def LBUI : LoadMI<0x38, "lbui   ", zextloadi8>;
   def LHUI : LoadMI<0x39, "lhui   ", zextloadi16>;
@@ -373,7 +398,10 @@
 
   def SB  :  StoreM<0x34, "sb     ", truncstorei8>;
   def SH  :  StoreM<0x35, "sh     ", truncstorei16>;
-  def SW  :  StoreM<0x36, "sw     ", store>;
+
+  def SW  :  StoreW<0x36, 0x0, "sw     ">;
+  def SWR :  StoreW<0x36, 0x2, "swr    ">;
+  def SWX :  StoreW<0x36, 0x4, "swx    ">;
 
   def SBI : StoreMI<0x3C, "sbi    ", truncstorei8>;
   def SHI : StoreMI<0x3D, "shi    ", truncstorei16>;
@@ -383,13 +411,12 @@
 // MBlaze branch instructions
 //===----------------------------------------------------------------------===//
 
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1, 
-    Form = FI in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
   def BRI    :  BranchI<0x2E, 0x00, "bri    ">;
   def BRAI   :  BranchI<0x2E, 0x08, "brai   ">;
 }
 
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, Form = FRI in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
   def BEQI   : BranchCI<0x2F, 0x00, "beqi   ", seteq>;
   def BNEI   : BranchCI<0x2F, 0x01, "bnei   ", setne>;
   def BLTI   : BranchCI<0x2F, 0x02, "blti   ", setlt>;
@@ -399,13 +426,12 @@
 }
 
 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
-    isBarrier = 1, Form = FR in {
+    isBarrier = 1 in {
   def BR     :   Branch<0x26, 0x00, 0x000, "br     ">;
   def BRA    :   Branch<0x26, 0x08, 0x000, "bra    ">;
 }
 
-let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
-    Form = FRR in {
+let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
   def BEQ    :  BranchC<0x27, 0x00, 0x000, "beq    ", seteq>;
   def BNE    :  BranchC<0x27, 0x01, 0x000, "bne    ", setne>;
   def BLT    :  BranchC<0x27, 0x02, 0x000, "blt    ", setlt>;
@@ -415,13 +441,12 @@
 }
 
 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
-    isBarrier = 1, Form = FI in {
+    isBarrier = 1 in {
   def BRID   :  BranchI<0x2E, 0x10, "brid   ">;
   def BRAID  :  BranchI<0x2E, 0x18, "braid  ">;
 }
 
-let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
-    Form = FRI in {
+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in {
   def BEQID  : BranchCI<0x2F, 0x10, "beqid  ", seteq>;
   def BNEID  : BranchCI<0x2F, 0x11, "bneid  ", setne>;
   def BLTID  : BranchCI<0x2F, 0x12, "bltid  ", setlt>;
@@ -430,14 +455,14 @@
   def BGEID  : BranchCI<0x2F, 0x15, "bgeid  ", setge>;
 }
 
-let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, Form = FR,
+let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
     hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in {
   def BRD    :   Branch<0x26, 0x10, 0x000, "brd    ">;
   def BRAD   :   Branch<0x26, 0x18, 0x000, "brad   ">;
 }
 
 let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
-    hasDelaySlot = 1, hasCtrlDep = 1, Form = FRR in {
+    hasDelaySlot = 1, hasCtrlDep = 1 in {
   def BEQD   :  BranchC<0x27, 0x10, 0x000, "beqd   ", seteq>;
   def BNED   :  BranchC<0x27, 0x11, 0x000, "bned   ", setne>;
   def BLTD   :  BranchC<0x27, 0x12, 0x000, "bltd   ", setlt>;
@@ -446,7 +471,7 @@
   def BGED   :  BranchC<0x27, 0x15, 0x000, "bged   ", setge>;
 }
 
-let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1, Form = FI,
+let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
     Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
     Uses = [R1,R5,R6,R7,R8,R9,R10] in {
   def BRLID  : BranchLI<0x2E, 0x14, "brlid  ">;
@@ -454,7 +479,7 @@
 }
 
 let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
-    isBarrier = 1, Form = FR,
+    isBarrier = 1,
     Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
     Uses = [R1,R5,R6,R7,R8,R9,R10] in {
   def BRLD   : BranchL<0x26, 0x14, 0x000, "brld   ">;
@@ -462,10 +487,34 @@
 }
 
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
-    hasCtrlDep=1, rd=0x10, imm16=0x8, Form=FR in {
-  def RTSD   : TB<0x2D, (outs), (ins GPR:$target),
-                  "rtsd      $target, 8",
-                  [(MBlazeRet GPR:$target)],
+    hasCtrlDep=1, rd=0x10, Form=FCRI in {
+  def RTSD   : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+                  "rtsd      $target, $imm",
+                  [], 
+                  IIBranch>;
+}
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
+    hasCtrlDep=1, rd=0x11, Form=FCRI in {
+  def RTID   : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+                  "rtsd      $target, $imm",
+                  [], 
+                  IIBranch>;
+}
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
+    hasCtrlDep=1, rd=0x12, Form=FCRI in {
+  def RTBD   : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+                  "rtsd      $target, $imm",
+                  [], 
+                  IIBranch>;
+}
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
+    hasCtrlDep=1, rd=0x14, Form=FCRI in {
+  def RTED   : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+                  "rtsd      $target, $imm",
+                  [], 
                   IIBranch>;
 }
 
@@ -474,7 +523,7 @@
 //===----------------------------------------------------------------------===//
 
 let neverHasSideEffects = 1 in {
-  def NOP :  MBlazeInst< 0x20, FRRR, (outs), (ins), "nop    ", [], IIAlu>;
+  def NOP :  MBlazeInst< 0x20, FC, (outs), (ins), "nop    ", [], IIAlu>;
 }
 
 let usesCustomInserter = 1 in {
@@ -520,6 +569,38 @@
 }
 
 //===----------------------------------------------------------------------===//
+// Misc. instructions
+//===----------------------------------------------------------------------===//
+def MFS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mfs", [], IIAlu> {
+}
+
+def MTS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mts", [], IIAlu> {
+}
+
+def MSRSET : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrset", [], IIAlu> {
+}
+
+def MSRCLR : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrclr", [], IIAlu> {
+}
+
+let rd=0x0, Form=FCRR in {
+  def WDC  : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), 
+                "wdc       $a, $b", [], IIAlu>;
+  def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b),
+                "wdc.flush $a, $b", [], IIAlu>;
+  def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b),
+                "wdc.clear $a, $b", [], IIAlu>;
+  def WIC  : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b),
+                "wic       $a, $b", [], IIAlu>;
+}
+
+def BRK  :  Branch<0x26, 0x0C, 0x000, "brk    ">;
+def BRKI : BranchI<0x2E, 0x0C, "brki   ">;
+
+def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), 
+                     "imm       $imm", [], IIAlu>;
+
+//===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
@@ -536,9 +617,14 @@
 def : Pat<(sext_inreg GPR:$src, i8),  (SEXT8 GPR:$src)>;
 
 // Call
-def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)), (BRLID tglobaladdr:$dst)>;
-def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),(BRLID texternalsym:$dst)>;
-def : Pat<(MBlazeJmpLink GPR:$dst), (BRLD GPR:$dst)>;
+def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)),
+          (BRLID (i32 R15), tglobaladdr:$dst)>;
+
+def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),
+          (BRLID (i32 R15), texternalsym:$dst)>;
+
+def : Pat<(MBlazeJmpLink GPR:$dst),
+          (BRLD (i32 R15), GPR:$dst)>;
 
 // Shift Instructions
 def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>;
@@ -613,6 +699,9 @@
                     (i32 GPR:$T), (i32 GPR:$F), SETULE),
           (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$L, GPR:$R), 6)>;
 
+// Ret instructions
+def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>;
+
 // BR instructions
 def : Pat<(br bb:$T), (BRID bb:$T)>;
 def : Pat<(brind GPR:$T), (BRD GPR:$T)>;
@@ -660,6 +749,10 @@
 def : Pat<(extloadi8  xaddr:$src), (i32 (LBU xaddr:$src))>;
 def : Pat<(extloadi16 xaddr:$src), (i32 (LHU xaddr:$src))>;
 
+// 32-bit load and store
+def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
+def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
+
 // Peepholes
 def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp Tue Oct 26 19:23:01 2010
@@ -14,7 +14,7 @@
 #include "MBlazeMCAsmInfo.h"
 using namespace llvm;
 
-MBlazeMCAsmInfo::MBlazeMCAsmInfo(const Target &T, StringRef TT) {
+MBlazeMCAsmInfo::MBlazeMCAsmInfo() {
   AlignmentIsInBytes          = false;
   Data16bitsDirective         = "\t.half\t";
   Data32bitsDirective         = "\t.word\t";

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h Tue Oct 26 19:23:01 2010
@@ -22,7 +22,7 @@
   
   class MBlazeMCAsmInfo : public MCAsmInfo {
   public:
-    explicit MBlazeMCAsmInfo(const Target &T, StringRef TT);
+    explicit MBlazeMCAsmInfo();
   };
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Tue Oct 26 19:23:01 2010
@@ -103,6 +103,8 @@
   }
 
   void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const;
+  void EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte, 
+               raw_ostream &OS) const;
 
   void EmitImmediate(const MCInst &MI,
                      unsigned opNo, MCFixupKind FixupKind,
@@ -153,6 +155,18 @@
 }
 
 void MBlazeMCCodeEmitter::
+EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte, 
+        raw_ostream &OS) const {
+    MCOperand mcop = MI.getOperand(op);
+    if (mcop.isExpr()) {
+        EmitByte(0x0D, CurByte, OS);
+        EmitByte(0x00, CurByte, OS);
+        EmitRawByte(0, CurByte, OS);
+        EmitRawByte(0, CurByte, OS);
+    }
+}
+
+void MBlazeMCCodeEmitter::
 EmitImmediate(const MCInst &MI, unsigned opNo, MCFixupKind FixupKind,
               unsigned &CurByte, raw_ostream &OS,
               SmallVectorImpl<MCFixup> &Fixups) const {
@@ -166,6 +180,8 @@
   }
 }
 
+
+
 void MBlazeMCCodeEmitter::
 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups) const {
@@ -177,24 +193,28 @@
 
   switch ((TSFlags & MBlazeII::FormMask)) {
   default: break;
-  case MBlazeII::Pseudo:
+  case MBlazeII::FPseudo:
     // Pseudo instructions don't get encoded.
     return;
 
-  case MBlazeII::RegRegImm:
+  case MBlazeII::FRRI:
     EmitImmediate( MI, 2, FK_Data_4, CurByte, OS, Fixups );
     break;
 
-  case MBlazeII::RegImmReg:
+  case MBlazeII::FRIR:
     EmitImmediate( MI, 1, FK_Data_4, CurByte, OS, Fixups );
     break;
 
-  case MBlazeII::RegImm:
+  case MBlazeII::FCRI:
     EmitImmediate( MI, 1, MCFixupKind(MBlaze::reloc_pcrel_2byte), CurByte, OS,
                    Fixups );
     break;
 
-  case MBlazeII::Imm:
+  case MBlazeII::FRCI:
+    EmitImmediate( MI, 1, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS,
+                   Fixups );
+
+  case MBlazeII::FCCI:
     EmitImmediate( MI, 0, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS,
                    Fixups );
     break;
@@ -207,19 +227,17 @@
     EmitConstant(Value, 4, CurByte, OS);
     break;
 
+  case MBlaze::BRLID:
+  case MBlaze::BRALID:
+    EmitIMM(MI,1,CurByte,OS);
+    EmitConstant(Value, 4, CurByte, OS);
+    break;
+
   case MBlaze::BRI:
   case MBlaze::BRAI:
   case MBlaze::BRID:
   case MBlaze::BRAID:
-  case MBlaze::BRLID:
-  case MBlaze::BRALID:
-    MCOperand op = MI.getOperand(0);
-    if (op.isExpr()) {
-        EmitByte(0x0D, CurByte, OS);
-        EmitByte(0x00, CurByte, OS);
-        EmitRawByte(0, CurByte, OS);
-        EmitRawByte(0, CurByte, OS);
-    }
+    EmitIMM(MI,0,CurByte,OS);
     EmitConstant(Value, 4, CurByte, OS);
     break;
   }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Tue Oct 26 19:23:01 2010
@@ -21,6 +21,14 @@
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
+static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
+  Triple TheTriple(TT);
+  switch (TheTriple.getOS()) {
+  default:
+    return new MBlazeMCAsmInfo();
+  }
+}
+
 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
                                     MCContext &Ctx, TargetAsmBackend &TAB,
                                     raw_ostream &_OS,
@@ -46,7 +54,9 @@
 extern "C" void LLVMInitializeMBlazeTarget() {
   // Register the target.
   RegisterTargetMachine<MBlazeTargetMachine> X(TheMBlazeTarget);
-  RegisterAsmInfo<MBlazeMCAsmInfo> A(TheMBlazeTarget);
+
+  // Register the target asm info.
+  RegisterAsmInfoFn A(TheMBlazeTarget, createMCAsmInfo);
 
   // Register the MC code emitter
   TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget,

Modified: llvm/trunk/lib/Target/MBlaze/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Makefile?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Makefile (original)
+++ llvm/trunk/lib/Target/MBlaze/Makefile Tue Oct 26 19:23:01 2010
@@ -16,9 +16,10 @@
                 MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
                 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
 		MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
-                MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc
+                MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+		MBlazeGenEDInfo.inc
 
-DIRS = InstPrinter AsmParser TargetInfo
+DIRS = InstPrinter AsmParser Disassembler TargetInfo
 
 include $(LEVEL)/Makefile.common
 

Modified: llvm/trunk/lib/Target/MBlaze/TODO
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/TODO?rev=117420&r1=117419&r2=117420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/TODO (original)
+++ llvm/trunk/lib/Target/MBlaze/TODO Tue Oct 26 19:23:01 2010
@@ -30,3 +30,5 @@
       slots but I'm not sure that is necessary.
     - The processor itineraries are copied from a different backend
       and need to be updated to model the MicroBlaze correctly.
+    - Look at the MBlazeGenFastISel.inc stuff and make use of it
+      if appropriate.



From stoklund at 2pi.dk  Tue Oct 26 19:39:35 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 26 Oct 2010 17:39:35 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h	include/llvm/CodeGen/Passes.h
	lib/CodeGen/CMakeLists.txt	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <EDB55FD0-3D52-42E8-ABC9-C454B12A2B03@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
	<403ED248-AFB7-43C1-865E-F465686B09BD@apple.com>
	<DAB3F4F4-42CB-4978-AE22-6DD29AC8F65B@2pi.dk>
	<F79E0D5E-2C2D-47E9-8F42-9C47CF6330E3@apple.com>
	<3A50637E-8C3D-47AD-AD5B-41128CFA01DD@2pi.dk>
	<EDB55FD0-3D52-42E8-ABC9-C454B12A2B03@apple.com>
Message-ID: <B8AB2821-DEA4-44FE-98F0-C66544C6C475@2pi.dk>


On Oct 26, 2010, at 5:22 PM, Evan Cheng wrote:

> 
> On Oct 26, 2010, at 3:59 PM, Jakob Stoklund Olesen wrote:
>>> No particular reason. LiveStacks is a bit of a hack, I just think we should work towards removing the hack. Not having the allocator updating it is a good start.
>> 
>> What do you have in mind? It seems like an OK design to me.
> 
> 1) LiveStacks is only used to track live time of spill slots. We would want to track non-spill ones as well.

Good point. But we probably need to have llvm.lifetime.{start,end} up and running before that is going anywhere.

> 2) It's using LiveIntervals. Doesn't it seem a bit heavy weight?

Yes, that is true. Currently, all VNInfo's are coalesced into one, but we are still storing a bunch of pointers to that one.




From grosbach at apple.com  Tue Oct 26 19:38:16 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 00:38:16 -0000
Subject: [llvm-commits] [llvm] r117421 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Message-ID: <20101027003816.A22C32A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 19:38:16 2010
New Revision: 117421

URL: http://llvm.org/viewvc/llvm-project?rev=117421&view=rev
Log:
One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=117421&r1=117420&r2=117421&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Oct 26 19:38:16 2010
@@ -860,7 +860,9 @@
                           ARMCC::CondCodes Pred, unsigned PredReg,
                           const TargetInstrInfo *TII, bool isT2) {
   int Offset = OffImm;
-  if (!isT2) {
+  // FIXME: This fancy offset encoding stuff goes away when we're done
+  // removing addrmode2.
+  if (!isT2 && !isDef) {
     if (OffImm < 0)
       Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
     else
@@ -871,8 +873,6 @@
                                       TII->get(NewOpc))
       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
-    if (!isT2)
-      MIB.addReg(OffReg,  getKillRegState(OffKill)|getUndefRegState(OffUndef));
     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
   } else {
     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),



From stoklund at 2pi.dk  Tue Oct 26 19:39:01 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 27 Oct 2010 00:39:01 -0000
Subject: [llvm-commits] [llvm] r117422 -
	/llvm/trunk/lib/CodeGen/MachineVerifier.cpp
Message-ID: <20101027003902.0525F2A6C12C@llvm.org>

Author: stoklund
Date: Tue Oct 26 19:39:01 2010
New Revision: 117422

URL: http://llvm.org/viewvc/llvm-project?rev=117422&view=rev
Log:
Physical registers trivially have multiple connected components all the time.
Only virtuals should be requires to be connected.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117422&r1=117421&r2=117422&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Oct 26 19:39:01 2010
@@ -1069,11 +1069,13 @@
     }
 
     // Check the LI only has one connected component.
-    ConnectedVNInfoEqClasses ConEQ(*LiveInts);
-    unsigned NumComp = ConEQ.Classify(&LI);
-    if (NumComp > 1) {
-      report("Multiple connected components in live interval", MF);
-      *OS << NumComp << " components in " << LI << '\n';
+    if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
+      ConnectedVNInfoEqClasses ConEQ(*LiveInts);
+      unsigned NumComp = ConEQ.Classify(&LI);
+      if (NumComp > 1) {
+        report("Multiple connected components in live interval", MF);
+        *OS << NumComp << " components in " << LI << '\n';
+      }
     }
   }
 }



From stoklund at 2pi.dk  Tue Oct 26 19:39:05 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 27 Oct 2010 00:39:05 -0000
Subject: [llvm-commits] [llvm] r117423 - in /llvm/trunk/lib/CodeGen:
	SplitKit.cpp SplitKit.h
Message-ID: <20101027003905.637512A6C12D@llvm.org>

Author: stoklund
Date: Tue Oct 26 19:39:05 2010
New Revision: 117423

URL: http://llvm.org/viewvc/llvm-project?rev=117423&view=rev
Log:
Compute critical loop predecessors in the same way as critical loop exits.

Critical edges going into a loop are not as bad as critical exits. We can handle
them by splitting the critical edge, or by having both inside and outside
registers live out of the predecessor.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117423&r1=117422&r2=117423&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Oct 26 19:39:05 2010
@@ -155,7 +155,7 @@
                                      BlockPtrSet &CriticalExits) {
   CriticalExits.clear();
 
-  // A critical exit block has curli line-in, and has a predecessor that is not
+  // A critical exit block has curli live-in, and has a predecessor that is not
   // in the loop nor a loop predecessor. For such an exit block, the edges
   // carrying the new variable must be moved to a new pre-exit block.
   for (BlockPtrSet::iterator I = Blocks.Exits.begin(), E = Blocks.Exits.end();
@@ -181,6 +181,38 @@
   }
 }
 
+void SplitAnalysis::getCriticalPreds(const SplitAnalysis::LoopBlocks &Blocks,
+                                     BlockPtrSet &CriticalPreds) {
+  CriticalPreds.clear();
+
+  // A critical predecessor block has curli live-out, and has a successor that
+  // has curli live-in and is not in the loop nor a loop exit block. For such a
+  // predecessor block, we must carry the value in both the 'inside' and
+  // 'outside' registers.
+  for (BlockPtrSet::iterator I = Blocks.Preds.begin(), E = Blocks.Preds.end();
+       I != E; ++I) {
+    const MachineBasicBlock *Pred = *I;
+    // Definitely not a critical edge.
+    if (Pred->succ_size() == 1)
+      continue;
+    // This block may not have curli live out at all if there is a PHI.
+    if (!lis_.isLiveOutOfMBB(*curli_, Pred))
+      continue;
+    // Does this block have a successor outside the loop?
+    for (MachineBasicBlock::const_pred_iterator SI = Pred->succ_begin(),
+         SE = Pred->succ_end(); SI != SE; ++SI) {
+      const MachineBasicBlock *Succ = *SI;
+      if (Blocks.Loop.count(Succ) || Blocks.Exits.count(Succ))
+        continue;
+      if (!lis_.isLiveInToMBB(*curli_, Succ))
+        continue;
+      // This is a critical predecessor block.
+      CriticalPreds.insert(Pred);
+      break;
+    }
+  }
+}
+
 /// canSplitCriticalExits - Return true if it is possible to insert new exit
 /// blocks before the blocks in CriticalExits.
 bool

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=117423&r1=117422&r2=117423&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Oct 26 19:39:05 2010
@@ -122,6 +122,11 @@
   bool canSplitCriticalExits(const LoopBlocks &Blocks,
                              BlockPtrSet &CriticalExits);
 
+  /// getCriticalPreds - Get the set of loop predecessors with critical edges to
+  /// blocks outside the loop that have curli live in. We don't have to break
+  /// these edges, but they do require special treatment.
+  void getCriticalPreds(const LoopBlocks &Blocks, BlockPtrSet &CriticalPreds);
+
   /// getBestSplitLoop - Return the loop where curli may best be split to a
   /// separate register, or NULL.
   const MachineLoop *getBestSplitLoop();



From stoklund at 2pi.dk  Tue Oct 26 19:39:07 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 27 Oct 2010 00:39:07 -0000
Subject: [llvm-commits] [llvm] r117424 - in /llvm/trunk/lib/CodeGen:
	SplitKit.cpp SplitKit.h
Message-ID: <20101027003907.7F03F2A6C12E@llvm.org>

Author: stoklund
Date: Tue Oct 26 19:39:07 2010
New Revision: 117424

URL: http://llvm.org/viewvc/llvm-project?rev=117424&view=rev
Log:
Handle critical loop predecessors by making both inside and outside registers
live out.

This doesn't prevent us from inserting a loop preheader later on, if that is
better.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117424&r1=117423&r2=117424&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Oct 26 19:39:07 2010
@@ -512,7 +512,7 @@
 // extendTo - Find the last li_ value defined in MBB at or before Idx. The
 // parentli_ is assumed to be live at Idx. Extend the live range to Idx.
 // Return the found VNInfo, or NULL.
-VNInfo *LiveIntervalMap::extendTo(MachineBasicBlock *MBB, SlotIndex Idx) {
+VNInfo *LiveIntervalMap::extendTo(const MachineBasicBlock *MBB, SlotIndex Idx) {
   assert(li_ && "call reset first");
   LiveInterval::iterator I = std::upper_bound(li_->begin(), li_->end(), Idx);
   if (I == li_->begin())
@@ -861,6 +861,16 @@
       dupli_.addSimpleRange(LR.start, LR.end, LR.valno);
     }
   }
+
+  // Extend dupli_ to be live out of any critical loop predecessors.
+  // This means we have multiple registers live out of those blocks.
+  // The alternative would be to split the critical edges.
+  if (criticalPreds_.empty())
+    return;
+  for (SplitAnalysis::BlockPtrSet::iterator I = criticalPreds_.begin(),
+       E = criticalPreds_.end(); I != E; ++I)
+     dupli_.extendTo(*I, lis_.getMBBEndIdx(*I).getPrevSlot());
+   criticalPreds_.clear();
 }
 
 void SplitEditor::finish() {
@@ -924,6 +934,9 @@
   sa_.getCriticalExits(Blocks, CriticalExits);
   assert(CriticalExits.empty() && "Cannot break critical exits yet");
 
+  // Get critical predecessors so computeRemainder can deal with them.
+  sa_.getCriticalPreds(Blocks, criticalPreds_);
+
   // Create new live interval for the loop.
   openIntv();
 

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=117424&r1=117423&r2=117424&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Oct 26 19:39:07 2010
@@ -200,7 +200,7 @@
   // extendTo - Find the last li_ value defined in MBB at or before Idx. The
   // parentli is assumed to be live at Idx. Extend the live range to include
   // Idx. Return the found VNInfo, or NULL.
-  VNInfo *extendTo(MachineBasicBlock *MBB, SlotIndex Idx);
+  VNInfo *extendTo(const MachineBasicBlock *MBB, SlotIndex Idx);
 
   /// isMapped - Return true is ParentVNI is a known mapped value. It may be a
   /// simple 1-1 mapping or a complex mapping to later defs.
@@ -271,6 +271,10 @@
   /// truncating any overlap with intervals_.
   void addTruncSimpleRange(SlotIndex Start, SlotIndex End, VNInfo *VNI);
 
+  /// criticalPreds_ - Set of basic blocks where both dupli and openli should be
+  /// live out because of a critical edge.
+  SplitAnalysis::BlockPtrSet criticalPreds_;
+
   /// computeRemainder - Compute the dupli liveness as the complement of all the
   /// new intervals.
   void computeRemainder();



From enderby at apple.com  Tue Oct 26 19:59:28 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 27 Oct 2010 00:59:28 -0000
Subject: [llvm-commits] [llvm] r117427 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/X86/x86-32.s
Message-ID: <20101027005928.581E52A6C12C@llvm.org>

Author: enderby
Date: Tue Oct 26 19:59:28 2010
New Revision: 117427

URL: http://llvm.org/viewvc/llvm-project?rev=117427&view=rev
Log:
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/X86/x86-32.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117427&r1=117426&r2=117427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Oct 26 19:59:28 2010
@@ -703,6 +703,8 @@
     .Case("fwait", "wait")
     .Case("movzx", "movzb")  // FIXME: Not correct.
     .Case("fildq", "fildll")
+    .Case("fcompi", "fcomip")
+    .Case("fucompi", "fucomip")
     .Default(Name);
 
   // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
@@ -991,9 +993,20 @@
                                              NameLoc, NameLoc));
   }
 
+  // The assembler accepts this instruction with no operand as a synonym for an
+  // instruction taking %st(1),%st(0). e.g. "fcompi" -> "fcompi %st(1),st(0)".
+  if (Name == "fcompi" && Operands.size() == 1) {
+    Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+                                             NameLoc, NameLoc));
+    Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
+                                             NameLoc, NameLoc));
+  }
+
   // The assembler accepts these instructions with two few operands as a synonym
   // for taking %st(1),%st(0) or X, %st(0).
-  if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
+  if ((Name == "fcomi" || Name == "fucomi" || Name == "fucompi" ||
+       Name == "fcompi" ) &&
+      Operands.size() < 3) {
     if (Operands.size() == 1)
       Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
                                                NameLoc, NameLoc));

Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=117427&r1=117426&r2=117427&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Tue Oct 26 19:59:28 2010
@@ -702,3 +702,27 @@
 // CHECK: sidt	4(%eax)
 // CHECK:  encoding: [0x0f,0x01,0x48,0x04]
         	sidtl	4(%eax)
+
+// CHECK: fcomip	%st(2), %st(0)
+// CHECK:  encoding: [0xdf,0xf2]
+        	fcompi	%st(2),%st
+
+// CHECK: fcomip	%st(2), %st(0)
+// CHECK:  encoding: [0xdf,0xf2]
+        	fcompi	%st(2)
+
+// CHECK: fcomip	%st(1), %st(0)
+// CHECK:  encoding: [0xdf,0xf1]
+        	fcompi
+
+// CHECK: fucomip	%st(2), %st(0)
+// CHECK:  encoding: [0xdf,0xea]
+        	fucompi	%st(2),%st
+
+// CHECK: fucomip	%st(2), %st(0)
+// CHECK:  encoding: [0xdf,0xea]
+        	fucompi	%st(2)
+
+// CHECK: fucomip	%st(1), %st(0)
+// CHECK:  encoding: [0xdf,0xe9]
+        	fucompi



From isanbard at gmail.com  Tue Oct 26 20:07:41 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 27 Oct 2010 01:07:41 -0000
Subject: [llvm-commits] [llvm] r117428 - /llvm/trunk/docs/LangRef.html
Message-ID: <20101027010741.BC9BD2A6C12C@llvm.org>

Author: void
Date: Tue Oct 26 20:07:41 2010
New Revision: 117428

URL: http://llvm.org/viewvc/llvm-project?rev=117428&view=rev
Log:
Random cleanups and format changes.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=117428&r1=117427&r2=117428&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Tue Oct 26 20:07:41 2010
@@ -2162,8 +2162,8 @@
 
 <p>The string '<tt>undef</tt>' can be used anywhere a constant is expected, and
    indicates that the user of the value may receive an unspecified bit-pattern.
-   Undefined values may be of any type (other than label or void) and be used
-   anywhere a constant is permitted.</p>
+   Undefined values may be of any type (other than '<tt>label</tt>'
+   or '<tt>void</tt>') and be used anywhere a constant is permitted.</p>
 
 <p>Undefined values are useful because they indicate to the compiler that the
    program is well defined no matter what value is used.  This gives the
@@ -2182,7 +2182,7 @@
 </pre>
 
 <p>This is safe because all of the output bits are affected by the undef bits.
-Any output bit can have a zero or one depending on the input bits.</p>
+   Any output bit can have a zero or one depending on the input bits.</p>
 
 <pre class="doc_code">
   %A = or %X, undef
@@ -2196,13 +2196,14 @@
 </pre>
 
 <p>These logical operations have bits that are not always affected by the input.
-For example, if "%X" has a zero bit, then the output of the 'and' operation will
-always be a zero, no matter what the corresponding bit from the undef is.  As
-such, it is unsafe to optimize or assume that the result of the and is undef.
-However, it is safe to assume that all bits of the undef could be 0, and
-optimize the and to 0.  Likewise, it is safe to assume that all the bits of
-the undef operand to the or could be set, allowing the or to be folded to
--1.</p>
+   For example, if <tt>%X</tt> has a zero bit, then the output of the
+   '<tt>and</tt>' operation will always be a zero for that bit, no matter what
+   the corresponding bit from the '<tt>undef</tt>' is. As such, it is unsafe to
+   optimize or assume that the result of the '<tt>and</tt>' is '<tt>undef</tt>'.
+   However, it is safe to assume that all bits of the '<tt>undef</tt>' could be
+   0, and optimize the '<tt>and</tt>' to 0. Likewise, it is safe to assume that
+   all the bits of the '<tt>undef</tt>' operand to the '<tt>or</tt>' could be
+   set, allowing the '<tt>or</tt>' to be folded to -1.</p>
 
 <pre class="doc_code">
   %A = select undef, %X, %Y
@@ -2218,13 +2219,14 @@
   %C = undef
 </pre>
 
-<p>This set of examples show that undefined select (and conditional branch)
-conditions can go "either way" but they have to come from one of the two
-operands.  In the %A example, if %X and %Y were both known to have a clear low
-bit, then %A would have to have a cleared low bit.  However, in the %C example,
-the optimizer is allowed to assume that the undef operand could be the same as
-%Y, allowing the whole select to be eliminated.</p>
-
+<p>This set of examples shows that undefined '<tt>select</tt>' (and conditional
+   branch) conditions can go <em>either way</em>, but they have to come from one
+   of the two operands.  In the <tt>%A</tt> example, if <tt>%X</tt> and
+   <tt>%Y</tt> were both known to have a clear low bit, then <tt>%A</tt> would
+   have to have a cleared low bit. However, in the <tt>%C</tt> example, the
+   optimizer is allowed to assume that the '<tt>undef</tt>' operand could be the
+   same as <tt>%Y</tt>, allowing the whole '<tt>select</tt>' to be
+   eliminated.</p>
 
 <pre class="doc_code">
   %A = xor undef, undef
@@ -2245,16 +2247,17 @@
   %F = undef
 </pre>
 
-<p>This example points out that two undef operands are not necessarily the same.
-This can be surprising to people (and also matches C semantics) where they
-assume that "X^X" is always zero, even if X is undef.  This isn't true for a
-number of reasons, but the short answer is that an undef "variable" can
-arbitrarily change its value over its "live range".  This is true because the
-"variable" doesn't actually <em>have a live range</em>.  Instead, the value is
-logically read from arbitrary registers that happen to be around when needed,
-so the value is not necessarily consistent over time.  In fact, %A and %C need
-to have the same semantics or the core LLVM "replace all uses with" concept
-would not hold.</p>
+<p>This example points out that two '<tt>undef</tt>' operands are not
+   necessarily the same. This can be surprising to people (and also matches C
+   semantics) where they assume that "<tt>X^X</tt>" is always zero, even
+   if <tt>X</tt> is undefined. This isn't true for a number of reasons, but the
+   short answer is that an '<tt>undef</tt>' "variable" can arbitrarily change
+   its value over its "live range".  This is true because the variable doesn't
+   actually <em>have a live range</em>. Instead, the value is logically read
+   from arbitrary registers that happen to be around when needed, so the value
+   is not necessarily consistent over time. In fact, <tt>%A</tt> and <tt>%C</tt>
+   need to have the same semantics or the core LLVM "replace all uses with"
+   concept would not hold.</p>
 
 <pre class="doc_code">
   %A = fdiv undef, %X
@@ -2265,17 +2268,17 @@
 </pre>
 
 <p>These examples show the crucial difference between an <em>undefined
-value</em> and <em>undefined behavior</em>.  An undefined value (like undef) is
-allowed to have an arbitrary bit-pattern.  This means that the %A operation
-can be constant folded to undef because the undef could be an SNaN, and fdiv is
-not (currently) defined on SNaN's.  However, in the second example, we can make
-a more aggressive assumption: because the undef is allowed to be an arbitrary
-value, we are allowed to assume that it could be zero.  Since a divide by zero
-has <em>undefined behavior</em>, we are allowed to assume that the operation
-does not execute at all.  This allows us to delete the divide and all code after
-it: since the undefined operation "can't happen", the optimizer can assume that
-it occurs in dead code.
-</p>
+  value</em> and <em>undefined behavior</em>. An undefined value (like
+  '<tt>undef</tt>') is allowed to have an arbitrary bit-pattern. This means that
+  the <tt>%A</tt> operation can be constant folded to '<tt>undef</tt>', because
+  the '<tt>undef</tt>' could be an SNaN, and <tt>fdiv</tt> is not (currently)
+  defined on SNaN's. However, in the second example, we can make a more
+  aggressive assumption: because the <tt>undef</tt> is allowed to be an
+  arbitrary value, we are allowed to assume that it could be zero. Since a
+  divide by zero has <em>undefined behavior</em>, we are allowed to assume that
+  the operation does not execute at all. This allows us to delete the divide and
+  all code after it. Because the undefined operation "can't happen", the
+  optimizer can assume that it occurs in dead code.</p>
 
 <pre class="doc_code">
 a:  store undef -> %X
@@ -2285,11 +2288,11 @@
 b: unreachable
 </pre>
 
-<p>These examples reiterate the fdiv example: a store "of" an undefined value
-can be assumed to not have any effect: we can assume that the value is
-overwritten with bits that happen to match what was already there.  However, a
-store "to" an undefined location could clobber arbitrary memory, therefore, it
-has undefined behavior.</p>
+<p>These examples reiterate the <tt>fdiv</tt> example: a store <em>of</em> an
+   undefined value can be assumed to not have any effect; we can assume that the
+   value is overwritten with bits that happen to match what was already there.
+   However, a store <em>to</em> an undefined location could clobber arbitrary
+   memory, therefore, it has undefined behavior.</p>
 
 </div>
 
@@ -2410,18 +2413,17 @@
    the address of the entry block is illegal.</p>
 
 <p>This value only has defined behavior when used as an operand to the
-   '<a href="#i_indirectbr"><tt>indirectbr</tt></a>' instruction or for comparisons
-   against null.  Pointer equality tests between labels addresses is undefined
-   behavior - though, again, comparison against null is ok, and no label is
-   equal to the null pointer.  This may also be passed around as an opaque
-   pointer sized value as long as the bits are not inspected.  This allows
-   <tt>ptrtoint</tt> and arithmetic to be performed on these values so long as
-   the original value is reconstituted before the <tt>indirectbr</tt>.</p>
-
-<p>Finally, some targets may provide defined semantics when
-   using the value as the operand to an inline assembly, but that is target
-   specific.
-   </p>
+   '<a href="#i_indirectbr"><tt>indirectbr</tt></a>' instruction, or for
+   comparisons against null. Pointer equality tests between labels addresses
+   results in undefined behavior &mdash; though, again, comparison against null
+   is ok, and no label is equal to the null pointer. This may be passed around
+   as an opaque pointer sized value as long as the bits are not inspected. This
+   allows <tt>ptrtoint</tt> and arithmetic to be performed on these values so
+   long as the original value is reconstituted before the <tt>indirectbr</tt>
+   instruction.</p>
+
+<p>Finally, some targets may provide defined semantics when using the value as
+   the operand to an inline assembly, but that is target specific.</p>
 
 </div>
 
@@ -2436,7 +2438,7 @@
    to be used as constants.  Constant expressions may be of
    any <a href="#t_firstclass">first class</a> type and may involve any LLVM
    operation that does not have side effects (e.g. load and call are not
-   supported).  The following is the syntax for constant expressions:</p>
+   supported). The following is the syntax for constant expressions:</p>
 
 <dl>
   <dt><b><tt>trunc (CST to TYPE)</tt></b></dt>
@@ -7674,7 +7676,7 @@
    the <tt>AllocaInst</tt> stack slot to be before local variables on the
    stack. This is to ensure that if a local variable on the stack is
    overwritten, it will destroy the value of the guard. When the function exits,
-   the guard on the stack is checked against the original guard. If they're
+   the guard on the stack is checked against the original guard. If they are
    different, then the program aborts by calling the <tt>__stack_chk_fail()</tt>
    function.</p>
 
@@ -7694,25 +7696,24 @@
 </pre>
 
 <h5>Overview:</h5>
-<p>The <tt>llvm.objectsize</tt> intrinsic is designed to provide information
-   to the optimizers to discover at compile time either a) when an
-   operation like memcpy will either overflow a buffer that corresponds to
-   an object, or b) to determine that a runtime check for overflow isn't
-   necessary. An object in this context means an allocation of a
-   specific class, structure, array, or other object.</p>
+<p>The <tt>llvm.objectsize</tt> intrinsic is designed to provide information to
+   the optimizers to determine at compile time whether a) an operation (like
+   memcpy) will overflow a buffer that corresponds to an object, or b) that a
+   runtime check for overflow isn't necessary. An object in this context means
+   an allocation of a specific class, structure, array, or other object.</p>
 
 <h5>Arguments:</h5>
-<p>The <tt>llvm.objectsize</tt> intrinsic takes two arguments.  The first
+<p>The <tt>llvm.objectsize</tt> intrinsic takes two arguments. The first
    argument is a pointer to or into the <tt>object</tt>. The second argument
-   is a boolean 0 or 1.  This argument determines whether you want the 
-   maximum (0) or minimum (1) bytes remaining.  This needs to be a literal 0 or
+   is a boolean 0 or 1. This argument determines whether you want the 
+   maximum (0) or minimum (1) bytes remaining. This needs to be a literal 0 or
    1, variables are not allowed.</p>
    
 <h5>Semantics:</h5>
 <p>The <tt>llvm.objectsize</tt> intrinsic is lowered to either a constant
-   representing the size of the object concerned or <tt>i32/i64 -1 or 0</tt>
-   (depending on the <tt>type</tt> argument if the size cannot be determined
-   at compile time.</p>
+   representing the size of the object concerned, or <tt>i32/i64 -1 or 0</tt>,
+   depending on the <tt>type</tt> argument, if the size cannot be determined at
+   compile time.</p>
 
 </div>
 



From grosbach at apple.com  Tue Oct 26 20:19:41 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 01:19:41 -0000
Subject: [llvm-commits] [llvm] r117429 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp InstPrinter/ARMInstPrinter.cpp
Message-ID: <20101027011941.B12DE2A6C12C@llvm.org>

Author: grosbach
Date: Tue Oct 26 20:19:41 2010
New Revision: 117429

URL: http://llvm.org/viewvc/llvm-project?rev=117429&view=rev
Log:
LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117429&r1=117428&r2=117429&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Oct 26 20:19:41 2010
@@ -1419,8 +1419,15 @@
       if ((unsigned)Offset <= Mask * Scale) {
         // Replace the FrameIndex with sp
         MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
-        if (isSub)
-          ImmedOffset |= 1 << NumBits;
+        // FIXME: When addrmode2 goes away, this will simplify (like the
+        // T2 version), as the LDR.i12 versions don't need the encoding
+        // tricks for the offset value.
+        if (isSub) {
+          if (AddrMode == ARMII::AddrMode_i12)
+            ImmedOffset = -ImmedOffset;
+          else
+            ImmedOffset |= 1 << NumBits;
+        }
         ImmOp.ChangeToImmediate(ImmedOffset);
         Offset = 0;
         return true;

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=117429&r1=117428&r2=117429&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Oct 26 20:19:41 2010
@@ -612,8 +612,11 @@
 
   O << "[" << getRegisterName(MO1.getReg());
 
-  unsigned OffImm = MO2.getImm();
-  if (OffImm)  // Don't print +0.
+  int32_t OffImm = (int32_t)MO2.getImm();
+  // Don't print +0.
+  if (OffImm < 0)
+    O << ", #-" << -OffImm;
+  else if (OffImm > 0)
     O << ", #" << OffImm;
   O << "]";
 }



From enderby at apple.com  Tue Oct 26 21:32:19 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 27 Oct 2010 02:32:19 -0000
Subject: [llvm-commits] [llvm] r117433 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/X86/x86-32.s
Message-ID: <20101027023219.C2F202A6C12C@llvm.org>

Author: enderby
Date: Tue Oct 26 21:32:19 2010
New Revision: 117433

URL: http://llvm.org/viewvc/llvm-project?rev=117433&view=rev
Log:
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/X86/x86-32.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117433&r1=117432&r2=117433&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Oct 26 21:32:19 2010
@@ -705,6 +705,12 @@
     .Case("fildq", "fildll")
     .Case("fcompi", "fcomip")
     .Case("fucompi", "fucomip")
+    .Case("fldcww", "fldcw")
+    .Case("fnstcww", "fnstcw")
+    .Case("fstcww", "fstcw")
+    .Case("fnstsww", "fnstsw")
+    .Case("fstsww", "fstsw")
+    .Case("verrw", "verr")
     .Default(Name);
 
   // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.

Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=117433&r1=117432&r2=117433&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Tue Oct 26 21:32:19 2010
@@ -726,3 +726,51 @@
 // CHECK: fucomip	%st(1), %st(0)
 // CHECK:  encoding: [0xdf,0xe9]
         	fucompi
+
+// CHECK: fldcw	32493
+// CHECK:  encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
+        	fldcww	0x7eed
+
+// CHECK: fldcw	32493
+// CHECK:  encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
+        	fldcw	0x7eed
+
+// CHECK: fnstcw	32493
+// CHECK:  encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
+        	fnstcww	0x7eed
+
+// CHECK: fnstcw	32493
+// CHECK:  encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
+        	fnstcw	0x7eed
+
+// CHECK: wait
+// CHECK:  encoding: [0x9b]
+        	fstcww	0x7eed
+
+// CHECK: wait
+// CHECK:  encoding: [0x9b]
+        	fstcw	0x7eed
+
+// CHECK: fnstsw	32493
+// CHECK:  encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
+        	fnstsww	0x7eed
+
+// CHECK: fnstsw	32493
+// CHECK:  encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
+        	fnstsw	0x7eed
+
+// CHECK: wait
+// CHECK:  encoding: [0x9b]
+        	fstsww	0x7eed
+
+// CHECK: wait
+// CHECK:  encoding: [0x9b]
+        	fstsw	0x7eed
+
+// CHECK: verr	32493
+// CHECK:  encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
+        	verrw	0x7eed
+
+// CHECK: verr	32493
+// CHECK:  encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
+        	verr	0x7eed



From enderby at apple.com  Tue Oct 26 21:53:04 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 27 Oct 2010 02:53:04 -0000
Subject: [llvm-commits] [llvm] r117434 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/X86/x86-32.s
Message-ID: <20101027025304.6F4202A6C12C@llvm.org>

Author: enderby
Date: Tue Oct 26 21:53:04 2010
New Revision: 117434

URL: http://llvm.org/viewvc/llvm-project?rev=117434&view=rev
Log:
Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/X86/x86-32.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117434&r1=117433&r2=117434&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Oct 26 21:53:04 2010
@@ -1196,7 +1196,7 @@
   // FIXME: This should be replaced with a real .td file alias mechanism.
   if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
       Op->getToken() == "finit" || Op->getToken() == "fsave" ||
-      Op->getToken() == "fstenv") {
+      Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
     MCInst Inst;
     Inst.setOpcode(X86::WAIT);
     Out.EmitInstruction(Inst);
@@ -1208,6 +1208,7 @@
         .Case("fstcw", "fnstcw")
         .Case("fstenv", "fnstenv")
         .Case("fstsw", "fnstsw")
+        .Case("fclex", "fnclex")
         .Default(0);
     assert(Repl && "Unknown wait-prefixed instruction");
     delete Operands[0];

Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=117434&r1=117433&r2=117434&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Tue Oct 26 21:53:04 2010
@@ -774,3 +774,11 @@
 // CHECK: verr	32493
 // CHECK:  encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
         	verr	0x7eed
+
+// CHECK: wait
+// CHECK:  encoding: [0x9b]
+        	fclex
+
+// CHECK: fnclex
+// CHECK:  encoding: [0xdb,0xe2]
+        	fnclex



From enderby at apple.com  Tue Oct 26 22:01:02 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 27 Oct 2010 03:01:02 -0000
Subject: [llvm-commits] [llvm] r117435 - in /llvm/trunk:
 lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/X86/x86-32.s
Message-ID: <20101027030102.D73D32A6C12C@llvm.org>

Author: enderby
Date: Tue Oct 26 22:01:02 2010
New Revision: 117435

URL: http://llvm.org/viewvc/llvm-project?rev=117435&view=rev
Log:
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).

Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/X86/x86-32.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117435&r1=117434&r2=117435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Oct 26 22:01:02 2010
@@ -711,6 +711,7 @@
     .Case("fnstsww", "fnstsw")
     .Case("fstsww", "fstsw")
     .Case("verrw", "verr")
+    .Case("ud2a", "ud2")
     .Default(Name);
 
   // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.

Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=117435&r1=117434&r2=117435&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Tue Oct 26 22:01:02 2010
@@ -782,3 +782,7 @@
 // CHECK: fnclex
 // CHECK:  encoding: [0xdb,0xe2]
         	fnclex
+
+// CHECK: ud2
+// CHECK:  encoding: [0x0f,0x0b]
+        	ud2a



From isanbard at gmail.com  Tue Oct 26 23:12:04 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 26 Oct 2010 21:12:04 -0700
Subject: [llvm-commits] [PATCH,
	PING] Peephole Infrastructure improvements and (ARM, T,
	T2) TSTrr optimizations
In-Reply-To: <AANLkTimndokWkx-UW+EeVkNwPPKpyTxyEJa-+wGu1wJS@mail.gmail.com>
References: <AANLkTi=Zh7SLJAHG_Uf2TBweKQvZ9_8UFbEbeWPkwrTz@mail.gmail.com>
	<AANLkTimndokWkx-UW+EeVkNwPPKpyTxyEJa-+wGu1wJS@mail.gmail.com>
Message-ID: <5C08D216-9091-46D7-A7AC-7A856B7FD364@apple.com>

Hi Gabor,

I've been on vacation. I'll have to look at this in a few days. :)

-bw

On Oct 25, 2010, at 1:28 AM, Gabor Greif wrote:

> Ping!
> 
> Attached the diff against recent trunk.
> 
> Cheers,
> 
>   Gabor
> 
> On 10/21/10, Gabor Greif <ggreif at gmail.com> wrote:
>> Hi all,
>> 
>> the last weeks I've been working on a flexible infrastructure for
>> peephole optimizations, which is potentially target independent and
>> extensible without needing interface changes.
>> 
>> The result of my work is attached. It moves all current ARM peepholes
>> over to the new architecture and adds TSTrr-related optimizations too.
>> 
>> The ordering and forward referencing of functions is still suboptimal,
>> but this is only done to keep the patch size manageable. I plan to
>> reorder in a cleanup commit after this patch has landed. Also some
>> currently freestanding functions will become methods.
>> 
>> You can also see the code in its entirety here:
>> <http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/>
>> 
>> Feedback is welcome.
>> 
>> Cheers,
>> 
>>   Gabor
>> 
> <peep-infra.patch>



From nicholas at mxc.ca  Wed Oct 27 01:34:33 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 26 Oct 2010 23:34:33 -0700
Subject: [llvm-commits] PATCH: new Value::getThruSplat API
Message-ID: <4CC7C7F9.9050806@mxc.ca>

This patch adds a new method on Value called getThruSplat() which 
returns the splatted value iff this is a ConstantValue with a splat, or 
'this' otherwise. I demonstrate its usage by updating 
InstructionSimplify to uniformly handle splat vectors alongside 
ConstantInt values.

Please review!

Nick
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From foldr at codedgers.com  Wed Oct 27 02:39:48 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 27 Oct 2010 07:39:48 -0000
Subject: [llvm-commits] [llvm] r117440 - in /llvm/trunk/include/llvm:
 Instructions.h Support/IRBuilder.h
Message-ID: <20101027073948.8F00C2A6C12D@llvm.org>

Author: foldr
Date: Wed Oct 27 02:39:48 2010
New Revision: 117440

URL: http://llvm.org/viewvc/llvm-project?rev=117440&view=rev
Log:
Trailing whitespace.

Modified:
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/IRBuilder.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=117440&r1=117439&r2=117440&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Wed Oct 27 02:39:48 2010
@@ -43,7 +43,7 @@
 public:
   explicit AllocaInst(const Type *Ty, Value *ArraySize = 0,
                       const Twine &Name = "", Instruction *InsertBefore = 0);
-  AllocaInst(const Type *Ty, Value *ArraySize, 
+  AllocaInst(const Type *Ty, Value *ArraySize,
              const Twine &Name, BasicBlock *InsertAtEnd);
 
   AllocaInst(const Type *Ty, const Twine &Name, Instruction *InsertBefore = 0);
@@ -166,8 +166,8 @@
   unsigned getPointerAddressSpace() const {
     return cast<PointerType>(getPointerOperand()->getType())->getAddressSpace();
   }
-  
-  
+
+
   // Methods for support type inquiry through isa, cast, and dyn_cast:
   static inline bool classof(const LoadInst *) { return true; }
   static inline bool classof(const Instruction *I) {
@@ -237,7 +237,7 @@
 
   Value *getValueOperand() { return getOperand(0); }
   const Value *getValueOperand() const { return getOperand(0); }
-  
+
   Value *getPointerOperand() { return getOperand(1); }
   const Value *getPointerOperand() const { return getOperand(1); }
   static unsigned getPointerOperandIndex() { return 1U; }
@@ -245,7 +245,7 @@
   unsigned getPointerAddressSpace() const {
     return cast<PointerType>(getPointerOperand()->getType())->getAddressSpace();
   }
-  
+
   // Methods for support type inquiry through isa, cast, and dyn_cast:
   static inline bool classof(const StoreInst *) { return true; }
   static inline bool classof(const Instruction *I) {
@@ -472,7 +472,7 @@
   static unsigned getPointerOperandIndex() {
     return 0U;                      // get index for modifying correct operand
   }
-  
+
   unsigned getPointerAddressSpace() const {
     return cast<PointerType>(getType())->getAddressSpace();
   }
@@ -575,7 +575,7 @@
 class ICmpInst: public CmpInst {
 protected:
   /// @brief Clone an indentical ICmpInst
-  virtual ICmpInst *clone_impl() const;  
+  virtual ICmpInst *clone_impl() const;
 public:
   /// @brief Constructor with insert-before-instruction semantics.
   ICmpInst(
@@ -746,7 +746,7 @@
     assert(getOperand(0)->getType()->isFPOrFPVectorTy() &&
            "Invalid operand types for FCmp instruction");
   }
-  
+
   /// @brief Constructor with insert-at-end semantics.
   FCmpInst(
     BasicBlock &InsertAtEnd, ///< Block to insert into.
@@ -984,7 +984,7 @@
   unsigned getParamAlignment(unsigned i) const {
     return AttributeList.getParamAlignment(i);
   }
-  
+
   /// @brief Return true if the call should not be inlined.
   bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
   void setIsNoInline(bool Value = true) {
@@ -1052,7 +1052,7 @@
   void setCalledFunction(Value* Fn) {
     Op<-1>() = Fn;
   }
-  
+
   /// isInlineAsm - Check if this call is an inline asm statement.
   bool isInlineAsm() const {
     return isa<InlineAsm>(Op<-1>());
@@ -1156,7 +1156,7 @@
   Value *getCondition() { return Op<0>(); }
   Value *getTrueValue() { return Op<1>(); }
   Value *getFalseValue() { return Op<2>(); }
-  
+
   /// areInvalidOperands - Return a string if the specified operands are invalid
   /// for a select operation, otherwise return null.
   static const char *areInvalidOperands(Value *Cond, Value *True, Value *False);
@@ -1256,12 +1256,12 @@
   Value *getIndexOperand() { return Op<1>(); }
   const Value *getVectorOperand() const { return Op<0>(); }
   const Value *getIndexOperand() const { return Op<1>(); }
-  
+
   const VectorType *getVectorOperandType() const {
     return reinterpret_cast<const VectorType*>(getVectorOperand()->getType());
   }
-  
-  
+
+
   /// Transparently provide more efficient getOperand methods.
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
@@ -1839,7 +1839,7 @@
   BasicBlock *getIncomingBlock(unsigned i) const {
     return cast<BasicBlock>(getOperand(i*2+1));
   }
-  
+
   /// getIncomingBlock - Return incoming basic block corresponding
   /// to an operand of the PHI.
   ///
@@ -1847,7 +1847,7 @@
     assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
     return cast<BasicBlock>((&U + 1)->get());
   }
-  
+
   /// getIncomingBlock - Return incoming basic block corresponding
   /// to value use iterator.
   ///
@@ -1855,8 +1855,8 @@
   BasicBlock *getIncomingBlock(value_use_iterator<U> I) const {
     return getIncomingBlock(I.getUse());
   }
-  
-  
+
+
   void setIncomingBlock(unsigned i, BasicBlock *BB) {
     setOperand(i*2+1, (Value*)BB);
   }
@@ -2300,7 +2300,7 @@
   /// here to make memory allocation more efficient.  This constructor can also
   /// autoinsert before another instruction.
   IndirectBrInst(Value *Address, unsigned NumDests, Instruction *InsertBefore);
-  
+
   /// IndirectBrInst ctor - Create a new indirectbr instruction, specifying an
   /// Address to jump to.  The number of expected destinations can be specified
   /// here to make memory allocation more efficient.  This constructor also
@@ -2318,32 +2318,32 @@
     return new IndirectBrInst(Address, NumDests, InsertAtEnd);
   }
   ~IndirectBrInst();
-  
+
   /// Provide fast operand accessors.
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
-  
+
   // Accessor Methods for IndirectBrInst instruction.
   Value *getAddress() { return getOperand(0); }
   const Value *getAddress() const { return getOperand(0); }
   void setAddress(Value *V) { setOperand(0, V); }
-  
-  
+
+
   /// getNumDestinations - return the number of possible destinations in this
   /// indirectbr instruction.
   unsigned getNumDestinations() const { return getNumOperands()-1; }
-  
+
   /// getDestination - Return the specified destination.
   BasicBlock *getDestination(unsigned i) { return getSuccessor(i); }
   const BasicBlock *getDestination(unsigned i) const { return getSuccessor(i); }
-  
+
   /// addDestination - Add a destination.
   ///
   void addDestination(BasicBlock *Dest);
-  
+
   /// removeDestination - This method removes the specified successor from the
   /// indirectbr instruction.
   void removeDestination(unsigned i);
-  
+
   unsigned getNumSuccessors() const { return getNumOperands()-1; }
   BasicBlock *getSuccessor(unsigned i) const {
     return cast<BasicBlock>(getOperand(i+1));
@@ -2351,7 +2351,7 @@
   void setSuccessor(unsigned i, BasicBlock *NewSucc) {
     setOperand(i+1, (Value*)NewSucc);
   }
-  
+
   // Methods for support type inquiry through isa, cast, and dyn_cast:
   static inline bool classof(const IndirectBrInst *) { return true; }
   static inline bool classof(const Instruction *I) {
@@ -2371,8 +2371,8 @@
 };
 
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(IndirectBrInst, Value)
-  
-  
+
+
 //===----------------------------------------------------------------------===//
 //                               InvokeInst Class
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=117440&r1=117439&r2=117440&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
+++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed Oct 27 02:39:48 2010
@@ -46,50 +46,50 @@
   BasicBlock::iterator InsertPt;
   LLVMContext &Context;
 public:
-  
+
   IRBuilderBase(LLVMContext &context)
     : Context(context) {
     ClearInsertionPoint();
   }
-  
+
   //===--------------------------------------------------------------------===//
   // Builder configuration methods
   //===--------------------------------------------------------------------===//
-  
+
   /// ClearInsertionPoint - Clear the insertion point: created instructions will
   /// not be inserted into a block.
   void ClearInsertionPoint() {
     BB = 0;
   }
-  
+
   BasicBlock *GetInsertBlock() const { return BB; }
   BasicBlock::iterator GetInsertPoint() const { return InsertPt; }
   LLVMContext &getContext() const { return Context; }
-  
+
   /// SetInsertPoint - This specifies that created instructions should be
   /// appended to the end of the specified block.
   void SetInsertPoint(BasicBlock *TheBB) {
     BB = TheBB;
     InsertPt = BB->end();
   }
-  
+
   /// SetInsertPoint - This specifies that created instructions should be
   /// inserted at the specified point.
   void SetInsertPoint(BasicBlock *TheBB, BasicBlock::iterator IP) {
     BB = TheBB;
     InsertPt = IP;
   }
-  
+
   /// SetCurrentDebugLocation - Set location information used by debugging
   /// information.
   void SetCurrentDebugLocation(const DebugLoc &L) {
     CurDbgLocation = L;
   }
-  
+
   /// getCurrentDebugLocation - Get location information used by debugging
   /// information.
   const DebugLoc &getCurrentDebugLocation() const { return CurDbgLocation; }
-  
+
   /// SetInstDebugLocation - If this builder has a current debug location, set
   /// it on the specified instruction.
   void SetInstDebugLocation(Instruction *I) const {
@@ -142,7 +142,7 @@
   //===--------------------------------------------------------------------===//
   // Miscellaneous creation methods.
   //===--------------------------------------------------------------------===//
-  
+
   /// CreateGlobalString - Make a new global variable with an initializer that
   /// has array of i8 type filled in with the nul terminated string value
   /// specified.  If Name is specified, it is the name of the global variable
@@ -178,65 +178,65 @@
   ConstantInt *getInt32(uint32_t C) {
     return ConstantInt::get(getInt32Ty(), C);
   }
-  
+
   /// getInt64 - Get a constant 64-bit value.
   ConstantInt *getInt64(uint64_t C) {
     return ConstantInt::get(getInt64Ty(), C);
   }
-  
+
   //===--------------------------------------------------------------------===//
   // Type creation methods
   //===--------------------------------------------------------------------===//
-  
+
   /// getInt1Ty - Fetch the type representing a single bit
   const IntegerType *getInt1Ty() {
     return Type::getInt1Ty(Context);
   }
-  
+
   /// getInt8Ty - Fetch the type representing an 8-bit integer.
   const IntegerType *getInt8Ty() {
     return Type::getInt8Ty(Context);
   }
-  
+
   /// getInt16Ty - Fetch the type representing a 16-bit integer.
   const IntegerType *getInt16Ty() {
     return Type::getInt16Ty(Context);
   }
-  
+
   /// getInt32Ty - Fetch the type resepresenting a 32-bit integer.
   const IntegerType *getInt32Ty() {
     return Type::getInt32Ty(Context);
   }
-  
+
   /// getInt64Ty - Fetch the type representing a 64-bit integer.
   const IntegerType *getInt64Ty() {
     return Type::getInt64Ty(Context);
   }
-  
+
   /// getFloatTy - Fetch the type representing a 32-bit floating point value.
   const Type *getFloatTy() {
     return Type::getFloatTy(Context);
   }
-  
+
   /// getDoubleTy - Fetch the type representing a 64-bit floating point value.
   const Type *getDoubleTy() {
     return Type::getDoubleTy(Context);
   }
-  
+
   /// getVoidTy - Fetch the type representing void.
   const Type *getVoidTy() {
     return Type::getVoidTy(Context);
   }
-  
+
   const PointerType *getInt8PtrTy() {
     return Type::getInt8PtrTy(Context);
   }
-  
+
   /// getCurrentFunctionReturnType - Get the return type of the current function
   /// that we're emitting into.
   const Type *getCurrentFunctionReturnType() const;
 };
-  
+
 /// IRBuilder - This provides a uniform API for creating instructions and
 /// inserting them into a basic block: either at the end of a BasicBlock, or
 /// at a specific iterator location in a block.
@@ -258,25 +258,25 @@
   IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter())
     : IRBuilderBase(C), Inserter(I), Folder(F) {
   }
-  
+
   explicit IRBuilder(LLVMContext &C) : IRBuilderBase(C), Folder(C) {
   }
-  
+
   explicit IRBuilder(BasicBlock *TheBB, const T &F)
     : IRBuilderBase(TheBB->getContext()), Folder(F) {
     SetInsertPoint(TheBB);
   }
-  
+
   explicit IRBuilder(BasicBlock *TheBB)
     : IRBuilderBase(TheBB->getContext()), Folder(Context) {
     SetInsertPoint(TheBB);
   }
-  
+
   IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F)
     : IRBuilderBase(TheBB->getContext()), Folder(F) {
     SetInsertPoint(TheBB, IP);
   }
-  
+
   IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP)
     : IRBuilderBase(TheBB->getContext()), Folder(Context) {
     SetInsertPoint(TheBB, IP);
@@ -288,7 +288,7 @@
   /// isNamePreserving - Return true if this builder is configured to actually
   /// add the requested names to IR created through it.
   bool isNamePreserving() const { return preserveNames; }
-  
+
   /// Insert - Insert and return the specified instruction.
   template<typename InstTy>
   InstTy *Insert(InstTy *I, const Twine &Name = "") const {
@@ -313,7 +313,7 @@
   ReturnInst *CreateRet(Value *V) {
     return Insert(ReturnInst::Create(Context, V));
   }
-  
+
   /// CreateAggregateRet - Create a sequence of N insertvalue instructions,
   /// with one Value from the retVals array each, that build a aggregate
   /// return value one value at a time, and a ret instruction to return
@@ -735,7 +735,7 @@
     if (Constant *PC = dyn_cast<Constant>(Ptr))
       return Folder.CreateGetElementPtr(PC, &Idx, 1);
 
-    return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);    
+    return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
   }
   Value *CreateConstInBoundsGEP1_32(Value *Ptr, unsigned Idx0,
                                     const Twine &Name = "") {
@@ -746,7 +746,7 @@
 
     return Insert(GetElementPtrInst::CreateInBounds(Ptr, &Idx, &Idx+1), Name);
   }
-  Value *CreateConstGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1, 
+  Value *CreateConstGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1,
                     const Twine &Name = "") {
     Value *Idxs[] = {
       ConstantInt::get(Type::getInt32Ty(Context), Idx0),
@@ -756,7 +756,7 @@
     if (Constant *PC = dyn_cast<Constant>(Ptr))
       return Folder.CreateGetElementPtr(PC, Idxs, 2);
 
-    return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);    
+    return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
   }
   Value *CreateConstInBoundsGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1,
                                     const Twine &Name = "") {
@@ -776,7 +776,7 @@
     if (Constant *PC = dyn_cast<Constant>(Ptr))
       return Folder.CreateGetElementPtr(PC, &Idx, 1);
 
-    return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);    
+    return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
   }
   Value *CreateConstInBoundsGEP1_64(Value *Ptr, uint64_t Idx0,
                                     const Twine &Name = "") {
@@ -797,7 +797,7 @@
     if (Constant *PC = dyn_cast<Constant>(Ptr))
       return Folder.CreateGetElementPtr(PC, Idxs, 2);
 
-    return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);    
+    return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
   }
   Value *CreateConstInBoundsGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1,
                                     const Twine &Name = "") {
@@ -814,7 +814,7 @@
   Value *CreateStructGEP(Value *Ptr, unsigned Idx, const Twine &Name = "") {
     return CreateConstInBoundsGEP2_32(Ptr, 0, Idx, Name);
   }
-  
+
   /// CreateGlobalStringPtr - Same as CreateGlobalString, but return a pointer
   /// with "i8*" type instead of a pointer to array of i8.
   Value *CreateGlobalStringPtr(const char *Str = "", const Twine &Name = "") {
@@ -823,7 +823,7 @@
     Value *Args[] = { zero, zero };
     return CreateInBoundsGEP(gv, Args, Args+2, Name);
   }
-  
+
   //===--------------------------------------------------------------------===//
   // Instruction creation methods: Cast/Conversion Operators
   //===--------------------------------------------------------------------===//



From foldr at codedgers.com  Wed Oct 27 02:39:54 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 27 Oct 2010 07:39:54 -0000
Subject: [llvm-commits] [llvm] r117441 - in /llvm/trunk/include/llvm:
 Instructions.h Support/IRBuilder.h
Message-ID: <20101027073954.DB9912A6C12E@llvm.org>

Author: foldr
Date: Wed Oct 27 02:39:54 2010
New Revision: 117441

URL: http://llvm.org/viewvc/llvm-project?rev=117441&view=rev
Log:
It is confusing to call a random-access iterator 'InputIterator'.

Modified:
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/IRBuilder.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=117441&r1=117440&r2=117441&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Wed Oct 27 02:39:54 2010
@@ -289,8 +289,10 @@
             const Twine &NameStr);
   void init(Value *Ptr, Value *Idx, const Twine &NameStr);
 
-  template<typename InputIterator>
-  void init(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  void init(Value *Ptr,
+            RandomAccessIterator IdxBegin,
+            RandomAccessIterator IdxEnd,
             const Twine &NameStr,
             // This argument ensures that we have an iterator we can
             // do arithmetic on in constant time
@@ -313,10 +315,10 @@
   /// Null is returned if the indices are invalid for the specified
   /// pointer type.
   ///
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static const Type *getIndexedType(const Type *Ptr,
-                                    InputIterator IdxBegin,
-                                    InputIterator IdxEnd,
+                                    RandomAccessIterator IdxBegin,
+                                    RandomAccessIterator IdxEnd,
                                     // This argument ensures that we
                                     // have an iterator we can do
                                     // arithmetic on in constant time
@@ -331,18 +333,19 @@
   }
 
   /// Constructors - Create a getelementptr instruction with a base pointer an
-  /// list of indices.  The first ctor can optionally insert before an existing
+  /// list of indices. The first ctor can optionally insert before an existing
   /// instruction, the second appends the new instruction to the specified
   /// BasicBlock.
-  template<typename InputIterator>
-  inline GetElementPtrInst(Value *Ptr, InputIterator IdxBegin,
-                           InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  inline GetElementPtrInst(Value *Ptr, RandomAccessIterator IdxBegin,
+                           RandomAccessIterator IdxEnd,
                            unsigned Values,
                            const Twine &NameStr,
                            Instruction *InsertBefore);
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   inline GetElementPtrInst(Value *Ptr,
-                           InputIterator IdxBegin, InputIterator IdxEnd,
+                           RandomAccessIterator IdxBegin,
+                           RandomAccessIterator IdxEnd,
                            unsigned Values,
                            const Twine &NameStr, BasicBlock *InsertAtEnd);
 
@@ -355,23 +358,24 @@
 protected:
   virtual GetElementPtrInst *clone_impl() const;
 public:
-  template<typename InputIterator>
-  static GetElementPtrInst *Create(Value *Ptr, InputIterator IdxBegin,
-                                   InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  static GetElementPtrInst *Create(Value *Ptr, RandomAccessIterator IdxBegin,
+                                   RandomAccessIterator IdxEnd,
                                    const Twine &NameStr = "",
                                    Instruction *InsertBefore = 0) {
-    typename std::iterator_traits<InputIterator>::difference_type Values =
-      1 + std::distance(IdxBegin, IdxEnd);
+    typename std::iterator_traits<RandomAccessIterator>::difference_type
+      Values = 1 + std::distance(IdxBegin, IdxEnd);
     return new(Values)
       GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertBefore);
   }
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static GetElementPtrInst *Create(Value *Ptr,
-                                   InputIterator IdxBegin, InputIterator IdxEnd,
+                                   RandomAccessIterator IdxBegin,
+                                   RandomAccessIterator IdxEnd,
                                    const Twine &NameStr,
                                    BasicBlock *InsertAtEnd) {
-    typename std::iterator_traits<InputIterator>::difference_type Values =
-      1 + std::distance(IdxBegin, IdxEnd);
+    typename std::iterator_traits<RandomAccessIterator>::difference_type
+      Values = 1 + std::distance(IdxBegin, IdxEnd);
     return new(Values)
       GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertAtEnd);
   }
@@ -391,9 +395,10 @@
 
   /// Create an "inbounds" getelementptr. See the documentation for the
   /// "inbounds" flag in LangRef.html for details.
-  template<typename InputIterator>
-  static GetElementPtrInst *CreateInBounds(Value *Ptr, InputIterator IdxBegin,
-                                           InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  static GetElementPtrInst *CreateInBounds(Value *Ptr,
+                                           RandomAccessIterator IdxBegin,
+                                           RandomAccessIterator IdxEnd,
                                            const Twine &NameStr = "",
                                            Instruction *InsertBefore = 0) {
     GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
@@ -401,10 +406,10 @@
     GEP->setIsInBounds(true);
     return GEP;
   }
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static GetElementPtrInst *CreateInBounds(Value *Ptr,
-                                           InputIterator IdxBegin,
-                                           InputIterator IdxEnd,
+                                           RandomAccessIterator IdxBegin,
+                                           RandomAccessIterator IdxEnd,
                                            const Twine &NameStr,
                                            BasicBlock *InsertAtEnd) {
     GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
@@ -441,12 +446,12 @@
   /// Null is returned if the indices are invalid for the specified
   /// pointer type.
   ///
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static const Type *getIndexedType(const Type *Ptr,
-                                    InputIterator IdxBegin,
-                                    InputIterator IdxEnd) {
+                                    RandomAccessIterator IdxBegin,
+                                    RandomAccessIterator IdxEnd) {
     return getIndexedType(Ptr, IdxBegin, IdxEnd,
-                          typename std::iterator_traits<InputIterator>::
+                          typename std::iterator_traits<RandomAccessIterator>::
                           iterator_category());
   }
 
@@ -523,10 +528,10 @@
 struct OperandTraits<GetElementPtrInst> : public VariadicOperandTraits<1> {
 };
 
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 GetElementPtrInst::GetElementPtrInst(Value *Ptr,
-                                     InputIterator IdxBegin,
-                                     InputIterator IdxEnd,
+                                     RandomAccessIterator IdxBegin,
+                                     RandomAccessIterator IdxEnd,
                                      unsigned Values,
                                      const Twine &NameStr,
                                      Instruction *InsertBefore)
@@ -539,12 +544,13 @@
                 OperandTraits<GetElementPtrInst>::op_end(this) - Values,
                 Values, InsertBefore) {
   init(Ptr, IdxBegin, IdxEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 GetElementPtrInst::GetElementPtrInst(Value *Ptr,
-                                     InputIterator IdxBegin,
-                                     InputIterator IdxEnd,
+                                     RandomAccessIterator IdxBegin,
+                                     RandomAccessIterator IdxEnd,
                                      unsigned Values,
                                      const Twine &NameStr,
                                      BasicBlock *InsertAtEnd)
@@ -557,7 +563,8 @@
                 OperandTraits<GetElementPtrInst>::op_end(this) - Values,
                 Values, InsertAtEnd) {
   init(Ptr, IdxBegin, IdxEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
 
 
@@ -838,8 +845,10 @@
   void init(Value *Func, Value *Actual);
   void init(Value *Func);
 
-  template<typename InputIterator>
-  void init(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+  template<typename RandomAccessIterator>
+  void init(Value *Func,
+            RandomAccessIterator ArgBegin,
+            RandomAccessIterator ArgEnd,
             const Twine &NameStr,
             // This argument ensures that we have an iterator we can
             // do arithmetic on in constant time
@@ -851,24 +860,26 @@
     setName(NameStr);
   }
 
-  /// Construct a CallInst given a range of arguments.  InputIterator
+  /// Construct a CallInst given a range of arguments. RandomAccessIterator
   /// must be a random-access iterator pointing to contiguous storage
-  /// (e.g. a std::vector<>::iterator).  Checks are made for
+  /// (e.g. a std::vector<>::iterator). Checks are made for
   /// random-accessness but not for contiguous storage as that would
   /// incur runtime overhead.
   /// @brief Construct a CallInst from a range of arguments
-  template<typename InputIterator>
-  CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+  template<typename RandomAccessIterator>
+  CallInst(Value *Func,
+           RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
            const Twine &NameStr, Instruction *InsertBefore);
 
-  /// Construct a CallInst given a range of arguments.  InputIterator
+  /// Construct a CallInst given a range of arguments.  RandomAccessIterator
   /// must be a random-access iterator pointing to contiguous storage
   /// (e.g. a std::vector<>::iterator).  Checks are made for
   /// random-accessness but not for contiguous storage as that would
   /// incur runtime overhead.
   /// @brief Construct a CallInst from a range of arguments
-  template<typename InputIterator>
-  inline CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+  template<typename RandomAccessIterator>
+  inline CallInst(Value *Func,
+                  RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
                   const Twine &NameStr, BasicBlock *InsertAtEnd);
 
   CallInst(Value *F, Value *Actual, const Twine &NameStr,
@@ -881,17 +892,19 @@
 protected:
   virtual CallInst *clone_impl() const;
 public:
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static CallInst *Create(Value *Func,
-                          InputIterator ArgBegin, InputIterator ArgEnd,
+                          RandomAccessIterator ArgBegin,
+                          RandomAccessIterator ArgEnd,
                           const Twine &NameStr = "",
                           Instruction *InsertBefore = 0) {
     return new(unsigned(ArgEnd - ArgBegin + 1))
       CallInst(Func, ArgBegin, ArgEnd, NameStr, InsertBefore);
   }
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static CallInst *Create(Value *Func,
-                          InputIterator ArgBegin, InputIterator ArgEnd,
+                          RandomAccessIterator ArgBegin,
+                          RandomAccessIterator ArgEnd,
                           const Twine &NameStr, BasicBlock *InsertAtEnd) {
     return new(unsigned(ArgEnd - ArgBegin + 1))
       CallInst(Func, ArgBegin, ArgEnd, NameStr, InsertAtEnd);
@@ -1078,8 +1091,9 @@
 struct OperandTraits<CallInst> : public VariadicOperandTraits<1> {
 };
 
-template<typename InputIterator>
-CallInst::CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+template<typename RandomAccessIterator>
+CallInst::CallInst(Value *Func,
+                   RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
                    const Twine &NameStr, BasicBlock *InsertAtEnd)
   : Instruction(cast<FunctionType>(cast<PointerType>(Func->getType())
                                    ->getElementType())->getReturnType(),
@@ -1087,11 +1101,13 @@
                 OperandTraits<CallInst>::op_end(this) - (ArgEnd - ArgBegin + 1),
                 unsigned(ArgEnd - ArgBegin + 1), InsertAtEnd) {
   init(Func, ArgBegin, ArgEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
 
-template<typename InputIterator>
-CallInst::CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+template<typename RandomAccessIterator>
+CallInst::CallInst(Value *Func,
+                   RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
                    const Twine &NameStr, Instruction *InsertBefore)
   : Instruction(cast<FunctionType>(cast<PointerType>(Func->getType())
                                    ->getElementType())->getReturnType(),
@@ -1099,7 +1115,8 @@
                 OperandTraits<CallInst>::op_end(this) - (ArgEnd - ArgBegin + 1),
                 unsigned(ArgEnd - ArgBegin + 1), InsertBefore) {
   init(Func, ArgBegin, ArgEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
 
 
@@ -1411,8 +1428,9 @@
             const Twine &NameStr);
   void init(unsigned Idx, const Twine &NameStr);
 
-  template<typename InputIterator>
-  void init(InputIterator IdxBegin, InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  void init(RandomAccessIterator IdxBegin,
+            RandomAccessIterator IdxEnd,
             const Twine &NameStr,
             // This argument ensures that we have an iterator we can
             // do arithmetic on in constant time
@@ -1439,10 +1457,10 @@
   static const Type *getIndexedType(const Type *Agg,
                                     const unsigned *Idx, unsigned NumIdx);
 
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static const Type *getIndexedType(const Type *Ptr,
-                                    InputIterator IdxBegin,
-                                    InputIterator IdxEnd,
+                                    RandomAccessIterator IdxBegin,
+                                    RandomAccessIterator IdxEnd,
                                     // This argument ensures that we
                                     // have an iterator we can do
                                     // arithmetic on in constant time
@@ -1460,14 +1478,16 @@
   /// value and a list of indices.  The first ctor can optionally insert before
   /// an existing instruction, the second appends the new instruction to the
   /// specified BasicBlock.
-  template<typename InputIterator>
-  inline ExtractValueInst(Value *Agg, InputIterator IdxBegin,
-                          InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  inline ExtractValueInst(Value *Agg,
+                          RandomAccessIterator IdxBegin,
+                          RandomAccessIterator IdxEnd,
                           const Twine &NameStr,
                           Instruction *InsertBefore);
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   inline ExtractValueInst(Value *Agg,
-                          InputIterator IdxBegin, InputIterator IdxEnd,
+                          RandomAccessIterator IdxBegin,
+                          RandomAccessIterator IdxEnd,
                           const Twine &NameStr, BasicBlock *InsertAtEnd);
 
   // allocate space for exactly one operand
@@ -1478,17 +1498,19 @@
   virtual ExtractValueInst *clone_impl() const;
 
 public:
-  template<typename InputIterator>
-  static ExtractValueInst *Create(Value *Agg, InputIterator IdxBegin,
-                                  InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  static ExtractValueInst *Create(Value *Agg,
+                                  RandomAccessIterator IdxBegin,
+                                  RandomAccessIterator IdxEnd,
                                   const Twine &NameStr = "",
                                   Instruction *InsertBefore = 0) {
     return new
       ExtractValueInst(Agg, IdxBegin, IdxEnd, NameStr, InsertBefore);
   }
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static ExtractValueInst *Create(Value *Agg,
-                                  InputIterator IdxBegin, InputIterator IdxEnd,
+                                  RandomAccessIterator IdxBegin,
+                                  RandomAccessIterator IdxEnd,
                                   const Twine &NameStr,
                                   BasicBlock *InsertAtEnd) {
     return new ExtractValueInst(Agg, IdxBegin, IdxEnd, NameStr, InsertAtEnd);
@@ -1516,12 +1538,12 @@
   /// Null is returned if the indices are invalid for the specified
   /// pointer type.
   ///
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static const Type *getIndexedType(const Type *Ptr,
-                                    InputIterator IdxBegin,
-                                    InputIterator IdxEnd) {
+                                    RandomAccessIterator IdxBegin,
+                                    RandomAccessIterator IdxEnd) {
     return getIndexedType(Ptr, IdxBegin, IdxEnd,
-                          typename std::iterator_traits<InputIterator>::
+                          typename std::iterator_traits<RandomAccessIterator>::
                           iterator_category());
   }
   static const Type *getIndexedType(const Type *Ptr, unsigned Idx);
@@ -1558,29 +1580,31 @@
   }
 };
 
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 ExtractValueInst::ExtractValueInst(Value *Agg,
-                                   InputIterator IdxBegin,
-                                   InputIterator IdxEnd,
+                                   RandomAccessIterator IdxBegin,
+                                   RandomAccessIterator IdxEnd,
                                    const Twine &NameStr,
                                    Instruction *InsertBefore)
   : UnaryInstruction(checkType(getIndexedType(Agg->getType(),
                                               IdxBegin, IdxEnd)),
                      ExtractValue, Agg, InsertBefore) {
   init(IdxBegin, IdxEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 ExtractValueInst::ExtractValueInst(Value *Agg,
-                                   InputIterator IdxBegin,
-                                   InputIterator IdxEnd,
+                                   RandomAccessIterator IdxBegin,
+                                   RandomAccessIterator IdxEnd,
                                    const Twine &NameStr,
                                    BasicBlock *InsertAtEnd)
   : UnaryInstruction(checkType(getIndexedType(Agg->getType(),
                                               IdxBegin, IdxEnd)),
                      ExtractValue, Agg, InsertAtEnd) {
   init(IdxBegin, IdxEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
 
 
@@ -1600,9 +1624,9 @@
             const Twine &NameStr);
   void init(Value *Agg, Value *Val, unsigned Idx, const Twine &NameStr);
 
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   void init(Value *Agg, Value *Val,
-            InputIterator IdxBegin, InputIterator IdxEnd,
+            RandomAccessIterator IdxBegin, RandomAccessIterator IdxEnd,
             const Twine &NameStr,
             // This argument ensures that we have an iterator we can
             // do arithmetic on in constant time
@@ -1624,14 +1648,16 @@
   /// value, a value to insert, and a list of indices.  The first ctor can
   /// optionally insert before an existing instruction, the second appends
   /// the new instruction to the specified BasicBlock.
-  template<typename InputIterator>
-  inline InsertValueInst(Value *Agg, Value *Val, InputIterator IdxBegin,
-                         InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  inline InsertValueInst(Value *Agg, Value *Val,
+                         RandomAccessIterator IdxBegin,
+                         RandomAccessIterator IdxEnd,
                          const Twine &NameStr,
                          Instruction *InsertBefore);
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   inline InsertValueInst(Value *Agg, Value *Val,
-                         InputIterator IdxBegin, InputIterator IdxEnd,
+                         RandomAccessIterator IdxBegin,
+                         RandomAccessIterator IdxEnd,
                          const Twine &NameStr, BasicBlock *InsertAtEnd);
 
   /// Constructors - These two constructors are convenience methods because one
@@ -1649,17 +1675,19 @@
     return User::operator new(s, 2);
   }
 
-  template<typename InputIterator>
-  static InsertValueInst *Create(Value *Agg, Value *Val, InputIterator IdxBegin,
-                                 InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  static InsertValueInst *Create(Value *Agg, Value *Val,
+                                 RandomAccessIterator IdxBegin,
+                                 RandomAccessIterator IdxEnd,
                                  const Twine &NameStr = "",
                                  Instruction *InsertBefore = 0) {
     return new InsertValueInst(Agg, Val, IdxBegin, IdxEnd,
                                NameStr, InsertBefore);
   }
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static InsertValueInst *Create(Value *Agg, Value *Val,
-                                 InputIterator IdxBegin, InputIterator IdxEnd,
+                                 RandomAccessIterator IdxBegin,
+                                 RandomAccessIterator IdxEnd,
                                  const Twine &NameStr,
                                  BasicBlock *InsertAtEnd) {
     return new InsertValueInst(Agg, Val, IdxBegin, IdxEnd,
@@ -1729,31 +1757,33 @@
 struct OperandTraits<InsertValueInst> : public FixedNumOperandTraits<2> {
 };
 
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 InsertValueInst::InsertValueInst(Value *Agg,
                                  Value *Val,
-                                 InputIterator IdxBegin,
-                                 InputIterator IdxEnd,
+                                 RandomAccessIterator IdxBegin,
+                                 RandomAccessIterator IdxEnd,
                                  const Twine &NameStr,
                                  Instruction *InsertBefore)
   : Instruction(Agg->getType(), InsertValue,
                 OperandTraits<InsertValueInst>::op_begin(this),
                 2, InsertBefore) {
   init(Agg, Val, IdxBegin, IdxEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 InsertValueInst::InsertValueInst(Value *Agg,
                                  Value *Val,
-                                 InputIterator IdxBegin,
-                                 InputIterator IdxEnd,
+                                 RandomAccessIterator IdxBegin,
+                                 RandomAccessIterator IdxEnd,
                                  const Twine &NameStr,
                                  BasicBlock *InsertAtEnd)
   : Instruction(Agg->getType(), InsertValue,
                 OperandTraits<InsertValueInst>::op_begin(this),
                 2, InsertAtEnd) {
   init(Agg, Val, IdxBegin, IdxEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
 
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertValueInst, Value)
@@ -2386,9 +2416,9 @@
   void init(Value *Fn, BasicBlock *IfNormal, BasicBlock *IfException,
             Value* const *Args, unsigned NumArgs);
 
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   void init(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
-            InputIterator ArgBegin, InputIterator ArgEnd,
+            RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
             const Twine &NameStr,
             // This argument ensures that we have an iterator we can
             // do arithmetic on in constant time
@@ -2401,47 +2431,49 @@
   }
 
   /// Construct an InvokeInst given a range of arguments.
-  /// InputIterator must be a random-access iterator pointing to
+  /// RandomAccessIterator must be a random-access iterator pointing to
   /// contiguous storage (e.g. a std::vector<>::iterator).  Checks are
   /// made for random-accessness but not for contiguous storage as
   /// that would incur runtime overhead.
   ///
   /// @brief Construct an InvokeInst from a range of arguments
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
-                    InputIterator ArgBegin, InputIterator ArgEnd,
+                    RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
                     unsigned Values,
                     const Twine &NameStr, Instruction *InsertBefore);
 
   /// Construct an InvokeInst given a range of arguments.
-  /// InputIterator must be a random-access iterator pointing to
+  /// RandomAccessIterator must be a random-access iterator pointing to
   /// contiguous storage (e.g. a std::vector<>::iterator).  Checks are
   /// made for random-accessness but not for contiguous storage as
   /// that would incur runtime overhead.
   ///
   /// @brief Construct an InvokeInst from a range of arguments
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
-                    InputIterator ArgBegin, InputIterator ArgEnd,
+                    RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
                     unsigned Values,
                     const Twine &NameStr, BasicBlock *InsertAtEnd);
 protected:
   virtual InvokeInst *clone_impl() const;
 public:
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static InvokeInst *Create(Value *Func,
                             BasicBlock *IfNormal, BasicBlock *IfException,
-                            InputIterator ArgBegin, InputIterator ArgEnd,
+                            RandomAccessIterator ArgBegin,
+                            RandomAccessIterator ArgEnd,
                             const Twine &NameStr = "",
                             Instruction *InsertBefore = 0) {
     unsigned Values(ArgEnd - ArgBegin + 3);
     return new(Values) InvokeInst(Func, IfNormal, IfException, ArgBegin, ArgEnd,
                                   Values, NameStr, InsertBefore);
   }
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   static InvokeInst *Create(Value *Func,
                             BasicBlock *IfNormal, BasicBlock *IfException,
-                            InputIterator ArgBegin, InputIterator ArgEnd,
+                            RandomAccessIterator ArgBegin,
+                            RandomAccessIterator ArgEnd,
                             const Twine &NameStr,
                             BasicBlock *InsertAtEnd) {
     unsigned Values(ArgEnd - ArgBegin + 3);
@@ -2611,10 +2643,11 @@
 struct OperandTraits<InvokeInst> : public VariadicOperandTraits<3> {
 };
 
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 InvokeInst::InvokeInst(Value *Func,
                        BasicBlock *IfNormal, BasicBlock *IfException,
-                       InputIterator ArgBegin, InputIterator ArgEnd,
+                       RandomAccessIterator ArgBegin,
+                       RandomAccessIterator ArgEnd,
                        unsigned Values,
                        const Twine &NameStr, Instruction *InsertBefore)
   : TerminatorInst(cast<FunctionType>(cast<PointerType>(Func->getType())
@@ -2623,12 +2656,14 @@
                    OperandTraits<InvokeInst>::op_end(this) - Values,
                    Values, InsertBefore) {
   init(Func, IfNormal, IfException, ArgBegin, ArgEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
-template<typename InputIterator>
+template<typename RandomAccessIterator>
 InvokeInst::InvokeInst(Value *Func,
                        BasicBlock *IfNormal, BasicBlock *IfException,
-                       InputIterator ArgBegin, InputIterator ArgEnd,
+                       RandomAccessIterator ArgBegin,
+                       RandomAccessIterator ArgEnd,
                        unsigned Values,
                        const Twine &NameStr, BasicBlock *InsertAtEnd)
   : TerminatorInst(cast<FunctionType>(cast<PointerType>(Func->getType())
@@ -2637,7 +2672,8 @@
                    OperandTraits<InvokeInst>::op_end(this) - Values,
                    Values, InsertAtEnd) {
   init(Func, IfNormal, IfException, ArgBegin, ArgEnd, NameStr,
-       typename std::iterator_traits<InputIterator>::iterator_category());
+       typename std::iterator_traits<RandomAccessIterator>
+       ::iterator_category());
 }
 
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InvokeInst, Value)

Modified: llvm/trunk/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=117441&r1=117440&r2=117441&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/IRBuilder.h (original)
+++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed Oct 27 02:39:54 2010
@@ -375,10 +375,12 @@
                                      Args+3), Name);
   }
   /// CreateInvoke - Create an invoke instruction.
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest,
-                           BasicBlock *UnwindDest, InputIterator ArgBegin,
-                           InputIterator ArgEnd, const Twine &Name = "") {
+                           BasicBlock *UnwindDest,
+                           RandomAccessIterator ArgBegin,
+                           RandomAccessIterator ArgEnd,
+                           const Twine &Name = "") {
     return Insert(InvokeInst::Create(Callee, NormalDest, UnwindDest,
                                      ArgBegin, ArgEnd), Name);
   }
@@ -686,12 +688,14 @@
   StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) {
     return Insert(new StoreInst(Val, Ptr, isVolatile));
   }
-  template<typename InputIterator>
-  Value *CreateGEP(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd,
+  template<typename RandomAccessIterator>
+  Value *CreateGEP(Value *Ptr,
+                   RandomAccessIterator IdxBegin,
+                   RandomAccessIterator IdxEnd,
                    const Twine &Name = "") {
     if (Constant *PC = dyn_cast<Constant>(Ptr)) {
       // Every index must be constant.
-      InputIterator i;
+      RandomAccessIterator i;
       for (i = IdxBegin; i < IdxEnd; ++i)
         if (!isa<Constant>(*i))
           break;
@@ -700,12 +704,13 @@
     }
     return Insert(GetElementPtrInst::Create(Ptr, IdxBegin, IdxEnd), Name);
   }
-  template<typename InputIterator>
-  Value *CreateInBoundsGEP(Value *Ptr, InputIterator IdxBegin,
-                           InputIterator IdxEnd, const Twine &Name = "") {
+  template<typename RandomAccessIterator>
+  Value *CreateInBoundsGEP(Value *Ptr, RandomAccessIterator IdxBegin,
+                           RandomAccessIterator IdxEnd,
+                           const Twine &Name = "") {
     if (Constant *PC = dyn_cast<Constant>(Ptr)) {
       // Every index must be constant.
-      InputIterator i;
+      RandomAccessIterator i;
       for (i = IdxBegin; i < IdxEnd; ++i)
         if (!isa<Constant>(*i))
           break;
@@ -1057,9 +1062,9 @@
     return Insert(CallInst::Create(Callee, Args, Args+5), Name);
   }
 
-  template<typename InputIterator>
-  CallInst *CreateCall(Value *Callee, InputIterator ArgBegin,
-                       InputIterator ArgEnd, const Twine &Name = "") {
+  template<typename RandomAccessIterator>
+  CallInst *CreateCall(Value *Callee, RandomAccessIterator ArgBegin,
+                       RandomAccessIterator ArgEnd, const Twine &Name = "") {
     return Insert(CallInst::Create(Callee, ArgBegin, ArgEnd), Name);
   }
 
@@ -1109,10 +1114,10 @@
     return Insert(ExtractValueInst::Create(Agg, Idx), Name);
   }
 
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   Value *CreateExtractValue(Value *Agg,
-                            InputIterator IdxBegin,
-                            InputIterator IdxEnd,
+                            RandomAccessIterator IdxBegin,
+                            RandomAccessIterator IdxEnd,
                             const Twine &Name = "") {
     if (Constant *AggC = dyn_cast<Constant>(Agg))
       return Folder.CreateExtractValue(AggC, IdxBegin, IdxEnd - IdxBegin);
@@ -1127,10 +1132,10 @@
     return Insert(InsertValueInst::Create(Agg, Val, Idx), Name);
   }
 
-  template<typename InputIterator>
+  template<typename RandomAccessIterator>
   Value *CreateInsertValue(Value *Agg, Value *Val,
-                           InputIterator IdxBegin,
-                           InputIterator IdxEnd,
+                           RandomAccessIterator IdxBegin,
+                           RandomAccessIterator IdxEnd,
                            const Twine &Name = "") {
     if (Constant *AggC = dyn_cast<Constant>(Agg))
       if (Constant *ValC = dyn_cast<Constant>(Val))



From anton at korobeynikov.info  Wed Oct 27 03:38:49 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 27 Oct 2010 12:38:49 +0400
Subject: [llvm-commits] [llvm] r117420 - in /llvm/trunk: cmake/modules/
 lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/
 lib/Target/MBlaze/Disassembler/
In-Reply-To: <20101027002302.2AE5F2A6C12C@llvm.org>
References: <20101027002302.2AE5F2A6C12C@llvm.org>
Message-ID: <AANLkTikrBdMaz6C0i5vBApHLVU1HhrTrbi75ZqYnY+9e@mail.gmail.com>

Hello Wesley,

> + ?// Get the MCInst opcode from the binary instruction and make sure
> + ?// that it is a valid instruction.
> + ?unsigned opcode = getOPCODE( insn );
> + ?if( opcode == UNSUPPORTED )
> + ? ?return false;
Could you please use the consistent code style in the files? E.g. no
spaces after "(" and before ")",
space before "(", etc.

Thanks!
-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From foldr at codedgers.com  Wed Oct 27 04:09:05 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 27 Oct 2010 09:09:05 -0000
Subject: [llvm-commits] [llvm] r117442 - in /llvm/trunk/lib/System: Makefile
	Win32/Signals.inc
Message-ID: <20101027090905.0FB3E2A6C12C@llvm.org>

Author: foldr
Date: Wed Oct 27 04:09:04 2010
New Revision: 117442

URL: http://llvm.org/viewvc/llvm-project?rev=117442&view=rev
Log:
Remove try/catch(...) from Win32/Signals.inc.

catch(...) is used in Win32/Signals.inc for catching Win32 structured
exceptions, but according to [1], this is wrong.

We can't simply change try/catch to __try/__finally, since this syntax is not
supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1
macros on MinGW [2], but I think that that solution obfuscates the code too
much.

The use of try/catch(...) in Signals.inc makes it impossible to link
MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we
just remove try/catch(...) from Signals.inc, since the meaning of the code won't
change.

[1] http://members.cox.net/doug_web/eh.htm
[2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315

Modified:
    llvm/trunk/lib/System/Makefile
    llvm/trunk/lib/System/Win32/Signals.inc

Modified: llvm/trunk/lib/System/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Makefile?rev=117442&r1=117441&r2=117442&view=diff
==============================================================================
--- llvm/trunk/lib/System/Makefile (original)
+++ llvm/trunk/lib/System/Makefile Wed Oct 27 04:09:04 2010
@@ -11,11 +11,6 @@
 LIBRARYNAME = LLVMSystem
 BUILD_ARCHIVE = 1
 REQUIRES_RTTI = 1
-include $(LEVEL)/Makefile.config
-
-ifeq ($(HOST_OS),MingW)
-  REQUIRES_EH := 1
-endif
 
 EXTRA_DIST = Unix Win32 README.txt
 

Modified: llvm/trunk/lib/System/Win32/Signals.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Signals.inc?rev=117442&r1=117441&r2=117442&view=diff
==============================================================================
--- llvm/trunk/lib/System/Win32/Signals.inc (original)
+++ llvm/trunk/lib/System/Win32/Signals.inc Wed Oct 27 04:09:04 2010
@@ -208,8 +208,7 @@
 }
 
 static LONG WINAPI LLVMUnhandledExceptionFilter(LPEXCEPTION_POINTERS ep) {
-  try {
-    Cleanup();
+  Cleanup();
 
 #ifdef _WIN64
   // TODO: provide a x64 friendly version of the following
@@ -291,10 +290,6 @@
 
 #endif
 
-  } catch (...) {
-      assert(0 && "Crashed in LLVMUnhandledExceptionFilter");
-  }
-
   if (ExitOnUnhandledExceptions)
     _exit(-3);
 



From foldr at codedgers.com  Wed Oct 27 04:09:10 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 27 Oct 2010 09:09:10 -0000
Subject: [llvm-commits] [llvm] r117443 -
	/llvm/trunk/lib/System/Win32/Signals.inc
Message-ID: <20101027090910.409EA2A6C12D@llvm.org>

Author: foldr
Date: Wed Oct 27 04:09:10 2010
New Revision: 117443

URL: http://llvm.org/viewvc/llvm-project?rev=117443&view=rev
Log:
80-col violation.

Modified:
    llvm/trunk/lib/System/Win32/Signals.inc

Modified: llvm/trunk/lib/System/Win32/Signals.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Signals.inc?rev=117443&r1=117442&r2=117443&view=diff
==============================================================================
--- llvm/trunk/lib/System/Win32/Signals.inc (original)
+++ llvm/trunk/lib/System/Win32/Signals.inc Wed Oct 27 04:09:10 2010
@@ -247,7 +247,8 @@
       fprintf(stderr, "%08lX", PC);
 
       // Print the parameters.  Assume there are four.
-      fprintf(stderr, " (0x%08lX 0x%08lX 0x%08lX 0x%08lX)", StackFrame.Params[0],
+      fprintf(stderr, " (0x%08lX 0x%08lX 0x%08lX 0x%08lX)",
+              StackFrame.Params[0],
               StackFrame.Params[1], StackFrame.Params[2], StackFrame.Params[3]);
 
       // Verify the PC belongs to a module in this process.



From peckw at wesleypeck.com  Wed Oct 27 08:12:19 2010
From: peckw at wesleypeck.com (Wesley Peck)
Date: Wed, 27 Oct 2010 08:12:19 -0500
Subject: [llvm-commits] [llvm] r117420 - in /llvm/trunk: cmake/modules/
	lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/
	lib/Target/MBlaze/Disassembler/
In-Reply-To: <AANLkTikrBdMaz6C0i5vBApHLVU1HhrTrbi75ZqYnY+9e@mail.gmail.com>
References: <20101027002302.2AE5F2A6C12C@llvm.org>
	<AANLkTikrBdMaz6C0i5vBApHLVU1HhrTrbi75ZqYnY+9e@mail.gmail.com>
Message-ID: <2E2A8CFD-2E1B-4420-8CBF-984487A9126B@wesleypeck.com>

No problem, I'll try to be more careful about looking at the spacing in the code I commit. I'll also go through the MicroBlaze backend in the next couple of days and clean it up.

I work on another project simultaneously that uses the other style so I end up mixing the two styles together a lot :(

-- Wesley Peck

On Oct 27, 2010, at 3:38 AM, Anton Korobeynikov wrote:

> Hello Wesley,
> 
>> +  // Get the MCInst opcode from the binary instruction and make sure
>> +  // that it is a valid instruction.
>> +  unsigned opcode = getOPCODE( insn );
>> +  if( opcode == UNSUPPORTED )
>> +    return false;
> Could you please use the consistent code style in the files? E.g. no
> spaces after "(" and before ")",
> space before "(", etc.
> 
> Thanks!
> -- 
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University



From rafael.espindola at gmail.com  Wed Oct 27 09:44:52 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 14:44:52 -0000
Subject: [llvm-commits] [llvm] r117447 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20101027144452.C48642A6C12C@llvm.org>

Author: rafael
Date: Wed Oct 27 09:44:52 2010
New Revision: 117447

URL: http://llvm.org/viewvc/llvm-project?rev=117447&view=rev
Log:
Move more logic to isInSymtab and simplify.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117447&r1=117446&r2=117447&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 09:44:52 2010
@@ -441,7 +441,8 @@
   const MCSymbol *S = &Symbol;
   while (S->isVariable()) {
     const MCExpr *Value = S->getVariableValue();
-    assert (Value->getKind() == MCExpr::SymbolRef && "Unimplemented");
+    if (Value->getKind() != MCExpr::SymbolRef)
+      return *S;
     const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Value);
     S = &Ref->getSymbol();
   }
@@ -769,6 +770,11 @@
     return true;
 
   const MCSymbol &Symbol = Data.getSymbol();
+
+  const MCSymbol &A = AliasedSymbol(Symbol);
+  if (&A != &Symbol && A.isUndefined())
+    return false;
+
   if (!Asm.isSymbolLinkerVisible(Symbol) && !Symbol.isUndefined())
     return false;
 
@@ -822,20 +828,16 @@
     MSD.SymbolData = it;
     bool Local = isLocal(*it);
 
-    bool Add = false;
     if (it->isCommon()) {
       assert(!Local);
       MSD.SectionIndex = ELF::SHN_COMMON;
-      Add = true;
     } else if (Symbol.isAbsolute()) {
       MSD.SectionIndex = ELF::SHN_ABS;
-      Add = true;
     } else if (Symbol.isVariable()) {
       const MCSymbol &RefSymbol = AliasedSymbol(Symbol);
       if (RefSymbol.isDefined()) {
         MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
         assert(MSD.SectionIndex && "Invalid section index!");
-        Add = true;
       }
     } else if (Symbol.isUndefined()) {
       assert(!Local);
@@ -844,28 +846,24 @@
       // are able to set it.
       if (GetBinding(*it) == ELF::STB_LOCAL)
         SetBinding(*it, ELF::STB_GLOBAL);
-      Add = true;
     } else {
       MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
       assert(MSD.SectionIndex && "Invalid section index!");
-      Add = true;
     }
 
-    if (Add) {
-      uint64_t &Entry = StringIndexMap[Symbol.getName()];
-      if (!Entry) {
-        Entry = StringTable.size();
-        StringTable += Symbol.getName();
-        StringTable += '\x00';
-      }
-      MSD.StringIndex = Entry;
-      if (MSD.SectionIndex == ELF::SHN_UNDEF)
-        UndefinedSymbolData.push_back(MSD);
-      else if (Local)
-        LocalSymbolData.push_back(MSD);
-      else
-        ExternalSymbolData.push_back(MSD);
-    }
+    uint64_t &Entry = StringIndexMap[Symbol.getName()];
+    if (!Entry) {
+      Entry = StringTable.size();
+      StringTable += Symbol.getName();
+      StringTable += '\x00';
+    }
+    MSD.StringIndex = Entry;
+    if (MSD.SectionIndex == ELF::SHN_UNDEF)
+      UndefinedSymbolData.push_back(MSD);
+    else if (Local)
+      LocalSymbolData.push_back(MSD);
+    else
+      ExternalSymbolData.push_back(MSD);
   }
 
   // Symbols are required to be in lexicographic order.



From bigcheesegs at gmail.com  Wed Oct 27 09:53:19 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Wed, 27 Oct 2010 10:53:19 -0400
Subject: [llvm-commits] [PATCH][x86] Add support for dynamic stack probing
 on Windows x64 (Microsoft and MinGW).
Message-ID: <AANLkTi=+E8D_s35rjOy1EH4iV0tSjs6Y6_POk8jOEqxR@mail.gmail.com>

This patch adds support for stack probing alloca instructions with a
variable size on x86-64.

- Michael Spencer
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From jolesen at apple.com  Tue Oct 26 14:48:06 2010
From: jolesen at apple.com (Jakob Olesen)
Date: Tue, 26 Oct 2010 12:48:06 -0700
Subject: [llvm-commits] [llvm] r117174 - in /llvm/trunk:
	include/llvm/CodeGen/LinkAllCodegenComponents.h
	include/llvm/CodeGen/Passes.h lib/CodeGen/CMakeLists.txt
	lib/CodeGen/LiveIntervalUnion.cpp
	lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h
	lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/SplitKit.h
In-Reply-To: <9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
References: <20101022230915.AB8EF2A6C12C@llvm.org>
	<99E538D4-57C7-411A-8277-FF3D6D0D6AFD@2pi.dk>
	<9E71992E-7A07-4D8E-9D30-717F02F210FE@apple.com>
Message-ID: <C0F0FE38-B27F-49F4-85BD-88D92C39CB69@apple.com>


On Oct 26, 2010, at 11:37 AM, Andrew Trick wrote:

> On Oct 25, 2010, at 2:58 PM, Jakob Stoklund Olesen wrote:
>>> +#include "llvm/CodeGen/LiveInterval.h"
>> 
>> Do you need this header? It looks like SlotIndexes.h is enough.
> 
> We could do that by moving certain inline functions, like overlap() into LiveIntervalUnion.cpp. But it only ever makes sense for LiveIntervalUnion users to include LiveInterval, so is it worth scattering the methods?

No. Keep it.

>>> Added: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=117174&view=auto
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (added)
>>> +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Oct 22 18:09:15 2010
>>> @@ -0,0 +1,259 @@
>> 
>>> +class RABasic : public MachineFunctionPass, public RegAllocBase
>> 
>> Instead of using multiple inheritance, would it make sense for RegAllocBase to be a MachineFunctionPass? It seems that any register allocator using RegAllocBase would need the same pass initialization code and so on.
> 
> I was also tempted to make RegAlloc an abstract MachineFunctionPass. In fact I originally did that, and it was a bit easier write the code. But I want to give you some time to reconsider, because I don't think that design follows what you originally asked for: an implementation of the basic allocation pass that would never change and serve as a clean reference point and boilerplate code for extensions. It will be easier for others to understand the design and how to extend it if we keep RegAllocBase pure so that it only handles logic fundamental to the register allocation data structures and algorithms. Each regalloc subclass is a different type of pass, so it is responsible for all pass-related implementation. If RegAllocBase is derived from MachineFunctionPass then it will implement some of the pass setup and dependencies and the subclasses will each have to figure out what's left over and add any new dependencies--I think that's bad design and leads to scattered implementation.

Alright.

Let's leave it as is, and change it if it causes problems.

/jakob



From rafael.espindola at gmail.com  Wed Oct 27 10:18:17 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 15:18:17 -0000
Subject: [llvm-commits] [llvm] r117448 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp lib/MC/MCParser/ELFAsmParser.cpp
 test/MC/ELF/symref.s
Message-ID: <20101027151818.0AD232A6C12C@llvm.org>

Author: rafael
Date: Wed Oct 27 10:18:17 2010
New Revision: 117448

URL: http://llvm.org/viewvc/llvm-project?rev=117448&view=rev
Log:
Add support for the .symver directive. This is really ugly, but most of it is
contained in the ELF object writer.

Added:
    llvm/trunk/test/MC/ELF/symref.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117448&r1=117447&r2=117448&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 10:18:17 2010
@@ -134,6 +134,7 @@
     };
 
     SmallPtrSet<const MCSymbol *, 16> UsedInReloc;
+    DenseMap<const MCSymbol *, const MCSymbol *> Renames;
 
     llvm::DenseMap<const MCSectionData*,
                    std::vector<ELFRelocationEntry> > Relocations;
@@ -292,8 +293,7 @@
 
     void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout);
 
-    void ExecutePostLayoutBinding(MCAssembler &Asm) {
-    }
+    void ExecutePostLayoutBinding(MCAssembler &Asm);
 
     void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags,
                           uint64_t Address, uint64_t Offset,
@@ -449,6 +449,30 @@
   return *S;
 }
 
+void ELFObjectWriterImpl::ExecutePostLayoutBinding(MCAssembler &Asm) {
+  // The presence of symbol versions causes undefined symbols and
+  // versions declared with @@@ to be renamed.
+
+  for (MCAssembler::symbol_iterator it = Asm.symbol_begin(),
+         ie = Asm.symbol_end(); it != ie; ++it) {
+    const MCSymbol &Alias = it->getSymbol();
+    if (!Alias.isVariable())
+      continue;
+    const MCSymbol &Symbol = AliasedSymbol(Alias);
+    const StringRef &AliasName = Alias.getName();
+    size_t Pos = AliasName.find('@');
+    if (Pos == StringRef::npos)
+      continue;
+
+    StringRef Rest(AliasName.begin() + Pos);
+    if (!Symbol.isUndefined() && !Rest.startswith("@@@"))
+      continue;
+
+    std::pair<const MCSymbol *, const MCSymbol *> t(&Symbol, &Alias);
+    Renames.insert(t);
+  }
+}
+
 void ELFObjectWriterImpl::WriteSymbol(MCDataFragment *F, ELFSymbolData &MSD,
                                       const MCAsmLayout &Layout) {
   MCSymbolData &OrigData = *MSD.SymbolData;
@@ -593,6 +617,9 @@
   bool IsPCRel = isFixupKindX86PCRel(Fixup.getKind());
   if (!Target.isAbsolute()) {
     Symbol = &AliasedSymbol(Target.getSymA()->getSymbol());
+    const MCSymbol *Renamed = Renames.lookup(Symbol);
+    if (Renamed)
+      Symbol = Renamed;
     MCSymbolData &SD = Asm.getSymbolData(*Symbol);
     MCFragment *F = SD.getFragment();
 
@@ -765,10 +792,13 @@
 }
 
 static bool isInSymtab(const MCAssembler &Asm, const MCSymbolData &Data,
-                       bool Used) {
+                       bool Used, bool Renamed) {
   if (Used)
     return true;
 
+  if (Renamed)
+    return false;
+
   const MCSymbol &Symbol = Data.getSymbol();
 
   const MCSymbol &A = AliasedSymbol(Symbol);
@@ -821,40 +851,52 @@
          ie = Asm.symbol_end(); it != ie; ++it) {
     const MCSymbol &Symbol = it->getSymbol();
 
-    if (!isInSymtab(Asm, *it, UsedInReloc.count(&Symbol)))
+    if (!isInSymtab(Asm, *it, UsedInReloc.count(&Symbol),
+                    Renames.count(&Symbol)))
       continue;
 
     ELFSymbolData MSD;
     MSD.SymbolData = it;
     bool Local = isLocal(*it);
+    const MCSymbol &RefSymbol = AliasedSymbol(Symbol);
 
     if (it->isCommon()) {
       assert(!Local);
       MSD.SectionIndex = ELF::SHN_COMMON;
     } else if (Symbol.isAbsolute()) {
       MSD.SectionIndex = ELF::SHN_ABS;
-    } else if (Symbol.isVariable()) {
-      const MCSymbol &RefSymbol = AliasedSymbol(Symbol);
-      if (RefSymbol.isDefined()) {
-        MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
-        assert(MSD.SectionIndex && "Invalid section index!");
-      }
-    } else if (Symbol.isUndefined()) {
-      assert(!Local);
+    } else if (RefSymbol.isUndefined()) {
       MSD.SectionIndex = ELF::SHN_UNDEF;
       // FIXME: Undefined symbols are global, but this is the first place we
       // are able to set it.
       if (GetBinding(*it) == ELF::STB_LOCAL)
         SetBinding(*it, ELF::STB_GLOBAL);
+    } else if (Symbol.isVariable()) {
+      MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
+      assert(MSD.SectionIndex && "Invalid section index!");
     } else {
       MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
       assert(MSD.SectionIndex && "Invalid section index!");
     }
 
-    uint64_t &Entry = StringIndexMap[Symbol.getName()];
+    // The @@@ in symbol version is replaced with @ in undefined symbols and
+    // @@ in defined ones.
+    StringRef Name = Symbol.getName();
+    size_t Pos = Name.find("@@@");
+    std::string FinalName;
+    if (Pos != StringRef::npos) {
+      StringRef Prefix(Name.begin(), Pos);
+      unsigned n = MSD.SectionIndex == ELF::SHN_UNDEF ? 2 : 1;
+      StringRef Suffix(Name.begin() + Pos + n);
+      FinalName = Prefix.str() + Suffix.str();
+    } else {
+      FinalName = Name.str();
+    }
+
+    uint64_t &Entry = StringIndexMap[FinalName];
     if (!Entry) {
       Entry = StringTable.size();
-      StringTable += Symbol.getName();
+      StringTable += FinalName;
       StringTable += '\x00';
     }
     MSD.StringIndex = Entry;

Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=117448&r1=117447&r2=117448&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Wed Oct 27 10:18:17 2010
@@ -12,6 +12,7 @@
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
@@ -51,6 +52,7 @@
     AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous");
     AddDirectiveHandler<&ELFAsmParser::ParseDirectiveType>(".type");
     AddDirectiveHandler<&ELFAsmParser::ParseDirectiveIdent>(".ident");
+    AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymver>(".symver");
   }
 
   // FIXME: Part of this logic is duplicated in the MCELFStreamer. What is
@@ -116,6 +118,7 @@
   bool ParseDirectivePrevious(StringRef, SMLoc);
   bool ParseDirectiveType(StringRef, SMLoc);
   bool ParseDirectiveIdent(StringRef, SMLoc);
+  bool ParseDirectiveSymver(StringRef, SMLoc);
 
 private:
   bool ParseSectionName(StringRef &SectionName);
@@ -377,6 +380,33 @@
   return false;
 }
 
+/// ParseDirectiveSymver
+///  ::= .symver foo, bar2 at zed
+bool ELFAsmParser::ParseDirectiveSymver(StringRef, SMLoc) {
+  StringRef Name;
+  if (getParser().ParseIdentifier(Name))
+    return TokError("expected identifier in directive");
+
+  if (getLexer().isNot(AsmToken::Comma))
+    return TokError("expected a comma");
+
+  Lex();
+
+  StringRef AliasName;
+  if (getParser().ParseIdentifier(AliasName))
+    return TokError("expected identifier in directive");
+
+  if (AliasName.find('@') == StringRef::npos)
+    return TokError("expected a '@' in the name");
+
+  MCSymbol *Alias = getContext().GetOrCreateSymbol(AliasName);
+  MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
+  const MCExpr *Value = MCSymbolRefExpr::Create(Sym, getContext());
+
+  getStreamer().EmitAssignment(Alias, Value);
+  return false;
+}
+
 namespace llvm {
 
 MCAsmParserExtension *createELFAsmParser() {

Added: llvm/trunk/test/MC/ELF/symref.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/symref.s?rev=117448&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/symref.s (added)
+++ llvm/trunk/test/MC/ELF/symref.s Wed Oct 27 10:18:17 2010
@@ -0,0 +1,142 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  | FileCheck %s
+
+defined1:
+defined2:
+defined3:
+        .symver defined1, bar1 at zed
+        .symver undefined1, bar2 at zed
+
+        .symver defined2, bar3@@zed
+
+        .symver defined3, bar5@@@zed
+        .symver undefined3, bar6@@@zed
+
+        .long defined1
+        .long undefined1
+        .long defined2
+        .long defined3
+        .long undefined3
+
+// CHECK:      # Symbol 0x00000001
+// CHECK-NEXT: (('st_name', 0x00000013) # 'bar1 at zed'
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000001)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000002
+// CHECK-NEXT: (('st_name', 0x00000025) # 'bar3@@zed'
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000001)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000003
+// CHECK-NEXT: (('st_name', 0x0000002f) # 'bar5@@zed'
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000001)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000004
+// CHECK-NEXT: (('st_name', 0x00000001) # 'defined1'
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000001)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000005
+// CHECK-NEXT: (('st_name', 0x0000000a) # 'defined2'
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000001)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000006
+// CHECK-NEXT: (('st_name', 0x00000000) # ''
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000003)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000001)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000007
+// CHECK-NEXT: (('st_name', 0x00000000) # ''
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000003)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000002)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000008
+// CHECK-NEXT: (('st_name', 0x00000000) # ''
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000003)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000003)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x00000009
+// CHECK-NEXT: (('st_name', 0x0000001c) # 'bar2 at zed'
+// CHECK-NEXT:  ('st_bind', 0x00000001)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000000)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Symbol 0x0000000a
+// CHECK-NEXT: (('st_name', 0x00000039) # 'bar6 at zed'
+// CHECK-NEXT:  ('st_bind', 0x00000001)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x00000000)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT:])
+
+// CHECK:      # Relocation 0x00000000
+// CHECK-NEXT: (('r_offset', 0x00000000)
+// CHECK-NEXT:  ('r_sym', 0x00000006)
+// CHECK-NEXT:  ('r_type', 0x0000000a)
+// CHECK-NEXT:  ('r_addend', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Relocation 0x00000001
+// CHECK-NEXT: (('r_offset', 0x00000004)
+// CHECK-NEXT:  ('r_sym', 0x00000009)
+// CHECK-NEXT:  ('r_type', 0x0000000a)
+// CHECK-NEXT:  ('r_addend', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Relocation 0x00000002
+// CHECK-NEXT: (('r_offset', 0x00000008)
+// CHECK-NEXT:  ('r_sym', 0x00000006)
+// CHECK-NEXT:  ('r_type', 0x0000000a)
+// CHECK-NEXT:  ('r_addend', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Relocation 0x00000003
+// CHECK-NEXT: (('r_offset', 0x0000000c)
+// CHECK-NEXT:  ('r_sym', 0x00000006)
+// CHECK-NEXT:  ('r_type', 0x0000000a)
+// CHECK-NEXT:  ('r_addend', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Relocation 0x00000004
+// CHECK-NEXT: (('r_offset', 0x00000010)
+// CHECK-NEXT:  ('r_sym', 0x0000000a)
+// CHECK-NEXT:  ('r_type', 0x0000000a)
+// CHECK-NEXT:  ('r_addend', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT:])



From rafael.espindola at gmail.com  Wed Oct 27 11:04:30 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 16:04:30 -0000
Subject: [llvm-commits] [llvm] r117451 - in /llvm/trunk:
	lib/MC/ELFObjectWriter.cpp test/MC/ELF/abs.s
Message-ID: <20101027160430.918C52A6C12C@llvm.org>

Author: rafael
Date: Wed Oct 27 11:04:30 2010
New Revision: 117451

URL: http://llvm.org/viewvc/llvm-project?rev=117451&view=rev
Log:
Symbols defined as the difference of other two end up in the ABS section.

Added:
    llvm/trunk/test/MC/ELF/abs.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117451&r1=117450&r2=117451&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 11:04:30 2010
@@ -863,7 +863,7 @@
     if (it->isCommon()) {
       assert(!Local);
       MSD.SectionIndex = ELF::SHN_COMMON;
-    } else if (Symbol.isAbsolute()) {
+    } else if (Symbol.isAbsolute() || RefSymbol.isVariable()) {
       MSD.SectionIndex = ELF::SHN_ABS;
     } else if (RefSymbol.isUndefined()) {
       MSD.SectionIndex = ELF::SHN_UNDEF;
@@ -871,11 +871,8 @@
       // are able to set it.
       if (GetBinding(*it) == ELF::STB_LOCAL)
         SetBinding(*it, ELF::STB_GLOBAL);
-    } else if (Symbol.isVariable()) {
-      MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
-      assert(MSD.SectionIndex && "Invalid section index!");
     } else {
-      MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
+      MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
       assert(MSD.SectionIndex && "Invalid section index!");
     }
 

Added: llvm/trunk/test/MC/ELF/abs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/abs.s?rev=117451&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/abs.s (added)
+++ llvm/trunk/test/MC/ELF/abs.s Wed Oct 27 11:04:30 2010
@@ -0,0 +1,16 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  | FileCheck %s
+
+// Test that zed will be an ABS symbol
+
+.Lfoo:
+.Lbar:
+        zed = .Lfoo - .Lbar
+
+// CHECK:      # Symbol 0x00000001
+// CHECK-NEXT: (('st_name', 0x00000001) # 'zed'
+// CHECK-NEXT:  ('st_bind', 0x00000000)
+// CHECK-NEXT:  ('st_type', 0x00000000)
+// CHECK-NEXT:  ('st_other', 0x00000000)
+// CHECK-NEXT:  ('st_shndx', 0x0000fff1)
+// CHECK-NEXT:  ('st_value', 0x00000000)
+// CHECK-NEXT:  ('st_size', 0x00000000)



From grosbach at apple.com  Wed Oct 27 11:30:19 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 16:30:19 -0000
Subject: [llvm-commits] [llvm] r117453 -
	/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
Message-ID: <20101027163019.1543A2A6C12C@llvm.org>

Author: grosbach
Date: Wed Oct 27 11:30:18 2010
New Revision: 117453

URL: http://llvm.org/viewvc/llvm-project?rev=117453&view=rev
Log:
Formatting.

Modified:
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=117453&r1=117452&r2=117453&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Oct 27 11:30:18 2010
@@ -759,8 +759,8 @@
           // If this instruction has a FrameIndex operand, we need to
           // use that target machine register info object to eliminate
           // it.
-            TRI.eliminateFrameIndex(MI, SPAdj,
-                                    FrameIndexVirtualScavenging ?  NULL : RS);
+          TRI.eliminateFrameIndex(MI, SPAdj,
+                                  FrameIndexVirtualScavenging ?  NULL : RS);
 
           // Reset the iterator if we were at the beginning of the BB.
           if (AtBeginning) {



From grosbach at apple.com  Wed Oct 27 11:50:31 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 16:50:31 -0000
Subject: [llvm-commits] [llvm] r117454 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20101027165031.A4B3F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Oct 27 11:50:31 2010
New Revision: 117454

URL: http://llvm.org/viewvc/llvm-project?rev=117454&view=rev
Log:
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117454&r1=117453&r2=117454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 27 11:50:31 2010
@@ -1435,8 +1435,12 @@
 
       // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
       ImmedOffset = ImmedOffset & Mask;
-      if (isSub)
-        ImmedOffset |= 1 << NumBits;
+      if (isSub) {
+        if (AddrMode == ARMII::AddrMode_i12)
+          ImmedOffset = -ImmedOffset;
+        else
+          ImmedOffset |= 1 << NumBits;
+      }
       ImmOp.ChangeToImmediate(ImmedOffset);
       Offset &= ~(Mask*Scale);
     }



From criswell at uiuc.edu  Wed Oct 27 12:01:24 2010
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 27 Oct 2010 17:01:24 -0000
Subject: [llvm-commits] [poolalloc] r117455 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20101027170124.5F7B72A6C12C@llvm.org>

Author: criswell
Date: Wed Oct 27 12:01:24 2010
New Revision: 117455

URL: http://llvm.org/viewvc/llvm-project?rev=117455&view=rev
Log:
Corrected spelling of getActualValue() call.

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=117455&r1=117454&r2=117455&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Wed Oct 27 12:01:24 2010
@@ -395,7 +395,7 @@
   processRuntimeCheck (M, "sc.boundscheck");
   processRuntimeCheck (M, "sc.boundscheckui");
   processRuntimeCheck (M, "sc.exactcheck2");
-  processRuntimeCheck (M, "sc.get_actual_value");
+  processRuntimeCheck (M, "sc.get_actual_val");
 
   // In Local we marked nodes passed to/returned from 'StdLib' functions as External, because at
   // that point they were.  However they no longer are necessarily so, and we need to update accordingly.



From resistor at mac.com  Wed Oct 27 12:29:29 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 17:29:29 -0000
Subject: [llvm-commits] [llvm] r117458 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shiftaccum-encoding.ll
Message-ID: <20101027172930.08B7D2A6C130@llvm.org>

Author: resistor
Date: Wed Oct 27 12:29:29 2010
New Revision: 117458

URL: http://llvm.org/viewvc/llvm-project?rev=117458&view=rev
Log:
Add correct NEON encodings for vsra and vrsra.

Added:
    llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117458&r1=117457&r2=117458&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Oct 27 12:29:29 2010
@@ -1730,18 +1730,18 @@
 // both double- and quad-register.
 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
-  : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
-           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
-           OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
-           [(set DPR:$dst, (Ty (add DPR:$src1,
-                                (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
+  : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
+           (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
+           OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+           [(set DPR:$Vd, (Ty (add DPR:$src1,
+                                (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
-  : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
-           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
-           OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
-           [(set QPR:$dst, (Ty (add QPR:$src1,
-                                (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
+  : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
+           (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
+           OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+           [(set QPR:$Vd, (Ty (add QPR:$src1,
+                                (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
 
 // Shift by immediate and insert,
 // both double- and quad-register.

Added: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll?rev=117458&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll Wed Oct 27 12:29:29 2010
@@ -0,0 +1,309 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vsra.s8	d16, d17, #8            @ encoding: [0x31,0x01,0xc8,0xf2]
+	%tmp3 = ashr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+        %tmp4 = add <8 x i8> %tmp1, %tmp3
+	ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vsra.s16	d16, d17, #16   @ encoding: [0x31,0x01,0xd0,0xf2]
+	%tmp3 = ashr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 >
+        %tmp4 = add <4 x i16> %tmp1, %tmp3
+	ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vsra.s32	d16, d17, #32   @ encoding: [0x31,0x01,0xe0,0xf2]
+	%tmp3 = ashr <2 x i32> %tmp2, < i32 32, i32 32 >
+        %tmp4 = add <2 x i32> %tmp1, %tmp3
+	ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vsra.s64	d16, d17, #64   @ encoding: [0xb1,0x01,0xc0,0xf2]
+	%tmp3 = ashr <1 x i64> %tmp2, < i64 64 >
+        %tmp4 = add <1 x i64> %tmp1, %tmp3
+	ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vsra.s8	q9, q8, #8              @ encoding: [0x70,0x21,0xc8,0xf2]
+	%tmp3 = ashr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+        %tmp4 = add <16 x i8> %tmp1, %tmp3
+	ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vsra.s16	q9, q8, #16     @ encoding: [0x70,0x21,0xd0,0xf2]
+	%tmp3 = ashr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+        %tmp4 = add <8 x i16> %tmp1, %tmp3
+	ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vsra.s32	q9, q8, #32     @ encoding: [0x70,0x21,0xe0,0xf2]
+	%tmp3 = ashr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 >
+        %tmp4 = add <4 x i32> %tmp1, %tmp3
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vsra.s64	q9, q8, #64     @ encoding: [0xf0,0x21,0xc0,0xf2]
+	%tmp3 = ashr <2 x i64> %tmp2, < i64 64, i64 64 >
+        %tmp4 = add <2 x i64> %tmp1, %tmp3
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vsra.u8	d16, d17, #8            @ encoding: [0x31,0x01,0xc8,0xf3]
+	%tmp3 = lshr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+        %tmp4 = add <8 x i8> %tmp1, %tmp3
+	ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vsra.u16	d16, d17, #16   @ encoding: [0x31,0x01,0xd0,0xf3]
+	%tmp3 = lshr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 >
+        %tmp4 = add <4 x i16> %tmp1, %tmp3
+	ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vsra.u32	d16, d17, #32   @ encoding: [0x31,0x01,0xe0,0xf3]
+	%tmp3 = lshr <2 x i32> %tmp2, < i32 32, i32 32 >
+        %tmp4 = add <2 x i32> %tmp1, %tmp3
+	ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vsra.u64	d16, d17, #64   @ encoding: [0xb1,0x01,0xc0,0xf3]
+	%tmp3 = lshr <1 x i64> %tmp2, < i64 64 >
+        %tmp4 = add <1 x i64> %tmp1, %tmp3
+	ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vsra.u8	q9, q8, #8              @ encoding: [0x70,0x21,0xc8,0xf3]
+	%tmp3 = lshr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+        %tmp4 = add <16 x i8> %tmp1, %tmp3
+	ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vsra.u16	q9, q8, #16     @ encoding: [0x70,0x21,0xd0,0xf3]
+	%tmp3 = lshr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+        %tmp4 = add <8 x i16> %tmp1, %tmp3
+	ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vsra.u32	q9, q8, #32     @ encoding: [0x70,0x21,0xe0,0xf3]
+	%tmp3 = lshr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 >
+        %tmp4 = add <4 x i32> %tmp1, %tmp3
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vsra.u64	q9, q8, #64     @ encoding: [0xf0,0x21,0xc0,0xf3]
+	%tmp3 = lshr <2 x i64> %tmp2, < i64 64, i64 64 >
+        %tmp4 = add <2 x i64> %tmp1, %tmp3
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vrsra.s8	d16, d17, #8    @ encoding: [0x31,0x03,0xc8,0xf2]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+        %tmp4 = add <8 x i8> %tmp1, %tmp3
+	ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vrsra.s16	d16, d17, #16   @ encoding: [0x31,0x03,0xd0,0xf2]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+        %tmp4 = add <4 x i16> %tmp1, %tmp3
+	ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vrsra.s32	d16, d17, #32   @ encoding: [0x31,0x03,0xe0,0xf2]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
+        %tmp4 = add <2 x i32> %tmp1, %tmp3
+	ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vrsra.s64	d16, d17, #64   @ encoding: [0xb1,0x03,0xc0,0xf2]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
+        %tmp4 = add <1 x i64> %tmp1, %tmp3
+	ret <1 x i64> %tmp4
+}
+
+define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vrsra.u8	d16, d17, #8    @ encoding: [0x31,0x03,0xc8,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+        %tmp4 = add <8 x i8> %tmp1, %tmp3
+	ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vrsra.u16	d16, d17, #16   @ encoding: [0x31,0x03,0xd0,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+        %tmp4 = add <4 x i16> %tmp1, %tmp3
+	ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vrsra.u32	d16, d17, #32   @ encoding: [0x31,0x03,0xe0,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
+        %tmp4 = add <2 x i32> %tmp1, %tmp3
+	ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vrsra.u64	d16, d17, #64   @ encoding: [0xb1,0x03,0xc0,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
+        %tmp4 = add <1 x i64> %tmp1, %tmp3
+	ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vrsra.s8	q9, q8, #8      @ encoding: [0x70,0x23,0xc8,0xf2]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+        %tmp4 = add <16 x i8> %tmp1, %tmp3
+	ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vrsra.s16	q9, q8, #16     @ encoding: [0x70,0x23,0xd0,0xf2]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+        %tmp4 = add <8 x i16> %tmp1, %tmp3
+	ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vrsra.s32	q9, q8, #32     @ encoding: [0x70,0x23,0xe0,0xf2]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+        %tmp4 = add <4 x i32> %tmp1, %tmp3
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vrsra.s64	q9, q8, #64     @ encoding: [0xf0,0x23,0xc0,0xf2]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
+        %tmp4 = add <2 x i64> %tmp1, %tmp3
+	ret <2 x i64> %tmp4
+}
+
+define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vrsra.u8	q9, q8, #8      @ encoding: [0x70,0x23,0xc8,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+        %tmp4 = add <16 x i8> %tmp1, %tmp3
+	ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vrsra.u16	q9, q8, #16     @ encoding: [0x70,0x23,0xd0,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+        %tmp4 = add <8 x i16> %tmp1, %tmp3
+	ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vrsra.u32	q9, q8, #32     @ encoding: [0x70,0x23,0xe0,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+        %tmp4 = add <4 x i32> %tmp1, %tmp3
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vrsra.u64	q9, q8, #64     @ encoding: [0xf0,0x23,0xc0,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
+        %tmp4 = add <2 x i64> %tmp1, %tmp3
+	ret <2 x i64> %tmp4
+}
+
+declare <8 x i8>  @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone



From resistor at mac.com  Wed Oct 27 12:40:09 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 17:40:09 -0000
Subject: [llvm-commits] [llvm] r117459 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shiftaccum-encoding.ll
Message-ID: <20101027174009.2B0222A6C130@llvm.org>

Author: resistor
Date: Wed Oct 27 12:40:08 2010
New Revision: 117459

URL: http://llvm.org/viewvc/llvm-project?rev=117459&view=rev
Log:
Add correct NEON encodings for vsli and vsri.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117459&r1=117458&r2=117459&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Oct 27 12:40:08 2010
@@ -1747,16 +1747,16 @@
 // both double- and quad-register.
 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
-  : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
-           (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
-           OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
-           [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
+  : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
+           (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
+           OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+           [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
                 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
-  : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
-           (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
-           OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
-           [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
+  : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
+           (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
+           OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+           [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
 
 // Convert, with fractional bits immediate,
 // both double- and quad-register.

Modified: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll?rev=117459&r1=117458&r2=117459&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll Wed Oct 27 12:40:08 2010
@@ -307,3 +307,141 @@
 declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
 declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vsli.8	d17, d16, #7            @ encoding: [0x30,0x15,0xcf,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vsli.16	d17, d16, #15           @ encoding: [0x30,0x15,0xdf,0xf3]
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+	ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vsli.32	d17, d16, #31           @ encoding: [0x30,0x15,0xff,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
+	ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vsli.64	d17, d16, #63           @ encoding: [0xb0,0x15,0xff,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
+	ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vsli.8	q8, q9, #7              @ encoding: [0x72,0x05,0xcf,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vsli.16	q8, q9, #15             @ encoding: [0x72,0x05,0xdf,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+	ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vsli.32	q8, q9, #31             @ encoding: [0x72,0x05,0xff,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vsli.64	q8, q9, #63             @ encoding: [0xf2,0x05,0xff,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
+	ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+	%tmp2 = load <8 x i8>* %B
+; CHECK: vsri.8	d17, d16, #8            @ encoding: [0x30,0x14,0xc8,0xf3]
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+	ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = load <4 x i16>* %B
+; CHECK: vsri.16	d17, d16, #16           @ encoding: [0x30,0x14,0xd0,0xf3
+	%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+	ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = load <2 x i32>* %B
+; CHECK: vsri.32	d17, d16, #32           @ encoding: [0x30,0x14,0xe0,0xf3]
+	%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
+	ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+	%tmp1 = load <1 x i64>* %A
+	%tmp2 = load <1 x i64>* %B
+; CHECK: vsri.64	d17, d16, #64           @ encoding: [0xb0,0x14,0xc0,0xf3]
+	%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
+	ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+	%tmp2 = load <16 x i8>* %B
+; CHECK: vsri.8	q8, q9, #8              @ encoding: [0x72,0x04,0xc8,0xf3]
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i16>* %B
+; CHECK: vsri.16	q8, q9, #16             @ encoding: [0x72,0x04,0xd0,0xf3]
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+	ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i32>* %B
+; CHECK: vsri.32	q8, q9, #32             @ encoding: [0x72,0x04,0xe0,0xf3]
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i64>* %B
+; CHECK: vsri.64	q8, q9, #64             @ encoding: [0xf2,0x04,0xc0,0xf3]
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
+	ret <2 x i64> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone



From rdivacky at freebsd.org  Wed Oct 27 12:44:21 2010
From: rdivacky at freebsd.org (Roman Divacky)
Date: Wed, 27 Oct 2010 19:44:21 +0200
Subject: [llvm-commits] [PATCH]: .equ parsing in AsmParser
Message-ID: <20101027174421.GA24109@freebsd.org>

hi,

the attached patch implementes .equ parsing. .equ is a synonym
to .set so this was really easy :)

please review this so I can commit that

thank you! roman
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From resistor at mac.com  Wed Oct 27 12:50:08 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 17:50:08 -0000
Subject: [llvm-commits] [llvm] r117460 -
	/llvm/trunk/test/MC/ARM/neon-abs-encoding.ll
Message-ID: <20101027175008.1FBB62A6C130@llvm.org>

Author: resistor
Date: Wed Oct 27 12:50:07 2010
New Revision: 117460

URL: http://llvm.org/viewvc/llvm-project?rev=117460&view=rev
Log:
Tests for NEON encoding of vabs and vqabs.

Added:
    llvm/trunk/test/MC/ARM/neon-abs-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-abs-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-abs-encoding.ll?rev=117460&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-abs-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-abs-encoding.ll Wed Oct 27 12:50:07 2010
@@ -0,0 +1,117 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vabs.s8	d16, d16                @ encoding: [0x20,0x03,0xf1,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vabs.s16	d16, d16        @ encoding: [0x20,0x03,0xf5,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vabs.s32	d16, d16        @ encoding: [0x20,0x03,0xf9,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vabs.f32	d16, d16        @ encoding: [0x20,0x07,0xf9,0xf3]
+	%tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
+	ret <2 x float> %tmp2
+}
+
+define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vabs.s8	q8, q8                  @ encoding: [0x60,0x03,0xf1,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vabs.s16	q8, q8          @ encoding: [0x60,0x03,0xf5,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vabs.s32	q8, q8          @ encoding: [0x60,0x03,0xf9,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vabs.f32	q8, q8          @ encoding: [0x60,0x07,0xf9,0xf3]
+	%tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
+	ret <4 x float> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
+
+define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vqabs.s8	d16, d16        @ encoding: [0x20,0x07,0xf0,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vqabs.s16	d16, d16        @ encoding: [0x20,0x07,0xf4,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vqabs.s32	d16, d16        @ encoding: [0x20,0x07,0xf8,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vqabs.s8	q8, q8          @ encoding: [0x60,0x07,0xf0,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqabs.s16	q8, q8          @ encoding: [0x60,0x07,0xf4,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqabs.s32	q8, q8          @ encoding: [0x60,0x07,0xf8,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone



From grosbach at apple.com  Wed Oct 27 12:52:51 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 17:52:51 -0000
Subject: [llvm-commits] [llvm] r117461 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20101027175251.5E2182A6C130@llvm.org>

Author: grosbach
Date: Wed Oct 27 12:52:51 2010
New Revision: 117461

URL: http://llvm.org/viewvc/llvm-project?rev=117461&view=rev
Log:
The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117461&r1=117460&r2=117461&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Oct 27 12:52:51 2010
@@ -946,6 +946,13 @@
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
+  // If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done.
+  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs
+      || MI.getOpcode() == ARM::LDRcp) {
+    emitWordLE(Binary);
+    return;
+  }
+
   // Set the conditional execution predicate
   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 



From gohman at apple.com  Wed Oct 27 12:57:45 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 27 Oct 2010 10:57:45 -0700
Subject: [llvm-commits] PATCH: new Value::getThruSplat API
In-Reply-To: <4CC7C7F9.9050806@mxc.ca>
References: <4CC7C7F9.9050806@mxc.ca>
Message-ID: <343AA845-309E-4A08-A29D-181ABDFDBC36@apple.com>


On Oct 26, 2010, at 11:34 PM, Nick Lewycky wrote:

> This patch adds a new method on Value called getThruSplat() which returns the splatted value iff this is a ConstantValue with a splat, or 'this' otherwise. I demonstrate its usage by updating InstructionSimplify to uniformly handle splat vectors alongside ConstantInt values.

Looks reasonable to me.

How about "getScalarValue" instead of "getThruSplat"?
I don't have strong opinions about it though.

Dan



From rafael.espindola at gmail.com  Wed Oct 27 12:56:18 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 17:56:18 -0000
Subject: [llvm-commits] [llvm] r117462 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/invalid-symver.s
Message-ID: <20101027175618.4E3AE2A6C130@llvm.org>

Author: rafael
Date: Wed Oct 27 12:56:18 2010
New Revision: 117462

URL: http://llvm.org/viewvc/llvm-project?rev=117462&view=rev
Log:
Produce an error for an invalid use of .symver.

Added:
    llvm/trunk/test/MC/ELF/invalid-symver.s
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117462&r1=117461&r2=117462&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 12:56:18 2010
@@ -468,6 +468,11 @@
     if (!Symbol.isUndefined() && !Rest.startswith("@@@"))
       continue;
 
+    // FIXME: produce a better error message.
+    if (Symbol.isUndefined() && Rest.startswith("@@") &&
+        !Rest.startswith("@@@"))
+      report_fatal_error("A @@ version cannot be undefined");
+
     std::pair<const MCSymbol *, const MCSymbol *> t(&Symbol, &Alias);
     Renames.insert(t);
   }

Added: llvm/trunk/test/MC/ELF/invalid-symver.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/invalid-symver.s?rev=117462&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/invalid-symver.s (added)
+++ llvm/trunk/test/MC/ELF/invalid-symver.s Wed Oct 27 12:56:18 2010
@@ -0,0 +1,7 @@
+// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t 2> %t.out
+// RUN: FileCheck --input-file=%t.out %s
+
+// CHECK: A @@ version cannot be undefined
+
+        .symver undefined, foo@@bar
+        .long undefined



From resistor at mac.com  Wed Oct 27 12:57:26 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 17:57:26 -0000
Subject: [llvm-commits] [llvm] r117463 -
	/llvm/trunk/test/MC/ARM/neon-neg-encoding.ll
Message-ID: <20101027175726.27B182A6C130@llvm.org>

Author: resistor
Date: Wed Oct 27 12:57:26 2010
New Revision: 117463

URL: http://llvm.org/viewvc/llvm-project?rev=117463&view=rev
Log:
Tests for NEON encoding of vneg and vqneg.

Added:
    llvm/trunk/test/MC/ARM/neon-neg-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-neg-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-neg-encoding.ll?rev=117463&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-neg-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-neg-encoding.ll Wed Oct 27 12:57:26 2010
@@ -0,0 +1,107 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vneg.s8	d16, d16                @ encoding: [0xa0,0x03,0xf1,0xf3]
+	%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vneg.s16	d16, d16        @ encoding: [0xa0,0x03,0xf5,0xf3
+	%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vneg.s32	d16, d16        @ encoding: [0xa0,0x03,0xf9,0xf3]
+	%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
+	ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vneg.f32	d16, d16        @ encoding: [0xa0,0x07,0xf9,0xf3]
+	%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
+	ret <2 x float> %tmp2
+}
+
+define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vneg.s8	q8, q8                  @ encoding: [0xe0,0x03,0xf1,0xf3]
+	%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vneg.s16	q8, q8          @ encoding: [0xe0,0x03,0xf5,0xf3]
+	%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vneg.s32	q8, q8          @ encoding: [0xe0,0x03,0xf9,0xf3]
+	%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
+	ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vneg.f32	q8, q8          @ encoding: [0xe0,0x07,0xf9,0xf3]
+	%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
+	ret <4 x float> %tmp2
+}
+
+define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vqneg.s8	d16, d16        @ encoding: [0xa0,0x07,0xf0,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vqneg.s16	d16, d16        @ encoding: [0xa0,0x07,0xf4,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vqneg.s32	d16, d16        @ encoding: [0xa0,0x07,0xf8,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vqneg.s8	q8, q8          @ encoding: [0xe0,0x07,0xf0,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqneg.s16	q8, q8          @ encoding: [0xe0,0x07,0xf4,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqneg.s32	q8, q8          @ encoding: [0xe0,0x07,0xf8,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone



From resistor at mac.com  Wed Oct 27 13:05:25 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 18:05:25 -0000
Subject: [llvm-commits] [llvm] r117466 -
	/llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll
Message-ID: <20101027180525.D38D52A6C130@llvm.org>

Author: resistor
Date: Wed Oct 27 13:05:25 2010
New Revision: 117466

URL: http://llvm.org/viewvc/llvm-project?rev=117466&view=rev
Log:
Tests for NEON encoding of vcls, vclz, and vcnt.

Added:
    llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll?rev=117466&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll Wed Oct 27 13:05:25 2010
@@ -0,0 +1,118 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vcnt.8	d16, d16                @ encoding: [0x20,0x05,0xf0,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vcnt.8	q8, q8                  @ encoding: [0x60,0x05,0xf0,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1)
+	ret <16 x i8> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone
+
+define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vclz.i8	d16, d16                @ encoding: [0xa0,0x04,0xf0,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vclz.i16	d16, d16        @ encoding: [0xa0,0x04,0xf4,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vclz.i32	d16, d16        @ encoding: [0xa0,0x04,0xf8,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vclz.i8	q8, q8                  @ encoding: [0xe0,0x04,0xf0,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vclz.i16	q8, q8          @ encoding: [0xe0,0x04,0xf4,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vclz.i32	q8, q8          @ encoding: [0xe0,0x04,0xf8,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vclz.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32>) nounwind readnone
+
+define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vcls.s8	d16, d16                @ encoding: [0x20,0x04,0xf0,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vcls.s16	d16, d16        @ encoding: [0x20,0x04,0xf4,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vcls.s32	d16, d16        @ encoding: [0x20,0x04,0xf8,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vcls.s8	q8, q8                  @ encoding: [0x60,0x04,0xf0,0xf3]
+	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vcls.s16	q8, q8          @ encoding: [0x60,0x04,0xf4,0xf3]
+	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vcls.s32	q8, q8          @ encoding: [0x60,0x04,0xf8,0xf3]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
+	ret <4 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone



From rafael.espindola at gmail.com  Wed Oct 27 13:09:58 2010
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Wed, 27 Oct 2010 14:09:58 -0400
Subject: [llvm-commits] [PATCH]: .equ parsing in AsmParser
In-Reply-To: <20101027174421.GA24109@freebsd.org>
References: <20101027174421.GA24109@freebsd.org>
Message-ID: <AANLkTimfnUAc7jq-QPFVsTML8nsKX-VvE45iuzG0s2J0@mail.gmail.com>

On 27 October 2010 13:44, Roman Divacky <rdivacky at freebsd.org> wrote:
> hi,
>
> the attached patch implementes .equ parsing. .equ is a synonym
> to .set so this was really easy :)

TokError takes a Twine, so you can use that instead of std::string.

OK with that change.

> please review this so I can commit that
>
> thank you! roman
>

Cheers,
Rafael

From dpatel at apple.com  Wed Oct 27 13:08:31 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 27 Oct 2010 18:08:31 -0000
Subject: [llvm-commits] [llvm] r117468 -
	/llvm/trunk/include/llvm/Analysis/DebugInfo.h
Message-ID: <20101027180831.C58D12A6C130@llvm.org>

Author: dpatel
Date: Wed Oct 27 13:08:31 2010
New Revision: 117468

URL: http://llvm.org/viewvc/llvm-project?rev=117468&view=rev
Log:
Give a name to nameless argument.

Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=117468&r1=117467&r2=117468&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Oct 27 13:08:31 2010
@@ -734,7 +734,7 @@
                                   bool isDefinition,
                                   unsigned VK = 0,
                                   unsigned VIndex = 0,
-                                  DIType = DIType(),
+                                  DIType ContainingType = DIType(),
                                   unsigned Flags = 0,
                                   bool isOptimized = false,
                                   Function *Fn = 0);



From resistor at mac.com  Wed Oct 27 13:17:12 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 18:17:12 -0000
Subject: [llvm-commits] [llvm] r117469 -
	/llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
Message-ID: <20101027181712.E88FE2A6C130@llvm.org>

Author: resistor
Date: Wed Oct 27 13:17:12 2010
New Revision: 117469

URL: http://llvm.org/viewvc/llvm-project?rev=117469&view=rev
Log:
Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun.

Modified:
    llvm/trunk/test/MC/ARM/neon-mov-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.ll?rev=117469&r1=117468&r2=117469&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mov-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-mov-encoding.ll Wed Oct 27 13:17:12 2010
@@ -167,3 +167,141 @@
 ; CHECK: vmvn.i32	d16, #0x20FFFF  @ encoding: [0x30,0x0d,0xc2,0xf2]
 	ret <2 x i32> < i32 4292804608, i32 4292804608 >
 }
+
+define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vmovl.s8	q8, d16         @ encoding: [0x30,0x0a,0xc8,0xf2]
+	%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vmovl.s16	q8, d16         @ encoding: [0x30,0x0a,0xd0,0xf2]
+	%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
+	ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vmovl.s32	q8, d16         @ encoding: [0x30,0x0a,0xe0,0xf2]
+	%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
+	ret <2 x i64> %tmp2
+}
+
+define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vmovl.u8	q8, d16         @ encoding: [0x30,0x0a,0xc8,0xf3]
+	%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vmovl.u16	q8, d16         @ encoding: [0x30,0x0a,0xd0,0xf3]
+	%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
+	ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vmovl.u32	q8, d16         @ encoding: [0x30,0x0a,0xe0,0xf3]
+	%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
+	ret <2 x i64> %tmp2
+}
+
+define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vmovn.i16	d16, q8         @ encoding: [0x20,0x02,0xf2,0xf3]
+	%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vmovn.i32	d16, q8         @ encoding: [0x20,0x02,0xf6,0xf3]
+	%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vmovn.i64	d16, q8         @ encoding: [0x20,0x02,0xfa,0xf3]
+	%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqmovn.s16	d16, q8         @ encoding: [0xa0,0x02,0xf2,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqmovn.s32	d16, q8         @ encoding: [0xa0,0x02,0xf6,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqmovn.s64	d16, q8         @ encoding: [0xa0,0x02,0xfa,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqmovn.u16	d16, q8         @ encoding: [0xe0,0x02,0xf2,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqmovn.u32	d16, q8         @ encoding: [0xe0,0x02,0xf6,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqmovn.u64	d16, q8         @ encoding: [0xe0,0x02,0xfa,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vqmovun.s16	d16, q8         @ encoding: [0x60,0x02,0xf2,0xf3]
+	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vqmovun.s32	d16, q8         @ encoding: [0x60,0x02,0xf6,0xf3]
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vqmovun.s64	d16, q8         @ encoding: [0x60,0x02,0xfa,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
+	ret <2 x i32> %tmp2
+}
+
+declare <8 x i8>  @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
+
+declare <8 x i8>  @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
\ No newline at end of file



From rafael.espindola at gmail.com  Wed Oct 27 13:45:20 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 18:45:20 -0000
Subject: [llvm-commits] [llvm] r117471 - in /llvm/trunk:
 lib/MC/MCParser/ELFAsmParser.cpp test/MC/ELF/section.s
Message-ID: <20101027184520.D96462A6C132@llvm.org>

Author: rafael
Date: Wed Oct 27 13:45:20 2010
New Revision: 117471

URL: http://llvm.org/viewvc/llvm-project?rev=117471&view=rev
Log:
Set default type and flags for .init and .fini.

Modified:
    llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp
    llvm/trunk/test/MC/ELF/section.s

Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=117471&r1=117470&r2=117471&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Wed Oct 27 13:45:20 2010
@@ -240,6 +240,15 @@
     return TokError("unexpected token in directive");
 
   unsigned Flags = 0;
+  unsigned Type = MCSectionELF::SHT_NULL;
+
+  // Set the defaults first.
+  if (SectionName == ".fini" || SectionName == ".init") {
+    Type = MCSectionELF::SHT_PROGBITS;
+    Flags |= MCSectionELF::SHF_ALLOC;
+    Flags |= MCSectionELF::SHF_EXECINSTR;
+  }
+
   for (unsigned i = 0; i < FlagsStr.size(); i++) {
     switch (FlagsStr[i]) {
     case 'a':
@@ -271,7 +280,6 @@
     }
   }
 
-  unsigned Type = MCSectionELF::SHT_NULL;
   if (!TypeName.empty()) {
     if (TypeName == "init_array")
       Type = MCSectionELF::SHT_INIT_ARRAY;

Modified: llvm/trunk/test/MC/ELF/section.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/section.s?rev=117471&r1=117470&r2=117471&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/section.s (original)
+++ llvm/trunk/test/MC/ELF/section.s Wed Oct 27 13:45:20 2010
@@ -9,3 +9,31 @@
 // CHECK: ('sh_name', 0x00000012) # '.note.GNU-stack'
 // CHECK: ('sh_name', 0x00000022) # '.note.GNU-'
 // CHECK: ('sh_name', 0x0000002d) # '-.note.GNU'
+
+// Test that the dafults for init and fini are used
+
+.section	.init
+.section	.fini
+
+// CHECK:      (('sh_name', 0x00000038) # '.init'
+// CHECK-NEXT:  ('sh_type', 0x00000001)
+// CHECK-NEXT:  ('sh_flags', 0x00000006)
+// CHECK-NEXT:  ('sh_addr', 0x00000000)
+// CHECK-NEXT:  ('sh_offset', 0x00000040)
+// CHECK-NEXT:  ('sh_size', 0x00000000)
+// CHECK-NEXT:  ('sh_link', 0x00000000)
+// CHECK-NEXT:  ('sh_info', 0x00000000)
+// CHECK-NEXT:  ('sh_addralign', 0x00000001)
+// CHECK-NEXT:  ('sh_entsize', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Section 0x00000008
+// CHECK-NEXT: (('sh_name', 0x0000003e) # '.fini'
+// CHECK-NEXT:  ('sh_type', 0x00000001)
+// CHECK-NEXT:  ('sh_flags', 0x00000006)
+// CHECK-NEXT:  ('sh_addr', 0x00000000)
+// CHECK-NEXT:  ('sh_offset', 0x00000040)
+// CHECK-NEXT:  ('sh_size', 0x00000000)
+// CHECK-NEXT:  ('sh_link', 0x00000000)
+// CHECK-NEXT:  ('sh_info', 0x00000000)
+// CHECK-NEXT:  ('sh_addralign', 0x00000001)
+// CHECK-NEXT:  ('sh_entsize', 0x00000000)



From bigcheesegs at gmail.com  Wed Oct 27 13:52:20 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 27 Oct 2010 18:52:20 -0000
Subject: [llvm-commits] [llvm] r117472 -
	/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Message-ID: <20101027185220.7CD7E2A6C132@llvm.org>

Author: mspencer
Date: Wed Oct 27 13:52:20 2010
New Revision: 117472

URL: http://llvm.org/viewvc/llvm-project?rev=117472&view=rev
Log:
Fix whitespace.

Modified:
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=117472&r1=117471&r2=117472&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Oct 27 13:52:20 2010
@@ -308,7 +308,7 @@
   bool EmitUniquedSection;
   if (Kind.isText())
     EmitUniquedSection = TM.getFunctionSections();
-  else 
+  else
     EmitUniquedSection = TM.getDataSections();
 
   // If this global is linkonce/weak and the target handles this by emitting it
@@ -464,7 +464,7 @@
       break;
     }
   }
-  
+
   TargetLoweringObjectFile::Initialize(Ctx, TM);
 
   TextSection // .text
@@ -483,20 +483,20 @@
     = getContext().getMachOSection("__DATA", "__thread_bss",
                                    MCSectionMachO::S_THREAD_LOCAL_ZEROFILL,
                                    SectionKind::getThreadBSS());
-                                   
+
   // TODO: Verify datarel below.
   TLSTLVSection // .tlv
     = getContext().getMachOSection("__DATA", "__thread_vars",
                                    MCSectionMachO::S_THREAD_LOCAL_VARIABLES,
                                    SectionKind::getDataRel());
-                                   
+
   TLSThreadInitSection
     = getContext().getMachOSection("__DATA", "__thread_init",
                           MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS,
                           SectionKind::getDataRel());
-                                   
+
   CStringSection // .cstring
-    = getContext().getMachOSection("__TEXT", "__cstring", 
+    = getContext().getMachOSection("__TEXT", "__cstring",
                                    MCSectionMachO::S_CSTRING_LITERALS,
                                    SectionKind::getMergeable1ByteCString());
   UStringSection
@@ -507,7 +507,7 @@
                                    MCSectionMachO::S_4BYTE_LITERALS,
                                    SectionKind::getMergeableConst4());
   EightByteConstantSection // .literal8
-    = getContext().getMachOSection("__TEXT", "__literal8", 
+    = getContext().getMachOSection("__TEXT", "__literal8",
                                    MCSectionMachO::S_8BYTE_LITERALS,
                                    SectionKind::getMergeableConst8());
 
@@ -531,14 +531,14 @@
                                    MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
                                    SectionKind::getText());
   ConstTextCoalSection
-    = getContext().getMachOSection("__TEXT", "__const_coal", 
+    = getContext().getMachOSection("__TEXT", "__const_coal",
                                    MCSectionMachO::S_COALESCED,
                                    SectionKind::getReadOnly());
   ConstDataSection  // .const_data
     = getContext().getMachOSection("__DATA", "__const", 0,
                                    SectionKind::getReadOnlyWithRel());
   DataCoalSection
-    = getContext().getMachOSection("__DATA","__datacoal_nt", 
+    = getContext().getMachOSection("__DATA","__datacoal_nt",
                                    MCSectionMachO::S_COALESCED,
                                    SectionKind::getDataRel());
   DataCommonSection
@@ -548,7 +548,7 @@
   DataBSSSection
     = getContext().getMachOSection("__DATA","__bss", MCSectionMachO::S_ZEROFILL,
                                    SectionKind::getBSS());
-  
+
 
   LazySymbolPointerSection
     = getContext().getMachOSection("__DATA", "__la_symbol_ptr",
@@ -590,7 +590,7 @@
 
   // Debug Information.
   DwarfAbbrevSection =
-    getContext().getMachOSection("__DWARF", "__debug_abbrev", 
+    getContext().getMachOSection("__DWARF", "__debug_abbrev",
                                  MCSectionMachO::S_ATTR_DEBUG,
                                  SectionKind::getMetadata());
   DwarfInfoSection =
@@ -637,7 +637,7 @@
     getContext().getMachOSection("__DWARF", "__debug_inlined",
                                  MCSectionMachO::S_ATTR_DEBUG,
                                  SectionKind::getMetadata());
-                                 
+
   TLSExtraDataSection = TLSTLVSection;
 }
 
@@ -679,7 +679,7 @@
 const MCSection *TargetLoweringObjectFileMachO::
 SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
                        Mangler *Mang, const TargetMachine &TM) const {
-  
+
   // Handle thread local data.
   if (Kind.isThreadBSS()) return TLSBSSSection;
   if (Kind.isThreadData()) return TLSDataSection;
@@ -699,7 +699,7 @@
   if (Kind.isMergeable1ByteCString() &&
       TM.getTargetData()->getPreferredAlignment(cast<GlobalVariable>(GV)) < 32)
     return CStringSection;
-      
+
   // Do not put 16-bit arrays in the UString section if they have an
   // externally visible label, this runs into issues with certain linker
   // versions.
@@ -735,7 +735,7 @@
   // with the .zerofill directive (aka .lcomm).
   if (Kind.isBSSLocal())
     return DataBSSSection;
-  
+
   // Otherwise, just drop the variable in the normal data section.
   return DataSection;
 }



From bigcheesegs at gmail.com  Wed Oct 27 13:52:29 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 27 Oct 2010 18:52:29 -0000
Subject: [llvm-commits] [llvm] r117473 -
	/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Message-ID: <20101027185229.5DDA22A6C132@llvm.org>

Author: mspencer
Date: Wed Oct 27 13:52:29 2010
New Revision: 117473

URL: http://llvm.org/viewvc/llvm-project?rev=117473&view=rev
Log:
COFF: Add IMAGE_SCN_MEM_READ to text sections.

There are currently 100 references to COFF::IMAGE_SCN in 6 files
and 11 different functions. Section to attribute mapping really
needs to happen in one place to avoid problems like this.

Modified:
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=117473&r1=117472&r2=117473&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Oct 27 13:52:29 2010
@@ -952,6 +952,7 @@
   else if (K.isText())
     Flags |=
       COFF::IMAGE_SCN_MEM_EXECUTE |
+      COFF::IMAGE_SCN_MEM_READ |
       COFF::IMAGE_SCN_CNT_CODE;
   else if (K.isBSS ())
     Flags |=



From bigcheesegs at gmail.com  Wed Oct 27 13:52:38 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 27 Oct 2010 18:52:38 -0000
Subject: [llvm-commits] [llvm] r117474 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20101027185238.E08C42A6C132@llvm.org>

Author: mspencer
Date: Wed Oct 27 13:52:38 2010
New Revision: 117474

URL: http://llvm.org/viewvc/llvm-project?rev=117474&view=rev
Log:
x86-Win32: Switch ftol2 calling convention from stdcall to C.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=117474&r1=117473&r2=117474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Oct 27 13:52:38 2010
@@ -104,8 +104,8 @@
     setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
     setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
     setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
-    setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::X86_StdCall);
-    setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::X86_StdCall);
+    setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
+    setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
   }
 
   if (Subtarget->isTargetDarwin()) {



From resistor at mac.com  Wed Oct 27 14:25:54 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 19:25:54 -0000
Subject: [llvm-commits] [llvm] r117475 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
 test/MC/ARM/neon-dup-encoding.ll
Message-ID: <20101027192554.742A02A6C136@llvm.org>

Author: resistor
Date: Wed Oct 27 14:25:54 2010
New Revision: 117475

URL: http://llvm.org/viewvc/llvm-project?rev=117475&view=rev
Log:
Provide correct NEON encodings for vdup.

Added:
    llvm/trunk/test/MC/ARM/neon-dup-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117475&r1=117474&r2=117475&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Oct 27 14:25:54 2010
@@ -1867,6 +1867,15 @@
   let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
   let Pattern = pattern;
   list<Predicate> Predicates = [HasNEON];
+  
+  bits<5> Vd;
+  bits<4> Rt;
+  bits<4> p;
+  
+  let Inst{31-28} = p{3-0};
+  let Inst{7}     = Vd{4};
+  let Inst{19-16} = Vd{3-0};
+  let Inst{15-12} = Rt{3-0};
 }
 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
                 dag oops, dag iops, InstrItinClass itin,
@@ -1895,6 +1904,15 @@
   let Inst{11-7}  = 0b11000;
   let Inst{6}     = op6;
   let Inst{4}     = 0;
+  
+  bits<5> Vd;
+  bits<5> Vm;
+  bits<4> lane;
+  
+  let Inst{22}     = Vd{4};
+  let Inst{15-12} = Vd{3-0};
+  let Inst{5}     = Vm{4};
+  let Inst{3-0} = Vm{3-0};
 }
 
 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117475&r1=117474&r2=117475&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Oct 27 14:25:54 2010
@@ -3679,14 +3679,30 @@
 
 // Inst{19-16} is partially specified depending on the element size.
 
-def VDUPLN8d  : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
-def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
-def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
-def VDUPLNfd  : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
-def VDUPLN8q  : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
-def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
-def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
-def VDUPLNfq  : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
+def VDUPLN8d  : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
+  let Inst{19-17} = lane{2-0};
+}
+def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
+  let Inst{19-18} = lane{1-0};
+}
+def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
+  let Inst{19} = lane{0};
+}
+def VDUPLNfd  : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
+  let Inst{19} = lane{0};
+}
+def VDUPLN8q  : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
+  let Inst{19-17} = lane{2-0};
+}
+def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
+  let Inst{19-18} = lane{1-0};
+}
+def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
+  let Inst{19} = lane{0};
+}
+def VDUPLNfq  : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
+  let Inst{19} = lane{0};
+}
 
 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
           (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,

Added: llvm/trunk/test/MC/ARM/neon-dup-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-dup-encoding.ll?rev=117475&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-dup-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-dup-encoding.ll Wed Oct 27 14:25:54 2010
@@ -0,0 +1,115 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @v_dup8(i8 %A) nounwind {
+; CHECK: vdup.8	d16, r0                 @ encoding: [0x90,0x0b,0xc0,0xee]
+	%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
+	%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
+	%tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
+	%tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3
+	%tmp5 = insertelement <8 x i8> %tmp4, i8 %A, i32 4
+	%tmp6 = insertelement <8 x i8> %tmp5, i8 %A, i32 5
+	%tmp7 = insertelement <8 x i8> %tmp6, i8 %A, i32 6
+	%tmp8 = insertelement <8 x i8> %tmp7, i8 %A, i32 7
+	ret <8 x i8> %tmp8
+}
+
+define <4 x i16> @v_dup16(i16 %A) nounwind {
+; CHECK: vdup.16	d16, r0                 @ encoding: [0xb0,0x0b,0x80,0xee]
+	%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
+	%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
+	%tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
+	%tmp4 = insertelement <4 x i16> %tmp3, i16 %A, i32 3
+	ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @v_dup32(i32 %A) nounwind {
+; CHECK: vdup.32	d16, r0                 @ encoding: [0x90,0x0b,0x80,0xee]
+	%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
+	%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @v_dupQ8(i8 %A) nounwind {
+; CHECK: vdup.8	q8, r0                  @ encoding: [0x90,0x0b,0xe0,0xee]
+	%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
+	%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
+	%tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
+	%tmp4 = insertelement <16 x i8> %tmp3, i8 %A, i32 3
+	%tmp5 = insertelement <16 x i8> %tmp4, i8 %A, i32 4
+	%tmp6 = insertelement <16 x i8> %tmp5, i8 %A, i32 5
+	%tmp7 = insertelement <16 x i8> %tmp6, i8 %A, i32 6
+	%tmp8 = insertelement <16 x i8> %tmp7, i8 %A, i32 7
+	%tmp9 = insertelement <16 x i8> %tmp8, i8 %A, i32 8
+	%tmp10 = insertelement <16 x i8> %tmp9, i8 %A, i32 9
+	%tmp11 = insertelement <16 x i8> %tmp10, i8 %A, i32 10
+	%tmp12 = insertelement <16 x i8> %tmp11, i8 %A, i32 11
+	%tmp13 = insertelement <16 x i8> %tmp12, i8 %A, i32 12
+	%tmp14 = insertelement <16 x i8> %tmp13, i8 %A, i32 13
+	%tmp15 = insertelement <16 x i8> %tmp14, i8 %A, i32 14
+	%tmp16 = insertelement <16 x i8> %tmp15, i8 %A, i32 15
+	ret <16 x i8> %tmp16
+}
+
+define <8 x i16> @v_dupQ16(i16 %A) nounwind {
+; CHECK: vdup.16	q8, r0                  @ encoding: [0xb0,0x0b,0xa0,0xee]
+	%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
+	%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
+	%tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
+	%tmp4 = insertelement <8 x i16> %tmp3, i16 %A, i32 3
+	%tmp5 = insertelement <8 x i16> %tmp4, i16 %A, i32 4
+	%tmp6 = insertelement <8 x i16> %tmp5, i16 %A, i32 5
+	%tmp7 = insertelement <8 x i16> %tmp6, i16 %A, i32 6
+	%tmp8 = insertelement <8 x i16> %tmp7, i16 %A, i32 7
+	ret <8 x i16> %tmp8
+}
+
+define <4 x i32> @v_dupQ32(i32 %A) nounwind {
+; CHECK: vdup.32	q8, r0                  @ encoding: [0x90,0x0b,0xa0,0xee]
+	%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
+	%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
+	%tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
+	%tmp4 = insertelement <4 x i32> %tmp3, i32 %A, i32 3
+	ret <4 x i32> %tmp4
+}
+
+define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vdup.8	d16, d16[1]             @ encoding: [0x20,0x0c,0xf3,0xf3]
+	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vdup.16	d16, d16[1]             @ encoding: [0x20,0x0c,0xf6,0xf3]
+	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vdup.32	d16, d16[1]             @ encoding: [0x20,0x0c,0xfc,0xf3]
+	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vdup.8	q8, d16[1]              @ encoding: [0x60,0x0c,0xf3,0xf3]
+	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vdup.16	q8, d16[1]              @ encoding: [0x60,0x0c,0xf6,0xf3]
+	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vdup.32	q8, d16[1]              @ encoding: [0x60,0x0c,0xfc,0xf3]
+	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
+	ret <4 x i32> %tmp2
+}



From rafael.espindola at gmail.com  Wed Oct 27 14:40:38 2010
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Wed, 27 Oct 2010 15:40:38 -0400
Subject: [llvm-commits] [patch] Change the 11 byte nop
Message-ID: <AANLkTinJNLNLBEdst6PaNA40mL2xQqVRk7T4HBis=N5e@mail.gmail.com>

I have no idea if using two 0x66 prefixes is faster or not (the Intel
manual goes till 9 bytes), but this matches what gnu as does.

Cheers,
Rafael
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From benny.kra at googlemail.com  Wed Oct 27 14:53:52 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Wed, 27 Oct 2010 19:53:52 -0000
Subject: [llvm-commits] [llvm] r117477 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20101027195352.303D62A6C136@llvm.org>

Author: d0k
Date: Wed Oct 27 14:53:52 2010
New Revision: 117477

URL: http://llvm.org/viewvc/llvm-project?rev=117477&view=rev
Log:
Replace pointer arithmetic with StringRef::substr.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117477&r1=117476&r2=117477&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 14:53:52 2010
@@ -459,12 +459,12 @@
     if (!Alias.isVariable())
       continue;
     const MCSymbol &Symbol = AliasedSymbol(Alias);
-    const StringRef &AliasName = Alias.getName();
+    StringRef AliasName = Alias.getName();
     size_t Pos = AliasName.find('@');
     if (Pos == StringRef::npos)
       continue;
 
-    StringRef Rest(AliasName.begin() + Pos);
+    StringRef Rest = AliasName.substr(Pos);
     if (!Symbol.isUndefined() && !Rest.startswith("@@@"))
       continue;
 
@@ -473,8 +473,7 @@
         !Rest.startswith("@@@"))
       report_fatal_error("A @@ version cannot be undefined");
 
-    std::pair<const MCSymbol *, const MCSymbol *> t(&Symbol, &Alias);
-    Renames.insert(t);
+    Renames.insert(std::make_pair(&Symbol, &Alias));
   }
 }
 
@@ -887,9 +886,9 @@
     size_t Pos = Name.find("@@@");
     std::string FinalName;
     if (Pos != StringRef::npos) {
-      StringRef Prefix(Name.begin(), Pos);
+      StringRef Prefix = Name.substr(0, Pos);
       unsigned n = MSD.SectionIndex == ELF::SHN_UNDEF ? 2 : 1;
-      StringRef Suffix(Name.begin() + Pos + n);
+      StringRef Suffix = Name.substr(Pos + n);
       FinalName = Prefix.str() + Suffix.str();
     } else {
       FinalName = Name.str();



From grosbach at apple.com  Wed Oct 27 14:55:59 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 19:55:59 -0000
Subject: [llvm-commits] [llvm] r117478 - in /llvm/trunk/lib/Target/ARM:
 ARMCodeEmitter.cpp ARMInstrInfo.td
Message-ID: <20101027195559.763B52A6C136@llvm.org>

Author: grosbach
Date: Wed Oct 27 14:55:59 2010
New Revision: 117478

URL: http://llvm.org/viewvc/llvm-project?rev=117478&view=rev
Log:
ARM JIT fix for LDRi12 and company.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117478&r1=117477&r2=117478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Oct 27 14:55:59 2010
@@ -175,7 +175,21 @@
     unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
                                             unsigned Op) const { return 0; }
     unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
-      const { return 0; }
+      const {
+        // {17-13} = reg
+        // {12}    = (U)nsigned (add == '1', sub == '0')
+        // {11-0}  = imm12
+        const MachineOperand &MO  = MI.getOperand(Op);
+        const MachineOperand &MO1 = MI.getOperand(Op + 1);
+        unsigned Reg = getARMRegisterNumbering(MO.getReg());
+        int32_t Imm12 = MO1.getImm();
+        uint32_t Binary;
+        Binary = Imm12 & 0xfff;
+        if (Imm12 >= 0)
+          Binary |= (1 << 12);
+        Binary |= (Reg << 13);
+        return Binary;
+      }
 
     /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
     /// machine operand requires relocation, record the relocation and return
@@ -946,9 +960,8 @@
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
-  // If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done.
-  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs
-      || MI.getOpcode() == ARM::LDRcp) {
+  // If this is an LDRi12 or LDRcp, nothing more needs be done.
+  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp) {
     emitWordLE(Binary);
     return;
   }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117478&r1=117477&r2=117478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Oct 27 14:55:59 2010
@@ -397,6 +397,7 @@
 def ldst_so_reg : Operand<i32>,
                   ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
   // FIXME: Simplify the printer
+  // FIXME: Add EncoderMethod for this addressing mode
   let PrintMethod = "printAddrMode2Operand";
   let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
 }



From rafael.espindola at gmail.com  Wed Oct 27 15:27:50 2010
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Wed, 27 Oct 2010 16:27:50 -0400
Subject: [llvm-commits] [llvm] r117477 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
In-Reply-To: <20101027195352.303D62A6C136@llvm.org>
References: <20101027195352.303D62A6C136@llvm.org>
Message-ID: <AANLkTik_3u650SZcOCbYrsreQgpOvcnbB1a_LvcYNd6m@mail.gmail.com>

On 27 October 2010 15:53, Benjamin Kramer <benny.kra at googlemail.com> wrote:
> Author: d0k
> Date: Wed Oct 27 14:53:52 2010
> New Revision: 117477
>
> URL: http://llvm.org/viewvc/llvm-project?rev=117477&view=rev
> Log:
> Replace pointer arithmetic with StringRef::substr.

Thanks!

> Modified:
> ? ?llvm/trunk/lib/MC/ELFObjectWriter.cpp
>
> Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117477&r1=117476&r2=117477&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
> +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 14:53:52 2010
> @@ -459,12 +459,12 @@
> ? ? if (!Alias.isVariable())
> ? ? ? continue;
> ? ? const MCSymbol &Symbol = AliasedSymbol(Alias);
> - ? ?const StringRef &AliasName = Alias.getName();
> + ? ?StringRef AliasName = Alias.getName();
> ? ? size_t Pos = AliasName.find('@');
> ? ? if (Pos == StringRef::npos)
> ? ? ? continue;
>
> - ? ?StringRef Rest(AliasName.begin() + Pos);
> + ? ?StringRef Rest = AliasName.substr(Pos);
> ? ? if (!Symbol.isUndefined() && !Rest.startswith("@@@"))
> ? ? ? continue;
>
> @@ -473,8 +473,7 @@
> ? ? ? ? !Rest.startswith("@@@"))
> ? ? ? report_fatal_error("A @@ version cannot be undefined");
>
> - ? ?std::pair<const MCSymbol *, const MCSymbol *> t(&Symbol, &Alias);
> - ? ?Renames.insert(t);
> + ? ?Renames.insert(std::make_pair(&Symbol, &Alias));
> ? }
> ?}
>
> @@ -887,9 +886,9 @@
> ? ? size_t Pos = Name.find("@@@");
> ? ? std::string FinalName;
> ? ? if (Pos != StringRef::npos) {
> - ? ? ?StringRef Prefix(Name.begin(), Pos);
> + ? ? ?StringRef Prefix = Name.substr(0, Pos);
> ? ? ? unsigned n = MSD.SectionIndex == ELF::SHN_UNDEF ? 2 : 1;
> - ? ? ?StringRef Suffix(Name.begin() + Pos + n);
> + ? ? ?StringRef Suffix = Name.substr(Pos + n);
> ? ? ? FinalName = Prefix.str() + Suffix.str();
> ? ? } else {
> ? ? ? FinalName = Name.str();
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From rafael.espindola at gmail.com  Wed Oct 27 15:28:07 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 20:28:07 -0000
Subject: [llvm-commits] [llvm] r117481 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/MC/ELF/relocation.s
Message-ID: <20101027202807.7E1882A6C137@llvm.org>

Author: rafael
Date: Wed Oct 27 15:28:07 2010
New Revision: 117481

URL: http://llvm.org/viewvc/llvm-project?rev=117481&view=rev
Log:
Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/test/MC/ELF/relocation.s

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117481&r1=117480&r2=117481&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 15:28:07 2010
@@ -85,6 +85,9 @@
   case ELF::R_X86_64_GOT32:
   case ELF::R_X86_64_PLT32:
   case ELF::R_X86_64_GOTPCREL:
+  case ELF::R_X86_64_TPOFF32:
+  case ELF::R_X86_64_TLSGD:
+  case ELF::R_X86_64_GOTTPOFF:
     return true;
   }
 }
@@ -687,6 +690,12 @@
       case llvm::MCSymbolRefExpr::VK_GOTPCREL:
         Type = ELF::R_X86_64_GOTPCREL;
         break;
+      case MCSymbolRefExpr::VK_GOTTPOFF:
+        Type = ELF::R_X86_64_GOTTPOFF;
+        break;
+      case MCSymbolRefExpr::VK_TLSGD:
+        Type = ELF::R_X86_64_TLSGD;
+        break;
       }
     } else {
       switch ((unsigned)Fixup.getKind()) {
@@ -707,6 +716,9 @@
         case MCSymbolRefExpr::VK_GOTPCREL:
           Type = ELF::R_X86_64_GOTPCREL;
           break;
+        case MCSymbolRefExpr::VK_TPOFF:
+          Type = ELF::R_X86_64_TPOFF32;
+          break;
         }
         break;
       case FK_Data_4:

Modified: llvm/trunk/test/MC/ELF/relocation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relocation.s?rev=117481&r1=117480&r2=117481&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/relocation.s (original)
+++ llvm/trunk/test/MC/ELF/relocation.s Wed Oct 27 15:28:07 2010
@@ -1,14 +1,17 @@
 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck  %s
 
-// Test that we produce a R_X86_64_32S or R_X86_64_32.
+// Test that we produce the correct relocation.
 
 bar:
-        movl	$bar, %edx        // R_X86_64_32
-        movq	$bar, %rdx        // R_X86_64_32S
-        movq	$bar, bar(%rip)   // R_X86_64_32S
-        movl	bar, %edx         // R_X86_64_32S
-        movq	bar, %rdx         // R_X86_64_32S
-.long bar                         // R_X86_64_32
+        movl	$bar, %edx        # R_X86_64_32
+        movq	$bar, %rdx        # R_X86_64_32S
+        movq	$bar, bar(%rip)   # R_X86_64_32S
+        movl	bar, %edx         # R_X86_64_32S
+        movq	bar, %rdx         # R_X86_64_32S
+.long bar                         # R_X86_64_32
+        leaq	foo at GOTTPOFF(%rip), %rax # R_X86_64_GOTTPOFF
+        leaq	foo at TLSGD(%rip), %rax    # R_X86_64_TLSGD
+        leaq	foo at TPOFF(%rax), %rax    # R_X86_64_TPOFF32
 
 // CHECK:  # Section 0x00000001
 // CHECK: (('sh_name', 0x00000001) # '.text'
@@ -55,3 +58,21 @@
 // CHECK-NEXT:   ('r_sym', 0x00000002)
 // CHECK-NEXT:   ('r_type', 0x0000000a)
 // CHECK-NEXT:   ('r_addend',
+
+// CHECK: # Relocation 0x00000006
+// CHECK-NEXT:  (('r_offset', 0x0000002d)
+// CHECK-NEXT:   ('r_sym', 0x00000006)
+// CHECK-NEXT:   ('r_type', 0x00000016)
+// CHECK-NEXT:   ('r_addend', 0xfffffffc)
+
+// CHECK:  # Relocation 0x00000007
+// CHECK-NEXT:  (('r_offset', 0x00000034)
+// CHECK-NEXT:   ('r_sym', 0x00000006)
+// CHECK-NEXT:   ('r_type', 0x00000013)
+// CHECK-NEXT:   ('r_addend', 0xfffffffc)
+
+// CHECK:  # Relocation 0x00000008
+// CHECK-NEXT:  (('r_offset', 0x0000003b)
+// CHECK-NEXT:   ('r_sym', 0x00000006)
+// CHECK-NEXT:   ('r_type', 0x00000017)
+// CHECK-NEXT:   ('r_addend', 0x00000000)



From bob.wilson at apple.com  Wed Oct 27 15:38:28 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 27 Oct 2010 20:38:28 -0000
Subject: [llvm-commits] [llvm] r117482 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vrev.ll
Message-ID: <20101027203828.D985D2A6C137@llvm.org>

Author: bwilson
Date: Wed Oct 27 15:38:28 2010
New Revision: 117482

URL: http://llvm.org/viewvc/llvm-project?rev=117482&view=rev
Log:
SelectionDAG shuffle nodes do not allow operands with different numbers of
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/vrev.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=117482&r1=117481&r2=117482&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 27 15:38:28 2010
@@ -460,6 +460,7 @@
     setTargetDAGCombine(ISD::ANY_EXTEND);
     setTargetDAGCombine(ISD::SELECT_CC);
     setTargetDAGCombine(ISD::BUILD_VECTOR);
+    setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
   }
 
   computeRegisterProperties();
@@ -4531,6 +4532,59 @@
   return SDValue();
 }
 
+/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
+/// ISD::VECTOR_SHUFFLE.
+static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
+  // The LLVM shufflevector instruction does not require the shuffle mask
+  // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
+  // have that requirement.  When translating to ISD::VECTOR_SHUFFLE, if the
+  // operands do not match the mask length, they are extended by concatenating
+  // them with undef vectors.  That is probably the right thing for other
+  // targets, but for NEON it is better to concatenate two double-register
+  // size vector operands into a single quad-register size vector.  Do that
+  // transformation here:
+  //   shuffle(concat(v1, undef), concat(v2, undef)) ->
+  //   shuffle(concat(v1, v2), undef)
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
+      Op1.getOpcode() != ISD::CONCAT_VECTORS ||
+      Op0.getNumOperands() != 2 ||
+      Op1.getNumOperands() != 2)
+    return SDValue();
+  SDValue Concat0Op1 = Op0.getOperand(1);
+  SDValue Concat1Op1 = Op1.getOperand(1);
+  if (Concat0Op1.getOpcode() != ISD::UNDEF ||
+      Concat1Op1.getOpcode() != ISD::UNDEF)
+    return SDValue();
+  // Skip the transformation if any of the types are illegal.
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  EVT VT = N->getValueType(0);
+  if (!TLI.isTypeLegal(VT) ||
+      !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
+      !TLI.isTypeLegal(Concat1Op1.getValueType()))
+    return SDValue();
+
+  SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
+                                  Op0.getOperand(0), Op1.getOperand(0));
+  // Translate the shuffle mask.
+  SmallVector<int, 16> NewMask;
+  unsigned NumElts = VT.getVectorNumElements();
+  unsigned HalfElts = NumElts/2;
+  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
+  for (unsigned n = 0; n < NumElts; ++n) {
+    int MaskElt = SVN->getMaskElt(n);
+    int NewElt = -1;
+    if (MaskElt < HalfElts)
+      NewElt = MaskElt;
+    else if (MaskElt >= NumElts && MaskElt < NumElts + HalfElts)
+      NewElt = HalfElts + MaskElt - NumElts;
+    NewMask.push_back(NewElt);
+  }
+  return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
+                              DAG.getUNDEF(VT), NewMask.data());
+}
+
 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
 /// ARMISD::VDUPLANE.
 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
@@ -4939,6 +4993,7 @@
   case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
   case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
   case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
+  case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
   case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
   case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
   case ISD::SHL:

Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=117482&r1=117481&r2=117482&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vrev.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vrev.ll Wed Oct 27 15:38:28 2010
@@ -129,3 +129,21 @@
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
 	ret <8 x i16> %tmp2
 }
+
+; A vcombine feeding a VREV should not obscure things.  Radar 8597007.
+
+define void @test_with_vcombine(<4 x float>* %v) nounwind {
+;CHECK: test_with_vcombine:
+;CHECK-NOT: vext
+;CHECK: vrev64.32
+  %tmp1 = load <4 x float>* %v, align 16
+  %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
+  %tmp3 = extractelement <2 x double> %tmp2, i32 0
+  %tmp4 = bitcast double %tmp3 to <2 x float>
+  %tmp5 = extractelement <2 x double> %tmp2, i32 1
+  %tmp6 = bitcast double %tmp5 to <2 x float>
+  %tmp7 = fadd <2 x float> %tmp6, %tmp6
+  %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  store <4 x float> %tmp8, <4 x float>* %v, align 16
+  ret void
+}



From grosbach at apple.com  Wed Oct 27 15:39:40 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 20:39:40 -0000
Subject: [llvm-commits] [llvm] r117483 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20101027203940.F05702A6C137@llvm.org>

Author: grosbach
Date: Wed Oct 27 15:39:40 2010
New Revision: 117483

URL: http://llvm.org/viewvc/llvm-project?rev=117483&view=rev
Log:
JIT imm12 encoding for constant pool entry references.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117483&r1=117482&r2=117483&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Oct 27 15:39:40 2010
@@ -181,6 +181,10 @@
         // {11-0}  = imm12
         const MachineOperand &MO  = MI.getOperand(Op);
         const MachineOperand &MO1 = MI.getOperand(Op + 1);
+        if (!MO.isReg()) {
+          emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
+          return 0;
+        }
         unsigned Reg = getARMRegisterNumbering(MO.getReg());
         int32_t Imm12 = MO1.getImm();
         uint32_t Binary;



From enderby at apple.com  Wed Oct 27 15:46:49 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 27 Oct 2010 20:46:49 -0000
Subject: [llvm-commits] [llvm] r117485 - in /llvm/trunk:
 lib/Target/X86/X86InstrSystem.td test/MC/X86/x86-32.s
 utils/TableGen/X86RecognizableInstr.cpp
Message-ID: <20101027204649.7DD4B2A6C137@llvm.org>

Author: enderby
Date: Wed Oct 27 15:46:49 2010
New Revision: 117485

URL: http://llvm.org/viewvc/llvm-project?rev=117485&view=rev
Log:
Added the x86 instruction ud2b (2nd official undefined instruction).

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSystem.td
    llvm/trunk/test/MC/X86/x86-32.s
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=117485&r1=117484&r2=117485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Wed Oct 27 15:46:49 2010
@@ -21,8 +21,10 @@
 
 // CPU flow control instructions
 
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
   def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
+  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
+}
 
 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;

Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=117485&r1=117484&r2=117485&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Wed Oct 27 15:46:49 2010
@@ -786,3 +786,7 @@
 // CHECK: ud2
 // CHECK:  encoding: [0x0f,0x0b]
         	ud2a
+
+// CHECK: ud2b
+// CHECK:  encoding: [0x0f,0xb9]
+        	ud2b

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=117485&r1=117484&r2=117485&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Wed Oct 27 15:46:49 2010
@@ -114,7 +114,6 @@
   EXTENSION_TABLE(72)             \
   EXTENSION_TABLE(73)             \
   EXTENSION_TABLE(ae)             \
-  EXTENSION_TABLE(b9)             \
   EXTENSION_TABLE(ba)             \
   EXTENSION_TABLE(c7)
 



From rafael.espindola at gmail.com  Wed Oct 27 16:23:52 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 27 Oct 2010 21:23:52 -0000
Subject: [llvm-commits] [llvm] r117494 - in /llvm/trunk:
 include/llvm/Support/ELF.h lib/MC/ELFObjectWriter.cpp
 test/MC/ELF/relocation-386.s
Message-ID: <20101027212352.35DC32A6C139@llvm.org>

Author: rafael
Date: Wed Oct 27 16:23:52 2010
New Revision: 117494

URL: http://llvm.org/viewvc/llvm-project?rev=117494&view=rev
Log:
Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.

Modified:
    llvm/trunk/include/llvm/Support/ELF.h
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/test/MC/ELF/relocation-386.s

Modified: llvm/trunk/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=117494&r1=117493&r2=117494&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ELF.h (original)
+++ llvm/trunk/include/llvm/Support/ELF.h Wed Oct 27 16:23:52 2010
@@ -232,10 +232,35 @@
   R_386_GOTOFF        = 9,
   R_386_GOTPC         = 10,
   R_386_32PLT         = 11,
+  R_386_TLS_TPOFF     = 14,
+  R_386_TLS_IE        = 15,
+  R_386_TLS_GOTIE     = 16,
+  R_386_TLS_LE        = 17,
+  R_386_TLS_GD        = 18,
+  R_386_TLS_LDM       = 19,
   R_386_16            = 20,
   R_386_PC16          = 21,
   R_386_8             = 22,
-  R_386_PC8           = 23
+  R_386_PC8           = 23,
+  R_386_TLS_GD_32     = 24,
+  R_386_TLS_GD_PUSH   = 25,
+  R_386_TLS_GD_CALL   = 26,
+  R_386_TLS_GD_POP    = 27,
+  R_386_TLS_LDM_32    = 28,
+  R_386_TLS_LDM_PUSH  = 29,
+  R_386_TLS_LDM_CALL  = 30,
+  R_386_TLS_LDM_POP   = 31,
+  R_386_TLS_LDO_32    = 32,
+  R_386_TLS_IE_32     = 33,
+  R_386_TLS_LE_32     = 34,
+  R_386_TLS_DTPMOD32  = 35,
+  R_386_TLS_DTPOFF32  = 36,
+  R_386_TLS_TPOFF32   = 37,
+  R_386_TLS_GOTDESC   = 39,
+  R_386_TLS_DESC_CALL = 40,
+  R_386_TLS_DESC      = 41,
+  R_386_IRELATIVE     = 42,
+  R_386_NUM           = 43
 };
 
 // Section header.

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117494&r1=117493&r2=117494&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Oct 27 16:23:52 2010
@@ -79,6 +79,7 @@
 }
 
 static bool RelocNeedsGOT(unsigned Type) {
+  // FIXME: Can we use the VariantKind?
   switch (Type) {
   default:
     return false;
@@ -88,6 +89,10 @@
   case ELF::R_X86_64_TPOFF32:
   case ELF::R_X86_64_TLSGD:
   case ELF::R_X86_64_GOTTPOFF:
+  case ELF::R_386_TLS_GD:
+  case ELF::R_386_TLS_LE_32:
+  case ELF::R_386_TLS_IE:
+  case ELF::R_386_TLS_LE:
     return true;
   }
 }
@@ -766,6 +771,18 @@
         case MCSymbolRefExpr::VK_GOTOFF:
           Type = ELF::R_386_GOTOFF;
           break;
+        case MCSymbolRefExpr::VK_TLSGD:
+          Type = ELF::R_386_TLS_GD;
+          break;
+        case MCSymbolRefExpr::VK_TPOFF:
+          Type = ELF::R_386_TLS_LE_32;
+          break;
+        case MCSymbolRefExpr::VK_INDNTPOFF:
+          Type = ELF::R_386_TLS_IE;
+          break;
+        case MCSymbolRefExpr::VK_NTPOFF:
+          Type = ELF::R_386_TLS_LE;
+          break;
         }
         break;
       case FK_Data_2: Type = ELF::R_386_16; break;

Modified: llvm/trunk/test/MC/ELF/relocation-386.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relocation-386.s?rev=117494&r1=117493&r2=117494&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/relocation-386.s (original)
+++ llvm/trunk/test/MC/ELF/relocation-386.s Wed Oct 27 16:23:52 2010
@@ -50,6 +50,33 @@
 // CHECK-NEXT:  ('r_type', 0x00000003
 // CHECK-NEXT: ),
 
+// Relocation 5 (foo at TLSGD) is of type R_386_TLS_GD
+// CHECK-NEXT: # Relocation 0x00000005
+// CHECK-NEXT: (('r_offset', 0x00000020)
+// CHECK-NEXT:  ('r_sym', 0x0000000b)
+// CHECK-NEXT:  ('r_type', 0x00000012)
+// CHECK-NEXT: ),
+
+// Relocation 6 ($foo at TPOFF) is of type R_386_TLS_LE_32
+// CHECK-NEXT: # Relocation 0x00000006
+// CHECK-NEXT: (('r_offset', 0x00000025)
+// CHECK-NEXT:  ('r_sym', 0x0000000b)
+// CHECK-NEXT:  ('r_type', 0x00000022)
+// CHECK-NEXT: ),
+
+// Relocation 7 (foo at INDNTPOFF) is of type R_386_TLS_IE
+// CHECK-NEXT: # Relocation 0x00000007
+// CHECK-NEXT: (('r_offset', 0x0000002b)
+// CHECK-NEXT:  ('r_sym', 0x0000000b)
+// CHECK-NEXT:  ('r_type', 0x0000000f)
+// CHECK-NEXT: ),
+
+// Relocation 8 (foo at NTPOFF) is of type R_386_TLS_LE
+// CHECK-NEXT: # Relocation 0x00000008
+// CHECK-NEXT: (('r_offset', 0x00000031)
+// CHECK-NEXT:  ('r_sym', 0x0000000b)
+// CHECK-NEXT:  ('r_type', 0x00000011)
+
         .text
 bar:
 	leal	.Lfoo at GOTOFF(%ebx), %eax
@@ -66,6 +93,11 @@
 
         movl	bar2j at GOT(%eax), %eax
 
+        leal foo at TLSGD(, %ebx,1), %eax
+        movl $foo at TPOFF, %edx
+        movl foo at INDNTPOFF, %ecx
+        addl foo at NTPOFF(%eax), %eax
+
         .section	.rodata.str1.16,"aMS", at progbits,1
 .Lfoo:
 	.asciz	 "bool llvm::llvm_start_multithreaded()"



From resistor at mac.com  Wed Oct 27 16:28:09 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 21:28:09 -0000
Subject: [llvm-commits] [llvm] r117495 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
 test/MC/ARM/neon-mov-encoding.ll
Message-ID: <20101027212809.E4C932A6C139@llvm.org>

Author: resistor
Date: Wed Oct 27 16:28:09 2010
New Revision: 117495

URL: http://llvm.org/viewvc/llvm-project?rev=117495&view=rev
Log:
Provide correct encodings for the get_lane and set_lane variants of vmov.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-mov-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117495&r1=117494&r2=117495&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Oct 27 16:28:09 2010
@@ -1868,14 +1868,15 @@
   let Pattern = pattern;
   list<Predicate> Predicates = [HasNEON];
   
-  bits<5> Vd;
-  bits<4> Rt;
+  bits<5> V;
+  bits<4> R;
   bits<4> p;
+  bits<4> lane;
   
   let Inst{31-28} = p{3-0};
-  let Inst{7}     = Vd{4};
-  let Inst{19-16} = Vd{3-0};
-  let Inst{15-12} = Rt{3-0};
+  let Inst{7}     = V{4};
+  let Inst{19-16} = V{3-0};
+  let Inst{15-12} = R{3-0};
 }
 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
                 dag oops, dag iops, InstrItinClass itin,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117495&r1=117494&r2=117495&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Oct 27 16:28:09 2010
@@ -3501,30 +3501,44 @@
 //   VMOV     : Vector Get Lane (move scalar to ARM core register)
 
 def VGETLNs8  : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
-                          (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
-                          IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
-                          [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
-                                           imm:$lane))]>;
+                          (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+                          IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
+                          [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
+                                           imm:$lane))]> {
+  let Inst{21}  = lane{2};
+  let Inst{6-5} = lane{1-0};
+}
 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
-                          (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
-                          IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
-                          [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
-                                           imm:$lane))]>;
+                          (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+                          IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
+                          [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
+                                           imm:$lane))]> {
+  let Inst{21} = lane{1};
+  let Inst{6}  = lane{0};
+}
 def VGETLNu8  : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
-                          (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
-                          IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
-                          [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
-                                           imm:$lane))]>;
+                          (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+                          IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
+                          [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
+                                           imm:$lane))]> {
+  let Inst{21}  = lane{2};
+  let Inst{6-5} = lane{1-0};
+}
 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
-                          (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
-                          IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
-                          [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
-                                           imm:$lane))]>;
+                          (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+                          IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
+                          [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
+                                           imm:$lane))]> {
+  let Inst{21} = lane{1};
+  let Inst{6}  = lane{0};
+}
 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
-                          (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
-                          IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
-                          [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
-                                           imm:$lane))]>;
+                          (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+                          IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
+                          [(set GPR:$R, (extractelt (v2i32 DPR:$V),
+                                           imm:$lane))]> {
+  let Inst{21} = lane{0};
+}
 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
           (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
@@ -3560,22 +3574,30 @@
 
 //   VMOV     : Vector Set Lane (move ARM core register to scalar)
 
-let Constraints = "$src1 = $dst" in {
-def VSETLNi8  : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
-                          (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
-                          IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
-                          [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
-                                           GPR:$src2, imm:$lane))]>;
-def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
-                          (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
-                          IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
-                          [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
-                                           GPR:$src2, imm:$lane))]>;
-def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
-                          (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
-                          IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
-                          [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
-                                           GPR:$src2, imm:$lane))]>;
+let Constraints = "$src1 = $V" in {
+def VSETLNi8  : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
+                          (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
+                          IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
+                          [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
+                                           GPR:$R, imm:$lane))]> {
+  let Inst{21}  = lane{2};
+  let Inst{6-5} = lane{1-0};
+}
+def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
+                          (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
+                          IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
+                          [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
+                                           GPR:$R, imm:$lane))]> {
+  let Inst{21} = lane{1};
+  let Inst{6}  = lane{0};
+}
+def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
+                          (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
+                          IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
+                          [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
+                                           GPR:$R, imm:$lane))]> {
+  let Inst{21} = lane{0};
+}
 }
 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
           (v16i8 (INSERT_SUBREG QPR:$src1, 

Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.ll?rev=117495&r1=117494&r2=117495&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mov-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-mov-encoding.ll Wed Oct 27 16:28:09 2010
@@ -304,4 +304,128 @@
 
 declare <8 x i8>  @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
 declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
\ No newline at end of file
+declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
+
+define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vmov.s8	r0, d16[1]              @ encoding: [0xb0,0x0b,0x50,0xee]
+	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
+	%tmp3 = sext i8 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vmov.s16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x10,0xee]
+	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
+	%tmp3 = sext i16 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vmov.u8	r0, d16[1]              @ encoding: [0xb0,0x0b,0xd0,0xee]
+	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
+	%tmp3 = zext i8 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vmov.u16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x90,0xee]
+	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
+	%tmp3 = zext i16 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+; Do a vector add to keep the extraction from being done directly from memory.
+define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+	%tmp2 = add <2 x i32> %tmp1, %tmp1
+; CHECK: vmov.32	r0, d16[1]              @ encoding: [0x90,0x0b,0x30,0xee]
+	%tmp3 = extractelement <2 x i32> %tmp2, i32 1
+	ret i32 %tmp3
+}
+
+define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vmov.s8	r0, d16[1]              @ encoding: [0xb0,0x0b,0x50,0xee]
+	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
+	%tmp3 = sext i8 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vmov.s16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x10,0xee]
+	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
+	%tmp3 = sext i16 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vmov.u8	r0, d16[1]              @ encoding: [0xb0,0x0b,0xd0,0xee]
+	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
+	%tmp3 = zext i8 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vmov.u16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x90,0xee]
+	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
+	%tmp3 = zext i16 %tmp2 to i32
+	ret i32 %tmp3
+}
+
+; Do a vector add to keep the extraction from being done directly from memory.
+define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = add <4 x i32> %tmp1, %tmp1
+; CHECK: vmov.32	r0, d16[1]              @ encoding: [0x90,0x0b,0x30,0xee]
+	%tmp3 = extractelement <4 x i32> %tmp2, i32 1
+	ret i32 %tmp3
+}
+
+define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vmov.8	d16[1], r1              @ encoding: [0xb0,0x1b,0x40,0xee]
+	%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vmov.16	d16[1], r1              @ encoding: [0xf0,0x1b,0x00,0xee
+	%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vmov.32	d16[1], r1              @ encoding: [0x90,0x1b,0x20,0xee]
+	%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vmov.8	d18[1], r1              @ encoding: [0xb0,0x1b,0x42,0xee]
+	%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vmov.16	d18[1], r1              @ encoding: [0xf0,0x1b,0x02,0xee]
+	%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vmov.32	d18[1], r1              @ encoding: [0x90,0x1b,0x22,0xee]
+	%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
+	ret <4 x i32> %tmp2
+}



From grosbach at apple.com  Wed Oct 27 16:39:08 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 21:39:08 -0000
Subject: [llvm-commits] [llvm] r117496 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20101027213908.7B5C92A6C13B@llvm.org>

Author: grosbach
Date: Wed Oct 27 16:39:08 2010
New Revision: 117496

URL: http://llvm.org/viewvc/llvm-project?rev=117496&view=rev
Log:
Trailing whitespace

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=117496&r1=117495&r2=117496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 27 16:39:08 2010
@@ -684,9 +684,9 @@
 }
 
 void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
-  
+
   assert(VT.isSimple() && "Non-simple types are invalid here!");
-  
+
   bool needsLowering = false;
   switch (VT.getSimpleVT().SimpleTy) {
     default:
@@ -704,7 +704,7 @@
       needsLowering = ((Offset & 0xff) != Offset);
       break;
   }
-  
+
   // Since the offset is too large for the load/store instruction
   // get the reg+offset into a register.
   if (needsLowering) {
@@ -766,14 +766,14 @@
   }
 
   ResultReg = createResultReg(RC);
-  
+
   ARMSimplifyRegOffset(Base, Offset, VT);
-  
+
   // addrmode5 output depends on the selection dag addressing dividing the
   // offset by 4 that it then later multiplies. Do this here as well.
   if (isFloat)
     Offset /= 4;
-  
+
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                           TII.get(Opc), ResultReg)
                   .addReg(Base).addImm(Offset));
@@ -830,12 +830,12 @@
   }
 
   ARMSimplifyRegOffset(Base, Offset, VT);
-  
+
   // addrmode5 output depends on the selection dag addressing dividing the
   // offset by 4 that it then later multiplies. Do this here as well.
   if (isFloat)
     Offset /= 4;
-  
+
   // The thumb addressing mode has operands swapped from the arm addressing
   // mode, the floating point one only has two operands.
   if (isFloat || isThumb)
@@ -1242,12 +1242,12 @@
                                  EVT SrcVT, unsigned &ResultReg) {
   unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
                            Src, /*TODO: Kill=*/false);
-  
+
   if (RR != 0) {
     ResultReg = RR;
     return true;
   } else
-    return false;                                   
+    return false;
 }
 
 // This is largely taken directly from CCAssignFnForNode - we don't support
@@ -1365,7 +1365,7 @@
     } else if (VA.needsCustom()) {
       // TODO: We need custom lowering for vector (v2f64) args.
       if (VA.getLocVT() != MVT::f64) return false;
-      
+
       CCValAssign &NextVA = ArgLocs[++i];
 
       // TODO: Only handle register args for now.
@@ -1418,7 +1418,7 @@
 
       UsedRegs.push_back(RVLocs[0].getLocReg());
       UsedRegs.push_back(RVLocs[1].getLocReg());
-      
+
       // Finally update the result.
       UpdateValueMap(I, ResultReg);
     } else {
@@ -1442,10 +1442,10 @@
 bool ARMFastISel::SelectRet(const Instruction *I) {
   const ReturnInst *Ret = cast<ReturnInst>(I);
   const Function &F = *I->getParent()->getParent();
-  
+
   if (!FuncInfo.CanLowerReturn)
     return false;
-    
+
   if (F.isVarArg())
     return false;
 
@@ -1470,7 +1470,7 @@
       return false;
 
     CCValAssign &VA = ValLocs[0];
-  
+
     // Don't bother handling odd stuff for now.
     if (VA.getLocInfo() != CCValAssign::Full)
       return false;
@@ -1481,7 +1481,7 @@
     // says Full but the types don't match.
     if (VA.getValVT() != TLI.getValueType(RV->getType()))
       return false;
-    
+
     // Make the copy.
     unsigned SrcReg = Reg + VA.getValNo();
     unsigned DstReg = VA.getLocReg();
@@ -1495,7 +1495,7 @@
     // Mark the register as live out of the function.
     MRI.addLiveOut(VA.getLocReg());
   }
-  
+
   unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                           TII.get(RetOpc)));



From bob.wilson at apple.com  Wed Oct 27 17:29:09 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 27 Oct 2010 22:29:09 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r117499 -
	/llvm-gcc-4.2/trunk/build_gcc
Message-ID: <20101027222909.0E1A12A6C149@llvm.org>

Author: bwilson
Date: Wed Oct 27 17:29:08 2010
New Revision: 117499

URL: http://llvm.org/viewvc/llvm-project?rev=117499&view=rev
Log:
Reapply svn r103367: Do not install a copy of libstdc++.dylib with llvm-gcc
ARM builds.  Radar 8175283.

Modified:
    llvm-gcc-4.2/trunk/build_gcc

Modified: llvm-gcc-4.2/trunk/build_gcc
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=117499&r1=117498&r2=117499&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/build_gcc (original)
+++ llvm-gcc-4.2/trunk/build_gcc Wed Oct 27 17:29:08 2010
@@ -578,18 +578,7 @@
 done
 # APPLE LOCAL end native compiler support
 
-if [ $BUILD_CXX -eq 1 ]; then
-for t in $TARGETS ; do
-    if [ "$t" == 'arm' ] ; then
-        cp -p $ARM_SYSROOT/usr/lib/libstdc++.6.dylib \
-            .$DEST_ROOT/lib/gcc/$t-apple-darwin$DARWIN_VERS/$VERS/libstdc++.dylib \
-            || exit 1
-        # LLVM LOCAL remove libstdc++ copying for non-ARM targets
-    fi
-# LLVM LOCAL
-#  strip -x -c .$DEST_ROOT/lib/gcc/$t-apple-darwin$DARWIN_VERS/$VERS/libstdc++.dylib || exit 1
-done
-fi
+# LLVM LOCAL remove libstdc++ copying
 
 # Add extra man page symlinks for 'c++' and for arch-specific names.
 MDIR=$DEST_DIR$DEST_ROOT/share/man/man1



From resistor at mac.com  Wed Oct 27 17:49:00 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 22:49:00 -0000
Subject: [llvm-commits] [llvm] r117501 - in /llvm/trunk:
 lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMMCCodeEmitter.cpp
 test/MC/ARM/neon-convert-encoding.ll utils/TableGen/EDEmitter.cpp
Message-ID: <20101027224900.E6B372A6C14A@llvm.org>

Author: resistor
Date: Wed Oct 27 17:49:00 2010
New Revision: 117501

URL: http://llvm.org/viewvc/llvm-project?rev=117501&view=rev
Log:
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.

Added:
    llvm/trunk/test/MC/ARM/neon-convert-encoding.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117501&r1=117500&r2=117501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Oct 27 17:49:00 2010
@@ -194,6 +194,8 @@
         Binary |= (Reg << 13);
         return Binary;
       }
+    unsigned getNEONVcvtImm32(const MachineInstr &MI, unsigned Op) const {
+       return 0; }
 
     /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
     /// machine operand requires relocation, record the relocation and return

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117501&r1=117500&r2=117501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Oct 27 17:49:00 2010
@@ -299,6 +299,10 @@
   let PrintMethod = "printPCLabel";
 }
 
+def neon_vcvt_imm32 : Operand<i32> {
+  string EncoderMethod = "getNEONVcvtImm32";
+}
+
 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
   int32_t v = (int32_t)N->getZExtValue();

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117501&r1=117500&r2=117501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Oct 27 17:49:00 2010
@@ -1764,16 +1764,16 @@
               string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
               Intrinsic IntOp>
   : N2VImm<op24, op23, op11_8, op7, 0, op4,
-           (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
-           IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
-           [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
+           (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
+           IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
+           [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
               string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
               Intrinsic IntOp>
   : N2VImm<op24, op23, op11_8, op7, 1, op4,
-           (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
-           IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
-           [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
+           (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
+           IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
+           [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
 
 //===----------------------------------------------------------------------===//
 // Multiclasses

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117501&r1=117500&r2=117501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Oct 27 17:49:00 2010
@@ -91,6 +91,10 @@
   unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
     return MI.getOperand(Op).getImm() - 1;
   }
+  
+  unsigned getNEONVcvtImm32(const MCInst &MI, unsigned Op) const {
+    return 64 - MI.getOperand(Op).getImm();
+  }
 
   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
 

Added: llvm/trunk/test/MC/ARM/neon-convert-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-convert-encoding.ll?rev=117501&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-convert-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-convert-encoding.ll Wed Oct 27 17:49:00 2010
@@ -0,0 +1,122 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vcvt.s32.f32	d16, d16        @ encoding: [0x20,0x07,0xfb,0xf3]
+	%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
+	ret <2 x i32> %tmp2
+}
+
+define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vcvt.u32.f32	d16, d16        @ encoding: [0xa0,0x07,0xfb,0xf3]
+	%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
+	ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vcvt.f32.s32	d16, d16        @ encoding: [0x20,0x06,0xfb,0xf3]
+	%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
+	ret <2 x float> %tmp2
+}
+
+define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vcvt.f32.u32	d16, d16        @ encoding: [0xa0,0x06,0xfb,0xf3]
+	%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
+	ret <2 x float> %tmp2
+}
+
+define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vcvt.s32.f32	q8, q8          @ encoding: [0x60,0x07,0xfb,0xf3]
+	%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
+	ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vcvt.u32.f32	q8, q8          @ encoding: [0xe0,0x07,0xfb,0xf3]
+	%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
+	ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vcvt.f32.s32	q8, q8          @ encoding: [0x60,0x06,0xfb,0xf3]
+	%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
+	ret <4 x float> %tmp2
+}
+
+define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vcvt.f32.u32	q8, q8          @ encoding: [0xe0,0x06,0xfb,0xf3]
+	%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
+	ret <4 x float> %tmp2
+}
+
+define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vcvt.s32.f32	d16, d16, #1    @ encoding: [0x30,0x0f,0xff,0xf2
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
+	ret <2 x i32> %tmp2
+}
+
+define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
+	%tmp1 = load <2 x float>* %A
+; CHECK: vcvt.u32.f32	d16, d16, #1    @ encoding: [0x30,0x0f,0xff,0xf3]
+	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
+	ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vcvt.f32.s32	d16, d16, #1    @ encoding: [0x30,0x0e,0xff,0xf2]
+	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
+	ret <2 x float> %tmp2
+}
+
+define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vcvt.f32.u32	d16, d16, #1    @ encoding: [0x30,0x0e,0xff,0xf3]
+	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
+	ret <2 x float> %tmp2
+}
+
+declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
+
+define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+; CHECK: vcvt.s32.f32	q8, q8, #1      @ encoding: [0x70,0x0f,0xff,0xf2]
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
+	ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
+	ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vcvt.u32.f32	q8, q8, #1      @ encoding: [0x70,0x0f,0xff,0xf3]
+	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
+	ret <4 x float> %tmp2
+}
+
+define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vcvt.f32.u32	q8, q8, #1      @ encoding: [0x70,0x0e,0xff,0xf3]
+	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
+	ret <4 x float> %tmp2
+}
+
+declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=117501&r1=117500&r2=117501&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Oct 27 17:49:00 2010
@@ -582,6 +582,7 @@
   IMM("t_imm_s4");
   IMM("pclabel");
   IMM("shift_imm");
+  IMM("neon_vcvt_imm32");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
   MISC("so_reg", "kOperandTypeARMSoReg");                         // R, R, I



From resistor at mac.com  Wed Oct 27 17:54:49 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 27 Oct 2010 22:54:49 -0000
Subject: [llvm-commits] [llvm] r117502 -
	/llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll
Message-ID: <20101027225449.DCCC42A6C14A@llvm.org>

Author: resistor
Date: Wed Oct 27 17:54:49 2010
New Revision: 117502

URL: http://llvm.org/viewvc/llvm-project?rev=117502&view=rev
Log:
Tests for NEON encoding of vrev.

Added:
    llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll

Added: llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll?rev=117502&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll (added)
+++ llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll Wed Oct 27 17:54:49 2010
@@ -0,0 +1,85 @@
+; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vrev64.8	d16, d16        @ encoding: [0x20,0x00,0xf0,0xf3]
+	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vrev64.16	d16, d16        @ encoding: [0x20,0x00,0xf4,0xf3]
+	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+	ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vrev64.32	d16, d16        @ encoding: [0x20,0x00,0xf8,0xf3]
+	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+	ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vrev64.8	q8, q8          @ encoding: [0x60,0x00,0xf0,0xf3]
+	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vrev64.16	q8, q8          @ encoding: [0x60,0x00,0xf4,0xf3]
+	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+	ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vrev64.32	q8, q8          @ encoding: [0x60,0x00,0xf8,0xf3]
+	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+	ret <4 x i32> %tmp2
+}
+
+define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vrev32.8	d16, d16        @ encoding: [0xa0,0x00,0xf0,0xf3]
+	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+	ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vrev32.16	d16, d16        @ encoding: [0xa0,0x00,0xf4,0xf3]
+	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+	ret <4 x i16> %tmp2
+}
+
+define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vrev32.8	q8, q8          @ encoding: [0xe0,0x00,0xf0,0xf3]
+	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+	ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vrev32.16	q8, q8          @ encoding: [0xe0,0x00,0xf4,0xf3]
+	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+	ret <8 x i16> %tmp2
+}
+
+define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vrev16.8	d16, d16        @ encoding: [0x20,0x01,0xf0,0xf3]
+	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+	ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vrev16.8	q8, q8          @ encoding: [0x60,0x01,0xf0,0xf3]
+	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+	ret <16 x i8> %tmp2
+}



From grosbach at apple.com  Wed Oct 27 18:12:14 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 27 Oct 2010 23:12:14 -0000
Subject: [llvm-commits] [llvm] r117505 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMBaseInstrInfo.cpp ARMBaseRegisterInfo.cpp
 ARMCodeEmitter.cpp ARMFastISel.cpp ARMInstrFormats.td ARMInstrInfo.cpp
 ARMInstrInfo.td ARMLoadStoreOptimizer.cpp
Message-ID: <20101027231214.B0BD32A6C14B@llvm.org>

Author: grosbach
Date: Wed Oct 27 18:12:14 2010
New Revision: 117505

URL: http://llvm.org/viewvc/llvm-project?rev=117505&view=rev
Log:
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117505&r1=117504&r2=117505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Oct 27 18:12:14 2010
@@ -870,8 +870,8 @@
     switch (MI->getOpcode()) {
     default:
       llvm_unreachable("Unexpected opcode!");
-    case ARM::PICSTR:   Opcode = ARM::STR; break;
-    case ARM::PICSTRB:  Opcode = ARM::STRB; break;
+    case ARM::PICSTR:   Opcode = ARM::STRrs; break;
+    case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
@@ -1161,10 +1161,9 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::STR);
+      TmpInst.setOpcode(ARM::STRi12);
       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       TmpInst.addOperand(MCOperand::CreateImm(4));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117505&r1=117504&r2=117505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 27 18:12:14 2010
@@ -676,9 +676,9 @@
 
   switch (RC->getID()) {
   case ARM::GPRRegClassID:
-    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
                    .addReg(SrcReg, getKillRegState(isKill))
-                   .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
+                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
     break;
   case ARM::SPRRegClassID:
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
@@ -755,7 +755,7 @@
                                      int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
-  case ARM::STR:
+  case ARM::STRrs:
   case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
     if (MI->getOperand(1).isFI() &&
         MI->getOperand(2).isReg() &&
@@ -766,6 +766,7 @@
       return MI->getOperand(0).getReg();
     }
     break;
+  case ARM::STRi12:
   case ARM::t2STRi12:
   case ARM::tSpill:
   case ARM::VSTRD:

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=117505&r1=117504&r2=117505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Oct 27 18:12:14 2010
@@ -1377,7 +1377,7 @@
   unsigned Opc = MI->getOpcode();
   switch (Opc) {
   case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
-  case ARM::STR: case ARM::STRH: case ARM::STRB:
+  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
   case ARM::t2LDRi12: case ARM::t2LDRi8:
   case ARM::t2STRi12: case ARM::t2STRi8:
   case ARM::VLDRS: case ARM::VLDRD:
@@ -1711,7 +1711,7 @@
 
   // Build the new SUBri