From sabre at nondot.org Mon Nov 1 00:06:46 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 05:06:46 -0000 Subject: [llvm-commits] [llvm] r117899 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101101050646.261D82A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 00:06:45 2010 New Revision: 117899 URL: http://llvm.org/viewvc/llvm-project?rev=117899&view=rev Log: rename InstructionInfo -> MatchableInfo since it now represents InstAliases as well. Rename isAssemblerInstruction -> Validate since that is what it does (modulo the ARM $lane hack). Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=117899&r1=117898&r2=117899&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Nov 1 00:06:45 2010 @@ -320,9 +320,9 @@ } }; -/// InstructionInfo - Helper class for storing the necessary information for an -/// instruction which is capable of being matched. -struct InstructionInfo { +/// MatchableInfo - Helper class for storing the necessary information for an +/// instruction or alias which is capable of being matched. +struct MatchableInfo { struct Operand { /// The unique class instance this operand should match. ClassInfo *Class; @@ -355,11 +355,11 @@ /// function. std::string ConversionFnKind; - InstructionInfo(const CodeGenInstruction &CGI) + MatchableInfo(const CodeGenInstruction &CGI) : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) { } - InstructionInfo(const CodeGenInstAlias *Alias) + MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), OperandList(Alias->Operands), AsmString(Alias->AsmString) { @@ -368,17 +368,17 @@ void Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters); - /// isAssemblerInstruction - Return true if this matchable is a valid thing to - /// match against. - bool isAssemblerInstruction(StringRef CommentDelimiter) const; + /// Validate - Return true if this matchable is a valid thing to match against + /// and perform a bunch of validity checking. + bool Validate(StringRef CommentDelimiter, bool Hack) const; /// getSingletonRegisterForToken - If the specified token is a singleton /// register, return the Record for it, otherwise return null. Record *getSingletonRegisterForToken(unsigned i, const AsmMatcherInfo &Info) const; - /// operator< - Compare two instructions. - bool operator<(const InstructionInfo &RHS) const { + /// operator< - Compare two matchables. + bool operator<(const MatchableInfo &RHS) const { // The primary comparator is the instruction mnemonic. if (Tokens[0] != RHS.Tokens[0]) return Tokens[0] < RHS.Tokens[0]; @@ -398,10 +398,10 @@ return false; } - /// CouldMatchAmiguouslyWith - Check whether this instruction could + /// CouldMatchAmiguouslyWith - Check whether this matchable could /// ambiguously match the same set of operands as \arg RHS (without being a /// strictly superior match). - bool CouldMatchAmiguouslyWith(const InstructionInfo &RHS) { + bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) { // The number of operands is unambiguous. if (Operands.size() != RHS.Operands.size()) return false; @@ -467,8 +467,8 @@ /// The classes which are needed for matching. std::vector Classes; - /// The information on the instruction to match. - std::vector Instructions; + /// The information on the matchables to match. + std::vector Matchables; /// Map of Register records to their class information. std::map RegisterClasses; @@ -520,7 +520,7 @@ } -void InstructionInfo::dump() { +void MatchableInfo::dump() { errs() << InstrName << " -- " << "flattened:\"" << AsmString << '\"' << ", tokens:["; for (unsigned i = 0, e = Tokens.size(); i != e; ++i) { @@ -549,8 +549,8 @@ } } -void InstructionInfo::Initialize(const AsmMatcherInfo &Info, - SmallPtrSet &SingletonRegisters) { +void MatchableInfo::Initialize(const AsmMatcherInfo &Info, + SmallPtrSet &SingletonRegisters) { InstrName = TheDef->getName(); // TODO: Eventually support asmparser for Variant != 0. @@ -584,12 +584,12 @@ return 0; } -bool InstructionInfo::isAssemblerInstruction(StringRef CommentDelimiter) const { - // Reject instructions with no .s string. +bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { + // Reject matchables with no .s string. if (AsmString.empty()) throw TGError(TheDef->getLoc(), "instruction with empty asm string"); - // Reject any instructions with a newline in them, they should be marked + // Reject any matchables with a newline in them, they should be marked // isCodeGenOnly if they are pseudo instructions. if (AsmString.find('\n') != std::string::npos) throw TGError(TheDef->getLoc(), @@ -604,8 +604,9 @@ "asmstring for instruction has comment character in it, " "mark it isCodeGenOnly"); - // Reject instructions with attributes, these aren't something we can handle, - // the target should be refactored to use operands instead of modifiers. + // Reject matchables with operand modifiers, these aren't something we can + /// handle, the target should be refactored to use operands instead of + /// modifiers. // // Also, check for instructions which reference the operand multiple times; // this implies a constraint we would not honor. @@ -613,16 +614,21 @@ for (unsigned i = 1, e = Tokens.size(); i < e; ++i) { if (Tokens[i][0] == '$' && Tokens[i].find(':') != StringRef::npos) throw TGError(TheDef->getLoc(), - "instruction with operand modifier '" + Tokens[i].str() + + "matchable with operand modifier '" + Tokens[i].str() + "' not supported by asm matcher. Mark isCodeGenOnly!"); - // FIXME: Should reject these. The ARM backend hits this with $lane in a - // bunch of instructions. It is unclear what the right answer is for this. + // Verify that any operand is only mentioned once. if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) { + if (!Hack) + throw TGError(TheDef->getLoc(), + "ERROR: matchable with tied operand '" + Tokens[i].str() + + "' can never be matched!"); + // FIXME: Should reject these. The ARM backend hits this with $lane in a + // bunch of instructions. It is unclear what the right answer is. DEBUG({ errs() << "warning: '" << InstrName << "': " - << "ignoring instruction with tied operand '" - << Tokens[i].str() << "'\n"; + << "ignoring instruction with tied operand '" + << Tokens[i].str() << "'\n"; }); return false; } @@ -634,7 +640,7 @@ /// getSingletonRegisterForToken - If the specified token is a singleton /// register, return the register name, otherwise return a null StringRef. -Record *InstructionInfo:: +Record *MatchableInfo:: getSingletonRegisterForToken(unsigned i, const AsmMatcherInfo &Info) const { StringRef Tok = Tokens[i]; if (!Tok.startswith(Info.RegisterPrefix)) @@ -935,13 +941,13 @@ if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) continue; - OwningPtr II(new InstructionInfo(CGI)); + OwningPtr II(new MatchableInfo(CGI)); II->Initialize(*this, SingletonRegisters); // Ignore instructions which shouldn't be matched and diagnose invalid // instruction definitions with an error. - if (!II->isAssemblerInstruction(CommentDelimiter)) + if (!II->Validate(CommentDelimiter, true)) continue; // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. @@ -951,7 +957,7 @@ StringRef(II->InstrName).endswith("_Int")) continue; - Instructions.push_back(II.take()); + Matchables.push_back(II.take()); } // Parse all of the InstAlias definitions and stick them in the list of @@ -961,11 +967,14 @@ for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]); - OwningPtr II(new InstructionInfo(Alias)); + OwningPtr II(new MatchableInfo(Alias)); II->Initialize(*this, SingletonRegisters); - //Instructions.push_back(II.take()); + // Validate the alias definitions. + II->Validate(CommentDelimiter, false); + + //Matchables.push_back(II.take()); } // Build info for the register classes. @@ -974,10 +983,10 @@ // Build info for the user defined assembly operand classes. BuildOperandClasses(); - // Build the instruction information. - for (std::vector::iterator it = Instructions.begin(), - ie = Instructions.end(); it != ie; ++it) { - InstructionInfo *II = *it; + // Build the information about matchables. + for (std::vector::iterator it = Matchables.begin(), + ie = Matchables.end(); it != ie; ++it) { + MatchableInfo *II = *it; // The first token of the instruction is the mnemonic, which must be a // simple string, not a $foo variable or a singleton register. @@ -993,7 +1002,7 @@ // Check for singleton registers. if (Record *RegRecord = II->getSingletonRegisterForToken(i, *this)) { - InstructionInfo::Operand Op; + MatchableInfo::Operand Op; Op.Class = RegisterClasses[RegRecord]; Op.OperandInfo = 0; assert(Op.Class && Op.Class->Registers.size() == 1 && @@ -1004,7 +1013,7 @@ // Check for simple tokens. if (Token[0] != '$') { - InstructionInfo::Operand Op; + MatchableInfo::Operand Op; Op.Class = getTokenClass(Token); Op.OperandInfo = 0; II->Operands.push_back(Op); @@ -1044,7 +1053,7 @@ assert(OI && "Unable to find tied operand target!"); } - InstructionInfo::Operand Op; + MatchableInfo::Operand Op; Op.Class = getOperandClass(Token, *OI); Op.OperandInfo = OI; II->Operands.push_back(Op); @@ -1066,7 +1075,7 @@ } static void EmitConvertToMCInst(CodeGenTarget &Target, - std::vector &Infos, + std::vector &Infos, raw_ostream &OS) { // Write the convert function to a separate stream, so we can drop it after // the enum. @@ -1094,14 +1103,14 @@ // TargetOperandClass - This is the target's operand class, like X86Operand. std::string TargetOperandClass = Target.getName() + "Operand"; - for (std::vector::const_iterator it = Infos.begin(), + for (std::vector::const_iterator it = Infos.begin(), ie = Infos.end(); it != ie; ++it) { - InstructionInfo &II = **it; + MatchableInfo &II = **it; // Order the (class) operands by the order to convert them into an MCInst. SmallVector, 4> MIOperandList; for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[i]; + MatchableInfo::Operand &Op = II.Operands[i]; if (Op.OperandInfo) MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i)); } @@ -1132,7 +1141,7 @@ std::string Signature = "Convert"; unsigned CurIndex = 0; for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second]; + MatchableInfo::Operand &Op = II.Operands[MIOperandList[i].second]; assert(CurIndex <= Op.OperandInfo->MIOperandNo && "Duplicate match for instruction operand!"); @@ -1191,7 +1200,7 @@ CvtOS << " case " << Signature << ":\n"; CurIndex = 0; for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second]; + MatchableInfo::Operand &Op = II.Operands[MIOperandList[i].second]; // Add the implicit operands. for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { @@ -1591,26 +1600,26 @@ // Sort the instruction table using the partial order on classes. We use // stable_sort to ensure that ambiguous instructions are still // deterministically ordered. - std::stable_sort(Info.Instructions.begin(), Info.Instructions.end(), - less_ptr()); + std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(), + less_ptr()); DEBUG_WITH_TYPE("instruction_info", { - for (std::vector::iterator - it = Info.Instructions.begin(), ie = Info.Instructions.end(); + for (std::vector::iterator + it = Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) (*it)->dump(); }); - // Check for ambiguous instructions. + // Check for ambiguous matchables. DEBUG_WITH_TYPE("ambiguous_instrs", { unsigned NumAmbiguous = 0; - for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) { + for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) { for (unsigned j = i + 1; j != e; ++j) { - InstructionInfo &A = *Info.Instructions[i]; - InstructionInfo &B = *Info.Instructions[j]; + MatchableInfo &A = *Info.Matchables[i]; + MatchableInfo &B = *Info.Matchables[j]; if (A.CouldMatchAmiguouslyWith(B)) { - errs() << "warning: ambiguous instruction match:\n"; + errs() << "warning: ambiguous matchables:\n"; A.dump(); errs() << "\nis incomparable with:\n"; B.dump(); @@ -1621,7 +1630,7 @@ } if (NumAmbiguous) errs() << "warning: " << NumAmbiguous - << " ambiguous instructions!\n"; + << " ambiguous matchables!\n"; }); // Write the output. @@ -1666,7 +1675,7 @@ bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info); // Generate the unified function to convert operands into an MCInst. - EmitConvertToMCInst(Target, Info.Instructions, OS); + EmitConvertToMCInst(Target, Info.Matchables, OS); // Emit the enumeration for classes which participate in matching. EmitMatchClassEnumeration(Target, Info.Classes, OS); @@ -1685,8 +1694,8 @@ size_t MaxNumOperands = 0; - for (std::vector::const_iterator it = - Info.Instructions.begin(), ie = Info.Instructions.end(); + for (std::vector::const_iterator it = + Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size()); @@ -1726,18 +1735,18 @@ OS << "} // end anonymous namespace.\n\n"; OS << "static const MatchEntry MatchTable[" - << Info.Instructions.size() << "] = {\n"; + << Info.Matchables.size() << "] = {\n"; - for (std::vector::const_iterator it = - Info.Instructions.begin(), ie = Info.Instructions.end(); + for (std::vector::const_iterator it = + Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) { - InstructionInfo &II = **it; + MatchableInfo &II = **it; OS << " { " << Target.getName() << "::" << II.InstrName << ", \"" << II.Tokens[0] << "\"" << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[i]; + MatchableInfo::Operand &Op = II.Operands[i]; if (i) OS << ", "; OS << Op.Class->Name; @@ -1812,7 +1821,7 @@ OS << " // Search the table.\n"; OS << " std::pair MnemonicRange =\n"; OS << " std::equal_range(MatchTable, MatchTable+" - << Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n"; + << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n"; OS << " // Return a more specific error code if no mnemonics match.\n"; OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; From resistor at mac.com Mon Nov 1 00:23:58 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 05:23:58 -0000 Subject: [llvm-commits] [llvm] r117900 - in /llvm/trunk/test/MC/ARM: neon-shift-encoding.ll neon-shift-encoding.s Message-ID: <20101101052358.4C9482A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 00:23:58 2010 New Revision: 117900 URL: http://llvm.org/viewvc/llvm-project?rev=117900&view=rev Log: Convert this test to .s form. Added: llvm/trunk/test/MC/ARM/neon-shift-encoding.s Removed: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Removed: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117899&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (original) +++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (removed) @@ -1,697 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -; XFAIL: * - -; CHECK: vshls_8xi8 -define <8 x i8> @vshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] - %tmp3 = shl <8 x i8> %tmp1, %tmp2 - ret <8 x i8> %tmp3 -} - -; CHECK: vshls_4xi16 -define <4 x i16> @vshls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] - %tmp3 = shl <4 x i16> %tmp1, %tmp2 - ret <4 x i16> %tmp3 -} - -; CHECK: vshls_2xi32 -define <2 x i32> @vshls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] - %tmp3 = shl <2 x i32> %tmp1, %tmp2 - ret <2 x i32> %tmp3 -} - -; CHECK: vshls_1xi64 -define <1 x i64> @vshls_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] - %tmp3 = shl <1 x i64> %tmp1, %tmp2 - ret <1 x i64> %tmp3 -} - -; CHECK: vshli_8xi8 -define <8 x i8> @vshli_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] - %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > - ret <8 x i8> %tmp2 -} - -; CHECK: vshli_4xi16 -define <4 x i16> @vshli_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2 - %tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 > - ret <4 x i16> %tmp2 -} - -; CHECK: vshli_2xi32 -define <2 x i32> @vshli_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] - %tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 > - ret <2 x i32> %tmp2 -} - -; CHECK: vshli_1xi64 -define <1 x i64> @vshli_1xi64(<1 x i64>* %A) nounwind { - %tmp1 = load <1 x i64>* %A -; CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] - %tmp2 = shl <1 x i64> %tmp1, < i64 63 > - ret <1 x i64> %tmp2 -} - -; CHECK: vshls_16xi8 -define <16 x i8> @vshls_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vshl.u8 q8, q8, q9 @ encoding: [0xe0,0x04,0x42,0xf3] - %tmp3 = shl <16 x i8> %tmp1, %tmp2 - ret <16 x i8> %tmp3 -} - -; CHECK: vshls_8xi16 -define <8 x i16> @vshls_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = shl <8 x i16> %tmp1, %tmp2 - ret <8 x i16> %tmp3 -} - -; CHECK: vshls_4xi32 -define <4 x i32> @vshls_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vshl.u32 q8, q8, q9 @ encoding: [0xe0,0x04,0x62,0xf3] - %tmp3 = shl <4 x i32> %tmp1, %tmp2 - ret <4 x i32> %tmp3 -} - -; CHECK: vshls_2xi64 -define <2 x i64> @vshls_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vshl.u64 q8, q8, q9 @ encoding: [0xe0,0x04,0x72,0xf3] - %tmp3 = shl <2 x i64> %tmp1, %tmp2 - ret <2 x i64> %tmp3 -} - -; CHECK: vshli_16xi8 -define <16 x i8> @vshli_16xi8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] - %tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > - ret <16 x i8> %tmp2 -} - -; CHECK: vshli_8xi16 -define <8 x i16> @vshli_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] - %tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > - ret <8 x i16> %tmp2 -} - -; CHECK: vshli_4xi32 -define <4 x i32> @vshli_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] - %tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 > - ret <4 x i32> %tmp2 -} - -; CHECK: vshli_2xi64 -define <2 x i64> @vshli_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] - %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 > - ret <2 x i64> %tmp2 -} - -; CHECK: vshru_8xi8 -define <8 x i8> @vshru_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] - %tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - ret <8 x i8> %tmp2 -} - -; CHECK: vshru_4xi16 -define <4 x i16> @vshru_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3] - %tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > - ret <4 x i16> %tmp2 -} - -; CHECK: vshru_2xi32 -define <2 x i32> @vshru_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3] - %tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 > - ret <2 x i32> %tmp2 -} - -; CHECK: vshru_1xi64 -define <1 x i64> @vshru_1xi64(<1 x i64>* %A) nounwind { - %tmp1 = load <1 x i64>* %A -; CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3] - %tmp2 = lshr <1 x i64> %tmp1, < i64 64 > - ret <1 x i64> %tmp2 -} - -; CHECK: vshru_16xi8 -define <16 x i8> @vshru_16xi8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3] - %tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - ret <16 x i8> %tmp2 -} - -; CHECK: vshru_8xi16 -define <8 x i16> @vshru_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3] - %tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > - ret <8 x i16> %tmp2 -} - -; CHECK: vshru_4xi32 -define <4 x i32> @vshru_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3] - %tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 > - ret <4 x i32> %tmp2 -} - -; CHECK: vshru_2xi64 -define <2 x i64> @vshru_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] - %tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 > - ret <2 x i64> %tmp2 -} - -; CHECK: vshrs_8xi8 -define <8 x i8> @vshrs_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2 - %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - ret <8 x i8> %tmp2 -} - -; CHECK: vshrs_4xi16 -define <4 x i16> @vshrs_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2] - %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > - ret <4 x i16> %tmp2 -} - -; CHECK: vshrs_2xi32 -define <2 x i32> @vshrs_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2] - %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 > - ret <2 x i32> %tmp2 -} - -; CHECK: vshrs_1xi64 -define <1 x i64> @vshrs_1xi64(<1 x i64>* %A) nounwind { - %tmp1 = load <1 x i64>* %A -; CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2] - %tmp2 = ashr <1 x i64> %tmp1, < i64 64 > - ret <1 x i64> %tmp2 -} - -; CHECK: vshrs_16xi8 -define <16 x i8> @vshrs_16xi8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2] - %tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - ret <16 x i8> %tmp2 -} - -; CHECK: vshrs_8xi16 -define <8 x i16> @vshrs_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2] - %tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > - ret <8 x i16> %tmp2 -} - -; CHECK: vshrs_4xi32 -define <4 x i32> @vshrs_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2] - %tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 > - ret <4 x i32> %tmp2 -} - -; CHECK: vshrs_2xi64 -define <2 x i64> @vshrs_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2] - %tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 > - ret <2 x i64> %tmp2 -} - -declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone - -; CHECK: vshlls_8xi8 -define <8 x i16> @vshlls_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] - %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) - ret <8 x i16> %tmp2 -} - -; CHECK: vshlls_4xi16 -define <4 x i32> @vshlls_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] - %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) - ret <4 x i32> %tmp2 -} - -; CHECK: vshlls_2xi32 -define <2 x i64> @vshlls_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] - %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) - ret <2 x i64> %tmp2 -} - -declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone - -; CHECK: vshllu_8xi8 -define <8 x i16> @vshllu_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] - %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) - ret <8 x i16> %tmp2 -} - -; CHECK: vshllu_4xi16 -define <4 x i32> @vshllu_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] - %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) - ret <4 x i32> %tmp2 -} - -; CHECK: vshllu_2xi32 -define <2 x i64> @vshllu_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] - %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) - ret <2 x i64> %tmp2 -} - -; The following tests use the maximum shift count, so the signedness is -; irrelevant. Test both signed and unsigned versions. - -; CHECK: vshlli_8xi8 -define <8 x i16> @vshlli_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] - %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >) - ret <8 x i16> %tmp2 -} - -; CHECK: vshlli_4xi16 -define <4 x i32> @vshlli_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] - %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >) - ret <4 x i32> %tmp2 -} - -; CHECK: vshlli_2xi32 -define <2 x i64> @vshlli_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] - %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >) - ret <2 x i64> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vshrns_8xi16 -define <8 x i8> @vshrns_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] - %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) - ret <8 x i8> %tmp2 -} - -; CHECK: vshrns_4xi32 -define <4 x i16> @vshrns_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] - %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) - ret <4 x i16> %tmp2 -} - -; CHECK: vshrns_2xi64 -define <2 x i32> @vshrns_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] - %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) - ret <2 x i32> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone - -; CHECK: vrshls_8xi8 -define <8 x i8> @vrshls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vrshl.s8 d16, d16, d17 @ encoding: [0xa0,0x05,0x41,0xf2] - %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vrshls_4xi16 -define <4 x i16> @vrshls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vrshl.s16 d16, d16, d17 @ encoding: [0xa0,0x05,0x51,0xf2] - %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vrshls_2xi32 -define <2 x i32> @vrshls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vrshl.s32 d16, d16, d17 @ encoding: [0xa0,0x05,0x61,0xf2] - %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i32> %tmp3 -} - -; CHECK: vrshls_1xi64 -define <1 x i64> @vrshls_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vrshl.s64 d16, d16, d17 @ encoding: [0xa0,0x05,0x71,0xf2] - %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) - ret <1 x i64> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone - -; CHECK: vrshlu_8xi8 -define <8 x i8> @vrshlu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vrshl.u8 d16, d16, d17 @ encoding: [0xa0,0x05,0x41,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vrshlu_4xi16 -define <4 x i16> @vrshlu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vrshl.u16 d16, d16, d17 @ encoding: [0xa0,0x05,0x51,0xf3] - %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vrshlu_2xi32 -define <2 x i32> @vrshlu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vrshl.u32 d16, d16, d17 @ encoding: [0xa0,0x05,0x61,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i32> %tmp3 -} - -; CHECK: vrshlu_1xi64 -define <1 x i64> @vrshlu_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vrshl.u64 d16, d16, d17 @ encoding: [0xa0,0x05,0x71,0xf3] - %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) - ret <1 x i64> %tmp3 -} - -declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vrshls_16xi8 -define <16 x i8> @vrshls_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vrshl.s8 q8, q8, q9 @ encoding: [0xe0,0x05,0x42,0xf2] - %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - ret <16 x i8> %tmp3 -} - -; CHECK: vrshls_8xi16 -define <8 x i16> @vrshls_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vrshl.s16 q8, q8, q9 @ encoding: [0xe0,0x05,0x52,0xf2] - %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i16> %tmp3 -} - -; CHECK: vrshls_4xi32 -define <4 x i32> @vrshls_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vrshl.s32 q8, q8, q9 @ encoding: [0xe0,0x05,0x62,0xf2] - %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i32> %tmp3 -} - -; CHECK: vrshls_2xi64 -define <2 x i64> @vrshls_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vrshl.s64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf2] - %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i64> %tmp3 -} - -declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vrshlu_16xi8 -define <16 x i8> @vrshlu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vrshl.u8 q8, q8, q9 @ encoding: [0xe0,0x05,0x42,0xf3] - %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - ret <16 x i8> %tmp3 -} - -; CHECK: vrshlu_8xi16 -define <8 x i16> @vrshlu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vrshl.u16 q8, q8, q9 @ encoding: [0xe0,0x05,0x52,0xf3] - %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i16> %tmp3 -} - -; CHECK: vrshlu_4xi32 -define <4 x i32> @vrshlu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vrshl.u32 q8, q8, q9 @ encoding: [0xe0,0x05,0x62,0xf3] - %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i32> %tmp3 -} - -; CHECK: vrshlu_2xi64 -define <2 x i64> @vrshlu_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vrshl.u64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf3] - %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i64> %tmp3 -} - -; CHECK: vrshrs_8xi8 -define <8 x i8> @vrshrs_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] - %tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - ret <8 x i8> %tmp2 -} - -; CHECK: vrshrs_4xi16 -define <4 x i16> @vrshrs_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] - %tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) - ret <4 x i16> %tmp2 -} - -; CHECK: vrshrs_2xi32 -define <2 x i32> @vrshrs_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] - %tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) - ret <2 x i32> %tmp2 -} - -; CHECK: vrshrs_1xi64 -define <1 x i64> @vrshrs_1xi64(<1 x i64>* %A) nounwind { - %tmp1 = load <1 x i64>* %A -; CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] - %tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) - ret <1 x i64> %tmp2 -} - -; CHECK: vrshru_8xi8 -define <8 x i8> @vrshru_8xi8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] - %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - ret <8 x i8> %tmp2 -} - -; CHECK: vrshru_4xi16 -define <4 x i16> @vrshru_4xi16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] - %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) - ret <4 x i16> %tmp2 -} - -; CHECK: vrshru_2xi32 -define <2 x i32> @vrshru_2xi32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] - %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) - ret <2 x i32> %tmp2 -} - -; CHECK: vrshru_1xi64 -define <1 x i64> @vrshru_1xi64(<1 x i64>* %A) nounwind { - %tmp1 = load <1 x i64>* %A -; CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] - %tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) - ret <1 x i64> %tmp2 -} - -; CHECK: vrshrs_16xi8 -define <16 x i8> @vrshrs_16xi8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] - %tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - ret <16 x i8> %tmp2 -} - -; CHECK: vrshrs_8xi16 -define <8 x i16> @vrshrs_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] - %tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) - ret <8 x i16> %tmp2 -} - -; CHECK: vrshrs_4xi32 -define <4 x i32> @vrshrs_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] - %tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) - ret <4 x i32> %tmp2 -} - -; CHECK: vrshrs_2xi64 -define <2 x i64> @vrshrs_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] - %tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) - ret <2 x i64> %tmp2 -} - -; CHECK: vrshru_16xi8 -define <16 x i8> @vrshru_16xi8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] - %tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - ret <16 x i8> %tmp2 -} - -; CHECK: vrshru_8xi16 -define <8 x i16> @vrshru_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] - %tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) - ret <8 x i16> %tmp2 -} - -; CHECK: vrshru_4xi32 -define <4 x i32> @vrshru_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] - %tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) - ret <4 x i32> %tmp2 -} - -; CHECK: vrshru_2xi64 -define <2 x i64> @vrshru_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] - %tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) - ret <2 x i64> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vrshrns_8xi16 -define <8 x i8> @vrshrns_8xi16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] - %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) - ret <8 x i8> %tmp2 -} - -; CHECK: vrshrns_4xi32 -define <4 x i16> @vrshrns_4xi32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] - %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) - ret <4 x i16> %tmp2 -} - -; CHECK: vrshrns_2xi64 -define <2 x i32> @vrshrns_2xi64(<2 x i64>* %A) nounwind { - %tmp1 = load <2 x i64>* %A -; CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] - %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) - ret <2 x i32> %tmp2 -} Added: llvm/trunk/test/MC/ARM/neon-shift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=117900&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Mon Nov 1 00:23:58 2010 @@ -0,0 +1,160 @@ +// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s + +// CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] + vshl.u8 d16, d17, d16 +// CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] + vshl.u16 d16, d17, d16 +// CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] + vshl.u32 d16, d17, d16 +// CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] + vshl.u64 d16, d17, d16 +// CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] + vshl.i8 d16, d16, #7 +// CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] + vshl.i16 d16, d16, #15 +// CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] + vshl.i32 d16, d16, #31 +// CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] + vshl.i64 d16, d16, #63 +// CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] + vshl.u8 q8, q9, q8 +// CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] + vshl.u16 q8, q9, q8 +// CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] + vshl.u32 q8, q9, q8 +// CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] + vshl.u64 q8, q9, q8 +// CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] + vshl.i8 q8, q8, #7 +// CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] + vshl.i16 q8, q8, #15 +// CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] + vshl.i32 q8, q8, #31 +// CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] + vshl.i64 q8, q8, #63 +// CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] + vshr.u8 d16, d16, #8 +// CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3] + vshr.u16 d16, d16, #16 +// CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3] + vshr.u32 d16, d16, #32 +// CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3] + vshr.u64 d16, d16, #64 +// CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3] + vshr.u8 q8, q8, #8 +// CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3] + vshr.u16 q8, q8, #16 +// CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3] + vshr.u32 q8, q8, #32 +// CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] + vshr.u64 q8, q8, #64 +// CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2] + vshr.s8 d16, d16, #8 +// CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2] + vshr.s16 d16, d16, #16 +// CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2] + vshr.s32 d16, d16, #32 +// CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2] + vshr.s64 d16, d16, #64 +// CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2] + vshr.s8 q8, q8, #8 +// CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2] + vshr.s16 q8, q8, #16 +// CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2 + vshr.s32 q8, q8, #32 +// CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2] + vshr.s64 q8, q8, #64 +// CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] + vshll.s8 q8, d16, #7 +// CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] + vshll.s16 q8, d16, #15 +// CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] + vshll.s32 q8, d16, #31 +// CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] + vshll.u8 q8, d16, #7 +// CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] + vshll.u16 q8, d16, #15 +// CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] + vshll.u32 q8, d16, #31 +// CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] + vshll.i8 q8, d16, #8 +// CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] + vshll.i16 q8, d16, #16 +// CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] + vshll.i32 q8, d16, #32 +// CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] + vshrn.i16 d16, q8, #8 +// CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] + vshrn.i32 d16, q8, #16 +// CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] + vshrn.i64 d16, q8, #32 +// CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] + vrshl.s8 d16, d17, d16 +// CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] + vrshl.s16 d16, d17, d16 +// CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] + vrshl.s32 d16, d17, d16 +// CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0 + vrshl.s64 d16, d17, d16 +// CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] + vrshl.u8 d16, d17, d16 +// CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] + vrshl.u16 d16, d17, d16 +// CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] + vrshl.u32 d16, d17, d16 +// CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] + vrshl.u64 d16, d17, d16 +// CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] + vrshl.s8 q8, q9, q8 +// CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] + vrshl.s16 q8, q9, q8 +// CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] + vrshl.s32 q8, q9, q8 +// CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] + vrshl.s64 q8, q9, q8 +// CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] + vrshl.u8 q8, q9, q8 +// CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] + vrshl.u16 q8, q9, q8 +// CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] + vrshl.u32 q8, q9, q8 +// CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] + vrshl.u64 q8, q9, q8 +// CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] + vrshr.s8 d16, d16, #8 +// CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] + vrshr.s16 d16, d16, #16 +// CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] + vrshr.s32 d16, d16, #32 +// CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] + vrshr.s64 d16, d16, #64 +// CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] + vrshr.u8 d16, d16, #8 +// CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] + vrshr.u16 d16, d16, #16 +// CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] + vrshr.u32 d16, d16, #32 +// CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] + vrshr.u64 d16, d16, #64 +// CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] + vrshr.s8 q8, q8, #8 +// CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] + vrshr.s16 q8, q8, #16 +// CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] + vrshr.s32 q8, q8, #32 +// CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] + vrshr.s64 q8, q8, #64 +// CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] + vrshr.u8 q8, q8, #8 +// CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] + vrshr.u16 q8, q8, #16 +// CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] + vrshr.u32 q8, q8, #32 +// CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] + vrshr.u64 q8, q8, #64 +// CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] + vrshrn.i16 d16, q8, #8 +// CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] + vrshrn.i32 d16, q8, #16 +// CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] + vrshrn.i64 d16, q8, #32 From sabre at nondot.org Mon Nov 1 00:34:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 05:34:34 -0000 Subject: [llvm-commits] [llvm] r117901 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s utils/TableGen/AsmMatcherEmitter.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h Message-ID: <20101101053434.763B72A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 00:34:34 2010 New Revision: 117901 URL: http://llvm.org/viewvc/llvm-project?rev=117901&view=rev Log: Implement enough of the missing instalias support to get aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-64.s llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117901&r1=117900&r2=117901&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Nov 1 00:34:34 2010 @@ -620,9 +620,6 @@ bool X86ATTAsmParser:: ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) { - // FIXME: This is not correct at all. - if (Name == "movzx") Name = "movzb"; - StringRef PatchedName = Name; // FIXME: Hack to recognize cmp{ss,sd,ps,pd}. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=117901&r1=117900&r2=117901&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 1 00:34:34 2010 @@ -1259,6 +1259,10 @@ //===----------------------------------------------------------------------===// // movsx aliases +def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), + "movsx $src, $dst", + (MOVSX16rr8W GR16:$dst, GR8:$src)>; + def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>; @@ -1266,6 +1270,35 @@ "movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), + "movsx $src, $dst", + (MOVSX64rr8 GR64:$dst, GR8:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR16:$src), + "movsx $src, $dst", + (MOVSX64rr16 GR64:$dst, GR16:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR32:$src), + "movsx $src, $dst", + (MOVSX64rr32 GR64:$dst, GR32:$src)>; + +// movzx aliases +def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), + "movzx $src, $dst", + (MOVZX16rr8W GR16:$dst, GR8:$src)>; + +def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), + "movzx $src, $dst", + (MOVZX32rr8 GR32:$dst, GR8:$src)>; +def : InstAlias<(outs GR32:$dst), (ins GR16:$src), + "movzx $src, $dst", + (MOVZX32rr16 GR32:$dst, GR16:$src)>; + +def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), + "movzx $src, $dst", + (MOVZX64rr8_Q GR64:$dst, GR8:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR16:$src), + "movzx $src, $dst", + (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; +// Note: No GR32->GR64 movzx form. // TODO: lidtl/lidtq can be opcode aliases, perhaps others. Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=117901&r1=117900&r2=117901&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Mon Nov 1 00:34:34 2010 @@ -648,9 +648,51 @@ // CHECK: encoding: [0x48,0x0f,0xb6,0xf0] movzx %al, %rsi -// CHECK: movzbq (%rsp), %rsi -// CHECK: encoding: [0x48,0x0f,0xb6,0x34,0x24] - movzx 0(%rsp), %rsi +// CHECK: movsbw %al, %ax +// CHECK: encoding: [0x66,0x0f,0xbe,0xc0] +movsx %al, %ax + +// CHECK: movsbl %al, %eax +// CHECK: encoding: [0x0f,0xbe,0xc0] +movsx %al, %eax + +// CHECK: movswl %ax, %eax +// CHECK: encoding: [0x0f,0xbf,0xc0] +movsx %ax, %eax + +// CHECK: movsbq %bl, %rax +// CHECK: encoding: [0x48,0x0f,0xbe,0xc3] +movsx %bl, %rax + +// CHECK: movswq %cx, %rax +// CHECK: encoding: [0x48,0x0f,0xbf,0xc1] +movsx %cx, %rax + +// CHECK: movslq %edi, %rax +// CHECK: encoding: [0x48,0x63,0xc7] +movsx %edi, %rax + +// CHECK: movzbw %al, %ax +// CHECK: encoding: [0x66,0x0f,0xb6,0xc0] +movzx %al, %ax + +// CHECK: movzbl %al, %eax +// CHECK: encoding: [0x0f,0xb6,0xc0] +movzx %al, %eax + +// CHECK: movzwl %ax, %eax +// CHECK: encoding: [0x0f,0xb7,0xc0] +movzx %ax, %eax + +// CHECK: movzbq %bl, %rax +// CHECK: encoding: [0x48,0x0f,0xb6,0xc3] +movzx %bl, %rax + +// CHECK: movzwq %cx, %rax +// CHECK: encoding: [0x48,0x0f,0xb7,0xc1] +movzx %cx, %rax + + // rdar://7873482 Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=117901&r1=117900&r2=117901&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Nov 1 00:34:34 2010 @@ -357,12 +357,18 @@ MatchableInfo(const CodeGenInstruction &CGI) : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) { + InstrName = TheDef->getName(); } MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), OperandList(Alias->Operands), AsmString(Alias->AsmString) { - + + // FIXME: Huge hack. + DefInit *DI = dynamic_cast(Alias->Result->getOperator()); + assert(DI); + + InstrName = DI->getDef()->getName(); } void Initialize(const AsmMatcherInfo &Info, @@ -551,8 +557,6 @@ void MatchableInfo::Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters) { - InstrName = TheDef->getName(); - // TODO: Eventually support asmparser for Variant != 0. AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); @@ -974,7 +978,7 @@ // Validate the alias definitions. II->Validate(CommentDelimiter, false); - //Matchables.push_back(II.take()); + Matchables.push_back(II.take()); } // Build info for the register classes. Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=117901&r1=117900&r2=117901&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Mon Nov 1 00:34:34 2010 @@ -110,6 +110,12 @@ MIOperandNo, NumOps, MIOpInfo)); MIOperandNo += NumOps; } + + + // Make sure the constraints list for each operand is large enough to hold + // constraint info, even if none is present. + for (unsigned i = 0, e = OperandList.size(); i != e; ++i) + OperandList[i].Constraints.resize(OperandList[i].MINumOperands); } @@ -235,11 +241,6 @@ } static void ParseConstraints(const std::string &CStr, CGIOperandList &Ops) { - // Make sure the constraints list for each operand is large enough to hold - // constraint info, even if none is present. - for (unsigned i = 0, e = Ops.size(); i != e; ++i) - Ops[i].Constraints.resize(Ops[i].MINumOperands); - if (CStr.empty()) return; const std::string delims(","); @@ -390,5 +391,5 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R) : TheDef(R), Operands(R) { AsmString = R->getValueAsString("AsmString"); - + Result = R->getValueAsDag("ResultInst"); } Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=117901&r1=117900&r2=117901&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Mon Nov 1 00:34:34 2010 @@ -250,6 +250,9 @@ /// to the alias. CGIOperandList Operands; + /// Result - The result instruction. + DagInit *Result; + CodeGenInstAlias(Record *R); }; } From sabre at nondot.org Mon Nov 1 00:41:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 05:41:10 -0000 Subject: [llvm-commits] [llvm] r117902 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s Message-ID: <20101101054110.9FCE32A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 00:41:10 2010 New Revision: 117902 URL: http://llvm.org/viewvc/llvm-project?rev=117902&view=rev Log: "mov[zs]x (mem), GR16" are not ambiguous: the mem must be 8 bits. Support this memory form. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=117902&r1=117901&r2=117902&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 1 00:41:10 2010 @@ -1262,6 +1262,9 @@ def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; +def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), + "movsx $src, $dst", + (MOVSX16rm8W GR16:$dst, i8mem:$src)>; def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), "movsx $src, $dst", @@ -1284,6 +1287,9 @@ def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>; +def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), + "movzx $src, $dst", + (MOVZX16rm8W GR16:$dst, i8mem:$src)>; def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), "movzx $src, $dst", Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=117902&r1=117901&r2=117902&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Mon Nov 1 00:41:10 2010 @@ -692,7 +692,13 @@ // CHECK: encoding: [0x48,0x0f,0xb7,0xc1] movzx %cx, %rax - +// CHECK: movsbw (%rax), %ax +// CHECK: encoding: [0x66,0x0f,0xbe,0x00] +movsx (%rax), %ax + +// CHECK: movzbw (%rax), %ax +// CHECK: encoding: [0x66,0x0f,0xb6,0x00] +movzx (%rax), %ax // rdar://7873482 From isanbard at gmail.com Mon Nov 1 00:48:44 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 05:48:44 -0000 Subject: [llvm-commits] [llvm] r117903 - /llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Message-ID: <20101101054844.98D072A6C12C@llvm.org> Author: void Date: Mon Nov 1 00:48:44 2010 New Revision: 117903 URL: http://llvm.org/viewvc/llvm-project?rev=117903&view=rev Log: Disable because peephole is disabled. Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=117903&r1=117902&r2=117903&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Mon Nov 1 00:48:44 2010 @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s +; XFAIL: * %struct.Foo = type { i8* } From isanbard at gmail.com Mon Nov 1 00:50:55 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 05:50:55 -0000 Subject: [llvm-commits] [llvm] r117904 - /llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Message-ID: <20101101055055.EBB942A6C12C@llvm.org> Author: void Date: Mon Nov 1 00:50:55 2010 New Revision: 117904 URL: http://llvm.org/viewvc/llvm-project?rev=117904&view=rev Log: The testcase is now XFAILed. Sorry about the breakage. Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=117904&r1=117903&r2=117904&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Mon Nov 1 00:50:55 2010 @@ -276,9 +276,11 @@ if (MI->getDesc().isCompare() && !MI->getDesc().hasUnmodeledSideEffects()) { +#if 0 if (OptimizeCmpInstr(MI, MBB, MII)) Changed = true; else +#endif ++MII; } else { Changed |= OptimizeExtInstr(MI, MBB, LocalMIs); From wendling at apple.com Mon Nov 1 00:52:50 2010 From: wendling at apple.com (Bill Wendling) Date: Sun, 31 Oct 2010 22:52:50 -0700 Subject: [llvm-commits] [llvm] r117879 - /llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp In-Reply-To: <20101031224256.09EA52A6C12C@llvm.org> References: <20101031224256.09EA52A6C12C@llvm.org> Message-ID: <4BD660C8-E964-4352-AB97-9516B9487B9F@apple.com> I XFAILed the testcase. Sorry about the breakage... -bw On Oct 31, 2010, at 3:42 PM, Eric Christopher wrote: > Author: echristo > Date: Sun Oct 31 17:42:55 2010 > New Revision: 117879 > > URL: http://llvm.org/viewvc/llvm-project?rev=117879&view=rev > Log: > Revert r117876 for now, it's causing more testsuite failures. > > Modified: > llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp > > Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=117879&r1=117878&r2=117879&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) > +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Sun Oct 31 17:42:55 2010 > @@ -276,11 +276,9 @@ > > if (MI->getDesc().isCompare() && > !MI->getDesc().hasUnmodeledSideEffects()) { > -#if 0 > if (OptimizeCmpInstr(MI, MBB, MII)) > Changed = true; > else > -#endif > ++MII; > } else { > Changed |= OptimizeExtInstr(MI, MBB, LocalMIs); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Nov 1 00:59:43 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 05:59:43 -0000 Subject: [llvm-commits] [llvm] r117905 - in /llvm/trunk/test/CodeGen/ARM: arm-and-tst-peephole.ll long_shift.ll Message-ID: <20101101055943.EF4EF2A6C12C@llvm.org> Author: void Date: Mon Nov 1 00:59:43 2010 New Revision: 117905 URL: http://llvm.org/viewvc/llvm-project?rev=117905&view=rev Log: More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the peephole optimizer is disabled. That's not good at all. Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll llvm/trunk/test/CodeGen/ARM/long_shift.ll Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=117905&r1=117904&r2=117905&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Mon Nov 1 00:59:43 2010 @@ -1,7 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s -; XFAIL: * +; RUN: llc < %s -march=arm +; FIXME: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s +; FIXME: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s %struct.Foo = type { i8* } Modified: llvm/trunk/test/CodeGen/ARM/long_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long_shift.ll?rev=117905&r1=117904&r2=117905&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long_shift.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long_shift.ll Mon Nov 1 00:59:43 2010 @@ -1,4 +1,6 @@ ; RUN: llc < %s -march=arm | FileCheck %s +; XFAIL: * +; FIXME: Fix after peephole optimizer is fixed. define i64 @f0(i64 %A, i64 %B) { ; CHECK: f0 From isanbard at gmail.com Mon Nov 1 01:00:39 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 06:00:39 -0000 Subject: [llvm-commits] [llvm] r117906 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrVFP.td Message-ID: <20101101060039.8425F2A6C12C@llvm.org> Author: void Date: Mon Nov 1 01:00:39 2010 New Revision: 117906 URL: http://llvm.org/viewvc/llvm-project?rev=117906&view=rev Log: Move instruction encoding bits into the parent class and remove the temporary *_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117906&r1=117905&r2=117906&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 1 01:00:39 2010 @@ -1523,6 +1523,16 @@ bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { + // Instruction operands. + bits<5> Dd; + bits<5> Dm; + + // Encode instruction operands. + let Inst{3-0} = Dm{3-0}; + let Inst{5} = Dm{4}; + let Inst{15-12} = Dd{3-0}; + let Inst{22} = Dd{4}; + let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; @@ -1537,6 +1547,19 @@ dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { + // Instruction operands. + bits<5> Dd; + bits<5> Dn; + bits<5> Dm; + + // Encode instruction operands. + let Inst{3-0} = Dm{3-0}; + let Inst{5} = Dm{4}; + let Inst{19-16} = Dn{3-0}; + let Inst{7} = Dn{4}; + let Inst{15-12} = Dd{3-0}; + let Inst{22} = Dd{4}; + let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; @@ -1564,6 +1587,16 @@ bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { + // Instruction operands. + bits<5> Sd; + bits<5> Sm; + + // Encode instruction operands. + let Inst{3-0} = Sm{4-1}; + let Inst{5} = Sm{0}; + let Inst{15-12} = Sd{4-1}; + let Inst{22} = Sd{0}; + let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; @@ -1587,6 +1620,19 @@ class ASbI opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { + // Instruction operands. + bits<5> Sd; + bits<5> Sn; + bits<5> Sm; + + // Encode instruction operands. + let Inst{3-0} = Sm{4-1}; + let Inst{5} = Sm{0}; + let Inst{19-16} = Sn{4-1}; + let Inst{7} = Sn{0}; + let Inst{15-12} = Sd{4-1}; + let Inst{22} = Sd{0}; + let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; @@ -1602,6 +1648,19 @@ list pattern> : ASbI { list Predicates = [HasVFP2,DontUseNEONForFP]; + + // Instruction operands. + bits<5> Sd; + bits<5> Sn; + bits<5> Sm; + + // Encode instruction operands. + let Inst{3-0} = Sm{4-1}; + let Inst{5} = Sm{0}; + let Inst{19-16} = Sn{4-1}; + let Inst{7} = Sn{0}; + let Inst{15-12} = Sd{4-1}; + let Inst{22} = Sd{0}; } // VFP conversion instructions Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=117906&r1=117905&r2=117906&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 1 01:00:39 2010 @@ -136,166 +136,59 @@ // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores - -// FIXME: Can these be placed into the base class? -class ADbI_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, - dag iops, InstrItinClass itin, string opc, string asm, - list pattern> - : ADbI { - // Instruction operands. - bits<5> Dd; - bits<5> Dn; - bits<5> Dm; - - // Encode instruction operands. - let Inst{3-0} = Dm{3-0}; - let Inst{5} = Dm{4}; - let Inst{19-16} = Dn{3-0}; - let Inst{7} = Dn{4}; - let Inst{15-12} = Dd{3-0}; - let Inst{22} = Dd{4}; -} - -class ADuI_Encode opcod1, bits<2> opcod2, bits<4> opcod3, - bits<2> opcod4, bit opcod5, dag oops, dag iops, - InstrItinClass itin, string opc, string asm, - list pattern> - : ADuI { - // Instruction operands. - bits<5> Dd; - bits<5> Dm; - - // Encode instruction operands. - let Inst{3-0} = Dm{3-0}; - let Inst{5} = Dm{4}; - let Inst{15-12} = Dd{3-0}; - let Inst{22} = Dd{4}; -} - -class ASbI_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, - dag iops, InstrItinClass itin, string opc, string asm, - list pattern> - : ASbI { - // Instruction operands. - bits<5> Sd; - bits<5> Sn; - bits<5> Sm; - - // Encode instruction operands. - let Inst{3-0} = Sm{4-1}; - let Inst{5} = Sm{0}; - let Inst{19-16} = Sn{4-1}; - let Inst{7} = Sn{0}; - let Inst{15-12} = Sd{4-1}; - let Inst{22} = Sd{0}; -} - -class ASbIn_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, - dag iops, InstrItinClass itin, string opc, string asm, - list pattern> - : ASbIn { - // Instruction operands. - bits<5> Sd; - bits<5> Sn; - bits<5> Sm; - - // Encode instruction operands. - let Inst{3-0} = Sm{4-1}; - let Inst{5} = Sm{0}; - let Inst{19-16} = Sn{4-1}; - let Inst{7} = Sn{0}; - let Inst{15-12} = Sd{4-1}; - let Inst{22} = Sd{0}; -} - -class ASuI_Encode opcod1, bits<2> opcod2, bits<4> opcod3, - bits<2> opcod4, bit opcod5, dag oops, dag iops, - InstrItinClass itin, string opc, string asm, - list pattern> - : ASuI { - // Instruction operands. - bits<5> Sd; - bits<5> Sm; - - // Encode instruction operands. - let Inst{3-0} = Sm{4-1}; - let Inst{5} = Sm{0}; - let Inst{15-12} = Sd{4-1}; - let Inst{22} = Sd{0}; -} - -class ASuIn_Encode opcod1, bits<2> opcod2, bits<4> opcod3, - bits<2> opcod4, bit opcod5, dag oops, dag iops, - InstrItinClass itin, string opc, string asm, - list pattern> - : ASuIn { - // Instruction operands. - bits<5> Sd; - bits<5> Sm; - - // Encode instruction operands. - let Inst{3-0} = Sm{4-1}; - let Inst{5} = Sm{0}; - let Inst{15-12} = Sd{4-1}; - let Inst{22} = Sd{0}; -} - //===----------------------------------------------------------------------===// // FP Binary Operations. // -def VADDD : ADbI_Encode<0b11100, 0b11, 0, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; - -def VADDS : ASbIn_Encode<0b11100, 0b11, 0, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>; - -def VSUBD : ADbI_Encode<0b11100, 0b11, 1, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; - -def VSUBS : ASbIn_Encode<0b11100, 0b11, 1, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>; - -def VDIVD : ADbI_Encode<0b11101, 0b00, 0, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; - -def VDIVS : ASbI_Encode<0b11101, 0b00, 0, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; - -def VMULD : ADbI_Encode<0b11100, 0b10, 0, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; - -def VMULS : ASbIn_Encode<0b11100, 0b10, 0, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>; - -def VNMULD : ADbI_Encode<0b11100, 0b10, 1, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; - -def VNMULS : ASbI_Encode<0b11100, 0b10, 1, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>; +def VADDD : ADbI<0b11100, 0b11, 0, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; + +def VADDS : ASbIn<0b11100, 0b11, 0, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>; + +def VSUBD : ADbI<0b11100, 0b11, 1, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; + +def VSUBS : ASbIn<0b11100, 0b11, 1, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>; + +def VDIVD : ADbI<0b11101, 0b00, 0, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; + +def VDIVS : ASbI<0b11101, 0b00, 0, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; + +def VMULD : ADbI<0b11100, 0b10, 0, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; + +def VMULS : ASbIn<0b11100, 0b10, 0, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>; + +def VNMULD : ADbI<0b11100, 0b10, 1, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; + +def VNMULS : ASbI<0b11100, 0b10, 1, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>; // Match reassociated forms only if not sign dependent rounding. def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), @@ -305,74 +198,74 @@ // These are encoded as unary instructions. let Defs = [FPSCR] in { -def VCMPED : ADuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0, - (outs), (ins DPR:$Dd, DPR:$Dm), - IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", - [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; - -def VCMPES : ASuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0, - (outs), (ins SPR:$Sd, SPR:$Sm), - IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", - [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>; +def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, + (outs), (ins DPR:$Dd, DPR:$Dm), + IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", + [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; + +def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, + (outs), (ins SPR:$Sd, SPR:$Sm), + IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", + [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>; // FIXME: Verify encoding after integrated assembler is working. -def VCMPD : ADuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0, - (outs), (ins DPR:$Dd, DPR:$Dm), - IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", - [/* For disassembly only; pattern left blank */]>; - -def VCMPS : ASuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0, - (outs), (ins SPR:$Sd, SPR:$Sm), - IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", - [/* For disassembly only; pattern left blank */]>; +def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, + (outs), (ins DPR:$Dd, DPR:$Dm), + IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", + [/* For disassembly only; pattern left blank */]>; + +def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, + (outs), (ins SPR:$Sd, SPR:$Sm), + IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", + [/* For disassembly only; pattern left blank */]>; } //===----------------------------------------------------------------------===// // FP Unary Operations. // -def VABSD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b11, 0, - (outs DPR:$Dd), (ins DPR:$Dm), - IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", - [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; - -def VABSS : ASuIn_Encode<0b11101, 0b11, 0b0000, 0b11, 0, - (outs SPR:$Sd), (ins SPR:$Sm), - IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", - [(set SPR:$Sd, (fabs SPR:$Sm))]>; +def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, + (outs DPR:$Dd), (ins DPR:$Dm), + IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", + [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; + +def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, + (outs SPR:$Sd), (ins SPR:$Sm), + IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", + [(set SPR:$Sd, (fabs SPR:$Sm))]>; let Defs = [FPSCR] in { -def VCMPEZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0, - (outs), (ins DPR:$Dd), - IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", - [(arm_cmpfp0 (f64 DPR:$Dd))]> { - let Inst{3-0} = 0b0000; - let Inst{5} = 0; +def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, + (outs), (ins DPR:$Dd), + IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", + [(arm_cmpfp0 (f64 DPR:$Dd))]> { + let Inst{3-0} = 0b0000; + let Inst{5} = 0; } -def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0, - (outs), (ins SPR:$Sd), - IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", - [(arm_cmpfp0 SPR:$Sd)]> { - let Inst{3-0} = 0b0000; - let Inst{5} = 0; +def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, + (outs), (ins SPR:$Sd), + IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", + [(arm_cmpfp0 SPR:$Sd)]> { + let Inst{3-0} = 0b0000; + let Inst{5} = 0; } // FIXME: Verify encoding after integrated assembler is working. -def VCMPZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0, - (outs), (ins DPR:$Dd), - IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", - [/* For disassembly only; pattern left blank */]> { - let Inst{3-0} = 0b0000; - let Inst{5} = 0; +def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, + (outs), (ins DPR:$Dd), + IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", + [/* For disassembly only; pattern left blank */]> { + let Inst{3-0} = 0b0000; + let Inst{5} = 0; } -def VCMPZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0, - (outs), (ins SPR:$Sd), - IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", - [/* For disassembly only; pattern left blank */]> { - let Inst{3-0} = 0b0000; - let Inst{5} = 0; +def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, + (outs), (ins SPR:$Sd), + IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", + [/* For disassembly only; pattern left blank */]> { + let Inst{3-0} = 0b0000; + let Inst{5} = 0; } } @@ -437,34 +330,34 @@ /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a", [/* For disassembly only; pattern left blank */]>; -def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0, - (outs DPR:$Dd), (ins DPR:$Dm), - IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", - [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; - -def VNEGS : ASuIn_Encode<0b11101, 0b11, 0b0001, 0b01, 0, - (outs SPR:$Sd), (ins SPR:$Sm), - IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", - [(set SPR:$Sd, (fneg SPR:$Sm))]>; - -def VSQRTD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0, - (outs DPR:$Dd), (ins DPR:$Dm), - IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", - [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; - -def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0, - (outs SPR:$Sd), (ins SPR:$Sm), - IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", - [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; +def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, + (outs DPR:$Dd), (ins DPR:$Dm), + IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", + [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; + +def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, + (outs SPR:$Sd), (ins SPR:$Sm), + IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", + [(set SPR:$Sd, (fneg SPR:$Sm))]>; + +def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, + (outs DPR:$Dd), (ins DPR:$Dm), + IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", + [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; + +def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, + (outs SPR:$Sd), (ins SPR:$Sm), + IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", + [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; let neverHasSideEffects = 1 in { -def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, - (outs DPR:$Dd), (ins DPR:$Dm), - IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; - -def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, - (outs SPR:$Sd), (ins SPR:$Sm), - IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; +def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, + (outs DPR:$Dd), (ins DPR:$Dm), + IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; + +def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, + (outs SPR:$Sd), (ins SPR:$Sm), + IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; } // neverHasSideEffects //===----------------------------------------------------------------------===// @@ -860,12 +753,12 @@ (f64 DPR:$Ddin)))]>, RegConstraint<"$Ddin = $Dd">; -def VMLAS : ASbIn_Encode<0b11100, 0b00, 0, 0, - (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), - IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm), - SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; +def VMLAS : ASbIn<0b11100, 0b00, 0, 0, + (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), + IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm), + SPR:$Sdin))]>, + RegConstraint<"$Sdin = $Sd">; def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))), (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; @@ -879,12 +772,12 @@ (f64 DPR:$Ddin)))]>, RegConstraint<"$Ddin = $Dd">; -def VMLSS : ASbIn_Encode<0b11100, 0b00, 1, 0, - (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), - IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)), - SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; +def VMLSS : ASbIn<0b11100, 0b00, 1, 0, + (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), + IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)), + SPR:$Sdin))]>, + RegConstraint<"$Sdin = $Sd">; def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))), (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; @@ -898,12 +791,12 @@ (f64 DPR:$Ddin)))]>, RegConstraint<"$Ddin = $Dd">; -def VNMLAS : ASbI_Encode<0b11100, 0b01, 1, 0, - (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), - IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)), - SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; +def VNMLAS : ASbI<0b11100, 0b01, 1, 0, + (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), + IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)), + SPR:$Sdin))]>, + RegConstraint<"$Sdin = $Sd">; def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin), (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; @@ -917,11 +810,10 @@ (f64 DPR:$Ddin)))]>, RegConstraint<"$Ddin = $Dd">; -def VNMLSS : ASbI_Encode<0b11100, 0b01, 0, 0, - (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), - IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", - [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm), - SPR:$Sdin))]>, +def VNMLSS : ASbI<0b11100, 0b01, 0, 0, + (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), + IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", + [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, RegConstraint<"$Sdin = $Sd">; def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin), @@ -935,29 +827,29 @@ // let neverHasSideEffects = 1 in { -def VMOVDcc : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", - [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, - RegConstraint<"$Dn = $Dd">; - -def VMOVScc : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", - [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, - RegConstraint<"$Sn = $Sd">; - -def VNEGDcc : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", - [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, - RegConstraint<"$Dn = $Dd">; - -def VNEGScc : ASuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", - [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, - RegConstraint<"$Sn = $Sd">; +def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", + [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, + RegConstraint<"$Dn = $Dd">; + +def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", + [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, + RegConstraint<"$Sn = $Sd">; + +def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, + (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), + IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", + [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, + RegConstraint<"$Dn = $Dd">; + +def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0, + (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", + [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, + RegConstraint<"$Sn = $Sd">; } // neverHasSideEffects //===----------------------------------------------------------------------===// From rafael.espindola at gmail.com Mon Nov 1 09:28:48 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 01 Nov 2010 14:28:48 -0000 Subject: [llvm-commits] [llvm] r117911 - in /llvm/trunk: include/llvm/MC/MCELFSymbolFlags.h include/llvm/MC/MCObjectStreamer.h include/llvm/MC/MCStreamer.h lib/MC/ELFObjectWriter.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCObjectStreamer.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCStreamer.cpp test/MC/ELF/weakref.s Message-ID: <20101101142848.BAB2C2A6C12C@llvm.org> Author: rafael Date: Mon Nov 1 09:28:48 2010 New Revision: 117911 URL: http://llvm.org/viewvc/llvm-project?rev=117911&view=rev Log: Implement .weakref. Added: llvm/trunk/test/MC/ELF/weakref.s Modified: llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h llvm/trunk/include/llvm/MC/MCObjectStreamer.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCLoggingStreamer.cpp llvm/trunk/lib/MC/MCNullStreamer.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h (original) +++ llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h Mon Nov 1 09:28:48 2010 @@ -21,9 +21,10 @@ namespace llvm { enum { - ELF_STT_Shift = 0, // Shift value for STT_* flags. - ELF_STB_Shift = 4, // Shift value for STB_* flags. - ELF_STV_Shift = 8 // Shift value ofr STV_* flags. + ELF_STT_Shift = 0, // Shift value for STT_* flags. + ELF_STB_Shift = 4, // Shift value for STB_* flags. + ELF_STV_Shift = 8, // Shift value for STV_* flags. + ELF_Other_Shift = 10 // Shift value for other flags. }; enum SymbolFlags { @@ -46,7 +47,9 @@ ELF_STV_Default = (ELF::STV_DEFAULT << ELF_STV_Shift), ELF_STV_Internal = (ELF::STV_INTERNAL << ELF_STV_Shift), ELF_STV_Hidden = (ELF::STV_HIDDEN << ELF_STV_Shift), - ELF_STV_Protected = (ELF::STV_PROTECTED << ELF_STV_Shift) + ELF_STV_Protected = (ELF::STV_PROTECTED << ELF_STV_Shift), + + ELF_Other_Weakref = (1 << ELF_Other_Shift) }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Mon Nov 1 09:28:48 2010 @@ -57,6 +57,7 @@ /// @name MCStreamer Interface /// @{ + virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void SwitchSection(const MCSection *Section); virtual void Finish(); Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Mon Nov 1 09:28:48 2010 @@ -139,6 +139,15 @@ /// @param Value - The value for the symbol. virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) = 0; + /// EmitWeakReference - Emit an weak reference from @p Alias to @p Symbol. + /// + /// This corresponds to an assembler statement such as: + /// .weakref alias, symbol + /// + /// @param Alias - The alias that is being created. + /// @param Symbol - The symbol being aliased. + virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) = 0; + /// EmitSymbolAttribute - Add the given @p Attribute to @p Symbol. virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) = 0; Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Nov 1 09:28:48 2010 @@ -143,6 +143,7 @@ }; SmallPtrSet UsedInReloc; + SmallPtrSet WeakrefUsedInReloc; DenseMap Renames; llvm::DenseMapgetSymbol()); Renamed = Renames.lookup(Symbol); if (!Renamed) - Renamed = Symbol; + Renamed = &Target.getSymA()->getSymbol(); MCSymbolData &SD = Asm.getSymbolData(*Symbol); MCFragment *F = SD.getFragment(); @@ -727,6 +728,10 @@ Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD); } else { UsedInReloc.insert(Renamed); + MCSymbolData &RenamedSD = Asm.getSymbolData(*Renamed); + if (RenamedSD.getFlags() & ELF_Other_Weakref) { + WeakrefUsedInReloc.insert(Symbol); + } Index = -1; } Addend = Value; @@ -901,6 +906,9 @@ static bool isInSymtab(const MCAssembler &Asm, const MCSymbolData &Data, bool Used, bool Renamed) { + if (Data.getFlags() & ELF_Other_Weakref) + return false; + if (Used) return true; @@ -963,7 +971,9 @@ ie = Asm.symbol_end(); it != ie; ++it) { const MCSymbol &Symbol = it->getSymbol(); - if (!isInSymtab(Asm, *it, UsedInReloc.count(&Symbol), + bool Used = UsedInReloc.count(&Symbol); + bool WeakrefUsed = WeakrefUsedInReloc.count(&Symbol); + if (!isInSymtab(Asm, *it, Used || WeakrefUsed, Renames.count(&Symbol))) continue; @@ -972,6 +982,9 @@ bool Local = isLocal(*it); const MCSymbol &RefSymbol = AliasedSymbol(Symbol); + if (RefSymbol.isUndefined() && !Used && WeakrefUsed) + SetBinding(*it, ELF::STB_WEAK); + if (it->isCommon()) { assert(!Local); MSD.SectionIndex = ELF::SHN_COMMON; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon Nov 1 09:28:48 2010 @@ -113,6 +113,7 @@ virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); + virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute); @@ -258,6 +259,11 @@ Symbol->setVariableValue(Value); } +void MCAsmStreamer::EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) { + OS << ".weakref " << *Alias << ", " << *Symbol; + EmitEOL(); +} + void MCAsmStreamer::EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) { switch (Attribute) { Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Nov 1 09:28:48 2010 @@ -24,6 +24,7 @@ #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCValue.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -51,6 +52,7 @@ virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); + virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute); virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) { assert(0 && "ELF doesn't support this directive"); @@ -193,6 +195,64 @@ Symbol->setVariableValue(AddValueSymbols(Value)); } +// This is a hack. To be able to implement weakrefs the writer has to be able +// to distinguish +// .weakref foo, bar +// .long foo +// from +// .weakref foo, bar +// .long bar +// since the first case should produce a weak undefined reference and the second +// one a strong one. +// If we created foo as a regular alias pointing to bar (foo = bar), then +// MCExpr::EvaluateAsRelocatable would recurse on foo and the writer would +// never see it used in a relocation. +// What we do is create a MCTargetExpr that when evaluated produces a symbol +// ref to a temporary symbol. This temporary symbol in turn is a variable +// that equals the original symbol (tmp = bar). With this hack the writer +// gets a relocation with tmp and can correctly implement weak references. + +class WeakRefExpr : public MCTargetExpr { +private: + const MCSymbolRefExpr *Alias; + + explicit WeakRefExpr(const MCSymbolRefExpr *Alias_) + : MCTargetExpr(), Alias(Alias_) {} + +public: + virtual void PrintImpl(raw_ostream &OS) const { + llvm_unreachable("Unimplemented"); + } + + virtual bool EvaluateAsRelocatableImpl(MCValue &Res, + const MCAsmLayout *Layout) const { + Res = MCValue::get(Alias, 0, 0); + return true; + } + + static const WeakRefExpr *Create(const MCSymbol *Alias, MCContext &Ctx) { + const MCSymbolRefExpr *A = MCSymbolRefExpr::Create(Alias, Ctx); + return new (Ctx) WeakRefExpr(A); + } +}; + +void MCELFStreamer::EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) { + getAssembler().getOrCreateSymbolData(*Symbol); + MCSymbolData &AliasSD = getAssembler().getOrCreateSymbolData(*Alias); + AliasSD.setFlags(AliasSD.getFlags() | ELF_Other_Weakref); + + // Create the alias that actually points to Symbol + const MCSymbolRefExpr *SymRef = MCSymbolRefExpr::Create(Symbol, getContext()); + MCSymbol *RealAlias = getContext().CreateTempSymbol(); + RealAlias->setVariableValue(SymRef); + + MCSymbolData &RealAliasSD = getAssembler().getOrCreateSymbolData(*RealAlias); + RealAliasSD.setFlags(RealAliasSD.getFlags() | ELF_Other_Weakref); + + const MCExpr *Value = WeakRefExpr::Create(RealAlias, getContext()); + Alias->setVariableValue(Value); +} + static void SetBinding(MCSymbolData &SD, unsigned Binding) { assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL || Binding == ELF::STB_WEAK); Modified: llvm/trunk/lib/MC/MCLoggingStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLoggingStreamer.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCLoggingStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCLoggingStreamer.cpp Mon Nov 1 09:28:48 2010 @@ -74,6 +74,11 @@ return Child->EmitAssignment(Symbol, Value); } + virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) { + LogCall("EmitWeakReference"); + return Child->EmitWeakReference(Alias, Symbol); + } + virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) { LogCall("EmitSymbolAttribute"); return Child->EmitSymbolAttribute(Symbol, Attribute); Modified: llvm/trunk/lib/MC/MCNullStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCNullStreamer.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCNullStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCNullStreamer.cpp Mon Nov 1 09:28:48 2010 @@ -42,6 +42,7 @@ virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) {} virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {} + virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol){} virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute){} Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Mon Nov 1 09:28:48 2010 @@ -74,6 +74,11 @@ return Value; } +void MCObjectStreamer::EmitWeakReference(MCSymbol *Alias, + const MCSymbol *Symbol) { + report_fatal_error("This file format doesn't support weak aliases."); +} + void MCObjectStreamer::SwitchSection(const MCSection *Section) { assert(Section && "Cannot switch to a null section!"); Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Mon Nov 1 09:28:48 2010 @@ -53,6 +53,7 @@ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveType>(".type"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveIdent>(".ident"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymver>(".symver"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveWeakref>(".weakref"); } // FIXME: Part of this logic is duplicated in the MCELFStreamer. What is @@ -119,6 +120,7 @@ bool ParseDirectiveType(StringRef, SMLoc); bool ParseDirectiveIdent(StringRef, SMLoc); bool ParseDirectiveSymver(StringRef, SMLoc); + bool ParseDirectiveWeakref(StringRef, SMLoc); private: bool ParseSectionName(StringRef &SectionName); @@ -443,6 +445,32 @@ return false; } +/// ParseDirectiveWeakref +/// ::= .weakref foo, bar +bool ELFAsmParser::ParseDirectiveWeakref(StringRef, SMLoc) { + // FIXME: Share code with the other alias building directives. + + StringRef AliasName; + if (getParser().ParseIdentifier(AliasName)) + return TokError("expected identifier in directive"); + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("expected a comma"); + + Lex(); + + StringRef Name; + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + MCSymbol *Alias = getContext().GetOrCreateSymbol(AliasName); + + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + getStreamer().EmitWeakReference(Alias, Sym); + return false; +} + namespace llvm { MCAsmParserExtension *createELFAsmParser() { Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=117911&r1=117910&r2=117911&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Mon Nov 1 09:28:48 2010 @@ -10,6 +10,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCObjectWriter.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/Twine.h" Added: llvm/trunk/test/MC/ELF/weakref.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/weakref.s?rev=117911&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/weakref.s (added) +++ llvm/trunk/test/MC/ELF/weakref.s Mon Nov 1 09:28:48 2010 @@ -0,0 +1,234 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// This is a long test that checks that the aliases created by weakref are +// never in the symbol table and that the only case it causes a symbol to +// be output as a weak undefined symbol is if that variable is not defined +// in this file and all the references to it are done via the alias. + + .weakref foo1, bar1 + + .weakref foo2, bar2 + .long bar2 + + .weakref foo3, bar3 + .long foo3 + + .weakref foo4, bar4 + .long foo4 + .long bar4 + + .weakref foo5, bar5 + .long bar5 + .long foo5 + +bar6: + .weakref foo6, bar6 + +bar7: + .weakref foo7, bar7 + .long bar7 + +bar8: + .weakref foo8, bar8 + .long foo8 + +bar9: + .weakref foo9, bar9 + .long foo9 + .long bar9 + +bar10: + .global bar10 + .weakref foo10, bar10 + .long bar10 + .long foo10 + +bar11: + .global bar11 + .weakref foo11, bar11 + +bar12: + .global bar12 + .weakref foo12, bar12 + .long bar12 + +bar13: + .global bar13 + .weakref foo13, bar13 + .long foo13 + +bar14: + .global bar14 + .weakref foo14, bar14 + .long foo14 + .long bar14 + +bar15: + .global bar15 + .weakref foo15, bar15 + .long bar15 + .long foo15 + +// CHECK: # Symbol 0x00000000 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000001 +// CHECK-NEXT: (('st_name', 0x00000015) # 'bar6' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000018) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000002 +// CHECK-NEXT: (('st_name', 0x0000001a) # 'bar7' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000018) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000003 +// CHECK-NEXT: (('st_name', 0x0000001f) # 'bar8' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x0000001c) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000004 +// CHECK-NEXT: (('st_name', 0x00000024) # 'bar9' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000020) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000005 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000003) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000006 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000003) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000002) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000007 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000003) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000003) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000008 +// CHECK-NEXT: (('st_name', 0x00000029) # 'bar10' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000028) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000009 +// CHECK-NEXT: (('st_name', 0x0000002f) # 'bar11' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000030) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000a +// CHECK-NEXT: (('st_name', 0x00000035) # 'bar12' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000030) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000b +// CHECK-NEXT: (('st_name', 0x0000003b) # 'bar13' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000034) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000c +// CHECK-NEXT: (('st_name', 0x00000041) # 'bar14' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000038) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000d +// CHECK-NEXT: (('st_name', 0x00000047) # 'bar15' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000040) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000e +// CHECK-NEXT: (('st_name', 0x00000001) # 'bar2' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000f +// CHECK-NEXT: (('st_name', 0x00000006) # 'bar3' +// CHECK-NEXT: ('st_bind', 0x00000002) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000010 +// CHECK-NEXT: (('st_name', 0x0000000b) # 'bar4' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000011 +// CHECK-NEXT: (('st_name', 0x00000010) # 'bar5' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) From rafael.espindola at gmail.com Mon Nov 1 09:53:37 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Mon, 1 Nov 2010 10:53:37 -0400 Subject: [llvm-commits] PATCH: llvm-gcc option to emit "va_arg" instruction In-Reply-To: References: <2CC138C3-4628-400A-AAEF-A030A21843A2@apple.com> <2646F00C-CDF0-402D-8C90-561B2C4B3B45@apple.com> <146F714B-AF1A-462F-B3F9-003E6EB2AE7D@apple.com> <4CB765E1.7060208@free.fr> <4CB9974A.5020004@free.fr> Message-ID: On 28 October 2010 17:46, David Meyer wrote: > If I may revive this thread from the graveyard... > Could somebody take another look at this patch (attached) and let me know > whether it is?acceptable? (or if not, what I can do to improve it?) This is not being used by any target. I assume that it is intentional while the completeness and efficiency of va_arg is worked out? Maybe we should get one target to use it first? I think it is OK, but lets see what Duncan has to say. He had concerns about the two step lowering... > Thanks, > ?- David Meyer Cheers, Rafael From rafael.espindola at gmail.com Mon Nov 1 10:29:07 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 01 Nov 2010 15:29:07 -0000 Subject: [llvm-commits] [llvm] r117922 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/directive_values.s Message-ID: <20101101152907.D7DD12A6C12C@llvm.org> Author: rafael Date: Mon Nov 1 10:29:07 2010 New Revision: 117922 URL: http://llvm.org/viewvc/llvm-project?rev=117922&view=rev Log: Add support for .value. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_values.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=117922&r1=117921&r2=117922&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Nov 1 10:29:07 2010 @@ -929,6 +929,8 @@ return ParseDirectiveValue(1); if (IDVal == ".short") return ParseDirectiveValue(2); + if (IDVal == ".value") + return ParseDirectiveValue(2); if (IDVal == ".long") return ParseDirectiveValue(4); if (IDVal == ".quad") Modified: llvm/trunk/test/MC/AsmParser/directive_values.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_values.s?rev=117922&r1=117921&r2=117922&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_values.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_values.s Mon Nov 1 10:29:07 2010 @@ -36,3 +36,7 @@ # CHECK: .quad 1075 +TEST5: + .value 8 +# CHECK: TEST5: +# CHECK: .short 8 From grosbach at apple.com Mon Nov 1 10:59:52 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 15:59:52 -0000 Subject: [llvm-commits] [llvm] r117923 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20101101155952.84D732A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 10:59:52 2010 New Revision: 117923 URL: http://llvm.org/viewvc/llvm-project?rev=117923&view=rev Log: The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the patterns as such Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=117923&r1=117922&r2=117923&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Nov 1 10:59:52 2010 @@ -690,7 +690,7 @@ def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iEXTr, opc, "\t$dst, $src", [(set rGPR:$dst, (opnode rGPR:$src))]>, - Requires<[HasT2ExtractPack]> { + Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; @@ -702,7 +702,7 @@ def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iEXTr, opc, "\t$dst, $src, ror $rot", [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>, - Requires<[HasT2ExtractPack]> { + Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; @@ -744,7 +744,7 @@ def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr, opc, "\t$dst, $LHS, $RHS", [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>, - Requires<[HasT2ExtractPack]> { + Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; @@ -756,7 +756,7 @@ IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot", [(set rGPR:$dst, (opnode rGPR:$LHS, (rotr rGPR:$RHS, rot_imm:$rot)))]>, - Requires<[HasT2ExtractPack]> { + Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0100; let Inst{22-20} = opcod; @@ -1384,9 +1384,11 @@ // instead so we can include a check for masking back in the upper // eight bits of the source into the lower eight bits of the result. //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), -// (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>; +// (t2UXTB16r_rot rGPR:$Src, 24)>, +// Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), - (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>; + (t2UXTB16r_rot rGPR:$Src, 8)>, + Requires<[HasT2ExtractPack, IsThumb2]>; defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; @@ -2124,7 +2126,7 @@ [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF), (and (shl rGPR:$src2, lsl_amt:$sh), 0xFFFF0000)))]>, - Requires<[HasT2ExtractPack]> { + Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-20} = 0b01100; @@ -2135,10 +2137,10 @@ // Alternate cases for PKHBT where identities eliminate some nodes. def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, - Requires<[HasT2ExtractPack]>; + Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>, - Requires<[HasT2ExtractPack]>; + Requires<[HasT2ExtractPack, IsThumb2]>; // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. @@ -2147,7 +2149,7 @@ [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000), (and (sra rGPR:$src2, asr_amt:$sh), 0xFFFF)))]>, - Requires<[HasT2ExtractPack]> { + Requires<[HasT2ExtractPack, IsThumb2]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-20} = 0b01100; @@ -2159,11 +2161,11 @@ // a shift amount of 0 is *not legal* here, it is PKHBT instead. def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)), (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>, - Requires<[HasT2ExtractPack]>; + Requires<[HasT2ExtractPack, IsThumb2]>; def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>, - Requires<[HasT2ExtractPack]>; + Requires<[HasT2ExtractPack, IsThumb2]>; //===----------------------------------------------------------------------===// // Comparison Instructions... From rafael.espindola at gmail.com Mon Nov 1 11:27:31 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 01 Nov 2010 16:27:31 -0000 Subject: [llvm-commits] [llvm] r117925 - in /llvm/trunk: include/llvm/MC/MCObjectStreamer.h lib/MC/MCELFStreamer.cpp lib/MC/MCMachOStreamer.cpp lib/MC/MCObjectStreamer.cpp lib/MC/WinCOFFStreamer.cpp Message-ID: <20101101162731.8D86F2A6C12D@llvm.org> Author: rafael Date: Mon Nov 1 11:27:31 2010 New Revision: 117925 URL: http://llvm.org/viewvc/llvm-project?rev=117925&view=rev Log: Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it. Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp llvm/trunk/lib/MC/WinCOFFStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=117925&r1=117924&r2=117925&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Mon Nov 1 11:27:31 2010 @@ -33,6 +33,9 @@ MCAssembler *Assembler; MCSectionData *CurSectionData; + virtual void EmitInstToFragment(const MCInst &Inst) = 0; + virtual void EmitInstToData(const MCInst &Inst) = 0; + protected: MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, @@ -59,6 +62,7 @@ virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void SwitchSection(const MCSection *Section); + virtual void EmitInstruction(const MCInst &Inst); virtual void Finish(); /// @} Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=117925&r1=117924&r2=117925&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Nov 1 11:27:31 2010 @@ -36,8 +36,6 @@ namespace { class MCELFStreamer : public MCObjectStreamer { - void EmitInstToFragment(const MCInst &Inst); - void EmitInstToData(const MCInst &Inst); public: MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter) @@ -109,10 +107,12 @@ DEBUG(dbgs() << "FIXME: MCELFStreamer:EmitDwarfFileDirective not implemented\n"); } - virtual void EmitInstruction(const MCInst &Inst); virtual void Finish(); private: + virtual void EmitInstToFragment(const MCInst &Inst); + virtual void EmitInstToData(const MCInst &Inst); + struct LocalCommon { MCSymbolData *SD; uint64_t Size; @@ -510,35 +510,6 @@ DF->getContents().append(Code.begin(), Code.end()); } -void MCELFStreamer::EmitInstruction(const MCInst &Inst) { - // Scan for values. - for (unsigned i = 0; i != Inst.getNumOperands(); ++i) - if (Inst.getOperand(i).isExpr()) - AddValueSymbols(Inst.getOperand(i).getExpr()); - - getCurrentSectionData()->setHasInstructions(true); - - // If this instruction doesn't need relaxation, just emit it as data. - if (!getAssembler().getBackend().MayNeedRelaxation(Inst)) { - EmitInstToData(Inst); - return; - } - - // Otherwise, if we are relaxing everything, relax the instruction as much as - // possible and emit it as data. - if (getAssembler().getRelaxAll()) { - MCInst Relaxed; - getAssembler().getBackend().RelaxInstruction(Inst, Relaxed); - while (getAssembler().getBackend().MayNeedRelaxation(Relaxed)) - getAssembler().getBackend().RelaxInstruction(Relaxed, Relaxed); - EmitInstToData(Relaxed); - return; - } - - // Otherwise emit to a separate fragment. - EmitInstToFragment(Inst); -} - void MCELFStreamer::Finish() { for (std::vector::const_iterator i = LocalCommons.begin(), e = LocalCommons.end(); Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=117925&r1=117924&r2=117925&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Mon Nov 1 11:27:31 2010 @@ -31,8 +31,8 @@ class MCMachOStreamer : public MCObjectStreamer { private: - void EmitInstToFragment(const MCInst &Inst); - void EmitInstToData(const MCInst &Inst); + virtual void EmitInstToFragment(const MCInst &Inst); + virtual void EmitInstToData(const MCInst &Inst); public: MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, @@ -98,8 +98,6 @@ //report_fatal_error("unsupported directive: '.file'"); } - virtual void EmitInstruction(const MCInst &Inst); - virtual void Finish(); /// @} @@ -406,39 +404,6 @@ DF->getContents().append(Code.begin(), Code.end()); } -void MCMachOStreamer::EmitInstruction(const MCInst &Inst) { - // Scan for values. - for (unsigned i = Inst.getNumOperands(); i--; ) - if (Inst.getOperand(i).isExpr()) - AddValueSymbols(Inst.getOperand(i).getExpr()); - - getCurrentSectionData()->setHasInstructions(true); - - // Now that a machine instruction has been assembled into this section, make - // a line entry for any .loc directive that has been seen. - MCLineEntry::Make(this, getCurrentSection()); - - // If this instruction doesn't need relaxation, just emit it as data. - if (!getAssembler().getBackend().MayNeedRelaxation(Inst)) { - EmitInstToData(Inst); - return; - } - - // Otherwise, if we are relaxing everything, relax the instruction as much as - // possible and emit it as data. - if (getAssembler().getRelaxAll()) { - MCInst Relaxed; - getAssembler().getBackend().RelaxInstruction(Inst, Relaxed); - while (getAssembler().getBackend().MayNeedRelaxation(Relaxed)) - getAssembler().getBackend().RelaxInstruction(Relaxed, Relaxed); - EmitInstToData(Relaxed); - return; - } - - // Otherwise emit to a separate fragment. - EmitInstToFragment(Inst); -} - void MCMachOStreamer::Finish() { // Dump out the dwarf file & directory tables and line tables. if (getContext().hasDwarfFiles()) { Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=117925&r1=117924&r2=117925&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Mon Nov 1 11:27:31 2010 @@ -12,6 +12,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCExpr.h" #include "llvm/Target/TargetAsmBackend.h" using namespace llvm; @@ -90,6 +91,39 @@ CurSectionData = &getAssembler().getOrCreateSectionData(*Section); } +void MCObjectStreamer::EmitInstruction(const MCInst &Inst) { + // Scan for values. + for (unsigned i = Inst.getNumOperands(); i--; ) + if (Inst.getOperand(i).isExpr()) + AddValueSymbols(Inst.getOperand(i).getExpr()); + + getCurrentSectionData()->setHasInstructions(true); + + // Now that a machine instruction has been assembled into this section, make + // a line entry for any .loc directive that has been seen. + MCLineEntry::Make(this, getCurrentSection()); + + // If this instruction doesn't need relaxation, just emit it as data. + if (!getAssembler().getBackend().MayNeedRelaxation(Inst)) { + EmitInstToData(Inst); + return; + } + + // Otherwise, if we are relaxing everything, relax the instruction as much as + // possible and emit it as data. + if (getAssembler().getRelaxAll()) { + MCInst Relaxed; + getAssembler().getBackend().RelaxInstruction(Inst, Relaxed); + while (getAssembler().getBackend().MayNeedRelaxation(Relaxed)) + getAssembler().getBackend().RelaxInstruction(Relaxed, Relaxed); + EmitInstToData(Relaxed); + return; + } + + // Otherwise emit to a separate fragment. + EmitInstToFragment(Inst); +} + void MCObjectStreamer::Finish() { getAssembler().Finish(); } Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=117925&r1=117924&r2=117925&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Mon Nov 1 11:27:31 2010 @@ -81,6 +81,13 @@ virtual void Finish(); private: + virtual void EmitInstToFragment(const MCInst &Inst) { + llvm_unreachable("Not used by WinCOFF."); + } + virtual void EmitInstToData(const MCInst &Inst) { + llvm_unreachable("Not used by WinCOFF."); + } + void SetSection(StringRef Section, unsigned Characteristics, SectionKind Kind) { From grosbach at apple.com Mon Nov 1 11:44:21 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 16:44:21 -0000 Subject: [llvm-commits] [llvm] r117927 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101101164421.F081F2A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 11:44:21 2010 New Revision: 117927 URL: http://llvm.org/viewvc/llvm-project?rev=117927&view=rev Log: trailing whitespace Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=117927&r1=117926&r2=117927&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Nov 1 11:44:21 2010 @@ -369,7 +369,7 @@ int ARMAsmParser::TryParseRegister() { const AsmToken &Tok = Parser.getTok(); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); - + // FIXME: Validate register for the current architecture; we have to do // validation later, so maybe there is no need for this here. int RegNum = MatchRegisterName(Tok.getString()); @@ -378,8 +378,8 @@ Parser.Lex(); // Eat identifier token. return RegNum; } - - + + /// Try to parse a register name. The token must be an Identifier when called, /// and if it is a register name the token is eaten and the register number is /// returned. Otherwise return -1. @@ -390,7 +390,7 @@ SMLoc S = Parser.getTok().getLoc(); int RegNo = TryParseRegister(); if (RegNo == -1) return 0; - + SMLoc E = Parser.getTok().getLoc(); bool Writeback = false; @@ -602,7 +602,7 @@ E = CurLoc; } } - + // If we parsed a register as the offset then their can be a shift after that if (OffsetRegNum != -1) { // Look for a comma then a shift From grosbach at apple.com Mon Nov 1 11:59:55 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 16:59:55 -0000 Subject: [llvm-commits] [llvm] r117929 - in /llvm/trunk: lib/Target/ARM/ lib/Target/ARM/AsmParser/ test/MC/ARM/ Message-ID: <20101101165955.415922A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 11:59:54 2010 New Revision: 117929 URL: http://llvm.org/viewvc/llvm-project?rev=117929&view=rev Log: Mark ARM subtarget features that are available for the assembler. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/arm_word_directive.s llvm/trunk/test/MC/ARM/neon-abs-encoding.s llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s llvm/trunk/test/MC/ARM/neon-add-encoding.s llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s llvm/trunk/test/MC/ARM/neon-cmp-encoding.s llvm/trunk/test/MC/ARM/neon-convert-encoding.s llvm/trunk/test/MC/ARM/neon-dup-encoding.s llvm/trunk/test/MC/ARM/neon-minmax-encoding.s llvm/trunk/test/MC/ARM/neon-mov-encoding.s llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s llvm/trunk/test/MC/ARM/neon-mul-encoding.s llvm/trunk/test/MC/ARM/neon-neg-encoding.s llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s llvm/trunk/test/MC/ARM/neon-reverse-encoding.s llvm/trunk/test/MC/ARM/neon-satshift-encoding.s llvm/trunk/test/MC/ARM/neon-shift-encoding.s llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 1 11:59:54 2010 @@ -142,27 +142,29 @@ //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // -def HasV4T : Predicate<"Subtarget->hasV4TOps()">; +def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">; -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; -def HasV6 : Predicate<"Subtarget->hasV6Ops()">; -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">; +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate; +def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate; +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; -def HasV7 : Predicate<"Subtarget->hasV7Ops()">; +def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; -def HasNEON : Predicate<"Subtarget->hasNEON()">; -def HasDivide : Predicate<"Subtarget->hasDivide()">; -def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">; -def HasDB : Predicate<"Subtarget->hasDataBarrier()">; +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate; +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate; +def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate; +def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate; +def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, + AssemblerPredicate; +def HasDB : Predicate<"Subtarget->hasDataBarrier()">, + AssemblerPredicate; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; -def IsThumb : Predicate<"Subtarget->isThumb()">; +def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; -def IsThumb2 : Predicate<"Subtarget->isThumb2()">; -def IsARM : Predicate<"!Subtarget->isThumb()">; +def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate; +def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Nov 1 11:59:54 2010 @@ -92,7 +92,11 @@ public: ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} + : TargetAsmParser(T), Parser(_Parser), TM(_TM) { + // Initialize the set of available features. + setAvailableFeatures(ComputeAvailableFeatures( + &TM.getSubtarget())); + } virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -@ RUN: llvm-mc -triple arm-unknown-unknown -show-encoding %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s @ CHECK: nop @ CHECK: encoding: [0x00,0xf0,0x20,0xe3] Modified: llvm/trunk/test/MC/ARM/arm_word_directive.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_word_directive.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_word_directive.s (original) +++ llvm/trunk/test/MC/ARM/arm_word_directive.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -@ RUN: llvm-mc -triple arm-unknown-unknown %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown %s | FileCheck %s @ CHECK: TEST0: @ CHECK: .long 3 Modified: llvm/trunk/test/MC/ARM/neon-abs-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-abs-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-abs-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-abs-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3] vabs.s8 d16, d16 Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // NOTE: This currently fails because the ASM parser doesn't parse vabal. Modified: llvm/trunk/test/MC/ARM/neon-add-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-add-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-add-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-add-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s // CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2] Modified: llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] vand d16, d17, d16 Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-cmp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // FIXME: We cannot currently test the following instructions, which are Modified: llvm/trunk/test/MC/ARM/neon-convert-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-convert-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-convert-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-convert-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3] vcvt.s32.f32 d16, d16 Modified: llvm/trunk/test/MC/ARM/neon-dup-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-dup-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-dup-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-dup-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] Modified: llvm/trunk/test/MC/ARM/neon-minmax-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-minmax-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-minmax-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-minmax-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2] vmin.s8 d16, d16, d17 Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] Modified: llvm/trunk/test/MC/ARM/neon-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] vmul.i8 d16, d16, d17 Modified: llvm/trunk/test/MC/ARM/neon-neg-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-neg-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-neg-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-neg-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] vneg.s8 d16, d16 Modified: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // XFAIL: * // CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2] Modified: llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3] vrecpe.u32 d16, d16 Modified: llvm/trunk/test/MC/ARM/neon-reverse-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reverse-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-reverse-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-reverse-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3] vrev64.8 d16, d16 Modified: llvm/trunk/test/MC/ARM/neon-satshift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-satshift-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-satshift-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-satshift-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2] vqshl.s8 d16, d16, d17 Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] vshl.u8 d16, d17, d16 Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=117929&r1=117928&r2=117929&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Nov 1 11:59:54 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s // CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] vadd.f64 d16, d17, d16 From rafael.espindola at gmail.com Mon Nov 1 12:07:14 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 01 Nov 2010 17:07:14 -0000 Subject: [llvm-commits] [llvm] r117930 - in /llvm/trunk: lib/MC/MCELFStreamer.cpp test/MC/ELF/debug-line.s Message-ID: <20101101170714.E65D92A6C12C@llvm.org> Author: rafael Date: Mon Nov 1 12:07:14 2010 New Revision: 117930 URL: http://llvm.org/viewvc/llvm-project?rev=117930&view=rev Log: Write the line info to .debug_line. Added: llvm/trunk/test/MC/ELF/debug-line.s Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=117930&r1=117929&r2=117930&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Nov 1 12:07:14 2010 @@ -511,6 +511,15 @@ } void MCELFStreamer::Finish() { + // FIXME: duplicated code with the MachO streamer. + // Dump out the dwarf file & directory tables and line tables. + if (getContext().hasDwarfFiles()) { + const MCSection *DwarfLineSection = + getContext().getELFSection(".debug_line", 0, 0, + SectionKind::getDataRelLocal()); + MCDwarfFileTable::Emit(this, DwarfLineSection); + } + for (std::vector::const_iterator i = LocalCommons.begin(), e = LocalCommons.end(); i != e; ++i) { Added: llvm/trunk/test/MC/ELF/debug-line.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/debug-line.s?rev=117930&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/debug-line.s (added) +++ llvm/trunk/test/MC/ELF/debug-line.s Mon Nov 1 12:07:14 2010 @@ -0,0 +1,22 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +// Test that .debug_line is populated. + +// CHECK: (('sh_name', 0x00000031) # '.debug_line' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000044) +// CHECK-NEXT: ('sh_size', 0x00000037) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000001) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '33000000 02001c00 00000101 fb0e0d00 01010101 00000001 00000100 666f6f2e 63000000 00000009 02000000 00000000 00150204 000101') + + .section .debug_line,"", at progbits + .text + + .file 1 "foo.c" + .loc 1 4 0 + subq $8, %rsp From grosbach at apple.com Mon Nov 1 12:08:59 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 17:08:59 -0000 Subject: [llvm-commits] [llvm] r117931 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrThumb.td Message-ID: <20101101170859.1B7E02A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 12:08:58 2010 New Revision: 117931 URL: http://llvm.org/viewvc/llvm-project?rev=117931&view=rev Log: Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates codegen using the patterns; the latter gates the assembler recognizing the instruction. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117931&r1=117930&r2=117931&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 1 12:08:58 2010 @@ -1147,7 +1147,7 @@ let InOperandList = iops; let AsmString = asm; let Pattern = pattern; - list Predicates = [IsThumb1Only]; + list Predicates = [IsThumb, IsThumb1Only]; } class T1I Predicates = [IsThumb1Only]; + list Predicates = [IsThumb, IsThumb1Only]; } class T1sI Predicates = [IsThumb1Only]; + list Predicates = [IsThumb, IsThumb1Only]; } class T1pI Predicates = [IsThumb1Only]; + list Predicates = [IsThumb, IsThumb1Only]; } class T2I, but requires V5T Thumb mode. class Tv5Pat : Pat { - list Predicates = [IsThumb1Only, HasV5T]; + list Predicates = [IsThumb, IsThumb1Only, HasV5T]; } // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. class T1Pat : Pat { - list Predicates = [IsThumb1Only]; + list Predicates = [IsThumb, IsThumb1Only]; } // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=117931&r1=117930&r2=117931&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Nov 1 12:08:58 2010 @@ -127,11 +127,13 @@ let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { def tADJCALLSTACKUP : PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, "", - [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>; + [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, + Requires<[IsThumb, IsThumb1Only]>; def tADJCALLSTACKDOWN : PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, "", - [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>; + [(ARMcallseq_start imm:$amt)]>, + Requires<[IsThumb, IsThumb1Only]>; } def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", @@ -316,7 +318,7 @@ (outs), (ins tGPR:$func, variable_ops), IIC_Br, "mov\tlr, pc\n\tbx\t$func", [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsThumb1Only, IsNotDarwin]>; + Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; } // On Darwin R9 is call-clobbered. @@ -352,7 +354,7 @@ (outs), (ins tGPR:$func, variable_ops), IIC_Br, "mov\tlr, pc\n\tbx\t$func", [(ARMcall_nolink tGPR:$func)]>, - Requires<[IsThumb1Only, IsDarwin]>; + Requires<[IsThumb, IsThumb1Only, IsDarwin]>; } let isBranch = 1, isTerminator = 1 in { @@ -764,7 +766,7 @@ def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, "rev", "\t$dst, $src", [(set tGPR:$dst, (bswap tGPR:$src))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{1,0,1,0,0,0,?}>; def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, @@ -774,7 +776,7 @@ (or (and (shl tGPR:$src, (i32 8)), 0xFF00), (or (and (srl tGPR:$src, (i32 8)), 0xFF0000), (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{1,0,1,0,0,1,?}>; def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, @@ -783,7 +785,7 @@ (sext_inreg (or (srl (and tGPR:$src, 0xFF00), (i32 8)), (shl tGPR:$src, (i32 8))), i16))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{1,0,1,0,1,1,?}>; // rotate right register @@ -828,14 +830,14 @@ def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, "sxtb", "\t$dst, $src", [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{0,0,1,0,0,1,?}>; // sign-extend short def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, "sxth", "\t$dst, $src", [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{0,0,1,0,0,0,?}>; // test @@ -849,14 +851,14 @@ def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, "uxtb", "\t$dst, $src", [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{0,0,1,0,1,1,?}>; // zero-extend short def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, "uxth", "\t$dst, $src", [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, - Requires<[IsThumb1Only, HasV6]>, + Requires<[IsThumb, IsThumb1Only, HasV6]>, T1Misc<{0,0,1,0,1,0,?}>; @@ -994,10 +996,10 @@ // ldr{b|h} + sxt{b|h} instead. def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), (tSXTB (tLDRB t_addrmode_s1:$addr))>, - Requires<[IsThumb1Only, HasV6]>; + Requires<[IsThumb, IsThumb1Only, HasV6]>; def : T1Pat<(sextloadi16 t_addrmode_s2:$addr), (tSXTH (tLDRH t_addrmode_s2:$addr))>, - Requires<[IsThumb1Only, HasV6]>; + Requires<[IsThumb, IsThumb1Only, HasV6]>; def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>; @@ -1022,4 +1024,4 @@ NoItinerary, "", [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), imm:$cp))]>, - Requires<[IsThumb1Only]>; + Requires<[IsThumb, IsThumb1Only]>; From rafael.espindola at gmail.com Mon Nov 1 12:10:53 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 01 Nov 2010 17:10:53 -0000 Subject: [llvm-commits] [llvm] r117932 - /llvm/trunk/test/MC/ELF/debug-line.s Message-ID: <20101101171053.6DD212A6C12C@llvm.org> Author: rafael Date: Mon Nov 1 12:10:53 2010 New Revision: 117932 URL: http://llvm.org/viewvc/llvm-project?rev=117932&view=rev Log: Fix test. Modified: llvm/trunk/test/MC/ELF/debug-line.s Modified: llvm/trunk/test/MC/ELF/debug-line.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/debug-line.s?rev=117932&r1=117931&r2=117932&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/debug-line.s (original) +++ llvm/trunk/test/MC/ELF/debug-line.s Mon Nov 1 12:10:53 2010 @@ -2,7 +2,7 @@ // Test that .debug_line is populated. -// CHECK: (('sh_name', 0x00000031) # '.debug_line' +// CHECK: (('sh_name', 0x00000012) # '.debug_line' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) From baldrick at free.fr Mon Nov 1 12:24:04 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 01 Nov 2010 18:24:04 +0100 Subject: [llvm-commits] PATCH: llvm-gcc option to emit "va_arg" instruction In-Reply-To: References: <2CC138C3-4628-400A-AAEF-A030A21843A2@apple.com> <2646F00C-CDF0-402D-8C90-561B2C4B3B45@apple.com> <146F714B-AF1A-462F-B3F9-003E6EB2AE7D@apple.com> <4CB765E1.7060208@free.fr> <4CB9974A.5020004@free.fr> Message-ID: <4CCEF7B4.8030400@free.fr> Hi Rafael, >> If I may revive this thread from the graveyard... >> Could somebody take another look at this patch (attached) and let me know >> whether it is acceptable? (or if not, what I can do to improve it?) > > This is not being used by any target. I assume that it is intentional > while the completeness and efficiency of va_arg is worked out? Maybe > we should get one target to use it first? > > I think it is OK, but lets see what Duncan has to say. He had concerns > about the two step lowering... I was intending to test if having va_arg continue to the end works ok, but forgot about it. I will try to do this tomorrow. Ciao, Duncan. From bob.wilson at apple.com Mon Nov 1 12:37:23 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 01 Nov 2010 17:37:23 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r117934 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20101101173723.69A3F2A6C12C@llvm.org> Author: bwilson Date: Mon Nov 1 12:37:23 2010 New Revision: 117934 URL: http://llvm.org/viewvc/llvm-project?rev=117934&view=rev Log: Use a store-only memory barrier before atomic intrinsics for ARM/Darwin. We need to make sure that all previous stores have completed before the load-exclusive instruction, but preceding loads don't matter. There is still a full memory barrier after the store-exclusive instruction succeeds, so from the user's perspective, the atomic builtins are still full memory barriers. Radar 8601999. I don't know so much about synchronization on other targets besides ARM, and since there was already a separate version of the barriers for ARM/Darwin, I've only changed that version. It seems like this change would apply to other targets as well, but I don't know for sure. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=117934&r1=117933&r2=117934&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Nov 1 12:37:23 2010 @@ -5343,7 +5343,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -5386,7 +5386,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -5919,7 +5919,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -5966,7 +5966,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -6013,7 +6013,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -6060,7 +6060,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -6107,7 +6107,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif @@ -6154,7 +6154,7 @@ // The gcc builtins are also full memory barriers. // FIXME: __sync_lock_test_and_set and __sync_lock_release require less. #if defined(TARGET_ARM) && defined(CONFIG_DARWIN_H) - EmitMemoryBarrier(true, true, true, true, false); + EmitMemoryBarrier(false, false, true, true, false); #else EmitMemoryBarrier(true, true, true, true, true); #endif From resistor at mac.com Mon Nov 1 13:03:16 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 18:03:16 -0000 Subject: [llvm-commits] [llvm] r117935 - in /llvm/trunk/test/MC/ARM: neon-shiftaccum-encoding.ll neon-shiftaccum-encoding.s Message-ID: <20101101180316.7BD9F2A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 13:03:16 2010 New Revision: 117935 URL: http://llvm.org/viewvc/llvm-project?rev=117935&view=rev Log: Covert this test to .s form. Added: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s Removed: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll Removed: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll?rev=117934&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll (original) +++ llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll (removed) @@ -1,449 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -; XFAIL: * - -define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vsra.s8 d16, d17, #8 @ encoding: [0x31,0x01,0xc8,0xf2] - %tmp3 = ashr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - %tmp4 = add <8 x i8> %tmp1, %tmp3 - ret <8 x i8> %tmp4 -} - -define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vsra.s16 d16, d17, #16 @ encoding: [0x31,0x01,0xd0,0xf2] - %tmp3 = ashr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 > - %tmp4 = add <4 x i16> %tmp1, %tmp3 - ret <4 x i16> %tmp4 -} - -define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vsra.s32 d16, d17, #32 @ encoding: [0x31,0x01,0xe0,0xf2] - %tmp3 = ashr <2 x i32> %tmp2, < i32 32, i32 32 > - %tmp4 = add <2 x i32> %tmp1, %tmp3 - ret <2 x i32> %tmp4 -} - -define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vsra.s64 d16, d17, #64 @ encoding: [0xb1,0x01,0xc0,0xf2] - %tmp3 = ashr <1 x i64> %tmp2, < i64 64 > - %tmp4 = add <1 x i64> %tmp1, %tmp3 - ret <1 x i64> %tmp4 -} - -define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vsra.s8 q9, q8, #8 @ encoding: [0x70,0x21,0xc8,0xf2] - %tmp3 = ashr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - %tmp4 = add <16 x i8> %tmp1, %tmp3 - ret <16 x i8> %tmp4 -} - -define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vsra.s16 q9, q8, #16 @ encoding: [0x70,0x21,0xd0,0xf2] - %tmp3 = ashr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > - %tmp4 = add <8 x i16> %tmp1, %tmp3 - ret <8 x i16> %tmp4 -} - -define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vsra.s32 q9, q8, #32 @ encoding: [0x70,0x21,0xe0,0xf2] - %tmp3 = ashr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 > - %tmp4 = add <4 x i32> %tmp1, %tmp3 - ret <4 x i32> %tmp4 -} - -define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vsra.s64 q9, q8, #64 @ encoding: [0xf0,0x21,0xc0,0xf2] - %tmp3 = ashr <2 x i64> %tmp2, < i64 64, i64 64 > - %tmp4 = add <2 x i64> %tmp1, %tmp3 - ret <2 x i64> %tmp4 -} - -define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vsra.u8 d16, d17, #8 @ encoding: [0x31,0x01,0xc8,0xf3] - %tmp3 = lshr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - %tmp4 = add <8 x i8> %tmp1, %tmp3 - ret <8 x i8> %tmp4 -} - -define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vsra.u16 d16, d17, #16 @ encoding: [0x31,0x01,0xd0,0xf3] - %tmp3 = lshr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 > - %tmp4 = add <4 x i16> %tmp1, %tmp3 - ret <4 x i16> %tmp4 -} - -define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vsra.u32 d16, d17, #32 @ encoding: [0x31,0x01,0xe0,0xf3] - %tmp3 = lshr <2 x i32> %tmp2, < i32 32, i32 32 > - %tmp4 = add <2 x i32> %tmp1, %tmp3 - ret <2 x i32> %tmp4 -} - -define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vsra.u64 d16, d17, #64 @ encoding: [0xb1,0x01,0xc0,0xf3] - %tmp3 = lshr <1 x i64> %tmp2, < i64 64 > - %tmp4 = add <1 x i64> %tmp1, %tmp3 - ret <1 x i64> %tmp4 -} - -define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vsra.u8 q9, q8, #8 @ encoding: [0x70,0x21,0xc8,0xf3] - %tmp3 = lshr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > - %tmp4 = add <16 x i8> %tmp1, %tmp3 - ret <16 x i8> %tmp4 -} - -define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vsra.u16 q9, q8, #16 @ encoding: [0x70,0x21,0xd0,0xf3] - %tmp3 = lshr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > - %tmp4 = add <8 x i16> %tmp1, %tmp3 - ret <8 x i16> %tmp4 -} - -define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vsra.u32 q9, q8, #32 @ encoding: [0x70,0x21,0xe0,0xf3] - %tmp3 = lshr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 > - %tmp4 = add <4 x i32> %tmp1, %tmp3 - ret <4 x i32> %tmp4 -} - -define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vsra.u64 q9, q8, #64 @ encoding: [0xf0,0x21,0xc0,0xf3] - %tmp3 = lshr <2 x i64> %tmp2, < i64 64, i64 64 > - %tmp4 = add <2 x i64> %tmp1, %tmp3 - ret <2 x i64> %tmp4 -} - -define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vrsra.s8 d16, d17, #8 @ encoding: [0x31,0x03,0xc8,0xf2] - %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - %tmp4 = add <8 x i8> %tmp1, %tmp3 - ret <8 x i8> %tmp4 -} - -define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vrsra.s16 d16, d17, #16 @ encoding: [0x31,0x03,0xd0,0xf2] - %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) - %tmp4 = add <4 x i16> %tmp1, %tmp3 - ret <4 x i16> %tmp4 -} - -define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vrsra.s32 d16, d17, #32 @ encoding: [0x31,0x03,0xe0,0xf2] - %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) - %tmp4 = add <2 x i32> %tmp1, %tmp3 - ret <2 x i32> %tmp4 -} - -define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vrsra.s64 d16, d17, #64 @ encoding: [0xb1,0x03,0xc0,0xf2] - %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >) - %tmp4 = add <1 x i64> %tmp1, %tmp3 - ret <1 x i64> %tmp4 -} - -define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vrsra.u8 d16, d17, #8 @ encoding: [0x31,0x03,0xc8,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - %tmp4 = add <8 x i8> %tmp1, %tmp3 - ret <8 x i8> %tmp4 -} - -define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vrsra.u16 d16, d17, #16 @ encoding: [0x31,0x03,0xd0,0xf3] - %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) - %tmp4 = add <4 x i16> %tmp1, %tmp3 - ret <4 x i16> %tmp4 -} - -define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vrsra.u32 d16, d17, #32 @ encoding: [0x31,0x03,0xe0,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) - %tmp4 = add <2 x i32> %tmp1, %tmp3 - ret <2 x i32> %tmp4 -} - -define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vrsra.u64 d16, d17, #64 @ encoding: [0xb1,0x03,0xc0,0xf3] - %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >) - %tmp4 = add <1 x i64> %tmp1, %tmp3 - ret <1 x i64> %tmp4 -} - -define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vrsra.s8 q9, q8, #8 @ encoding: [0x70,0x23,0xc8,0xf2] - %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - %tmp4 = add <16 x i8> %tmp1, %tmp3 - ret <16 x i8> %tmp4 -} - -define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vrsra.s16 q9, q8, #16 @ encoding: [0x70,0x23,0xd0,0xf2] - %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) - %tmp4 = add <8 x i16> %tmp1, %tmp3 - ret <8 x i16> %tmp4 -} - -define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vrsra.s32 q9, q8, #32 @ encoding: [0x70,0x23,0xe0,0xf2] - %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) - %tmp4 = add <4 x i32> %tmp1, %tmp3 - ret <4 x i32> %tmp4 -} - -define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vrsra.s64 q9, q8, #64 @ encoding: [0xf0,0x23,0xc0,0xf2] - %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) - %tmp4 = add <2 x i64> %tmp1, %tmp3 - ret <2 x i64> %tmp4 -} - -define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vrsra.u8 q9, q8, #8 @ encoding: [0x70,0x23,0xc8,0xf3] - %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - %tmp4 = add <16 x i8> %tmp1, %tmp3 - ret <16 x i8> %tmp4 -} - -define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vrsra.u16 q9, q8, #16 @ encoding: [0x70,0x23,0xd0,0xf3] - %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) - %tmp4 = add <8 x i16> %tmp1, %tmp3 - ret <8 x i16> %tmp4 -} - -define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vrsra.u32 q9, q8, #32 @ encoding: [0x70,0x23,0xe0,0xf3] - %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) - %tmp4 = add <4 x i32> %tmp1, %tmp3 - ret <4 x i32> %tmp4 -} - -define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vrsra.u64 q9, q8, #64 @ encoding: [0xf0,0x23,0xc0,0xf3] - %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) - %tmp4 = add <2 x i64> %tmp1, %tmp3 - ret <2 x i64> %tmp4 -} - -declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone - -declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone - -declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone - -declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone - -define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vsli.8 d17, d16, #7 @ encoding: [0x30,0x15,0xcf,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) - ret <8 x i8> %tmp3 -} - -define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vsli.16 d17, d16, #15 @ encoding: [0x30,0x15,0xdf,0xf3] - %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) - ret <4 x i16> %tmp3 -} - -define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vsli.32 d17, d16, #31 @ encoding: [0x30,0x15,0xff,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >) - ret <2 x i32> %tmp3 -} - -define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vsli.64 d17, d16, #63 @ encoding: [0xb0,0x15,0xff,0xf3] - %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >) - ret <1 x i64> %tmp3 -} - -define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vsli.8 q8, q9, #7 @ encoding: [0x72,0x05,0xcf,0xf3] - %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) - ret <16 x i8> %tmp3 -} - -define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vsli.16 q8, q9, #15 @ encoding: [0x72,0x05,0xdf,0xf3] - %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) - ret <8 x i16> %tmp3 -} - -define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vsli.32 q8, q9, #31 @ encoding: [0x72,0x05,0xff,0xf3] - %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) - ret <4 x i32> %tmp3 -} - -define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vsli.64 q8, q9, #63 @ encoding: [0xf2,0x05,0xff,0xf3] - %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >) - ret <2 x i64> %tmp3 -} - -define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vsri.8 d17, d16, #8 @ encoding: [0x30,0x14,0xc8,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - ret <8 x i8> %tmp3 -} - -define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vsri.16 d17, d16, #16 @ encoding: [0x30,0x14,0xd0,0xf3 - %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) - ret <4 x i16> %tmp3 -} - -define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vsri.32 d17, d16, #32 @ encoding: [0x30,0x14,0xe0,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) - ret <2 x i32> %tmp3 -} - -define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vsri.64 d17, d16, #64 @ encoding: [0xb0,0x14,0xc0,0xf3] - %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >) - ret <1 x i64> %tmp3 -} - -define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vsri.8 q8, q9, #8 @ encoding: [0x72,0x04,0xc8,0xf3] - %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) - ret <16 x i8> %tmp3 -} - -define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vsri.16 q8, q9, #16 @ encoding: [0x72,0x04,0xd0,0xf3] - %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) - ret <8 x i16> %tmp3 -} - -define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vsri.32 q8, q9, #32 @ encoding: [0x72,0x04,0xe0,0xf3] - %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) - ret <4 x i32> %tmp3 -} - -define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vsri.64 q8, q9, #64 @ encoding: [0xf2,0x04,0xc0,0xf3] - %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) - ret <2 x i64> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone - -declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone Added: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s?rev=117935&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s Mon Nov 1 13:03:16 2010 @@ -0,0 +1,98 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s + +@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf2] + vsra.s8 d17, d16, #8 +@ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf2] + vsra.s16 d17, d16, #16 +@ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf2] + vsra.s32 d17, d16, #32 +@ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf2] + vsra.s64 d17, d16, #64 +@ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf2] + vsra.s8 q8, q9, #8 +@ CHECK: vsra.s16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xf2] + vsra.s16 q8, q9, #16 +@ CHECK: vsra.s32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xf2] + vsra.s32 q8, q9, #32 +@ CHECK: vsra.s64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xf2] + vsra.s64 q8, q9, #64 +@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xf3] + vsra.u8 d17, d16, #8 +@ CHECK: vsra.u16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xf3] + vsra.u16 d17, d16, #16 +@ CHECK: vsra.u32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xf3] + vsra.u32 d17, d16, #32 +@ CHECK: vsra.u64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xf3] + vsra.u64 d17, d16, #64 +@ CHECK: vsra.u8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xf3] + vsra.u8 q8, q9, #8 +@ CHECK: vsra.u16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xf3] + vsra.u16 q8, q9, #16 +@ CHECK: vsra.u32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xf3] + vsra.u32 q8, q9, #32 +@ CHECK: vsra.u64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xf3] + vsra.u64 q8, q9, #64 +@ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf2] + vrsra.s8 d17, d16, #8 +@ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf2] + vrsra.s16 d17, d16, #16 +@ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf2] + vrsra.s32 d17, d16, #32 +@ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf2] + vrsra.s64 d17, d16, #64 +@ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf3] + vrsra.u8 d17, d16, #8 +@ CHECK: vrsra.u16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf3] + vrsra.u16 d17, d16, #16 +@ CHECK: vrsra.u32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf3] + vrsra.u32 d17, d16, #32 +@ CHECK: vrsra.u64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf3] + vrsra.u64 d17, d16, #64 +@ CHECK: vrsra.s8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xf2] + vrsra.s8 q8, q9, #8 +@ CHECK: vrsra.s16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xf2] + vrsra.s16 q8, q9, #16 +@ CHECK: vrsra.s32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xf2] + vrsra.s32 q8, q9, #32 +@ CHECK: vrsra.s64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf2] + vrsra.s64 q8, q9, #64 +@ CHECK: vrsra.u8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xf3] + vrsra.u8 q8, q9, #8 +@ CHECK: vrsra.u16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xf3] + vrsra.u16 q8, q9, #16 +@ CHECK: vrsra.u32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xf3] + vrsra.u32 q8, q9, #32 +@ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xf3] + vrsra.u64 q8, q9, #64 +@ CHECK: vsli.8 d17, d16, #7 @ encoding: [0x30,0x15,0xcf,0xf3] + vsli.8 d17, d16, #7 +@ CHECK: vsli.16 d17, d16, #15 @ encoding: [0x30,0x15,0xdf,0xf3] + vsli.16 d17, d16, #15 +@ CHECK: vsli.32 d17, d16, #31 @ encoding: [0x30,0x15,0xff,0xf3] + vsli.32 d17, d16, #31 +@ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xb0,0x15,0xff,0xf3] + vsli.64 d17, d16, #63 +@ CHECK: vsli.8 q9, q8, #7 @ encoding: [0x70,0x25,0xcf,0xf3] + vsli.8 q9, q8, #7 +@ CHECK: vsli.16 q9, q8, #15 @ encoding: [0x70,0x25,0xdf,0xf3] + vsli.16 q9, q8, #15 +@ CHECK: vsli.32 q9, q8, #31 @ encoding: [0x70,0x25,0xff,0xf3] + vsli.32 q9, q8, #31 +@ CHECK: vsli.64 q9, q8, #63 @ encoding: [0xf0,0x25,0xff,0xf3] + vsli.64 q9, q8, #63 +@ CHECK: vsri.8 d17, d16, #8 @ encoding: [0x30,0x14,0xc8,0xf3] + vsri.8 d17, d16, #8 +@ CHECK: vsri.16 d17, d16, #16 @ encoding: [0x30,0x14,0xd0,0xf3] + vsri.16 d17, d16, #16 +@ CHECK: vsri.32 d17, d16, #32 @ encoding: [0x30,0x14,0xe0,0xf3] + vsri.32 d17, d16, #32 +@ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xb0,0x14,0xc0,0xf3] + vsri.64 d17, d16, #64 +@ CHECK: vsri.8 q9, q8, #8 @ encoding: [0x70,0x24,0xc8,0xf3] + vsri.8 q9, q8, #8 +@ CHECK: vsri.16 q9, q8, #16 @ encoding: [0x70,0x24,0xd0,0xf3] + vsri.16 q9, q8, #16 +@ CHECK: vsri.32 q9, q8, #32 @ encoding: [0x70,0x24,0xe0,0xf3] + vsri.32 q9, q8, #32 +@ CHECK: vsri.64 q9, q8, #64 @ encoding: [0xf0,0x24,0xc0,0xf3] + vsri.64 q9, q8, #64 From grosbach at apple.com Mon Nov 1 13:11:14 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 18:11:14 -0000 Subject: [llvm-commits] [llvm] r117936 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101101181114.DBF502A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 13:11:14 2010 New Revision: 117936 URL: http://llvm.org/viewvc/llvm-project?rev=117936&view=rev Log: Add FIXME. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=117936&r1=117935&r2=117936&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Nov 1 13:11:14 2010 @@ -756,6 +756,7 @@ } Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); + // FIXME: Should only add this operand for predicated instructions Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc)); // Add the remaining tokens in the mnemonic. From resistor at mac.com Mon Nov 1 13:13:11 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 18:13:11 -0000 Subject: [llvm-commits] [llvm] r117937 - in /llvm/trunk/test/MC/ARM: neon-shuffle-encoding.ll neon-shuffle-encoding.s Message-ID: <20101101181311.3F37C2A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 13:13:11 2010 New Revision: 117937 URL: http://llvm.org/viewvc/llvm-project?rev=117937&view=rev Log: Covert this test to .s form. Added: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Removed: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.ll Removed: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.ll?rev=117936&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.ll (original) +++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.ll (removed) @@ -1,215 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -; XFAIL: * - -define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] - %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - ret <8 x i8> %tmp3 -} - -define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2] - %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - ret <8 x i8> %tmp3 -} - -define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vext.8 q8, q8, q9, #3 @ encoding: [0xe2,0x03,0xf0,0xf2 - %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - ret <16 x i8> %tmp3 -} - -define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vext.8 q8, q8, q9, #7 @ encoding: [0xe2,0x07,0xf0,0xf2] - %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - ret <16 x i8> %tmp3 -} - -define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] - %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - ret <4 x i16> %tmp3 -} - -define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vext.32 q8, q8, q9, #3 @ encoding: [0xe2,0x03,0xf0,0xf2] - %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - ret <4 x i32> %tmp3 -} - -define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] - %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - %tmp5 = add <8 x i8> %tmp3, %tmp4 - ret <8 x i8> %tmp5 -} - -define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xf3] - %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp5 = add <4 x i16> %tmp3, %tmp4 - ret <4 x i16> %tmp5 -} - -define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xf3] - %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> - %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> - %tmp5 = add <2 x i32> %tmp3, %tmp4 - ret <2 x i32> %tmp5 -} - -define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vadd.i8 q8, q9, q8 @ encoding: [0xe0,0x08,0x42,0xf2] - %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - %tmp5 = add <16 x i8> %tmp3, %tmp4 - ret <16 x i8> %tmp5 -} - -define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vadd.i16 q8, q9, q8 @ encoding: [0xe0,0x08,0x52,0xf2] - %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp5 = add <8 x i16> %tmp3, %tmp4 - ret <8 x i16> %tmp5 -} - -define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xf3] - %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - %tmp5 = add <4 x i32> %tmp3, %tmp4 - ret <4 x i32> %tmp5 -} - -define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3] - %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - %tmp5 = add <8 x i8> %tmp3, %tmp4 - ret <8 x i8> %tmp5 -} - -define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3 - %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp5 = add <4 x i16> %tmp3, %tmp4 - ret <4 x i16> %tmp5 -} - -; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors. - -define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3] - %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - %tmp5 = add <16 x i8> %tmp3, %tmp4 - ret <16 x i8> %tmp5 -} - -define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3] - %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp5 = add <8 x i16> %tmp3, %tmp4 - ret <8 x i16> %tmp5 -} - -define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xf3] - %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - %tmp5 = add <4 x i32> %tmp3, %tmp4 - ret <4 x i32> %tmp5 -} - -define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xf3] - %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> - %tmp5 = add <8 x i8> %tmp3, %tmp4 - ret <8 x i8> %tmp5 -} - -define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xf3] - %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp5 = add <4 x i16> %tmp3, %tmp4 - ret <4 x i16> %tmp5 -} - -; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors. - -define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3] - %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> - %tmp5 = add <16 x i8> %tmp3, %tmp4 - ret <16 x i8> %tmp5 -} - -define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3] - %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp5 = add <8 x i16> %tmp3, %tmp4 - ret <8 x i16> %tmp5 -} - -define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] - %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> - %tmp5 = add <4 x i32> %tmp3, %tmp4 - ret <4 x i32> %tmp5 -} Added: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s?rev=117937&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Mon Nov 1 13:13:11 2010 @@ -0,0 +1,46 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] + vext.8 d16, d17, d16, #3 +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2] + vext.8 d16, d17, d16, #5 +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] + vext.8 q8, q9, q8, #3 +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2] + vext.8 q8, q9, q8, #7 +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] + vext.16 d16, d17, d16, #3 +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] + vext.32 q8, q9, q8, #3 +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] + vtrn.8 d17, d16 +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xf3] + vtrn.16 d17, d16 +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xf3] + vtrn.32 d17, d16 +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xe0,0x20,0xf2,0xf3] + vtrn.8 q9, q8 +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xe0,0x20,0xf6,0xf3] + vtrn.16 q9, q8 +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xf3] + vtrn.32 q9, q8 +@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3] + vuzp.8 d17, d16 +@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3] + vuzp.16 d17, d16 +@ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3] + vuzp.8 q9, q8 +@ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3] + vuzp.16 q9, q8 +@ CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xf3] + vuzp.32 q9, q8 +@ CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xf3] + vzip.8 d17, d16 +@ CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xf3] + vzip.16 d17, d16 +@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xf3] + vzip.8 q9, q8 +@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xf3] + vzip.16 q9, q8 +@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xf3] + vzip.32 q9, q8 From resistor at mac.com Mon Nov 1 13:26:43 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 18:26:43 -0000 Subject: [llvm-commits] [llvm] r117938 - in /llvm/trunk/test/MC/ARM: neon-sub-encoding.ll neon-sub-encoding.s Message-ID: <20101101182643.5E1552A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 13:26:43 2010 New Revision: 117938 URL: http://llvm.org/viewvc/llvm-project?rev=117938&view=rev Log: Convert this test to .s form. Added: llvm/trunk/test/MC/ARM/neon-sub-encoding.s Removed: llvm/trunk/test/MC/ARM/neon-sub-encoding.ll Removed: llvm/trunk/test/MC/ARM/neon-sub-encoding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-sub-encoding.ll?rev=117937&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-sub-encoding.ll (original) +++ llvm/trunk/test/MC/ARM/neon-sub-encoding.ll (removed) @@ -1,538 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -; XFAIL: * - -; CHECK: vsub_8xi8 -define <8 x i8> @vsub_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3] - %tmp3 = sub <8 x i8> %tmp1, %tmp2 - ret <8 x i8> %tmp3 -} - -; CHECK: vsub_4xi16 -define <4 x i16> @vsub_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] - %tmp3 = sub <4 x i16> %tmp1, %tmp2 - ret <4 x i16> %tmp3 -} - -; CHECK: vsub_2xi32 -define <2 x i32> @vsub_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3] - %tmp2 = load <2 x i32>* %B - %tmp3 = sub <2 x i32> %tmp1, %tmp2 - ret <2 x i32> %tmp3 -} - -; CHECK: vsub_1xi64 -define <1 x i64> @vsub_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3] - %tmp3 = sub <1 x i64> %tmp1, %tmp2 - ret <1 x i64> %tmp3 -} - -; CHECK: vsub_2xifloat -define <2 x float> @vsub_2xifloat(<2 x float>* %A, <2 x float>* %B) nounwind { - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B -; CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2] - %tmp3 = fsub <2 x float> %tmp1, %tmp2 - ret <2 x float> %tmp3 -} - -; CHECK: vsub_16xi8 -define <16 x i8> @vsub_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3] - %tmp3 = sub <16 x i8> %tmp1, %tmp2 - ret <16 x i8> %tmp3 -} - -; CHECK: vsub_8xi16 -define <8 x i16> @vsub_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] - %tmp3 = sub <8 x i16> %tmp1, %tmp2 - ret <8 x i16> %tmp3 -} - -; CHECK: vsub_4xi32 -define <4 x i32> @vsub_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3] - %tmp3 = sub <4 x i32> %tmp1, %tmp2 - ret <4 x i32> %tmp3 -} - -; CHECK: vsub_2xi64 -define <2 x i64> @vsub_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3] - %tmp3 = sub <2 x i64> %tmp1, %tmp2 - ret <2 x i64> %tmp3 -} - -; CHECK: vsub_4xfloat -define <4 x float> @vsub_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind { - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B -; CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2] - %tmp3 = fsub <4 x float> %tmp1, %tmp2 - ret <4 x float> %tmp3 -} - -; CHECK: vsubls_8xi8 -define <8 x i16> @vsubls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> - %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> -; CHECK: vsubl.s8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf2] - %tmp5 = sub <8 x i16> %tmp3, %tmp4 - ret <8 x i16> %tmp5 -} - -; CHECK: vsubls_4xi16 -define <4 x i32> @vsubls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> - %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> -; CHECK: vsubl.s16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf2] - %tmp5 = sub <4 x i32> %tmp3, %tmp4 - ret <4 x i32> %tmp5 -} - -; CHECK: vsubls_2xi32 -define <2 x i64> @vsubls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> - %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> -; CHECK: vsubl.s32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf2] - %tmp5 = sub <2 x i64> %tmp3, %tmp4 - ret <2 x i64> %tmp5 -} - -; CHECK: vsublu_8xi8 -define <8 x i16> @vsublu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> - %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> -; CHECK: vsubl.u8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf3] - %tmp5 = sub <8 x i16> %tmp3, %tmp4 - ret <8 x i16> %tmp5 -} - -; CHECK: vsublu_4xi16 -define <4 x i32> @vsublu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> - %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> -; CHECK: vsubl.u16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf3] - %tmp5 = sub <4 x i32> %tmp3, %tmp4 - ret <4 x i32> %tmp5 -} - -; CHECK: vsublu_2xi32 -define <2 x i64> @vsublu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> - %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> -; CHECK: vsubl.u32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf3] - %tmp5 = sub <2 x i64> %tmp3, %tmp4 - ret <2 x i64> %tmp5 -} - -; CHECK: vsubws_8xi8 -define <8 x i16> @vsubws_8xi8(<8 x i16>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = sext <8 x i8> %tmp2 to <8 x i16> -; CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2] - %tmp4 = sub <8 x i16> %tmp1, %tmp3 - ret <8 x i16> %tmp4 -} - -; CHECK: vsubws_4xi16 -define <4 x i32> @vsubws_4xi16(<4 x i32>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = sext <4 x i16> %tmp2 to <4 x i32> -; CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2] - %tmp4 = sub <4 x i32> %tmp1, %tmp3 - ret <4 x i32> %tmp4 -} - -; CHECK: vsubws_2xi32 -define <2 x i64> @vsubws_2xi32(<2 x i64>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = sext <2 x i32> %tmp2 to <2 x i64> -; CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2] - %tmp4 = sub <2 x i64> %tmp1, %tmp3 - ret <2 x i64> %tmp4 -} - -; CHECK: vsubwu_8xi8 -define <8 x i16> @vsubwu_8xi8(<8 x i16>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = zext <8 x i8> %tmp2 to <8 x i16> -; CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3] - %tmp4 = sub <8 x i16> %tmp1, %tmp3 - ret <8 x i16> %tmp4 -} - -; CHECK: vsubwu_4xi16 -define <4 x i32> @vsubwu_4xi16(<4 x i32>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = zext <4 x i16> %tmp2 to <4 x i32> -; CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3] - %tmp4 = sub <4 x i32> %tmp1, %tmp3 - ret <4 x i32> %tmp4 -} - -; CHECK: vsubwu_2xi32 -define <2 x i64> @vsubwu_2xi32(<2 x i64>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = zext <2 x i32> %tmp2 to <2 x i64> -; CHECK: vsubw.u32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf3] - %tmp4 = sub <2 x i64> %tmp1, %tmp3 - ret <2 x i64> %tmp4 -} - -declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone - -; CHECK: vhsubs_8xi8 -define <8 x i8> @vhsubs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2] - %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vhsubs_4xi16 -define <4 x i16> @vhsubs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2] - %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vhsubs_2xi32 -define <2 x i32> @vhsubs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2] - %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i32> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone - -; CHECK: vhsubu_8xi8 -define <8 x i8> @vhsubu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vhsubu_4xi16 -define <4 x i16> @vhsubu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3] - %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vhsubu_2xi32 -define <2 x i32> @vhsubu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vhsub.u32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i32> %tmp3 -} - -declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone - -; CHECK: vhsubs_16xi8 -define <16 x i8> @vhsubs_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vhsub.s8 q8, q8, q9 @ encoding: [0xe2,0x02,0x40,0xf2] - %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - ret <16 x i8> %tmp3 -} - -; CHECK: vhsubs_8xi16 -define <8 x i16> @vhsubs_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vhsub.s16 q8, q8, q9 @ encoding: [0xe2,0x02,0x50,0xf2] - %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i16> %tmp3 -} - -; CHECK: vhsubs_4xi32 -define <4 x i32> @vhsubs_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vhsub.s32 q8, q8, q9 @ encoding: [0xe2,0x02,0x60,0xf2] - %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i32> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone - -; CHECK: vqsubs_8xi8 -define <8 x i8> @vqsubs_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vqsub.s8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf2] - %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vqsubs_4xi16 -define <4 x i16> @vqsubs_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vqsub.s16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf2] - %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vqsubs_2xi32 -define <2 x i32> @vqsubs_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vqsub.s32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf2] - %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i32> %tmp3 -} - -; CHECK: vqsubs_1xi64 -define <1 x i64> @vqsubs_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vqsub.s64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf2] - %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) - ret <1 x i64> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone - -; CHECK: vqsubu_8xi8 -define <8 x i8> @vqsubu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vqsub.u8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vqsubu_4xi16 -define <4 x i16> @vqsubu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B -; CHECK: vqsub.u16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf3] - %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vqsubu_2xi32 -define <2 x i32> @vqsubu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B -; CHECK: vqsub.u32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i32> %tmp3 -} - -; CHECK: vqsubu_1xi64 -define <1 x i64> @vqsubu_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B -; CHECK: vqsub.u64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf3] - %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2) - ret <1 x i64> %tmp3 -} - -declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vqsubs_16xi8 -define <16 x i8> @vqsubs_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vqsub.s8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf2] - %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - ret <16 x i8> %tmp3 -} - -; CHECK: vqsubs_8xi16 -define <8 x i16> @vqsubs_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vqsub.s16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf2] - %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i16> %tmp3 -} - -; CHECK: vqsubs_4xi32 -define <4 x i32> @vqsubs_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vqsub.s32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf2] - %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i32> %tmp3 -} - -; CHECK: vqsubs_2xi64 -define <2 x i64> @vqsubs_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vqsub.s64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf2] - %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i64> %tmp3 -} - -declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vqsubu_16xi8 -define <16 x i8> @vqsubu_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B -; CHECK: vqsub.u8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf3] - %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - ret <16 x i8> %tmp3 -} - -; CHECK: vqsubu_8xi16 -define <8 x i16> @vqsubu_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vqsub.u16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf3] - %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i16> %tmp3 -} - -; CHECK: vqsubu_4xi32 -define <4 x i32> @vqsubu_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vqsub.u32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf3] - %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i32> %tmp3 -} - -; CHECK: vqsubu_2xi64 -define <2 x i64> @vqsubu_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vqsub.u64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf3] - %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i64> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vsubhn_8xi16 -define <8 x i8> @vsubhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2] - %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vsubhn_4xi32 -define <4 x i16> @vsubhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf2] - %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vsubhn_2xi64 -define <2 x i32> @vsubhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2] - %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i32> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone - -; CHECK: vrsubhn_8xi16 -define <8 x i8> @vrsubhn_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B -; CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i8> %tmp3 -} - -; CHECK: vrsubhn_4xi32 -define <4 x i16> @vrsubhn_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B -; CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3] - %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i16> %tmp3 -} - -; CHECK: vrsubhn_2xi64 -define <2 x i32> @vrsubhn_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B -; CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3] - %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i32> %tmp3 -} Added: llvm/trunk/test/MC/ARM/neon-sub-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-sub-encoding.s?rev=117938&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-sub-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-sub-encoding.s Mon Nov 1 13:26:43 2010 @@ -0,0 +1,108 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s + +@ CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3] + vsub.i8 d16, d17, d16 +@ CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] + vsub.i16 d16, d17, d16 +@ CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3] + vsub.i32 d16, d17, d16 +@ CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3] + vsub.i64 d16, d17, d16 +@ CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2] + vsub.f32 d16, d16, d17 +@ CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3] + vsub.i8 q8, q8, q9 +@ CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] + vsub.i16 q8, q8, q9 +@ CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3] + vsub.i32 q8, q8, q9 +@ CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3] + vsub.i64 q8, q8, q9 +@ CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2] + vsub.f32 q8, q8, q9 +@ CHECK: vsubl.s8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf2] + vsubl.s8 q8, d17, d16 +@ CHECK: vsubl.s16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf2] + vsubl.s16 q8, d17, d16 +@ CHECK: vsubl.s32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf2] + vsubl.s32 q8, d17, d16 +@ CHECK: vsubl.u8 q8, d17, d16 @ encoding: [0xa0,0x02,0xc1,0xf3] + vsubl.u8 q8, d17, d16 +@ CHECK: vsubl.u16 q8, d17, d16 @ encoding: [0xa0,0x02,0xd1,0xf3] + vsubl.u16 q8, d17, d16 +@ CHECK: vsubl.u32 q8, d17, d16 @ encoding: [0xa0,0x02,0xe1,0xf3] + vsubl.u32 q8, d17, d16 +@ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2] + vsubw.s8 q8, q8, d18 +@ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2] + vsubw.s16 q8, q8, d18 +@ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2] + vsubw.s32 q8, q8, d18 +@ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3] + vsubw.u8 q8, q8, d18 +@ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3] + vsubw.u16 q8, q8, d18 +@ CHECK: vsubw.u32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf3] + vsubw.u32 q8, q8, d18 +@ CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2] + vhsub.s8 d16, d16, d17 +@ CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2] + vhsub.s16 d16, d16, d17 +@ CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2] + vhsub.s32 d16, d16, d17 +@ CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3] + vhsub.u8 d16, d16, d17 +@ CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3] + vhsub.u16 d16, d16, d17 +@ CHECK: vhsub.u32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf3] + vhsub.u32 d16, d16, d17 +@ CHECK: vhsub.s8 q8, q8, q9 @ encoding: [0xe2,0x02,0x40,0xf2] + vhsub.s8 q8, q8, q9 +@ CHECK: vhsub.s16 q8, q8, q9 @ encoding: [0xe2,0x02,0x50,0xf2] + vhsub.s16 q8, q8, q9 +@ CHECK: vhsub.s32 q8, q8, q9 @ encoding: [0xe2,0x02,0x60,0xf2] + vhsub.s32 q8, q8, q9 +@ CHECK: vqsub.s8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf2] + vqsub.s8 d16, d16, d17 +@ CHECK: vqsub.s16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf2] + vqsub.s16 d16, d16, d17 +@ CHECK: vqsub.s32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf2] + vqsub.s32 d16, d16, d17 +@ CHECK: vqsub.s64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf2] + vqsub.s64 d16, d16, d17 +@ CHECK: vqsub.u8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf3] + vqsub.u8 d16, d16, d17 +@ CHECK: vqsub.u16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf3] + vqsub.u16 d16, d16, d17 +@ CHECK: vqsub.u32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf3] + vqsub.u32 d16, d16, d17 +@ CHECK: vqsub.u64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf3] + vqsub.u64 d16, d16, d17 +@ CHECK: vqsub.s8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf2] + vqsub.s8 q8, q8, q9 +@ CHECK: vqsub.s16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf2] + vqsub.s16 q8, q8, q9 +@ CHECK: vqsub.s32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf2] + vqsub.s32 q8, q8, q9 +@ CHECK: vqsub.s64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf2] + vqsub.s64 q8, q8, q9 +@ CHECK: vqsub.u8 q8, q8, q9 @ encoding: [0xf2,0x02,0x40,0xf3] + vqsub.u8 q8, q8, q9 +@ CHECK: vqsub.u16 q8, q8, q9 @ encoding: [0xf2,0x02,0x50,0xf3] + vqsub.u16 q8, q8, q9 +@ CHECK: vqsub.u32 q8, q8, q9 @ encoding: [0xf2,0x02,0x60,0xf3] + vqsub.u32 q8, q8, q9 +@ CHECK: vqsub.u64 q8, q8, q9 @ encoding: [0xf2,0x02,0x70,0xf3] + vqsub.u64 q8, q8, q9 +@ CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2] + vsubhn.i16 d16, q8, q9 +@ CHECK: vsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf2] + vsubhn.i32 d16, q8, q9 +@ CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2] + vsubhn.i64 d16, q8, q9 +@ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3] + vrsubhn.i16 d16, q8, q9 +@ CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3] + vrsubhn.i32 d16, q8, q9 +@ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3] + vrsubhn.i64 d16, q8, q9 From resistor at mac.com Mon Nov 1 13:30:39 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 18:30:39 -0000 Subject: [llvm-commits] [llvm] r117939 - in /llvm/trunk/test/MC/ARM: neon-table-encoding.ll neon-table-encoding.s Message-ID: <20101101183039.55EDC2A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 13:30:39 2010 New Revision: 117939 URL: http://llvm.org/viewvc/llvm-project?rev=117939&view=rev Log: Covert this test to .s form. Added: llvm/trunk/test/MC/ARM/neon-table-encoding.s Removed: llvm/trunk/test/MC/ARM/neon-table-encoding.ll Removed: llvm/trunk/test/MC/ARM/neon-table-encoding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-table-encoding.ll?rev=117938&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-table-encoding.ll (original) +++ llvm/trunk/test/MC/ARM/neon-table-encoding.ll (removed) @@ -1,103 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -; XFAIL: * - -%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } -%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } -%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } - -define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B -; CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] - %tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i8> %tmp3 -} - -define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x2_t* %B - %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 - %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 -; CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] - %tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4) - ret <8 x i8> %tmp5 -} - -define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x3_t* %B - %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0 - %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1 - %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2 -; CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] - %tmp6 = call <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5) - ret <8 x i8> %tmp6 -} - -define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x4_t* %B - %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 - %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 - %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 - %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3 -; CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3] - %tmp7 = call <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6) - ret <8 x i8> %tmp7 -} - -define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C -; CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3] - %tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i8> %tmp4 -} - -define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x2_t* %B - %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 - %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 - %tmp5 = load <8 x i8>* %C -; CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3] - %tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5) - ret <8 x i8> %tmp6 -} - -define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x3_t* %B - %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0 - %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1 - %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2 - %tmp6 = load <8 x i8>* %C -; CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3] - %tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6) - ret <8 x i8> %tmp7 -} - -define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x4_t* %B - %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 - %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 - %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 - %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3 - %tmp7 = load <8 x i8>* %C -; CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3] - %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7) - ret <8 x i8> %tmp8 -} - -declare <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8>, <8 x i8>) nounwind readnone -declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone - -declare <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone Added: llvm/trunk/test/MC/ARM/neon-table-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-table-encoding.s?rev=117939&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-table-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-table-encoding.s Mon Nov 1 13:30:39 2010 @@ -0,0 +1,19 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] + vtbl.8 d16, {d17}, d16 +@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] + vtbl.8 d16, {d16, d17}, d18 +@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] + vtbl.8 d16, {d16, d17, d18}, d20 +@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3] + vtbl.8 d16, {d16, d17, d18, d19}, d20 +@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3] + vtbx.8 d18, {d16}, d17 +@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3] + vtbx.8 d19, {d16, d17}, d18 +@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3] + vtbx.8 d20, {d16, d17, d18}, d21 +@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3] + vtbx.8 d20, {d16, d17, d18, d19}, d21 From bob.wilson at apple.com Mon Nov 1 13:31:39 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 01 Nov 2010 18:31:39 -0000 Subject: [llvm-commits] [llvm] r117940 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vmov.ll Message-ID: <20101101183139.C60F92A6C12C@llvm.org> Author: bwilson Date: Mon Nov 1 13:31:39 2010 New Revision: 117940 URL: http://llvm.org/viewvc/llvm-project?rev=117940&view=rev Log: NEON does not support truncating vector stores. Radar 8598391. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/vmov.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=117940&r1=117939&r2=117940&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 1 13:31:39 2010 @@ -104,6 +104,10 @@ setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); + for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) + setTruncStoreAction(VT.getSimpleVT(), + (MVT::SimpleValueType)InnerVT, Expand); } setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=117940&r1=117939&r2=117940&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmov.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmov.ll Mon Nov 1 13:31:39 2010 @@ -343,3 +343,13 @@ declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone + +; Truncating vector stores are not supported. The following should not crash. +; Radar 8598391. +define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind { +;CHECK: vmovn + %tmp1 = load <4 x i32>* %a, align 16 + %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> + store <4 x i16> %tmp2, <4 x i16>* %b, align 8 + ret void +} From resistor at mac.com Mon Nov 1 13:33:37 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 18:33:37 -0000 Subject: [llvm-commits] [llvm] r117941 - in /llvm/trunk/test/MC/ARM: neon-abs-encoding.s neon-absdiff-encoding.s neon-add-encoding.s neon-bitcount-encoding.s neon-bitwise-encoding.s neon-cmp-encoding.s neon-convert-encoding.s neon-dup-encoding.s neon-minmax-encoding.s neon-mov-encoding.s neon-mul-accum-encoding.s neon-mul-encoding.s neon-neg-encoding.s neon-pairwise-encoding.s neon-reciprocal-encoding.s neon-reverse-encoding.s neon-satshift-encoding.s neon-shift-encoding.s Message-ID: <20101101183337.9F0662A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 13:33:37 2010 New Revision: 117941 URL: http://llvm.org/viewvc/llvm-project?rev=117941&view=rev Log: Use ARM-style comment syntax. Modified: llvm/trunk/test/MC/ARM/neon-abs-encoding.s llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s llvm/trunk/test/MC/ARM/neon-add-encoding.s llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s llvm/trunk/test/MC/ARM/neon-cmp-encoding.s llvm/trunk/test/MC/ARM/neon-convert-encoding.s llvm/trunk/test/MC/ARM/neon-dup-encoding.s llvm/trunk/test/MC/ARM/neon-minmax-encoding.s llvm/trunk/test/MC/ARM/neon-mov-encoding.s llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s llvm/trunk/test/MC/ARM/neon-mul-encoding.s llvm/trunk/test/MC/ARM/neon-neg-encoding.s llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s llvm/trunk/test/MC/ARM/neon-reverse-encoding.s llvm/trunk/test/MC/ARM/neon-satshift-encoding.s llvm/trunk/test/MC/ARM/neon-shift-encoding.s Modified: llvm/trunk/test/MC/ARM/neon-abs-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-abs-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-abs-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-abs-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,31 +1,31 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3] +@ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3] vabs.s8 d16, d16 -// CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xf3] +@ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xf3] vabs.s16 d16, d16 -// CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3] +@ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xf3] vabs.s32 d16, d16 -// CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3] +@ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xf3] vabs.f32 d16, d16 -// CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xf3] +@ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xf3] vabs.s8 q8, q8 -// CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xf3] +@ CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xf3] vabs.s16 q8, q8 -// CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xf3] +@ CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xf3] vabs.s32 q8, q8 -// CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xf3] +@ CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xf3] vabs.f32 q8, q8 -// CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xf3] +@ CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xf3] vqabs.s8 d16, d16 -// CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xf3] +@ CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xf3] vqabs.s16 d16, d16 -// CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xf3] +@ CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xf3] vqabs.s32 d16, d16 -// CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xf3] +@ CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xf3] vqabs.s8 q8, q8 -// CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xf3] +@ CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xf3] vqabs.s16 q8, q8 -// CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xf3] +@ CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xf3] vqabs.s32 q8, q8 Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,84 +1,84 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * -// NOTE: This currently fails because the ASM parser doesn't parse vabal. +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * +@ NOTE: This currently fails because the ASM parser doesn't parse vabal. -// CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf2] +@ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf2] vabd.s8 d16, d16, d17 -// CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf2] +@ CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf2] vabd.s16 d16, d16, d17 -// CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf2] +@ CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf2] vabd.s32 d16, d16, d17 -// CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf3] +@ CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf3] vabd.u8 d16, d16, d17 -// CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf3] +@ CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xf3] vabd.u16 d16, d16, d17 - // CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf3] + @ CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xf3] vabd.u32 d16, d16, d17 -// CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf3] +@ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf3] vabd.f32 d16, d16, d17 -// CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf2] +@ CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf2] vabd.s8 q8, q8, q9 -// CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf2] +@ CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf2] vabd.s16 q8, q8, q9 -// CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf2] +@ CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf2] vabd.s32 q8, q8, q9 -// CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf3] +@ CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xf3] vabd.u8 q8, q8, q9 -// CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf3] +@ CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xf3] vabd.u16 q8, q8, q9 -// CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf3] +@ CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xf3] vabd.u32 q8, q8, q9 -// CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf3] +@ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf3] vabd.f32 q8, q8, q9 -// CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf2] +@ CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf2] vabdl.s8 q8, d16, d17 -// CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf2] +@ CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf2] vabdl.s16 q8, d16, d17 -// CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf2] +@ CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf2] vabdl.s32 q8, d16, d17 -// CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf3] +@ CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xf3] vabdl.u8 q8, d16, d17 -// CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf3] +@ CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xf3] vabdl.u16 q8, d16, d17 -// CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf3] +@ CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xf3] vabdl.u32 q8, d16, d17 -// CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf2] +@ CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf2] vaba.s8 d16, d18, d17 -// CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf2] +@ CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf2] vaba.s16 d16, d18, d17 -// CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf2] +@ CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf2] vaba.s32 d16, d18, d17 -// CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf3] +@ CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xf3] vaba.u8 d16, d18, d17 -// CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf3] +@ CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xf3] vaba.u16 d16, d18, d17 -// CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf3] +@ CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xf3] vaba.u32 d16, d18, d17 -// CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf2] +@ CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf2] vaba.s8 q9, q8, q10 -// CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf2] +@ CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf2] vaba.s16 q9, q8, q10 -// CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf2] +@ CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf2] vaba.s32 q9, q8, q10 -// CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf3] +@ CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xf3] vaba.u8 q9, q8, q10 -// CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf3] +@ CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xf3] vaba.u16 q9, q8, q10 -// CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf3] +@ CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xf3] vaba.u32 q9, q8, q10 -// CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf2] +@ CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf2] vabal.s8 q8, d19, d18 -// CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf2] +@ CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf2] vabal.s16 q8, d19, d18 -// CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf2] +@ CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf2] vabal.s32 q8, d19, d18 -// CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf3] +@ CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xf3] vabal.u8 q8, d19, d18 -// CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf3] +@ CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xf3] vabal.u16 q8, d19, d18 -// CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf3] +@ CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xf3] vabal.u32 q8, d19, d18 Modified: llvm/trunk/test/MC/ARM/neon-add-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-add-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-add-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-add-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,137 +1,137 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s -// CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2] +@ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2] vadd.i8 d16, d17, d16 -// CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf2] +@ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf2] vadd.i16 d16, d17, d16 -// CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2] +@ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2] vadd.i64 d16, d17, d16 -// CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf2] +@ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf2] vadd.i32 d16, d17, d16 -// CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf2] +@ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf2] vadd.f32 d16, d16, d17 -// CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xf2] +@ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xf2] vadd.f32 q8, q8, q9 -// CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf2] +@ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf2] vaddl.s8 q8, d17, d16 -// CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf2] +@ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf2] vaddl.s16 q8, d17, d16 -// CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf2] +@ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf2] vaddl.s32 q8, d17, d16 -// CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf3] +@ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf3] vaddl.u8 q8, d17, d16 -// CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf3] +@ CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf3] vaddl.u16 q8, d17, d16 -// CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf3] +@ CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf3] vaddl.u32 q8, d17, d16 -// CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xf2] +@ CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xf2] vaddw.s8 q8, q8, d18 -// CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xf2] +@ CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xf2] vaddw.s16 q8, q8, d18 -// CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xf2] +@ CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xf2] vaddw.s32 q8, q8, d18 -// CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xf3] +@ CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xf3] vaddw.u8 q8, q8, d18 -// CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xf3] +@ CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xf3] vaddw.u16 q8, q8, d18 -// CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xf3] +@ CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xf3] vaddw.u32 q8, q8, d18 -// CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xf2] +@ CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xf2] vhadd.s8 d16, d16, d17 -// CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xf2] +@ CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xf2] vhadd.s16 d16, d16, d17 -// CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xf2] +@ CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xf2] vhadd.s32 d16, d16, d17 -// CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xf3] +@ CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xf3] vhadd.u8 d16, d16, d17 -// CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xf3] +@ CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xf3] vhadd.u16 d16, d16, d17 -// CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xf3] +@ CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xf3] vhadd.u32 d16, d16, d17 -// CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xf2] +@ CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xf2] vhadd.s8 q8, q8, q9 -// CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xf2] +@ CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xf2] vhadd.s16 q8, q8, q9 -// CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf2] +@ CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf2] vhadd.s32 q8, q8, q9 - // CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xf3] + @ CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xf3] vhadd.u8 q8, q8, q9 -// CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xf3] +@ CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xf3] vhadd.u16 q8, q8, q9 -// CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3] +@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3] vhadd.u32 q8, q8, q9 -// CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2] +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2] vrhadd.s8 d16, d16, d17 -// CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2] +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2] vrhadd.s16 d16, d16, d17 -// CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2] +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2] vrhadd.s32 d16, d16, d17 -// CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3] +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3] vrhadd.u8 d16, d16, d17 -// CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3] +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3] vrhadd.u16 d16, d16, d17 -// CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3] +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3] vrhadd.u32 d16, d16, d17 -// CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2] +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2] vrhadd.s8 q8, q8, q9 -// CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2] +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2] vrhadd.s16 q8, q8, q9 -// CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2] +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2] vrhadd.s32 q8, q8, q9 -// CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3] +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3] vrhadd.u8 q8, q8, q9 -// CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3] +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3] vrhadd.u16 q8, q8, q9 -// CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3] vrhadd.u32 q8, q8, q9 -// CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf2] +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf2] vqadd.s8 d16, d16, d17 -// CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf2] +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf2] vqadd.s16 d16, d16, d17 -// CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf2] +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf2] vqadd.s32 d16, d16, d17 -// CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf2] +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf2] vqadd.s64 d16, d16, d17 -// CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf3] +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xf3] vqadd.u8 d16, d16, d17 -// CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf3] +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xf3] vqadd.u16 d16, d16, d17 -// CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf3] +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xf3] vqadd.u32 d16, d16, d17 -// CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf3] +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xf3] vqadd.u64 d16, d16, d17 -// CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf2] +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf2] vqadd.s8 q8, q8, q9 -// CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf2] +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf2] vqadd.s16 q8, q8, q9 -// CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf2] +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf2] vqadd.s32 q8, q8, q9 -// CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf2] +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf2] vqadd.s64 q8, q8, q9 -// CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf3] +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xf3] vqadd.u8 q8, q8, q9 -// CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf3] +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xf3] vqadd.u16 q8, q8, q9 -// CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf3] +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xf3] vqadd.u32 q8, q8, q9 -// CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf3] +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xf3] vqadd.u64 q8, q8, q9 -// CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2] +@ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2] vaddhn.i16 d16, q8, q9 -// CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2] +@ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2] vaddhn.i32 d16, q8, q9 -// CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2] +@ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2] vaddhn.i64 d16, q8, q9 -// CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf3] +@ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf3] vraddhn.i16 d16, q8, q9 -// CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf3] +@ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf3] vraddhn.i32 d16, q8, q9 -// CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3] +@ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3] vraddhn.i64 d16, q8, q9 Modified: llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,32 +1,32 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * -// CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] +@ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] vcnt.8 d16, d16 -// CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3] +@ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3] vcnt.8 q8, q8 -// CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3] +@ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3] vclz.i8 d16, d16 -// CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3] +@ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3] vclz.i16 d16, d16 -// CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3] +@ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3] vclz.i32 d16, d16 -// CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3] +@ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3] vclz.i8 q8, q8 -// CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3] +@ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3] vclz.i16 q8, q8 -// CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xf3] +@ CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xf3] vclz.i32 q8, q8 -// CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3] +@ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3] vcls.s8 d16, d16 -// CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3] +@ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3] vcls.s16 d16, d16 -// CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3] +@ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3] vcls.s32 d16, d16 -// CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3] +@ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3] vcls.s8 q8, q8 -// CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3] +@ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3] vcls.s16 q8, q8 -// CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xf3] +@ CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xf3] vcls.s32 q8, q8 Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,36 +1,36 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] +@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] vand d16, d17, d16 -// CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2] +@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2] vand q8, q8, q9 -// CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3] +@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3] veor d16, d17, d16 -// CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3] +@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3] veor q8, q8, q9 -// CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2] +@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2] vorr d16, d17, d16 -// CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] +@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] vorr q8, q8, q9 -// CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] +@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] vbic d16, d17, d16 -// CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] +@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] vbic q8, q8, q9 -// CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] +@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] vorn d16, d17, d16 -// CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xf2] +@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xf2] vorn q8, q8, q9 -// CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xf3] +@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xf3] vmvn d16, d16 -// CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xf3] +@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xf3] vmvn q8, q8 -// CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3] +@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3] vbsl d18, d17, d16 -// CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3] +@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3] vbsl q8, q10, q9 Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-cmp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,104 +1,104 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * -// FIXME: We cannot currently test the following instructions, which are -// currently marked as for-disassembly only in the .td files: -// - VCEQz -// - VCGEz, VCLEz -// - VCGTz, VCLTz +@ FIXME: We cannot currently test the following instructions, which are +@ currently marked as for-disassembly only in the .td files: +@ - VCEQz +@ - VCGEz, VCLEz +@ - VCGTz, VCLTz -// CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3] +@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3] vceq.i8 d16, d16, d17 -// CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3] +@ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3] vceq.i16 d16, d16, d17 -// CHECK: vceq.i32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf3] +@ CHECK: vceq.i32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf3] vceq.i32 d16, d16, d17 -// CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2] +@ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2] vceq.f32 d16, d16, d17 -// CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3] +@ CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3] vceq.i8 q8, q8, q9 -// CHECK: vceq.i16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf3] +@ CHECK: vceq.i16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf3] vceq.i16 q8, q8, q9 -// CHECK: vceq.i32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf3] +@ CHECK: vceq.i32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf3] vceq.i32 q8, q8, q9 -// CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2] +@ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2] vceq.f32 q8, q8, q9 -// CHECK: vcge.s8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf2] +@ CHECK: vcge.s8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf2] vcge.s8 d16, d16, d17 -// CHECK: vcge.s16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf2] +@ CHECK: vcge.s16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf2] vcge.s16 d16, d16, d17 -// CHECK: vcge.s32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf2] +@ CHECK: vcge.s32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf2] vcge.s32 d16, d16, d17 -// CHECK: vcge.u8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf3] +@ CHECK: vcge.u8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf3] vcge.u8 d16, d16, d17 -// CHECK: vcge.u16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf3] +@ CHECK: vcge.u16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf3] vcge.u16 d16, d16, d17 -// CHECK: vcge.u32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf3] +@ CHECK: vcge.u32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf3] vcge.u32 d16, d16, d17 -// CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3] +@ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3] vcge.f32 d16, d16, d17 -// CHECK: vcge.s8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf2] +@ CHECK: vcge.s8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf2] vcge.s8 q8, q8, q9 -// CHECK: vcge.s16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf2] +@ CHECK: vcge.s16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf2] vcge.s16 q8, q8, q9 -// CHECK: vcge.s32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf2] +@ CHECK: vcge.s32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf2] vcge.s32 q8, q8, q9 -// CHECK: vcge.u8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf3] +@ CHECK: vcge.u8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf3] vcge.u8 q8, q8, q9 -// CHECK: vcge.u16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf3] +@ CHECK: vcge.u16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf3] vcge.u16 q8, q8, q9 -// CHECK: vcge.u32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf3] +@ CHECK: vcge.u32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf3] vcge.u32 q8, q8, q9 -// CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3] +@ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3] vcge.f32 q8, q8, q9 -// CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3] +@ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3] vacge.f32 d16, d16, d17 -// CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3] +@ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3] vacge.f32 q8, q8, q9 -// CHECK: vcgt.s8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf2] +@ CHECK: vcgt.s8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf2] vcgt.s8 d16, d16, d17 -// CHECK: vcgt.s16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf2] +@ CHECK: vcgt.s16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf2] vcgt.s16 d16, d16, d17 -// CHECK: vcgt.s32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf2] +@ CHECK: vcgt.s32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf2] vcgt.s32 d16, d16, d17 -// CHECK: vcgt.u8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf3] +@ CHECK: vcgt.u8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf3] vcgt.u8 d16, d16, d17 -// CHECK: vcgt.u16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf3] +@ CHECK: vcgt.u16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf3] vcgt.u16 d16, d16, d17 -// CHECK: vcgt.u32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf3] +@ CHECK: vcgt.u32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf3] vcgt.u32 d16, d16, d17 -// CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3] +@ CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3] vcgt.f32 d16, d16, d17 -// CHECK: vcgt.s8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf2] +@ CHECK: vcgt.s8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf2] vcgt.s8 q8, q8, q9 -// CHECK: vcgt.s16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf2] +@ CHECK: vcgt.s16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf2] vcgt.s16 q8, q8, q9 -// CHECK: vcgt.s32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf2] +@ CHECK: vcgt.s32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf2] vcgt.s32 q8, q8, q9 -// CHECK: vcgt.u8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf3] +@ CHECK: vcgt.u8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf3] vcgt.u8 q8, q8, q9 -// CHECK: vcgt.u16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf3] +@ CHECK: vcgt.u16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf3] vcgt.u16 q8, q8, q9 -// CHECK: vcgt.u32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf3] +@ CHECK: vcgt.u32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf3] vcgt.u32 q8, q8, q9 -// CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3] +@ CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3] vcgt.f32 q8, q8, q9 -// CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3] +@ CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3] vacgt.f32 d16, d16, d17 -// CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3] +@ CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3] vacgt.f32 q8, q8, q9 -// CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2] +@ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2] vtst.8 d16, d16, d17 -// CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2] +@ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2] vtst.16 d16, d16, d17 -// CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2] +@ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2] vtst.32 d16, d16, d17 -// CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2] +@ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2] vtst.8 q8, q8, q9 -// CHECK: vtst.16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf2] +@ CHECK: vtst.16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf2] vtst.16 q8, q8, q9 -// CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] +@ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] vtst.32 q8, q8, q9 Modified: llvm/trunk/test/MC/ARM/neon-convert-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-convert-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-convert-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-convert-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,34 +1,34 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3] +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3] vcvt.s32.f32 d16, d16 -// CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3] +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3] vcvt.u32.f32 d16, d16 -// CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3] +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3] vcvt.f32.s32 d16, d16 -// CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3] +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3] vcvt.f32.u32 d16, d16 -// CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3] +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3] vcvt.s32.f32 q8, q8 -// CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3] +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3] vcvt.u32.f32 q8, q8 -// CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3] +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3] vcvt.f32.s32 q8, q8 -// CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3] +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3] vcvt.f32.u32 q8, q8 -// CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2] +@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2] vcvt.s32.f32 d16, d16, #1 -// CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3] +@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3] vcvt.u32.f32 d16, d16, #1 -// CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2] +@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2] vcvt.f32.s32 d16, d16, #1 -// CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3] +@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3] vcvt.f32.u32 d16, d16, #1 -// CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2] +@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2] vcvt.s32.f32 q8, q8, #1 -// CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3] +@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3] vcvt.u32.f32 q8, q8, #1 -// CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2] +@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2] vcvt.f32.s32 q8, q8, #1 -// CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3] +@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3] vcvt.f32.u32 q8, q8, #1 Modified: llvm/trunk/test/MC/ARM/neon-dup-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-dup-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-dup-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-dup-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,27 +1,27 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * -// CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] +@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] vdup.8 d16, r0 -// CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] +@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] vdup.16 d16, r0 -// CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] +@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] vdup.32 d16, r0 -// CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] +@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] vdup.8 q8, r0 -// CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] +@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] vdup.16 q8, r0 -// CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] +@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] vdup.32 q8, r0 -// CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xf3] +@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xf3] vdup.8 d16, d16[1] -// CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xf3] +@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xf3] vdup.16 d16, d16[1] -// CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xf3] +@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xf3] vdup.32 d16, d16[1] -// CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xf3] +@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xf3] vdup.8 q8, d16[1] -// CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xf3] +@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xf3] vdup.16 q8, d16[1] -// CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xf3] +@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xf3] vdup.32 q8, d16[1] Modified: llvm/trunk/test/MC/ARM/neon-minmax-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-minmax-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-minmax-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-minmax-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,58 +1,58 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2] +@ CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2] vmin.s8 d16, d16, d17 -// CHECK: vmin.s16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf2] +@ CHECK: vmin.s16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf2] vmin.s16 d16, d16, d17 -// CHECK: vmin.s32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf2] +@ CHECK: vmin.s32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf2] vmin.s32 d16, d16, d17 -// CHECK: vmin.u8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf3] +@ CHECK: vmin.u8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf3] vmin.u8 d16, d16, d17 -// CHECK: vmin.u16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf3] +@ CHECK: vmin.u16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xf3] vmin.u16 d16, d16, d17 -// CHECK: vmin.u32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf3] +@ CHECK: vmin.u32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xf3] vmin.u32 d16, d16, d17 -// CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf2] +@ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf2] vmin.f32 d16, d16, d17 -// CHECK: vmin.s8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf2] +@ CHECK: vmin.s8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf2] vmin.s8 q8, q8, q9 -// CHECK: vmin.s16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf2] +@ CHECK: vmin.s16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf2] vmin.s16 q8, q8, q9 -// CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf2] +@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf2] vmin.s32 q8, q8, q9 -// CHECK: vmin.u8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf3] +@ CHECK: vmin.u8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xf3] vmin.u8 q8, q8, q9 -// CHECK: vmin.u16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf3] +@ CHECK: vmin.u16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xf3] vmin.u16 q8, q8, q9 -// CHECK: vmin.u32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf3] +@ CHECK: vmin.u32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xf3] vmin.u32 q8, q8, q9 -// CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xf2] +@ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xf2] vmin.f32 q8, q8, q9 -// CHECK: vmax.s8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf2] +@ CHECK: vmax.s8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf2] vmax.s8 d16, d16, d17 -// CHECK: vmax.s16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf2] +@ CHECK: vmax.s16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf2] vmax.s16 d16, d16, d17 -// CHECK: vmax.s32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf2] +@ CHECK: vmax.s32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf2] vmax.s32 d16, d16, d17 -// CHECK: vmax.u8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf3] +@ CHECK: vmax.u8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xf3] vmax.u8 d16, d16, d17 -// CHECK: vmax.u16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf3] +@ CHECK: vmax.u16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xf3] vmax.u16 d16, d16, d17 -// CHECK: vmax.u32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf3] +@ CHECK: vmax.u32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xf3] vmax.u32 d16, d16, d17 -// CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf2] +@ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf2] vmax.f32 d16, d16, d17 -// CHECK: vmax.s8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf2] +@ CHECK: vmax.s8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf2] vmax.s8 q8, q8, q9 -// CHECK: vmax.s16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf2] +@ CHECK: vmax.s16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf2] vmax.s16 q8, q8, q9 -// CHECK: vmax.s32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf2] +@ CHECK: vmax.s32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf2] vmax.s32 q8, q8, q9 -// CHECK: vmax.u8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf3] +@ CHECK: vmax.u8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xf3] vmax.u8 q8, q8, q9 -// CHECK: vmax.u16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf3] +@ CHECK: vmax.u16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xf3] vmax.u16 q8, q8, q9 -// CHECK: vmax.u32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf3] +@ CHECK: vmax.u32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xf3] vmax.u32 q8, q8, q9 -// CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xf2] +@ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xf2] vmax.f32 q8, q8, q9 Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,117 +1,117 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * -// CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] vmov.i8 d16, #0x8 -// CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] vmov.i16 d16, #0x10 -// CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] vmov.i16 d16, #0x1000 -// CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] vmov.i32 d16, #0x20 -// CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] vmov.i32 d16, #0x2000 -// CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] vmov.i32 d16, #0x200000 -// CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] vmov.i32 d16, #0x20000000 -// CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] vmov.i32 d16, #0x20FF -// CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] vmov.i32 d16, #0x20FFFF -// CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] vmov.i64 d16, #0xFF0000FF0000FFFF -// CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] vmov.i8 q8, #0x8 -// CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] vmov.i16 q8, #0x10 -// CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] vmov.i16 q8, #0x1000 -// CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] vmov.i32 q8, #0x20 -// CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] vmov.i32 q8, #0x2000 -// CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] vmov.i32 q8, #0x200000 -// CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] vmov.i32 q8, #0x20000000 -// CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] vmov.i32 q8, #0x20FF -// CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] vmov.i32 q8, #0x20FFFF -// CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] vmov.i64 q8, #0xFF0000FF0000FFFF -// CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] vmvn.i16 d16, #0x10 -// CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] vmvn.i16 d16, #0x1000 -// CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] vmvn.i32 d16, #0x20 -// CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] vmvn.i32 d16, #0x2000 -// CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] vmvn.i32 d16, #0x200000 -// CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] vmvn.i32 d16, #0x20000000 -// CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] vmvn.i32 d16, #0x20FF -// CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] vmvn.i32 d16, #0x20FFFF -// CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2] +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2] vmovl.s8 q8, d16 -// CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2] +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2] vmovl.s16 q8, d16 -// CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2] +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2] vmovl.s32 q8, d16 -// CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3] +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3] vmovl.u8 q8, d16 -// CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3] +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3] vmovl.u16 q8, d16 -// CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3] +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3] vmovl.u32 q8, d16 -// CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3] +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3] vmovn.i16 d16, q8 -// CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3] +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3] vmovn.i32 d16, q8 -// CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3] +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3] vmovn.i64 d16, q8 -// CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3] +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3] vqmovn.s16 d16, q8 -// CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3] +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3] vqmovn.s32 d16, q8 -// CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3] +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3] vqmovn.s64 d16, q8 -// CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3] +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3] vqmovn.u16 d16, q8 -// CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3] +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3] vqmovn.u32 d16, q8 -// CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3] +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3] vqmovn.u64 d16, q8 -// CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3] +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3] vqmovun.s16 d16, q8 -// CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] vqmovun.s32 d16, q8 -// CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] vqmovun.s64 d16, q8 -// CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] vmov.s8 r0, d16[1] -// CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] vmov.s16 r0, d16[1] -// CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] vmov.u8 r0, d16[1] -// CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] vmov.u16 r0, d16[1] -// CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] vmov.32 r0, d16[1] -// CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] vmov.8 d16[1], r1 -// CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] vmov.16 d16[1], r1 -// CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] vmov.32 d16[1], r1 -// CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] vmov.8 d18[1], r1 -// CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] vmov.16 d18[1], r1 -// CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] vmov.32 d18[1], r1 Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,67 +1,67 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * -// CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] vmla.i8 d16, d18, d17 -// CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] vmla.i16 d16, d18, d17 -// CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] vmla.i32 d16, d18, d17 -// CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] vmla.f32 d16, d18, d17 -// CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] vmla.i8 q9, q8, q10 -// CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] vmla.i16 q9, q8, q10 -// CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] vmla.i32 q9, q8, q10 -// CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] vmla.f32 q9, q8, q10 -// CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] vmlal.s8 q8, d19, d18 -// CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] vmlal.s16 q8, d19, d18 -// CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] vmlal.s32 q8, d19, d18 -// CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] vmlal.u8 q8, d19, d18 -// CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] vmlal.u16 q8, d19, d18 -// CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] vmlal.u32 q8, d19, d18 -// CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] vqdmlal.s16 q8, d19, d18 -// CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] vqdmlal.s32 q8, d19, d18 -// CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] vmls.i8 d16, d18, d17 -// CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] vmls.i16 d16, d18, d17 -// CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] vmls.i32 d16, d18, d17 -// CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] vmls.f32 d16, d18, d17 -// CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] vmls.i8 q9, q8, q10 -// CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] vmls.i16 q9, q8, q10 -// CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] vmls.i32 q9, q8, q10 -// CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] vmls.f32 q9, q8, q10 -// CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] vmlsl.s8 q8, d19, d18 -// CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] vmlsl.s16 q8, d19, d18 -// CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] vmlsl.s32 q8, d19, d18 -// CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] vmlsl.u8 q8, d19, d18 -// CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] vmlsl.u16 q8, d19, d18 -// CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] vmlsl.u32 q8, d19, d18 -// CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] vqdmlsl.s16 q8, d19, d18 -// CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] vqdmlsl.s32 q8, d19, d18 Modified: llvm/trunk/test/MC/ARM/neon-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,56 +1,56 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] vmul.i8 d16, d16, d17 -// CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] vmul.i16 d16, d16, d17 -// CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] vmul.i32 d16, d16, d17 -// CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] vmul.f32 d16, d16, d17 -// CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] vmul.i8 q8, q8, q9 -// CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] vmul.i16 q8, q8, q9 -// CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] vmul.i32 q8, q8, q9 -// CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] vmul.f32 q8, q8, q9 -// CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] vmul.p8 d16, d16, d17 -// CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] vmul.p8 q8, q8, q9 -// CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] vqdmulh.s16 d16, d16, d17 -// CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] vqdmulh.s32 d16, d16, d17 -// CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] vqdmulh.s16 q8, q8, q9 -// CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] vqdmulh.s32 q8, q8, q9 -// CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3] +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3] vqrdmulh.s16 d16, d16, d17 -// CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3] +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3] vqrdmulh.s32 d16, d16, d17 -// CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3] +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3] vqrdmulh.s16 q8, q8, q9 -// CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3] +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3] vqrdmulh.s32 q8, q8, q9 -// CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf2] +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf2] vmull.s8 q8, d16, d17 -// CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf2] +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf2] vmull.s16 q8, d16, d17 -// CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf2] +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf2] vmull.s32 q8, d16, d17 -// CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf3] +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf3] vmull.u8 q8, d16, d17 -// CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf3] +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf3] vmull.u16 q8, d16, d17 -// CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf3] +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf3] vmull.u32 q8, d16, d17 -// CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xf2] +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xf2] vmull.p8 q8, d16, d17 -// CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] vqdmull.s16 q8, d16, d17 -// CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] vqdmull.s32 q8, d16, d17 Modified: llvm/trunk/test/MC/ARM/neon-neg-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-neg-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-neg-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-neg-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,30 +1,30 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] +@ CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] vneg.s8 d16, d16 -// CHECK: vneg.s16 d16, d16 @ encoding: [0xa0,0x03,0xf5,0xf3] +@ CHECK: vneg.s16 d16, d16 @ encoding: [0xa0,0x03,0xf5,0xf3] vneg.s16 d16, d16 -// CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xf3] +@ CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xf3] vneg.s32 d16, d16 -// CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xf3] +@ CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xf3] vneg.f32 d16, d16 -// CHECK: vneg.s8 q8, q8 @ encoding: [0xe0,0x03,0xf1,0xf3] +@ CHECK: vneg.s8 q8, q8 @ encoding: [0xe0,0x03,0xf1,0xf3] vneg.s8 q8, q8 -// CHECK: vneg.s16 q8, q8 @ encoding: [0xe0,0x03,0xf5,0xf3] +@ CHECK: vneg.s16 q8, q8 @ encoding: [0xe0,0x03,0xf5,0xf3] vneg.s16 q8, q8 -// CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xf3] +@ CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xf3] vneg.s32 q8, q8 -// CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xf3] +@ CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xf3] vneg.f32 q8, q8 -// CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3] +@ CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3] vqneg.s8 d16, d16 -// CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3] +@ CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3] vqneg.s16 d16, d16 -// CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3] +@ CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3] vqneg.s32 d16, d16 -// CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3] +@ CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3] vqneg.s8 q8, q8 -// CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3] +@ CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3] vqneg.s16 q8, q8 -// CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xf3] +@ CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xf3] vqneg.s32 q8, q8 Modified: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,87 +1,87 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// XFAIL: * +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * -// CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2] +@ CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2] vpadd.i8 d16, d17, d16 -// CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xf2] +@ CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xf2] vpadd.i16 d16, d17, d16 -// CHECK: vpadd.i32 d16, d17, d16 @ encoding: [0xb0,0x0b,0x61,0xf2] +@ CHECK: vpadd.i32 d16, d17, d16 @ encoding: [0xb0,0x0b,0x61,0xf2] vpadd.i32 d16, d17, d16 -// CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] +@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] vpadd.f32 d16, d16, d17 -// CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xf3] +@ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xf3] vpaddl.s8 d16, d16 -// CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xf3] +@ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xf3] vpaddl.s16 d16, d16 -// CHECK: vpaddl.s32 d16, d16 @ encoding: [0x20,0x02,0xf8,0xf3] +@ CHECK: vpaddl.s32 d16, d16 @ encoding: [0x20,0x02,0xf8,0xf3] vpaddl.s32 d16, d16 -// CHECK: vpaddl.u8 d16, d16 @ encoding: [0xa0,0x02,0xf0,0xf3] +@ CHECK: vpaddl.u8 d16, d16 @ encoding: [0xa0,0x02,0xf0,0xf3] vpaddl.u8 d16, d16 -// CHECK: vpaddl.u16 d16, d16 @ encoding: [0xa0,0x02,0xf4,0xf3] +@ CHECK: vpaddl.u16 d16, d16 @ encoding: [0xa0,0x02,0xf4,0xf3] vpaddl.u16 d16, d16 -// CHECK: vpaddl.u32 d16, d16 @ encoding: [0xa0,0x02,0xf8,0xf3] +@ CHECK: vpaddl.u32 d16, d16 @ encoding: [0xa0,0x02,0xf8,0xf3] vpaddl.u32 d16, d16 -// CHECK: vpaddl.s8 q8, q8 @ encoding: [0x60,0x02,0xf0,0xf3] +@ CHECK: vpaddl.s8 q8, q8 @ encoding: [0x60,0x02,0xf0,0xf3] vpaddl.s8 q8, q8 -// CHECK: vpaddl.s16 q8, q8 @ encoding: [0x60,0x02,0xf4,0xf3] +@ CHECK: vpaddl.s16 q8, q8 @ encoding: [0x60,0x02,0xf4,0xf3] vpaddl.s16 q8, q8 -// CHECK: vpaddl.s32 q8, q8 @ encoding: [0x60,0x02,0xf8,0xf3] +@ CHECK: vpaddl.s32 q8, q8 @ encoding: [0x60,0x02,0xf8,0xf3] vpaddl.s32 q8, q8 -// CHECK: vpaddl.u8 q8, q8 @ encoding: [0xe0,0x02,0xf0,0xf3] +@ CHECK: vpaddl.u8 q8, q8 @ encoding: [0xe0,0x02,0xf0,0xf3] vpaddl.u8 q8, q8 -// CHECK: vpaddl.u16 q8, q8 @ encoding: [0xe0,0x02,0xf4,0xf3] +@ CHECK: vpaddl.u16 q8, q8 @ encoding: [0xe0,0x02,0xf4,0xf3] vpaddl.u16 q8, q8 -// CHECK: vpaddl.u32 q8, q8 @ encoding: [0xe0,0x02,0xf8,0xf3] +@ CHECK: vpaddl.u32 q8, q8 @ encoding: [0xe0,0x02,0xf8,0xf3] vpaddl.u32 q8, q8 -// CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xf3] +@ CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xf3] vpadal.s8 d16, d17 -// CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xf3] +@ CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xf3] vpadal.s16 d16, d17 -// CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xf3] +@ CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xf3] vpadal.s32 d16, d17 -// CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xf3] +@ CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xf3] vpadal.u8 d16, d17 -// CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xf3] +@ CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xf3] vpadal.u16 d16, d17 -// CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xf3] +@ CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xf3] vpadal.u32 d16, d17 - // CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xf3] +@ CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xf3] vpadal.s8 q9, q8 -// CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xf3] +@ CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xf3] vpadal.s16 q9, q8 -// CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xf3] +@ CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xf3] vpadal.s32 q9, q8 -// CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xf3] +@ CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xf3] vpadal.u8 q9, q8 -// CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xf3] +@ CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xf3] vpadal.u16 q9, q8 -// CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xf3] +@ CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xf3] vpadal.u32 q9, q8 -// CHECK: vpmin.s8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xf2] +@ CHECK: vpmin.s8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xf2] vpmin.s8 d16, d16, d17 -// CHECK: vpmin.s16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xf2] +@ CHECK: vpmin.s16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xf2] vpmin.s16 d16, d16, d17 -// CHECK: vpmin.s32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xf2] +@ CHECK: vpmin.s32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xf2] vpmin.s32 d16, d16, d17 -// CHECK: vpmin.u8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xf3] +@ CHECK: vpmin.u8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xf3] vpmin.u8 d16, d16, d17 -// CHECK: vpmin.u16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xf3] +@ CHECK: vpmin.u16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xf3] vpmin.u16 d16, d16, d17 -// CHECK: vpmin.u32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xf3] +@ CHECK: vpmin.u32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xf3] vpmin.u32 d16, d16, d17 -// CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf3] +@ CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf3] vpmin.f32 d16, d16, d17 -// CHECK: vpmax.s8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xf2] +@ CHECK: vpmax.s8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xf2] vpmax.s8 d16, d16, d17 -// CHECK: vpmax.s16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xf2] +@ CHECK: vpmax.s16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xf2] vpmax.s16 d16, d16, d17 -// CHECK: vpmax.s32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xf2] +@ CHECK: vpmax.s32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xf2] vpmax.s32 d16, d16, d17 -// CHECK: vpmax.u8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xf3] +@ CHECK: vpmax.u8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xf3] vpmax.u8 d16, d16, d17 -// CHECK: vpmax.u16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xf3] +@ CHECK: vpmax.u16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xf3] vpmax.u16 d16, d16, d17 -// CHECK: vpmax.u32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xf3] +@ CHECK: vpmax.u32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xf3] vpmax.u32 d16, d16, d17 -// CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf3] +@ CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf3] vpmax.f32 d16, d16, d17 Modified: llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,26 +1,26 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3] +@ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3] vrecpe.u32 d16, d16 -// CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3] +@ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3] vrecpe.u32 q8, q8 -// CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3] +@ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3] vrecpe.f32 d16, d16 -// CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3] +@ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3] vrecpe.f32 q8, q8 -// CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2] +@ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2] vrecps.f32 d16, d16, d17 -// CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2] +@ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2] vrecps.f32 q8, q8, q9 -// CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3] +@ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3] vrsqrte.u32 d16, d16 -// CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3] +@ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3] vrsqrte.u32 q8, q8 -// CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3] +@ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3] vrsqrte.f32 d16, d16 -// CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3] +@ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3] vrsqrte.f32 q8, q8 -// CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2] +@ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2] vrsqrts.f32 d16, d16, d17 -// CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2] +@ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2] vrsqrts.f32 q8, q8, q9 Modified: llvm/trunk/test/MC/ARM/neon-reverse-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reverse-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-reverse-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-reverse-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,26 +1,26 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3] +@ CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3] vrev64.8 d16, d16 -// CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xf3] +@ CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xf3] vrev64.16 d16, d16 -// CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xf3] +@ CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xf3] vrev64.32 d16, d16 -// CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xf3] +@ CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xf3] vrev64.8 q8, q8 -// CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xf3] +@ CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xf3] vrev64.16 q8, q8 -// CHECK: vrev64.32 q8, q8 @ encoding: [0x60,0x00,0xf8,0xf3] +@ CHECK: vrev64.32 q8, q8 @ encoding: [0x60,0x00,0xf8,0xf3] vrev64.32 q8, q8 -// CHECK: vrev32.8 d16, d16 @ encoding: [0xa0,0x00,0xf0,0xf3] +@ CHECK: vrev32.8 d16, d16 @ encoding: [0xa0,0x00,0xf0,0xf3] vrev32.8 d16, d16 -// CHECK: vrev32.16 d16, d16 @ encoding: [0xa0,0x00,0xf4,0xf3] +@ CHECK: vrev32.16 d16, d16 @ encoding: [0xa0,0x00,0xf4,0xf3] vrev32.16 d16, d16 -// CHECK: vrev32.8 q8, q8 @ encoding: [0xe0,0x00,0xf0,0xf3] +@ CHECK: vrev32.8 q8, q8 @ encoding: [0xe0,0x00,0xf0,0xf3] vrev32.8 q8, q8 -// CHECK: vrev32.16 q8, q8 @ encoding: [0xe0,0x00,0xf4,0xf3] +@ CHECK: vrev32.16 q8, q8 @ encoding: [0xe0,0x00,0xf4,0xf3] vrev32.16 q8, q8 -// CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3] +@ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3] vrev16.8 d16, d16 -// CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3] +@ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3] vrev16.8 q8, q8 Modified: llvm/trunk/test/MC/ARM/neon-satshift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-satshift-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-satshift-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-satshift-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,150 +1,150 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2] +@ CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2] vqshl.s8 d16, d16, d17 -// CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf2] +@ CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf2] vqshl.s16 d16, d16, d17 -// CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf2] +@ CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf2] vqshl.s32 d16, d16, d17 -// CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf2] +@ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf2] vqshl.s64 d16, d16, d17 -// CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf3] +@ CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf3] vqshl.u8 d16, d16, d17 -// CHECK: vqshl.u16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf3] +@ CHECK: vqshl.u16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xf3] vqshl.u16 d16, d16, d17 -// CHECK: vqshl.u32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf3] +@ CHECK: vqshl.u32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xf3] vqshl.u32 d16, d16, d17 -// CHECK: vqshl.u64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf3] +@ CHECK: vqshl.u64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf3] vqshl.u64 d16, d16, d17 -// CHECK: vqshl.s8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xf2] +@ CHECK: vqshl.s8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xf2] vqshl.s8 q8, q8, q9 -// CHECK: vqshl.s16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xf2] +@ CHECK: vqshl.s16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xf2] vqshl.s16 q8, q8, q9 -// CHECK: vqshl.s32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xf2] +@ CHECK: vqshl.s32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xf2] vqshl.s32 q8, q8, q9 -// CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf2] +@ CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf2] vqshl.s64 q8, q8, q9 -// CHECK: vqshl.u8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xf3] +@ CHECK: vqshl.u8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xf3] vqshl.u8 q8, q8, q9 -// CHECK: vqshl.u16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xf3] +@ CHECK: vqshl.u16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xf3] vqshl.u16 q8, q8, q9 -// CHECK: vqshl.u32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xf3] +@ CHECK: vqshl.u32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xf3] vqshl.u32 q8, q8, q9 -// CHECK: vqshl.u64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf3] +@ CHECK: vqshl.u64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf3] vqshl.u64 q8, q8, q9 -// CHECK: vqshl.s8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xf2] +@ CHECK: vqshl.s8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xf2] vqshl.s8 d16, d16, #7 -// CHECK: vqshl.s16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xf2] +@ CHECK: vqshl.s16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xf2] vqshl.s16 d16, d16, #15 -// CHECK: vqshl.s32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xf2] +@ CHECK: vqshl.s32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xf2] vqshl.s32 d16, d16, #31 -// CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf2] +@ CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf2] vqshl.s64 d16, d16, #63 -// CHECK: vqshl.u8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xf3] +@ CHECK: vqshl.u8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xf3] vqshl.u8 d16, d16, #7 -// CHECK: vqshl.u16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xf3] +@ CHECK: vqshl.u16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xf3] vqshl.u16 d16, d16, #15 -// CHECK: vqshl.u32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xf3] +@ CHECK: vqshl.u32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xf3] vqshl.u32 d16, d16, #31 -// CHECK: vqshl.u64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf3] +@ CHECK: vqshl.u64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf3] vqshl.u64 d16, d16, #63 -// CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0x30,0x06,0xcf,0xf3] +@ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0x30,0x06,0xcf,0xf3] vqshlu.s8 d16, d16, #7 -// CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0x30,0x06,0xdf,0xf3] +@ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0x30,0x06,0xdf,0xf3] vqshlu.s16 d16, d16, #15 -// CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0x30,0x06,0xff,0xf3] +@ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0x30,0x06,0xff,0xf3] vqshlu.s32 d16, d16, #31 -// CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xf3] +@ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xf3] vqshlu.s64 d16, d16, #63 -// CHECK: vqshl.s8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xf2] +@ CHECK: vqshl.s8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xf2] vqshl.s8 q8, q8, #7 -// CHECK: vqshl.s16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xf2] +@ CHECK: vqshl.s16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xf2] vqshl.s16 q8, q8, #15 -// CHECK: vqshl.s32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xf2] +@ CHECK: vqshl.s32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xf2] vqshl.s32 q8, q8, #31 -// CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf2] +@ CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf2] vqshl.s64 q8, q8, #63 -// CHECK: vqshl.u8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xf3] +@ CHECK: vqshl.u8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xf3] vqshl.u8 q8, q8, #7 -// CHECK: vqshl.u16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xf3] +@ CHECK: vqshl.u16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xf3] vqshl.u16 q8, q8, #15 -// CHECK: vqshl.u32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xf3] +@ CHECK: vqshl.u32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xf3] vqshl.u32 q8, q8, #31 -// CHECK: vqshl.u64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf3] +@ CHECK: vqshl.u64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf3] vqshl.u64 q8, q8, #63 -// CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0x70,0x06,0xcf,0xf3] +@ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0x70,0x06,0xcf,0xf3] vqshlu.s8 q8, q8, #7 -// CHECK: vqshlu.s16 q8, q8, #15 @ encoding: [0x70,0x06,0xdf,0xf3] +@ CHECK: vqshlu.s16 q8, q8, #15 @ encoding: [0x70,0x06,0xdf,0xf3] vqshlu.s16 q8, q8, #15 -// CHECK: vqshlu.s32 q8, q8, #31 @ encoding: [0x70,0x06,0xff,0xf3] +@ CHECK: vqshlu.s32 q8, q8, #31 @ encoding: [0x70,0x06,0xff,0xf3] vqshlu.s32 q8, q8, #31 -// CHECK: vqshlu.s64 q8, q8, #63 @ encoding: [0xf0,0x06,0xff,0xf3] +@ CHECK: vqshlu.s64 q8, q8, #63 @ encoding: [0xf0,0x06,0xff,0xf3] vqshlu.s64 q8, q8, #63 -// CHECK: vqrshl.s8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xf2] +@ CHECK: vqrshl.s8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xf2] vqrshl.s8 d16, d16, d17 -// CHECK: vqrshl.s16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xf2] +@ CHECK: vqrshl.s16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xf2] vqrshl.s16 d16, d16, d17 -// CHECK: vqrshl.s32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xf2] +@ CHECK: vqrshl.s32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xf2] vqrshl.s32 d16, d16, d17 -// CHECK: vqrshl.s64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xf2] +@ CHECK: vqrshl.s64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xf2] vqrshl.s64 d16, d16, d17 -// CHECK: vqrshl.u8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xf3] +@ CHECK: vqrshl.u8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xf3] vqrshl.u8 d16, d16, d17 -// CHECK: vqrshl.u16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xf3] +@ CHECK: vqrshl.u16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xf3] vqrshl.u16 d16, d16, d17 -// CHECK: vqrshl.u32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xf3] +@ CHECK: vqrshl.u32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xf3] vqrshl.u32 d16, d16, d17 -// CHECK: vqrshl.u64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xf3] +@ CHECK: vqrshl.u64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xf3] vqrshl.u64 d16, d16, d17 -// CHECK: vqrshl.s8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xf2] +@ CHECK: vqrshl.s8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xf2] vqrshl.s8 q8, q8, q9 -// CHECK: vqrshl.s16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xf2] +@ CHECK: vqrshl.s16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xf2] vqrshl.s16 q8, q8, q9 -// CHECK: vqrshl.s32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xf2] +@ CHECK: vqrshl.s32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xf2] vqrshl.s32 q8, q8, q9 -// CHECK: vqrshl.s64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xf2] +@ CHECK: vqrshl.s64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xf2] vqrshl.s64 q8, q8, q9 -// CHECK: vqrshl.u8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xf3] +@ CHECK: vqrshl.u8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xf3] vqrshl.u8 q8, q8, q9 -// CHECK: vqrshl.u16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xf3] +@ CHECK: vqrshl.u16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xf3] vqrshl.u16 q8, q8, q9 -// CHECK: vqrshl.u32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xf3] +@ CHECK: vqrshl.u32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xf3] vqrshl.u32 q8, q8, q9 -// CHECK: vqrshl.u64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xf3] +@ CHECK: vqrshl.u64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xf3] vqrshl.u64 q8, q8, q9 -// CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf2] +@ CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf2] vqshrn.s16 d16, q8, #8 -// CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf2] +@ CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf2] vqshrn.s32 d16, q8, #16 -// CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf2] +@ CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf2] vqshrn.s64 d16, q8, #32 -// CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf3] +@ CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xf3] vqshrn.u16 d16, q8, #8 -// CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf3] +@ CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xf3] vqshrn.u32 d16, q8, #16 -// CHECK: vqshrn.u64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf3] +@ CHECK: vqshrn.u64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xf3] vqshrn.u64 d16, q8, #32 -// CHECK: vqshrun.s16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf3] +@ CHECK: vqshrun.s16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf3] vqshrun.s16 d16, q8, #8 -// CHECK: vqshrun.s32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf3] +@ CHECK: vqshrun.s32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf3] vqshrun.s32 d16, q8, #16 -// CHECK: vqshrun.s64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf3] +@ CHECK: vqshrun.s64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf3] vqshrun.s64 d16, q8, #32 -// CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2] +@ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2] vqrshrn.s16 d16, q8, #8 -// CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2] +@ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2] vqrshrn.s32 d16, q8, #16 -// CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2] +@ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2] vqrshrn.s64 d16, q8, #32 -// CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3] +@ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3] vqrshrn.u16 d16, q8, #8 -// CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3] +@ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3] vqrshrn.u32 d16, q8, #16 -// CHECK: vqrshrn.u64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf3] +@ CHECK: vqrshrn.u64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf3] vqrshrn.u64 d16, q8, #32 -// CHECK: vqrshrun.s16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf3] +@ CHECK: vqrshrun.s16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf3] vqrshrun.s16 d16, q8, #8 -// CHECK: vqrshrun.s32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf3] +@ CHECK: vqrshrun.s32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf3] vqrshrun.s32 d16, q8, #16 -// CHECK: vqrshrun.s64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf3] +@ CHECK: vqrshrun.s64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf3] vqrshrun.s64 d16, q8, #32 Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=117941&r1=117940&r2=117941&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Mon Nov 1 13:33:37 2010 @@ -1,160 +1,160 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s -// CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] +@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] vshl.u8 d16, d17, d16 -// CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] +@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] vshl.u16 d16, d17, d16 -// CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] +@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] vshl.u32 d16, d17, d16 -// CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] +@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] vshl.u64 d16, d17, d16 -// CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] +@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] vshl.i8 d16, d16, #7 -// CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] +@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] vshl.i16 d16, d16, #15 -// CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] +@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] vshl.i32 d16, d16, #31 -// CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] +@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] vshl.i64 d16, d16, #63 -// CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] +@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] vshl.u8 q8, q9, q8 -// CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] +@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] vshl.u16 q8, q9, q8 -// CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] +@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] vshl.u32 q8, q9, q8 -// CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] +@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] vshl.u64 q8, q9, q8 -// CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] +@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] vshl.i8 q8, q8, #7 -// CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] +@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] vshl.i16 q8, q8, #15 -// CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] +@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] vshl.i32 q8, q8, #31 -// CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] +@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] vshl.i64 q8, q8, #63 -// CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] +@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] vshr.u8 d16, d16, #8 -// CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3] +@ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3] vshr.u16 d16, d16, #16 -// CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3] +@ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3] vshr.u32 d16, d16, #32 -// CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3] +@ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3] vshr.u64 d16, d16, #64 -// CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3] +@ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3] vshr.u8 q8, q8, #8 -// CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3] +@ CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3] vshr.u16 q8, q8, #16 -// CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3] +@ CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3] vshr.u32 q8, q8, #32 -// CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] +@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] vshr.u64 q8, q8, #64 -// CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2] +@ CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2] vshr.s8 d16, d16, #8 -// CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2] +@ CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2] vshr.s16 d16, d16, #16 -// CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2] +@ CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2] vshr.s32 d16, d16, #32 -// CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2] +@ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2] vshr.s64 d16, d16, #64 -// CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2] +@ CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2] vshr.s8 q8, q8, #8 -// CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2] +@ CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2] vshr.s16 q8, q8, #16 -// CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2 +@ CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2 vshr.s32 q8, q8, #32 -// CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2] +@ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2] vshr.s64 q8, q8, #64 -// CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] +@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] vshll.s8 q8, d16, #7 -// CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] +@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] vshll.s16 q8, d16, #15 -// CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] +@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] vshll.s32 q8, d16, #31 -// CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] +@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] vshll.u8 q8, d16, #7 -// CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] +@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] vshll.u16 q8, d16, #15 -// CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] +@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] vshll.u32 q8, d16, #31 -// CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] +@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] vshll.i8 q8, d16, #8 -// CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] +@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] vshll.i16 q8, d16, #16 -// CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] +@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] vshll.i32 q8, d16, #32 -// CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] +@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] vshrn.i16 d16, q8, #8 -// CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] +@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] vshrn.i32 d16, q8, #16 -// CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] +@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] vshrn.i64 d16, q8, #32 -// CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] +@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] vrshl.s8 d16, d17, d16 -// CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] +@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] vrshl.s16 d16, d17, d16 -// CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] +@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] vrshl.s32 d16, d17, d16 -// CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0 +@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0 vrshl.s64 d16, d17, d16 -// CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] +@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] vrshl.u8 d16, d17, d16 -// CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] +@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] vrshl.u16 d16, d17, d16 -// CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] +@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] vrshl.u32 d16, d17, d16 -// CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] +@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] vrshl.u64 d16, d17, d16 -// CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] +@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] vrshl.s8 q8, q9, q8 -// CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] +@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] vrshl.s16 q8, q9, q8 -// CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] +@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] vrshl.s32 q8, q9, q8 -// CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] +@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] vrshl.s64 q8, q9, q8 -// CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] +@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] vrshl.u8 q8, q9, q8 -// CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] +@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] vrshl.u16 q8, q9, q8 -// CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] +@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] vrshl.u32 q8, q9, q8 -// CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] +@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] vrshl.u64 q8, q9, q8 -// CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] +@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] vrshr.s8 d16, d16, #8 -// CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] +@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] vrshr.s16 d16, d16, #16 -// CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] +@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] vrshr.s32 d16, d16, #32 -// CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] +@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] vrshr.s64 d16, d16, #64 -// CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] vrshr.u8 d16, d16, #8 -// CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] +@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] vrshr.u16 d16, d16, #16 -// CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] +@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] vrshr.u32 d16, d16, #32 -// CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] +@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] vrshr.u64 d16, d16, #64 -// CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] +@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] vrshr.s8 q8, q8, #8 -// CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] +@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] vrshr.s16 q8, q8, #16 -// CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] +@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] vrshr.s32 q8, q8, #32 -// CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] +@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] vrshr.s64 q8, q8, #64 -// CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] +@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] vrshr.u8 q8, q8, #8 -// CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] +@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] vrshr.u16 q8, q8, #16 -// CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] +@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] vrshr.u32 q8, q8, #32 -// CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] vrshr.u64 q8, q8, #64 -// CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] +@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] vrshrn.i16 d16, q8, #8 -// CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] +@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] vrshrn.i32 d16, q8, #16 -// CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] +@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] vrshrn.i64 d16, q8, #32 From stoklund at 2pi.dk Mon Nov 1 14:49:52 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 19:49:52 -0000 Subject: [llvm-commits] [llvm] r117944 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp Message-ID: <20101101194953.06AE92A6C12C@llvm.org> Author: stoklund Date: Mon Nov 1 14:49:52 2010 New Revision: 117944 URL: http://llvm.org/viewvc/llvm-project?rev=117944&view=rev Log: Add basic LiveStacks verification. When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117944&r1=117943&r2=117944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Nov 1 14:49:52 2010 @@ -26,6 +26,7 @@ #include "llvm/Function.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineMemOperand.h" @@ -168,6 +169,7 @@ // Analysis information if available LiveVariables *LiveVars; LiveIntervals *LiveInts; + LiveStacks *LiveStks; SlotIndexes *Indexes; void visitMachineFunctionBefore(); @@ -250,12 +252,14 @@ LiveVars = NULL; LiveInts = NULL; + LiveStks = NULL; Indexes = NULL; if (PASS) { LiveInts = PASS->getAnalysisIfAvailable(); // We don't want to verify LiveVariables if LiveIntervals is available. if (!LiveInts) LiveVars = PASS->getAnalysisIfAvailable(); + LiveStks = PASS->getAnalysisIfAvailable(); Indexes = PASS->getAnalysisIfAvailable(); } @@ -726,6 +730,22 @@ report("PHI operand is not in the CFG", MO, MONum); break; + case MachineOperand::MO_FrameIndex: + if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && + LiveInts && !LiveInts->isNotInMIMap(MI)) { + LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); + SlotIndex Idx = LiveInts->getInstructionIndex(MI); + if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) { + report("Instruction loads from dead spill slot", MO, MONum); + *OS << "Live stack: " << LI << '\n'; + } + if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) { + report("Instruction stores to dead spill slot", MO, MONum); + *OS << "Live stack: " << LI << '\n'; + } + } + break; + default: break; } From stoklund at 2pi.dk Mon Nov 1 14:49:57 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 19:49:57 -0000 Subject: [llvm-commits] [llvm] r117945 - in /llvm/trunk/lib/CodeGen: InlineSpiller.cpp LiveRangeEdit.cpp LiveRangeEdit.h Message-ID: <20101101194957.D95402A6C12D@llvm.org> Author: stoklund Date: Mon Nov 1 14:49:57 2010 New Revision: 117945 URL: http://llvm.org/viewvc/llvm-project?rev=117945&view=rev Log: Don't assign new registers created during a split to the same stack slot, but give them individual stack slots once the are actually spilled. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp llvm/trunk/lib/CodeGen/LiveRangeEdit.h Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=117945&r1=117944&r2=117945&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Mon Nov 1 14:49:57 2010 @@ -369,12 +369,12 @@ return; rc_ = mri_.getRegClass(edit.getReg()); - stackSlot_ = edit.assignStackSlot(vrm_); + stackSlot_ = vrm_.assignVirt2StackSlot(edit_->getReg()); // Update LiveStacks now that we are committed to spilling. LiveInterval &stacklvr = lss_.getOrCreateInterval(stackSlot_, rc_); - if (!stacklvr.hasAtLeastOneValue()) - stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator()); + assert(stacklvr.empty() && "Just created stack slot not empty"); + stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator()); stacklvr.MergeRangesInAsValue(edit_->getParent(), stacklvr.getValNumInfo(0)); // Iterate over instructions using register. Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=117945&r1=117944&r2=117945&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Mon Nov 1 14:49:57 2010 @@ -19,21 +19,12 @@ using namespace llvm; -int LiveRangeEdit::assignStackSlot(VirtRegMap &vrm) { - int ss = vrm.getStackSlot(getReg()); - if (ss != VirtRegMap::NO_STACK_SLOT) - return ss; - return vrm.assignVirt2StackSlot(getReg()); -} - LiveInterval &LiveRangeEdit::create(MachineRegisterInfo &mri, LiveIntervals &lis, VirtRegMap &vrm) { const TargetRegisterClass *RC = mri.getRegClass(parent_.reg); unsigned VReg = mri.createVirtualRegister(RC); vrm.grow(); - // Immediately assign to the same stack slot as parent. - vrm.assignVirt2StackSlot(VReg, assignStackSlot(vrm)); LiveInterval &li = lis.getOrCreateInterval(VReg); newRegs_.push_back(&li); return li; Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.h?rev=117945&r1=117944&r2=117945&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.h (original) +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.h Mon Nov 1 14:49:57 2010 @@ -80,10 +80,6 @@ unsigned size() const { return newRegs_.size()-firstNew_; } LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; } - /// assignStackSlot - Ensure a stack slot is assigned to parent. - /// @return the assigned stack slot number. - int assignStackSlot(VirtRegMap&); - /// create - Create a new register with the same class and stack slot as /// parent. LiveInterval &create(MachineRegisterInfo&, LiveIntervals&, VirtRegMap&); From gohman at apple.com Mon Nov 1 14:59:45 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 1 Nov 2010 12:59:45 -0700 Subject: [llvm-commits] PATCH: new Value::getThruSplat API In-Reply-To: References: <4CC7C7F9.9050806@mxc.ca> <343AA845-309E-4A08-A29D-181ABDFDBC36@apple.com> <6C49D21B-7E9B-4B73-9B13-B6FD93DD8B87@apple.com> Message-ID: <6F71E7C7-52C5-4A69-95B4-6E0DF67F94F4@apple.com> On Oct 30, 2010, at 9:54 AM, Chris Lattner wrote: > > On Oct 30, 2010, at 9:27 AM, Dan Gohman wrote: > >> seems pretty readable. And it would avoid the double-dyncast issue. But I'm not attatched. >> >> Or if you like: >> >> if (ConstantInt *CI = C->getAs()) >> >> clang uses some idioms like this, for example. *shrug* > > How is this different than > > if (ConstantInt *CI = dyn_cast(C)) ? For splat vectors, it would get the splat value. Unless you're suggesting making dyn_cast do that. Which you could, I suppose. That'd be dancing on the edge of just letting ConstantInt and ConstantFP have vector types. Dan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101101/cc879864/attachment.html From john.thompson.jtsoftware at gmail.com Mon Nov 1 15:23:50 2010 From: john.thompson.jtsoftware at gmail.com (John Thompson) Date: Mon, 1 Nov 2010 13:23:50 -0700 Subject: [llvm-commits] [llvm] r117667 - in /llvm/trunk: include/llvm/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Ta In-Reply-To: References: Message-ID: I did some investigation into some sizes, with the following results. First some sizes of the items using vector: ConstraintString = =*m,*m,~{dirflag},~{fpsr},~{flags} visitInlineAsm stack size = 2120 sizeof(SDISelAsmOperandInfo) = 240 sizeof(AsmOperandInfo) = 104 sizeof(ConstraintInfo) = 56 vector<*> = 20 Next with some reduced SmallVector sizes: ConstraintString = =*m,*m,~{dirflag},~{fpsr},~{flags} visitInlineAsm stack size = 14480 sizeof(SDISelAsmOperandInfo) = 672 sizeof(AsmOperandInfo) = 536 sizeof(ConstraintInfo) = 488 sizeof(SmallVector) = 3376 sizeof(SmallVector) = 2696 sizeof(SmallVector) = 2456 sizeof(SmallVector) = 320 sizeof(SmallVector) = 144 Note that I picked 5 for the main size for the constraint info structures because with x86, the 3 clobbers always make the total constraint info count 5, and we want the typical case to not cause the SmallVector to switch to dynamic. Finally with the original SmallVector sizes: ConstraintString = =*m,*m,~{dirflag},~{fpsr},~{flags} stackSize = 53024 sizeof(SDISelAsmOperandInfo) = 1616 sizeof(AsmOperandInfo) = 1480 sizeof(ConstraintInfo) = 1432 sizeof(SmallVector) = 25872 sizeof(SmallVector) = 23696 sizeof(SmallVector) = 22928 sizeof(SmallVector) = 1136 sizeof(SmallVector) = 272 To approximate the stack frame size I used the difference between call arguments in a run of a debug-built llc, i.e. void dumpSizes(void *stackRefInner) { printf("visitInlineAsm stack size = %d\n", (char*)stackRefInner - (char*)&stackRefInner); } void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { dumpSizes(&CS); ...} Question 1: >From the above, it appears that reducing the SmallVector sizes to the intermediate size used will get the visitInline stack frame size down to a bit less than 16K. So, would having the still somewhat largish 14.5K stack frame be better than having the dynamic allocations otherwise done with vector? I'm thinking yes, because the heap activity is probably slower and fragments memory. Question 2: If we wanted to look deeper into this, we'd probably want to look at timing and heap activity. I see that there is a Timer class that could be used for measuring timing. I didn't see a mechanism for tracking memory usage, i.e the total allocations and frees, and peak memory usage. Is there something like this in there? -John On Fri, Oct 29, 2010 at 3:47 PM, John Thompson < john.thompson.jtsoftware at gmail.com> wrote: > If stack space is of concern, I think it would be safer to go back to > vector. Using vector will mean more heap allocations, but the overall > memory usage would probably be less. > > How do you measure the stack space (i.e. is there a simple way besides > inspection in the debugger)? I'd like to measure both. > -John > On Fri, Oct 29, 2010 at 2:22 PM, Dale Johannesen wrote: > >> Interesting. It's true very small sizes are most common for these >> vectors, but I wouldn't have expected the overhead to be that significant. >> Perhaps try lowering all the fixed allocations to 4? >> >> On Oct 29, 2010, at 2:10 PMPDT, Nick Lewycky wrote: >> >> On 29 October 2010 10:29, John Thompson < >> John.Thompson.JTSoftware at gmail.com> wrote: >> >>> Author: jtsoftware >>> Date: Fri Oct 29 12:29:13 2010 >>> New Revision: 117667 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=117667&view=rev >>> Log: >>> Inline asm multiple alternative constraints development phase 2 - >>> improved basic logic, added initial platform support. >>> >> >> This change makes SelectionDAGBuilder::visitInlineAsm use up 30k of stack >> space, largely due to the switch from std::vector to SmallVector. Please >> fix! >> >> >> > > > -- > John Thompson > John.Thompson.JTSoftware at gmail.com > > -- John Thompson John.Thompson.JTSoftware at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101101/6abcab9c/attachment.html From rafael.espindola at gmail.com Mon Nov 1 15:42:45 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Mon, 1 Nov 2010 16:42:45 -0400 Subject: [llvm-commits] [patch] Fix FIXME by adding .org to the relaxation Message-ID: The attached patch fixes: // FIXME: We should compute this sooner, we don't want to recurse here, and // we would like to be more functional. by adding .org directives to the relaxation. We start by assuming they have 0 size and update as the relaxation advances. Cheers, Rafael -------------- next part -------------- A non-text attachment was scrubbed... Name: org.patch Type: text/x-diff Size: 6768 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101101/a41adaa8/attachment.bin From isanbard at gmail.com Mon Nov 1 15:41:43 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 20:41:43 -0000 Subject: [llvm-commits] [llvm] r117950 - in /llvm/trunk: lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll test/CodeGen/ARM/long_shift.ll Message-ID: <20101101204143.4CDD82A6C12C@llvm.org> Author: void Date: Mon Nov 1 15:41:43 2010 New Revision: 117950 URL: http://llvm.org/viewvc/llvm-project?rev=117950&view=rev Log: When we look at instructions to convert to setting the 's' flag, we need to look at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll llvm/trunk/test/CodeGen/ARM/long_shift.ll Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=117950&r1=117949&r2=117950&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Mon Nov 1 15:41:43 2010 @@ -50,6 +50,10 @@ Aggressive("aggressive-ext-opt", cl::Hidden, cl::desc("Aggressive extension optimization")); +static cl::opt +DisablePeephole("disable-peephole", cl::Hidden, cl::init(false), + cl::desc("Disable the peephole optimizer")); + STATISTIC(NumReuse, "Number of extension results reused"); STATISTIC(NumEliminated, "Number of compares eliminated"); @@ -276,11 +280,9 @@ if (MI->getDesc().isCompare() && !MI->getDesc().hasUnmodeledSideEffects()) { -#if 0 - if (OptimizeCmpInstr(MI, MBB, MII)) + if (!DisablePeephole && OptimizeCmpInstr(MI, MBB, MII)) Changed = true; else -#endif ++MII; } else { Changed |= OptimizeExtInstr(MI, MBB, LocalMIs); Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117950&r1=117949&r2=117950&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Nov 1 15:41:43 2010 @@ -21,7 +21,6 @@ #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/GlobalValue.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -34,6 +33,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/STLExtras.h" using namespace llvm; static cl::opt @@ -1557,10 +1557,10 @@ for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { const MachineOperand &MO = Instr.getOperand(IO); - if (!MO.isReg() || !MO.isDef()) continue; + if (!MO.isReg()) continue; - // This instruction modifies CPSR before the one we want to change. We - // can't do this transformation. + // This instruction modifies or uses CPSR after the one we want to + // change. We can't do this transformation. if (MO.getReg() == ARM::CPSR) return false; } Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=117950&r1=117949&r2=117950&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Mon Nov 1 15:41:43 2010 @@ -1,10 +1,15 @@ -; RUN: llc < %s -march=arm -; FIXME: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s -; FIXME: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s +; RUN: llc < %s -march=arm | FileCheck -check-prefix=ARM %s +; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s + +; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified. %struct.Foo = type { i8* } -define %struct.Foo* @_ZN3Foo7collectEj(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { +; ARM: foo +; THUMB: foo +; T2: foo +define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { entry: %scevgep = getelementptr %struct.Foo* %this, i32 1 br label %tailrecurse @@ -18,8 +23,8 @@ %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; CHECK: ands r12, r12, #3 -; CHECK-NEXT: beq +; ARM: ands r12, r12, #3 +; ARM-NEXT: beq ; THUMB: movs r5, #3 ; THUMB-NEXT: mov r6, r4 @@ -66,7 +71,7 @@ %struct.S = type { i8* (i8*)*, [1 x i8] } -; CHECK: bar +; ARM: bar ; THUMB: bar ; T2: bar define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { @@ -74,7 +79,7 @@ %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0 %1 = load i8* %0, align 1 %2 = zext i8 %1 to i32 -; CHECK: ands +; ARM: ands ; THUMB: ands ; T2: ands %3 = and i32 %2, 112 @@ -85,7 +90,7 @@ %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0 %6 = load i8* %5, align 1 %7 = zext i8 %6 to i32 -; CHECK: andsne +; ARM: andsne ; THUMB: ands ; T2: andsne %8 = and i32 %7, 112 Modified: llvm/trunk/test/CodeGen/ARM/long_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long_shift.ll?rev=117950&r1=117949&r2=117950&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/long_shift.ll (original) +++ llvm/trunk/test/CodeGen/ARM/long_shift.ll Mon Nov 1 15:41:43 2010 @@ -1,6 +1,4 @@ ; RUN: llc < %s -march=arm | FileCheck %s -; XFAIL: * -; FIXME: Fix after peephole optimizer is fixed. define i64 @f0(i64 %A, i64 %B) { ; CHECK: f0 From clattner at apple.com Mon Nov 1 16:01:47 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 1 Nov 2010 14:01:47 -0700 Subject: [llvm-commits] [llvm] r117667 - in /llvm/trunk: include/llvm/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Ta In-Reply-To: References: Message-ID: <44675C9D-2C9C-4626-93BB-34DB0A0D0AB3@apple.com> On Nov 1, 2010, at 1:23 PM, John Thompson wrote: > I did some investigation into some sizes, with the following results. John, Inline asm is not common enough that we care about optimizing its compile time. > Question 1: > > From the above, it appears that reducing the SmallVector sizes to the intermediate size used will get the visitInline stack frame size down to a bit less than 16K. So, would having the still somewhat largish 14.5K stack frame be better than having the dynamic allocations otherwise done with vector? I'm thinking yes, because the heap activity is probably slower and fragments memory. Please just use vector. > > Question 2: > > If we wanted to look deeper into this, we'd probably want to look at timing and heap activity. I see that there is a Timer class that could be used for measuring timing. I didn't see a mechanism for tracking memory usage, i.e the total allocations and frees, and peak memory usage. Is there something like this in there? Nope, but you can use the profiling tools available to your system. There is no specific need to build this stuff into LLVM itself. -Chris From rafael.espindola at gmail.com Mon Nov 1 16:04:50 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Mon, 1 Nov 2010 17:04:50 -0400 Subject: [llvm-commits] [PATCH] MCFragments Clean Up In-Reply-To: References: Message-ID: > http://codereview.chromium.org/4204007/diff/1/2 ?(MCAssembler.h) > http://codereview.chromium.org/4204007/diff/1/3 ?(MCAssembler.cpp) + // Compute fragment size + // ComputeSize() may call getFragmentOffset(), so mark F valid, + // but leave EffectiveSize invalid to catch errorneous calls to + // getFragmentEffectiveSize( This is better than having PendingLayout, but still think it is better to just pass StartAddress down as I did in my patch. Have you found any problems with that approach? > Thanks, > ??David Meyer Cheers, Rafael From sabre at nondot.org Mon Nov 1 16:06:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 21:06:34 -0000 Subject: [llvm-commits] [llvm] r117952 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101101210634.451C72A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 16:06:34 2010 New Revision: 117952 URL: http://llvm.org/viewvc/llvm-project?rev=117952&view=rev Log: use our fancy new MnemonicAlias mechanism to remove a bunch of hacks from X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117952&r1=117951&r2=117952&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Nov 1 16:06:34 2010 @@ -969,14 +969,6 @@ NameLoc); } - // call foo is not ambiguous with callw. - if (Name == "call" && Operands.size() == 2) { - const char *NewName = Is64Bit ? "callq" : "calll"; - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(NewName, NameLoc); - Name = NewName; - } - // movsd -> movsl (when no operands are specified). if (Name == "movsd" && Operands.size() == 1) { delete Operands[0]; @@ -1009,46 +1001,6 @@ Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc)); } - // "lgdtl" is not ambiguous 32-bit mode and is the same as "lgdt". - // "lgdtq" is not ambiguous 64-bit mode and is the same as "lgdt". - if ((Name == "lgdtl" && Is64Bit == false) || - (Name == "lgdtq" && Is64Bit == true)) { - const char *NewName = "lgdt"; - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(NewName, NameLoc); - Name = NewName; - } - - // "lidtl" is not ambiguous 32-bit mode and is the same as "lidt". - // "lidtq" is not ambiguous 64-bit mode and is the same as "lidt". - if ((Name == "lidtl" && Is64Bit == false) || - (Name == "lidtq" && Is64Bit == true)) { - const char *NewName = "lidt"; - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(NewName, NameLoc); - Name = NewName; - } - - // "sgdtl" is not ambiguous 32-bit mode and is the same as "sgdt". - // "sgdtq" is not ambiguous 64-bit mode and is the same as "sgdt". - if ((Name == "sgdtl" && Is64Bit == false) || - (Name == "sgdtq" && Is64Bit == true)) { - const char *NewName = "sgdt"; - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(NewName, NameLoc); - Name = NewName; - } - - // "sidtl" is not ambiguous 32-bit mode and is the same as "sidt". - // "sidtq" is not ambiguous 64-bit mode and is the same as "sidt". - if ((Name == "sidtl" && Is64Bit == false) || - (Name == "sidtq" && Is64Bit == true)) { - const char *NewName = "sidt"; - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(NewName, NameLoc); - Name = NewName; - } - return false; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=117952&r1=117951&r2=117952&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 1 16:06:34 2010 @@ -1306,10 +1306,10 @@ (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; // Note: No GR32->GR64 movzx form. -// TODO: lidtl/lidtq can be opcode aliases, perhaps others. -def : MnemonicAlias<"iret", "iretl">; -def : MnemonicAlias<"sysret", "sysretl">; +def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>; +def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>; + def : MnemonicAlias<"cbw", "cbtw">; def : MnemonicAlias<"cwd", "cwtd">; def : MnemonicAlias<"cdq", "cltd">; @@ -1351,6 +1351,19 @@ def : MnemonicAlias<"ud2a", "ud2">; def : MnemonicAlias<"verrw", "verr">; +// System instruction aliases. +def : MnemonicAlias<"iret", "iretl">; +def : MnemonicAlias<"sysret", "sysretl">; + +def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>; +def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>; +def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>; +def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>; +def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>; + // Floating point stack aliases. def : MnemonicAlias<"fcmovz", "fcmove">; From resistor at mac.com Mon Nov 1 16:08:20 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 01 Nov 2010 21:08:20 -0000 Subject: [llvm-commits] [llvm] r117953 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp test/Transforms/InstCombine/2010-11-01-lshr-mask.ll Message-ID: <20101101210820.AEB892A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 16:08:20 2010 New Revision: 117953 URL: http://llvm.org/viewvc/llvm-project?rev=117953&view=rev Log: When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low bits are zero, not that the current low bits are zero. Fixes . Added: llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=117953&r1=117952&r2=117953&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Mon Nov 1 16:08:20 2010 @@ -157,7 +157,7 @@ if (CI->getZExtValue() > NumBits) { unsigned LowBits = CI->getZExtValue() - NumBits; if (MaskedValueIsZero(I->getOperand(0), - APInt::getLowBitsSet(TypeWidth, LowBits))) + APInt::getLowBitsSet(TypeWidth, LowBits) << NumBits)) return true; } Added: llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll?rev=117953&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll Mon Nov 1 16:08:20 2010 @@ -0,0 +1,20 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s +; + +define i32 @main(i32 %argc) nounwind ssp { +entry: + %tmp3151 = trunc i32 %argc to i8 + %tmp3161 = or i8 %tmp3151, -17 + %tmp3162 = and i8 %tmp3151, 122 + %tmp3163 = xor i8 %tmp3162, -17 + %tmp4114 = shl i8 %tmp3163, 6 + %tmp4115 = xor i8 %tmp4114, %tmp3163 + %tmp4120 = xor i8 %tmp3161, %tmp4115 +; CHECK: lshr i8 %tmp4115, 1 +; CHECK-NOT: shl i8 %tmp4126, 6 + %tmp4126 = lshr i8 %tmp4120, 7 + %tmp4127 = mul i8 %tmp4126, 64 + %tmp4086 = zext i8 %tmp4127 to i32 +; CHECK: ret i32 + ret i32 %tmp4086 +} From isanbard at gmail.com Mon Nov 1 16:16:39 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 21:16:39 -0000 Subject: [llvm-commits] [llvm] r117955 - /llvm/trunk/test/MC/ARM/simple-fp-encoding.s Message-ID: <20101101211639.BB6022A6C12C@llvm.org> Author: void Date: Mon Nov 1 16:16:39 2010 New Revision: 117955 URL: http://llvm.org/viewvc/llvm-project?rev=117955&view=rev Log: Use ARM-style comments. Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=117955&r1=117954&r2=117955&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Nov 1 16:16:39 2010 @@ -1,160 +1,159 @@ -// RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s -// CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] +@ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] vadd.f64 d16, d17, d16 -// CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] +@ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] vadd.f32 s0, s1, s0 -// CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee] +@ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee] vsub.f64 d16, d17, d16 -// CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee] +@ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee] vsub.f32 s0, s1, s0 -// CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] +@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] vdiv.f64 d16, d17, d16 -// CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] +@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] vdiv.f32 s0, s1, s0 -// CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] +@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee] vmul.f64 d16, d17, d16 -// CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] +@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee] vmul.f32 s0, s1, s0 -// CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] +@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee] vnmul.f64 d16, d17, d16 -// CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee] +@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee] vnmul.f32 s0, s1, s0 -// CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] +@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee] vcmpe.f64 d17, d16 -// CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee] +@ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee] vcmpe.f32 s1, s0 -// FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] -// vcmpe.f64 d16, #0 +@ FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] +@ vcmpe.f64 d16, #0 -// FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] -// vcmpe.f32 s0, #0 +@ FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] +@ vcmpe.f32 s0, #0 -// CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] +@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] vabs.f64 d16, d16 -// CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] +@ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] vabs.f32 s0, s0 -// CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] +@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] vcvt.f32.f64 s0, d16 -// CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee] +@ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee] vcvt.f64.f32 d16, s0 -// CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] +@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee] vneg.f64 d16, d16 -// CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee] +@ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee] vneg.f32 s0, s0 -// CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] +@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee] vsqrt.f64 d16, d16 -// CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee] +@ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee] vsqrt.f32 s0, s0 -// CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] +@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee] vcvt.f64.s32 d16, s0 -// CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] +@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee] vcvt.f32.s32 s0, s0 -// CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] +@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee] vcvt.f64.u32 d16, s0 -// CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] +@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee] vcvt.f32.u32 s0, s0 -// CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] +@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee] vcvt.s32.f64 s0, d16 -// CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] +@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee] vcvt.s32.f32 s0, s0 -// CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] +@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee] vcvt.u32.f64 s0, d16 -// CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee] +@ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee] vcvt.u32.f32 s0, s0 -// CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] +@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee] vmla.f64 d16, d18, d17 -// CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] +@ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee] vmla.f32 s1, s2, s0 -// CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] +@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee] vmls.f64 d16, d18, d17 -// CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] +@ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee] vmls.f32 s1, s2, s0 -// CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] +@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee] vnmla.f64 d16, d18, d17 -// CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] +@ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee] vnmla.f32 s1, s2, s0 -// CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] +@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee] vnmls.f64 d16, d18, d17 -// CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] +@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] vnmls.f32 s1, s2, s0 -// FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] -// vmrs apsr_nzcv, fpscr +@ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ vmrs apsr_nzcv, fpscr -// CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] +@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] vnegne.f64 d16, d16 -// CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e] -// CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e] +@ CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e] +@ CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e] vmovne s0, r0 vmoveq s0, r1 -// CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee] +@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee] vmrs r0, fpscr -// CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee] +@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee] vmsr fpscr, r0 -// FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee] -// vmov.f64 d16, #3.000000e+00 +@ FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee] +@ vmov.f64 d16, #3.000000e+00 -// FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee] -// vmov.f32 s0, #3.000000e+00 +@ FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee] +@ vmov.f32 s0, #3.000000e+00 -// CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee] -// CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee] -// CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee] -// CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee] +@ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee] +@ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee] +@ CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee] +@ CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee] vmov s0, r0 vmov s1, r1 vmov s2, r2 vmov s3, r3 -// CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee] -// CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee] -// CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee] -// CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee] +@ CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee] +@ CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee] +@ CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee] +@ CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee] vmov r0, s0 vmov r1, s1 vmov r2, s2 vmov r3, s3 -// CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] +@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] vmov r0, r1, d16 - From isanbard at gmail.com Mon Nov 1 16:17:06 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 21:17:06 -0000 Subject: [llvm-commits] [llvm] r117956 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrVFP.td Message-ID: <20101101211706.3D3C12A6C12C@llvm.org> Author: void Date: Mon Nov 1 16:17:06 2010 New Revision: 117956 URL: http://llvm.org/viewvc/llvm-project?rev=117956&view=rev Log: Move the machine operand MC encoding patterns to the parent classes. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117956&r1=117955&r2=117956&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 1 16:17:06 2010 @@ -1573,6 +1573,19 @@ dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { + // Instruction operands. + bits<5> Dd; + bits<5> Dn; + bits<5> Dm; + + // Encode instruction operands. + let Inst{19-16} = Dn{3-0}; + let Inst{7} = Dn{4}; + let Inst{15-12} = Dd{3-0}; + let Inst{22} = Dd{4}; + let Inst{3-0} = Dm{3-0}; + let Inst{5} = Dm{4}; + let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=117956&r1=117955&r2=117956&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 1 16:17:06 2010 @@ -728,30 +728,12 @@ // FP FMA Operations. // -class ADbI_vmlX_Encode opcod1, bits<2> opcod2, bit op6, bit op4, - dag oops, dag iops, InstrItinClass itin, string opc, - string asm, list pattern> - : ADbI_vmlX { - // Instruction operands. - bits<5> Dd; - bits<5> Dn; - bits<5> Dm; - - // Encode instruction operands. - let Inst{19-16} = Dn{3-0}; - let Inst{7} = Dn{4}; - let Inst{15-12} = Dd{3-0}; - let Inst{22} = Dd{4}; - let Inst{3-0} = Dm{3-0}; - let Inst{5} = Dm{4}; -} - -def VMLAD : ADbI_vmlX_Encode<0b11100, 0b00, 0, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">; def VMLAS : ASbIn<0b11100, 0b00, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), @@ -765,12 +747,12 @@ def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)), (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; -def VMLSD : ADbI_vmlX_Encode<0b11100, 0b00, 1, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">; def VMLSS : ASbIn<0b11100, 0b00, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), @@ -784,11 +766,11 @@ def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)), (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; -def VNMLAD : ADbI_vmlX_Encode<0b11100, 0b01, 1, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)), - (f64 DPR:$Ddin)))]>, +def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)), + (f64 DPR:$Ddin)))]>, RegConstraint<"$Ddin = $Dd">; def VNMLAS : ASbI<0b11100, 0b01, 1, 0, @@ -803,12 +785,12 @@ def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin), (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; -def VNMLSD : ADbI_vmlX_Encode<0b11100, 0b01, 0, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">; def VNMLSS : ASbI<0b11100, 0b01, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), From gkistanova at gmail.com Mon Nov 1 16:41:43 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 01 Nov 2010 21:41:43 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r117958 - /llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Message-ID: <20101101214143.B32E82A6C12E@llvm.org> Author: gkistanova Date: Mon Nov 1 16:41:43 2010 New Revision: 117958 URL: http://llvm.org/viewvc/llvm-project?rev=117958&view=rev Log: Added build script for build on i686-pc-linux-gnu of cross llvm-gcc for arm-none-linux-gnueabi. Added: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi (with props) Added: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi?rev=117958&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi (added) +++ llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Mon Nov 1 16:41:43 2010 @@ -0,0 +1,223 @@ +#!/bin/bash + +set -e # Terminate script at the first line that fails. +set -o pipefail # Return the first non-zero pipe command error. +set -x # Print commands as they are executed + +# This script performs an automated build on i686-pc-linux-gnu of +# cross llvm-gcc for arm-none-linux-gnueabi. It assumes the valid native +# compiler for i686-pc-linux-gnu is in place and available as well as +# cross libraries and headers for arm-none-linux-gnueabi. + +# --build=i686-pc-linux-gnu +# --host=i686-pc-linux-gnu2 +# --target=arm-none-linux-gnueabi +# + +# The usage: +# Run this build from the build from the build root directory as +# build-self-4-mingw32 [] [] + +# Expected project tree structure: +# +# +-- ${LLVM_src} +# +-- ${LLVM_GCC_src} +# +-- ${LLVM_obj} +# +-- ${LLVM_GCC_obj} +# +-- ${INSTALL} + +LLVM_src=llvm.src # The LLVM source code root directory name. +LLVM_GCC_src=llvm-gcc.src # The LLVM-GCC source code root directory name. +LLVM_obj=llvm.obj # The LLVM build root directory name. +LLVM_GCC_obj=llvm-gcc.obj # The LLVM-GCC build root directory name. +INSTALL=install # Where the result will be installed. + +BUILD_ROOT=$PWD # Where build happens. +PRIVATE_INSTALL=${BUILD_ROOT}/${INSTALL} # Where the result will be installed. + +#------------------------------------------------------------------------------ +# Define build steps, parse and validate input parameters +#------------------------------------------------------------------------------ + +# This script supports the following steps: +do_clean=no # Clean up the build directory. +do_copy_cross_tools=no # Copy cross-tools. +do_configure_llvm=no # Configure LLVM. +do_make_llvm=no # Make LLVM. +do_install_llvm=no # Install LLVM-GCC. +do_test_llvm=no # Test LLVM. +do_configure_llvmgcc=no # Configure LLVM-GCC. +do_make_llvmgcc=no # Make LLVM-GCC. +do_install_llvmgcc=no # Install LLVM-GCC. +do_all=no # Runs all steps at once when requested. + +# Set step parameter +if (( $# == 0 )) ; then + do_all=yes +fi +# else +if (( ! $# == 0 )) ; then + # First check that the parameter actually defines a step. + case $1 in + clean | \ + copy_cross_tools | \ + configure_llvm | \ + make_llvm | \ + install_llvm | \ + test_llvm | \ + configure_llvmgcc | \ + make_llvmgcc | \ + install_llvmgcc | \ + all) + eval do_$1=yes # Set the flag for the requested step . + shift # Remove it since is is ours and already precessed. + ;; + + *) + # Not our parameter. Pass it as is. + esac +fi + +# Set all steps if do_all requested +if [ "$do_all" == "yes" ] ; then + # Set all steps to yes + do_clean=yes + do_copy_cross_tools=yes + do_configure_llvm=yes + do_make_llvm=yes + do_install_llvm=yes + do_test_llvm=yes + do_configure_llvmgcc=yes + do_make_llvmgcc=yes + do_install_llvmgcc=yes +fi + +#------------------------------------------------------------------------------ +# Step: Clean up. +#------------------------------------------------------------------------------ +if [ "$do_clean" == "yes" ] ; then + + # Remove everything from where we will be installing the result. + rm -rf ${PRIVATE_INSTALL} + mkdir -p ${PRIVATE_INSTALL} + chmod a+rx ${PRIVATE_INSTALL} + +fi + +#------------------------------------------------------------------------------ +# Step: Copy cross-tools. +#------------------------------------------------------------------------------ +if [ "$do_copy_cross_tools" == "yes" ] ; then + + # We need a local copy of binutils, system libraries and headers, + # since we will be installing there. + cp -RL /opt/codesourcery/* ${PRIVATE_INSTALL} + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvm" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_obj} + cd ${BUILD_ROOT}/${LLVM_obj} + + ../${LLVM_src}/configure --prefix=${PRIVATE_INSTALL} \ + --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu \ + --target=arm-none-linux-gnueabi \ + --enable-shared \ + --disable-multilib \ + --disable-nls \ + --disable-bootstrap \ + --without-llvmgcc \ + --without-llvmgxx \ + --enable-optimized \ + --enable-assertions \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM. +#------------------------------------------------------------------------------ +if [ "$do_make_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM. +#------------------------------------------------------------------------------ +if [ "$do_install_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make install VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Test LLVM. +#------------------------------------------------------------------------------ +if [ "$do_test_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + make check-lit VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvmgcc" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_GCC_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_GCC_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_GCC_obj} + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + + ../${LLVM_GCC_src}/configure --prefix=${PRIVATE_INSTALL} \ + --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu \ + --target=arm-none-linux-gnueabi \ + --enable-shared \ + --disable-nls \ + --disable-bootstrap \ + --with-sysroot=${PRIVATE_INSTALL}/arm-none-linux-gnueabi/libc \ + --enable-languages=c,c++ \ + --program-prefix=llvm- \ + --enable-llvm=${BUILD_ROOT}/${LLVM_obj} \ + $@ # Extra args if any +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_make_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_install_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make install \ + $@ # Extra args if any + +fi Propchange: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi ------------------------------------------------------------------------------ svn:executable = * From stoklund at 2pi.dk Mon Nov 1 16:51:29 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 21:51:29 -0000 Subject: [llvm-commits] [llvm] r117959 - /llvm/trunk/lib/CodeGen/SplitKit.cpp Message-ID: <20101101215129.B8F032A6C12C@llvm.org> Author: stoklund Date: Mon Nov 1 16:51:29 2010 New Revision: 117959 URL: http://llvm.org/viewvc/llvm-project?rev=117959&view=rev Log: Update kill flags while rewriting instructions after splitting. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117959&r1=117958&r2=117959&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Nov 1 16:51:29 2010 @@ -822,6 +822,7 @@ for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(reg), RE = mri_.reg_end(); RI != RE;) { MachineOperand &MO = RI.getOperand(); + unsigned OpNum = RI.getOperandNo(); MachineInstr *MI = MO.getParent(); ++RI; if (MI->isDebugValue()) { @@ -844,6 +845,8 @@ DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'<< Idx); assert(LI && "No register was live at use"); MO.setReg(LI->reg); + if (MO.isUse() && !MI->isRegTiedToDefOperand(OpNum)) + MO.setIsKill(LI->killedAt(Idx.getDefIndex())); DEBUG(dbgs() << '\t' << *MI); } } From stoklund at 2pi.dk Mon Nov 1 16:51:31 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 21:51:31 -0000 Subject: [llvm-commits] [llvm] r117960 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp Message-ID: <20101101215131.C3A8C2A6C12D@llvm.org> Author: stoklund Date: Mon Nov 1 16:51:31 2010 New Revision: 117960 URL: http://llvm.org/viewvc/llvm-project?rev=117960&view=rev Log: Add kill flag verification. At least X86FloatingPoint requires correct kill flags after register allocation, and targets using register scavenging benefit. Conservative kill flags are not enough. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117960&r1=117959&r2=117960&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Nov 1 16:51:31 2010 @@ -589,7 +589,7 @@ unsigned DefReg = MI->getOperand(defIdx).getReg(); if (Reg == DefReg) { isKill = true; - // ANd in that case an explicit kill flag is not allowed. + // And in that case an explicit kill flag is not allowed. if (MO->isKill()) report("Illegal kill flag on two-address instruction operand", MO, MONum); @@ -622,7 +622,18 @@ report("No live range at use", MO, MONum); *OS << UseIdx << " is not live in " << LI << '\n'; } - // TODO: Verify isKill == LI.killedAt. + // Verify isKill == LI.killedAt. + if (!MI->isRegTiedToDefOperand(MONum)) { + bool liKill = LI.killedAt(UseIdx.getDefIndex()); + if (isKill && !liKill) { + report("Live range continues after kill flag", MO, MONum); + *OS << "Live range: " << LI << '\n'; + } + if (!isKill && liKill) { + report("Live range ends without kill flag", MO, MONum); + *OS << "Live range: " << LI << '\n'; + } + } } else { report("Virtual register has no Live interval", MO, MONum); } From bob.wilson at apple.com Mon Nov 1 17:04:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 01 Nov 2010 22:04:05 -0000 Subject: [llvm-commits] [llvm] r117964 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMSchedule.td lib/Target/ARM/ARMScheduleA8.td lib/Target/ARM/ARMScheduleA9.td test/CodeGen/ARM/vldlane.ll Message-ID: <20101101220406.0AF782A6C12C@llvm.org> Author: bwilson Date: Mon Nov 1 17:04:05 2010 New Revision: 117964 URL: http://llvm.org/viewvc/llvm-project?rev=117964&view=rev Log: Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMSchedule.td llvm/trunk/lib/Target/ARM/ARMScheduleA8.td llvm/trunk/lib/Target/ARM/ARMScheduleA9.td llvm/trunk/test/CodeGen/ARM/vldlane.ll Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=117964&r1=117963&r2=117964&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Nov 1 17:04:05 2010 @@ -110,6 +110,13 @@ } static const NEONLdStTableEntry NEONLdStTable[] = { +{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 }, +{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, false, EvenDblSpc, 1, 4 }, +{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 }, +{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, false, EvenDblSpc, 1, 2 }, +{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 }, +{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, false, EvenDblSpc, 1, 8 }, + { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, @@ -476,8 +483,9 @@ DstIsDead = MI.getOperand(OpIdx).isDead(); DstReg = MI.getOperand(OpIdx++).getReg(); GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); - MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); + if (NumRegs > 1) + MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); if (NumRegs > 2) MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); if (NumRegs > 3) @@ -502,7 +510,9 @@ // Add the subregs as sources of the new instruction. unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | getKillRegState(MO.isKill())); - MIB.addReg(D0, SrcFlags).addReg(D1, SrcFlags); + MIB.addReg(D0, SrcFlags); + if (NumRegs > 1) + MIB.addReg(D1, SrcFlags); if (NumRegs > 2) MIB.addReg(D2, SrcFlags); if (NumRegs > 3) @@ -943,6 +953,12 @@ ExpandVST(MBBI); break; + case ARM::VLD1LNq8Pseudo: + case ARM::VLD1LNq16Pseudo: + case ARM::VLD1LNq32Pseudo: + case ARM::VLD1LNq8Pseudo_UPD: + case ARM::VLD1LNq16Pseudo_UPD: + case ARM::VLD1LNq32Pseudo_UPD: case ARM::VLD2LNd8Pseudo: case ARM::VLD2LNd16Pseudo: case ARM::VLD2LNd32Pseudo: Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117964&r1=117963&r2=117964&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 1 17:04:05 2010 @@ -421,6 +421,8 @@ def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo; def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo; +} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 + // Classes for VLD*LN pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VLDQLNPseudo @@ -449,7 +451,46 @@ nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; // VLD1LN : Vector Load (single element to one lane) -// FIXME: Not yet implemented. +class VLD1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, + PatFrag LoadOp> + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst), + (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), + IIC_VLD1ln, "vld1", Dt, "\\{$dst[$lane]\\}, $addr", + "$src = $dst", + [(set DPR:$dst, (vector_insert (Ty DPR:$src), + (i32 (LoadOp addrmode6:$addr)), + imm:$lane))]>; +class VLD1QLNPseudo : VLDQLNPseudo { + let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), + (i32 (LoadOp addrmode6:$addr)), + imm:$lane))]; +} + +def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8>; +def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16>; +def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load>; + +def VLD1LNq8Pseudo : VLD1QLNPseudo; +def VLD1LNq16Pseudo : VLD1QLNPseudo; +def VLD1LNq32Pseudo : VLD1QLNPseudo; + +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { + +// ...with address register writeback: +class VLD1LNWB op11_8, bits<4> op7_4, string Dt> + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, + DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, + "\\{$dst[$lane]\\}, $addr$offset", + "$src = $dst, $addr.addr = $wb", []>; + +def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8">; +def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16">; +def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32">; + +def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo; +def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo; +def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo; // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, bits<4> op7_4, string Dt> Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=117964&r1=117963&r2=117964&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original) +++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Mon Nov 1 17:04:05 2010 @@ -134,6 +134,8 @@ def IIC_VLD1x2u : InstrItinClass; def IIC_VLD1x3u : InstrItinClass; def IIC_VLD1x4u : InstrItinClass; +def IIC_VLD1ln : InstrItinClass; +def IIC_VLD1lnu : InstrItinClass; def IIC_VLD2 : InstrItinClass; def IIC_VLD2x2 : InstrItinClass; def IIC_VLD2u : InstrItinClass; Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=117964&r1=117963&r2=117964&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Mon Nov 1 17:04:05 2010 @@ -457,6 +457,18 @@ InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 2, 1]>, // + // VLD1ln + InstrItinData, + InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_LSPipe]>], + [3, 1, 1, 1]>, + // + // VLD1lnu + InstrItinData, + InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_LSPipe]>], + [3, 2, 1, 1, 1, 1]>, + // // VLD2 InstrItinData, InstrStage<2, [A8_NLSPipe], 1>, Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=117964&r1=117963&r2=117964&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Mon Nov 1 17:04:05 2010 @@ -787,6 +787,24 @@ InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 2, 1]>, // + // VLD1ln + InstrItinData, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<9, [A9_DRegsVFP], 0, Reserved>, + InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_LSUnit]>], + [4, 1, 1, 1]>, + // + // VLD1lnu + InstrItinData, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<9, [A9_DRegsVFP], 0, Reserved>, + InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_LSUnit]>], + [4, 2, 1, 1, 1, 1]>, + // // VLD2 InstrItinData, InstrStage<1, [A9_MUX0], 0>, Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=117964&r1=117963&r2=117964&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Mon Nov 1 17:04:05 2010 @@ -1,5 +1,32 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { +;CHECK: vld1lanei8: +;CHECK: vld1.8 {d16[3]}, [r0] + %tmp1 = load <8 x i8>* %B + %tmp2 = load i8* %A, align 1 + %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { +;CHECK: vld1lanei16: +;CHECK: vld1.16 {d16[2]}, [r0] + %tmp1 = load <4 x i16>* %B + %tmp2 = load i16* %A, align 2 + %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { +;CHECK: vld1lanei32: +;CHECK: vld1.32 {d16[1]}, [r0] + %tmp1 = load <2 x i32>* %B + %tmp2 = load i32* %A, align 4 + %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 + ret <2 x i32> %tmp3 +} + %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> } %struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> } From gkistanova at gmail.com Mon Nov 1 17:06:52 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 01 Nov 2010 22:06:52 -0000 Subject: [llvm-commits] [zorg] r117965 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20101101220652.D7B9C2A6C12C@llvm.org> Author: gkistanova Date: Mon Nov 1 17:06:52 2010 New Revision: 117965 URL: http://llvm.org/viewvc/llvm-project?rev=117965&view=rev Log: Added new llvm-gcc scripted builder to build i686-pc-linux-gnu-cross-arm-none-linux-gnueabi. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=117965&r1=117964&r2=117965&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov 1 17:06:52 2010 @@ -522,6 +522,53 @@ 'haltOnFailure' : True },]), 'category' : 'llvm-gcc' }, + {'name' : "llvm-gcc-i686-pc-linux-gnu-cross-gnueabi", + 'slavenames': [ "kistanova4" ], + 'builddir' : "llvm-gcc-i686-pc-linux-gnu-cross-gnueabi", + 'factory' : ScriptedBuilder.getScriptedBuildFactory( + source_code = [SVN(name='svn-llvm', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/', + defaultBranch='trunk', + workdir="llvm.src"), + SVN(name='svn-llvm-gcc', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm-gcc-4.2/', + defaultBranch='trunk', + workdir="llvm-gcc.src"),], + launcher = 'llvm-gcc.src/extras/buildbot-launcher', + build_script = 'llvm-gcc.src/extras/build-x-4-gnueabi', + extra_args = [], + build_steps = [{'name' : 'clean', + 'description' : 'clean', + 'haltOnFailure' : True }, + {'name' : 'copy_cross_tools', + 'description' : 'copy cross-tools', + 'haltOnFailure' : True }, + {'name' : 'configure_llvm', + 'description' : 'configure llvm', + 'haltOnFailure' : True }, + {'name' : 'make_llvm', + 'description' : 'make llvm', + 'extra_args' : ['-j8'], + 'haltOnFailure' : True }, + {'name' : 'install_llvm', + 'description' : 'install llvm', + 'extra_args' : ['-j8'], + 'haltOnFailure' : False }, + {'name' : 'test_llvm', + 'description' : 'test llvm', + 'haltOnFailure' : False }, + {'name' : 'configure_llvmgcc', + 'description' : 'configure llvm-gcc', + 'haltOnFailure' : True }, + {'name' : 'make_llvmgcc', + 'description' : 'make llvm-gcc', + 'extra_args' : ['-j8'], + 'haltOnFailure' : True }, + {'name' : 'install_llvmgcc', + 'description' : 'install llvm-gcc', + 'haltOnFailure' : True },]), + 'category' : 'llvm-gcc' }, + {'name' : "clang-i686-linux-selfhost-rel", 'slavenames' : ["osu8"], 'builddir' : "clang-i686-linux-selfhost-rel", From gkistanova at gmail.com Mon Nov 1 17:26:58 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 01 Nov 2010 22:26:58 -0000 Subject: [llvm-commits] [zorg] r117966 - /zorg/trunk/buildbot/osuosl/master/config/slaves.py Message-ID: <20101101222658.ACE912A6C12C@llvm.org> Author: gkistanova Date: Mon Nov 1 17:26:58 2010 New Revision: 117966 URL: http://llvm.org/viewvc/llvm-project?rev=117966&view=rev Log: Added new llvm-gcc slave to build i686-pc-linux-gnu-cross-arm-none-linux-gnueabi. Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=117966&r1=117965&r2=117966&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Mon Nov 1 17:26:58 2010 @@ -51,6 +51,9 @@ # Windows 7 Ultimate. create_slave("kistanova3", properties={'jobs' : 1}, max_builds=1), + # CentOS 5.4. + create_slave("kistanova4", properties={'jobs' : 1}, max_builds=2), + # Quad Core x86_64, Solaris / AurorAUX create_slave("evocallaghan", properties={'jobs' : 4}, max_builds=1), From sabre at nondot.org Mon Nov 1 18:07:52 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 23:07:52 -0000 Subject: [llvm-commits] [llvm] r117967 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <20101101230752.78BCD2A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 18:07:52 2010 New Revision: 117967 URL: http://llvm.org/viewvc/llvm-project?rev=117967&view=rev Log: rearrange a bit. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=117967&r1=117966&r2=117967&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 1 18:07:52 2010 @@ -1255,58 +1255,9 @@ include "X86InstrCompiler.td" //===----------------------------------------------------------------------===// -// Assembler Aliases +// Assembler Mnemonic Aliases //===----------------------------------------------------------------------===// -// movsx aliases -def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), - "movsx $src, $dst", - (MOVSX16rr8W GR16:$dst, GR8:$src)>; -def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), - "movsx $src, $dst", - (MOVSX16rm8W GR16:$dst, i8mem:$src)>; - -def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), - "movsx $src, $dst", - (MOVSX32rr8 GR32:$dst, GR8:$src)>; -def : InstAlias<(outs GR32:$dst), (ins GR16:$src), - "movsx $src, $dst", - (MOVSX32rr16 GR32:$dst, GR16:$src)>; - -def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), - "movsx $src, $dst", - (MOVSX64rr8 GR64:$dst, GR8:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR16:$src), - "movsx $src, $dst", - (MOVSX64rr16 GR64:$dst, GR16:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR32:$src), - "movsx $src, $dst", - (MOVSX64rr32 GR64:$dst, GR32:$src)>; - -// movzx aliases -def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), - "movzx $src, $dst", - (MOVZX16rr8W GR16:$dst, GR8:$src)>; -def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), - "movzx $src, $dst", - (MOVZX16rm8W GR16:$dst, i8mem:$src)>; - -def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), - "movzx $src, $dst", - (MOVZX32rr8 GR32:$dst, GR8:$src)>; -def : InstAlias<(outs GR32:$dst), (ins GR16:$src), - "movzx $src, $dst", - (MOVZX32rr16 GR32:$dst, GR16:$src)>; - -def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), - "movzx $src, $dst", - (MOVZX64rr8_Q GR64:$dst, GR8:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR16:$src), - "movzx $src, $dst", - (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; -// Note: No GR32->GR64 movzx form. - - def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>; def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>; @@ -1414,3 +1365,57 @@ defm : IntegerCondCodeMnemonicAlias<"cmov", "l">; defm : IntegerCondCodeMnemonicAlias<"cmov", "q">; + +//===----------------------------------------------------------------------===// +// Assembler Instruction Aliases +//===----------------------------------------------------------------------===// + +// movsx aliases +def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), + "movsx $src, $dst", + (MOVSX16rr8W GR16:$dst, GR8:$src)>; +def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), + "movsx $src, $dst", + (MOVSX16rm8W GR16:$dst, i8mem:$src)>; + +def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), + "movsx $src, $dst", + (MOVSX32rr8 GR32:$dst, GR8:$src)>; +def : InstAlias<(outs GR32:$dst), (ins GR16:$src), + "movsx $src, $dst", + (MOVSX32rr16 GR32:$dst, GR16:$src)>; + +def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), + "movsx $src, $dst", + (MOVSX64rr8 GR64:$dst, GR8:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR16:$src), + "movsx $src, $dst", + (MOVSX64rr16 GR64:$dst, GR16:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR32:$src), + "movsx $src, $dst", + (MOVSX64rr32 GR64:$dst, GR32:$src)>; + +// movzx aliases +def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), + "movzx $src, $dst", + (MOVZX16rr8W GR16:$dst, GR8:$src)>; +def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), + "movzx $src, $dst", + (MOVZX16rm8W GR16:$dst, i8mem:$src)>; + +def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), + "movzx $src, $dst", + (MOVZX32rr8 GR32:$dst, GR8:$src)>; +def : InstAlias<(outs GR32:$dst), (ins GR16:$src), + "movzx $src, $dst", + (MOVZX32rr16 GR32:$dst, GR16:$src)>; + +def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), + "movzx $src, $dst", + (MOVZX64rr8_Q GR64:$dst, GR8:$src)>; +def : InstAlias<(outs GR64:$dst), (ins GR16:$src), + "movzx $src, $dst", + (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; +// Note: No GR32->GR64 movzx form. + + From sabre at nondot.org Mon Nov 1 18:08:02 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 23:08:02 -0000 Subject: [llvm-commits] [llvm] r117968 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101101230802.86F212A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 18:08:02 2010 New Revision: 117968 URL: http://llvm.org/viewvc/llvm-project?rev=117968&view=rev Log: give MatchableInfo::Operand a constructor Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=117968&r1=117967&r2=117968&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Nov 1 18:08:02 2010 @@ -329,6 +329,9 @@ /// The original operand this corresponds to, if any. const CGIOperandList::OperandInfo *OperandInfo; + + Operand(ClassInfo *C, const CGIOperandList::OperandInfo *OpInfo) + : Class(C), OperandInfo(OpInfo) {} }; /// InstrName - The target name for this instruction. @@ -1006,9 +1009,7 @@ // Check for singleton registers. if (Record *RegRecord = II->getSingletonRegisterForToken(i, *this)) { - MatchableInfo::Operand Op; - Op.Class = RegisterClasses[RegRecord]; - Op.OperandInfo = 0; + MatchableInfo::Operand Op(RegisterClasses[RegRecord], 0); assert(Op.Class && Op.Class->Registers.size() == 1 && "Unexpected class for singleton register"); II->Operands.push_back(Op); @@ -1017,10 +1018,7 @@ // Check for simple tokens. if (Token[0] != '$') { - MatchableInfo::Operand Op; - Op.Class = getTokenClass(Token); - Op.OperandInfo = 0; - II->Operands.push_back(Op); + II->Operands.push_back(MatchableInfo::Operand(getTokenClass(Token), 0)); continue; } @@ -1057,10 +1055,8 @@ assert(OI && "Unable to find tied operand target!"); } - MatchableInfo::Operand Op; - Op.Class = getOperandClass(Token, *OI); - Op.OperandInfo = OI; - II->Operands.push_back(Op); + II->Operands.push_back(MatchableInfo::Operand(getOperandClass(Token, + *OI), OI)); } } From isanbard at gmail.com Mon Nov 1 18:11:22 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 23:11:22 -0000 Subject: [llvm-commits] [llvm] r117969 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Message-ID: <20101101231122.AF9452A6C12C@llvm.org> Author: void Date: Mon Nov 1 18:11:22 2010 New Revision: 117969 URL: http://llvm.org/viewvc/llvm-project?rev=117969&view=rev Log: Minor cleanup. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=117969&r1=117968&r2=117969&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 1 18:11:22 2010 @@ -630,15 +630,14 @@ // S32 (U=0, sx=1) -> SL // U32 (U=1, sx=1) -> UL -let Constraints = "$a = $dst" in { +// FIXME: Marking these as codegen only seems wrong. They are real +// instructions(?) +let Constraints = "$a = $dst", isCodeGenOnly = 1 in { // FP to Fixed-Point: -// FIXME: Marking these as codegen only seems wrong. They are real -// instructions(?) -let isCodeGenOnly = 1 in { def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0, - (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), + (outs SPR:$dst), (ins SPR_S16:$a, i32imm:$fbits), IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", [/* For disassembly only; pattern left blank */]>; @@ -676,11 +675,9 @@ (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", [/* For disassembly only; pattern left blank */]>; -} // End of 'let isCodeGenOnly = 1 in' // Fixed-Point to FP: -let isCodeGenOnly = 1 in { def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0, (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", @@ -720,9 +717,8 @@ (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits), IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", [/* For disassembly only; pattern left blank */]>; -} // End of 'let isCodeGenOnly = 1 in' -} // End of 'let Constraints = "$src = $dst" in' +} // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in' //===----------------------------------------------------------------------===// // FP FMA Operations. @@ -841,8 +837,8 @@ // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags // to APSR. let Defs = [CPSR], Uses = [FPSCR] in -def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs", - "\tapsr_nzcv, fpscr", +def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, + "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]> { let Inst{27-20} = 0b11101111; let Inst{19-16} = 0b0001; From isanbard at gmail.com Mon Nov 1 18:17:54 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 01 Nov 2010 23:17:54 -0000 Subject: [llvm-commits] [llvm] r117971 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Message-ID: <20101101231754.CEBEF2A6C12C@llvm.org> Author: void Date: Mon Nov 1 18:17:54 2010 New Revision: 117971 URL: http://llvm.org/viewvc/llvm-project?rev=117971&view=rev Log: Missed reverting this bit. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=117971&r1=117970&r2=117971&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 1 18:17:54 2010 @@ -637,7 +637,7 @@ // FP to Fixed-Point: def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0, - (outs SPR:$dst), (ins SPR_S16:$a, i32imm:$fbits), + (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits), IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", [/* For disassembly only; pattern left blank */]>; From bob.wilson at apple.com Mon Nov 1 18:40:46 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 01 Nov 2010 23:40:46 -0000 Subject: [llvm-commits] [llvm] r117975 - /llvm/trunk/test/CodeGen/ARM/vldlane.ll Message-ID: <20101101234046.6439F2A6C12C@llvm.org> Author: bwilson Date: Mon Nov 1 18:40:46 2010 New Revision: 117975 URL: http://llvm.org/viewvc/llvm-project?rev=117975&view=rev Log: Add VLD1-lane testcases for quad-register types. Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=117975&r1=117974&r2=117975&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Mon Nov 1 18:40:46 2010 @@ -27,6 +27,33 @@ ret <2 x i32> %tmp3 } +define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { +;CHECK: vld1laneQi8: +;CHECK: vld1.8 {d17[1]}, [r0] + %tmp1 = load <16 x i8>* %B + %tmp2 = load i8* %A, align 1 + %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { +;CHECK: vld1laneQi16: +;CHECK: vld1.16 {d17[1]}, [r0] + %tmp1 = load <8 x i16>* %B + %tmp2 = load i16* %A, align 2 + %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { +;CHECK: vld1laneQi32: +;CHECK: vld1.32 {d17[1]}, [r0] + %tmp1 = load <4 x i32>* %B + %tmp2 = load i32* %A, align 4 + %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3 + ret <4 x i32> %tmp3 +} + %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> } %struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> } From bob.wilson at apple.com Mon Nov 1 18:40:51 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 01 Nov 2010 23:40:51 -0000 Subject: [llvm-commits] [llvm] r117976 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/vldlane.ll Message-ID: <20101101234051.7CDB82A6C12D@llvm.org> Author: bwilson Date: Mon Nov 1 18:40:51 2010 New Revision: 117976 URL: http://llvm.org/viewvc/llvm-project?rev=117976&view=rev Log: Add support for alignment operands on VLD1-lane instructions. This is another part of the fix for Radar 8599955. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/vldlane.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=117976&r1=117975&r2=117976&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Nov 1 18:40:51 2010 @@ -116,7 +116,7 @@ bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode); bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset); - bool SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align); + bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align); bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label); @@ -222,6 +222,9 @@ SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); + + // Get the alignment operand for a NEON VLD or VST instruction. + SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector); }; } @@ -769,10 +772,26 @@ return true; } -bool ARMDAGToDAGISel::SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align){ +bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr, + SDValue &Align) { Addr = N; - // Default to no alignment. - Align = CurDAG->getTargetConstant(0, MVT::i32); + + unsigned Alignment = 0; + if (LSBaseSDNode *LSN = dyn_cast(Parent)) { + // This case occurs only for VLD1-lane/dup and VST1-lane instructions. + // The maximum alignment is equal to the memory size being referenced. + unsigned LSNAlign = LSN->getAlignment(); + unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8; + if (LSNAlign > MemSize && MemSize > 1) + Alignment = MemSize; + } else { + // All other uses of addrmode6 are for intrinsics. For now just record + // the raw alignment value; it will be refined later based on the legal + // alignment operands for the intrinsic. + Alignment = cast(Parent)->getAlignment(); + } + + Align = CurDAG->getTargetConstant(Alignment, MVT::i32); return true; } @@ -1261,19 +1280,23 @@ /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand /// of a NEON VLD or VST instruction. The supported values depend on the /// number of registers being loaded. -static unsigned GetVLDSTAlign(SDNode *N, unsigned NumVecs, bool is64BitVector) { +SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs, + bool is64BitVector) { unsigned NumRegs = NumVecs; if (!is64BitVector && NumVecs < 3) NumRegs *= 2; - unsigned Alignment = cast(N)->getAlignment(); + unsigned Alignment = cast(Align)->getZExtValue(); if (Alignment >= 32 && NumRegs == 4) - return 32; - if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4)) - return 16; - if (Alignment >= 8) - return 8; - return 0; + Alignment = 32; + else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4)) + Alignment = 16; + else if (Alignment >= 8) + Alignment = 8; + else + Alignment = 0; + + return CurDAG->getTargetConstant(Alignment, MVT::i32); } SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs, @@ -1283,15 +1306,13 @@ DebugLoc dl = N->getDebugLoc(); SDValue MemAddr, Align; - if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align)) + if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) return NULL; SDValue Chain = N->getOperand(0); EVT VT = N->getValueType(0); bool is64BitVector = VT.is64BitVector(); - - unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector); - Align = CurDAG->getTargetConstant(Alignment, MVT::i32); + Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); unsigned OpcodeIndex; switch (VT.getSimpleVT().SimpleTy) { @@ -1397,15 +1418,13 @@ DebugLoc dl = N->getDebugLoc(); SDValue MemAddr, Align; - if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align)) + if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) return NULL; SDValue Chain = N->getOperand(0); EVT VT = N->getOperand(3).getValueType(); bool is64BitVector = VT.is64BitVector(); - - unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector); - Align = CurDAG->getTargetConstant(Alignment, MVT::i32); + Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); unsigned OpcodeIndex; switch (VT.getSimpleVT().SimpleTy) { @@ -1520,7 +1539,7 @@ DebugLoc dl = N->getDebugLoc(); SDValue MemAddr, Align; - if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align)) + if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) return NULL; SDValue Chain = N->getOperand(0); @@ -1529,16 +1548,18 @@ EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType(); bool is64BitVector = VT.is64BitVector(); + unsigned Alignment = 0; if (NumVecs != 3) { - unsigned Alignment = cast(N)->getAlignment(); + Alignment = cast(Align)->getZExtValue(); unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8; if (Alignment > NumBytes) Alignment = NumBytes; // Alignment must be a power of two; make sure of that. Alignment = (Alignment & -Alignment); - if (Alignment > 1) - Align = CurDAG->getTargetConstant(Alignment, MVT::i32); + if (Alignment == 1) + Alignment = 0; } + Align = CurDAG->getTargetConstant(Alignment, MVT::i32); unsigned OpcodeIndex; switch (VT.getSimpleVT().SimpleTy) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117976&r1=117975&r2=117976&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 1 18:40:51 2010 @@ -469,7 +469,7 @@ // addrmode6 := reg with optional writeback // def addrmode6 : Operand, - ComplexPattern { + ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); } Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=117976&r1=117975&r2=117976&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Mon Nov 1 18:40:51 2010 @@ -2,27 +2,30 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld1lanei8: +;Check the (default) alignment value. ;CHECK: vld1.8 {d16[3]}, [r0] %tmp1 = load <8 x i8>* %B - %tmp2 = load i8* %A, align 1 + %tmp2 = load i8* %A, align 8 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3 ret <8 x i8> %tmp3 } define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld1lanei16: -;CHECK: vld1.16 {d16[2]}, [r0] +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld1.16 {d16[2]}, [r0, :16] %tmp1 = load <4 x i16>* %B - %tmp2 = load i16* %A, align 2 + %tmp2 = load i16* %A, align 8 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2 ret <4 x i16> %tmp3 } define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld1lanei32: -;CHECK: vld1.32 {d16[1]}, [r0] +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld1.32 {d16[1]}, [r0, :32] %tmp1 = load <2 x i32>* %B - %tmp2 = load i32* %A, align 4 + %tmp2 = load i32* %A, align 8 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 ret <2 x i32> %tmp3 } @@ -31,25 +34,25 @@ ;CHECK: vld1laneQi8: ;CHECK: vld1.8 {d17[1]}, [r0] %tmp1 = load <16 x i8>* %B - %tmp2 = load i8* %A, align 1 + %tmp2 = load i8* %A, align 8 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9 ret <16 x i8> %tmp3 } define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld1laneQi16: -;CHECK: vld1.16 {d17[1]}, [r0] +;CHECK: vld1.16 {d17[1]}, [r0, :16] %tmp1 = load <8 x i16>* %B - %tmp2 = load i16* %A, align 2 + %tmp2 = load i16* %A, align 8 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5 ret <8 x i16> %tmp3 } define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld1laneQi32: -;CHECK: vld1.32 {d17[1]}, [r0] +;CHECK: vld1.32 {d17[1]}, [r0, :32] %tmp1 = load <4 x i32>* %B - %tmp2 = load i32* %A, align 4 + %tmp2 = load i32* %A, align 8 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3 ret <4 x i32> %tmp3 } From grosbach at apple.com Mon Nov 1 18:40:56 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 23:40:56 -0000 Subject: [llvm-commits] [llvm] r117977 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101101234056.4403B2A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 18:40:56 2010 New Revision: 117977 URL: http://llvm.org/viewvc/llvm-project?rev=117977&view=rev Log: Remove unused function. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117977&r1=117976&r2=117977&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 1 18:40:56 2010 @@ -126,12 +126,6 @@ } } - void EmitImmediate(const MCOperand &Disp, - unsigned ImmSize, MCFixupKind FixupKind, - unsigned &CurByte, raw_ostream &OS, - SmallVectorImpl &Fixups, - int ImmOffset = 0) const; - void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const; }; @@ -144,13 +138,6 @@ return new ARMMCCodeEmitter(TM, Ctx); } -void ARMMCCodeEmitter:: -EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, - unsigned &CurByte, raw_ostream &OS, - SmallVectorImpl &Fixups, int ImmOffset) const { - assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented."); -} - /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, From grosbach at apple.com Mon Nov 1 18:45:50 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 01 Nov 2010 23:45:50 -0000 Subject: [llvm-commits] [llvm] r117978 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101101234550.F1A702A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 18:45:50 2010 New Revision: 117978 URL: http://llvm.org/viewvc/llvm-project?rev=117978&view=rev Log: Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME for handling the fixup necessary. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117978&r1=117977&r2=117978&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 1 18:45:50 2010 @@ -178,6 +178,15 @@ // {11-0} = imm12 const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); + uint32_t Binary = 0; + + // If The first operand isn't a register, we have a label reference. + if (!MO.isReg()) { + Binary |= ARM::PC << 13; // Rn is PC. + // FIXME: Add a fixup referencing the label. + return Binary; + } + unsigned Reg = getARMRegisterNumbering(MO.getReg()); int32_t Imm12 = MO1.getImm(); bool isAdd = Imm12 >= 0; @@ -187,7 +196,7 @@ // Immediate is always encoded as positive. The 'U' bit controls add vs sub. if (Imm12 < 0) Imm12 = -Imm12; - uint32_t Binary = Imm12 & 0xfff; + Binary = Imm12 & 0xfff; if (isAdd) Binary |= (1 << 12); Binary |= (Reg << 13); From sabre at nondot.org Mon Nov 1 18:57:24 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 01 Nov 2010 23:57:24 -0000 Subject: [llvm-commits] [llvm] r117979 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101101235724.213942A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 18:57:23 2010 New Revision: 117979 URL: http://llvm.org/viewvc/llvm-project?rev=117979&view=rev Log: fix computation of ambiguous instructions to not ignore the mnemonic. FWIW, X86 has 254 ambiguous instructions. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=117979&r1=117978&r2=117979&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Nov 1 18:57:23 2010 @@ -411,6 +411,10 @@ /// ambiguously match the same set of operands as \arg RHS (without being a /// strictly superior match). bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) { + // The primary comparator is the instruction mnemonic. + if (Tokens[0] != RHS.Tokens[0]) + return false; + // The number of operands is unambiguous. if (Operands.size() != RHS.Operands.size()) return false; @@ -849,8 +853,8 @@ } void AsmMatcherInfo::BuildOperandClasses() { - std::vector AsmOperands; - AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass"); + std::vector AsmOperands = + Records.getAllDerivedDefinitions("AsmOperandClass"); // Pre-populate AsmOperandClasses map. for (std::vector::iterator it = AsmOperands.begin(), @@ -1127,7 +1131,7 @@ } } - std::sort(MIOperandList.begin(), MIOperandList.end()); + array_pod_sort(MIOperandList.begin(), MIOperandList.end()); // Compute the total number of operands. unsigned NumMIOperands = 0; From stoklund at 2pi.dk Mon Nov 1 18:59:49 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 23:59:49 -0000 Subject: [llvm-commits] [llvm] r117980 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h Message-ID: <20101101235949.21EE42A6C12C@llvm.org> Author: stoklund Date: Mon Nov 1 18:59:48 2010 New Revision: 117980 URL: http://llvm.org/viewvc/llvm-project?rev=117980&view=rev Log: When inserting copies during splitting, always use the parent register as the source, and let rewrite() clean it up. This way, kill flags on the inserted copies are fixed as well during rewrite(). We can't just assume that all the copies we insert are going to be kills since critical edges into loop headers sometimes require both source and dest to be live out of a block. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=117980&r1=117979&r2=117980&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Nov 1 18:59:48 2010 @@ -659,13 +659,13 @@ addSimpleRange(I->start, std::min(End, I->end), I->valno); } -VNInfo *LiveIntervalMap::defByCopyFrom(unsigned Reg, - const VNInfo *ParentVNI, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) { +VNInfo *LiveIntervalMap::defByCopy(const VNInfo *ParentVNI, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) { const TargetInstrDesc &TID = MBB.getParent()->getTarget().getInstrInfo()-> get(TargetOpcode::COPY); - MachineInstr *MI = BuildMI(MBB, I, DebugLoc(), TID, li_->reg).addReg(Reg); + MachineInstr *MI = BuildMI(MBB, I, DebugLoc(), TID, li_->reg) + .addReg(parentli_.reg); SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); VNInfo *VNI = defValue(ParentVNI, DefIdx); VNI->setCopy(MI); @@ -723,8 +723,7 @@ truncatedValues.insert(ParentVNI); MachineInstr *MI = lis_.getInstructionFromIndex(Idx); assert(MI && "enterIntvBefore called with invalid index"); - VNInfo *VNI = openli_.defByCopyFrom(edit_.getReg(), ParentVNI, - *MI->getParent(), MI); + VNInfo *VNI = openli_.defByCopy(ParentVNI, *MI->getParent(), MI); openli_.getLI()->addRange(LiveRange(VNI->def, Idx.getDefIndex(), VNI)); DEBUG(dbgs() << ": " << *openli_.getLI() << '\n'); } @@ -741,8 +740,7 @@ } DEBUG(dbgs() << ": valno " << ParentVNI->id); truncatedValues.insert(ParentVNI); - VNInfo *VNI = openli_.defByCopyFrom(edit_.getReg(), ParentVNI, - MBB, MBB.getFirstTerminator()); + VNInfo *VNI = openli_.defByCopy(ParentVNI, MBB, MBB.getFirstTerminator()); // Make sure openli is live out of MBB. openli_.getLI()->addRange(LiveRange(VNI->def, End, VNI)); DEBUG(dbgs() << ": " << *openli_.getLI() << '\n'); @@ -775,8 +773,7 @@ MachineBasicBlock::iterator MII = lis_.getInstructionFromIndex(Idx); MachineBasicBlock *MBB = MII->getParent(); - VNInfo *VNI = dupli_.defByCopyFrom(openli_.getLI()->reg, ParentVNI, *MBB, - llvm::next(MII)); + VNInfo *VNI = dupli_.defByCopy(ParentVNI, *MBB, llvm::next(MII)); // Finally we must make sure that openli is properly extended from Idx to the // new copy. @@ -798,8 +795,8 @@ } // We are going to insert a back copy, so we must have a dupli_. - VNInfo *VNI = dupli_.defByCopyFrom(openli_.getLI()->reg, ParentVNI, - MBB, MBB.SkipPHIsAndLabels(MBB.begin())); + VNInfo *VNI = dupli_.defByCopy(ParentVNI, MBB, + MBB.SkipPHIsAndLabels(MBB.begin())); // Finally we must make sure that openli is properly extended from Start to // the new copy. Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=117980&r1=117979&r2=117980&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Nov 1 18:59:48 2010 @@ -246,12 +246,12 @@ /// beforehand so mapValue will work. void addRange(SlotIndex Start, SlotIndex End); - /// defByCopyFrom - Insert a copy from Reg to li, assuming that Reg carries - /// ParentVNI. Add a minimal live range for the new value and return it. - VNInfo *defByCopyFrom(unsigned Reg, - const VNInfo *ParentVNI, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I); + /// defByCopy- Insert a copy from parentli to li, assuming that ParentVNI is + /// live at the insert location. Add a minimal live range for the new value + /// and return it. + VNInfo *defByCopy(const VNInfo *ParentVNI, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I); }; From stoklund at 2pi.dk Mon Nov 1 18:59:53 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 23:59:53 -0000 Subject: [llvm-commits] [llvm] r117981 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp Message-ID: <20101101235953.7C9472A6C12D@llvm.org> Author: stoklund Date: Mon Nov 1 18:59:53 2010 New Revision: 117981 URL: http://llvm.org/viewvc/llvm-project?rev=117981&view=rev Log: Be more precise about verifying missing kill flags. It is legal for an instruction to have two operands using the same register, only one a kill. This is interpreted as a kill. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=117981&r1=117980&r2=117981&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Nov 1 18:59:53 2010 @@ -624,12 +624,14 @@ } // Verify isKill == LI.killedAt. if (!MI->isRegTiedToDefOperand(MONum)) { + // MI could kill register without a kill flag on MO. + bool miKill = MI->killsRegister(Reg); bool liKill = LI.killedAt(UseIdx.getDefIndex()); - if (isKill && !liKill) { + if (miKill && !liKill) { report("Live range continues after kill flag", MO, MONum); *OS << "Live range: " << LI << '\n'; } - if (!isKill && liKill) { + if (!miKill && liKill) { report("Live range ends without kill flag", MO, MONum); *OS << "Live range: " << LI << '\n'; } From stoklund at 2pi.dk Mon Nov 1 18:59:55 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 01 Nov 2010 23:59:55 -0000 Subject: [llvm-commits] [llvm] r117982 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <20101101235955.7A48C2A6C12E@llvm.org> Author: stoklund Date: Mon Nov 1 18:59:55 2010 New Revision: 117982 URL: http://llvm.org/viewvc/llvm-project?rev=117982&view=rev Log: MachineLICM should not claim to be preserving the CFG when it can split critical edges on demand. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=117982&r1=117981&r2=117982&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Mon Nov 1 18:59:55 2010 @@ -109,7 +109,6 @@ const char *getPassName() const { return "Machine Instruction LICM"; } virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesCFG(); AU.addRequired(); AU.addRequired(); AU.addRequired(); From resistor at mac.com Mon Nov 1 19:05:05 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 00:05:05 -0000 Subject: [llvm-commits] [llvm] r117984 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neon-vld-encoding.s Message-ID: <20101102000505.803712A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 19:05:05 2010 New Revision: 117984 URL: http://llvm.org/viewvc/llvm-project?rev=117984&view=rev Log: Add correct NEON encodings for the "multiple single elements" form of vld. Added: llvm/trunk/test/MC/ARM/neon-vld-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117984&r1=117983&r2=117984&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Nov 1 19:05:05 2010 @@ -101,7 +101,8 @@ unsigned OpIdx); unsigned getMachineSoImmOpValue(unsigned SoImm); - + unsigned getAddrMode6RegisterOperand(const MachineInstr &MI); + unsigned getAddrModeSBit(const MachineInstr &MI, const TargetInstrDesc &TID) const; @@ -172,6 +173,8 @@ const { return 0; } unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op) + const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=117984&r1=117983&r2=117984&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 1 19:05:05 2010 @@ -1771,6 +1771,15 @@ let Inst{21-20} = op21_20; let Inst{11-8} = op11_8; let Inst{7-4} = op7_4; + + bits<5> Vd; + bits<6> Rn; + bits<4> Rm; + + let Inst{22} = Vd{4}; + let Inst{15-12} = Vd{3-0}; + let Inst{19-16} = Rn{3-0}; + let Inst{3-0} = Rm{3-0}; } class PseudoNLdSt Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117984&r1=117983&r2=117984&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 1 19:05:05 2010 @@ -472,6 +472,7 @@ ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); + string EncoderMethod = "getAddrMode6RegisterOperand"; } def am6offset : Operand { Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117984&r1=117983&r2=117984&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 1 19:05:05 2010 @@ -164,23 +164,29 @@ // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string Dt> - : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), - (ins addrmode6:$addr), IIC_VLD1, - "vld1", Dt, "\\{$dst\\}, $addr", "", []>; + : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd), + (ins addrmode6:$Rn), IIC_VLD1, + "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} class VLD1Q op7_4, string Dt> - : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr), IIC_VLD1x2, - "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>; - -def VLD1d8 : VLD1D<0b0000, "8">; -def VLD1d16 : VLD1D<0b0100, "16">; -def VLD1d32 : VLD1D<0b1000, "32">; -def VLD1d64 : VLD1D<0b1100, "64">; - -def VLD1q8 : VLD1Q<0b0000, "8">; -def VLD1q16 : VLD1Q<0b0100, "16">; -def VLD1q32 : VLD1Q<0b1000, "32">; -def VLD1q64 : VLD1Q<0b1100, "64">; + : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2), + (ins addrmode6:$Rn), IIC_VLD1x2, + "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} + +def VLD1d8 : VLD1D<{0,0,0,?}, "8">; +def VLD1d16 : VLD1D<{0,1,0,?}, "16">; +def VLD1d32 : VLD1D<{1,0,0,?}, "32">; +def VLD1d64 : VLD1D<{1,1,0,?}, "64">; + +def VLD1q8 : VLD1Q<{0,0,?,?}, "8">; +def VLD1q16 : VLD1Q<{0,1,?,?}, "16">; +def VLD1q32 : VLD1Q<{1,0,?,?}, "32">; +def VLD1q64 : VLD1Q<{1,1,?,?}, "64">; def VLD1q8Pseudo : VLDQPseudo; def VLD1q16Pseudo : VLDQPseudo; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117984&r1=117983&r2=117984&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 1 19:05:05 2010 @@ -99,7 +99,7 @@ unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const; unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const; - + unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const; unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); @@ -296,6 +296,22 @@ return Binary; } +unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI, + unsigned Op) const { + const MCOperand &Reg = MI.getOperand(Op); + const MCOperand &Imm = MI.getOperand(Op+1); + + unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); + unsigned Align = Imm.getImm(); + switch(Align) { + case 8: Align = 0x01; break; + case 16: Align = 0x02; break; + case 32: Align = 0x03; break; + default: Align = 0x00; + } + return RegNo | (Align << 4); +} + void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { Added: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=117984&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Nov 1 19:05:05 2010 @@ -0,0 +1,19 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] + vld1.8 {d16}, [r0, :64] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] + vld1.16 {d16}, [r0] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] + vld1.32 {d16}, [r0] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] + vld1.64 {d16}, [r0] +@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] + vld1.8 {d16, d17}, [r0, :64] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] + vld1.16 {d16, d17}, [r0, :128] +@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] + vld1.32 {d16, d17}, [r0] +@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] + vld1.64 {d16, d17}, [r0] From grosbach at apple.com Mon Nov 1 19:13:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 02 Nov 2010 00:13:15 -0000 Subject: [llvm-commits] [llvm] r117985 - /llvm/trunk/include/llvm/Target/Target.td Message-ID: <20101102001315.CA40D2A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 19:13:15 2010 New Revision: 117985 URL: http://llvm.org/viewvc/llvm-project?rev=117985&view=rev Log: Tweak to fix spelling and grammar in comment. Modified: llvm/trunk/include/llvm/Target/Target.td Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=117985&r1=117984&r2=117985&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Mon Nov 1 19:13:15 2010 @@ -267,9 +267,9 @@ list Predicates = preds; } -/// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. outs and ins are identical both syntatically and -/// semantically, they are used to define def operands and use operands to +/// ops definition - This is just a simple marker used to identify the operand +/// list for an instruction. outs and ins are identical both syntactically and +/// semanticallyr; they are used to define def operands and use operands to /// improve readibility. This should be used like this: /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; From resistor at mac.com Mon Nov 1 19:14:00 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 00:14:00 -0000 Subject: [llvm-commits] [llvm] r117986 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101102001400.8D6D02A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 19:14:00 2010 New Revision: 117986 URL: http://llvm.org/viewvc/llvm-project?rev=117986&view=rev Log: Add aesthetic break. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117986&r1=117985&r2=117986&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 1 19:14:00 2010 @@ -307,7 +307,7 @@ case 8: Align = 0x01; break; case 16: Align = 0x02; break; case 32: Align = 0x03; break; - default: Align = 0x00; + default: Align = 0x00; break; } return RegNo | (Align << 4); } From grosbach at apple.com Mon Nov 1 19:16:40 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 02 Nov 2010 00:16:40 -0000 Subject: [llvm-commits] [llvm] r117987 - /llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Message-ID: <20101102001640.256CE2A6C12C@llvm.org> Author: grosbach Date: Mon Nov 1 19:16:39 2010 New Revision: 117987 URL: http://llvm.org/viewvc/llvm-project?rev=117987&view=rev Log: Tidy up. Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=117987&r1=117986&r2=117987&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Mon Nov 1 19:16:39 2010 @@ -49,7 +49,6 @@ } } - // If the VarBitInit at position 'bit' matches the specified variable then // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, @@ -65,7 +64,6 @@ return -1; } - void CodeEmitterGen::run(raw_ostream &o) { CodeGenTarget Target; std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); @@ -217,7 +215,6 @@ InstList.push_back(InstName); } - // Emit initial function code o << " const unsigned opcode = MI.getOpcode();\n" << " unsigned Value = InstBits[opcode];\n" From resistor at mac.com Mon Nov 1 19:24:52 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 00:24:52 -0000 Subject: [llvm-commits] [llvm] r117988 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20101102002452.D64302A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 19:24:52 2010 New Revision: 117988 URL: http://llvm.org/viewvc/llvm-project?rev=117988&view=rev Log: Attempt to provide correct encodings for a number of other vld1 variants, which we can't test since we can neither generate nor parse them at the moment. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117988&r1=117987&r2=117988&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 1 19:24:52 2010 @@ -195,25 +195,29 @@ // ...with address register writeback: class VLD1DWB op7_4, string Dt> - : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1u, - "vld1", Dt, "\\{$dst\\}, $addr$offset", - "$addr.addr = $wb", []>; + : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u, + "vld1", Dt, "\\{$Vd\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} class VLD1QWB op7_4, string Dt> - : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x2u, - "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset", - "$addr.addr = $wb", []>; - -def VLD1d8_UPD : VLD1DWB<0b0000, "8">; -def VLD1d16_UPD : VLD1DWB<0b0100, "16">; -def VLD1d32_UPD : VLD1DWB<0b1000, "32">; -def VLD1d64_UPD : VLD1DWB<0b1100, "64">; - -def VLD1q8_UPD : VLD1QWB<0b0000, "8">; -def VLD1q16_UPD : VLD1QWB<0b0100, "16">; -def VLD1q32_UPD : VLD1QWB<0b1000, "32">; -def VLD1q64_UPD : VLD1QWB<0b1100, "64">; + : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u, + "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} + +def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">; +def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">; +def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">; +def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">; + +def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">; +def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">; +def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">; +def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">; def VLD1q8Pseudo_UPD : VLDQWBPseudo; def VLD1q16Pseudo_UPD : VLDQWBPseudo; @@ -222,48 +226,58 @@ // ...with 3 registers (some of these are only for the disassembler): class VLD1D3 op7_4, string Dt> - : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr), IIC_VLD1x3, "vld1", Dt, - "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>; + : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt, + "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} class VLD1D3WB op7_4, string Dt> - : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x3u, "vld1", Dt, - "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>; - -def VLD1d8T : VLD1D3<0b0000, "8">; -def VLD1d16T : VLD1D3<0b0100, "16">; -def VLD1d32T : VLD1D3<0b1000, "32">; -def VLD1d64T : VLD1D3<0b1100, "64">; - -def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">; -def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">; -def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">; -def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">; + : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt, + "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} + +def VLD1d8T : VLD1D3<{0,0,0,?}, "8">; +def VLD1d16T : VLD1D3<{0,1,0,?}, "16">; +def VLD1d32T : VLD1D3<{1,0,0,?}, "32">; +def VLD1d64T : VLD1D3<{1,1,0,?}, "64">; + +def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">; +def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">; +def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">; +def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">; def VLD1d64TPseudo : VLDQQPseudo; def VLD1d64TPseudo_UPD : VLDQQWBPseudo; // ...with 4 registers (some of these are only for the disassembler): class VLD1D4 op7_4, string Dt> - : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD1x4, "vld1", Dt, - "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; + : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt, + "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} class VLD1D4WB op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "vld1", Dt, - "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb", - []>; - -def VLD1d8Q : VLD1D4<0b0000, "8">; -def VLD1d16Q : VLD1D4<0b0100, "16">; -def VLD1d32Q : VLD1D4<0b1000, "32">; -def VLD1d64Q : VLD1D4<0b1100, "64">; - -def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">; -def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">; -def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">; -def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">; + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt, + "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb", + []> { + let Inst{5-4} = Rn{5-4}; +} + +def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">; +def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">; +def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">; +def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">; + +def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">; +def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">; +def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">; +def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">; def VLD1d64QPseudo : VLDQQPseudo; def VLD1d64QPseudo_UPD : VLDQQWBPseudo; From dalej at apple.com Mon Nov 1 19:25:43 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 02 Nov 2010 00:25:43 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r117989 - /llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Message-ID: <20101102002543.61ADB2A6C12C@llvm.org> Author: johannes Date: Mon Nov 1 19:25:43 2010 New Revision: 117989 URL: http://llvm.org/viewvc/llvm-project?rev=117989&view=rev Log: Emit D and Q register clobber information on inline asm's correctly. Often this will be not what the user specified exactly, but some equivalent set. 8602365. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=117989&r1=117988&r2=117989&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Mon Nov 1 19:25:43 2010 @@ -24499,9 +24499,12 @@ /* APPLE LOCAL end 5571707 Allow R9 as caller-saved register */ /* APPLE LOCAL begin 6902792 Q register clobbers in inline asm */ +/* LLVM LOCAL begin 8602365 */ /* Worker function for TARGET_MD_ASM_CLOBBERS. - We do this to translate references to Qn registers into the equivalent - D(2n)/D(2n+1) register pairs. */ + Some fancy footwork is needed to represent clobbers of D and Q registers. + LLVM_REG_NAME, used by EmitASM_EXPR, will only emit S0..S31 and D16..D31. + Thus D0..D15 and all Q registers are reduced here to some combination of + these. */ static tree arm_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED, tree inputs ATTRIBUTE_UNUSED, @@ -24511,20 +24514,51 @@ for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) { - const char *clobber_name; - clobber_name = TREE_STRING_POINTER (TREE_VALUE (tail)); - if (TOLOWER (clobber_name[0]) == 'q' && ISDIGIT (clobber_name[1]) + const char *clobber_name = TREE_STRING_POINTER (TREE_VALUE (tail)); + char regkind = TOLOWER (clobber_name[0]); + if ((regkind == 'q' || regkind == 'd') && ISDIGIT (clobber_name[1]) && (ISDIGIT (clobber_name[2]) || clobber_name[2] == '\0')) { - char regname[4] = "dXX"; - /* found a Q register in the clobber list, so add the D reference - to the upper dword of it. The existing clobber for the Q - register will automatically translate to the low dword. */ - int regno = atoi (clobber_name + 1) * 2 + 1; - snprintf (regname + 1, 3, "%d", regno); - clobbers = - tree_cons (NULL_TREE, build_string (strlen(regname), regname), - clobbers); + int regno = atoi (clobber_name + 1); + if (regkind == 'q' && (regno >= 8 && regno < 16)) + { + char regname[4] = "dXX"; + /* The existing clobber will automatically translate to the low + D register. */ + snprintf (regname + 1, 3, "%d", regno * 2 + 1); + clobbers = + tree_cons (NULL_TREE, build_string (strlen(regname), regname), + clobbers); + } + else if (regkind == 'q' && (regno >=0 && regno < 8)) + { + char regname[4] = "sXX"; + /* The existing clobber will automatically translate to the low + S register. */ + snprintf (regname + 1, 3, "%d", regno * 4 + 1); + clobbers = + tree_cons (NULL_TREE, build_string (strlen(regname), regname), + clobbers); + snprintf (regname + 1, 3, "%d", regno * 4 + 2); + clobbers = + tree_cons (NULL_TREE, build_string (strlen(regname), regname), + clobbers); + snprintf (regname + 1, 3, "%d", regno * 4 + 3); + clobbers = + tree_cons (NULL_TREE, build_string (strlen(regname), regname), + clobbers); + } + else if (regkind == 'd' && (regno >= 0 && regno < 16)) + { + char regname[4] = "sXX"; + /* The existing clobber will automatically translate to the low + S register. */ + snprintf (regname + 1, 3, "%d", regno * 2 + 1); + clobbers = + tree_cons (NULL_TREE, build_string (strlen(regname), regname), + clobbers); + } +/* LLVM LOCAL end 8602365 */ } } return clobbers; From stoklund at 2pi.dk Mon Nov 1 19:58:37 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 02 Nov 2010 00:58:37 -0000 Subject: [llvm-commits] [llvm] r117992 - /llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Message-ID: <20101102005837.DF96D2A6C12C@llvm.org> Author: stoklund Date: Mon Nov 1 19:58:37 2010 New Revision: 117992 URL: http://llvm.org/viewvc/llvm-project?rev=117992&view=rev Log: Don't try to split weird critical edges that really aren't: BB#1: derived from LLVM BB %bb.nph28 Live Ins: %AL Predecessors according to CFG: BB#0 TEST8rr %reg16384, %reg16384, %EFLAGS; GR8:%reg16384 JNE_4 , %EFLAGS JMP_4 Successors according to CFG: BB#2 BB#2 These double CFG edges only ever occur in bugpoint-generated code, so there is no need to attempt something clever. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=117992&r1=117991&r2=117992&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Mon Nov 1 19:58:37 2010 @@ -450,14 +450,24 @@ MachineFunction *MF = getParent(); DebugLoc dl; // FIXME: this is nowhere - // We may need to update this's terminator, but we can't do that if AnalyzeBranch - // fails. If this uses a jump table, we won't touch it. + // We may need to update this's terminator, but we can't do that if + // AnalyzeBranch fails. If this uses a jump table, we won't touch it. const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) return NULL; + // Avoid bugpoint weirdness: A block may end with a conditional branch but + // jumps to the same MBB is either case. We have duplicate CFG edges in that + // case that we can't handle. Since this never happens in properly optimized + // code, just skip those edges. + if (TBB && TBB == FBB) { + DEBUG(dbgs() << "Won't split critical edge after degenerate BB#" + << getNumber() << '\n'); + return NULL; + } + MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); MF->insert(llvm::next(MachineFunction::iterator(this)), NMBB); DEBUG(dbgs() << "Splitting critical edge:" From sabre at nondot.org Mon Nov 1 20:03:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 01:03:43 -0000 Subject: [llvm-commits] [llvm] r117993 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101102010344.0ACC52A6C12C@llvm.org> Author: lattner Date: Mon Nov 1 20:03:43 2010 New Revision: 117993 URL: http://llvm.org/viewvc/llvm-project?rev=117993&view=rev Log: rename operands -> asmoperands to be more descriptive. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=117993&r1=117992&r2=117993&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Nov 1 20:03:43 2010 @@ -347,8 +347,9 @@ /// Tokens - The tokenized assembly pattern that this instruction matches. SmallVector Tokens; - /// Operands - The operands that this instruction matches. - SmallVector Operands; + /// AsmOperands - The textual operands that this instruction matches, + /// including literal tokens for the mnemonic, etc. + SmallVector AsmOperands; /// Predicates - The required subtarget features to match this instruction. SmallVector RequiredFeatures; @@ -392,15 +393,15 @@ if (Tokens[0] != RHS.Tokens[0]) return Tokens[0] < RHS.Tokens[0]; - if (Operands.size() != RHS.Operands.size()) - return Operands.size() < RHS.Operands.size(); + if (AsmOperands.size() != RHS.AsmOperands.size()) + return AsmOperands.size() < RHS.AsmOperands.size(); // Compare lexicographically by operand. The matcher validates that other // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith(). - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (*Operands[i].Class < *RHS.Operands[i].Class) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) return true; - if (*RHS.Operands[i].Class < *Operands[i].Class) + if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) return false; } @@ -416,7 +417,7 @@ return false; // The number of operands is unambiguous. - if (Operands.size() != RHS.Operands.size()) + if (AsmOperands.size() != RHS.AsmOperands.size()) return false; // Otherwise, make sure the ordering of the two instructions is unambiguous @@ -425,21 +426,21 @@ // Tokens and operand kinds are unambiguous (assuming a correct target // specific parser). - for (unsigned i = 0, e = Operands.size(); i != e; ++i) - if (Operands[i].Class->Kind != RHS.Operands[i].Class->Kind || - Operands[i].Class->Kind == ClassInfo::Token) - if (*Operands[i].Class < *RHS.Operands[i].Class || - *RHS.Operands[i].Class < *Operands[i].Class) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) + if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind || + AsmOperands[i].Class->Kind == ClassInfo::Token) + if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class || + *RHS.AsmOperands[i].Class < *AsmOperands[i].Class) return false; // Otherwise, this operand could commute if all operands are equivalent, or // there is a pair of operands that compare less than and a pair that // compare greater than. bool HasLT = false, HasGT = false; - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (*Operands[i].Class < *RHS.Operands[i].Class) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) HasLT = true; - if (*RHS.Operands[i].Class < *Operands[i].Class) + if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) HasGT = true; } @@ -543,8 +544,8 @@ } errs() << "]\n"; - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - Operand &Op = Operands[i]; + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + Operand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; if (Op.Class->Kind == ClassInfo::Token) { errs() << '\"' << Tokens[i] << "\"\n"; @@ -1016,13 +1017,14 @@ MatchableInfo::Operand Op(RegisterClasses[RegRecord], 0); assert(Op.Class && Op.Class->Registers.size() == 1 && "Unexpected class for singleton register"); - II->Operands.push_back(Op); + II->AsmOperands.push_back(Op); continue; } // Check for simple tokens. if (Token[0] != '$') { - II->Operands.push_back(MatchableInfo::Operand(getTokenClass(Token), 0)); + II->AsmOperands.push_back(MatchableInfo::Operand(getTokenClass(Token), + 0)); continue; } @@ -1059,7 +1061,7 @@ assert(OI && "Unable to find tied operand target!"); } - II->Operands.push_back(MatchableInfo::Operand(getOperandClass(Token, + II->AsmOperands.push_back(MatchableInfo::Operand(getOperandClass(Token, *OI), OI)); } } @@ -1113,8 +1115,8 @@ // Order the (class) operands by the order to convert them into an MCInst. SmallVector, 4> MIOperandList; - for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.Operands[i]; + for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { + MatchableInfo::Operand &Op = II.AsmOperands[i]; if (Op.OperandInfo) MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i)); } @@ -1145,7 +1147,7 @@ std::string Signature = "Convert"; unsigned CurIndex = 0; for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.Operands[MIOperandList[i].second]; + MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; assert(CurIndex <= Op.OperandInfo->MIOperandNo && "Duplicate match for instruction operand!"); @@ -1204,7 +1206,7 @@ CvtOS << " case " << Signature << ":\n"; CurIndex = 0; for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.Operands[MIOperandList[i].second]; + MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; // Add the implicit operands. for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { @@ -1701,7 +1703,7 @@ for (std::vector::const_iterator it = Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) - MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size()); + MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size()); // Emit the static match table; unused classes get initalized to 0 which is @@ -1749,8 +1751,8 @@ OS << " { " << Target.getName() << "::" << II.InstrName << ", \"" << II.Tokens[0] << "\"" << ", " << II.ConversionFnKind << ", { "; - for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.Operands[i]; + for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { + MatchableInfo::Operand &Op = II.AsmOperands[i]; if (i) OS << ", "; OS << Op.Class->Name; From foldr at codedgers.com Mon Nov 1 20:22:41 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 2 Nov 2010 02:22:41 +0100 Subject: [llvm-commits] [llvm] r117596 - /llvm/trunk/lib/System/Unix/Program.inc In-Reply-To: <361CB234-1D15-44A4-ADC7-4E4E249DC3F5@apple.com> References: <20101028203433.BDCB82A6C12C@llvm.org> <20101029102425.GA2668@localhost.localdomain> <361CB234-1D15-44A4-ADC7-4E4E249DC3F5@apple.com> Message-ID: <20101102012241.GA5452@localhost.localdomain> Hi, On Fri, Oct 29, 2010 at 11:12:01AM -0700, Dan Gohman wrote: > > >>> Alternatively, we can change FindExecutable to take into account that > >>> canExecute can be false for the path returned by FindProgramByName. > >> > >> > >> My assumption is that it's perfectly acceptable for FindExecutable > >> to return a non-executable path here; its caller will attempt to > >> execute the path, get an error, and report the error to the user, > > > > I think it's not. Currently, FindExecutable always succeeds (on unix-likes), > > even if given a non-absolute path. FindExecutable("something") = > > Path("$EXE_DIR").appendComponent("something"), which was not the original > > intent. > > The code to call FindProgramByName there was only added as a > hack for Windows to add a ".exe" suffix. FindExecutable ideally should > always succeed, because it is primarily just a path manipulation. Originally, FindExecutable looked like this: sys::Path Result = sys::Path::GetMainExecutable(Argv0, MainAddr); Result.eraseComponent(); if (!Result.isEmpty()) { Result.appendComponent(ExeName); if (Result.canExecute()) return Result; } Then the call to FindProgramByName was added to append the '.exe' suffix: if (Result.isAbsolute()) { Result = sys::Program::FindProgramByName(Result.str()); return Result; } On Windows, the behaviour is still the same (because FindProgramByName always checks for executability), but on unix-likes FindExecutable now always succeeds (because of the special treatment of absolute paths). IMO, this is a bug. > > > >> What problem are you trying to solve here? > > > > I find the current behaviour confusing and I want it to be consistent across > > platforms. If we decide to standardise on the Unix behaviour, then we should > > also make the Win32 version of FindProgramByName return absolute paths > > untouched, and mention this issue in the comments. > > > Currently my understanding is that it modifies absolute paths by appending a > ".exe" suffix. If there's another way to achieve this, that would probably be > better. I propose the following changes (patches attached): 1. Make FindProgramByName() return absolute paths untouched on all platforms and mention this in the comments. 2. Add a GetEXESuffix() function to the Path class (there is already GetDLLSuffix()). 3. Make FindExecutable() use GetEXESuffix() instead of FindProgramByName(). 4. Make FindExecutable() always return an executable path, as it used to. -- () ascii ribbon campaign - against html e-mail /\ www.asciiribbon.org - against proprietary attachments -------------- next part -------------- A non-text attachment was scrubbed... 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Name: 0004-Make-FindExecutable-always-return-an-executable-path.patch Type: text/x-diff Size: 3100 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/b95177cc/attachment-0003.bin From echristo at apple.com Mon Nov 1 20:21:28 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 02 Nov 2010 01:21:28 -0000 Subject: [llvm-commits] [llvm] r117994 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101102012128.D82EA2A6C12C@llvm.org> Author: echristo Date: Mon Nov 1 20:21:28 2010 New Revision: 117994 URL: http://llvm.org/viewvc/llvm-project?rev=117994&view=rev Log: No really, no thumb1 for arm fast isel. Also add an informative comment as to what someone would need to do to support thumb1. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=117994&r1=117993&r2=117994&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 1 20:21:28 2010 @@ -195,6 +195,9 @@ // If the machine is predicable go ahead and add the predicate operands, if // it needs default CC operands add those. +// TODO: If we want to support thumb1 then we'll need to deal with optional +// CPSR defs that need to be added before the remaining operands. See s_cc_out +// for descriptions why. const MachineInstrBuilder & ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { MachineInstr *MI = &*MIB; @@ -1761,8 +1764,6 @@ // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { - // No Thumb-1 for now. - if (isThumb && !AFI->isThumb2Function()) return false; switch (I->getOpcode()) { case Instruction::Load: @@ -1807,8 +1808,11 @@ llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { // Completely untested on non-darwin. const TargetMachine &TM = funcInfo.MF->getTarget(); + + // Darwin and thumb1 only for now. const ARMSubtarget *Subtarget = &TM.getSubtarget(); - if (Subtarget->isTargetDarwin() && !DisableARMFastISel) + if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && + !DisableARMFastISel) return new ARMFastISel(funcInfo); return 0; } From echristo at apple.com Mon Nov 1 20:22:45 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 02 Nov 2010 01:22:45 -0000 Subject: [llvm-commits] [llvm] r117995 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101102012245.9933A2A6C12C@llvm.org> Author: echristo Date: Mon Nov 1 20:22:45 2010 New Revision: 117995 URL: http://llvm.org/viewvc/llvm-project?rev=117995&view=rev Log: Whitespeace Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=117995&r1=117994&r2=117995&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 1 20:22:45 2010 @@ -682,7 +682,7 @@ } // Try to get this in a register if nothing else has worked. - if (Base == 0) Base = getRegForValue(Obj); + if (Base == 0) Base = getRegForValue(Obj); return Base != 0; } From echristo at apple.com Mon Nov 1 20:24:49 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 02 Nov 2010 01:24:49 -0000 Subject: [llvm-commits] [llvm] r117996 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101102012449.2E6752A6C12C@llvm.org> Author: echristo Date: Mon Nov 1 20:24:49 2010 New Revision: 117996 URL: http://llvm.org/viewvc/llvm-project?rev=117996&view=rev Log: Remove an assert - it's possible to be hit, and we just want to avoid handling those cases for now. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=117996&r1=117995&r2=117996&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 1 20:24:49 2010 @@ -889,7 +889,7 @@ case CmpInst::FCMP_ONE: case CmpInst::FCMP_UEQ: default: - assert(false && "Unhandled CmpInst::Predicate!"); + // AL is our "false" for now. The other two need more compares. return ARMCC::AL; case CmpInst::ICMP_EQ: case CmpInst::FCMP_OEQ: From resistor at mac.com Mon Nov 1 20:24:55 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 01:24:55 -0000 Subject: [llvm-commits] [llvm] r117997 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neon-vld-encoding.s Message-ID: <20101102012456.0AA7C2A6C12C@llvm.org> Author: resistor Date: Mon Nov 1 20:24:55 2010 New Revision: 117997 URL: http://llvm.org/viewvc/llvm-project?rev=117997&view=rev Log: Add correct NEON encodings for vld2, vld3, and vld4 basic variants. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/neon-vld-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117997&r1=117996&r2=117997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Nov 1 20:24:55 2010 @@ -102,6 +102,7 @@ unsigned getMachineSoImmOpValue(unsigned SoImm); unsigned getAddrMode6RegisterOperand(const MachineInstr &MI); + unsigned getAddrMode6OffsetOperand(const MachineInstr &MI); unsigned getAddrModeSBit(const MachineInstr &MI, const TargetInstrDesc &TID) const; @@ -175,6 +176,8 @@ const { return 0; } unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getAddrMode6OffsetOperand(const MachineInstr &MI, unsigned Op) + const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117997&r1=117996&r2=117997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 1 20:24:55 2010 @@ -478,6 +478,7 @@ def am6offset : Operand { let PrintMethod = "printAddrMode6OffsetOperand"; let MIOperandInfo = (ops GPR); + string EncoderMethod = "getAddrMode6OffsetOperand"; } // addrmodepc := pc + reg Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117997&r1=117996&r2=117997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 1 20:24:55 2010 @@ -284,22 +284,28 @@ // VLD2 : Vector Load (multiple 2-element structures) class VLD2D op11_8, bits<4> op7_4, string Dt> - : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr), IIC_VLD2, - "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>; + : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), + (ins addrmode6:$Rn), IIC_VLD2, + "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} class VLD2Q op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD2x2, - "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$Rn), IIC_VLD2x2, + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} -def VLD2d8 : VLD2D<0b1000, 0b0000, "8">; -def VLD2d16 : VLD2D<0b1000, 0b0100, "16">; -def VLD2d32 : VLD2D<0b1000, 0b1000, "32">; - -def VLD2q8 : VLD2Q<0b0000, "8">; -def VLD2q16 : VLD2Q<0b0100, "16">; -def VLD2q32 : VLD2Q<0b1000, "32">; +def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">; +def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">; +def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">; + +def VLD2q8 : VLD2Q<{0,0,?,?}, "8">; +def VLD2q16 : VLD2Q<{0,1,?,?}, "16">; +def VLD2q32 : VLD2Q<{1,0,?,?}, "32">; def VLD2d8Pseudo : VLDQPseudo; def VLD2d16Pseudo : VLDQPseudo; @@ -311,24 +317,28 @@ // ...with address register writeback: class VLD2DWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2u, - "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset", - "$addr.addr = $wb", []>; + : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u, + "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} class VLD2QWB op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2x2u, - "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", - "$addr.addr = $wb", []>; + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u, + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} -def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">; -def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">; -def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">; - -def VLD2q8_UPD : VLD2QWB<0b0000, "8">; -def VLD2q16_UPD : VLD2QWB<0b0100, "16">; -def VLD2q32_UPD : VLD2QWB<0b1000, "32">; +def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">; +def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">; +def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">; + +def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">; +def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">; +def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">; def VLD2d8Pseudo_UPD : VLDQWBPseudo; def VLD2d16Pseudo_UPD : VLDQWBPseudo; @@ -339,22 +349,25 @@ def VLD2q32Pseudo_UPD : VLDQQWBPseudo; // ...with double-spaced registers (for disassembly only): -def VLD2b8 : VLD2D<0b1001, 0b0000, "8">; -def VLD2b16 : VLD2D<0b1001, 0b0100, "16">; -def VLD2b32 : VLD2D<0b1001, 0b1000, "32">; -def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">; -def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">; -def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">; +def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">; +def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">; +def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">; +def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">; +def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">; +def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">; // VLD3 : Vector Load (multiple 3-element structures) class VLD3D op11_8, bits<4> op7_4, string Dt> - : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr), IIC_VLD3, - "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>; - -def VLD3d8 : VLD3D<0b0100, 0b0000, "8">; -def VLD3d16 : VLD3D<0b0100, 0b0100, "16">; -def VLD3d32 : VLD3D<0b0100, 0b1000, "32">; + : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$Rn), IIC_VLD3, + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} + +def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; +def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">; +def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">; def VLD3d8Pseudo : VLDQQPseudo; def VLD3d16Pseudo : VLDQQPseudo; @@ -363,26 +376,28 @@ // ...with address register writeback: class VLD3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3u, - "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset", - "$addr.addr = $wb", []>; + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} -def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">; -def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">; -def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">; +def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; +def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">; +def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">; def VLD3d8Pseudo_UPD : VLDQQWBPseudo; def VLD3d16Pseudo_UPD : VLDQQWBPseudo; def VLD3d32Pseudo_UPD : VLDQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): -def VLD3q8 : VLD3D<0b0101, 0b0000, "8">; -def VLD3q16 : VLD3D<0b0101, 0b0100, "16">; -def VLD3q32 : VLD3D<0b0101, 0b1000, "32">; -def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">; -def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">; -def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">; +def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">; +def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">; +def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">; +def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">; +def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">; +def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">; def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo; def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo; @@ -396,13 +411,16 @@ // VLD4 : Vector Load (multiple 4-element structures) class VLD4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD4, - "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$Rn), IIC_VLD4, + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} -def VLD4d8 : VLD4D<0b0000, 0b0000, "8">; -def VLD4d16 : VLD4D<0b0000, 0b0100, "16">; -def VLD4d32 : VLD4D<0b0000, 0b1000, "32">; +def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; +def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">; +def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">; def VLD4d8Pseudo : VLDQQPseudo; def VLD4d16Pseudo : VLDQQPseudo; @@ -411,26 +429,28 @@ // ...with address register writeback: class VLD4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, - "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", - "$addr.addr = $wb", []>; + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} -def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">; -def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">; -def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">; +def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; +def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">; +def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">; def VLD4d8Pseudo_UPD : VLDQQWBPseudo; def VLD4d16Pseudo_UPD : VLDQQWBPseudo; def VLD4d32Pseudo_UPD : VLDQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): -def VLD4q8 : VLD4D<0b0001, 0b0000, "8">; -def VLD4q16 : VLD4D<0b0001, 0b0100, "16">; -def VLD4q32 : VLD4D<0b0001, 0b1000, "32">; -def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">; -def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">; -def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">; +def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">; +def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">; +def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">; +def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">; +def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">; +def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">; def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo; def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117997&r1=117996&r2=117997&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 1 20:24:55 2010 @@ -100,6 +100,7 @@ unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const; unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const; + unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const; unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); @@ -312,6 +313,14 @@ return RegNo | (Align << 4); } +unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI, + unsigned Op) const { + const MCOperand ®no = MI.getOperand(Op); + if (regno.getReg() == 0) return 0x0D; + return regno.getReg(); +} + + void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=117997&r1=117996&r2=117997&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Nov 1 20:24:55 2010 @@ -17,3 +17,57 @@ vld1.32 {d16, d17}, [r0] @ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] vld1.64 {d16, d17}, [r0] + +@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] + vld2.8 {d16, d17}, [r0, :64] +@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] + vld2.16 {d16, d17}, [r0, :128] +@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] + vld2.32 {d16, d17}, [r0] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4] + vld2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] + vld2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] + vld2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4] + vld3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4] + vld3.16 {d16, d17, d18}, [r0] +@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4] + vld3.32 {d16, d17, d18}, [r0] +@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4] + vld3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4] + vld3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4] + vld3.16 {d16, d18, d20}, [r0]! +@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4] + vld3.16 {d17, d19, d21}, [r0]! +@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4] + vld3.32 {d16, d18, d20}, [r0]! +@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4] + vld3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf4] + vld4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf4] + vld4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf4] + vld4.32 {d16, d17, d18, d19}, [r0, :256] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf4] + vld4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf4] + vld4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4] + vld4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4] + vld4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4] + vld4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] + vld4.32 {d17, d19, d21, d23}, [r0]! + + + \ No newline at end of file From echristo at apple.com Mon Nov 1 22:52:29 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 1 Nov 2010 20:52:29 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r117934 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <20101101173723.69A3F2A6C12C@llvm.org> References: <20101101173723.69A3F2A6C12C@llvm.org> Message-ID: <491B6BA9-C313-4D27-A9A5-D442F874B641@apple.com> On Nov 1, 2010, at 10:37 AM, Bob Wilson wrote: > I don't know so much about synchronization on other targets besides ARM, and > since there was already a separate version of the barriers for ARM/Darwin, > I've only changed that version. It seems like this change would apply to > other targets as well, but I don't know for sure. x86 largely uses the lock prefix to handle this sort of thing as opposed to emitting a memory barrier instruction (mfence, lfence, sfence). This change in particular isn't real interesting for x86 since we'll still just use an mfence there I think. :) -eric From jasonwkim at google.com Mon Nov 1 23:04:26 2010 From: jasonwkim at google.com (Jason Kim) Date: Mon, 1 Nov 2010 21:04:26 -0700 Subject: [llvm-commits] [PATCH] ARM/MC/ELF Relocation Stubs/Refactoring Message-ID: Hi everyone, please find enclosed two patches in sequence They need to be applied together, but I broke them into two pieces for (hopefully) easier comprehension. They both are hg mq patches, but they should apply cleanly (in sequence) to trunk with patch -p1 The patches are for adding relocation support to ARM/MC. They required slight changes to the TargetELFWriterInfo hierarchy as well as modifications to the ELFWriter class. The first patch arm-mc-elf-s07 changes the getRelocationType() to take the MachineRelocation and ELFSection instances directly. This allows for the second patch arm-mc-elf-s07-tew - RelocateField() now dispatches to a new class/method TargetELFRelocHelper::RelocateField() to handle the non-simple relocations used (if any). The rationale for these is to support the various non-simple (i.e. not just a 32/64bit sequential blob) - relocation types mandated by the ARM architecture manual. There are over 100 of these relocation types, and selecting the actual ELF32_R_TYPE() field depends on the actual instruction sequence - and the most obvious way to do this is to examine the ELFSection& object directly. There are several alternate ways to do this, but for the sake of a discussion starter, I chose the most straight forward way which was to make the ELFSecton object visible to the getRelocationType() routine. There might be additional refactoring to make the code "neater" (perhaps moving isolating the arch-specific stuff completely to the new helper class?), but hopefully this will be a good enough as a starting point for discussion. The two diffviews are at http://codereview.chromium.org/4294001 http://codereview.chromium.org/4295001 The patches do not change any code behavior. Feedback is greatly appreciated. Thanks! -jason -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf-s07 Type: application/octet-stream Size: 7104 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101101/b920b321/attachment-0002.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf-s07-tew Type: application/octet-stream Size: 8511 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101101/b920b321/attachment-0003.obj From tonic at nondot.org Mon Nov 1 23:40:28 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:40:28 -0000 Subject: [llvm-commits] [www] r118004 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044028.5989D2A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:40:28 2010 New Revision: 118004 URL: http://llvm.org/viewvc/llvm-project?rev=118004&view=rev Log: Add schedule. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118004&r1=118003&r2=118004&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:40:28 2010 @@ -47,29 +47,39 @@

You will find the meeting location, times, and other important information on the Registration Website. -

Tentative Agenda
- -

The following is a tentative list of schedule talks (more information to come):

+
Agenda
- - - - - - - - - - - - - - - - - - + + + +Almaden Ballroom + + + + + + + + + + + + + + + + + + + + + + + + + +
Talk TitleSpeaker
LLDBGreg Clayton
Symbolic Crosschecking of Floating-Point and SIMD CodePeter Collingbourne, Imperial College London
The LLVM Assembler & Machine Code InfrastructureDaniel Dunbar
Connecting the EDG front-end to LLVMRenato Golin, ARM
libclang: Thinking Beyond the CompilerDoug Gregor
LLVM for Open Shading LanguageLarry Gritz, Sony Pictures Imageworks
Polly - Polyhedral optimizations in LLVMTobias Grosser, University of Passau
libc++Howard Hinnant
Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardwareJames Kempf, Ericsson Research Silicon Valley
The Crack Scripting LanguageMichael Muller, Google
Creating cling, an interactive interpreter interface for clangAxel Naumann, CERN
C-to-Verilog.com : High-level synthesis using LLVMNadav Rotem, Haifa University
Portable Native ClientDavid Sehr, Google
Implementing Include-What-You-Use using clangCraig Silverstein, Google
Object Files in LLVMMichael Spencer, Gainsville U
AMD OpenCL Compiler ??? Using LLVM to produce a cross-platform heterogeneous compiler tool chain.Micah Villmow, AMD Inc.
Hardening LLVM With Random TestingXuejun Yang, University of Utah
TimeTalkLocation
8:00 - 8:45BreakfastMarket Room
>8:45 - 9:00Welcome
Chris Lattner, Apple Inc.
9:00 - 9:40Portable Native Client
David Sehr, Google
9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
Micah Villmow, AMD Inc.		Almaden Ballroom
Implementing Include-What-You-Use using clang
Craig Silverstein, Google		Winchester Room
Debugging Information BOF
Devang Patel, Apple Inc.		Market Room
10:20 - 10:50BreakMarket Room
10:50 - 11:30libclang: Thinking Beyond the Compiler
Doug Gregor, Apple Inc.		Almaden Ballroom
Polly - Polyhedral optimizations in LLVM
Tobias Grosser , University of Passau		Winchester Room
11:30 - 12:10libc++: A Standard Library for C++0x
Howard Hinnant, Apple Inc.		Almaden Room
Symbolic Crosschecking of Floating-Point and SIMD Code
Peter Collingbourne, Imperial College London		Winchester Room
12:10 - 1:20LunchMarket Room
1:20 - 2:00The LLVM Assembler & Machine Code Infrastructure
Daniel Dunbar, Apple Inc.		Almaden Ballroom
Creating cling, an interactive interpreter interface for clang
Axel Naumann, CERN		Winchester Room
OpenCL BOF
Alasdair Grant, ARM		Market Room
2:00 - 2:40>LLDB: Modular Debugging Infrastructure
Greg Clayton, Apple Inc.		Almaden Ballroom
The Crack Scripting Language
Michael Muller, Google		Winchester Room
ARM-MC and EABI support BOF
Renato Golin, ARM		Market Room
2:40 - 3:20Hardening LLVM With Random Testing
Xuejun Yang, University of Utah		Almaden Ballroom
C-to-Verilog.com : High-level synthesis using LLVM
Nadav Rotem, Haifa University		Winchester Room
3:20 - 3:50BreakMarket Room
3:50 - 4:30Object Files in LLVM
Michael Spencer, Gainsville University		Almaden Ballroom
Connecting the EDG front-end to LLVM
Renato Golin, ARM		Almaden Ballroom
Building Linux BOF
Taylor Simpson, QuIC		Market Room
4:30 - 5:10LLVM for Open Shading Language
Larry Gritz, Sony Pictures Imageworks		Almaden Ballroom
Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
James Kempf, Ericsson Research Silicon Valley		Winchester Room
Optimizations BOF
Taylor Simpson, QuIC		Market Room
6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required)
From tonic at nondot.org Mon Nov 1 23:41:59 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:41:59 -0000 Subject: [llvm-commits] [www] r118005 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044159.CEF252A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:41:59 2010 New Revision: 118005 URL: http://llvm.org/viewvc/llvm-project?rev=118005&view=rev Log: Fix typo. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118005&r1=118004&r2=118005&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:41:59 2010 @@ -53,7 +53,7 @@ TimeTalkLocation 8:00 - 8:45BreakfastMarket Room ->8:45 - 9:00Welcome
Chris Lattner, Apple Inc.Almaden Ballroom +8:45 - 9:00Welcome
Chris Lattner, Apple Inc.Almaden Ballroom 9:00 - 9:40Portable Native Client
David Sehr, Google 9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
Micah Villmow, AMD Inc.Almaden Ballroom Implementing Include-What-You-Use using clang
Craig Silverstein, GoogleWinchester Room From tonic at nondot.org Mon Nov 1 23:43:18 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:43:18 -0000 Subject: [llvm-commits] [www] r118006 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044318.58F0C2A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:43:18 2010 New Revision: 118006 URL: http://llvm.org/viewvc/llvm-project?rev=118006&view=rev Log: More cleanups Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118006&r1=118005&r2=118006&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:43:18 2010 @@ -5,7 +5,7 @@
  1. Registration & Logistics
    2. -
  2. Tentative Agenda
    3. +
  3. Agenda
    @@ -39,11 +39,7 @@
    Registration & Logistics
    -

    The deadline for registration is October 21, 2010 or if we reach 200 attendees before this deadline.

    - -

    Please only register if you are confident that you are able to attend the meeting. Last year, we had a large percentage of attendees register without attending. If this continues, will need to start charging attendees to cover the costs associated with the meeting. Thank you!

    - -

    Please visit our Registration Website to register and book hotel rooms at the meeting location. We have a room block and you will only get the reduced rate if you book your hotel through the registration process.

    +

    Registration is full for the meeting.

    You will find the meeting location, times, and other important information on the Registration Website. From tonic at nondot.org Mon Nov 1 23:44:00 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:44:00 -0000 Subject: [llvm-commits] [www] r118007 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044400.4D68E2A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:44:00 2010 New Revision: 118007 URL: http://llvm.org/viewvc/llvm-project?rev=118007&view=rev Log: Fix typo. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118007&r1=118006&r2=118007&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:44:00 2010 @@ -49,7 +49,7 @@ TimeTalkLocation 8:00 - 8:45BreakfastMarket Room -8:45 - 9:00Welcome
    Chris Lattner, Apple Inc.Almaden Ballroom +8:45 - 9:00Welcome
    Chris Lattner, Apple Inc.Almaden Ballroom 9:00 - 9:40Portable Native Client
    David Sehr, Google 9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
    Micah Villmow, AMD Inc.Almaden Ballroom Implementing Include-What-You-Use using clang
    Craig Silverstein, GoogleWinchester Room From tonic at nondot.org Mon Nov 1 23:44:41 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:44:41 -0000 Subject: [llvm-commits] [www] r118008 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044442.065BD2A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:44:41 2010 New Revision: 118008 URL: http://llvm.org/viewvc/llvm-project?rev=118008&view=rev Log: Fix table. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118008&r1=118007&r2=118008&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:44:41 2010 @@ -49,7 +49,7 @@ TimeTalkLocation 8:00 - 8:45BreakfastMarket Room -8:45 - 9:00Welcome
    Chris Lattner, Apple Inc.Almaden Ballroom +8:45 - 9:00Welcome
    Chris Lattner, Apple Inc.Almaden Ballroom 9:00 - 9:40Portable Native Client
    David Sehr, Google 9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
    Micah Villmow, AMD Inc.Almaden Ballroom Implementing Include-What-You-Use using clang
    Craig Silverstein, GoogleWinchester Room From tonic at nondot.org Mon Nov 1 23:45:19 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:45:19 -0000 Subject: [llvm-commits] [www] r118009 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044519.DD9CC2A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:45:19 2010 New Revision: 118009 URL: http://llvm.org/viewvc/llvm-project?rev=118009&view=rev Log: Fix table. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118009&r1=118008&r2=118009&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:45:19 2010 @@ -50,7 +50,7 @@ 8:00 - 8:45BreakfastMarket Room 8:45 - 9:00Welcome
    Chris Lattner, Apple Inc.Almaden Ballroom -9:00 - 9:40Portable Native Client
    David Sehr, Google +9:00 - 9:40Portable Native Client
    David Sehr, GoogleAlmaden Ballroom 9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
    Micah Villmow, AMD Inc.Almaden Ballroom Implementing Include-What-You-Use using clang
    Craig Silverstein, GoogleWinchester Room Debugging Information BOF
    Devang Patel, Apple Inc.Market Room From tonic at nondot.org Mon Nov 1 23:48:01 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:48:01 -0000 Subject: [llvm-commits] [www] r118010 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102044801.B0A4B2A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:48:01 2010 New Revision: 118010 URL: http://llvm.org/viewvc/llvm-project?rev=118010&view=rev Log: Fixing typos. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118010&r1=118009&r2=118010&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:48:01 2010 @@ -63,13 +63,13 @@ 1:20 - 2:00The LLVM Assembler & Machine Code Infrastructure
    Daniel Dunbar, Apple Inc.Almaden Ballroom Creating cling, an interactive interpreter interface for clang
    Axel Naumann, CERNWinchester Room OpenCL BOF
    Alasdair Grant, ARMMarket Room -2:00 - 2:40>LLDB: Modular Debugging Infrastructure
    Greg Clayton, Apple Inc.Almaden Ballroom +2:00 - 2:40>LLDB: Modular Debugging Infrastructure
    Greg Clayton, Apple Inc.Almaden Ballroom The Crack Scripting Language
    Michael Muller, GoogleWinchester Room ARM-MC and EABI support BOF
    Renato Golin, ARMMarket Room 2:40 - 3:20Hardening LLVM With Random Testing
    Xuejun Yang, University of UtahAlmaden Ballroom C-to-Verilog.com : High-level synthesis using LLVM
    Nadav Rotem, Haifa UniversityWinchester Room 3:20 - 3:50BreakMarket Room -3:50 - 4:30Object Files in LLVM
    Michael Spencer, Gainsville UniversityAlmaden Ballroom +3:50 - 4:30Object Files in LLVM
    Michael Spencer, Gainsville UniversityAlmaden Ballroom Connecting the EDG front-end to LLVM
    Renato Golin, ARMAlmaden Ballroom Building Linux BOF
    Taylor Simpson, QuICMarket Room 4:30 - 5:10LLVM for Open Shading Language
    Larry Gritz, Sony Pictures ImageworksAlmaden Ballroom From tonic at nondot.org Mon Nov 1 23:53:50 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 04:53:50 -0000 Subject: [llvm-commits] [www] r118011 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102045350.8BFE72A6C12C@llvm.org> Author: tbrethou Date: Mon Nov 1 23:53:50 2010 New Revision: 118011 URL: http://llvm.org/viewvc/llvm-project?rev=118011&view=rev Log: Fix typo. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118011&r1=118010&r2=118011&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Mon Nov 1 23:53:50 2010 @@ -63,7 +63,7 @@ 1:20 - 2:00The LLVM Assembler & Machine Code Infrastructure
    Daniel Dunbar, Apple Inc.Almaden Ballroom Creating cling, an interactive interpreter interface for clang
    Axel Naumann, CERNWinchester Room OpenCL BOF
    Alasdair Grant, ARMMarket Room -2:00 - 2:40>LLDB: Modular Debugging Infrastructure
    Greg Clayton, Apple Inc.Almaden Ballroom +2:00 - 2:40LLDB: Modular Debugging Infrastructure
    Greg Clayton, Apple Inc.Almaden Ballroom The Crack Scripting Language
    Michael Muller, GoogleWinchester Room ARM-MC and EABI support BOF
    Renato Golin, ARMMarket Room 2:40 - 3:20Hardening LLVM With Random Testing
    Xuejun Yang, University of UtahAlmaden Ballroom From aggarwa4 at illinois.edu Tue Nov 2 02:24:21 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 02 Nov 2010 07:24:21 -0000 Subject: [llvm-commits] [poolalloc] r118012 - /poolalloc/trunk/test/pa/clone/AttrTest.ll Message-ID: <20101102072421.394E02A6C12C@llvm.org> Author: aggarwa4 Date: Tue Nov 2 02:24:21 2010 New Revision: 118012 URL: http://llvm.org/viewvc/llvm-project?rev=118012&view=rev Log: Make function linkage internal. If it is not so, it gets the E flag, making poolalloc, not assign pools Modified: poolalloc/trunk/test/pa/clone/AttrTest.ll Modified: poolalloc/trunk/test/pa/clone/AttrTest.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/clone/AttrTest.ll?rev=118012&r1=118011&r2=118012&view=diff ============================================================================== --- poolalloc/trunk/test/pa/clone/AttrTest.ll (original) +++ poolalloc/trunk/test/pa/clone/AttrTest.ll Tue Nov 2 02:24:21 2010 @@ -13,7 +13,7 @@ unreachable } -define void @attr(i16 zeroext %IntParam, i8** nocapture %NeedsPool) { +define internal void @attr(i16 zeroext %IntParam, i8** nocapture %NeedsPool) { entry: unreachable } From clchiou at gmail.com Tue Nov 2 04:17:37 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Tue, 2 Nov 2010 17:17:37 +0800 Subject: [llvm-commits] [PATCH][Target/PTX] Add new hooks for register MCStreamer for assembly text In-Reply-To: References: Message-ID: I will submit by tomorrow if no further comments. On Thu, Oct 28, 2010 at 10:19 PM, Che-Liang Chiou wrote: > Re-send patch. > > On Mon, Oct 25, 2010 at 12:30 PM, Che-Liang Chiou wrote: >> Hi there, >> >> This patch adds new hooks for registering MCStreamer in class Target >> (for assembly text). ?It is tested against SVN revision 117227. ?I >> will send a separate patch for PTX's MCStreamer implementation of its >> assembly text output. >> >> Regards, >> Che-Liang >> > From baldrick at free.fr Tue Nov 2 07:25:33 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Nov 2010 13:25:33 +0100 Subject: [llvm-commits] PATCH: llvm-gcc option to emit "va_arg" instruction In-Reply-To: References: <2CC138C3-4628-400A-AAEF-A030A21843A2@apple.com> <2646F00C-CDF0-402D-8C90-561B2C4B3B45@apple.com> <146F714B-AF1A-462F-B3F9-003E6EB2AE7D@apple.com> <4CB765E1.7060208@free.fr> <4CB9974A.5020004@free.fr> Message-ID: <4CD0033D.2000102@free.fr> The attached patch just passes va_arg through. Unfortunately bootstrap fails, not because the compiler crashes but because the genmddeps tool built by the new compiler crashes, i.e. there is a miscompilation. But perhaps that would also happen with the builtin version? Ciao, Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: vaarg.diff Type: text/x-patch Size: 3395 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/0b536f0d/attachment.bin From baldrick at free.fr Tue Nov 2 08:43:07 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Nov 2010 13:43:07 -0000 Subject: [llvm-commits] [llvm] r118013 - /llvm/trunk/include/llvm/CodeGen/ValueTypes.h Message-ID: <20101102134307.860572A6C12C@llvm.org> Author: baldrick Date: Tue Nov 2 08:43:07 2010 New Revision: 118013 URL: http://llvm.org/viewvc/llvm-project?rev=118013&view=rev Log: Remove trailing whitespace. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=118013&r1=118012&r2=118013&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Nov 2 08:43:07 2010 @@ -126,13 +126,13 @@ MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {} MVT(SimpleValueType SVT) : SimpleTy(SVT) { } - + bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; } bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; } bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; } bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; } bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; } - + /// isFloatingPoint - Return true if this is a FP, or a vector FP type. bool isFloatingPoint() const { return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) || @@ -151,7 +151,7 @@ return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE && SimpleTy <= MVT::LAST_VECTOR_VALUETYPE); } - + /// isPow2VectorType - Returns true if the given vector is a power of 2. bool isPow2VectorType() const { unsigned NElts = getVectorNumElements(); @@ -174,7 +174,7 @@ MVT getScalarType() const { return isVector() ? getVectorElementType() : *this; } - + MVT getVectorElementType() const { switch (SimpleTy) { default: @@ -202,7 +202,7 @@ case v4f64: return f64; } } - + unsigned getVectorNumElements() const { switch (SimpleTy) { default: @@ -230,7 +230,7 @@ case v1i64: return 1; } } - + unsigned getSizeInBits() const { switch (SimpleTy) { case iPTR: @@ -276,7 +276,7 @@ case v8i64: return 512; } } - + static MVT getFloatingPointVT(unsigned BitWidth) { switch (BitWidth) { default: @@ -291,7 +291,7 @@ return MVT::f128; } } - + static MVT getIntegerVT(unsigned BitWidth) { switch (BitWidth) { default: @@ -310,7 +310,7 @@ return MVT::i128; } } - + static MVT getVectorVT(MVT VT, unsigned NumElements) { switch (VT.SimpleTy) { default: @@ -530,7 +530,7 @@ EVT getScalarType() const { return isVector() ? getVectorElementType() : *this; } - + /// getVectorElementType - Given a vector type, return the type of /// each element. EVT getVectorElementType() const { From baldrick at free.fr Tue Nov 2 08:57:10 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Nov 2010 13:57:10 -0000 Subject: [llvm-commits] [llvm] r118014 - /llvm/trunk/include/llvm/CodeGen/ValueTypes.h Message-ID: <20101102135710.14D3D2A6C12C@llvm.org> Author: baldrick Date: Tue Nov 2 08:57:09 2010 New Revision: 118014 URL: http://llvm.org/viewvc/llvm-project?rev=118014&view=rev Log: Add some comments explaining what MVT and EVT are, and how they differ. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=118014&r1=118013&r2=118014&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Nov 2 08:57:09 2010 @@ -26,7 +26,10 @@ class LLVMContext; struct EVT; - class MVT { // MVT = Machine Value Type + /// MVT - Machine Value Type. Every type that is supported natively by some + /// processor targeted by LLVM occurs here. This means that any legal value + /// type can be represented by a MVT. + class MVT { public: enum SimpleValueType { // If you change this numbering, you must change the values in @@ -158,7 +161,7 @@ return !(NElts & (NElts - 1)); } - /// getPow2VectorType - Widens the length of the given vector EVT up to + /// getPow2VectorType - Widens the length of the given vector MVT up to /// the nearest power of 2 and returns that type. MVT getPow2VectorType() const { if (isPow2VectorType()) @@ -353,7 +356,11 @@ } }; - struct EVT { // EVT = Extended Value Type + + /// EVT - Extended Value Type. Capable of holding value types which are not + /// native for any processor (such as the i12345 type), as well as the types + /// a MVT can represent. + struct EVT { private: MVT V; const Type *LLVMTy; From rafael.espindola at gmail.com Tue Nov 2 09:25:15 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 2 Nov 2010 10:25:15 -0400 Subject: [llvm-commits] PATCH: llvm-gcc option to emit "va_arg" instruction In-Reply-To: <4CD0033D.2000102@free.fr> References: <2CC138C3-4628-400A-AAEF-A030A21843A2@apple.com> <2646F00C-CDF0-402D-8C90-561B2C4B3B45@apple.com> <146F714B-AF1A-462F-B3F9-003E6EB2AE7D@apple.com> <4CB765E1.7060208@free.fr> <4CB9974A.5020004@free.fr> <4CD0033D.2000102@free.fr> Message-ID: 2010/11/2 Duncan Sands : > The attached patch just passes va_arg through. ?Unfortunately bootstrap > fails, > not because the compiler crashes but because the genmddeps tool built by the > new compiler crashes, i.e. there is a miscompilation. ?But perhaps that > would > also happen with the builtin version? My first impression is that they are equivalent, other than the fact that your patches enables it :-) It is too soon to enable it for all architectures as the va_arg implementation is incomplete. We need some way to do it in a target by target basis. Not sure if va_arg is feature complete in any target at the moment... > Ciao, > > Duncan. > Cheers, Rafael From rafael.espindola at gmail.com Tue Nov 2 09:31:12 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 2 Nov 2010 10:31:12 -0400 Subject: [llvm-commits] [PATCH][Target/PTX] Add new hooks for register MCStreamer for assembly text In-Reply-To: References: Message-ID: On 2 November 2010 05:17, Che-Liang Chiou wrote: > I will submit by tomorrow if no further comments. Why do you need a different streamer? The syntax is too different? hasAsmStreamer is unused. Do you need RegisterAsmStreamer? Can you make AsmStreamerCtorFn an argument to the Target constructor (with a default value)? Cheers, Rafael From baldrick at free.fr Tue Nov 2 10:12:48 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 02 Nov 2010 15:12:48 -0000 Subject: [llvm-commits] [llvm] r118016 - /llvm/trunk/include/llvm-c/LinkTimeOptimizer.h Message-ID: <20101102151248.A0BF12A6C12C@llvm.org> Author: baldrick Date: Tue Nov 2 10:12:48 2010 New Revision: 118016 URL: http://llvm.org/viewvc/llvm-project?rev=118016&view=rev Log: Fix comment typo. Modified: llvm/trunk/include/llvm-c/LinkTimeOptimizer.h Modified: llvm/trunk/include/llvm-c/LinkTimeOptimizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/LinkTimeOptimizer.h?rev=118016&r1=118015&r2=118016&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/LinkTimeOptimizer.h (original) +++ llvm/trunk/include/llvm-c/LinkTimeOptimizer.h Tue Nov 2 10:12:48 2010 @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // // This header provides a C API to use the LLVM link time optimization -// library. This is inteded to be used by linkers which are C-only in +// library. This is intended to be used by linkers which are C-only in // their implementation for performing LTO. // //===----------------------------------------------------------------------===// From dpatel at apple.com Tue Nov 2 12:01:30 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 02 Nov 2010 17:01:30 -0000 Subject: [llvm-commits] [llvm] r118020 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/X86/2010-11-02-DbgParameter.ll Message-ID: <20101102170130.7E4D92A6C12C@llvm.org> Author: dpatel Date: Tue Nov 2 12:01:30 2010 New Revision: 118020 URL: http://llvm.org/viewvc/llvm-project?rev=118020&view=rev Log: Use frameindex, if available, as a last resort to emit debug info for a parameter. Added: llvm/trunk/test/CodeGen/X86/2010-11-02-DbgParameter.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118020&r1=118019&r2=118020&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Nov 2 12:01:30 2010 @@ -3944,6 +3944,9 @@ return false; MachineFunction &MF = DAG.getMachineFunction(); + const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); + // Ignore inlined function arguments here. DIVariable DV(Variable); if (DV.isInlinedFnArgument(MF.getFunction())) @@ -3957,7 +3960,6 @@ if (Arg->hasByValAttr()) { // Byval arguments' frame index is recorded during argument lowering. // Use this info directly. - const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); Reg = TRI->getFrameRegister(MF); Offset = FuncInfo.getByValArgumentFrameIndex(Arg); // If byval argument ofset is not recorded then ignore this. @@ -3976,13 +3978,22 @@ } if (!Reg) { + // Check if ValueMap has reg number. DenseMap::iterator VMI = FuncInfo.ValueMap.find(V); if (VMI == FuncInfo.ValueMap.end()) return false; Reg = VMI->second; } - const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); + if (!Reg && N.getNode()) + // Check if frame index is available. + if (LoadSDNode *LNode = dyn_cast(N.getNode())) + if (FrameIndexSDNode *FINode = + dyn_cast(LNode->getBasePtr().getNode())) { + Reg = TRI->getFrameRegister(MF); + Offset = FINode->getIndex(); + } + MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE)) .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); Added: llvm/trunk/test/CodeGen/X86/2010-11-02-DbgParameter.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-11-02-DbgParameter.ll?rev=118020&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-11-02-DbgParameter.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-11-02-DbgParameter.ll Tue Nov 2 12:01:30 2010 @@ -0,0 +1,35 @@ +; RUN: llc -O2 -asm-verbose < %s | FileCheck %s +; Radar 8616981 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin11.0.0" + +%struct.bar = type { i32, i32 } + +define i32 @foo(%struct.bar* nocapture %i) nounwind readnone optsize noinline ssp { +; CHECK: TAG_formal_parameter +entry: + tail call void @llvm.dbg.value(metadata !{%struct.bar* %i}, i64 0, metadata !6), !dbg !12 + ret i32 1, !dbg !13 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} +!llvm.dbg.lv.foo = !{!6} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"one.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"one.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 117922)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 590081, metadata !0, metadata !"i", metadata !1, i32 3, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!7 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 589843, metadata !1, metadata !"bar", metadata !1, i32 2, i64 64, i64 32, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{metadata !10, metadata !11} +!10 = metadata !{i32 589837, metadata !1, metadata !"x", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!11 = metadata !{i32 589837, metadata !1, metadata !"y", metadata !1, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!12 = metadata !{i32 3, i32 47, metadata !0, null} +!13 = metadata !{i32 4, i32 2, metadata !14, null} +!14 = metadata !{i32 589835, metadata !0, i32 3, i32 50, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] From dpatel at apple.com Tue Nov 2 12:19:04 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 02 Nov 2010 17:19:04 -0000 Subject: [llvm-commits] [llvm] r118022 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20101102171904.2D2AA2A6C12C@llvm.org> Author: dpatel Date: Tue Nov 2 12:19:03 2010 New Revision: 118022 URL: http://llvm.org/viewvc/llvm-project?rev=118022&view=rev Log: If value map does not have register for an argument then try to find frame index before giving up. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118022&r1=118021&r2=118022&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Nov 2 12:19:03 2010 @@ -3980,12 +3980,11 @@ if (!Reg) { // Check if ValueMap has reg number. DenseMap::iterator VMI = FuncInfo.ValueMap.find(V); - if (VMI == FuncInfo.ValueMap.end()) - return false; - Reg = VMI->second; + if (VMI != FuncInfo.ValueMap.end()) + Reg = VMI->second; } - - if (!Reg && N.getNode()) + + if (!Reg && N.getNode()) { // Check if frame index is available. if (LoadSDNode *LNode = dyn_cast(N.getNode())) if (FrameIndexSDNode *FINode = @@ -3993,6 +3992,10 @@ Reg = TRI->getFrameRegister(MF); Offset = FINode->getIndex(); } + } + + if (!Reg) + return false; MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE)) From rafael.espindola at gmail.com Tue Nov 2 12:22:24 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 02 Nov 2010 17:22:24 -0000 Subject: [llvm-commits] [llvm] r118023 - in /llvm/trunk: include/llvm/MC/MCAssembler.h include/llvm/MC/MCObjectStreamer.h include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCAssembler.cpp lib/MC/MCDwarf.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCObjectStreamer.cpp lib/MC/MCParser/AsmParser.cpp lib/MC/MCStreamer.cpp test/MC/ELF/leb128.s Message-ID: <20101102172225.1275F2A6C12C@llvm.org> Author: rafael Date: Tue Nov 2 12:22:24 2010 New Revision: 118023 URL: http://llvm.org/viewvc/llvm-project?rev=118023&view=rev Log: Add support for expressions in .sleb/.uleb directives. Added: llvm/trunk/test/MC/ELF/leb128.s Modified: llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/include/llvm/MC/MCObjectStreamer.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/MC/MCLoggingStreamer.cpp llvm/trunk/lib/MC/MCNullStreamer.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Tue Nov 2 12:22:24 2010 @@ -50,7 +50,8 @@ FT_Fill, FT_Inst, FT_Org, - FT_Dwarf + FT_Dwarf, + FT_LEB }; private: @@ -338,6 +339,40 @@ static bool classof(const MCOrgFragment *) { return true; } }; +class MCLEBFragment : public MCFragment { + /// Value - The value this fragment should contain. + const MCExpr *Value; + + /// IsSigned - True if this is a sleb128, false if uleb128. + bool IsSigned; + + /// Size - The current size estimate. + uint64_t Size; + +public: + MCLEBFragment(const MCExpr &Value_, bool IsSigned_, MCSectionData *SD) + : MCFragment(FT_LEB, SD), + Value(&Value_), IsSigned(IsSigned_), Size(1) {} + + /// @name Accessors + /// @{ + + const MCExpr &getValue() const { return *Value; } + + bool isSigned() const { return IsSigned; } + + uint64_t getSize() const { return Size; } + + void setSize(uint64_t Size_) { Size = Size_; } + + /// @} + + static bool classof(const MCFragment *F) { + return F->getKind() == MCFragment::FT_LEB; + } + static bool classof(const MCLEBFragment *) { return true; } +}; + class MCDwarfLineAddrFragment : public MCFragment { /// LineDelta - the value of the difference between the two line numbers /// between two .loc dwarf directives. @@ -677,6 +712,12 @@ /// were adjusted. bool LayoutOnce(const MCObjectWriter &Writer, MCAsmLayout &Layout); + bool RelaxInstruction(const MCObjectWriter &Writer, MCAsmLayout &Layout, + MCInstFragment &IF); + + bool RelaxLEB(const MCObjectWriter &Writer, MCAsmLayout &Layout, + MCLEBFragment &IF); + /// FinishLayout - Finalize a layout, including fragment lowering. void FinishLayout(MCAsmLayout &Layout); Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Tue Nov 2 12:22:24 2010 @@ -60,6 +60,8 @@ /// @name MCStreamer Interface /// @{ + virtual void EmitULEB128Value(const MCExpr *Value, unsigned AddrSpace = 0); + virtual void EmitSLEB128Value(const MCExpr *Value, unsigned AddrSpace = 0); virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void SwitchSection(const MCSection *Section); virtual void EmitInstruction(const MCInst &Inst); Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Nov 2 12:22:24 2010 @@ -244,13 +244,20 @@ virtual void EmitIntValue(uint64_t Value, unsigned Size, unsigned AddrSpace = 0); - /// EmitULEB128Value - Special case of EmitValue that takes an ULEB128 and - /// emits the needed bytes for the encoded value. - virtual void EmitULEB128Value(uint64_t Value, unsigned AddrSpace = 0); - - /// EmitSLEB128Value - Special case of EmitValue that takes an SLEB128 and - /// emits the needed bytes for the encoded value. - virtual void EmitSLEB128Value(int64_t Value, unsigned AddrSpace = 0); + + virtual void EmitULEB128Value(const MCExpr *Value, + unsigned AddrSpace = 0) = 0; + + virtual void EmitSLEB128Value(const MCExpr *Value, + unsigned AddrSpace = 0) = 0; + + /// EmitULEB128Value - Special case of EmitULEB128Value that avoids the + /// client having to pass in a MCExpr for constant integers. + virtual void EmitULEB128IntValue(uint64_t Value, unsigned AddrSpace = 0); + + /// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the + /// client having to pass in a MCExpr for constant integers. + virtual void EmitSLEB128IntValue(int64_t Value, unsigned AddrSpace = 0); /// EmitSymbolValue - Special case of EmitValue that avoids the client /// having to pass in a MCExpr for MCSymbols. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue Nov 2 12:22:24 2010 @@ -141,7 +141,13 @@ virtual void EmitBytes(StringRef Data, unsigned AddrSpace); virtual void EmitValue(const MCExpr *Value, unsigned Size,unsigned AddrSpace); + virtual void EmitIntValue(uint64_t Value, unsigned Size, unsigned AddrSpace); + + virtual void EmitULEB128Value(const MCExpr *Value, unsigned AddrSpace = 0); + + virtual void EmitSLEB128Value(const MCExpr *Value, unsigned AddrSpace = 0); + virtual void EmitGPRel32Value(const MCExpr *Value); @@ -505,6 +511,16 @@ EmitEOL(); } +void MCAsmStreamer::EmitULEB128Value(const MCExpr *Value, unsigned AddrSpace) { + OS << ".uleb " << *Value; + EmitEOL(); +} + +void MCAsmStreamer::EmitSLEB128Value(const MCExpr *Value, unsigned AddrSpace) { + OS << ".sleb " << *Value; + EmitEOL(); +} + void MCAsmStreamer::EmitGPRel32Value(const MCExpr *Value) { assert(MAI.getGPRel32Directive() != 0); OS << MAI.getGPRel32Directive() << *Value; Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Nov 2 12:22:24 2010 @@ -318,6 +318,9 @@ case MCFragment::FT_Inst: return cast(F).getInstSize(); + case MCFragment::FT_LEB: + return cast(F).getSize(); + case MCFragment::FT_Align: { const MCAlignFragment &AF = cast(F); @@ -514,6 +517,23 @@ llvm_unreachable("unexpected inst fragment after lowering"); break; + case MCFragment::FT_LEB: { + MCLEBFragment &LF = cast(F); + + // FIXME: It is probably better if we don't call EvaluateAsAbsolute in + // here. + int64_t Value; + LF.getValue().EvaluateAsAbsolute(Value, &Layout); + SmallString<32> Tmp; + raw_svector_ostream OSE(Tmp); + if (LF.isSigned()) + MCObjectWriter::EncodeSLEB128(Value, OSE); + else + MCObjectWriter::EncodeULEB128(Value, OSE); + OW->WriteBytes(OSE.str()); + break; + } + case MCFragment::FT_Org: { MCOrgFragment &OF = cast(F); @@ -781,6 +801,63 @@ return false; } +bool MCAssembler::RelaxInstruction(const MCObjectWriter &Writer, + MCAsmLayout &Layout, + MCInstFragment &IF) { + if (!FragmentNeedsRelaxation(Writer, &IF, Layout)) + return false; + + ++stats::RelaxedInstructions; + + // FIXME-PERF: We could immediately lower out instructions if we can tell + // they are fully resolved, to avoid retesting on later passes. + + // Relax the fragment. + + MCInst Relaxed; + getBackend().RelaxInstruction(IF.getInst(), Relaxed); + + // Encode the new instruction. + // + // FIXME-PERF: If it matters, we could let the target do this. It can + // probably do so more efficiently in many cases. + SmallVector Fixups; + SmallString<256> Code; + raw_svector_ostream VecOS(Code); + getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups); + VecOS.flush(); + + // Update the instruction fragment. + int SlideAmount = Code.size() - IF.getInstSize(); + IF.setInst(Relaxed); + IF.getCode() = Code; + IF.getFixups().clear(); + // FIXME: Eliminate copy. + for (unsigned i = 0, e = Fixups.size(); i != e; ++i) + IF.getFixups().push_back(Fixups[i]); + + // Update the layout, and remember that we relaxed. + Layout.UpdateForSlide(&IF, SlideAmount); + return true; +} + +bool MCAssembler::RelaxLEB(const MCObjectWriter &Writer, + MCAsmLayout &Layout, + MCLEBFragment &LF) { + int64_t Value; + LF.getValue().EvaluateAsAbsolute(Value, &Layout); + SmallString<32> Tmp; + raw_svector_ostream OSE(Tmp); + if (LF.isSigned()) + MCObjectWriter::EncodeSLEB128(Value, OSE); + else + MCObjectWriter::EncodeULEB128(Value, OSE); + uint64_t OldSize = LF.getSize(); + LF.setSize(OSE.GetNumBytesInBuffer()); + return OldSize != LF.getSize(); +} + + bool MCAssembler::LayoutOnce(const MCObjectWriter &Writer, MCAsmLayout &Layout) { ++stats::RelaxationSteps; @@ -795,43 +872,18 @@ for (MCSectionData::iterator it2 = SD.begin(), ie2 = SD.end(); it2 != ie2; ++it2) { - // Check if this is an instruction fragment that needs relaxation. - MCInstFragment *IF = dyn_cast(it2); - if (!IF || !FragmentNeedsRelaxation(Writer, IF, Layout)) - continue; - - ++stats::RelaxedInstructions; - - // FIXME-PERF: We could immediately lower out instructions if we can tell - // they are fully resolved, to avoid retesting on later passes. - - // Relax the fragment. - - MCInst Relaxed; - getBackend().RelaxInstruction(IF->getInst(), Relaxed); - - // Encode the new instruction. - // - // FIXME-PERF: If it matters, we could let the target do this. It can - // probably do so more efficiently in many cases. - SmallVector Fixups; - SmallString<256> Code; - raw_svector_ostream VecOS(Code); - getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups); - VecOS.flush(); - - // Update the instruction fragment. - int SlideAmount = Code.size() - IF->getInstSize(); - IF->setInst(Relaxed); - IF->getCode() = Code; - IF->getFixups().clear(); - // FIXME: Eliminate copy. - for (unsigned i = 0, e = Fixups.size(); i != e; ++i) - IF->getFixups().push_back(Fixups[i]); - - // Update the layout, and remember that we relaxed. - Layout.UpdateForSlide(IF, SlideAmount); - WasRelaxed = true; + // Check if this is an fragment that needs relaxation. + switch(it2->getKind()) { + default: + break; + case MCFragment::FT_Inst: + WasRelaxed |= RelaxInstruction(Writer, Layout, + *cast(it2)); + break; + case MCFragment::FT_LEB: + WasRelaxed |= RelaxLEB(Writer, Layout, *cast(it2)); + break; + } } } @@ -903,6 +955,7 @@ case MCFragment::FT_Inst: OS << "MCInstFragment"; break; case MCFragment::FT_Org: OS << "MCOrgFragment"; break; case MCFragment::FT_Dwarf: OS << "MCDwarfFragment"; break; + case MCFragment::FT_LEB: OS << "MCLEBFragment"; break; } OS << "getLineDelta(); break; } + case MCFragment::FT_LEB: { + const MCLEBFragment *LF = cast(this); + OS << "\n "; + OS << " Value:" << LF->getValue() << " Signed:" << LF->isSigned(); + break; + } } OS << ">"; } Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Tue Nov 2 12:22:24 2010 @@ -125,7 +125,7 @@ MCOS->EmitIntValue(dwarf::DW_LNS_extended_op, 1); int sizeof_address = MCOS->getAssembler().getBackend().getPointerSize(); - MCOS->EmitULEB128Value(sizeof_address + 1); + MCOS->EmitULEB128IntValue(sizeof_address + 1); MCOS->EmitIntValue(dwarf::DW_LNE_set_address, 1); MCOS->EmitSymbolValue(Symbol, sizeof_address); @@ -157,17 +157,17 @@ if (FileNum != it->getFileNum()) { FileNum = it->getFileNum(); MCOS->EmitIntValue(dwarf::DW_LNS_set_file, 1); - MCOS->EmitULEB128Value(FileNum); + MCOS->EmitULEB128IntValue(FileNum); } if (Column != it->getColumn()) { Column = it->getColumn(); MCOS->EmitIntValue(dwarf::DW_LNS_set_column, 1); - MCOS->EmitULEB128Value(Column); + MCOS->EmitULEB128IntValue(Column); } if (Isa != it->getIsa()) { Isa = it->getIsa(); MCOS->EmitIntValue(dwarf::DW_LNS_set_isa, 1); - MCOS->EmitULEB128Value(Isa); + MCOS->EmitULEB128IntValue(Isa); } if ((it->getFlags() ^ Flags) & DWARF2_FLAG_IS_STMT) { Flags = it->getFlags(); @@ -303,7 +303,8 @@ for (unsigned i = 1; i < MCDwarfFiles.size(); i++) { MCOS->EmitBytes(MCDwarfFiles[i]->getName(), 0); // FileName MCOS->EmitBytes(StringRef("\0", 1), 0); // the null term. of the string - MCOS->EmitULEB128Value(MCDwarfFiles[i]->getDirIndex()); // the Directory num + // the Directory num + MCOS->EmitULEB128IntValue(MCDwarfFiles[i]->getDirIndex()); MCOS->EmitIntValue(0, 1); // last modification timestamp (always 0) MCOS->EmitIntValue(0, 1); // filesize (always 0) } Modified: llvm/trunk/lib/MC/MCLoggingStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLoggingStreamer.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCLoggingStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCLoggingStreamer.cpp Tue Nov 2 12:22:24 2010 @@ -152,6 +152,18 @@ return Child->EmitIntValue(Value, Size, AddrSpace); } + virtual void EmitULEB128Value(const MCExpr *Value, + unsigned AddrSpace = 0) { + LogCall("EmitULEB128Value"); + return Child->EmitULEB128Value(Value, AddrSpace); + } + + virtual void EmitSLEB128Value(const MCExpr *Value, + unsigned AddrSpace = 0) { + LogCall("EmitSLEB128Value"); + return Child->EmitSLEB128Value(Value, AddrSpace); + } + virtual void EmitGPRel32Value(const MCExpr *Value) { LogCall("EmitGPRel32Value"); return Child->EmitGPRel32Value(Value); Modified: llvm/trunk/lib/MC/MCNullStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCNullStreamer.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCNullStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCNullStreamer.cpp Tue Nov 2 12:22:24 2010 @@ -66,6 +66,10 @@ virtual void EmitValue(const MCExpr *Value, unsigned Size, unsigned AddrSpace) {} + virtual void EmitULEB128Value(const MCExpr *Value, + unsigned AddrSpace = 0) {} + virtual void EmitSLEB128Value(const MCExpr *Value, + unsigned AddrSpace = 0) {} virtual void EmitGPRel32Value(const MCExpr *Value) {} virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0, unsigned ValueSize = 1, Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Tue Nov 2 12:22:24 2010 @@ -75,6 +75,16 @@ return Value; } +void MCObjectStreamer::EmitULEB128Value(const MCExpr *Value, + unsigned AddrSpace) { + new MCLEBFragment(*Value, false, getCurrentSectionData()); +} + +void MCObjectStreamer::EmitSLEB128Value(const MCExpr *Value, + unsigned AddrSpace) { + new MCLEBFragment(*Value, true, getCurrentSectionData()); +} + void MCObjectStreamer::EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) { report_fatal_error("This file format doesn't support weak aliases."); Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Tue Nov 2 12:22:24 2010 @@ -261,8 +261,6 @@ bool ParseDirectiveMacro(StringRef, SMLoc DirectiveLoc); bool ParseDirectiveEndMacro(StringRef, SMLoc DirectiveLoc); - void ParseUleb128(uint64_t Value); - void ParseSleb128(int64_t Value); bool ParseDirectiveLEB128(StringRef, SMLoc); }; @@ -2178,44 +2176,22 @@ "no current macro definition"); } -void GenericAsmParser::ParseUleb128(uint64_t Value) { - const uint64_t Mask = (1 << 7) - 1; - do { - unsigned Byte = Value & Mask; - Value >>= 7; - if (Value) // Not the last one - Byte |= (1 << 7); - getStreamer().EmitIntValue(Byte, 1, DEFAULT_ADDRSPACE); - } while (Value); -} - -void GenericAsmParser::ParseSleb128(int64_t Value) { - const int64_t Mask = (1 << 7) - 1; - for(;;) { - unsigned Byte = Value & Mask; - Value >>= 7; - bool Done = ((Value == 0 && (Byte & 0x40) == 0) || - (Value == -1 && (Byte & 0x40) != 0)); - if (!Done) - Byte |= (1 << 7); - getStreamer().EmitIntValue(Byte, 1, DEFAULT_ADDRSPACE); - if (Done) - break; - } -} - bool GenericAsmParser::ParseDirectiveLEB128(StringRef DirName, SMLoc) { - int64_t Value; - if (getParser().ParseAbsoluteExpression(Value)) + getParser().CheckForValidSection(); + + const MCExpr *Value; + + if (getParser().ParseExpression(Value)) return true; if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in directive"); if (DirName[1] == 's') - ParseSleb128(Value); + getStreamer().EmitSLEB128Value(Value); else - ParseUleb128(Value); + getStreamer().EmitULEB128Value(Value); + return false; } Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=118023&r1=118022&r2=118023&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Tue Nov 2 12:22:24 2010 @@ -37,22 +37,16 @@ EmitValue(MCConstantExpr::Create(Value, getContext()), Size, AddrSpace); } -// EmitULEB128Value - Special case of EmitValue that emits a ULEB128 of the -// Value as the sequence of ULEB128 encoded bytes. -void MCStreamer::EmitULEB128Value(uint64_t Value, unsigned AddrSpace) { - SmallString<32> Tmp; - raw_svector_ostream OS(Tmp); - MCObjectWriter::EncodeULEB128(Value, OS); - EmitBytes(OS.str(), AddrSpace); -} - -// EmitSLEB128Value - Special case of EmitValue that emits a SLEB128 of the -// Value as the sequence of ULEB128 encoded bytes. -void MCStreamer::EmitSLEB128Value(int64_t Value, unsigned AddrSpace) { - SmallString<32> Tmp; - raw_svector_ostream OS(Tmp); - MCObjectWriter::EncodeSLEB128(Value, OS); - EmitBytes(OS.str(), AddrSpace); +/// EmitULEB128Value - Special case of EmitULEB128Value that avoids the +/// client having to pass in a MCExpr for constant integers. +void MCStreamer::EmitULEB128IntValue(uint64_t Value, unsigned AddrSpace) { + EmitULEB128Value(MCConstantExpr::Create(Value, getContext()), AddrSpace); +} + +/// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the +/// client having to pass in a MCExpr for constant integers. +void MCStreamer::EmitSLEB128IntValue(int64_t Value, unsigned AddrSpace) { + EmitSLEB128Value(MCConstantExpr::Create(Value, getContext()), AddrSpace); } void MCStreamer::EmitSymbolValue(const MCSymbol *Sym, unsigned Size, Added: llvm/trunk/test/MC/ELF/leb128.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/leb128.s?rev=118023&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/leb128.s (added) +++ llvm/trunk/test/MC/ELF/leb128.s Tue Nov 2 12:22:24 2010 @@ -0,0 +1,19 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + + .sleb128 .Lfoo - .Lbar +.Lfoo: + .uleb128 .Lbar - .Lfoo + .fill 126, 1, 0x90 +.Lbar: + +// CHECK: (('sh_name', 0x00000001) # '.text' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x00000006) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000040) +// CHECK-NEXT: ('sh_size', 0x00000081) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000004) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '817f7f90 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90') From sabre at nondot.org Tue Nov 2 12:30:52 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 17:30:52 -0000 Subject: [llvm-commits] [llvm] r118024 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101102173052.326632A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 12:30:52 2010 New Revision: 118024 URL: http://llvm.org/viewvc/llvm-project?rev=118024&view=rev Log: refactor/cleanup MatchableInfo by eliminating the Tokens array, merging it into a Token field in Operand, and moving the first token to an explicit mnemonic field. These were parallel arrays before (except for the mnemonic) which kept confusing me. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118024&r1=118023&r2=118024&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 12:30:52 2010 @@ -93,82 +93,6 @@ MatchPrefix("match-prefix", cl::init(""), cl::desc("Only match instructions with the given prefix")); -/// TokenizeAsmString - Tokenize a simplified assembly string. -static void TokenizeAsmString(StringRef AsmString, - SmallVectorImpl &Tokens) { - unsigned Prev = 0; - bool InTok = true; - for (unsigned i = 0, e = AsmString.size(); i != e; ++i) { - switch (AsmString[i]) { - case '[': - case ']': - case '*': - case '!': - case ' ': - case '\t': - case ',': - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - if (!isspace(AsmString[i]) && AsmString[i] != ',') - Tokens.push_back(AsmString.substr(i, 1)); - Prev = i + 1; - break; - - case '\\': - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - ++i; - assert(i != AsmString.size() && "Invalid quoted character"); - Tokens.push_back(AsmString.substr(i, 1)); - Prev = i + 1; - break; - - case '$': { - // If this isn't "${", treat like a normal token. - if (i + 1 == AsmString.size() || AsmString[i + 1] != '{') { - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - Prev = i; - break; - } - - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - - StringRef::iterator End = - std::find(AsmString.begin() + i, AsmString.end(), '}'); - assert(End != AsmString.end() && "Missing brace in operand reference!"); - size_t EndPos = End - AsmString.begin(); - Tokens.push_back(AsmString.slice(i, EndPos+1)); - Prev = EndPos + 1; - i = EndPos; - break; - } - - case '.': - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - } - Prev = i; - InTok = true; - break; - - default: - InTok = true; - } - } - if (InTok && Prev != AsmString.size()) - Tokens.push_back(AsmString.substr(Prev)); -} - namespace { class AsmMatcherInfo; @@ -324,14 +248,16 @@ /// instruction or alias which is capable of being matched. struct MatchableInfo { struct Operand { + /// Token - This is the token that the operand came from. + StringRef Token; + /// The unique class instance this operand should match. ClassInfo *Class; /// The original operand this corresponds to, if any. const CGIOperandList::OperandInfo *OperandInfo; - Operand(ClassInfo *C, const CGIOperandList::OperandInfo *OpInfo) - : Class(C), OperandInfo(OpInfo) {} + explicit Operand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} }; /// InstrName - The target name for this instruction. @@ -344,9 +270,10 @@ /// removed). std::string AsmString; - /// Tokens - The tokenized assembly pattern that this instruction matches. - SmallVector Tokens; - + /// Mnemonic - This is the first token of the matched instruction, its + /// mnemonic. + StringRef Mnemonic; + /// AsmOperands - The textual operands that this instruction matches, /// including literal tokens for the mnemonic, etc. SmallVector AsmOperands; @@ -382,16 +309,16 @@ /// and perform a bunch of validity checking. bool Validate(StringRef CommentDelimiter, bool Hack) const; - /// getSingletonRegisterForToken - If the specified token is a singleton + /// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the Record for it, otherwise return null. - Record *getSingletonRegisterForToken(unsigned i, - const AsmMatcherInfo &Info) const; + Record *getSingletonRegisterForAsmOperand(unsigned i, + const AsmMatcherInfo &Info) const; /// operator< - Compare two matchables. bool operator<(const MatchableInfo &RHS) const { // The primary comparator is the instruction mnemonic. - if (Tokens[0] != RHS.Tokens[0]) - return Tokens[0] < RHS.Tokens[0]; + if (Mnemonic != RHS.Mnemonic) + return Mnemonic < RHS.Mnemonic; if (AsmOperands.size() != RHS.AsmOperands.size()) return AsmOperands.size() < RHS.AsmOperands.size(); @@ -413,7 +340,7 @@ /// strictly superior match). bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) { // The primary comparator is the instruction mnemonic. - if (Tokens[0] != RHS.Tokens[0]) + if (Mnemonic != RHS.Mnemonic) return false; // The number of operands is unambiguous. @@ -448,6 +375,9 @@ } void dump(); + +private: + void TokenizeAsmString(const AsmMatcherInfo &Info); }; /// SubtargetFeatureInfo - Helper class for storing information on a subtarget @@ -535,20 +465,13 @@ } void MatchableInfo::dump() { - errs() << InstrName << " -- " << "flattened:\"" << AsmString << '\"' - << ", tokens:["; - for (unsigned i = 0, e = Tokens.size(); i != e; ++i) { - errs() << Tokens[i]; - if (i + 1 != e) - errs() << ", "; - } - errs() << "]\n"; + errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n"; for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { Operand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; if (Op.Class->Kind == ClassInfo::Token) { - errs() << '\"' << Tokens[i] << "\"\n"; + errs() << '\"' << Op.Token << "\"\n"; continue; } @@ -568,7 +491,7 @@ // TODO: Eventually support asmparser for Variant != 0. AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); - TokenizeAsmString(AsmString, Tokens); + TokenizeAsmString(Info); // Compute the require features. std::vector Predicates =TheDef->getValueAsListOfDefs("Predicates"); @@ -578,12 +501,98 @@ RequiredFeatures.push_back(Feature); // Collect singleton registers, if used. - for (unsigned i = 0, e = Tokens.size(); i != e; ++i) { - if (Record *Reg = getSingletonRegisterForToken(i, Info)) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info)) SingletonRegisters.insert(Reg); } } +/// TokenizeAsmString - Tokenize a simplified assembly string. +void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { + StringRef String = AsmString; + unsigned Prev = 0; + bool InTok = true; + for (unsigned i = 0, e = String.size(); i != e; ++i) { + switch (String[i]) { + case '[': + case ']': + case '*': + case '!': + case ' ': + case '\t': + case ',': + if (InTok) { + AsmOperands.push_back(Operand(String.slice(Prev, i))); + InTok = false; + } + if (!isspace(String[i]) && String[i] != ',') + AsmOperands.push_back(Operand(String.substr(i, 1))); + Prev = i + 1; + break; + + case '\\': + if (InTok) { + AsmOperands.push_back(Operand(String.slice(Prev, i))); + InTok = false; + } + ++i; + assert(i != String.size() && "Invalid quoted character"); + AsmOperands.push_back(Operand(String.substr(i, 1))); + Prev = i + 1; + break; + + case '$': { + // If this isn't "${", treat like a normal token. + if (i + 1 == String.size() || String[i + 1] != '{') { + if (InTok) { + AsmOperands.push_back(Operand(String.slice(Prev, i))); + InTok = false; + } + Prev = i; + break; + } + + if (InTok) { + AsmOperands.push_back(Operand(String.slice(Prev, i))); + InTok = false; + } + + StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); + assert(End != String.end() && "Missing brace in operand reference!"); + size_t EndPos = End - String.begin(); + AsmOperands.push_back(Operand(String.slice(i, EndPos+1))); + Prev = EndPos + 1; + i = EndPos; + break; + } + + case '.': + if (InTok) + AsmOperands.push_back(Operand(String.slice(Prev, i))); + Prev = i; + InTok = true; + break; + + default: + InTok = true; + } + } + if (InTok && Prev != String.size()) + AsmOperands.push_back(Operand(String.substr(Prev))); + + // The first token of the instruction is the mnemonic, which must be a + // simple string, not a $foo variable or a singleton register. + assert(!AsmOperands.empty() && "Instruction has no tokens?"); + Mnemonic = AsmOperands[0].Token; + if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info)) + throw TGError(TheDef->getLoc(), + "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); + + // Remove the first operand, it is tracked in the mnemonic field. + AsmOperands.erase(AsmOperands.begin()); +} + + /// getRegisterRecord - Get the register record for \arg name, or 0. static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) { @@ -623,24 +632,25 @@ // Also, check for instructions which reference the operand multiple times; // this implies a constraint we would not honor. std::set OperandNames; - for (unsigned i = 1, e = Tokens.size(); i < e; ++i) { - if (Tokens[i][0] == '$' && Tokens[i].find(':') != StringRef::npos) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + StringRef Tok = AsmOperands[i].Token; + if (Tok[0] == '$' && Tok.find(':') != StringRef::npos) throw TGError(TheDef->getLoc(), - "matchable with operand modifier '" + Tokens[i].str() + + "matchable with operand modifier '" + Tok.str() + "' not supported by asm matcher. Mark isCodeGenOnly!"); // Verify that any operand is only mentioned once. - if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) { + if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { if (!Hack) throw TGError(TheDef->getLoc(), - "ERROR: matchable with tied operand '" + Tokens[i].str() + + "ERROR: matchable with tied operand '" + Tok.str() + "' can never be matched!"); // FIXME: Should reject these. The ARM backend hits this with $lane in a // bunch of instructions. It is unclear what the right answer is. DEBUG({ errs() << "warning: '" << InstrName << "': " << "ignoring instruction with tied operand '" - << Tokens[i].str() << "'\n"; + << Tok.str() << "'\n"; }); return false; } @@ -650,11 +660,11 @@ } -/// getSingletonRegisterForToken - If the specified token is a singleton +/// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the register name, otherwise return a null StringRef. Record *MatchableInfo:: -getSingletonRegisterForToken(unsigned i, const AsmMatcherInfo &Info) const { - StringRef Tok = Tokens[i]; +getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ + StringRef Tok = AsmOperands[i].Token; if (!Tok.startswith(Info.RegisterPrefix)) return 0; @@ -1000,31 +1010,22 @@ ie = Matchables.end(); it != ie; ++it) { MatchableInfo *II = *it; - // The first token of the instruction is the mnemonic, which must be a - // simple string, not a $foo variable or a singleton register. - assert(!II->Tokens.empty() && "Instruction has no tokens?"); - StringRef Mnemonic = II->Tokens[0]; - if (Mnemonic[0] == '$' || II->getSingletonRegisterForToken(0, *this)) - throw TGError(II->TheDef->getLoc(), - "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); - // Parse the tokens after the mnemonic. - for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) { - StringRef Token = II->Tokens[i]; + for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) { + MatchableInfo::Operand &Op = II->AsmOperands[i]; + StringRef Token = Op.Token; // Check for singleton registers. - if (Record *RegRecord = II->getSingletonRegisterForToken(i, *this)) { - MatchableInfo::Operand Op(RegisterClasses[RegRecord], 0); + if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) { + Op.Class = RegisterClasses[RegRecord]; assert(Op.Class && Op.Class->Registers.size() == 1 && "Unexpected class for singleton register"); - II->AsmOperands.push_back(Op); continue; } // Check for simple tokens. if (Token[0] != '$') { - II->AsmOperands.push_back(MatchableInfo::Operand(getTokenClass(Token), - 0)); + Op.Class = getTokenClass(Token); continue; } @@ -1061,8 +1062,8 @@ assert(OI && "Unable to find tied operand target!"); } - II->AsmOperands.push_back(MatchableInfo::Operand(getOperandClass(Token, - *OI), OI)); + Op.Class = getOperandClass(Token, *OI); + Op.OperandInfo = OI; } } @@ -1749,7 +1750,7 @@ MatchableInfo &II = **it; OS << " { " << Target.getName() << "::" << II.InstrName - << ", \"" << II.Tokens[0] << "\"" + << ", \"" << II.Mnemonic << "\"" << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { MatchableInfo::Operand &Op = II.AsmOperands[i]; From sabre at nondot.org Tue Nov 2 12:34:28 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 17:34:28 -0000 Subject: [llvm-commits] [llvm] r118025 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101102173428.8F2A92A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 12:34:28 2010 New Revision: 118025 URL: http://llvm.org/viewvc/llvm-project?rev=118025&view=rev Log: add and update comments. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118025&r1=118024&r2=118025&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 12:34:28 2010 @@ -263,11 +263,16 @@ /// InstrName - The target name for this instruction. std::string InstrName; + /// TheDef - This is the definition of the instruction or InstAlias that this + /// matchable came from. Record *const TheDef; + + /// OperandList - This is the operand list that came from the (ins) and (outs) + /// list of the alias or instruction. const CGIOperandList &OperandList; /// AsmString - The assembly string for this instruction (with variants - /// removed). + /// removed), e.g. "movsx $src, $dst". std::string AsmString; /// Mnemonic - This is the first token of the matched instruction, its @@ -275,7 +280,9 @@ StringRef Mnemonic; /// AsmOperands - The textual operands that this instruction matches, - /// including literal tokens for the mnemonic, etc. + /// annotated with a class and where in the OperandList they were defined. + /// This directly corresponds to the tokenized AsmString after the mnemonic is + /// removed. SmallVector AsmOperands; /// Predicates - The required subtarget features to match this instruction. From grosbach at apple.com Tue Nov 2 12:35:25 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 02 Nov 2010 17:35:25 -0000 Subject: [llvm-commits] [llvm] r118026 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMMachineFunctionInfo.h lib/Target/ARM/Thumb1RegisterInfo.cpp test/CodeGen/ARM/lsr-code-insertion.ll test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll utils/TableGen/CodeEmitterGen.cpp Message-ID: <20101102173525.9CD0E2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 2 12:35:25 2010 New Revision: 118026 URL: http://llvm.org/viewvc/llvm-project?rev=118026&view=rev Log: Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke assumptions about stack layout. Specifically, LR must be saved next to FP. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=118026&r1=118025&r2=118026&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Nov 2 12:35:25 2010 @@ -77,8 +77,8 @@ static const unsigned DarwinCalleeSavedRegs[] = { // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved // register. - ARM::LR, ARM::R11, ARM::R10, ARM::R8, - ARM::R7, ARM::R6, ARM::R5, ARM::R4, + ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, + ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, @@ -702,6 +702,7 @@ bool LRSpilled = false; unsigned NumGPRSpills = 0; SmallVector UnspilledCS1GPRs; + SmallVector UnspilledCS2GPRs; ARMFunctionInfo *AFI = MF.getInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -768,7 +769,23 @@ break; } } else { - UnspilledCS1GPRs.push_back(Reg); + if (!STI.isTargetDarwin()) { + UnspilledCS1GPRs.push_back(Reg); + continue; + } + + switch (Reg) { + case ARM::R4: + case ARM::R5: + case ARM::R6: + case ARM::R7: + case ARM::LR: + UnspilledCS1GPRs.push_back(Reg); + break; + default: + UnspilledCS2GPRs.push_back(Reg); + break; + } } } @@ -844,6 +861,13 @@ break; } } + } else if (!UnspilledCS2GPRs.empty() && + !AFI->isThumb1OnlyFunction()) { + unsigned Reg = UnspilledCS2GPRs.front(); + MF.getRegInfo().setPhysRegUsed(Reg); + AFI->setCSRegisterIsSpilled(Reg); + if (!isReservedReg(MF, Reg)) + ExtraCSSpill = true; } } @@ -867,6 +891,17 @@ NumExtras--; } } + // For non-Thumb1 functions, also check for hi-reg CS registers + if (!AFI->isThumb1OnlyFunction()) { + while (NumExtras && !UnspilledCS2GPRs.empty()) { + unsigned Reg = UnspilledCS2GPRs.back(); + UnspilledCS2GPRs.pop_back(); + if (!isReservedReg(MF, Reg)) { + Extras.push_back(Reg); + NumExtras--; + } + } + } if (Extras.size() && NumExtras == 0) { for (unsigned i = 0, e = Extras.size(); i != e; ++i) { MF.getRegInfo().setPhysRegUsed(Extras[i]); @@ -924,8 +959,10 @@ FrameReg = ARM::SP; Offset += SPAdj; - if (AFI->isGPRCalleeSavedAreaFrame(FI)) - return Offset - AFI->getGPRCalleeSavedAreaOffset(); + if (AFI->isGPRCalleeSavedArea1Frame(FI)) + return Offset - AFI->getGPRCalleeSavedArea1Offset(); + else if (AFI->isGPRCalleeSavedArea2Frame(FI)) + return Offset - AFI->getGPRCalleeSavedArea2Offset(); else if (AFI->isDPRCalleeSavedAreaFrame(FI)) return Offset - AFI->getDPRCalleeSavedAreaOffset(); @@ -1623,7 +1660,8 @@ } /// Move iterator past the next bunch of callee save load / store ops for -/// the particular spill area (1: integer area 1, 2: fp area, 0: don't care). +/// the particular spill area (1: integer area 1, 2: integer area 2, +/// 3: fp area, 0: don't care). static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Opc1, int Opc2, unsigned Area, @@ -1636,13 +1674,15 @@ unsigned Category = 0; switch (MBBI->getOperand(0).getReg()) { case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: - case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: case ARM::LR: Category = 1; break; + case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: + Category = STI.isTargetDarwin() ? 2 : 1; + break; case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: - Category = 2; + Category = 3; break; default: Done = true; @@ -1672,7 +1712,7 @@ // Determine the sizes of each callee-save spill areas and record which frame // belongs to which callee-save spill areas. - unsigned GPRCSSize = 0, DPRCSSize = 0; + unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; int FramePtrSpillFI = 0; // Allocate the vararg register save area. This is not counted in NumBytes. @@ -1693,15 +1733,25 @@ case ARM::R5: case ARM::R6: case ARM::R7: + case ARM::LR: + if (Reg == FramePtr) + FramePtrSpillFI = FI; + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + break; case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: - case ARM::LR: if (Reg == FramePtr) FramePtrSpillFI = FI; - AFI->addGPRCalleeSavedAreaFrame(FI); - GPRCSSize += 4; + if (STI.isTargetDarwin()) { + AFI->addGPRCalleeSavedArea2Frame(FI); + GPRCS2Size += 4; + } else { + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + } break; default: AFI->addDPRCalleeSavedAreaFrame(FI); @@ -1709,11 +1759,15 @@ } } - // Build the new SUBri to adjust SP for integer callee-save spill area. - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize); + // Build the new SUBri to adjust SP for integer callee-save spill area 1. + emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI); // Set FP to point to the stack slot that contains the previous FP. + // For Darwin, FP is R7, which has now been stored in spill area 1. + // Otherwise, if this is not Darwin, all the callee-saved registers go + // into spill area 1, including the FP in R11. In either case, it is + // now safe to emit this assignment. bool HasFP = hasFP(MF); if (HasFP) { unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; @@ -1723,19 +1777,25 @@ AddDefaultCC(AddDefaultPred(MIB)); } + // Build the new SUBri to adjust SP for integer callee-save spill area 2. + emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); + // Build the new SUBri to adjust SP for FP callee-save spill area. + movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); // Determine starting offsets of spill areas. - unsigned DPRCSOffset = NumBytes - (GPRCSSize + DPRCSSize); - unsigned GPRCSOffset = DPRCSOffset + DPRCSSize; + unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); + unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; + unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; if (HasFP) AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); - AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset); + AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); + AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); - movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); NumBytes = DPRCSOffset; if (NumBytes) { // Adjust SP after all the callee-save spills. @@ -1750,7 +1810,8 @@ AFI->setShouldRestoreSPFromFP(true); } - AFI->setGPRCalleeSavedAreaSize(GPRCSSize); + AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); + AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); // If we need dynamic stack realignment, do it here. Be paranoid and make @@ -1852,7 +1913,8 @@ } // Move SP to start of FP callee save spill area. - NumBytes -= (AFI->getGPRCalleeSavedAreaSize() + + NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + + AFI->getGPRCalleeSavedArea2Size() + AFI->getDPRCalleeSavedAreaSize()); // Reset SP based on frame pointer only if the stack frame extends beyond @@ -1878,13 +1940,17 @@ } else if (NumBytes) emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); - // Move SP to start of integer callee save spill area. - movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 2, STI); + // Move SP to start of integer callee save spill area 2. + movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); + // Move SP to start of integer callee save spill area 1. + movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI); + emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); + // Move SP to SP upon entry to the function. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI); - emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize()); + emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); } if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || Modified: llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h?rev=118026&r1=118025&r2=118026&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h Tue Nov 2 12:35:25 2010 @@ -55,22 +55,28 @@ /// spill stack offset. unsigned FramePtrSpillOffset; - /// GPRCSOffset, DPRCSOffset - Starting offset of callee saved register - /// spills areas (excluding R9 for Mac OS X): + /// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved + /// register spills areas. For Mac OS X: /// - /// GPR callee-saved (1) : r4, r5, r6, r7, r8, r9, r10, r11, lr + /// GPR callee-saved (1) : r4, r5, r6, r7, lr + /// -------------------------------------------- + /// GPR callee-saved (2) : r8, r10, r11 /// -------------------------------------------- /// DPR callee-saved : d8 - d15 - unsigned GPRCSOffset; + unsigned GPRCS1Offset; + unsigned GPRCS2Offset; unsigned DPRCSOffset; - /// GPRCSSize, DPRCSSize - Sizes of callee saved register spills areas. - unsigned GPRCSSize; + /// GPRCS1Size, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills + /// areas. + unsigned GPRCS1Size; + unsigned GPRCS2Size; unsigned DPRCSSize; - /// GPRCSFrames, DPRCSFrames - Keeps track of frame indices which belong - /// to these spill areas. - BitVector GPRCSFrames; + /// GPRCS1Frames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices + /// which belong to these spill areas. + BitVector GPRCS1Frames; + BitVector GPRCS2Frames; BitVector DPRCSFrames; /// SpilledCSRegs - A BitVector mask of all spilled callee-saved registers. @@ -95,9 +101,9 @@ hasThumb2(false), VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false), LRSpilledForFarJump(false), - FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0), - GPRCSSize(0), DPRCSSize(0), - GPRCSFrames(0), DPRCSFrames(0), + FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), + GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), + GPRCS1Frames(0), GPRCS2Frames(0), DPRCSFrames(0), JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0), HasITBlocks(false) {} @@ -106,9 +112,9 @@ hasThumb2(MF.getTarget().getSubtarget().hasThumb2()), VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false), LRSpilledForFarJump(false), - FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0), - GPRCSSize(0), DPRCSSize(0), - GPRCSFrames(32), DPRCSFrames(32), + FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), + GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), + GPRCS1Frames(32), GPRCS2Frames(32), DPRCSFrames(32), SpilledCSRegs(MF.getTarget().getRegisterInfo()->getNumRegs()), JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0), HasITBlocks(false) {} @@ -132,22 +138,31 @@ unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; } void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; } - unsigned getGPRCalleeSavedAreaOffset() const { return GPRCSOffset; } + unsigned getGPRCalleeSavedArea1Offset() const { return GPRCS1Offset; } + unsigned getGPRCalleeSavedArea2Offset() const { return GPRCS2Offset; } unsigned getDPRCalleeSavedAreaOffset() const { return DPRCSOffset; } - void setGPRCalleeSavedAreaOffset(unsigned o) { GPRCSOffset = o; } + void setGPRCalleeSavedArea1Offset(unsigned o) { GPRCS1Offset = o; } + void setGPRCalleeSavedArea2Offset(unsigned o) { GPRCS2Offset = o; } void setDPRCalleeSavedAreaOffset(unsigned o) { DPRCSOffset = o; } - unsigned getGPRCalleeSavedAreaSize() const { return GPRCSSize; } + unsigned getGPRCalleeSavedArea1Size() const { return GPRCS1Size; } + unsigned getGPRCalleeSavedArea2Size() const { return GPRCS2Size; } unsigned getDPRCalleeSavedAreaSize() const { return DPRCSSize; } - void setGPRCalleeSavedAreaSize(unsigned s) { GPRCSSize = s; } + void setGPRCalleeSavedArea1Size(unsigned s) { GPRCS1Size = s; } + void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; } void setDPRCalleeSavedAreaSize(unsigned s) { DPRCSSize = s; } - bool isGPRCalleeSavedAreaFrame(int fi) const { - if (fi < 0 || fi >= (int)GPRCSFrames.size()) + bool isGPRCalleeSavedArea1Frame(int fi) const { + if (fi < 0 || fi >= (int)GPRCS1Frames.size()) + return false; + return GPRCS1Frames[fi]; + } + bool isGPRCalleeSavedArea2Frame(int fi) const { + if (fi < 0 || fi >= (int)GPRCS2Frames.size()) return false; - return GPRCSFrames[fi]; + return GPRCS2Frames[fi]; } bool isDPRCalleeSavedAreaFrame(int fi) const { if (fi < 0 || fi >= (int)DPRCSFrames.size()) @@ -155,16 +170,28 @@ return DPRCSFrames[fi]; } - void addGPRCalleeSavedAreaFrame(int fi) { + void addGPRCalleeSavedArea1Frame(int fi) { + if (fi >= 0) { + int Size = GPRCS1Frames.size(); + if (fi >= Size) { + Size *= 2; + if (fi >= Size) + Size = fi+1; + GPRCS1Frames.resize(Size); + } + GPRCS1Frames[fi] = true; + } + } + void addGPRCalleeSavedArea2Frame(int fi) { if (fi >= 0) { - int Size = GPRCSFrames.size(); + int Size = GPRCS2Frames.size(); if (fi >= Size) { Size *= 2; if (fi >= Size) Size = fi+1; - GPRCSFrames.resize(Size); + GPRCS2Frames.resize(Size); } - GPRCSFrames[fi] = true; + GPRCS2Frames[fi] = true; } } void addDPRCalleeSavedAreaFrame(int fi) { Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=118026&r1=118025&r2=118026&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Tue Nov 2 12:35:25 2010 @@ -596,8 +596,10 @@ int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + MF.getFrameInfo()->getStackSize() + SPAdj; - if (AFI->isGPRCalleeSavedAreaFrame(FrameIndex)) - Offset -= AFI->getGPRCalleeSavedAreaOffset(); + if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) + Offset -= AFI->getGPRCalleeSavedArea1Offset(); + else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) + Offset -= AFI->getGPRCalleeSavedArea2Offset(); else if (MF.getFrameInfo()->hasVarSizedObjects()) { assert(SPAdj == 0 && hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame @@ -706,7 +708,7 @@ // Determine the sizes of each callee-save spill areas and record which frame // belongs to which callee-save spill areas. - unsigned GPRCSSize = 0, DPRCSSize = 0; + unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; int FramePtrSpillFI = 0; if (VARegSaveSize) @@ -726,15 +728,25 @@ case ARM::R5: case ARM::R6: case ARM::R7: + case ARM::LR: + if (Reg == FramePtr) + FramePtrSpillFI = FI; + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + break; case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: - case ARM::LR: if (Reg == FramePtr) FramePtrSpillFI = FI; - AFI->addGPRCalleeSavedAreaFrame(FI); - GPRCSSize += 4; + if (STI.isTargetDarwin()) { + AFI->addGPRCalleeSavedArea2Frame(FI); + GPRCS2Size += 4; + } else { + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + } break; default: AFI->addDPRCalleeSavedAreaFrame(FI); @@ -756,10 +768,12 @@ } // Determine starting offsets of spill areas. - unsigned DPRCSOffset = NumBytes - (GPRCSSize + DPRCSSize); - unsigned GPRCSOffset = DPRCSOffset + DPRCSSize; + unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); + unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; + unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); - AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset); + AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); + AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); NumBytes = DPRCSOffset; @@ -772,7 +786,8 @@ MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - AFI->getFramePtrSpillOffset()); - AFI->setGPRCalleeSavedAreaSize(GPRCSSize); + AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); + AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); // If we need a base pointer, set it up here. It's whatever the value @@ -833,7 +848,8 @@ } // Move SP to start of FP callee save spill area. - NumBytes -= (AFI->getGPRCalleeSavedAreaSize() + + NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + + AFI->getGPRCalleeSavedArea2Size() + AFI->getDPRCalleeSavedAreaSize()); if (AFI->shouldRestoreSPFromFP()) { Modified: llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll?rev=118026&r1=118025&r2=118026&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-code-insertion.ll Tue Nov 2 12:35:25 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -stats |& grep {36.*Number of machine instrs printed} +; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed} ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll?rev=118026&r1=118025&r2=118026&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll Tue Nov 2 12:35:25 2010 @@ -32,14 +32,15 @@ define fastcc i32 @parse_percent_token() nounwind { entry: -; CHECK: itt eq -; CHECK: itt eq -; CHECK: itt eq -; CHECK: itt eq -; CHECK: itt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq ; CHECK: moveq r0 ; CHECK-NOT: LBB0_ -; CHECK: ldmiaeq +; CHECK: ldreq +; CHECK: popeq switch i32 undef, label %bb7 [ i32 37, label %bb43 i32 48, label %bb5 Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=118026&r1=118025&r2=118026&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Tue Nov 2 12:35:25 2010 @@ -17,9 +17,15 @@ #include "CodeGenTarget.h" #include "Record.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" using namespace llvm; +static cl::opt +MCEmitter("mc-code-emitter", + cl::desc("Generate CodeEmitter for use with the MC library."), + cl::init(false)); + void CodeEmitterGen::reverseBits(std::vector &Insts) { for (std::vector::iterator I = Insts.begin(), E = Insts.end(); I != E; ++I) { From dpatel at apple.com Tue Nov 2 12:37:00 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 02 Nov 2010 17:37:00 -0000 Subject: [llvm-commits] [llvm] r118027 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20101102173700.363322A6C12C@llvm.org> Author: dpatel Date: Tue Nov 2 12:37:00 2010 New Revision: 118027 URL: http://llvm.org/viewvc/llvm-project?rev=118027&view=rev Log: Simplify. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=118027&r1=118026&r2=118027&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Nov 2 12:37:00 2010 @@ -822,9 +822,8 @@ const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new (DIEValueAllocator) DIEBlock(); - const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); - if (TRI->getFrameRegister(*Asm->MF) == Location.getReg() + if (RI->getFrameRegister(*Asm->MF) == Location.getReg() && Location.getOffset()) { // If variable offset is based in frame register then use fbreg. addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_fbreg); From gkistanova at gmail.com Tue Nov 2 12:43:14 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 02 Nov 2010 17:43:14 -0000 Subject: [llvm-commits] [zorg] r118028 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20101102174314.688422A6C12C@llvm.org> Author: gkistanova Date: Tue Nov 2 12:43:14 2010 New Revision: 118028 URL: http://llvm.org/viewvc/llvm-project?rev=118028&view=rev Log: Test step temporally removed from builder llvm-gcc-i686-pc-linux-gnu-cross-gnueabi. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=118028&r1=118027&r2=118028&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Tue Nov 2 12:43:14 2010 @@ -554,9 +554,6 @@ 'description' : 'install llvm', 'extra_args' : ['-j8'], 'haltOnFailure' : False }, - {'name' : 'test_llvm', - 'description' : 'test llvm', - 'haltOnFailure' : False }, {'name' : 'configure_llvmgcc', 'description' : 'configure llvm-gcc', 'haltOnFailure' : True }, From grosbach at apple.com Tue Nov 2 12:59:05 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 02 Nov 2010 17:59:05 -0000 Subject: [llvm-commits] [llvm] r118029 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20101102175905.0DE352A6C12C@llvm.org> Author: grosbach Date: Tue Nov 2 12:59:04 2010 New Revision: 118029 URL: http://llvm.org/viewvc/llvm-project?rev=118029&view=rev Log: Sort bit assignments. Cosmetic change only. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118029&r1=118028&r2=118029&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 12:59:04 2010 @@ -516,8 +516,8 @@ bits<4> Rn; bits<12> imm; let Inst{25} = 1; - let Inst{15-12} = Rd; let Inst{19-16} = Rn; + let Inst{15-12} = Rd; let Inst{11-0} = imm; } } @@ -527,12 +527,12 @@ bits<4> Rd; bits<4> Rn; bits<4> Rm; - let Inst{11-4} = 0b00000000; let Inst{25} = 0; let isCommutable = Commutable; - let Inst{3-0} = Rm; - let Inst{15-12} = Rd; let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-4} = 0b00000000; + let Inst{3-0} = Rm; } def rs : AsI1 Rn; bits<12> shift; let Inst{25} = 0; - let Inst{11-0} = shift; - let Inst{15-12} = Rd; let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-0} = shift; } } @@ -560,10 +560,10 @@ bits<4> Rn; bits<12> imm; let Inst{25} = 1; - let Inst{15-12} = Rd; + let Inst{20} = 1; let Inst{19-16} = Rn; + let Inst{15-12} = Rd; let Inst{11-0} = imm; - let Inst{20} = 1; } def rr : AI1 Rd; bits<4> Rn; bits<4> Rm; - let Inst{11-4} = 0b00000000; - let Inst{25} = 0; let isCommutable = Commutable; - let Inst{3-0} = Rm; - let Inst{15-12} = Rd; - let Inst{19-16} = Rn; + let Inst{25} = 0; let Inst{20} = 1; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-4} = 0b00000000; + let Inst{3-0} = Rm; } def rs : AI1 Rn; bits<12> shift; let Inst{25} = 0; - let Inst{11-0} = shift; - let Inst{15-12} = Rd; - let Inst{19-16} = Rn; let Inst{20} = 1; + let Inst{19-16} = Rn; + let Inst{15-12} = Rd; + let Inst{11-0} = shift; } } } @@ -607,24 +607,23 @@ bits<4> Rn; bits<12> imm; let Inst{25} = 1; - let Inst{15-12} = 0b0000; + let Inst{20} = 1; let Inst{19-16} = Rn; + let Inst{15-12} = 0b0000; let Inst{11-0} = imm; - let Inst{20} = 1; - let Inst{20} = 1; } def rr : AI1 { bits<4> Rn; bits<4> Rm; - let Inst{11-4} = 0b00000000; - let Inst{25} = 0; let isCommutable = Commutable; - let Inst{3-0} = Rm; - let Inst{15-12} = 0b0000; - let Inst{19-16} = Rn; + let Inst{25} = 0; let Inst{20} = 1; + let Inst{19-16} = Rn; + let Inst{15-12} = 0b0000; + let Inst{11-4} = 0b00000000; + let Inst{3-0} = Rm; } def rs : AI1 Rn; bits<12> shift; let Inst{25} = 0; - let Inst{11-0} = shift; - let Inst{15-12} = 0b0000; - let Inst{19-16} = Rn; let Inst{20} = 1; + let Inst{19-16} = Rn; + let Inst{15-12} = 0b0000; + let Inst{11-0} = shift; } } } @@ -650,10 +649,10 @@ Requires<[IsARM, HasV6]> { bits<4> Rd; bits<4> Rm; + let Inst{19-16} = 0b1111; let Inst{15-12} = Rd; - let Inst{3-0} = Rm; let Inst{11-10} = 0b00; - let Inst{19-16} = 0b1111; + let Inst{3-0} = Rm; } def r_rot : AExtI Rd; bits<4> Rm; bits<2> rot; + let Inst{19-16} = 0b1111; let Inst{15-12} = Rd; let Inst{11-10} = rot; let Inst{3-0} = Rm; - let Inst{19-16} = 0b1111; } } @@ -674,16 +673,16 @@ IIC_iEXTr, opc, "\t$Rd, $Rm", [/* For disassembly only; pattern left blank */]>, Requires<[IsARM, HasV6]> { - let Inst{11-10} = 0b00; let Inst{19-16} = 0b1111; + let Inst{11-10} = 0b00; } def r_rot : AExtI, Requires<[IsARM, HasV6]> { bits<2> rot; - let Inst{11-10} = rot; let Inst{19-16} = 0b1111; + let Inst{11-10} = rot; } } From dalej at apple.com Tue Nov 2 12:59:27 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 02 Nov 2010 17:59:27 -0000 Subject: [llvm-commits] [llvm] r118030 - /llvm/trunk/lib/VMCore/InlineAsm.cpp Message-ID: <20101102175927.582502A6C12C@llvm.org> Author: johannes Date: Tue Nov 2 12:59:27 2010 New Revision: 118030 URL: http://llvm.org/viewvc/llvm-project?rev=118030&view=rev Log: Apply patch for use-after-free in InlineAsm constant handling, PR 8522 / 8616046. Test reduction, analysis and patch by Tim Deegan! (However, review by someone who understands the classes here better is welcome. John Krum will return!) Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=118030&r1=118029&r2=118030&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Tue Nov 2 12:59:27 2010 @@ -47,6 +47,7 @@ } void InlineAsm::destroyConstant() { + getRawType()->getContext().pImpl->InlineAsms.remove(this); delete this; } From gohman at apple.com Tue Nov 2 13:04:27 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 2 Nov 2010 11:04:27 -0700 Subject: [llvm-commits] [llvm] r117596 - /llvm/trunk/lib/System/Unix/Program.inc In-Reply-To: <20101102012241.GA5452@localhost.localdomain> References: <20101028203433.BDCB82A6C12C@llvm.org> <20101029102425.GA2668@localhost.localdomain> <361CB234-1D15-44A4-ADC7-4E4E249DC3F5@apple.com> <20101102012241.GA5452@localhost.localdomain> Message-ID: On Nov 1, 2010, at 6:22 PM, Mikhail Glushenkov wrote: > Hi, > > On Fri, Oct 29, 2010 at 11:12:01AM -0700, Dan Gohman wrote: >> >>>>> Alternatively, we can change FindExecutable to take into account that >>>>> canExecute can be false for the path returned by FindProgramByName. >>>> >>>> >>>> My assumption is that it's perfectly acceptable for FindExecutable >>>> to return a non-executable path here; its caller will attempt to >>>> execute the path, get an error, and report the error to the user, >>> >>> I think it's not. Currently, FindExecutable always succeeds (on unix-likes), >>> even if given a non-absolute path. FindExecutable("something") = >>> Path("$EXE_DIR").appendComponent("something"), which was not the original >>> intent. >> >> The code to call FindProgramByName there was only added as a >> hack for Windows to add a ".exe" suffix. FindExecutable ideally should >> always succeed, because it is primarily just a path manipulation. > > Originally, FindExecutable looked like this: > > sys::Path Result = sys::Path::GetMainExecutable(Argv0, MainAddr); > Result.eraseComponent(); > if (!Result.isEmpty()) { > Result.appendComponent(ExeName); > if (Result.canExecute()) > return Result; > } This was an obsolete artifact. Going back in time further, this code was followed by a PATH search, and in those days the canExecute() check had a purpose. In r78240, I removed the PATH search, and it appears I failed to remove the canExecute() check, even though it was no longer needed. > > Then the call to FindProgramByName was added to append the '.exe' suffix: > > if (Result.isAbsolute()) { > Result = sys::Program::FindProgramByName(Result.str()); > return Result; > } > > On Windows, the behaviour is still the same (because FindProgramByName always > checks for executability), but on unix-likes FindExecutable now always succeeds > (because of the special treatment of absolute paths). IMO, this is a bug. The current usage of FindProgramByName in FindExecutable is admittedly awkward. It solved a problem for someone working on Windows, and the isAbsolute thing was a way to stay pretty close to the desired behavior on Unix. > >>> >>>> What problem are you trying to solve here? >>> >>> I find the current behaviour confusing and I want it to be consistent across >>> platforms. If we decide to standardise on the Unix behaviour, then we should >>> also make the Win32 version of FindProgramByName return absolute paths >>> untouched, and mention this issue in the comments. >> >> >> Currently my understanding is that it modifies absolute paths by appending a >> ".exe" suffix. If there's another way to achieve this, that would probably be >> better. > > I propose the following changes (patches attached): > > 1. Make FindProgramByName() return absolute paths untouched on all platforms > and mention this in the comments. This is fine by me, though I don't know what FindProgramByName's callers expectations are with respect to ".exe" suffixes on Windows. Also, note that on Unix it's not just absolute paths, it's any path containing slashes. I don't know how that translates on Windows. > 2. Add a GetEXESuffix() function to the Path class (there is already > GetDLLSuffix()). Ok. > 3. Make FindExecutable() use GetEXESuffix() instead of FindProgramByName(). Ok. > 4. Make FindExecutable() always return an executable path, as it used to. FindExecutable shouldn't do this. If LLVM tools are installed with .exe suffixes on Windows, FindExecutable should unconditionally append the GetEXESuffix string and return the resulting path. FindExecutable is used when one LLVM tool wants to invoke another LLVM tool. These tools are installed together, so they shouldn't have to do any checking to figure out how to locate each other. Also, it's rare for these tools to be missing, much less present but non-executable. Client code is expected to check for errors after an execute anyway, so doing extra checking up front is redundant and makes the code harder to follow. Dan From sabre at nondot.org Tue Nov 2 13:10:06 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 18:10:06 -0000 Subject: [llvm-commits] [llvm] r118031 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp CodeGenTarget.cpp CodeGenTarget.h Message-ID: <20101102181006.377642A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 13:10:06 2010 New Revision: 118031 URL: http://llvm.org/viewvc/llvm-project?rev=118031&view=rev Log: a bunch of random cleanup, move a helper to CGT where it belongs. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118031&r1=118030&r2=118031&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 13:10:06 2010 @@ -254,7 +254,9 @@ /// The unique class instance this operand should match. ClassInfo *Class; - /// The original operand this corresponds to, if any. + /// The original operand this corresponds to. This is unset for singleton + /// registers and tokens, because they don't have a list in the ins/outs + /// list. If an operand is tied ($a=$b), this refers to source operand: $b. const CGIOperandList::OperandInfo *OperandInfo; explicit Operand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} @@ -601,17 +603,6 @@ -/// getRegisterRecord - Get the register record for \arg name, or 0. -static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) { - for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { - const CodeGenRegister &Reg = Target.getRegisters()[i]; - if (Name == Reg.TheDef->getValueAsString("AsmName")) - return Reg.TheDef; - } - - return 0; -} - bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { // Reject matchables with no .s string. if (AsmString.empty()) @@ -676,14 +667,16 @@ return 0; StringRef RegName = Tok.substr(Info.RegisterPrefix.size()); - if (Record *Rec = getRegisterRecord(Info.Target, RegName)) - return Rec; + if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) + return Reg->TheDef; // If there is no register prefix (i.e. "%" in "%eax"), then this may // be some random non-register token, just ignore it. if (Info.RegisterPrefix.empty()) return 0; + // Otherwise, we have something invalid prefixed with the register prefix, + // such as %foo. std::string Err = "unable to find register for '" + RegName.str() + "' (which matches register prefix)"; throw TGError(TheDef->getLoc(), Err); @@ -730,38 +723,31 @@ AsmMatcherInfo::getOperandClass(StringRef Token, const CGIOperandList::OperandInfo &OI) { if (OI.Rec->isSubClassOf("RegisterClass")) { - ClassInfo *CI = RegisterClassClasses[OI.Rec]; - - if (!CI) - throw TGError(OI.Rec->getLoc(), "register class has no class info!"); - - return CI; + if (ClassInfo *CI = RegisterClassClasses[OI.Rec]) + return CI; + throw TGError(OI.Rec->getLoc(), "register class has no class info!"); } assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!"); Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass"); - ClassInfo *CI = AsmOperandClasses[MatchClass]; - - if (!CI) - throw TGError(OI.Rec->getLoc(), "operand has no match class!"); + if (ClassInfo *CI = AsmOperandClasses[MatchClass]) + return CI; - return CI; + throw TGError(OI.Rec->getLoc(), "operand has no match class!"); } void AsmMatcherInfo:: BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { - std::vector RegisterClasses; - std::vector Registers; - - RegisterClasses = Target.getRegisterClasses(); - Registers = Target.getRegisters(); + const std::vector &Registers = Target.getRegisters(); + const std::vector &RegClassList = + Target.getRegisterClasses(); // The register sets used for matching. std::set< std::set > RegisterSets; // Gather the defined sets. - for (std::vector::iterator it = RegisterClasses.begin(), - ie = RegisterClasses.end(); it != ie; ++it) + for (std::vector::const_iterator it = + RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) RegisterSets.insert(std::set(it->Elements.begin(), it->Elements.end())); @@ -776,9 +762,9 @@ // a unique register set class), and build the mapping of registers to the set // they should classify to. std::map > RegisterMap; - for (std::vector::iterator it = Registers.begin(), + for (std::vector::const_iterator it = Registers.begin(), ie = Registers.end(); it != ie; ++it) { - CodeGenRegister &CGR = *it; + const CodeGenRegister &CGR = *it; // Compute the intersection of all sets containing this register. std::set ContainingSet; @@ -789,14 +775,14 @@ if (ContainingSet.empty()) { ContainingSet = *it; - } else { - std::set Tmp; - std::swap(Tmp, ContainingSet); - std::insert_iterator< std::set > II(ContainingSet, - ContainingSet.begin()); - std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), - II); + continue; } + + std::set Tmp; + std::swap(Tmp, ContainingSet); + std::insert_iterator< std::set > II(ContainingSet, + ContainingSet.begin()); + std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II); } if (!ContainingSet.empty()) { @@ -835,8 +821,8 @@ } // Name the register classes which correspond to a user defined RegisterClass. - for (std::vector::iterator it = RegisterClasses.begin(), - ie = RegisterClasses.end(); it != ie; ++it) { + for (std::vector::const_iterator + it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { ClassInfo *CI = RegisterSetClasses[std::set(it->Elements.begin(), it->Elements.end())]; if (CI->ValueName.empty()) { @@ -852,13 +838,13 @@ // Populate the map for individual registers. for (std::map >::iterator it = RegisterMap.begin(), ie = RegisterMap.end(); it != ie; ++it) - this->RegisterClasses[it->first] = RegisterSetClasses[it->second]; + RegisterClasses[it->first] = RegisterSetClasses[it->second]; // Name the register classes which correspond to singleton registers. for (SmallPtrSet::iterator it = SingletonRegisters.begin(), ie = SingletonRegisters.end(); it != ie; ++it) { Record *Rec = *it; - ClassInfo *CI = this->RegisterClasses[Rec]; + ClassInfo *CI = RegisterClasses[Rec]; assert(CI && "Missing singleton register class info!"); if (CI->ValueName.empty()) { @@ -1135,9 +1121,9 @@ const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i]; for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) { const CGIOperandList::ConstraintInfo &CI = OpInfo.Constraints[j]; - if (CI.isTied()) - TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j, - CI.getTiedOperand())); + if (!CI.isTied()) continue; + TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo, + CI.getTiedOperand())); } } @@ -1147,8 +1133,7 @@ unsigned NumMIOperands = 0; for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { const CGIOperandList::OperandInfo &OI = II.OperandList[i]; - NumMIOperands = std::max(NumMIOperands, - OI.MIOperandNo + OI.MINumOperands); + NumMIOperands = std::max(NumMIOperands, OI.MIOperandNo+OI.MINumOperands); } // Build the conversion function signature. Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=118031&r1=118030&r2=118031&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Nov 2 13:10:06 2010 @@ -190,6 +190,19 @@ RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); } +/// getRegisterByName - If there is a register with the specific AsmName, +/// return it. +const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { + const std::vector &Regs = getRegisters(); + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = Regs[i]; + if (Reg.TheDef->getValueAsString("AsmName") == Name) + return &Reg; + } + + return 0; +} + std::vector CodeGenTarget:: getRegisterVTs(Record *R) const { std::vector Result; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=118031&r1=118030&r2=118031&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Tue Nov 2 13:10:06 2010 @@ -101,6 +101,10 @@ if (Registers.empty()) ReadRegisters(); return Registers; } + + /// getRegisterByName - If there is a register with the specific AsmName, + /// return it. + const CodeGenRegister *getRegisterByName(StringRef Name) const; const std::vector &getSubRegIndices() const { if (SubRegIndices.empty()) ReadSubRegIndices(); From atrick at apple.com Tue Nov 2 13:16:45 2010 From: atrick at apple.com (Andrew Trick) Date: Tue, 02 Nov 2010 18:16:45 -0000 Subject: [llvm-commits] [llvm] r118032 - in /llvm/trunk/lib/CodeGen: CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker.h Message-ID: <20101102181645.B193F2A6C12C@llvm.org> Author: atrick Date: Tue Nov 2 13:16:45 2010 New Revision: 118032 URL: http://llvm.org/viewvc/llvm-project?rev=118032&view=rev Log: Fixes : During postRAsched, the antidependence breaker needs to check all definitions of the antidepenent register to avoid multiple defs of the same new register. Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=118032&r1=118031&r2=118032&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Tue Nov 2 13:16:45 2010 @@ -325,8 +325,25 @@ } } +// Check all machine instructions that define the antidependent register. +// Return true if any of these instructions define the new register. +bool +CriticalAntiDepBreaker::isNewRegModifiedByRefs(RegRefIter RegRefBegin, + RegRefIter RegRefEnd, + unsigned NewReg) +{ + for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) { + MachineOperand *MO = I->second; + if (MO->isDef()) continue; + if (MO->getParent()->modifiesRegister(NewReg, TRI)) + return true; + } + return false; +} + unsigned -CriticalAntiDepBreaker::findSuitableFreeRegister(MachineInstr *MI, +CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin, + RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC) @@ -342,10 +359,10 @@ // an anti-dependence with this AntiDepReg, because that would // re-introduce that anti-dependence. if (NewReg == LastNewReg) continue; - // If the instruction already has a def of the NewReg, it's not suitable. - // For example, Instruction with multiple definitions can result in this - // condition. - if (MI->modifiesRegister(NewReg, TRI)) continue; + // If any instructions that define AntiDepReg also define the NewReg, it's + // not suitable. For example, Instruction with multiple definitions can + // result in this condition. + if (isNewRegModifiedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue; // If NewReg is dead and NewReg's most recent def is not before // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg. assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) @@ -552,7 +569,11 @@ // TODO: Instead of picking the first free register, consider which might // be the best. if (AntiDepReg != 0) { - if (unsigned NewReg = findSuitableFreeRegister(MI, AntiDepReg, + std::pair::iterator, + std::multimap::iterator> + Range = RegRefs.equal_range(AntiDepReg); + if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second, + AntiDepReg, LastNewReg[AntiDepReg], RC)) { DEBUG(dbgs() << "Breaking anti-dependence edge on " @@ -562,9 +583,6 @@ // Update the references to the old register to refer to the new // register. - std::pair::iterator, - std::multimap::iterator> - Range = RegRefs.equal_range(AntiDepReg); for (std::multimap::iterator Q = Range.first, QE = Range.second; Q != QE; ++Q) { Q->second->setReg(NewReg); Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=118032&r1=118031&r2=118032&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Tue Nov 2 13:16:45 2010 @@ -50,6 +50,8 @@ /// RegRegs - Map registers to all their references within a live range. std::multimap RegRefs; + typedef std::multimap::const_iterator + RegRefIter; /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. @@ -90,10 +92,14 @@ private: void PrescanInstruction(MachineInstr *MI); void ScanInstruction(MachineInstr *MI, unsigned Count); - unsigned findSuitableFreeRegister(MachineInstr *MI, + bool isNewRegModifiedByRefs(RegRefIter RegRefBegin, + RegRefIter RegRefEnd, + unsigned NewReg); + unsigned findSuitableFreeRegister(RegRefIter RegRefBegin, + RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, - const TargetRegisterClass *); + const TargetRegisterClass *RC); }; } From john.thompson.jtsoftware at gmail.com Tue Nov 2 14:23:28 2010 From: john.thompson.jtsoftware at gmail.com (John Thompson) Date: Tue, 2 Nov 2010 12:23:28 -0700 Subject: [llvm-commits] [PATCH] Tests for inline asm mult-alt constraint selection - LLVM side Message-ID: I've been sitting on some new test files that just check to make sure llc doesn't abort when it sees the covered subsets of constraints. Should I check them in? I didn't want to check them in with the main changes, as I had a small worry that the behavior might be different on other platforms. I've run these successfully on Win32 and a Linux x86 64-bit system. Is there a possibility that these might behave differently on other platforms? This (plus a clang-side patch I just posted), should be the last of the mult-alt stuff for me for now (barring any problems that come up), as I'm moving on to other Clang areas. -John -- John Thompson John.Thompson.JTSoftware at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/4c11abaa/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvmmultalt19.patch Type: application/octet-stream Size: 96742 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/4c11abaa/attachment-0001.obj From foldr at codedgers.com Tue Nov 2 15:34:03 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 2 Nov 2010 21:34:03 +0100 Subject: [llvm-commits] [llvm] r117596 - /llvm/trunk/lib/System/Unix/Program.inc In-Reply-To: References: <20101028203433.BDCB82A6C12C@llvm.org> <20101029102425.GA2668@localhost.localdomain> <361CB234-1D15-44A4-ADC7-4E4E249DC3F5@apple.com> <20101102012241.GA5452@localhost.localdomain> Message-ID: <20101102203403.GA4908@localhost.localdomain> Hi, On Tue, Nov 02, 2010 at 11:04:27AM -0700, Dan Gohman wrote: > > > 4. Make FindExecutable() always return an executable path, as it used to. > > > FindExecutable shouldn't do this. If LLVM tools are installed with .exe > suffixes on Windows, FindExecutable should unconditionally append the > GetEXESuffix string and return the resulting path. > > FindExecutable is used when one LLVM tool wants to invoke another LLVM > tool. These tools are installed together, so they shouldn't have to do > any checking to figure out how to locate each other. Also, it's rare > for these tools to be missing, much less present but non-executable. > Client code is expected to check for errors after an execute anyway, so > doing extra checking up front is redundant and makes the code harder > to follow. I've applied my patches (with your suggested changes). I also removed the executability check from FindExecutable. The only thing I'm not very happy with is the name of FindExecutable - it's not obvious that this function can return a non-executable path. -- () ascii ribbon campaign - against html e-mail /\ www.asciiribbon.org - against proprietary attachments From foldr at codedgers.com Tue Nov 2 15:32:26 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:32:26 -0000 Subject: [llvm-commits] [llvm] r118042 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Unix/Path.inc lib/System/Win32/Path.inc Message-ID: <20101102203226.A4FA92A6C12E@llvm.org> Author: foldr Date: Tue Nov 2 15:32:26 2010 New Revision: 118042 URL: http://llvm.org/viewvc/llvm-project?rev=118042&view=rev Log: Path: Add GetEXESuffix() to complement GetDLLSuffix(). Modified: llvm/trunk/include/llvm/System/Path.h llvm/trunk/lib/System/Unix/Path.inc llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=118042&r1=118041&r2=118042&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Tue Nov 2 15:32:26 2010 @@ -154,6 +154,12 @@ /// @brief Returns the current working directory. static Path GetCurrentDirectory(); + /// Return the suffix commonly used on file names that contain an + /// executable. + /// @returns The executable file suffix for the current platform. + /// @brief Return the executable file suffix. + static StringRef GetEXESuffix(); + /// Return the suffix commonly used on file names that contain a shared /// object, shared archive, or dynamic link library. Such files are /// linked at runtime into a process and their code images are shared Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118042&r1=118041&r2=118042&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 15:32:26 2010 @@ -78,6 +78,10 @@ const char sys::PathSeparator = ':'; +StringRef Path::GetEXESuffix() { + return ""; +} + Path::Path(StringRef p) : path(p) {} Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118042&r1=118041&r2=118042&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 2 15:32:26 2010 @@ -45,8 +45,13 @@ namespace llvm { namespace sys { + const char PathSeparator = ';'; +StringRef Path::GetEXESuffix() { + return "exe"; +} + Path::Path(llvm::StringRef p) : path(p) { FlipBackSlashes(path); From foldr at codedgers.com Tue Nov 2 15:32:31 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:32:31 -0000 Subject: [llvm-commits] [llvm] r118045 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20101102203231.C08AA2A6C12C@llvm.org> Author: foldr Date: Tue Nov 2 15:32:31 2010 New Revision: 118045 URL: http://llvm.org/viewvc/llvm-project?rev=118045&view=rev Log: 80-col violations. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118045&r1=118044&r2=118045&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 2 15:32:31 2010 @@ -175,8 +175,9 @@ case 2: return NameStart[0] == '/'; default: - return (NameStart[0] == '/' || (NameStart[1] == ':' && NameStart[2] == '/')) || - (NameStart[0] == '\\' || (NameStart[1] == ':' && NameStart[2] == '\\')); + return + (NameStart[0] == '/' || (NameStart[1] == ':' && NameStart[2] == '/')) || + (NameStart[0] == '\\' || (NameStart[1] == ':' && NameStart[2] == '\\')); } } @@ -641,7 +642,8 @@ pathname[len-1] = 0; if (!CreateDirectory(pathname, NULL) && GetLastError() != ERROR_ALREADY_EXISTS) { - return MakeErrMsg(ErrMsg, std::string(pathname) + ": Can't create directory: "); + return MakeErrMsg(ErrMsg, std::string(pathname) + + ": Can't create directory: "); } } return false; From foldr at codedgers.com Tue Nov 2 15:32:39 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:32:39 -0000 Subject: [llvm-commits] [llvm] r118048 - in /llvm/trunk: include/llvm/System/Program.h lib/System/Unix/Program.inc lib/System/Win32/Program.inc Message-ID: <20101102203239.E18B42A6C12C@llvm.org> Author: foldr Date: Tue Nov 2 15:32:39 2010 New Revision: 118048 URL: http://llvm.org/viewvc/llvm-project?rev=118048&view=rev Log: Make FindProgramByName return paths with slashes unmodified on Windows. This makes its behaviour more consistent across platforms. Modified: llvm/trunk/include/llvm/System/Program.h llvm/trunk/lib/System/Unix/Program.inc llvm/trunk/lib/System/Win32/Program.inc Modified: llvm/trunk/include/llvm/System/Program.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Program.h?rev=118048&r1=118047&r2=118048&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Program.h (original) +++ llvm/trunk/include/llvm/System/Program.h Tue Nov 2 15:32:39 2010 @@ -114,7 +114,8 @@ /// This static constructor (factory) will attempt to locate a program in /// the operating system's file system using some pre-determined set of - /// locations to search (e.g. the PATH on Unix). + /// locations to search (e.g. the PATH on Unix). Paths with slashes are + /// returned unmodified. /// @returns A Path object initialized to the path of the program or a /// Path object that is empty (invalid) if the program could not be found. /// @brief Construct a Program by finding it by name. Modified: llvm/trunk/lib/System/Unix/Program.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Program.inc?rev=118048&r1=118047&r2=118048&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Program.inc (original) +++ llvm/trunk/lib/System/Unix/Program.inc Tue Nov 2 15:32:39 2010 @@ -66,8 +66,8 @@ if (progName.find('/') != std::string::npos) return temp; - // At this point, the file name does not contain slashes. Search for it - // through the directories specified in the PATH environment variable. + // At this point, the file name is valid and does not contain slashes. Search + // for it through the directories specified in the PATH environment variable. // Get the path. If its empty, we can't do anything to find it. const char *PathStr = getenv("PATH"); Modified: llvm/trunk/lib/System/Win32/Program.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Program.inc?rev=118048&r1=118047&r2=118048&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Program.inc (original) +++ llvm/trunk/lib/System/Win32/Program.inc Tue Nov 2 15:32:39 2010 @@ -67,10 +67,12 @@ Path temp; if (!temp.set(progName)) // invalid name return Path(); - if (temp.canExecute()) // already executable as is + // Return paths with slashes verbatim. + if (progName.find('\\') != std::string::npos || + progName.find('/') != std::string::npos) return temp; - // At this point, the file name is valid and its not executable. + // At this point, the file name is valid and does not contain slashes. // Let Windows search for it. char buffer[MAX_PATH]; char *dummy = NULL; From foldr at codedgers.com Tue Nov 2 15:32:46 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:32:46 -0000 Subject: [llvm-commits] [llvm] r118049 - in /llvm/trunk: include/llvm/Support/SystemUtils.h lib/Support/SystemUtils.cpp Message-ID: <20101102203246.58AED2A6C12C@llvm.org> Author: foldr Date: Tue Nov 2 15:32:46 2010 New Revision: 118049 URL: http://llvm.org/viewvc/llvm-project?rev=118049&view=rev Log: FindExecutable: remove the executability check. This makes the behaviour of FindExecutable more consistent across platforms, but I'm not very happy with the name... Modified: llvm/trunk/include/llvm/Support/SystemUtils.h llvm/trunk/lib/Support/SystemUtils.cpp Modified: llvm/trunk/include/llvm/Support/SystemUtils.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SystemUtils.h?rev=118049&r1=118048&r2=118049&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/SystemUtils.h (original) +++ llvm/trunk/include/llvm/Support/SystemUtils.h Tue Nov 2 15:32:46 2010 @@ -30,10 +30,10 @@ bool print_warning = true ///< Control whether warnings are printed ); -/// FindExecutable - Find a named executable, giving the argv[0] of program -/// being executed. This allows us to find another LLVM tool if it is built in -/// the same directory. If the executable cannot be found, return an -/// empty string. +/// FindExecutable - Find a named executable, given the value of argv[0] of the +/// program being executed and the address of main itself. This allows us to +/// find another LLVM tool if it is built in the same directory. An empty string +/// is returned on error. /// @brief Find a named executable. sys::Path FindExecutable(const std::string &ExeName, const char *Argv0, void *MainAddr); Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=118049&r1=118048&r2=118049&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Tue Nov 2 15:32:46 2010 @@ -32,11 +32,10 @@ return false; } -/// FindExecutable - Find a named executable, giving the argv[0] of program -/// being executed. This allows us to find another LLVM tool if it is built in -/// the same directory. If the executable cannot be found, return an -/// empty string. -/// @brief Find a named executable. +/// FindExecutable - Find a named executable, given the value of argv[0] of the +/// program being executed and the address of main itself. This allows us to +/// find another LLVM tool if it is built in the same directory. An empty string +/// is returned on error. #undef FindExecutable // needed on windows :( sys::Path llvm::FindExecutable(const std::string &ExeName, const char *Argv0, void *MainAddr) { @@ -45,19 +44,10 @@ // is a relative path to the executable itself. sys::Path Result = sys::Path::GetMainExecutable(Argv0, MainAddr); Result.eraseComponent(); + if (!Result.isEmpty()) { Result.appendComponent(ExeName); - if (Result.canExecute()) - return Result; - // If the path is absolute (and it usually is), call FindProgramByName to - // allow it to try platform-specific logic, such as appending a .exe suffix - // on Windows. Don't do this if we somehow have a relative path, because - // we don't want to go searching the PATH and accidentally find an unrelated - // version of the program. - if (Result.isAbsolute()) { - Result = sys::Program::FindProgramByName(Result.str()); - return Result; - } + Result.appendSuffix(sys::Path::GetEXESuffix()); } return Result; From foldr at codedgers.com Tue Nov 2 15:32:52 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:32:52 -0000 Subject: [llvm-commits] [llvm] r118050 - in /llvm/trunk: lib/Linker/Linker.cpp tools/llvm-ld/llvm-ld.cpp Message-ID: <20101102203252.699D42A6C12D@llvm.org> Author: foldr Date: Tue Nov 2 15:32:52 2010 New Revision: 118050 URL: http://llvm.org/viewvc/llvm-project?rev=118050&view=rev Log: Trailing whitespace. Modified: llvm/trunk/lib/Linker/Linker.cpp llvm/trunk/tools/llvm-ld/llvm-ld.cpp Modified: llvm/trunk/lib/Linker/Linker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/Linker.cpp?rev=118050&r1=118049&r2=118050&view=diff ============================================================================== --- llvm/trunk/lib/Linker/Linker.cpp (original) +++ llvm/trunk/lib/Linker/Linker.cpp Tue Nov 2 15:32:52 2010 @@ -97,13 +97,13 @@ Linker::LoadObject(const sys::Path &FN) { std::string ParseErrorMessage; Module *Result = 0; - + std::auto_ptr Buffer(MemoryBuffer::getFileOrSTDIN(FN.c_str())); if (Buffer.get()) Result = ParseBitcodeFile(Buffer.get(), Context, &ParseErrorMessage); else ParseErrorMessage = "Error reading file '" + FN.str() + "'"; - + if (Result) return std::auto_ptr(Result); Error = "Bitcode file '" + FN.str() + "' could not be loaded"; Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=118050&r1=118049&r2=118050&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original) +++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Tue Nov 2 15:32:52 2010 @@ -98,7 +98,7 @@ static cl::list XLinker("Xlinker", cl::value_desc("option"), cl::desc("Pass options to the system linker")); -// Compatibility options that llvm-ld ignores but are supported for +// Compatibility options that llvm-ld ignores but are supported for // compatibility with LD static cl::opt CO3("soname", cl::Hidden, cl::desc("Compatibility option: ignored")); @@ -112,13 +112,13 @@ static cl::opt CO6("h", cl::Hidden, cl::desc("Compatibility option: ignored")); -static cl::opt CO7("start-group", cl::Hidden, +static cl::opt CO7("start-group", cl::Hidden, cl::desc("Compatibility option: ignored")); -static cl::opt CO8("end-group", cl::Hidden, +static cl::opt CO8("end-group", cl::Hidden, cl::desc("Compatibility option: ignored")); -static cl::opt CO9("m", cl::Hidden, +static cl::opt CO9("m", cl::Hidden, cl::desc("Compatibility option: ignored")); /// This is just for convenience so it doesn't have to be passed around @@ -142,7 +142,7 @@ } static void PrintCommand(const std::vector &args) { - std::vector::const_iterator I = args.begin(), E = args.end(); + std::vector::const_iterator I = args.begin(), E = args.end(); for (; I != E; ++I) if (*I) errs() << "'" << *I << "'" << " "; @@ -384,7 +384,7 @@ args.push_back("-framework"); args.push_back(Frameworks[index]); } - + // Now that "args" owns all the std::strings for the arguments, call the c_str // method to get the underlying string array. We do this game so that the // std::string array is guaranteed to outlive the const char* array. @@ -414,7 +414,7 @@ // Windows doesn't support #!/bin/sh style shell scripts in .exe files. To // support windows systems, we copy the llvm-stub.exe executable from the // build tree to the destination file. - std::string ErrMsg; + std::string ErrMsg; sys::Path llvmstub = FindExecutable("llvm-stub.exe", argv[0], (void *)(intptr_t)&Optimize); if (llvmstub.isEmpty()) @@ -513,7 +513,7 @@ LLVMContext &Context = getGlobalContext(); llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. - + // Initialize passes PassRegistry &Registry = *PassRegistry::getPassRegistry(); initializeCore(Registry); @@ -524,7 +524,7 @@ initializeTransformUtils(Registry); initializeInstCombine(Registry); initializeTarget(Registry); - + // Initial global variable above for convenience printing of program name. progname = sys::Path(argv[0]).getBasename(); @@ -705,7 +705,7 @@ if (GenerateCFile(CFile.str(), BitcodeOutputFilename, llc, ErrMsg)) PrintAndExit(ErrMsg, Composite.get()); - if (GenerateNative(OutputFilename, CFile.str(), + if (GenerateNative(OutputFilename, CFile.str(), NativeLinkItems, gcc, envp, ErrMsg)) PrintAndExit(ErrMsg, Composite.get()); } else { From foldr at codedgers.com Tue Nov 2 15:32:59 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:32:59 -0000 Subject: [llvm-commits] [llvm] r118051 - in /llvm/trunk: lib/Linker/Linker.cpp lib/System/Path.cpp tools/llvm-ld/llvm-ld.cpp Message-ID: <20101102203259.B9C052A6C12C@llvm.org> Author: foldr Date: Tue Nov 2 15:32:59 2010 New Revision: 118051 URL: http://llvm.org/viewvc/llvm-project?rev=118051&view=rev Log: GetDLLSuffix: Remove the leading dot from LTDL_SHLIB_EXT. This allows using GetDLLSuffix() with appendSuffix(). Modified: llvm/trunk/lib/Linker/Linker.cpp llvm/trunk/lib/System/Path.cpp llvm/trunk/tools/llvm-ld/llvm-ld.cpp Modified: llvm/trunk/lib/Linker/Linker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/Linker.cpp?rev=118051&r1=118050&r2=118051&view=diff ============================================================================== --- llvm/trunk/lib/Linker/Linker.cpp (original) +++ llvm/trunk/lib/Linker/Linker.cpp Tue Nov 2 15:32:59 2010 @@ -133,7 +133,7 @@ // Try the libX.so (or .dylib) form FullPath.eraseSuffix(); - FullPath.appendSuffix(&(LTDL_SHLIB_EXT[1])); + FullPath.appendSuffix(sys::Path::GetDLLSuffix()); if (FullPath.isDynamicLibrary()) // Native shared library? return FullPath; if (FullPath.isBitcodeFile()) // .so file containing bitcode? Modified: llvm/trunk/lib/System/Path.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Path.cpp?rev=118051&r1=118050&r2=118051&view=diff ============================================================================== --- llvm/trunk/lib/System/Path.cpp (original) +++ llvm/trunk/lib/System/Path.cpp Tue Nov 2 15:32:59 2010 @@ -192,7 +192,7 @@ } StringRef Path::GetDLLSuffix() { - return LTDL_SHLIB_EXT; + return &(LTDL_SHLIB_EXT[1]); } bool Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=118051&r1=118050&r2=118051&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original) +++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Tue Nov 2 15:32:59 2010 @@ -455,7 +455,7 @@ E = LibPaths.end(); P != E; ++P) { FullLibraryPath = *P; FullLibraryPath.appendComponent("lib" + *i); - FullLibraryPath.appendSuffix(&(LTDL_SHLIB_EXT[1])); + FullLibraryPath.appendSuffix(sys::Path::GetDLLSuffix()); if (!FullLibraryPath.isEmpty()) { if (!FullLibraryPath.isDynamicLibrary()) { // Not a native shared library; mark as invalid From resistor at mac.com Tue Nov 2 15:41:00 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 20:41:00 -0000 Subject: [llvm-commits] [llvm] r118053 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neon-vld-encoding.s Message-ID: <20101102204100.284FE2A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 15:40:59 2010 New Revision: 118053 URL: http://llvm.org/viewvc/llvm-project?rev=118053&view=rev Log: Add correct encodings for the rest of the vld instructions that we generate. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/neon-vld-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118053&r1=118052&r2=118053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 15:40:59 2010 @@ -493,22 +493,34 @@ // VLD1LN : Vector Load (single element to one lane) class VLD1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst), - (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), - IIC_VLD1ln, "vld1", Dt, "\\{$dst[$lane]\\}, $addr", - "$src = $dst", - [(set DPR:$dst, (vector_insert (Ty DPR:$src), - (i32 (LoadOp addrmode6:$addr)), - imm:$lane))]>; + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), + (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), + IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", + "$src = $Vd", + [(set DPR:$Vd, (vector_insert (Ty DPR:$src), + (i32 (LoadOp addrmode6:$Rn)), + imm:$lane))]> { + let Rm = 0b1111; + bits<3> lane; +} class VLD1QLNPseudo : VLDQLNPseudo { let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), (i32 (LoadOp addrmode6:$addr)), imm:$lane))]; } -def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8>; -def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16>; -def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load>; +def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> { + let Inst{7-5} = lane{2-0}; +} +def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> { + let Inst{7-6} = lane{1-0}; + let Inst{4} = Rn{4}; +} +def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{4}; + let Inst{4} = Rn{4}; +} def VLD1LNq8Pseudo : VLD1QLNPseudo; def VLD1LNq16Pseudo : VLD1QLNPseudo; @@ -518,15 +530,26 @@ // ...with address register writeback: class VLD1LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, - "\\{$dst[$lane]\\}, $addr$offset", - "$src = $dst, $addr.addr = $wb", []>; - -def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8">; -def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16">; -def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32">; + "\\{$Vd[$lane]\\}, $Rn$Rm", + "$src = $Vd, $Rn.addr = $wb", []> { + bits<3> lane; +} + +def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; + let Inst{4} = Rn{4}; +} +def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{4}; + let Inst{4} = Rn{4}; +} def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo; def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo; @@ -534,67 +557,108 @@ // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VLD2ln, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr", - "$src1 = $dst1, $src2 = $dst2", []>; + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), + (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", + "$src1 = $Vd, $src2 = $dst2", []> { + let Rm = 0b1111; + bits<3> lane; + + let Inst{4} = Rn{4}; +} -def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">; -def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">; -def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">; +def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VLD2LNd8Pseudo : VLDQLNPseudo; def VLD2LNd16Pseudo : VLDQLNPseudo; def VLD2LNd32Pseudo : VLDQLNPseudo; // ...with double-spaced registers: -def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">; -def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">; +def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VLD2LNq16Pseudo : VLDQQLNPseudo; def VLD2LNq32Pseudo : VLDQQLNPseudo; // ...with address register writeback: class VLD2LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, - "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset", - "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>; + "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", + "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { + bits<3> lane; + let Inst{4} = Rn{4}; +} -def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">; -def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">; -def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">; +def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo; def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo; def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo; -def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">; -def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">; +def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo; def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo; // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, - "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr", - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", + "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> { + let Rm = 0b1111; + bits<3> lane; +} -def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8">; -def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">; -def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">; +def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VLD3LNd8Pseudo : VLDQQLNPseudo; def VLD3LNd16Pseudo : VLDQQLNPseudo; def VLD3LNd32Pseudo : VLDQQLNPseudo; // ...with double-spaced registers: -def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">; -def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">; +def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VLD3LNq16Pseudo : VLDQQQQLNPseudo; def VLD3LNq32Pseudo : VLDQQQQLNPseudo; @@ -602,24 +666,36 @@ // ...with address register writeback: class VLD3LNWB op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3lnu, "vld3", Dt, - "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset", - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb", - []>; + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", + "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", + []> { + bits<3> lane; +} -def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8">; -def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">; -def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">; +def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo; def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo; def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo; -def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">; -def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">; +def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo; def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo; @@ -627,23 +703,40 @@ // VLD4LN : Vector Load (single 4-element structure to one lane) class VLD4LN op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, - "\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr", - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; - -def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8">; -def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16">; -def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32">; + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", + "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { + let Rm = 0b1111; + bits<3> lane; + + let Inst{4} = Rn{4}; +} + +def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VLD4LNd8Pseudo : VLDQQLNPseudo; def VLD4LNd16Pseudo : VLDQQLNPseudo; def VLD4LNd32Pseudo : VLDQQLNPseudo; // ...with double-spaced registers: -def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16">; -def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32">; +def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VLD4LNq16Pseudo : VLDQQQQLNPseudo; def VLD4LNq32Pseudo : VLDQQQQLNPseudo; @@ -651,24 +744,39 @@ // ...with address register writeback: class VLD4LNWB op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, -"\\{$dst1[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset", -"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb", - []>; - -def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8">; -def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16">; -def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32">; +"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", +"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", + []> { + bits<3> lane; + let Inst{4} = Rn{4}; +} + +def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo; def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo; def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo; -def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16">; -def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">; +def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo; def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118053&r1=118052&r2=118053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 15:40:59 2010 @@ -305,7 +305,7 @@ unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); unsigned Align = Imm.getImm(); switch(Align) { - case 8: Align = 0x01; break; + case 2: case 4: case 8: Align = 0x01; break; case 16: Align = 0x02; break; case 32: Align = 0x03; break; default: Align = 0x00; break; Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=118053&r1=118052&r2=118053&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Nov 2 15:40:59 2010 @@ -69,5 +69,42 @@ @ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] vld4.32 {d17, d19, d21, d23}, [r0]! - - \ No newline at end of file +@ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4] + vld1.8 {d16[3]}, [r0] +@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4] + vld1.16 {d16[2]}, [r0, :16] +@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4] + vld1.32 {d16[1]}, [r0, :32] + +@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] + vld2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] + vld2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] + vld2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] + vld2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] + vld2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf4] + vld3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xe0,0xf4] + vld3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xe0,0xf4] + vld3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] @ encoding: [0x6f,0x06,0xe0,0xf4] + vld3.16 {d16[1], d18[1], d20[1]}, [r0] +@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf4] + vld3.32 {d17[1], d19[1], d21[1]}, [r0] + +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf4] + vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf4] + vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4] + vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4] + vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4] + vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] From dpatel at apple.com Tue Nov 2 15:41:14 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 02 Nov 2010 20:41:14 -0000 Subject: [llvm-commits] [llvm] r118054 - /llvm/trunk/lib/Analysis/DebugInfo.cpp Message-ID: <20101102204114.2502B2A6C12C@llvm.org> Author: dpatel Date: Tue Nov 2 15:41:13 2010 New Revision: 118054 URL: http://llvm.org/viewvc/llvm-project?rev=118054&view=rev Log: Fix DIType verifier. The element 3 is DIFile now. Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=118054&r1=118053&r2=118054&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Nov 2 15:41:13 2010 @@ -305,9 +305,10 @@ return false; if (!getContext().Verify()) return false; - - DICompileUnit CU = getCompileUnit(); - if (!CU.Verify()) + unsigned Tag = getTag(); + if (!isBasicType() && Tag != dwarf::DW_TAG_const_type && + Tag != dwarf::DW_TAG_volatile_type && Tag != dwarf::DW_TAG_pointer_type && + Tag != dwarf::DW_TAG_restrict_type && getFilename().empty()) return false; return true; } From resistor at mac.com Tue Nov 2 15:47:39 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 20:47:39 -0000 Subject: [llvm-commits] [llvm] r118055 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td Message-ID: <20101102204739.AEDCF2A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 15:47:39 2010 New Revision: 118055 URL: http://llvm.org/viewvc/llvm-project?rev=118055&view=rev Log: Factor out a common encoding class for loads and stores with a lane parameter. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118055&r1=118054&r2=118055&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 2 15:47:39 2010 @@ -1782,6 +1782,14 @@ let Inst{3-0} = Rm{3-0}; } +class NLdStLn op21_20, bits<4> op11_8, bits<4> op7_4, + dag oops, dag iops, InstrItinClass itin, + string opc, string dt, string asm, string cstr, list pattern> + : NLdSt { + bits<3> lane; +} + class PseudoNLdSt : InstARM { Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118055&r1=118054&r2=118055&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 15:47:39 2010 @@ -493,7 +493,7 @@ // VLD1LN : Vector Load (single element to one lane) class VLD1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", "$src = $Vd", @@ -501,7 +501,6 @@ (i32 (LoadOp addrmode6:$Rn)), imm:$lane))]> { let Rm = 0b1111; - bits<3> lane; } class VLD1QLNPseudo : VLDQLNPseudo { let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), @@ -530,13 +529,11 @@ // ...with address register writeback: class VLD1LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn$Rm", - "$src = $Vd, $Rn.addr = $wb", []> { - bits<3> lane; -} + "$src = $Vd, $Rn.addr = $wb", []>; def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; @@ -557,13 +554,11 @@ // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2", []> { let Rm = 0b1111; - bits<3> lane; - let Inst{4} = Rn{4}; } @@ -594,12 +589,11 @@ // ...with address register writeback: class VLD2LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { - bits<3> lane; let Inst{4} = Rn{4}; } @@ -629,13 +623,12 @@ // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> { let Rm = 0b1111; - bits<3> lane; } def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { @@ -665,16 +658,14 @@ // ...with address register writeback: class VLD3LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3lnu, "vld3", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", - []> { - bits<3> lane; -} + []>; def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; @@ -702,15 +693,13 @@ // VLD4LN : Vector Load (single 4-element structure to one lane) class VLD4LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { let Rm = 0b1111; - bits<3> lane; - let Inst{4} = Rn{4}; } @@ -743,7 +732,7 @@ // ...with address register writeback: class VLD4LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b10, op11_8, op7_4, + : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), @@ -751,7 +740,6 @@ "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", []> { - bits<3> lane; let Inst{4} = Rn{4}; } From foldr at codedgers.com Tue Nov 2 15:47:41 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 20:47:41 -0000 Subject: [llvm-commits] [llvm] r118056 - /llvm/trunk/lib/CompilerDriver/Action.cpp Message-ID: <20101102204741.957D12A6C12D@llvm.org> Author: foldr Date: Tue Nov 2 15:47:41 2010 New Revision: 118056 URL: http://llvm.org/viewvc/llvm-project?rev=118056&view=rev Log: llvmc: Fix tool finding logic. Modified: llvm/trunk/lib/CompilerDriver/Action.cpp Modified: llvm/trunk/lib/CompilerDriver/Action.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/Action.cpp?rev=118056&r1=118055&r2=118056&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/Action.cpp (original) +++ llvm/trunk/lib/CompilerDriver/Action.cpp Tue Nov 2 15:47:41 2010 @@ -53,18 +53,18 @@ #endif } - int ExecuteProgram (const std::string& name, - const StrVector& args) { + int ExecuteProgram (const std::string& name, const StrVector& args) { sys::Path prog(name); - if (!prog.isAbsolute()) + if (!prog.isAbsolute()) { prog = FindExecutable(name, ProgramName, (void *)(intptr_t)&Main); - if (prog.isEmpty()) { - prog = sys::Program::FindProgramByName(name); - if (prog.isEmpty()) { - PrintError("Can't find program '" + name + "'"); - return -1; + if (!prog.canExecute()) { + prog = sys::Program::FindProgramByName(name); + if (prog.isEmpty()) { + PrintError("Can't find program '" + name + "'"); + return -1; + } } } if (!prog.canExecute()) { From gohman at apple.com Tue Nov 2 15:49:49 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 20:49:49 -0000 Subject: [llvm-commits] [llvm] r118057 - /llvm/trunk/lib/Support/SystemUtils.cpp Message-ID: <20101102204949.1CD932A6C12C@llvm.org> Author: djg Date: Tue Nov 2 15:49:48 2010 New Revision: 118057 URL: http://llvm.org/viewvc/llvm-project?rev=118057&view=rev Log: Don't append a dot on platforms which don't use exe suffixes. Modified: llvm/trunk/lib/Support/SystemUtils.cpp Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=118057&r1=118056&r2=118057&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Tue Nov 2 15:49:48 2010 @@ -47,7 +47,9 @@ if (!Result.isEmpty()) { Result.appendComponent(ExeName); - Result.appendSuffix(sys::Path::GetEXESuffix()); + StringRef EXESuffix = sys::Path::GetEXESuffix(); + if (!EXESuffix.empty()) + Result.appendSuffix(EXESuffix); } return Result; From gohman at apple.com Tue Nov 2 15:52:47 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 20:52:47 -0000 Subject: [llvm-commits] [llvm] r118058 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102205247.7264A2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 15:52:47 2010 New Revision: 118058 URL: http://llvm.org/viewvc/llvm-project?rev=118058&view=rev Log: Micro-optimize. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118058&r1=118057&r2=118058&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 15:52:47 2010 @@ -79,7 +79,7 @@ const char sys::PathSeparator = ':'; StringRef Path::GetEXESuffix() { - return ""; + return StringRef(); } Path::Path(StringRef p) From dalej at apple.com Tue Nov 2 16:02:01 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 2 Nov 2010 14:02:01 -0700 Subject: [llvm-commits] [PATCH] Tests for inline asm mult-alt constraint selection - LLVM side In-Reply-To: References: Message-ID: <5361938A-21BB-4CEB-A884-1DC9F09E6FEA@apple.com> On Nov 2, 2010, at 12:23 PMPDT, John Thompson wrote: > I've been sitting on some new test files that just check to make sure llc doesn't abort when it sees the covered subsets of constraints. > > Should I check them in? > > I didn't want to check them in with the main changes, as I had a small worry that the behavior might be different on other platforms. I've run these successfully on Win32 and a Linux x86 64-bit system. Is there a possibility that these might behave differently on other platforms? Sure, but the only way to find out what the behavior is on systems you don't have is to check something in:( Go ahead, but keep an eye on the regression testers. Most portability problems of this sort can be fixed by using -mtriple instead of -march. You might want to strip the metadata first, as I don't think that has anything to do with what you're testing. > This (plus a clang-side patch I just posted), should be the last of the mult-alt stuff for me for now (barring any problems that come up), as I'm moving on to other Clang areas. > -John > > -- > John Thompson > John.Thompson.JTSoftware at gmail.com > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/9cb69c72/attachment-0002.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvmmultalt19.patch Type: application/octet-stream Size: 96743 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/9cb69c72/attachment-0001.obj -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/9cb69c72/attachment-0003.html From foldr at codedgers.com Tue Nov 2 16:06:59 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 2 Nov 2010 21:06:59 +0000 (UTC) Subject: [llvm-commits] =?utf-8?q?=5Bllvm=5D_r118057_-=09/llvm/trunk/lib/S?= =?utf-8?q?upport/SystemUtils=2Ecpp?= References: <20101102204949.1CD932A6C12C@llvm.org> Message-ID: Hi, Dan Gohman writes: > > Author: djg > Date: Tue Nov 2 15:49:48 2010 > New Revision: 118057 > > URL: http://llvm.org/viewvc/llvm-project?rev=118057&view=rev > Log: > Don't append a dot on platforms which don't use exe suffixes. Shouldn't this check be performed in appendSuffix? From resistor at mac.com Tue Nov 2 16:06:06 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 21:06:06 -0000 Subject: [llvm-commits] [llvm] r118067 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vst-encoding.s Message-ID: <20101102210606.9A2072A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 16:06:06 2010 New Revision: 118067 URL: http://llvm.org/viewvc/llvm-project?rev=118067&view=rev Log: Add correct encodings for the basic form of vst1. Added: llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118067&r1=118066&r2=118067&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 16:06:06 2010 @@ -799,22 +799,28 @@ // VST1 : Vector Store (multiple single elements) class VST1D op7_4, string Dt> - : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), - IIC_VST1, "vst1", Dt, "\\{$src\\}, $addr", "", []>; + : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd), + IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} class VST1Q op7_4, string Dt> : NLdSt<0,0b00,0b1010,op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST1x2, - "vst1", Dt, "\\{$src1, $src2\\}, $addr", "", []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2, + "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} -def VST1d8 : VST1D<0b0000, "8">; -def VST1d16 : VST1D<0b0100, "16">; -def VST1d32 : VST1D<0b1000, "32">; -def VST1d64 : VST1D<0b1100, "64">; - -def VST1q8 : VST1Q<0b0000, "8">; -def VST1q16 : VST1Q<0b0100, "16">; -def VST1q32 : VST1Q<0b1000, "32">; -def VST1q64 : VST1Q<0b1100, "64">; +def VST1d8 : VST1D<{0,0,0,?}, "8">; +def VST1d16 : VST1D<{0,1,0,?}, "16">; +def VST1d32 : VST1D<{1,0,0,?}, "32">; +def VST1d64 : VST1D<{1,1,0,?}, "64">; + +def VST1q8 : VST1Q<{0,0,?,?}, "8">; +def VST1q16 : VST1Q<{0,1,?,?}, "16">; +def VST1q32 : VST1Q<{1,0,?,?}, "32">; +def VST1q64 : VST1Q<{1,1,?,?}, "64">; def VST1q8Pseudo : VSTQPseudo; def VST1q16Pseudo : VSTQPseudo; @@ -824,23 +830,27 @@ // ...with address register writeback: class VST1DWB op7_4, string Dt> : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, DPR:$src), IIC_VST1u, - "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>; + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u, + "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} class VST1QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2), - IIC_VST1x2u, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset", - "$addr.addr = $wb", []>; + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2), + IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} -def VST1d8_UPD : VST1DWB<0b0000, "8">; -def VST1d16_UPD : VST1DWB<0b0100, "16">; -def VST1d32_UPD : VST1DWB<0b1000, "32">; -def VST1d64_UPD : VST1DWB<0b1100, "64">; - -def VST1q8_UPD : VST1QWB<0b0000, "8">; -def VST1q16_UPD : VST1QWB<0b0100, "16">; -def VST1q32_UPD : VST1QWB<0b1000, "32">; -def VST1q64_UPD : VST1QWB<0b1100, "64">; +def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">; +def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">; +def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">; +def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">; + +def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">; +def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">; +def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">; +def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">; def VST1q8Pseudo_UPD : VSTQWBPseudo; def VST1q16Pseudo_UPD : VSTQWBPseudo; @@ -850,24 +860,29 @@ // ...with 3 registers (some of these are only for the disassembler): class VST1D3 op7_4, string Dt> : NLdSt<0, 0b00, 0b0110, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), - IIC_VST1x3, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), + IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} class VST1D3WB op7_4, string Dt> : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3), - IIC_VST1x3u, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset", - "$addr.addr = $wb", []>; - -def VST1d8T : VST1D3<0b0000, "8">; -def VST1d16T : VST1D3<0b0100, "16">; -def VST1d32T : VST1D3<0b1000, "32">; -def VST1d64T : VST1D3<0b1100, "64">; - -def VST1d8T_UPD : VST1D3WB<0b0000, "8">; -def VST1d16T_UPD : VST1D3WB<0b0100, "16">; -def VST1d32T_UPD : VST1D3WB<0b1000, "32">; -def VST1d64T_UPD : VST1D3WB<0b1100, "64">; + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3), + IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} + +def VST1d8T : VST1D3<{0,0,0,?}, "8">; +def VST1d16T : VST1D3<{0,1,0,?}, "16">; +def VST1d32T : VST1D3<{1,0,0,?}, "32">; +def VST1d64T : VST1D3<{1,1,0,?}, "64">; + +def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">; +def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">; +def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">; +def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">; def VST1d64TPseudo : VSTQQPseudo; def VST1d64TPseudo_UPD : VSTQQWBPseudo; @@ -875,25 +890,30 @@ // ...with 4 registers (some of these are only for the disassembler): class VST1D4 op7_4, string Dt> : NLdSt<0, 0b00, 0b0010, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST1x4, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "", - []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "", + []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} class VST1D4WB op7_4, string Dt> : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u, - "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset", - "$addr.addr = $wb", []>; - -def VST1d8Q : VST1D4<0b0000, "8">; -def VST1d16Q : VST1D4<0b0100, "16">; -def VST1d32Q : VST1D4<0b1000, "32">; -def VST1d64Q : VST1D4<0b1100, "64">; - -def VST1d8Q_UPD : VST1D4WB<0b0000, "8">; -def VST1d16Q_UPD : VST1D4WB<0b0100, "16">; -def VST1d32Q_UPD : VST1D4WB<0b1000, "32">; -def VST1d64Q_UPD : VST1D4WB<0b1100, "64">; + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u, + "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} + +def VST1d8Q : VST1D4<{0,0,?,?}, "8">; +def VST1d16Q : VST1D4<{0,1,?,?}, "16">; +def VST1d32Q : VST1D4<{1,0,?,?}, "32">; +def VST1d64Q : VST1D4<{1,1,?,?}, "64">; + +def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">; +def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">; +def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">; +def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">; def VST1d64QPseudo : VSTQQPseudo; def VST1d64QPseudo_UPD : VSTQQWBPseudo; Added: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=118067&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Nov 2 16:06:06 2010 @@ -0,0 +1,20 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s +@ XFAIL: * + +@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4] + vst1.8 {d16}, [r0, :64] +@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4] + vst1.16 {d16}, [r0] +@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4] + vst1.32 {d16}, [r0] +@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4] + vst1.64 {d16}, [r0] +@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4] + vst1.8 {d16, d17}, [r0, :64] +@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4] + vst1.16 {d16, d17}, [r0, :128] +@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4] + vst1.32 {d16, d17}, [r0] +@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4] + vst1.64 {d16, d17}, [r0] + From resistor at mac.com Tue Nov 2 16:16:58 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 21:16:58 -0000 Subject: [llvm-commits] [llvm] r118068 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vst-encoding.s Message-ID: <20101102211658.95FF62A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 16:16:58 2010 New Revision: 118068 URL: http://llvm.org/viewvc/llvm-project?rev=118068&view=rev Log: Add correct encodings for the basic variants for vst2. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118068&r1=118067&r2=118068&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 16:16:58 2010 @@ -921,21 +921,27 @@ // VST2 : Vector Store (multiple 2-element structures) class VST2D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2), - IIC_VST2, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), + IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} class VST2Q op7_4, string Dt> : NLdSt<0, 0b00, 0b0011, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST2x2, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", - "", []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", + "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} -def VST2d8 : VST2D<0b1000, 0b0000, "8">; -def VST2d16 : VST2D<0b1000, 0b0100, "16">; -def VST2d32 : VST2D<0b1000, 0b1000, "32">; - -def VST2q8 : VST2Q<0b0000, "8">; -def VST2q16 : VST2Q<0b0100, "16">; -def VST2q32 : VST2Q<0b1000, "32">; +def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">; +def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">; +def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">; + +def VST2q8 : VST2Q<{0,0,?,?}, "8">; +def VST2q16 : VST2Q<{0,1,?,?}, "16">; +def VST2q32 : VST2Q<{1,0,?,?}, "32">; def VST2d8Pseudo : VSTQPseudo; def VST2d16Pseudo : VSTQPseudo; @@ -948,23 +954,27 @@ // ...with address register writeback: class VST2DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2), - IIC_VST2u, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset", - "$addr.addr = $wb", []>; + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2), + IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} class VST2QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u, - "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset", - "$addr.addr = $wb", []>; + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u, + "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} -def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">; -def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">; -def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">; - -def VST2q8_UPD : VST2QWB<0b0000, "8">; -def VST2q16_UPD : VST2QWB<0b0100, "16">; -def VST2q32_UPD : VST2QWB<0b1000, "32">; +def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">; +def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">; +def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">; + +def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">; +def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">; +def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">; def VST2d8Pseudo_UPD : VSTQWBPseudo; def VST2d16Pseudo_UPD : VSTQWBPseudo; @@ -975,12 +985,12 @@ def VST2q32Pseudo_UPD : VSTQQWBPseudo; // ...with double-spaced registers (for disassembly only): -def VST2b8 : VST2D<0b1001, 0b0000, "8">; -def VST2b16 : VST2D<0b1001, 0b0100, "16">; -def VST2b32 : VST2D<0b1001, 0b1000, "32">; -def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">; -def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">; -def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">; +def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">; +def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">; +def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">; +def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">; +def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">; +def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">; // VST3 : Vector Store (multiple 3-element structures) class VST3D op11_8, bits<4> op7_4, string Dt> Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=118068&r1=118067&r2=118068&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Nov 2 16:16:58 2010 @@ -18,3 +18,15 @@ @ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4] vst1.64 {d16, d17}, [r0] +@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4] + vst2.8 {d16, d17}, [r0, :64] +@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4] + vst2.16 {d16, d17}, [r0, :128] +@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4] + vst2.32 {d16, d17}, [r0] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4] + vst2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4] + vst2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4] + vst2.32 {d16, d17, d18, d19}, [r0, :256] From bob.wilson at apple.com Tue Nov 2 16:18:25 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 02 Nov 2010 21:18:25 -0000 Subject: [llvm-commits] [llvm] r118069 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMInstrNEON.td ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td Message-ID: <20101102211825.B9FB52A6C12C@llvm.org> Author: bwilson Date: Tue Nov 2 16:18:25 2010 New Revision: 118069 URL: http://llvm.org/viewvc/llvm-project?rev=118069&view=rev Log: Add NEON VST1-lane instructions. Partial fix for Radar 8599955. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMSchedule.td llvm/trunk/lib/Target/ARM/ARMScheduleA8.td llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=118069&r1=118068&r2=118069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Nov 2 16:18:25 2010 @@ -111,11 +111,11 @@ static const NEONLdStTableEntry NEONLdStTable[] = { { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 }, -{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, false, EvenDblSpc, 1, 4 }, +{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 }, { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 }, -{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, false, EvenDblSpc, 1, 2 }, +{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 }, { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 }, -{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, false, EvenDblSpc, 1, 8 }, +{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 }, { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, @@ -206,6 +206,13 @@ { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, +{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 }, +{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 }, +{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 }, +{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 }, +{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 }, +{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 }, + { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, @@ -989,6 +996,12 @@ case ARM::VLD4LNd32Pseudo_UPD: case ARM::VLD4LNq16Pseudo_UPD: case ARM::VLD4LNq32Pseudo_UPD: + case ARM::VST1LNq8Pseudo: + case ARM::VST1LNq16Pseudo: + case ARM::VST1LNq32Pseudo: + case ARM::VST1LNq8Pseudo_UPD: + case ARM::VST1LNq16Pseudo_UPD: + case ARM::VST1LNq32Pseudo_UPD: case ARM::VST2LNd8Pseudo: case ARM::VST2LNd16Pseudo: case ARM::VST2LNd32Pseudo: Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118069&r1=118068&r2=118069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 16:18:25 2010 @@ -1087,6 +1087,8 @@ def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo; def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo; +} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 + // Classes for VST*LN pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VSTQLNPseudo @@ -1112,7 +1114,36 @@ nohash_imm:$lane), itin, "$addr.addr = $wb">; // VST1LN : Vector Store (single element from one lane) -// FIXME: Not yet implemented. +class VST1LN op11_8, bits<4> op7_4, string Dt> + : NLdSt<1, 0b00, op11_8, op7_4, (outs), + (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), + IIC_VST1ln, "vst1", Dt, "\\{$src[$lane]\\}, $addr", "", []>; + +def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8">; +def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16">; +def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32">; + +def VST1LNq8Pseudo : VSTQLNPseudo; +def VST1LNq16Pseudo : VSTQLNPseudo; +def VST1LNq32Pseudo : VSTQLNPseudo; + +let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { + +// ...with address register writeback: +class VST1LNWB op11_8, bits<4> op7_4, string Dt> + : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, + DPR:$src, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, + "\\{$src[$lane]\\}, $addr$offset", + "$addr.addr = $wb", []>; + +def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8">; +def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16">; +def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32">; + +def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo; +def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo; +def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo; // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, bits<4> op7_4, string Dt> Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=118069&r1=118068&r2=118069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original) +++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Tue Nov 2 16:18:25 2010 @@ -158,6 +158,8 @@ def IIC_VST1x2u : InstrItinClass; def IIC_VST1x3u : InstrItinClass; def IIC_VST1x4u : InstrItinClass; +def IIC_VST1ln : InstrItinClass; +def IIC_VST1lnu : InstrItinClass; def IIC_VST2 : InstrItinClass; def IIC_VST2x2 : InstrItinClass; def IIC_VST2u : InstrItinClass; Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=118069&r1=118068&r2=118069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Tue Nov 2 16:18:25 2010 @@ -601,6 +601,18 @@ InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // + // VST1ln + InstrItinData, + InstrStage<2, [A8_NLSPipe], 1>, + InstrStage<2, [A8_LSPipe]>], + [1, 1, 1]>, + // + // VST1lnu + InstrItinData, + InstrStage<2, [A8_NLSPipe], 1>, + InstrStage<2, [A8_LSPipe]>], + [2, 1, 1, 1, 1]>, + // // VST2 InstrItinData, InstrStage<2, [A8_NLSPipe], 1>, Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=118069&r1=118068&r2=118069&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Tue Nov 2 16:18:25 2010 @@ -1005,6 +1005,24 @@ InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // + // VST1ln + InstrItinData, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<2, [A9_DRegsVFP], 0, Reserved>, + InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_LSUnit]>], + [1, 1, 1]>, + // + // VST1lnu + InstrItinData, + InstrStage<1, [A9_MUX0], 0>, + InstrStage<1, [A9_DRegsN], 0, Required>, + InstrStage<3, [A9_DRegsVFP], 0, Reserved>, + InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_LSUnit]>], + [2, 1, 1, 1, 1]>, + // // VST2 InstrItinData, InstrStage<1, [A9_MUX0], 0>, From sabre at nondot.org Tue Nov 2 16:28:23 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 21:28:23 -0000 Subject: [llvm-commits] [www] r118071 - /www/trunk/index.html Message-ID: <20101102212823.B26222A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 16:28:23 2010 New Revision: 118071 URL: http://llvm.org/viewvc/llvm-project?rev=118071&view=rev Log: fix typo, PR8533 Modified: www/trunk/index.html Modified: www/trunk/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=118071&r1=118070&r2=118071&view=diff ============================================================================== --- www/trunk/index.html (original) +++ www/trunk/index.html Tue Nov 2 16:28:23 2010 @@ -34,7 +34,7 @@ known as the LLVM intermediate representation ("LLVM IR"). The LLVM Core libraries are well documented, and it is particularly easy to invent your own language (or port an existing compiler) to use - LLVM as a optimizer and code generator.

    + LLVM as an optimizer and code generator.

  • Clang is an "LLVM native" From ofv at wanadoo.es Tue Nov 2 16:34:20 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Tue, 02 Nov 2010 21:34:20 -0000 Subject: [llvm-commits] [llvm] r118072 - /llvm/trunk/docs/GettingStarted.html Message-ID: <20101102213420.377DC2A6C12C@llvm.org> Author: ofv Date: Tue Nov 2 16:34:19 2010 New Revision: 118072 URL: http://llvm.org/viewvc/llvm-project?rev=118072&view=rev Log: Removed obsolete section about VC++ project files. Modified: llvm/trunk/docs/GettingStarted.html Modified: llvm/trunk/docs/GettingStarted.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=118072&r1=118071&r2=118072&view=diff ============================================================================== --- llvm/trunk/docs/GettingStarted.html (original) +++ llvm/trunk/docs/GettingStarted.html Tue Nov 2 16:34:19 2010 @@ -47,7 +47,6 @@

  • test-suite
  • llvm/tools
  • llvm/utils
    • -
  • llvm/win32
  • An Example Using the LLVM Tool Chain @@ -1518,15 +1517,6 @@ - -
    llvm/win32
    -
    -

    This directory contains build scripts and project files for use with - Visual C++. This allows developers on Windows to build LLVM without the need - for Cygwin. The contents of this directory should be considered experimental - at this time. -

    -
    An Example Using the LLVM Tool Chain From rafael.espindola at gmail.com Tue Nov 2 16:38:23 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 02 Nov 2010 21:38:23 -0000 Subject: [llvm-commits] [llvm] r118080 - in /llvm/trunk: include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp Message-ID: <20101102213823.3BC262A6C12C@llvm.org> Author: rafael Date: Tue Nov 2 16:38:23 2010 New Revision: 118080 URL: http://llvm.org/viewvc/llvm-project?rev=118080&view=rev Log: Do relaxations with FT_Org fragments. Fixes the FIXME: // FIXME: We should compute this sooner, we don't want to recurse here, and // we would like to be more functional. In MCAssembler::ComputeFragmentSize. Modified: llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/lib/MC/MCAssembler.cpp Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=118080&r1=118079&r2=118080&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Tue Nov 2 16:38:23 2010 @@ -319,10 +319,13 @@ /// Value - Value to use for filling bytes. int8_t Value; + /// Size - The current estimate of the size. + unsigned Size; + public: MCOrgFragment(const MCExpr &_Offset, int8_t _Value, MCSectionData *SD = 0) : MCFragment(FT_Org, SD), - Offset(&_Offset), Value(_Value) {} + Offset(&_Offset), Value(_Value), Size(0) {} /// @name Accessors /// @{ @@ -331,6 +334,9 @@ uint8_t getValue() const { return Value; } + unsigned getSize() const { return Size; } + + void setSize(unsigned Size_) { Size = Size_; } /// @} static bool classof(const MCFragment *F) { @@ -715,6 +721,9 @@ bool RelaxInstruction(const MCObjectWriter &Writer, MCAsmLayout &Layout, MCInstFragment &IF); + bool RelaxOrg(const MCObjectWriter &Writer, MCAsmLayout &Layout, + MCOrgFragment &OF); + bool RelaxLEB(const MCObjectWriter &Writer, MCAsmLayout &Layout, MCLEBFragment &IF); Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=118080&r1=118079&r2=118080&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Nov 2 16:38:23 2010 @@ -337,23 +337,8 @@ return Size; } - case MCFragment::FT_Org: { - const MCOrgFragment &OF = cast(F); - - // FIXME: We should compute this sooner, we don't want to recurse here, and - // we would like to be more functional. - int64_t TargetLocation; - if (!OF.getOffset().EvaluateAsAbsolute(TargetLocation, &Layout)) - report_fatal_error("expected assembly-time absolute expression"); - - // FIXME: We need a way to communicate this error. - int64_t Offset = TargetLocation - FragmentOffset; - if (Offset < 0 || Offset >= 0x40000000) - report_fatal_error("invalid .org offset '" + Twine(TargetLocation) + - "' (at offset '" + Twine(FragmentOffset) + "')"); - - return Offset; - } + case MCFragment::FT_Org: + return cast(F).getSize(); case MCFragment::FT_Dwarf: { const MCDwarfLineAddrFragment &OF = cast(F); @@ -841,6 +826,25 @@ return true; } +bool MCAssembler::RelaxOrg(const MCObjectWriter &Writer, + MCAsmLayout &Layout, + MCOrgFragment &OF) { + int64_t TargetLocation; + if (!OF.getOffset().EvaluateAsAbsolute(TargetLocation, &Layout)) + report_fatal_error("expected assembly-time absolute expression"); + + // FIXME: We need a way to communicate this error. + uint64_t FragmentOffset = Layout.getFragmentOffset(&OF); + int64_t Offset = TargetLocation - FragmentOffset; + if (Offset < 0 || Offset >= 0x40000000) + report_fatal_error("invalid .org offset '" + Twine(TargetLocation) + + "' (at offset '" + Twine(FragmentOffset) + "')"); + + unsigned OldSize = OF.getSize(); + OF.setSize(Offset); + return OldSize != OF.getSize(); +} + bool MCAssembler::RelaxLEB(const MCObjectWriter &Writer, MCAsmLayout &Layout, MCLEBFragment &LF) { @@ -857,7 +861,6 @@ return OldSize != LF.getSize(); } - bool MCAssembler::LayoutOnce(const MCObjectWriter &Writer, MCAsmLayout &Layout) { ++stats::RelaxationSteps; @@ -880,6 +883,9 @@ WasRelaxed |= RelaxInstruction(Writer, Layout, *cast(it2)); break; + case MCFragment::FT_Org: + WasRelaxed |= RelaxOrg(Writer, Layout, *cast(it2)); + break; case MCFragment::FT_LEB: WasRelaxed |= RelaxLEB(Writer, Layout, *cast(it2)); break; From gohman at apple.com Tue Nov 2 16:44:17 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 2 Nov 2010 14:44:17 -0700 Subject: [llvm-commits] [llvm] r118057 - /llvm/trunk/lib/Support/SystemUtils.cpp In-Reply-To: References: <20101102204949.1CD932A6C12C@llvm.org> Message-ID: On Nov 2, 2010, at 2:06 PM, Mikhail Glushenkov wrote: > Hi, > > Dan Gohman writes: > >> >> Author: djg >> Date: Tue Nov 2 15:49:48 2010 >> New Revision: 118057 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118057&view=rev >> Log: >> Don't append a dot on platforms which don't use exe suffixes. > > Shouldn't this check be performed in appendSuffix? Either way is fine by me. Dan From resistor at mac.com Tue Nov 2 16:47:04 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 21:47:04 -0000 Subject: [llvm-commits] [llvm] r118082 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vst-encoding.s Message-ID: <20101102214704.28D352A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 16:47:03 2010 New Revision: 118082 URL: http://llvm.org/viewvc/llvm-project?rev=118082&view=rev Log: Add correct encodings for basic variants for vst3 and vst4. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118082&r1=118081&r2=118082&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 16:47:03 2010 @@ -995,12 +995,15 @@ // VST3 : Vector Store (multiple 3-element structures) class VST3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST3, - "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, + "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} -def VST3d8 : VST3D<0b0100, 0b0000, "8">; -def VST3d16 : VST3D<0b0100, 0b0100, "16">; -def VST3d32 : VST3D<0b0100, 0b1000, "32">; +def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">; +def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">; +def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">; def VST3d8Pseudo : VSTQQPseudo; def VST3d16Pseudo : VSTQQPseudo; @@ -1009,26 +1012,28 @@ // ...with address register writeback: class VST3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST3u, - "vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset", - "$addr.addr = $wb", []>; + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u, + "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} -def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">; -def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">; -def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">; +def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">; +def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">; +def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">; def VST3d8Pseudo_UPD : VSTQQWBPseudo; def VST3d16Pseudo_UPD : VSTQQWBPseudo; def VST3d32Pseudo_UPD : VSTQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): -def VST3q8 : VST3D<0b0101, 0b0000, "8">; -def VST3q16 : VST3D<0b0101, 0b0100, "16">; -def VST3q32 : VST3D<0b0101, 0b1000, "32">; -def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">; -def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">; -def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">; +def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">; +def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">; +def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">; +def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">; +def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">; +def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">; def VST3q8Pseudo_UPD : VSTQQQQWBPseudo; def VST3q16Pseudo_UPD : VSTQQQQWBPseudo; @@ -1042,13 +1047,16 @@ // VST4 : Vector Store (multiple 4-element structures) class VST4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST4, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", - "", []>; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", + "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; +} -def VST4d8 : VST4D<0b0000, 0b0000, "8">; -def VST4d16 : VST4D<0b0000, 0b0100, "16">; -def VST4d32 : VST4D<0b0000, 0b1000, "32">; +def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">; +def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">; +def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">; def VST4d8Pseudo : VSTQQPseudo; def VST4d16Pseudo : VSTQQPseudo; @@ -1057,26 +1065,28 @@ // ...with address register writeback: class VST4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, - "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset", - "$addr.addr = $wb", []>; + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, + "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; +} -def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">; -def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">; -def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">; +def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">; +def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">; +def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">; def VST4d8Pseudo_UPD : VSTQQWBPseudo; def VST4d16Pseudo_UPD : VSTQQWBPseudo; def VST4d32Pseudo_UPD : VSTQQWBPseudo; // ...with double-spaced registers (non-updating versions for disassembly only): -def VST4q8 : VST4D<0b0001, 0b0000, "8">; -def VST4q16 : VST4D<0b0001, 0b0100, "16">; -def VST4q32 : VST4D<0b0001, 0b1000, "32">; -def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">; -def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">; -def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">; +def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">; +def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">; +def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">; +def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">; +def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">; +def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">; def VST4q8Pseudo_UPD : VSTQQQQWBPseudo; def VST4q16Pseudo_UPD : VSTQQQQWBPseudo; Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=118082&r1=118081&r2=118082&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Nov 2 16:47:03 2010 @@ -30,3 +30,39 @@ vst2.16 {d16, d17, d18, d19}, [r0, :128] @ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4] vst2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf4] + vst3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf4] + vst3.16 {d16, d17, d18}, [r0] +@ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf4] + vst3.32 {d16, d17, d18}, [r0] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4] + vst3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf4] + vst3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf4] + vst3.16 {d16, d18, d20}, [r0]! +@ CHECK: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf4] + vst3.16 {d17, d19, d21}, [r0]! +@ CHECK: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf4] + vst3.32 {d16, d18, d20}, [r0]! +@ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf4] + vst3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf4] + vst4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf4] + vst4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf4] + vst4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf4] + vst4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf4] + vst4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf4] + vst4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf4] + vst4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4] + vst4.32 {d17, d19, d21, d23}, [r0]! From sabre at nondot.org Tue Nov 2 16:49:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 21:49:44 -0000 Subject: [llvm-commits] [llvm] r118083 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101102214944.6058F2A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 16:49:44 2010 New Revision: 118083 URL: http://llvm.org/viewvc/llvm-project?rev=118083&view=rev Log: merge two large parallel loops in EmitConvertToMCInst, no change in the generated .inc files. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118083&r1=118082&r2=118083&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 16:49:44 2010 @@ -1139,49 +1139,73 @@ // Build the conversion function signature. std::string Signature = "Convert"; unsigned CurIndex = 0; + + std::string CaseBody; + raw_string_ostream CaseOS(CaseBody); + + // Compute the convert enum and the case body. for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; assert(CurIndex <= Op.OperandInfo->MIOperandNo && "Duplicate match for instruction operand!"); - // Skip operands which weren't matched by anything, this occurs when the - // .td file encodes "implicit" operands as explicit ones. - // - // FIXME: This should be removed from the MCInst structure. + // Add the implicit operands. for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { + // See if this is a tied operand. std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, CurIndex); - if (!Tie) + + if (!Tie) { + // If not, this is some implicit operand. Just assume it is a register + // for now. + CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; Signature += "__Imp"; - else + } else { + // Copy the tied operand. + assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); + CaseOS << " Inst.addOperand(Inst.getOperand(" + << Tie->second << "));\n"; Signature += "__Tie" + utostr(Tie->second); + } } - - Signature += "__"; - + // Registers are always converted the same, don't duplicate the conversion // function based on them. // // FIXME: We could generalize this based on the render method, if it // mattered. + Signature += "__"; if (Op.Class->isRegisterClass()) Signature += "Reg"; else Signature += Op.Class->ClassName; Signature += utostr(Op.OperandInfo->MINumOperands); Signature += "_" + utostr(MIOperandList[i].second); - + + + CaseOS << " ((" << TargetOperandClass << "*)Operands[" + << MIOperandList[i].second << "+1])->" << Op.Class->RenderMethod + << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; CurIndex += Op.OperandInfo->MINumOperands; } - - // Add any trailing implicit operands. + + // And add trailing implicit operands. for (; CurIndex != NumMIOperands; ++CurIndex) { std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, CurIndex); - if (!Tie) + + if (!Tie) { + // If not, this is some implicit operand. Just assume it is a register + // for now. + CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; Signature += "__Imp"; - else + } else { + // Copy the tied operand. + assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); + CaseOS << " Inst.addOperand(Inst.getOperand(" + << Tie->second << "));\n"; Signature += "__Tie" + utostr(Tie->second); + } } II.ConversionFnKind = Signature; @@ -1190,59 +1214,11 @@ if (!GeneratedFns.insert(Signature).second) continue; - // If not, emit it now. - - // Add to the enum list. + // If not, emit it now. Add to the enum list. OS << " " << Signature << ",\n"; - // And to the convert function. CvtOS << " case " << Signature << ":\n"; - CurIndex = 0; - for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; - - // Add the implicit operands. - for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { - // See if this is a tied operand. - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - - if (!Tie) { - // If not, this is some implicit operand. Just assume it is a register - // for now. - CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - } else { - // Copy the tied operand. - assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); - CvtOS << " Inst.addOperand(Inst.getOperand(" - << Tie->second << "));\n"; - } - } - - CvtOS << " ((" << TargetOperandClass << "*)Operands[" - << MIOperandList[i].second - << "+1])->" << Op.Class->RenderMethod - << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; - CurIndex += Op.OperandInfo->MINumOperands; - } - - // And add trailing implicit operands. - for (; CurIndex != NumMIOperands; ++CurIndex) { - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - - if (!Tie) { - // If not, this is some implicit operand. Just assume it is a register - // for now. - CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - } else { - // Copy the tied operand. - assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); - CvtOS << " Inst.addOperand(Inst.getOperand(" - << Tie->second << "));\n"; - } - } - + CvtOS << CaseOS.str(); CvtOS << " return;\n"; } From resistor at mac.com Tue Nov 2 16:54:45 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 21:54:45 -0000 Subject: [llvm-commits] [llvm] r118084 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20101102215445.E67472A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 16:54:45 2010 New Revision: 118084 URL: http://llvm.org/viewvc/llvm-project?rev=118084&view=rev Log: Tentative encodings for the "single element from one lane" variant of vst1. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118084&r1=118083&r2=118084&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 16:54:45 2010 @@ -1125,13 +1125,23 @@ // VST1LN : Vector Store (single element from one lane) class VST1LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), - IIC_VST1ln, "vst1", Dt, "\\{$src[$lane]\\}, $addr", "", []>; - -def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8">; -def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16">; -def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32">; + : NLdStLn<1, 0b00, op11_8, op7_4, (outs), + (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), + IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", []> { + let Rm = 0b1111; +} + +def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; + let Inst{4} = Rn{5}; +} +def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5-4} = Rn{5-4}; +} def VST1LNq8Pseudo : VSTQLNPseudo; def VST1LNq16Pseudo : VSTQLNPseudo; @@ -1141,15 +1151,23 @@ // ...with address register writeback: class VST1LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, - "\\{$src[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []>; - -def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8">; -def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16">; -def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32">; + : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, + "\\{$Vd[$lane]\\}, $Rn$Rm", + "$Rn.addr = $wb", []>; + +def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; + let Inst{4} = Rn{5}; +} +def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5-4} = Rn{5-4}; +} def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo; def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo; From bob.wilson at apple.com Tue Nov 2 17:02:33 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 2 Nov 2010 15:02:33 -0700 Subject: [llvm-commits] [llvm] r118084 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td In-Reply-To: <20101102215445.E67472A6C12C@llvm.org> References: <20101102215445.E67472A6C12C@llvm.org> Message-ID: Oh, no! Owen is catching up to me. I'd better add some more instructions.... ;-) Thanks, Owen On Nov 2, 2010, at 2:54 PM, Owen Anderson wrote: > Author: resistor > Date: Tue Nov 2 16:54:45 2010 > New Revision: 118084 > > URL: http://llvm.org/viewvc/llvm-project?rev=118084&view=rev > Log: > Tentative encodings for the "single element from one lane" variant of vst1. > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118084&r1=118083&r2=118084&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 16:54:45 2010 > @@ -1125,13 +1125,23 @@ > > // VST1LN : Vector Store (single element from one lane) > class VST1LN op11_8, bits<4> op7_4, string Dt> > - : NLdSt<1, 0b00, op11_8, op7_4, (outs), > - (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), > - IIC_VST1ln, "vst1", Dt, "\\{$src[$lane]\\}, $addr", "", []>; > - > -def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8">; > -def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16">; > -def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32">; > + : NLdStLn<1, 0b00, op11_8, op7_4, (outs), > + (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), > + IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", []> { > + let Rm = 0b1111; > +} > + > +def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8"> { > + let Inst{7-5} = lane{2-0}; > +} > +def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16"> { > + let Inst{7-6} = lane{1-0}; > + let Inst{4} = Rn{5}; > +} > +def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32"> { > + let Inst{7} = lane{0}; > + let Inst{5-4} = Rn{5-4}; > +} > > def VST1LNq8Pseudo : VSTQLNPseudo; > def VST1LNq16Pseudo : VSTQLNPseudo; > @@ -1141,15 +1151,23 @@ > > // ...with address register writeback: > class VST1LNWB op11_8, bits<4> op7_4, string Dt> > - : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb), > - (ins addrmode6:$addr, am6offset:$offset, > - DPR:$src, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, > - "\\{$src[$lane]\\}, $addr$offset", > - "$addr.addr = $wb", []>; > - > -def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8">; > -def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16">; > -def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32">; > + : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), > + (ins addrmode6:$Rn, am6offset:$Rm, > + DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, > + "\\{$Vd[$lane]\\}, $Rn$Rm", > + "$Rn.addr = $wb", []>; > + > +def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> { > + let Inst{7-5} = lane{2-0}; > +} > +def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> { > + let Inst{7-6} = lane{1-0}; > + let Inst{4} = Rn{5}; > +} > +def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> { > + let Inst{7} = lane{0}; > + let Inst{5-4} = Rn{5-4}; > +} > > def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo; > def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Nov 2 17:09:25 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 2 Nov 2010 15:09:25 -0700 Subject: [llvm-commits] [llvm] r117997 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neon-vld-encoding.s In-Reply-To: <20101102012456.0AA7C2A6C12C@llvm.org> References: <20101102012456.0AA7C2A6C12C@llvm.org> Message-ID: Good fixes. A few, mostly stylistic, comments below. On Nov 1, 2010, at 6:24 PM, Owen Anderson wrote: > Author: resistor > Date: Mon Nov 1 20:24:55 2010 > New Revision: 117997 > > URL: http://llvm.org/viewvc/llvm-project?rev=117997&view=rev > Log: > Add correct NEON encodings for vld2, vld3, and vld4 basic variants. > > Modified: > llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > llvm/trunk/test/MC/ARM/neon-vld-encoding.s > > Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117997&r1=117996&r2=117997&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Nov 1 20:24:55 2010 > @@ -102,6 +102,7 @@ > > unsigned getMachineSoImmOpValue(unsigned SoImm); > unsigned getAddrMode6RegisterOperand(const MachineInstr &MI); > + unsigned getAddrMode6OffsetOperand(const MachineInstr &MI); > > unsigned getAddrModeSBit(const MachineInstr &MI, > const TargetInstrDesc &TID) const; > @@ -175,6 +176,8 @@ > const { return 0; } > unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op) > const { return 0; } > + unsigned getAddrMode6OffsetOperand(const MachineInstr &MI, unsigned Op) > + const { return 0; } > unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, > unsigned Op) const { return 0; } > unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117997&r1=117996&r2=117997&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 1 20:24:55 2010 > @@ -478,6 +478,7 @@ > def am6offset : Operand { > let PrintMethod = "printAddrMode6OffsetOperand"; > let MIOperandInfo = (ops GPR); > + string EncoderMethod = "getAddrMode6OffsetOperand"; The encoder method naming convention is get{blah}OpValue(). The addrmode6 encoder method has the same issue, which I didn't catch before. > } > > // addrmodepc := pc + reg > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117997&r1=117996&r2=117997&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 1 20:24:55 2010 > @@ -284,22 +284,28 @@ > > // VLD2 : Vector Load (multiple 2-element structures) > class VLD2D op11_8, bits<4> op7_4, string Dt> > - : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2), > - (ins addrmode6:$addr), IIC_VLD2, > - "vld2", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>; > + : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), > + (ins addrmode6:$Rn), IIC_VLD2, > + "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { > + let Rm = 0b1111; > + let Inst{5-4} = Rn{5-4}; > +} Since these addrmode6 operands describe more than just the Rn register, it'd be better to name them something else. Keeping them as 'addr' like before is fine. I've been renaming the operands when they match exactly an operand as indicated in the ARM documentation, otherwise using a more generic name. Ditto below for other renames for addrmode6 and am6offset operands. > class VLD2Q op7_4, string Dt> > : NLdSt<0, 0b10, 0b0011, op7_4, > - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > - (ins addrmode6:$addr), IIC_VLD2x2, > - "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; > + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), > + (ins addrmode6:$Rn), IIC_VLD2x2, > + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { > + let Rm = 0b1111; > + let Inst{5-4} = Rn{5-4}; > +} > > -def VLD2d8 : VLD2D<0b1000, 0b0000, "8">; > -def VLD2d16 : VLD2D<0b1000, 0b0100, "16">; > -def VLD2d32 : VLD2D<0b1000, 0b1000, "32">; > - > -def VLD2q8 : VLD2Q<0b0000, "8">; > -def VLD2q16 : VLD2Q<0b0100, "16">; > -def VLD2q32 : VLD2Q<0b1000, "32">; > +def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">; > +def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">; > +def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">; > + > +def VLD2q8 : VLD2Q<{0,0,?,?}, "8">; > +def VLD2q16 : VLD2Q<{0,1,?,?}, "16">; > +def VLD2q32 : VLD2Q<{1,0,?,?}, "32">; > > def VLD2d8Pseudo : VLDQPseudo; > def VLD2d16Pseudo : VLDQPseudo; > @@ -311,24 +317,28 @@ > > // ...with address register writeback: > class VLD2DWB op11_8, bits<4> op7_4, string Dt> > - : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), > - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2u, > - "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset", > - "$addr.addr = $wb", []>; > + : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), > + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u, > + "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", > + "$Rn.addr = $wb", []> { > + let Inst{5-4} = Rn{5-4}; > +} > class VLD2QWB op7_4, string Dt> > : NLdSt<0, 0b10, 0b0011, op7_4, > - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), > - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2x2u, > - "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", > - "$addr.addr = $wb", []>; > + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), > + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u, > + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", > + "$Rn.addr = $wb", []> { > + let Inst{5-4} = Rn{5-4}; > +} > > -def VLD2d8_UPD : VLD2DWB<0b1000, 0b0000, "8">; > -def VLD2d16_UPD : VLD2DWB<0b1000, 0b0100, "16">; > -def VLD2d32_UPD : VLD2DWB<0b1000, 0b1000, "32">; > - > -def VLD2q8_UPD : VLD2QWB<0b0000, "8">; > -def VLD2q16_UPD : VLD2QWB<0b0100, "16">; > -def VLD2q32_UPD : VLD2QWB<0b1000, "32">; > +def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">; > +def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">; > +def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">; > + > +def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">; > +def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">; > +def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">; > > def VLD2d8Pseudo_UPD : VLDQWBPseudo; > def VLD2d16Pseudo_UPD : VLDQWBPseudo; > @@ -339,22 +349,25 @@ > def VLD2q32Pseudo_UPD : VLDQQWBPseudo; > > // ...with double-spaced registers (for disassembly only): > -def VLD2b8 : VLD2D<0b1001, 0b0000, "8">; > -def VLD2b16 : VLD2D<0b1001, 0b0100, "16">; > -def VLD2b32 : VLD2D<0b1001, 0b1000, "32">; > -def VLD2b8_UPD : VLD2DWB<0b1001, 0b0000, "8">; > -def VLD2b16_UPD : VLD2DWB<0b1001, 0b0100, "16">; > -def VLD2b32_UPD : VLD2DWB<0b1001, 0b1000, "32">; > +def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">; > +def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">; > +def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">; > +def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">; > +def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">; > +def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">; > > // VLD3 : Vector Load (multiple 3-element structures) > class VLD3D op11_8, bits<4> op7_4, string Dt> > - : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), > - (ins addrmode6:$addr), IIC_VLD3, > - "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>; > - > -def VLD3d8 : VLD3D<0b0100, 0b0000, "8">; > -def VLD3d16 : VLD3D<0b0100, 0b0100, "16">; > -def VLD3d32 : VLD3D<0b0100, 0b1000, "32">; > + : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), > + (ins addrmode6:$Rn), IIC_VLD3, > + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { > + let Rm = 0b1111; > + let Inst{4} = Rn{4}; > +} > + > +def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; > +def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">; > +def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">; > > def VLD3d8Pseudo : VLDQQPseudo; > def VLD3d16Pseudo : VLDQQPseudo; > @@ -363,26 +376,28 @@ > // ...with address register writeback: > class VLD3DWB op11_8, bits<4> op7_4, string Dt> > : NLdSt<0, 0b10, op11_8, op7_4, > - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), > - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3u, > - "vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset", > - "$addr.addr = $wb", []>; > + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), > + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, > + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", > + "$Rn.addr = $wb", []> { > + let Inst{4} = Rn{4}; > +} > > -def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">; > -def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">; > -def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">; > +def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; > +def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">; > +def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">; > > def VLD3d8Pseudo_UPD : VLDQQWBPseudo; > def VLD3d16Pseudo_UPD : VLDQQWBPseudo; > def VLD3d32Pseudo_UPD : VLDQQWBPseudo; > > // ...with double-spaced registers (non-updating versions for disassembly only): > -def VLD3q8 : VLD3D<0b0101, 0b0000, "8">; > -def VLD3q16 : VLD3D<0b0101, 0b0100, "16">; > -def VLD3q32 : VLD3D<0b0101, 0b1000, "32">; > -def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">; > -def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">; > -def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">; > +def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">; > +def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">; > +def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">; > +def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">; > +def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">; > +def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">; > > def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo; > def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo; > @@ -396,13 +411,16 @@ > // VLD4 : Vector Load (multiple 4-element structures) > class VLD4D op11_8, bits<4> op7_4, string Dt> > : NLdSt<0, 0b10, op11_8, op7_4, > - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), > - (ins addrmode6:$addr), IIC_VLD4, > - "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; > + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), > + (ins addrmode6:$Rn), IIC_VLD4, > + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { > + let Rm = 0b1111; > + let Inst{5-4} = Rn{5-4}; > +} > > -def VLD4d8 : VLD4D<0b0000, 0b0000, "8">; > -def VLD4d16 : VLD4D<0b0000, 0b0100, "16">; > -def VLD4d32 : VLD4D<0b0000, 0b1000, "32">; > +def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; > +def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">; > +def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">; > > def VLD4d8Pseudo : VLDQQPseudo; > def VLD4d16Pseudo : VLDQQPseudo; > @@ -411,26 +429,28 @@ > // ...with address register writeback: > class VLD4DWB op11_8, bits<4> op7_4, string Dt> > : NLdSt<0, 0b10, op11_8, op7_4, > - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), > - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, > - "vld4", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", > - "$addr.addr = $wb", []>; > + (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), > + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, > + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", > + "$Rn.addr = $wb", []> { > + let Inst{5-4} = Rn{5-4}; > +} > > -def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">; > -def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">; > -def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">; > +def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; > +def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">; > +def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">; > > def VLD4d8Pseudo_UPD : VLDQQWBPseudo; > def VLD4d16Pseudo_UPD : VLDQQWBPseudo; > def VLD4d32Pseudo_UPD : VLDQQWBPseudo; > > // ...with double-spaced registers (non-updating versions for disassembly only): > -def VLD4q8 : VLD4D<0b0001, 0b0000, "8">; > -def VLD4q16 : VLD4D<0b0001, 0b0100, "16">; > -def VLD4q32 : VLD4D<0b0001, 0b1000, "32">; > -def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">; > -def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">; > -def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">; > +def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">; > +def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">; > +def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">; > +def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">; > +def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">; > +def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">; > > def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo; > def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo; > > Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117997&r1=117996&r2=117997&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 1 20:24:55 2010 > @@ -100,6 +100,7 @@ > > unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const; > unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const; > + unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const; > > unsigned getNumFixupKinds() const { > assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); > @@ -312,6 +313,14 @@ > return RegNo | (Align << 4); > } > > +unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI, > + unsigned Op) const { > + const MCOperand ®no = MI.getOperand(Op); > + if (regno.getReg() == 0) return 0x0D; > + return regno.getReg(); > +} > + > + Extra vertical whitespace here. > void ARMMCCodeEmitter:: > EncodeInstruction(const MCInst &MI, raw_ostream &OS, > SmallVectorImpl &Fixups) const { > > Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=117997&r1=117996&r2=117997&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original) > +++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Nov 1 20:24:55 2010 > @@ -17,3 +17,57 @@ > vld1.32 {d16, d17}, [r0] > @ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] > vld1.64 {d16, d17}, [r0] > + > +@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] > + vld2.8 {d16, d17}, [r0, :64] > +@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] > + vld2.16 {d16, d17}, [r0, :128] > +@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] > + vld2.32 {d16, d17}, [r0] > +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4] > + vld2.8 {d16, d17, d18, d19}, [r0, :64] > +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] > + vld2.16 {d16, d17, d18, d19}, [r0, :128] > +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] > + vld2.32 {d16, d17, d18, d19}, [r0, :256] > + > +@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4] > + vld3.8 {d16, d17, d18}, [r0, :64] > +@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4] > + vld3.16 {d16, d17, d18}, [r0] > +@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4] > + vld3.32 {d16, d17, d18}, [r0] > +@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4] > + vld3.8 {d16, d18, d20}, [r0, :64]! > +@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4] > + vld3.8 {d17, d19, d21}, [r0, :64]! > +@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4] > + vld3.16 {d16, d18, d20}, [r0]! > +@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4] > + vld3.16 {d17, d19, d21}, [r0]! > +@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4] > + vld3.32 {d16, d18, d20}, [r0]! > +@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4] > + vld3.32 {d17, d19, d21}, [r0]! > + > +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf4] > + vld4.8 {d16, d17, d18, d19}, [r0, :64] > +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf4] > + vld4.16 {d16, d17, d18, d19}, [r0, :128] > +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf4] > + vld4.32 {d16, d17, d18, d19}, [r0, :256] > +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf4] > + vld4.8 {d16, d18, d20, d22}, [r0, :256]! > +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf4] > + vld4.8 {d17, d19, d21, d23}, [r0, :256]! > +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4] > + vld4.16 {d16, d18, d20, d22}, [r0]! > +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4] > + vld4.16 {d17, d19, d21, d23}, [r0]! > +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4] > + vld4.32 {d16, d18, d20, d22}, [r0]! > +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] > + vld4.32 {d17, d19, d21, d23}, [r0]! > + > + > + > \ No newline at end of file > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Tue Nov 2 17:07:47 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 22:07:47 -0000 Subject: [llvm-commits] [llvm] r118086 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102220747.8307D2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 17:07:47 2010 New Revision: 118086 URL: http://llvm.org/viewvc/llvm-project?rev=118086&view=rev Log: Eliminate some temporary std::strings. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118086&r1=118085&r2=118086&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 17:07:47 2010 @@ -352,18 +352,18 @@ if (_NSGetExecutablePath(exe_path, &size) == 0) { char link_path[MAXPATHLEN]; if (realpath(exe_path, link_path)) - return Path(std::string(link_path)); + return Path(link_path); } #elif defined(__FreeBSD__) || defined (__NetBSD__) || defined(__minix) char exe_path[PATH_MAX]; if (getprogpath(exe_path, argv0) != NULL) - return Path(std::string(exe_path)); + return Path(exe_path); #elif defined(__linux__) || defined(__CYGWIN__) char exe_path[MAXPATHLEN]; ssize_t len = readlink("/proc/self/exe", exe_path, sizeof(exe_path)); if (len >= 0) - return Path(std::string(exe_path, len)); + return Path(StringRef(exe_path, len)); #elif defined(HAVE_DLFCN_H) // Use dladdr to get executable path if available. Dl_info DLInfo; @@ -375,7 +375,7 @@ // the actual executable. char link_path[MAXPATHLEN]; if (realpath(DLInfo.dli_fname, link_path)) - return Path(std::string(link_path)); + return Path(link_path); #else #error GetMainExecutable is not implemented on this host yet. #endif From resistor at mac.com Tue Nov 2 17:18:19 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 22:18:19 -0000 Subject: [llvm-commits] [llvm] r118087 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vst-encoding.s Message-ID: <20101102221819.2CBAF2A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 17:18:18 2010 New Revision: 118087 URL: http://llvm.org/viewvc/llvm-project?rev=118087&view=rev Log: Provide correct encodings for the remaining vst variants that we currently generate. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neon-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118087&r1=118086&r2=118087&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 17:18:18 2010 @@ -1175,135 +1175,213 @@ // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VST2ln, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr", - "", []>; - -def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8">; -def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16">; -def VST2LNd32 : VST2LN<0b1001, {?,0,?,?}, "32">; + : NLdStLn<1, 0b00, op11_8, op7_4, (outs), + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane), + IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn", + "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} + +def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VST2LNd8Pseudo : VSTQLNPseudo; def VST2LNd16Pseudo : VSTQLNPseudo; def VST2LNd32Pseudo : VSTQLNPseudo; // ...with double-spaced registers: -def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16">; -def VST2LNq32 : VST2LN<0b1001, {?,1,?,?}, "32">; +def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; + let Inst{4} = Rn{4}; +} +def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{4} = Rn{4}; +} def VST2LNq16Pseudo : VSTQQLNPseudo; def VST2LNq32Pseudo : VSTQQLNPseudo; // ...with address register writeback: class VST2LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb), + : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []>; + "$addr.addr = $wb", []> { + let Inst{4} = Rn{4}; +} -def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8">; -def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16">; -def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,?,?}, "32">; +def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo; def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo; def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo; -def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16">; -def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,?,?}, "32">; +def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> { + let Inst{7} = lane{0}; +} def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo; def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo; // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + : NLdStLn<1, 0b00, op11_8, op7_4, (outs), + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3ln, "vst3", Dt, - "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []>; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> { + let Rm = 0b1111; +} -def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8">; -def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16">; -def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32">; +def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VST3LNd8Pseudo : VSTQQLNPseudo; def VST3LNd16Pseudo : VSTQQLNPseudo; def VST3LNd32Pseudo : VSTQQLNPseudo; // ...with double-spaced registers: -def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16">; -def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32">; +def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VST3LNq16Pseudo : VSTQQQQLNPseudo; def VST3LNq32Pseudo : VSTQQQQLNPseudo; // ...with address register writeback: class VST3LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), + : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3lnu, "vst3", Dt, - "\\{$src1[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []>; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", + "$Rn.addr = $wb", []>; -def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8">; -def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16">; -def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32">; +def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo; def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo; def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo; -def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16">; -def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32">; +def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> { + let Inst{7} = lane{0}; +} def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo; def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo; // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + : NLdStLn<1, 0b00, op11_8, op7_4, (outs), + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4ln, "vst4", Dt, - "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr", - "", []>; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", + "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; +} -def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8">; -def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16">; -def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32">; +def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VST4LNd8Pseudo : VSTQQLNPseudo; def VST4LNd16Pseudo : VSTQQLNPseudo; def VST4LNd32Pseudo : VSTQQLNPseudo; // ...with double-spaced registers: -def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16">; -def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32">; +def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VST4LNq16Pseudo : VSTQQQQLNPseudo; def VST4LNq32Pseudo : VSTQQQQLNPseudo; // ...with address register writeback: class VST4LNWB op11_8, bits<4> op7_4, string Dt> - : NLdSt<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), + : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), + (ins addrmode6:$Rn, am6offset:$Rm, + DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4lnu, "vst4", Dt, - "\\{$src1[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []>; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} -def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8">; -def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16">; -def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32">; +def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> { + let Inst{7-5} = lane{2-0}; +} +def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo; def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo; def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo; -def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16">; -def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32">; +def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> { + let Inst{7-6} = lane{1-0}; +} +def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> { + let Inst{7} = lane{0}; + let Inst{5} = Rn{5}; +} def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo; def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo; Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=118087&r1=118086&r2=118087&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Nov 2 17:18:18 2010 @@ -66,3 +66,36 @@ vst4.32 {d16, d18, d20, d22}, [r0]! @ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4] vst4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4] + vst2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4] + vst2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4] + vst2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4] + vst2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4] + vst2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf4] + vst3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xc0,0xf4] + vst3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xc0,0xf4] + vst3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] @ encoding: [0xaf,0x16,0xc0,0xf4] + vst3.16 {d17[2], d19[2], d21[2]}, [r0] +@ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf4] + vst3.32 {d16[0], d18[0], d20[0]}, [r0] + +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf4] + vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf4] + vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4] + vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4] + vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4] + vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] From foldr at codedgers.com Tue Nov 2 17:18:28 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 22:18:28 -0000 Subject: [llvm-commits] [llvm] r118088 - /llvm/trunk/lib/Support/SystemUtils.cpp Message-ID: <20101102221828.A874C2A6C12C@llvm.org> Author: foldr Date: Tue Nov 2 17:18:28 2010 New Revision: 118088 URL: http://llvm.org/viewvc/llvm-project?rev=118088&view=rev Log: Revert r118057, this is better fixed in appendSuffix itself. Modified: llvm/trunk/lib/Support/SystemUtils.cpp Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=118088&r1=118087&r2=118088&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Tue Nov 2 17:18:28 2010 @@ -47,9 +47,7 @@ if (!Result.isEmpty()) { Result.appendComponent(ExeName); - StringRef EXESuffix = sys::Path::GetEXESuffix(); - if (!EXESuffix.empty()) - Result.appendSuffix(EXESuffix); + Result.appendSuffix(sys::Path::GetEXESuffix()); } return Result; From foldr at codedgers.com Tue Nov 2 17:18:37 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Tue, 02 Nov 2010 22:18:37 -0000 Subject: [llvm-commits] [llvm] r118089 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Path.cpp lib/System/Unix/Path.inc lib/System/Win32/Path.inc Message-ID: <20101102221837.AFD332A6C12C@llvm.org> Author: foldr Date: Tue Nov 2 17:18:37 2010 New Revision: 118089 URL: http://llvm.org/viewvc/llvm-project?rev=118089&view=rev Log: appendSuffix: don't append a dot when the suffix is empty. Additionally, move the implementation of appendSuffix to Path.cpp: it is platform-independent. Modified: llvm/trunk/include/llvm/System/Path.h llvm/trunk/lib/System/Path.cpp llvm/trunk/lib/System/Unix/Path.inc llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=118089&r1=118088&r2=118089&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Tue Nov 2 17:18:37 2010 @@ -454,7 +454,8 @@ /// The precondition for this function is that the Path reference a file /// name (i.e. isFile() returns true). If the Path is not a file, no /// action is taken and the function returns false. If the path would - /// become invalid for the host operating system, false is returned. + /// become invalid for the host operating system, false is returned. When + /// the \p suffix is empty, no action is performed. /// @returns false if the suffix could not be added, true if it was. /// @brief Adds a period and the \p suffix to the end of the pathname. bool appendSuffix(StringRef suffix); Modified: llvm/trunk/lib/System/Path.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Path.cpp?rev=118089&r1=118088&r2=118089&view=diff ============================================================================== --- llvm/trunk/lib/System/Path.cpp (original) +++ llvm/trunk/lib/System/Path.cpp Tue Nov 2 17:18:37 2010 @@ -196,6 +196,21 @@ } bool +Path::appendSuffix(StringRef suffix) { + if (!suffix.empty()) { + std::string save(path); + path.append("."); + path.append(suffix); + if (!isValid()) { + path = save; + return false; + } + } + + return true; +} + +bool Path::isBitcodeFile() const { std::string actualMagic; if (!getMagicNumber(actualMagic, 4)) Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118089&r1=118088&r2=118089&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 17:18:37 2010 @@ -638,18 +638,6 @@ } bool -Path::appendSuffix(StringRef suffix) { - std::string save(path); - path.append("."); - path.append(suffix); - if (!isValid()) { - path = save; - return false; - } - return true; -} - -bool Path::eraseSuffix() { std::string save = path; size_t dotpos = path.rfind('.',path.size()); Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118089&r1=118088&r2=118089&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 2 17:18:37 2010 @@ -552,18 +552,6 @@ } bool -Path::appendSuffix(StringRef suffix) { - std::string save(path); - path.append("."); - path.append(suffix); - if (!isValid()) { - path = save; - return false; - } - return true; -} - -bool Path::eraseSuffix() { size_t dotpos = path.rfind('.',path.size()); size_t slashpos = path.rfind('/',path.size()); From tonic at nondot.org Tue Nov 2 17:23:31 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 22:23:31 -0000 Subject: [llvm-commits] [www] r118090 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102222331.2E1372A6C12C@llvm.org> Author: tbrethou Date: Tue Nov 2 17:23:30 2010 New Revision: 118090 URL: http://llvm.org/viewvc/llvm-project?rev=118090&view=rev Log: Add Qualcomm sponsor. Fix room typo. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118090&r1=118089&r2=118090&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Tue Nov 2 17:23:30 2010 @@ -18,7 +18,7 @@
-

SPONSORED BY: Apple, QuIC, Google

+

SPONSORED BY: Apple, QuIC, Google, LLVM, Clang, LLDB and @@ -70,7 +70,7 @@ C-to-Verilog.com : High-level synthesis using LLVM
Nadav Rotem, Haifa UniversityWinchester Room 3:20 - 3:50BreakMarket Room 3:50 - 4:30Object Files in LLVM
Michael Spencer, Gainsville UniversityAlmaden Ballroom -Connecting the EDG front-end to LLVM
Renato Golin, ARMAlmaden Ballroom +Connecting the EDG front-end to LLVM
Renato Golin, ARMWinchester Ballroom Building Linux BOF
Taylor Simpson, QuICMarket Room 4:30 - 5:10LLVM for Open Shading Language
Larry Gritz, Sony Pictures ImageworksAlmaden Ballroom Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
James Kempf, Ericsson Research Silicon ValleyWinchester Room From tonic at nondot.org Tue Nov 2 17:24:07 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 02 Nov 2010 22:24:07 -0000 Subject: [llvm-commits] [www] r118091 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101102222407.592DD2A6C12C@llvm.org> Author: tbrethou Date: Tue Nov 2 17:24:07 2010 New Revision: 118091 URL: http://llvm.org/viewvc/llvm-project?rev=118091&view=rev Log: Close quote. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118091&r1=118090&r2=118091&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Tue Nov 2 17:24:07 2010 @@ -18,7 +18,7 @@ -

SPONSORED BY: Apple, QuIC, Google,

SPONSORED BY: Apple, QuIC, Google, Qualcomm

The meeting serves as a forum for LLVM, Clang, LLDB and From sabre at nondot.org Tue Nov 2 17:26:33 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 22:26:33 -0000 Subject: [llvm-commits] [llvm] r118092 - in /llvm/trunk/lib/Target/MBlaze: MBlazeInstrFPU.td MBlazeInstrInfo.td Message-ID: <20101102222633.7FFF22A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 17:26:33 2010 New Revision: 118092 URL: http://llvm.org/viewvc/llvm-project?rev=118092&view=rev Log: mark a few codegenonly instructions. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td?rev=118092&r1=118091&r2=118092&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td Tue Nov 2 17:26:33 2010 @@ -124,7 +124,7 @@ } -let usesCustomInserter = 1 in { +let usesCustomInserter = 1, isCodeGenOnly = 1 in { def Select_FCC : MBlazePseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), "; SELECT_FCC PSEUDO!", Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118092&r1=118091&r2=118092&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Tue Nov 2 17:26:33 2010 @@ -125,7 +125,7 @@ //===----------------------------------------------------------------------===// // As stack alignment is always done with addiu, we need a 16-bit immediate -let Defs = [R1], Uses = [R1] in { +let Defs = [R1], Uses = [R1], isCodeGenOnly = 1 in { def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt), "#ADJCALLSTACKDOWN $amt", [(callseq_start timm:$amt)]>; @@ -526,7 +526,7 @@ def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>; } -let usesCustomInserter = 1 in { +let usesCustomInserter = 1, isCodeGenOnly = 1 in { def Select_CC : MBlazePseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), "; SELECT_CC PSEUDO!", From resistor at mac.com Tue Nov 2 17:28:01 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 22:28:01 -0000 Subject: [llvm-commits] [llvm] r118093 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101102222801.6201E2A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 17:28:01 2010 New Revision: 118093 URL: http://llvm.org/viewvc/llvm-project?rev=118093&view=rev Log: Rename encoder methods to match naming convention. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118093&r1=118092&r2=118093&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 17:28:01 2010 @@ -101,9 +101,6 @@ unsigned OpIdx); unsigned getMachineSoImmOpValue(unsigned SoImm); - unsigned getAddrMode6RegisterOperand(const MachineInstr &MI); - unsigned getAddrMode6OffsetOperand(const MachineInstr &MI); - unsigned getAddrModeSBit(const MachineInstr &MI, const TargetInstrDesc &TID) const; @@ -174,9 +171,9 @@ const { return 0; } unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op) + unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getAddrMode6OffsetOperand(const MachineInstr &MI, unsigned Op) + unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118093&r1=118092&r2=118093&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 17:28:01 2010 @@ -472,13 +472,13 @@ ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); - string EncoderMethod = "getAddrMode6RegisterOperand"; + string EncoderMethod = "getAddrMode6AddressOpValue"; } def am6offset : Operand { let PrintMethod = "printAddrMode6OffsetOperand"; let MIOperandInfo = (ops GPR); - string EncoderMethod = "getAddrMode6OffsetOperand"; + string EncoderMethod = "getAddrMode6OffsetOpValue"; } // addrmodepc := pc + reg Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118093&r1=118092&r2=118093&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:28:01 2010 @@ -99,8 +99,8 @@ unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const; unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const; - unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const; - unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const; + unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const; + unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const; unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); @@ -297,7 +297,7 @@ return Binary; } -unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI, +unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const { const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Imm = MI.getOperand(Op+1); @@ -313,7 +313,7 @@ return RegNo | (Align << 4); } -unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI, +unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const { const MCOperand ®no = MI.getOperand(Op); if (regno.getReg() == 0) return 0x0D; From isanbard at gmail.com Tue Nov 2 17:31:46 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 02 Nov 2010 22:31:46 -0000 Subject: [llvm-commits] [llvm] r118094 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/simple-fp-encoding.s Message-ID: <20101102223146.47EA52A6C12C@llvm.org> Author: void Date: Tue Nov 2 17:31:46 2010 New Revision: 118094 URL: http://llvm.org/viewvc/llvm-project?rev=118094&view=rev Log: Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 17:31:46 2010 @@ -177,26 +177,27 @@ const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) - const { - // {17-13} = reg - // {12} = (U)nsigned (add == '1', sub == '0') - // {11-0} = imm12 - const MachineOperand &MO = MI.getOperand(Op); - const MachineOperand &MO1 = MI.getOperand(Op + 1); - if (!MO.isReg()) { - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); - return 0; - } - unsigned Reg = getARMRegisterNumbering(MO.getReg()); - int32_t Imm12 = MO1.getImm(); - uint32_t Binary; - Binary = Imm12 & 0xfff; - if (Imm12 >= 0) - Binary |= (1 << 12); - Binary |= (Reg << 13); - return Binary; + uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const { + // {20-17} = reg + // {16} = (U)nsigned (add == '1', sub == '0') + // {15-0} = imm + const MachineOperand &MO = MI.getOperand(Op); + const MachineOperand &MO1 = MI.getOperand(Op + 1); + if (!MO.isReg()) { + emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); + return 0; } + + unsigned Reg = getARMRegisterNumbering(MO.getReg()); + int32_t Imm = MO1.getImm(); + uint32_t Binary; + Binary = Imm & 0xffff; + if (Imm >= 0) + Binary |= (1 << 16); + + Binary |= (Reg << 17); + return Binary; + } unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) const { return 0; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118094&r1=118093&r2=118094&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 17:31:46 2010 @@ -398,7 +398,7 @@ // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other // immediate values are as normal. - string EncoderMethod = "getAddrModeImm12OpValue"; + string EncoderMethod = "getAddrModeImmOpValue"; let PrintMethod = "printAddrModeImm12Operand"; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } @@ -464,6 +464,7 @@ let PrintMethod = "printAddrMode5Operand"; let MIOperandInfo = (ops GPR:$base, i32imm); let ParserMatchClass = ARMMemMode5AsmOperand; + string EncoderMethod = "getAddrModeImmOpValue"; } // addrmode6 := reg with optional writeback @@ -830,9 +831,9 @@ AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { bits<4> Rt; - bits<17> addr; - let Inst{23} = addr{12}; // U (add = ('U' == 1)) - let Inst{19-16} = addr{16-13}; // Rn + bits<32> addr; + let Inst{23} = addr{16}; // U (add = ('U' == 1)) + let Inst{19-16} = addr{20-17}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } @@ -840,9 +841,9 @@ AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { bits<4> Rt; - bits<17> shift; - let Inst{23} = shift{12}; // U (add = ('U' == 1)) - let Inst{19-16} = shift{16-13}; // Rn + bits<32> shift; + let Inst{23} = shift{16}; // U (add = ('U' == 1)) + let Inst{19-16} = shift{20-17}; // Rn let Inst{11-0} = shift{11-0}; } } Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118094&r1=118093&r2=118094&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 17:31:46 2010 @@ -53,18 +53,29 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in { def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", - [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { + // Instruction operands. + bits<5> Dd; + bits<32> addr; + + // Encode instruction operands. + let Inst{23} = addr{16}; // U (add = (U == '1')) + let Inst{22} = Dd{4}; + let Inst{19-16} = addr{20-17}; // Rn + let Inst{15-12} = Dd{3-0}; + let Inst{7-0} = addr{7-0}; // imm8 +} def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), IIC_fpLoad32, "vldr", ".32\t$dst, $addr", [(set SPR:$dst, (load addrmode5:$addr))]>; } // canFoldAsLoad -def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), +def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), IIC_fpStore64, "vstr", ".64\t$src, $addr", [(store (f64 DPR:$src), addrmode5:$addr)]>; -def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), +def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), IIC_fpStore32, "vstr", ".32\t$src, $addr", [(store SPR:$src, addrmode5:$addr)]>; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:31:46 2010 @@ -49,9 +49,8 @@ /// operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' - /// operand. - unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const; + /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. + uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const; /// getCCOutOpValue - Return encoding of the 's' bit. unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { @@ -170,37 +169,38 @@ return 0; } -/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' -/// operand. -unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, - unsigned OpIdx) const { - // {17-13} = reg - // {12} = (U)nsigned (add == '1', sub == '0') - // {11-0} = imm12 +/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. +uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI, + unsigned OpIdx) const { + // {20-17} = reg + // {16} = (U)nsigned (add == '1', sub == '0') + // {15-0} = imm const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); uint32_t Binary = 0; // If The first operand isn't a register, we have a label reference. if (!MO.isReg()) { - Binary |= ARM::PC << 13; // Rn is PC. + Binary |= ARM::PC << 17; // Rn is PC. // FIXME: Add a fixup referencing the label. return Binary; } unsigned Reg = getARMRegisterNumbering(MO.getReg()); - int32_t Imm12 = MO1.getImm(); - bool isAdd = Imm12 >= 0; + int32_t Imm = MO1.getImm(); + bool isAdd = Imm >= 0; + // Special value for #-0 - if (Imm12 == INT32_MIN) - Imm12 = 0; + if (Imm == INT32_MIN) + Imm = 0; + // Immediate is always encoded as positive. The 'U' bit controls add vs sub. - if (Imm12 < 0) - Imm12 = -Imm12; - Binary = Imm12 & 0xfff; + if (Imm < 0) Imm = -Imm; + + Binary = Imm & 0xffff; if (isAdd) - Binary |= (1 << 12); - Binary |= (Reg << 13); + Binary |= (1 << 16); + Binary |= (Reg << 17); return Binary; } @@ -320,7 +320,6 @@ return regno.getReg(); } - void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=118094&r1=118093&r2=118094&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Nov 2 17:31:46 2010 @@ -10,13 +10,8 @@ @ CHECK: bx lr @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1] -bx lr + bx lr @ CHECK: vqdmull.s32 q8, d17, d16 @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] -vqdmull.s32 q8, d17, d16 - -@ CHECK: vldr.64 d17, [r0] -@ CHECK: encoding: [0x00,0x0b,0x10,0xed] -vldr.64 d17, [r0] - + vqdmull.s32 q8, d17, d16 Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118094&r1=118093&r2=118094&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 2 17:31:46 2010 @@ -157,3 +157,20 @@ @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] vmov r0, r1, d16 + +@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] + vldr.64 d17, [r0] + +@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] + vldr.64 d1, [r2, #32] + + +@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] + vldr.64 d2, [r3] + +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] + vldr.64 d3, [pc] + vldr.64 d3, [pc,#0] + vldr.64 d3, [pc,#-0] From gohman at apple.com Tue Nov 2 17:41:19 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 22:41:19 -0000 Subject: [llvm-commits] [llvm] r118096 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102224119.BAA172A6C12C@llvm.org> Author: djg Date: Tue Nov 2 17:41:19 2010 New Revision: 118096 URL: http://llvm.org/viewvc/llvm-project?rev=118096&view=rev Log: Use '\0' instead of 0 for nul character constants. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118096&r1=118095&r2=118096&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 17:41:19 2010 @@ -693,7 +693,7 @@ if (pathname[lastchar] != '/') ++lastchar; - pathname[lastchar] = 0; + pathname[lastchar] = '\0'; if (createDirectoryHelper(pathname, pathname+lastchar, create_parents)) return MakeErrMsg(ErrMsg, @@ -766,9 +766,9 @@ path.copy(pathname, MAXPATHLEN); size_t lastchar = path.length() - 1; if (pathname[lastchar] == '/') - pathname[lastchar] = 0; + pathname[lastchar] = '\0'; else - pathname[lastchar+1] = 0; + pathname[lastchar+1] = '\0'; if (rmdir(pathname) != 0) return MakeErrMsg(ErrStr, From resistor at mac.com Tue Nov 2 17:41:42 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 22:41:42 -0000 Subject: [llvm-commits] [llvm] r118097 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td Message-ID: <20101102224142.619522A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 17:41:42 2010 New Revision: 118097 URL: http://llvm.org/viewvc/llvm-project?rev=118097&view=rev Log: Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118097&r1=118096&r2=118097&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 2 17:41:42 2010 @@ -1773,13 +1773,13 @@ let Inst{7-4} = op7_4; bits<5> Vd; - bits<6> Rn; - bits<4> Rm; + bits<6> addr; + bits<4> offset; let Inst{22} = Vd{4}; let Inst{15-12} = Vd{3-0}; - let Inst{19-16} = Rn{3-0}; - let Inst{3-0} = Rm{3-0}; + let Inst{19-16} = addr{3-0}; + let Inst{3-0} = offset{3-0}; } class NLdStLn op21_20, bits<4> op11_8, bits<4> op7_4, Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118097&r1=118096&r2=118097&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 17:41:42 2010 @@ -165,17 +165,17 @@ // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd), - (ins addrmode6:$Rn), IIC_VLD1, - "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + (ins addrmode6:$addr), IIC_VLD1, + "vld1", Dt, "\\{$Vd\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{4} = addr{4}; } class VLD1Q op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2), - (ins addrmode6:$Rn), IIC_VLD1x2, - "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr), IIC_VLD1x2, + "vld1", Dt, "\\{$Vd, $dst2\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } def VLD1d8 : VLD1D<{0,0,0,?}, "8">; @@ -196,17 +196,17 @@ // ...with address register writeback: class VLD1DWB op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u, - "vld1", Dt, "\\{$Vd\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD1u, + "vld1", Dt, "\\{$Vd\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } class VLD1QWB op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u, - "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD1x2u, + "vld1", Dt, "\\{$Vd, $dst2\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">; @@ -227,16 +227,16 @@ // ...with 3 registers (some of these are only for the disassembler): class VLD1D3 op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt, - "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + (ins addrmode6:$addr), IIC_VLD1x3, "vld1", Dt, + "\\{$Vd, $dst2, $dst3\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{4} = addr{4}; } class VLD1D3WB op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt, - "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD1x3u, "vld1", Dt, + "\\{$Vd, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } def VLD1d8T : VLD1D3<{0,0,0,?}, "8">; @@ -255,18 +255,18 @@ // ...with 4 registers (some of these are only for the disassembler): class VLD1D4 op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt, - "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr), IIC_VLD1x4, "vld1", Dt, + "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } class VLD1D4WB op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt, - "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb", + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD4, "vld1", Dt, + "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + let Inst{5-4} = addr{5-4}; } def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">; @@ -285,18 +285,18 @@ // VLD2 : Vector Load (multiple 2-element structures) class VLD2D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), - (ins addrmode6:$Rn), IIC_VLD2, - "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr), IIC_VLD2, + "vld2", Dt, "\\{$Vd, $dst2\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } class VLD2Q op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$Rn), IIC_VLD2x2, - "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr), IIC_VLD2x2, + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">; @@ -318,18 +318,18 @@ // ...with address register writeback: class VLD2DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u, - "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD2u, + "vld2", Dt, "\\{$Vd, $dst2\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } class VLD2QWB op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u, - "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD2x2u, + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">; @@ -359,10 +359,10 @@ // VLD3 : Vector Load (multiple 3-element structures) class VLD3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$Rn), IIC_VLD3, - "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + (ins addrmode6:$addr), IIC_VLD3, + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{4} = addr{4}; } def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; @@ -377,10 +377,10 @@ class VLD3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, - "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD3u, + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; @@ -412,10 +412,10 @@ class VLD4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$Rn), IIC_VLD4, - "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr), IIC_VLD4, + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; @@ -430,10 +430,10 @@ class VLD4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, - "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD4, + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; @@ -494,13 +494,13 @@ class VLD1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), - (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), - IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", + (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), + IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $addr", "$src = $Vd", [(set DPR:$Vd, (vector_insert (Ty DPR:$src), - (i32 (LoadOp addrmode6:$Rn)), + (i32 (LoadOp addrmode6:$addr)), imm:$lane))]> { - let Rm = 0b1111; + let offset = 0b1111; } class VLD1QLNPseudo : VLDQLNPseudo { let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), @@ -513,12 +513,12 @@ } def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> { let Inst{7-6} = lane{1-0}; - let Inst{4} = Rn{4}; + let Inst{4} = addr{4}; } def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> { let Inst{7} = lane{0}; - let Inst{5} = Rn{4}; - let Inst{4} = Rn{4}; + let Inst{5} = addr{4}; + let Inst{4} = addr{4}; } def VLD1LNq8Pseudo : VLD1QLNPseudo; @@ -530,22 +530,22 @@ // ...with address register writeback: class VLD1LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, - "\\{$Vd[$lane]\\}, $Rn$Rm", - "$src = $Vd, $Rn.addr = $wb", []>; + "\\{$Vd[$lane]\\}, $addr$offset", + "$src = $Vd, $addr.addr = $wb", []>; def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = Rn{4}; + let Inst{4} = addr{4}; } def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{4}; - let Inst{4} = Rn{4}; + let Inst{5} = addr{4}; + let Inst{4} = addr{4}; } def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo; @@ -555,11 +555,11 @@ // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), - (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $addr", "$src1 = $Vd, $src2 = $dst2", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + let offset = 0b1111; + let Inst{4} = addr{4}; } def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> { @@ -590,11 +590,11 @@ // ...with address register writeback: class VLD2LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, - "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", - "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + "\\{$Vd[$lane], $dst2[$lane]\\}, $addr$offset", + "$src1 = $Vd, $src2 = $dst2, $addr.addr = $wb", []> { + let Inst{4} = addr{4}; } def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> { @@ -624,11 +624,11 @@ // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, - "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> { - let Rm = 0b1111; + let offset = 0b1111; } def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { @@ -660,11 +660,11 @@ class VLD3LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3lnu, "vld3", Dt, - "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", - "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset", + "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb", []>; def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { @@ -695,12 +695,12 @@ class VLD4LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, - "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + let offset = 0b1111; + let Inst{4} = addr{4}; } def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> { @@ -711,7 +711,7 @@ } def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VLD4LNd8Pseudo : VLDQQLNPseudo; @@ -724,7 +724,7 @@ } def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VLD4LNq16Pseudo : VLDQQQQLNPseudo; @@ -734,13 +734,13 @@ class VLD4LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, -"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", -"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", +"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset", +"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb", []> { - let Inst{4} = Rn{4}; + let Inst{4} = addr{4}; } def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> { @@ -751,7 +751,7 @@ } def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo; @@ -763,7 +763,7 @@ } def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo; @@ -799,17 +799,17 @@ // VST1 : Vector Store (multiple single elements) class VST1D op7_4, string Dt> - : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd), - IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$Vd), + IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{4} = addr{4}; } class VST1Q op7_4, string Dt> : NLdSt<0,0b00,0b1010,op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2, - "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2), IIC_VST1x2, + "vst1", Dt, "\\{$Vd, $src2\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } def VST1d8 : VST1D<{0,0,0,?}, "8">; @@ -830,16 +830,16 @@ // ...with address register writeback: class VST1DWB op7_4, string Dt> : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u, - "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd), IIC_VST1u, + "vst1", Dt, "\\{$Vd\\}, $addr$offset", "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } class VST1QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2), - IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2), + IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">; @@ -860,18 +860,18 @@ // ...with 3 registers (some of these are only for the disassembler): class VST1D3 op7_4, string Dt> : NLdSt<0, 0b00, 0b0110, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), - IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3), + IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{4} = addr{4}; } class VST1D3WB op7_4, string Dt> : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3), - IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } def VST1d8T : VST1D3<{0,0,0,?}, "8">; @@ -890,19 +890,19 @@ // ...with 4 registers (some of these are only for the disassembler): class VST1D4 op7_4, string Dt> : NLdSt<0, 0b00, 0b0010, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "", + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } class VST1D4WB op7_4, string Dt> : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u, - "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VST1d8Q : VST1D4<{0,0,?,?}, "8">; @@ -921,18 +921,18 @@ // VST2 : Vector Store (multiple 2-element structures) class VST2D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), - IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2), + IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } class VST2Q op7_4, string Dt> : NLdSt<0, 0b00, 0b0011, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">; @@ -954,18 +954,18 @@ // ...with address register writeback: class VST2DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2), - IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2), + IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } class VST2QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u, - "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">; @@ -995,10 +995,10 @@ // VST3 : Vector Store (multiple 3-element structures) class VST3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, - "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, + "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $addr", "", []> { + let offset = 0b1111; + let Inst{4} = addr{4}; } def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">; @@ -1012,11 +1012,11 @@ // ...with address register writeback: class VST3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u, - "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">; @@ -1047,11 +1047,11 @@ // VST4 : Vector Store (multiple 4-element structures) class VST4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr", "", []> { - let Rm = 0b1111; - let Inst{5-4} = Rn{5-4}; + let offset = 0b1111; + let Inst{5-4} = addr{5-4}; } def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">; @@ -1065,11 +1065,11 @@ // ...with address register writeback: class VST4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, - "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{5-4} = Rn{5-4}; + "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{5-4} = addr{5-4}; } def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">; @@ -1126,9 +1126,9 @@ // VST1LN : Vector Store (single element from one lane) class VST1LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), - IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", []> { - let Rm = 0b1111; + (ins addrmode6:$addr, DPR:$Vd, nohash_imm:$lane), + IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $addr", "", []> { + let offset = 0b1111; } def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8"> { @@ -1136,11 +1136,11 @@ } def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = Rn{5}; + let Inst{4} = addr{5}; } def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5-4} = Rn{5-4}; + let Inst{5-4} = addr{5-4}; } def VST1LNq8Pseudo : VSTQLNPseudo; @@ -1152,21 +1152,21 @@ // ...with address register writeback: class VST1LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, - "\\{$Vd[$lane]\\}, $Rn$Rm", - "$Rn.addr = $wb", []>; + "\\{$Vd[$lane]\\}, $addr$offset", + "$addr.addr = $wb", []>; def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = Rn{5}; + let Inst{4} = addr{5}; } def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5-4} = Rn{5-4}; + let Inst{5-4} = addr{5-4}; } def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo; @@ -1176,11 +1176,11 @@ // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane), - IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn", + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, nohash_imm:$lane), + IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $addr", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + let offset = 0b1111; + let Inst{4} = addr{4}; } def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> { @@ -1200,11 +1200,11 @@ // ...with double-spaced registers: def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = Rn{4}; + let Inst{4} = addr{4}; } def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> { let Inst{7} = lane{0}; - let Inst{4} = Rn{4}; + let Inst{4} = addr{4}; } def VST2LNq16Pseudo : VSTQQLNPseudo; @@ -1217,7 +1217,7 @@ DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset", "$addr.addr = $wb", []> { - let Inst{4} = Rn{4}; + let Inst{4} = addr{4}; } def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> { @@ -1247,10 +1247,10 @@ // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3ln, "vst3", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> { - let Rm = 0b1111; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []> { + let offset = 0b1111; } def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> { @@ -1281,11 +1281,11 @@ // ...with address register writeback: class VST3LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3lnu, "vst3", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", - "$Rn.addr = $wb", []>; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset", + "$addr.addr = $wb", []>; def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; @@ -1314,12 +1314,12 @@ // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, + (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4ln, "vst4", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", + "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr", "", []> { - let Rm = 0b1111; - let Inst{4} = Rn{4}; + let offset = 0b1111; + let Inst{4} = addr{4}; } def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> { @@ -1330,7 +1330,7 @@ } def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VST4LNd8Pseudo : VSTQQLNPseudo; @@ -1343,7 +1343,7 @@ } def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VST4LNq16Pseudo : VSTQQQQLNPseudo; @@ -1352,12 +1352,12 @@ // ...with address register writeback: class VST4LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$Rn, am6offset:$Rm, + (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4lnu, "vst4", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", - "$Rn.addr = $wb", []> { - let Inst{4} = Rn{4}; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset", + "$addr.addr = $wb", []> { + let Inst{4} = addr{4}; } def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> { @@ -1368,7 +1368,7 @@ } def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo; @@ -1380,7 +1380,7 @@ } def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = Rn{5}; + let Inst{5} = addr{5}; } def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo; From isanbard at gmail.com Tue Nov 2 17:44:12 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 02 Nov 2010 22:44:12 -0000 Subject: [llvm-commits] [llvm] r118098 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101102224412.46C832A6C12C@llvm.org> Author: void Date: Tue Nov 2 17:44:12 2010 New Revision: 118098 URL: http://llvm.org/viewvc/llvm-project?rev=118098&view=rev Log: Simplify the EncodeInstruction method now that a lot of the special case stuff is handled with the MC encoder. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118098&r1=118097&r2=118098&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:44:12 2010 @@ -323,22 +323,15 @@ void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { - unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = TII.get(Opcode); - uint64_t TSFlags = Desc.TSFlags; - // Keep track of the current byte being emitted. - unsigned CurByte = 0; - // Pseudo instructions don't get encoded. - if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) + const TargetInstrDesc &Desc = TII.get(MI.getOpcode()); + if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo) return; - ++MCNumEmitted; // Keep track of the # of mi's emitted - unsigned Value = getBinaryCodeForInstr(MI); - switch (Opcode) { - default: break; - } - EmitConstant(Value, 4, CurByte, OS); + // Keep track of the current byte being emitted. + unsigned CurByte = 0; + EmitConstant(getBinaryCodeForInstr(MI), 4, CurByte, OS); + ++MCNumEmitted; // Keep track of the # of mi's emitted. } // FIXME: These #defines shouldn't be necessary. Instead, tblgen should From isanbard at gmail.com Tue Nov 2 17:46:04 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 02 Nov 2010 22:46:04 -0000 Subject: [llvm-commits] [llvm] r118099 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101102224604.CE65F2A6C12C@llvm.org> Author: void Date: Tue Nov 2 17:46:04 2010 New Revision: 118099 URL: http://llvm.org/viewvc/llvm-project?rev=118099&view=rev Log: Omit unused parameter name. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118099&r1=118098&r2=118099&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:46:04 2010 @@ -322,7 +322,7 @@ void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &) const { // Pseudo instructions don't get encoded. const TargetInstrDesc &Desc = TII.get(MI.getOpcode()); if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo) From wdietz2 at illinois.edu Tue Nov 2 17:46:43 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 02 Nov 2010 22:46:43 -0000 Subject: [llvm-commits] [poolalloc] r118100 - in /poolalloc/trunk/test/dsa/extern: extern_global2.ll extern_global_escape.ll Message-ID: <20101102224643.48D922A6C12C@llvm.org> Author: wdietz2 Date: Tue Nov 2 17:46:43 2010 New Revision: 118100 URL: http://llvm.org/viewvc/llvm-project?rev=118100&view=rev Log: Update external test cases. All of these (test/dsa/extern/*) should probably be reviewed at some point. Modified: poolalloc/trunk/test/dsa/extern/extern_global2.ll poolalloc/trunk/test/dsa/extern/extern_global_escape.ll Modified: poolalloc/trunk/test/dsa/extern/extern_global2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern_global2.ll?rev=118100&r1=118099&r2=118100&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/extern/extern_global2.ll (original) +++ poolalloc/trunk/test/dsa/extern/extern_global2.ll Tue Nov 2 17:46:43 2010 @@ -32,14 +32,12 @@ ret void } -; FIXME: These runlines are wrong, the 'a' points to sometihng reachable -; from what will be an external global, so it should be +E! -; RUNX: dsaopt %s -dsa-local -analyze -verify-flags "B:ptr-E" -; RUNX: dsaopt %s -dsa-local -analyze -verify-flags "B:a-E" -; RUNX: dsaopt %s -dsa-bu -analyze -verify-flags "B:ptr-E" -; RUNX: dsaopt %s -dsa-bu -analyze -verify-flags "B:a-E" -; RUNX: dsaopt %s -dsa-td -analyze -verify-flags "B:ptr-E" -; RUNX: dsaopt %s -dsa-td -analyze -verify-flags "B:a-E" +; RUN: dsaopt %s -dsa-local -analyze -verify-flags "B:ptr:0-E" +; RUN: dsaopt %s -dsa-local -analyze -verify-flags "B:a-E" +; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "B:ptr:0-E" +; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "B:a-E" +; RUN: dsaopt %s -dsa-td -analyze -verify-flags "B:ptr:0+E" +; RUN: dsaopt %s -dsa-td -analyze -verify-flags "B:a+E" define internal void @B() nounwind { entry: %a = alloca i32 ; [#uses=1] Modified: poolalloc/trunk/test/dsa/extern/extern_global_escape.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern_global_escape.ll?rev=118100&r1=118099&r2=118100&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/extern/extern_global_escape.ll (original) +++ poolalloc/trunk/test/dsa/extern/extern_global_escape.ll Tue Nov 2 17:46:43 2010 @@ -10,15 +10,15 @@ ; This global itself isn't externally accessible, only via 'externallyVisible' ; RUN: dsaopt %s -dsa-local -analyze -verify-flags "globalptr+G-E" -; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "globalptr+G-E" -; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "globalptr:0+E" -; RUN: dsaopt %s -dsa-td -analyze -verify-flags "globalptr+G-E" +; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "globalptr+G-IE" +; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "globalptr:0-E" +; RUN: dsaopt %s -dsa-td -analyze -verify-flags "globalptr+G-IE" ; RUN: dsaopt %s -dsa-td -analyze -verify-flags "globalptr:0+E" @globalptr = internal global i32* null ; [#uses=2] ; RUN: dsaopt %s -dsa-local -analyze -verify-flags "externallyVisible:ptr+I" ; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "externallyVisible:ptr+I-E" -; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "externallyVisible:ptr:0+IE" +; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "externallyVisible:ptr:0-E" ; RUN: dsaopt %s -dsa-td -analyze -verify-flags "externallyVisible:ptr+E-I" ; RUN: dsaopt %s -dsa-td -analyze -verify-flags "externallyVisible:ptr+E-I" define void @externallyVisible(i32** %ptr) nounwind { @@ -29,7 +29,7 @@ } ; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "usesGlobalPtr:ptr-IE" -; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "usesGlobalPtr:ptr:0+E-I" +; RUN: dsaopt %s -dsa-bu -analyze -verify-flags "usesGlobalPtr:ptr:0-EI" ; RUN: dsaopt %s -dsa-td -analyze -verify-flags "usesGlobalPtr:ptr-E" ; RUN: dsaopt %s -dsa-td -analyze -verify-flags "usesGlobalPtr:ptr:0+E" define void @usesGlobalPtr() nounwind { From wdietz2 at illinois.edu Tue Nov 2 17:48:26 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 02 Nov 2010 22:48:26 -0000 Subject: [llvm-commits] [poolalloc] r118101 - in /poolalloc/trunk: include/dsa/DSGraph.h lib/DSA/BottomUpClosure.cpp lib/DSA/DSGraph.cpp lib/DSA/Local.cpp lib/DSA/StdLibPass.cpp lib/DSA/TopDownClosure.cpp Message-ID: <20101102224826.9B25A2A6C12C@llvm.org> Author: wdietz2 Date: Tue Nov 2 17:48:26 2010 New Revision: 118101 URL: http://llvm.org/viewvc/llvm-project?rev=118101&view=rev Log: Remove 'hack' of marking globals reachable from formals, and instead clone the GG's back at the end of TD and recompute external with that. Modified: poolalloc/trunk/include/dsa/DSGraph.h poolalloc/trunk/lib/DSA/BottomUpClosure.cpp poolalloc/trunk/lib/DSA/DSGraph.cpp poolalloc/trunk/lib/DSA/Local.cpp poolalloc/trunk/lib/DSA/StdLibPass.cpp poolalloc/trunk/lib/DSA/TopDownClosure.cpp Modified: poolalloc/trunk/include/dsa/DSGraph.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=118101&r1=118100&r2=118101&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSGraph.h (original) +++ poolalloc/trunk/include/dsa/DSGraph.h Tue Nov 2 17:48:26 2010 @@ -507,12 +507,11 @@ }; void markIncompleteNodes(unsigned Flags); - // Mark all reachable from external as external. + // Mark all reachable from external as external. enum ComputeExternalFlags { MarkFormalsExternal = 1, DontMarkFormalsExternal = 0, ProcessCallSites = 2, IgnoreCallSites = 0, - ResetExternal = 4, DontResetExternal = 0, - MarkGlobalsReachableFromFormals = 8, IgnoreGlobalsReachableFromFormals = 0 + ResetExternal = 4, DontResetExternal = 0 }; void computeExternalFlags(unsigned Flags); Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=118101&r1=118100&r2=118101&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Tue Nov 2 17:48:26 2010 @@ -144,8 +144,8 @@ // Merge the globals variables (not the calls) from the globals graph back // into the individual function's graph so that changes made to globals during - // BU can be reflected. This is specifically needed for correct call graph - + // BU can be reflected. This is specifically needed for correct call graph + for (Module::iterator F = M.begin(); F != M.end(); ++F) { if (!(F->isDeclaration())){ DSGraph *Graph = getOrCreateGraph(F); Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=118101&r1=118100&r2=118101&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSGraph.cpp Tue Nov 2 17:48:26 2010 @@ -728,48 +728,6 @@ maskNodeTypes(~DSNode::ExternalNode); } - if (Flags & MarkGlobalsReachableFromFormals) { - DenseSet ReachableFromFormals; - for (ReturnNodesTy::iterator FI = ReturnNodes.begin(), E = ReturnNodes.end(); - FI != E; ++FI) { - const Function &F = *FI->first; - // Find all reachable from arguments... - for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); - I != E; ++I) - if (isa(I->getType())) { - DSNode * N = getNodeForValue(I).getNode(); - if (N) N->markReachableNodes(ReachableFromFormals); - } - // ...and the return value... - if (!FI->second.isNull()) - FI->second.getNode()->markReachableNodes(ReachableFromFormals); - if (!getVANodeFor(F).isNull()) - getVANodeFor(F).getNode()->markReachableNodes(ReachableFromFormals); - } - - DenseSet ReachableFromGlobals; - - for (DSScalarMap::global_iterator I = ScalarMap.global_begin(), - E = ScalarMap.global_end(); I != E; ++I) { - DSNode * N = getNodeForValue(*I).getNode(); - if (N) N->markReachableNodes(ReachableFromGlobals); - } - - // Find intersection of the two... - // FIXME: This works fine for local, but what about in other places where we might newly - // discover that something reachable from an externally visible function's argument is - // also reachable from a global and as such should be marked external in all graphs - // that use it? - for (DenseSet::iterator I = ReachableFromFormals.begin(), - E = ReachableFromFormals.end(); I != E; ++I) { - DSNode * N = (DSNode *)*I; - if (ReachableFromGlobals.count(N)) { - // Reachable from both a global and the formals, mark external! - markExternalNode(N, processedNodes); - } - } - } - // Make sure that everything reachable from something already external is also external propagateExternal(this, processedNodes); @@ -829,7 +787,7 @@ // Finally handle all external globals... for (DSScalarMap::global_iterator I = ScalarMap.global_begin(), - E = ScalarMap.global_end(); I != E; ++I) + E = ScalarMap.global_end(); I != E; ++I) { if (const GlobalVariable *GV = dyn_cast(*I)) { // If the global is external... mark it as such! // FIXME: It's unclear to me that a global we initialize @@ -839,9 +797,8 @@ if (!GV->hasInitializer() || N->isExternalNode()) markExternalNode(N, processedNodes); } + } - // FIXME: Sync with globals graph? - // For now, trust the caller to do this as appropriate. } static inline void killIfUselessEdge(DSNodeHandle &Edge) { Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=118101&r1=118100&r2=118101&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Tue Nov 2 17:48:26 2010 @@ -186,11 +186,6 @@ unsigned EFlags = 0 | DSGraph::DontMarkFormalsExternal | DSGraph::ProcessCallSites; - // Mark globals reachable from formals as external if we don't have - // internal linkage. - if (!f.hasInternalLinkage()) { - EFlags |= DSGraph::MarkGlobalsReachableFromFormals; - } g.computeExternalFlags(EFlags); Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=118101&r1=118100&r2=118101&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Nov 2 17:48:26 2010 @@ -407,9 +407,6 @@ | DSGraph::ResetExternal | DSGraph::DontMarkFormalsExternal | DSGraph::ProcessCallSites; - if (!I->hasInternalLinkage()) { - EFlags |= DSGraph::MarkGlobalsReachableFromFormals; - } G->computeExternalFlags(EFlags); } GlobalsGraph->computeExternalFlags(DSGraph::ProcessCallSites); Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=118101&r1=118100&r2=118101&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Tue Nov 2 17:48:26 2010 @@ -167,6 +167,28 @@ GlobalsGraph->removeTriviallyDeadNodes(); GlobalsGraph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + // Make sure each graph has updated external information about globals + // in the globals graph. + for (Module::iterator F = M.begin(); F != M.end(); ++F) { + if (!(F->isDeclaration())){ + DSGraph *Graph = getOrCreateGraph(F); + + ReachabilityCloner RC(Graph, GlobalsGraph, + DSGraph::DontCloneCallNodes | + DSGraph::DontCloneAuxCallNodes); + for (DSScalarMap::global_iterator + GI = Graph->getScalarMap().global_begin(), + E = Graph->getScalarMap().global_end(); GI != E; ++GI) + RC.getClonedNH(GlobalsGraph->getNodeForValue(*GI)); + + // Clean up uninteresting nodes + Graph->removeDeadNodes(0); + + Graph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + + } + } + // CBU contains the correct call graph. // Restore it, so that subsequent passes and clients can get it. restoreCorrectCallGraph(); From grosbach at apple.com Tue Nov 2 17:51:39 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 2 Nov 2010 15:51:39 -0700 Subject: [llvm-commits] [llvm] r118094 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/simple-fp-encoding.s In-Reply-To: <20101102223146.47EA52A6C12C@llvm.org> References: <20101102223146.47EA52A6C12C@llvm.org> Message-ID: <39F60132-FCF3-4D15-A988-09A6A5484874@apple.com> Hi Bill, We should add a new addrmode_i16 for this rather than re-using the current one. How many bits are legal is part of the semantics, and is enforced by the selection dag stuff (SelectAddrModeImm12() in this case). For a parallel example, see the Thumb2 t2addrmode_imm12 and t2addrmode_imm8 modes in ARMInstrThumb2.td. -Jim On Nov 2, 2010, at 3:31 PM, Bill Wendling wrote: > Author: void > Date: Tue Nov 2 17:31:46 2010 > New Revision: 118094 > > URL: http://llvm.org/viewvc/llvm-project?rev=118094&view=rev > Log: > Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work > with immediates up to 16-bits in size. The same logic is applied to other LDR > encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in > VLDR's case). Removing the "12" allows it to be more generic. > > Modified: > llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMInstrVFP.td > llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > llvm/trunk/test/MC/ARM/arm_instructions.s > llvm/trunk/test/MC/ARM/simple-fp-encoding.s > > Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 17:31:46 2010 > @@ -177,26 +177,27 @@ > const { return 0; } > unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, > unsigned Op) const { return 0; } > - unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) > - const { > - // {17-13} = reg > - // {12} = (U)nsigned (add == '1', sub == '0') > - // {11-0} = imm12 > - const MachineOperand &MO = MI.getOperand(Op); > - const MachineOperand &MO1 = MI.getOperand(Op + 1); > - if (!MO.isReg()) { > - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); > - return 0; > - } > - unsigned Reg = getARMRegisterNumbering(MO.getReg()); > - int32_t Imm12 = MO1.getImm(); > - uint32_t Binary; > - Binary = Imm12 & 0xfff; > - if (Imm12 >= 0) > - Binary |= (1 << 12); > - Binary |= (Reg << 13); > - return Binary; > + uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const { > + // {20-17} = reg > + // {16} = (U)nsigned (add == '1', sub == '0') > + // {15-0} = imm > + const MachineOperand &MO = MI.getOperand(Op); > + const MachineOperand &MO1 = MI.getOperand(Op + 1); > + if (!MO.isReg()) { > + emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); > + return 0; > } > + > + unsigned Reg = getARMRegisterNumbering(MO.getReg()); > + int32_t Imm = MO1.getImm(); > + uint32_t Binary; > + Binary = Imm & 0xffff; > + if (Imm >= 0) > + Binary |= (1 << 16); > + > + Binary |= (Reg << 17); > + return Binary; > + } > unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) > const { return 0; } > > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118094&r1=118093&r2=118094&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 17:31:46 2010 > @@ -398,7 +398,7 @@ > // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other > // immediate values are as normal. > > - string EncoderMethod = "getAddrModeImm12OpValue"; > + string EncoderMethod = "getAddrModeImmOpValue"; > let PrintMethod = "printAddrModeImm12Operand"; > let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); > } > @@ -464,6 +464,7 @@ > let PrintMethod = "printAddrMode5Operand"; > let MIOperandInfo = (ops GPR:$base, i32imm); > let ParserMatchClass = ARMMemMode5AsmOperand; > + string EncoderMethod = "getAddrModeImmOpValue"; > } > > // addrmode6 := reg with optional writeback > @@ -830,9 +831,9 @@ > AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", > [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { > bits<4> Rt; > - bits<17> addr; > - let Inst{23} = addr{12}; // U (add = ('U' == 1)) > - let Inst{19-16} = addr{16-13}; // Rn > + bits<32> addr; > + let Inst{23} = addr{16}; // U (add = ('U' == 1)) > + let Inst{19-16} = addr{20-17}; // Rn > let Inst{15-12} = Rt; > let Inst{11-0} = addr{11-0}; // imm12 > } > @@ -840,9 +841,9 @@ > AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", > [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { > bits<4> Rt; > - bits<17> shift; > - let Inst{23} = shift{12}; // U (add = ('U' == 1)) > - let Inst{19-16} = shift{16-13}; // Rn > + bits<32> shift; > + let Inst{23} = shift{16}; // U (add = ('U' == 1)) > + let Inst{19-16} = shift{20-17}; // Rn > let Inst{11-0} = shift{11-0}; > } > } > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118094&r1=118093&r2=118094&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 17:31:46 2010 > @@ -53,18 +53,29 @@ > let canFoldAsLoad = 1, isReMaterializable = 1 in { > def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), > IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", > - [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; > + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { > + // Instruction operands. > + bits<5> Dd; > + bits<32> addr; > + > + // Encode instruction operands. > + let Inst{23} = addr{16}; // U (add = (U == '1')) > + let Inst{22} = Dd{4}; > + let Inst{19-16} = addr{20-17}; // Rn > + let Inst{15-12} = Dd{3-0}; > + let Inst{7-0} = addr{7-0}; // imm8 > +} > > def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), > IIC_fpLoad32, "vldr", ".32\t$dst, $addr", > [(set SPR:$dst, (load addrmode5:$addr))]>; > } // canFoldAsLoad > > -def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), > +def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), > IIC_fpStore64, "vstr", ".64\t$src, $addr", > [(store (f64 DPR:$src), addrmode5:$addr)]>; > > -def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), > +def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), > IIC_fpStore32, "vstr", ".32\t$src, $addr", > [(store SPR:$src, addrmode5:$addr)]>; > > > Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:31:46 2010 > @@ -49,9 +49,8 @@ > /// operand requires relocation, record the relocation and return zero. > unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; > > - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' > - /// operand. > - unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const; > + /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. > + uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const; > > /// getCCOutOpValue - Return encoding of the 's' bit. > unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { > @@ -170,37 +169,38 @@ > return 0; > } > > -/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' > -/// operand. > -unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, > - unsigned OpIdx) const { > - // {17-13} = reg > - // {12} = (U)nsigned (add == '1', sub == '0') > - // {11-0} = imm12 > +/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. > +uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI, > + unsigned OpIdx) const { > + // {20-17} = reg > + // {16} = (U)nsigned (add == '1', sub == '0') > + // {15-0} = imm > const MCOperand &MO = MI.getOperand(OpIdx); > const MCOperand &MO1 = MI.getOperand(OpIdx + 1); > uint32_t Binary = 0; > > // If The first operand isn't a register, we have a label reference. > if (!MO.isReg()) { > - Binary |= ARM::PC << 13; // Rn is PC. > + Binary |= ARM::PC << 17; // Rn is PC. > // FIXME: Add a fixup referencing the label. > return Binary; > } > > unsigned Reg = getARMRegisterNumbering(MO.getReg()); > - int32_t Imm12 = MO1.getImm(); > - bool isAdd = Imm12 >= 0; > + int32_t Imm = MO1.getImm(); > + bool isAdd = Imm >= 0; > + > // Special value for #-0 > - if (Imm12 == INT32_MIN) > - Imm12 = 0; > + if (Imm == INT32_MIN) > + Imm = 0; > + > // Immediate is always encoded as positive. The 'U' bit controls add vs sub. > - if (Imm12 < 0) > - Imm12 = -Imm12; > - Binary = Imm12 & 0xfff; > + if (Imm < 0) Imm = -Imm; > + > + Binary = Imm & 0xffff; > if (isAdd) > - Binary |= (1 << 12); > - Binary |= (Reg << 13); > + Binary |= (1 << 16); > + Binary |= (Reg << 17); > return Binary; > } > > @@ -320,7 +320,6 @@ > return regno.getReg(); > } > > - > void ARMMCCodeEmitter:: > EncodeInstruction(const MCInst &MI, raw_ostream &OS, > SmallVectorImpl &Fixups) const { > > Modified: llvm/trunk/test/MC/ARM/arm_instructions.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=118094&r1=118093&r2=118094&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) > +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Nov 2 17:31:46 2010 > @@ -10,13 +10,8 @@ > > @ CHECK: bx lr > @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1] > -bx lr > + bx lr > > @ CHECK: vqdmull.s32 q8, d17, d16 > @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] > -vqdmull.s32 q8, d17, d16 > - > -@ CHECK: vldr.64 d17, [r0] > -@ CHECK: encoding: [0x00,0x0b,0x10,0xed] > -vldr.64 d17, [r0] > - > + vqdmull.s32 q8, d17, d16 > > Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118094&r1=118093&r2=118094&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) > +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 2 17:31:46 2010 > @@ -157,3 +157,20 @@ > > @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] > vmov r0, r1, d16 > + > +@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] > + vldr.64 d17, [r0] > + > +@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] > + vldr.64 d1, [r2, #32] > + > + > +@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] > + vldr.64 d2, [r3] > + > +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] > +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] > +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] > + vldr.64 d3, [pc] > + vldr.64 d3, [pc,#0] > + vldr.64 d3, [pc,#-0] > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Tue Nov 2 17:50:10 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 22:50:10 -0000 Subject: [llvm-commits] [llvm] r118102 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102225011.03CA42A6C12C@llvm.org> Author: djg Date: Tue Nov 2 17:50:10 2010 New Revision: 118102 URL: http://llvm.org/viewvc/llvm-project?rev=118102&view=rev Log: Simplify this code. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118102&r1=118101&r2=118102&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 17:50:10 2010 @@ -141,8 +141,7 @@ #if defined(HAVE_MKDTEMP) // The best way is with mkdtemp but that's not available on many systems, // Linux and FreeBSD have it. Others probably won't. - char pathname[MAXPATHLEN]; - strcpy(pathname,"/tmp/llvm_XXXXXX"); + char pathname[] = "/tmp/llvm_XXXXXX"; if (0 == mkdtemp(pathname)) { MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create temporary directory"); @@ -158,8 +157,7 @@ // mktemp because of mktemp's inherent security and threading risks. We still // have a slight race condition from the time the temporary file is created to // the time it is re-created as a directoy. - char pathname[MAXPATHLEN]; - strcpy(pathname, "/tmp/llvm_XXXXXX"); + char pathname[] = "/tmp/llvm_XXXXXX"; int fd = 0; if (-1 == (fd = mkstemp(pathname))) { MakeErrMsg(ErrMsg, @@ -183,8 +181,7 @@ // implementation of mktemp(3) and doesn't follow BSD 4.3's lead of replacing // the XXXXXX with the pid of the process and a letter. That leads to only // twenty six temporary files that can be generated. - char pathname[MAXPATHLEN]; - strcpy(pathname, "/tmp/llvm_XXXXXX"); + char pathname[] = "/tmp/llvm_XXXXXX"; char *TmpName = ::mktemp(pathname); if (TmpName == 0) { MakeErrMsg(ErrMsg, From isanbard at gmail.com Tue Nov 2 17:53:11 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 02 Nov 2010 22:53:11 -0000 Subject: [llvm-commits] [llvm] r118103 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101102225311.AC0342A6C12C@llvm.org> Author: void Date: Tue Nov 2 17:53:11 2010 New Revision: 118103 URL: http://llvm.org/viewvc/llvm-project?rev=118103&view=rev Log: Obsessive formatting changes. No functionality impact. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118103&r1=118102&r2=118103&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:53:11 2010 @@ -132,9 +132,8 @@ } // end anonymous namespace -MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, - TargetMachine &TM, - MCContext &Ctx) { +MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM, + MCContext &Ctx) { return new ARMMCCodeEmitter(TM, Ctx); } @@ -143,29 +142,30 @@ unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO) const { if (MO.isReg()) { - unsigned regno = getARMRegisterNumbering(MO.getReg()); + unsigned Reg = MO.getReg(); + unsigned RegNo = getARMRegisterNumbering(Reg); // Q registers are encodes as 2x their register number. - switch (MO.getReg()) { - case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: - case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: - case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: - case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: - return 2 * regno; - default: - return regno; + switch (Reg) { + default: + return RegNo; + case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: + case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: + case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: + case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: + return 2 * RegNo; } } else if (MO.isImm()) { return static_cast(MO.getImm()); } else if (MO.isFPImm()) { return static_cast(APFloat(MO.getFPImm()) .bitcastToAPInt().getHiBits(32).getLimitedValue()); - } else { + } + #ifndef NDEBUG - errs() << MO; + errs() << MO; #endif - llvm_unreachable(0); - } + llvm_unreachable(0); return 0; } @@ -206,15 +206,16 @@ unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI, unsigned OpIdx) const { - // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg - // to be shifted. The second is either Rs, the amount to shift by, or - // reg0 in which case the imm contains the amount to shift by. + // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be + // shifted. The second is either Rs, the amount to shift by, or reg0 in which + // case the imm contains the amount to shift by. + // // {3-0} = Rm. - // {4} = 1 if reg shift, 0 if imm shift + // {4} = 1 if reg shift, 0 if imm shift // {6-5} = type // If reg shift: - // {7} = 0 // {11-8} = Rs + // {7} = 0 // else (imm shift) // {11-7} = imm @@ -258,6 +259,7 @@ case ARM_AM::ror: SBits = 0x6; break; } } + Binary |= SBits << 4; if (SOpc == ARM_AM::rrx) return Binary; @@ -300,24 +302,28 @@ unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const { const MCOperand &Reg = MI.getOperand(Op); - const MCOperand &Imm = MI.getOperand(Op+1); + const MCOperand &Imm = MI.getOperand(Op + 1); unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); - unsigned Align = Imm.getImm(); - switch(Align) { - case 2: case 4: case 8: Align = 0x01; break; - case 16: Align = 0x02; break; - case 32: Align = 0x03; break; - default: Align = 0x00; break; + unsigned Align = 0; + + switch (Imm.getImm()) { + default: break; + case 2: + case 4: + case 8: Align = 0x01; break; + case 16: Align = 0x02; break; + case 32: Align = 0x03; break; } + return RegNo | (Align << 4); } unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const { - const MCOperand ®no = MI.getOperand(Op); - if (regno.getReg() == 0) return 0x0D; - return regno.getReg(); + const MCOperand &MO = MI.getOperand(Op); + if (MO.getReg() == 0) return 0x0D; + return MO.getReg(); } void ARMMCCodeEmitter:: From sabre at nondot.org Tue Nov 2 17:55:03 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 22:55:03 -0000 Subject: [llvm-commits] [llvm] r118104 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp CodeGenInstruction.h Message-ID: <20101102225503.E86B62A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 17:55:03 2010 New Revision: 118104 URL: http://llvm.org/viewvc/llvm-project?rev=118104&view=rev Log: rewrite EmitConvertToMCInst to iterate over the MCInst operands, filling them in one at a time. Previously this iterated over the asmoperands, which left the problem of "holes". The new approach simplifies things. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118104&r1=118103&r2=118104&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 17:55:03 2010 @@ -1040,13 +1040,12 @@ // grovel for. Only worry about this for single entry operands, we have to // clean this up anyway. const CGIOperandList::OperandInfo *OI = &II->OperandList[Idx]; - if (OI->Constraints[0].isTied()) { - unsigned TiedOp = OI->Constraints[0].getTiedOperand(); - + int OITied = OI->getTiedRegister(); + if (OITied != -1) { // The tied operand index is an MIOperand index, find the operand that // contains it. for (unsigned i = 0, e = II->OperandList.size(); i != e; ++i) { - if (II->OperandList[i].MIOperandNo == TiedOp) { + if (II->OperandList[i].MIOperandNo == unsigned(OITied)) { OI = &II->OperandList[i]; break; } @@ -1064,16 +1063,6 @@ std::sort(Classes.begin(), Classes.end(), less_ptr()); } -static std::pair * -GetTiedOperandAtIndex(SmallVectorImpl > &List, - unsigned Index) { - for (unsigned i = 0, e = List.size(); i != e; ++i) - if (Index == List[i].first) - return &List[i]; - - return 0; -} - static void EmitConvertToMCInst(CodeGenTarget &Target, std::vector &Infos, raw_ostream &OS) { @@ -1103,111 +1092,88 @@ // TargetOperandClass - This is the target's operand class, like X86Operand. std::string TargetOperandClass = Target.getName() + "Operand"; + /// OperandMap - This is a mapping from the MCInst operands (specified by the + /// II.OperandList operands) to the AsmOperands that they filled in from. + SmallVector OperandMap; + for (std::vector::const_iterator it = Infos.begin(), ie = Infos.end(); it != ie; ++it) { MatchableInfo &II = **it; + OperandMap.clear(); + OperandMap.resize(II.OperandList.size(), -1); + // Order the (class) operands by the order to convert them into an MCInst. - SmallVector, 4> MIOperandList; for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { MatchableInfo::Operand &Op = II.AsmOperands[i]; - if (Op.OperandInfo) - MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i)); - } - - // Find any tied operands. - SmallVector, 4> TiedOperands; - for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i]; - for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) { - const CGIOperandList::ConstraintInfo &CI = OpInfo.Constraints[j]; - if (!CI.isTied()) continue; - TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo, - CI.getTiedOperand())); - } - } - - array_pod_sort(MIOperandList.begin(), MIOperandList.end()); - - // Compute the total number of operands. - unsigned NumMIOperands = 0; - for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OI = II.OperandList[i]; - NumMIOperands = std::max(NumMIOperands, OI.MIOperandNo+OI.MINumOperands); + if (!Op.OperandInfo) continue; + + unsigned LogicalOpNum = Op.OperandInfo - &II.OperandList[0]; + assert(LogicalOpNum < OperandMap.size() && "Invalid operand number"); + OperandMap[LogicalOpNum] = i; } // Build the conversion function signature. std::string Signature = "Convert"; - unsigned CurIndex = 0; - std::string CaseBody; raw_string_ostream CaseOS(CaseBody); // Compute the convert enum and the case body. - for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.AsmOperands[MIOperandList[i].second]; - assert(CurIndex <= Op.OperandInfo->MIOperandNo && - "Duplicate match for instruction operand!"); - - // Add the implicit operands. - for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { - // See if this is a tied operand. - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); + for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i]; + + // Find out what operand from the asmparser that this MCInst operand comes + // from. + int SrcOperand = OperandMap[i]; + if (SrcOperand != -1) { + // Otherwise, this comes from something we parsed. + MatchableInfo::Operand &Op = II.AsmOperands[SrcOperand]; - if (!Tie) { - // If not, this is some implicit operand. Just assume it is a register - // for now. - CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - Signature += "__Imp"; - } else { - // Copy the tied operand. - assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); - CaseOS << " Inst.addOperand(Inst.getOperand(" - << Tie->second << "));\n"; - Signature += "__Tie" + utostr(Tie->second); - } + // Registers are always converted the same, don't duplicate the + // conversion function based on them. + // + // FIXME: We could generalize this based on the render method, if it + // mattered. + Signature += "__"; + if (Op.Class->isRegisterClass()) + Signature += "Reg"; + else + Signature += Op.Class->ClassName; + Signature += utostr(Op.OperandInfo->MINumOperands); + Signature += "_" + itostr(SrcOperand); + + CaseOS << " ((" << TargetOperandClass << "*)Operands[" + << SrcOperand << "+1])->" << Op.Class->RenderMethod + << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; + continue; } - // Registers are always converted the same, don't duplicate the conversion - // function based on them. - // - // FIXME: We could generalize this based on the render method, if it - // mattered. - Signature += "__"; - if (Op.Class->isRegisterClass()) - Signature += "Reg"; - else - Signature += Op.Class->ClassName; - Signature += utostr(Op.OperandInfo->MINumOperands); - Signature += "_" + utostr(MIOperandList[i].second); - - - CaseOS << " ((" << TargetOperandClass << "*)Operands[" - << MIOperandList[i].second << "+1])->" << Op.Class->RenderMethod - << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; - CurIndex += Op.OperandInfo->MINumOperands; - } - - // And add trailing implicit operands. - for (; CurIndex != NumMIOperands; ++CurIndex) { - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - - if (!Tie) { - // If not, this is some implicit operand. Just assume it is a register - // for now. - CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - Signature += "__Imp"; - } else { + + // If this operand is tied to a previous one, just copy the MCInst operand + // from the earlier one. + int TiedOp = OpInfo.getTiedRegister(); + if (TiedOp != -1) { // Copy the tied operand. - assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); - CaseOS << " Inst.addOperand(Inst.getOperand(" - << Tie->second << "));\n"; - Signature += "__Tie" + utostr(Tie->second); + // FIXME: What if the operand has multiple MINumOperands? This happens + // in ARM. + //assert(OpInfo.MINumOperands == 1); + + assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!"); + CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; + Signature += "__Tie" + itostr(TiedOp); + continue; } - } + // Otherwise this is some sort of dummy operand that is mentioned in the + // ins/outs list but not mentioned in the asmstring, brutalize a dummy + // value into the operand. + // FIXME: This is a terrible hack: If an MCInst operand doesn't occur in + // the asmstring, there is no way to parse something meaningful. + // Just assume it is a zero register for now. + CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; + Signature += "__Imp"; + } + II.ConversionFnKind = Signature; // Check if we have already generated this signature. Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=118104&r1=118103&r2=118104&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Tue Nov 2 17:55:03 2010 @@ -102,7 +102,18 @@ const std::string &EMN, unsigned MION, unsigned MINO, DagInit *MIOI) : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN), - MIOperandNo(MION), MINumOperands(MINO), MIOperandInfo(MIOI) {} + MIOperandNo(MION), MINumOperands(MINO), MIOperandInfo(MIOI) {} + + + /// getTiedOperand - If this operand is tied to another one, return the + /// other operand number. Otherwise, return -1. + int getTiedRegister() const { + for (unsigned j = 0, e = Constraints.size(); j != e; ++j) { + const CGIOperandList::ConstraintInfo &CI = Constraints[j]; + if (CI.isTied()) return CI.getTiedOperand(); + } + return -1; + } }; CGIOperandList(Record *D); From gohman at apple.com Tue Nov 2 17:55:34 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 22:55:34 -0000 Subject: [llvm-commits] [llvm] r118105 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102225534.5A7BB2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 17:55:34 2010 New Revision: 118105 URL: http://llvm.org/viewvc/llvm-project?rev=118105&view=rev Log: Avoid manipulating paths in fixed-sized arrays. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118105&r1=118104&r2=118105&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 17:55:34 2010 @@ -143,8 +143,7 @@ // Linux and FreeBSD have it. Others probably won't. char pathname[] = "/tmp/llvm_XXXXXX"; if (0 == mkdtemp(pathname)) { - MakeErrMsg(ErrMsg, - std::string(pathname) + ": can't create temporary directory"); + MakeErrMsg(ErrMsg, pathname + ": can't create temporary directory"); return Path(); } Path result; @@ -681,8 +680,7 @@ bool Path::createDirectoryOnDisk( bool create_parents, std::string* ErrMsg ) { // Get a writeable copy of the path name - char pathname[MAXPATHLEN]; - path.copy(pathname,MAXPATHLEN); + std::string pathname(path); // Null-terminate the last component size_t lastchar = path.length() - 1 ; @@ -692,7 +690,7 @@ pathname[lastchar] = '\0'; - if (createDirectoryHelper(pathname, pathname+lastchar, create_parents)) + if (createDirectoryHelper(&pathname[0], &pathname[lastchar], create_parents)) return MakeErrMsg(ErrMsg, std::string(pathname) + ": can't create directory"); @@ -759,17 +757,15 @@ } // Otherwise, try to just remove the one directory. - char pathname[MAXPATHLEN]; - path.copy(pathname, MAXPATHLEN); + std::string pathname(path); size_t lastchar = path.length() - 1; if (pathname[lastchar] == '/') pathname[lastchar] = '\0'; else pathname[lastchar+1] = '\0'; - if (rmdir(pathname) != 0) - return MakeErrMsg(ErrStr, - std::string(pathname) + ": can't erase directory"); + if (rmdir(pathname.c_str()) != 0) + return MakeErrMsg(ErrStr, pathname + ": can't erase directory"); return false; } From gohman at apple.com Tue Nov 2 17:56:51 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 22:56:51 -0000 Subject: [llvm-commits] [llvm] r118106 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102225651.DCD8E2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 17:56:51 2010 New Revision: 118106 URL: http://llvm.org/viewvc/llvm-project?rev=118106&view=rev Log: Fix a copy+pasto. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118106&r1=118105&r2=118106&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 17:56:51 2010 @@ -143,7 +143,8 @@ // Linux and FreeBSD have it. Others probably won't. char pathname[] = "/tmp/llvm_XXXXXX"; if (0 == mkdtemp(pathname)) { - MakeErrMsg(ErrMsg, pathname + ": can't create temporary directory"); + MakeErrMsg(ErrMsg, + std::string(pathname) + ": can't create temporary directory"); return Path(); } Path result; From isanbard at gmail.com Tue Nov 2 18:02:39 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 2 Nov 2010 16:02:39 -0700 Subject: [llvm-commits] [llvm] r118094 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/simple-fp-encoding.s In-Reply-To: <39F60132-FCF3-4D15-A988-09A6A5484874@apple.com> References: <20101102223146.47EA52A6C12C@llvm.org> <39F60132-FCF3-4D15-A988-09A6A5484874@apple.com> Message-ID: Hi Jim, I might not have explained my change very well. I wanted to convert the getAddrModeImm12OpValue into a generic function that gets the register and address information, and encodes that into an i32 to be used by the MC encoding stuff. The immediate isn't necessarily 16-bits in size (though it can be). In fact, for the VLDR stuff it's expecting an 8-bit immediate. The reason why I didn't create a getAddrModeImm8OpValue method was because it had the exact same code as getAddrModeImm12OpValue, just that the offsets of the values were different (the U bit was at {8} instead of {12}, etc.). :-) I'll be happy to rework this and create an imm8-specific method if that's desirable. It would be easy to refactor the original code to do that. -bw On Nov 2, 2010, at 3:51 PM, Jim Grosbach wrote: > Hi Bill, > > We should add a new addrmode_i16 for this rather than re-using the current one. How many bits are legal is part of the semantics, and is enforced by the selection dag stuff (SelectAddrModeImm12() in this case). For a parallel example, see the Thumb2 t2addrmode_imm12 and t2addrmode_imm8 modes in ARMInstrThumb2.td. > > -Jim > > On Nov 2, 2010, at 3:31 PM, Bill Wendling wrote: > >> Author: void >> Date: Tue Nov 2 17:31:46 2010 >> New Revision: 118094 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118094&view=rev >> Log: >> Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work >> with immediates up to 16-bits in size. The same logic is applied to other LDR >> encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in >> VLDR's case). Removing the "12" allows it to be more generic. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp >> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td >> llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >> llvm/trunk/test/MC/ARM/arm_instructions.s >> llvm/trunk/test/MC/ARM/simple-fp-encoding.s >> >> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 17:31:46 2010 >> @@ -177,26 +177,27 @@ >> const { return 0; } >> unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, >> unsigned Op) const { return 0; } >> - unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) >> - const { >> - // {17-13} = reg >> - // {12} = (U)nsigned (add == '1', sub == '0') >> - // {11-0} = imm12 >> - const MachineOperand &MO = MI.getOperand(Op); >> - const MachineOperand &MO1 = MI.getOperand(Op + 1); >> - if (!MO.isReg()) { >> - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); >> - return 0; >> - } >> - unsigned Reg = getARMRegisterNumbering(MO.getReg()); >> - int32_t Imm12 = MO1.getImm(); >> - uint32_t Binary; >> - Binary = Imm12 & 0xfff; >> - if (Imm12 >= 0) >> - Binary |= (1 << 12); >> - Binary |= (Reg << 13); >> - return Binary; >> + uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const { >> + // {20-17} = reg >> + // {16} = (U)nsigned (add == '1', sub == '0') >> + // {15-0} = imm >> + const MachineOperand &MO = MI.getOperand(Op); >> + const MachineOperand &MO1 = MI.getOperand(Op + 1); >> + if (!MO.isReg()) { >> + emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); >> + return 0; >> } >> + >> + unsigned Reg = getARMRegisterNumbering(MO.getReg()); >> + int32_t Imm = MO1.getImm(); >> + uint32_t Binary; >> + Binary = Imm & 0xffff; >> + if (Imm >= 0) >> + Binary |= (1 << 16); >> + >> + Binary |= (Reg << 17); >> + return Binary; >> + } >> unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) >> const { return 0; } >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118094&r1=118093&r2=118094&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 17:31:46 2010 >> @@ -398,7 +398,7 @@ >> // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other >> // immediate values are as normal. >> >> - string EncoderMethod = "getAddrModeImm12OpValue"; >> + string EncoderMethod = "getAddrModeImmOpValue"; >> let PrintMethod = "printAddrModeImm12Operand"; >> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); >> } >> @@ -464,6 +464,7 @@ >> let PrintMethod = "printAddrMode5Operand"; >> let MIOperandInfo = (ops GPR:$base, i32imm); >> let ParserMatchClass = ARMMemMode5AsmOperand; >> + string EncoderMethod = "getAddrModeImmOpValue"; >> } >> >> // addrmode6 := reg with optional writeback >> @@ -830,9 +831,9 @@ >> AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", >> [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { >> bits<4> Rt; >> - bits<17> addr; >> - let Inst{23} = addr{12}; // U (add = ('U' == 1)) >> - let Inst{19-16} = addr{16-13}; // Rn >> + bits<32> addr; >> + let Inst{23} = addr{16}; // U (add = ('U' == 1)) >> + let Inst{19-16} = addr{20-17}; // Rn >> let Inst{15-12} = Rt; >> let Inst{11-0} = addr{11-0}; // imm12 >> } >> @@ -840,9 +841,9 @@ >> AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", >> [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { >> bits<4> Rt; >> - bits<17> shift; >> - let Inst{23} = shift{12}; // U (add = ('U' == 1)) >> - let Inst{19-16} = shift{16-13}; // Rn >> + bits<32> shift; >> + let Inst{23} = shift{16}; // U (add = ('U' == 1)) >> + let Inst{19-16} = shift{20-17}; // Rn >> let Inst{11-0} = shift{11-0}; >> } >> } >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118094&r1=118093&r2=118094&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 17:31:46 2010 >> @@ -53,18 +53,29 @@ >> let canFoldAsLoad = 1, isReMaterializable = 1 in { >> def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), >> IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", >> - [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; >> + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { >> + // Instruction operands. >> + bits<5> Dd; >> + bits<32> addr; >> + >> + // Encode instruction operands. >> + let Inst{23} = addr{16}; // U (add = (U == '1')) >> + let Inst{22} = Dd{4}; >> + let Inst{19-16} = addr{20-17}; // Rn >> + let Inst{15-12} = Dd{3-0}; >> + let Inst{7-0} = addr{7-0}; // imm8 >> +} >> >> def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), >> IIC_fpLoad32, "vldr", ".32\t$dst, $addr", >> [(set SPR:$dst, (load addrmode5:$addr))]>; >> } // canFoldAsLoad >> >> -def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), >> +def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), >> IIC_fpStore64, "vstr", ".64\t$src, $addr", >> [(store (f64 DPR:$src), addrmode5:$addr)]>; >> >> -def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), >> +def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), >> IIC_fpStore32, "vstr", ".32\t$src, $addr", >> [(store SPR:$src, addrmode5:$addr)]>; >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:31:46 2010 >> @@ -49,9 +49,8 @@ >> /// operand requires relocation, record the relocation and return zero. >> unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; >> >> - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' >> - /// operand. >> - unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const; >> + /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. >> + uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const; >> >> /// getCCOutOpValue - Return encoding of the 's' bit. >> unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { >> @@ -170,37 +169,38 @@ >> return 0; >> } >> >> -/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' >> -/// operand. >> -unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, >> - unsigned OpIdx) const { >> - // {17-13} = reg >> - // {12} = (U)nsigned (add == '1', sub == '0') >> - // {11-0} = imm12 >> +/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. >> +uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI, >> + unsigned OpIdx) const { >> + // {20-17} = reg >> + // {16} = (U)nsigned (add == '1', sub == '0') >> + // {15-0} = imm >> const MCOperand &MO = MI.getOperand(OpIdx); >> const MCOperand &MO1 = MI.getOperand(OpIdx + 1); >> uint32_t Binary = 0; >> >> // If The first operand isn't a register, we have a label reference. >> if (!MO.isReg()) { >> - Binary |= ARM::PC << 13; // Rn is PC. >> + Binary |= ARM::PC << 17; // Rn is PC. >> // FIXME: Add a fixup referencing the label. >> return Binary; >> } >> >> unsigned Reg = getARMRegisterNumbering(MO.getReg()); >> - int32_t Imm12 = MO1.getImm(); >> - bool isAdd = Imm12 >= 0; >> + int32_t Imm = MO1.getImm(); >> + bool isAdd = Imm >= 0; >> + >> // Special value for #-0 >> - if (Imm12 == INT32_MIN) >> - Imm12 = 0; >> + if (Imm == INT32_MIN) >> + Imm = 0; >> + >> // Immediate is always encoded as positive. The 'U' bit controls add vs sub. >> - if (Imm12 < 0) >> - Imm12 = -Imm12; >> - Binary = Imm12 & 0xfff; >> + if (Imm < 0) Imm = -Imm; >> + >> + Binary = Imm & 0xffff; >> if (isAdd) >> - Binary |= (1 << 12); >> - Binary |= (Reg << 13); >> + Binary |= (1 << 16); >> + Binary |= (Reg << 17); >> return Binary; >> } >> >> @@ -320,7 +320,6 @@ >> return regno.getReg(); >> } >> >> - >> void ARMMCCodeEmitter:: >> EncodeInstruction(const MCInst &MI, raw_ostream &OS, >> SmallVectorImpl &Fixups) const { >> >> Modified: llvm/trunk/test/MC/ARM/arm_instructions.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=118094&r1=118093&r2=118094&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) >> +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Nov 2 17:31:46 2010 >> @@ -10,13 +10,8 @@ >> >> @ CHECK: bx lr >> @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1] >> -bx lr >> + bx lr >> >> @ CHECK: vqdmull.s32 q8, d17, d16 >> @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] >> -vqdmull.s32 q8, d17, d16 >> - >> -@ CHECK: vldr.64 d17, [r0] >> -@ CHECK: encoding: [0x00,0x0b,0x10,0xed] >> -vldr.64 d17, [r0] >> - >> + vqdmull.s32 q8, d17, d16 >> >> Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118094&r1=118093&r2=118094&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) >> +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 2 17:31:46 2010 >> @@ -157,3 +157,20 @@ >> >> @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] >> vmov r0, r1, d16 >> + >> +@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] >> + vldr.64 d17, [r0] >> + >> +@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] >> + vldr.64 d1, [r2, #32] >> + >> + >> +@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] >> + vldr.64 d2, [r3] >> + >> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >> + vldr.64 d3, [pc] >> + vldr.64 d3, [pc,#0] >> + vldr.64 d3, [pc,#-0] >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From John.Thompson.JTSoftware at gmail.com Tue Nov 2 18:01:45 2010 From: John.Thompson.JTSoftware at gmail.com (John Thompson) Date: Tue, 02 Nov 2010 23:01:45 -0000 Subject: [llvm-commits] [llvm] r118107 - in /llvm/trunk/test/CodeGen: ARM/mult-alt-generic-arm.ll MSP430/mult-alt-generic-msp430.ll PowerPC/mult-alt-generic-powerpc.ll PowerPC/mult-alt-generic-powerpc64.ll SPARC/mult-alt-generic-sparc.ll X86/mult-alt-generic-i686.ll X86/mult-alt-generic-x86_64.ll X86/mult-alt-x86.ll Message-ID: <20101102230145.244BE2A6C12C@llvm.org> Author: jtsoftware Date: Tue Nov 2 18:01:44 2010 New Revision: 118107 URL: http://llvm.org/viewvc/llvm-project?rev=118107&view=rev Log: Inline asm mult-alt constraint tests. Added: llvm/trunk/test/CodeGen/ARM/mult-alt-generic-arm.ll llvm/trunk/test/CodeGen/MSP430/mult-alt-generic-msp430.ll llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll llvm/trunk/test/CodeGen/SPARC/mult-alt-generic-sparc.ll llvm/trunk/test/CodeGen/X86/mult-alt-generic-i686.ll llvm/trunk/test/CodeGen/X86/mult-alt-generic-x86_64.ll llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll Added: llvm/trunk/test/CodeGen/ARM/mult-alt-generic-arm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mult-alt-generic-arm.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/mult-alt-generic-arm.ll (added) +++ llvm/trunk/test/CodeGen/ARM/mult-alt-generic-arm.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,323 @@ +; RUN: llc < %s -march=arm +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "arm" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define arm_aapcscc void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define arm_aapcscc void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define arm_aapcscc void @single_V() nounwind { +entry: + ret void +} + +define arm_aapcscc void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define arm_aapcscc void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define arm_aapcscc void @multi_V() nounwind { +entry: + ret void +} + +define arm_aapcscc void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} Added: llvm/trunk/test/CodeGen/MSP430/mult-alt-generic-msp430.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/mult-alt-generic-msp430.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/MSP430/mult-alt-generic-msp430.ll (added) +++ llvm/trunk/test/CodeGen/MSP430/mult-alt-generic-msp430.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,323 @@ +; RUN: llc < %s -march=msp430 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" +target triple = "msp430" + + at mout0 = common global i16 0, align 2 + at min1 = common global i16 0, align 2 + at marray = common global [2 x i16] zeroinitializer, align 2 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i16* @mout0, i16* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i16, align 2 + %index = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %index, align 2 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,r"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* %in1, align 2 + %1 = call i16 asm "foo $1,$0", "=r,r>"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,r"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r,i"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r,n"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,imr"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r,imr"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r,imr"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,X"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r,X"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r,X"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + %3 = call i16 asm "foo $1,$0", "=r,X"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %3, i16* %out0, align 2 +; No lowering support. +; %4 = call i16 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind +; store i16 %4, i16* %out0, align 2 +; %5 = call i16 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind +; store i16 %5, i16* %out0, align 2 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r,r"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i16* @min1, align 2 + call void asm "foo $1,$0", "=*m|r,m|r"(i16* @mout0, i16 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i16, align 2 + %index = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %index, align 2 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|r"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* %in1, align 2 + %1 = call i16 asm "foo $1,$0", "=r|r,r|r>"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|m"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|i"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|n"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + %3 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %3, i16* %out0, align 2 +; No lowering support. +; %4 = call i16 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind +; store i16 %4, i16* %out0, align 2 +; %5 = call i16 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind +; store i16 %5, i16* %out0, align 2 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|r"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} Added: llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,321 @@ +; RUN: llc < %s -march=ppc32 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} Added: llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,321 @@ +; RUN: llc < %s -march=ppc64 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} Added: llvm/trunk/test/CodeGen/SPARC/mult-alt-generic-sparc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/mult-alt-generic-sparc.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/SPARC/mult-alt-generic-sparc.ll (added) +++ llvm/trunk/test/CodeGen/SPARC/mult-alt-generic-sparc.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,323 @@ +; RUN: llc < %s -march=sparc +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32" +target triple = "sparc" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} Added: llvm/trunk/test/CodeGen/X86/mult-alt-generic-i686.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mult-alt-generic-i686.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/mult-alt-generic-i686.ll (added) +++ llvm/trunk/test/CodeGen/X86/mult-alt-generic-i686.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,321 @@ +; RUN: llc < %s -march=x86 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i686" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} Added: llvm/trunk/test/CodeGen/X86/mult-alt-generic-x86_64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mult-alt-generic-x86_64.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/mult-alt-generic-x86_64.ll (added) +++ llvm/trunk/test/CodeGen/X86/mult-alt-generic-x86_64.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,321 @@ +; RUN: llc < %s -march=x86-64 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r,X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r|r,r|X,~{dirflag},~{fpsr},~{flags}"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|im,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} Added: llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll?rev=118107&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll (added) +++ llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll Tue Nov 2 18:01:44 2010 @@ -0,0 +1,358 @@ +; RUN: llc < %s -march=x86 +; ModuleID = 'mult-alt-x86.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i686-pc-win32" + + at mout0 = common global i32 0, align 4 + at min1 = common global i32 0, align 4 + at dout0 = common global double 0.000000e+000, align 8 + at din1 = common global double 0.000000e+000, align 8 + at marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_R() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "=R,R,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_q() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "=q,q,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_Q() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "=Q,Q,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_a() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "={ax},{ax},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_b() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "={bx},{bx},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_c() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "={cx},{cx},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_d() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "={dx},{dx},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_S() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "={si},{si},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_D() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "={di},{di},~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_A() nounwind { +entry: + %tmp = load i32* @min1, align 4 + %0 = call i32 asm "foo $1,$0", "=A,A,~{dirflag},~{fpsr},~{flags}"(i32 %tmp) nounwind + store i32 %0, i32* @mout0, align 4 + ret void +} + +define void @single_f() nounwind { +entry: + ret void +} + +define void @single_t() nounwind { +entry: + ret void +} + +define void @single_u() nounwind { +entry: + ret void +} + +define void @single_y() nounwind { +entry: + %tmp = load double* @din1, align 8 + %0 = call double asm "foo $1,$0", "=y,y,~{dirflag},~{fpsr},~{flags}"(double %tmp) nounwind + store double %0, double* @dout0, align 8 + ret void +} + +define void @single_x() nounwind { +entry: + %tmp = load double* @din1, align 8 + %0 = call double asm "foo $1,$0", "=x,x,~{dirflag},~{fpsr},~{flags}"(double %tmp) nounwind + store double %0, double* @dout0, align 8 + ret void +} + +define void @single_Y0() nounwind { +entry: + ret void +} + +define void @single_I() nounwind { +entry: + call void asm "foo $1,$0", "=*m,I,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_J() nounwind { +entry: + call void asm "foo $1,$0", "=*m,J,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_K() nounwind { +entry: + call void asm "foo $1,$0", "=*m,K,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_L() nounwind { +entry: +; Missing lowering support for 'L'. +; call void asm "foo $1,$0", "=*m,L,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_M() nounwind { +entry: +; Missing lowering support for 'M'. +; call void asm "foo $1,$0", "=*m,M,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_N() nounwind { +entry: + call void asm "foo $1,$0", "=*m,N,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_G() nounwind { +entry: +; Missing lowering support for 'G'. +; call void asm "foo $1,$0", "=*m,G,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, double 1.000000e+000) nounwind + ret void +} + +define void @single_C() nounwind { +entry: +; Missing lowering support for 'C'. +; call void asm "foo $1,$0", "=*m,C,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, double 1.000000e+000) nounwind + ret void +} + +define void @single_e() nounwind { +entry: + call void asm "foo $1,$0", "=*m,e,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @single_Z() nounwind { +entry: + call void asm "foo $1,$0", "=*m,Z,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_R() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|R|m,r|R|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_q() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|q|m,r|q|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_Q() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|Q|m,r|Q|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_a() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|{ax}|m,r|{ax}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_b() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|{bx}|m,r|{bx}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_c() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|{cx}|m,r|{cx}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_d() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|{dx}|m,r|{dx},~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_S() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|{si}|m,r|{si}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_D() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|{di}|m,r|{di}|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_A() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*r|A|m,r|A|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_f() nounwind { +entry: + ret void +} + +define void @multi_t() nounwind { +entry: + ret void +} + +define void @multi_u() nounwind { +entry: + ret void +} + +define void @multi_y() nounwind { +entry: + %tmp = load double* @din1, align 8 + call void asm "foo $1,$0", "=*r|y|m,r|y|m,~{dirflag},~{fpsr},~{flags}"(double* @dout0, double %tmp) nounwind + ret void +} + +define void @multi_x() nounwind { +entry: + %tmp = load double* @din1, align 8 + call void asm "foo $1,$0", "=*r|x|m,r|x|m,~{dirflag},~{fpsr},~{flags}"(double* @dout0, double %tmp) nounwind + ret void +} + +define void @multi_Y0() nounwind { +entry: + ret void +} + +define void @multi_I() nounwind { +entry: + call void asm "foo $1,$0", "=*r|m|m,r|I|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_J() nounwind { +entry: + call void asm "foo $1,$0", "=*r|m|m,r|J|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_K() nounwind { +entry: + call void asm "foo $1,$0", "=*r|m|m,r|K|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_L() nounwind { +entry: +; Missing lowering support for 'L'. +; call void asm "foo $1,$0", "=*r|m|m,r|L|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_M() nounwind { +entry: +; Missing lowering support for 'M'. +; call void asm "foo $1,$0", "=*r|m|m,r|M|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_N() nounwind { +entry: + call void asm "foo $1,$0", "=*r|m|m,r|N|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_G() nounwind { +entry: +; Missing lowering support for 'G'. +; call void asm "foo $1,$0", "=*r|m|m,r|G|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, double 1.000000e+000) nounwind + ret void +} + +define void @multi_C() nounwind { +entry: +; Missing lowering support for 'C'. +; call void asm "foo $1,$0", "=*r|m|m,r|C|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, double 1.000000e+000) nounwind + ret void +} + +define void @multi_e() nounwind { +entry: + call void asm "foo $1,$0", "=*r|m|m,r|e|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} + +define void @multi_Z() nounwind { +entry: + call void asm "foo $1,$0", "=*r|m|m,r|Z|m,~{dirflag},~{fpsr},~{flags}"(i32* @mout0, i32 1) nounwind + ret void +} From gohman at apple.com Tue Nov 2 18:16:26 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 23:16:26 -0000 Subject: [llvm-commits] [llvm] r118110 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102231626.AD97A2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 18:16:26 2010 New Revision: 118110 URL: http://llvm.org/viewvc/llvm-project?rev=118110&view=rev Log: Simplify. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118110&r1=118109&r2=118110&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 18:16:26 2010 @@ -692,8 +692,7 @@ pathname[lastchar] = '\0'; if (createDirectoryHelper(&pathname[0], &pathname[lastchar], create_parents)) - return MakeErrMsg(ErrMsg, - std::string(pathname) + ": can't create directory"); + return MakeErrMsg(ErrMsg, pathname + ": can't create directory"); return false; } From sabre at nondot.org Tue Nov 2 18:18:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 23:18:43 -0000 Subject: [llvm-commits] [llvm] r118112 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101102231843.571F92A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 18:18:43 2010 New Revision: 118112 URL: http://llvm.org/viewvc/llvm-project?rev=118112&view=rev Log: make MatchableInfo::Validate reject instructions (like LDR_PRE in ARM) that have complicated tying going on. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118112&r1=118111&r2=118112&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 18:18:43 2010 @@ -638,6 +638,7 @@ "' not supported by asm matcher. Mark isCodeGenOnly!"); // Verify that any operand is only mentioned once. + // We reject aliases and ignore instructions for now. if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { if (!Hack) throw TGError(TheDef->getLoc(), @@ -654,6 +655,33 @@ } } + // Validate the operand list to ensure we can handle this instruction. + for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OI = OperandList[i]; + + // Validate tied operands. + if (OI.getTiedRegister() != -1) { + // If we have a tied operand that consists of multiple MCOperands, reject + // it. We reject aliases and ignore instructions for now. + if (OI.MINumOperands != 1) { + if (!Hack) + throw TGError(TheDef->getLoc(), + "ERROR: tied operand '" + OI.Name + + "' has multiple MCOperands!"); + + // FIXME: Should reject these. The ARM backend hits this with $lane in a + // bunch of instructions. It is unclear what the right answer is. + DEBUG({ + errs() << "warning: '" << InstrName << "': " + << "ignoring instruction with multi-operand tied operand '" + << OI.Name << "'\n"; + }); + return false; + } + } + } + + return true; } @@ -1086,7 +1114,7 @@ // Start the enum, which we will generate inline. - OS << "// Unified function for converting operants to MCInst instances.\n\n"; + OS << "// Unified function for converting operands to MCInst instances.\n\n"; OS << "enum ConversionKind {\n"; // TargetOperandClass - This is the target's operand class, like X86Operand. @@ -1153,11 +1181,8 @@ // from the earlier one. int TiedOp = OpInfo.getTiedRegister(); if (TiedOp != -1) { - // Copy the tied operand. - // FIXME: What if the operand has multiple MINumOperands? This happens - // in ARM. - //assert(OpInfo.MINumOperands == 1); - + // Copy the tied operand. We can only tie single MCOperand values. + assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!"); CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; Signature += "__Tie" + itostr(TiedOp); From gohman at apple.com Tue Nov 2 18:19:55 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 02 Nov 2010 23:19:55 -0000 Subject: [llvm-commits] [llvm] r118113 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101102231955.B50B82A6C12C@llvm.org> Author: djg Date: Tue Nov 2 18:19:55 2010 New Revision: 118113 URL: http://llvm.org/viewvc/llvm-project?rev=118113&view=rev Log: Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can check limits on their own. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118113&r1=118112&r2=118113&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 18:19:55 2010 @@ -96,10 +96,12 @@ bool Path::isValid() const { - // Check some obvious things - if (path.empty()) - return false; - return path.length() < MAXPATHLEN; + // Empty paths are considered invalid here. + // This code doesn't check MAXPATHLEN because there's no need. Nothing in + // LLVM manipulates Paths with fixed-sizes arrays, and if the OS can't + // handle names longer than some limit, it'll report this on demand using + // ENAMETOLONG. + return !path.empty(); } bool From fvbommel at gmail.com Tue Nov 2 18:37:59 2010 From: fvbommel at gmail.com (Frits van Bommel) Date: Wed, 3 Nov 2010 00:37:59 +0100 Subject: [llvm-commits] [llvm] r118092 - in /llvm/trunk/lib/Target/MBlaze: MBlazeInstrFPU.td MBlazeInstrInfo.td In-Reply-To: <20101102222633.7FFF22A6C12C@llvm.org> References: <20101102222633.7FFF22A6C12C@llvm.org> Message-ID: On Tue, Nov 2, 2010 at 11:26 PM, Chris Lattner wrote: > Author: lattner > Date: Tue Nov ?2 17:26:33 2010 > New Revision: 118092 > > URL: http://llvm.org/viewvc/llvm-project?rev=118092&view=rev > Log: > mark a few codegenonly instructions. Since these all use MBlazePseudo, and all MBlazePseudo-derived instructions now set isCodegenOnly = 1, wouldn't it make more sense to set it in once in that class? Or automatically set it in it's superclass, like you did for X86 and ARM in r117862[1]? [1]: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101025/110856.html From pdox at google.com Tue Nov 2 18:40:48 2010 From: pdox at google.com (David Meyer) Date: Tue, 2 Nov 2010 16:40:48 -0700 Subject: [llvm-commits] [PATCH] MCFragments Clean Up In-Reply-To: References: Message-ID: Rafael, If I didn't do this, ComputeSize() would need two more arguments: SectionAddress and FragmentOffset. MCAlignFragment uses SectionAddress + FragmentOffset, while MCOrgFragment uses FragmentOffset. I was trying to avoid cluttering up the function arguments with specific values needed for one or two fragment types. Since we have to pass the MCAsmLayout anyway, it seems reasonable that it should be capable of answering those values for the current fragment (since they are guaranteed to be known). In order to avoid passing FragmentOffset, your patch uses private member "Offset" directly, which is fragile (what if it is uninitialized?) and against the convention of using the accessor. Also, this won't work when you move the code away from MCFragment and into the subclasses. (Offset is a private member of MCFragment). - David M -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101102/101f5a06/attachment.html From stoklund at 2pi.dk Tue Nov 2 18:40:26 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 02 Nov 2010 23:40:26 -0000 Subject: [llvm-commits] [llvm] r118117 - in /llvm/trunk: include/llvm/Transforms/IPO.h lib/Transforms/IPO/Inliner.cpp Message-ID: <20101102234027.01A732A6C12C@llvm.org> Author: stoklund Date: Tue Nov 2 18:40:26 2010 New Revision: 118117 URL: http://llvm.org/viewvc/llvm-project?rev=118117&view=rev Log: Let the -inline-threshold command line argument take precedence over the threshold given to createFunctionInliningPass(). Both opt -O3 and clang would silently ignore the -inline-threshold option. Modified: llvm/trunk/include/llvm/Transforms/IPO.h llvm/trunk/lib/Transforms/IPO/Inliner.cpp Modified: llvm/trunk/include/llvm/Transforms/IPO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO.h?rev=118117&r1=118116&r2=118117&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/IPO.h (original) +++ llvm/trunk/include/llvm/Transforms/IPO.h Tue Nov 2 18:40:26 2010 @@ -99,6 +99,8 @@ /// createFunctionInliningPass - Return a new pass object that uses a heuristic /// to inline direct function calls to small functions. /// +/// The -inline-threshold command line option takes precedence over the +/// threshold given here. Pass *createFunctionInliningPass(); Pass *createFunctionInliningPass(int Threshold); Modified: llvm/trunk/lib/Transforms/IPO/Inliner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/Inliner.cpp?rev=118117&r1=118116&r2=118117&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/Inliner.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/Inliner.cpp Tue Nov 2 18:40:26 2010 @@ -52,7 +52,8 @@ : CallGraphSCCPass(ID), InlineThreshold(InlineLimit) {} Inliner::Inliner(char &ID, int Threshold) - : CallGraphSCCPass(ID), InlineThreshold(Threshold) {} + : CallGraphSCCPass(ID), InlineThreshold(InlineLimit.getNumOccurrences() > 0 ? + InlineLimit : Threshold) {} /// getAnalysisUsage - For this class, we declare that we require and preserve /// the call graph. If the derived class implements this method, it should From stoklund at 2pi.dk Tue Nov 2 18:40:29 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 02 Nov 2010 23:40:29 -0000 Subject: [llvm-commits] [llvm] r118118 - /llvm/trunk/tools/opt/opt.cpp Message-ID: <20101102234029.257F22A6C12D@llvm.org> Author: stoklund Date: Tue Nov 2 18:40:28 2010 New Revision: 118118 URL: http://llvm.org/viewvc/llvm-project?rev=118118&view=rev Log: Tweak the opt -O2 / opt -O3 inliner thresholds to be the same as llvm-gcc and clang are using. Modified: llvm/trunk/tools/opt/opt.cpp Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=118118&r1=118117&r2=118118&view=diff ============================================================================== --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Tue Nov 2 18:40:28 2010 @@ -355,9 +355,9 @@ if (DisableInline) { // No inlining pass } else if (OptLevel) { - unsigned Threshold = 200; + unsigned Threshold = 225; if (OptLevel > 2) - Threshold = 250; + Threshold = 275; InliningPass = createFunctionInliningPass(Threshold); } else { InliningPass = createAlwaysInlinerPass(); From sabre at nondot.org Tue Nov 2 18:40:41 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 23:40:41 -0000 Subject: [llvm-commits] [llvm] r118119 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101102234041.AC05D2A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 18:40:41 2010 New Revision: 118119 URL: http://llvm.org/viewvc/llvm-project?rev=118119&view=rev Log: Completely reject instructions that have an operand in their ins/outs list that isn't specified by their asmstring. Previously the asmmatcher would just force a 0 register into it, which clearly isn't right. Mark a bunch of ARM instructions that use this as isCodeGenOnly. Some of them are clearly pseudo instructions (like t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will either need to be removed or the asmmatcher will need to be taught about it (someday). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118119&r1=118118&r2=118119&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 18:40:41 2010 @@ -1352,39 +1352,41 @@ def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, "b\t$target", [(br bb:$target)]>; - let isNotDuplicable = 1, isIndirectBranch = 1 in { - def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), - IIC_Br, "mov\tpc, $target$jt", - [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { - let Inst{11-4} = 0b00000000; - let Inst{15-12} = 0b1111; - let Inst{20} = 0; // S Bit - let Inst{24-21} = 0b1101; - let Inst{27-25} = 0b000; - } - def BR_JTm : JTI<(outs), - (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), - IIC_Br, "ldr\tpc, $target$jt", - [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, - imm:$id)]> { - let Inst{15-12} = 0b1111; - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 1; // P bit - let Inst{27-25} = 0b011; - } - def BR_JTadd : JTI<(outs), - (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), - IIC_Br, "add\tpc, $target, $idx$jt", - [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, - imm:$id)]> { - let Inst{15-12} = 0b1111; - let Inst{20} = 0; // S bit - let Inst{24-21} = 0b0100; - let Inst{27-25} = 0b000; - } - } // isNotDuplicable = 1, isIndirectBranch = 1 + let isNotDuplicable = 1, isIndirectBranch = 1, + // FIXME: $imm field is not specified by asm string. Mark as cgonly. + isCodeGenOnly = 1 in { + def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), + IIC_Br, "mov\tpc, $target$jt", + [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { + let Inst{11-4} = 0b00000000; + let Inst{15-12} = 0b1111; + let Inst{20} = 0; // S Bit + let Inst{24-21} = 0b1101; + let Inst{27-25} = 0b000; + } + def BR_JTm : JTI<(outs), + (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), + IIC_Br, "ldr\tpc, $target$jt", + [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, + imm:$id)]> { + let Inst{15-12} = 0b1111; + let Inst{20} = 1; // L bit + let Inst{21} = 0; // W bit + let Inst{22} = 0; // B bit + let Inst{24} = 1; // P bit + let Inst{27-25} = 0b011; + } + def BR_JTadd : JTI<(outs), + (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), + IIC_Br, "add\tpc, $target, $idx$jt", + [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, + imm:$id)]> { + let Inst{15-12} = 0b1111; + let Inst{20} = 0; // S bit + let Inst{24-21} = 0b0100; + let Inst{27-25} = 0b000; + } + } // isNotDuplicable = 1, isIndirectBranch = 1 } // isBarrier = 1 // FIXME: should be able to write a pattern for ARMBrcond, but can't use @@ -1494,7 +1496,8 @@ IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr", [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, + isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring? // Load doubleword def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr", @@ -1595,7 +1598,8 @@ [(truncstorei16 GPR:$src, addrmode3:$addr)]>; // Store doubleword -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in +let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, + isCodeGenOnly = 1 in // $src2 doesn't exist in asm string def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), StMiscFrm, IIC_iStore_d_r, "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118119&r1=118118&r2=118119&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Nov 2 18:40:41 2010 @@ -931,7 +931,8 @@ defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, UnOpFrag<(sextloadi8 node:$Src)>>; -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, + isCodeGenOnly = 1 in { // $dst doesn't exist in asmstring? // Load doubleword def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2), (ins t2addrmode_imm8s4:$addr), @@ -1078,7 +1079,8 @@ BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; // Store doubleword -let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in +let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, + isCodeGenOnly = 1 in // $src2 doesn't exist in asm string def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr), IIC_iStore_d_r, "strd", "\t$src1, $addr", []>; @@ -1195,6 +1197,7 @@ let Inst{11-8} = 0b1100; } + let isCodeGenOnly = 1 in // $base doesn't exist in asmstring? def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc, "\t[pc, $imm]", []> { let Inst{31-25} = 0b1111100; @@ -2457,7 +2460,8 @@ let Inst{12} = 1; } -let isNotDuplicable = 1, isIndirectBranch = 1 in { +let isNotDuplicable = 1, isIndirectBranch = 1, + isCodeGenOnly = 1 in { // $id doesn't exist in asmstring, should be lowered. def t2BR_JT : T2JTI<(outs), (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), @@ -2472,6 +2476,7 @@ } // FIXME: Add a non-pc based case that can be predicated. +let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered. def t2TBB : T2JTI<(outs), (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), @@ -2483,6 +2488,7 @@ let Inst{7-4} = 0b0000; // B form } +let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered. def t2TBH : T2JTI<(outs), (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118119&r1=118118&r2=118119&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Nov 2 18:40:41 2010 @@ -1176,27 +1176,21 @@ continue; } + // Otherwise, this must be a tied operand if not, it is something that is + // mentioned in the ins/outs list but not in the asm string. + int TiedOp = OpInfo.getTiedRegister(); + if (TiedOp == -1) + throw TGError(II.TheDef->getLoc(), "Instruction '" + + II.TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); // If this operand is tied to a previous one, just copy the MCInst operand // from the earlier one. - int TiedOp = OpInfo.getTiedRegister(); - if (TiedOp != -1) { - // Copy the tied operand. We can only tie single MCOperand values. - assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); - assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!"); - CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; - Signature += "__Tie" + itostr(TiedOp); - continue; - } - - // Otherwise this is some sort of dummy operand that is mentioned in the - // ins/outs list but not mentioned in the asmstring, brutalize a dummy - // value into the operand. - // FIXME: This is a terrible hack: If an MCInst operand doesn't occur in - // the asmstring, there is no way to parse something meaningful. - // Just assume it is a zero register for now. - CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - Signature += "__Imp"; + // Copy the tied operand. We can only tie single MCOperand values. + assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); + assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!"); + CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; + Signature += "__Tie" + itostr(TiedOp); } II.ConversionFnKind = Signature; From sabre at nondot.org Tue Nov 2 18:44:50 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 23:44:50 -0000 Subject: [llvm-commits] [llvm] r118120 - /llvm/trunk/test/MC/Disassembler/neon-tests.txt Message-ID: <20101102234450.92D452A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 18:44:50 2010 New Revision: 118120 URL: http://llvm.org/viewvc/llvm-project?rev=118120&view=rev Log: temporarily xfail this. Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=118120&r1=118119&r2=118120&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Tue Nov 2 18:44:50 2010 @@ -1,4 +1,5 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# XFAIL: * # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 @@ -9,8 +10,8 @@ # CHECK: vdup.32 q3, d1[0] 0x41 0x6c 0xb4 0xf3 -# CHECK: vld1.8 {d17, d18}, [r6], r5 -0x05 0x1a 0x66 0xf4 +# HECK: vld1.8 {d17, d18}, [r6], r5 +#0x05 0x1a 0x66 0xf4 # CHECK: vld1.8 {d17, d18, d19}, [r6], r5 0x05 0x16 0x66 0xf4 From resistor at mac.com Tue Nov 2 18:47:29 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 02 Nov 2010 23:47:29 -0000 Subject: [llvm-commits] [llvm] r118121 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td Message-ID: <20101102234729.E6BFF2A6C12C@llvm.org> Author: resistor Date: Tue Nov 2 18:47:29 2010 New Revision: 118121 URL: http://llvm.org/viewvc/llvm-project?rev=118121&view=rev Log: Revert r118097 to fix buildbots. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118121&r1=118120&r2=118121&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 2 18:47:29 2010 @@ -1773,13 +1773,13 @@ let Inst{7-4} = op7_4; bits<5> Vd; - bits<6> addr; - bits<4> offset; + bits<6> Rn; + bits<4> Rm; let Inst{22} = Vd{4}; let Inst{15-12} = Vd{3-0}; - let Inst{19-16} = addr{3-0}; - let Inst{3-0} = offset{3-0}; + let Inst{19-16} = Rn{3-0}; + let Inst{3-0} = Rm{3-0}; } class NLdStLn op21_20, bits<4> op11_8, bits<4> op7_4, Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118121&r1=118120&r2=118121&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 18:47:29 2010 @@ -165,17 +165,17 @@ // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd), - (ins addrmode6:$addr), IIC_VLD1, - "vld1", Dt, "\\{$Vd\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + (ins addrmode6:$Rn), IIC_VLD1, + "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; } class VLD1Q op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2), - (ins addrmode6:$addr), IIC_VLD1x2, - "vld1", Dt, "\\{$Vd, $dst2\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn), IIC_VLD1x2, + "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } def VLD1d8 : VLD1D<{0,0,0,?}, "8">; @@ -196,17 +196,17 @@ // ...with address register writeback: class VLD1DWB op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD1u, - "vld1", Dt, "\\{$Vd\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u, + "vld1", Dt, "\\{$Vd\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } class VLD1QWB op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD1x2u, - "vld1", Dt, "\\{$Vd, $dst2\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u, + "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">; @@ -227,16 +227,16 @@ // ...with 3 registers (some of these are only for the disassembler): class VLD1D3 op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr), IIC_VLD1x3, "vld1", Dt, - "\\{$Vd, $dst2, $dst3\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt, + "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; } class VLD1D3WB op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD1x3u, "vld1", Dt, - "\\{$Vd, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt, + "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } def VLD1d8T : VLD1D3<{0,0,0,?}, "8">; @@ -255,18 +255,18 @@ // ...with 4 registers (some of these are only for the disassembler): class VLD1D4 op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD1x4, "vld1", Dt, - "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt, + "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } class VLD1D4WB op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD4, "vld1", Dt, - "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb", + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt, + "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + let Inst{5-4} = Rn{5-4}; } def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">; @@ -285,18 +285,18 @@ // VLD2 : Vector Load (multiple 2-element structures) class VLD2D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), - (ins addrmode6:$addr), IIC_VLD2, - "vld2", Dt, "\\{$Vd, $dst2\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn), IIC_VLD2, + "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } class VLD2Q op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD2x2, - "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn), IIC_VLD2x2, + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">; @@ -318,18 +318,18 @@ // ...with address register writeback: class VLD2DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD2u, - "vld2", Dt, "\\{$Vd, $dst2\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u, + "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } class VLD2QWB op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD2x2u, - "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u, + "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">; @@ -359,10 +359,10 @@ // VLD3 : Vector Load (multiple 3-element structures) class VLD3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr), IIC_VLD3, - "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + (ins addrmode6:$Rn), IIC_VLD3, + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; @@ -377,10 +377,10 @@ class VLD3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD3u, - "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, + "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; @@ -412,10 +412,10 @@ class VLD4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD4, - "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn), IIC_VLD4, + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; @@ -430,10 +430,10 @@ class VLD4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset), IIC_VLD4, - "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, + "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; @@ -494,13 +494,13 @@ class VLD1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), - (ins addrmode6:$addr, DPR:$src, nohash_imm:$lane), - IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $addr", + (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), + IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", "$src = $Vd", [(set DPR:$Vd, (vector_insert (Ty DPR:$src), - (i32 (LoadOp addrmode6:$addr)), + (i32 (LoadOp addrmode6:$Rn)), imm:$lane))]> { - let offset = 0b1111; + let Rm = 0b1111; } class VLD1QLNPseudo : VLDQLNPseudo { let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), @@ -513,12 +513,12 @@ } def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> { let Inst{7-6} = lane{1-0}; - let Inst{4} = addr{4}; + let Inst{4} = Rn{4}; } def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> { let Inst{7} = lane{0}; - let Inst{5} = addr{4}; - let Inst{4} = addr{4}; + let Inst{5} = Rn{4}; + let Inst{4} = Rn{4}; } def VLD1LNq8Pseudo : VLD1QLNPseudo; @@ -530,22 +530,22 @@ // ...with address register writeback: class VLD1LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, - "\\{$Vd[$lane]\\}, $addr$offset", - "$src = $Vd, $addr.addr = $wb", []>; + "\\{$Vd[$lane]\\}, $Rn$Rm", + "$src = $Vd, $Rn.addr = $wb", []>; def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = addr{4}; + let Inst{4} = Rn{4}; } def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{4}; - let Inst{4} = addr{4}; + let Inst{5} = Rn{4}; + let Inst{4} = Rn{4}; } def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo; @@ -555,11 +555,11 @@ // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $addr", + (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> { @@ -590,11 +590,11 @@ // ...with address register writeback: class VLD2LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, - "\\{$Vd[$lane], $dst2[$lane]\\}, $addr$offset", - "$src1 = $Vd, $src2 = $dst2, $addr.addr = $wb", []> { - let Inst{4} = addr{4}; + "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", + "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> { @@ -624,11 +624,11 @@ // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, - "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr", + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> { - let offset = 0b1111; + let Rm = 0b1111; } def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { @@ -660,11 +660,11 @@ class VLD3LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3lnu, "vld3", Dt, - "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset", - "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb", + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", + "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", []>; def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { @@ -695,12 +695,12 @@ class VLD4LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, - "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr", + "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> { @@ -711,7 +711,7 @@ } def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VLD4LNd8Pseudo : VLDQQLNPseudo; @@ -724,7 +724,7 @@ } def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VLD4LNq16Pseudo : VLDQQQQLNPseudo; @@ -734,13 +734,13 @@ class VLD4LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, -"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $addr$offset", -"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $addr.addr = $wb", +"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", +"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", []> { - let Inst{4} = addr{4}; + let Inst{4} = Rn{4}; } def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> { @@ -751,7 +751,7 @@ } def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo; @@ -763,7 +763,7 @@ } def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo; @@ -799,17 +799,17 @@ // VST1 : Vector Store (multiple single elements) class VST1D op7_4, string Dt> - : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$Vd), - IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd), + IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; } class VST1Q op7_4, string Dt> : NLdSt<0,0b00,0b1010,op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2), IIC_VST1x2, - "vst1", Dt, "\\{$Vd, $src2\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2, + "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } def VST1d8 : VST1D<{0,0,0,?}, "8">; @@ -830,16 +830,16 @@ // ...with address register writeback: class VST1DWB op7_4, string Dt> : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd), IIC_VST1u, - "vst1", Dt, "\\{$Vd\\}, $addr$offset", "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u, + "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } class VST1QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2), - IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2), + IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">; @@ -860,18 +860,18 @@ // ...with 3 registers (some of these are only for the disassembler): class VST1D3 op7_4, string Dt> : NLdSt<0, 0b00, 0b0110, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3), - IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), + IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; } class VST1D3WB op7_4, string Dt> : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3), - IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } def VST1d8T : VST1D3<{0,0,0,?}, "8">; @@ -890,19 +890,19 @@ // ...with 4 registers (some of these are only for the disassembler): class VST1D4 op7_4, string Dt> : NLdSt<0, 0b00, 0b0010, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr", "", + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } class VST1D4WB op7_4, string Dt> : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u, - "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VST1d8Q : VST1D4<{0,0,?,?}, "8">; @@ -921,18 +921,18 @@ // VST2 : Vector Store (multiple 2-element structures) class VST2D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2), - IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), + IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } class VST2Q op7_4, string Dt> : NLdSt<0, 0b00, 0b0011, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr", + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">; @@ -954,18 +954,18 @@ // ...with address register writeback: class VST2DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, DPR:$Vd, DPR:$src2), - IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2), + IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } class VST2QWB op7_4, string Dt> : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u, - "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">; @@ -995,10 +995,10 @@ // VST3 : Vector Store (multiple 3-element structures) class VST3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, - "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $addr", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, + "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { + let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">; @@ -1012,11 +1012,11 @@ // ...with address register writeback: class VST3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u, - "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">; @@ -1047,11 +1047,11 @@ // VST4 : Vector Store (multiple 4-element structures) class VST4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), - IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr", + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), + IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "", []> { - let offset = 0b1111; - let Inst{5-4} = addr{5-4}; + let Rm = 0b1111; + let Inst{5-4} = Rn{5-4}; } def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">; @@ -1065,11 +1065,11 @@ // ...with address register writeback: class VST4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, - "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{5-4} = addr{5-4}; + "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{5-4} = Rn{5-4}; } def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">; @@ -1126,9 +1126,9 @@ // VST1LN : Vector Store (single element from one lane) class VST1LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, nohash_imm:$lane), - IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $addr", "", []> { - let offset = 0b1111; + (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), + IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", []> { + let Rm = 0b1111; } def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8"> { @@ -1136,11 +1136,11 @@ } def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = addr{5}; + let Inst{4} = Rn{5}; } def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5-4} = addr{5-4}; + let Inst{5-4} = Rn{5-4}; } def VST1LNq8Pseudo : VSTQLNPseudo; @@ -1152,21 +1152,21 @@ // ...with address register writeback: class VST1LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, - "\\{$Vd[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []>; + "\\{$Vd[$lane]\\}, $Rn$Rm", + "$Rn.addr = $wb", []>; def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = addr{5}; + let Inst{4} = Rn{5}; } def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5-4} = addr{5-4}; + let Inst{5-4} = Rn{5-4}; } def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo; @@ -1176,11 +1176,11 @@ // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, nohash_imm:$lane), - IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $addr", + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane), + IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> { @@ -1200,11 +1200,11 @@ // ...with double-spaced registers: def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; - let Inst{4} = addr{4}; + let Inst{4} = Rn{4}; } def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> { let Inst{7} = lane{0}; - let Inst{4} = addr{4}; + let Inst{4} = Rn{4}; } def VST2LNq16Pseudo : VSTQQLNPseudo; @@ -1217,7 +1217,7 @@ DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt, "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset", "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + let Inst{4} = Rn{4}; } def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> { @@ -1247,10 +1247,10 @@ // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3ln, "vst3", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $addr", "", []> { - let offset = 0b1111; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> { + let Rm = 0b1111; } def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> { @@ -1281,11 +1281,11 @@ // ...with address register writeback: class VST3LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3lnu, "vst3", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []>; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", + "$Rn.addr = $wb", []>; def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; @@ -1314,12 +1314,12 @@ // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), - (ins addrmode6:$addr, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, + (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4ln, "vst4", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr", + "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", "", []> { - let offset = 0b1111; - let Inst{4} = addr{4}; + let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> { @@ -1330,7 +1330,7 @@ } def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VST4LNd8Pseudo : VSTQQLNPseudo; @@ -1343,7 +1343,7 @@ } def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VST4LNq16Pseudo : VSTQQQQLNPseudo; @@ -1352,12 +1352,12 @@ // ...with address register writeback: class VST4LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, addrmode6:$offset, + (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4lnu, "vst4", Dt, - "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $addr$offset", - "$addr.addr = $wb", []> { - let Inst{4} = addr{4}; + "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", + "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; } def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> { @@ -1368,7 +1368,7 @@ } def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo; @@ -1380,7 +1380,7 @@ } def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; - let Inst{5} = addr{5}; + let Inst{5} = Rn{5}; } def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo; From sabre at nondot.org Tue Nov 2 18:50:17 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 23:50:17 -0000 Subject: [llvm-commits] [llvm] r118122 - /llvm/trunk/test/MC/Disassembler/neon-tests.txt Message-ID: <20101102235017.C13E12A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 18:50:17 2010 New Revision: 118122 URL: http://llvm.org/viewvc/llvm-project?rev=118122&view=rev Log: tweak this to pass. Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=118122&r1=118121&r2=118122&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Tue Nov 2 18:50:17 2010 @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s -# XFAIL: * # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 @@ -10,13 +9,13 @@ # CHECK: vdup.32 q3, d1[0] 0x41 0x6c 0xb4 0xf3 -# HECK: vld1.8 {d17, d18}, [r6], r5 -#0x05 0x1a 0x66 0xf4 +# CHECK: vld1.8 {d17, d18}, [r6][r5] +0x05 0x1a 0x66 0xf4 -# CHECK: vld1.8 {d17, d18, d19}, [r6], r5 +# CHECK: vld1.8 {d17, d18, d19}, [r6][r5] 0x05 0x16 0x66 0xf4 -# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 +# CHECK: vld4.8 {d0, d1, d2, d3}, [r2][r7] 0x07 0x00 0x22 0xf4 # CHECK: vld4.8 {d4, d6, d8, d10}, [r2] From sabre at nondot.org Tue Nov 2 18:55:24 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 23:55:24 -0000 Subject: [llvm-commits] [llvm] r118124 - /llvm/trunk/test/MC/Disassembler/neon-tests.txt Message-ID: <20101102235524.718F82A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 18:55:24 2010 New Revision: 118124 URL: http://llvm.org/viewvc/llvm-project?rev=118124&view=rev Log: chase owen. Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=118124&r1=118123&r2=118124&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Tue Nov 2 18:55:24 2010 @@ -9,13 +9,13 @@ # CHECK: vdup.32 q3, d1[0] 0x41 0x6c 0xb4 0xf3 -# CHECK: vld1.8 {d17, d18}, [r6][r5] +# CHECK: vld1.8 {d17, d18}, [r6], r5 0x05 0x1a 0x66 0xf4 -# CHECK: vld1.8 {d17, d18, d19}, [r6][r5] +# CHECK: vld1.8 {d17, d18, d19}, [r6], r5 0x05 0x16 0x66 0xf4 -# CHECK: vld4.8 {d0, d1, d2, d3}, [r2][r7] +# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 0x07 0x00 0x22 0xf4 # CHECK: vld4.8 {d4, d6, d8, d10}, [r2] From sabre at nondot.org Tue Nov 2 18:57:06 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 02 Nov 2010 23:57:06 -0000 Subject: [llvm-commits] [llvm] r118125 - in /llvm/trunk/lib/Target/MBlaze: MBlazeInstrFPU.td MBlazeInstrFormats.td MBlazeInstrInfo.td Message-ID: <20101102235706.0DC402A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 18:57:05 2010 New Revision: 118125 URL: http://llvm.org/viewvc/llvm-project?rev=118125&view=rev Log: per a suggestion by Frits van Bommel, mark all MBlaze Pseudo instructions as isCodeGenOnly in the parent class instead of sprinkling it throughout the .td files. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td?rev=118125&r1=118124&r2=118125&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td Tue Nov 2 18:57:05 2010 @@ -124,7 +124,7 @@ } -let usesCustomInserter = 1, isCodeGenOnly = 1 in { +let usesCustomInserter = 1 in { def Select_FCC : MBlazePseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), "; SELECT_FCC PSEUDO!", Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=118125&r1=118124&r2=118125&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td Tue Nov 2 18:57:05 2010 @@ -49,8 +49,7 @@ // Generic MBlaze Format class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin> : Instruction -{ + list pattern, InstrItinClass itin> : Instruction { let Namespace = "MBlaze"; field bits<32> Inst; @@ -61,6 +60,10 @@ // Top 6 bits are the 'opcode' field let Inst{0-5} = opcode; + // If the instruction is marked as a pseudo, set isCodeGenOnly so that the + // assembler and disassmbler ignore it. + let isCodeGenOnly = !eq(!cast(form), "FPseudo"); + dag OutOperandList = outs; dag InOperandList = ins; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118125&r1=118124&r2=118125&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Tue Nov 2 18:57:05 2010 @@ -125,7 +125,7 @@ //===----------------------------------------------------------------------===// // As stack alignment is always done with addiu, we need a 16-bit immediate -let Defs = [R1], Uses = [R1], isCodeGenOnly = 1 in { +let Defs = [R1], Uses = [R1] in { def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt), "#ADJCALLSTACKDOWN $amt", [(callseq_start timm:$amt)]>; @@ -526,7 +526,7 @@ def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>; } -let usesCustomInserter = 1, isCodeGenOnly = 1 in { +let usesCustomInserter = 1 in { def Select_CC : MBlazePseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), "; SELECT_CC PSEUDO!", From echristo at apple.com Tue Nov 2 18:59:09 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 02 Nov 2010 23:59:09 -0000 Subject: [llvm-commits] [llvm] r118126 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101102235909.AB40F2A6C12C@llvm.org> Author: echristo Date: Tue Nov 2 18:59:09 2010 New Revision: 118126 URL: http://llvm.org/viewvc/llvm-project?rev=118126&view=rev Log: Make sure we're only storing a single bit here. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118126&r1=118125&r2=118126&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 2 18:59:09 2010 @@ -811,7 +811,15 @@ bool needReg0Op = false; switch (VT.getSimpleVT().SimpleTy) { default: return false; - case MVT::i1: + case MVT::i1: { + unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass : + ARM::GPRRegisterClass); + unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), Res) + .addReg(SrcReg).addImm(1)); + SrcReg = Res; + } // Fallthrough here. case MVT::i8: StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12; break; @@ -841,7 +849,6 @@ if (isFloat) Offset /= 4; - // FIXME: The 'needReg0Op' bit goes away once STRH is converted to // not use the mega-addrmode stuff. if (!needReg0Op) From gohman at apple.com Tue Nov 2 19:01:23 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Nov 2010 00:01:23 -0000 Subject: [llvm-commits] [llvm] r118127 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101103000123.66F002A6C12C@llvm.org> Author: djg Date: Tue Nov 2 19:01:23 2010 New Revision: 118127 URL: http://llvm.org/viewvc/llvm-project?rev=118127&view=rev Log: Remove several unhelpful checks for isValid from sys::Path. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118127&r1=118126&r2=118127&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 19:01:23 2010 @@ -149,10 +149,7 @@ std::string(pathname) + ": can't create temporary directory"); return Path(); } - Path result; - result.set(pathname); - assert(result.isValid() && "mkdtemp didn't create a valid pathname!"); - return result; + return Path(pathname); #elif defined(HAVE_MKSTEMP) // If no mkdtemp is available, mkstemp can be used to create a temporary file // which is then removed and created as a directory. We prefer this over @@ -173,10 +170,7 @@ std::string(pathname) + ": can't create temporary directory"); return Path(); } - Path result; - result.set(pathname); - assert(result.isValid() && "mkstemp didn't create a valid pathname!"); - return result; + return Path(pathname); #elif defined(HAVE_MKTEMP) // If a system doesn't have mkdtemp(3) or mkstemp(3) but it does have // mktemp(3) then we'll assume that system (e.g. AIX) has a reasonable @@ -195,10 +189,7 @@ std::string(TmpName) + ": can't create temporary directory"); return Path(); } - Path result; - result.set(TmpName); - assert(result.isValid() && "mktemp didn't create a valid pathname!"); - return result; + return Path(TmpName); #else // This is the worst case implementation. tempnam(3) leaks memory unless its // on an SVID2 (or later) system. On BSD 4.3 it leaks. tmpnam(3) has thread @@ -219,10 +210,7 @@ std::string(pathname) + ": can't create temporary directory"); return Path(); } - Path result; - result.set(pathname); - assert(result.isValid() && "mkstemp didn't create a valid pathname!"); - return result; + return Path(pathname); #endif } @@ -597,10 +585,6 @@ return false; std::string save(path); path = a_path; - if (!isValid()) { - path = save; - return false; - } return true; } @@ -612,10 +596,6 @@ if (!lastIsSlash(path)) path += '/'; path += name; - if (!isValid()) { - path = save; - return false; - } return true; } @@ -647,8 +627,6 @@ return true; } } - if (!isValid()) - path = save; return false; } From gohman at apple.com Tue Nov 2 19:09:12 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Nov 2010 00:09:12 -0000 Subject: [llvm-commits] [llvm] r118128 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20101103000912.CF90D2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 19:09:12 2010 New Revision: 118128 URL: http://llvm.org/viewvc/llvm-project?rev=118128&view=rev Log: Delete unused variables. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118128&r1=118127&r2=118128&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Nov 2 19:09:12 2010 @@ -583,7 +583,6 @@ Path::set(StringRef a_path) { if (a_path.empty()) return false; - std::string save(path); path = a_path; return true; } @@ -592,7 +591,6 @@ Path::appendComponent(StringRef name) { if (name.empty()) return false; - std::string save(path); if (!lastIsSlash(path)) path += '/'; path += name; @@ -618,7 +616,6 @@ bool Path::eraseSuffix() { - std::string save = path; size_t dotpos = path.rfind('.',path.size()); size_t slashpos = path.rfind('/',path.size()); if (dotpos != std::string::npos) { From gohman at apple.com Tue Nov 2 19:24:33 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Nov 2010 00:24:33 -0000 Subject: [llvm-commits] [llvm] r118130 - /llvm/trunk/lib/Support/SystemUtils.cpp Message-ID: <20101103002434.01BE52A6C12C@llvm.org> Author: djg Date: Tue Nov 2 19:24:33 2010 New Revision: 118130 URL: http://llvm.org/viewvc/llvm-project?rev=118130&view=rev Log: Print an error as one big string instead of breaking it up. Modified: llvm/trunk/lib/Support/SystemUtils.cpp Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=118130&r1=118129&r2=118130&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Tue Nov 2 19:24:33 2010 @@ -23,9 +23,9 @@ if (stream_to_check.is_displayed()) { if (print_warning) { errs() << "WARNING: You're attempting to print out a bitcode file.\n" - << "This is inadvisable as it may cause display problems. If\n" - << "you REALLY want to taste LLVM bitcode first-hand, you\n" - << "can force output with the `-f' option.\n\n"; + "This is inadvisable as it may cause display problems. If\n" + "you REALLY want to taste LLVM bitcode first-hand, you\n" + "can force output with the `-f' option.\n\n"; } return true; } From sabre at nondot.org Tue Nov 2 19:30:29 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 03 Nov 2010 00:30:29 -0000 Subject: [llvm-commits] [llvm] r118131 - /llvm/trunk/docs/TestingGuide.html Message-ID: <20101103003029.6C1622A6C12C@llvm.org> Author: lattner Date: Tue Nov 2 19:30:29 2010 New Revision: 118131 URL: http://llvm.org/viewvc/llvm-project?rev=118131&view=rev Log: fix typo, patch by Trevor Harmon (PR8537) Modified: llvm/trunk/docs/TestingGuide.html Modified: llvm/trunk/docs/TestingGuide.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TestingGuide.html?rev=118131&r1=118130&r2=118131&view=diff ============================================================================== --- llvm/trunk/docs/TestingGuide.html (original) +++ llvm/trunk/docs/TestingGuide.html Tue Nov 2 19:30:29 2010 @@ -237,7 +237,7 @@

where $LLVM_GCC_DIR is the directory where -you installed llvm-gcc, not it's src or obj +you installed llvm-gcc, not its src or obj dir. The --with-llvmgccdir option assumes that the llvm-gcc-4.2 module was configured with --program-prefix=llvm-, and therefore that the C and C++ From gohman at apple.com Tue Nov 2 19:38:41 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Nov 2010 00:38:41 -0000 Subject: [llvm-commits] [llvm] r118133 - in /llvm/trunk/include/llvm: ADT/APInt.h Support/MathExtras.h Message-ID: <20101103003841.1BC2C2A6C12C@llvm.org> Author: djg Date: Tue Nov 2 19:38:40 2010 New Revision: 118133 URL: http://llvm.org/viewvc/llvm-project?rev=118133&view=rev Log: Factor code out of APInt to form a isUIntN helper function. Modified: llvm/trunk/include/llvm/ADT/APInt.h llvm/trunk/include/llvm/Support/MathExtras.h Modified: llvm/trunk/include/llvm/ADT/APInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=118133&r1=118132&r2=118133&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APInt.h (original) +++ llvm/trunk/include/llvm/ADT/APInt.h Tue Nov 2 19:38:40 2010 @@ -348,7 +348,7 @@ return true; if (isSingleWord()) - return VAL == (VAL & (~0ULL >> (64 - N))); + return isUIntN(N, VAL); APInt Tmp(N, getNumWords(), pVal); Tmp.zext(getBitWidth()); return Tmp == (*this); Modified: llvm/trunk/include/llvm/Support/MathExtras.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MathExtras.h?rev=118133&r1=118132&r2=118133&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/MathExtras.h (original) +++ llvm/trunk/include/llvm/Support/MathExtras.h Tue Nov 2 19:38:40 2010 @@ -71,6 +71,12 @@ return static_cast(x) == x; } +/// isUIntN - Checks if an unsigned integer fits into the given (dynamic) +/// bit width. +inline bool isUIntN(unsigned N, uint64_t x) { + return x == (x & (~0ULL >> (64 - N))); +} + /// isMask_32 - This function returns true if the argument is a sequence of ones /// starting at the least significant bit with the remainder zero (32 bit /// version). Ex. isMask_32(0x0000FFFFU) == true. From evan.cheng at apple.com Tue Nov 2 19:40:22 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Nov 2010 00:40:22 -0000 Subject: [llvm-commits] [llvm] r118134 - in /llvm/trunk/lib/Target/ARM: ARMScheduleA8.td ARMScheduleA9.td Message-ID: <20101103004022.7BE062A6C12C@llvm.org> Author: evancheng Date: Tue Nov 2 19:40:22 2010 New Revision: 118134 URL: http://llvm.org/viewvc/llvm-project?rev=118134&view=rev Log: Modify scheduling itineraries to correct instruction latencies (not operand latencies) of loads. Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=118134&r1=118133&r2=118134&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Tue Nov 2 19:40:22 2010 @@ -98,76 +98,76 @@ // Integer load pipeline // // Immediate offset - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1]>, // // Register offset - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, // // Scaled register offset, issues over 2 cycles // FIXME: lsl by 2 takes 1 cycle. - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, // // Immediate offset with update - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, // // Register offset with update - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, // // Scaled register offset with update, issues over 2 cycles - InstrItinData, - InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>, - InstrItinData, - InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>, + InstrItinData, + InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, + InstrItinData, + InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, // // Load multiple, def is the 5th operand. Pipeline 0 only. // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>, // // Load multiple + update, defs are the 1st and 5th operands. - InstrItinData, + InstrItinData, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>, // // Load multiple plus branch - InstrItinData, + InstrItinData, InstrStage<3, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 2, 1, 1, 3]>, // // Pop, def is the 3rd operand. - InstrItinData, + InstrItinData, InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>, // // Push, def is the 3th operand. - InstrItinData, + InstrItinData, InstrStage<3, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 3]>, // // iLoadi + iALUr for t2LDRpci_pic. - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>, @@ -175,54 +175,54 @@ // Integer store pipeline // // Immediate offset - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1]>, // // Register offset - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, // // Scaled register offset, issues over 2 cycles - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, // // Immediate offset with update - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, // // Register offset with update - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, // // Scaled register offset with update, issues over 2 cycles - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, // // Store multiple. Pipeline 0 only. // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>]>, // // Store multiple + update - InstrItinData, + InstrItinData, InstrStage<2, [A8_LSPipe]>], [2]>, // Branch @@ -236,224 +236,224 @@ // possible. // // FP Special Register to Integer Register File Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [20]>, // // Single-precision FP Unary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [7, 1]>, // // Double-precision FP Unary - InstrItinData, + InstrItinData, InstrStage<4, [A8_NPipe], 0>, InstrStage<4, [A8_NLSPipe]>], [4, 1]>, // // Single-precision FP Compare - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [1, 1]>, // // Double-precision FP Compare - InstrItinData, + InstrItinData, InstrStage<4, [A8_NPipe], 0>, InstrStage<4, [A8_NLSPipe]>], [4, 1]>, // // Single to Double FP Convert - InstrItinData, + InstrItinData, InstrStage<7, [A8_NPipe], 0>, InstrStage<7, [A8_NLSPipe]>], [7, 1]>, // // Double to Single FP Convert - InstrItinData, + InstrItinData, InstrStage<5, [A8_NPipe], 0>, InstrStage<5, [A8_NLSPipe]>], [5, 1]>, // // Single-Precision FP to Integer Convert - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [7, 1]>, // // Double-Precision FP to Integer Convert - InstrItinData, + InstrItinData, InstrStage<8, [A8_NPipe], 0>, InstrStage<8, [A8_NLSPipe]>], [8, 1]>, // // Integer to Single-Precision FP Convert - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [7, 1]>, // // Integer to Double-Precision FP Convert - InstrItinData, + InstrItinData, InstrStage<8, [A8_NPipe], 0>, InstrStage<8, [A8_NLSPipe]>], [8, 1]>, // // Single-precision FP ALU - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, // // Double-precision FP ALU - InstrItinData, + InstrItinData, InstrStage<9, [A8_NPipe], 0>, InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>, // // Single-precision FP Multiply - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, // // Double-precision FP Multiply - InstrItinData, + InstrItinData, InstrStage<11, [A8_NPipe], 0>, InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>, // // Single-precision FP MAC - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>, // // Double-precision FP MAC - InstrItinData, + InstrItinData, InstrStage<19, [A8_NPipe], 0>, InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>, // // Single-precision FP DIV - InstrItinData, + InstrItinData, InstrStage<20, [A8_NPipe], 0>, InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>, // // Double-precision FP DIV - InstrItinData, + InstrItinData, InstrStage<29, [A8_NPipe], 0>, InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>, // // Single-precision FP SQRT - InstrItinData, + InstrItinData, InstrStage<19, [A8_NPipe], 0>, InstrStage<19, [A8_NLSPipe]>], [19, 1]>, // // Double-precision FP SQRT - InstrItinData, + InstrItinData, InstrStage<29, [A8_NPipe], 0>, InstrStage<29, [A8_NLSPipe]>], [29, 1]>, // // Integer to Single-precision Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [2, 1]>, // // Integer to Double-precision Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [2, 1, 1]>, // // Single-precision to Integer Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [20, 1]>, // // Double-precision to Integer Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [20, 20, 1]>, // // Single-precision FP Load - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1]>, // // Double-precision FP Load - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1]>, // // FP Load Multiple // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>, // // FP Load Multiple + update - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>, // // Single-precision FP Store - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1]>, // // Double-precision FP Store - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1]>, // // FP Store Multiple - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>, // // FP Store Multiple + update - InstrItinData, - InstrStage<1, [A8_NLSPipe]>, + InstrItinData, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, - InstrStage<1, [A8_NLSPipe]>, + InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>, // NEON // Issue through integer pipeline, and execute in NEON unit. // // VLD1 - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1]>, // VLD1x2 - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 1]>, // // VLD1x3 - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 1]>, // // VLD1x4 - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 1]>, // // VLD1u - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 1]>, // // VLD1x2u - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 2, 1]>, // // VLD1x3u - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 2, 1]>, // // VLD1x4u - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 2, 1]>, // @@ -470,134 +470,134 @@ [3, 2, 1, 1, 1, 1]>, // // VLD2 - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 1]>, // // VLD2x2 - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 1]>, // // VLD2ln - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [3, 3, 1, 1, 1, 1]>, // // VLD2u - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 2, 2, 1, 1, 1]>, // // VLD2x2u - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 2, 3, 3, 2, 1]>, // // VLD2lnu - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [3, 3, 2, 1, 1, 1, 1, 1]>, // // VLD3 - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 1]>, // // VLD3ln - InstrItinData, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 1, 1, 1, 1, 2]>, // // VLD3u - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 2, 1]>, // // VLD3lnu - InstrItinData, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>, // // VLD4 - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 4, 1]>, // // VLD4ln - InstrItinData, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>, // // VLD4u - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [3, 3, 4, 4, 2, 1]>, // // VLD4lnu - InstrItinData, - InstrStage<5, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<5, [A8_NLSPipe], 0>, InstrStage<5, [A8_LSPipe]>], [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>, // // VST1 - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1]>, // // VST1x2 - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1]>, // // VST1x3 - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2]>, // // VST1x4 - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST1u - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1]>, // // VST1x2u - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1]>, // // VST1x3u - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2]>, // // VST1x4u - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -614,360 +614,360 @@ [2, 1, 1, 1, 1]>, // // VST2 - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1]>, // // VST2x2 - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST2u - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1]>, // // VST2x2u - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // // VST2ln - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1]>, // // VST2lnu - InstrItinData, - InstrStage<2, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1]>, // // VST3 - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2]>, // // VST3u - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2]>, // // VST3ln - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [1, 1, 1, 1, 2]>, // // VST3lnu - InstrItinData, - InstrStage<3, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2]>, // // VST4 - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST4u - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // // VST4ln - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [1, 1, 1, 1, 2, 2]>, // // VST4lnu - InstrItinData, - InstrStage<4, [A8_NLSPipe], 1>, + InstrItinData, + InstrStage<4, [A8_NLSPipe], 0>, InstrStage<4, [A8_LSPipe]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // // Double-register FP Unary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [5, 2]>, // // Quad-register FP Unary // Result written in N5, but that is relative to the last cycle of multicycle, // so we use 6 for those cases - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [6, 2]>, // // Double-register FP Binary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, // // VPADD, etc. - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, // // Double-register FP VMUL - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [5, 2, 1]>, // // Quad-register FP Binary // Result written in N5, but that is relative to the last cycle of multicycle, // so we use 6 for those cases - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [6, 2, 2]>, // // Quad-register FP VMUL - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [6, 2, 1]>, // // Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [1, 1]>, // // Move Immediate - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3]>, // // Double-register Permute Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [2, 1]>, // // Quad-register Permute Move // Result written in N2, but that is relative to the last cycle of multicycle, // so we use 3 for those cases - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 1]>, // // Integer to Single-precision Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [2, 1]>, // // Integer to Double-precision Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, // // Single-precision to Integer Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [20, 1]>, // // Double-precision to Integer Move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>, // // Integer to Lane Move - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, // // Vector narrow move - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [2, 1]>, // // Double-register Permute - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>, // // Quad-register Permute // Result written in N2, but that is relative to the last cycle of multicycle, // so we use 3 for those cases - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>, // // Quad-register Permute (3 cycle issue) // Result written in N2, but that is relative to the last cycle of multicycle, // so we use 4 for those cases - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>, // // Double-register FP Multiple-Accumulate - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>, // // Quad-register FP Multiple-Accumulate // Result written in N9, but that is relative to the last cycle of multicycle, // so we use 10 for those cases - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>, // // Double-register Reciprical Step - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [9, 2, 2]>, // // Quad-register Reciprical Step - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [10, 2, 2]>, // // Double-register Integer Count - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, // // Quad-register Integer Count // Result written in N3, but that is relative to the last cycle of multicycle, // so we use 4 for those cases - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [4, 2, 2]>, // // Double-register Integer Unary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 2]>, // // Quad-register Integer Unary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 2]>, // // Double-register Integer Q-Unary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 1]>, // // Quad-register Integer CountQ-Unary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 1]>, // // Double-register Integer Binary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, // // Quad-register Integer Binary - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, // // Double-register Integer Binary (4 cycle) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Quad-register Integer Binary (4 cycle) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Double-register Integer Subtract - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, // // Quad-register Integer Subtract - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, // // Double-register Integer Subtract - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Quad-register Integer Subtract - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, // // Double-register Integer Shift - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [3, 1, 1]>, // // Quad-register Integer Shift - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [4, 1, 1]>, // // Double-register Integer Shift (4 cycle) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [4, 1, 1]>, // // Quad-register Integer Shift (4 cycle) - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [5, 1, 1]>, // // Double-register Integer Pair Add Long - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [6, 3, 1]>, // // Quad-register Integer Pair Add Long - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [7, 3, 1]>, // // Double-register Absolute Difference and Accumulate - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>, // // Quad-register Absolute Difference and Accumulate - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>, // // Double-register Integer Multiply (.8, .16) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [6, 2, 2]>, // // Double-register Integer Multiply (.32) - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [7, 2, 1]>, // // Quad-register Integer Multiply (.8, .16) - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [7, 2, 2]>, // // Quad-register Integer Multiply (.32) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>, InstrStage<2, [A8_NLSPipe], 0>, InstrStage<3, [A8_NPipe]>], [9, 2, 1]>, // // Double-register Integer Multiply-Accumulate (.8, .16) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>, // // Double-register Integer Multiply-Accumulate (.32) - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>, // // Quad-register Integer Multiply-Accumulate (.8, .16) - InstrItinData, + InstrItinData, InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>, // // Quad-register Integer Multiply-Accumulate (.32) - InstrItinData, + InstrItinData, InstrStage<1, [A8_NPipe]>, InstrStage<2, [A8_NLSPipe], 0>, InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>, // // Double-register VEXT - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, // // Quad-register VEXT - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, // // VTB - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>, - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>, // // VTBX - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>, - InstrItinData, + InstrItinData, InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>, - InstrItinData, + InstrItinData, InstrStage<1, [A8_NLSPipe]>, InstrStage<1, [A8_NPipe], 0>, InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]> Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=118134&r1=118133&r2=118134&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Tue Nov 2 19:40:22 2010 @@ -173,88 +173,88 @@ // Immediate offset InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 1], [A9_LdBypass]>, // FIXME: If address is 64-bit aligned, AGU cycles is 1. InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1], [A9_LdBypass]>, // // Register offset InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 1, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 1, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1, 1], [A9_LdBypass]>, // // Scaled register offset InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, - InstrStage<1, [A9_LSUnit]>], + InstrStage<1, [A9_AGU], 0>, + InstrStage<1, [A9_LSUnit], 0>], [4, 1, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [5, 1, 1], [A9_LdBypass]>, // // Immediate offset with update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 2, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1], [A9_LdBypass]>, // // Register offset with update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 2, 1, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [3, 3, 1, 1], [A9_LdBypass]>, // // Scaled register offset with update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [4, 3, 1, 1], [A9_LdBypass]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<2, [A9_AGU]>, + InstrStage<2, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [5, 4, 1, 1], [A9_LdBypass]>, // @@ -305,7 +305,7 @@ // iLoadi + iALUr for t2LDRpci_pic. InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>, InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>, @@ -315,7 +315,7 @@ // Immediate offset InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, @@ -330,7 +330,7 @@ // Register offset InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, @@ -344,7 +344,7 @@ // Scaled register offset InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, @@ -354,7 +354,7 @@ // Immediate offset with update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>, InstrItinData, InstrStage<1, [A9_MUX0], 0>, @@ -364,7 +364,7 @@ // Register offset with update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, InstrItinData, @@ -381,7 +381,7 @@ // Scaled register offset with update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, InstrItinData, @@ -393,13 +393,13 @@ // Store multiple InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>]>, // // Store multiple + update InstrItinData, InstrStage<1, [A9_MUX0], 0>, - InstrStage<1, [A9_AGU]>, + InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>], [2]>, // Branch @@ -657,7 +657,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -667,7 +667,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1]>, // @@ -676,7 +676,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>, // // FP Load Multiple + update @@ -684,7 +684,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, // // Single-precision FP Store @@ -692,7 +692,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -701,7 +701,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1]>, // @@ -710,7 +710,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>, // // FP Store Multiple + update @@ -718,7 +718,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, - InstrStage<1, [A9_NPipe]>, + InstrStage<1, [A9_NPipe], 0>, InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>, // NEON // VLD1 @@ -727,7 +727,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1]>, // VLD1x2 @@ -735,7 +735,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 1]>, // VLD1x3 @@ -743,7 +743,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 1]>, // VLD1x4 @@ -751,7 +751,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 1]>, // VLD1u @@ -759,7 +759,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 1]>, // VLD1x2u @@ -767,7 +767,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 2, 2, 1]>, // VLD1x3u @@ -775,7 +775,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 2, 1]>, // VLD1x4u @@ -783,7 +783,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 2, 3, 3, 2, 1]>, // @@ -811,7 +811,7 @@ InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 7 cycles InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [3, 3, 1]>, // @@ -820,7 +820,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [3, 4, 3, 4, 1]>, // @@ -829,7 +829,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 4, 1, 1, 1, 1]>, // @@ -839,7 +839,7 @@ InstrStage<1, [A9_DRegsN], 0, Required>, // Extra latency cycles since wbck is 7 cycles InstrStage<8, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [3, 3, 2, 1, 1, 1]>, // @@ -848,7 +848,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [3, 4, 3, 4, 2, 1]>, // @@ -857,7 +857,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 4, 2, 1, 1, 1, 1, 1]>, // @@ -866,7 +866,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 1]>, // @@ -875,7 +875,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 1, 1, 1, 1, 2]>, // @@ -884,7 +884,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 2, 1]>, // @@ -893,7 +893,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>, // @@ -902,7 +902,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 5, 1]>, // @@ -911,7 +911,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>, // @@ -920,7 +920,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<10,[A9_DRegsVFP], 0, Reserved>, - InstrStage<4, [A9_NPipe], 1>, + InstrStage<4, [A9_NPipe], 0>, InstrStage<4, [A9_LSUnit]>], [4, 4, 5, 5, 2, 1]>, // @@ -929,7 +929,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<11,[A9_DRegsVFP], 0, Reserved>, - InstrStage<5, [A9_NPipe], 1>, + InstrStage<5, [A9_NPipe], 0>, InstrStage<5, [A9_LSUnit]>], [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -938,7 +938,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1]>, // @@ -947,7 +947,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -956,7 +956,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -965,7 +965,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -974,7 +974,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1]>, // @@ -983,7 +983,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -992,7 +992,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1001,7 +1001,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1028,7 +1028,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -1037,7 +1037,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1046,7 +1046,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -1055,7 +1055,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1064,7 +1064,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>, // @@ -1073,7 +1073,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1]>, // @@ -1082,7 +1082,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -1091,7 +1091,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1100,7 +1100,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2]>, // @@ -1109,7 +1109,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2]>, // @@ -1118,7 +1118,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1127,7 +1127,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, // @@ -1136,7 +1136,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [1, 1, 1, 1, 2, 2]>, // @@ -1145,7 +1145,7 @@ InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1, 1, 2, 2]>, From evan.cheng at apple.com Tue Nov 2 19:45:17 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Nov 2010 00:45:17 -0000 Subject: [llvm-commits] [llvm] r118135 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ Message-ID: <20101103004517.AEC6B2A6C12C@llvm.org> Author: evancheng Date: Tue Nov 2 19:45:17 2010 New Revision: 118135 URL: http://llvm.org/viewvc/llvm-project?rev=118135&view=rev Log: Two sets of changes. Sorry they are intermingled. 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 Added: llvm/trunk/test/CodeGen/ARM/ifcvt11.ll Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll llvm/trunk/test/CodeGen/ARM/ifcvt10.ll llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll llvm/trunk/test/CodeGen/ARM/reg_sequence.ll llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Tue Nov 2 19:45:17 2010 @@ -247,6 +247,7 @@ unsigned NumSuccs; // # of SDep::Data sucss. unsigned NumPredsLeft; // # of preds not scheduled. unsigned NumSuccsLeft; // # of succs not scheduled. + bool isCall : 1; // Is a function call. bool isTwoAddress : 1; // Is a two-address instruction. bool isCommutable : 1; // Is a commutable instruction. bool hasPhysRegDefs : 1; // Has physreg defs that are being used. @@ -273,7 +274,8 @@ SUnit(SDNode *node, unsigned nodenum) : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), - NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), + NumSuccsLeft(0), + isCall(false), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), @@ -286,7 +288,8 @@ SUnit(MachineInstr *instr, unsigned nodenum) : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), - NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), + NumSuccsLeft(0), + isCall(false), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), @@ -298,7 +301,8 @@ SUnit() : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), - NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), + NumSuccsLeft(0), + isCall(false), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Nov 2 19:45:17 2010 @@ -304,12 +304,14 @@ return true; } - /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs" + /// isProfitableToIfCvt - Return true if it's profitable to predicate + /// instructions with accumulated instruction latency of "NumCycles" /// of the specified basic block, where the probability of the instructions /// being executed is given by Probability, and Confidence is a measure /// of our confidence that it will be properly predicted. virtual - bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, + bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, + unsigned ExtraPredCycles, float Probability, float Confidence) const { return false; } @@ -321,19 +323,22 @@ /// by Probability, and Confidence is a measure of our confidence that it /// will be properly predicted. virtual bool - isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, - MachineBasicBlock &FMBB, unsigned NumFInstrs, + isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned NumTCycles, unsigned ExtraTCycles, + MachineBasicBlock &FMBB, + unsigned NumFCycles, unsigned ExtraFCycles, float Probability, float Confidence) const { return false; } /// isProfitableToDupForIfCvt - Return true if it's profitable for - /// if-converter to duplicate a specific number of instructions in the - /// specified MBB to enable if-conversion, where the probability of the - /// instructions being executed is given by Probability, and Confidence is - /// a measure of our confidence that it will be properly predicted. + /// if-converter to duplicate instructions of specified accumulated + /// instruction latencies in the specified MBB to enable if-conversion. + /// The probability of the instructions being executed is given by + /// Probability, and Confidence is a measure of our confidence that it + /// will be properly predicted. virtual bool - isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, + isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, float Probability, float Confidence) const { return false; } @@ -608,24 +613,31 @@ /// getNumMicroOps - Return the number of u-operations the given machine /// instruction will be decoded to on the target cpu. - virtual unsigned getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData *ItinData) const; + virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, + const MachineInstr *MI) const; /// getOperandLatency - Compute and return the use operand latency of a given - /// itinerary class and operand index if the value is produced by an - /// instruction of the specified itinerary class and def operand index. + /// pair of def and use. /// In most cases, the static scheduling itinerary was enough to determine the /// operand latency. But it may not be possible for instructions with variable /// number of defs / uses. - virtual - int getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, unsigned UseIdx) const; + virtual int getOperandLatency(const InstrItineraryData *ItinData, + const MachineInstr *DefMI, unsigned DefIdx, + const MachineInstr *UseMI, unsigned UseIdx) const; + + virtual int getOperandLatency(const InstrItineraryData *ItinData, + SDNode *DefNode, unsigned DefIdx, + SDNode *UseNode, unsigned UseIdx) const; + + /// getInstrLatency - Compute the instruction latency of a given instruction. + /// If the instruction has higher cost when predicated, it's returned via + /// PredCost. + virtual int getInstrLatency(const InstrItineraryData *ItinData, + const MachineInstr *MI, + unsigned *PredCost = 0) const; - virtual - int getOperandLatency(const InstrItineraryData *ItinData, - SDNode *DefNode, unsigned DefIdx, - SDNode *UseNode, unsigned UseIdx) const; + virtual int getInstrLatency(const InstrItineraryData *ItinData, + SDNode *Node) const; /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' /// and an use in the current loop, return true if the target considered Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Nov 2 19:45:17 2010 @@ -93,7 +93,8 @@ /// ClobbersPred - True if BB could modify predicates (e.g. has /// cmp, call, etc.) /// NonPredSize - Number of non-predicated instructions. - /// ExtraCost - Extra cost for microcoded instructions. + /// ExtraCost - Extra cost for multi-cycle instructions. + /// ExtraCost2 - Some instructions are slower when predicated /// BB - Corresponding MachineBasicBlock. /// TrueBB / FalseBB- See AnalyzeBranch(). /// BrCond - Conditions for end of block conditional branches. @@ -110,6 +111,7 @@ bool ClobbersPred : 1; unsigned NonPredSize; unsigned ExtraCost; + unsigned ExtraCost2; MachineBasicBlock *BB; MachineBasicBlock *TrueBB; MachineBasicBlock *FalseBB; @@ -119,7 +121,7 @@ IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false), HasFallThrough(false), IsUnpredicable(false), CannotBeCopied(false), ClobbersPred(false), NonPredSize(0), - ExtraCost(0), BB(0), TrueBB(0), FalseBB(0) {} + ExtraCost(0), ExtraCost2(0), BB(0), TrueBB(0), FalseBB(0) {} }; /// IfcvtToken - Record information about pending if-conversions to attempt: @@ -203,17 +205,20 @@ bool IgnoreBr = false); void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true); - bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Size, + bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, + unsigned Cycle, unsigned Extra, float Prediction, float Confidence) const { - return Size > 0 && TII->isProfitableToIfCvt(BB, Size, - Prediction, Confidence); + return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, + Prediction, Confidence); } - bool MeetIfcvtSizeLimit(MachineBasicBlock &TBB, unsigned TSize, - MachineBasicBlock &FBB, unsigned FSize, + bool MeetIfcvtSizeLimit(MachineBasicBlock &TBB, + unsigned TCycle, unsigned TExtra, + MachineBasicBlock &FBB, + unsigned FCycle, unsigned FExtra, float Prediction, float Confidence) const { - return TSize > 0 && FSize > 0 && - TII->isProfitableToIfCvt(TBB, TSize, FBB, FSize, + return TCycle > 0 && FCycle > 0 && + TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra, Prediction, Confidence); } @@ -649,6 +654,7 @@ // Then scan all the instructions. BBI.NonPredSize = 0; BBI.ExtraCost = 0; + BBI.ExtraCost2 = 0; BBI.ClobbersPred = false; for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end(); I != E; ++I) { @@ -665,9 +671,12 @@ if (!isCondBr) { if (!isPredicated) { BBI.NonPredSize++; - unsigned NumOps = TII->getNumMicroOps(&*I, InstrItins); - if (NumOps > 1) - BBI.ExtraCost += NumOps-1; + unsigned ExtraPredCost = 0; + unsigned NumCycles = TII->getInstrLatency(InstrItins, &*I, + &ExtraPredCost); + if (NumCycles > 1) + BBI.ExtraCost += NumCycles-1; + BBI.ExtraCost2 += ExtraPredCost; } else if (!AlreadyPredicated) { // FIXME: This instruction is already predicated before the // if-conversion pass. It's probably something like a conditional move. @@ -815,9 +824,9 @@ if (CanRevCond && ValidDiamond(TrueBBI, FalseBBI, Dups, Dups2) && MeetIfcvtSizeLimit(*TrueBBI.BB, (TrueBBI.NonPredSize - (Dups + Dups2) + - TrueBBI.ExtraCost), + TrueBBI.ExtraCost), TrueBBI.ExtraCost2, *FalseBBI.BB, (FalseBBI.NonPredSize - (Dups + Dups2) + - FalseBBI.ExtraCost), + FalseBBI.ExtraCost),FalseBBI.ExtraCost2, Prediction, Confidence) && FeasibilityAnalysis(TrueBBI, BBI.BrCond) && FeasibilityAnalysis(FalseBBI, RevCond)) { @@ -836,7 +845,7 @@ if (ValidTriangle(TrueBBI, FalseBBI, false, Dups, Prediction, Confidence) && MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost, - Prediction, Confidence) && + TrueBBI.ExtraCost2, Prediction, Confidence) && FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) { // Triangle: // EBB @@ -851,7 +860,7 @@ if (ValidTriangle(TrueBBI, FalseBBI, true, Dups, Prediction, Confidence) && MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost, - Prediction, Confidence) && + TrueBBI.ExtraCost2, Prediction, Confidence) && FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) { Tokens.push_back(new IfcvtToken(BBI, ICTriangleRev, TNeedSub, Dups)); Enqueued = true; @@ -859,7 +868,7 @@ if (ValidSimple(TrueBBI, Dups, Prediction, Confidence) && MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost, - Prediction, Confidence) && + TrueBBI.ExtraCost2, Prediction, Confidence) && FeasibilityAnalysis(TrueBBI, BBI.BrCond)) { // Simple (split, no rejoin): // EBB @@ -878,7 +887,7 @@ 1.0-Prediction, Confidence) && MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize + FalseBBI.ExtraCost, - 1.0-Prediction, Confidence) && + FalseBBI.ExtraCost2, 1.0-Prediction, Confidence) && FeasibilityAnalysis(FalseBBI, RevCond, true)) { Tokens.push_back(new IfcvtToken(BBI, ICTriangleFalse, FNeedSub, Dups)); Enqueued = true; @@ -888,7 +897,7 @@ 1.0-Prediction, Confidence) && MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize + FalseBBI.ExtraCost, - 1.0-Prediction, Confidence) && + FalseBBI.ExtraCost2, 1.0-Prediction, Confidence) && FeasibilityAnalysis(FalseBBI, RevCond, true, true)) { Tokens.push_back(new IfcvtToken(BBI, ICTriangleFRev, FNeedSub, Dups)); Enqueued = true; @@ -897,7 +906,7 @@ if (ValidSimple(FalseBBI, Dups, 1.0-Prediction, Confidence) && MeetIfcvtSizeLimit(*FalseBBI.BB, FalseBBI.NonPredSize + FalseBBI.ExtraCost, - 1.0-Prediction, Confidence) && + FalseBBI.ExtraCost2, 1.0-Prediction, Confidence) && FeasibilityAnalysis(FalseBBI, RevCond)) { Tokens.push_back(new IfcvtToken(BBI, ICSimpleFalse, FNeedSub, Dups)); Enqueued = true; @@ -1427,9 +1436,11 @@ MachineInstr *MI = MF.CloneMachineInstr(I); ToBBI.BB->insert(ToBBI.BB->end(), MI); ToBBI.NonPredSize++; - unsigned NumOps = TII->getNumMicroOps(MI, InstrItins); - if (NumOps > 1) - ToBBI.ExtraCost += NumOps-1; + unsigned ExtraPredCost = 0; + unsigned NumCycles = TII->getInstrLatency(InstrItins, &*I, &ExtraPredCost); + if (NumCycles > 1) + ToBBI.ExtraCost += NumCycles-1; + ToBBI.ExtraCost2 += ExtraPredCost; if (!TII->isPredicated(I) && !MI->isDebugValue()) { if (!TII->PredicateInstruction(MI, Cond)) { @@ -1504,8 +1515,10 @@ ToBBI.NonPredSize += FromBBI.NonPredSize; ToBBI.ExtraCost += FromBBI.ExtraCost; + ToBBI.ExtraCost2 += FromBBI.ExtraCost2; FromBBI.NonPredSize = 0; FromBBI.ExtraCost = 0; + FromBBI.ExtraCost2 = 0; ToBBI.ClobbersPred |= FromBBI.ClobbersPred; ToBBI.HasFallThrough = FromBBI.HasFallThrough; Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Nov 2 19:45:17 2010 @@ -238,6 +238,8 @@ "Cannot schedule terminators or labels!"); // Create the SUnit for this MI. SUnit *SU = NewSUnit(MI); + SU->isCall = TID.isCall(); + SU->isCommutable = TID.isCommutable(); // Assign the Latency field of SU using target-provided information. if (UnitLatencies) @@ -564,9 +566,9 @@ // extra time. if (SU->getInstr()->getDesc().mayLoad()) SU->Latency += 2; - } else - SU->Latency = - InstrItins->getStageLatency(SU->getInstr()->getDesc().getSchedClass()); + } else { + SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr()); + } } void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 2 19:45:17 2010 @@ -1589,6 +1589,10 @@ } bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{ + if (left->isCall || right->isCall) + // No way to compute latency of calls. + return BURRSort(left, right, SPQ); + bool LHigh = SPQ->HighRegPressure(left); bool RHigh = SPQ->HighRegPressure(right); // Avoid causing spills. If register pressure is high, schedule for @@ -1648,6 +1652,10 @@ bool ilp_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { + if (left->isCall || right->isCall) + // No way to compute latency of calls. + return BURRSort(left, right, SPQ); + bool LHigh = SPQ->HighRegPressure(left); bool RHigh = SPQ->HighRegPressure(right); // Avoid causing spills. If register pressure is high, schedule for Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Nov 2 19:45:17 2010 @@ -72,6 +72,7 @@ SUnit *SU = NewSUnit(Old->getNode()); SU->OrigNode = Old->OrigNode; SU->Latency = Old->Latency; + SU->isCall = Old->isCall; SU->isTwoAddress = Old->isTwoAddress; SU->isCommutable = Old->isCommutable; SU->hasPhysRegDefs = Old->hasPhysRegDefs; @@ -300,6 +301,8 @@ N = N->getOperand(N->getNumOperands()-1).getNode(); assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NodeSUnit->NodeNum); + if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) + NodeSUnit->isCall = true; } // Scan down to find any flagged succs. @@ -316,6 +319,8 @@ assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NodeSUnit->NodeNum); N = *UI; + if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) + NodeSUnit->isCall = true; break; } if (!HasFlagUse) break; @@ -438,10 +443,8 @@ // all nodes flagged together into this SUnit. SU->Latency = 0; for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) - if (N->isMachineOpcode()) { - SU->Latency += InstrItins-> - getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass()); - } + if (N->isMachineOpcode()) + SU->Latency += TII->getInstrLatency(InstrItins, N); } void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use, Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 2 19:45:17 2010 @@ -40,10 +40,6 @@ EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); -static cl::opt -OldARMIfCvt("old-arm-ifcvt", cl::Hidden, - cl::desc("Use old-style ARM if-conversion heuristics")); - ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), Subtarget(STI) { @@ -1205,53 +1201,36 @@ } bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, - unsigned NumInstrs, + unsigned NumCyles, + unsigned ExtraPredCycles, float Probability, float Confidence) const { - if (!NumInstrs) + if (!NumCyles) return false; - // Use old-style heuristics - if (OldARMIfCvt) { - if (Subtarget.getCPUString() == "generic") - // Generic (and overly aggressive) if-conversion limits for testing. - return NumInstrs <= 10; - if (Subtarget.hasV7Ops()) - return NumInstrs <= 3; - return NumInstrs <= 2; - } - // Attempt to estimate the relative costs of predication versus branching. - float UnpredCost = Probability * NumInstrs; + float UnpredCost = Probability * NumCyles; UnpredCost += 1.0; // The branch itself UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); - float PredCost = NumInstrs; - - return PredCost < UnpredCost; - + return (float)(NumCyles + ExtraPredCycles) < UnpredCost; } bool ARMBaseInstrInfo:: -isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, - MachineBasicBlock &FMBB, unsigned NumF, +isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned TCycles, unsigned TExtra, + MachineBasicBlock &FMBB, + unsigned FCycles, unsigned FExtra, float Probability, float Confidence) const { - // Use old-style if-conversion heuristics - if (OldARMIfCvt) { - return NumT && NumF && NumT <= 2 && NumF <= 2; - } - - if (!NumT || !NumF) + if (!TCycles || !FCycles) return false; // Attempt to estimate the relative costs of predication versus branching. - float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF; + float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles; UnpredCost += 1.0; // The branch itself UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty(); - float PredCost = NumT + NumF; - - return PredCost < UnpredCost; + return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost; } /// getInstrPredicate - If instruction is predicated, returns its predicate @@ -1591,8 +1570,8 @@ } unsigned -ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData *ItinData) const { +ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, + const MachineInstr *MI) const { if (!ItinData || ItinData->isEmpty()) return 1; @@ -1649,9 +1628,14 @@ case ARM::t2STM_UPD: { unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; if (Subtarget.isCortexA8()) { - // 4 registers would be issued: 1, 2, 1. - // 5 registers would be issued: 1, 2, 2. - return 1 + (NumRegs / 2); + if (NumRegs < 4) + return 2; + // 4 registers would be issued: 2, 2. + // 5 registers would be issued: 2, 2, 1. + UOps = (NumRegs / 2); + if (NumRegs % 2) + ++UOps; + return UOps; } else if (Subtarget.isCortexA9()) { UOps = (NumRegs / 2); // If there are odd number of registers or if it's not 64-bit aligned, @@ -2025,6 +2009,46 @@ return Latency; } +int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, + const MachineInstr *MI, + unsigned *PredCost) const { + if (MI->isCopyLike() || MI->isInsertSubreg() || + MI->isRegSequence() || MI->isImplicitDef()) + return 1; + + if (!ItinData || ItinData->isEmpty()) + return 1; + + const TargetInstrDesc &TID = MI->getDesc(); + unsigned Class = TID.getSchedClass(); + unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; + if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR)) + // When predicated, CPSR is an additional source operand for CPSR updating + // instructions, this apparently increases their latencies. + *PredCost = 1; + if (UOps) + return ItinData->getStageLatency(Class); + return getNumMicroOps(ItinData, MI); +} + +int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, + SDNode *Node) const { + if (!Node->isMachineOpcode()) + return 1; + + if (!ItinData || ItinData->isEmpty()) + return 1; + + unsigned Opcode = Node->getMachineOpcode(); + switch (Opcode) { + default: + return ItinData->getStageLatency(get(Opcode).getSchedClass()); + case ARM::VLDMQ: + case ARM::VSTMQ: + return 2; + } +} + bool ARMBaseInstrInfo:: hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Nov 2 19:45:17 2010 @@ -318,18 +318,20 @@ const MachineFunction &MF) const; virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, - unsigned NumInstrs, + unsigned NumCyles, unsigned ExtraPredCycles, float Prob, float Confidence) const; - virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT, - MachineBasicBlock &FMBB,unsigned NumF, + virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned NumT, unsigned ExtraT, + MachineBasicBlock &FMBB, + unsigned NumF, unsigned ExtraF, float Probability, float Confidence) const; virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, - unsigned NumInstrs, + unsigned NumCyles, float Probability, float Confidence) const { - return NumInstrs == 1; + return NumCyles == 1; } /// AnalyzeCompare - For a comparison instruction, return the source register @@ -345,8 +347,8 @@ const MachineRegisterInfo *MRI, MachineBasicBlock::iterator &MII) const; - virtual unsigned getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData *ItinData) const; + virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, + const MachineInstr *MI) const; virtual int getOperandLatency(const InstrItineraryData *ItinData, @@ -379,6 +381,12 @@ const TargetInstrDesc &UseTID, unsigned UseIdx, unsigned UseAlign) const; + int getInstrLatency(const InstrItineraryData *ItinData, + const MachineInstr *MI, unsigned *PredCost = 0) const; + + int getInstrLatency(const InstrItineraryData *ItinData, + SDNode *Node) const; + bool hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Nov 2 19:45:17 2010 @@ -42,33 +42,6 @@ return 0; } -bool Thumb2InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, - unsigned NumInstrs, - float Prediction, - float Confidence) const { - if (!OldT2IfCvt) - return ARMBaseInstrInfo::isProfitableToIfCvt(MBB, NumInstrs, - Prediction, Confidence); - return NumInstrs && NumInstrs <= 3; -} - -bool Thumb2InstrInfo:: -isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, - MachineBasicBlock &FMBB, unsigned NumF, - float Prediction, float Confidence) const { - if (!OldT2IfCvt) - return ARMBaseInstrInfo::isProfitableToIfCvt(TMBB, NumT, - FMBB, NumF, - Prediction, Confidence); - - // FIXME: Catch optimization such as: - // r0 = movne - // r0 = moveq - return NumT && NumF && - NumT <= 3 && NumF <= 3; -} - - void Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const { Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h Tue Nov 2 19:45:17 2010 @@ -38,12 +38,6 @@ bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const; - bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, - float Prediction, float Confidence) const; - bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, - MachineBasicBlock &FMBB, unsigned NumFInstrs, - float Prediction, float Confidence) const; - void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Tue Nov 2 19:45:17 2010 @@ -50,8 +50,8 @@ } unsigned -TargetInstrInfo::getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData *ItinData) const { +TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, + const MachineInstr *MI) const { if (!ItinData || ItinData->isEmpty()) return 1; @@ -94,6 +94,26 @@ return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); } +int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, + const MachineInstr *MI, + unsigned *PredCost) const { + if (!ItinData || ItinData->isEmpty()) + return 1; + + return ItinData->getStageLatency(MI->getDesc().getSchedClass()); +} + +int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, + SDNode *N) const { + if (!ItinData || ItinData->isEmpty()) + return 1; + + if (!N->isMachineOpcode()) + return 1; + + return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); +} + bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const { Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Tue Nov 2 19:45:17 2010 @@ -8,8 +8,9 @@ define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { entry: ; Make sure to use base-updating stores for saving callee-saved registers. +; CHECK: push ; CHECK-NOT: sub sp -; CHECK: vpush +; CHECK: push %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] br label %cond_next489 Modified: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt10.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Tue Nov 2 19:45:17 2010 @@ -4,27 +4,40 @@ ; micro-coded and would have long issue latency even if predicated on ; false predicate. -%0 = type { float, float, float, float } -%pln = type { %vec, float } -%vec = type { [4 x float] } - -define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) { -; CHECK: aaa: -; CHECK: vldr.32 -; CHECK-NOT: vldrne -; CHECK-NOT: vpopne -; CHECK-NOT: popne -; CHECK: vpop -; CHECK: pop +define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind { entry: - br i1 undef, label %bb81, label %bb48 +; CHECK: t: +; CHECK: vpop {d8} +; CHECK-NOT: vpopne +; CHECK: ldmia sp!, {r7, pc} +; CHECK: vpop {d8} +; CHECK: ldmia sp!, {r7, pc} + br i1 undef, label %if.else, label %if.then -bb48: ; preds = %entry - %0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0] - ret float 0.000000e+00 +if.then: ; preds = %entry + %mul73 = fmul double undef, 0.000000e+00 + %sub76 = fsub double %mul73, undef + store double %sub76, double* undef, align 4 + %call88 = tail call double @cos(double 0.000000e+00) nounwind + %mul89 = fmul double undef, %call88 + %sub92 = fsub double %mul89, undef + store double %sub92, double* undef, align 4 + ret void -bb81: ; preds = %entry - ret float 0.000000e+00 +if.else: ; preds = %entry + %tmp101 = tail call double @llvm.pow.f64(double undef, double 0x3FD5555555555555) + %add112 = fadd double %tmp101, undef + %mul118 = fmul double %add112, undef + store double 0.000000e+00, double* %x, align 4 + ret void } -declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind +declare double @acos(double) + +declare double @sqrt(double) readnone + +declare double @cos(double) readnone + +declare double @fabs(double) + +declare double @llvm.pow.f64(double, double) nounwind readonly Added: llvm/trunk/test/CodeGen/ARM/ifcvt11.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt11.ll?rev=118135&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt11.ll (added) +++ llvm/trunk/test/CodeGen/ARM/ifcvt11.ll Tue Nov 2 19:45:17 2010 @@ -0,0 +1,59 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; rdar://8598427 +; Adjust if-converter heuristics to avoid predicating vmrs which can cause +; significant regression. + +%struct.xyz_t = type { double, double, double } + +define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline { +; CHECK: effie: +entry: + %0 = icmp sgt i32 %tsets, 0 + br i1 %0, label %bb.nph, label %bb6 + +bb.nph: ; preds = %entry + %1 = add nsw i32 %b, %a + %2 = add nsw i32 %1, %c + br label %bb + +bb: ; preds = %bb4, %bb.nph +; CHECK: vcmpe.f64 +; CHECK: vmrs apsr_nzcv, fpscr + %r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ] + %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ] + %scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0 + %scevgep11 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 1 + %3 = load double* %scevgep10, align 4 + %4 = load double* %scevgep11, align 4 + %5 = fcmp uge double %3, %4 + br i1 %5, label %bb3, label %bb1 + +bb1: ; preds = %bb +; CHECK-NOT: it +; CHECK-NOT: vcmpemi +; CHECK-NOT: vmrsmi +; CHECK: vcmpe.f64 +; CHECK: vmrs apsr_nzcv, fpscr + %scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2 + %6 = load double* %scevgep12, align 4 + %7 = fcmp uge double %3, %6 + br i1 %7, label %bb3, label %bb2 + +bb2: ; preds = %bb1 + %8 = add nsw i32 %2, %r.19 + br label %bb4 + +bb3: ; preds = %bb1, %bb + %9 = add nsw i32 %r.19, 1 + br label %bb4 + +bb4: ; preds = %bb3, %bb2 + %r.0 = phi i32 [ %9, %bb3 ], [ %8, %bb2 ] + %10 = add nsw i32 %n.08, 1 + %exitcond = icmp eq i32 %10, %tsets + br i1 %exitcond, label %bb6, label %bb + +bb6: ; preds = %bb4, %entry + %r.1.lcssa = phi i32 [ 0, %entry ], [ %r.0, %bb4 ] + ret i32 %r.1.lcssa +} Modified: llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Tue Nov 2 19:45:17 2010 @@ -4,14 +4,14 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-128] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-96] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-64] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-32] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #32] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #64] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #96] +; CHECK: vstr.32 s{{.*}}, [lr, #-128] +; CHECK: vstr.32 s{{.*}}, [lr, #-96] +; CHECK: vstr.32 s{{.*}}, [lr, #-64] +; CHECK: vstr.32 s{{.*}}, [lr, #-32] +; CHECK: vstr.32 s{{.*}}, [lr] +; CHECK: vstr.32 s{{.*}}, [lr, #32] +; CHECK: vstr.32 s{{.*}}, [lr, #64] +; CHECK: vstr.32 s{{.*}}, [lr, #96] target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Tue Nov 2 19:45:17 2010 @@ -271,7 +271,6 @@ entry: ; CHECK: t10: ; CHECK: vmov.i32 q9, #0x3F000000 -; CHECK: vmov d0, d17 ; CHECK: vmla.f32 q8, q8, d0[0] %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll?rev=118135&r1=118134&r2=118135&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Tue Nov 2 19:45:17 2010 @@ -23,8 +23,6 @@ %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2] ; Constant pool load followed by add. ; Then clobber the loaded register, not the sum. -; CHECK: vldr.64 -; CHECK: vadd.f64 ; CHECK: vldr.64 [[LDR:d.*]], ; CHECK: LPC0_0: ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] From wdietz2 at illinois.edu Tue Nov 2 19:59:08 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 03 Nov 2010 00:59:08 -0000 Subject: [llvm-commits] [poolalloc] r118136 - in /poolalloc/trunk: lib/DSA/DSGraph.cpp test/dsa/extern/extern_global.ll Message-ID: <20101103005908.4CCDB2A6C12C@llvm.org> Author: wdietz2 Date: Tue Nov 2 19:59:08 2010 New Revision: 118136 URL: http://llvm.org/viewvc/llvm-project?rev=118136&view=rev Log: Mark globals that aren't both iniitalized and constant as incomplete (except when ignoring globals) Don't care about initializer in external, mark all non-internal globals external. Update testcase to reflect that default linkage on global is external. Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp poolalloc/trunk/test/dsa/extern/extern_global.ll Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=118136&r1=118135&r2=118136&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSGraph.cpp Tue Nov 2 19:59:08 2010 @@ -650,12 +650,13 @@ E = AuxFunctionCalls.end(); I != E; ++I) markIncomplete(*I); - // Mark all global nodes as incomplete. - for (DSScalarMap::global_iterator I = ScalarMap.global_begin(), - E = ScalarMap.global_end(); I != E; ++I) - if (const GlobalVariable *GV = dyn_cast(*I)) - if (!GV->isConstant() && (Flags & DSGraph::IgnoreGlobals) == 0) - markIncompleteNode(ScalarMap[GV].getNode()); + // Mark all global nodes as incomplete that aren't initialized and constant. + if ((Flags & DSGraph::IgnoreGlobals) == 0) + for (DSScalarMap::global_iterator I = ScalarMap.global_begin(), + E = ScalarMap.global_end(); I != E; ++I) + if (const GlobalVariable *GV = dyn_cast(*I)) + if (!(GV->hasInitializer() && GV->isConstant())) + markIncompleteNode(ScalarMap[GV].getNode()); // Mark any node with the VAStart flag as incomplete. if (Flags & DSGraph::MarkVAStart) { @@ -790,11 +791,8 @@ E = ScalarMap.global_end(); I != E; ++I) { if (const GlobalVariable *GV = dyn_cast(*I)) { // If the global is external... mark it as such! - // FIXME: It's unclear to me that a global we initialize - // can't be externally visible. For now following original - // behavior and marking external. DSNode * N = ScalarMap[GV].getNode(); - if (!GV->hasInitializer() || N->isExternalNode()) + if (!GV->hasInternalLinkage() || N->isExternalNode()) markExternalNode(N, processedNodes); } } Modified: poolalloc/trunk/test/dsa/extern/extern_global.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/extern/extern_global.ll?rev=118136&r1=118135&r2=118136&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/extern/extern_global.ll (original) +++ poolalloc/trunk/test/dsa/extern/extern_global.ll Tue Nov 2 19:59:08 2010 @@ -3,6 +3,8 @@ ; Externally visible globals should be marked external, but complete ;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalInt+GE-I +; (When linkage is not specified, it is external) +;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal+GE-I ; Externally visible global and what it points to should be complete/external ;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr+GE-I ;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalIntPtr:0+GE-I @@ -13,7 +15,6 @@ ;RUN: dsaopt %s -dsa-td -analyze -verify-flags globalStructWithPointers:8:8+E-I ;RUN: dsaopt %s -dsa-td -analyze -verify-flags main:s+ES-I ; Globals that aren't marked 'external' shouldn't be incomplete (or external) -;RUN: dsaopt %s -dsa-td -analyze -verify-flags normalGlobal+G-IE ;RUN: dsaopt %s -dsa-td -analyze -verify-flags internalGlobal+G-IE ; Check some edges of the graph ;RUN: dsaopt %s -dsa-td -analyze -check-same-node=normalGlobal:0,globalIntPtr From grosbach at apple.com Tue Nov 2 20:01:43 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 01:01:43 -0000 Subject: [llvm-commits] [llvm] r118137 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h utils/TableGen/EDEmitter.cpp Message-ID: <20101103010143.9B44B2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 2 20:01:43 2010 New Revision: 118137 URL: http://llvm.org/viewvc/llvm-project?rev=118137&view=rev Log: Break ARM addrmode4 (load/store multiple base address) into its constituent parts. Represent the operation mode as an optional operand instead. rdar://8614429 Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Nov 2 20:01:43 2010 @@ -113,7 +113,6 @@ SDValue &Offset, SDValue &Opc); bool SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc); - bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode); bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset); bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align); @@ -718,12 +717,6 @@ return true; } -bool ARMDAGToDAGISel::SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode) { - Addr = N; - Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32); - return true; -} - bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset) { if (N.getOpcode() != ISD::ADD) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 20:01:43 2010 @@ -444,12 +444,10 @@ let MIOperandInfo = (ops GPR, i32imm); } -// addrmode4 := reg, +// ldstm_mode := {ia, ib, da, db} // -def addrmode4 : Operand, - ComplexPattern { - let PrintMethod = "printAddrMode4Operand"; - let MIOperandInfo = (ops GPR:$addr, i32imm); +def ldstm_mode : OptionalDefOperand { + let PrintMethod = "printLdStmModeOperand"; } def ARMMemMode5AsmOperand : AsmOperandClass { @@ -1171,11 +1169,11 @@ // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in - def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, + def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, - "ldm${addr:submode}${p}\t$addr!, $dsts", - "$addr.addr = $wb", []>; + "ldm${mode}${p}\t$Rn!, $dsts", + "$Rn = $wb", []>; // On non-Darwin platforms R9 is callee-saved. let isCall = 1, @@ -1423,30 +1421,30 @@ // Store Return State is a system instruction -- for disassembly only let isCodeGenOnly = 1 in { // FIXME: This should not use submode! -def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), - NoItinerary, "srs${addr:submode}\tsp!, $mode", +def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode), + NoItinerary, "srs${amode}\tsp!, $mode", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{22-20} = 0b110; // W = 1 } -def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), - NoItinerary, "srs${addr:submode}\tsp, $mode", +def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode), + NoItinerary, "srs${amode}\tsp, $mode", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{22-20} = 0b100; // W = 0 } // Return From Exception is a system instruction -- for disassembly only -def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), - NoItinerary, "rfe${addr:submode}\t$base!", +def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base), + NoItinerary, "rfe${amode}\t$base!", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{22-20} = 0b011; // W = 1 } -def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), - NoItinerary, "rfe${addr:submode}\t$base", +def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base), + NoItinerary, "rfe${amode}\t$base", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{22-20} = 0b001; // W = 0 @@ -1693,30 +1691,30 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in { -def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, +def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, LdStMulFrm, IIC_iLoad_m, - "ldm${addr:submode}${p}\t$addr, $dsts", "", []>; + "ldm${amode}${p}\t$Rn, $dsts", "", []>; -def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, - "ldm${addr:submode}${p}\t$addr!, $dsts", - "$addr.addr = $wb", []>; + "ldm${amode}${p}\t$Rn!, $dsts", + "$Rn = $wb", []>; } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, isCodeGenOnly = 1 in { -def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, +def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeNone, LdStMulFrm, IIC_iStore_m, - "stm${addr:submode}${p}\t$addr, $srcs", "", []>; + "stm${amode}${p}\t$Rn, $srcs", "", []>; -def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iStore_mu, - "stm${addr:submode}${p}\t$addr!, $srcs", - "$addr.addr = $wb", []>; + "stm${amode}${p}\t$Rn!, $srcs", + "$Rn = $wb", []>; } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 2 20:01:43 2010 @@ -132,14 +132,16 @@ // Use VLDM to load a Q register as a D register pair. // This is a pseudo instruction that is expanded to VLDMD after reg alloc. def VLDMQ - : PseudoVFPLdStM<(outs QPR:$dst), (ins addrmode4:$addr), IIC_fpLoad_m, "", - [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>; + : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn, ldstm_mode:$mode), + IIC_fpLoad_m, "", + [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>; // Use VSTM to store a Q register as a D register pair. // This is a pseudo instruction that is expanded to VSTMD after reg alloc. def VSTMQ - : PseudoVFPLdStM<(outs), (ins QPR:$src, addrmode4:$addr), IIC_fpStore_m, "", - [(store (v2f64 QPR:$src), addrmode4:$addr)]>; + : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn, ldstm_mode:$mode), + IIC_fpStore_m, "", + [(store (v2f64 QPR:$src), GPR:$Rn)]>; let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Nov 2 20:01:43 2010 @@ -540,26 +540,29 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in { def tLDM : T1I<(outs), - (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), + (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, + variable_ops), IIC_iLoad_m, - "ldm${addr:submode}${p}\t$addr, $dsts", []>, + "ldm${amode}${p}\t$Rn, $dsts", []>, T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 def tLDM_UPD : T1It<(outs tGPR:$wb), - (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), + (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, + variable_ops), IIC_iLoad_m, - "ldm${addr:submode}${p}\t$addr!, $dsts", - "$addr.addr = $wb", []>, + "ldm${amode}${p}\t$Rn!, $dsts", + "$Rn = $wb", []>, T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 } // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, isCodeGenOnly = 1 in def tSTM_UPD : T1It<(outs tGPR:$wb), - (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), + (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, + variable_ops), IIC_iStore_mu, - "stm${addr:submode}${p}\t$addr!, $srcs", - "$addr.addr = $wb", []>, + "stm${amode}${p}\t$Rn!, $srcs", + "$Rn = $wb", []>, T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Nov 2 20:01:43 2010 @@ -1246,9 +1246,9 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in { -def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, +def t2LDM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IIC_iLoad_m, - "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> { + "ldm${amode}${p}.w\t$Rn, $dsts", []> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' @@ -1257,11 +1257,11 @@ let Inst{20} = 1; // Load } -def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IIC_iLoad_mu, - "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", - "$addr.addr = $wb", []> { + "ldm${amode}${p}.w\t$Rn!, $dsts", + "$Rn = $wb", []> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' @@ -1273,9 +1273,9 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, isCodeGenOnly = 1 in { -def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, +def t2STM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IIC_iStore_m, - "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> { + "stm${amode}${p}.w\t$Rn, $srcs", []> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' @@ -1284,11 +1284,11 @@ let Inst{20} = 0; // Store } -def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IIC_iStore_m, - "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs", - "$addr.addr = $wb", []> { + "stm${amode}${p}.w\t$Rn!, $srcs", + "$Rn = $wb", []> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' @@ -2437,11 +2437,11 @@ // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in - def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, - reglist:$dsts, variable_ops), + def t2LDM_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, + reglist:$dsts, variable_ops), IIC_iLoad_mBr, - "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", - "$addr.addr = $wb", []> { + "ldm${amode}${p}.w\t$Rn!, $dsts", + "$Rn = $wb", []> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 20:01:43 2010 @@ -85,62 +85,66 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in { -def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, - variable_ops), IndexModeNone, IIC_fpLoad_m, - "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { +def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, + reglist:$dsts, variable_ops), + IndexModeNone, IIC_fpLoad_m, + "vldm${amode}${p}\t$Rn, $dsts", "", []> { let Inst{20} = 1; } -def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, - variable_ops), IndexModeNone, IIC_fpLoad_m, - "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { +def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, + reglist:$dsts, variable_ops), + IndexModeNone, IIC_fpLoad_m, + "vldm${amode}${p}\t$Rn, $dsts", "", []> { let Inst{20} = 1; } -def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, IIC_fpLoad_mu, - "vldm${addr:submode}${p}\t$addr!, $dsts", - "$addr.addr = $wb", []> { + "vldm${amode}${p}\t$Rn!, $dsts", + "$Rn = $wb", []> { let Inst{20} = 1; } -def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, IIC_fpLoad_mu, - "vldm${addr:submode}${p}\t$addr!, $dsts", - "$addr.addr = $wb", []> { + "vldm${amode}${p}\t$Rn!, $dsts", + "$Rn = $wb", []> { let Inst{20} = 1; } } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, isCodeGenOnly = 1 in { -def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, - variable_ops), IndexModeNone, IIC_fpStore_m, - "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { +def VSTMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, + reglist:$srcs, variable_ops), + IndexModeNone, IIC_fpStore_m, + "vstm${amode}${p}\t$Rn, $srcs", "", []> { let Inst{20} = 0; } -def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, - variable_ops), IndexModeNone, IIC_fpStore_m, - "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { +def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, + reglist:$srcs, variable_ops), IndexModeNone, + IIC_fpStore_m, + "vstm${amode}${p}\t$Rn, $srcs", "", []> { let Inst{20} = 0; } -def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, IIC_fpStore_mu, - "vstm${addr:submode}${p}\t$addr!, $srcs", - "$addr.addr = $wb", []> { + "vstm${amode}${p}\t$Rn!, $srcs", + "$Rn = $wb", []> { let Inst{20} = 0; } -def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, IIC_fpStore_mu, - "vstm${addr:submode}${p}\t$addr!, $srcs", - "$addr.addr = $wb", []> { + "vstm${amode}${p}\t$Rn!, $srcs", + "$Rn = $wb", []> { let Inst{20} = 0; } } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Nov 2 20:01:43 2010 @@ -691,8 +691,8 @@ // MSR/MSRsys: Rm mask=Inst{19-16} // BXJ: Rm // MSRi/MSRsysi: so_imm -// SRSW/SRS: addrmode4:$addr mode_imm -// RFEW/RFE: addrmode4:$addr Rn +// SRSW/SRS: ldstm_mode:$amode mode_imm +// RFEW/RFE: ldstm_mode:$amode Rn static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -742,13 +742,8 @@ NumOpsAdded = 2; return true; } - // SRSW and SRS requires addrmode4:$addr for ${addr:submode}, followed by the - // mode immediate (Inst{4-0}). if (Opcode == ARM::SRSW || Opcode == ARM::SRS || Opcode == ARM::RFEW || Opcode == ARM::RFE) { - // ARMInstPrinter::printAddrMode4Operand() prints special mode string - // if the base register is SP; so don't set ARM::SP. - MI.addOperand(MCOperand::CreateReg(0)); ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn)); MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode))); Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Nov 2 20:01:43 2010 @@ -290,21 +290,12 @@ << ImmOffs; } - -void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, +void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier) { - const MCOperand &MO2 = MI->getOperand(OpNum+1); - ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); - if (Modifier && strcmp(Modifier, "submode") == 0) { - O << ARM_AM::getAMSubModeStr(Mode); - } else if (Modifier && strcmp(Modifier, "wide") == 0) { - ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); - if (Mode == ARM_AM::ia) - O << ".w"; - } else { - printOperand(MI, OpNum, O); - } + ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) + .getImm()); + O << ARM_AM::getAMSubModeStr(Mode); } void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Nov 2 20:01:43 2010 @@ -46,7 +46,7 @@ void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, + void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=118137&r1=118136&r2=118137&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Nov 2 20:01:43 2010 @@ -599,7 +599,7 @@ MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I - MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I + MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I @@ -815,7 +815,7 @@ operandTypes.addEntry("kOperandTypeARMAddrMode2Offset"); operandTypes.addEntry("kOperandTypeARMAddrMode3"); operandTypes.addEntry("kOperandTypeARMAddrMode3Offset"); - operandTypes.addEntry("kOperandTypeARMAddrMode4"); + operandTypes.addEntry("kOperandTypeARMLdStmMode"); operandTypes.addEntry("kOperandTypeARMAddrMode5"); operandTypes.addEntry("kOperandTypeARMAddrMode6"); operandTypes.addEntry("kOperandTypeARMAddrMode6Offset"); From grosbach at apple.com Tue Nov 2 20:07:48 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 01:07:48 -0000 Subject: [llvm-commits] [llvm] r118139 - in /llvm/trunk/lib/Target/ARM/InstPrinter: ARMInstPrinter.cpp ARMInstPrinter.h Message-ID: <20101103010749.02D772A6C12C@llvm.org> Author: grosbach Date: Tue Nov 2 20:07:48 2010 New Revision: 118139 URL: http://llvm.org/viewvc/llvm-project?rev=118139&view=rev Log: Remove unused function. Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118139&r1=118138&r2=118139&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Nov 2 20:07:48 2010 @@ -475,21 +475,11 @@ } } - - -void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O, - const char *Modifier) { - // FIXME: remove this. - abort(); -} - void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } - void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) { llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=118139&r1=118138&r2=118139&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Nov 2 20:07:48 2010 @@ -100,8 +100,6 @@ void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printCPInstOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, - const char *Modifier); // The jump table instructions have custom handling in ARMAsmPrinter // to output the jump table. Nothing further is necessary here. void printJTBlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} From grosbach at apple.com Tue Nov 2 20:11:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 01:11:15 -0000 Subject: [llvm-commits] [llvm] r118140 - in /llvm/trunk/lib/Target/ARM/InstPrinter: ARMInstPrinter.cpp ARMInstPrinter.h Message-ID: <20101103011115.6A4D92A6C12C@llvm.org> Author: grosbach Date: Tue Nov 2 20:11:15 2010 New Revision: 118140 URL: http://llvm.org/viewvc/llvm-project?rev=118140&view=rev Log: Remove the no longer used 'Modifier' optional operand to the ARM printOperand() asm printer helper functions. rdar://8425198 Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118140&r1=118139&r2=118140&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Nov 2 20:11:15 2010 @@ -116,16 +116,14 @@ } void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, const char *Modifier) { + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { unsigned Reg = Op.getReg(); O << getRegisterName(Reg); } else if (Op.isImm()) { - assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); O << '#' << Op.getImm(); } else { - assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); assert(Op.isExpr() && "unknown operand kind in printOperand"); O << *Op.getExpr(); } @@ -291,16 +289,14 @@ } void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O, - const char *Modifier) { + raw_ostream &O) { ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) .getImm()); O << ARM_AM::getAMSubModeStr(Mode); } void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, - raw_ostream &O, - const char *Modifier) { + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -343,8 +339,7 @@ } void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O, - const char *Modifier) { + raw_ostream &O) { // All instructions using addrmodepc are pseudos and should have been // handled explicitly in printInstructionThroughMCStreamer(). If one got // here, it wasn't, so something's wrong. Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=118140&r1=118139&r2=118140&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Nov 2 20:11:15 2010 @@ -33,8 +33,7 @@ static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = 0); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); @@ -46,15 +45,12 @@ void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, - const char *Modifier = 0); - void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, - const char *Modifier = 0); + void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, - const char *Modifier = 0); + void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); From grosbach at apple.com Tue Nov 2 20:26:52 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 2 Nov 2010 18:26:52 -0700 Subject: [llvm-commits] [llvm] r118094 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/simple-fp-encoding.s In-Reply-To: References: <20101102223146.47EA52A6C12C@llvm.org> <39F60132-FCF3-4D15-A988-09A6A5484874@apple.com> Message-ID: <68FDE696-8AC9-409F-B571-84CEF0D6AFB6@apple.com> Hey Bill, Hmmm.... So you're looking to reuse the encoder method for other complex operands that need the same basic information (register/offset pair)? That makes a lot more sense and I don't see any reason why that's a bad thing (quite the opposite). Where we need to be careful is in re-using the operand definitions themselves, as those have the matchers, printers, and such that will be different. Sounds like we're on the same page there and I was just a bit confused. Thanks! -Jim On Nov 2, 2010, at 4:02 PM, Bill Wendling wrote: > Hi Jim, > > I might not have explained my change very well. I wanted to convert the getAddrModeImm12OpValue into a generic function that gets the register and address information, and encodes that into an i32 to be used by the MC encoding stuff. The immediate isn't necessarily 16-bits in size (though it can be). In fact, for the VLDR stuff it's expecting an 8-bit immediate. > > The reason why I didn't create a getAddrModeImm8OpValue method was because it had the exact same code as getAddrModeImm12OpValue, just that the offsets of the values were different (the U bit was at {8} instead of {12}, etc.). :-) > > I'll be happy to rework this and create an imm8-specific method if that's desirable. It would be easy to refactor the original code to do that. > > -bw > > On Nov 2, 2010, at 3:51 PM, Jim Grosbach wrote: > >> Hi Bill, >> >> We should add a new addrmode_i16 for this rather than re-using the current one. How many bits are legal is part of the semantics, and is enforced by the selection dag stuff (SelectAddrModeImm12() in this case). For a parallel example, see the Thumb2 t2addrmode_imm12 and t2addrmode_imm8 modes in ARMInstrThumb2.td. >> >> -Jim >> >> On Nov 2, 2010, at 3:31 PM, Bill Wendling wrote: >> >>> Author: void >>> Date: Tue Nov 2 17:31:46 2010 >>> New Revision: 118094 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=118094&view=rev >>> Log: >>> Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work >>> with immediates up to 16-bits in size. The same logic is applied to other LDR >>> encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in >>> VLDR's case). Removing the "12" allows it to be more generic. >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp >>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >>> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td >>> llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >>> llvm/trunk/test/MC/ARM/arm_instructions.s >>> llvm/trunk/test/MC/ARM/simple-fp-encoding.s >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 17:31:46 2010 >>> @@ -177,26 +177,27 @@ >>> const { return 0; } >>> unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, >>> unsigned Op) const { return 0; } >>> - unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) >>> - const { >>> - // {17-13} = reg >>> - // {12} = (U)nsigned (add == '1', sub == '0') >>> - // {11-0} = imm12 >>> - const MachineOperand &MO = MI.getOperand(Op); >>> - const MachineOperand &MO1 = MI.getOperand(Op + 1); >>> - if (!MO.isReg()) { >>> - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); >>> - return 0; >>> - } >>> - unsigned Reg = getARMRegisterNumbering(MO.getReg()); >>> - int32_t Imm12 = MO1.getImm(); >>> - uint32_t Binary; >>> - Binary = Imm12 & 0xfff; >>> - if (Imm12 >= 0) >>> - Binary |= (1 << 12); >>> - Binary |= (Reg << 13); >>> - return Binary; >>> + uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const { >>> + // {20-17} = reg >>> + // {16} = (U)nsigned (add == '1', sub == '0') >>> + // {15-0} = imm >>> + const MachineOperand &MO = MI.getOperand(Op); >>> + const MachineOperand &MO1 = MI.getOperand(Op + 1); >>> + if (!MO.isReg()) { >>> + emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); >>> + return 0; >>> } >>> + >>> + unsigned Reg = getARMRegisterNumbering(MO.getReg()); >>> + int32_t Imm = MO1.getImm(); >>> + uint32_t Binary; >>> + Binary = Imm & 0xffff; >>> + if (Imm >= 0) >>> + Binary |= (1 << 16); >>> + >>> + Binary |= (Reg << 17); >>> + return Binary; >>> + } >>> unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) >>> const { return 0; } >>> >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118094&r1=118093&r2=118094&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 17:31:46 2010 >>> @@ -398,7 +398,7 @@ >>> // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other >>> // immediate values are as normal. >>> >>> - string EncoderMethod = "getAddrModeImm12OpValue"; >>> + string EncoderMethod = "getAddrModeImmOpValue"; >>> let PrintMethod = "printAddrModeImm12Operand"; >>> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); >>> } >>> @@ -464,6 +464,7 @@ >>> let PrintMethod = "printAddrMode5Operand"; >>> let MIOperandInfo = (ops GPR:$base, i32imm); >>> let ParserMatchClass = ARMMemMode5AsmOperand; >>> + string EncoderMethod = "getAddrModeImmOpValue"; >>> } >>> >>> // addrmode6 := reg with optional writeback >>> @@ -830,9 +831,9 @@ >>> AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", >>> [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { >>> bits<4> Rt; >>> - bits<17> addr; >>> - let Inst{23} = addr{12}; // U (add = ('U' == 1)) >>> - let Inst{19-16} = addr{16-13}; // Rn >>> + bits<32> addr; >>> + let Inst{23} = addr{16}; // U (add = ('U' == 1)) >>> + let Inst{19-16} = addr{20-17}; // Rn >>> let Inst{15-12} = Rt; >>> let Inst{11-0} = addr{11-0}; // imm12 >>> } >>> @@ -840,9 +841,9 @@ >>> AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", >>> [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { >>> bits<4> Rt; >>> - bits<17> shift; >>> - let Inst{23} = shift{12}; // U (add = ('U' == 1)) >>> - let Inst{19-16} = shift{16-13}; // Rn >>> + bits<32> shift; >>> + let Inst{23} = shift{16}; // U (add = ('U' == 1)) >>> + let Inst{19-16} = shift{20-17}; // Rn >>> let Inst{11-0} = shift{11-0}; >>> } >>> } >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118094&r1=118093&r2=118094&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 17:31:46 2010 >>> @@ -53,18 +53,29 @@ >>> let canFoldAsLoad = 1, isReMaterializable = 1 in { >>> def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), >>> IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", >>> - [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; >>> + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { >>> + // Instruction operands. >>> + bits<5> Dd; >>> + bits<32> addr; >>> + >>> + // Encode instruction operands. >>> + let Inst{23} = addr{16}; // U (add = (U == '1')) >>> + let Inst{22} = Dd{4}; >>> + let Inst{19-16} = addr{20-17}; // Rn >>> + let Inst{15-12} = Dd{3-0}; >>> + let Inst{7-0} = addr{7-0}; // imm8 >>> +} >>> >>> def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), >>> IIC_fpLoad32, "vldr", ".32\t$dst, $addr", >>> [(set SPR:$dst, (load addrmode5:$addr))]>; >>> } // canFoldAsLoad >>> >>> -def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), >>> +def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), >>> IIC_fpStore64, "vstr", ".64\t$src, $addr", >>> [(store (f64 DPR:$src), addrmode5:$addr)]>; >>> >>> -def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), >>> +def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), >>> IIC_fpStore32, "vstr", ".32\t$src, $addr", >>> [(store SPR:$src, addrmode5:$addr)]>; >>> >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:31:46 2010 >>> @@ -49,9 +49,8 @@ >>> /// operand requires relocation, record the relocation and return zero. >>> unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; >>> >>> - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' >>> - /// operand. >>> - unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const; >>> + /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. >>> + uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const; >>> >>> /// getCCOutOpValue - Return encoding of the 's' bit. >>> unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { >>> @@ -170,37 +169,38 @@ >>> return 0; >>> } >>> >>> -/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' >>> -/// operand. >>> -unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, >>> - unsigned OpIdx) const { >>> - // {17-13} = reg >>> - // {12} = (U)nsigned (add == '1', sub == '0') >>> - // {11-0} = imm12 >>> +/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. >>> +uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI, >>> + unsigned OpIdx) const { >>> + // {20-17} = reg >>> + // {16} = (U)nsigned (add == '1', sub == '0') >>> + // {15-0} = imm >>> const MCOperand &MO = MI.getOperand(OpIdx); >>> const MCOperand &MO1 = MI.getOperand(OpIdx + 1); >>> uint32_t Binary = 0; >>> >>> // If The first operand isn't a register, we have a label reference. >>> if (!MO.isReg()) { >>> - Binary |= ARM::PC << 13; // Rn is PC. >>> + Binary |= ARM::PC << 17; // Rn is PC. >>> // FIXME: Add a fixup referencing the label. >>> return Binary; >>> } >>> >>> unsigned Reg = getARMRegisterNumbering(MO.getReg()); >>> - int32_t Imm12 = MO1.getImm(); >>> - bool isAdd = Imm12 >= 0; >>> + int32_t Imm = MO1.getImm(); >>> + bool isAdd = Imm >= 0; >>> + >>> // Special value for #-0 >>> - if (Imm12 == INT32_MIN) >>> - Imm12 = 0; >>> + if (Imm == INT32_MIN) >>> + Imm = 0; >>> + >>> // Immediate is always encoded as positive. The 'U' bit controls add vs sub. >>> - if (Imm12 < 0) >>> - Imm12 = -Imm12; >>> - Binary = Imm12 & 0xfff; >>> + if (Imm < 0) Imm = -Imm; >>> + >>> + Binary = Imm & 0xffff; >>> if (isAdd) >>> - Binary |= (1 << 12); >>> - Binary |= (Reg << 13); >>> + Binary |= (1 << 16); >>> + Binary |= (Reg << 17); >>> return Binary; >>> } >>> >>> @@ -320,7 +320,6 @@ >>> return regno.getReg(); >>> } >>> >>> - >>> void ARMMCCodeEmitter:: >>> EncodeInstruction(const MCInst &MI, raw_ostream &OS, >>> SmallVectorImpl &Fixups) const { >>> >>> Modified: llvm/trunk/test/MC/ARM/arm_instructions.s >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=118094&r1=118093&r2=118094&view=diff >>> ============================================================================== >>> --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) >>> +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Nov 2 17:31:46 2010 >>> @@ -10,13 +10,8 @@ >>> >>> @ CHECK: bx lr >>> @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1] >>> -bx lr >>> + bx lr >>> >>> @ CHECK: vqdmull.s32 q8, d17, d16 >>> @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] >>> -vqdmull.s32 q8, d17, d16 >>> - >>> -@ CHECK: vldr.64 d17, [r0] >>> -@ CHECK: encoding: [0x00,0x0b,0x10,0xed] >>> -vldr.64 d17, [r0] >>> - >>> + vqdmull.s32 q8, d17, d16 >>> >>> Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118094&r1=118093&r2=118094&view=diff >>> ============================================================================== >>> --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) >>> +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 2 17:31:46 2010 >>> @@ -157,3 +157,20 @@ >>> >>> @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] >>> vmov r0, r1, d16 >>> + >>> +@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] >>> + vldr.64 d17, [r0] >>> + >>> +@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] >>> + vldr.64 d1, [r2, #32] >>> + >>> + >>> +@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] >>> + vldr.64 d2, [r3] >>> + >>> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >>> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >>> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >>> + vldr.64 d3, [pc] >>> + vldr.64 d3, [pc,#0] >>> + vldr.64 d3, [pc,#-0] >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From grosbach at apple.com Tue Nov 2 20:35:16 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 01:35:16 -0000 Subject: [llvm-commits] [llvm] r118141 - in /llvm/trunk/lib/Target/ARM/InstPrinter: ARMInstPrinter.cpp ARMInstPrinter.h Message-ID: <20101103013516.2AB6F2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 2 20:35:15 2010 New Revision: 118141 URL: http://llvm.org/viewvc/llvm-project?rev=118141&view=rev Log: Remove unused function. Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118141&r1=118140&r2=118141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Nov 2 20:35:15 2010 @@ -338,14 +338,6 @@ O << ", " << getRegisterName(MO.getReg()); } -void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - // All instructions using addrmodepc are pseudos and should have been - // handled explicitly in printInstructionThroughMCStreamer(). If one got - // here, it wasn't, so something's wrong. - llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); -} - void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=118141&r1=118140&r2=118141&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Tue Nov 2 20:35:15 2010 @@ -50,7 +50,6 @@ void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); From grosbach at apple.com Tue Nov 2 20:39:21 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 2 Nov 2010 18:39:21 -0700 Subject: [llvm-commits] [llvm] r117858 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMInstrVFP.td lib/Target/MBlaze/MBlazeInstrInfo.td utils/TableGen/AsmMatcherEmitter.cpp In-Reply-To: <20101031184812.7DA9A2A6C12C@llvm.org> References: <20101031184812.7DA9A2A6C12C@llvm.org> Message-ID: <9E3EA4E2-C91A-4BC0-B5CB-AE9B2169A1F2@apple.com> Hi Chris, I think r118137 has fixed the ARM instructions that were causing heartburn. -Jim On Oct 31, 2010, at 11:48 AM, Chris Lattner wrote: > Author: lattner > Date: Sun Oct 31 13:48:12 2010 > New Revision: 117858 > > URL: http://llvm.org/viewvc/llvm-project?rev=117858&view=rev > Log: > the asm matcher can't handle operands with modifiers (like ${foo:bar}). > Instead of silently ignoring these instructions, emit a hard error and > force the target author to either refactor the target or mark the > instruction 'isCodeGenOnly'. > > Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are > doing this. > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMInstrThumb.td > llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > llvm/trunk/lib/Target/ARM/ARMInstrVFP.td > llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td > llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117858&r1=117857&r2=117858&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sun Oct 31 13:48:12 2010 > @@ -1166,7 +1166,7 @@ > // FIXME: remove when we have a way to marking a MI with these properties. > // FIXME: Should pc be an implicit operand like PICADD, etc? > let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, > - hasExtraDefRegAllocReq = 1 in > + hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in > def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), > IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, > @@ -1416,6 +1416,7 @@ > } > > // Store Return State is a system instruction -- for disassembly only > +let isCodeGenOnly = 1 in { // FIXME: This should not use submode! > def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), > NoItinerary, "srs${addr:submode}\tsp!, $mode", > [/* For disassembly only; pattern left blank */]> { > @@ -1444,6 +1445,7 @@ > let Inst{31-28} = 0b1111; > let Inst{22-20} = 0b001; // W = 0 > } > +} // isCodeGenOnly = 1 > > //===----------------------------------------------------------------------===// > // Load / store Instructions. > @@ -1681,7 +1683,8 @@ > // Load / store multiple Instructions. > // > > -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { > +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), > IndexModeNone, LdStMulFrm, IIC_iLoad_m, > @@ -1694,7 +1697,8 @@ > "$addr.addr = $wb", []>; > } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq > > -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { > +let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, > reglist:$srcs, variable_ops), > IndexModeNone, LdStMulFrm, IIC_iStore_m, > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=117858&r1=117857&r2=117858&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sun Oct 31 13:48:12 2010 > @@ -532,7 +532,8 @@ > // > > // These require base address to be written back or one of the loaded regs. > -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { > +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def tLDM : T1I<(outs), > (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), > IIC_iLoad_m, > @@ -547,7 +548,8 @@ > T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 > } // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq > > -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in > +let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, > + isCodeGenOnly = 1 in > def tSTM_UPD : T1It<(outs tGPR:$wb), > (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), > IIC_iStore_mu, > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=117858&r1=117857&r2=117858&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sun Oct 31 13:48:12 2010 > @@ -1241,7 +1241,8 @@ > // Load / store multiple Instructions. > // > > -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { > +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), IIC_iLoad_m, > "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> { > @@ -1267,7 +1268,8 @@ > } > } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq > > -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { > +let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, > reglist:$srcs, variable_ops), IIC_iStore_m, > "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> { > @@ -2429,7 +2431,7 @@ > // operand list. > // FIXME: Should pc be an implicit operand like PICADD, etc? > let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, > - hasExtraDefRegAllocReq = 1 in > + hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in > def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), > IIC_iLoad_mBr, > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=117858&r1=117857&r2=117858&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sun Oct 31 13:48:12 2010 > @@ -72,7 +72,8 @@ > // Load / store multiple Instructions. > // > > -let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { > +let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, > variable_ops), IndexModeNone, IIC_fpLoad_m, > "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { > @@ -102,7 +103,8 @@ > } > } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq > > -let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { > +let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, > + isCodeGenOnly = 1 in { > def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, > variable_ops), IndexModeNone, IIC_fpStore_m, > "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=117858&r1=117857&r2=117858&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Sun Oct 31 13:48:12 2010 > @@ -562,7 +562,7 @@ > "src $dst, $src", [], IIAlu>; > } > > -let opcode=0x08 in { > +let opcode=0x08, isCodeGenOnly=1 in { > def LEA_ADDI : TB<0x08, (outs GPR:$dst), (ins memri:$addr), > "addi $dst, ${addr:stackloc}", > [(set GPR:$dst, iaddr:$addr)], IIAlu>; > > Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=117858&r1=117857&r2=117858&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sun Oct 31 13:48:12 2010 > @@ -257,27 +257,26 @@ > // this implies a constraint we would not honor. > std::set OperandNames; > for (unsigned i = 1, e = Tokens.size(); i < e; ++i) { > - if (Tokens[i][0] == '$' && > - std::find(Tokens[i].begin(), > - Tokens[i].end(), ':') != Tokens[i].end()) { > - DEBUG({ > - errs() << "warning: '" << Name << "': " > - << "ignoring instruction; operand with attribute '" > - << Tokens[i] << "'\n"; > - }); > - return false; > - } > - > - if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) { > - DEBUG({ > + for (unsigned i = 1, e = Tokens.size(); i < e; ++i) { > + if (Tokens[i][0] == '$' && > + Tokens[i].find(':') != StringRef::npos) { > + PrintError(CGI.TheDef->getLoc(), > + "instruction with operand modifier '" + Tokens[i].str() + > + "' not supported by asm matcher. Mark isCodeGenOnly!"); > + throw std::string("ERROR: Invalid instruction"); > + } > + > + if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) { > + DEBUG({ > errs() << "warning: '" << Name << "': " > << "ignoring instruction with tied operand '" > << Tokens[i].str() << "'\n"; > }); > - return false; > + return false; > + } > } > } > - > + > return true; > } > > @@ -648,13 +647,11 @@ > case '*': Res += "_STAR_"; break; > case '%': Res += "_PCT_"; break; > case ':': Res += "_COLON_"; break; > - > default: > - if (isalnum(*it)) { > + if (isalnum(*it)) > Res += *it; > - } else { > + else > Res += "_" + utostr((unsigned) *it) + "_"; > - } > } > } > > @@ -904,14 +901,6 @@ > } > > void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) { > - // Parse the instructions; we need to do this first so that we can gather the > - // singleton register classes. > - std::set SingletonRegisterNames; > - > - const std::vector &InstrList = > - Target.getInstructionsByEnumValue(); > - > - > // Build information about all of the AssemblerPredicates. > std::vector AllPredicates = > Records.getAllDerivedDefinitions("Predicate"); > @@ -931,9 +920,16 @@ > assert(FeatureNo < 32 && "Too many subtarget features!"); > } > > + // Parse the instructions; we need to do this first so that we can gather the > + // singleton register classes. > + std::set SingletonRegisterNames; > + const std::vector &InstrList = > + Target.getInstructionsByEnumValue(); > for (unsigned i = 0, e = InstrList.size(); i != e; ++i) { > const CodeGenInstruction &CGI = *InstrList[i]; > > + // If the tblgen -match-prefix option is specified (for tblgen hackers), > + // filter the set of instructions we consider. > if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix)) > continue; > > @@ -943,7 +939,8 @@ > II->Instr = &CGI; > II->AsmString = FlattenVariants(CGI.AsmString, 0); > > - // Remove comments from the asm string. > + // Remove comments from the asm string. We know that the asmstring only > + // has one line. > if (!CommentDelimiter.empty()) { > size_t Idx = StringRef(II->AsmString).find(CommentDelimiter); > if (Idx != StringRef::npos) > @@ -955,7 +952,7 @@ > // Ignore instructions which shouldn't be matched. > if (!IsAssemblerInstruction(CGI.TheDef->getName(), CGI, II->Tokens)) > continue; > - > + > // Collect singleton registers, if used. > for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) { > if (!II->Tokens[i].startswith(RegisterPrefix)) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Tue Nov 2 20:40:58 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 2 Nov 2010 18:40:58 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r117934 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <491B6BA9-C313-4D27-A9A5-D442F874B641@apple.com> References: <20101101173723.69A3F2A6C12C@llvm.org> <491B6BA9-C313-4D27-A9A5-D442F874B641@apple.com> Message-ID: <53F6E3F9-DD11-4EDF-B962-A218FE5DF064@apple.com> On Nov 1, 2010, at 8:52 PM, Eric Christopher wrote: > > On Nov 1, 2010, at 10:37 AM, Bob Wilson wrote: > >> I don't know so much about synchronization on other targets besides ARM, and >> since there was already a separate version of the barriers for ARM/Darwin, >> I've only changed that version. It seems like this change would apply to >> other targets as well, but I don't know for sure. > > x86 largely uses the lock prefix to handle this sort of thing as opposed to emitting > a memory barrier instruction (mfence, lfence, sfence). > Yeah, the X86 atomic stuff explicitly removes the membarrier intrinsics when they surround one of the atomic operation intrinsics. > This change in particular isn't real interesting for x86 since we'll still just use an > mfence there I think. :) > > -eric > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Tue Nov 2 20:41:51 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 2 Nov 2010 18:41:51 -0700 Subject: [llvm-commits] [llvm] r118094 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/simple-fp-encoding.s In-Reply-To: <68FDE696-8AC9-409F-B571-84CEF0D6AFB6@apple.com> References: <20101102223146.47EA52A6C12C@llvm.org> <39F60132-FCF3-4D15-A988-09A6A5484874@apple.com> <68FDE696-8AC9-409F-B571-84CEF0D6AFB6@apple.com> Message-ID: Thanks. :-) I ran into another problem^Wfeature where address mode 5 negative offsets weren't being handled correctly with the MC stuff. So I ended up having to refactor this code and use the ARM_AM addressing mode functions to get it to work properly. So it will go back to the same encoding, but the main way register and immediate information is retrieved is the same. :) -bw On Nov 2, 2010, at 6:26 PM, Jim Grosbach wrote: > Hey Bill, > > Hmmm.... So you're looking to reuse the encoder method for other complex operands that need the same basic information (register/offset pair)? That makes a lot more sense and I don't see any reason why that's a bad thing (quite the opposite). Where we need to be careful is in re-using the operand definitions themselves, as those have the matchers, printers, and such that will be different. Sounds like we're on the same page there and I was just a bit confused. > > Thanks! > > -Jim > > On Nov 2, 2010, at 4:02 PM, Bill Wendling wrote: > >> Hi Jim, >> >> I might not have explained my change very well. I wanted to convert the getAddrModeImm12OpValue into a generic function that gets the register and address information, and encodes that into an i32 to be used by the MC encoding stuff. The immediate isn't necessarily 16-bits in size (though it can be). In fact, for the VLDR stuff it's expecting an 8-bit immediate. >> >> The reason why I didn't create a getAddrModeImm8OpValue method was because it had the exact same code as getAddrModeImm12OpValue, just that the offsets of the values were different (the U bit was at {8} instead of {12}, etc.). :-) >> >> I'll be happy to rework this and create an imm8-specific method if that's desirable. It would be easy to refactor the original code to do that. >> >> -bw >> >> On Nov 2, 2010, at 3:51 PM, Jim Grosbach wrote: >> >>> Hi Bill, >>> >>> We should add a new addrmode_i16 for this rather than re-using the current one. How many bits are legal is part of the semantics, and is enforced by the selection dag stuff (SelectAddrModeImm12() in this case). For a parallel example, see the Thumb2 t2addrmode_imm12 and t2addrmode_imm8 modes in ARMInstrThumb2.td. >>> >>> -Jim >>> >>> On Nov 2, 2010, at 3:31 PM, Bill Wendling wrote: >>> >>>> Author: void >>>> Date: Tue Nov 2 17:31:46 2010 >>>> New Revision: 118094 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=118094&view=rev >>>> Log: >>>> Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work >>>> with immediates up to 16-bits in size. The same logic is applied to other LDR >>>> encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in >>>> VLDR's case). Removing the "12" allows it to be more generic. >>>> >>>> Modified: >>>> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp >>>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >>>> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td >>>> llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >>>> llvm/trunk/test/MC/ARM/arm_instructions.s >>>> llvm/trunk/test/MC/ARM/simple-fp-encoding.s >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) >>>> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 17:31:46 2010 >>>> @@ -177,26 +177,27 @@ >>>> const { return 0; } >>>> unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, >>>> unsigned Op) const { return 0; } >>>> - unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) >>>> - const { >>>> - // {17-13} = reg >>>> - // {12} = (U)nsigned (add == '1', sub == '0') >>>> - // {11-0} = imm12 >>>> - const MachineOperand &MO = MI.getOperand(Op); >>>> - const MachineOperand &MO1 = MI.getOperand(Op + 1); >>>> - if (!MO.isReg()) { >>>> - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); >>>> - return 0; >>>> - } >>>> - unsigned Reg = getARMRegisterNumbering(MO.getReg()); >>>> - int32_t Imm12 = MO1.getImm(); >>>> - uint32_t Binary; >>>> - Binary = Imm12 & 0xfff; >>>> - if (Imm12 >= 0) >>>> - Binary |= (1 << 12); >>>> - Binary |= (Reg << 13); >>>> - return Binary; >>>> + uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const { >>>> + // {20-17} = reg >>>> + // {16} = (U)nsigned (add == '1', sub == '0') >>>> + // {15-0} = imm >>>> + const MachineOperand &MO = MI.getOperand(Op); >>>> + const MachineOperand &MO1 = MI.getOperand(Op + 1); >>>> + if (!MO.isReg()) { >>>> + emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); >>>> + return 0; >>>> } >>>> + >>>> + unsigned Reg = getARMRegisterNumbering(MO.getReg()); >>>> + int32_t Imm = MO1.getImm(); >>>> + uint32_t Binary; >>>> + Binary = Imm & 0xffff; >>>> + if (Imm >= 0) >>>> + Binary |= (1 << 16); >>>> + >>>> + Binary |= (Reg << 17); >>>> + return Binary; >>>> + } >>>> unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) >>>> const { return 0; } >>>> >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118094&r1=118093&r2=118094&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) >>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 17:31:46 2010 >>>> @@ -398,7 +398,7 @@ >>>> // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other >>>> // immediate values are as normal. >>>> >>>> - string EncoderMethod = "getAddrModeImm12OpValue"; >>>> + string EncoderMethod = "getAddrModeImmOpValue"; >>>> let PrintMethod = "printAddrModeImm12Operand"; >>>> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); >>>> } >>>> @@ -464,6 +464,7 @@ >>>> let PrintMethod = "printAddrMode5Operand"; >>>> let MIOperandInfo = (ops GPR:$base, i32imm); >>>> let ParserMatchClass = ARMMemMode5AsmOperand; >>>> + string EncoderMethod = "getAddrModeImmOpValue"; >>>> } >>>> >>>> // addrmode6 := reg with optional writeback >>>> @@ -830,9 +831,9 @@ >>>> AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", >>>> [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { >>>> bits<4> Rt; >>>> - bits<17> addr; >>>> - let Inst{23} = addr{12}; // U (add = ('U' == 1)) >>>> - let Inst{19-16} = addr{16-13}; // Rn >>>> + bits<32> addr; >>>> + let Inst{23} = addr{16}; // U (add = ('U' == 1)) >>>> + let Inst{19-16} = addr{20-17}; // Rn >>>> let Inst{15-12} = Rt; >>>> let Inst{11-0} = addr{11-0}; // imm12 >>>> } >>>> @@ -840,9 +841,9 @@ >>>> AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", >>>> [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { >>>> bits<4> Rt; >>>> - bits<17> shift; >>>> - let Inst{23} = shift{12}; // U (add = ('U' == 1)) >>>> - let Inst{19-16} = shift{16-13}; // Rn >>>> + bits<32> shift; >>>> + let Inst{23} = shift{16}; // U (add = ('U' == 1)) >>>> + let Inst{19-16} = shift{20-17}; // Rn >>>> let Inst{11-0} = shift{11-0}; >>>> } >>>> } >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118094&r1=118093&r2=118094&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) >>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 17:31:46 2010 >>>> @@ -53,18 +53,29 @@ >>>> let canFoldAsLoad = 1, isReMaterializable = 1 in { >>>> def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), >>>> IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", >>>> - [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; >>>> + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { >>>> + // Instruction operands. >>>> + bits<5> Dd; >>>> + bits<32> addr; >>>> + >>>> + // Encode instruction operands. >>>> + let Inst{23} = addr{16}; // U (add = (U == '1')) >>>> + let Inst{22} = Dd{4}; >>>> + let Inst{19-16} = addr{20-17}; // Rn >>>> + let Inst{15-12} = Dd{3-0}; >>>> + let Inst{7-0} = addr{7-0}; // imm8 >>>> +} >>>> >>>> def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), >>>> IIC_fpLoad32, "vldr", ".32\t$dst, $addr", >>>> [(set SPR:$dst, (load addrmode5:$addr))]>; >>>> } // canFoldAsLoad >>>> >>>> -def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), >>>> +def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), >>>> IIC_fpStore64, "vstr", ".64\t$src, $addr", >>>> [(store (f64 DPR:$src), addrmode5:$addr)]>; >>>> >>>> -def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), >>>> +def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), >>>> IIC_fpStore32, "vstr", ".32\t$src, $addr", >>>> [(store SPR:$src, addrmode5:$addr)]>; >>>> >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118094&r1=118093&r2=118094&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) >>>> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 17:31:46 2010 >>>> @@ -49,9 +49,8 @@ >>>> /// operand requires relocation, record the relocation and return zero. >>>> unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; >>>> >>>> - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' >>>> - /// operand. >>>> - unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const; >>>> + /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. >>>> + uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const; >>>> >>>> /// getCCOutOpValue - Return encoding of the 's' bit. >>>> unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { >>>> @@ -170,37 +169,38 @@ >>>> return 0; >>>> } >>>> >>>> -/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' >>>> -/// operand. >>>> -unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, >>>> - unsigned OpIdx) const { >>>> - // {17-13} = reg >>>> - // {12} = (U)nsigned (add == '1', sub == '0') >>>> - // {11-0} = imm12 >>>> +/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. >>>> +uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI, >>>> + unsigned OpIdx) const { >>>> + // {20-17} = reg >>>> + // {16} = (U)nsigned (add == '1', sub == '0') >>>> + // {15-0} = imm >>>> const MCOperand &MO = MI.getOperand(OpIdx); >>>> const MCOperand &MO1 = MI.getOperand(OpIdx + 1); >>>> uint32_t Binary = 0; >>>> >>>> // If The first operand isn't a register, we have a label reference. >>>> if (!MO.isReg()) { >>>> - Binary |= ARM::PC << 13; // Rn is PC. >>>> + Binary |= ARM::PC << 17; // Rn is PC. >>>> // FIXME: Add a fixup referencing the label. >>>> return Binary; >>>> } >>>> >>>> unsigned Reg = getARMRegisterNumbering(MO.getReg()); >>>> - int32_t Imm12 = MO1.getImm(); >>>> - bool isAdd = Imm12 >= 0; >>>> + int32_t Imm = MO1.getImm(); >>>> + bool isAdd = Imm >= 0; >>>> + >>>> // Special value for #-0 >>>> - if (Imm12 == INT32_MIN) >>>> - Imm12 = 0; >>>> + if (Imm == INT32_MIN) >>>> + Imm = 0; >>>> + >>>> // Immediate is always encoded as positive. The 'U' bit controls add vs sub. >>>> - if (Imm12 < 0) >>>> - Imm12 = -Imm12; >>>> - Binary = Imm12 & 0xfff; >>>> + if (Imm < 0) Imm = -Imm; >>>> + >>>> + Binary = Imm & 0xffff; >>>> if (isAdd) >>>> - Binary |= (1 << 12); >>>> - Binary |= (Reg << 13); >>>> + Binary |= (1 << 16); >>>> + Binary |= (Reg << 17); >>>> return Binary; >>>> } >>>> >>>> @@ -320,7 +320,6 @@ >>>> return regno.getReg(); >>>> } >>>> >>>> - >>>> void ARMMCCodeEmitter:: >>>> EncodeInstruction(const MCInst &MI, raw_ostream &OS, >>>> SmallVectorImpl &Fixups) const { >>>> >>>> Modified: llvm/trunk/test/MC/ARM/arm_instructions.s >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=118094&r1=118093&r2=118094&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) >>>> +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Nov 2 17:31:46 2010 >>>> @@ -10,13 +10,8 @@ >>>> >>>> @ CHECK: bx lr >>>> @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1] >>>> -bx lr >>>> + bx lr >>>> >>>> @ CHECK: vqdmull.s32 q8, d17, d16 >>>> @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2] >>>> -vqdmull.s32 q8, d17, d16 >>>> - >>>> -@ CHECK: vldr.64 d17, [r0] >>>> -@ CHECK: encoding: [0x00,0x0b,0x10,0xed] >>>> -vldr.64 d17, [r0] >>>> - >>>> + vqdmull.s32 q8, d17, d16 >>>> >>>> Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118094&r1=118093&r2=118094&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) >>>> +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 2 17:31:46 2010 >>>> @@ -157,3 +157,20 @@ >>>> >>>> @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec] >>>> vmov r0, r1, d16 >>>> + >>>> +@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed] >>>> + vldr.64 d17, [r0] >>>> + >>>> +@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] >>>> + vldr.64 d1, [r2, #32] >>>> + >>>> + >>>> +@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] >>>> + vldr.64 d2, [r3] >>>> + >>>> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >>>> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >>>> +@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] >>>> + vldr.64 d3, [pc] >>>> + vldr.64 d3, [pc,#0] >>>> + vldr.64 d3, [pc,#-0] >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> > From gohman at apple.com Tue Nov 2 20:47:47 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 03 Nov 2010 01:47:47 -0000 Subject: [llvm-commits] [llvm] r118143 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/narrow-shl-load.ll Message-ID: <20101103014747.346532A6C12C@llvm.org> Author: djg Date: Tue Nov 2 20:47:46 2010 New Revision: 118143 URL: http://llvm.org/viewvc/llvm-project?rev=118143&view=rev Log: Fix DAGCombiner to avoid going into an infinite loop when it encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. Added: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll (with props) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=118143&r1=118142&r2=118143&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 2 20:47:46 2010 @@ -3667,6 +3667,20 @@ // fold (zext (truncate x)) -> (and x, mask) if (N0.getOpcode() == ISD::TRUNCATE && (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { + + // fold (zext (truncate (load x))) -> (zext (smaller load x)) + // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) + SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); + if (NarrowLoad.getNode()) { + SDNode* oye = N0.getNode()->getOperand(0).getNode(); + if (NarrowLoad.getNode() != N0.getNode()) { + CombineTo(N0.getNode(), NarrowLoad); + // CombineTo deleted the truncate, if needed, but not what's under it. + AddToWorkList(oye); + } + return SDValue(N, 0); // Return N so it doesn't get rechecked! + } + SDValue Op = N0.getOperand(0); if (Op.getValueType().bitsLT(VT)) { Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); @@ -4102,6 +4116,17 @@ } } + // If the load is shifted left (and the result isn't shifted back right), + // we can fold the truncate through the shift. + unsigned ShLeftAmt = 0; + if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && + TLI.isNarrowingProfitable(N0.getValueType(), VT)) { + if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) { + ShLeftAmt = N01->getZExtValue(); + N0 = N0.getOperand(0); + } + } + // Do not generate loads of non-round integer types since these can // be expensive (and would be wrong if the type is not byte sized). if (isa(N0) && N0.hasOneUse() && ExtVT.isRound() && @@ -4140,8 +4165,18 @@ DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), &DeadNodes); + // Shift the result left, if we've swallowed a left shift. + SDValue Result = Load; + if (ShLeftAmt != 0) { + EVT ShImmTy = getShiftAmountTy(); + if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) + ShImmTy = VT; + Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, + Result, DAG.getConstant(ShLeftAmt, ShImmTy)); + } + // Return the new loaded value. - return Load; + return Result; } return SDValue(); Added: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll?rev=118143&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll (added) +++ llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll Tue Nov 2 20:47:46 2010 @@ -0,0 +1,32 @@ +; RUN: llc -march=x86-64 < %s + +; DAGCombiner should fold this code in finite time. + +; rdar://8606584 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-pc-linux-gnu" + +define void @D() nounwind readnone { +bb.nph: + br label %while.cond + +while.cond: ; preds = %while.cond, %bb.nph + %tmp6 = load i32* undef, align 4 + %and = or i64 undef, undef + %conv11 = zext i32 undef to i64 + %conv14 = zext i32 %tmp6 to i64 + %shl15 = shl i64 %conv14, 1 + %shl15.masked = and i64 %shl15, 4294967294 + %and17 = or i64 %shl15.masked, %conv11 + %add = add i64 %and17, 1 + %xor = xor i64 %add, %and + %tmp20 = load i64* undef, align 8 + %add21 = add i64 %xor, %tmp20 + %conv22 = trunc i64 %add21 to i32 + store i32 %conv22, i32* undef, align 4 + br i1 false, label %while.end, label %while.cond + +while.end: ; preds = %while.cond + ret void +} Propchange: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll ------------------------------------------------------------------------------ svn:executable = * From isanbard at gmail.com Tue Nov 2 20:49:29 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 03 Nov 2010 01:49:29 -0000 Subject: [llvm-commits] [llvm] r118144 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMMCCodeEmitter.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp test/MC/ARM/simple-fp-encoding.s Message-ID: <20101103014929.431412A6C12C@llvm.org> Author: void Date: Tue Nov 2 20:49:29 2010 New Revision: 118144 URL: http://llvm.org/viewvc/llvm-project?rev=118144&view=rev Log: The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 2 20:49:29 2010 @@ -177,25 +177,44 @@ const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - uint32_t getAddrModeImmOpValue(const MachineInstr &MI, unsigned Op) const { - // {20-17} = reg - // {16} = (U)nsigned (add == '1', sub == '0') - // {15-0} = imm + + unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) + const { + // {17-13} = reg + // {12} = (U)nsigned (add == '1', sub == '0') + // {11-0} = imm12 const MachineOperand &MO = MI.getOperand(Op); const MachineOperand &MO1 = MI.getOperand(Op + 1); if (!MO.isReg()) { emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); return 0; } - unsigned Reg = getARMRegisterNumbering(MO.getReg()); - int32_t Imm = MO1.getImm(); + int32_t Imm12 = MO1.getImm(); uint32_t Binary; - Binary = Imm & 0xffff; - if (Imm >= 0) - Binary |= (1 << 16); - - Binary |= (Reg << 17); + Binary = Imm12 & 0xfff; + if (Imm12 >= 0) + Binary |= (1 << 12); + Binary |= (Reg << 13); + return Binary; + } + uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { + // {12-9} = reg + // {8} = (U)nsigned (add == '1', sub == '0') + // {7-0} = imm12 + const MachineOperand &MO = MI.getOperand(Op); + const MachineOperand &MO1 = MI.getOperand(Op + 1); + if (!MO.isReg()) { + emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); + return 0; + } + unsigned Reg = getARMRegisterNumbering(MO.getReg()); + int32_t Imm8 = MO1.getImm(); + uint32_t Binary; + Binary = Imm8 & 0xff; + if (Imm8 >= 0) + Binary |= (1 << 8); + Binary |= (Reg << 9); return Binary; } unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 2 20:49:29 2010 @@ -398,7 +398,7 @@ // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other // immediate values are as normal. - string EncoderMethod = "getAddrModeImmOpValue"; + string EncoderMethod = "getAddrModeImm12OpValue"; let PrintMethod = "printAddrModeImm12Operand"; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } @@ -462,7 +462,7 @@ let PrintMethod = "printAddrMode5Operand"; let MIOperandInfo = (ops GPR:$base, i32imm); let ParserMatchClass = ARMMemMode5AsmOperand; - string EncoderMethod = "getAddrModeImmOpValue"; + string EncoderMethod = "getAddrMode5OpValue"; } // addrmode6 := reg with optional writeback @@ -828,20 +828,20 @@ def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr), AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { - bits<4> Rt; - bits<32> addr; - let Inst{23} = addr{16}; // U (add = ('U' == 1)) - let Inst{19-16} = addr{20-17}; // Rn + bits<4> Rt; + bits<17> addr; + let Inst{23} = addr{12}; // U (add = ('U' == 1)) + let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift), AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { - bits<4> Rt; - bits<32> shift; - let Inst{23} = shift{16}; // U (add = ('U' == 1)) - let Inst{19-16} = shift{20-17}; // Rn + bits<4> Rt; + bits<17> shift; + let Inst{23} = shift{12}; // U (add = ('U' == 1)) + let Inst{19-16} = shift{16-13}; // Rn let Inst{11-0} = shift{11-0}; } } Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 2 20:49:29 2010 @@ -51,25 +51,38 @@ // let canFoldAsLoad = 1, isReMaterializable = 1 in { + def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { // Instruction operands. - bits<5> Dd; - bits<32> addr; + bits<5> Dd; + bits<13> addr; // Encode instruction operands. - let Inst{23} = addr{16}; // U (add = (U == '1')) + let Inst{23} = addr{8}; // U (add = (U == '1')) let Inst{22} = Dd{4}; - let Inst{19-16} = addr{20-17}; // Rn + let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Dd{3-0}; let Inst{7-0} = addr{7-0}; // imm8 } -def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr), - IIC_fpLoad32, "vldr", ".32\t$dst, $addr", - [(set SPR:$dst, (load addrmode5:$addr))]>; -} // canFoldAsLoad +def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), + IIC_fpLoad32, "vldr", ".32\t$Sd, $addr", + [(set SPR:$Sd, (load addrmode5:$addr))]> { + // Instruction operands. + bits<5> Sd; + bits<13> addr; + + // Encode instruction operands. + let Inst{23} = addr{8}; // U (add = (U == '1')) + let Inst{22} = Sd{0}; + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Sd{4-1}; + let Inst{7-0} = addr{7-0}; // imm8 +} + +} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), IIC_fpStore64, "vstr", ".64\t$src, $addr", Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 20:49:29 2010 @@ -49,8 +49,15 @@ /// operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; - /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. - uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const; + bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, + unsigned &Reg, unsigned &Imm) const; + + /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' + /// operand. + uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx) const; + + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. + uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx) const; /// getCCOutOpValue - Return encoding of the 's' bit. unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { @@ -170,37 +177,76 @@ } /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. -uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI, - unsigned OpIdx) const { - // {20-17} = reg - // {16} = (U)nsigned (add == '1', sub == '0') - // {15-0} = imm +bool ARMMCCodeEmitter::EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, + unsigned &Reg, + unsigned &Imm) const { const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); - uint32_t Binary = 0; // If The first operand isn't a register, we have a label reference. if (!MO.isReg()) { - Binary |= ARM::PC << 17; // Rn is PC. + Reg = ARM::PC; // Rn is PC. + Imm = 0; // FIXME: Add a fixup referencing the label. - return Binary; + return true; } - unsigned Reg = getARMRegisterNumbering(MO.getReg()); - int32_t Imm = MO1.getImm(); - bool isAdd = Imm >= 0; + Reg = getARMRegisterNumbering(MO.getReg()); + + int32_t SImm = MO1.getImm(); + bool isAdd = true; // Special value for #-0 - if (Imm == INT32_MIN) - Imm = 0; + if (SImm == INT32_MIN) + SImm = 0; // Immediate is always encoded as positive. The 'U' bit controls add vs sub. - if (Imm < 0) Imm = -Imm; + if (SImm < 0) { + SImm = -SImm; + isAdd = false; + } + + Imm = SImm; + return isAdd; +} - Binary = Imm & 0xffff; +/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. +uint32_t ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, + unsigned OpIdx) const { + // {17-13} = reg + // {12} = (U)nsigned (add == '1', sub == '0') + // {11-0} = imm12 + unsigned Reg, Imm12; + bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12); + + if (Reg == ARM::PC) + return ARM::PC << 13; // Rn is PC; + + uint32_t Binary = Imm12 & 0xfff; + // Immediate is always encoded as positive. The 'U' bit controls add vs sub. if (isAdd) - Binary |= (1 << 16); - Binary |= (Reg << 17); + Binary |= (1 << 12); + Binary |= (Reg << 13); + return Binary; +} + +/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand. +uint32_t ARMMCCodeEmitter::getAddrMode5OpValue(const MCInst &MI, + unsigned OpIdx) const { + // {12-9} = reg + // {8} = (U)nsigned (add == '1', sub == '0') + // {7-0} = imm8 + unsigned Reg, Imm8; + EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8); + + if (Reg == ARM::PC) + return ARM::PC << 13; // Rn is PC; + + uint32_t Binary = ARM_AM::getAM5Offset(Imm8); + // Immediate is always encoded as positive. The 'U' bit controls add vs sub. + if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add) + Binary |= (1 << 8); + Binary |= (Reg << 9); return Binary; } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 2 20:49:29 2010 @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "ARM.h" +#include "ARMAddressingModes.h" #include "ARMSubtarget.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" @@ -260,16 +261,25 @@ Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); assert(!Mem.OffsetIsReg && "invalid mode 5 operand"); + // FIXME: #-0 is encoded differently than #0. Does the parser preserve // the difference? if (Mem.Offset) { const MCConstantExpr *CE = dyn_cast(Mem.Offset); - assert(CE && "non-constant mode 5 offset operand!"); + assert(CE && "Non-constant mode 5 offset operand!"); + // The MCInst offset operand doesn't include the low two bits (like // the instruction encoding). - Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); - } else + int64_t Offset = CE->getValue() / 4; + if (Offset >= 0) + Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, + Offset))); + else + Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, + -Offset))); + } else { Inst.addOperand(MCOperand::CreateImm(0)); + } } virtual void dump(raw_ostream &OS) const; Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Nov 2 20:49:29 2010 @@ -310,7 +310,7 @@ if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) { O << ", #" << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm())) - << ImmOffs*4; + << ImmOffs * 4; } O << "]"; } Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118144&r1=118143&r2=118144&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 2 20:49:29 2010 @@ -162,8 +162,9 @@ vldr.64 d17, [r0] @ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed] +@ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] vldr.64 d1, [r2, #32] - + vldr.64 d1, [r2, #-32] @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] vldr.64 d2, [r3] @@ -174,3 +175,21 @@ vldr.64 d3, [pc] vldr.64 d3, [pc,#0] vldr.64 d3, [pc,#-0] + +@ CHECK: vldr.32 s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed] + vldr.32 s13, [r0] + +@ CHECK: vldr.32 s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed] +@ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] + vldr.32 s1, [r2, #32] + vldr.32 s1, [r2, #-32] + +@ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] + vldr.32 s2, [r3] + +@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] + vldr.32 s5, [pc] + vldr.32 s5, [pc,#0] + vldr.32 s5, [pc,#-0] From rafael.espindola at gmail.com Tue Nov 2 21:27:38 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 2 Nov 2010 22:27:38 -0400 Subject: [llvm-commits] [PATCH] MCFragments Clean Up In-Reply-To: References: Message-ID: 2010/11/2 David Meyer : > Rafael, > If I didn't do this, ComputeSize() would need two more arguments: > SectionAddress and FragmentOffset. MCAlignFragment uses SectionAddress + > FragmentOffset, while MCOrgFragment uses FragmentOffset.?I was trying to > avoid cluttering up the function arguments with specific values needed for > one or two fragment types.?Since we have to pass?the MCAsmLayout anyway, it > seems reasonable that it should be?capable of answering those values for the > current fragment?(since they are guaranteed to be known). > In order to avoid passing FragmentOffset, your patch uses private member > "Offset" directly, which is fragile (what if it is uninitialized?) and > against the convention of using the accessor. Also, this won't work when you > move the code away from MCFragment and into the subclasses. (Offset is a > private member of MCFragment). The information is an "argument". It can be made explicit or implicit via some value in this->. Note also that you only need SectionAddress (see patch attached two emails ago). As for being private, I think it is reasonable to make it protected as you are moving responsibility from MCFragment itself to it its subclasses. > - David M > Cheers, Rafael From echristo at apple.com Tue Nov 2 23:29:11 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 03 Nov 2010 04:29:11 -0000 Subject: [llvm-commits] [llvm] r118148 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101103042911.710B62A6C12C@llvm.org> Author: echristo Date: Tue Nov 2 23:29:11 2010 New Revision: 118148 URL: http://llvm.org/viewvc/llvm-project?rev=118148&view=rev Log: Invert these branches by default, it makes assembly comparisons a little easier to read. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118148&r1=118147&r2=118148&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 2 23:29:11 2010 @@ -1014,11 +1014,11 @@ // Re-set the flags just in case. unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) - .addReg(CmpReg).addImm(1)); + .addReg(CmpReg).addImm(0)); unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) - .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); + .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR); FastEmitBranch(FBB, DL); FuncInfo.MBB->addSuccessor(TBB); return true; From isanbard at gmail.com Tue Nov 2 23:57:44 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 03 Nov 2010 04:57:44 -0000 Subject: [llvm-commits] [llvm] r118151 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101103045744.DA5422A6C12C@llvm.org> Author: void Date: Tue Nov 2 23:57:44 2010 New Revision: 118151 URL: http://llvm.org/viewvc/llvm-project?rev=118151&view=rev Log: Put the PC encoding in the correct bit position. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118151&r1=118150&r2=118151&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 2 23:57:44 2010 @@ -240,7 +240,7 @@ EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8); if (Reg == ARM::PC) - return ARM::PC << 13; // Rn is PC; + return ARM::PC << 9; // Rn is PC; uint32_t Binary = ARM_AM::getAM5Offset(Imm8); // Immediate is always encoded as positive. The 'U' bit controls add vs sub. From evan.cheng at apple.com Wed Nov 3 00:14:24 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Nov 2010 05:14:24 -0000 Subject: [llvm-commits] [llvm] r118152 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h test/CodeGen/ARM/prefetch.ll Message-ID: <20101103051424.E45BB2A6C12C@llvm.org> Author: evancheng Date: Wed Nov 3 00:14:24 2010 New Revision: 118152 URL: http://llvm.org/viewvc/llvm-project?rev=118152&view=rev Log: Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. Added: llvm/trunk/test/CodeGen/ARM/prefetch.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118152&r1=118151&r2=118152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 00:14:24 2010 @@ -598,6 +598,11 @@ setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); + // ARM v5TE+ and Thumb2 has preload instructions. + if (Subtarget->isThumb2() || + (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())) + setOperationAction(ISD::PREFETCH, MVT::Other, Legal); + // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. if (!Subtarget->hasV6Ops()) { setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118152&r1=118151&r2=118152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 3 00:14:24 2010 @@ -991,17 +991,18 @@ // // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. -multiclass APreLoad { +multiclass APreLoad data_read, string opc> { def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary, - !strconcat(opc, "\t$addr"), []> { + !strconcat(opc, "\t$addr"), + [(prefetch addrmode_imm12:$addr, imm, (i32 data_read))]> { bits<4> Rt; bits<17> addr; let Inst{31-26} = 0b111101; let Inst{25} = 0; // 0 for immediate form - let Inst{24} = data; + let Inst{24} = data_read{1}; let Inst{23} = addr{12}; // U (add = ('U' == 1)) - let Inst{22} = read; + let Inst{22} = data_read{0}; let Inst{21-20} = 0b01; let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; @@ -1009,23 +1010,24 @@ } def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary, - !strconcat(opc, "\t$shift"), []> { + !strconcat(opc, "\t$shift"), + [(prefetch ldst_so_reg:$shift, imm, (i32 data_read))]> { bits<4> Rt; bits<17> shift; let Inst{31-26} = 0b111101; let Inst{25} = 1; // 1 for register form - let Inst{24} = data; + let Inst{24} = data_read{1}; let Inst{23} = shift{12}; // U (add = ('U' == 1)) - let Inst{22} = read; + let Inst{22} = data_read{0}; let Inst{21-20} = 0b01; let Inst{19-16} = shift{16-13}; // Rn let Inst{11-0} = shift{11-0}; } } -defm PLD : APreLoad<1, 1, "pld">; -defm PLDW : APreLoad<1, 0, "pldw">; -defm PLI : APreLoad<0, 1, "pli">; +defm PLD : APreLoad<3, "pld">; +defm PLDW : APreLoad<2, "pldw">; +defm PLI : APreLoad<1, "pli">; def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, "setend\t$end", Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118152&r1=118151&r2=118152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Nov 3 00:14:24 2010 @@ -610,6 +610,8 @@ let Inst{20} = 1; // load let Inst{11-6} = 0b000000; } + + // FIXME: Is the pci variant actually needed? def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), iii, opc, ".w\t$dst, $addr", [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> { @@ -1172,10 +1174,11 @@ // // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. -multiclass T2Ipl { +multiclass T2Ipl data_read, string opc> { - def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoad_i, opc, - "\t[$base, $imm]", []> { + def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_iLoad_i, opc, + "\t$addr", + [(prefetch t2addrmode_imm12:$addr, imm, (i32 data_read))]> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; let Inst{23} = 1; // U = 1 @@ -1185,8 +1188,9 @@ let Inst{15-12} = 0b1111; } - def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc, - "\t[$base, $imm]", []> { + def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_iLoad_i, opc, + "\t$addr", + [(prefetch t2addrmode_imm8:$addr, imm, (i32 data_read))]> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; let Inst{23} = 0; // U = 0 @@ -1197,21 +1201,9 @@ let Inst{11-8} = 0b1100; } - let isCodeGenOnly = 1 in // $base doesn't exist in asmstring? - def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc, - "\t[pc, $imm]", []> { - let Inst{31-25} = 0b1111100; - let Inst{24} = instr; - let Inst{23} = ?; // add = (U == 1) - let Inst{22} = 0; - let Inst{21} = write; - let Inst{20} = 1; - let Inst{19-16} = 0b1111; // Rn = 0b1111 - let Inst{15-12} = 0b1111; - } - - def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc, - "\t[$base, $a]", []> { + def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_iLoad_i, opc, + "\t$addr", + [(prefetch t2addrmode_so_reg:$addr, imm, (i32 data_read))]> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; let Inst{23} = 0; // add = TRUE for T1 @@ -1220,25 +1212,26 @@ let Inst{20} = 1; let Inst{15-12} = 0b1111; let Inst{11-6} = 0000000; - let Inst{5-4} = 0b00; // no shift is applied } - def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc, - "\t[$base, $a, lsl $shamt]", []> { + let isCodeGenOnly = 1 in + def pci : T2Ipc<(outs), (ins i32imm:$addr), IIC_iLoad_i, opc, + "\t$addr", + []> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; - let Inst{23} = 0; // add = TRUE for T1 + let Inst{23} = ?; // add = (U == 1) let Inst{22} = 0; let Inst{21} = write; let Inst{20} = 1; + let Inst{19-16} = 0b1111; // Rn = 0b1111 let Inst{15-12} = 0b1111; - let Inst{11-6} = 0000000; } } -defm t2PLD : T2Ipl<0, 0, "pld">; -defm t2PLDW : T2Ipl<0, 1, "pldw">; -defm t2PLI : T2Ipl<1, 0, "pli">; +defm t2PLD : T2Ipl<0, 0, 3, "pld">; +defm t2PLDW : T2Ipl<0, 1, 2, "pldw">; +defm t2PLI : T2Ipl<1, 0, 1, "pli">; //===----------------------------------------------------------------------===// // Load / store multiple Instructions. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=118152&r1=118151&r2=118152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Nov 3 00:14:24 2010 @@ -355,11 +355,11 @@ default: return false; case ARM::t2PLDi12: case ARM::t2PLDi8: - case ARM::t2PLDr: case ARM::t2PLDs: + case ARM::t2PLDs: case ARM::t2PLDWi12: case ARM::t2PLDWi8: - case ARM::t2PLDWr: case ARM::t2PLDWs: + case ARM::t2PLDWs: case ARM::t2PLIi12: case ARM::t2PLIi8: - case ARM::t2PLIr: case ARM::t2PLIs: + case ARM::t2PLIs: return true; } } @@ -369,13 +369,13 @@ default: return 0; case ARM::t2PLDi12: case ARM::t2PLDi8: - case ARM::t2PLDr: case ARM::t2PLDs: + case ARM::t2PLDs: return ARM::t2PLDpci; case ARM::t2PLDWi12: case ARM::t2PLDWi8: - case ARM::t2PLDWr: case ARM::t2PLDWs: + case ARM::t2PLDWs: return ARM::t2PLDWpci; case ARM::t2PLIi12: case ARM::t2PLIi8: - case ARM::t2PLIr: case ARM::t2PLIs: + case ARM::t2PLIs: return ARM::t2PLIpci; } } Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=118152&r1=118151&r2=118152&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Nov 3 00:14:24 2010 @@ -1731,11 +1731,11 @@ default: return false; case ARM::t2PLDi12: case ARM::t2PLDi8: case ARM::t2PLDpci: - case ARM::t2PLDr: case ARM::t2PLDs: + case ARM::t2PLDs: case ARM::t2PLDWi12: case ARM::t2PLDWi8: case ARM::t2PLDWpci: - case ARM::t2PLDWr: case ARM::t2PLDWs: + case ARM::t2PLDWs: case ARM::t2PLIi12: case ARM::t2PLIi8: case ARM::t2PLIpci: - case ARM::t2PLIr: case ARM::t2PLIs: + case ARM::t2PLIs: return true; } } Added: llvm/trunk/test/CodeGen/ARM/prefetch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=118152&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/prefetch.ll (added) +++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Wed Nov 3 00:14:24 2010 @@ -0,0 +1,64 @@ +; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v5te | FileCheck %s -check-prefix=ARM +; rdar://8601536 + +define void @t1(i8* %ptr) nounwind { +entry: +; ARM: t1: +; ARM: pli [r0] +; ARM: pldw [r0] +; ARM: pld [r0] + +; THUMB2: t1: +; THUMB2: pli [r0] +; THUMB2: pldw [r0] +; THUMB2: pld [r0] + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) + ret void +} + +define void @t2(i8* %ptr) nounwind { +entry: +; ARM: t2: +; ARM: pld [r0, #1023] + +; THUMB2: t2: +; THUMB2: pld [r0, #1023] + %tmp = getelementptr i8* %ptr, i32 1023 + tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 ) + ret void +} + +define void @t3(i32 %base, i32 %offset) nounwind { +entry: +; ARM: t3: +; ARM: pld [r0, r1, lsr #2] + +; THUMB2: t3: +; THUMB2: lsrs r1, r1, #2 +; THUMB2: pld [r0, r1] + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + ret void +} + +define void @t4(i32 %base, i32 %offset) nounwind { +entry: +; ARM: t4: +; ARM: pld [r0, r1, lsl #2] + +; THUMB2: t4: +; THUMB2: pld [r0, r1, lsl #2] + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + ret void +} + +declare void @llvm.prefetch(i8*, i32, i32) nounwind From tonic at nondot.org Wed Nov 3 00:43:23 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 05:43:23 -0000 Subject: [llvm-commits] [www] r118153 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101103054323.A11032A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 00:43:23 2010 New Revision: 118153 URL: http://llvm.org/viewvc/llvm-project?rev=118153&view=rev Log: Add location and dinner details. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118153&r1=118152&r2=118153&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 00:43:23 2010 @@ -4,8 +4,10 @@
    -
  1. Registration & Logistics
    2. +
  2. Registration
    3. +
  3. Location
  4. Agenda
    5. +
  5. Dinner
    @@ -37,11 +39,30 @@ We also invite you to sign up for the official Developer Meeting mailing list to be kept informed of updates concerning the meeting: -
    Registration & Logistics
    +
    Registration

    Registration is full for the meeting.

    -

    You will find the meeting location, times, and other important information on the Registration Website. +

    Due to budget and space restrictions, we are capped at 200 attendees and can not accept day of registration.

    + +
    Location
    + +

    The LLVM Developers' Meeting is held at the San Jose Hilton. Attendees may park at the hotel ($19 day self park, $24 valet) or in the numerous parking lots downtown.

    + +

    Hilton San Jose
    +300 Almaden Boulevard
    +San Jose, CA 95110
    +

    + +

    +Directions From San Jose Airport (Approximately 8 mins): +
    +Head southeast on Terminal Dr toward Airport Pkwy. Continue onto Airport Blvd. +Continue onto Angelo Way. Slight left at Airport Blvd. Slight left to stay on Airport Blvd. Turn right to merge onto CA-87 S toward I-280/Downtown. Take exit 6A for Park Ave toward San Carlos St/CA-82. +Turn left at Park Ave. Take the 1st right onto Woz Way. Turn left at W San Carlos St. +Take the 1st right onto S Almaden Blvd. Make U Turn - Destination on the right + +

    Agenda
    @@ -78,6 +99,22 @@
6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required)
+

Dinner
+

+QuIC will host a dinner on November 4 from 6:00pm - 8:00pm at Paolo's Restaurant. +You must have selected to attend dinner during the registration process to attend. +

+ +

Paolo's Restaurant
+333 West San Carlos Street +# 150
+San Jose, California
+(408) 294-2558
+ +Walking directions from the hotel (5 minute walk):
+Exit the hotel and head west on San Carlos Street. The restaurant will a half a block up on your right.

+
From tonic at nondot.org Wed Nov 3 00:43:47 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 05:43:47 -0000 Subject: [llvm-commits] [www] r118154 - /www/trunk/devmtg/2010-11/LLVMHotelMap.jpg Message-ID: <20101103054348.1716F2A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 00:43:47 2010 New Revision: 118154 URL: http://llvm.org/viewvc/llvm-project?rev=118154&view=rev Log: Add hotel map. Added: www/trunk/devmtg/2010-11/LLVMHotelMap.jpg (with props) Added: www/trunk/devmtg/2010-11/LLVMHotelMap.jpg URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/LLVMHotelMap.jpg?rev=118154&view=auto ============================================================================== Binary file - no diff available. Propchange: www/trunk/devmtg/2010-11/LLVMHotelMap.jpg ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream From tonic at nondot.org Wed Nov 3 00:48:33 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 05:48:33 -0000 Subject: [llvm-commits] [www] r118155 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101103054833.3F6662A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 00:48:33 2010 New Revision: 118155 URL: http://llvm.org/viewvc/llvm-project?rev=118155&view=rev Log: Add formatting. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118155&r1=118154&r2=118155&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 00:48:33 2010 @@ -57,11 +57,19 @@

Directions From San Jose Airport (Approximately 8 mins):
-Head southeast on Terminal Dr toward Airport Pkwy. Continue onto Airport Blvd. -Continue onto Angelo Way. Slight left at Airport Blvd. Slight left to stay on Airport Blvd. Turn right to merge onto CA-87 S toward I-280/Downtown. Take exit 6A for Park Ave toward San Carlos St/CA-82. -Turn left at Park Ave. Take the 1st right onto Woz Way. Turn left at W San Carlos St. -Take the 1st right onto S Almaden Blvd. Make U Turn - Destination on the right - +
+Head southeast on Terminal Dr toward Airport Pkwy.
+Continue onto Airport Blvd.
+Continue onto Angelo Way.
+Slight left at Airport Blvd.
+Slight left to stay on Airport Blvd.
+Turn right to merge onto CA-87 S toward I-280/Downtown.
+Take exit 6A for Park Ave toward San Carlos St/CA-82.
+Turn left at Park Ave. Take the 1st right onto Woz Way.
+Turn left at W San Carlos St.
+Take the 1st right onto S Almaden Blvd.
+Make U Turn - Destination on the right
+		>

Agenda
From tonic at nondot.org Wed Nov 3 00:50:09 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 05:50:09 -0000 Subject: [llvm-commits] [www] r118156 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101103055009.EC6262A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 00:50:09 2010 New Revision: 118156 URL: http://llvm.org/viewvc/llvm-project?rev=118156&view=rev Log: More formatting. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118156&r1=118155&r2=118156&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 00:50:09 2010 @@ -55,8 +55,8 @@

-Directions From San Jose Airport (Approximately 8 mins): -
+Directions From San Jose Airport
+(Approximately 8 mins)
Head southeast on Terminal Dr toward Airport Pkwy.
Continue onto Airport Blvd.
@@ -69,7 +69,7 @@ Turn left at W San Carlos St.
Take the 1st right onto S Almaden Blvd.
Make U Turn - Destination on the right
-		>
+

Agenda
From tonic at nondot.org Wed Nov 3 00:56:30 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 05:56:30 -0000 Subject: [llvm-commits] [www] r118157 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101103055630.31EB62A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 00:56:30 2010 New Revision: 118157 URL: http://llvm.org/viewvc/llvm-project?rev=118157&view=rev Log: Update speaker. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118157&r1=118156&r2=118157&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 00:56:30 2010 @@ -73,7 +73,7 @@

Agenda
- +

@@ -102,10 +102,11 @@ - +
TimeTalkLocation
Connecting the EDG front-end to LLVM
Renato Golin, ARM		Winchester Ballroom
Building Linux BOF
Taylor Simpson, QuIC		Market Room
4:30 - 5:10LLVM for Open Shading Language
Larry Gritz, Sony Pictures Imageworks		Almaden Ballroom
Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
James Kempf, Ericsson Research Silicon Valley		Winchester Room
Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
Erik Rubow, Ericsson Research Silicon Valley		Winchester Room
Optimizations BOF
Taylor Simpson, QuIC		Market Room
6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required)
+

Dinner

From tonic at nondot.org Wed Nov 3 01:25:13 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 06:25:13 -0000 Subject: [llvm-commits] [www] r118159 - in /www/trunk: devmtg/2010-11/index.html llvm.css Message-ID: <20101103062513.DED3C2A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 01:25:13 2010 New Revision: 118159 URL: http://llvm.org/viewvc/llvm-project?rev=118159&view=rev Log: Work on css style for agenda table for devmtg. Modified: www/trunk/devmtg/2010-11/index.html www/trunk/llvm.css Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118159&r1=118158&r2=118159&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 01:25:13 2010 @@ -74,7 +74,7 @@

Agenda

- +
Modified: www/trunk/llvm.css URL: http://llvm.org/viewvc/llvm-project/www/trunk/llvm.css?rev=118159&r1=118158&r2=118159&view=diff ============================================================================== --- www/trunk/llvm.css (original) +++ www/trunk/llvm.css Wed Nov 3 01:25:13 2010 @@ -99,3 +99,13 @@ TABLE.www { text-align: left; border: 2px solid black; border-collapse: collapse; margin-top: 1em; margin-left: 1em; margin-right: 1em; margin-bottom: 1em; } + +/* Dev Meeting Agenda */ +table.devmtg { + border: 1px solid #cef;} +th.devmtg { + font-weight: bold; + background-color: #58ACFA; + border-bottom: 1px solid #58ACFA; } +tr.devmtg { + background-color: #A9D0F5} From evan.cheng at apple.com Wed Nov 3 01:34:55 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Nov 2010 06:34:55 -0000 Subject: [llvm-commits] [llvm] r118160 - in /llvm/trunk: include/llvm/Target/TargetSelectionDAG.td lib/Target/ARM/ARM.td lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMSchedule.td lib/Target/ARM/ARMScheduleA8.td lib/Target/ARM/ARMScheduleA9.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h test/CodeGen/ARM/prefetch.ll Message-ID: <20101103063455.F14072A6C12C@llvm.org> Author: evancheng Date: Wed Nov 3 01:34:55 2010 New Revision: 118160 URL: http://llvm.org/viewvc/llvm-project?rev=118160&view=rev Log: Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMSchedule.td llvm/trunk/lib/Target/ARM/ARMScheduleA8.td llvm/trunk/lib/Target/ARM/ARMScheduleA9.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/test/CodeGen/ARM/prefetch.ll Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Wed Nov 3 01:34:55 2010 @@ -183,18 +183,18 @@ SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> ]>; -def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch +def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> ]>; -def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier +def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, SDTCisInt<0> ]>; -def STDAtomic3 : SDTypeProfile<1, 3, [ +def SDTAtomic3 : SDTypeProfile<1, 3, [ SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> ]>; -def STDAtomic2 : SDTypeProfile<1, 2, [ +def SDTAtomic2 : SDTypeProfile<1, 2, [ SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> ]>; @@ -374,35 +374,35 @@ def trap : SDNode<"ISD::TRAP" , SDTNone, [SDNPHasChain, SDNPSideEffect]>; -def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, +def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; -def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, +def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, [SDNPHasChain, SDNPSideEffect]>; -def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, +def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, +def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, +def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, +def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, +def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, +def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, +def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, +def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, +def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, +def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, +def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; -def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, +def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; // Do not use ld, st directly. Use load, extload, sextload, zextload, store, Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Nov 3 01:34:55 2010 @@ -64,6 +64,9 @@ def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", "Prefer 32-bit Thumb instrs">; +// Multiprocessing extension. +def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", + "Supports Multiprocessing extension">; // ARM architectures. def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T", Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 01:34:55 2010 @@ -598,10 +598,7 @@ setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); - // ARM v5TE+ and Thumb2 has preload instructions. - if (Subtarget->isThumb2() || - (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())) - setOperationAction(ISD::PREFETCH, MVT::Other, Legal); + setOperationAction(ISD::PREFETCH, MVT::Other, Custom); // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. if (!Subtarget->hasV6Ops()) { @@ -777,6 +774,8 @@ case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; + case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; + case ARMISD::VCEQ: return "ARMISD::VCEQ"; case ARMISD::VCGE: return "ARMISD::VCGE"; case ARMISD::VCGEU: return "ARMISD::VCGEU"; @@ -2060,6 +2059,31 @@ DAG.getConstant(DMBOpt, MVT::i32)); } +static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, + const ARMSubtarget *Subtarget) { + // ARM pre v5TE and Thumb1 does not have preload instructions. + if (!(Subtarget->isThumb2() || + (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) + // Just preserve the chain. + return Op.getOperand(0); + + DebugLoc dl = Op.getDebugLoc(); + unsigned Flavor = cast(Op.getOperand(3))->getZExtValue(); + if (Flavor != 3) { + if (!Subtarget->hasV7Ops()) + return Op.getOperand(0); + else if (Flavor == 2 && !Subtarget->hasMPExtension()) + return Op.getOperand(0); + } + + if (Subtarget->isThumb()) + // Invert the bits. + Flavor = ~Flavor & 0x3; + + return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), + Op.getOperand(1), DAG.getConstant(Flavor, MVT::i32)); +} + static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); ARMFunctionInfo *FuncInfo = MF.getInfo(); @@ -3842,6 +3866,7 @@ case ISD::BR_JT: return LowerBR_JT(Op, DAG); case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); + case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); case ISD::FP_TO_SINT: Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Nov 3 01:34:55 2010 @@ -83,6 +83,8 @@ MEMBARRIER, // Memory barrier (DMB) MEMBARRIER_MCR, // Memory barrier (MCR) + + PRELOAD, // Preload VCEQ, // Vector compare equal. VCGE, // Vector compare greater than or equal. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 3 01:34:55 2010 @@ -62,6 +62,8 @@ def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; +def SDT_ARMPRELOAD : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; + def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, @@ -130,6 +132,8 @@ [SDNPHasChain]>; def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, [SDNPHasChain]>; +def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPRELOAD, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; @@ -159,6 +163,8 @@ AssemblerPredicate; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, AssemblerPredicate; +def HasMP : Predicate<"Subtarget->hasMPExtension()">, + AssemblerPredicate; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate; @@ -988,14 +994,11 @@ // Preload signals the memory system of possible future data/instruction access. // These are for disassembly only. -// -// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. -// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. multiclass APreLoad data_read, string opc> { - def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary, + def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, !strconcat(opc, "\t$addr"), - [(prefetch addrmode_imm12:$addr, imm, (i32 data_read))]> { + [(ARMPreload addrmode_imm12:$addr, (i32 data_read))]> { bits<4> Rt; bits<17> addr; let Inst{31-26} = 0b111101; @@ -1009,9 +1012,9 @@ let Inst{11-0} = addr{11-0}; // imm12 } - def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary, + def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, !strconcat(opc, "\t$shift"), - [(prefetch ldst_so_reg:$shift, imm, (i32 data_read))]> { + [(ARMPreload ldst_so_reg:$shift, (i32 data_read))]> { bits<4> Rt; bits<17> shift; let Inst{31-26} = 0b111101; @@ -1025,9 +1028,9 @@ } } -defm PLD : APreLoad<3, "pld">; -defm PLDW : APreLoad<2, "pldw">; -defm PLI : APreLoad<1, "pli">; +defm PLD : APreLoad<3, "pld">, Requires<[IsARM]>; +defm PLDW : APreLoad<2, "pldw">, Requires<[IsARM,HasV7,HasMP]>; +defm PLI : APreLoad<1, "pli">, Requires<[IsARM,HasV7]>; def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, "setend\t$end", Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Nov 3 01:34:55 2010 @@ -1171,67 +1171,66 @@ // T2Ipl (Preload Data/Instruction) signals the memory system of possible future // data/instruction access. These are for disassembly only. -// -// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. -// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. -multiclass T2Ipl data_read, string opc> { +// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), +// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). +multiclass T2Ipl instr_write, string opc> { - def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_iLoad_i, opc, + def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, "\t$addr", - [(prefetch t2addrmode_imm12:$addr, imm, (i32 data_read))]> { + [(ARMPreload t2addrmode_imm12:$addr, (i32 instr_write))]> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr; + let Inst{24} = instr_write{1}; let Inst{23} = 1; // U = 1 let Inst{22} = 0; - let Inst{21} = write; + let Inst{21} = instr_write{0}; let Inst{20} = 1; let Inst{15-12} = 0b1111; } - def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_iLoad_i, opc, + def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc, "\t$addr", - [(prefetch t2addrmode_imm8:$addr, imm, (i32 data_read))]> { + [(ARMPreload t2addrmode_imm8:$addr, (i32 instr_write))]> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr; + let Inst{24} = instr_write{1}; let Inst{23} = 0; // U = 0 let Inst{22} = 0; - let Inst{21} = write; + let Inst{21} = instr_write{0}; let Inst{20} = 1; let Inst{15-12} = 0b1111; let Inst{11-8} = 0b1100; } - def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_iLoad_i, opc, + def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, "\t$addr", - [(prefetch t2addrmode_so_reg:$addr, imm, (i32 data_read))]> { + [(ARMPreload t2addrmode_so_reg:$addr, (i32 instr_write))]> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr; + let Inst{24} = instr_write{1}; let Inst{23} = 0; // add = TRUE for T1 let Inst{22} = 0; - let Inst{21} = write; + let Inst{21} = instr_write{0}; let Inst{20} = 1; let Inst{15-12} = 0b1111; let Inst{11-6} = 0000000; } let isCodeGenOnly = 1 in - def pci : T2Ipc<(outs), (ins i32imm:$addr), IIC_iLoad_i, opc, + def pci : T2Ipc<(outs), (ins i32imm:$addr), IIC_Preload, opc, "\t$addr", []> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr; + let Inst{24} = instr_write{1}; let Inst{23} = ?; // add = (U == 1) let Inst{22} = 0; - let Inst{21} = write; + let Inst{21} = instr_write{0}; let Inst{20} = 1; let Inst{19-16} = 0b1111; // Rn = 0b1111 let Inst{15-12} = 0b1111; } } -defm t2PLD : T2Ipl<0, 0, 3, "pld">; -defm t2PLDW : T2Ipl<0, 1, 2, "pldw">; -defm t2PLI : T2Ipl<1, 0, 1, "pli">; +defm t2PLD : T2Ipl<0, "pld">, Requires<[IsThumb2]>; +defm t2PLDW : T2Ipl<1, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; +defm t2PLI : T2Ipl<2, "pli">, Requires<[IsThumb2,HasV7]>; //===----------------------------------------------------------------------===// // Load / store multiple Instructions. Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original) +++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Wed Nov 3 01:34:55 2010 @@ -90,6 +90,7 @@ def IIC_iStore_d_ru : InstrItinClass; def IIC_iStore_m : InstrItinClass<0>; // micro-coded def IIC_iStore_mu : InstrItinClass<0>; // micro-coded +def IIC_Preload : InstrItinClass; def IIC_Br : InstrItinClass; def IIC_fpSTAT : InstrItinClass; def IIC_fpUNA32 : InstrItinClass; Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Wed Nov 3 01:34:55 2010 @@ -225,6 +225,10 @@ InstrItinData, InstrStage<2, [A8_LSPipe]>], [2]>, + // + // Preload + InstrItinData], [2, 2]>, + // Branch // // no delay slots, so the latency of a branch is unimportant Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Wed Nov 3 01:34:55 2010 @@ -402,6 +402,10 @@ InstrStage<1, [A9_AGU], 0>, InstrStage<2, [A9_LSUnit]>], [2]>, + // + // Preload + InstrItinData], [1, 1]>, + // Branch // // no delay slots, so the latency of a branch is unimportant Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Nov 3 01:34:55 2010 @@ -51,6 +51,7 @@ , HasT2ExtractPack(false) , HasDataBarrier(false) , Pref32BitThumb(false) + , HasMPExtension(false) , FPOnlySP(false) , AllowsUnalignedMem(false) , stackAlignment(4) Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Nov 3 01:34:55 2010 @@ -106,6 +106,10 @@ /// over 16-bit ones. bool Pref32BitThumb; + /// HasMPExtension - True if the subtarget supports Multiprocessing + /// extension (ARMv7 only). + bool HasMPExtension; + /// FPOnlySP - If true, the floating point unit only supports single /// precision. bool FPOnlySP; @@ -176,6 +180,7 @@ bool isFPBrccSlow() const { return SlowFPBrcc; } bool isFPOnlySP() const { return FPOnlySP; } bool prefers32BitThumb() const { return Pref32BitThumb; } + bool hasMPExtension() const { return HasMPExtension; } bool hasFP16() const { return HasFP16; } bool hasD16() const { return HasD16; } Modified: llvm/trunk/test/CodeGen/ARM/prefetch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=118160&r1=118159&r2=118160&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/prefetch.ll (original) +++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Wed Nov 3 01:34:55 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v5te | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+v7a,+mp | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7a,+mp | FileCheck %s -check-prefix=ARM ; rdar://8601536 define void @t1(i8* %ptr) nounwind { From tonic at nondot.org Wed Nov 3 01:37:36 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 06:37:36 -0000 Subject: [llvm-commits] [www] r118161 - in /www/trunk: devmtg/2010-11/index.html llvm.css Message-ID: <20101103063736.1F0762A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 01:37:35 2010 New Revision: 118161 URL: http://llvm.org/viewvc/llvm-project?rev=118161&view=rev Log: Tweak css style Modified: www/trunk/devmtg/2010-11/index.html www/trunk/llvm.css Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118161&r1=118160&r2=118161&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 01:37:35 2010 @@ -74,37 +74,37 @@
Agenda

-

TimeTalkLocation
8:00 - 8:45BreakfastMarket Room
+
- + - + - + - + - + - + - + - + - + - + - + - + - + - +
TimeTalkLocation
8:00 - 8:45BreakfastMarket Room
8:45 - 9:00Welcome
Chris Lattner, Apple Inc.		Almaden Ballroom
8:45 - 9:00Welcome
Chris Lattner, Apple Inc.		Almaden Ballroom
9:00 - 9:40Portable Native Client
David Sehr, Google		Almaden Ballroom
9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
Micah Villmow, AMD Inc.		Almaden Ballroom
9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
Micah Villmow, AMD Inc.		Almaden Ballroom
Implementing Include-What-You-Use using clang
Craig Silverstein, Google		Winchester Room
Debugging Information BOF
Devang Patel, Apple Inc.		Market Room
Debugging Information BOF
Devang Patel, Apple Inc.		Market Room
10:20 - 10:50BreakMarket Room
10:50 - 11:30libclang: Thinking Beyond the Compiler
Doug Gregor, Apple Inc.		Almaden Ballroom
10:50 - 11:30libclang: Thinking Beyond the Compiler
Doug Gregor, Apple Inc.		Almaden Ballroom
Polly - Polyhedral optimizations in LLVM
Tobias Grosser , University of Passau		Winchester Room
11:30 - 12:10libc++: A Standard Library for C++0x
Howard Hinnant, Apple Inc.		Almaden Room
11:30 - 12:10libc++: A Standard Library for C++0x
Howard Hinnant, Apple Inc.		Almaden Room
Symbolic Crosschecking of Floating-Point and SIMD Code
Peter Collingbourne, Imperial College London		Winchester Room
12:10 - 1:20LunchMarket Room
12:10 - 1:20LunchMarket Room
1:20 - 2:00The LLVM Assembler & Machine Code Infrastructure
Daniel Dunbar, Apple Inc.		Almaden Ballroom
Creating cling, an interactive interpreter interface for clang
Axel Naumann, CERN		Winchester Room
Creating cling, an interactive interpreter interface for clang
Axel Naumann, CERN		Winchester Room
OpenCL BOF
Alasdair Grant, ARM		Market Room
2:00 - 2:40LLDB: Modular Debugging Infrastructure
Greg Clayton, Apple Inc.		Almaden Ballroom
2:00 - 2:40LLDB: Modular Debugging Infrastructure
Greg Clayton, Apple Inc.		Almaden Ballroom
The Crack Scripting Language
Michael Muller, Google		Winchester Room
ARM-MC and EABI support BOF
Renato Golin, ARM		Market Room
ARM-MC and EABI support BOF
Renato Golin, ARM		Market Room
2:40 - 3:20Hardening LLVM With Random Testing
Xuejun Yang, University of Utah		Almaden Ballroom
C-to-Verilog.com : High-level synthesis using LLVM
Nadav Rotem, Haifa University		Winchester Room
C-to-Verilog.com : High-level synthesis using LLVM
Nadav Rotem, Haifa University		Winchester Room
3:20 - 3:50BreakMarket Room
3:50 - 4:30Object Files in LLVM
Michael Spencer, Gainsville University		Almaden Ballroom
3:50 - 4:30Object Files in LLVM
Michael Spencer, Gainsville University		Almaden Ballroom
Connecting the EDG front-end to LLVM
Renato Golin, ARM		Winchester Ballroom
Building Linux BOF
Taylor Simpson, QuIC		Market Room
Building Linux BOF
Taylor Simpson, QuIC		Market Room
4:30 - 5:10LLVM for Open Shading Language
Larry Gritz, Sony Pictures Imageworks		Almaden Ballroom
Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
Erik Rubow, Ericsson Research Silicon Valley		Winchester Room
Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
Erik Rubow, Ericsson Research Silicon Valley		Winchester Room
Optimizations BOF
Taylor Simpson, QuIC		Market Room
6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required)
6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required)

Modified: www/trunk/llvm.css URL: http://llvm.org/viewvc/llvm-project/www/trunk/llvm.css?rev=118161&r1=118160&r2=118161&view=diff ============================================================================== --- www/trunk/llvm.css (original) +++ www/trunk/llvm.css Wed Nov 3 01:37:35 2010 @@ -101,11 +101,28 @@ margin-right: 1em; margin-bottom: 1em; } /* Dev Meeting Agenda */ -table.devmtg { - border: 1px solid #cef;} -th.devmtg { - font-weight: bold; - background-color: #58ACFA; - border-bottom: 1px solid #58ACFA; } -tr.devmtg { - background-color: #A9D0F5} +#devmtg +{ +font-family:"Trebuchet MS", Arial, Helvetica, sans-serif; +border-collapse:collapse; +} +#devmtg td, #devmtg th +{ +font-size:1em; +border:1px solid #045FB4; +padding:3px 7px 2px 7px; +} +#devmtg th +{ +font-size:1.1em; +text-align:left; +padding-top:5px; +padding-bottom:4px; +background-color:#045FB4; +color:#ffffff; +} +#devmtg tr.alt td +{ +color:#000000; +background-color:#81BEF7; +} From tonic at nondot.org Wed Nov 3 01:40:53 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 03 Nov 2010 06:40:53 -0000 Subject: [llvm-commits] [www] r118162 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101103064053.59C402A6C12C@llvm.org> Author: tbrethou Date: Wed Nov 3 01:40:53 2010 New Revision: 118162 URL: http://llvm.org/viewvc/llvm-project?rev=118162&view=rev Log: Tweak css style. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118162&r1=118161&r2=118162&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Nov 3 01:40:53 2010 @@ -81,30 +81,30 @@ 8:45 - 9:00Welcome
Chris Lattner, Apple Inc.Almaden Ballroom 9:00 - 9:40Portable Native Client
David Sehr, GoogleAlmaden Ballroom 9:40 - 10:20AMD OpenCL Compiler - Using LLVM to produce a cross-platform heterogeneous compiler tool chain
Micah Villmow, AMD Inc.Almaden Ballroom -Implementing Include-What-You-Use using clang
Craig Silverstein, GoogleWinchester Room +Implementing Include-What-You-Use using clang
Craig Silverstein, GoogleWinchester Room Debugging Information BOF
Devang Patel, Apple Inc.Market Room 10:20 - 10:50BreakMarket Room 10:50 - 11:30libclang: Thinking Beyond the Compiler
Doug Gregor, Apple Inc.Almaden Ballroom -Polly - Polyhedral optimizations in LLVM
Tobias Grosser , University of PassauWinchester Room -11:30 - 12:10libc++: A Standard Library for C++0x
Howard Hinnant, Apple Inc.Almaden Room +Polly - Polyhedral optimizations in LLVM
Tobias Grosser , University of PassauWinchester Room +11:30 - 12:10libc++: A Standard Library for C++0x
Howard Hinnant, Apple Inc.Almaden Room Symbolic Crosschecking of Floating-Point and SIMD Code
Peter Collingbourne, Imperial College LondonWinchester Room 12:10 - 1:20LunchMarket Room 1:20 - 2:00The LLVM Assembler & Machine Code Infrastructure
Daniel Dunbar, Apple Inc.Almaden Ballroom -Creating cling, an interactive interpreter interface for clang
Axel Naumann, CERNWinchester Room +Creating cling, an interactive interpreter interface for clang
Axel Naumann, CERNWinchester Room OpenCL BOF
Alasdair Grant, ARMMarket Room 2:00 - 2:40LLDB: Modular Debugging Infrastructure
Greg Clayton, Apple Inc.Almaden Ballroom -The Crack Scripting Language
Michael Muller, GoogleWinchester Room +The Crack Scripting Language
Michael Muller, GoogleWinchester Room ARM-MC and EABI support BOF
Renato Golin, ARMMarket Room 2:40 - 3:20Hardening LLVM With Random Testing
Xuejun Yang, University of UtahAlmaden Ballroom -C-to-Verilog.com : High-level synthesis using LLVM
Nadav Rotem, Haifa UniversityWinchester Room -3:20 - 3:50BreakMarket Room -3:50 - 4:30Object Files in LLVM
Michael Spencer, Gainsville UniversityAlmaden Ballroom +C-to-Verilog.com : High-level synthesis using LLVM
Nadav Rotem, Haifa UniversityWinchester Room +3:20 - 3:50BreakMarket Room +3:50 - 4:30Object Files in LLVM
Michael Spencer, Gainsville UniversityAlmaden Ballroom Connecting the EDG front-end to LLVM
Renato Golin, ARMWinchester Ballroom -Building Linux BOF
Taylor Simpson, QuICMarket Room -4:30 - 5:10LLVM for Open Shading Language
Larry Gritz, Sony Pictures ImageworksAlmaden Ballroom +Building Linux BOF
Taylor Simpson, QuICMarket Room +4:30 - 5:10LLVM for Open Shading Language
Larry Gritz, Sony Pictures ImageworksAlmaden Ballroom Experiences on using LLVM to compile Click packet processing code to Stanford NetFPGA hardware
Erik Rubow, Ericsson Research Silicon ValleyWinchester Room -Optimizations BOF
Taylor Simpson, QuICMarket Room -6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required) +Optimizations BOF
Taylor Simpson, QuICMarket Room +6:00 - 8:00Dinner (Paolo's Restaurant - Separate registration required)

From baldrick at free.fr Wed Nov 3 03:15:17 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Nov 2010 09:15:17 +0100 Subject: [llvm-commits] [llvm] r118089 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Path.cpp lib/System/Unix/Path.inc lib/System/Win32/Path.inc In-Reply-To: <20101102221837.AFD332A6C12C@llvm.org> References: <20101102221837.AFD332A6C12C@llvm.org> Message-ID: <4CD11A15.7010904@free.fr> Hi Mikhail, > appendSuffix: don't append a dot when the suffix is empty. why is this needed? If you want to append ".exe" shouldn't you just append ".exe" rather than passing "exe" and expecting appendSuffix to add the "."? Is "." universal? Ciao, Duncan. From baldrick at free.fr Wed Nov 3 03:16:50 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Nov 2010 08:16:50 -0000 Subject: [llvm-commits] [llvm] r118163 - /llvm/trunk/docs/TestingGuide.html Message-ID: <20101103081650.DA3EA2A6C12D@llvm.org> Author: baldrick Date: Wed Nov 3 03:16:50 2010 New Revision: 118163 URL: http://llvm.org/viewvc/llvm-project?rev=118163&view=rev Log: Fix typo, pointed out by Trevor Harmon. Modified: llvm/trunk/docs/TestingGuide.html Modified: llvm/trunk/docs/TestingGuide.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TestingGuide.html?rev=118163&r1=118162&r2=118163&view=diff ============================================================================== --- llvm/trunk/docs/TestingGuide.html (original) +++ llvm/trunk/docs/TestingGuide.html Wed Nov 3 03:16:50 2010 @@ -153,7 +153,7 @@ The more comprehensive test suite that includes whole programs in C and C++ is in the test-suite module. This module should be checked out to the llvm/projects directory (don't use another name -then the default "test-suite", for then the test suite will be run every time +than the default "test-suite", for then the test suite will be run every time you run make in the main llvm directory). When you configure the llvm module, the test-suite directory will be automatically configured. From clchiou at gmail.com Wed Nov 3 04:03:53 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Wed, 3 Nov 2010 17:03:53 +0800 Subject: [llvm-commits] [PATCH][Target/PTX] Add ptx asm streamer Message-ID: Hi, This patch adds a target-specific (ptx) asm streamer class. Most of its methods are empty for now, and will be implemented in the future. Regards, Che-Liang -------------- next part -------------- A non-text attachment was scrubbed... Name: r117227-add-ptx-mc-asm-streamer.patch Type: text/x-patch Size: 26570 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101103/966cd5be/attachment.bin From clchiou at gmail.com Wed Nov 3 04:06:19 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Wed, 3 Nov 2010 17:06:19 +0800 Subject: [llvm-commits] [PATCH][Target/PTX] Add ptx asm streamer In-Reply-To: References: Message-ID: This patch accidentally includes changes of a previous patch that this patch depends on. I am sorry for any inconvenience. On Wed, Nov 3, 2010 at 5:03 PM, Che-Liang Chiou wrote: > Hi, > > This patch adds a target-specific (ptx) asm streamer class. ?Most of > its methods are empty for now, and will be implemented in the future. > > Regards, > Che-Liang > From clchiou at gmail.com Wed Nov 3 04:13:36 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Wed, 3 Nov 2010 17:13:36 +0800 Subject: [llvm-commits] [PATCH][Target/PTX] Add MachineFunctionPass to extract number of physical register used Message-ID: Hi, This patch adds a MachineFunctionPass to extract number of physical register used. PTX requires this information and declare used register in the beginning of a function. Regards, Che-Liang -------------- next part -------------- A non-text attachment was scrubbed... Name: r117227-add-reg-counter.patch Type: text/x-patch Size: 9427 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101103/98877511/attachment.bin From clchiou at gmail.com Wed Nov 3 04:20:29 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Wed, 3 Nov 2010 17:20:29 +0800 Subject: [llvm-commits] [PATCH][Target/PTX] Add PTXAsmPrinter implementation Message-ID: Hi, This patch adds PTXAsmPrinter implementation so that it could generate code for declare function signature and local physical registers. Regards, Che-Liang -------------- next part -------------- A non-text attachment was scrubbed... Name: r117227-change-asm-printer.patch Type: text/x-patch Size: 5954 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101103/ff666d38/attachment.bin From echristo at apple.com Wed Nov 3 04:36:40 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 03 Nov 2010 09:36:40 -0000 Subject: [llvm-commits] [llvm] r118164 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20101103093640.C1E392A6C12C@llvm.org> Author: echristo Date: Wed Nov 3 04:36:40 2010 New Revision: 118164 URL: http://llvm.org/viewvc/llvm-project?rev=118164&view=rev Log: If we have an undef mask our Elt will be -1 for our access, handle this by using an undef as a pointer. Fixes rdar://8625016 Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=118164&r1=118163&r2=118164&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 3 04:36:40 2010 @@ -6190,7 +6190,7 @@ SDValue EltNo = N->getOperand(1); if (isa(EltNo)) { - unsigned Elt = cast(EltNo)->getZExtValue(); + int Elt = cast(EltNo)->getZExtValue(); bool NewLoad = false; bool BCNumEltsChanged = false; EVT VT = InVec.getValueType(); @@ -6228,7 +6228,7 @@ // Select the input vector, guarding against out of range extract vector. unsigned NumElems = VT.getVectorNumElements(); - int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); + int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); if (InVec.getOpcode() == ISD::BIT_CONVERT) @@ -6257,7 +6257,11 @@ SDValue NewPtr = LN0->getBasePtr(); unsigned PtrOff = 0; - if (Elt) { + // If Idx was -1 above, Elt is going to be -1, so just use undef as our + // new pointer. + if (Elt == -1) { + NewPtr = DAG.getUNDEF(NewPtr.getValueType()); + } else if (Elt) { PtrOff = LVT.getSizeInBits() * Elt / 8; EVT PtrType = NewPtr.getValueType(); if (TLI.isBigEndian()) From baldrick at free.fr Wed Nov 3 06:35:32 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Nov 2010 11:35:32 -0000 Subject: [llvm-commits] [llvm] r118167 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20101103113532.60B842A6C12C@llvm.org> Author: baldrick Date: Wed Nov 3 06:35:31 2010 New Revision: 118167 URL: http://llvm.org/viewvc/llvm-project?rev=118167&view=rev Log: Inside the calling convention logic LocVT is always a simple value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/include/llvm/Target/TargetCallingConv.h llvm/trunk/lib/CodeGen/CallingConvLower.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/ARM/ARMCallingConv.h llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp llvm/trunk/utils/TableGen/CallingConvEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Wed Nov 3 06:35:31 2010 @@ -60,11 +60,11 @@ EVT ValVT; /// LocVT - The type of the location being assigned to. - EVT LocVT; + MVT LocVT; public: static CCValAssign getReg(unsigned ValNo, EVT ValVT, - unsigned RegNo, EVT LocVT, + unsigned RegNo, MVT LocVT, LocInfo HTP) { CCValAssign Ret; Ret.ValNo = ValNo; @@ -78,7 +78,7 @@ } static CCValAssign getCustomReg(unsigned ValNo, EVT ValVT, - unsigned RegNo, EVT LocVT, + unsigned RegNo, MVT LocVT, LocInfo HTP) { CCValAssign Ret; Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP); @@ -87,7 +87,7 @@ } static CCValAssign getMem(unsigned ValNo, EVT ValVT, - unsigned Offset, EVT LocVT, + unsigned Offset, MVT LocVT, LocInfo HTP) { CCValAssign Ret; Ret.ValNo = ValNo; @@ -101,7 +101,7 @@ } static CCValAssign getCustomMem(unsigned ValNo, EVT ValVT, - unsigned Offset, EVT LocVT, + unsigned Offset, MVT LocVT, LocInfo HTP) { CCValAssign Ret; Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP); @@ -119,7 +119,7 @@ unsigned getLocReg() const { assert(isRegLoc()); return Loc; } unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; } - EVT getLocVT() const { return LocVT; } + MVT getLocVT() const { return LocVT; } LocInfo getLocInfo() const { return HTP; } bool isExtInLoc() const { @@ -131,14 +131,14 @@ /// CCAssignFn - This function assigns a location for Val, updating State to /// reflect the change. It returns 'true' if it failed to handle Val. typedef bool CCAssignFn(unsigned ValNo, EVT ValVT, - EVT LocVT, CCValAssign::LocInfo LocInfo, + MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); /// CCCustomFn - This function assigns a location for Val, possibly updating /// all args to reflect changes and indicates if it handled it. It must set /// isCustom if it handles the arg and returns true. typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT, - EVT &LocVT, CCValAssign::LocInfo &LocInfo, + MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); /// CCState - This class holds information needed while lowering arguments and @@ -198,7 +198,7 @@ /// AnalyzeCallOperands - Same as above except it takes vectors of types /// and argument flags. - void AnalyzeCallOperands(SmallVectorImpl &ArgVTs, + void AnalyzeCallOperands(SmallVectorImpl &ArgVTs, SmallVectorImpl &Flags, CCAssignFn Fn); @@ -209,7 +209,7 @@ /// AnalyzeCallResult - Same as above except it's specialized for calls which /// produce a single value. - void AnalyzeCallResult(EVT VT, CCAssignFn Fn); + void AnalyzeCallResult(MVT VT, CCAssignFn Fn); /// getFirstUnallocated - Return the first unallocated register in the set, or /// NumRegs if they are all allocated. @@ -285,7 +285,7 @@ // value. The size and alignment information of the argument is encoded in its // parameter attribute. void HandleByVal(unsigned ValNo, EVT ValVT, - EVT LocVT, CCValAssign::LocInfo LocInfo, + MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags); private: Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Wed Nov 3 06:35:31 2010 @@ -133,6 +133,7 @@ bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; } bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; } bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; } + bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; } bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; } bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; } @@ -280,6 +281,18 @@ } } + /// getStoreSize - Return the number of bytes overwritten by a store + /// of the specified value type. + unsigned getStoreSize() const { + return (getSizeInBits() + 7) / 8; + } + + /// getStoreSizeInBits - Return the number of bits overwritten by a store + /// of the specified value type. + unsigned getStoreSizeInBits() const { + return getStoreSize() * 8; + } + static MVT getFloatingPointVT(unsigned BitWidth) { switch (BitWidth) { default: Modified: llvm/trunk/include/llvm/Target/TargetCallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetCallingConv.h?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetCallingConv.h (original) +++ llvm/trunk/include/llvm/Target/TargetCallingConv.h Wed Nov 3 06:35:31 2010 @@ -106,14 +106,13 @@ /// struct InputArg { ArgFlagsTy Flags; - EVT VT; + MVT VT; bool Used; InputArg() : VT(MVT::Other), Used(false) {} InputArg(ArgFlagsTy flags, EVT vt, bool used) - : Flags(flags), VT(vt), Used(used) { - assert(VT.isSimple() && - "InputArg value type must be Simple!"); + : Flags(flags), Used(used) { + VT = vt.getSimpleVT(); } }; @@ -123,16 +122,15 @@ /// struct OutputArg { ArgFlagsTy Flags; - EVT VT; + MVT VT; /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...". bool IsFixed; OutputArg() : IsFixed(false) {} OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed) - : Flags(flags), VT(vt), IsFixed(isfixed) { - assert(VT.isSimple() && - "OutputArg value type must be Simple!"); + : Flags(flags), IsFixed(isfixed) { + VT = vt.getSimpleVT(); } }; } Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Wed Nov 3 06:35:31 2010 @@ -35,7 +35,7 @@ // value. The size and alignment information of the argument is encoded in its // parameter attribute. void CCState::HandleByVal(unsigned ValNo, EVT ValVT, - EVT LocVT, CCValAssign::LocInfo LocInfo, + MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags) { unsigned Align = ArgFlags.getByValAlign(); @@ -66,12 +66,12 @@ unsigned NumArgs = Ins.size(); for (unsigned i = 0; i != NumArgs; ++i) { - EVT ArgVT = Ins[i].VT; + MVT ArgVT = Ins[i].VT; ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG dbgs() << "Formal argument #" << i << " has unhandled type " - << ArgVT.getEVTString(); + << EVT(ArgVT).getEVTString(); #endif llvm_unreachable(0); } @@ -84,7 +84,7 @@ CCAssignFn Fn) { // Determine which register each value should be copied into. for (unsigned i = 0, e = Outs.size(); i != e; ++i) { - EVT VT = Outs[i].VT; + MVT VT = Outs[i].VT; ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) return false; @@ -98,12 +98,12 @@ CCAssignFn Fn) { // Determine which register each value should be copied into. for (unsigned i = 0, e = Outs.size(); i != e; ++i) { - EVT VT = Outs[i].VT; + MVT VT = Outs[i].VT; ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG dbgs() << "Return operand #" << i << " has unhandled type " - << VT.getEVTString(); + << EVT(VT).getEVTString(); #endif llvm_unreachable(0); } @@ -116,12 +116,12 @@ CCAssignFn Fn) { unsigned NumOps = Outs.size(); for (unsigned i = 0; i != NumOps; ++i) { - EVT ArgVT = Outs[i].VT; + MVT ArgVT = Outs[i].VT; ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG dbgs() << "Call operand #" << i << " has unhandled type " - << ArgVT.getEVTString(); + << EVT(ArgVT).getEVTString(); #endif llvm_unreachable(0); } @@ -130,17 +130,17 @@ /// AnalyzeCallOperands - Same as above except it takes vectors of types /// and argument flags. -void CCState::AnalyzeCallOperands(SmallVectorImpl &ArgVTs, +void CCState::AnalyzeCallOperands(SmallVectorImpl &ArgVTs, SmallVectorImpl &Flags, CCAssignFn Fn) { unsigned NumOps = ArgVTs.size(); for (unsigned i = 0; i != NumOps; ++i) { - EVT ArgVT = ArgVTs[i]; + MVT ArgVT = ArgVTs[i]; ISD::ArgFlagsTy ArgFlags = Flags[i]; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG dbgs() << "Call operand #" << i << " has unhandled type " - << ArgVT.getEVTString(); + << EVT(ArgVT).getEVTString(); #endif llvm_unreachable(0); } @@ -152,12 +152,12 @@ void CCState::AnalyzeCallResult(const SmallVectorImpl &Ins, CCAssignFn Fn) { for (unsigned i = 0, e = Ins.size(); i != e; ++i) { - EVT VT = Ins[i].VT; + MVT VT = Ins[i].VT; ISD::ArgFlagsTy Flags = Ins[i].Flags; if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { #ifndef NDEBUG dbgs() << "Call result #" << i << " has unhandled type " - << VT.getEVTString(); + << EVT(VT).getEVTString(); #endif llvm_unreachable(0); } @@ -166,11 +166,11 @@ /// AnalyzeCallResult - Same as above except it's specialized for calls which /// produce a single value. -void CCState::AnalyzeCallResult(EVT VT, CCAssignFn Fn) { +void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { #ifndef NDEBUG dbgs() << "Call result has unhandled type " - << VT.getEVTString(); + << EVT(VT).getEVTString(); #endif llvm_unreachable(0); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Nov 3 06:35:31 2010 @@ -6050,7 +6050,7 @@ unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); for (unsigned i = 0; i != NumRegs; ++i) { ISD::InputArg MyFlags; - MyFlags.VT = RegisterVT; + MyFlags.VT = RegisterVT.getSimpleVT(); MyFlags.Used = isReturnValueUsed; if (RetSExt) MyFlags.Flags.setSExt(); @@ -6086,7 +6086,7 @@ DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { assert(InVals[i].getNode() && "LowerCall emitted a null value!"); - assert(Ins[i].VT == InVals[i].getValueType() && + assert(EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerCall emitted a value with the wrong type!"); }); @@ -6247,7 +6247,7 @@ for (unsigned i = 0, e = Ins.size(); i != e; ++i) { assert(InVals[i].getNode() && "LowerFormalArguments emitted a null value!"); - assert(Ins[i].VT == InVals[i].getValueType() && + assert(EVT(Ins[i].VT) == InVals[i].getValueType() && "LowerFormalArguments emitted a value with the wrong type!"); } }); Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.h?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.h (original) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.h Wed Nov 3 06:35:31 2010 @@ -26,7 +26,7 @@ namespace llvm { // APCS f64 is in register pairs, possibly split to stack -static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail) { static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; @@ -56,7 +56,7 @@ return true; } -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -69,7 +69,7 @@ } // AAPCS f64 is in aligned register pairs -static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; @@ -104,7 +104,7 @@ return true; } -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -116,7 +116,7 @@ return true; // we handled it } -static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; @@ -136,7 +136,7 @@ return true; } -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -147,7 +147,7 @@ return true; // we handled it } -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 3 06:35:31 2010 @@ -136,8 +136,8 @@ // Utility routines. private: - bool isTypeLegal(const Type *Ty, EVT &VT); - bool isLoadTypeLegal(const Type *Ty, EVT &VT); + bool isTypeLegal(const Type *Ty, MVT &VT); + bool isLoadTypeLegal(const Type *Ty, MVT &VT); bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset); bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset); bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset); @@ -155,12 +155,12 @@ CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return); bool ProcessCallArgs(SmallVectorImpl &Args, SmallVectorImpl &ArgRegs, - SmallVectorImpl &ArgVTs, + SmallVectorImpl &ArgVTs, SmallVectorImpl &ArgFlags, SmallVectorImpl &RegArgs, CallingConv::ID CC, unsigned &NumBytes); - bool FinishCall(EVT RetVT, SmallVectorImpl &UsedRegs, + bool FinishCall(MVT RetVT, SmallVectorImpl &UsedRegs, const Instruction *I, CallingConv::ID CC, unsigned &NumBytes); bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call); @@ -523,7 +523,7 @@ // Don't handle dynamic allocas. if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; - EVT VT; + MVT VT; if (!isLoadTypeLegal(AI->getType(), VT)) return false; DenseMap::iterator SI = @@ -545,18 +545,19 @@ return 0; } -bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { - VT = TLI.getValueType(Ty, true); +bool ARMFastISel::isTypeLegal(const Type *Ty, MVT &VT) { + EVT evt = TLI.getValueType(Ty, true); // Only handle simple types. - if (VT == MVT::Other || !VT.isSimple()) return false; + if (evt == MVT::Other || !evt.isSimple()) return false; + VT = evt.getSimpleVT(); // Handle all legal types, i.e. a register that will directly hold this // value. return TLI.isTypeLegal(VT); } -bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) { +bool ARMFastISel::isLoadTypeLegal(const Type *Ty, MVT &VT) { if (isTypeLegal(Ty, VT)) return true; // If this is a type than can be sign or zero-extended to a basic operation @@ -785,7 +786,7 @@ bool ARMFastISel::SelectLoad(const Instruction *I) { // Verify we have a legal type before going any further. - EVT VT; + MVT VT; if (!isLoadTypeLegal(I->getType(), VT)) return false; @@ -868,7 +869,7 @@ unsigned SrcReg = 0; // Yay type legalization - EVT VT; + MVT VT; if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) return false; @@ -949,7 +950,7 @@ // TODO: Factor this out. if (const CmpInst *CI = dyn_cast(BI->getCondition())) { if (CI->hasOneUse() && (CI->getParent() == I->getParent())) { - EVT VT; + MVT VT; const Type *Ty = CI->getOperand(0)->getType(); if (!isTypeLegal(Ty, VT)) return false; @@ -960,7 +961,7 @@ unsigned CmpOpc; unsigned CondReg; - switch (VT.getSimpleVT().SimpleTy) { + switch (VT.SimpleTy) { default: return false; // TODO: Verify compares. case MVT::f32: @@ -1027,7 +1028,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) { const CmpInst *CI = cast(I); - EVT VT; + MVT VT; const Type *Ty = CI->getOperand(0)->getType(); if (!isTypeLegal(Ty, VT)) return false; @@ -1038,7 +1039,7 @@ unsigned CmpOpc; unsigned CondReg; - switch (VT.getSimpleVT().SimpleTy) { + switch (VT.SimpleTy) { default: return false; // TODO: Verify compares. case MVT::f32: @@ -1135,7 +1136,7 @@ // Make sure we have VFP. if (!Subtarget->hasVFP2()) return false; - EVT DstVT; + MVT DstVT; const Type *Ty = I->getType(); if (!isTypeLegal(Ty, DstVT)) return false; @@ -1165,7 +1166,7 @@ // Make sure we have VFP. if (!Subtarget->hasVFP2()) return false; - EVT DstVT; + MVT DstVT; const Type *RetTy = I->getType(); if (!isTypeLegal(RetTy, DstVT)) return false; @@ -1195,12 +1196,12 @@ } bool ARMFastISel::SelectSelect(const Instruction *I) { - EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); - if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) + MVT VT; + if (!isTypeLegal(I->getType(), VT)) return false; // Things need to be register sized for register moves. - if (VT.getSimpleVT().SimpleTy != MVT::i32) return false; + if (VT != MVT::i32) return false; const TargetRegisterClass *RC = TLI.getRegClassFor(VT); unsigned CondReg = getRegForValue(I->getOperand(0)); @@ -1223,7 +1224,7 @@ } bool ARMFastISel::SelectSDiv(const Instruction *I) { - EVT VT; + MVT VT; const Type *Ty = I->getType(); if (!isTypeLegal(Ty, VT)) return false; @@ -1251,7 +1252,7 @@ } bool ARMFastISel::SelectSRem(const Instruction *I) { - EVT VT; + MVT VT; const Type *Ty = I->getType(); if (!isTypeLegal(Ty, VT)) return false; @@ -1360,7 +1361,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl &Args, SmallVectorImpl &ArgRegs, - SmallVectorImpl &ArgVTs, + SmallVectorImpl &ArgVTs, SmallVectorImpl &ArgFlags, SmallVectorImpl &RegArgs, CallingConv::ID CC, @@ -1382,7 +1383,7 @@ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; unsigned Arg = ArgRegs[VA.getValNo()]; - EVT ArgVT = ArgVTs[VA.getValNo()]; + MVT ArgVT = ArgVTs[VA.getValNo()]; // We don't handle NEON parameters yet. if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() > 64) @@ -1422,9 +1423,8 @@ break; } case CCValAssign::BCvt: { - unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), - VA.getLocVT().getSimpleVT(), - ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false); + unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BIT_CONVERT, Arg, + /*TODO: Kill=*/false); assert(BC != 0 && "Failed to emit a bitcast!"); Arg = BC; ArgVT = VA.getLocVT(); @@ -1466,7 +1466,7 @@ return true; } -bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl &UsedRegs, +bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl &UsedRegs, const Instruction *I, CallingConv::ID CC, unsigned &NumBytes) { // Issue CALLSEQ_END @@ -1476,13 +1476,13 @@ .addImm(NumBytes).addImm(0)); // Now the return value. - if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { + if (RetVT != MVT::isVoid) { SmallVector RVLocs; CCState CCInfo(CC, false, TM, RVLocs, *Context); CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true)); // Copy all of the result registers out of their specified physreg. - if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) { + if (RVLocs.size() == 2 && RetVT == MVT::f64) { // For this move we copy into two registers and then move into the // double fp reg we want. EVT DestVT = RVLocs[0].getValVT(); @@ -1591,7 +1591,7 @@ // Handle *simple* calls for now. const Type *RetTy = I->getType(); - EVT RetVT; + MVT RetVT; if (RetTy->isVoidTy()) RetVT = MVT::isVoid; else if (!isTypeLegal(RetTy, RetVT)) @@ -1603,7 +1603,7 @@ // Set up the argument vectors. SmallVector Args; SmallVector ArgRegs; - SmallVector ArgVTs; + SmallVector ArgVTs; SmallVector ArgFlags; Args.reserve(I->getNumOperands()); ArgRegs.reserve(I->getNumOperands()); @@ -1615,7 +1615,7 @@ if (Arg == 0) return false; const Type *ArgTy = Op->getType(); - EVT ArgVT; + MVT ArgVT; if (!isTypeLegal(ArgTy, ArgVT)) return false; ISD::ArgFlagsTy Flags; @@ -1685,7 +1685,7 @@ // Handle *simple* calls for now. const Type *RetTy = I->getType(); - EVT RetVT; + MVT RetVT; if (RetTy->isVoidTy()) RetVT = MVT::isVoid; else if (!isTypeLegal(RetTy, RetVT)) @@ -1698,7 +1698,7 @@ // Set up the argument vectors. SmallVector Args; SmallVector ArgRegs; - SmallVector ArgVTs; + SmallVector ArgVTs; SmallVector ArgFlags; Args.reserve(CS.arg_size()); ArgRegs.reserve(CS.arg_size()); @@ -1725,7 +1725,7 @@ return false; const Type *ArgTy = (*i)->getType(); - EVT ArgVT; + MVT ArgVT; if (!isTypeLegal(ArgTy, ArgVT)) return false; unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -469,7 +469,7 @@ #include "MBlazeGenCallingConv.inc" static bool CC_MBlaze2(unsigned ValNo, EVT ValVT, - EVT LocVT, CCValAssign::LocInfo LocInfo, + MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { static const unsigned RegsSize=6; static const unsigned IntRegs[] = { Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -366,7 +366,7 @@ unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; if (ObjSize > 2) { errs() << "LowerFormalArguments Unhandled argument type: " - << VA.getLocVT().getSimpleVT().SimpleTy + << EVT(VA.getLocVT()).getEVTString() << "\n"; } // Create the frame index object for this incoming parameter... Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -630,7 +630,7 @@ //===----------------------------------------------------------------------===// static bool CC_MipsO32(unsigned ValNo, EVT ValVT, - EVT LocVT, CCValAssign::LocInfo LocInfo, + MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { static const unsigned IntRegsSize=4, FloatRegsSize=2; @@ -696,7 +696,7 @@ } static bool CC_MipsO32_VarArgs(unsigned ValNo, EVT ValVT, - EVT LocVT, CCValAssign::LocInfo LocInfo, + MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { static const unsigned IntRegsSize=4; Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -127,7 +127,7 @@ i->reset(); for (int i = 0, e = Ins.size(); i != e; ++ i) { - MVT::SimpleValueType VT = Ins[i].VT.getSimpleVT().SimpleTy; + MVT::SimpleValueType VT = Ins[i].VT.SimpleTy; struct argmap_entry *entry = std::find(argmap, argmap + array_lengthof(argmap), VT); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -38,17 +38,17 @@ #include "llvm/DerivedTypes.h" using namespace llvm; -static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, - EVT &LocVT, + MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, - EVT &LocVT, + MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); @@ -1443,7 +1443,7 @@ #include "PPCGenCallingConv.inc" -static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, +static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -1451,7 +1451,7 @@ } static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, - EVT &LocVT, + MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -1478,7 +1478,7 @@ } static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, - EVT &LocVT, + MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -2774,7 +2774,7 @@ unsigned NumArgs = Outs.size(); for (unsigned i = 0; i != NumArgs; ++i) { - EVT ArgVT = Outs[i].VT; + MVT ArgVT = Outs[i].VT; ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; bool Result; @@ -2789,7 +2789,7 @@ if (Result) { #ifndef NDEBUG errs() << "Call operand #" << i << " has unhandled type " - << ArgVT.getEVTString() << "\n"; + << EVT(ArgVT).getEVTString() << "\n"; #endif llvm_unreachable(0); } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -287,7 +287,7 @@ // Count the size of the outgoing arguments. unsigned ArgsSize = 0; for (unsigned i = 0, e = Outs.size(); i != e; ++i) { - switch (Outs[i].VT.getSimpleVT().SimpleTy) { + switch (Outs[i].VT.SimpleTy) { default: llvm_unreachable("Unknown value type!"); case MVT::i1: case MVT::i8: Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Nov 3 06:35:31 2010 @@ -132,17 +132,18 @@ (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 } - bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); + bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false); }; } // end anonymous namespace. -bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { - VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); - if (VT == MVT::Other || !VT.isSimple()) +bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) { + EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true); + if (evt == MVT::Other || !evt.isSimple()) // Unhandled type. Halt "fast" selection and bail. return false; - + + VT = evt.getSimpleVT(); // For now, require SSE/SSE2 for performing floating-point operations, // since x87 requires additional work. if (VT == MVT::f64 && !X86ScalarSSEf64) @@ -639,7 +640,7 @@ /// X86SelectStore - Select and emit code to implement store instructions. bool X86FastISel::X86SelectStore(const Instruction *I) { - EVT VT; + MVT VT; if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) return false; @@ -740,7 +741,7 @@ /// X86SelectLoad - Select and emit code to implement load instructions. /// bool X86FastISel::X86SelectLoad(const Instruction *I) { - EVT VT; + MVT VT; if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) return false; @@ -823,7 +824,7 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) { const CmpInst *CI = cast(I); - EVT VT; + MVT VT; if (!isTypeLegal(I->getOperand(0)->getType(), VT)) return false; @@ -1112,8 +1113,8 @@ return false; } - EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); - if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) + MVT VT; + if (!isTypeLegal(I->getType(), VT)) return false; unsigned Op0Reg = getRegForValue(I->getOperand(0)); @@ -1148,8 +1149,8 @@ } bool X86FastISel::X86SelectSelect(const Instruction *I) { - EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); - if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) + MVT VT; + if (!isTypeLegal(I->getType(), VT)) return false; // We only use cmov here, if we don't have a cmov instruction bail. @@ -1157,13 +1158,13 @@ unsigned Opc = 0; const TargetRegisterClass *RC = NULL; - if (VT.getSimpleVT() == MVT::i16) { + if (VT == MVT::i16) { Opc = X86::CMOVE16rr; RC = &X86::GR16RegClass; - } else if (VT.getSimpleVT() == MVT::i32) { + } else if (VT == MVT::i32) { Opc = X86::CMOVE32rr; RC = &X86::GR32RegClass; - } else if (VT.getSimpleVT() == MVT::i64) { + } else if (VT == MVT::i64) { Opc = X86::CMOVE64rr; RC = &X86::GR64RegClass; } else { @@ -1314,7 +1315,7 @@ assert(CI && "Non-constant type in Intrinsic::objectsize?"); - EVT VT; + MVT VT; if (!isTypeLegal(Ty, VT)) return false; @@ -1360,7 +1361,7 @@ const Type *RetTy = cast(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); - EVT VT; + MVT VT; if (!isTypeLegal(RetTy, VT)) return false; @@ -1444,7 +1445,7 @@ // Handle *simple* calls for now. const Type *RetTy = CS.getType(); - EVT RetVT; + MVT RetVT; if (RetTy->isVoidTy()) RetVT = MVT::isVoid; else if (!isTypeLegal(RetTy, RetVT, true)) @@ -1474,7 +1475,7 @@ // Deal with call operands first. SmallVector ArgVals; SmallVector Args; - SmallVector ArgVTs; + SmallVector ArgVTs; SmallVector ArgFlags; Args.reserve(CS.arg_size()); ArgVals.reserve(CS.arg_size()); @@ -1500,7 +1501,7 @@ return false; const Type *ArgTy = (*i)->getType(); - EVT ArgVT; + MVT ArgVT; if (!isTypeLegal(ArgTy, ArgVT)) return false; unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); @@ -1577,7 +1578,7 @@ break; } case CCValAssign::BCvt: { - unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), + unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(), ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false); assert(BC != 0 && "Failed to emit a bitcast!"); Arg = BC; @@ -1680,7 +1681,7 @@ // Now handle call return value (if any). SmallVector UsedRegs; - if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { + if (RetVT != MVT::isVoid) { SmallVector RVLocs; CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); @@ -1794,14 +1795,14 @@ } unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) { - EVT VT; + MVT VT; if (!isTypeLegal(C->getType(), VT)) return false; // Get opcode and regclass of the output for the given load instruction. unsigned Opc = 0; const TargetRegisterClass *RC = NULL; - switch (VT.getSimpleVT().SimpleTy) { + switch (VT.SimpleTy) { default: return false; case MVT::i8: Opc = X86::MOV8rm; Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Nov 3 06:35:31 2010 @@ -1065,7 +1065,7 @@ unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; if (ObjSize > StackSlotSize) { errs() << "LowerFormalArguments Unhandled argument type: " - << (unsigned)VA.getLocVT().getSimpleVT().SimpleTy + << EVT(VA.getLocVT()).getEVTString() << "\n"; } // Create the frame index object for this incoming parameter... Modified: llvm/trunk/utils/TableGen/CallingConvEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CallingConvEmitter.cpp?rev=118167&r1=118166&r2=118167&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CallingConvEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/CallingConvEmitter.cpp Wed Nov 3 06:35:31 2010 @@ -28,7 +28,7 @@ O << "static bool " << CCs[i]->getName() << "(unsigned ValNo, EVT ValVT,\n" << std::string(CCs[i]->getName().size()+13, ' ') - << "EVT LocVT, CCValAssign::LocInfo LocInfo,\n" + << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(CCs[i]->getName().size()+13, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State);\n"; } @@ -46,7 +46,7 @@ O << "\n\nstatic bool " << CC->getName() << "(unsigned ValNo, EVT ValVT,\n" << std::string(CC->getName().size()+13, ' ') - << "EVT LocVT, CCValAssign::LocInfo LocInfo,\n" + << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(CC->getName().size()+13, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n"; // Emit all of the actions, in order. @@ -163,12 +163,12 @@ O << Size << ", "; else O << "\n" << IndentStr << " State.getTarget().getTargetData()" - "->getTypeAllocSize(LocVT.getTypeForEVT(State.getContext())), "; + "->getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), "; if (Align) O << Align; else O << "\n" << IndentStr << " State.getTarget().getTargetData()" - "->getABITypeAlignment(LocVT.getTypeForEVT(State.getContext()))"; + "->getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))"; if (Action->isSubClassOf("CCAssignToStackWithShadow")) O << ", " << getQualifiedName(Action->getValueAsDef("ShadowReg")); O << ");\n" << IndentStr From baldrick at free.fr Wed Nov 3 06:55:04 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Nov 2010 11:55:04 -0000 Subject: [llvm-commits] [llvm] r118168 - /llvm/trunk/include/llvm/CodeGen/ValueTypes.h Message-ID: <20101103115504.0B09B2A6C12C@llvm.org> Author: baldrick Date: Wed Nov 3 06:55:03 2010 New Revision: 118168 URL: http://llvm.org/viewvc/llvm-project?rev=118168&view=rev Log: Fix a comment typo. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=118168&r1=118167&r2=118168&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Wed Nov 3 06:55:03 2010 @@ -86,7 +86,7 @@ LAST_VALUETYPE = 36, // This always remains at the end of the list. // This is the current maximum for LAST_VALUETYPE. - // EVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors + // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors // This value must be a multiple of 32. MAX_ALLOWED_VALUETYPE = 64, From baldrick at free.fr Wed Nov 3 07:17:33 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Nov 2010 12:17:33 -0000 Subject: [llvm-commits] [llvm] r118169 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/Target/TargetLowering.h include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/ARM/ARMFastISel.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp Message-ID: <20101103121734.238512A6C12C@llvm.org> Author: baldrick Date: Wed Nov 3 07:17:33 2010 New Revision: 118169 URL: http://llvm.org/viewvc/llvm-project?rev=118169&view=rev Log: Simplify uses of MVT and EVT. An MVT can be compared directly with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Nov 3 07:17:33 2010 @@ -528,7 +528,7 @@ /// to which the flag operand points. Otherwise return NULL. SDNode *getFlaggedNode() const { if (getNumOperands() != 0 && - getOperand(getNumOperands()-1).getValueType().getSimpleVT() == MVT::Flag) + getOperand(getNumOperands()-1).getValueType() == MVT::Flag) return getOperand(getNumOperands()-1).getNode(); return 0; } Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Nov 3 07:17:33 2010 @@ -435,7 +435,7 @@ /// for it. LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { assert(ExtType < ISD::LAST_LOADEXT_TYPE && - (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && + VT.getSimpleVT() < MVT::LAST_VALUETYPE && "Table isn't big enough!"); return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; } @@ -453,8 +453,8 @@ /// to be expanded to some other code sequence, or the target has a custom /// expander for it. LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { - assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && - (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && + assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE && + MemVT.getSimpleVT() < MVT::LAST_VALUETYPE && "Table isn't big enough!"); return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] [MemVT.getSimpleVT().SimpleTy]; @@ -474,8 +474,8 @@ /// for it. LegalizeAction getIndexedLoadAction(unsigned IdxMode, EVT VT) const { - assert( IdxMode < ISD::LAST_INDEXED_MODE && - ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && + assert(IdxMode < ISD::LAST_INDEXED_MODE && + VT.getSimpleVT() < MVT::LAST_VALUETYPE && "Table isn't big enough!"); unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); @@ -495,8 +495,8 @@ /// for it. LegalizeAction getIndexedStoreAction(unsigned IdxMode, EVT VT) const { - assert( IdxMode < ISD::LAST_INDEXED_MODE && - ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && + assert(IdxMode < ISD::LAST_INDEXED_MODE && + VT.getSimpleVT() < MVT::LAST_VALUETYPE && "Table isn't big enough!"); unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); @@ -1057,8 +1057,7 @@ /// not work with the specified type and indicate what to do about it. void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action) { - assert(ExtType < ISD::LAST_LOADEXT_TYPE && - (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && + assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && "Table isn't big enough!"); LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; } @@ -1067,8 +1066,7 @@ /// not work with the specified type and indicate what to do about it. void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) { - assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE && - (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE && + assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && "Table isn't big enough!"); TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; } @@ -1079,10 +1077,8 @@ /// TargetLowering.cpp void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { - assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && - IdxMode < ISD::LAST_INDEXED_MODE && - (unsigned)Action < 0xf && - "Table isn't big enough!"); + assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && + (unsigned)Action < 0xf && "Table isn't big enough!"); // Load action are kept in the upper half. IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; @@ -1094,10 +1090,8 @@ /// TargetLowering.cpp void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { - assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && - IdxMode < ISD::LAST_INDEXED_MODE && - (unsigned)Action < 0xf && - "Table isn't big enough!"); + assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && + (unsigned)Action < 0xf && "Table isn't big enough!"); // Store action are kept in the lower half. IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); @@ -1107,7 +1101,7 @@ /// supported on the target and indicate what to do about it. void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { - assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && + assert(VT < MVT::LAST_VALUETYPE && (unsigned)CC < array_lengthof(CondCodeActions) && "Table isn't big enough!"); CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Nov 3 07:17:33 2010 @@ -123,7 +123,7 @@ /// hasType - return true if this TargetRegisterClass has the ValueType vt. /// bool hasType(EVT vt) const { - for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i) + for(int i = 0; VTs[i] != MVT::Other; ++i) if (VTs[i] == vt) return true; return false; @@ -137,7 +137,7 @@ vt_iterator vt_end() const { vt_iterator I = VTs; - while (I->getSimpleVT().SimpleTy != MVT::Other) ++I; + while (*I != MVT::Other) ++I; return I; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Nov 3 07:17:33 2010 @@ -3131,8 +3131,7 @@ if (Str.empty()) { if (VT.isInteger()) return DAG.getConstant(0, VT); - else if (VT.getSimpleVT().SimpleTy == MVT::f32 || - VT.getSimpleVT().SimpleTy == MVT::f64) + else if (VT == MVT::f32 || VT == MVT::f64) return DAG.getConstantFP(0.0, VT); else if (VT.isVector()) { unsigned NumElts = VT.getVectorNumElements(); @@ -5428,7 +5427,7 @@ sys::SmartScopedLock Lock(*VTMutex); return &(*EVTs->insert(VT).first); } else { - assert(VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && + assert(VT.getSimpleVT() < MVT::LAST_VALUETYPE && "Value type out of range!"); return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy]; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Nov 3 07:17:33 2010 @@ -2232,7 +2232,7 @@ } case OPC_SwitchType: { - MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy; + MVT CurNodeVT = N.getValueType().getSimpleVT(); unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; unsigned CaseSize; while (1) { @@ -2242,10 +2242,9 @@ CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); if (CaseSize == 0) break; - MVT::SimpleValueType CaseVT = - (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; + MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; if (CaseVT == MVT::iPTR) - CaseVT = TLI.getPointerTy().SimpleTy; + CaseVT = TLI.getPointerTy(); // If the VT matches, then we will execute this case. if (CurNodeVT == CaseVT) Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 3 07:17:33 2010 @@ -371,7 +371,7 @@ // TODO: Don't worry about 64-bit now, but when this is fixed remove the // checks from the various callers. unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { - if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0; + if (VT == MVT::f64) return 0; unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, @@ -381,7 +381,7 @@ } unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { - if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0; + if (VT == MVT::i64) return 0; unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, @@ -395,7 +395,7 @@ // the combined constant into an FP reg. unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) { const APFloat Val = CFP->getValueAPF(); - bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64; + bool is64bit = VT == MVT::f64; // This checks to see if we can use VFP3 instructions to materialize // a constant, otherwise we have to go through the constant pool. @@ -432,7 +432,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { // For now 32-bit only. - if (VT.getSimpleVT().SimpleTy != MVT::i32) return false; + if (VT != MVT::i32) return false; // MachineConstantPool wants an explicit alignment. unsigned Align = TD.getPrefTypeAlignment(C->getType()); @@ -459,7 +459,7 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) { // For now 32-bit only. - if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0; + if (VT != MVT::i32) return 0; Reloc::Model RelocM = TM.getRelocationModel(); @@ -1292,8 +1292,7 @@ if (Op2 == 0) return false; unsigned Opc; - bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 || - VT.getSimpleVT().SimpleTy == MVT::i64; + bool is64bit = VT == MVT::f64 || VT == MVT::i64; switch (ISDOpcode) { default: return false; case ISD::FADD: Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Nov 3 07:17:33 2010 @@ -2240,12 +2240,11 @@ EVT VecVT = N->getValueType(0); EVT EltVT = VecVT.getVectorElementType(); unsigned NumElts = VecVT.getVectorNumElements(); - if (EltVT.getSimpleVT() == MVT::f64) { + if (EltVT == MVT::f64) { assert(NumElts == 2 && "unexpected type for BUILD_VECTOR"); return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1)); } - assert(EltVT.getSimpleVT() == MVT::f32 && - "unexpected type for BUILD_VECTOR"); + assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR"); if (NumElts == 2) return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1)); assert(NumElts == 4 && "unexpected type for BUILD_VECTOR"); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 07:17:33 2010 @@ -3832,7 +3832,7 @@ } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) && (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) { NewOpc = ARMISD::VMULLu; - } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) { + } else if (VT == MVT::v2i64) { // Fall through to expand this. It is not legal. return SDValue(); } else { Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Nov 3 07:17:33 2010 @@ -2578,7 +2578,7 @@ SDValue Op0 = Op.getOperand(0); EVT Op0VT = Op0.getValueType(); - if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) { + if (Op0VT == MVT::i128 && simpleVT == MVT::i64) { // Create shuffle mask, least significant doubleword of quadword unsigned maskHigh = 0x08090a0b; unsigned maskLow = 0x0c0d0e0f; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=118169&r1=118168&r2=118169&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 3 07:17:33 2010 @@ -4893,7 +4893,7 @@ // movssrr and movsdrr do not clear top bits. Try to use movd, movq // instead. MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; - if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && + if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { From baldrick at free.fr Wed Nov 3 09:45:05 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 03 Nov 2010 14:45:05 -0000 Subject: [llvm-commits] [llvm] r118171 - /llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20101103144505.AA6CD2A6C12C@llvm.org> Author: baldrick Date: Wed Nov 3 09:45:05 2010 New Revision: 118171 URL: http://llvm.org/viewvc/llvm-project?rev=118171&view=rev Log: Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make the code more self-documenting. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118171&r1=118170&r2=118171&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Wed Nov 3 09:45:05 2010 @@ -65,7 +65,7 @@ CallGraphSCCPass::getAnalysisUsage(AU); } - bool PointsToLocalMemory(Value *V); + bool PointsToLocalOrConstantMemory(Value *V); }; } @@ -79,10 +79,10 @@ Pass *llvm::createFunctionAttrsPass() { return new FunctionAttrs(); } -/// PointsToLocalMemory - Returns whether the given pointer value points to -/// memory that is local to the function. Global constants are considered -/// local to all functions. -bool FunctionAttrs::PointsToLocalMemory(Value *V) { +/// PointsToLocalOrConstantMemory - Returns whether the given pointer value +/// points to memory that is local to the function, with global constants being +/// considered local to all functions. +bool FunctionAttrs::PointsToLocalOrConstantMemory(Value *V) { SmallVector Worklist; unsigned MaxLookup = 8; @@ -179,7 +179,8 @@ for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); CI != CE; ++CI) { Value *Arg = *CI; - if (Arg->getType()->isPointerTy() && !PointsToLocalMemory(Arg)) + if (Arg->getType()->isPointerTy() && + !PointsToLocalOrConstantMemory(Arg)) // Writes memory. Just give up. return false; } @@ -188,11 +189,13 @@ } } else if (LoadInst *LI = dyn_cast(I)) { // Ignore non-volatile loads from local memory. - if (!LI->isVolatile() && PointsToLocalMemory(LI->getPointerOperand())) + if (!LI->isVolatile() && + PointsToLocalOrConstantMemory(LI->getPointerOperand())) continue; } else if (StoreInst *SI = dyn_cast(I)) { // Ignore non-volatile stores to local memory. - if (!SI->isVolatile() && PointsToLocalMemory(SI->getPointerOperand())) + if (!SI->isVolatile() && + PointsToLocalOrConstantMemory(SI->getPointerOperand())) continue; } From bob.wilson at apple.com Wed Nov 3 10:44:25 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 3 Nov 2010 08:44:25 -0700 Subject: [llvm-commits] [llvm] r118164 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <20101103093640.C1E392A6C12C@llvm.org> References: <20101103093640.C1E392A6C12C@llvm.org> Message-ID: <8DC866B8-CD38-400B-A938-86607F58E8A8@apple.com> This should be safe, but you could take it one step further and just return undef instead of creating a load from an undef pointer. On Nov 3, 2010, at 2:36 AM, Eric Christopher wrote: > Author: echristo > Date: Wed Nov 3 04:36:40 2010 > New Revision: 118164 > > URL: http://llvm.org/viewvc/llvm-project?rev=118164&view=rev > Log: > If we have an undef mask our Elt will be -1 for our access, handle > this by using an undef as a pointer. > > Fixes rdar://8625016 > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=118164&r1=118163&r2=118164&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 3 04:36:40 2010 > @@ -6190,7 +6190,7 @@ > SDValue EltNo = N->getOperand(1); > > if (isa(EltNo)) { > - unsigned Elt = cast(EltNo)->getZExtValue(); > + int Elt = cast(EltNo)->getZExtValue(); > bool NewLoad = false; > bool BCNumEltsChanged = false; > EVT VT = InVec.getValueType(); > @@ -6228,7 +6228,7 @@ > > // Select the input vector, guarding against out of range extract vector. > unsigned NumElems = VT.getVectorNumElements(); > - int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); > + int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); > InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); > > if (InVec.getOpcode() == ISD::BIT_CONVERT) > @@ -6257,7 +6257,11 @@ > > SDValue NewPtr = LN0->getBasePtr(); > unsigned PtrOff = 0; > - if (Elt) { > + // If Idx was -1 above, Elt is going to be -1, so just use undef as our > + // new pointer. > + if (Elt == -1) { > + NewPtr = DAG.getUNDEF(NewPtr.getValueType()); > + } else if (Elt) { > PtrOff = LVT.getSizeInBits() * Elt / 8; > EVT PtrType = NewPtr.getValueType(); > if (TLI.isBigEndian()) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From foldr at codedgers.com Wed Nov 3 11:14:07 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 03 Nov 2010 16:14:07 -0000 Subject: [llvm-commits] [llvm] r118173 - in /llvm/trunk/tools/bugpoint: OptimizerDriver.cpp ToolRunner.cpp Message-ID: <20101103161407.723032A6C12C@llvm.org> Author: foldr Date: Wed Nov 3 11:14:07 2010 New Revision: 118173 URL: http://llvm.org/viewvc/llvm-project?rev=118173&view=rev Log: 80-col violations, trailing whitespace. Modified: llvm/trunk/tools/bugpoint/OptimizerDriver.cpp llvm/trunk/tools/bugpoint/ToolRunner.cpp Modified: llvm/trunk/tools/bugpoint/OptimizerDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/OptimizerDriver.cpp?rev=118173&r1=118172&r2=118173&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/OptimizerDriver.cpp (original) +++ llvm/trunk/tools/bugpoint/OptimizerDriver.cpp Wed Nov 3 11:14:07 2010 @@ -126,12 +126,12 @@ << ErrMsg << "\n"; return(1); } - + std::string ErrInfo; tool_output_file InFile(inputFilename.c_str(), ErrInfo, raw_fd_ostream::F_Binary); - - + + if (!ErrInfo.empty()) { errs() << "Error opening bitcode file: " << inputFilename.str() << "\n"; return 1; @@ -195,7 +195,7 @@ prog = sys::Program::FindProgramByName("valgrind"); else prog = tool; - + // Redirect stdout and stderr to nowhere if SilencePasses is given sys::Path Nowhere; const sys::Path *Redirects[3] = {0, &Nowhere, &Nowhere}; Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=118173&r1=118172&r2=118173&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Wed Nov 3 11:14:07 2010 @@ -141,7 +141,7 @@ for (const char **Arg = Args; *Arg; ++Arg) OS << " " << *Arg; OS << "\n"; - + // Rerun the compiler, capturing any error messages to print them. sys::Path ErrorFilename("bugpoint.program_error_messages"); std::string ErrMsg; @@ -206,7 +206,8 @@ LLIArgs.push_back(LLIPath.c_str()); LLIArgs.push_back("-force-interpreter=true"); - for (std::vector::const_iterator i = SharedLibs.begin(), e = SharedLibs.end(); i != e; ++i) { + for (std::vector::const_iterator i = SharedLibs.begin(), + e = SharedLibs.end(); i != e; ++i) { LLIArgs.push_back("-load"); LLIArgs.push_back((*i).c_str()); } @@ -251,7 +252,7 @@ // Custom execution command implementation of AbstractIntepreter interface // // Allows using a custom command for executing the bitcode, thus allows, -// for example, to invoke a cross compiler for code generation followed by +// for example, to invoke a cross compiler for code generation followed by // a simulator that executes the generated binary. namespace { class CustomExecutor : public AbstractInterpreter { @@ -299,7 +300,7 @@ return RunProgramWithTimeout( sys::Path(ExecutionCommand), - &ProgramArgs[0], sys::Path(InputFile), sys::Path(OutputFile), + &ProgramArgs[0], sys::Path(InputFile), sys::Path(OutputFile), sys::Path(OutputFile), Timeout, MemoryLimit); } @@ -317,14 +318,14 @@ // defining a full command line as the command instead of just the // executed program. We cannot just pass the whole string after the command // as a single argument because then program sees only a single - // command line argument (with spaces in it: "foo bar" instead + // command line argument (with spaces in it: "foo bar" instead // of "foo" and "bar"). - // code borrowed from: + // code borrowed from: // http://oopweb.com/CPP/Documents/CPPHOWTO/Volume/C++Programming-HOWTO-7.html - std::string::size_type lastPos = + std::string::size_type lastPos = ExecCommandLine.find_first_not_of(delimiters, 0); - std::string::size_type pos = + std::string::size_type pos = ExecCommandLine.find_first_of(delimiters, lastPos); while (std::string::npos != pos || std::string::npos != lastPos) { @@ -341,8 +342,8 @@ std::string CmdPath = sys::Program::FindProgramByName(Command).str(); if (CmdPath.empty()) { - Message = - std::string("Cannot find '") + Command + + Message = + std::string("Cannot find '") + Command + "' in PATH!\n"; return 0; } @@ -355,7 +356,7 @@ //===----------------------------------------------------------------------===// // LLC Implementation of AbstractIntepreter interface // -GCC::FileType LLC::OutputCode(const std::string &Bitcode, +GCC::FileType LLC::OutputCode(const std::string &Bitcode, sys::Path &OutputAsmFile, std::string &Error, unsigned Timeout, unsigned MemoryLimit) { const char *Suffix = (UseIntegratedAssembler ? ".llc.o" : ".llc.s"); @@ -376,10 +377,10 @@ LLCArgs.push_back("-o"); LLCArgs.push_back(OutputAsmFile.c_str()); // Output to the Asm file LLCArgs.push_back(Bitcode.c_str()); // This is the input bitcode - + if (UseIntegratedAssembler) LLCArgs.push_back("-filetype=obj"); - + LLCArgs.push_back (0); outs() << (UseIntegratedAssembler ? "" : ""); @@ -394,7 +395,7 @@ Timeout, MemoryLimit)) Error = ProcessFailure(sys::Path(LLCPath), &LLCArgs[0], Timeout, MemoryLimit); - return UseIntegratedAssembler ? GCC::ObjectFile : GCC::AsmFile; + return UseIntegratedAssembler ? GCC::ObjectFile : GCC::AsmFile; } void LLC::compileProgram(const std::string &Bitcode, std::string *Error, @@ -474,7 +475,7 @@ const std::vector &GCCArgs = std::vector(), const std::vector &SharedLibs = - std::vector(), + std::vector(), unsigned Timeout = 0, unsigned MemoryLimit = 0); }; @@ -677,9 +678,9 @@ GCCArgs.push_back("-force_cpusubtype_ALL"); } } - + GCCArgs.push_back(ProgramFile.c_str()); // Specify the input filename. - + GCCArgs.push_back("-x"); GCCArgs.push_back("none"); GCCArgs.push_back("-o"); @@ -793,7 +794,7 @@ OutputFile = uniqueFilename.str(); std::vector GCCArgs; - + GCCArgs.push_back(GCCPath.c_str()); if (TargetTriple.getArch() == Triple::x86) @@ -816,7 +817,7 @@ GCCArgs.push_back("-G"); // Compile a shared library, `-G' for Sparc else if (TargetTriple.getOS() == Triple::Darwin) { // link all source files into a single module in data segment, rather than - // generating blocks. dynamic_lookup requires that you set + // generating blocks. dynamic_lookup requires that you set // MACOSX_DEPLOYMENT_TARGET=10.3 in your env. FIXME: it would be better for // bugpoint to just pass that in the environment of GCC. GCCArgs.push_back("-single_module"); @@ -837,8 +838,8 @@ GCCArgs.push_back(OutputFile.c_str()); // Output to the right filename. GCCArgs.push_back("-O2"); // Optimize the program a bit. - - + + // Add any arguments intended for GCC. We locate them here because this is // most likely -L and -l options that need to come before other libraries but // after the source. Other options won't be sensitive to placement on the @@ -847,7 +848,7 @@ GCCArgs.push_back(ArgsForGCC[i].c_str()); GCCArgs.push_back(0); // NULL terminator - + outs() << ""; outs().flush(); DEBUG(errs() << "\nAbout to run:\t"; From foldr at codedgers.com Wed Nov 3 11:14:17 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Wed, 03 Nov 2010 16:14:17 -0000 Subject: [llvm-commits] [llvm] r118174 - in /llvm/trunk: include/llvm/Support/SystemUtils.h lib/CompilerDriver/Action.cpp lib/Support/SystemUtils.cpp tools/bugpoint/OptimizerDriver.cpp tools/bugpoint/ToolRunner.cpp tools/llvm-ld/llvm-ld.cpp Message-ID: <20101103161417.320712A6C12C@llvm.org> Author: foldr Date: Wed Nov 3 11:14:16 2010 New Revision: 118174 URL: http://llvm.org/viewvc/llvm-project?rev=118174&view=rev Log: Rename FindExecutable to PrependMainExecutablePath. Makes it more clear that it is just a path manipulation function. Modified: llvm/trunk/include/llvm/Support/SystemUtils.h llvm/trunk/lib/CompilerDriver/Action.cpp llvm/trunk/lib/Support/SystemUtils.cpp llvm/trunk/tools/bugpoint/OptimizerDriver.cpp llvm/trunk/tools/bugpoint/ToolRunner.cpp llvm/trunk/tools/llvm-ld/llvm-ld.cpp Modified: llvm/trunk/include/llvm/Support/SystemUtils.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SystemUtils.h?rev=118174&r1=118173&r2=118174&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/SystemUtils.h (original) +++ llvm/trunk/include/llvm/Support/SystemUtils.h Wed Nov 3 11:14:16 2010 @@ -30,13 +30,14 @@ bool print_warning = true ///< Control whether warnings are printed ); -/// FindExecutable - Find a named executable, given the value of argv[0] of the -/// program being executed and the address of main itself. This allows us to -/// find another LLVM tool if it is built in the same directory. An empty string -/// is returned on error. +/// PrependMainExecutablePath - Prepend the path to the program being executed +/// to \p ExeName, given the value of argv[0] and the address of main() +/// itself. This allows us to find another LLVM tool if it is built in the same +/// directory. An empty string is returned on error; note that this function +/// just mainpulates the path and doesn't check for executability. /// @brief Find a named executable. -sys::Path FindExecutable(const std::string &ExeName, - const char *Argv0, void *MainAddr); +sys::Path PrependMainExecutablePath(const std::string &ExeName, + const char *Argv0, void *MainAddr); } // End llvm namespace Modified: llvm/trunk/lib/CompilerDriver/Action.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/Action.cpp?rev=118174&r1=118173&r2=118174&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/Action.cpp (original) +++ llvm/trunk/lib/CompilerDriver/Action.cpp Wed Nov 3 11:14:16 2010 @@ -57,7 +57,8 @@ sys::Path prog(name); if (!prog.isAbsolute()) { - prog = FindExecutable(name, ProgramName, (void *)(intptr_t)&Main); + prog = PrependMainExecutablePath(name, ProgramName, + (void *)(intptr_t)&Main); if (!prog.canExecute()) { prog = sys::Program::FindProgramByName(name); Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=118174&r1=118173&r2=118174&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Wed Nov 3 11:14:16 2010 @@ -32,13 +32,14 @@ return false; } -/// FindExecutable - Find a named executable, given the value of argv[0] of the -/// program being executed and the address of main itself. This allows us to -/// find another LLVM tool if it is built in the same directory. An empty string -/// is returned on error. -#undef FindExecutable // needed on windows :( -sys::Path llvm::FindExecutable(const std::string &ExeName, - const char *Argv0, void *MainAddr) { +/// PrependMainExecutablePath - Prepend the path to the program being executed +/// to \p ExeName, given the value of argv[0] and the address of main() +/// itself. This allows us to find another LLVM tool if it is built in the same +/// directory. An empty string is returned on error; note that this function +/// just mainpulates the path and doesn't check for executability. +/// @brief Find a named executable. +sys::Path llvm::PrependMainExecutablePath(const std::string &ExeName, + const char *Argv0, void *MainAddr) { // Check the directory that the calling program is in. We can do // this if ProgramPath contains at least one / character, indicating that it // is a relative path to the executable itself. Modified: llvm/trunk/tools/bugpoint/OptimizerDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/OptimizerDriver.cpp?rev=118174&r1=118173&r2=118174&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/OptimizerDriver.cpp (original) +++ llvm/trunk/tools/bugpoint/OptimizerDriver.cpp Wed Nov 3 11:14:16 2010 @@ -144,7 +144,8 @@ return 1; } - sys::Path tool = FindExecutable("opt", getToolName(), (void*)"opt"); + sys::Path tool = PrependMainExecutablePath("opt", getToolName(), + (void*)"opt"); if (tool.empty()) { errs() << "Cannot find `opt' in executable directory!\n"; return 1; Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=118174&r1=118173&r2=118174&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Wed Nov 3 11:14:16 2010 @@ -238,7 +238,7 @@ std::string &Message, const std::vector *ToolArgs) { std::string LLIPath = - FindExecutable("lli", Argv0, (void *)(intptr_t)&createLLI).str(); + PrependMainExecutablePath("lli", Argv0, (void *)(intptr_t)&createLLI).str(); if (!LLIPath.empty()) { Message = "Found lli: " + LLIPath + "\n"; return new LLI(LLIPath, ToolArgs); @@ -438,7 +438,7 @@ const std::vector *GCCArgs, bool UseIntegratedAssembler) { std::string LLCPath = - FindExecutable("llc", Argv0, (void *)(intptr_t)&createLLC).str(); + PrependMainExecutablePath("llc", Argv0, (void *)(intptr_t)&createLLC).str(); if (LLCPath.empty()) { Message = "Cannot find `llc' in executable directory!\n"; return 0; @@ -526,7 +526,7 @@ AbstractInterpreter *AbstractInterpreter::createJIT(const char *Argv0, std::string &Message, const std::vector *Args) { std::string LLIPath = - FindExecutable("lli", Argv0, (void *)(intptr_t)&createJIT).str(); + PrependMainExecutablePath("lli", Argv0, (void *)(intptr_t)&createJIT).str(); if (!LLIPath.empty()) { Message = "Found lli: " + LLIPath + "\n"; return new JIT(LLIPath, Args); @@ -604,11 +604,11 @@ /// CBE *AbstractInterpreter::createCBE(const char *Argv0, std::string &Message, - const std::string &GCCBinary, + const std::string &GCCBinary, const std::vector *Args, const std::vector *GCCArgs) { sys::Path LLCPath = - FindExecutable("llc", Argv0, (void *)(intptr_t)&createCBE); + PrependMainExecutablePath("llc", Argv0, (void *)(intptr_t)&createCBE); if (LLCPath.isEmpty()) { Message = "Cannot find `llc' in executable directory!\n"; Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=118174&r1=118173&r2=118174&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original) +++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Wed Nov 3 11:14:16 2010 @@ -415,8 +415,8 @@ // support windows systems, we copy the llvm-stub.exe executable from the // build tree to the destination file. std::string ErrMsg; - sys::Path llvmstub = FindExecutable("llvm-stub.exe", argv[0], - (void *)(intptr_t)&Optimize); + sys::Path llvmstub = PrependMainExecutablePath("llvm-stub", argv[0], + (void *)(intptr_t)&Optimize); if (llvmstub.isEmpty()) PrintAndExit("Could not find llvm-stub.exe executable!", M); @@ -664,8 +664,8 @@ sys::RemoveFileOnSignal(AssemblyFile); // Determine the locations of the llc and gcc programs. - sys::Path llc = FindExecutable("llc", argv[0], - (void *)(intptr_t)&Optimize); + sys::Path llc = PrependMainExecutablePath("llc", argv[0], + (void *)(intptr_t)&Optimize); if (llc.isEmpty()) PrintAndExit("Failed to find llc", Composite.get()); @@ -691,8 +691,8 @@ sys::RemoveFileOnSignal(CFile); // Determine the locations of the llc and gcc programs. - sys::Path llc = FindExecutable("llc", argv[0], - (void *)(intptr_t)&Optimize); + sys::Path llc = PrependMainExecutablePath("llc", argv[0], + (void *)(intptr_t)&Optimize); if (llc.isEmpty()) PrintAndExit("Failed to find llc", Composite.get()); From bob.wilson at apple.com Wed Nov 3 11:24:50 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 03 Nov 2010 16:24:50 -0000 Subject: [llvm-commits] [llvm] r118175 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vget_lane.ll Message-ID: <20101103162450.545172A6C12C@llvm.org> Author: bwilson Date: Wed Nov 3 11:24:50 2010 New Revision: 118175 URL: http://llvm.org/viewvc/llvm-project?rev=118175&view=rev Log: Check for extractelement with a variable operand for the element number. For NEON we had been assuming this was always an immediate constant. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/vget_lane.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118175&r1=118174&r2=118175&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 11:24:50 2010 @@ -84,8 +84,7 @@ EVT ElemTy = VT.getVectorElementType(); if (ElemTy != MVT::i64 && ElemTy != MVT::f64) setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); - if (ElemTy == MVT::i8 || ElemTy == MVT::i16) - setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); if (ElemTy != MVT::i32) { setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); @@ -3777,14 +3776,19 @@ } static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { - EVT VT = Op.getValueType(); - DebugLoc dl = Op.getDebugLoc(); - SDValue Vec = Op.getOperand(0); + // EXTRACT_VECTOR_ELT is legal only for immediate indexes. SDValue Lane = Op.getOperand(1); - assert(VT == MVT::i32 && - Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && - "unexpected type for custom-lowering vector extract"); - return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); + if (!isa(Lane)) + return SDValue(); + + SDValue Vec = Op.getOperand(0); + if (Op.getValueType() == MVT::i32 && + Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); + } + + return Op; } static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { @@ -4923,7 +4927,8 @@ if (VT == MVT::i32 && (EltVT == MVT::i8 || EltVT == MVT::i16) && - TLI.isTypeLegal(Vec.getValueType())) { + TLI.isTypeLegal(Vec.getValueType()) && + isa(Lane)) { unsigned Opc = 0; switch (N->getOpcode()) { Modified: llvm/trunk/test/CodeGen/ARM/vget_lane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=118175&r1=118174&r2=118175&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Wed Nov 3 11:24:50 2010 @@ -210,3 +210,20 @@ %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1] ret <2 x float> %0 } + +; The llvm extractelement instruction does not require that the lane number +; be an immediate constant. Make sure a variable lane number is handled. + +define i32 @vget_variable_lanes8(<8 x i8>* %A, i32 %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = extractelement <8 x i8> %tmp1, i32 %B + %tmp3 = sext i8 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vgetQ_variable_lanei32(<4 x i32>* %A, i32 %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = add <4 x i32> %tmp1, %tmp1 + %tmp3 = extractelement <4 x i32> %tmp2, i32 %B + ret i32 %tmp3 +} From bob.wilson at apple.com Wed Nov 3 11:24:53 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 03 Nov 2010 16:24:53 -0000 Subject: [llvm-commits] [llvm] r118176 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vget_lane.ll test/CodeGen/ARM/vldlane.ll test/CodeGen/ARM/vstlane.ll Message-ID: <20101103162453.CB01D2A6C12D@llvm.org> Author: bwilson Date: Wed Nov 3 11:24:53 2010 New Revision: 118176 URL: http://llvm.org/viewvc/llvm-project?rev=118176&view=rev Log: Add codegen patterns for VST1-lane instructions. Radar 8599955. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/vget_lane.ll llvm/trunk/test/CodeGen/ARM/vldlane.ll llvm/trunk/test/CodeGen/ARM/vstlane.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118176&r1=118175&r2=118176&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Nov 3 11:24:53 2010 @@ -1126,28 +1126,37 @@ nohash_imm:$lane), itin, "$addr.addr = $wb">; // VST1LN : Vector Store (single element from one lane) -class VST1LN op11_8, bits<4> op7_4, string Dt> +class VST1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, + PatFrag StoreOp, SDNode ExtractOp> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), - IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", []> { + IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", + [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> { let Rm = 0b1111; } +class VST1QLNPseudo + : VSTQLNPseudo { + let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), + addrmode6:$addr)]; +} -def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8"> { +def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8, + NEONvgetlaneu> { let Inst{7-5} = lane{2-0}; } -def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16"> { +def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16, + NEONvgetlaneu> { let Inst{7-6} = lane{1-0}; let Inst{4} = Rn{5}; } -def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32"> { +def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> { let Inst{7} = lane{0}; let Inst{5-4} = Rn{5-4}; } -def VST1LNq8Pseudo : VSTQLNPseudo; -def VST1LNq16Pseudo : VSTQLNPseudo; -def VST1LNq32Pseudo : VSTQLNPseudo; +def VST1LNq8Pseudo : VST1QLNPseudo; +def VST1LNq16Pseudo : VST1QLNPseudo; +def VST1LNq32Pseudo : VST1QLNPseudo; let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { Modified: llvm/trunk/test/CodeGen/ARM/vget_lane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=118176&r1=118175&r2=118176&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Wed Nov 3 11:24:53 2010 @@ -102,7 +102,8 @@ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; [#uses=1] - store i16 %1, i16* %out_uint16_t, align 2 + %2 = add i16 %1, %1 + store i16 %2, i16* %out_uint16_t, align 2 br label %return return: ; preds = %entry @@ -117,7 +118,8 @@ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1] %1 = extractelement <8 x i8> %0, i32 1 ; [#uses=1] - store i8 %1, i8* %out_uint8_t, align 1 + %2 = add i8 %1, %1 + store i8 %2, i8* %out_uint8_t, align 1 br label %return return: ; preds = %entry @@ -132,7 +134,8 @@ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1] %1 = extractelement <8 x i16> %0, i32 1 ; [#uses=1] - store i16 %1, i16* %out_uint16_t, align 2 + %2 = add i16 %1, %1 + store i16 %2, i16* %out_uint16_t, align 2 br label %return return: ; preds = %entry @@ -147,7 +150,8 @@ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1] %1 = extractelement <16 x i8> %0, i32 1 ; [#uses=1] - store i8 %1, i8* %out_uint8_t, align 1 + %2 = add i8 %1, %1 + store i8 %2, i8* %out_uint8_t, align 1 br label %return return: ; preds = %entry Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=118176&r1=118175&r2=118176&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Wed Nov 3 11:24:53 2010 @@ -22,7 +22,7 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld1lanei32: -;Check the alignment value. Max for this instruction is 16 bits: +;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld1.32 {d16[1]}, [r0, :32] %tmp1 = load <2 x i32>* %B %tmp2 = load i32* %A, align 8 Modified: llvm/trunk/test/CodeGen/ARM/vstlane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vstlane.ll?rev=118176&r1=118175&r2=118176&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vstlane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vstlane.ll Wed Nov 3 11:24:53 2010 @@ -1,5 +1,62 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { +;CHECK: vst1lanei8: +;Check the (default) alignment. +;CHECK: vst1.8 {d16[3]}, [r0] + %tmp1 = load <8 x i8>* %B + %tmp2 = extractelement <8 x i8> %tmp1, i32 3 + store i8 %tmp2, i8* %A, align 8 + ret void +} + +define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { +;CHECK: vst1lanei16: +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vst1.16 {d16[2]}, [r0, :16] + %tmp1 = load <4 x i16>* %B + %tmp2 = extractelement <4 x i16> %tmp1, i32 2 + store i16 %tmp2, i16* %A, align 8 + ret void +} + +define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { +;CHECK: vst1lanei32: +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vst1.32 {d16[1]}, [r0, :32] + %tmp1 = load <2 x i32>* %B + %tmp2 = extractelement <2 x i32> %tmp1, i32 1 + store i32 %tmp2, i32* %A, align 8 + ret void +} + +define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { +;CHECK: vst1laneQi8: +;CHECK: vst1.8 {d17[1]}, [r0] + %tmp1 = load <16 x i8>* %B + %tmp2 = extractelement <16 x i8> %tmp1, i32 9 + store i8 %tmp2, i8* %A, align 8 + ret void +} + +define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { +;CHECK: vst1laneQi16: +;CHECK: vst1.16 {d17[1]}, [r0, :16] + %tmp1 = load <8 x i16>* %B + %tmp2 = extractelement <8 x i16> %tmp1, i32 5 + store i16 %tmp2, i16* %A, align 8 + ret void +} + +define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { +;CHECK: vst1laneQi32: +;CHECK: vst1.32 {d17[1]}, [r0, :32] + %tmp1 = load <4 x i32>* %B + %tmp2 = extractelement <4 x i32> %tmp1, i32 3 + store i32 %tmp2, i32* %A, align 8 + ret void +} + define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: From dalej at apple.com Wed Nov 3 13:08:41 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 03 Nov 2010 18:08:41 -0000 Subject: [llvm-commits] [llvm] r118182 - /llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll Message-ID: <20101103180841.B27B22A6C12C@llvm.org> Author: johannes Date: Wed Nov 3 13:08:41 2010 New Revision: 118182 URL: http://llvm.org/viewvc/llvm-project?rev=118182&view=rev Log: This test assumes SSE is present; that is not the default on non-X86 hosts. Hopefully fixes ppc-host buildbot. Modified: llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll Modified: llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll?rev=118182&r1=118181&r2=118182&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll (original) +++ llvm/trunk/test/CodeGen/X86/mult-alt-x86.ll Wed Nov 3 13:08:41 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -march=x86 -mattr=+sse2 ; ModuleID = 'mult-alt-x86.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i686-pc-win32" From resistor at mac.com Wed Nov 3 13:16:27 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 03 Nov 2010 18:16:27 -0000 Subject: [llvm-commits] [llvm] r118183 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shuffle-encoding.s Message-ID: <20101103181627.B76CC2A6C12E@llvm.org> Author: resistor Date: Wed Nov 3 13:16:27 2010 New Revision: 118183 URL: http://llvm.org/viewvc/llvm-project?rev=118183&view=rev Log: Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with the immediate shifted left to reflect the increased element size. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118183&r1=118182&r2=118183&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Nov 3 13:16:27 2010 @@ -4241,15 +4241,37 @@ let Inst{11-8} = index{3-0}; } -def VEXTd8 : VEXTd<"vext", "8", v8i8>; -def VEXTd16 : VEXTd<"vext", "16", v4i16>; -def VEXTd32 : VEXTd<"vext", "32", v2i32>; -def VEXTdf : VEXTd<"vext", "32", v2f32>; - -def VEXTq8 : VEXTq<"vext", "8", v16i8>; -def VEXTq16 : VEXTq<"vext", "16", v8i16>; -def VEXTq32 : VEXTq<"vext", "32", v4i32>; -def VEXTqf : VEXTq<"vext", "32", v4f32>; +def VEXTd8 : VEXTd<"vext", "8", v8i8> { + let Inst{11-8} = index{3-0}; +} +def VEXTd16 : VEXTd<"vext", "16", v4i16> { + let Inst{11-9} = index{2-0}; + let Inst{8} = 0b0; +} +def VEXTd32 : VEXTd<"vext", "32", v2i32> { + let Inst{11-10} = index{1-0}; + let Inst{9-8} = 0b00; +} +def VEXTdf : VEXTd<"vext", "32", v2f32> { + let Inst{11} = index{0}; + let Inst{10-8} = 0b000; +} + +def VEXTq8 : VEXTq<"vext", "8", v16i8> { + let Inst{11-8} = index{3-0}; +} +def VEXTq16 : VEXTq<"vext", "16", v8i16> { + let Inst{11-9} = index{2-0}; + let Inst{8} = 0b0; +} +def VEXTq32 : VEXTq<"vext", "32", v4i32> { + let Inst{11-10} = index{1-0}; + let Inst{9-8} = 0b00; +} +def VEXTqf : VEXTq<"vext", "32", v4f32> { + let Inst{11} = index{0}; + let Inst{10-8} = 0b000; +} // VTRN : Vector Transpose Modified: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s?rev=118183&r1=118182&r2=118183&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Wed Nov 3 13:16:27 2010 @@ -8,9 +8,9 @@ vext.8 q8, q9, q8, #3 @ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2] vext.8 q8, q9, q8, #7 -@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2] vext.16 d16, d17, d16, #3 -@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2] vext.32 q8, q9, q8, #3 @ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] vtrn.8 d17, d16 From aggarwa4 at illinois.edu Wed Nov 3 13:16:50 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 03 Nov 2010 18:16:50 -0000 Subject: [llvm-commits] [poolalloc] r118184 - /poolalloc/trunk/lib/DSA/DSTest.cpp Message-ID: <20101103181650.A8EB02A6C12E@llvm.org> Author: aggarwa4 Date: Wed Nov 3 13:16:50 2010 New Revision: 118184 URL: http://llvm.org/viewvc/llvm-project?rev=118184&view=rev Log: More robust checking in case of SCCs Modified: poolalloc/trunk/lib/DSA/DSTest.cpp Modified: poolalloc/trunk/lib/DSA/DSTest.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=118184&r1=118183&r2=118184&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSTest.cpp (original) +++ poolalloc/trunk/lib/DSA/DSTest.cpp Wed Nov 3 13:16:50 2010 @@ -558,16 +558,23 @@ std::string &func = *(I); Function *caller = M->getFunction(func); assert(caller && "Function not found in module"); - const DSCallGraph callgraph = DS->getCallGraph(); + //const DSCallGraph callgraph = DS->getCallGraph(); + (const_cast(callgraph)).dump(); ++I; while(I != E ){ std::string &func = *(I); Function *callee = M->getFunction(func); bool found = false; + // either the callee is found in the DSGraph for(DSCallGraph::flat_iterator CI = callgraph.flat_callee_begin(caller); CI != callgraph.flat_callee_end(caller); CI ++) { - if ( callee == *CI) + if (callee == *CI) found = true; //(*CI)->dump(); + } + // or the callee is in the same SCC as the caller, and hence does not show up + for(DSCallGraph::scc_iterator sccii = callgraph.scc_begin(caller), sccee = callgraph.scc_end(caller); sccii != sccee; ++sccii) { + if(callee == *sccii) + found = true; } assert(found && "callee not in call graph"); ++I; From aggarwa4 at illinois.edu Wed Nov 3 13:18:55 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 03 Nov 2010 18:18:55 -0000 Subject: [llvm-commits] [poolalloc] r118186 - /poolalloc/trunk/lib/DSA/DSTest.cpp Message-ID: <20101103181855.21FE02A6C12E@llvm.org> Author: aggarwa4 Date: Wed Nov 3 13:18:54 2010 New Revision: 118186 URL: http://llvm.org/viewvc/llvm-project?rev=118186&view=rev Log: Fix a small issue in previous commit. Modified: poolalloc/trunk/lib/DSA/DSTest.cpp Modified: poolalloc/trunk/lib/DSA/DSTest.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=118186&r1=118185&r2=118186&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSTest.cpp (original) +++ poolalloc/trunk/lib/DSA/DSTest.cpp Wed Nov 3 13:18:54 2010 @@ -558,8 +558,8 @@ std::string &func = *(I); Function *caller = M->getFunction(func); assert(caller && "Function not found in module"); - //const DSCallGraph callgraph = DS->getCallGraph(); - (const_cast(callgraph)).dump(); + const DSCallGraph callgraph = DS->getCallGraph(); + //(const_cast(callgraph)).dump(); ++I; while(I != E ){ std::string &func = *(I); From evan.cheng at apple.com Wed Nov 3 13:21:33 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 03 Nov 2010 18:21:33 -0000 Subject: [llvm-commits] [llvm] r118187 - /llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Message-ID: <20101103182133.3C66A2A6C12E@llvm.org> Author: evancheng Date: Wed Nov 3 13:21:33 2010 New Revision: 118187 URL: http://llvm.org/viewvc/llvm-project?rev=118187&view=rev Log: Fix test. Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=118187&r1=118186&r2=118187&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Wed Nov 3 13:21:33 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] From aggarwa4 at illinois.edu Wed Nov 3 14:00:34 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 03 Nov 2010 19:00:34 -0000 Subject: [llvm-commits] [poolalloc] r118188 - in /poolalloc/trunk/test/dsa/local: struct4.ll union_P2I_1.ll Message-ID: <20101103190034.56B9F2A6C12C@llvm.org> Author: aggarwa4 Date: Wed Nov 3 14:00:34 2010 New Revision: 118188 URL: http://llvm.org/viewvc/llvm-project?rev=118188&view=rev Log: Fixes for test cases. Modified: poolalloc/trunk/test/dsa/local/struct4.ll poolalloc/trunk/test/dsa/local/union_P2I_1.ll Modified: poolalloc/trunk/test/dsa/local/struct4.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/struct4.ll?rev=118188&r1=118187&r2=118188&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/local/struct4.ll (original) +++ poolalloc/trunk/test/dsa/local/struct4.ll Wed Nov 3 14:00:34 2010 @@ -1,8 +1,8 @@ ;accessing 1st field using struct pointer -;RUN: dsaopt %s -dsa-local -analyze -check-type=main:r,0:i32|i32*::8:i32*::16:i8* +;RUN: dsaopt %s -dsa-local -analyze -check-type=main:r,0:i32*::8:i32*::16:i8* -; ModuleID = 'struct4.bc' +; ModuleID = 'struct4.o' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" @@ -13,26 +13,28 @@ %retval = alloca i32 ; [#uses=2] %0 = alloca i32 ; [#uses=2] %r = alloca %struct.R ; <%struct.R*> [#uses=4] - %x = alloca i32 ; [#uses=1] + %x = alloca i32 ; [#uses=2] %y = alloca i32 ; [#uses=1] %c = alloca i8 ; [#uses=1] - %p = alloca i32* ; [#uses=2] + %p = alloca i32** ; [#uses=2] %d = alloca i32 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 5, i32* %x, align 4 %1 = getelementptr inbounds %struct.R* %r, i32 0, i32 0 ; [#uses=1] store i32* %x, i32** %1, align 8 %2 = getelementptr inbounds %struct.R* %r, i32 0, i32 1 ; [#uses=1] store i32* %y, i32** %2, align 8 %3 = getelementptr inbounds %struct.R* %r, i32 0, i32 2 ; [#uses=1] store i8* %c, i8** %3, align 8 - %r1 = bitcast %struct.R* %r to i32* ; [#uses=1] - store i32* %r1, i32** %p, align 8 - %4 = load i32** %p, align 8 ; [#uses=1] - %5 = load i32* %4, align 4 ; [#uses=1] - store i32 %5, i32* %d, align 4 + %r1 = bitcast %struct.R* %r to i32** ; [#uses=1] + store i32** %r1, i32*** %p, align 8 + %4 = load i32*** %p, align 8 ; [#uses=1] + %5 = load i32** %4, align 8 ; [#uses=1] + %6 = load i32* %5, align 4 ; [#uses=1] + store i32 %6, i32* %d, align 4 store i32 0, i32* %0, align 4 - %6 = load i32* %0, align 4 ; [#uses=1] - store i32 %6, i32* %retval, align 4 + %7 = load i32* %0, align 4 ; [#uses=1] + store i32 %7, i32* %retval, align 4 br label %return return: ; preds = %entry Modified: poolalloc/trunk/test/dsa/local/union_P2I_1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/union_P2I_1.ll?rev=118188&r1=118187&r2=118188&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/local/union_P2I_1.ll (original) +++ poolalloc/trunk/test/dsa/local/union_P2I_1.ll Wed Nov 3 14:00:34 2010 @@ -1,6 +1,7 @@ ;RUN: dsaopt %s -dsa-local -analyze -check-same-node=main:c:0,main:obj:0 -;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:c:0+UP2" -;RUN: dsaopt %s -dsa-local -analyze -check-type=main:obj,0:i32|i32*Array +;RUN: dsaopt %s -dsa-local -analyze -check-type=main:obj,FoldedVOID + +;union of array of int/int*. Must get collapsed, as the element type is not of consistent size ; ModuleID = 'union_P2I_1.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" From sabre at nondot.org Wed Nov 3 14:47:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 03 Nov 2010 19:47:34 -0000 Subject: [llvm-commits] [llvm] r118190 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101103194734.9840B2A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 14:47:34 2010 New Revision: 118190 URL: http://llvm.org/viewvc/llvm-project?rev=118190&view=rev Log: rename Operand -> AsmOperand for clarity. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118190&r1=118189&r2=118190&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 14:47:34 2010 @@ -63,9 +63,6 @@ // In addition, the subset relation amongst classes induces a partial order // on such tuples, which we use to resolve ambiguities. // -// FIXME: What do we do if a crazy case shows up where this is the wrong -// resolution? -// // 2. The input can now be treated as a tuple of classes (static tokens are // simple singleton sets). Each such tuple should generally map to a single // instruction (we currently ignore cases where this isn't true, whee!!!), @@ -247,7 +244,7 @@ /// MatchableInfo - Helper class for storing the necessary information for an /// instruction or alias which is capable of being matched. struct MatchableInfo { - struct Operand { + struct AsmOperand { /// Token - This is the token that the operand came from. StringRef Token; @@ -259,7 +256,7 @@ /// list. If an operand is tied ($a=$b), this refers to source operand: $b. const CGIOperandList::OperandInfo *OperandInfo; - explicit Operand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} + explicit AsmOperand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} }; /// InstrName - The target name for this instruction. @@ -285,7 +282,7 @@ /// annotated with a class and where in the OperandList they were defined. /// This directly corresponds to the tokenized AsmString after the mnemonic is /// removed. - SmallVector AsmOperands; + SmallVector AsmOperands; /// Predicates - The required subtarget features to match this instruction. SmallVector RequiredFeatures; @@ -477,7 +474,7 @@ errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n"; for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { - Operand &Op = AsmOperands[i]; + AsmOperand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; if (Op.Class->Kind == ClassInfo::Token) { errs() << '\"' << Op.Token << "\"\n"; @@ -531,22 +528,22 @@ case '\t': case ',': if (InTok) { - AsmOperands.push_back(Operand(String.slice(Prev, i))); + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); InTok = false; } if (!isspace(String[i]) && String[i] != ',') - AsmOperands.push_back(Operand(String.substr(i, 1))); + AsmOperands.push_back(AsmOperand(String.substr(i, 1))); Prev = i + 1; break; case '\\': if (InTok) { - AsmOperands.push_back(Operand(String.slice(Prev, i))); + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); InTok = false; } ++i; assert(i != String.size() && "Invalid quoted character"); - AsmOperands.push_back(Operand(String.substr(i, 1))); + AsmOperands.push_back(AsmOperand(String.substr(i, 1))); Prev = i + 1; break; @@ -554,7 +551,7 @@ // If this isn't "${", treat like a normal token. if (i + 1 == String.size() || String[i + 1] != '{') { if (InTok) { - AsmOperands.push_back(Operand(String.slice(Prev, i))); + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); InTok = false; } Prev = i; @@ -562,14 +559,14 @@ } if (InTok) { - AsmOperands.push_back(Operand(String.slice(Prev, i))); + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); InTok = false; } StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); assert(End != String.end() && "Missing brace in operand reference!"); size_t EndPos = End - String.begin(); - AsmOperands.push_back(Operand(String.slice(i, EndPos+1))); + AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1))); Prev = EndPos + 1; i = EndPos; break; @@ -577,7 +574,7 @@ case '.': if (InTok) - AsmOperands.push_back(Operand(String.slice(Prev, i))); + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); Prev = i; InTok = true; break; @@ -587,7 +584,7 @@ } } if (InTok && Prev != String.size()) - AsmOperands.push_back(Operand(String.substr(Prev))); + AsmOperands.push_back(AsmOperand(String.substr(Prev))); // The first token of the instruction is the mnemonic, which must be a // simple string, not a $foo variable or a singleton register. @@ -1033,7 +1030,7 @@ // Parse the tokens after the mnemonic. for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II->AsmOperands[i]; + MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; StringRef Token = Op.Token; // Check for singleton registers. @@ -1133,7 +1130,7 @@ // Order the (class) operands by the order to convert them into an MCInst. for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.AsmOperands[i]; + MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; if (!Op.OperandInfo) continue; unsigned LogicalOpNum = Op.OperandInfo - &II.OperandList[0]; @@ -1155,13 +1152,10 @@ int SrcOperand = OperandMap[i]; if (SrcOperand != -1) { // Otherwise, this comes from something we parsed. - MatchableInfo::Operand &Op = II.AsmOperands[SrcOperand]; + MatchableInfo::AsmOperand &Op = II.AsmOperands[SrcOperand]; // Registers are always converted the same, don't duplicate the // conversion function based on them. - // - // FIXME: We could generalize this based on the render method, if it - // mattered. Signature += "__"; if (Op.Class->isRegisterClass()) Signature += "Reg"; @@ -1706,7 +1700,7 @@ << ", \"" << II.Mnemonic << "\"" << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { - MatchableInfo::Operand &Op = II.AsmOperands[i]; + MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; if (i) OS << ", "; OS << Op.Class->Name; From aggarwa4 at illinois.edu Wed Nov 3 15:13:13 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 03 Nov 2010 20:13:13 -0000 Subject: [llvm-commits] [poolalloc] r118191 - in /poolalloc/trunk: include/dsa/DSGraph.h include/dsa/DataStructure.h lib/DSA/BottomUpClosure.cpp lib/DSA/DSGraph.cpp lib/DSA/DataStructure.cpp lib/DSA/Local.cpp lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <20101103201313.825FE2A6C12C@llvm.org> Author: aggarwa4 Date: Wed Nov 3 15:13:13 2010 New Revision: 118191 URL: http://llvm.org/viewvc/llvm-project?rev=118191&view=rev Log: The call graph, now reports the conservatively correct, set of all address taken functions, for any unresolved call site. Fixes 252.eon Modified: poolalloc/trunk/include/dsa/DSGraph.h poolalloc/trunk/include/dsa/DataStructure.h poolalloc/trunk/lib/DSA/BottomUpClosure.cpp poolalloc/trunk/lib/DSA/DSGraph.cpp poolalloc/trunk/lib/DSA/DataStructure.cpp poolalloc/trunk/lib/DSA/Local.cpp poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/include/dsa/DSGraph.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSGraph.h (original) +++ poolalloc/trunk/include/dsa/DSGraph.h Wed Nov 3 15:13:13 2010 @@ -345,7 +345,7 @@ // addAuxFunctionCall - Add a call site to the AuxFunctionCallList void addAuxFunctionCall(DSCallSite D) { AuxFunctionCalls.push_front(D); } - void buildCallGraph(DSCallGraph& DCG, bool filter) const; + void buildCallGraph(DSCallGraph& DCG, std::vector &GlobalFunctionList, bool filter) const; /// removeFunction - Specify that all call sites to the function have been /// fully specified by a pass such as StdLibPass. Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Wed Nov 3 15:13:13 2010 @@ -80,6 +80,9 @@ // Callgraph, as computed so far DSCallGraph callgraph; + // List of all address taken functions. + // This is used as target, of indirect calls for any indirect call site with // incomplete callee node. + std::vector GlobalFunctionList; void init(DataStructures* D, bool clone, bool useAuxCalls, bool copyGlobalAuxCalls, bool resetAux); void init(TargetData* T); @@ -87,6 +90,8 @@ void formGlobalECs(); void restoreCorrectCallGraph(); + + void formGlobalFunctionList(); DataStructures(intptr_t id, const char* name) : ModulePass(id), TD(0), GraphSource(0), printname(name), GlobalsGraph(0) { Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Wed Nov 3 15:13:13 2010 @@ -150,7 +150,7 @@ if (!(F->isDeclaration())){ DSGraph *Graph = getOrCreateGraph(F); cloneGlobalsInto(Graph); - Graph->buildCallGraph(callgraph, filterCallees); + Graph->buildCallGraph(callgraph, GlobalFunctionList, filterCallees); Graph->maskIncompleteMarkers(); Graph->markIncompleteNodes(DSGraph::MarkFormalArgs | DSGraph::IgnoreGlobals); @@ -840,7 +840,7 @@ // Update the callgraph with the new information that we have gleaned. // NOTE : This must be called before removeDeadNodes, so that no // information is lost due to deletion of DSCallNodes. - Graph->buildCallGraph(callgraph,filterCallees); + Graph->buildCallGraph(callgraph,GlobalFunctionList, filterCallees); // Delete dead nodes. Treat globals that are unreachable but that can // reach live nodes as live. Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSGraph.cpp Wed Nov 3 15:13:13 2010 @@ -480,7 +480,7 @@ AuxCallToCopy.push_back(&*I); // else if (I->isIndirectCall()){ // //If the call node doesn't have any callees, clone it -// std::vector< Function *> List; +// std::vector< const Function *> List; // I->getCalleeNode()->addFullFunctionList(List); // if (!List.size()) // AuxCallToCopy.push_back(&*I); @@ -1601,10 +1601,14 @@ // of function calls that can be inferred from the unresolved call sites // within the DSGraph. // +// The parameter GlobalFunctionList, is a list of all the address taken +// functions in the module. This is used as the list of targets when a callee +// node is Incomplete. +// // The parameter 'filter' determines if we should attempt to prune callees // that are illegal to be called from the callsite. // -void DSGraph::buildCallGraph(DSCallGraph& DCG, bool filter) const { +void DSGraph::buildCallGraph(DSCallGraph& DCG, std::vector& GlobalFunctionList, bool filter) const { // // Get the list of unresolved call sites. // @@ -1624,7 +1628,11 @@ // // Get the list of known targets of this function. // - ii->getCalleeNode()->addFullFunctionList(MaybeTargets); + if(ii->getCalleeNode()->isIncompleteNode()) { + MaybeTargets.assign(GlobalFunctionList.begin(), GlobalFunctionList.end()); + } else { + ii->getCalleeNode()->addFullFunctionList(MaybeTargets); + } // // Ensure that the call graph at least knows about (has a record of) this Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Wed Nov 3 15:13:13 2010 @@ -1302,6 +1302,26 @@ return G; } +void DataStructures::formGlobalFunctionList() { + std::vector List; + DSScalarMap &SN = GlobalsGraph->getScalarMap(); + EquivalenceClasses &EC = GlobalsGraph->getGlobalECs(); + for (DSScalarMap::global_iterator I = SN.global_begin(), E = SN.global_end(); I != E; ++I) { + EquivalenceClasses::iterator ECI = EC.findValue(*I); + if (ECI == EC.end()) { + if (const Function *F = dyn_cast(*I)) + List.push_back(F); + } else { + for (EquivalenceClasses::member_iterator MI = + EC.member_begin(ECI), ME = EC.member_end(); MI != ME; ++MI){ + if (const Function *F = dyn_cast(*MI)) + List.push_back(F); + } + } + } + GlobalFunctionList.swap(List); +} + void DataStructures::formGlobalECs() { // Grow the equivalence classes for the globals to include anything that we @@ -1412,6 +1432,7 @@ TD = D->TD; TypeSS = D->TypeSS; callgraph = D->callgraph; + GlobalFunctionList = D->GlobalFunctionList; GlobalECs = D->getGlobalECs(); GlobalsGraph = new DSGraph(D->getGlobalsGraph(), GlobalECs, *TypeSS, copyGlobalAuxCalls? DSGraph::CloneAuxCallNodes Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Wed Nov 3 15:13:13 2010 @@ -1253,6 +1253,11 @@ // Next step, iterate through the nodes in the globals graph, unioning // together the globals into equivalence classes. formGlobalECs(); + + // Iterate through the address taken functions in the globals graph, + // collecting them in a list, to be used as target for call sites that + // cant be resolved. + formGlobalFunctionList(); // Calculate all of the graphs... for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) @@ -1263,7 +1268,7 @@ setDSGraph(*I, G); propagateUnknownFlag(G); callgraph.insureEntry(I); - G->buildCallGraph(callgraph, true); + G->buildCallGraph(callgraph, GlobalFunctionList, true); } GlobalsGraph->removeTriviallyDeadNodes(); Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=118191&r1=118190&r2=118191&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Wed Nov 3 15:13:13 2010 @@ -917,8 +917,10 @@ // Get the information for this function. Since this is coming from DSA, // it should be an original function. // + // This call site calls a function, that is not defined in this module + if (!(Graphs.hasDSGraph(**I))) return; + // For all other cases Func Info must exist. FuncInfo *CFI = PAInfo.getFuncInfo(**I); - assert(CFI && "Func Info not found"); // // If this target takes more DSNodes than the last one we found, then // make *this* target our canonical target. @@ -928,14 +930,16 @@ CF = *I; } } - + + // Assuming the call graph is always correct. And if the call graph reports, + // no callees, we can assume that it is right. // // If we didn't find the callee in the constructed call graph, try // checking in the DSNode itself. // This isn't ideal as it means that this call site didn't have inlining // happen. // - if (!CF) { + /*if (!CF) { DSGraph* dg = Graphs.getDSGraph(*OrigInst->getParent()->getParent()); DSNode* d = dg->getNodeForValue(OrigInst->getOperand(0)).getNode(); assert (d && "No DSNode!\n"); @@ -961,7 +965,7 @@ break; } } - } + }*/ // // If we still haven't been able to find a target function of the call site From echristo at apple.com Wed Nov 3 15:21:17 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 03 Nov 2010 20:21:17 -0000 Subject: [llvm-commits] [llvm] r118192 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101103202117.3C1982A6C12C@llvm.org> Author: echristo Date: Wed Nov 3 15:21:17 2010 New Revision: 118192 URL: http://llvm.org/viewvc/llvm-project?rev=118192&view=rev Log: Optimize generated code for integer materialization a bit. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118192&r1=118191&r2=118192&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 3 15:21:17 2010 @@ -434,6 +434,19 @@ // For now 32-bit only. if (VT != MVT::i32) return false; + unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); + + // If we can do this in a single instruction without a constant pool entry + // do so now. + const ConstantInt *CI = cast(C); + if (isUInt<16>(CI->getSExtValue())) { + unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16; + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), DestReg) + .addImm(CI->getSExtValue())); + return DestReg; + } + // MachineConstantPool wants an explicit alignment. unsigned Align = TD.getPrefTypeAlignment(C->getType()); if (Align == 0) { @@ -441,7 +454,6 @@ Align = TD.getTypeAllocSize(C->getType()); } unsigned Idx = MCP.getConstantPoolIndex(C, Align); - unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, From stoklund at 2pi.dk Wed Nov 3 15:39:24 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 03 Nov 2010 20:39:24 -0000 Subject: [llvm-commits] [llvm] r118193 - in /llvm/trunk/lib/CodeGen: InlineSpiller.cpp SplitKit.cpp Message-ID: <20101103203924.234CF2A6C12C@llvm.org> Author: stoklund Date: Wed Nov 3 15:39:23 2010 New Revision: 118193 URL: http://llvm.org/viewvc/llvm-project?rev=118193&view=rev Log: Tag debug output as regalloc Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp llvm/trunk/lib/CodeGen/SplitKit.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=118193&r1=118192&r2=118193&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Nov 3 15:39:23 2010 @@ -12,7 +12,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "spiller" +#define DEBUG_TYPE "regalloc" #include "Spiller.h" #include "LiveRangeEdit.h" #include "SplitKit.h" Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=118193&r1=118192&r2=118193&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Nov 3 15:39:23 2010 @@ -12,7 +12,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "splitter" +#define DEBUG_TYPE "regalloc" #include "SplitKit.h" #include "LiveRangeEdit.h" #include "VirtRegMap.h" From stoklund at 2pi.dk Wed Nov 3 15:39:26 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 03 Nov 2010 20:39:26 -0000 Subject: [llvm-commits] [llvm] r118194 - /llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Message-ID: <20101103203926.6B9582A6C12D@llvm.org> Author: stoklund Date: Wed Nov 3 15:39:26 2010 New Revision: 118194 URL: http://llvm.org/viewvc/llvm-project?rev=118194&view=rev Log: Let RegAllocBasic require MachineDominators - they are already available and splitting needs them. Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118194&r1=118193&r2=118194&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Wed Nov 3 15:39:26 2010 @@ -120,6 +120,7 @@ initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry()); initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); initializeLiveStacksPass(*PassRegistry::getPassRegistry()); + initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry()); @@ -135,6 +136,8 @@ au.addRequired(); au.addRequired(); au.addPreserved(); + au.addRequiredID(MachineDominatorsID); + au.addPreservedID(MachineDominatorsID); au.addRequired(); au.addPreserved(); au.addRequired(); From echristo at apple.com Wed Nov 3 15:44:42 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 03 Nov 2010 20:44:42 -0000 Subject: [llvm-commits] [llvm] r118195 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20101103204442.7DB782A6C12C@llvm.org> Author: echristo Date: Wed Nov 3 15:44:42 2010 New Revision: 118195 URL: http://llvm.org/viewvc/llvm-project?rev=118195&view=rev Log: Just return undef for invalid masks or elts, and since we're doing that, just do it earlier too. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=118195&r1=118194&r2=118195&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 3 15:44:42 2010 @@ -6242,6 +6242,10 @@ if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) return SDValue(); + // If Idx was -1 above, Elt is going to be -1, so just return undef. + if (Elt == -1) + return DAG.getUNDEF(LN0->getBasePtr().getValueType()); + unsigned Align = LN0->getAlignment(); if (NewLoad) { // Check the resultant load doesn't need a higher alignment than the @@ -6257,11 +6261,8 @@ SDValue NewPtr = LN0->getBasePtr(); unsigned PtrOff = 0; - // If Idx was -1 above, Elt is going to be -1, so just use undef as our - // new pointer. - if (Elt == -1) { - NewPtr = DAG.getUNDEF(NewPtr.getValueType()); - } else if (Elt) { + + if (Elt) { PtrOff = LVT.getSizeInBits() * Elt / 8; EVT PtrType = NewPtr.getValueType(); if (TLI.isBigEndian()) From echristo at apple.com Wed Nov 3 15:46:50 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 3 Nov 2010 13:46:50 -0700 Subject: [llvm-commits] [llvm] r118164 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <8DC866B8-CD38-400B-A938-86607F58E8A8@apple.com> References: <20101103093640.C1E392A6C12C@llvm.org> <8DC866B8-CD38-400B-A938-86607F58E8A8@apple.com> Message-ID: On Nov 3, 2010, at 8:44 AM, Bob Wilson wrote: > This should be safe, but you could take it one step further and just return undef instead of creating a load from an undef pointer. Cool, thanks. Done in r118195 :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101103/9f2a038a/attachment.html From grosbach at apple.com Wed Nov 3 17:03:20 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 22:03:20 -0000 Subject: [llvm-commits] [llvm] r118199 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101103220320.A7C062A6C12C@llvm.org> Author: grosbach Date: Wed Nov 3 17:03:20 2010 New Revision: 118199 URL: http://llvm.org/viewvc/llvm-project?rev=118199&view=rev Log: trailing whitespace Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118199&r1=118198&r2=118199&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Nov 3 17:03:20 2010 @@ -255,7 +255,7 @@ // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be // shifted. The second is either Rs, the amount to shift by, or reg0 in which // case the imm contains the amount to shift by. - // + // // {3-0} = Rm. // {4} = 1 if reg shift, 0 if imm shift // {6-5} = type @@ -349,7 +349,7 @@ unsigned Op) const { const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Imm = MI.getOperand(Op + 1); - + unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); unsigned Align = 0; From resistor at mac.com Wed Nov 3 17:44:51 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 03 Nov 2010 22:44:51 -0000 Subject: [llvm-commits] [llvm] r118201 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s Message-ID: <20101103224451.76A212A6C12C@llvm.org> Author: resistor Date: Wed Nov 3 17:44:51 2010 New Revision: 118201 URL: http://llvm.org/viewvc/llvm-project?rev=118201&view=rev Log: Add support for code generation of the one register with immediate form of vorr. We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/vbits.ll llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118201&r1=118200&r2=118201&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 17:44:51 2010 @@ -101,6 +101,7 @@ setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); + setOperationAction(ISD::OR, VT.getSimpleVT(), Custom); setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; @@ -820,6 +821,7 @@ case ARMISD::FMAX: return "ARMISD::FMAX"; case ARMISD::FMIN: return "ARMISD::FMIN"; case ARMISD::BFI: return "ARMISD::BFI"; + case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; } } @@ -3431,6 +3433,32 @@ return SDValue(); } +static SDValue LowerOR(SDValue Op, SelectionDAG &DAG) { + SDValue Op1 = Op.getOperand(1); + while (Op1.getOpcode() == ISD::BIT_CONVERT && Op1.getOperand(0) != Op1) + Op1 = Op1.getOperand(0); + if (Op1.getOpcode() != ARMISD::VMOVIMM) return Op; + + ConstantSDNode* TargetConstant = cast(Op1.getOperand(0)); + uint32_t ConstVal = TargetConstant->getZExtValue(); + + // FIXME: VORRIMM only supports immediate encodings of 16 and 32 bit size. + // In theory for VMOVIMMs whose value is already encoded as with an + // 8 bit encoding, we could re-encode it as a 16 or 32 bit immediate. + EVT VorrVT = Op1.getValueType(); + EVT EltVT = VorrVT.getVectorElementType(); + if (EltVT != MVT::i16 && EltVT != MVT::i32) return Op; + + ConstVal |= 0x0100; + SDValue OrConst = DAG.getTargetConstant(ConstVal, MVT::i32); + + DebugLoc dl = Op.getDebugLoc(); + EVT VT = Op.getValueType(); + SDValue toTy = DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, Op.getOperand(0)); + SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, toTy, OrConst); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr); +} + // If this is a case we can't handle, return null and let the default // expansion code take care of it. static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, @@ -3899,6 +3927,7 @@ case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); case ISD::MUL: return LowerMUL(Op, DAG); + case ISD::OR: return LowerOR(Op, DAG); } return SDValue(); } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118201&r1=118200&r2=118201&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Nov 3 17:44:51 2010 @@ -162,7 +162,10 @@ FMIN, // Bit-field insert - BFI + BFI, + + // Vector OR with immediate + VORRIMM }; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118201&r1=118200&r2=118201&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Nov 3 17:44:51 2010 @@ -69,6 +69,10 @@ def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; +def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, + SDTCisVT<2, i32>]>; +def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; + def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; // VDUPLANE can produce a quad-register result from a double-register source, @@ -3295,6 +3299,43 @@ def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>; +def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1, + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + IIC_VMOVImm, + "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", + [(set DPR:$Vd, + (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + +def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1, + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + IIC_VMOVImm, + "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", + [(set DPR:$Vd, + (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { + let Inst{11-9} = SIMM{11-9}; +} + +def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + IIC_VMOVImm, + "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", + [(set QPR:$Vd, + (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + +def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1, + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + IIC_VMOVImm, + "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", + [(set QPR:$Vd, + (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { + let Inst{11-9} = SIMM{11-9}; +} + + // VBIC : Vector Bitwise Bit Clear (AND NOT) def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118201&r1=118200&r2=118201&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Wed Nov 3 17:44:51 2010 @@ -505,3 +505,23 @@ %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> ret <4 x i32> %tmp5 } + +define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { +; CHECK: v_orrimm: +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vorr + %tmp1 = load <8 x i8>* %A + %tmp3 = or <8 x i8> %tmp1, + ret <8 x i8> %tmp3 +} + +define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { +; CHECK: v_orrimmQ +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vorr + %tmp1 = load <16 x i8>* %A + %tmp3 = or <16 x i8> %tmp1, + ret <16 x i8> %tmp3 +} Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118201&r1=118200&r2=118201&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Wed Nov 3 17:44:51 2010 @@ -1,4 +1,5 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * @ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] vand d16, d17, d16 @@ -14,6 +15,10 @@ vorr d16, d17, d16 @ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] vorr q8, q8, q9 +@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2] + vorr.i32 d16, #0x1000000 +@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] + vorr.i32 q8, #0x1000000 @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] vbic d16, d17, d16 From ismail at namtrac.org Wed Nov 3 17:54:08 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Thu, 4 Nov 2010 00:54:08 +0200 Subject: [llvm-commits] PATCH: Fix PR8528 Message-ID: Hi; Original patch by pdox on #llvm . Asm parser was not handling fist and fistp instructions correctly. Please apply. Regards, ismail -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101104/d360dcae/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: PR8528.patch Type: application/octet-stream Size: 1112 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101104/d360dcae/attachment.obj From resistor at mac.com Wed Nov 3 18:15:27 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 03 Nov 2010 23:15:27 -0000 Subject: [llvm-commits] [llvm] r118204 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s Message-ID: <20101103231527.261332A6C12C@llvm.org> Author: resistor Date: Wed Nov 3 18:15:26 2010 New Revision: 118204 URL: http://llvm.org/viewvc/llvm-project?rev=118204&view=rev Log: Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/vbits.ll llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118204&r1=118203&r2=118204&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 18:15:26 2010 @@ -101,7 +101,6 @@ setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); - setOperationAction(ISD::OR, VT.getSimpleVT(), Custom); setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; @@ -3433,32 +3432,6 @@ return SDValue(); } -static SDValue LowerOR(SDValue Op, SelectionDAG &DAG) { - SDValue Op1 = Op.getOperand(1); - while (Op1.getOpcode() == ISD::BIT_CONVERT && Op1.getOperand(0) != Op1) - Op1 = Op1.getOperand(0); - if (Op1.getOpcode() != ARMISD::VMOVIMM) return Op; - - ConstantSDNode* TargetConstant = cast(Op1.getOperand(0)); - uint32_t ConstVal = TargetConstant->getZExtValue(); - - // FIXME: VORRIMM only supports immediate encodings of 16 and 32 bit size. - // In theory for VMOVIMMs whose value is already encoded as with an - // 8 bit encoding, we could re-encode it as a 16 or 32 bit immediate. - EVT VorrVT = Op1.getValueType(); - EVT EltVT = VorrVT.getVectorElementType(); - if (EltVT != MVT::i16 && EltVT != MVT::i32) return Op; - - ConstVal |= 0x0100; - SDValue OrConst = DAG.getTargetConstant(ConstVal, MVT::i32); - - DebugLoc dl = Op.getDebugLoc(); - EVT VT = Op.getValueType(); - SDValue toTy = DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, Op.getOperand(0)); - SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, toTy, OrConst); - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr); -} - // If this is a case we can't handle, return null and let the default // expansion code take care of it. static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, @@ -3927,7 +3900,6 @@ case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); case ISD::MUL: return LowerMUL(Op, DAG); - case ISD::OR: return LowerOR(Op, DAG); } return SDValue(); } @@ -4474,6 +4446,31 @@ static SDValue PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) { + // Attempt to use immediate-form VORR + BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1)); + DebugLoc dl = N->getDebugLoc(); + EVT VT = N->getValueType(0); + SelectionDAG &DAG = DCI.DAG; + + APInt SplatBits, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (BVN && Subtarget->hasNEON() && + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { + if (SplatBitSize <= 64) { + EVT VorrVT; + SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), + SplatUndef.getZExtValue(), SplatBitSize, + DAG, VorrVT, VT.is128BitVector(), false); + if (Val.getNode()) { + SDValue Input = + DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, N->getOperand(0)); + SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr); + } + } + } + // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when // reasonable. @@ -4481,7 +4478,6 @@ if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) return SDValue(); - SelectionDAG &DAG = DCI.DAG; SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); DebugLoc DL = N->getDebugLoc(); // 1) or (and A, mask), val => ARMbfi A, val, mask @@ -4496,7 +4492,6 @@ if (N0.getOpcode() != ISD::AND) return SDValue(); - EVT VT = N->getValueType(0); if (VT != MVT::i32) return SDValue(); @@ -4565,7 +4560,7 @@ DCI.CombineTo(N, Res, false); } } - + return SDValue(); } Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118204&r1=118203&r2=118204&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Wed Nov 3 18:15:26 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: v_andi8: Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118204&r1=118203&r2=118204&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Wed Nov 3 18:15:26 2010 @@ -19,6 +19,8 @@ vorr.i32 d16, #0x1000000 @ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] vorr.i32 q8, #0x1000000 +@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] + vorr.i32 q8, #0x0 @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] vbic d16, d17, d16 From bob.wilson at apple.com Wed Nov 3 18:32:38 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 3 Nov 2010 16:32:38 -0700 Subject: [llvm-commits] [llvm] r118204 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s In-Reply-To: <20101103231527.261332A6C12C@llvm.org> References: <20101103231527.261332A6C12C@llvm.org> Message-ID: Thanks, Owen. I like this better. The "setTargetDAGCombine(ISD::OR)" call is currently guarded by Subtarget->hasV6T2Ops(); it would be good to also call that for Subtarget->hasNEON(). The isNEONModifiedImm function currently distinguishes VMOV vs. non-VMOV immediates. The encodings with cmode=1100 and 1101 are only available with VMOV and VMVN, so you need to add another parameter or change "isVMOV" to be an enum so that it can distinguish VORR/VBIC from VMOV/VMVN for those encodings. On Nov 3, 2010, at 4:15 PM, Owen Anderson wrote: > Author: resistor > Date: Wed Nov 3 18:15:26 2010 > New Revision: 118204 > > URL: http://llvm.org/viewvc/llvm-project?rev=118204&view=rev > Log: > Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. > This is both the conceptually correct place for it, as well as allowing it to be more aggressive. > > Modified: > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/test/CodeGen/ARM/vbits.ll > llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118204&r1=118203&r2=118204&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 3 18:15:26 2010 > @@ -101,7 +101,6 @@ > setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); > setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); > setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); > - setOperationAction(ISD::OR, VT.getSimpleVT(), Custom); > setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); > setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); > for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; > @@ -3433,32 +3432,6 @@ > return SDValue(); > } > > -static SDValue LowerOR(SDValue Op, SelectionDAG &DAG) { > - SDValue Op1 = Op.getOperand(1); > - while (Op1.getOpcode() == ISD::BIT_CONVERT && Op1.getOperand(0) != Op1) > - Op1 = Op1.getOperand(0); > - if (Op1.getOpcode() != ARMISD::VMOVIMM) return Op; > - > - ConstantSDNode* TargetConstant = cast(Op1.getOperand(0)); > - uint32_t ConstVal = TargetConstant->getZExtValue(); > - > - // FIXME: VORRIMM only supports immediate encodings of 16 and 32 bit size. > - // In theory for VMOVIMMs whose value is already encoded as with an > - // 8 bit encoding, we could re-encode it as a 16 or 32 bit immediate. > - EVT VorrVT = Op1.getValueType(); > - EVT EltVT = VorrVT.getVectorElementType(); > - if (EltVT != MVT::i16 && EltVT != MVT::i32) return Op; > - > - ConstVal |= 0x0100; > - SDValue OrConst = DAG.getTargetConstant(ConstVal, MVT::i32); > - > - DebugLoc dl = Op.getDebugLoc(); > - EVT VT = Op.getValueType(); > - SDValue toTy = DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, Op.getOperand(0)); > - SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, toTy, OrConst); > - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr); > -} > - > // If this is a case we can't handle, return null and let the default > // expansion code take care of it. > static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, > @@ -3927,7 +3900,6 @@ > case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); > case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); > case ISD::MUL: return LowerMUL(Op, DAG); > - case ISD::OR: return LowerOR(Op, DAG); > } > return SDValue(); > } > @@ -4474,6 +4446,31 @@ > static SDValue PerformORCombine(SDNode *N, > TargetLowering::DAGCombinerInfo &DCI, > const ARMSubtarget *Subtarget) { > + // Attempt to use immediate-form VORR > + BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1)); > + DebugLoc dl = N->getDebugLoc(); > + EVT VT = N->getValueType(0); > + SelectionDAG &DAG = DCI.DAG; > + > + APInt SplatBits, SplatUndef; > + unsigned SplatBitSize; > + bool HasAnyUndefs; > + if (BVN && Subtarget->hasNEON() && > + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { > + if (SplatBitSize <= 64) { > + EVT VorrVT; > + SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), > + SplatUndef.getZExtValue(), SplatBitSize, > + DAG, VorrVT, VT.is128BitVector(), false); > + if (Val.getNode()) { > + SDValue Input = > + DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, N->getOperand(0)); > + SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); > + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr); > + } > + } > + } > + > // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when > // reasonable. > > @@ -4481,7 +4478,6 @@ > if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) > return SDValue(); > > - SelectionDAG &DAG = DCI.DAG; > SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); > DebugLoc DL = N->getDebugLoc(); > // 1) or (and A, mask), val => ARMbfi A, val, mask > @@ -4496,7 +4492,6 @@ > if (N0.getOpcode() != ISD::AND) > return SDValue(); > > - EVT VT = N->getValueType(0); > if (VT != MVT::i32) > return SDValue(); > > @@ -4565,7 +4560,7 @@ > DCI.CombineTo(N, Res, false); > } > } > - > + > return SDValue(); > } > > > Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118204&r1=118203&r2=118204&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Wed Nov 3 18:15:26 2010 > @@ -1,4 +1,4 @@ > -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s > +; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s > > define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { > ;CHECK: v_andi8: > > Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118204&r1=118203&r2=118204&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) > +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Wed Nov 3 18:15:26 2010 > @@ -19,6 +19,8 @@ > vorr.i32 d16, #0x1000000 > @ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] > vorr.i32 q8, #0x1000000 > +@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] > + vorr.i32 q8, #0x0 > > @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] > vbic d16, d17, d16 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Nov 3 18:38:14 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 23:38:14 -0000 Subject: [llvm-commits] [llvm] r118206 - /llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Message-ID: <20101103233814.C24F72A6C12C@llvm.org> Author: grosbach Date: Wed Nov 3 18:38:14 2010 New Revision: 118206 URL: http://llvm.org/viewvc/llvm-project?rev=118206&view=rev Log: Support generating an MC'ized CodeEmitter directly. Maintain a reference to the Fixups list for the instruction so the operand encoders can add to it as needed. Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=118206&r1=118205&r2=118206&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Wed Nov 3 18:38:14 2010 @@ -21,8 +21,11 @@ #include "llvm/Support/Debug.h" using namespace llvm; +// FIXME: Somewhat hackish to use a command line option for this. There should +// be a CodeEmitter class in the Target.td that controls this sort of thing +// instead. static cl::opt -MCEmitter("mc-code-emitter", +MCEmitter("mc-emitter", cl::desc("Generate CodeEmitter for use with the MC library."), cl::init(false)); @@ -84,8 +87,12 @@ Target.getInstructionsByEnumValue(); // Emit function declaration - o << "unsigned " << Target.getName() << "CodeEmitter::" - << "getBinaryCodeForInstr(const MachineInstr &MI) const {\n"; + o << "unsigned " << Target.getName(); + if (MCEmitter) + o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + << " SmallVectorImpl &Fixups) const {\n"; + else + o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n"; // Emit instruction base values o << " static const unsigned InstBits[] = {\n"; @@ -188,12 +195,18 @@ if (SO.second == 0) { Case += " // op: " + VarName + "\n" + " op = " + EncoderMethodName + "(MI, " - + utostr(OpIdx) + ");\n"; + + utostr(OpIdx); + if (MCEmitter) + Case += ", Fixups"; + Case += ");\n"; } } else { Case += " // op: " + VarName + "\n" + " op = getMachineOpValue(MI, MI.getOperand(" - + utostr(OpIdx) + "));\n"; + + utostr(OpIdx) + ")"; + if (MCEmitter) + Case += ", Fixups"; + Case += ");\n"; } gotOp = true; } From grosbach at apple.com Wed Nov 3 18:46:01 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 03 Nov 2010 23:46:01 -0000 Subject: [llvm-commits] [llvm] r118207 - /llvm/trunk/Makefile.rules Message-ID: <20101103234601.C96812A6C12C@llvm.org> Author: grosbach Date: Wed Nov 3 18:46:01 2010 New Revision: 118207 URL: http://llvm.org/viewvc/llvm-project?rev=118207&view=rev Log: Add rule to build MC'ized CodeEmitter. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=118207&r1=118206&r2=118207&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Nov 3 18:46:01 2010 @@ -1721,6 +1721,11 @@ $(Echo) "Building $( Author: grosbach Date: Wed Nov 3 18:52:49 2010 New Revision: 118209 URL: http://llvm.org/viewvc/llvm-project?rev=118209&view=rev Log: Teach ARM Target to use the tblgen support for generating an MC'ized CodeEmitter. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/ARM/Makefile Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118209&r1=118208&r2=118209&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Nov 3 18:52:49 2010 @@ -43,31 +43,38 @@ // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. - unsigned getBinaryCodeForInstr(const MCInst &MI) const; + unsigned getBinaryCodeForInstr(const MCInst &MI, + SmallVectorImpl &Fixups) const; /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. - unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; + unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, + SmallVectorImpl &Fixups) const; bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, - unsigned &Reg, unsigned &Imm) const; + unsigned &Reg, unsigned &Imm, + SmallVectorImpl &Fixups) const; /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' /// operand. - uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx) const; + uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. - uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx) const; + uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; /// getCCOutOpValue - Return encoding of the 's' bit. - unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const { + unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or // '1' respectively. return MI.getOperand(Op).getReg() == ARM::CPSR; } /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. - unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const { + unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { unsigned SoImm = MI.getOperand(Op).getImm(); int SoImmVal = ARM_AM::getSOImmVal(SoImm); assert(SoImmVal != -1 && "Not a valid so_imm value!"); @@ -82,9 +89,11 @@ } /// getSORegOpValue - Return an encoded so_reg shifted register value. - unsigned getSORegOpValue(const MCInst &MI, unsigned Op) const; + unsigned getSORegOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; - unsigned getRotImmOpValue(const MCInst &MI, unsigned Op) const { + unsigned getRotImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { switch (MI.getOperand(Op).getImm()) { default: assert (0 && "Not a valid rot_imm value!"); case 0: return 0; @@ -94,19 +103,25 @@ } } - unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const { + unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { return MI.getOperand(Op).getImm() - 1; } - unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op) const { + unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { return 64 - MI.getOperand(Op).getImm(); } - unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const; + unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; - unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const; - unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const; - unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const; + unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; + unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; + unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); @@ -146,8 +161,9 @@ /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. -unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, - const MCOperand &MO) const { +unsigned ARMMCCodeEmitter:: +getMachineOpValue(const MCInst &MI, const MCOperand &MO, + SmallVectorImpl &Fixups) const { if (MO.isReg()) { unsigned Reg = MO.getReg(); unsigned RegNo = getARMRegisterNumbering(Reg); @@ -177,9 +193,9 @@ } /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. -bool ARMMCCodeEmitter::EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, - unsigned &Reg, - unsigned &Imm) const { +bool ARMMCCodeEmitter:: +EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, + unsigned &Imm, SmallVectorImpl &Fixups) const { const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); @@ -211,13 +227,14 @@ } /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. -uint32_t ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI, - unsigned OpIdx) const { +uint32_t ARMMCCodeEmitter:: +getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { // {17-13} = reg // {12} = (U)nsigned (add == '1', sub == '0') // {11-0} = imm12 unsigned Reg, Imm12; - bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12); + bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); if (Reg == ARM::PC) return ARM::PC << 13; // Rn is PC; @@ -231,13 +248,14 @@ } /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand. -uint32_t ARMMCCodeEmitter::getAddrMode5OpValue(const MCInst &MI, - unsigned OpIdx) const { +uint32_t ARMMCCodeEmitter:: +getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { // {12-9} = reg // {8} = (U)nsigned (add == '1', sub == '0') // {7-0} = imm8 unsigned Reg, Imm8; - EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8); + EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); if (Reg == ARM::PC) return ARM::PC << 9; // Rn is PC; @@ -250,8 +268,9 @@ return Binary; } -unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI, - unsigned OpIdx) const { +unsigned ARMMCCodeEmitter:: +getSORegOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be // shifted. The second is either Rs, the amount to shift by, or reg0 in which // case the imm contains the amount to shift by. @@ -321,8 +340,9 @@ return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; } -unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI, - unsigned Op) const { +unsigned ARMMCCodeEmitter:: +getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the // msb of the mask. const MCOperand &MO = MI.getOperand(Op); @@ -333,8 +353,9 @@ return lsb | (msb << 5); } -unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, - unsigned Op) const { +unsigned ARMMCCodeEmitter:: +getRegisterListOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each // register in the list, set the corresponding bit. unsigned Binary = 0; @@ -345,8 +366,9 @@ return Binary; } -unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI, - unsigned Op) const { +unsigned ARMMCCodeEmitter:: +getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Imm = MI.getOperand(Op + 1); @@ -365,8 +387,9 @@ return RegNo | (Align << 4); } -unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI, - unsigned Op) const { +unsigned ARMMCCodeEmitter:: +getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { const MCOperand &MO = MI.getOperand(Op); if (MO.getReg() == 0) return 0x0D; return MO.getReg(); @@ -374,7 +397,7 @@ void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl &) const { + SmallVectorImpl &Fixups) const { // Pseudo instructions don't get encoded. const TargetInstrDesc &Desc = TII.get(MI.getOpcode()); if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo) @@ -382,15 +405,8 @@ // Keep track of the current byte being emitted. unsigned CurByte = 0; - EmitConstant(getBinaryCodeForInstr(MI), 4, CurByte, OS); + EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, CurByte, OS); ++MCNumEmitted; // Keep track of the # of mi's emitted. } -// FIXME: These #defines shouldn't be necessary. Instead, tblgen should -// be able to generate code emitter helpers for either variant, like it -// does for the AsmWriter. -#define ARMCodeEmitter ARMMCCodeEmitter -#define MachineInstr MCInst -#include "ARMGenCodeEmitter.inc" -#undef ARMCodeEmitter -#undef MachineInstr +#include "ARMGenMCCodeEmitter.inc" Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=118209&r1=118208&r2=118209&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Nov 3 18:52:49 2010 @@ -6,6 +6,7 @@ tablegen(ARMGenInstrNames.inc -gen-instr-enums) tablegen(ARMGenInstrInfo.inc -gen-instr-desc) tablegen(ARMGenCodeEmitter.inc -gen-emitter) +tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(ARMGenAsmWriter.inc -gen-asm-writer) tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher) tablegen(ARMGenDAGISel.inc -gen-dag-isel) Modified: llvm/trunk/lib/Target/ARM/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=118209&r1=118208&r2=118209&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Makefile (original) +++ llvm/trunk/lib/Target/ARM/Makefile Wed Nov 3 18:52:49 2010 @@ -18,7 +18,7 @@ ARMGenDAGISel.inc ARMGenSubtarget.inc \ ARMGenCodeEmitter.inc ARMGenCallingConv.inc \ ARMGenDecoderTables.inc ARMGenEDInfo.inc \ - ARMGenFastISel.inc + ARMGenFastISel.inc ARMGenMCCodeEmitter.inc DIRS = InstPrinter AsmParser Disassembler TargetInfo From aggarwa4 at illinois.edu Wed Nov 3 18:58:24 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 03 Nov 2010 23:58:24 -0000 Subject: [llvm-commits] [poolalloc] r118210 - /poolalloc/trunk/lib/DSA/DataStructure.cpp Message-ID: <20101103235824.9FE542A6C12C@llvm.org> Author: aggarwa4 Date: Wed Nov 3 18:58:24 2010 New Revision: 118210 URL: http://llvm.org/viewvc/llvm-project?rev=118210&view=rev Log: Allow scalar type to be merged into an array node if the size is the same. Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=118210&r1=118209&r2=118210&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Wed Nov 3 18:58:24 2010 @@ -793,8 +793,11 @@ if ((SN->isArrayNode() && !DN->isArrayNode()) || (!SN->isArrayNode() && DN->isArrayNode())) { - DN->foldNodeCompletely(); - DN = NH.getNode(); + if(SN->getSize() != 0 && DN->getSize() != 0 + && (SN->getSize() != DN->getSize())){ + DN->foldNodeCompletely(); + DN = NH.getNode(); + } } if ((SN->isArrayNode() && DN->isArrayNode()) && (SN->getSize() != DN->getSize())) { From stoklund at 2pi.dk Wed Nov 3 19:32:32 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 04 Nov 2010 00:32:32 -0000 Subject: [llvm-commits] [llvm] r118216 - /llvm/trunk/lib/CodeGen/InlineSpiller.cpp Message-ID: <20101104003232.CC99C2A6C12C@llvm.org> Author: stoklund Date: Wed Nov 3 19:32:32 2010 New Revision: 118216 URL: http://llvm.org/viewvc/llvm-project?rev=118216&view=rev Log: Disable fancy splitting during spilling unless -extra-spiller-splits is given. This way, InlineSpiller does the same amount of splitting as the standard spiller. Splitting should really be guided by the register allocator, and doesn't belong in the spiller at all. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=118216&r1=118215&r2=118216&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Nov 3 19:32:32 2010 @@ -35,6 +35,10 @@ static cl::opt VerifySpills("verify-spills", cl::desc("Verify after each spill/split")); +static cl::opt +ExtraSpillerSplits("extra-spiller-splits", + cl::desc("Enable additional splitting during splitting")); + namespace { class InlineSpiller : public Spiller { MachineFunctionPass &pass_; @@ -116,10 +120,13 @@ splitAnalysis_.analyze(&edit_->getParent()); // Try splitting around loops. - if (const MachineLoop *loop = splitAnalysis_.getBestSplitLoop()) { - SplitEditor(splitAnalysis_, lis_, vrm_, mdt_, *edit_) - .splitAroundLoop(loop); - return true; + if (ExtraSpillerSplits) { + const MachineLoop *loop = splitAnalysis_.getBestSplitLoop(); + if (loop) { + SplitEditor(splitAnalysis_, lis_, vrm_, mdt_, *edit_) + .splitAroundLoop(loop); + return true; + } } // Try splitting into single block intervals. @@ -131,10 +138,13 @@ } // Try splitting inside a basic block. - if (const MachineBasicBlock *MBB = splitAnalysis_.getBlockForInsideSplit()) { - SplitEditor(splitAnalysis_, lis_, vrm_, mdt_, *edit_) - .splitInsideBlock(MBB); - return true; + if (ExtraSpillerSplits) { + const MachineBasicBlock *MBB = splitAnalysis_.getBlockForInsideSplit(); + if (MBB){ + SplitEditor(splitAnalysis_, lis_, vrm_, mdt_, *edit_) + .splitInsideBlock(MBB); + return true; + } } return false; From sabre at nondot.org Wed Nov 3 19:43:46 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 04 Nov 2010 00:43:46 -0000 Subject: [llvm-commits] [llvm] r118217 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101104004346.5FB7F2A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 19:43:46 2010 New Revision: 118217 URL: http://llvm.org/viewvc/llvm-project?rev=118217&view=rev Log: take a big step to making aliases more general and less of a hack: now matchables contain an explicit list of how to populate each operand in the result instruction instead of having them somehow magically be correlated to the input inst. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118217&r1=118216&r2=118217&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 19:43:46 2010 @@ -81,7 +81,6 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" -#include #include #include using namespace llvm; @@ -258,6 +257,55 @@ explicit AsmOperand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} }; + + /// ResOperand - This represents a single operand in the result instruction + /// generated by the match. In cases (like addressing modes) where a single + /// assembler operand expands to multiple MCOperands, this represents the + /// single assembler operand, not the MCOperand. + struct ResOperand { + enum { + /// RenderAsmOperand - This represents an operand result that is + /// generated by calling the render method on the assembly operand. The + /// corresponding AsmOperand is specified by AsmOperandNum. + RenderAsmOperand, + + /// TiedOperand - This represents a result operand that is a duplicate of + /// a previous result operand. + TiedOperand + } Kind; + + union { + /// This is the operand # in the AsmOperands list that this should be + /// copied from. + unsigned AsmOperandNum; + + /// TiedOperandNum - This is the (earlier) result operand that should be + /// copied from. + unsigned TiedOperandNum; + }; + + /// OpInfo - This is the information about the instruction operand that is + /// being populated. + const CGIOperandList::OperandInfo *OpInfo; + + static ResOperand getRenderedOp(unsigned AsmOpNum, + const CGIOperandList::OperandInfo *Op) { + ResOperand X; + X.Kind = RenderAsmOperand; + X.AsmOperandNum = AsmOpNum; + X.OpInfo = Op; + return X; + } + + static ResOperand getTiedOp(unsigned TiedOperandNum, + const CGIOperandList::OperandInfo *Op) { + ResOperand X; + X.Kind = TiedOperand; + X.TiedOperandNum = TiedOperandNum; + X.OpInfo = Op; + return X; + } + }; /// InstrName - The target name for this instruction. std::string InstrName; @@ -266,9 +314,13 @@ /// matchable came from. Record *const TheDef; - /// OperandList - This is the operand list that came from the (ins) and (outs) - /// list of the alias or instruction. - const CGIOperandList &OperandList; + // FIXME: REMOVE. + const CGIOperandList &TheOperandList; + + + /// ResOperands - This is the operand list that should be built for the result + /// MCInst. + std::vector ResOperands; /// AsmString - The assembly string for this instruction (with variants /// removed), e.g. "movsx $src, $dst". @@ -293,12 +345,12 @@ std::string ConversionFnKind; MatchableInfo(const CodeGenInstruction &CGI) - : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) { + : TheDef(CGI.TheDef), TheOperandList(CGI.Operands), AsmString(CGI.AsmString) { InstrName = TheDef->getName(); } MatchableInfo(const CodeGenInstAlias *Alias) - : TheDef(Alias->TheDef), OperandList(Alias->Operands), + : TheDef(Alias->TheDef), TheOperandList(Alias->Operands), AsmString(Alias->AsmString) { // FIXME: Huge hack. @@ -320,6 +372,8 @@ Record *getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const; + void BuildResultOperands(); + /// operator< - Compare two matchables. bool operator<(const MatchableInfo &RHS) const { // The primary comparator is the instruction mnemonic. @@ -452,6 +506,9 @@ /// operand classes. void BuildOperandClasses(); + void BuildInstructionOperandReference(MatchableInfo *II, + MatchableInfo::AsmOperand &Op); + public: AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target); @@ -652,33 +709,6 @@ } } - // Validate the operand list to ensure we can handle this instruction. - for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OI = OperandList[i]; - - // Validate tied operands. - if (OI.getTiedRegister() != -1) { - // If we have a tied operand that consists of multiple MCOperands, reject - // it. We reject aliases and ignore instructions for now. - if (OI.MINumOperands != 1) { - if (!Hack) - throw TGError(TheDef->getLoc(), - "ERROR: tied operand '" + OI.Name + - "' has multiple MCOperands!"); - - // FIXME: Should reject these. The ARM backend hits this with $lane in a - // bunch of instructions. It is unclear what the right answer is. - DEBUG({ - errs() << "warning: '" << InstrName << "': " - << "ignoring instruction with multi-operand tied operand '" - << OI.Name << "'\n"; - }); - return false; - } - } - } - - return true; } @@ -944,6 +974,52 @@ RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { } +/// BuildInstructionOperandReference - The specified operand is a reference to a +/// named operand such as $src. Resolve the Class and OperandInfo pointers. +void AsmMatcherInfo:: +BuildInstructionOperandReference(MatchableInfo *II, + MatchableInfo::AsmOperand &Op) { + StringRef Token = Op.Token; + assert(Token[0] == '$' && "Not an operand name ref"); + + StringRef OperandName; + if (Token[1] == '{') + OperandName = Token.substr(2, Token.size() - 3); + else + OperandName = Token.substr(1); + + const CGIOperandList &Operands = II->TheOperandList; + + + // Map this token to an operand. FIXME: Move elsewhere. + unsigned Idx; + if (!Operands.hasOperandNamed(OperandName, Idx)) + throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + + OperandName.str() + "'"); + + // FIXME: This is annoying, the named operand may be tied (e.g., + // XCHG8rm). What we want is the untied operand, which we now have to + // grovel for. Only worry about this for single entry operands, we have to + // clean this up anyway. + const CGIOperandList::OperandInfo *OI = &Operands[Idx]; + int OITied = OI->getTiedRegister(); + if (OITied != -1) { + // The tied operand index is an MIOperand index, find the operand that + // contains it. + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (Operands[i].MIOperandNo == unsigned(OITied)) { + OI = &Operands[i]; + break; + } + } + + assert(OI && "Unable to find tied operand target!"); + } + + Op.Class = getOperandClass(Token, *OI); + Op.OperandInfo = OI; +} + void AsmMatcherInfo::BuildInfo() { // Build information about all of the AssemblerPredicates. @@ -981,6 +1057,27 @@ if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) continue; + // Validate the operand list to ensure we can handle this instruction. + for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OI = CGI.Operands[i]; + + // Validate tied operands. + if (OI.getTiedRegister() != -1) { + // If we have a tied operand that consists of multiple MCOperands, reject + // it. We reject aliases and ignore instructions for now. + if (OI.MINumOperands != 1) { + // FIXME: Should reject these. The ARM backend hits this with $lane + // in a bunch of instructions. It is unclear what the right answer is. + DEBUG({ + errs() << "warning: '" << CGI.TheDef->getName() << "': " + << "ignoring instruction with multi-operand tied operand '" + << OI.Name << "'\n"; + }); + continue; + } + } + } + OwningPtr II(new MatchableInfo(CGI)); II->Initialize(*this, SingletonRegisters); @@ -1048,46 +1145,56 @@ } // Otherwise this is an operand reference. - StringRef OperandName; - if (Token[1] == '{') - OperandName = Token.substr(2, Token.size() - 3); - else - OperandName = Token.substr(1); - - // Map this token to an operand. FIXME: Move elsewhere. - unsigned Idx; - if (!II->OperandList.hasOperandNamed(OperandName, Idx)) - throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + - OperandName.str() + "'"); - - // FIXME: This is annoying, the named operand may be tied (e.g., - // XCHG8rm). What we want is the untied operand, which we now have to - // grovel for. Only worry about this for single entry operands, we have to - // clean this up anyway. - const CGIOperandList::OperandInfo *OI = &II->OperandList[Idx]; - int OITied = OI->getTiedRegister(); - if (OITied != -1) { - // The tied operand index is an MIOperand index, find the operand that - // contains it. - for (unsigned i = 0, e = II->OperandList.size(); i != e; ++i) { - if (II->OperandList[i].MIOperandNo == unsigned(OITied)) { - OI = &II->OperandList[i]; - break; - } - } - - assert(OI && "Unable to find tied operand target!"); - } - - Op.Class = getOperandClass(Token, *OI); - Op.OperandInfo = OI; + BuildInstructionOperandReference(II, Op); } + + II->BuildResultOperands(); } // Reorder classes so that classes preceed super classes. std::sort(Classes.begin(), Classes.end(), less_ptr()); } +void MatchableInfo::BuildResultOperands() { + /// OperandMap - This is a mapping from the MCInst operands (specified by the + /// II.OperandList operands) to the AsmOperands that they are filled in from. + SmallVector OperandMap(TheOperandList.size(), -1); + + // Order the (class) operands by the order to convert them into an MCInst. + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + MatchableInfo::AsmOperand &Op = AsmOperands[i]; + if (!Op.OperandInfo) continue; + + + // FIXME: eliminate the mapping+unmapping. + unsigned LogicalOpNum = Op.OperandInfo - &TheOperandList[0]; + assert(LogicalOpNum < OperandMap.size() && "Invalid operand number"); + OperandMap[LogicalOpNum] = i; + } + + for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OpInfo = TheOperandList[i]; + + // Find out what operand from the asmparser that this MCInst operand comes + // from. + int SrcOperand = OperandMap[i]; + if (SrcOperand != -1) { + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); + continue; + } + + // Otherwise, this must be a tied operand. + int TiedOp = OpInfo.getTiedRegister(); + if (TiedOp == -1) + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); + + ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); + } +} + + static void EmitConvertToMCInst(CodeGenTarget &Target, std::vector &Infos, raw_ostream &OS) { @@ -1100,7 +1207,6 @@ std::set GeneratedFns; // Start the unified conversion function. - CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, " << "unsigned Opcode,\n" << " const SmallVectorImpl OperandMap; - for (std::vector::const_iterator it = Infos.begin(), ie = Infos.end(); it != ie; ++it) { MatchableInfo &II = **it; - OperandMap.clear(); - OperandMap.resize(II.OperandList.size(), -1); - - // Order the (class) operands by the order to convert them into an MCInst. - for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { - MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; - if (!Op.OperandInfo) continue; - - unsigned LogicalOpNum = Op.OperandInfo - &II.OperandList[0]; - assert(LogicalOpNum < OperandMap.size() && "Invalid operand number"); - OperandMap[LogicalOpNum] = i; - } - // Build the conversion function signature. std::string Signature = "Convert"; std::string CaseBody; raw_string_ostream CaseOS(CaseBody); // Compute the convert enum and the case body. - for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i]; + for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { + const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; - // Find out what operand from the asmparser that this MCInst operand comes - // from. - int SrcOperand = OperandMap[i]; - if (SrcOperand != -1) { - // Otherwise, this comes from something we parsed. - MatchableInfo::AsmOperand &Op = II.AsmOperands[SrcOperand]; + // Generate code to populate each result operand. + switch (OpInfo.Kind) { + default: assert(0 && "Unknown result operand kind"); + case MatchableInfo::ResOperand::RenderAsmOperand: { + // This comes from something we parsed. + MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; // Registers are always converted the same, don't duplicate the // conversion function based on them. @@ -1162,29 +1251,25 @@ else Signature += Op.Class->ClassName; Signature += utostr(Op.OperandInfo->MINumOperands); - Signature += "_" + itostr(SrcOperand); + Signature += "_" + itostr(OpInfo.AsmOperandNum); CaseOS << " ((" << TargetOperandClass << "*)Operands[" - << SrcOperand << "+1])->" << Op.Class->RenderMethod + << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; - continue; + break; + } + + case MatchableInfo::ResOperand::TiedOperand: { + // If this operand is tied to a previous one, just copy the MCInst + // operand from the earlier one.We can only tie single MCOperand values. + //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand"); + unsigned TiedOp = OpInfo.TiedOperandNum; + assert(i > TiedOp && "Tied operand preceeds its target!"); + CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; + Signature += "__Tie" + utostr(TiedOp); + break; + } } - - // Otherwise, this must be a tied operand if not, it is something that is - // mentioned in the ins/outs list but not in the asm string. - int TiedOp = OpInfo.getTiedRegister(); - if (TiedOp == -1) - throw TGError(II.TheDef->getLoc(), "Instruction '" + - II.TheDef->getName() + "' has operand '" + OpInfo.Name + - "' that doesn't appear in asm string!"); - - // If this operand is tied to a previous one, just copy the MCInst operand - // from the earlier one. - // Copy the tied operand. We can only tie single MCOperand values. - assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); - assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!"); - CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; - Signature += "__Tie" + itostr(TiedOp); } II.ConversionFnKind = Signature; From sabre at nondot.org Wed Nov 3 19:57:06 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 04 Nov 2010 00:57:06 -0000 Subject: [llvm-commits] [llvm] r118219 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101104005706.6573E2A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 19:57:06 2010 New Revision: 118219 URL: http://llvm.org/viewvc/llvm-project?rev=118219&view=rev Log: strength reduce some code, resolving a fixme. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118219&r1=118218&r2=118219&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 19:57:06 2010 @@ -250,12 +250,10 @@ /// The unique class instance this operand should match. ClassInfo *Class; - /// The original operand this corresponds to. This is unset for singleton - /// registers and tokens, because they don't have a list in the ins/outs - /// list. If an operand is tied ($a=$b), this refers to source operand: $b. - const CGIOperandList::OperandInfo *OperandInfo; + /// The original operand this corresponds to. + int SrcOpNum; - explicit AsmOperand(StringRef T) : Token(T), Class(0), OperandInfo(0) {} + explicit AsmOperand(StringRef T) : Token(T), Class(0), SrcOpNum(-1) {} }; /// ResOperand - This represents a single operand in the result instruction @@ -533,11 +531,8 @@ for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { AsmOperand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; - if (Op.Class->Kind == ClassInfo::Token) { - errs() << '\"' << Op.Token << "\"\n"; - continue; - } - + errs() << '\"' << Op.Token << "\"\n"; +#if 0 if (!Op.OperandInfo) { errs() << "(singleton register)\n"; continue; @@ -546,6 +541,7 @@ const CGIOperandList::OperandInfo &OI = *Op.OperandInfo; errs() << OI.Name << " " << OI.Rec->getName() << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n"; +#endif } } @@ -974,52 +970,6 @@ RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { } -/// BuildInstructionOperandReference - The specified operand is a reference to a -/// named operand such as $src. Resolve the Class and OperandInfo pointers. -void AsmMatcherInfo:: -BuildInstructionOperandReference(MatchableInfo *II, - MatchableInfo::AsmOperand &Op) { - StringRef Token = Op.Token; - assert(Token[0] == '$' && "Not an operand name ref"); - - StringRef OperandName; - if (Token[1] == '{') - OperandName = Token.substr(2, Token.size() - 3); - else - OperandName = Token.substr(1); - - const CGIOperandList &Operands = II->TheOperandList; - - - // Map this token to an operand. FIXME: Move elsewhere. - unsigned Idx; - if (!Operands.hasOperandNamed(OperandName, Idx)) - throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + - OperandName.str() + "'"); - - // FIXME: This is annoying, the named operand may be tied (e.g., - // XCHG8rm). What we want is the untied operand, which we now have to - // grovel for. Only worry about this for single entry operands, we have to - // clean this up anyway. - const CGIOperandList::OperandInfo *OI = &Operands[Idx]; - int OITied = OI->getTiedRegister(); - if (OITied != -1) { - // The tied operand index is an MIOperand index, find the operand that - // contains it. - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].MIOperandNo == unsigned(OITied)) { - OI = &Operands[i]; - break; - } - } - - assert(OI && "Unable to find tied operand target!"); - } - - Op.Class = getOperandClass(Token, *OI); - Op.OperandInfo = OI; -} - void AsmMatcherInfo::BuildInfo() { // Build information about all of the AssemblerPredicates. @@ -1120,7 +1070,8 @@ // Build info for the user defined assembly operand classes. BuildOperandClasses(); - // Build the information about matchables. + // Build the information about matchables, now that we have fully formed + // classes. for (std::vector::iterator it = Matchables.begin(), ie = Matchables.end(); it != ie; ++it) { MatchableInfo *II = *it; @@ -1155,6 +1106,53 @@ std::sort(Classes.begin(), Classes.end(), less_ptr()); } +/// BuildInstructionOperandReference - The specified operand is a reference to a +/// named operand such as $src. Resolve the Class and OperandInfo pointers. +void AsmMatcherInfo:: +BuildInstructionOperandReference(MatchableInfo *II, + MatchableInfo::AsmOperand &Op) { + StringRef Token = Op.Token; + assert(Token[0] == '$' && "Not an operand name ref"); + + StringRef OperandName; + if (Token[1] == '{') + OperandName = Token.substr(2, Token.size() - 3); + else + OperandName = Token.substr(1); + + const CGIOperandList &Operands = II->TheOperandList; + + + // Map this token to an operand. FIXME: Move elsewhere. + unsigned Idx; + if (!Operands.hasOperandNamed(OperandName, Idx)) + throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + + OperandName.str() + "'"); + + // FIXME: This is annoying, the named operand may be tied (e.g., + // XCHG8rm). What we want is the untied operand, which we now have to + // grovel for. Only worry about this for single entry operands, we have to + // clean this up anyway. + const CGIOperandList::OperandInfo *OI = &Operands[Idx]; + int OITied = OI->getTiedRegister(); + if (OITied != -1) { + // The tied operand index is an MIOperand index, find the operand that + // contains it. + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (Operands[i].MIOperandNo == unsigned(OITied)) { + OI = &Operands[i]; + Idx = i; + break; + } + } + + assert(OI && "Unable to find tied operand target!"); + } + + Op.Class = getOperandClass(Token, *OI); + Op.SrcOpNum = Idx; +} + void MatchableInfo::BuildResultOperands() { /// OperandMap - This is a mapping from the MCInst operands (specified by the /// II.OperandList operands) to the AsmOperands that they are filled in from. @@ -1163,13 +1161,8 @@ // Order the (class) operands by the order to convert them into an MCInst. for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { MatchableInfo::AsmOperand &Op = AsmOperands[i]; - if (!Op.OperandInfo) continue; - - - // FIXME: eliminate the mapping+unmapping. - unsigned LogicalOpNum = Op.OperandInfo - &TheOperandList[0]; - assert(LogicalOpNum < OperandMap.size() && "Invalid operand number"); - OperandMap[LogicalOpNum] = i; + if (Op.SrcOpNum != -1) + OperandMap[Op.SrcOpNum] = i; } for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) { @@ -1250,12 +1243,12 @@ Signature += "Reg"; else Signature += Op.Class->ClassName; - Signature += utostr(Op.OperandInfo->MINumOperands); + Signature += utostr(OpInfo.OpInfo->MINumOperands); Signature += "_" + itostr(OpInfo.AsmOperandNum); CaseOS << " ((" << TargetOperandClass << "*)Operands[" << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod - << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; + << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n"; break; } From isanbard at gmail.com Wed Nov 3 19:59:42 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 04 Nov 2010 00:59:42 -0000 Subject: [llvm-commits] [llvm] r118220 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.s Message-ID: <20101104005942.71DE32A6C12C@llvm.org> Author: void Date: Wed Nov 3 19:59:42 2010 New Revision: 118220 URL: http://llvm.org/viewvc/llvm-project?rev=118220&view=rev Log: Add encoding for VSTR. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/test/MC/ARM/simple-fp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118220&r1=118219&r2=118220&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 3 19:59:42 2010 @@ -1461,6 +1461,17 @@ string opc, string asm, list pattern> : VFPI { + // Instruction operands. + bits<5> Dd; + bits<13> addr; + + // Encode instruction operands. + let Inst{23} = addr{8}; // U (add = (U == '1')) + let Inst{22} = Dd{4}; + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Dd{3-0}; + let Inst{7-0} = addr{7-0}; // imm8 + // TODO: Mark the instructions with the appropriate subtarget info. let Inst{27-24} = opcod1; let Inst{21-20} = opcod2; @@ -1476,6 +1487,17 @@ string opc, string asm, list pattern> : VFPI { + // Instruction operands. + bits<5> Sd; + bits<13> addr; + + // Encode instruction operands. + let Inst{23} = addr{8}; // U (add = (U == '1')) + let Inst{22} = Sd{0}; + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Sd{4-1}; + let Inst{7-0} = addr{7-0}; // imm8 + // TODO: Mark the instructions with the appropriate subtarget info. let Inst{27-24} = opcod1; let Inst{21-20} = opcod2; Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118220&r1=118219&r2=118220&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Nov 3 19:59:42 2010 @@ -54,43 +54,21 @@ def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), IIC_fpLoad64, "vldr", ".64\t$Dd, $addr", - [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> { - // Instruction operands. - bits<5> Dd; - bits<13> addr; - - // Encode instruction operands. - let Inst{23} = addr{8}; // U (add = (U == '1')) - let Inst{22} = Dd{4}; - let Inst{19-16} = addr{12-9}; // Rn - let Inst{15-12} = Dd{3-0}; - let Inst{7-0} = addr{7-0}; // imm8 -} + [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>; def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), IIC_fpLoad32, "vldr", ".32\t$Sd, $addr", - [(set SPR:$Sd, (load addrmode5:$addr))]> { - // Instruction operands. - bits<5> Sd; - bits<13> addr; - - // Encode instruction operands. - let Inst{23} = addr{8}; // U (add = (U == '1')) - let Inst{22} = Sd{0}; - let Inst{19-16} = addr{12-9}; // Rn - let Inst{15-12} = Sd{4-1}; - let Inst{7-0} = addr{7-0}; // imm8 -} + [(set SPR:$Sd, (load addrmode5:$addr))]>; } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' -def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr), - IIC_fpStore64, "vstr", ".64\t$src, $addr", - [(store (f64 DPR:$src), addrmode5:$addr)]>; - -def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr), - IIC_fpStore32, "vstr", ".32\t$src, $addr", - [(store SPR:$src, addrmode5:$addr)]>; +def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), + IIC_fpStore64, "vstr", ".64\t$Dd, $addr", + [(store (f64 DPR:$Dd), addrmode5:$addr)]>; + +def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), + IIC_fpStore32, "vstr", ".32\t$Sd, $addr", + [(store SPR:$Sd, addrmode5:$addr)]>; //===----------------------------------------------------------------------===// // Load / store multiple Instructions. Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=118220&r1=118219&r2=118220&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Wed Nov 3 19:59:42 2010 @@ -193,3 +193,17 @@ vldr.32 s5, [pc] vldr.32 s5, [pc,#0] vldr.32 s5, [pc,#-0] + +@ CHECK: vstr.64 d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed] +@ CHECK: vstr.64 d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed] +@ CHECK: vstr.64 d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed] + vstr.64 d4, [r1] + vstr.64 d4, [r1, #24] + vstr.64 d4, [r1, #-24] + +@ CHECK: vstr.32 s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed] +@ CHECK: vstr.32 s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed] +@ CHECK: vstr.32 s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed] + vstr.32 s4, [r1] + vstr.32 s4, [r1, #24] + vstr.32 s4, [r1, #-24] From grosbach at apple.com Wed Nov 3 20:12:30 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 04 Nov 2010 01:12:30 -0000 Subject: [llvm-commits] [llvm] r118221 - in /llvm/trunk/lib/Target/ARM: ARMFixupKinds.h ARMMCCodeEmitter.cpp Message-ID: <20101104011230.726F72A6C12C@llvm.org> Author: grosbach Date: Wed Nov 3 20:12:30 2010 New Revision: 118221 URL: http://llvm.org/viewvc/llvm-project?rev=118221&view=rev Log: Add ARM fixup info for load/store label references. Probably will need a bit of tweaking when we start using it for object file emission or JIT, but it's a start. Added: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Added: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=118221&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (added) +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Wed Nov 3 20:12:30 2010 @@ -0,0 +1,28 @@ +//===-- ARM/ARMFixupKinds.h - ARM Specific Fixup Entries --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ARM_ARMFIXUPKINDS_H +#define LLVM_ARM_ARMFIXUPKINDS_H + +#include "llvm/MC/MCFixup.h" + +namespace llvm { +namespace ARM { +enum Fixups { + // fixup_arm_pcrel_12 - 12-bit PC relative relocation for symbol addresses + fixup_arm_pcrel_12 = FirstTargetFixupKind, + // fixup_arm_vfp_pcrel_12 - 12-bit PC relative relocation for symbol addresses + // used in VFP instructions where the lower 2 bits are not encoded (so it's + // encoded as an 8-bit immediate). + fixup_arm_vfp_pcrel_12 +}; +} +} + +#endif Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118221&r1=118220&r2=118221&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Nov 3 20:12:30 2010 @@ -14,6 +14,7 @@ #define DEBUG_TYPE "arm-emitter" #include "ARM.h" #include "ARMAddressingModes.h" +#include "ARMFixupKinds.h" #include "ARMInstrInfo.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" @@ -22,7 +23,8 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; -STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); +STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); +STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); namespace { class ARMMCCodeEmitter : public MCCodeEmitter { @@ -39,6 +41,21 @@ ~ARMMCCodeEmitter() {} + unsigned getNumFixupKinds() const { return 2; } + + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo Infos[] = { + { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel }, + }; + + if (Kind < FirstTargetFixupKind) + return MCCodeEmitter::getFixupKindInfo(Kind); + + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && + "Invalid kind!"); + return Infos[Kind - FirstTargetFixupKind]; + } unsigned getMachineSoImmOpValue(unsigned SoImm) const; // getBinaryCodeForInstr - TableGen'erated function for getting the @@ -123,27 +140,14 @@ unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const; - unsigned getNumFixupKinds() const { - assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); - return 0; - } - - const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { - static MCFixupKindInfo rtn; - assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented."); - return rtn; - } - - void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { + void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; - ++CurByte; } - void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, - raw_ostream &OS) const { + void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { // Output the constant in little endian byte order. for (unsigned i = 0; i != Size; ++i) { - EmitByte(Val & 255, CurByte, OS); + EmitByte(Val & 255, OS); Val >>= 8; } } @@ -199,14 +203,6 @@ const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); - // If The first operand isn't a register, we have a label reference. - if (!MO.isReg()) { - Reg = ARM::PC; // Rn is PC. - Imm = 0; - // FIXME: Add a fixup referencing the label. - return true; - } - Reg = getARMRegisterNumbering(MO.getReg()); int32_t SImm = MO1.getImm(); @@ -234,7 +230,21 @@ // {12} = (U)nsigned (add == '1', sub == '0') // {11-0} = imm12 unsigned Reg, Imm12; - bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); + bool isAdd = true; + // If The first operand isn't a register, we have a label reference. + const MCOperand &MO = MI.getOperand(OpIdx); + if (!MO.isReg()) { + Reg = ARM::PC; // Rn is PC. + Imm12 = 0; + + assert(MO.isExpr() && "Unexpected machine operand type!"); + const MCExpr *Expr = MO.getExpr(); + MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12); + Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + + ++MCNumCPRelocations; + } else + isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); if (Reg == ARM::PC) return ARM::PC << 13; // Rn is PC; @@ -255,7 +265,20 @@ // {8} = (U)nsigned (add == '1', sub == '0') // {7-0} = imm8 unsigned Reg, Imm8; - EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); + // If The first operand isn't a register, we have a label reference. + const MCOperand &MO = MI.getOperand(OpIdx); + if (!MO.isReg()) { + Reg = ARM::PC; // Rn is PC. + Imm8 = 0; + + assert(MO.isExpr() && "Unexpected machine operand type!"); + const MCExpr *Expr = MO.getExpr(); + MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12); + Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + + ++MCNumCPRelocations; + } else + EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); if (Reg == ARM::PC) return ARM::PC << 9; // Rn is PC; @@ -403,9 +426,7 @@ if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo) return; - // Keep track of the current byte being emitted. - unsigned CurByte = 0; - EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, CurByte, OS); + EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS); ++MCNumEmitted; // Keep track of the # of mi's emitted. } From daniel at zuster.org Wed Nov 3 20:26:25 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 04 Nov 2010 01:26:25 -0000 Subject: [llvm-commits] [llvm] r118222 - in /llvm/trunk: include/llvm/System/Threading.h lib/System/Threading.cpp Message-ID: <20101104012625.A30242A6C12C@llvm.org> Author: ddunbar Date: Wed Nov 3 20:26:25 2010 New Revision: 118222 URL: http://llvm.org/viewvc/llvm-project?rev=118222&view=rev Log: System: Add llvm_execute_on_thread, which does what it says. - Primarily useful for running some code with a specified stack size, when pthreads are available. Modified: llvm/trunk/include/llvm/System/Threading.h llvm/trunk/lib/System/Threading.cpp Modified: llvm/trunk/include/llvm/System/Threading.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Threading.h?rev=118222&r1=118221&r2=118222&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Threading.h (original) +++ llvm/trunk/include/llvm/System/Threading.h Wed Nov 3 20:26:25 2010 @@ -40,6 +40,20 @@ /// release_global_lock - Release the global lock. This is a no-op if called /// before llvm_start_multithreaded(). void llvm_release_global_lock(); + + /// llvm_execute_on_thread - Execute the given \arg UserFn on a separate + /// thread, passing it the provided \arg UserData. + /// + /// This function does not guarantee that the code will actually be executed + /// on a separate thread or honoring the requested stack size, but tries to do + /// so where system support is available. + /// + /// \param UserFn - The callback to execute. + /// \param UserData - An argument to pass to the callback function. + /// \param RequestedStackSize - If non-zero, a requested size (in bytes) for + /// the thread stack. + void llvm_execute_on_thread(void (*UserFn)(void*), void *UserData, + unsigned RequestedStackSize = 0); } #endif Modified: llvm/trunk/lib/System/Threading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Threading.cpp?rev=118222&r1=118221&r2=118222&view=diff ============================================================================== --- llvm/trunk/lib/System/Threading.cpp (original) +++ llvm/trunk/lib/System/Threading.cpp Wed Nov 3 20:26:25 2010 @@ -62,3 +62,55 @@ void llvm::llvm_release_global_lock() { if (multithreaded_mode) global_lock->release(); } + +#if defined(LLVM_MULTITHREADED) && defined(HAVE_PTHREAD_H) +#include + +struct ThreadInfo { + void (*UserFn)(void *); + void *UserData; +}; +static void *ExecuteOnThread_Dispatch(void *Arg) { + ThreadInfo *TI = reinterpret_cast(Arg); + TI->UserFn(TI->UserData); + return 0; +} + +void llvm::llvm_execute_on_thread(void (*Fn)(void*), void *UserData, + unsigned RequestedStackSize) { + ThreadInfo Info = { Fn, UserData }; + pthread_attr_t Attr; + pthread_t Thread; + + // Construct the attributes object. + if (::pthread_attr_init(&Attr) != 0) + return; + + // Set the requested stack size, if given. + if (RequestedStackSize != 0) { + if (::pthread_attr_setstacksize(&Attr, RequestedStackSize) != 0) + goto error; + } + + // Construct and execute the thread. + if (::pthread_create(&Thread, &Attr, ExecuteOnThread_Dispatch, &Info) != 0) + goto error; + + // Wait for the thread and clean up. + ::pthread_join(Thread, 0); + + error: + ::pthread_attr_destroy(&Attr); +} + +#else + +// No non-pthread implementation, currently. + +void llvm::llvm_execute_on_thread(void (*Fn)(void*), void *UserData, + unsigned RequestedStackSize) { + (void) RequestedStackSize; + Fn(UserData); +} + +#endif From sabre at nondot.org Wed Nov 3 20:42:59 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 04 Nov 2010 01:42:59 -0000 Subject: [llvm-commits] [llvm] r118225 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101104014259.A046E2A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 20:42:59 2010 New Revision: 118225 URL: http://llvm.org/viewvc/llvm-project?rev=118225&view=rev Log: replace SrcOpNum with SrcOpName, eliminating a numering dependency on the incoming operand list. This also makes the code simpler. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118225&r1=118224&r2=118225&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 20:42:59 2010 @@ -250,10 +250,10 @@ /// The unique class instance this operand should match. ClassInfo *Class; - /// The original operand this corresponds to. - int SrcOpNum; + /// The operand name this is, if anything. + StringRef SrcOpName; - explicit AsmOperand(StringRef T) : Token(T), Class(0), SrcOpNum(-1) {} + explicit AsmOperand(StringRef T) : Token(T), Class(0) {} }; /// ResOperand - This represents a single operand in the result instruction @@ -1141,7 +1141,7 @@ for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (Operands[i].MIOperandNo == unsigned(OITied)) { OI = &Operands[i]; - Idx = i; + OperandName = OI->Name; break; } } @@ -1150,40 +1150,37 @@ } Op.Class = getOperandClass(Token, *OI); - Op.SrcOpNum = Idx; + Op.SrcOpName = OperandName; } void MatchableInfo::BuildResultOperands() { - /// OperandMap - This is a mapping from the MCInst operands (specified by the - /// II.OperandList operands) to the AsmOperands that they are filled in from. - SmallVector OperandMap(TheOperandList.size(), -1); - - // Order the (class) operands by the order to convert them into an MCInst. - for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { - MatchableInfo::AsmOperand &Op = AsmOperands[i]; - if (Op.SrcOpNum != -1) - OperandMap[Op.SrcOpNum] = i; - } - for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) { const CGIOperandList::OperandInfo &OpInfo = TheOperandList[i]; + + // If this is a tied operand, just copy from the previously handled operand. + int TiedOp = OpInfo.getTiedRegister(); + if (TiedOp != -1) { + ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); + continue; + } // Find out what operand from the asmparser that this MCInst operand comes // from. - int SrcOperand = OperandMap[i]; - if (SrcOperand != -1) { + int SrcOperand = -1; + for (unsigned op = 0, e = AsmOperands.size(); op != e; ++op) + if (OpInfo.Name == AsmOperands[op].SrcOpName) { + SrcOperand = op; + break; + } + + if (!OpInfo.Name.empty() && SrcOperand != -1) { ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); continue; } - // Otherwise, this must be a tied operand. - int TiedOp = OpInfo.getTiedRegister(); - if (TiedOp == -1) - throw TGError(TheDef->getLoc(), "Instruction '" + - TheDef->getName() + "' has operand '" + OpInfo.Name + - "' that doesn't appear in asm string!"); - - ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); } } From sabre at nondot.org Wed Nov 3 20:55:24 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 04 Nov 2010 01:55:24 -0000 Subject: [llvm-commits] [llvm] r118228 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101104015524.284DA2A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 20:55:23 2010 New Revision: 118228 URL: http://llvm.org/viewvc/llvm-project?rev=118228&view=rev Log: cleanups. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118228&r1=118227&r2=118228&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 20:55:23 2010 @@ -370,6 +370,13 @@ Record *getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const; + int FindAsmOperandNamed(StringRef N) const { + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) + if (N == AsmOperands[i].SrcOpName) + return i; + return -1; + } + void BuildResultOperands(); /// operator< - Compare two matchables. @@ -1128,28 +1135,30 @@ if (!Operands.hasOperandNamed(OperandName, Idx)) throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + OperandName.str() + "'"); - - // FIXME: This is annoying, the named operand may be tied (e.g., - // XCHG8rm). What we want is the untied operand, which we now have to - // grovel for. Only worry about this for single entry operands, we have to - // clean this up anyway. - const CGIOperandList::OperandInfo *OI = &Operands[Idx]; - int OITied = OI->getTiedRegister(); + + // Set up the operand class. + Op.Class = getOperandClass(Token, Operands[Idx]); + + // If the named operand is tied, canonicalize it to the untied operand. + // For example, something like: + // (outs GPR:$dst), (ins GPR:$src) + // with an asmstring of + // "inc $src" + // we want to canonicalize to: + // "inc $dst" + // so that we know how to provide the $dst operand when filling in the result. + int OITied = Operands[Idx].getTiedRegister(); if (OITied != -1) { // The tied operand index is an MIOperand index, find the operand that // contains it. for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (Operands[i].MIOperandNo == unsigned(OITied)) { - OI = &Operands[i]; - OperandName = OI->Name; + OperandName = Operands[i].Name; break; } } - - assert(OI && "Unable to find tied operand target!"); } - Op.Class = getOperandClass(Token, *OI); Op.SrcOpName = OperandName; } @@ -1166,12 +1175,7 @@ // Find out what operand from the asmparser that this MCInst operand comes // from. - int SrcOperand = -1; - for (unsigned op = 0, e = AsmOperands.size(); op != e; ++op) - if (OpInfo.Name == AsmOperands[op].SrcOpName) { - SrcOperand = op; - break; - } + int SrcOperand = FindAsmOperandNamed(OpInfo.Name); if (!OpInfo.Name.empty() && SrcOperand != -1) { ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); From sabre at nondot.org Wed Nov 3 20:58:23 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 04 Nov 2010 01:58:23 -0000 Subject: [llvm-commits] [llvm] r118230 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101104015823.AC6C22A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 20:58:23 2010 New Revision: 118230 URL: http://llvm.org/viewvc/llvm-project?rev=118230&view=rev Log: pull name slicing out of BuildInstructionOperandReference so it doesn't do any lexical stuff anymore. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118230&r1=118229&r2=118230&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 20:58:23 2010 @@ -500,8 +500,7 @@ ClassInfo *getTokenClass(StringRef Token); /// getOperandClass - Lookup or create the class for the given operand. - ClassInfo *getOperandClass(StringRef Token, - const CGIOperandList::OperandInfo &OI); + ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI); /// BuildRegisterClasses - Build the ClassInfo* instances for register /// classes. @@ -511,7 +510,7 @@ /// operand classes. void BuildOperandClasses(); - void BuildInstructionOperandReference(MatchableInfo *II, + void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName, MatchableInfo::AsmOperand &Op); public: @@ -778,8 +777,7 @@ } ClassInfo * -AsmMatcherInfo::getOperandClass(StringRef Token, - const CGIOperandList::OperandInfo &OI) { +AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) { if (OI.Rec->isSubClassOf("RegisterClass")) { if (ClassInfo *CI = RegisterClassClasses[OI.Rec]) return CI; @@ -1102,8 +1100,14 @@ continue; } + StringRef OperandName; + if (Token[1] == '{') + OperandName = Token.substr(2, Token.size() - 3); + else + OperandName = Token.substr(1); + // Otherwise this is an operand reference. - BuildInstructionOperandReference(II, Op); + BuildInstructionOperandReference(II, OperandName, Op); } II->BuildResultOperands(); @@ -1117,16 +1121,8 @@ /// named operand such as $src. Resolve the Class and OperandInfo pointers. void AsmMatcherInfo:: BuildInstructionOperandReference(MatchableInfo *II, + StringRef OperandName, MatchableInfo::AsmOperand &Op) { - StringRef Token = Op.Token; - assert(Token[0] == '$' && "Not an operand name ref"); - - StringRef OperandName; - if (Token[1] == '{') - OperandName = Token.substr(2, Token.size() - 3); - else - OperandName = Token.substr(1); - const CGIOperandList &Operands = II->TheOperandList; @@ -1137,7 +1133,7 @@ OperandName.str() + "'"); // Set up the operand class. - Op.Class = getOperandClass(Token, Operands[Idx]); + Op.Class = getOperandClass(Operands[Idx]); // If the named operand is tied, canonicalize it to the untied operand. // For example, something like: From sabre at nondot.org Wed Nov 3 21:11:18 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 04 Nov 2010 02:11:18 -0000 Subject: [llvm-commits] [llvm] r118232 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101104021118.B1A142A6C12C@llvm.org> Author: lattner Date: Wed Nov 3 21:11:18 2010 New Revision: 118232 URL: http://llvm.org/viewvc/llvm-project?rev=118232&view=rev Log: partition operand processing between aliases and instructions. Right now the code is partitioned but the behavior is the same. This should be improved in the near future. This removes some uses of TheOperandList. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118232&r1=118231&r2=118232&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed Nov 3 21:11:18 2010 @@ -75,6 +75,7 @@ #include "Record.h" #include "StringMatcher.h" #include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" @@ -312,6 +313,9 @@ /// matchable came from. Record *const TheDef; + /// DefRec - This is the definition that it came from. + PointerUnion DefRec; + // FIXME: REMOVE. const CGIOperandList &TheOperandList; @@ -343,12 +347,13 @@ std::string ConversionFnKind; MatchableInfo(const CodeGenInstruction &CGI) - : TheDef(CGI.TheDef), TheOperandList(CGI.Operands), AsmString(CGI.AsmString) { + : TheDef(CGI.TheDef), DefRec(&CGI), + TheOperandList(CGI.Operands), AsmString(CGI.AsmString) { InstrName = TheDef->getName(); } MatchableInfo(const CodeGenInstAlias *Alias) - : TheDef(Alias->TheDef), TheOperandList(Alias->Operands), + : TheDef(Alias->TheDef), DefRec(Alias), TheOperandList(Alias->Operands), AsmString(Alias->AsmString) { // FIXME: Huge hack. @@ -510,9 +515,13 @@ /// operand classes. void BuildOperandClasses(); - void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName, + void BuildInstructionOperandReference(MatchableInfo *II, + StringRef OpName, MatchableInfo::AsmOperand &Op); - + void BuildAliasOperandReference(MatchableInfo *II, + StringRef OpName, + MatchableInfo::AsmOperand &Op); + public: AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target); @@ -1100,14 +1109,19 @@ continue; } + // Otherwise this is an operand reference. StringRef OperandName; if (Token[1] == '{') OperandName = Token.substr(2, Token.size() - 3); else OperandName = Token.substr(1); - // Otherwise this is an operand reference. - BuildInstructionOperandReference(II, OperandName, Op); + if (II->DefRec.is()) + BuildInstructionOperandReference(II, + OperandName, Op); + else + BuildAliasOperandReference(II, + OperandName, Op); } II->BuildResultOperands(); @@ -1123,8 +1137,8 @@ BuildInstructionOperandReference(MatchableInfo *II, StringRef OperandName, MatchableInfo::AsmOperand &Op) { - const CGIOperandList &Operands = II->TheOperandList; - + const CodeGenInstruction &CGI = *II->DefRec.get(); + const CGIOperandList &Operands = CGI.Operands; // Map this token to an operand. FIXME: Move elsewhere. unsigned Idx; @@ -1158,6 +1172,49 @@ Op.SrcOpName = OperandName; } +void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, + StringRef OperandName, + MatchableInfo::AsmOperand &Op) { + const CodeGenInstAlias &CGA = *II->DefRec.get(); + + + // FIXME: This is a total hack, it should not be a copy of + // BuildInstructionOperandReference + + const CGIOperandList &Operands = CGA.Operands; + + // Map this token to an operand. FIXME: Move elsewhere. + unsigned Idx; + if (!Operands.hasOperandNamed(OperandName, Idx)) + throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + + OperandName.str() + "'"); + + // Set up the operand class. + Op.Class = getOperandClass(Operands[Idx]); + + // If the named operand is tied, canonicalize it to the untied operand. + // For example, something like: + // (outs GPR:$dst), (ins GPR:$src) + // with an asmstring of + // "inc $src" + // we want to canonicalize to: + // "inc $dst" + // so that we know how to provide the $dst operand when filling in the result. + int OITied = Operands[Idx].getTiedRegister(); + if (OITied != -1) { + // The tied operand index is an MIOperand index, find the operand that + // contains it. + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (Operands[i].MIOperandNo == unsigned(OITied)) { + OperandName = Operands[i].Name; + break; + } + } + } + + Op.SrcOpName = OperandName; +} + void MatchableInfo::BuildResultOperands() { for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) { const CGIOperandList::OperandInfo &OpInfo = TheOperandList[i]; From echristo at apple.com Wed Nov 3 21:15:22 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 04 Nov 2010 02:15:22 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118233 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h Message-ID: <20101104021523.2D23E2A6C12C@llvm.org> Author: echristo Date: Wed Nov 3 21:15:22 2010 New Revision: 118233 URL: http://llvm.org/viewvc/llvm-project?rev=118233&view=rev Log: Use the arch to set the architecture, not the mtune value. Fixes rdar://8516205. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=118233&r1=118232&r2=118233&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Wed Nov 3 21:15:22 2010 @@ -551,6 +551,9 @@ /* The processor for which instructions should be scheduled. */ enum processor_type arm_tune = arm_none; +/* LLVM LOCAL global arch value */ +enum processor_type target_arch_cpu = arm_none; + /* APPLE LOCAL begin v7 support. Merge from mainline */ /* The default processor used if not overriden by commandline. */ static enum processor_type arm_default_cpu = arm_none; @@ -1289,12 +1292,13 @@ unsigned i; /* APPLE LOCAL v7 support. Merge from Codesourcery */ int len; - enum processor_type target_arch_cpu = arm_none; + /* LLVM LOCAL global arch value */ + /* Moved target_arch_cpu to arm.h */ /* Set up the flags based on the cpu/architecture selected by the user. */ for (i = ARRAY_SIZE (arm_select); i--;) { - struct arm_cpu_select * ptr = arm_select + i; + struct arm_cpu_select * ptr = &arm_select[i]; if (ptr->string != NULL && ptr->string[0] != '\0') { Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=118233&r1=118232&r2=118233&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Wed Nov 3 21:15:22 2010 @@ -149,6 +149,9 @@ /* The processor for which instructions should be scheduled. */ extern enum processor_type arm_tune; +/* LLVM LOCAL global arch value */ +extern enum processor_type target_arch_cpu; + typedef enum arm_cond_code { ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, @@ -3456,7 +3459,7 @@ /* Turn -march=xx into a CPU type. */ #define LLVM_SET_SUBTARGET_FEATURES(F) \ - { switch (arm_tune) { \ + { switch (target_arch_cpu) { \ case arm8: F.setCPU("arm8"); break;\ case arm810: F.setCPU("arm810"); break;\ case strongarm: F.setCPU("strongarm"); break;\ From evan.cheng at apple.com Thu Nov 4 00:19:35 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 04 Nov 2010 05:19:35 -0000 Subject: [llvm-commits] [llvm] r118237 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/prefetch.ll Message-ID: <20101104051935.DCCBE2A6C12C@llvm.org> Author: evancheng Date: Thu Nov 4 00:19:35 2010 New Revision: 118237 URL: http://llvm.org/viewvc/llvm-project?rev=118237&view=rev Log: Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/CodeGen/ARM/prefetch.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118237&r1=118236&r2=118237&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Nov 4 00:19:35 2010 @@ -597,7 +597,7 @@ setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); - setOperationAction(ISD::PREFETCH, MVT::Other, Custom); + setOperationAction(ISD::PREFETCH, MVT::Other, Custom); // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. if (!Subtarget->hasV6Ops()) { @@ -2068,20 +2068,21 @@ return Op.getOperand(0); DebugLoc dl = Op.getDebugLoc(); - unsigned Flavor = cast(Op.getOperand(3))->getZExtValue(); - if (Flavor != 3) { - if (!Subtarget->hasV7Ops()) - return Op.getOperand(0); - else if (Flavor == 2 && !Subtarget->hasMPExtension()) - return Op.getOperand(0); - } + unsigned isRead = ~cast(Op.getOperand(2))->getZExtValue() & 1; + if (!isRead && + (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) + // ARMv7 with MP extension has PLDW. + return Op.getOperand(0); if (Subtarget->isThumb()) // Invert the bits. - Flavor = ~Flavor & 0x3; + isRead = ~isRead & 1; + unsigned isData = Subtarget->isThumb() ? 0 : 1; + // Currently there is no intrinsic that matches pli. return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), - Op.getOperand(1), DAG.getConstant(Flavor, MVT::i32)); + Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), + DAG.getConstant(isData, MVT::i32)); } static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118237&r1=118236&r2=118237&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 4 00:19:35 2010 @@ -62,8 +62,6 @@ def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; -def SDT_ARMPRELOAD : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; - def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, @@ -132,7 +130,7 @@ [SDNPHasChain]>; def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, [SDNPHasChain]>; -def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPRELOAD, +def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch, [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; @@ -994,18 +992,18 @@ // Preload signals the memory system of possible future data/instruction access. // These are for disassembly only. -multiclass APreLoad data_read, string opc> { +multiclass APreLoad read, bits<1> data, string opc> { def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, !strconcat(opc, "\t$addr"), - [(ARMPreload addrmode_imm12:$addr, (i32 data_read))]> { + [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> { bits<4> Rt; bits<17> addr; let Inst{31-26} = 0b111101; let Inst{25} = 0; // 0 for immediate form - let Inst{24} = data_read{1}; + let Inst{24} = data; let Inst{23} = addr{12}; // U (add = ('U' == 1)) - let Inst{22} = data_read{0}; + let Inst{22} = read; let Inst{21-20} = 0b01; let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; @@ -1014,23 +1012,23 @@ def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, !strconcat(opc, "\t$shift"), - [(ARMPreload ldst_so_reg:$shift, (i32 data_read))]> { + [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> { bits<4> Rt; bits<17> shift; let Inst{31-26} = 0b111101; let Inst{25} = 1; // 1 for register form - let Inst{24} = data_read{1}; + let Inst{24} = data; let Inst{23} = shift{12}; // U (add = ('U' == 1)) - let Inst{22} = data_read{0}; + let Inst{22} = read; let Inst{21-20} = 0b01; let Inst{19-16} = shift{16-13}; // Rn let Inst{11-0} = shift{11-0}; } } -defm PLD : APreLoad<3, "pld">, Requires<[IsARM]>; -defm PLDW : APreLoad<2, "pldw">, Requires<[IsARM,HasV7,HasMP]>; -defm PLI : APreLoad<1, "pli">, Requires<[IsARM,HasV7]>; +defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; +defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; +defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, "setend\t$end", Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118237&r1=118236&r2=118237&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Nov 4 00:19:35 2010 @@ -1173,28 +1173,28 @@ // data/instruction access. These are for disassembly only. // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). -multiclass T2Ipl instr_write, string opc> { +multiclass T2Ipl write, bits<1> instr, string opc> { def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, "\t$addr", - [(ARMPreload t2addrmode_imm12:$addr, (i32 instr_write))]> { + [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr_write{1}; + let Inst{24} = instr; let Inst{23} = 1; // U = 1 let Inst{22} = 0; - let Inst{21} = instr_write{0}; + let Inst{21} = write; let Inst{20} = 1; let Inst{15-12} = 0b1111; } def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc, "\t$addr", - [(ARMPreload t2addrmode_imm8:$addr, (i32 instr_write))]> { + [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr_write{1}; + let Inst{24} = instr; let Inst{23} = 0; // U = 0 let Inst{22} = 0; - let Inst{21} = instr_write{0}; + let Inst{21} = write; let Inst{20} = 1; let Inst{15-12} = 0b1111; let Inst{11-8} = 0b1100; @@ -1202,12 +1202,12 @@ def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, "\t$addr", - [(ARMPreload t2addrmode_so_reg:$addr, (i32 instr_write))]> { + [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr_write{1}; + let Inst{24} = instr; let Inst{23} = 0; // add = TRUE for T1 let Inst{22} = 0; - let Inst{21} = instr_write{0}; + let Inst{21} = write; let Inst{20} = 1; let Inst{15-12} = 0b1111; let Inst{11-6} = 0000000; @@ -1218,19 +1218,19 @@ "\t$addr", []> { let Inst{31-25} = 0b1111100; - let Inst{24} = instr_write{1}; + let Inst{24} = write; let Inst{23} = ?; // add = (U == 1) let Inst{22} = 0; - let Inst{21} = instr_write{0}; + let Inst{21} = instr; let Inst{20} = 1; let Inst{19-16} = 0b1111; // Rn = 0b1111 let Inst{15-12} = 0b1111; } } -defm t2PLD : T2Ipl<0, "pld">, Requires<[IsThumb2]>; -defm t2PLDW : T2Ipl<1, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; -defm t2PLI : T2Ipl<2, "pli">, Requires<[IsThumb2,HasV7]>; +defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; +defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; +defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; //===----------------------------------------------------------------------===// // Load / store multiple Instructions. Modified: llvm/trunk/test/CodeGen/ARM/prefetch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=118237&r1=118236&r2=118237&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/prefetch.ll (original) +++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Thu Nov 4 00:19:35 2010 @@ -1,29 +1,26 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a,+mp | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a,+mp | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7a,+mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 define void @t1(i8* %ptr) nounwind { entry: -; ARM: t1: -; ARM: pli [r0] -; ARM: pldw [r0] -; ARM: pld [r0] +; ARM-MP: t1: +; ARM-MP: pldw [r0] +; ARM-MP: pld [r0] ; THUMB2: t1: -; THUMB2: pli [r0] -; THUMB2: pldw [r0] +; THUMB2-NOT: pldw [r0] ; THUMB2: pld [r0] - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 ) - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 ) + tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) ret void } define void @t2(i8* %ptr) nounwind { entry: -; ARM: t2: -; ARM: pld [r0, #1023] +; ARM-MP: t2: +; ARM-MP: pld [r0, #1023] ; THUMB2: t2: ; THUMB2: pld [r0, #1023] @@ -34,8 +31,8 @@ define void @t3(i32 %base, i32 %offset) nounwind { entry: -; ARM: t3: -; ARM: pld [r0, r1, lsr #2] +; ARM-MP: t3: +; ARM-MP: pld [r0, r1, lsr #2] ; THUMB2: t3: ; THUMB2: lsrs r1, r1, #2 @@ -49,8 +46,8 @@ define void @t4(i32 %base, i32 %offset) nounwind { entry: -; ARM: t4: -; ARM: pld [r0, r1, lsl #2] +; ARM-MP: t4: +; ARM-MP: pld [r0, r1, lsl #2] ; THUMB2: t4: ; THUMB2: pld [r0, r1, lsl #2] From fvbommel at gmail.com Thu Nov 4 04:39:32 2010 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 4 Nov 2010 10:39:32 +0100 Subject: [llvm-commits] [llvm] r118222 - in /llvm/trunk: include/llvm/System/Threading.h lib/System/Threading.cpp In-Reply-To: <20101104012625.A30242A6C12C@llvm.org> References: <20101104012625.A30242A6C12C@llvm.org> Message-ID: > +void llvm::llvm_execute_on_thread(void (*Fn)(void*), void *UserData, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned RequestedStackSize) { > + ?ThreadInfo Info = { Fn, UserData }; > + ?pthread_attr_t Attr; > + ?pthread_t Thread; > + > + ?// Construct the attributes object. > + ?if (::pthread_attr_init(&Attr) != 0) > + ? ?return; I'm not sure what kind of errors can occur here, but shouldn't the threaded version fall back to a non-threaded call if there's some kind of error? > + ?// Construct and execute the thread. > + ?if (::pthread_create(&Thread, &Attr, ExecuteOnThread_Dispatch, &Info) != 0) > + ? ?goto error; > + > + ?// Wait for the thread and clean up. > + ?::pthread_join(Thread, 0); What's the point of running something on a separate thread if you're just going to immediately make this thread wait for it to finish? From baldrick at free.fr Thu Nov 4 05:49:57 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 04 Nov 2010 10:49:57 -0000 Subject: [llvm-commits] [llvm] r118245 - in /llvm/trunk: include/llvm/CodeGen/CallingConvLower.h lib/CodeGen/CallingConvLower.cpp lib/Target/ARM/ARMCallingConv.h lib/Target/ARM/ARMFastISel.cpp lib/Target/MBlaze/MBlazeISelLowering.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86FastISel.cpp utils/TableGen/CallingConvEmitter.cpp Message-ID: <20101104104957.67E502A6C12C@llvm.org> Author: baldrick Date: Thu Nov 4 05:49:57 2010 New Revision: 118245 URL: http://llvm.org/viewvc/llvm-project?rev=118245&view=rev Log: In the calling convention logic, ValVT is always a legal type, and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/lib/CodeGen/CallingConvLower.cpp llvm/trunk/lib/Target/ARM/ARMCallingConv.h llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/utils/TableGen/CallingConvEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Thu Nov 4 05:49:57 2010 @@ -57,13 +57,13 @@ LocInfo HTP : 6; /// ValVT - The type of the value being assigned. - EVT ValVT; + MVT ValVT; /// LocVT - The type of the location being assigned to. MVT LocVT; public: - static CCValAssign getReg(unsigned ValNo, EVT ValVT, + static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP) { CCValAssign Ret; @@ -77,7 +77,7 @@ return Ret; } - static CCValAssign getCustomReg(unsigned ValNo, EVT ValVT, + static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP) { CCValAssign Ret; @@ -86,7 +86,7 @@ return Ret; } - static CCValAssign getMem(unsigned ValNo, EVT ValVT, + static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP) { CCValAssign Ret; @@ -100,7 +100,7 @@ return Ret; } - static CCValAssign getCustomMem(unsigned ValNo, EVT ValVT, + static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP) { CCValAssign Ret; @@ -110,7 +110,7 @@ } unsigned getValNo() const { return ValNo; } - EVT getValVT() const { return ValVT; } + MVT getValVT() const { return ValVT; } bool isRegLoc() const { return !isMem; } bool isMemLoc() const { return isMem; } @@ -130,14 +130,14 @@ /// CCAssignFn - This function assigns a location for Val, updating State to /// reflect the change. It returns 'true' if it failed to handle Val. -typedef bool CCAssignFn(unsigned ValNo, EVT ValVT, +typedef bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); /// CCCustomFn - This function assigns a location for Val, possibly updating /// all args to reflect changes and indicates if it handled it. It must set /// isCustom if it handles the arg and returns true. -typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT, +typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); @@ -284,7 +284,7 @@ // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. - void HandleByVal(unsigned ValNo, EVT ValVT, + void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags); Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Thu Nov 4 05:49:57 2010 @@ -34,7 +34,7 @@ // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. -void CCState::HandleByVal(unsigned ValNo, EVT ValVT, +void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags) { Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.h?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.h (original) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.h Thu Nov 4 05:49:57 2010 @@ -26,7 +26,7 @@ namespace llvm { // APCS f64 is in register pairs, possibly split to stack -static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail) { static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; @@ -56,7 +56,7 @@ return true; } -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -69,7 +69,7 @@ } // AAPCS f64 is in aligned register pairs -static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; @@ -104,7 +104,7 @@ return true; } -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -116,7 +116,7 @@ return true; // we handled it } -static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; @@ -136,7 +136,7 @@ return true; } -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -147,7 +147,7 @@ return true; // we handled it } -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Nov 4 05:49:57 2010 @@ -1567,7 +1567,7 @@ return false; // TODO: For now, don't try to handle cases where getLocInfo() // says Full but the types don't match. - if (VA.getValVT() != TLI.getValueType(RV->getType())) + if (TLI.getValueType(RV->getType()) != VA.getValVT()) return false; // Make the copy. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Thu Nov 4 05:49:57 2010 @@ -468,7 +468,7 @@ #include "MBlazeGenCallingConv.inc" -static bool CC_MBlaze2(unsigned ValNo, EVT ValVT, +static bool CC_MBlaze2(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { static const unsigned RegsSize=6; @@ -553,7 +553,7 @@ // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; - EVT RegVT = VA.getLocVT(); + MVT RegVT = VA.getLocVT(); SDValue Arg = OutVals[i]; // Promote the value if needed. @@ -720,7 +720,7 @@ // Arguments stored on registers if (VA.isRegLoc()) { - EVT RegVT = VA.getLocVT(); + MVT RegVT = VA.getLocVT(); ArgRegEnd = VA.getLocReg(); TargetRegisterClass *RC = 0; Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Nov 4 05:49:57 2010 @@ -629,7 +629,7 @@ // go to stack. //===----------------------------------------------------------------------===// -static bool CC_MipsO32(unsigned ValNo, EVT ValVT, +static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { @@ -695,7 +695,7 @@ return false; // CC must always match } -static bool CC_MipsO32_VarArgs(unsigned ValNo, EVT ValVT, +static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { @@ -789,7 +789,7 @@ // To meet O32 ABI, Mips must always allocate 16 bytes on // the stack (even if less than 4 are used as arguments) if (Subtarget->isABI_O32()) { - int VTsize = EVT(MVT::i32).getSizeInBits()/8; + int VTsize = MVT(MVT::i32).getSizeInBits()/8; MFI->CreateFixedObject(VTsize, (VTsize*3), true); CCInfo.AnalyzeCallOperands(Outs, isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 4 05:49:57 2010 @@ -38,16 +38,16 @@ #include "llvm/DerivedTypes.h" using namespace llvm; -static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, +static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, +static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, @@ -1443,14 +1443,14 @@ #include "PPCGenCallingConv.inc" -static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, MVT &LocVT, +static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { return true; } -static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, +static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, @@ -1477,7 +1477,7 @@ return false; } -static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, +static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Nov 4 05:49:57 2010 @@ -711,7 +711,7 @@ return false; // TODO: For now, don't try to handle cases where getLocInfo() // says Full but the types don't match. - if (VA.getValVT() != TLI.getValueType(RV->getType())) + if (TLI.getValueType(RV->getType()) != VA.getValVT()) return false; // The calling-convention tables for x87 returns don't tell Modified: llvm/trunk/utils/TableGen/CallingConvEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CallingConvEmitter.cpp?rev=118245&r1=118244&r2=118245&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CallingConvEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/CallingConvEmitter.cpp Thu Nov 4 05:49:57 2010 @@ -26,7 +26,7 @@ // other. for (unsigned i = 0, e = CCs.size(); i != e; ++i) { O << "static bool " << CCs[i]->getName() - << "(unsigned ValNo, EVT ValVT,\n" + << "(unsigned ValNo, MVT ValVT,\n" << std::string(CCs[i]->getName().size()+13, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(CCs[i]->getName().size()+13, ' ') @@ -44,7 +44,7 @@ Counter = 0; O << "\n\nstatic bool " << CC->getName() - << "(unsigned ValNo, EVT ValVT,\n" + << "(unsigned ValNo, MVT ValVT,\n" << std::string(CC->getName().size()+13, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(CC->getName().size()+13, ' ') From dpatel at apple.com Thu Nov 4 09:56:34 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 04 Nov 2010 14:56:34 -0000 Subject: [llvm-commits] [llvm] r118247 - /llvm/trunk/include/llvm/Analysis/DebugInfo.h Message-ID: <20101104145634.DBCC72A6C12C@llvm.org> Author: dpatel Date: Thu Nov 4 09:56:34 2010 New Revision: 118247 URL: http://llvm.org/viewvc/llvm-project?rev=118247&view=rev Log: Add getFile() to get DIFile of a DIType. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=118247&r1=118246&r2=118247&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Thu Nov 4 09:56:34 2010 @@ -238,6 +238,7 @@ return getFieldAs(3).getCompileUnit(); } + DIFile getFile() const { return getFieldAs(3); } unsigned getLineNumber() const { return getUnsignedField(4); } uint64_t getSizeInBits() const { return getUInt64Field(5); } uint64_t getAlignInBits() const { return getUInt64Field(6); } From dpatel at apple.com Thu Nov 4 10:01:39 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 04 Nov 2010 15:01:39 -0000 Subject: [llvm-commits] [llvm] r118248 - in /llvm/trunk: include/llvm/Analysis/DIBuilder.h lib/Analysis/CMakeLists.txt lib/Analysis/DIBuilder.cpp Message-ID: <20101104150139.2385E2A6C12C@llvm.org> Author: dpatel Date: Thu Nov 4 10:01:38 2010 New Revision: 118248 URL: http://llvm.org/viewvc/llvm-project?rev=118248&view=rev Log: Introduce DIBuilder. It is intended to be a front-end friendly interface to emit debuggging information entries in LLVM IR. To create debugging information for a pointer, using DIBUilder front-end just needs DBuilder.CreatePointerType(Ty, Size); instead of DebugFactory.CreateDerivedType(llvm::dwarf::DW_TAG_pointer_type, TheCU, "", getOrCreateMainFile(), 0, Size, 0, 0, 0, OCTy); Added: llvm/trunk/include/llvm/Analysis/DIBuilder.h llvm/trunk/lib/Analysis/DIBuilder.cpp Modified: llvm/trunk/lib/Analysis/CMakeLists.txt Added: llvm/trunk/include/llvm/Analysis/DIBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=118248&view=auto ============================================================================== --- llvm/trunk/include/llvm/Analysis/DIBuilder.h (added) +++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Thu Nov 4 10:01:38 2010 @@ -0,0 +1,94 @@ +//===--- llvm/Analysis/DIBuilder.h - Debug Information Builder --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines a DIBuilder that is useful for creating debugging +// information entries in LLVM IR form. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ANALYSIS_DIBUILDER_H +#define LLVM_ANALYSIS_DIBUILDER_H + +#include "llvm/System/DataTypes.h" +#include "llvm/ADT/StringRef.h" + +namespace llvm { + class Module; + class LLVMContext; + class MDNode; + class StringRef; + class DIDescriptor; + class DIFile; + class DIEnumerator; + class DIType; + + class DIBuilder { + private: + Module &M; + LLVMContext & VMContext; + MDNode *TheCU; + + DIBuilder(const DIBuilder &); // DO NOT IMPLEMENT + void operator=(const DIBuilder &); // DO NOT IMPLEMENT + + public: + explicit DIBuilder(Module &M); + const MDNode *getCU() { return TheCU; } + + /// CreateCompileUnit - A CompileUnit provides an anchor for all debugging + /// information generated during this instance of compilation. + void CreateCompileUnit(unsigned Lang, StringRef F, StringRef D, StringRef P, + bool isOptimized, StringRef Flags, unsigned RV); + + /// CreateFile - Create a file descriptor to hold debugging information + /// for a file. + DIFile CreateFile(StringRef Filename, StringRef Directory); + + /// CreateEnumerator - Create a single enumerator value. + DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); + + /// CreateBasicType - Create debugging information entry for a basic + /// type, e.g 'char'. + DIType CreateBasicType(StringRef Name, uint64_t SizeInBits, + uint64_t AlignInBits, unsigned Encoding); + + /// CreateQaulifiedType - Create debugging information entry for a qualified + /// type, e.g. 'const int'. + DIType CreateQualifiedType(unsigned Tag, DIType FromTy); + + /// CreatePointerType - Create debugging information entry for a pointer. + DIType CreatePointerType(DIType PointeeTy, uint64_t SizeInBits, + uint64_t AlignInBits = 0, StringRef Name = StringRef()); + + /// CreateReferenceType - Create debugging information entry for a reference. + DIType CreateReferenceType(DIType RTy); + + /// CreateTypedef - Create debugging information entry for a typedef. + DIType CreateTypedef(DIType Ty, StringRef Name, DIFile F, unsigned LineNo); + + /// CreateFriend - Create debugging information entry for a 'friend'. + DIType CreateFriend(DIType Ty, DIType FriendTy); + + /// CreateInheritance - Create debugging information entry to establish + /// inheritnace relationship between two types. + DIType CreateInheritance(DIType Ty, DIType BaseTy, uint64_t BaseOffset, + unsigned Flags); + + /// CreateMemberType - Create debugging information entry for a member. + DIType CreateMemberType(DIDescriptor Context, StringRef Name, DIFile F, + unsigned LineNumber, uint64_t SizeInBits, + uint64_t AlignInBits, uint64_t OffsetInBits, + unsigned Flags, DIType Ty); + + /// CreateArtificialType - Create a new DIType with "artificial" flag set. + DIType CreateArtificialType(DIType Ty); + }; +} // end namespace llvm + +#endif Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=118248&r1=118247&r2=118248&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Thu Nov 4 10:01:38 2010 @@ -11,6 +11,7 @@ ConstantFolding.cpp DbgInfoPrinter.cpp DebugInfo.cpp + DIBuilder.cpp DomPrinter.cpp IVUsers.cpp InlineCost.cpp Added: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=118248&view=auto ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (added) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Thu Nov 4 10:01:38 2010 @@ -0,0 +1,249 @@ +//===--- DIBuilder.cpp - Debug Information Builder ------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the DIBuilder. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Analysis/DIBuilder.h" +#include "llvm/Analysis/DebugInfo.h" +#include "llvm/Constants.h" +#include "llvm/IntrinsicInst.h" +#include "llvm/Module.h" +#include "llvm/Support/Dwarf.h" + +using namespace llvm; +using namespace llvm::dwarf; + +static Constant *GetTagConstant(LLVMContext &VMContext, unsigned Tag) { + assert((Tag & LLVMDebugVersionMask) == 0 && + "Tag too large for debug encoding!"); + return ConstantInt::get(Type::getInt32Ty(VMContext), Tag | LLVMDebugVersion); +} +DIBuilder::DIBuilder(Module &m) + : M(m), VMContext(M.getContext()), TheCU(0) {} + +/// CreateCompileUnit - A CompileUnit provides an anchor for all debugging +/// information generated during this instance of compilation. +void DIBuilder::CreateCompileUnit(unsigned Lang, StringRef Filename, + StringRef Directory, StringRef Producer, + bool isOptimized, StringRef Flags, + unsigned RunTimeVer) { + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_compile_unit)); + Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Lang)); + Elts.push_back(MDString::get(VMContext, Filename)); + Elts.push_back(MDString::get(VMContext, Directory)); + Elts.push_back(MDString::get(VMContext, Producer)); + // Deprecate isMain field. + Elts.push_back(ConstantInt::get(Type::getInt1Ty(VMContext), true)); // isMain + Elts.push_back(ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized)); + Elts.push_back(MDString::get(VMContext, Flags)); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), RunTimeVer)); + + TheCU = DICompileUnit(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateFile - Create a file descriptor to hold debugging information +/// for a file. +DIFile DIBuilder::CreateFile(StringRef Filename, StringRef Directory) { + assert (TheCU && "Unable to create DW_TAG_file_type without CompileUnit"); + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_file_type)); + Elts.push_back(MDString::get(VMContext, Filename)); + Elts.push_back(MDString::get(VMContext, Directory)); + Elts.push_back(TheCU); + return DIFile(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateEnumerator - Create a single enumerator value. +DIEnumerator DIBuilder::CreateEnumerator(StringRef Name, uint64_t Val) { + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_enumerator)); + Elts.push_back(MDString::get(VMContext, Name)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), Val)); + return DIEnumerator(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateBasicType - Create debugging information entry for a basic +/// type, e.g 'char'. +DIType DIBuilder::CreateBasicType(StringRef Name, uint64_t SizeInBits, + uint64_t AlignInBits, + unsigned Encoding) { + // Basic types are encoded in DIBasicType format. Line number, filename, + // offset and flags are always empty here. + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_base_type)); + Elts.push_back(TheCU); + Elts.push_back(MDString::get(VMContext, Name)); + Elts.push_back(NULL); // Filename + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags; + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Encoding)); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateQaulifiedType - Create debugging information entry for a qualified +/// type, e.g. 'const int'. +DIType DIBuilder::CreateQualifiedType(unsigned Tag, DIType FromTy) { + /// Qualified types are encoded in DIDerivedType format. + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, Tag)); + Elts.push_back(TheCU); + Elts.push_back(MDString::get(VMContext, StringRef())); // Empty name. + Elts.push_back(NULL); // Filename + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags + Elts.push_back(FromTy); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreatePointerType - Create debugging information entry for a pointer. +DIType DIBuilder::CreatePointerType(DIType PointeeTy, uint64_t SizeInBits, + uint64_t AlignInBits, StringRef Name) { + /// pointer types are encoded in DIDerivedType format. + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_pointer_type)); + Elts.push_back(TheCU); + Elts.push_back(MDString::get(VMContext, Name)); + Elts.push_back(NULL); // Filename + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags + Elts.push_back(PointeeTy); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateReferenceType - Create debugging information entry for a reference. +DIType DIBuilder::CreateReferenceType(DIType RTy) { + /// references are encoded in DIDerivedType format. + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_reference_type)); + Elts.push_back(TheCU); + Elts.push_back(NULL); // Name + Elts.push_back(NULL); // Filename + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags + Elts.push_back(RTy); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateTypedef - Create debugging information entry for a typedef. +DIType DIBuilder::CreateTypedef(DIType Ty, StringRef Name, DIFile File, + unsigned LineNo) { + /// typedefs are encoded in DIDerivedType format. + assert (Ty.Verify() && "Invalid typedef type!"); + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_typedef)); + Elts.push_back(Ty.getContext()); + Elts.push_back(MDString::get(VMContext, Name)); + Elts.push_back(File); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags + Elts.push_back(Ty); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateFriend - Create debugging information entry for a 'friend'. +DIType DIBuilder::CreateFriend(DIType Ty, DIType FriendTy) { + /// typedefs are encoded in DIDerivedType format. + assert (Ty.Verify() && "Invalid type!"); + assert (FriendTy.Verify() && "Invalid friend type!"); + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_friend)); + Elts.push_back(Ty); + Elts.push_back(NULL); // Name + Elts.push_back(Ty.getFile()); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags + Elts.push_back(FriendTy); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateInheritance - Create debugging information entry to establish +/// inheritnace relationship between two types. +DIType DIBuilder::CreateInheritance(DIType Ty, DIType BaseTy, + uint64_t BaseOffset, unsigned Flags) { + /// TAG_inheritance is encoded in DIDerivedType format. + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_inheritance)); + Elts.push_back(Ty); + Elts.push_back(NULL); // Name + Elts.push_back(NULL); // File + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), BaseOffset)); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Flags)); + Elts.push_back(BaseTy); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateMemberType - Create debugging information entry for a member. +DIType DIBuilder::CreateMemberType(DIDescriptor Context, StringRef Name, + DIFile F, unsigned LineNumber, + uint64_t SizeInBits, uint64_t AlignInBits, + uint64_t OffsetInBits, unsigned Flags, + DIType Ty) { + /// TAG_member is encoded in DIDerivedType format. + SmallVector Elts; + Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_member)); + Elts.push_back(Context); + Elts.push_back(MDString::get(VMContext, Name)); + Elts.push_back(F); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits)); + Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), OffsetInBits)); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Flags)); + Elts.push_back(Ty); + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} + +/// CreateArtificialType - Create a new DIType with "artificial" flag set. +DIType DIBuilder::CreateArtificialType(DIType Ty) { + if (Ty.isArtificial()) + return Ty; + + SmallVector Elts; + MDNode *N = Ty; + assert (N && "Unexpected input DIType!"); + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { + if (Value *V = N->getOperand(i)) + Elts.push_back(V); + else + Elts.push_back(Constant::getNullValue(Type::getInt32Ty(VMContext))); + } + + unsigned CurFlags = Ty.getFlags(); + CurFlags = CurFlags | DIType::FlagArtificial; + + // Flags are stored at this slot. + Elts[8] = ConstantInt::get(Type::getInt32Ty(VMContext), CurFlags); + + return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); +} From rafael.espindola at gmail.com Thu Nov 4 11:32:18 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 04 Nov 2010 16:32:18 -0000 Subject: [llvm-commits] [llvm] r118249 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Message-ID: <20101104163218.D02E92A6C12C@llvm.org> Author: rafael Date: Thu Nov 4 11:32:18 2010 New Revision: 118249 URL: http://llvm.org/viewvc/llvm-project?rev=118249&view=rev Log: MCize. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp?rev=118249&r1=118248&r2=118249&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Thu Nov 4 11:32:18 2010 @@ -36,9 +36,8 @@ if (isVerbose() && Desc) OutStreamer.AddComment(Desc); - if (MAI->hasLEB128() && OutStreamer.hasRawTextSupport()) { - // FIXME: MCize. - OutStreamer.EmitRawText("\t.sleb128\t" + Twine(Value)); + if (MAI->hasLEB128()) { + OutStreamer.EmitSLEB128IntValue(Value); return; } @@ -60,10 +59,10 @@ unsigned PadTo) const { if (isVerbose() && Desc) OutStreamer.AddComment(Desc); - - if (MAI->hasLEB128() && PadTo == 0 && OutStreamer.hasRawTextSupport()) { - // FIXME: MCize. - OutStreamer.EmitRawText("\t.uleb128\t" + Twine(Value)); + + // FIXME: Should we add a PadTo option to the streamer? + if (MAI->hasLEB128() && PadTo == 0) { + OutStreamer.EmitULEB128IntValue(Value); return; } From rafael.espindola at gmail.com Thu Nov 4 12:04:24 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 04 Nov 2010 17:04:24 -0000 Subject: [llvm-commits] [llvm] r118250 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Message-ID: <20101104170424.701542A6C12C@llvm.org> Author: rafael Date: Thu Nov 4 12:04:24 2010 New Revision: 118250 URL: http://llvm.org/viewvc/llvm-project?rev=118250&view=rev Log: Revert previous patch. Some targets don't support uleb and say they do :-( Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp?rev=118250&r1=118249&r2=118250&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Thu Nov 4 12:04:24 2010 @@ -36,8 +36,9 @@ if (isVerbose() && Desc) OutStreamer.AddComment(Desc); - if (MAI->hasLEB128()) { - OutStreamer.EmitSLEB128IntValue(Value); + if (MAI->hasLEB128() && OutStreamer.hasRawTextSupport()) { + // FIXME: MCize. + OutStreamer.EmitRawText("\t.sleb128\t" + Twine(Value)); return; } @@ -59,10 +60,10 @@ unsigned PadTo) const { if (isVerbose() && Desc) OutStreamer.AddComment(Desc); - - // FIXME: Should we add a PadTo option to the streamer? - if (MAI->hasLEB128() && PadTo == 0) { - OutStreamer.EmitULEB128IntValue(Value); + + if (MAI->hasLEB128() && PadTo == 0 && OutStreamer.hasRawTextSupport()) { + // FIXME: MCize. + OutStreamer.EmitRawText("\t.uleb128\t" + Twine(Value)); return; } From tonic at nondot.org Thu Nov 4 12:38:13 2010 From: tonic at nondot.org (Tanya Lattner) Date: Thu, 04 Nov 2010 17:38:13 -0000 Subject: [llvm-commits] [www] r118253 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20101104173813.85E402A6C12C@llvm.org> Author: tbrethou Date: Thu Nov 4 12:38:13 2010 New Revision: 118253 URL: http://llvm.org/viewvc/llvm-project?rev=118253&view=rev Log: Update OpenCL BOF organizer name. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=118253&r1=118252&r2=118253&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Thu Nov 4 12:38:13 2010 @@ -91,7 +91,7 @@ 12:10 - 1:20LunchMarket Room 1:20 - 2:00The LLVM Assembler & Machine Code Infrastructure
Daniel Dunbar, Apple Inc.Almaden Ballroom Creating cling, an interactive interpreter interface for clang
Axel Naumann, CERNWinchester Room -OpenCL BOF
Alasdair Grant, ARMMarket Room +OpenCL BOF
Anton Lokhmotov, ARMMarket Room 2:00 - 2:40LLDB: Modular Debugging Infrastructure
Greg Clayton, Apple Inc.Almaden Ballroom The Crack Scripting Language
Michael Muller, GoogleWinchester Room ARM-MC and EABI support BOF
Renato Golin, ARMMarket Room From fvbommel at gmail.com Thu Nov 4 12:44:41 2010 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 4 Nov 2010 18:44:41 +0100 Subject: [llvm-commits] [llvm] r118248 - in /llvm/trunk: include/llvm/Analysis/DIBuilder.h lib/Analysis/CMakeLists.txt lib/Analysis/DIBuilder.cpp In-Reply-To: <20101104150139.2385E2A6C12C@llvm.org> References: <20101104150139.2385E2A6C12C@llvm.org> Message-ID: > + ? ?/// CreateCompileUnit - A CompileUnit provides an anchor for all debugging > + ? ?/// information generated during this instance of compilation. > + ? ?void CreateCompileUnit(unsigned Lang, StringRef F, StringRef D, StringRef P, > + ? ? ? ? ? ? ? ? ? ? ? ? ? bool isOptimized, StringRef Flags, unsigned RV); Since it's "intended to be a front-end friendly interface", maybe you should document these parameters? Or at least give them more meaningful names? > + ? ?/// CreateBasicType - Create debugging information entry for a basic > + ? ?/// type, e.g 'char'. > + ? ?DIType CreateBasicType(StringRef Name, uint64_t SizeInBits, > + ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t AlignInBits, unsigned Encoding); Ditto. Especially "Encoding" -- what's that for? How is the encoding encoded? :) (Maybe it should have an enum type instead?) > + ? ?/// CreateQaulifiedType - Create debugging information entry for a qualified > + ? ?/// type, e.g. 'const int'. > + ? ?DIType CreateQualifiedType(unsigned Tag, DIType FromTy); Tag is also unclear, what value is one supposed to pass here? Also, you typo'd the function name in the comment. > + ? ?/// CreateInheritance - Create debugging information entry to establish > + ? ?/// inheritnace relationship between two types. > + ? ?DIType CreateInheritance(DIType Ty, DIType BaseTy, uint64_t BaseOffset, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned Flags); typo'd inheritance. From rafael.espindola at gmail.com Thu Nov 4 13:17:08 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 04 Nov 2010 18:17:08 -0000 Subject: [llvm-commits] [llvm] r118254 - in /llvm/trunk/lib: CodeGen/AsmPrinter/AsmPrinterDwarf.cpp MC/MCAsmStreamer.cpp Message-ID: <20101104181708.753E92A6C12C@llvm.org> Author: rafael Date: Thu Nov 4 13:17:08 2010 New Revision: 118254 URL: http://llvm.org/viewvc/llvm-project?rev=118254&view=rev Log: Add 118023 back, but with proper spelling for .uleb128/.sleb128. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp?rev=118254&r1=118253&r2=118254&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Thu Nov 4 13:17:08 2010 @@ -36,9 +36,8 @@ if (isVerbose() && Desc) OutStreamer.AddComment(Desc); - if (MAI->hasLEB128() && OutStreamer.hasRawTextSupport()) { - // FIXME: MCize. - OutStreamer.EmitRawText("\t.sleb128\t" + Twine(Value)); + if (MAI->hasLEB128()) { + OutStreamer.EmitSLEB128IntValue(Value); return; } @@ -60,10 +59,10 @@ unsigned PadTo) const { if (isVerbose() && Desc) OutStreamer.AddComment(Desc); - - if (MAI->hasLEB128() && PadTo == 0 && OutStreamer.hasRawTextSupport()) { - // FIXME: MCize. - OutStreamer.EmitRawText("\t.uleb128\t" + Twine(Value)); + + // FIXME: Should we add a PadTo option to the streamer? + if (MAI->hasLEB128() && PadTo == 0) { + OutStreamer.EmitULEB128IntValue(Value); return; } Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=118254&r1=118253&r2=118254&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Nov 4 13:17:08 2010 @@ -512,12 +512,14 @@ } void MCAsmStreamer::EmitULEB128Value(const MCExpr *Value, unsigned AddrSpace) { - OS << ".uleb " << *Value; + assert(MAI.hasLEB128() && "Cannot print a .uleb"); + OS << ".uleb128 " << *Value; EmitEOL(); } void MCAsmStreamer::EmitSLEB128Value(const MCExpr *Value, unsigned AddrSpace) { - OS << ".sleb " << *Value; + assert(MAI.hasLEB128() && "Cannot print a .sleb"); + OS << ".sleb128 " << *Value; EmitEOL(); } From aggarwa4 at illinois.edu Thu Nov 4 13:42:16 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 04 Nov 2010 18:42:16 -0000 Subject: [llvm-commits] [poolalloc] r118256 - /poolalloc/trunk/lib/DSA/DataStructure.cpp Message-ID: <20101104184216.2952B2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Nov 4 13:42:15 2010 New Revision: 118256 URL: http://llvm.org/viewvc/llvm-project?rev=118256&view=rev Log: Do not collapse nodes, if one is a VOID array , and the other is an array node with some other type. Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=118256&r1=118255&r2=118256&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Thu Nov 4 13:42:15 2010 @@ -524,13 +524,15 @@ NOffset = NH.getOffset(); } } - if ((CurNodeH.getNode()->isArrayNode() && NH.getNode()->isArrayNode()) && - (CurNodeH.getNode()->getSize() != NH.getNode()->getSize())) { + if (CurNodeH.getNode()->isArrayNode() && NH.getNode()->isArrayNode()) { + if(NH.getNode()->getSize() != 1 && CurNodeH.getNode()->getSize() != 1 + && (NH.getNode()->getSize() != CurNodeH.getNode()->getSize())){ CurNodeH.getNode()->foldNodeCompletely(); NH.getNode()->foldNodeCompletely(); NSize = NH.getNode()->getSize(); // N = NH.getNode(); NOffset = NH.getOffset(); + } } @@ -799,11 +801,12 @@ DN = NH.getNode(); } } - if ((SN->isArrayNode() && DN->isArrayNode()) && - (SN->getSize() != DN->getSize())) { + if (SN->isArrayNode() && DN->isArrayNode()) { + if((SN->getSize() != DN->getSize()) && (SN->getSize() != 1) && DN->getSize() != 1) { DN->foldNodeCompletely(); DN = NH.getNode(); - } + } + } // Merge the type entries of the two nodes together... From benny.kra at googlemail.com Thu Nov 4 13:45:27 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 04 Nov 2010 18:45:27 -0000 Subject: [llvm-commits] [llvm] r118257 - /llvm/trunk/lib/Analysis/DIBuilder.cpp Message-ID: <20101104184527.6FA6D2A6C12C@llvm.org> Author: d0k Date: Thu Nov 4 13:45:27 2010 New Revision: 118257 URL: http://llvm.org/viewvc/llvm-project?rev=118257&view=rev Log: Use arrays instead of constant-sized SmallVectors. Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=118257&r1=118256&r2=118257&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (original) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Thu Nov 4 13:45:27 2010 @@ -16,6 +16,7 @@ #include "llvm/Constants.h" #include "llvm/IntrinsicInst.h" #include "llvm/Module.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Support/Dwarf.h" using namespace llvm; @@ -35,41 +36,43 @@ StringRef Directory, StringRef Producer, bool isOptimized, StringRef Flags, unsigned RunTimeVer) { - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_compile_unit)); - Elts.push_back(llvm::Constant::getNullValue(Type::getInt32Ty(VMContext))); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Lang)); - Elts.push_back(MDString::get(VMContext, Filename)); - Elts.push_back(MDString::get(VMContext, Directory)); - Elts.push_back(MDString::get(VMContext, Producer)); - // Deprecate isMain field. - Elts.push_back(ConstantInt::get(Type::getInt1Ty(VMContext), true)); // isMain - Elts.push_back(ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized)); - Elts.push_back(MDString::get(VMContext, Flags)); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), RunTimeVer)); - - TheCU = DICompileUnit(MDNode::get(VMContext, Elts.data(), Elts.size())); + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_compile_unit), + llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)), + ConstantInt::get(Type::getInt32Ty(VMContext), Lang), + MDString::get(VMContext, Filename), + MDString::get(VMContext, Directory), + MDString::get(VMContext, Producer), + // Deprecate isMain field. + ConstantInt::get(Type::getInt1Ty(VMContext), true), // isMain + ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized), + MDString::get(VMContext, Flags), + ConstantInt::get(Type::getInt32Ty(VMContext), RunTimeVer) + }; + TheCU = DICompileUnit(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateFile - Create a file descriptor to hold debugging information /// for a file. DIFile DIBuilder::CreateFile(StringRef Filename, StringRef Directory) { - assert (TheCU && "Unable to create DW_TAG_file_type without CompileUnit"); - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_file_type)); - Elts.push_back(MDString::get(VMContext, Filename)); - Elts.push_back(MDString::get(VMContext, Directory)); - Elts.push_back(TheCU); - return DIFile(MDNode::get(VMContext, Elts.data(), Elts.size())); + assert(TheCU && "Unable to create DW_TAG_file_type without CompileUnit"); + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_file_type), + MDString::get(VMContext, Filename), + MDString::get(VMContext, Directory), + TheCU + }; + return DIFile(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateEnumerator - Create a single enumerator value. DIEnumerator DIBuilder::CreateEnumerator(StringRef Name, uint64_t Val) { - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_enumerator)); - Elts.push_back(MDString::get(VMContext, Name)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), Val)); - return DIEnumerator(MDNode::get(VMContext, Elts.data(), Elts.size())); + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_enumerator), + MDString::get(VMContext, Name), + ConstantInt::get(Type::getInt64Ty(VMContext), Val) + }; + return DIEnumerator(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateBasicType - Create debugging information entry for a basic @@ -79,128 +82,135 @@ unsigned Encoding) { // Basic types are encoded in DIBasicType format. Line number, filename, // offset and flags are always empty here. - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_base_type)); - Elts.push_back(TheCU); - Elts.push_back(MDString::get(VMContext, Name)); - Elts.push_back(NULL); // Filename - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags; - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Encoding)); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_base_type), + TheCU, + MDString::get(VMContext, Name), + NULL, // Filename + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line + ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits), + ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits), + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Offset + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Flags; + ConstantInt::get(Type::getInt32Ty(VMContext), Encoding) + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateQaulifiedType - Create debugging information entry for a qualified /// type, e.g. 'const int'. DIType DIBuilder::CreateQualifiedType(unsigned Tag, DIType FromTy) { - /// Qualified types are encoded in DIDerivedType format. - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, Tag)); - Elts.push_back(TheCU); - Elts.push_back(MDString::get(VMContext, StringRef())); // Empty name. - Elts.push_back(NULL); // Filename - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags - Elts.push_back(FromTy); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // Qualified types are encoded in DIDerivedType format. + Value *Elts[] = { + GetTagConstant(VMContext, Tag), + TheCU, + MDString::get(VMContext, StringRef()), // Empty name. + NULL, // Filename + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Size + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Align + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Offset + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Flags + FromTy + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreatePointerType - Create debugging information entry for a pointer. DIType DIBuilder::CreatePointerType(DIType PointeeTy, uint64_t SizeInBits, uint64_t AlignInBits, StringRef Name) { - /// pointer types are encoded in DIDerivedType format. - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_pointer_type)); - Elts.push_back(TheCU); - Elts.push_back(MDString::get(VMContext, Name)); - Elts.push_back(NULL); // Filename - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags - Elts.push_back(PointeeTy); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // Pointer types are encoded in DIDerivedType format. + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_pointer_type), + TheCU, + MDString::get(VMContext, Name), + NULL, // Filename + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line + ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits), + ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits), + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Offset + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Flags + PointeeTy + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateReferenceType - Create debugging information entry for a reference. DIType DIBuilder::CreateReferenceType(DIType RTy) { - /// references are encoded in DIDerivedType format. - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_reference_type)); - Elts.push_back(TheCU); - Elts.push_back(NULL); // Name - Elts.push_back(NULL); // Filename - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags - Elts.push_back(RTy); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // References are encoded in DIDerivedType format. + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_reference_type), + TheCU, + NULL, // Name + NULL, // Filename + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Size + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Align + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Offset + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Flags + RTy + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateTypedef - Create debugging information entry for a typedef. DIType DIBuilder::CreateTypedef(DIType Ty, StringRef Name, DIFile File, unsigned LineNo) { - /// typedefs are encoded in DIDerivedType format. - assert (Ty.Verify() && "Invalid typedef type!"); - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_typedef)); - Elts.push_back(Ty.getContext()); - Elts.push_back(MDString::get(VMContext, Name)); - Elts.push_back(File); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNo)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags - Elts.push_back(Ty); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // typedefs are encoded in DIDerivedType format. + assert(Ty.Verify() && "Invalid typedef type!"); + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_typedef), + Ty.getContext(), + MDString::get(VMContext, Name), + File, + ConstantInt::get(Type::getInt32Ty(VMContext), LineNo), + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Size + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Align + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Offset + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Flags + Ty + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateFriend - Create debugging information entry for a 'friend'. DIType DIBuilder::CreateFriend(DIType Ty, DIType FriendTy) { - /// typedefs are encoded in DIDerivedType format. - assert (Ty.Verify() && "Invalid type!"); - assert (FriendTy.Verify() && "Invalid friend type!"); - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_friend)); - Elts.push_back(Ty); - Elts.push_back(NULL); // Name - Elts.push_back(Ty.getFile()); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Offset - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Flags - Elts.push_back(FriendTy); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // typedefs are encoded in DIDerivedType format. + assert(Ty.Verify() && "Invalid type!"); + assert(FriendTy.Verify() && "Invalid friend type!"); + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_friend), + Ty, + NULL, // Name + Ty.getFile(), + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Size + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Align + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Offset + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Flags + FriendTy + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateInheritance - Create debugging information entry to establish /// inheritnace relationship between two types. DIType DIBuilder::CreateInheritance(DIType Ty, DIType BaseTy, uint64_t BaseOffset, unsigned Flags) { - /// TAG_inheritance is encoded in DIDerivedType format. - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_inheritance)); - Elts.push_back(Ty); - Elts.push_back(NULL); // Name - Elts.push_back(NULL); // File - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), 0)); // Line - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Size - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), 0)); // Align - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), BaseOffset)); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Flags)); - Elts.push_back(BaseTy); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // TAG_inheritance is encoded in DIDerivedType format. + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_inheritance), + Ty, + NULL, // Name + NULL, // File + ConstantInt::get(Type::getInt32Ty(VMContext), 0), // Line + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Size + ConstantInt::get(Type::getInt64Ty(VMContext), 0), // Align + ConstantInt::get(Type::getInt64Ty(VMContext), BaseOffset), + ConstantInt::get(Type::getInt32Ty(VMContext), Flags), + BaseTy + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateMemberType - Create debugging information entry for a member. @@ -209,19 +219,20 @@ uint64_t SizeInBits, uint64_t AlignInBits, uint64_t OffsetInBits, unsigned Flags, DIType Ty) { - /// TAG_member is encoded in DIDerivedType format. - SmallVector Elts; - Elts.push_back(GetTagConstant(VMContext, dwarf::DW_TAG_member)); - Elts.push_back(Context); - Elts.push_back(MDString::get(VMContext, Name)); - Elts.push_back(F); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits)); - Elts.push_back(ConstantInt::get(Type::getInt64Ty(VMContext), OffsetInBits)); - Elts.push_back(ConstantInt::get(Type::getInt32Ty(VMContext), Flags)); - Elts.push_back(Ty); - return DIType(MDNode::get(VMContext, Elts.data(), Elts.size())); + // TAG_member is encoded in DIDerivedType format. + Value *Elts[] = { + GetTagConstant(VMContext, dwarf::DW_TAG_member), + Context, + MDString::get(VMContext, Name), + F, + ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber), + ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits), + ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits), + ConstantInt::get(Type::getInt64Ty(VMContext), OffsetInBits), + ConstantInt::get(Type::getInt32Ty(VMContext), Flags), + Ty + }; + return DIType(MDNode::get(VMContext, &Elts[0], array_lengthof(Elts))); } /// CreateArtificialType - Create a new DIType with "artificial" flag set. From baldrick at free.fr Thu Nov 4 16:16:46 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 04 Nov 2010 21:16:46 -0000 Subject: [llvm-commits] [llvm] r118260 - in /llvm/trunk: lib/Target/X86/X86SelectionDAGInfo.cpp test/CodeGen/Generic/2010-11-04-BigByval.ll Message-ID: <20101104211646.715492A6C12C@llvm.org> Author: baldrick Date: Thu Nov 4 16:16:46 2010 New Revision: 118260 URL: http://llvm.org/viewvc/llvm-project?rev=118260&view=rev Log: When passing a huge parameter using the byval mechanism, a long sequence of loads and stores was being generated to perform the copy on the x86 targets if the parameter was less than 4 byte aligned, causing llc to use up vast amounts of memory and time. Use a "rep movs" form instead. PR7170. Added: llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=118260&r1=118259&r2=118260&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Thu Nov 4 16:16:46 2010 @@ -187,19 +187,29 @@ if (!AlwaysInline && SizeVal > Subtarget->getMaxInlineSizeThreshold()) return SDValue(); - /// If not DWORD aligned, call the library. - if ((Align & 3) != 0) + /// If not DWORD aligned, it is more efficient to call the library. However + /// if calling the library is not allowed (AlwaysInline), then soldier on as + /// the code generated here is better than the long load-store sequence we + /// would otherwise get. + if (!AlwaysInline && (Align & 3) != 0) return SDValue(); // If to a segment-relative address space, use the default lowering. if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256) return SDValue(); - - // DWORD aligned - EVT AVT = MVT::i32; - if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned - AVT = MVT::i64; + + MVT AVT; + if (Align & 1) + AVT = MVT::i8; + else if (Align & 2) + AVT = MVT::i16; + else if (Align & 4) + // DWORD aligned + AVT = MVT::i32; + else + // QWORD aligned + AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; unsigned UBytes = AVT.getSizeInBits() / 8; unsigned CountVal = SizeVal / UBytes; Added: llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll?rev=118260&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll Thu Nov 4 16:16:46 2010 @@ -0,0 +1,11 @@ +; RUN: llc < %s +; PR7170 + +%big = type [131072 x i8] + +declare void @foo(%big* byval align 1) + +define void @bar(%big* byval align 1 %x) { + call void @foo(%big* byval align 1 %x) + ret void +} From daniel at zuster.org Fri Nov 5 02:19:10 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 05 Nov 2010 07:19:10 -0000 Subject: [llvm-commits] [llvm] r118272 - in /llvm/trunk: include/llvm/Support/CrashRecoveryContext.h lib/Support/CrashRecoveryContext.cpp Message-ID: <20101105071910.19B192A6C12C@llvm.org> Author: ddunbar Date: Fri Nov 5 02:19:09 2010 New Revision: 118272 URL: http://llvm.org/viewvc/llvm-project?rev=118272&view=rev Log: CrashRecoveryContext: Add RunSafelyOnThread helper function. Modified: llvm/trunk/include/llvm/Support/CrashRecoveryContext.h llvm/trunk/lib/Support/CrashRecoveryContext.cpp Modified: llvm/trunk/include/llvm/Support/CrashRecoveryContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CrashRecoveryContext.h?rev=118272&r1=118271&r2=118272&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CrashRecoveryContext.h (original) +++ llvm/trunk/include/llvm/Support/CrashRecoveryContext.h Fri Nov 5 02:19:09 2010 @@ -67,6 +67,14 @@ /// the backtrace of the crash on failures. bool RunSafely(void (*Fn)(void*), void *UserData); + /// \brief Execute the provide callback function (with the given arguments) in + /// a protected context which is run in another thread (optionally with a + /// requested stack size). + /// + /// See RunSafely() and llvm_execute_on_thread(). + bool RunSafelyOnThread(void (*Fn)(void*), void *UserData, + unsigned RequestedStackSize = 0); + /// \brief Explicitly trigger a crash recovery in the current process, and /// return failure from RunSafely(). This function does not return. void HandleCrash(); Modified: llvm/trunk/lib/Support/CrashRecoveryContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CrashRecoveryContext.cpp?rev=118272&r1=118271&r2=118272&view=diff ============================================================================== --- llvm/trunk/lib/Support/CrashRecoveryContext.cpp (original) +++ llvm/trunk/lib/Support/CrashRecoveryContext.cpp Fri Nov 5 02:19:09 2010 @@ -205,3 +205,26 @@ assert(CRC->Failed && "No crash was detected!"); return CRC->Backtrace; } + +// + +namespace { +struct RunSafelyOnThreadInfo { + void (*UserFn)(void*); + void *UserData; + CrashRecoveryContext *CRC; + bool Result; +}; +} + +static void RunSafelyOnThread_Dispatch(void *UserData) { + RunSafelyOnThreadInfo *Info = + reinterpret_cast(UserData); + Info->Result = Info->CRC->RunSafely(Info->UserFn, Info->UserData); +} +bool CrashRecoveryContext::RunSafelyOnThread(void (*Fn)(void*), void *UserData, + unsigned RequestedStackSize) { + RunSafelyOnThreadInfo Info = { Fn, UserData, this, false }; + llvm_execute_on_thread(RunSafelyOnThread_Dispatch, &Info, RequestedStackSize); + return Info.Result; +} From ismail at namtrac.org Fri Nov 5 10:07:29 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Fri, 5 Nov 2010 17:07:29 +0200 Subject: [llvm-commits] PATCH: Fix PR8528 In-Reply-To: References: Message-ID: ping ? On Thu, Nov 4, 2010 at 12:54 AM, ?smail D?nmez wrote: > Hi; > > Original patch by pdox on #llvm . Asm parser was not handling fist and > fistp instructions correctly. Please apply. > > Regards, > ismail > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101105/9644af21/attachment.html From baldrick at free.fr Fri Nov 5 10:20:29 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 05 Nov 2010 15:20:29 -0000 Subject: [llvm-commits] [llvm] r118275 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20101105152029.A52B22A6C12C@llvm.org> Author: baldrick Date: Fri Nov 5 10:20:29 2010 New Revision: 118275 URL: http://llvm.org/viewvc/llvm-project?rev=118275&view=rev Log: When passing a parameter using the 'byval' mechanism, inline code needs to be used to perform the copy, which may be of lots of memory [*]. It would be good if the fall-back code generated something reasonable, i.e. did the copy in a loop, rather than vast numbers of loads and stores. Add a note about this. Currently target specific code seems to always kick in so this is more of a theoretical issue rather than a practical one now that X86 has been fixed. [*] It's amazing how often people pass mega-byte long arrays by copy... Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=118275&r1=118274&r2=118275&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Nov 5 10:20:29 2010 @@ -3283,6 +3283,8 @@ // Expand memcpy to a series of load and store ops if the size operand falls // below a certain threshold. + // TODO: In the AlwaysInline case, if the size is big then generate a loop + // rather than maybe a humongous number of loads and stores. const TargetLowering &TLI = DAG.getTargetLoweringInfo(); std::vector MemOps; bool DstAlignCanChange = false; From grosbach at apple.com Fri Nov 5 12:37:13 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 17:37:13 -0000 Subject: [llvm-commits] [llvm] r118280 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101105173713.C701D2A6C12C@llvm.org> Author: grosbach Date: Fri Nov 5 12:37:13 2010 New Revision: 118280 URL: http://llvm.org/viewvc/llvm-project?rev=118280&view=rev Log: Add FIXME. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118280&r1=118279&r2=118280&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Nov 5 12:37:13 2010 @@ -231,6 +231,7 @@ SmallString<128> Str; raw_svector_ostream OS(Str); EmitMachineConstantPoolValue(MCPV, OS); + // FIXME: non-assembly streamer support. OutStreamer.EmitRawText(OS.str()); } From grosbach at apple.com Fri Nov 5 12:48:05 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 17:48:05 -0000 Subject: [llvm-commits] [llvm] r118281 - /llvm/trunk/include/llvm/Support/MachO.h Message-ID: <20101105174805.4F49D2A6C12C@llvm.org> Author: grosbach Date: Fri Nov 5 12:48:05 2010 New Revision: 118281 URL: http://llvm.org/viewvc/llvm-project?rev=118281&view=rev Log: Add v5 and v7 ARM CPU subtype values. Modified: llvm/trunk/include/llvm/Support/MachO.h Modified: llvm/trunk/include/llvm/Support/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MachO.h?rev=118281&r1=118280&r2=118281&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/MachO.h (original) +++ llvm/trunk/include/llvm/Support/MachO.h Fri Nov 5 12:48:05 2010 @@ -681,7 +681,9 @@ // ARM CPUSubType_ARM_ALL = 0, CPUSubType_ARM_V4T = 5, + CPUSubType_ARM_V5 = 7, CPUSubType_ARM_V6 = 6, + CPUSubType_ARM_V7 = 9, // PowerPC CPUSubType_POWERPC_ALL = 0, From daniel at zuster.org Fri Nov 5 13:09:57 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 5 Nov 2010 11:09:57 -0700 Subject: [llvm-commits] [PATCH] MCFragments Clean Up In-Reply-To: References: Message-ID: Hi David, MCFragment actually used to be virtual. I eventually killed this because in practice I felt like the number of interesting fragments was likely to be small, and the vtable construction cost wasn't worth it. I would propose making an extensible MCFragment subclass to cover the case of wanting to add plugable MCFragments, instead of imposing a vtable construction cost on the core classes (which was construct many hundreds of, and don't actually dispatch on much). - Daniel On Thu, Oct 14, 2010 at 11:48 AM, David Meyer wrote: > Hi Dan, > > This patch against rev 116493?does the following: > > * Adds four virtual methods to MCFragment: > ?? ?ComputeSize() - Compute the size of this fragment > ?? ?WriteData() - Write the data of this fragment > ?? ?AssertLegalInVirtualSection() - Assert that this fragment is legal > in a virtual section > ?? ?dump_kind_data() - Dump the kind-specific data for this fragment > > * Moves the implementation of these actions from MCAssembler.cpp to a > new file "MCFragment.cpp" > > * As a benefit, most of the switches on MCFragment::Kind and many of > the MCFragment casts go away. > > * Introduces the PendingLayout flag to make it possible to reuse the MCAsmLayout > getter functions?(i.e. getFragmentAddress() and getFragmentOffset()) > while inside of > ComputeSize(). > > Thanks. Please let me know what you think. > > - David M > From grosbach at apple.com Fri Nov 5 13:47:32 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 18:47:32 -0000 Subject: [llvm-commits] [llvm] r118287 - /llvm/trunk/lib/MC/MCMachOStreamer.cpp Message-ID: <20101105184732.716532A6C12C@llvm.org> Author: grosbach Date: Fri Nov 5 13:47:32 2010 New Revision: 118287 URL: http://llvm.org/viewvc/llvm-project?rev=118287&view=rev Log: syntaxunified directive is a no-op for MachO writing. Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=118287&r1=118286&r2=118287&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Fri Nov 5 13:47:32 2010 @@ -149,6 +149,7 @@ void MCMachOStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { switch (Flag) { + case MCAF_SyntaxUnified: return; // no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; From grosbach at apple.com Fri Nov 5 13:48:58 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 18:48:58 -0000 Subject: [llvm-commits] [llvm] r118288 - in /llvm/trunk: include/llvm/MC/MachObjectWriter.h lib/MC/MachObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/X86/X86AsmBackend.cpp Message-ID: <20101105184858.A66812A6C12C@llvm.org> Author: grosbach Date: Fri Nov 5 13:48:58 2010 New Revision: 118288 URL: http://llvm.org/viewvc/llvm-project?rev=118288&view=rev Log: Allow targets to specify the MachO CPUType/CPUSubtype information. Modified: llvm/trunk/include/llvm/MC/MachObjectWriter.h llvm/trunk/lib/MC/MachObjectWriter.cpp llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Modified: llvm/trunk/include/llvm/MC/MachObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MachObjectWriter.h?rev=118288&r1=118287&r2=118288&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MachObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/MachObjectWriter.h Fri Nov 5 13:48:58 2010 @@ -25,7 +25,8 @@ void *Impl; public: - MachObjectWriter(raw_ostream &OS, bool Is64Bit, bool IsLittleEndian = true); + MachObjectWriter(raw_ostream &OS, bool Is64Bit, uint32_t CPUType, + uint32_t CPUSubtype, bool IsLittleEndian = true); virtual ~MachObjectWriter(); virtual void ExecutePostLayoutBinding(MCAssembler &Asm); Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=118288&r1=118287&r2=118288&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Fri Nov 5 13:48:58 2010 @@ -290,9 +290,14 @@ unsigned Is64Bit : 1; + uint32_t CPUType; + uint32_t CPUSubtype; + public: - MachObjectWriterImpl(MachObjectWriter *_Writer, bool _Is64Bit) - : Writer(_Writer), OS(Writer->getStream()), Is64Bit(_Is64Bit) { + MachObjectWriterImpl(MachObjectWriter *_Writer, bool _Is64Bit, + uint32_t _CPUType, uint32_t _CPUSubtype) + : Writer(_Writer), OS(Writer->getStream()), Is64Bit(_Is64Bit), + CPUType(_CPUType), CPUSubtype(_CPUSubtype) { } void Write8(uint8_t Value) { Writer->Write8(Value); } @@ -319,10 +324,9 @@ Write32(Is64Bit ? Header_Magic64 : Header_Magic32); - // FIXME: Support cputype. - Write32(Is64Bit ? MachO::CPUTypeX86_64 : MachO::CPUTypeI386); - // FIXME: Support cpusubtype. - Write32(MachO::CPUSubType_I386_ALL); + Write32(CPUType); + Write32(CPUSubtype); + Write32(HFT_Object); Write32(NumLoadCommands); // Object files have a single load command, the // segment. @@ -1329,10 +1333,12 @@ MachObjectWriter::MachObjectWriter(raw_ostream &OS, bool Is64Bit, + uint32_t CPUType, + uint32_t CPUSubtype, bool IsLittleEndian) : MCObjectWriter(OS, IsLittleEndian) { - Impl = new MachObjectWriterImpl(this, Is64Bit); + Impl = new MachObjectWriterImpl(this, Is64Bit, CPUType, CPUSubtype); } MachObjectWriter::~MachObjectWriter() { Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118288&r1=118287&r2=118288&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Fri Nov 5 13:48:58 2010 @@ -20,6 +20,7 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MachObjectWriter.h" #include "llvm/Support/ELF.h" +#include "llvm/Support/MachO.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetRegistry.h" @@ -128,7 +129,9 @@ } MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return new MachObjectWriter(OS, /*Is64Bit=*/false); + // FIXME: Subtarget info should be derived. Force v7 for now. + return new MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeARM, + MachO::CPUSubType_ARM_V7); } virtual bool doesSectionRequireSymbols(const MCSection &Section) const { Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=118288&r1=118287&r2=118288&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Fri Nov 5 13:48:58 2010 @@ -21,6 +21,7 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MachObjectWriter.h" #include "llvm/Support/ELF.h" +#include "llvm/Support/MachO.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetRegistry.h" @@ -396,7 +397,8 @@ } MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return new MachObjectWriter(OS, /*Is64Bit=*/false); + return new MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeI386, + MachO::CPUSubType_I386_ALL); } }; @@ -412,7 +414,8 @@ } MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return new MachObjectWriter(OS, /*Is64Bit=*/true); + return new MachObjectWriter(OS, /*Is64Bit=*/true, MachO::CPUTypeX86_64, + MachO::CPUSubType_I386_ALL); } virtual bool doesSectionRequireSymbols(const MCSection &Section) const { From grosbach at apple.com Fri Nov 5 13:50:35 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 18:50:35 -0000 Subject: [llvm-commits] [llvm] r118289 - /llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Message-ID: <20101105185035.567F42A6C12C@llvm.org> Author: grosbach Date: Fri Nov 5 13:50:35 2010 New Revision: 118289 URL: http://llvm.org/viewvc/llvm-project?rev=118289&view=rev Log: Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work (relocations, e.g.), but this will allow simple things to flow through. Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118289&r1=118288&r2=118289&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Fri Nov 5 13:50:35 2010 @@ -111,7 +111,6 @@ DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) { HasScatteredSymbols = true; - assert(0 && "DarwinARMAsmBackend::DarwinARMAsmBackend() unimplemented"); } virtual const MCObjectFormat &getObjectFormat() const { From resistor at mac.com Fri Nov 5 14:27:47 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 05 Nov 2010 19:27:47 -0000 Subject: [llvm-commits] [llvm] r118291 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s Message-ID: <20101105192747.2F8C42A6C12C@llvm.org> Author: resistor Date: Fri Nov 5 14:27:46 2010 New Revision: 118291 URL: http://llvm.org/viewvc/llvm-project?rev=118291&view=rev Log: Add codegen and encoding support for the immediate form of vbic. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/vbits.ll llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 14:27:46 2010 @@ -673,8 +673,10 @@ setTargetDAGCombine(ISD::SUB); setTargetDAGCombine(ISD::MUL); - if (Subtarget->hasV6T2Ops()) + if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) setTargetDAGCombine(ISD::OR); + if (Subtarget->hasNEON()) + setTargetDAGCombine(ISD::AND); setStackPointerRegisterToSaveRestore(ARM::SP); @@ -4443,6 +4445,36 @@ return SDValue(); } +static SDValue PerformANDCombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI) { + // Attempt to use immediate-form VBIC + BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1)); + DebugLoc dl = N->getDebugLoc(); + EVT VT = N->getValueType(0); + SelectionDAG &DAG = DCI.DAG; + + APInt SplatBits, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (BVN && + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { + if (SplatBitSize <= 64) { + EVT VbicVT; + SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), + SplatUndef.getZExtValue(), SplatBitSize, + DAG, VbicVT, VT.is128BitVector(), false); + if (Val.getNode()) { + SDValue Input = + DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0)); + SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic); + } + } + } + + return SDValue(); +} + /// PerformORCombine - Target-specific dag combine xforms for ISD::OR static SDValue PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, @@ -5066,6 +5098,7 @@ case ISD::SUB: return PerformSUBCombine(N, DCI); case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); case ISD::OR: return PerformORCombine(N, DCI, Subtarget); + case ISD::AND: return PerformANDCombine(N, DCI); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 14:27:46 2010 @@ -165,7 +165,9 @@ BFI, // Vector OR with immediate - VORRIMM + VORRIMM, + // Vector AND with NOT of immediate + VBICIMM }; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Nov 5 14:27:46 2010 @@ -72,6 +72,7 @@ def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; +def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; @@ -3308,13 +3309,13 @@ let Inst{9} = SIMM{9}; } -def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1, +def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), IIC_VMOVImm, "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { - let Inst{11-9} = SIMM{11-9}; + let Inst{10-9} = SIMM{10-9}; } def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, @@ -3326,13 +3327,13 @@ let Inst{9} = SIMM{9}; } -def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1, +def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), IIC_VMOVImm, "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { - let Inst{11-9} = SIMM{11-9}; + let Inst{10-9} = SIMM{10-9}; } @@ -3348,6 +3349,42 @@ [(set QPR:$dst, (v4i32 (and QPR:$src1, (vnotq QPR:$src2))))]>; +def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + IIC_VMOVImm, + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", + [(set DPR:$Vd, + (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + +def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + IIC_VMOVImm, + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", + [(set DPR:$Vd, + (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { + let Inst{10-9} = SIMM{10-9}; +} + +def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + IIC_VMOVImm, + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", + [(set QPR:$Vd, + (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + +def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + IIC_VMOVImm, + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", + [(set QPR:$Vd, + (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { + let Inst{10-9} = SIMM{10-9}; +} + // VORN : Vector Bitwise OR NOT def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Fri Nov 5 14:27:46 2010 @@ -525,3 +525,23 @@ %tmp3 = or <16 x i8> %tmp1, ret <16 x i8> %tmp3 } + +define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { +; CHECK: v_bicimm: +; CHECK-NOT: vmov +; CHECK-NOT vmvn +; CHECK: vbic + %tmp1 = load <8 x i8>* %A + %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > + ret <8 x i8> %tmp3 +} + +define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { +; CHECK: v_bicimmQ: +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vbic + %tmp1 = load <16 x i8>* %A + %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > + ret <16 x i8> %tmp3 +} Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Fri Nov 5 14:27:46 2010 @@ -26,6 +26,10 @@ vbic d16, d17, d16 @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] vbic q8, q8, q9 +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] + vbic.i32 d16, #0xFF000000 +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] + vbic.i32 q8, #0xFF000000 @ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] vorn d16, d17, d16 From benny.kra at googlemail.com Fri Nov 5 14:56:38 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 05 Nov 2010 19:56:38 -0000 Subject: [llvm-commits] [llvm] r118294 - /llvm/trunk/lib/MC/MCELFStreamer.cpp Message-ID: <20101105195638.325A92A6C12D@llvm.org> Author: d0k Date: Fri Nov 5 14:56:38 2010 New Revision: 118294 URL: http://llvm.org/viewvc/llvm-project?rev=118294&view=rev Log: Put class into an anonymous namespace. Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=118294&r1=118293&r2=118294&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Fri Nov 5 14:56:38 2010 @@ -212,6 +212,7 @@ // that equals the original symbol (tmp = bar). With this hack the writer // gets a relocation with tmp and can correctly implement weak references. +namespace { class WeakRefExpr : public MCTargetExpr { private: const MCSymbolRefExpr *Alias; @@ -235,6 +236,7 @@ return new (Ctx) WeakRefExpr(A); } }; +} // end anonymous namespace void MCELFStreamer::EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) { getAssembler().getOrCreateSymbolData(*Symbol); From grosbach at apple.com Fri Nov 5 15:34:24 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 20:34:24 -0000 Subject: [llvm-commits] [llvm] r118295 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101105203424.3E5ED2A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 15:34:24 2010 New Revision: 118295 URL: http://llvm.org/viewvc/llvm-project?rev=118295&view=rev Log: MC'ize simple ARMConstantValue entry emission (with a FIXME). Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118295&r1=118294&r2=118295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Nov 5 15:34:24 2010 @@ -228,38 +228,26 @@ /// EmitMachineConstantPoolValue - Print a machine constantpool value to /// the .s file. virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { - SmallString<128> Str; - raw_svector_ostream OS(Str); - EmitMachineConstantPoolValue(MCPV, OS); - // FIXME: non-assembly streamer support. - OutStreamer.EmitRawText(OS.str()); - } - - void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV, - raw_ostream &O) { - switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) { - case 1: O << MAI->getData8bitsDirective(0); break; - case 2: O << MAI->getData16bitsDirective(0); break; - case 4: O << MAI->getData32bitsDirective(0); break; - default: assert(0 && "Unknown CPV size"); - } + int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); ARMConstantPoolValue *ACPV = static_cast(MCPV); + SmallString<128> Str; + raw_svector_ostream OS(Str); if (ACPV->isLSDA()) { - O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); + OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); } else if (ACPV->isBlockAddress()) { - O << *GetBlockAddressSymbol(ACPV->getBlockAddress()); + OS << *GetBlockAddressSymbol(ACPV->getBlockAddress()); } else if (ACPV->isGlobalValue()) { const GlobalValue *GV = ACPV->getGV(); bool isIndirect = Subtarget->isTargetDarwin() && Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); if (!isIndirect) - O << *Mang->getSymbol(GV); + OS << *Mang->getSymbol(GV); else { // FIXME: Remove this when Darwin transition to @GOT like syntax. MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); - O << *Sym; + OS << *Sym; MachineModuleInfoMachO &MMIMachO = MMI->getObjFileInfo(); @@ -272,17 +260,38 @@ } } else { assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); - O << *GetExternalSymbolSymbol(ACPV->getSymbol()); + OS << *GetExternalSymbolSymbol(ACPV->getSymbol()); } - if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")"; - if (ACPV->getPCAdjustment() != 0) { - O << "-(" << MAI->getPrivateGlobalPrefix() << "PC" - << getFunctionNumber() << "_" << ACPV->getLabelId() - << "+" << (unsigned)ACPV->getPCAdjustment(); - if (ACPV->mustAddCurrentAddress()) - O << "-."; - O << ')'; + // Create an MCSymbol for the reference. + MCSymbol *MCSym = OutContext.GetOrCreateSymbol(OS.str()); + const MCExpr *Expr = MCSymbolRefExpr::Create(MCSym, OutContext); + + // FIXME: Model the whole expression an an MCExpr and we can get rid + // of this hasRawTextSupport() clause and just do an EmitValue(). + if (OutStreamer.hasRawTextSupport()) { + if (ACPV->hasModifier()) OS << "(" << ACPV->getModifier() << ")"; + if (ACPV->getPCAdjustment() != 0) { + OS << "-(" << MAI->getPrivateGlobalPrefix() << "PC" + << getFunctionNumber() << "_" << ACPV->getLabelId() + << "+" << (unsigned)ACPV->getPCAdjustment(); + if (ACPV->mustAddCurrentAddress()) + OS << "-."; + OS << ')'; + } + const char *DataDirective = 0; + switch (Size) { + case 1: DataDirective = MAI->getData8bitsDirective(0); break; + case 2: DataDirective = MAI->getData16bitsDirective(0); break; + case 4: DataDirective = MAI->getData32bitsDirective(0); break; + default: assert(0 && "Unknown CPV size"); + } + Twine Text(DataDirective, OS.str()); + OutStreamer.EmitRawText(Text); + } else { + assert(!ACPV->hasModifier() && ACPV->getPCAdjustment() == 0 && + "ARM binary streamer of non-trivial constant pool value!"); + OutStreamer.EmitValue(Expr, Size); } } }; From grosbach at apple.com Fri Nov 5 15:41:12 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 20:41:12 -0000 Subject: [llvm-commits] [llvm] r118296 - /llvm/trunk/include/llvm/MC/MCDirectives.h Message-ID: <20101105204112.4AEB02A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 15:41:12 2010 New Revision: 118296 URL: http://llvm.org/viewvc/llvm-project?rev=118296&view=rev Log: Trailing whitespace. Modified: llvm/trunk/include/llvm/MC/MCDirectives.h Modified: llvm/trunk/include/llvm/MC/MCDirectives.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDirectives.h?rev=118296&r1=118295&r2=118296&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDirectives.h (original) +++ llvm/trunk/include/llvm/MC/MCDirectives.h Fri Nov 5 15:41:12 2010 @@ -46,7 +46,7 @@ MCAF_SyntaxUnified, ///< .syntax (ARM/ELF) MCAF_SubsectionsViaSymbols ///< .subsections_via_symbols (MachO) }; - + } // end namespace llvm #endif From bob.wilson at apple.com Fri Nov 5 16:35:39 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 5 Nov 2010 14:35:39 -0700 Subject: [llvm-commits] [llvm] r118291 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s In-Reply-To: <20101105192747.2F8C42A6C12C@llvm.org> References: <20101105192747.2F8C42A6C12C@llvm.org> Message-ID: This looks good. You're still going to fix isNEONModifiedImm to distinguish VBIC/VORR, right? On Nov 5, 2010, at 12:27 PM, Owen Anderson wrote: > Author: resistor > Date: Fri Nov 5 14:27:46 2010 > New Revision: 118291 > > URL: http://llvm.org/viewvc/llvm-project?rev=118291&view=rev > Log: > Add codegen and encoding support for the immediate form of vbic. > > Modified: > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.h > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/test/CodeGen/ARM/vbits.ll > llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 14:27:46 2010 > @@ -673,8 +673,10 @@ > setTargetDAGCombine(ISD::SUB); > setTargetDAGCombine(ISD::MUL); > > - if (Subtarget->hasV6T2Ops()) > + if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) > setTargetDAGCombine(ISD::OR); > + if (Subtarget->hasNEON()) > + setTargetDAGCombine(ISD::AND); > > setStackPointerRegisterToSaveRestore(ARM::SP); > > @@ -4443,6 +4445,36 @@ > return SDValue(); > } > > +static SDValue PerformANDCombine(SDNode *N, > + TargetLowering::DAGCombinerInfo &DCI) { > + // Attempt to use immediate-form VBIC > + BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1)); > + DebugLoc dl = N->getDebugLoc(); > + EVT VT = N->getValueType(0); > + SelectionDAG &DAG = DCI.DAG; > + > + APInt SplatBits, SplatUndef; > + unsigned SplatBitSize; > + bool HasAnyUndefs; > + if (BVN && > + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { > + if (SplatBitSize <= 64) { > + EVT VbicVT; > + SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), > + SplatUndef.getZExtValue(), SplatBitSize, > + DAG, VbicVT, VT.is128BitVector(), false); > + if (Val.getNode()) { > + SDValue Input = > + DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0)); > + SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); > + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic); > + } > + } > + } > + > + return SDValue(); > +} > + > /// PerformORCombine - Target-specific dag combine xforms for ISD::OR > static SDValue PerformORCombine(SDNode *N, > TargetLowering::DAGCombinerInfo &DCI, > @@ -5066,6 +5098,7 @@ > case ISD::SUB: return PerformSUBCombine(N, DCI); > case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); > case ISD::OR: return PerformORCombine(N, DCI, Subtarget); > + case ISD::AND: return PerformANDCombine(N, DCI); > case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); > case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); > case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 14:27:46 2010 > @@ -165,7 +165,9 @@ > BFI, > > // Vector OR with immediate > - VORRIMM > + VORRIMM, > + // Vector AND with NOT of immediate > + VBICIMM > }; > } > > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Nov 5 14:27:46 2010 > @@ -72,6 +72,7 @@ > def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, > SDTCisVT<2, i32>]>; > def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; > +def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; > > def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; > > @@ -3308,13 +3309,13 @@ > let Inst{9} = SIMM{9}; > } > > -def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1, > +def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, > (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), > IIC_VMOVImm, > "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", > [(set DPR:$Vd, > (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { > - let Inst{11-9} = SIMM{11-9}; > + let Inst{10-9} = SIMM{10-9}; > } > > def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, > @@ -3326,13 +3327,13 @@ > let Inst{9} = SIMM{9}; > } > > -def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1, > +def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, > (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), > IIC_VMOVImm, > "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", > [(set QPR:$Vd, > (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { > - let Inst{11-9} = SIMM{11-9}; > + let Inst{10-9} = SIMM{10-9}; > } > > > @@ -3348,6 +3349,42 @@ > [(set QPR:$dst, (v4i32 (and QPR:$src1, > (vnotq QPR:$src2))))]>; > > +def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, > + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), > + IIC_VMOVImm, > + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", > + [(set DPR:$Vd, > + (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { > + let Inst{9} = SIMM{9}; > +} > + > +def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, > + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), > + IIC_VMOVImm, > + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", > + [(set DPR:$Vd, > + (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { > + let Inst{10-9} = SIMM{10-9}; > +} > + > +def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, > + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), > + IIC_VMOVImm, > + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", > + [(set QPR:$Vd, > + (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { > + let Inst{9} = SIMM{9}; > +} > + > +def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, > + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), > + IIC_VMOVImm, > + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", > + [(set QPR:$Vd, > + (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { > + let Inst{10-9} = SIMM{10-9}; > +} > + > // VORN : Vector Bitwise OR NOT > def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), > (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, > > Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Fri Nov 5 14:27:46 2010 > @@ -525,3 +525,23 @@ > %tmp3 = or <16 x i8> %tmp1, > ret <16 x i8> %tmp3 > } > + > +define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { > +; CHECK: v_bicimm: > +; CHECK-NOT: vmov > +; CHECK-NOT vmvn > +; CHECK: vbic > + %tmp1 = load <8 x i8>* %A > + %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > > + ret <8 x i8> %tmp3 > +} > + > +define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { > +; CHECK: v_bicimmQ: > +; CHECK-NOT: vmov > +; CHECK-NOT: vmvn > +; CHECK: vbic > + %tmp1 = load <16 x i8>* %A > + %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > > + ret <16 x i8> %tmp3 > +} > > Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) > +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Fri Nov 5 14:27:46 2010 > @@ -26,6 +26,10 @@ > vbic d16, d17, d16 > @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] > vbic q8, q8, q9 > +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] > + vbic.i32 d16, #0xFF000000 > +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] > + vbic.i32 q8, #0xFF000000 > > @ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] > vorn d16, d17, d16 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Fri Nov 5 16:39:03 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 05 Nov 2010 14:39:03 -0700 Subject: [llvm-commits] [llvm] r118291 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s In-Reply-To: References: <20101105192747.2F8C42A6C12C@llvm.org> Message-ID: <3FA1A513-3D3F-45E0-AB92-03B8C52D6A75@mac.com> On Nov 5, 2010, at 2:35 PM, Bob Wilson wrote: > This looks good. You're still going to fix isNEONModifiedImm to distinguish VBIC/VORR, right? I'm not sure it needs to. There seem to be only two cases: all types allowed (isVMOV == true) and only i16 and i32 allows (isVMOV == false). Are there other modified immediate instructions that have some different type combination they allow? --Owen > On Nov 5, 2010, at 12:27 PM, Owen Anderson wrote: > >> Author: resistor >> Date: Fri Nov 5 14:27:46 2010 >> New Revision: 118291 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118291&view=rev >> Log: >> Add codegen and encoding support for the immediate form of vbic. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp >> llvm/trunk/lib/Target/ARM/ARMISelLowering.h >> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> llvm/trunk/test/CodeGen/ARM/vbits.ll >> llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s >> >> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 14:27:46 2010 >> @@ -673,8 +673,10 @@ >> setTargetDAGCombine(ISD::SUB); >> setTargetDAGCombine(ISD::MUL); >> >> - if (Subtarget->hasV6T2Ops()) >> + if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) >> setTargetDAGCombine(ISD::OR); >> + if (Subtarget->hasNEON()) >> + setTargetDAGCombine(ISD::AND); >> >> setStackPointerRegisterToSaveRestore(ARM::SP); >> >> @@ -4443,6 +4445,36 @@ >> return SDValue(); >> } >> >> +static SDValue PerformANDCombine(SDNode *N, >> + TargetLowering::DAGCombinerInfo &DCI) { >> + // Attempt to use immediate-form VBIC >> + BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1)); >> + DebugLoc dl = N->getDebugLoc(); >> + EVT VT = N->getValueType(0); >> + SelectionDAG &DAG = DCI.DAG; >> + >> + APInt SplatBits, SplatUndef; >> + unsigned SplatBitSize; >> + bool HasAnyUndefs; >> + if (BVN && >> + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { >> + if (SplatBitSize <= 64) { >> + EVT VbicVT; >> + SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), >> + SplatUndef.getZExtValue(), SplatBitSize, >> + DAG, VbicVT, VT.is128BitVector(), false); >> + if (Val.getNode()) { >> + SDValue Input = >> + DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0)); >> + SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); >> + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic); >> + } >> + } >> + } >> + >> + return SDValue(); >> +} >> + >> /// PerformORCombine - Target-specific dag combine xforms for ISD::OR >> static SDValue PerformORCombine(SDNode *N, >> TargetLowering::DAGCombinerInfo &DCI, >> @@ -5066,6 +5098,7 @@ >> case ISD::SUB: return PerformSUBCombine(N, DCI); >> case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); >> case ISD::OR: return PerformORCombine(N, DCI, Subtarget); >> + case ISD::AND: return PerformANDCombine(N, DCI); >> case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); >> case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); >> case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); >> >> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 14:27:46 2010 >> @@ -165,7 +165,9 @@ >> BFI, >> >> // Vector OR with immediate >> - VORRIMM >> + VORRIMM, >> + // Vector AND with NOT of immediate >> + VBICIMM >> }; >> } >> >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Nov 5 14:27:46 2010 >> @@ -72,6 +72,7 @@ >> def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, >> SDTCisVT<2, i32>]>; >> def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; >> +def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; >> >> def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; >> >> @@ -3308,13 +3309,13 @@ >> let Inst{9} = SIMM{9}; >> } >> >> -def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1, >> +def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, >> (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), >> IIC_VMOVImm, >> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", >> [(set DPR:$Vd, >> (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { >> - let Inst{11-9} = SIMM{11-9}; >> + let Inst{10-9} = SIMM{10-9}; >> } >> >> def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, >> @@ -3326,13 +3327,13 @@ >> let Inst{9} = SIMM{9}; >> } >> >> -def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1, >> +def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, >> (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), >> IIC_VMOVImm, >> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", >> [(set QPR:$Vd, >> (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { >> - let Inst{11-9} = SIMM{11-9}; >> + let Inst{10-9} = SIMM{10-9}; >> } >> >> >> @@ -3348,6 +3349,42 @@ >> [(set QPR:$dst, (v4i32 (and QPR:$src1, >> (vnotq QPR:$src2))))]>; >> >> +def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, >> + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), >> + IIC_VMOVImm, >> + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", >> + [(set DPR:$Vd, >> + (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { >> + let Inst{9} = SIMM{9}; >> +} >> + >> +def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, >> + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), >> + IIC_VMOVImm, >> + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", >> + [(set DPR:$Vd, >> + (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { >> + let Inst{10-9} = SIMM{10-9}; >> +} >> + >> +def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, >> + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), >> + IIC_VMOVImm, >> + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", >> + [(set QPR:$Vd, >> + (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { >> + let Inst{9} = SIMM{9}; >> +} >> + >> +def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, >> + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), >> + IIC_VMOVImm, >> + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", >> + [(set QPR:$Vd, >> + (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { >> + let Inst{10-9} = SIMM{10-9}; >> +} >> + >> // VORN : Vector Bitwise OR NOT >> def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), >> (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, >> >> Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Fri Nov 5 14:27:46 2010 >> @@ -525,3 +525,23 @@ >> %tmp3 = or <16 x i8> %tmp1, >> ret <16 x i8> %tmp3 >> } >> + >> +define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { >> +; CHECK: v_bicimm: >> +; CHECK-NOT: vmov >> +; CHECK-NOT vmvn >> +; CHECK: vbic >> + %tmp1 = load <8 x i8>* %A >> + %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > >> + ret <8 x i8> %tmp3 >> +} >> + >> +define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { >> +; CHECK: v_bicimmQ: >> +; CHECK-NOT: vmov >> +; CHECK-NOT: vmvn >> +; CHECK: vbic >> + %tmp1 = load <16 x i8>* %A >> + %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > >> + ret <16 x i8> %tmp3 >> +} >> >> Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) >> +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Fri Nov 5 14:27:46 2010 >> @@ -26,6 +26,10 @@ >> vbic d16, d17, d16 >> @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] >> vbic q8, q8, q9 >> +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] >> + vbic.i32 d16, #0xFF000000 >> +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] >> + vbic.i32 q8, #0xFF000000 >> >> @ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] >> vorn d16, d17, d16 >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101105/7b8a9a5e/attachment-0001.html From bob.wilson at apple.com Fri Nov 5 16:43:04 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 5 Nov 2010 14:43:04 -0700 Subject: [llvm-commits] [llvm] r118291 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s In-Reply-To: <3FA1A513-3D3F-45E0-AB92-03B8C52D6A75@mac.com> References: <20101105192747.2F8C42A6C12C@llvm.org> <3FA1A513-3D3F-45E0-AB92-03B8C52D6A75@mac.com> Message-ID: <90B1197E-2F05-4565-A3B6-A56C11067B33@apple.com> On Nov 5, 2010, at 2:39 PM, Owen Anderson wrote: > > On Nov 5, 2010, at 2:35 PM, Bob Wilson wrote: > >> This looks good. You're still going to fix isNEONModifiedImm to distinguish VBIC/VORR, right? > > I'm not sure it needs to. There seem to be only two cases: all types allowed (isVMOV == true) and only i16 and i32 allows (isVMOV == false). Are there other modified immediate instructions that have some different type combination they allow? See my comments on your previous patch: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101101/111110.html The encodings with cmode=1100 and 1101 are not supported for VORR and VBIC. > > --Owen > >> On Nov 5, 2010, at 12:27 PM, Owen Anderson wrote: >> >>> Author: resistor >>> Date: Fri Nov 5 14:27:46 2010 >>> New Revision: 118291 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=118291&view=rev >>> Log: >>> Add codegen and encoding support for the immediate form of vbic. >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp >>> llvm/trunk/lib/Target/ARM/ARMISelLowering.h >>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >>> llvm/trunk/test/CodeGen/ARM/vbits.ll >>> llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 14:27:46 2010 >>> @@ -673,8 +673,10 @@ >>> setTargetDAGCombine(ISD::SUB); >>> setTargetDAGCombine(ISD::MUL); >>> >>> - if (Subtarget->hasV6T2Ops()) >>> + if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) >>> setTargetDAGCombine(ISD::OR); >>> + if (Subtarget->hasNEON()) >>> + setTargetDAGCombine(ISD::AND); >>> >>> setStackPointerRegisterToSaveRestore(ARM::SP); >>> >>> @@ -4443,6 +4445,36 @@ >>> return SDValue(); >>> } >>> >>> +static SDValue PerformANDCombine(SDNode *N, >>> + TargetLowering::DAGCombinerInfo &DCI) { >>> + // Attempt to use immediate-form VBIC >>> + BuildVectorSDNode *BVN = dyn_cast(N->getOperand(1)); >>> + DebugLoc dl = N->getDebugLoc(); >>> + EVT VT = N->getValueType(0); >>> + SelectionDAG &DAG = DCI.DAG; >>> + >>> + APInt SplatBits, SplatUndef; >>> + unsigned SplatBitSize; >>> + bool HasAnyUndefs; >>> + if (BVN && >>> + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { >>> + if (SplatBitSize <= 64) { >>> + EVT VbicVT; >>> + SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), >>> + SplatUndef.getZExtValue(), SplatBitSize, >>> + DAG, VbicVT, VT.is128BitVector(), false); >>> + if (Val.getNode()) { >>> + SDValue Input = >>> + DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0)); >>> + SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); >>> + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic); >>> + } >>> + } >>> + } >>> + >>> + return SDValue(); >>> +} >>> + >>> /// PerformORCombine - Target-specific dag combine xforms for ISD::OR >>> static SDValue PerformORCombine(SDNode *N, >>> TargetLowering::DAGCombinerInfo &DCI, >>> @@ -5066,6 +5098,7 @@ >>> case ISD::SUB: return PerformSUBCombine(N, DCI); >>> case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); >>> case ISD::OR: return PerformORCombine(N, DCI, Subtarget); >>> + case ISD::AND: return PerformANDCombine(N, DCI); >>> case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); >>> case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); >>> case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 14:27:46 2010 >>> @@ -165,7 +165,9 @@ >>> BFI, >>> >>> // Vector OR with immediate >>> - VORRIMM >>> + VORRIMM, >>> + // Vector AND with NOT of immediate >>> + VBICIMM >>> }; >>> } >>> >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Nov 5 14:27:46 2010 >>> @@ -72,6 +72,7 @@ >>> def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, >>> SDTCisVT<2, i32>]>; >>> def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; >>> +def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; >>> >>> def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; >>> >>> @@ -3308,13 +3309,13 @@ >>> let Inst{9} = SIMM{9}; >>> } >>> >>> -def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1, >>> +def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, >>> (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), >>> IIC_VMOVImm, >>> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", >>> [(set DPR:$Vd, >>> (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { >>> - let Inst{11-9} = SIMM{11-9}; >>> + let Inst{10-9} = SIMM{10-9}; >>> } >>> >>> def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, >>> @@ -3326,13 +3327,13 @@ >>> let Inst{9} = SIMM{9}; >>> } >>> >>> -def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1, >>> +def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, >>> (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), >>> IIC_VMOVImm, >>> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", >>> [(set QPR:$Vd, >>> (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { >>> - let Inst{11-9} = SIMM{11-9}; >>> + let Inst{10-9} = SIMM{10-9}; >>> } >>> >>> >>> @@ -3348,6 +3349,42 @@ >>> [(set QPR:$dst, (v4i32 (and QPR:$src1, >>> (vnotq QPR:$src2))))]>; >>> >>> +def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, >>> + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), >>> + IIC_VMOVImm, >>> + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", >>> + [(set DPR:$Vd, >>> + (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { >>> + let Inst{9} = SIMM{9}; >>> +} >>> + >>> +def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, >>> + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), >>> + IIC_VMOVImm, >>> + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", >>> + [(set DPR:$Vd, >>> + (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { >>> + let Inst{10-9} = SIMM{10-9}; >>> +} >>> + >>> +def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, >>> + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), >>> + IIC_VMOVImm, >>> + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", >>> + [(set QPR:$Vd, >>> + (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { >>> + let Inst{9} = SIMM{9}; >>> +} >>> + >>> +def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, >>> + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), >>> + IIC_VMOVImm, >>> + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", >>> + [(set QPR:$Vd, >>> + (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { >>> + let Inst{10-9} = SIMM{10-9}; >>> +} >>> + >>> // VORN : Vector Bitwise OR NOT >>> def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), >>> (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, >>> >>> Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff >>> ============================================================================== >>> --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original) >>> +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Fri Nov 5 14:27:46 2010 >>> @@ -525,3 +525,23 @@ >>> %tmp3 = or <16 x i8> %tmp1, >>> ret <16 x i8> %tmp3 >>> } >>> + >>> +define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { >>> +; CHECK: v_bicimm: >>> +; CHECK-NOT: vmov >>> +; CHECK-NOT vmvn >>> +; CHECK: vbic >>> + %tmp1 = load <8 x i8>* %A >>> + %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > >>> + ret <8 x i8> %tmp3 >>> +} >>> + >>> +define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { >>> +; CHECK: v_bicimmQ: >>> +; CHECK-NOT: vmov >>> +; CHECK-NOT: vmvn >>> +; CHECK: vbic >>> + %tmp1 = load <16 x i8>* %A >>> + %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > >>> + ret <16 x i8> %tmp3 >>> +} >>> >>> Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff >>> ============================================================================== >>> --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) >>> +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Fri Nov 5 14:27:46 2010 >>> @@ -26,6 +26,10 @@ >>> vbic d16, d17, d16 >>> @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] >>> vbic q8, q8, q9 >>> +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] >>> + vbic.i32 d16, #0xFF000000 >>> +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] >>> + vbic.i32 q8, #0xFF000000 >>> >>> @ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] >>> vorn d16, d17, d16 >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101105/d8cf43a2/attachment.html From wdietz2 at illinois.edu Fri Nov 5 16:43:13 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Fri, 05 Nov 2010 21:43:13 -0000 Subject: [llvm-commits] [poolalloc] r118298 - /poolalloc/trunk/lib/DSA/Local.cpp Message-ID: <20101105214313.EBE7A2A6C12D@llvm.org> Author: wdietz2 Date: Fri Nov 5 16:43:13 2010 New Revision: 118298 URL: http://llvm.org/viewvc/llvm-project?rev=118298&view=rev Log: Formatting issues, minor code cleanup. No functionality changes. Modified: poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=118298&r1=118297&r2=118298&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Fri Nov 5 16:43:13 2010 @@ -560,40 +560,38 @@ int FieldNo = CUI->getSExtValue(); // increment the offset by the actual byte offset being accessed Offset += (unsigned)TD.getStructLayout(STy)->getElementOffset(FieldNo); - + if(!Value.getNode()->isArrayNode() || Value.getNode()->getSize() <= 1){ if (TD.getTypeAllocSize(STy) + Value.getOffset() > Value.getNode()->getSize()) Value.getNode()->growSize(TD.getTypeAllocSize(STy) + Value.getOffset()); } } else if(const ArrayType *ATy = dyn_cast(*I)) { - // indexing into an array. - Value.getNode()->setArrayMarker(); - const Type *CurTy = ATy->getElementType(); + // indexing into an array. + Value.getNode()->setArrayMarker(); + const Type *CurTy = ATy->getElementType(); if(!isa(CurTy) && - Value.getNode()->getSize() <= 1) { - Value.getNode()->growSize(TD.getTypeAllocSize(CurTy)); - } - if(CurTy->isVoidTy()) { + Value.getNode()->getSize() <= 1) { + Value.getNode()->growSize(TD.getTypeAllocSize(CurTy)); + } else if(CurTy->isVoidTy()) { Value.getNode()->growSize(1); - } - if(isa(CurTy) && Value.getNode()->getSize() <= 1){ + } else if(isa(CurTy) && Value.getNode()->getSize() <= 1){ const Type *ETy = (cast(CurTy))->getElementType(); while(isa(ETy)) { ETy = (cast(ETy))->getElementType(); - } + } Value.getNode()->growSize(TD.getTypeAllocSize(ETy)); if(ETy->isVoidTy()) { Value.getNode()->growSize(1); } - } -// indexing into an array. - + } + // indexing into an array. + // Find if the DSNode belongs to the array // If not fold. - if((Value.getOffset() || Offset != 0) - || (!isa(CurTy) + if((Value.getOffset() || Offset != 0) + || (!isa(CurTy) && (Value.getNode()->getSize() != TD.getTypeAllocSize(CurTy)))) { Value.getNode()->foldNodeCompletely(); @@ -612,7 +610,7 @@ // Note that we break out of the loop if we fold the node. Once // something is folded, all values within it are considered to alias. // - + if (!isa(I.getOperand()) || !cast(I.getOperand())->isNullValue()) { Value.getNode()->setArrayMarker(); @@ -620,11 +618,9 @@ if(!isa(CurTy) && Value.getNode()->getSize() <= 1){ Value.getNode()->growSize(TD.getTypeAllocSize(CurTy)); - } - if(CurTy->isVoidTy()) { + } else if(CurTy->isVoidTy()) { Value.getNode()->growSize(1); - } - if(isa(CurTy) && Value.getNode()->getSize() <= 1){ + } else if(isa(CurTy) && Value.getNode()->getSize() <= 1){ const Type *ETy = (cast(CurTy))->getElementType(); while(isa(ETy)) { ETy = (cast(ETy))->getElementType(); @@ -635,8 +631,8 @@ } } if(Value.getOffset() || Offset != 0 - || (!isa(CurTy) - && (Value.getNode()->getSize() != TD.getTypeAllocSize(CurTy)))) { + || (!isa(CurTy) + && (Value.getNode()->getSize() != TD.getTypeAllocSize(CurTy)))) { Value.getNode()->foldNodeCompletely(); Value.getNode(); Offset = 0; From resistor at mac.com Fri Nov 5 16:57:54 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 05 Nov 2010 21:57:54 -0000 Subject: [llvm-commits] [llvm] r118300 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h Message-ID: <20101105215754.A25372A6C12D@llvm.org> Author: resistor Date: Fri Nov 5 16:57:54 2010 New Revision: 118300 URL: http://llvm.org/viewvc/llvm-project?rev=118300&view=rev Log: Disallow the certain NEON modified-immediate forms when generating vorr or vbic. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118300&r1=118299&r2=118300&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 16:57:54 2010 @@ -3087,7 +3087,7 @@ /// operand (e.g., VMOV). If so, return the encoded value. static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, - EVT &VT, bool is128Bits, bool isVMOV) { + EVT &VT, bool is128Bits, NEONModImmType type) { unsigned OpCmode, Imm; // SplatBitSize is set to the smallest size that splats the vector, so a @@ -3100,7 +3100,7 @@ switch (SplatBitSize) { case 8: - if (!isVMOV) + if (type != VMOVModImm) return SDValue(); // Any 1-byte value is OK. Op=0, Cmode=1110. assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); @@ -3157,6 +3157,9 @@ break; } + // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC + if (type == OtherModImm) return SDValue(); + if ((SplatBits & ~0xffff) == 0 && ((SplatBits | SplatUndef) & 0xff) == 0xff) { // Value = 0x0000nnff: Op=x, Cmode=1100. @@ -3183,7 +3186,7 @@ return SDValue(); case 64: { - if (!isVMOV) + if (type != VMOVModImm) return SDValue(); // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. uint64_t BitMask = 0xff; @@ -3452,7 +3455,8 @@ EVT VmovVT; SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), SplatBitSize, - DAG, VmovVT, VT.is128BitVector(), true); + DAG, VmovVT, VT.is128BitVector(), + VMOVModImm); if (Val.getNode()) { SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); @@ -3463,7 +3467,8 @@ ((1LL << SplatBitSize) - 1)); Val = isNEONModifiedImm(NegatedImm, SplatUndef.getZExtValue(), SplatBitSize, - DAG, VmovVT, VT.is128BitVector(), false); + DAG, VmovVT, VT.is128BitVector(), + VMVNModImm); if (Val.getNode()) { SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); @@ -4462,7 +4467,8 @@ EVT VbicVT; SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), SplatUndef.getZExtValue(), SplatBitSize, - DAG, VbicVT, VT.is128BitVector(), false); + DAG, VbicVT, VT.is128BitVector(), + OtherModImm); if (Val.getNode()) { SDValue Input = DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0)); @@ -4494,7 +4500,8 @@ EVT VorrVT; SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), SplatBitSize, - DAG, VorrVT, VT.is128BitVector(), false); + DAG, VorrVT, VT.is128BitVector(), + OtherModImm); if (Val.getNode()) { SDValue Input = DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, N->getOperand(0)); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118300&r1=118299&r2=118300&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 16:57:54 2010 @@ -428,6 +428,13 @@ }; + enum NEONModImmType { + VMOVModImm, + VMVNModImm, + OtherModImm + }; + + namespace ARM { FastISel *createFastISel(FunctionLoweringInfo &funcInfo); } From grosbach at apple.com Fri Nov 5 17:08:08 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 22:08:08 -0000 Subject: [llvm-commits] [llvm] r118301 - in /llvm/trunk: include/llvm/MC/MCDirectives.h include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCLoggingStreamer.cpp lib/MC/MCMachOStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/WinCOFFStreamer.cpp lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101105220808.923D62A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 17:08:08 2010 New Revision: 118301 URL: http://llvm.org/viewvc/llvm-project?rev=118301&view=rev Log: MC'ize the '.code 16' and '.thumb_func' ARM directives. Modified: llvm/trunk/include/llvm/MC/MCDirectives.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCLoggingStreamer.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCNullStreamer.cpp llvm/trunk/lib/MC/WinCOFFStreamer.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/include/llvm/MC/MCDirectives.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDirectives.h?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDirectives.h (original) +++ llvm/trunk/include/llvm/MC/MCDirectives.h Fri Nov 5 17:08:08 2010 @@ -44,7 +44,8 @@ enum MCAssemblerFlag { MCAF_SyntaxUnified, ///< .syntax (ARM/ELF) - MCAF_SubsectionsViaSymbols ///< .subsections_via_symbols (MachO) + MCAF_SubsectionsViaSymbols, ///< .subsections_via_symbols (MachO) + MCAF_Code16 ///< .code 16 }; } // end namespace llvm Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Fri Nov 5 17:08:08 2010 @@ -126,6 +126,10 @@ /// EmitAssemblerFlag - Note in the output the specified @p Flag virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) = 0; + /// EmitThumbFunc - Note in the output that the specified @p Func is + /// a Thumb mode function (ARM target only). + virtual void EmitThumbFunc(MCSymbol *Func) = 0; + /// EmitAssignment - Emit an assignment of @p Value to @p Symbol. /// /// This corresponds to an assembler statement such as: Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Fri Nov 5 17:08:08 2010 @@ -111,6 +111,7 @@ virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); + virtual void EmitThumbFunc(MCSymbol *Func); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); @@ -253,10 +254,20 @@ default: assert(0 && "Invalid flag!"); case MCAF_SyntaxUnified: OS << "\t.syntax unified"; break; case MCAF_SubsectionsViaSymbols: OS << ".subsections_via_symbols"; break; + case MCAF_Code16: OS << "\t.code\t16"; break; } EmitEOL(); } +void MCAsmStreamer::EmitThumbFunc(MCSymbol *Func) { + // This needs to emit to a temporary string to get properly quoted + // MCSymbols when they have spaces in them. + OS << "\t.thumb_func"; + if (Func) + OS << '\t' << *Func; + EmitEOL(); +} + void MCAsmStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { OS << *Symbol << " = " << *Value; EmitEOL(); Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Fri Nov 5 17:08:08 2010 @@ -49,6 +49,7 @@ virtual void InitSections(); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); + virtual void EmitThumbFunc(MCSymbol *Func); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol); virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute); @@ -178,7 +179,8 @@ void MCELFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { switch (Flag) { - case MCAF_SyntaxUnified: return; // no-op here? + case MCAF_SyntaxUnified: return; // no-op here. + case MCAF_Code16: return; // no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; @@ -187,6 +189,10 @@ assert(0 && "invalid assembler flag!"); } +void MCELFStreamer::EmitThumbFunc(MCSymbol *Func) { + // FIXME: Anything needed here to flag the function as thumb? +} + void MCELFStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into // MCObjectStreamer. Modified: llvm/trunk/lib/MC/MCLoggingStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLoggingStreamer.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCLoggingStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCLoggingStreamer.cpp Fri Nov 5 17:08:08 2010 @@ -69,6 +69,11 @@ return Child->EmitAssemblerFlag(Flag); } + virtual void EmitThumbFunc(MCSymbol *Func) { + LogCall("EmitThumbFunc"); + return Child->EmitThumbFunc(Func); + } + virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { LogCall("EmitAssignment"); return Child->EmitAssignment(Symbol, Value); Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Fri Nov 5 17:08:08 2010 @@ -45,6 +45,7 @@ virtual void InitSections(); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); + virtual void EmitThumbFunc(MCSymbol *Func); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute); virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue); @@ -149,7 +150,8 @@ void MCMachOStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { switch (Flag) { - case MCAF_SyntaxUnified: return; // no-op here. + case MCAF_SyntaxUnified: return; // no-op here. + case MCAF_Code16: return; // no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; @@ -158,6 +160,10 @@ } } +void MCMachOStreamer::EmitThumbFunc(MCSymbol *Func) { + // FIXME: Flag the function ISA as thumb with DW_AT_APPLE_isa. +} + void MCMachOStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into // MCObjectStreamer. Modified: llvm/trunk/lib/MC/MCNullStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCNullStreamer.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCNullStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCNullStreamer.cpp Fri Nov 5 17:08:08 2010 @@ -40,6 +40,7 @@ } virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) {} + virtual void EmitThumbFunc(MCSymbol *Func) {} virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {} virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol){} Modified: llvm/trunk/lib/MC/WinCOFFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFStreamer.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFStreamer.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFStreamer.cpp Fri Nov 5 17:08:08 2010 @@ -51,6 +51,7 @@ virtual void InitSections(); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); + virtual void EmitThumbFunc(MCSymbol *Func); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute); virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue); @@ -202,6 +203,10 @@ llvm_unreachable("not implemented"); } +void WinCOFFStreamer::EmitThumbFunc(MCSymbol *Func) { + llvm_unreachable("not implemented"); +} + void WinCOFFStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { assert((Symbol->isInSection() ? Symbol->getSection().getVariant() == MCSection::SV_COFF Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118301&r1=118300&r2=118301&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Nov 5 17:08:08 2010 @@ -299,17 +299,8 @@ void ARMAsmPrinter::EmitFunctionEntryLabel() { if (AFI->isThumbFunction()) { - OutStreamer.EmitRawText(StringRef("\t.code\t16")); - if (!Subtarget->isTargetDarwin()) - OutStreamer.EmitRawText(StringRef("\t.thumb_func")); - else { - // This needs to emit to a temporary string to get properly quoted - // MCSymbols when they have spaces in them. - SmallString<128> Tmp; - raw_svector_ostream OS(Tmp); - OS << "\t.thumb_func\t" << *CurrentFnSym; - OutStreamer.EmitRawText(OS.str()); - } + OutStreamer.EmitAssemblerFlag(MCAF_Code16); + OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0); } OutStreamer.EmitLabel(CurrentFnSym); From grosbach at apple.com Fri Nov 5 17:11:33 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 22:11:33 -0000 Subject: [llvm-commits] [llvm] r118304 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101105221133.3D9C92A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 17:11:33 2010 New Revision: 118304 URL: http://llvm.org/viewvc/llvm-project?rev=118304&view=rev Log: Fix past-o. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118304&r1=118303&r2=118304&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Nov 5 17:11:33 2010 @@ -903,7 +903,7 @@ bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) { const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) - return Error(L, "unexpected token in .syntax directive"); + return Error(L, "unexpected token in .thumb_func directive"); Parser.Lex(); // Consume the identifier token. if (getLexer().isNot(AsmToken::EndOfStatement)) From grosbach at apple.com Fri Nov 5 17:33:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 22:33:53 -0000 Subject: [llvm-commits] [llvm] r118307 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101105223353.E6BDD2A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 17:33:53 2010 New Revision: 118307 URL: http://llvm.org/viewvc/llvm-project?rev=118307&view=rev Log: Hook up the '.thumb_func' directive to the streamer. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118307&r1=118306&r2=118307&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Nov 5 17:33:53 2010 @@ -13,6 +13,7 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -904,14 +905,15 @@ const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) return Error(L, "unexpected token in .thumb_func directive"); + StringRef Name = Tok.getString(); Parser.Lex(); // Consume the identifier token. - if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(L, "unexpected token in directive"); Parser.Lex(); - // TODO: mark symbol as a thumb symbol - // getParser().getStreamer().Emit???(); + // Mark symbol as a thumb symbol. + MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); + getParser().getStreamer().EmitThumbFunc(Func); return false; } From grosbach at apple.com Fri Nov 5 17:40:09 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 22:40:09 -0000 Subject: [llvm-commits] [llvm] r118309 - in /llvm/trunk: include/llvm/MC/MCDirectives.h lib/MC/MCAsmStreamer.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCMachOStreamer.cpp Message-ID: <20101105224009.DF1F12A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 17:40:09 2010 New Revision: 118309 URL: http://llvm.org/viewvc/llvm-project?rev=118309&view=rev Log: Add '.code 32' assembler directive to MC streamers. Modified: llvm/trunk/include/llvm/MC/MCDirectives.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCDirectives.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDirectives.h?rev=118309&r1=118308&r2=118309&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDirectives.h (original) +++ llvm/trunk/include/llvm/MC/MCDirectives.h Fri Nov 5 17:40:09 2010 @@ -45,7 +45,8 @@ enum MCAssemblerFlag { MCAF_SyntaxUnified, ///< .syntax (ARM/ELF) MCAF_SubsectionsViaSymbols, ///< .subsections_via_symbols (MachO) - MCAF_Code16 ///< .code 16 + MCAF_Code16, ///< .code 16 + MCAF_Code32 ///< .code 32 }; } // end namespace llvm Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=118309&r1=118308&r2=118309&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Fri Nov 5 17:40:09 2010 @@ -255,6 +255,7 @@ case MCAF_SyntaxUnified: OS << "\t.syntax unified"; break; case MCAF_SubsectionsViaSymbols: OS << ".subsections_via_symbols"; break; case MCAF_Code16: OS << "\t.code\t16"; break; + case MCAF_Code32: OS << "\t.code\t32"; break; } EmitEOL(); } Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=118309&r1=118308&r2=118309&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Fri Nov 5 17:40:09 2010 @@ -181,6 +181,7 @@ switch (Flag) { case MCAF_SyntaxUnified: return; // no-op here. case MCAF_Code16: return; // no-op here. + case MCAF_Code32: return; // no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=118309&r1=118308&r2=118309&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Fri Nov 5 17:40:09 2010 @@ -152,6 +152,7 @@ switch (Flag) { case MCAF_SyntaxUnified: return; // no-op here. case MCAF_Code16: return; // no-op here. + case MCAF_Code32: return; // no-op here. case MCAF_SubsectionsViaSymbols: getAssembler().setSubsectionsViaSymbols(true); return; From grosbach at apple.com Fri Nov 5 17:40:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 05 Nov 2010 22:40:53 -0000 Subject: [llvm-commits] [llvm] r118310 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101105224053.EE67B2A6C12D@llvm.org> Author: grosbach Date: Fri Nov 5 17:40:53 2010 New Revision: 118310 URL: http://llvm.org/viewvc/llvm-project?rev=118310&view=rev Log: Hook up the '.code {16|32}' directive to the streamer. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118310&r1=118309&r2=118310&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Nov 5 17:40:53 2010 @@ -958,8 +958,11 @@ return Error(Parser.getTok().getLoc(), "unexpected token in directive"); Parser.Lex(); - // TODO tell the MC streamer the mode - // getParser().getStreamer().Emit???(); + if (Val == 16) + getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); + else + getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); + return false; } From daniel at zuster.org Fri Nov 5 18:14:29 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 05 Nov 2010 23:14:29 -0000 Subject: [llvm-commits] [zorg] r118311 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20101105231429.8E4FC2A6C12D@llvm.org> Author: ddunbar Date: Fri Nov 5 18:14:29 2010 New Revision: 118311 URL: http://llvm.org/viewvc/llvm-project?rev=118311&view=rev Log: Downgrade llvm-gcc-i686-pc-linux-gnu-cross-gnueabi to experimental, to disable spurious failure notifications. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=118311&r1=118310&r2=118311&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Nov 5 18:14:29 2010 @@ -564,7 +564,7 @@ {'name' : 'install_llvmgcc', 'description' : 'install llvm-gcc', 'haltOnFailure' : True },]), - 'category' : 'llvm-gcc' }, + 'category' : 'llvm-gcc.exp' }, {'name' : "clang-i686-linux-selfhost-rel", 'slavenames' : ["osu8"], From clattner at apple.com Sat Nov 6 01:18:32 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 5 Nov 2010 23:18:32 -0700 Subject: [llvm-commits] PATCH: Fix PR8528 In-Reply-To: References: Message-ID: <0E166CE5-A645-4C3B-A09D-8D5151396737@apple.com> On Nov 3, 2010, at 3:54 PM, ?smail D?nmez wrote: > Hi; > > Original patch by pdox on #llvm . Asm parser was not handling fist and fistp instructions correctly. Please apply. Hi Ismail, This is great detective work! Just to verify my understanding, the issue is that GAS is treating: fistp (%rax) as an alias for: fistps (%rax) and we're compiling it to: fistpl (%rax) If this is the case, I think that the MC assembler should be changed to *reject* fisp, not to emulate GAS's behavior. With a simple mem operand, there is nothing to say that "4 bytes" is the right size of the store, it should be diagnosed as an ambiguous instruction. Reporting it as a bug in the code is much more friendly than miscompiling it of course. :) What do you think? -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101105/d52b55bb/attachment.html From sabre at nondot.org Sat Nov 6 01:39:48 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 06:39:48 -0000 Subject: [llvm-commits] [llvm] r118324 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp CodeGenInstruction.cpp CodeGenInstruction.h Message-ID: <20101106063948.1EE792A6C133@llvm.org> Author: lattner Date: Sat Nov 6 01:39:47 2010 New Revision: 118324 URL: http://llvm.org/viewvc/llvm-project?rev=118324&view=rev Log: disolve a hack, having CodeGenInstAlias decode the alias in the .td file instead of the asmmatcher. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118324&r1=118323&r2=118324&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 01:39:47 2010 @@ -355,12 +355,8 @@ MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), DefRec(Alias), TheOperandList(Alias->Operands), AsmString(Alias->AsmString) { - - // FIXME: Huge hack. - DefInit *DI = dynamic_cast(Alias->Result->getOperator()); - assert(DI); - - InstrName = DI->getDef()->getName(); + // FIXME: InstrName should be a CGI. + InstrName = Alias->ResultInst->TheDef->getName(); } void Initialize(const AsmMatcherInfo &Info, @@ -1066,7 +1062,7 @@ std::vector AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { - CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]); + CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target); OwningPtr II(new MatchableInfo(Alias)); @@ -1117,11 +1113,9 @@ OperandName = Token.substr(1); if (II->DefRec.is()) - BuildInstructionOperandReference(II, - OperandName, Op); + BuildInstructionOperandReference(II, OperandName, Op); else - BuildAliasOperandReference(II, - OperandName, Op); + BuildAliasOperandReference(II, OperandName, Op); } II->BuildResultOperands(); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118324&r1=118323&r2=118324&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 01:39:47 2010 @@ -388,8 +388,16 @@ /// CodeGenInstAlias Implementation //===----------------------------------------------------------------------===// -CodeGenInstAlias::CodeGenInstAlias(Record *R) : TheDef(R), Operands(R) { +CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) + : TheDef(R), Operands(R) { AsmString = R->getValueAsString("AsmString"); Result = R->getValueAsDag("ResultInst"); + + // Verify that the root of the result is an instruction. + DefInit *DI = dynamic_cast(Result->getOperator()); + if (DI == 0 || !DI->getDef()->isSubClassOf("Instruction")) + throw TGError(R->getLoc(), "result of inst alias should be an instruction"); + + ResultInst = &T.getInstruction(DI->getDef()); } Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=118324&r1=118323&r2=118324&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sat Nov 6 01:39:47 2010 @@ -15,6 +15,7 @@ #define CODEGEN_INSTRUCTION_H #include "llvm/CodeGen/ValueTypes.h" +#include "llvm/ADT/StringRef.h" #include #include #include @@ -264,7 +265,22 @@ /// Result - The result instruction. DagInit *Result; - CodeGenInstAlias(Record *R); + /// ResultInst - The instruction generated by the alias (decoded from + /// Result). + CodeGenInstruction *ResultInst; + + + struct ResultOperand { + StringRef Name; + Record *R; + + ResultOperand(StringRef N, Record *r) : Name(N), R(r) {} + }; + + /// ResultOperands - The decoded operands for the result instruction. + std::vector ResultOperands; + + CodeGenInstAlias(Record *R, CodeGenTarget &T); }; } From sabre at nondot.org Sat Nov 6 01:43:11 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 06:43:11 -0000 Subject: [llvm-commits] [llvm] r118325 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101106064311.8EDFA2A6C133@llvm.org> Author: lattner Date: Sat Nov 6 01:43:11 2010 New Revision: 118325 URL: http://llvm.org/viewvc/llvm-project?rev=118325&view=rev Log: fix another fixme, replacing a string with a semantic pointer. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118325&r1=118324&r2=118325&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 01:43:11 2010 @@ -306,8 +306,8 @@ } }; - /// InstrName - The target name for this instruction. - std::string InstrName; + /// ResultInst - The result instruction generated. + const CodeGenInstruction *ResultInst; /// TheDef - This is the definition of the instruction or InstAlias that this /// matchable came from. @@ -349,14 +349,13 @@ MatchableInfo(const CodeGenInstruction &CGI) : TheDef(CGI.TheDef), DefRec(&CGI), TheOperandList(CGI.Operands), AsmString(CGI.AsmString) { - InstrName = TheDef->getName(); + ResultInst = &CGI; } MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), DefRec(Alias), TheOperandList(Alias->Operands), AsmString(Alias->AsmString) { - // FIXME: InstrName should be a CGI. - InstrName = Alias->ResultInst->TheDef->getName(); + ResultInst = Alias->ResultInst; } void Initialize(const AsmMatcherInfo &Info, @@ -537,7 +536,7 @@ } void MatchableInfo::dump() { - errs() << InstrName << " -- " << "flattened:\"" << AsmString << "\"\n"; + errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"; for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { AsmOperand &Op = AsmOperands[i]; @@ -708,7 +707,7 @@ // FIXME: Should reject these. The ARM backend hits this with $lane in a // bunch of instructions. It is unclear what the right answer is. DEBUG({ - errs() << "warning: '" << InstrName << "': " + errs() << "warning: '" << TheDef->getName() << "': " << "ignoring instruction with tied operand '" << Tok.str() << "'\n"; }); @@ -1050,8 +1049,8 @@ // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. // // FIXME: This is a total hack. - if (StringRef(II->InstrName).startswith("Int_") || - StringRef(II->InstrName).endswith("_Int")) + if (StringRef(II->TheDef->getName()).startswith("Int_") || + StringRef(II->TheDef->getName()).endswith("_Int")) continue; Matchables.push_back(II.take()); @@ -1822,7 +1821,7 @@ it != ie; ++it) { MatchableInfo &II = **it; - OS << " { " << Target.getName() << "::" << II.InstrName + OS << " { " << Target.getName() << "::" << II.ResultInst->TheDef->getName() << ", \"" << II.Mnemonic << "\"" << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { From sabre at nondot.org Sat Nov 6 01:45:08 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 06:45:08 -0000 Subject: [llvm-commits] [llvm] r118326 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101106064508.C6B582A6C133@llvm.org> Author: lattner Date: Sat Nov 6 01:45:08 2010 New Revision: 118326 URL: http://llvm.org/viewvc/llvm-project?rev=118326&view=rev Log: simplify Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118326&r1=118325&r2=118326&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 01:45:08 2010 @@ -306,9 +306,6 @@ } }; - /// ResultInst - The result instruction generated. - const CodeGenInstruction *ResultInst; - /// TheDef - This is the definition of the instruction or InstAlias that this /// matchable came from. Record *const TheDef; @@ -349,13 +346,11 @@ MatchableInfo(const CodeGenInstruction &CGI) : TheDef(CGI.TheDef), DefRec(&CGI), TheOperandList(CGI.Operands), AsmString(CGI.AsmString) { - ResultInst = &CGI; } MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), DefRec(Alias), TheOperandList(Alias->Operands), AsmString(Alias->AsmString) { - ResultInst = Alias->ResultInst; } void Initialize(const AsmMatcherInfo &Info, @@ -1821,7 +1816,14 @@ it != ie; ++it) { MatchableInfo &II = **it; - OS << " { " << Target.getName() << "::" << II.ResultInst->TheDef->getName() + + const CodeGenInstruction *ResultInst; + if (II.DefRec.is()) + ResultInst = II.DefRec.get(); + else + ResultInst = II.DefRec.get()->ResultInst; + + OS << " { " << Target.getName() << "::" << ResultInst->TheDef->getName() << ", \"" << II.Mnemonic << "\"" << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { From sabre at nondot.org Sat Nov 6 01:54:39 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 06:54:39 -0000 Subject: [llvm-commits] [llvm] r118327 - /llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Message-ID: <20101106065439.1A5BF2A6C133@llvm.org> Author: lattner Date: Sat Nov 6 01:54:38 2010 New Revision: 118327 URL: http://llvm.org/viewvc/llvm-project?rev=118327&view=rev Log: decode and validate instruction alias result definitions. Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118327&r1=118326&r2=118327&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 01:54:38 2010 @@ -400,4 +400,37 @@ throw TGError(R->getLoc(), "result of inst alias should be an instruction"); ResultInst = &T.getInstruction(DI->getDef()); + + // Check number of arguments in the result. + if (ResultInst->Operands.size() != Result->getNumArgs()) + throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) + + " arguments, but " + ResultInst->TheDef->getName() + + " instruction expects " + utostr(ResultInst->Operands.size())+ + " operands!"); + + // Decode and validate the arguments of the result. + for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) { + Init *Arg = Result->getArg(i); + + // If the operand is a record, it must have a name, and the record type must + // match up with the instruction's argument type. + if (DefInit *ADI = dynamic_cast(Arg)) { + if (Result->getArgName(i).empty()) + throw TGError(R->getLoc(), "result argument #" + utostr(i) + + " must have a name!"); + + if (ADI->getDef() != ResultInst->Operands[i].Rec) + throw TGError(R->getLoc(), "result argument #" + utostr(i) + + " declared with class " + ADI->getDef()->getName() + + ", instruction operand is class " + + ResultInst->Operands[i].Rec->getName()); + + // Now that it is validated, add it. + ResultOperands.push_back(ResultOperand(Result->getArgName(i), + ADI->getDef())); + continue; + } + + throw TGError(R->getLoc(), "result of inst alias has unknown operand type"); + } } From sabre at nondot.org Sat Nov 6 02:06:09 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 07:06:09 -0000 Subject: [llvm-commits] [llvm] r118328 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp CodeGenInstruction.cpp Message-ID: <20101106070609.4221D2A6C133@llvm.org> Author: lattner Date: Sat Nov 6 02:06:09 2010 New Revision: 118328 URL: http://llvm.org/viewvc/llvm-project?rev=118328&view=rev Log: implement more checking to reject things like: (someinst GR16:$foo, GR32:$foo) Reimplement BuildAliasOperandReference to be correctly based on the names of operands in the result pattern, instead of on the instruction operand definitions. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118328&r1=118327&r2=118328&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 02:06:09 2010 @@ -1160,47 +1160,24 @@ Op.SrcOpName = OperandName; } +/// BuildAliasOperandReference - When parsing an operand reference out of the +/// matching string (e.g. "movsx $src, $dst"), determine what the class of the +/// operand reference is by looking it up in the result pattern definition. void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, StringRef OperandName, MatchableInfo::AsmOperand &Op) { const CodeGenInstAlias &CGA = *II->DefRec.get(); - - // FIXME: This is a total hack, it should not be a copy of - // BuildInstructionOperandReference - - const CGIOperandList &Operands = CGA.Operands; - - // Map this token to an operand. FIXME: Move elsewhere. - unsigned Idx; - if (!Operands.hasOperandNamed(OperandName, Idx)) - throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + - OperandName.str() + "'"); - // Set up the operand class. - Op.Class = getOperandClass(Operands[Idx]); - - // If the named operand is tied, canonicalize it to the untied operand. - // For example, something like: - // (outs GPR:$dst), (ins GPR:$src) - // with an asmstring of - // "inc $src" - // we want to canonicalize to: - // "inc $dst" - // so that we know how to provide the $dst operand when filling in the result. - int OITied = Operands[Idx].getTiedRegister(); - if (OITied != -1) { - // The tied operand index is an MIOperand index, find the operand that - // contains it. - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].MIOperandNo == unsigned(OITied)) { - OperandName = Operands[i].Name; - break; - } + for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) + if (CGA.ResultOperands[i].Name == OperandName) { + Op.Class = getOperandClass(CGA.ResultInst->Operands[i]); + Op.SrcOpName = OperandName; + return; } - } - - Op.SrcOpName = OperandName; + + throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + + OperandName.str() + "'"); } void MatchableInfo::BuildResultOperands() { Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118328&r1=118327&r2=118328&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 02:06:09 2010 @@ -15,6 +15,7 @@ #include "CodeGenTarget.h" #include "Record.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringMap.h" #include "llvm/ADT/STLExtras.h" #include using namespace llvm; @@ -407,6 +408,10 @@ " arguments, but " + ResultInst->TheDef->getName() + " instruction expects " + utostr(ResultInst->Operands.size())+ " operands!"); + + // NameClass - If argument names are repeated, we need to verify they have + // the same class. + StringMap NameClass; // Decode and validate the arguments of the result. for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) { @@ -425,6 +430,15 @@ ", instruction operand is class " + ResultInst->Operands[i].Rec->getName()); + // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo) + // $foo can exist multiple times in the result list, but it must have the + // same type. + Record *&Entry = NameClass[Result->getArgName(i)]; + if (Entry && Entry != ADI->getDef()) + throw TGError(R->getLoc(), "result value $" + Result->getArgName(i) + + " is both " + Entry->getName() + " and " + + ADI->getDef()->getName() + "!"); + // Now that it is validated, add it. ResultOperands.push_back(ResultOperand(Result->getArgName(i), ADI->getDef())); From sabre at nondot.org Sat Nov 6 02:14:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 07:14:44 -0000 Subject: [llvm-commits] [llvm] r118329 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/X86/X86InstrInfo.td utils/TableGen/AsmMatcherEmitter.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h Message-ID: <20101106071444.DCC3A2A6C133@llvm.org> Author: lattner Date: Sat Nov 6 02:14:44 2010 New Revision: 118329 URL: http://llvm.org/viewvc/llvm-project?rev=118329&view=rev Log: Reimplement BuildResultOperands to be in terms of the result instruction's operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=118329&r1=118328&r2=118329&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Sat Nov 6 02:14:44 2010 @@ -570,9 +570,7 @@ /// InstAlias - This defines an alternate assembly syntax that is allowed to /// match an instruction that has a different (more canonical) assembly /// representation. -class InstAlias { - dag OutOperandList = Outs; // An dag containing the MI def operand list. - dag InOperandList = Ins; // An dag containing the MI use operand list. +class InstAlias { string AsmString = Asm; // The .s format to match the instruction with. dag ResultInst = Result; // The MCInst to generate. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118329&r1=118328&r2=118329&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 02:14:44 2010 @@ -1371,50 +1371,37 @@ //===----------------------------------------------------------------------===// // movsx aliases -def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; -def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>; -def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>; -def : InstAlias<(outs GR32:$dst), (ins GR16:$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR16:$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR32:$src), - "movsx $src, $dst", +def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>; // movzx aliases -def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), - "movzx $src, $dst", +def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>; -def : InstAlias<(outs GR16:$dst), (ins i8mem:$src), - "movzx $src, $dst", +def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>; -def : InstAlias<(outs GR32:$dst), (ins GR8 :$src), - "movzx $src, $dst", +def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>; -def : InstAlias<(outs GR32:$dst), (ins GR16:$src), - "movzx $src, $dst", +def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR8 :$src), - "movzx $src, $dst", +def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>; -def : InstAlias<(outs GR64:$dst), (ins GR16:$src), - "movzx $src, $dst", +def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; // Note: No GR32->GR64 movzx form. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118329&r1=118328&r2=118329&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 02:14:44 2010 @@ -313,9 +313,11 @@ /// DefRec - This is the definition that it came from. PointerUnion DefRec; - // FIXME: REMOVE. - const CGIOperandList &TheOperandList; - + const CodeGenInstruction *getResultInst() const { + if (DefRec.is()) + return DefRec.get(); + return DefRec.get()->ResultInst; + } /// ResOperands - This is the operand list that should be built for the result /// MCInst. @@ -344,13 +346,11 @@ std::string ConversionFnKind; MatchableInfo(const CodeGenInstruction &CGI) - : TheDef(CGI.TheDef), DefRec(&CGI), - TheOperandList(CGI.Operands), AsmString(CGI.AsmString) { + : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) { } MatchableInfo(const CodeGenInstAlias *Alias) - : TheDef(Alias->TheDef), DefRec(Alias), TheOperandList(Alias->Operands), - AsmString(Alias->AsmString) { + : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) { } void Initialize(const AsmMatcherInfo &Info, @@ -1128,7 +1128,7 @@ const CodeGenInstruction &CGI = *II->DefRec.get(); const CGIOperandList &Operands = CGI.Operands; - // Map this token to an operand. FIXME: Move elsewhere. + // Map this token to an operand. unsigned Idx; if (!Operands.hasOperandNamed(OperandName, Idx)) throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + @@ -1171,6 +1171,8 @@ // Set up the operand class. for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) if (CGA.ResultOperands[i].Name == OperandName) { + // It's safe to go with the first one we find, because CodeGenInstAlias + // validates that all operands with the same name have the same record. Op.Class = getOperandClass(CGA.ResultInst->Operands[i]); Op.SrcOpName = OperandName; return; @@ -1181,8 +1183,12 @@ } void MatchableInfo::BuildResultOperands() { - for (unsigned i = 0, e = TheOperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OpInfo = TheOperandList[i]; + const CodeGenInstruction *ResultInst = getResultInst(); + + // Loop over all operands of the result instruction, determining how to + // populate them. + for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; // If this is a tied operand, just copy from the previously handled operand. int TiedOp = OpInfo.getTiedRegister(); @@ -1794,15 +1800,9 @@ MatchableInfo &II = **it; - const CodeGenInstruction *ResultInst; - if (II.DefRec.is()) - ResultInst = II.DefRec.get(); - else - ResultInst = II.DefRec.get()->ResultInst; - - OS << " { " << Target.getName() << "::" << ResultInst->TheDef->getName() - << ", \"" << II.Mnemonic << "\"" - << ", " << II.ConversionFnKind << ", { "; + OS << " { " << Target.getName() << "::" + << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\"" + << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118329&r1=118328&r2=118329&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 02:14:44 2010 @@ -389,10 +389,8 @@ /// CodeGenInstAlias Implementation //===----------------------------------------------------------------------===// -CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) - : TheDef(R), Operands(R) { +CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) { AsmString = R->getValueAsString("AsmString"); - Result = R->getValueAsDag("ResultInst"); // Verify that the root of the result is an instruction. Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=118329&r1=118328&r2=118329&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sat Nov 6 02:14:44 2010 @@ -258,10 +258,6 @@ /// instruction. std::string AsmString; - /// Operands - This is information about the (ins) and (outs) list specified - /// to the alias. - CGIOperandList Operands; - /// Result - The result instruction. DagInit *Result; From sabre at nondot.org Sat Nov 6 02:31:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 07:31:43 -0000 Subject: [llvm-commits] [llvm] r118330 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td utils/TableGen/AsmMatcherEmitter.cpp utils/TableGen/CodeGenInstruction.cpp Message-ID: <20101106073143.51ECB2A6C134@llvm.org> Author: lattner Date: Sat Nov 6 02:31:43 2010 New Revision: 118330 URL: http://llvm.org/viewvc/llvm-project?rev=118330&view=rev Log: fix some bugs in the alias support, unblocking changing of "clr" aliases from c++ hacks to proper .td InstAlias definitions. Change them! Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118330&r1=118329&r2=118330&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 02:31:43 2010 @@ -983,17 +983,6 @@ Operands[0] = X86Operand::CreateToken("fstps", NameLoc); } - - // "clr " -> "xor , ". - if ((Name == "clrb" || Name == "clrw" || Name == "clrl" || Name == "clrq" || - Name == "clr") && Operands.size() == 2 && - static_cast(Operands[1])->isReg()) { - unsigned RegNo = static_cast(Operands[1])->getReg(); - Operands.push_back(X86Operand::CreateReg(RegNo, NameLoc, NameLoc)); - delete Operands[0]; - Operands[0] = X86Operand::CreateToken("xor", NameLoc); - } - // FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA". if ((Name.startswith("aad") || Name.startswith("aam")) && Operands.size() == 1) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118330&r1=118329&r2=118330&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 02:31:43 2010 @@ -1370,6 +1370,12 @@ // Assembler Instruction Aliases //===----------------------------------------------------------------------===// +// clr aliases. +def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; +def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; +def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; +def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; + // movsx aliases def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118330&r1=118329&r2=118330&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 02:31:43 2010 @@ -372,7 +372,8 @@ return -1; } - void BuildResultOperands(); + void BuildInstructionResultOperands(); + void BuildAliasResultOperands(); /// operator< - Compare two matchables. bool operator<(const MatchableInfo &RHS) const { @@ -1112,7 +1113,10 @@ BuildAliasOperandReference(II, OperandName, Op); } - II->BuildResultOperands(); + if (II->DefRec.is()) + II->BuildInstructionResultOperands(); + else + II->BuildAliasResultOperands(); } // Reorder classes so that classes preceed super classes. @@ -1182,7 +1186,7 @@ OperandName.str() + "'"); } -void MatchableInfo::BuildResultOperands() { +void MatchableInfo::BuildInstructionResultOperands() { const CodeGenInstruction *ResultInst = getResultInst(); // Loop over all operands of the result instruction, determining how to @@ -1212,6 +1216,36 @@ } } +void MatchableInfo::BuildAliasResultOperands() { + const CodeGenInstAlias &CGA = *DefRec.get(); + const CodeGenInstruction *ResultInst = getResultInst(); + + // Loop over all operands of the result instruction, determining how to + // populate them. + unsigned AliasOpNo = 0; + for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; + + // If this is a tied operand, just copy from the previously handled operand. + int TiedOp = OpInfo.getTiedRegister(); + if (TiedOp != -1) { + ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); + continue; + } + + // Find out what operand from the asmparser that this MCInst operand comes + // from. + int SrcOperand = FindAsmOperandNamed(CGA.ResultOperands[AliasOpNo++].Name); + if (SrcOperand != -1) { + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); + continue; + } + + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); + } +} static void EmitConvertToMCInst(CodeGenTarget &Target, std::vector &Infos, Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118330&r1=118329&r2=118330&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 02:31:43 2010 @@ -400,30 +400,35 @@ ResultInst = &T.getInstruction(DI->getDef()); - // Check number of arguments in the result. - if (ResultInst->Operands.size() != Result->getNumArgs()) - throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) + - " arguments, but " + ResultInst->TheDef->getName() + - " instruction expects " + utostr(ResultInst->Operands.size())+ - " operands!"); - // NameClass - If argument names are repeated, we need to verify they have // the same class. StringMap NameClass; // Decode and validate the arguments of the result. - for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) { - Init *Arg = Result->getArg(i); + unsigned AliasOpNo = 0; + for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { + // Tied registers don't have an entry in the result dag. + if (ResultInst->Operands[i].getTiedRegister() != -1) + continue; + + if (AliasOpNo >= Result->getNumArgs()) + throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) + + " arguments, but " + ResultInst->TheDef->getName() + + " instruction expects " + + utostr(ResultInst->Operands.size()) + " operands!"); + + + Init *Arg = Result->getArg(AliasOpNo); // If the operand is a record, it must have a name, and the record type must // match up with the instruction's argument type. if (DefInit *ADI = dynamic_cast(Arg)) { - if (Result->getArgName(i).empty()) - throw TGError(R->getLoc(), "result argument #" + utostr(i) + + if (Result->getArgName(AliasOpNo).empty()) + throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) + " must have a name!"); if (ADI->getDef() != ResultInst->Operands[i].Rec) - throw TGError(R->getLoc(), "result argument #" + utostr(i) + + throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) + " declared with class " + ADI->getDef()->getName() + ", instruction operand is class " + ResultInst->Operands[i].Rec->getName()); @@ -431,18 +436,26 @@ // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo) // $foo can exist multiple times in the result list, but it must have the // same type. - Record *&Entry = NameClass[Result->getArgName(i)]; + Record *&Entry = NameClass[Result->getArgName(AliasOpNo)]; if (Entry && Entry != ADI->getDef()) - throw TGError(R->getLoc(), "result value $" + Result->getArgName(i) + + throw TGError(R->getLoc(), "result value $" + + Result->getArgName(AliasOpNo) + " is both " + Entry->getName() + " and " + ADI->getDef()->getName() + "!"); // Now that it is validated, add it. - ResultOperands.push_back(ResultOperand(Result->getArgName(i), + ResultOperands.push_back(ResultOperand(Result->getArgName(AliasOpNo), ADI->getDef())); + ++AliasOpNo; continue; } throw TGError(R->getLoc(), "result of inst alias has unknown operand type"); } + + if (AliasOpNo != Result->getNumArgs()) + throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) + + " arguments, but " + ResultInst->TheDef->getName() + + " instruction expects " + utostr(ResultInst->Operands.size())+ + " operands!"); } From sabre at nondot.org Sat Nov 6 02:34:58 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 07:34:58 -0000 Subject: [llvm-commits] [llvm] r118331 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106073458.EA4482A6C134@llvm.org> Author: lattner Date: Sat Nov 6 02:34:58 2010 New Revision: 118331 URL: http://llvm.org/viewvc/llvm-project?rev=118331&view=rev Log: move the "movsd -> movsl" alias to the .td files, tidy up the movsx and movzx aliases. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118331&r1=118330&r2=118331&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 02:34:58 2010 @@ -969,12 +969,6 @@ NameLoc); } - // movsd -> movsl (when no operands are specified). - if (Name == "movsd" && Operands.size() == 1) { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken("movsl", NameLoc); - } - // fstp -> fstps . Without this, we'll default to fstpl due to // suffix searching. if (Name == "fstp" && Operands.size() == 2 && Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118331&r1=118330&r2=118331&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 02:34:58 2010 @@ -1370,6 +1370,10 @@ // Assembler Instruction Aliases //===----------------------------------------------------------------------===// +// movsd with no operands (as opposed to the SSE scalar move of a double) is an +// alias for movsl. (as in rep; movsd) +def : InstAlias<"movsd", (MOVSD)>; + // clr aliases. def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; @@ -1377,38 +1381,21 @@ def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; // movsx aliases -def : InstAlias<"movsx $src, $dst", - (MOVSX16rr8W GR16:$dst, GR8:$src)>; -def : InstAlias<"movsx $src, $dst", - (MOVSX16rm8W GR16:$dst, i8mem:$src)>; - -def : InstAlias<"movsx $src, $dst", - (MOVSX32rr8 GR32:$dst, GR8:$src)>; -def : InstAlias<"movsx $src, $dst", - (MOVSX32rr16 GR32:$dst, GR16:$src)>; - -def : InstAlias<"movsx $src, $dst", - (MOVSX64rr8 GR64:$dst, GR8:$src)>; -def : InstAlias<"movsx $src, $dst", - (MOVSX64rr16 GR64:$dst, GR16:$src)>; -def : InstAlias<"movsx $src, $dst", - (MOVSX64rr32 GR64:$dst, GR32:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>; // movzx aliases -def : InstAlias<"movzx $src, $dst", - (MOVZX16rr8W GR16:$dst, GR8:$src)>; -def : InstAlias<"movzx $src, $dst", - (MOVZX16rm8W GR16:$dst, i8mem:$src)>; - -def : InstAlias<"movzx $src, $dst", - (MOVZX32rr8 GR32:$dst, GR8:$src)>; -def : InstAlias<"movzx $src, $dst", - (MOVZX32rr16 GR32:$dst, GR16:$src)>; - -def : InstAlias<"movzx $src, $dst", - (MOVZX64rr8_Q GR64:$dst, GR8:$src)>; -def : InstAlias<"movzx $src, $dst", - (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; +def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>; +def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>; +def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>; +def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>; +def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>; +def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; // Note: No GR32->GR64 movzx form. From sabre at nondot.org Sat Nov 6 02:48:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 07:48:45 -0000 Subject: [llvm-commits] [llvm] r118332 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106074846.0527C2A6C134@llvm.org> Author: lattner Date: Sat Nov 6 02:48:45 2010 New Revision: 118332 URL: http://llvm.org/viewvc/llvm-project?rev=118332&view=rev Log: move the lcall/ljmp aliases to the .td file. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118332&r1=118331&r2=118332&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 02:48:45 2010 @@ -940,35 +940,6 @@ NameLoc, NameLoc)); } - // jmp $42,$5 -> ljmp, similarly for call. - if ((Name.startswith("call") || Name.startswith("jmp")) && - Operands.size() == 3 && - static_cast(Operands[1])->isImm() && - static_cast(Operands[2])->isImm()) { - const char *NewOpName = StringSwitch(Name) - .Case("jmp", "ljmp") - .Case("jmpw", "ljmpw") - .Case("jmpl", "ljmpl") - .Case("jmpq", "ljmpq") - .Case("call", "lcall") - .Case("callw", "lcallw") - .Case("calll", "lcalll") - .Case("callq", "lcallq") - .Default(0); - if (NewOpName) { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc); - Name = NewOpName; - } - } - - // lcall and ljmp -> lcalll and ljmpl - if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl", - NameLoc); - } - // fstp -> fstps . Without this, we'll default to fstpl due to // suffix searching. if (Name == "fstp" && Operands.size() == 2 && Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118332&r1=118331&r2=118332&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 02:48:45 2010 @@ -1370,16 +1370,32 @@ // Assembler Instruction Aliases //===----------------------------------------------------------------------===// -// movsd with no operands (as opposed to the SSE scalar move of a double) is an -// alias for movsl. (as in rep; movsd) -def : InstAlias<"movsd", (MOVSD)>; - // clr aliases. def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; +// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but +// this is compatible with what GAS does. +def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; +def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; +def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>; +def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>; + +// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp +def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; +def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; +def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; +def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; +def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; +def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; + + +// movsd with no operands (as opposed to the SSE scalar move of a double) is an +// alias for movsl. (as in rep; movsd) +def : InstAlias<"movsd", (MOVSD)>; + // movsx aliases def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>; From echristo at apple.com Sat Nov 6 02:53:11 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 06 Nov 2010 07:53:11 -0000 Subject: [llvm-commits] [llvm] r118333 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101106075311.7B9AD2A6C134@llvm.org> Author: echristo Date: Sat Nov 6 02:53:11 2010 New Revision: 118333 URL: http://llvm.org/viewvc/llvm-project?rev=118333&view=rev Log: Make sure we have movw on the target before using it. Fixes 8559. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118333&r1=118332&r2=118333&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Sat Nov 6 02:53:11 2010 @@ -439,7 +439,7 @@ // If we can do this in a single instruction without a constant pool entry // do so now. const ConstantInt *CI = cast(C); - if (isUInt<16>(CI->getSExtValue())) { + if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) { unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) From sabre at nondot.org Sat Nov 6 03:20:59 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 08:20:59 -0000 Subject: [llvm-commits] [llvm] r118334 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td utils/TableGen/AsmMatcherEmitter.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h Message-ID: <20101106082100.090E22A6C134@llvm.org> Author: lattner Date: Sat Nov 6 03:20:59 2010 New Revision: 118334 URL: http://llvm.org/viewvc/llvm-project?rev=118334&view=rev Log: fix a bug where we had an implicit assumption that the result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118334&r1=118333&r2=118334&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 03:20:59 2010 @@ -877,27 +877,6 @@ Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); } - // The assembler accepts "xchgX , " and "xchgX , " as - // synonyms. Our tables only have the ", " form, so if we see the - // other operand order, swap them. - if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"|| - Name == "xchg") - if (Operands.size() == 3 && - static_cast(Operands[1])->isMem() && - static_cast(Operands[2])->isReg()) { - std::swap(Operands[1], Operands[2]); - } - - // The assembler accepts "testX , " and "testX , " as - // synonyms. Our tables only have the ", " form, so if we see the - // other operand order, swap them. - if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"|| - Name == "test") - if (Operands.size() == 3 && - static_cast(Operands[1])->isReg() && - static_cast(Operands[2])->isMem()) { - std::swap(Operands[1], Operands[2]); - } // The assembler accepts these instructions with no operand as a synonym for // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)". Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118334&r1=118333&r2=118334&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 03:20:59 2010 @@ -1060,17 +1060,14 @@ def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), "xchg{b}\t{$val, $ptr|$ptr, $val}", [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; -def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), - (ins GR16:$val, i16mem:$ptr), +def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr), "xchg{w}\t{$val, $ptr|$ptr, $val}", [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, OpSize; -def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), - (ins GR32:$val, i32mem:$ptr), +def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr), "xchg{l}\t{$val, $ptr|$ptr, $val}", [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; -def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), - (ins GR64:$val,i64mem:$ptr), +def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr), "xchg{q}\t{$val, $ptr|$ptr, $val}", [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>; @@ -1414,4 +1411,15 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; // Note: No GR32->GR64 movzx form. +// test: We accept "testX , " and "testX , " as synonyms. +def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; +def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>; +def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>; +def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>; + +// xchg: We accept "xchgX , " and "xchgX , " as synonyms. +def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>; +def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>; +def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>; +def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>; Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118334&r1=118333&r2=118334&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 03:20:59 2010 @@ -1171,13 +1171,14 @@ StringRef OperandName, MatchableInfo::AsmOperand &Op) { const CodeGenInstAlias &CGA = *II->DefRec.get(); - + // Set up the operand class. for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) if (CGA.ResultOperands[i].Name == OperandName) { // It's safe to go with the first one we find, because CodeGenInstAlias // validates that all operands with the same name have the same record. - Op.Class = getOperandClass(CGA.ResultInst->Operands[i]); + unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i); + Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]); Op.SrcOpName = OperandName; return; } Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118334&r1=118333&r2=118334&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 03:20:59 2010 @@ -459,3 +459,21 @@ " instruction expects " + utostr(ResultInst->Operands.size())+ " operands!"); } + +/// getResultInstOperandIndexForResultOperandIndex - Given an index into the +/// ResultOperands array, translate it to a valid index in ResultInst's +/// operand list. +unsigned CodeGenInstAlias:: +getResultInstOperandIndexForResultOperandIndex(unsigned OpNo) const { + unsigned OpIdx = 0; + + for (unsigned i = 0;; ++i) { + assert(i != ResultInst->Operands.size() && "Didn't find entry"); + if (ResultInst->Operands[i].getTiedRegister() != -1) + continue; + + if (OpIdx == OpNo) return i; + + ++OpIdx; + } +} Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=118334&r1=118333&r2=118334&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sat Nov 6 03:20:59 2010 @@ -277,6 +277,11 @@ std::vector ResultOperands; CodeGenInstAlias(Record *R, CodeGenTarget &T); + + /// getResultInstOperandIndexForResultOperandIndex - Given an index into the + /// ResultOperands array, translate it to a valid index in ResultInst's + /// operand list. + unsigned getResultInstOperandIndexForResultOperandIndex(unsigned i) const; }; } From sabre at nondot.org Sat Nov 6 03:30:26 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 08:30:26 -0000 Subject: [llvm-commits] [llvm] r118335 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20101106083026.D90BE2A6C133@llvm.org> Author: lattner Date: Sat Nov 6 03:30:26 2010 New Revision: 118335 URL: http://llvm.org/viewvc/llvm-project?rev=118335&view=rev Log: document instalias. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=118335&r1=118334&r2=118335&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Sat Nov 6 03:30:26 2010 @@ -1957,6 +1957,55 @@ + +
Instruction Aliases
+ +
+ +

The most general phase of alias processing occurs while matching is +happening: it provides new forms for the matcher to match along with a specific +instruction to generate. An instruction alias has two parts: the string to +match and the instruction to generate. For example: +

+ +
+
+def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8  :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX32rr8  GR32:$dst, GR8  :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr8  GR64:$dst, GR8  :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)>;
+
+
+ +

This shows a powerful example of the instruction aliases, matching the +same mnemonic in multiple different ways depending on what operands are present +in the assembly. The result of instruction aliases can include operands in a +different order than the destination instruction, and can use an input +multiple times, for example:

+ +
+
+def : InstAlias<"clrb $reg", (XOR8rr  GR8 :$reg, GR8 :$reg)>;
+def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
+def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
+def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
+
+
+ +

This example also shows that tied operands are only listed once. In the X86 +backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied +to the output). InstAliases take a flattened operand list without duplicates +for tied operands.

+ +

Instruction aliases can also have a Requires clause to make them +subtarget specific.

+ +
+ +
Instruction Matching
From ismail at namtrac.org Sat Nov 6 03:37:57 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Sat, 6 Nov 2010 10:37:57 +0200 Subject: [llvm-commits] PATCH: Fix PR8528 In-Reply-To: <0E166CE5-A645-4C3B-A09D-8D5151396737@apple.com> References: <0E166CE5-A645-4C3B-A09D-8D5151396737@apple.com> Message-ID: Hi Chris; On Sat, Nov 6, 2010 at 8:18 AM, Chris Lattner wrote: > > On Nov 3, 2010, at 3:54 PM, ?smail D?nmez wrote: > > Hi; > > Original patch by pdox on #llvm . Asm parser was not handling fist and > fistp instructions correctly. Please apply. > > > Hi Ismail, > > This is great detective work! Just to verify my understanding, the issue > is that GAS is treating: > fistp (%rax) > as an alias for: > fistps (%rax) > and we're compiling it to: > fistpl (%rax) > > You are correct. > If this is the case, I think that the MC assembler should be changed to > *reject* fisp, not to emulate GAS's behavior. With a simple mem operand, > there is nothing to say that "4 bytes" is the right size of the store, it > should be diagnosed as an ambiguous instruction. Reporting it as a bug in > the code is much more friendly than miscompiling it of course. :) > > What do you think? > I am no assembly expert but this seems to be another vague gas behaviour. I guess rejecting this is the correct behaviour indeed. Regards, ismail -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101106/7320dfe6/attachment.html From ismail at namtrac.org Sat Nov 6 03:42:39 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Sat, 6 Nov 2010 10:42:39 +0200 Subject: [llvm-commits] PATCH: Fix PR8528 In-Reply-To: References: <0E166CE5-A645-4C3B-A09D-8D5151396737@apple.com> Message-ID: On Sat, Nov 6, 2010 at 10:37 AM, ?smail D?nmez wrote: > Hi Chris; > > On Sat, Nov 6, 2010 at 8:18 AM, Chris Lattner wrote: > >> >> On Nov 3, 2010, at 3:54 PM, ?smail D?nmez wrote: >> >> Hi; >> >> Original patch by pdox on #llvm . Asm parser was not handling fist and >> fistp instructions correctly. Please apply. >> >> >> Hi Ismail, >> >> This is great detective work! Just to verify my understanding, the issue >> is that GAS is treating: >> fistp (%rax) >> as an alias for: >> fistps (%rax) >> and we're compiling it to: >> fistpl (%rax) >> >> > You are correct. > > >> If this is the case, I think that the MC assembler should be changed to >> *reject* fisp, not to emulate GAS's behavior. With a simple mem operand, >> there is nothing to say that "4 bytes" is the right size of the store, it >> should be diagnosed as an ambiguous instruction. Reporting it as a bug in >> the code is much more friendly than miscompiling it of course. :) >> >> What do you think? >> > > I am no assembly expert but this seems to be another vague gas behaviour. I > guess rejecting this is the correct behaviour indeed. > Also there is an existing alias for fstp, should that be removed also? Regards, ismail -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101106/656173a5/attachment.html From benny.kra at googlemail.com Sat Nov 6 05:37:16 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sat, 06 Nov 2010 10:37:16 -0000 Subject: [llvm-commits] [llvm] r118337 - /llvm/trunk/lib/Target/README.txt Message-ID: <20101106103716.F2FFD2A6C133@llvm.org> Author: d0k Date: Sat Nov 6 05:37:16 2010 New Revision: 118337 URL: http://llvm.org/viewvc/llvm-project?rev=118337&view=rev Log: Add a note. Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=118337&r1=118336&r2=118337&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Sat Nov 6 05:37:16 2010 @@ -1963,3 +1963,15 @@ ret i32 %b } //===---------------------------------------------------------------------===// +We should fold this code into "ret i1 false" since neither %zero nor %one can +ever be null pointers. + +define i1 @foo(i1 %cond) { + %zero = alloca i32 + %one = alloca i32 + + %ptr = select i1 %cond, i32* %zero, i32* %one + %isnull = icmp eq i32* %ptr, null + ret i1 %isnull +} +//===---------------------------------------------------------------------===// From isanbard at gmail.com Sat Nov 6 05:40:24 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 10:40:24 -0000 Subject: [llvm-commits] [llvm] r118338 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106104024.ECB5E2A6C133@llvm.org> Author: void Date: Sat Nov 6 05:40:24 2010 New Revision: 118338 URL: http://llvm.org/viewvc/llvm-project?rev=118338&view=rev Log: Use TryParseRegister() instead of MatchRegisterName(). The former returns -1 while the latter doesn't. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118338&r1=118337&r2=118338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 05:40:24 2010 @@ -434,13 +434,12 @@ Error(RegLoc, "register expected"); return 0; } - int RegNum = MatchRegisterName(RegTok.getString()); + int RegNum = TryParseRegister(); if (RegNum == -1) { Error(RegLoc, "register expected"); return 0; } - Parser.Lex(); // Eat identifier token. unsigned RegList = 1 << RegNum; int HighRegNum = RegNum; @@ -454,7 +453,7 @@ Error(RegLoc, "register expected"); return 0; } - int RegNum = MatchRegisterName(RegTok.getString()); + int RegNum = TryParseRegister(); if (RegNum == -1) { Error(RegLoc, "register expected"); return 0; @@ -466,8 +465,6 @@ Warning(RegLoc, "register not in ascending order in register list"); RegList |= 1 << RegNum; HighRegNum = RegNum; - - Parser.Lex(); // Eat identifier token. } const AsmToken &RCurlyTok = Parser.getTok(); if (RCurlyTok.isNot(AsmToken::RCurly)) { From isanbard at gmail.com Sat Nov 6 05:45:34 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 10:45:34 -0000 Subject: [llvm-commits] [llvm] r118339 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106104534.AA8D12A6C133@llvm.org> Author: void Date: Sat Nov 6 05:45:34 2010 New Revision: 118339 URL: http://llvm.org/viewvc/llvm-project?rev=118339&view=rev Log: MatchRegisterName() returns 0 if it can't match the register. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118339&r1=118338&r2=118339&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 05:45:34 2010 @@ -387,8 +387,8 @@ // FIXME: Validate register for the current architecture; we have to do // validation later, so maybe there is no need for this here. - int RegNum = MatchRegisterName(Tok.getString()); - if (RegNum == -1) + unsigned RegNum = MatchRegisterName(Tok.getString()); + if (RegNum == 0) return -1; Parser.Lex(); // Eat identifier token. return RegNum; From isanbard at gmail.com Sat Nov 6 05:48:19 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 10:48:19 -0000 Subject: [llvm-commits] [llvm] r118340 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106104819.1C50C2A6C133@llvm.org> Author: void Date: Sat Nov 6 05:48:18 2010 New Revision: 118340 URL: http://llvm.org/viewvc/llvm-project?rev=118340&view=rev Log: Fix grammar. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118340&r1=118339&r2=118340&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 05:48:18 2010 @@ -261,7 +261,7 @@ assert(N == 2 && isMemMode5() && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); - assert(!Mem.OffsetIsReg && "invalid mode 5 operand"); + assert(!Mem.OffsetIsReg && "Invalid mode 5 operand"); // FIXME: #-0 is encoded differently than #0. Does the parser preserve // the difference? @@ -424,7 +424,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() { SMLoc S, E; assert(Parser.getTok().is(AsmToken::LCurly) && - "Token is not an Left Curly Brace"); + "Token is not a Left Curly Brace"); S = Parser.getTok().getLoc(); Parser.Lex(); // Eat left curly brace token. @@ -486,7 +486,7 @@ ARMOperand *ARMAsmParser::ParseMemory() { SMLoc S, E; assert(Parser.getTok().is(AsmToken::LBrac) && - "Token is not an Left Bracket"); + "Token is not a Left Bracket"); S = Parser.getTok().getLoc(); Parser.Lex(); // Eat left bracket token. From isanbard at gmail.com Sat Nov 6 05:51:53 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 10:51:53 -0000 Subject: [llvm-commits] [llvm] r118341 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106105153.BF9FF2A6C133@llvm.org> Author: void Date: Sat Nov 6 05:51:53 2010 New Revision: 118341 URL: http://llvm.org/viewvc/llvm-project?rev=118341&view=rev Log: Fix grammar. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118341&r1=118340&r2=118341&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 05:51:53 2010 @@ -615,7 +615,7 @@ } } - // If we parsed a register as the offset then their can be a shift after that + // If we parsed a register as the offset then there can be a shift after that. if (OffsetRegNum != -1) { // Look for a comma then a shift const AsmToken &Tok = Parser.getTok(); From benny.kra at googlemail.com Sat Nov 6 06:45:59 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sat, 06 Nov 2010 11:45:59 -0000 Subject: [llvm-commits] [llvm] r118342 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h include/llvm/Target/TargetLowering.h lib/CodeGen/IfConversion.cpp lib/CodeGen/SjLjEHPrepare.cpp lib/CodeGen/VirtRegRewriter.cpp Message-ID: <20101106114559.AFD732A6C133@llvm.org> Author: d0k Date: Sat Nov 6 06:45:59 2010 New Revision: 118342 URL: http://llvm.org/viewvc/llvm-project?rev=118342&view=rev Log: Prune includes. Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=118342&r1=118341&r2=118342&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Sat Nov 6 06:45:59 2010 @@ -15,9 +15,6 @@ #define LLVM_CODEGEN_FASTISEL_H #include "llvm/ADT/DenseMap.h" -#ifndef NDEBUG -#include "llvm/ADT/SmallSet.h" -#endif #include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/MachineBasicBlock.h" Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=118342&r1=118341&r2=118342&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Sat Nov 6 06:45:59 2010 @@ -25,13 +25,9 @@ #include "llvm/CallingConv.h" #include "llvm/InlineAsm.h" #include "llvm/Attributes.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/RuntimeLibcalls.h" -#include "llvm/ADT/APFloat.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/SmallSet.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/STLExtras.h" #include "llvm/Support/DebugLoc.h" #include "llvm/Target/TargetCallingConv.h" #include "llvm/Target/TargetMachine.h" @@ -41,6 +37,7 @@ namespace llvm { class AllocaInst; + class APFloat; class CallInst; class Function; class FastISel; @@ -56,6 +53,7 @@ class SDNode; class SDValue; class SelectionDAG; + template class SmallVectorImpl; class TargetData; class TargetMachine; class TargetRegisterClass; Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=118342&r1=118341&r2=118342&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Sat Nov 6 06:45:59 2010 @@ -28,6 +28,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" using namespace llvm; Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=118342&r1=118341&r2=118342&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Sat Nov 6 06:45:59 2010 @@ -21,15 +21,14 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/Pass.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/Transforms/Utils/BasicBlockUtils.h" -#include "llvm/Transforms/Utils/Local.h" -#include "llvm/ADT/Statistic.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/Support/CommandLine.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetLowering.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/Local.h" +#include using namespace llvm; STATISTIC(NumInvokes, "Number of invokes replaced"); Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=118342&r1=118341&r2=118342&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Sat Nov 6 06:45:59 2010 @@ -22,8 +22,8 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" -#include using namespace llvm; STATISTIC(NumDSE , "Number of dead stores elided"); From baldrick at free.fr Sat Nov 6 08:19:22 2010 From: baldrick at free.fr (Duncan Sands) Date: Sat, 06 Nov 2010 13:19:22 -0000 Subject: [llvm-commits] [dragonegg] r118343 - /dragonegg/trunk/www/index.html Message-ID: <20101106131923.0756A2A6C133@llvm.org> Author: baldrick Date: Sat Nov 6 08:19:22 2010 New Revision: 118343 URL: http://llvm.org/viewvc/llvm-project?rev=118343&view=rev Log: Note a rather nasty bug in the dragonegg-2.8 release, with a link to a patch that can be applied to fix it. Modified: dragonegg/trunk/www/index.html Modified: dragonegg/trunk/www/index.html URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/www/index.html?rev=118343&r1=118342&r2=118343&view=diff ============================================================================== --- dragonegg/trunk/www/index.html (original) +++ dragonegg/trunk/www/index.html Sat Nov 6 08:19:22 2010 @@ -78,6 +78,15 @@
  • GNU OMP constructs no longer crash the compiler.
    • +

    Known problems with the DragonEgg-2.8 release:

    +
      +
    • Functions returning complex numbers are not handled in an ABI + conformant way. This means for example that if code compiled with + dragonegg calls a function in a system library that returns a complex + number then you get a bogus result. This was fixed in + subversion commit 117649. + That patch applies correctly to the dragonegg-2.8 source.
      • +

  • DragonEgg-2.7 was the first ever DragonEgg release. It works with LLVM-2.7 and gcc-4.5.

    From sabre at nondot.org Sat Nov 6 13:28:02 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 18:28:02 -0000 Subject: [llvm-commits] [llvm] r118346 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/X86/x86-64.s Message-ID: <20101106182802.78DF42A6C133@llvm.org> Author: lattner Date: Sat Nov 6 13:28:02 2010 New Revision: 118346 URL: http://llvm.org/viewvc/llvm-project?rev=118346&view=rev Log: correct suffix matching to search for s/l/t suffixes on floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118346&r1=118345&r2=118346&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 13:28:02 2010 @@ -919,14 +919,6 @@ NameLoc, NameLoc)); } - // fstp -> fstps . Without this, we'll default to fstpl due to - // suffix searching. - if (Name == "fstp" && Operands.size() == 2 && - static_cast(Operands[1])->isMem()) { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken("fstps", NameLoc); - } - // FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA". if ((Name.startswith("aad") || Name.startswith("aam")) && Operands.size() == 1) { @@ -1002,16 +994,26 @@ Tmp += ' '; Op->setTokenValue(Tmp.str()); + // If this instruction starts with an 'f', then it is a floating point stack + // instruction. These come in up to three forms for 32-bit, 64-bit, and + // 80-bit floating point, which use the suffixes s,l,t respectively. + // + // Otherwise, we assume that this may be an integer instruction, which comes + // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively. + const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0"; + // Check for the various suffix matches. - Tmp[Base.size()] = 'b'; - unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo; - MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo); - Tmp[Base.size()] = 'w'; - MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo); - Tmp[Base.size()] = 'l'; - MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo); - Tmp[Base.size()] = 'q'; - MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo); + Tmp[Base.size()] = Suffixes[0]; + unsigned ErrorInfoIgnore; + MatchResultTy Match1, Match2, Match3, Match4; + + Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore); + Tmp[Base.size()] = Suffixes[1]; + Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore); + Tmp[Base.size()] = Suffixes[2]; + Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore); + Tmp[Base.size()] = Suffixes[3]; + Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore); // Restore the old token. Op->setTokenValue(Base); @@ -1020,8 +1022,8 @@ // instruction will already have been filled in correctly, since the failing // matches won't have modified it). unsigned NumSuccessfulMatches = - (MatchB == Match_Success) + (MatchW == Match_Success) + - (MatchL == Match_Success) + (MatchQ == Match_Success); + (Match1 == Match_Success) + (Match2 == Match_Success) + + (Match3 == Match_Success) + (Match4 == Match_Success); if (NumSuccessfulMatches == 1) { Out.EmitInstruction(Inst); return false; @@ -1034,14 +1036,10 @@ if (NumSuccessfulMatches > 1) { char MatchChars[4]; unsigned NumMatches = 0; - if (MatchB == Match_Success) - MatchChars[NumMatches++] = 'b'; - if (MatchW == Match_Success) - MatchChars[NumMatches++] = 'w'; - if (MatchL == Match_Success) - MatchChars[NumMatches++] = 'l'; - if (MatchQ == Match_Success) - MatchChars[NumMatches++] = 'q'; + if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0]; + if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1]; + if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2]; + if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3]; SmallString<126> Msg; raw_svector_ostream OS(Msg); @@ -1062,8 +1060,8 @@ // If all of the instructions reported an invalid mnemonic, then the original // mnemonic was invalid. - if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) && - (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) { + if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) && + (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) { if (!WasOriginallyInvalidOperand) { Error(IDLoc, "invalid instruction mnemonic '" + Base + "'"); return true; @@ -1084,16 +1082,16 @@ // If one instruction matched with a missing feature, report this as a // missing feature. - if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) + - (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){ + if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) + + (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){ Error(IDLoc, "instruction requires a CPU feature not currently enabled"); return true; } // If one instruction matched with an invalid operand, report this as an // operand failure. - if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) + - (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){ + if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) + + (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){ Error(IDLoc, "invalid operand for instruction"); return true; } Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118346&r1=118345&r2=118346&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Sat Nov 6 13:28:02 2010 @@ -331,11 +331,6 @@ enter $0x7ace,$0x7f -// rdar://8456389 -// CHECK: fstps (%eax) -// CHECK: encoding: [0x67,0xd9,0x18] -fstp (%eax) - // rdar://8456364 // CHECK: movw %cs, %ax mov %CS, %ax From clattner at apple.com Sat Nov 6 13:32:44 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 6 Nov 2010 11:32:44 -0700 Subject: [llvm-commits] PATCH: Fix PR8528 In-Reply-To: References: <0E166CE5-A645-4C3B-A09D-8D5151396737@apple.com> Message-ID: <7C5B4A46-6277-40AE-BCA4-73DF726CB6E4@apple.com> On Nov 6, 2010, at 1:42 AM, ?smail D?nmez wrote: > > > On Sat, Nov 6, 2010 at 10:37 AM, ?smail D?nmez wrote: > Hi Chris; > > On Sat, Nov 6, 2010 at 8:18 AM, Chris Lattner wrote: > > On Nov 3, 2010, at 3:54 PM, ?smail D?nmez wrote: > >> Hi; >> >> Original patch by pdox on #llvm . Asm parser was not handling fist and fistp instructions correctly. Please apply. > > Hi Ismail, > > This is great detective work! Just to verify my understanding, the issue is that GAS is treating: > fistp (%rax) > as an alias for: > fistps (%rax) > and we're compiling it to: > fistpl (%rax) > > > You are correct. > > If this is the case, I think that the MC assembler should be changed to *reject* fisp, not to emulate GAS's behavior. With a simple mem operand, there is nothing to say that "4 bytes" is the right size of the store, it should be diagnosed as an ambiguous instruction. Reporting it as a bug in the code is much more friendly than miscompiling it of course. :) > > What do you think? > > I am no assembly expert but this seems to be another vague gas behaviour. I guess rejecting this is the correct behaviour indeed. > > Also there is an existing alias for fstp, should that be removed also? Yes, you're completely right! I fixed this in r118346, we now get: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) ^ t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks again for tracking this down! -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101106/0b5039e2/attachment.html From ismail at namtrac.org Sat Nov 6 13:39:02 2010 From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=) Date: Sat, 6 Nov 2010 20:39:02 +0200 Subject: [llvm-commits] PATCH: Fix PR8528 In-Reply-To: <7C5B4A46-6277-40AE-BCA4-73DF726CB6E4@apple.com> References: <0E166CE5-A645-4C3B-A09D-8D5151396737@apple.com> <7C5B4A46-6277-40AE-BCA4-73DF726CB6E4@apple.com> Message-ID: Hi; On Sat, Nov 6, 2010 at 8:32 PM, Chris Lattner wrote: > On Nov 6, 2010, at 1:42 AM, ?smail D?nmez wrote: > Also there is an existing alias for fstp, should that be removed also? > > Yes, you're completely right! ?I fixed this in r118346, we now get: > t.s:1:1: error: ambiguous instructions require an explicit suffix (could be > 'fstps', 'fstpl', or 'fstpt') > fstp (%rax) > ^ > t.s:2:1: error: ambiguous instructions require an explicit suffix (could be > 'fistps', or 'fistpl') > fistp (%rax) > ^ > t.s:3:1: error: ambiguous instructions require an explicit suffix (could be > 'fists', or 'fistl') > fist (%rax) > ^ > Thanks again for tracking this down! Thanks for fixing this, I submitted a patch for MPlayer to use the correct instructions. Regards, ismail From sabre at nondot.org Sat Nov 6 13:44:27 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 18:44:27 -0000 Subject: [llvm-commits] [llvm] r118347 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106184427.17A832A6C133@llvm.org> Author: lattner Date: Sat Nov 6 13:44:26 2010 New Revision: 118347 URL: http://llvm.org/viewvc/llvm-project?rev=118347&view=rev Log: move sldt, imul, and movabsq aliases from c++ to .td file. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118347&r1=118346&r2=118347&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 13:44:26 2010 @@ -752,15 +752,6 @@ if (getLexer().is(AsmToken::EndOfStatement)) Parser.Lex(); // Consume the EndOfStatement - // Hack to allow 'movq , ' as an alias for movabsq. - if ((Name == "movq" || Name == "mov") && Operands.size() == 3 && - static_cast(Operands[2])->isReg() && - static_cast(Operands[1])->isImm() && - !static_cast(Operands[1])->isImmSExti64i32()) { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken("movabsq", NameLoc); - } - // FIXME: Hack to handle recognize s{hr,ar,hl} $1, . Canonicalize to // "shift ". if ((Name.startswith("shr") || Name.startswith("sar") || @@ -858,26 +849,6 @@ Operands.erase(Operands.begin() + 1); } - // FIXME: Hack to handle "imul , B" which is an alias for "imul , B, - // B". - if (Name.startswith("imul") && Operands.size() == 3 && - static_cast(Operands[1])->isImm() && - static_cast(Operands.back())->isReg()) { - X86Operand *Op = static_cast(Operands.back()); - Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(), - Op->getEndLoc())); - } - - // 'sldt ' can be encoded with either sldtw or sldtq with the same - // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity - // errors, since its encoding is the most compact. - if (Name == "sldt" && Operands.size() == 2 && - static_cast(Operands[1])->isMem()) { - delete Operands[0]; - Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); - } - - // The assembler accepts these instructions with no operand as a synonym for // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)". if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" || Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118347&r1=118346&r2=118347&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 13:44:26 2010 @@ -1380,6 +1380,15 @@ def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>; def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>; +// "imul , B" is an alias for "imul , B, B". +def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; +def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; +def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; +def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; +def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; +def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; + + // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; @@ -1389,6 +1398,9 @@ def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; +// Match 'movq , ' as an alias for movabsq. +def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>; + // movsd with no operands (as opposed to the SSE scalar move of a double) is an // alias for movsl. (as in rep; movsd) def : InstAlias<"movsd", (MOVSD)>; @@ -1411,6 +1423,12 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; // Note: No GR32->GR64 movzx form. +// 'sldt ' can be encoded with either sldtw or sldtq with the same +// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity +// errors, since its encoding is the most compact. +def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; + + // test: We accept "testX , " and "testX , " as synonyms. def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>; From sabre at nondot.org Sat Nov 6 13:52:40 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 18:52:40 -0000 Subject: [llvm-commits] [llvm] r118348 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106185240.D91B72A6C133@llvm.org> Author: lattner Date: Sat Nov 6 13:52:40 2010 New Revision: 118348 URL: http://llvm.org/viewvc/llvm-project?rev=118348&view=rev Log: move in/out aliases to the .td files. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118348&r1=118347&r2=118348&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 13:52:40 2010 @@ -797,22 +797,6 @@ Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc)); } - // FIXME: Hack to handle recognize "out[bwl] ". Canonicalize it to - // "outb %al, ". - if ((Name == "outb" || Name == "outw" || Name == "outl") && - Operands.size() == 2) { - unsigned Reg; - if (Name[3] == 'b') - Reg = MatchRegisterName("al"); - else if (Name[3] == 'w') - Reg = MatchRegisterName("ax"); - else - Reg = MatchRegisterName("eax"); - SMLoc Loc = Operands.back()->getEndLoc(); - Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc)); - std::swap(Operands[1], Operands[2]); - } - // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx". if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") && Operands.size() == 3) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118348&r1=118347&r2=118348&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 13:52:40 2010 @@ -1388,6 +1388,14 @@ def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; +// inb %dx -> inb %al, %dx +def : InstAlias<"inb %dx", (IN8rr)>; +def : InstAlias<"inw %dx", (IN16rr)>; +def : InstAlias<"inl %dx", (IN32rr)>; +def : InstAlias<"inb $port", (IN8ri i8imm:$port)>; +def : InstAlias<"inw $port", (IN16rir i8imm:$port)>; +def : InstAlias<"inl $port", (IN32ri i8imm:$port)>; + // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; @@ -1423,6 +1431,14 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>; // Note: No GR32->GR64 movzx form. +// outb %dx -> outb %al, %dx +def : InstAlias<"outb %dx", (OUT8rr)>; +def : InstAlias<"outw %dx", (OUT16rr)>; +def : InstAlias<"outl %dx", (OUT32rr)>; +def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>; +def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>; +def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>; + // 'sldt ' can be encoded with either sldtw or sldtq with the same // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity // errors, since its encoding is the most compact. From sabre at nondot.org Sat Nov 6 13:58:32 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 18:58:32 -0000 Subject: [llvm-commits] [llvm] r118349 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106185832.456A92A6C133@llvm.org> Author: lattner Date: Sat Nov 6 13:58:32 2010 New Revision: 118349 URL: http://llvm.org/viewvc/llvm-project?rev=118349&view=rev Log: move fnstsw aliases to .td file, fix typo Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118349&r1=118348&r2=118349&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 13:58:32 2010 @@ -781,22 +781,6 @@ X86Operand::CreateImm(One, NameLoc, NameLoc)); } - - // FIXME: Hack to handle recognize "in[bwl] ". Canonicalize it to - // "inb , %al". - if ((Name == "inb" || Name == "inw" || Name == "inl") && - Operands.size() == 2) { - unsigned Reg; - if (Name[2] == 'b') - Reg = MatchRegisterName("al"); - else if (Name[2] == 'w') - Reg = MatchRegisterName("ax"); - else - Reg = MatchRegisterName("eax"); - SMLoc Loc = Operands.back()->getEndLoc(); - Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc)); - } - // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx". if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") && Operands.size() == 3) { @@ -855,25 +839,6 @@ NameLoc, NameLoc)); } - // The assembler accepts various amounts of brokenness for fnstsw. - if (Name == "fnstsw" || Name == "fnstsww") { - if (Operands.size() == 2 && - static_cast(Operands[1])->isReg()) { - // "fnstsw al" and "fnstsw eax" -> "fnstw" - unsigned Reg = static_cast(Operands[1])->Reg.RegNo; - if (Reg == MatchRegisterName("eax") || - Reg == MatchRegisterName("al")) { - delete Operands[1]; - Operands.pop_back(); - } - } - - // "fnstw" -> "fnstw %ax" - if (Operands.size() == 1) - Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"), - NameLoc, NameLoc)); - } - // FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA". if ((Name.startswith("aad") || Name.startswith("aam")) && Operands.size() == 1) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118349&r1=118348&r2=118349&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 13:58:32 2010 @@ -1373,6 +1373,11 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; +// We accepts "fnstsw %eax" even though it only writes %ax. +def : InstAlias<"fnstsw %eax", (FNSTSW8r)>; +def : InstAlias<"fnstsw %al" , (FNSTSW8r)>; +def : InstAlias<"fnstsw" , (FNSTSW8r)>; + // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but // this is compatible with what GAS does. def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; @@ -1393,7 +1398,7 @@ def : InstAlias<"inw %dx", (IN16rr)>; def : InstAlias<"inl %dx", (IN32rr)>; def : InstAlias<"inb $port", (IN8ri i8imm:$port)>; -def : InstAlias<"inw $port", (IN16rir i8imm:$port)>; +def : InstAlias<"inw $port", (IN16ri i8imm:$port)>; def : InstAlias<"inl $port", (IN32ri i8imm:$port)>; From sabre at nondot.org Sat Nov 6 14:25:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 19:25:43 -0000 Subject: [llvm-commits] [llvm] r118350 - in /llvm/trunk: docs/CodeGenerator.html lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td utils/TableGen/AsmMatcherEmitter.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h Message-ID: <20101106192543.E23B22A6C136@llvm.org> Author: lattner Date: Sat Nov 6 14:25:43 2010 New Revision: 118350 URL: http://llvm.org/viewvc/llvm-project?rev=118350&view=rev Log: generalize alias support to allow the result of an alias to add fixed immediate values. Move the aad and aam aliases to use this, and document it. Modified: llvm/trunk/docs/CodeGenerator.html llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=118350&r1=118349&r2=118350&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Sat Nov 6 14:25:43 2010 @@ -1998,7 +1998,15 @@

    This example also shows that tied operands are only listed once. In the X86 backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied to the output). InstAliases take a flattened operand list without duplicates -for tied operands.

    +for tied operands. The result of an instruction alias can also use immediates, +which are added as simple immediate operands in the result, for example:

    + +
    +
    +def : InstAlias<"aad", (AAD8i8 10)>;
+
    +
    +

    Instruction aliases can also have a Requires clause to make them subtarget specific.

    Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118350&r1=118349&r2=118350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 14:25:43 2010 @@ -752,6 +752,22 @@ if (getLexer().is(AsmToken::EndOfStatement)) Parser.Lex(); // Consume the EndOfStatement + // This is a terrible hack to handle "out[bwl]? %al, (%dx)" -> + // "outb %al, %dx". Out doesn't take a memory form, but this is a widely + // documented form in various unofficial manuals, so a lot of code uses it. + if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") && + Operands.size() == 3) { + X86Operand &Op = *(X86Operand*)Operands.back(); + if (Op.isMem() && Op.Mem.SegReg == 0 && + isa(Op.Mem.Disp) && + cast(Op.Mem.Disp)->getValue() == 0 && + Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) { + SMLoc Loc = Op.getEndLoc(); + Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); + delete &Op; + } + } + // FIXME: Hack to handle recognize s{hr,ar,hl} $1, . Canonicalize to // "shift ". if ((Name.startswith("shr") || Name.startswith("sar") || @@ -781,20 +797,6 @@ X86Operand::CreateImm(One, NameLoc, NameLoc)); } - // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx". - if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") && - Operands.size() == 3) { - X86Operand &Op = *(X86Operand*)Operands.back(); - if (Op.isMem() && Op.Mem.SegReg == 0 && - isa(Op.Mem.Disp) && - cast(Op.Mem.Disp)->getValue() == 0 && - Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) { - SMLoc Loc = Op.getEndLoc(); - Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); - delete &Op; - } - } - // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as // "f{mul*,add*,sub*,div*} $op" if ((Name.startswith("fmul") || Name.startswith("fadd") || @@ -839,13 +841,6 @@ NameLoc, NameLoc)); } - // FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA". - if ((Name.startswith("aad") || Name.startswith("aam")) && - Operands.size() == 1) { - const MCExpr *A = MCConstantExpr::Create(0xA, getParser().getContext()); - Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc)); - } - return false; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118350&r1=118349&r2=118350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 14:25:43 2010 @@ -1367,6 +1367,10 @@ // Assembler Instruction Aliases //===----------------------------------------------------------------------===// +// aad/aam default to base 10 if no operand is specified. +def : InstAlias<"aad", (AAD8i8 10)>; +def : InstAlias<"aam", (AAM8i8 10)>; + // clr aliases. def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118350&r1=118349&r2=118350&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 14:25:43 2010 @@ -270,7 +270,11 @@ /// TiedOperand - This represents a result operand that is a duplicate of /// a previous result operand. - TiedOperand + TiedOperand, + + /// ImmOperand - This represents an immediate value that is dumped into + /// the operand. + ImmOperand } Kind; union { @@ -281,6 +285,9 @@ /// TiedOperandNum - This is the (earlier) result operand that should be /// copied from. unsigned TiedOperandNum; + + /// ImmVal - This is the immediate value added to the instruction. + int64_t ImmVal; }; /// OpInfo - This is the information about the instruction operand that is @@ -304,6 +311,15 @@ X.OpInfo = Op; return X; } + + static ResOperand getImmOp(int64_t Val, + const CGIOperandList::OperandInfo *Op) { + ResOperand X; + X.Kind = ImmOperand; + X.ImmVal = Val; + X.OpInfo = Op; + return X; + } }; /// TheDef - This is the definition of the instruction or InstAlias that this @@ -538,16 +554,6 @@ AsmOperand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; errs() << '\"' << Op.Token << "\"\n"; -#if 0 - if (!Op.OperandInfo) { - errs() << "(singleton register)\n"; - continue; - } - - const CGIOperandList::OperandInfo &OI = *Op.OperandInfo; - errs() << OI.Name << " " << OI.Rec->getName() - << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n"; -#endif } } @@ -1174,7 +1180,8 @@ // Set up the operand class. for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) - if (CGA.ResultOperands[i].Name == OperandName) { + if (CGA.ResultOperands[i].isRecord() && + CGA.ResultOperands[i].getName() == OperandName) { // It's safe to go with the first one we find, because CodeGenInstAlias // validates that all operands with the same name have the same record. unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i); @@ -1236,15 +1243,22 @@ // Find out what operand from the asmparser that this MCInst operand comes // from. - int SrcOperand = FindAsmOperandNamed(CGA.ResultOperands[AliasOpNo++].Name); - if (SrcOperand != -1) { - ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); - continue; + if (CGA.ResultOperands[AliasOpNo].isRecord()) { + StringRef Name = CGA.ResultOperands[AliasOpNo++].getName(); + int SrcOperand = FindAsmOperandNamed(Name); + if (SrcOperand != -1) { + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); + continue; + } + + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); } - throw TGError(TheDef->getLoc(), "Instruction '" + - TheDef->getName() + "' has operand '" + OpInfo.Name + - "' that doesn't appear in asm string!"); + int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm(); + ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo)); + continue; } } @@ -1291,7 +1305,6 @@ // Generate code to populate each result operand. switch (OpInfo.Kind) { - default: assert(0 && "Unknown result operand kind"); case MatchableInfo::ResOperand::RenderAsmOperand: { // This comes from something we parsed. MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; @@ -1322,6 +1335,12 @@ Signature += "__Tie" + utostr(TiedOp); break; } + case MatchableInfo::ResOperand::ImmOperand: { + int64_t Val = OpInfo.ImmVal; + CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"; + Signature += "__imm" + itostr(Val); + break; + } } } Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118350&r1=118349&r2=118350&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 14:25:43 2010 @@ -449,6 +449,21 @@ ++AliasOpNo; continue; } + + if (IntInit *II = dynamic_cast(Arg)) { + // Integer arguments can't have names. + if (!Result->getArgName(AliasOpNo).empty()) + throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) + + " must not have a name!"); + if (ResultInst->Operands[i].MINumOperands != 1 || + !ResultInst->Operands[i].Rec->isSubClassOf("Operand")) + throw TGError(R->getLoc(), "invalid argument class " + + ResultInst->Operands[i].Rec->getName() + + " for integer result operand!"); + ResultOperands.push_back(ResultOperand(II->getValue())); + ++AliasOpNo; + continue; + } throw TGError(R->getLoc(), "result of inst alias has unknown operand type"); } Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=118350&r1=118349&r2=118350&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sat Nov 6 14:25:43 2010 @@ -267,10 +267,26 @@ struct ResultOperand { + private: StringRef Name; Record *R; - ResultOperand(StringRef N, Record *r) : Name(N), R(r) {} + int64_t Imm; + public: + enum { + K_Record, + K_Imm + } Kind; + + ResultOperand(StringRef N, Record *r) : Name(N), R(r), Kind(K_Record) {} + ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {} + + bool isRecord() const { return Kind == K_Record; } + bool isImm() const { return Kind == K_Imm; } + + StringRef getName() const { assert(isRecord()); return Name; } + Record *getRecord() const { assert(isRecord()); return R; } + int64_t getImm() const { assert(isImm()); return Imm; } }; /// ResultOperands - The decoded operands for the result instruction. From isanbard at gmail.com Sat Nov 6 14:56:04 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 19:56:04 -0000 Subject: [llvm-commits] [llvm] r118351 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106195604.E1BD62A6C136@llvm.org> Author: void Date: Sat Nov 6 14:56:04 2010 New Revision: 118351 URL: http://llvm.org/viewvc/llvm-project?rev=118351&view=rev Log: Add a RegList (register list) object to ARMOperand. It will be used soon to hold (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118351&r1=118350&r2=118351&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 14:56:04 2010 @@ -42,7 +42,6 @@ MCAsmParser &Parser; TargetMachine &TM; -private: MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -118,6 +117,7 @@ Immediate, Memory, Register, + RegisterList, Token } Kind; @@ -138,6 +138,11 @@ bool Writeback; } Reg; + struct { + unsigned RegStart; + unsigned Number; + } RegList; + struct { const MCExpr *Val; } Imm; @@ -174,6 +179,9 @@ case Register: Reg = o.Reg; break; + case RegisterList: + RegList = o.RegList; + break; case Immediate: Imm = o.Imm; break; @@ -203,6 +211,11 @@ return Reg.RegNum; } + std::pair getRegList() const { + assert(Kind == RegisterList && "Invalid access!"); + return std::make_pair(RegList.RegStart, RegList.Number); + } + const MCExpr *getImm() const { assert(Kind == Immediate && "Invalid access!"); return Imm.Val; @@ -211,6 +224,7 @@ bool isCondCode() const { return Kind == CondCode; } bool isImm() const { return Kind == Immediate; } bool isReg() const { return Kind == Register; } + bool isRegList() const { return Kind == RegisterList; } bool isToken() const { return Kind == Token; } bool isMemory() const { return Kind == Memory; } @@ -312,6 +326,16 @@ return Op; } + static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number, + SMLoc S, SMLoc E) { + ARMOperand *Op = new ARMOperand(RegisterList); + Op->RegList.RegStart = RegStart; + Op->RegList.Number = Number; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; + } + static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(Immediate); Op->Imm.Val = Val; @@ -364,6 +388,19 @@ case Register: OS << ""; break; + case RegisterList: { + OS << " List = getRegList(); + unsigned RegEnd = List.first + List.second; + + for (unsigned Idx = List.first; Idx < RegEnd; ) { + OS << Idx; + if (++Idx < RegEnd) OS << ", "; + } + + OS << ">"; + break; + } case Token: OS << "'" << getToken() << "'"; break; From sabre at nondot.org Sat Nov 6 14:57:21 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 19:57:21 -0000 Subject: [llvm-commits] [llvm] r118352 - in /llvm/trunk: docs/CodeGenerator.html lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td utils/TableGen/AsmMatcherEmitter.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/CodeGenRegisters.h Message-ID: <20101106195721.E4D2C2A6C134@llvm.org> Author: lattner Date: Sat Nov 6 14:57:21 2010 New Revision: 118352 URL: http://llvm.org/viewvc/llvm-project?rev=118352&view=rev Log: add (and document) the ability for alias results to have fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). Modified: llvm/trunk/docs/CodeGenerator.html llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h llvm/trunk/utils/TableGen/CodeGenRegisters.h Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Sat Nov 6 14:57:21 2010 @@ -1998,12 +1998,20 @@

    This example also shows that tied operands are only listed once. In the X86 backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied to the output). InstAliases take a flattened operand list without duplicates -for tied operands. The result of an instruction alias can also use immediates, -which are added as simple immediate operands in the result, for example:

    +for tied operands. The result of an instruction alias can also use immediates +and fixed physical registers which are added as simple immediate operands in the +result, for example:

    +// Fixed Immediate operand.
 def : InstAlias<"aad", (AAD8i8 10)>;
+
+// Fixed register operand.
+def : InstAlias<"fcomi", (COM_FIr ST1)>;
+
+// Simple alias.
+def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>;
    Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 14:57:21 2010 @@ -821,7 +821,7 @@ // The assembler accepts these instructions with no operand as a synonym for // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)". - if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" || + if ((Name == "fxch" || Name == "faddp" || Name == "fsubp" || Name == "fsubrp" || Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") && Operands.size() == 1) { @@ -829,18 +829,6 @@ NameLoc, NameLoc)); } - // The assembler accepts these instructions with two few operands as a synonym - // for taking %st(1),%st(0) or X, %st(0). - if ((Name == "fcomi" || Name == "fucomi" || Name == "fucompi" || - Name == "fcompi" ) && - Operands.size() < 3) { - if (Operands.size() == 1) - Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), - NameLoc, NameLoc)); - Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"), - NameLoc, NameLoc)); - } - return false; } @@ -854,6 +842,8 @@ // First, handle aliases that expand to multiple instructions. // FIXME: This should be replaced with a real .td file alias mechanism. + // Also, MatchInstructionImpl should do actually *do* the EmitInstruction + // call. if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" || Op->getToken() == "fstsww" || Op->getToken() == "fstcww" || Op->getToken() == "finit" || Op->getToken() == "fsave" || Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 14:57:21 2010 @@ -1377,6 +1377,19 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; +// Default arguments for various fp stack instructions. +def : InstAlias<"fucom", (UCOM_Fr ST1)>; +def : InstAlias<"fucomp", (UCOM_FPr ST1)>; +def : InstAlias<"fcomi", (COM_FIr ST1)>; +def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>; +def : InstAlias<"fcomip", (COM_FIPr ST1)>; +def : InstAlias<"fcomip $reg", (COM_FIPr RST:$reg)>; +def : InstAlias<"fucomi", (UCOM_FIr ST1)>; +def : InstAlias<"fucomi $reg", (UCOM_FIr RST:$reg)>; +def : InstAlias<"fucomip", (UCOM_FIPr ST1)>; +def : InstAlias<"fucomip $reg", (UCOM_FIPr RST:$reg)>; + + // We accepts "fnstsw %eax" even though it only writes %ax. def : InstAlias<"fnstsw %eax", (FNSTSW8r)>; def : InstAlias<"fnstsw %al" , (FNSTSW8r)>; Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 14:57:21 2010 @@ -274,7 +274,10 @@ /// ImmOperand - This represents an immediate value that is dumped into /// the operand. - ImmOperand + ImmOperand, + + /// RegOperand - This represents a fixed register that is dumped in. + RegOperand } Kind; union { @@ -288,6 +291,9 @@ /// ImmVal - This is the immediate value added to the instruction. int64_t ImmVal; + + /// Register - This is the register record. + Record *Register; }; /// OpInfo - This is the information about the instruction operand that is @@ -320,6 +326,16 @@ X.OpInfo = Op; return X; } + + static ResOperand getRegOp(Record *Reg, + const CGIOperandList::OperandInfo *Op) { + ResOperand X; + X.Kind = RegOperand; + X.Register = Reg; + X.OpInfo = Op; + return X; + } + }; /// TheDef - This is the definition of the instruction or InstAlias that this @@ -1243,7 +1259,8 @@ // Find out what operand from the asmparser that this MCInst operand comes // from. - if (CGA.ResultOperands[AliasOpNo].isRecord()) { + switch (CGA.ResultOperands[AliasOpNo].Kind) { + case CodeGenInstAlias::ResultOperand::K_Record: { StringRef Name = CGA.ResultOperands[AliasOpNo++].getName(); int SrcOperand = FindAsmOperandNamed(Name); if (SrcOperand != -1) { @@ -1255,10 +1272,18 @@ TheDef->getName() + "' has operand '" + OpInfo.Name + "' that doesn't appear in asm string!"); } - - int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm(); - ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo)); - continue; + case CodeGenInstAlias::ResultOperand::K_Imm: { + int64_t ImmVal = CGA.ResultOperands[AliasOpNo++].getImm(); + ResOperands.push_back(ResOperand::getImmOp(ImmVal, &OpInfo)); + continue; + } + + case CodeGenInstAlias::ResultOperand::K_Reg: { + Record *Reg = CGA.ResultOperands[AliasOpNo++].getRegister(); + ResOperands.push_back(ResOperand::getRegOp(Reg, &OpInfo)); + continue; + } + } } } @@ -1341,6 +1366,11 @@ Signature += "__imm" + itostr(Val); break; } + case MatchableInfo::ResOperand::RegOperand: { + std::string N = getQualifiedName(OpInfo.Register); + CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n"; + Signature += "__reg" + OpInfo.Register->getName(); + } } } Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sat Nov 6 14:57:21 2010 @@ -419,6 +419,30 @@ Init *Arg = Result->getArg(AliasOpNo); + Record *ResultOpRec = ResultInst->Operands[i].Rec; + + // Handle explicit registers. + if (DefInit *ADI = dynamic_cast(Arg)) { + if (ADI->getDef()->isSubClassOf("Register")) { + if (!Result->getArgName(AliasOpNo).empty()) + throw TGError(R->getLoc(), "result fixed register argument must " + "not have a name!"); + + if (!ResultOpRec->isSubClassOf("RegisterClass")) + throw TGError(R->getLoc(), "result fixed register argument is not " + "passed to a RegisterClass operand!"); + + if (!T.getRegisterClass(ResultOpRec).containsRegister(ADI->getDef())) + throw TGError(R->getLoc(), "fixed register " +ADI->getDef()->getName() + + " is not a member of the " + ResultOpRec->getName() + + " register class!"); + + // Now that it is validated, add it. + ResultOperands.push_back(ResultOperand(ADI->getDef())); + ++AliasOpNo; + continue; + } + } // If the operand is a record, it must have a name, and the record type must // match up with the instruction's argument type. @@ -427,11 +451,11 @@ throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) + " must have a name!"); - if (ADI->getDef() != ResultInst->Operands[i].Rec) + if (ADI->getDef() != ResultOpRec) throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) + " declared with class " + ADI->getDef()->getName() + ", instruction operand is class " + - ResultInst->Operands[i].Rec->getName()); + ResultOpRec->getName()); // Verify we don't have something like: (someinst GR16:$foo, GR32:$foo) // $foo can exist multiple times in the result list, but it must have the @@ -456,9 +480,9 @@ throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) + " must not have a name!"); if (ResultInst->Operands[i].MINumOperands != 1 || - !ResultInst->Operands[i].Rec->isSubClassOf("Operand")) + !ResultOpRec->isSubClassOf("Operand")) throw TGError(R->getLoc(), "invalid argument class " + - ResultInst->Operands[i].Rec->getName() + + ResultOpRec->getName() + " for integer result operand!"); ResultOperands.push_back(ResultOperand(II->getValue())); ++AliasOpNo; Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sat Nov 6 14:57:21 2010 @@ -275,18 +275,22 @@ public: enum { K_Record, - K_Imm + K_Imm, + K_Reg } Kind; ResultOperand(StringRef N, Record *r) : Name(N), R(r), Kind(K_Record) {} ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {} + ResultOperand(Record *r) : R(r), Kind(K_Reg) {} bool isRecord() const { return Kind == K_Record; } bool isImm() const { return Kind == K_Imm; } + bool isReg() const { return Kind == K_Reg; } StringRef getName() const { assert(isRecord()); return Name; } Record *getRecord() const { assert(isRecord()); return R; } int64_t getImm() const { assert(isImm()); return Imm; } + Record *getRegister() const { assert(isReg()); return R; } }; /// ResultOperands - The decoded operands for the result instruction. Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=118352&r1=118351&r2=118352&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Sat Nov 6 14:57:21 2010 @@ -57,6 +57,12 @@ abort(); } + bool containsRegister(Record *R) const { + for (unsigned i = 0, e = Elements.size(); i != e; ++i) + if (Elements[i] == R) return true; + return false; + } + // Returns true if RC is a strict subclass. // RC is a sub-class of this class if it is a valid replacement for any // instruction operand where a register of this classis required. It must From wendling at apple.com Sat Nov 6 15:09:09 2010 From: wendling at apple.com (Bill Wendling) Date: Sat, 6 Nov 2010 13:09:09 -0700 Subject: [llvm-commits] [llvm] r118331 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td In-Reply-To: <20101106073458.EA4482A6C134@llvm.org> References: <20101106073458.EA4482A6C134@llvm.org> Message-ID: On Nov 6, 2010, at 12:34 AM, Chris Lattner wrote: > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118331&r1=118330&r2=118331&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 02:34:58 2010 > @@ -1370,6 +1370,10 @@ > // Assembler Instruction Aliases > //===----------------------------------------------------------------------===// > > +// movsd with no operands (as opposed to the SSE scalar move of a double) is an > +// alias for movsl. (as in rep; movsd) > +def : InstAlias<"movsd", (MOVSD)>; > + I'm not too familiar with the InstAlias, so this question may be stupid. But shouldn't the MOVSD be MOVSL in this case? -bw From sabre at nondot.org Sat Nov 6 15:41:32 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 6 Nov 2010 13:41:32 -0700 Subject: [llvm-commits] [llvm] r118331 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td In-Reply-To: References: <20101106073458.EA4482A6C134@llvm.org> Message-ID: On Nov 6, 2010, at 1:09 PM, Bill Wendling wrote: > On Nov 6, 2010, at 12:34 AM, Chris Lattner wrote: > >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118331&r1=118330&r2=118331&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 02:34:58 2010 >> @@ -1370,6 +1370,10 @@ >> // Assembler Instruction Aliases >> //===----------------------------------------------------------------------===// >> >> +// movsd with no operands (as opposed to the SSE scalar move of a double) is an >> +// alias for movsl. (as in rep; movsd) >> +def : InstAlias<"movsd", (MOVSD)>; >> + > I'm not too familiar with the InstAlias, so this question may be stupid. But shouldn't the MOVSD be MOVSL in this case? Nope, the asmstring for the MOVSD record is "movsl". -Chris From sabre at nondot.org Sat Nov 6 15:47:39 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 20:47:39 -0000 Subject: [llvm-commits] [llvm] r118353 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106204739.2D4482A6C136@llvm.org> Author: lattner Date: Sat Nov 6 15:47:38 2010 New Revision: 118353 URL: http://llvm.org/viewvc/llvm-project?rev=118353&view=rev Log: move the plethora of fp stack aliases to the .td file. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118353&r1=118352&r2=118353&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 15:47:38 2010 @@ -797,38 +797,6 @@ X86Operand::CreateImm(One, NameLoc, NameLoc)); } - // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as - // "f{mul*,add*,sub*,div*} $op" - if ((Name.startswith("fmul") || Name.startswith("fadd") || - Name.startswith("fsub") || Name.startswith("fdiv")) && - Operands.size() == 3 && - static_cast(Operands[2])->isReg() && - static_cast(Operands[2])->getReg() == X86::ST0) { - delete Operands[2]; - Operands.erase(Operands.begin() + 2); - } - - // FIXME: Hack to handle "f{mulp,addp} st(0), $op" the same as - // "f{mulp,addp} $op", since they commute. We also allow fdivrp/fsubrp even - // though they don't commute, solely because gas does support this. - if ((Name=="fmulp" || Name=="faddp" || Name=="fsubrp" || Name=="fdivrp") && - Operands.size() == 3 && - static_cast(Operands[1])->isReg() && - static_cast(Operands[1])->getReg() == X86::ST0) { - delete Operands[1]; - Operands.erase(Operands.begin() + 1); - } - - // The assembler accepts these instructions with no operand as a synonym for - // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)". - if ((Name == "fxch" || - Name == "faddp" || Name == "fsubp" || Name == "fsubrp" || - Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") && - Operands.size() == 1) { - Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), - NameLoc, NameLoc)); - } - return false; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118353&r1=118352&r2=118353&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 15:47:38 2010 @@ -1377,18 +1377,59 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; -// Default arguments for various fp stack instructions. -def : InstAlias<"fucom", (UCOM_Fr ST1)>; -def : InstAlias<"fucomp", (UCOM_FPr ST1)>; -def : InstAlias<"fcomi", (COM_FIr ST1)>; +// The instruction patterns for these instructions were written with st(0) +// explicitly in the pattern, match the form with implicit st(0). +// FIXME: Tweak these to work like fadd etc. def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>; -def : InstAlias<"fcomip", (COM_FIPr ST1)>; def : InstAlias<"fcomip $reg", (COM_FIPr RST:$reg)>; -def : InstAlias<"fucomi", (UCOM_FIr ST1)>; def : InstAlias<"fucomi $reg", (UCOM_FIr RST:$reg)>; -def : InstAlias<"fucomip", (UCOM_FIPr ST1)>; def : InstAlias<"fucomip $reg", (UCOM_FIPr RST:$reg)>; +// Various unary fpstack operations default to operating on on ST1. +// For example, "fxch" -> "fxch %st(1)" +def : InstAlias<"faddp", (ADD_FPrST0 ST1)>; +def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>; +def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>; +def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>; +def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>; +def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>; +def : InstAlias<"fxch", (XCH_F ST1)>; +def : InstAlias<"fcomi", (COM_FIr ST1)>; +def : InstAlias<"fcomip", (COM_FIPr ST1)>; +def : InstAlias<"fucom", (UCOM_Fr ST1)>; +def : InstAlias<"fucomp", (UCOM_FPr ST1)>; +def : InstAlias<"fucomi", (UCOM_FIr ST1)>; +def : InstAlias<"fucomip", (UCOM_FIPr ST1)>; + +// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. +// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate +// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with +// gas. +multiclass FpUnaryAlias { + def : InstAlias; + def : InstAlias; +} + +defm : FpUnaryAlias<"fadd", ADD_FST0r>; +defm : FpUnaryAlias<"faddp", ADD_FPrST0>; +defm : FpUnaryAlias<"fsub", SUB_FST0r>; +defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>; +defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; +defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>; +defm : FpUnaryAlias<"fmul", MUL_FST0r>; +defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; +defm : FpUnaryAlias<"fdiv", DIV_FST0r>; +defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>; +defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; +defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; + +// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they +// commute. We also allow fdivrp/fsubrp even though they don't commute, solely +// because gas supports it. +def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op)>; +def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>; +def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>; +def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>; // We accepts "fnstsw %eax" even though it only writes %ax. def : InstAlias<"fnstsw %eax", (FNSTSW8r)>; From sabre at nondot.org Sat Nov 6 15:55:09 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 20:55:09 -0000 Subject: [llvm-commits] [llvm] r118354 - in /llvm/trunk: lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-32-coverage.s test/MC/X86/x86-32.s test/MC/X86/x86-64.s Message-ID: <20101106205510.29B542A6C136@llvm.org> Author: lattner Date: Sat Nov 6 15:55:09 2010 New Revision: 118354 URL: http://llvm.org/viewvc/llvm-project?rev=118354&view=rev Log: change the fp comparison instructions to not have %st0 explicitly listed in its asm string, for consistency with the other similar instructions. Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-32-coverage.s llvm/trunk/test/MC/X86/x86-32.s llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=118354&r1=118353&r2=118354&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Sat Nov 6 15:55:09 2010 @@ -583,16 +583,16 @@ def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) (outs), (ins RST:$reg), - "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB; + "fucomi\t$reg">, DB; def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop (outs), (ins RST:$reg), - "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF; + "fucomip\t$reg">, DF; } def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), - "fcomi\t{$reg, %st(0)|%ST(0), $reg}">, DB; + "fcomi\t$reg">, DB; def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), - "fcomip\t{$reg, %st(0)|%ST(0), $reg}">, DF; + "fcomip\t$reg">, DF; // Floating point flag ops. let Defs = [AX] in Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118354&r1=118353&r2=118354&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 15:55:09 2010 @@ -1377,14 +1377,6 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; -// The instruction patterns for these instructions were written with st(0) -// explicitly in the pattern, match the form with implicit st(0). -// FIXME: Tweak these to work like fadd etc. -def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>; -def : InstAlias<"fcomip $reg", (COM_FIPr RST:$reg)>; -def : InstAlias<"fucomi $reg", (UCOM_FIr RST:$reg)>; -def : InstAlias<"fucomip $reg", (UCOM_FIPr RST:$reg)>; - // Various unary fpstack operations default to operating on on ST1. // For example, "fxch" -> "fxch %st(1)" def : InstAlias<"faddp", (ADD_FPrST0 ST1)>; @@ -1422,6 +1414,11 @@ defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>; defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; +defm : FpUnaryAlias<"fcomi", COM_FIr>; +defm : FpUnaryAlias<"fcomip", COM_FIPr>; +defm : FpUnaryAlias<"fucomi", UCOM_FIr>; +defm : FpUnaryAlias<"fucomip", UCOM_FIPr>; + // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they // commute. We also allow fdivrp/fsubrp even though they don't commute, solely Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=118354&r1=118353&r2=118354&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-32-coverage.s (original) +++ llvm/trunk/test/MC/X86/x86-32-coverage.s Sat Nov 6 15:55:09 2010 @@ -4474,19 +4474,19 @@ // CHECK: encoding: [0xdb,0xda] fcmovnu %st(2),%st -// CHECK: fcomi %st(2), %st(0) +// CHECK: fcomi %st(2) // CHECK: encoding: [0xdb,0xf2] fcomi %st(2),%st -// CHECK: fucomi %st(2), %st(0) +// CHECK: fucomi %st(2) // CHECK: encoding: [0xdb,0xea] fucomi %st(2),%st -// CHECK: fcomip %st(2), %st(0) +// CHECK: fcomip %st(2) // CHECK: encoding: [0xdf,0xf2] fcomip %st(2),%st -// CHECK: fucomip %st(2), %st(0) +// CHECK: fucomip %st(2) // CHECK: encoding: [0xdf,0xea] fucomip %st(2),%st @@ -14150,16 +14150,16 @@ // CHECK: fcmovnu %st(2), %st(0) fcmovnu %st(2),%st -// CHECK: fcomi %st(2), %st(0) +// CHECK: fcomi %st(2) fcomi %st(2),%st -// CHECK: fucomi %st(2), %st(0) +// CHECK: fucomi %st(2) fucomi %st(2),%st -// CHECK: fcomip %st(2), %st(0) +// CHECK: fcomip %st(2) fcomip %st(2),%st -// CHECK: fucomip %st(2), %st(0) +// CHECK: fucomip %st(2) fucomip %st(2),%st // CHECK: movnti %ecx, 3735928559(%ebx,%ecx,8) Modified: llvm/trunk/test/MC/X86/x86-32.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=118354&r1=118353&r2=118354&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-32.s (original) +++ llvm/trunk/test/MC/X86/x86-32.s Sat Nov 6 15:55:09 2010 @@ -708,27 +708,27 @@ // CHECK: encoding: [0x0f,0x01,0x48,0x04] sidtl 4(%eax) -// CHECK: fcomip %st(2), %st(0) +// CHECK: fcomip %st(2) // CHECK: encoding: [0xdf,0xf2] fcompi %st(2),%st -// CHECK: fcomip %st(2), %st(0) +// CHECK: fcomip %st(2) // CHECK: encoding: [0xdf,0xf2] fcompi %st(2) -// CHECK: fcomip %st(1), %st(0) +// CHECK: fcomip %st(1) // CHECK: encoding: [0xdf,0xf1] fcompi -// CHECK: fucomip %st(2), %st(0) +// CHECK: fucomip %st(2) // CHECK: encoding: [0xdf,0xea] fucompi %st(2),%st -// CHECK: fucomip %st(2), %st(0) +// CHECK: fucomip %st(2) // CHECK: encoding: [0xdf,0xea] fucompi %st(2) -// CHECK: fucomip %st(1), %st(0) +// CHECK: fucomip %st(1) // CHECK: encoding: [0xdf,0xe9] fucompi Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118354&r1=118353&r2=118354&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Sat Nov 6 15:55:09 2010 @@ -261,11 +261,11 @@ fdivp fdivrp -// CHECK: fcomi %st(1), %st(0) -// CHECK: fcomi %st(2), %st(0) -// CHECK: fucomi %st(1), %st(0) -// CHECK: fucomi %st(2), %st(0) -// CHECK: fucomi %st(2), %st(0) +// CHECK: fcomi %st(1) +// CHECK: fcomi %st(2) +// CHECK: fucomi %st(1) +// CHECK: fucomi %st(2) +// CHECK: fucomi %st(2) fcomi fcomi %st(2) From sabre at nondot.org Sat Nov 6 16:23:41 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 21:23:41 -0000 Subject: [llvm-commits] [llvm] r118355 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrShiftRotate.td test/MC/X86/x86-64.s Message-ID: <20101106212341.31DFA2A6C136@llvm.org> Author: lattner Date: Sat Nov 6 16:23:40 2010 New Revision: 118355 URL: http://llvm.org/viewvc/llvm-project?rev=118355&view=rev Log: rework the rotate-by-1 instructions to be defined like the shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118355&r1=118354&r2=118355&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 16:23:40 2010 @@ -771,7 +771,9 @@ // FIXME: Hack to handle recognize s{hr,ar,hl} $1, . Canonicalize to // "shift ". if ((Name.startswith("shr") || Name.startswith("sar") || - Name.startswith("shl") || Name.startswith("sal")) && + Name.startswith("shl") || Name.startswith("sal") || + Name.startswith("rcl") || Name.startswith("rcr") || + Name.startswith("rol") || Name.startswith("ror")) && Operands.size() == 3) { X86Operand *Op1 = static_cast(Operands[1]); if (Op1->isImm() && isa(Op1->getImm()) && @@ -781,14 +783,6 @@ } } - // FIXME: Hack to handle recognize "rc[lr] " -> "rcl $1, ". - if ((Name.startswith("rcl") || Name.startswith("rcr")) && - Operands.size() == 2) { - const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext()); - Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc)); - std::swap(Operands[1], Operands[2]); - } - // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op". if ((Name.startswith("shld") || Name.startswith("shrd")) && Operands.size() == 3) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118355&r1=118354&r2=118355&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 16:23:40 2010 @@ -1504,6 +1504,33 @@ // errors, since its encoding is the most compact. def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; +// "rc[lr] X" is an alias for "rcl X, 1" +/* +multiclass RotateAlias { + def : InstAlias(!strconcat(Opc, "8r1")) GR8:$op)>; + def : InstAlias(!strconcat(Opc, "16r1")) GR16:$op)>; + def : InstAlias(!strconcat(Opc, "32r1")) GR32:$op)>; + def : InstAlias(!strconcat(Opc, "64r1")) GR64:$op)>; + def : InstAlias(!strconcat(Opc, "8m1")) i8mem:$op)>; + def : InstAlias(!strconcat(Opc, "16m1")) i16mem:$op)>; + def : InstAlias(!strconcat(Opc, "32m1")) i32mem:$op)>; + def : InstAlias(!strconcat(Opc, "64m1")) i64mem:$op)>; +} + +defm : RotateAlias<"rcl", "RCL">; +defm : RotateAlias<"rcr", "RCR">; +defm : RotateAlias<"rol", "ROL">; +defm : RotateAlias<"ror", "ROR">; +*/ + // test: We accept "testX , " and "testX , " as synonyms. def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=118355&r1=118354&r2=118355&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Sat Nov 6 16:23:40 2010 @@ -290,7 +290,7 @@ let Constraints = "$src1 = $dst" in { def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), - "rcl{b}\t{1, $dst|$dst, 1}", []>; + "rcl{b}\t$dst", []>; def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; let Uses = [CL] in @@ -298,7 +298,7 @@ "rcl{b}\t{%cl, $dst|$dst, CL}", []>; def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), - "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; + "rcl{w}\t$dst", []>, OpSize; def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; let Uses = [CL] in @@ -306,7 +306,7 @@ "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), - "rcl{l}\t{1, $dst|$dst, 1}", []>; + "rcl{l}\t$dst", []>; def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; let Uses = [CL] in @@ -315,7 +315,7 @@ def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), - "rcl{q}\t{1, $dst|$dst, 1}", []>; + "rcl{q}\t$dst", []>; def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; let Uses = [CL] in @@ -324,7 +324,7 @@ def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), - "rcr{b}\t{1, $dst|$dst, 1}", []>; + "rcr{b}\t$dst", []>; def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; let Uses = [CL] in @@ -332,7 +332,7 @@ "rcr{b}\t{%cl, $dst|$dst, CL}", []>; def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), - "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; + "rcr{w}\t$dst", []>, OpSize; def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; let Uses = [CL] in @@ -340,7 +340,7 @@ "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), - "rcr{l}\t{1, $dst|$dst, 1}", []>; + "rcr{l}\t$dst", []>; def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; let Uses = [CL] in @@ -348,7 +348,7 @@ "rcr{l}\t{%cl, $dst|$dst, CL}", []>; def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), - "rcr{q}\t{1, $dst|$dst, 1}", []>; + "rcr{q}\t$dst", []>; def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; let Uses = [CL] in @@ -358,36 +358,36 @@ } // Constraints = "$src = $dst" def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), - "rcl{b}\t{1, $dst|$dst, 1}", []>; + "rcl{b}\t$dst", []>; def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt), "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), - "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; + "rcl{w}\t$dst", []>, OpSize; def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt), "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), - "rcl{l}\t{1, $dst|$dst, 1}", []>; + "rcl{l}\t$dst", []>; def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt), "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), - "rcl{q}\t{1, $dst|$dst, 1}", []>; + "rcl{q}\t$dst", []>; def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt), "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), - "rcr{b}\t{1, $dst|$dst, 1}", []>; + "rcr{b}\t$dst", []>; def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt), "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), - "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; + "rcr{w}\t$dst", []>, OpSize; def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt), "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), - "rcr{l}\t{1, $dst|$dst, 1}", []>; + "rcr{l}\t$dst", []>; def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt), "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), - "rcr{q}\t{1, $dst|$dst, 1}", []>; + "rcr{q}\t$dst", []>; def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt), "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118355&r1=118354&r2=118355&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Sat Nov 6 16:23:40 2010 @@ -284,16 +284,19 @@ fnstsw %al // rdar://8431880 -// CHECK: rclb $1, %bl -// CHECK: rcll $1, 3735928559(%ebx,%ecx,8) -// CHECK: rcrl $1, %ecx -// CHECK: rcrl $1, 305419896 - +// CHECK: rclb %bl +// CHECK: rcll 3735928559(%ebx,%ecx,8) +// CHECK: rcrl %ecx +// CHECK: rcrl 305419896 rcl %bl rcll 0xdeadbeef(%ebx,%ecx,8) rcr %ecx rcrl 0x12345678 +rclb %bl // CHECK: rclb %bl # encoding: [0xd0,0xd3] +rclb $1, %bl // CHECK: rclb %bl # encoding: [0xd0,0xd3] +rclb $2, %bl // CHECK: rclb $2, %bl # encoding: [0xc0,0xd3,0x02] + // rdar://8418316 // CHECK: shldw $1, %bx, %bx // CHECK: shldw $1, %bx, %bx From sabre at nondot.org Sat Nov 6 16:37:06 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 21:37:06 -0000 Subject: [llvm-commits] [llvm] r118356 - in /llvm/trunk: lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/fp-stack-compare.ll test/MC/X86/x86-32-coverage.s test/MC/X86/x86-32.s Message-ID: <20101106213706.740932A6C136@llvm.org> Author: lattner Date: Sat Nov 6 16:37:06 2010 New Revision: 118356 URL: http://llvm.org/viewvc/llvm-project?rev=118356&view=rev Log: go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/CodeGen/X86/fp-stack-compare.ll llvm/trunk/test/MC/X86/x86-32-coverage.s llvm/trunk/test/MC/X86/x86-32.s Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=118356&r1=118355&r2=118356&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Sat Nov 6 16:37:06 2010 @@ -586,13 +586,13 @@ "fucomi\t$reg">, DB; def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop (outs), (ins RST:$reg), - "fucomip\t$reg">, DF; + "fucompi\t$reg">, DF; } def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), "fcomi\t$reg">, DB; def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), - "fcomip\t$reg">, DF; + "fcompi\t$reg">, DF; // Floating point flag ops. let Defs = [AX] in Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118356&r1=118355&r2=118356&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 16:37:06 2010 @@ -1319,12 +1319,12 @@ def : MnemonicAlias<"fcmovnae", "fcmovb">; def : MnemonicAlias<"fcmovna", "fcmovbe">; def : MnemonicAlias<"fcmovae", "fcmovnb">; -def : MnemonicAlias<"fcompi", "fcomip">; +def : MnemonicAlias<"fcomip", "fcompi">; def : MnemonicAlias<"fildq", "fildll">; def : MnemonicAlias<"fldcww", "fldcw">; def : MnemonicAlias<"fnstcww", "fnstcw">; def : MnemonicAlias<"fnstsww", "fnstsw">; -def : MnemonicAlias<"fucompi", "fucomip">; +def : MnemonicAlias<"fucomip", "fucompi">; def : MnemonicAlias<"fwait", "wait">; @@ -1387,11 +1387,11 @@ def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>; def : InstAlias<"fxch", (XCH_F ST1)>; def : InstAlias<"fcomi", (COM_FIr ST1)>; -def : InstAlias<"fcomip", (COM_FIPr ST1)>; +def : InstAlias<"fcompi", (COM_FIPr ST1)>; def : InstAlias<"fucom", (UCOM_Fr ST1)>; def : InstAlias<"fucomp", (UCOM_FPr ST1)>; def : InstAlias<"fucomi", (UCOM_FIr ST1)>; -def : InstAlias<"fucomip", (UCOM_FIPr ST1)>; +def : InstAlias<"fucompi", (UCOM_FIPr ST1)>; // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate @@ -1415,9 +1415,9 @@ defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; defm : FpUnaryAlias<"fcomi", COM_FIr>; -defm : FpUnaryAlias<"fcomip", COM_FIPr>; defm : FpUnaryAlias<"fucomi", UCOM_FIr>; -defm : FpUnaryAlias<"fucomip", UCOM_FIPr>; +defm : FpUnaryAlias<"fcompi", COM_FIPr>; +defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they Modified: llvm/trunk/test/CodeGen/X86/fp-stack-compare.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-stack-compare.ll?rev=118356&r1=118355&r2=118356&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fp-stack-compare.ll (original) +++ llvm/trunk/test/CodeGen/X86/fp-stack-compare.ll Sat Nov 6 16:37:06 2010 @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=i386 | \ -; RUN: grep {fucomi.*st.\[12\]} +; RUN: llc < %s -march=x86 -mcpu=i386 | grep {fucompi.*st.\[12\]} ; PR1012 define float @foo(float* %col.2.0) { Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=118356&r1=118355&r2=118356&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-32-coverage.s (original) +++ llvm/trunk/test/MC/X86/x86-32-coverage.s Sat Nov 6 16:37:06 2010 @@ -4482,11 +4482,11 @@ // CHECK: encoding: [0xdb,0xea] fucomi %st(2),%st -// CHECK: fcomip %st(2) +// CHECK: fcompi %st(2) // CHECK: encoding: [0xdf,0xf2] fcomip %st(2),%st -// CHECK: fucomip %st(2) +// CHECK: fucompi %st(2) // CHECK: encoding: [0xdf,0xea] fucomip %st(2),%st @@ -14156,10 +14156,10 @@ // CHECK: fucomi %st(2) fucomi %st(2),%st -// CHECK: fcomip %st(2) +// CHECK: fcompi %st(2) fcomip %st(2),%st -// CHECK: fucomip %st(2) +// CHECK: fucompi %st(2) fucomip %st(2),%st // CHECK: movnti %ecx, 3735928559(%ebx,%ecx,8) Modified: llvm/trunk/test/MC/X86/x86-32.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=118356&r1=118355&r2=118356&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-32.s (original) +++ llvm/trunk/test/MC/X86/x86-32.s Sat Nov 6 16:37:06 2010 @@ -708,27 +708,27 @@ // CHECK: encoding: [0x0f,0x01,0x48,0x04] sidtl 4(%eax) -// CHECK: fcomip %st(2) +// CHECK: fcompi %st(2) // CHECK: encoding: [0xdf,0xf2] - fcompi %st(2),%st + fcompi %st(2), %st -// CHECK: fcomip %st(2) +// CHECK: fcompi %st(2) // CHECK: encoding: [0xdf,0xf2] fcompi %st(2) -// CHECK: fcomip %st(1) +// CHECK: fcompi %st(1) // CHECK: encoding: [0xdf,0xf1] fcompi -// CHECK: fucomip %st(2) +// CHECK: fucompi %st(2) // CHECK: encoding: [0xdf,0xea] fucompi %st(2),%st -// CHECK: fucomip %st(2) +// CHECK: fucompi %st(2) // CHECK: encoding: [0xdf,0xea] fucompi %st(2) -// CHECK: fucomip %st(1) +// CHECK: fucompi %st(1) // CHECK: encoding: [0xdf,0xe9] fucompi From isanbard at gmail.com Sat Nov 6 16:42:12 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 21:42:12 -0000 Subject: [llvm-commits] [llvm] r118357 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106214212.E24392A6C134@llvm.org> Author: void Date: Sat Nov 6 16:42:12 2010 New Revision: 118357 URL: http://llvm.org/viewvc/llvm-project?rev=118357&view=rev Log: General cleanup: - Make ARMOperand a class so that some things are internal to the class. - Reformatting. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118357&r1=118356&r2=118357&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 16:42:12 2010 @@ -36,24 +36,24 @@ }; namespace { - struct ARMOperand; + +class ARMOperand; class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; TargetMachine &TM; MCAsmParser &getParser() const { return Parser; } - MCAsmLexer &getLexer() const { return Parser.getLexer(); } void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } - bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } int TryParseRegister(); ARMOperand *TryParseRegisterWithWriteBack(); ARMOperand *ParseRegisterList(); ARMOperand *ParseMemory(); + ARMOperand *ParseOperand(); bool ParseMemoryOffsetReg(bool &Negative, bool &OffsetRegShifted, @@ -63,19 +63,11 @@ bool &OffsetIsReg, int &OffsetRegNum, SMLoc &E); - bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E); - - ARMOperand *ParseOperand(); - bool ParseDirectiveWord(unsigned Size, SMLoc L); - bool ParseDirectiveThumb(SMLoc L); - bool ParseDirectiveThumbFunc(SMLoc L); - bool ParseDirectiveCode(SMLoc L); - bool ParseDirectiveSyntax(SMLoc L); bool MatchAndEmitInstruction(SMLoc IDLoc, @@ -110,8 +102,7 @@ /// ARMOperand - Instances of this class represent a parsed ARM machine /// instruction. -struct ARMOperand : public MCParsedAsmOperand { -public: +class ARMOperand : public MCParsedAsmOperand { enum KindTy { CondCode, Immediate, @@ -150,21 +141,21 @@ // This is for all forms of ARM address expressions struct { unsigned BaseRegNum; - unsigned OffsetRegNum; // used when OffsetIsReg is true - const MCExpr *Offset; // used when OffsetIsReg is false - const MCExpr *ShiftAmount; // used when OffsetRegShifted is true - enum ShiftType ShiftType; // used when OffsetRegShifted is true - unsigned - OffsetRegShifted : 1, // only used when OffsetIsReg is true - Preindexed : 1, - Postindexed : 1, - OffsetIsReg : 1, - Negative : 1, // only used when OffsetIsReg is true - Writeback : 1; + unsigned OffsetRegNum; // used when OffsetIsReg is true + const MCExpr *Offset; // used when OffsetIsReg is false + const MCExpr *ShiftAmount; // used when OffsetRegShifted is true + enum ShiftType ShiftType; // used when OffsetRegShifted is true + unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true + unsigned Preindexed : 1; + unsigned Postindexed : 1; + unsigned OffsetIsReg : 1; + unsigned Negative : 1; // only used when OffsetIsReg is true + unsigned Writeback : 1; } Mem; - }; + ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} +public: ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { Kind = o.Kind; StartLoc = o.StartLoc; @@ -255,7 +246,6 @@ addExpr(Inst, getImm()); } - bool isMemMode5() const { if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted || Mem.Writeback || Mem.Negative) @@ -367,9 +357,6 @@ Op->EndLoc = E; return Op; } - -private: - ARMOperand(KindTy K) : Kind(K) {} }; } // end anonymous namespace. @@ -724,8 +711,10 @@ /// of the mnemonic. ARMOperand *ARMAsmParser::ParseOperand() { SMLoc S, E; - switch (getLexer().getKind()) { + default: + Error(Parser.getTok().getLoc(), "unexpected token in operand"); + return 0; case AsmToken::Identifier: if (ARMOperand *Op = TryParseRegisterWithWriteBack()) return Op; @@ -752,9 +741,6 @@ return 0; E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); return ARMOperand::CreateImm(ImmVal, S, E); - default: - Error(Parser.getTok().getLoc(), "unexpected token in operand"); - return 0; } } @@ -840,6 +826,7 @@ Parser.EatToEndOfStatement(); return TokError("unexpected token in argument list"); } + Parser.Lex(); // Consume the EndOfStatement return false; } @@ -854,7 +841,6 @@ case Match_Success: Out.EmitInstruction(Inst); return false; - case Match_MissingFeature: Error(IDLoc, "instruction requires a CPU feature not currently enabled"); return true; @@ -875,10 +861,9 @@ } llvm_unreachable("Implement any new match types added!"); + return true; } - - /// ParseDirective parses the arm specific directives bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { StringRef IDVal = DirectiveID.getIdentifier(); From sabre at nondot.org Sat Nov 6 17:05:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 22:05:44 -0000 Subject: [llvm-commits] [llvm] r118358 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <20101106220544.0FF462A6C136@llvm.org> Author: lattner Date: Sat Nov 6 17:05:43 2010 New Revision: 118358 URL: http://llvm.org/viewvc/llvm-project?rev=118358&view=rev Log: work-in-progress Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118358&r1=118357&r2=118358&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 17:05:43 2010 @@ -1504,9 +1504,9 @@ // errors, since its encoding is the most compact. def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; -// "rc[lr] X" is an alias for "rcl X, 1" /* -multiclass RotateAlias { +// "shl X, $1" is an alias for "shl X". +multiclass ShiftRotateByOneAlias { def : InstAlias(!strconcat(Opc, "8r1")) GR8:$op)>; def : InstAlias(!strconcat(Opc, "64m1")) i64mem:$op)>; } -defm : RotateAlias<"rcl", "RCL">; -defm : RotateAlias<"rcr", "RCR">; -defm : RotateAlias<"rol", "ROL">; -defm : RotateAlias<"ror", "ROR">; +defm : ShiftRotateByOneAlias<"rcl", "RCL">; +defm : ShiftRotateByOneAlias<"rcr", "RCR">; +defm : ShiftRotateByOneAlias<"rol", "ROL">; +defm : ShiftRotateByOneAlias<"ror", "ROR">; */ - // test: We accept "testX , " and "testX , " as synonyms. def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>; From sabre at nondot.org Sat Nov 6 17:06:04 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 22:06:04 -0000 Subject: [llvm-commits] [llvm] r118359 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20101106220604.18EF52A6C136@llvm.org> Author: lattner Date: Sat Nov 6 17:06:03 2010 New Revision: 118359 URL: http://llvm.org/viewvc/llvm-project?rev=118359&view=rev Log: pass literals like $$1 through to the asm matcher. This isn't right yet, but doesn't hurt. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=118359&r1=118358&r2=118359&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sat Nov 6 17:06:03 2010 @@ -629,21 +629,17 @@ break; case '$': { + if (InTok) { + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + InTok = false; + } + // If this isn't "${", treat like a normal token. if (i + 1 == String.size() || String[i + 1] != '{') { - if (InTok) { - AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); - InTok = false; - } Prev = i; break; } - if (InTok) { - AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); - InTok = false; - } - StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); assert(End != String.end() && "Missing brace in operand reference!"); size_t EndPos = End - String.begin(); @@ -1122,6 +1118,11 @@ continue; } + if (Token.size() > 1 && isdigit(Token[1])) { + Op.Class = getTokenClass(Token); + continue; + } + // Otherwise this is an operand reference. StringRef OperandName; if (Token[1] == '{') From isanbard at gmail.com Sat Nov 6 17:19:44 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 22:19:44 -0000 Subject: [llvm-commits] [llvm] r118360 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106221944.1243B2A6C136@llvm.org> Author: void Date: Sat Nov 6 17:19:43 2010 New Revision: 118360 URL: http://llvm.org/viewvc/llvm-project?rev=118360&view=rev Log: Return the base register of a register list for the "getReg()" method. This is to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118360&r1=118359&r2=118360&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 17:19:43 2010 @@ -129,7 +129,7 @@ bool Writeback; } Reg; - struct { + struct { unsigned RegStart; unsigned Number; } RegList; @@ -198,8 +198,13 @@ } unsigned getReg() const { - assert(Kind == Register && "Invalid access!"); - return Reg.RegNum; + assert((Kind == Register || Kind == RegisterList) && "Invalid access!"); + unsigned RegNum = 0; + if (Kind == Register) + RegNum = Reg.RegNum; + else + RegNum = RegList.RegStart; + return RegNum; } std::pair getRegList() const { From sabre at nondot.org Sat Nov 6 17:25:39 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 22:25:39 -0000 Subject: [llvm-commits] [llvm] r118361 - in /llvm/trunk/lib/Target/X86: AsmParser/X86AsmParser.cpp X86InstrInfo.td Message-ID: <20101106222540.05FFA2A6C136@llvm.org> Author: lattner Date: Sat Nov 6 17:25:39 2010 New Revision: 118361 URL: http://llvm.org/viewvc/llvm-project?rev=118361&view=rev Log: move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=118361&r1=118360&r2=118361&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Nov 6 17:25:39 2010 @@ -783,14 +783,6 @@ } } - // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op". - if ((Name.startswith("shld") || Name.startswith("shrd")) && - Operands.size() == 3) { - const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext()); - Operands.insert(Operands.begin()+1, - X86Operand::CreateImm(One, NameLoc, NameLoc)); - } - return false; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118361&r1=118360&r2=118361&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 17:25:39 2010 @@ -1504,7 +1504,23 @@ // errors, since its encoding is the most compact. def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; -/* +// shld/shrd op,op -> shld op, op, 1 +def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>; +def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>; +def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>; +def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>; +def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>; +def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>; + +def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>; +def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>; +def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>; +def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>; +def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>; +def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>; + +/* FIXME: This is disabled because the asm matcher is currently incapable of + * matching a fixed immediate like $1. // "shl X, $1" is an alias for "shl X". multiclass ShiftRotateByOneAlias { def : InstAlias; defm : ShiftRotateByOneAlias<"rol", "ROL">; defm : ShiftRotateByOneAlias<"ror", "ROR">; -*/ +FIXME */ // test: We accept "testX , " and "testX , " as synonyms. def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; From sabre at nondot.org Sat Nov 6 17:35:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 22:35:34 -0000 Subject: [llvm-commits] [llvm] r118362 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s Message-ID: <20101106223534.58CFE2A6C136@llvm.org> Author: lattner Date: Sat Nov 6 17:35:34 2010 New Revision: 118362 URL: http://llvm.org/viewvc/llvm-project?rev=118362&view=rev Log: add aliases for movs between seg registers and mem. There are multiple different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118362&r1=118361&r2=118362&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 17:35:34 2010 @@ -1465,6 +1465,11 @@ def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; +// Force mov without a suffix with a segment and mem to prefer the 'l' form of +// the move. All segment/mem forms are equivalent, this has the shortest +// encoding. +def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>; +def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>; // Match 'movq , ' as an alias for movabsq. def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>; Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118362&r1=118361&r2=118362&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Sat Nov 6 17:35:34 2010 @@ -873,3 +873,10 @@ // CHECK: sidt 4(%rax) // CHECK: encoding: [0x0f,0x01,0x48,0x04] sidtq 4(%rax) + + +// rdar://8208615 +mov (%rsi), %gs // CHECK: movl (%rsi), %gs # encoding: [0x8e,0x2e] +mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e] + + From isanbard at gmail.com Sat Nov 6 17:36:58 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 06 Nov 2010 22:36:58 -0000 Subject: [llvm-commits] [llvm] r118363 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101106223658.C3C3F2A6C136@llvm.org> Author: void Date: Sat Nov 6 17:36:58 2010 New Revision: 118363 URL: http://llvm.org/viewvc/llvm-project?rev=118363&view=rev Log: Add support for parsing register lists. We can't use a bitfield to keep track of the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118363&r1=118362&r2=118363&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 17:36:58 2010 @@ -82,7 +82,6 @@ /// } - public: ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) : TargetAsmParser(T), Parser(_Parser), TM(_TM) { @@ -93,7 +92,6 @@ virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); - virtual bool ParseDirective(AsmToken DirectiveID); }; } // end anonymous namespace @@ -433,7 +431,8 @@ ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() { SMLoc S = Parser.getTok().getLoc(); int RegNo = TryParseRegister(); - if (RegNo == -1) return 0; + if (RegNo == -1) + return 0; SMLoc E = Parser.getTok().getLoc(); @@ -451,10 +450,9 @@ /// Parse a register list, return it if successful else return null. The first /// token must be a '{' when called. ARMOperand *ARMAsmParser::ParseRegisterList() { - SMLoc S, E; assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Curly Brace"); - S = Parser.getTok().getLoc(); + SMLoc S = Parser.getTok().getLoc(); Parser.Lex(); // Eat left curly brace token. const AsmToken &RegTok = Parser.getTok(); @@ -463,18 +461,22 @@ Error(RegLoc, "register expected"); return 0; } + int RegNum = TryParseRegister(); if (RegNum == -1) { Error(RegLoc, "register expected"); return 0; } - unsigned RegList = 1 << RegNum; - - int HighRegNum = RegNum; - // TODO ranges like "{Rn-Rm}" - while (Parser.getTok().is(AsmToken::Comma)) { - Parser.Lex(); // Eat comma token. + unsigned PrevRegNum = RegNum; + std::vector > Registers; + Registers.reserve(32); + Registers.push_back(std::make_pair(RegNum, RegLoc)); + + while (Parser.getTok().is(AsmToken::Comma) || + Parser.getTok().is(AsmToken::Minus)) { + bool IsRange = Parser.getTok().is(AsmToken::Minus); + Parser.Lex(); // Eat comma or minus token. const AsmToken &RegTok = Parser.getTok(); SMLoc RegLoc = RegTok.getLoc(); @@ -482,33 +484,73 @@ Error(RegLoc, "register expected"); return 0; } + int RegNum = TryParseRegister(); if (RegNum == -1) { Error(RegLoc, "register expected"); return 0; } - if (RegList & (1 << RegNum)) - Warning(RegLoc, "register duplicated in register list"); - else if (RegNum <= HighRegNum) - Warning(RegLoc, "register not in ascending order in register list"); - RegList |= 1 << RegNum; - HighRegNum = RegNum; + if (IsRange) { + int Reg = PrevRegNum; + do { + ++Reg; + Registers.push_back(std::make_pair(Reg, RegLoc)); + } while (Reg != RegNum); + } else { + Registers.push_back(std::make_pair(RegNum, RegLoc)); + } + + PrevRegNum = RegNum; } + + // Process the right curly brace of the list. const AsmToken &RCurlyTok = Parser.getTok(); if (RCurlyTok.isNot(AsmToken::RCurly)) { Error(RCurlyTok.getLoc(), "'}' expected"); return 0; } - E = RCurlyTok.getLoc(); - Parser.Lex(); // Eat left curly brace token. - // FIXME: Need to return an operand! - Error(E, "FIXME: register list parsing not implemented"); - return 0; + SMLoc E = RCurlyTok.getLoc(); + Parser.Lex(); // Eat right curly brace token. + + // Verify the register list. + std::vector >::iterator + RI = Registers.begin(), RE = Registers.end(); + + unsigned Number = Registers.size(); + unsigned HighRegNum = RI->first; + unsigned RegStart = RI->first; + + DenseMap RegMap; + RegMap[RI->first] = true; + + for (++RI; RI != RE; ++RI) { + std::pair &RegInfo = *RI; + + if (RegMap[RegInfo.first]) { + Error(RegInfo.second, "register duplicated in register list"); + return 0; + } + + if (RegInfo.first < HighRegNum) + Warning(RegInfo.second, + "register not in ascending order in register list"); + + RegMap[RegInfo.first] = true; + HighRegNum = std::max(RegInfo.first, HighRegNum); + RegStart = std::min(RegInfo.first, RegStart); + } + + if (RegStart + Number - 1 != HighRegNum) { + Error(RegLoc, "non-contiguous register range"); + return 0; + } + + return ARMOperand::CreateRegList(RegStart, Number, S, E); } -/// Parse an arm memory expression, return false if successful else return true +/// Parse an ARM memory expression, return false if successful else return true /// or an error. The first token must be a '[' when called. /// TODO Only preindexing and postindexing addressing are started, unindexed /// with option, etc are still to do. From sabre at nondot.org Sat Nov 6 17:41:18 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 06 Nov 2010 22:41:18 -0000 Subject: [llvm-commits] [llvm] r118364 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s Message-ID: <20101106224118.C7DD12A6C136@llvm.org> Author: lattner Date: Sat Nov 6 17:41:18 2010 New Revision: 118364 URL: http://llvm.org/viewvc/llvm-project?rev=118364&view=rev Log: implement aliases for div/idiv that have an explicit A register operand, implementing rdar://8431864 Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118364&r1=118363&r2=118364&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Nov 6 17:41:18 2010 @@ -1377,6 +1377,26 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; +// div and idiv aliases for explicit A register. +def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>; +def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>; +def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>; +def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>; +def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>; +def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>; +def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>; +def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>; +def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>; +def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>; +def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>; +def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>; +def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>; +def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>; +def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>; +def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>; + + + // Various unary fpstack operations default to operating on on ST1. // For example, "fxch" -> "fxch %st(1)" def : InstAlias<"faddp", (ADD_FPrST0 ST1)>; Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118364&r1=118363&r2=118364&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Sat Nov 6 17:41:18 2010 @@ -880,3 +880,20 @@ mov %gs, (%rsi) // CHECK: movl %gs, (%rsi) # encoding: [0x8c,0x2e] +// rdar://8431864 + div %bl,%al + div %bx,%ax + div %ecx,%eax + div 0xdeadbeef(%ebx,%ecx,8),%eax + div 0x45,%eax + div 0x7eed,%eax + div 0xbabecafe,%eax + div 0x12345678,%eax + idiv %bl,%al + idiv %bx,%ax + idiv %ecx,%eax + idiv 0xdeadbeef(%ebx,%ecx,8),%eax + idiv 0x45,%eax + idiv 0x7eed,%eax + idiv 0xbabecafe,%eax + idiv 0x12345678,%eax From cdavis at mymail.mines.edu Sat Nov 6 19:44:44 2010 From: cdavis at mymail.mines.edu (Charles Davis) Date: Sat, 06 Nov 2010 18:44:44 -0600 Subject: [llvm-commits] [llvm] r118364 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s In-Reply-To: <20101106224118.C7DD12A6C136@llvm.org> References: <20101106224118.C7DD12A6C136@llvm.org> Message-ID: <4CD5F67C.3070707@mymail.mines.edu> On 11/6/10 4:41 PM, Chris Lattner wrote: > Author: lattner > Date: Sat Nov 6 17:41:18 2010 > New Revision: 118364 > > URL: http://llvm.org/viewvc/llvm-project?rev=118364&view=rev > Log: > implement aliases for div/idiv that have an explicit A register operand, > implementing rdar://8431864 Also fixes PR8418. Chip From rafael.espindola at gmail.com Sat Nov 6 21:07:12 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 07 Nov 2010 02:07:12 -0000 Subject: [llvm-commits] [llvm] r118365 - in /llvm/trunk: include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp test/MC/ELF/relax-crash.s Message-ID: <20101107020712.DACEB2A6C136@llvm.org> Author: rafael Date: Sat Nov 6 21:07:12 2010 New Revision: 118365 URL: http://llvm.org/viewvc/llvm-project?rev=118365&view=rev Log: Relax dwarf line fragments. This fixes a crash in the included testcase. Added: llvm/trunk/test/MC/ELF/relax-crash.s Modified: llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/lib/MC/MCAssembler.cpp Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=118365&r1=118364&r2=118365&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Sat Nov 6 21:07:12 2010 @@ -388,11 +388,14 @@ /// make up the address delta between two .loc dwarf directives. const MCExpr *AddrDelta; + /// Size - The current size estimate. + uint64_t Size; + public: MCDwarfLineAddrFragment(int64_t _LineDelta, const MCExpr &_AddrDelta, MCSectionData *SD = 0) : MCFragment(FT_Dwarf, SD), - LineDelta(_LineDelta), AddrDelta(&_AddrDelta) {} + LineDelta(_LineDelta), AddrDelta(&_AddrDelta), Size(1) {} /// @name Accessors /// @{ @@ -401,6 +404,10 @@ const MCExpr &getAddrDelta() const { return *AddrDelta; } + uint64_t getSize() const { return Size; } + + void setSize(uint64_t Size_) { Size = Size_; } + /// @} static bool classof(const MCFragment *F) { @@ -727,6 +734,9 @@ bool RelaxLEB(const MCObjectWriter &Writer, MCAsmLayout &Layout, MCLEBFragment &IF); + bool RelaxDwarfLineAddr(const MCObjectWriter &Writer, MCAsmLayout &Layout, + MCDwarfLineAddrFragment &DF); + /// FinishLayout - Finalize a layout, including fragment lowering. void FinishLayout(MCAsmLayout &Layout); Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=118365&r1=118364&r2=118365&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Sat Nov 6 21:07:12 2010 @@ -340,19 +340,8 @@ case MCFragment::FT_Org: return cast(F).getSize(); - case MCFragment::FT_Dwarf: { - const MCDwarfLineAddrFragment &OF = cast(F); - - // The AddrDelta is really unsigned and it can only increase. - int64_t AddrDelta; - - OF.getAddrDelta().EvaluateAsAbsolute(AddrDelta, &Layout); - - int64_t LineDelta; - LineDelta = OF.getLineDelta(); - - return MCDwarfLineAddr::ComputeSize(LineDelta, AddrDelta); - } + case MCFragment::FT_Dwarf: + return cast(F).getSize(); } assert(0 && "invalid fragment kind"); @@ -861,6 +850,18 @@ return OldSize != LF.getSize(); } +bool MCAssembler::RelaxDwarfLineAddr(const MCObjectWriter &Writer, + MCAsmLayout &Layout, + MCDwarfLineAddrFragment &DF) { + int64_t AddrDelta; + DF.getAddrDelta().EvaluateAsAbsolute(AddrDelta, &Layout); + int64_t LineDelta; + LineDelta = DF.getLineDelta(); + uint64_t OldSize = DF.getSize(); + DF.setSize(MCDwarfLineAddr::ComputeSize(LineDelta, AddrDelta)); + return OldSize != DF.getSize(); +} + bool MCAssembler::LayoutOnce(const MCObjectWriter &Writer, MCAsmLayout &Layout) { ++stats::RelaxationSteps; @@ -886,6 +887,10 @@ case MCFragment::FT_Org: WasRelaxed |= RelaxOrg(Writer, Layout, *cast(it2)); break; + case MCFragment::FT_Dwarf: + WasRelaxed |= RelaxDwarfLineAddr(Writer, Layout, + *cast(it2)); + break; case MCFragment::FT_LEB: WasRelaxed |= RelaxLEB(Writer, Layout, *cast(it2)); break; Added: llvm/trunk/test/MC/ELF/relax-crash.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-crash.s?rev=118365&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/relax-crash.s (added) +++ llvm/trunk/test/MC/ELF/relax-crash.s Sat Nov 6 21:07:12 2010 @@ -0,0 +1,11 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t + +// This is a test that we don't crash. We used to do so by going in a infinite +// recursion trying to compute the size of a MCDwarfLineAddrFragment. + + .section .debug_line,"", at progbits + .text + .file 1 "Disassembler.ii" + .section foo + .loc 1 1 0 + ret From rafael.espindola at gmail.com Sat Nov 6 23:36:50 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 07 Nov 2010 04:36:50 -0000 Subject: [llvm-commits] [llvm] r118367 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Unix/Path.inc lib/System/Win32/Path.inc Message-ID: <20101107043650.C10C82A6C136@llvm.org> Author: rafael Date: Sat Nov 6 23:36:50 2010 New Revision: 118367 URL: http://llvm.org/viewvc/llvm-project?rev=118367&view=rev Log: Add method for checking if a path is a symbolic link. Modified: llvm/trunk/include/llvm/System/Path.h llvm/trunk/lib/System/Unix/Path.inc llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=118367&r1=118366&r2=118367&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Sat Nov 6 23:36:50 2010 @@ -373,6 +373,12 @@ /// @brief Determins if the path is a directory in the file system. bool isDirectory() const; + /// This function determines if the path name refences an + /// existing symbolic link. + /// @returns true if the pathname references an existing symlink. + /// @brief Determins if the path is a symlink in the file system. + bool isSymLink() const; + /// This function determines if the path name references a readable file /// or directory in the file system. This function checks for /// the existence and readability (by the current program) of the file Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=118367&r1=118366&r2=118367&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Sat Nov 6 23:36:50 2010 @@ -434,6 +434,15 @@ } bool +Path::isSymLink() const { + struct stat buf; + if (0 != lstat(path.c_str(), &buf)) + return false; + return S_ISLNK(buf.st_mode); +} + + +bool Path::canRead() const { return 0 == access(path.c_str(), R_OK); } Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118367&r1=118366&r2=118367&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Sat Nov 6 23:36:50 2010 @@ -351,6 +351,11 @@ } bool +Path::isSymLink() const { + return false; +} + +bool Path::canRead() const { // FIXME: take security attributes into account. DWORD attr = GetFileAttributes(path.c_str()); From dalej at apple.com Sat Nov 6 23:56:41 2010 From: dalej at apple.com (Dale Johannesen) Date: Sun, 07 Nov 2010 04:56:41 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118368 - /llvm-gcc-4.2/trunk/gcc/c-typeck.c Message-ID: <20101107045641.4664D2A6C136@llvm.org> Author: johannes Date: Sat Nov 6 23:56:41 2010 New Revision: 118368 URL: http://llvm.org/viewvc/llvm-project?rev=118368&view=rev Log: Apply the "outwit the common [albeit wrong] implementation of offsetof" hack only if a constant is being derefenced. Doing it for more cases did not mix well with LLVM's representation of some pointer derefs as array accesses. 8629268. See testcase in llvm/test, coming. Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-typeck.c?rev=118368&r1=118367&r2=118368&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-typeck.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-typeck.c Sat Nov 6 23:56:41 2010 @@ -3418,7 +3418,8 @@ when we have proper support for integer constant expressions. */ val = get_base_address (arg); if (val && TREE_CODE (val) == INDIRECT_REF - && TREE_CONSTANT (TREE_OPERAND (val, 0))) + /* LLVM LOCAL treat only constant deref as pseudo-offsetof 8629268 */ + && TREE_CODE (TREE_OPERAND (val, 0)) == INTEGER_CST) { tree op0 = fold_convert (argtype, fold_offsetof (arg, val)), op1; From dalej at apple.com Sat Nov 6 23:58:48 2010 From: dalej at apple.com (Dale Johannesen) Date: Sun, 07 Nov 2010 04:58:48 -0000 Subject: [llvm-commits] [llvm] r118369 - /llvm/trunk/test/FrontendC/arrayderef.c Message-ID: <20101107045848.B8F212A6C136@llvm.org> Author: johannes Date: Sat Nov 6 23:58:48 2010 New Revision: 118369 URL: http://llvm.org/viewvc/llvm-project?rev=118369&view=rev Log: Testcase for llvm-gcc 118368. 8629268. Added: llvm/trunk/test/FrontendC/arrayderef.c Added: llvm/trunk/test/FrontendC/arrayderef.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/arrayderef.c?rev=118369&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/arrayderef.c (added) +++ llvm/trunk/test/FrontendC/arrayderef.c Sat Nov 6 23:58:48 2010 @@ -0,0 +1,17 @@ +// RUN: %llvmgcc %s -S -O -o - | FileCheck %s +// The load here was getting lost because this code was close +// enough to the traditional (wrong) implementation of offsetof +// to confuse the gcc FE. 8629268. + +struct foo { + int x; + int *y; +}; + +struct foo Foo[1]; + +int * bar(unsigned int ix) { +// CHECK: load + return &Foo->y[ix]; +} + From kremenek at apple.com Sun Nov 7 01:09:02 2010 From: kremenek at apple.com (Ted Kremenek) Date: Sun, 07 Nov 2010 06:09:02 -0000 Subject: [llvm-commits] [llvm] r118370 - /llvm/trunk/lib/Support/StringRef.cpp Message-ID: <20101107060902.D5AE52A6C136@llvm.org> Author: kremenek Date: Sun Nov 7 01:09:02 2010 New Revision: 118370 URL: http://llvm.org/viewvc/llvm-project?rev=118370&view=rev Log: Fix memory leak in StringRef::edit_distance(). 'Allocated' could be leaked on an early return. Modified: llvm/trunk/lib/Support/StringRef.cpp Modified: llvm/trunk/lib/Support/StringRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StringRef.cpp?rev=118370&r1=118369&r2=118370&view=diff ============================================================================== --- llvm/trunk/lib/Support/StringRef.cpp (original) +++ llvm/trunk/lib/Support/StringRef.cpp Sun Nov 7 01:09:02 2010 @@ -9,6 +9,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/APInt.h" +#include "llvm/ADT/OwningPtr.h" #include using namespace llvm; @@ -84,10 +85,12 @@ const unsigned SmallBufferSize = 64; unsigned SmallBuffer[SmallBufferSize]; - unsigned *Allocated = 0; + llvm::OwningArrayPtr Allocated; unsigned *previous = SmallBuffer; - if (2*(n + 1) > SmallBufferSize) - Allocated = previous = new unsigned [2*(n+1)]; + if (2*(n + 1) > SmallBufferSize) { + previous = new unsigned [2*(n+1)]; + Allocated.reset(previous); + } unsigned *current = previous + (n + 1); for (unsigned i = 0; i <= n; ++i) @@ -118,8 +121,6 @@ } unsigned Result = previous[n]; - delete [] Allocated; - return Result; } From anton at korobeynikov.info Sun Nov 7 01:57:55 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Sun, 7 Nov 2010 10:57:55 +0300 Subject: [llvm-commits] [zorg] r118311 - /zorg/trunk/buildbot/osuosl/master/config/builders.py In-Reply-To: <20101105231429.8E4FC2A6C12D@llvm.org> References: <20101105231429.8E4FC2A6C12D@llvm.org> Message-ID: Daniel, > URL: http://llvm.org/viewvc/llvm-project?rev=118311&view=rev > Log: > Downgrade llvm-gcc-i686-pc-linux-gnu-cross-gnueabi to experimental, to disable spurious failure notifications. These are real bugs which need to be eventually fixed. It's not a good idea to disable buildbot just because it shows someone had broken the build. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From anton at korobeynikov.info Sun Nov 7 03:07:26 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Sun, 7 Nov 2010 12:07:26 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r118233 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: <20101104021523.2D23E2A6C12C@llvm.org> References: <20101104021523.2D23E2A6C12C@llvm.org> Message-ID: Hi Eric, > Use the arch to set the architecture, not the mtune value. This at least breaks the buildbot :) The actual problem is that now you cannot configure llvm-gcc with setting just cpu (which matches gcc's behavior) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From asl at math.spbu.ru Sun Nov 7 03:11:35 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 07 Nov 2010 09:11:35 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118373 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h Message-ID: <20101107091136.14C132A6C139@llvm.org> Author: asl Date: Sun Nov 7 03:11:35 2010 New Revision: 118373 URL: http://llvm.org/viewvc/llvm-project?rev=118373&view=rev Log: Revert r118233: 1. It breaks the buildbot. 2. It makes the logic of arch selection does not match what gcc does. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=118373&r1=118372&r2=118373&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Sun Nov 7 03:11:35 2010 @@ -551,9 +551,6 @@ /* The processor for which instructions should be scheduled. */ enum processor_type arm_tune = arm_none; -/* LLVM LOCAL global arch value */ -enum processor_type target_arch_cpu = arm_none; - /* APPLE LOCAL begin v7 support. Merge from mainline */ /* The default processor used if not overriden by commandline. */ static enum processor_type arm_default_cpu = arm_none; @@ -1292,13 +1289,12 @@ unsigned i; /* APPLE LOCAL v7 support. Merge from Codesourcery */ int len; - /* LLVM LOCAL global arch value */ - /* Moved target_arch_cpu to arm.h */ + enum processor_type target_arch_cpu = arm_none; /* Set up the flags based on the cpu/architecture selected by the user. */ for (i = ARRAY_SIZE (arm_select); i--;) { - struct arm_cpu_select * ptr = &arm_select[i]; + struct arm_cpu_select * ptr = arm_select + i; if (ptr->string != NULL && ptr->string[0] != '\0') { Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=118373&r1=118372&r2=118373&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Sun Nov 7 03:11:35 2010 @@ -149,9 +149,6 @@ /* The processor for which instructions should be scheduled. */ extern enum processor_type arm_tune; -/* LLVM LOCAL global arch value */ -extern enum processor_type target_arch_cpu; - typedef enum arm_cond_code { ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, @@ -3459,7 +3456,7 @@ /* Turn -march=xx into a CPU type. */ #define LLVM_SET_SUBTARGET_FEATURES(F) \ - { switch (target_arch_cpu) { \ + { switch (arm_tune) { \ case arm8: F.setCPU("arm8"); break;\ case arm810: F.setCPU("arm810"); break;\ case strongarm: F.setCPU("strongarm"); break;\ From echristo at apple.com Sun Nov 7 03:14:40 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 7 Nov 2010 01:14:40 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r118233 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: References: <20101104021523.2D23E2A6C12C@llvm.org> Message-ID: <447A3F77-A294-4D9C-B20F-1F81029DC3BD@apple.com> On Nov 7, 2010, at 1:07 AM, Anton Korobeynikov wrote: > Hi Eric, > >> Use the arch to set the architecture, not the mtune value. > This at least breaks the buildbot :) > The actual problem is that now you cannot configure llvm-gcc with > setting just cpu (which matches gcc's behavior) Hmm? I haven't seen anything from the bots, but the existing behavior was broken as well, and arguably worse - -mtune shouldn't set the architecture :) If you file a bug I'll try to get it where -mcpu will set arch and tune if -march isn't passed and -mtune aren't passed. The arm port is just broken if it tries anything else. -eric From echristo at apple.com Sun Nov 7 03:19:28 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 7 Nov 2010 01:19:28 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r118373 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: <20101107091136.14C132A6C139@llvm.org> References: <20101107091136.14C132A6C139@llvm.org> Message-ID: On Nov 7, 2010, at 1:11 AM, Anton Korobeynikov wrote: > Author: asl > Date: Sun Nov 7 03:11:35 2010 > New Revision: 118373 > > URL: http://llvm.org/viewvc/llvm-project?rev=118373&view=rev > Log: > Revert r118233: > 1. It breaks the buildbot. > 2. It makes the logic of arch selection does not match what gcc does. Next time please wait for my response. The bot is performing the wrong behavior and the existing behavior is worse than the behavior from this. I'm going to reapply this and we can argue out what the correct behavior is. -eric From echristo at apple.com Sun Nov 7 03:20:21 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 7 Nov 2010 01:20:21 -0800 Subject: [llvm-commits] [zorg] r118311 - /zorg/trunk/buildbot/osuosl/master/config/builders.py In-Reply-To: References: <20101105231429.8E4FC2A6C12D@llvm.org> Message-ID: On Nov 7, 2010, at 12:57 AM, Anton Korobeynikov wrote: > Daniel, > >> URL: http://llvm.org/viewvc/llvm-project?rev=118311&view=rev >> Log: >> Downgrade llvm-gcc-i686-pc-linux-gnu-cross-gnueabi to experimental, to disable spurious failure notifications. > These are real bugs which need to be eventually fixed. It's not a good > idea to disable buildbot just because it shows someone had broken the > build. > If we can't figure out what it is complaining about nor duplicate it's not much use. -eric From anton at korobeynikov.info Sun Nov 7 03:29:53 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Sun, 7 Nov 2010 12:29:53 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r118233 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: <447A3F77-A294-4D9C-B20F-1F81029DC3BD@apple.com> References: <20101104021523.2D23E2A6C12C@llvm.org> <447A3F77-A294-4D9C-B20F-1F81029DC3BD@apple.com> Message-ID: > Hmm? I haven't seen anything from the bots, but the existing behavior was broken as well, and arguably worse - -mtune shouldn't set the architecture :) > If you file a bug I'll try to get it where -mcpu will set arch and tune if -march isn't passed and -mtune aren't passed. > The arm port is just broken if it tries anything else. The problem with your commit is the following: when I just set -mcpu LLVM emits wrong cpu into .s file (e.g. with -mcpu=cortex-a8 it emits .cpu arm7tdmi into .s file) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From asl at math.spbu.ru Sun Nov 7 03:34:37 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 7 Nov 2010 12:34:37 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r118373 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: References: <20101107091136.14C132A6C139@llvm.org> Message-ID: > Next time please wait for my response. The bot is performing the wrong behavior and the existing behavior is worse than the behavior from this. I believe the current policy was the following: it breaks the buildbot => revert until the problem would be figured out. Please correct me if I was wrong, I won't care about the buildbots next (should we remove them then?). -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From echristo at apple.com Sun Nov 7 03:38:24 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 7 Nov 2010 01:38:24 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r118373 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: References: <20101107091136.14C132A6C139@llvm.org> Message-ID: <5ECD539D-0B0F-43E6-A795-0F3BCEB64E79@apple.com> On Nov 7, 2010, at 1:34 AM, Anton Korobeynikov wrote: >> Next time please wait for my response. The bot is performing the wrong behavior and the existing behavior is worse than the behavior from this. > I believe the current policy was the following: it breaks the buildbot > => revert until the problem would be figured out. Please correct me if > I was wrong, I won't care about the buildbots next (should we remove > them then?). Which buildbot? Since I can't access it I asked about it days ago and no one has mentioned anything. I'm sitting online right now and all you had to do was ask me about the patch - which is usually considered polite. -eric From echristo at apple.com Sun Nov 7 05:09:37 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 07 Nov 2010 11:09:37 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118374 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h Message-ID: <20101107110938.36B1C2A6C132@llvm.org> Author: echristo Date: Sun Nov 7 05:09:37 2010 New Revision: 118374 URL: http://llvm.org/viewvc/llvm-project?rev=118374&view=rev Log: Reapply r118233 with some fixes for arm-linux .cpu handling output. Tested by Anton on arm-none-linux-gnueabi. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=118374&r1=118373&r2=118374&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Sun Nov 7 05:09:37 2010 @@ -551,6 +551,10 @@ /* The processor for which instructions should be scheduled. */ enum processor_type arm_tune = arm_none; +/* LLVM LOCAL global arch value */ +enum processor_type arm_arch = arm_none; +enum processor_type arm_cpu = arm_none; + /* APPLE LOCAL begin v7 support. Merge from mainline */ /* The default processor used if not overriden by commandline. */ static enum processor_type arm_default_cpu = arm_none; @@ -1289,12 +1293,13 @@ unsigned i; /* APPLE LOCAL v7 support. Merge from Codesourcery */ int len; - enum processor_type target_arch_cpu = arm_none; + /* LLVM LOCAL global arch value */ + /* Moved arm_arch to arm.h as arm_arch and arm_cpu */ /* Set up the flags based on the cpu/architecture selected by the user. */ for (i = ARRAY_SIZE (arm_select); i--;) { - struct arm_cpu_select * ptr = arm_select + i; + struct arm_cpu_select * ptr = &arm_select[i]; if (ptr->string != NULL && ptr->string[0] != '\0') { @@ -1325,8 +1330,14 @@ If no other option is used to set the CPU type, we'll use this to guess the most suitable tuning options. */ - if (i == ARM_OPT_SET_ARCH) - target_arch_cpu = sel->core; + if (/* -mcpu is a sensible default. */ + i == ARM_OPT_SET_CPU + /* But -march= overrides -mcpu. */ + || i == ARM_OPT_SET_ARCH) + arm_arch = (enum processor_type) (sel - ptr->processors); + + if (i == ARM_OPT_SET_CPU) + arm_cpu = (enum processor_type) (sel - ptr->processors); if (i != ARM_OPT_SET_TUNE) { @@ -1360,7 +1371,7 @@ /* Guess the tuning options from the architecture if necessary. */ if (arm_tune == arm_none) - arm_tune = target_arch_cpu; + arm_tune = arm_arch; /* If the user did not specify a processor, choose one for them. */ if (insn_flags == 0) @@ -1454,6 +1465,8 @@ arm_default_cpu = (enum processor_type) (sel - all_cores); if (arm_tune == arm_none) arm_tune = arm_default_cpu; + if (arm_cpu == arm_none) + arm_cpu = arm_default_cpu; /* APPLE LOCAL end v7 support. Merge from Codesourcery */ } Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=118374&r1=118373&r2=118374&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Sun Nov 7 05:09:37 2010 @@ -149,6 +149,10 @@ /* The processor for which instructions should be scheduled. */ extern enum processor_type arm_tune; +/* LLVM LOCAL global arch value */ +extern enum processor_type arm_arch; +extern enum processor_type arm_cpu; + typedef enum arm_cond_code { ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, @@ -3456,7 +3460,7 @@ /* Turn -march=xx into a CPU type. */ #define LLVM_SET_SUBTARGET_FEATURES(F) \ - { switch (arm_tune) { \ + { switch (arm_cpu) { \ case arm8: F.setCPU("arm8"); break;\ case arm810: F.setCPU("arm810"); break;\ case strongarm: F.setCPU("strongarm"); break;\ From baldrick at free.fr Sun Nov 7 05:15:16 2010 From: baldrick at free.fr (Duncan Sands) Date: Sun, 07 Nov 2010 12:15:16 +0100 Subject: [llvm-commits] [llvm] r118367 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Unix/Path.inc lib/System/Win32/Path.inc In-Reply-To: <20101107043650.C10C82A6C136@llvm.org> References: <20101107043650.C10C82A6C136@llvm.org> Message-ID: <4CD68A44.4040307@free.fr> Hi Rafael, ===================================== > --- llvm/trunk/include/llvm/System/Path.h (original) > +++ llvm/trunk/include/llvm/System/Path.h Sat Nov 6 23:36:50 2010 > @@ -373,6 +373,12 @@ > /// @brief Determins if the path is a directory in the file system. > bool isDirectory() const; > > + /// This function determines if the path name refences an refences -> references > + /// existing symbolic link. > + /// @returns true if the pathname references an existing symlink. > + /// @brief Determins if the path is a symlink in the file system. Determins -> Determines > ============================================================================== > --- llvm/trunk/lib/System/Win32/Path.inc (original) > +++ llvm/trunk/lib/System/Win32/Path.inc Sat Nov 6 23:36:50 2010 > @@ -351,6 +351,11 @@ > } > > bool > +Path::isSymLink() const { > + return false; > +} Doesn't windows support a kind of symbolic link nowadays? Ciao, Duncan. From echristo at apple.com Sun Nov 7 05:18:03 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 7 Nov 2010 03:18:03 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r118374 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h In-Reply-To: <20101107110938.36B1C2A6C132@llvm.org> References: <20101107110938.36B1C2A6C132@llvm.org> Message-ID: <2A9E781C-8A90-4A20-BC4A-F832DFE8798A@apple.com> On Nov 7, 2010, at 3:09 AM, Eric Christopher wrote: > Reapply r118233 with some fixes for arm-linux .cpu handling output. > > Tested by Anton on arm-none-linux-gnueabi. In case anyone is curious, this is better, but still not ideal. Needs a bit better handling for edge cases, but I'll rework that shortly and this is better than it was. -eric From isanbard at gmail.com Sun Nov 7 07:08:28 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sun, 07 Nov 2010 13:08:28 -0000 Subject: [llvm-commits] [llvm] r118375 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101107130828.9E6522A6C12D@llvm.org> Author: void Date: Sun Nov 7 07:08:28 2010 New Revision: 118375 URL: http://llvm.org/viewvc/llvm-project?rev=118375&view=rev Log: In this context, a reglist is a reg. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118375&r1=118374&r2=118375&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sun Nov 7 07:08:28 2010 @@ -217,7 +217,7 @@ bool isCondCode() const { return Kind == CondCode; } bool isImm() const { return Kind == Immediate; } - bool isReg() const { return Kind == Register; } + bool isReg() const { return Kind == Register || Kind == RegisterList; } bool isRegList() const { return Kind == RegisterList; } bool isToken() const { return Kind == Token; } bool isMemory() const { return Kind == Memory; } From rafael.espindola at gmail.com Sun Nov 7 07:48:10 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 07 Nov 2010 13:48:10 -0000 Subject: [llvm-commits] [llvm] r118376 - /llvm/trunk/include/llvm/System/Path.h Message-ID: <20101107134810.3C9BF2A6C12C@llvm.org> Author: rafael Date: Sun Nov 7 07:48:10 2010 New Revision: 118376 URL: http://llvm.org/viewvc/llvm-project?rev=118376&view=rev Log: typos Modified: llvm/trunk/include/llvm/System/Path.h Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=118376&r1=118375&r2=118376&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Sun Nov 7 07:48:10 2010 @@ -367,16 +367,16 @@ /// the file system. bool exists() const; - /// This function determines if the path name refences an + /// This function determines if the path name references an /// existing directory. /// @returns true if the pathname references an existing directory. - /// @brief Determins if the path is a directory in the file system. + /// @brief Determines if the path is a directory in the file system. bool isDirectory() const; - /// This function determines if the path name refences an + /// This function determines if the path name references an /// existing symbolic link. /// @returns true if the pathname references an existing symlink. - /// @brief Determins if the path is a symlink in the file system. + /// @brief Determines if the path is a symlink in the file system. bool isSymLink() const; /// This function determines if the path name references a reada