From benny.kra at googlemail.com Mon Nov 8 04:52:43 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 08 Nov 2010 10:52:43 -0000 Subject: [llvm-commits] [llvm] r118405 - in /llvm/trunk: bindings/ocaml/analysis/ bindings/ocaml/bitreader/ bindings/ocaml/bitwriter/ bindings/ocaml/executionengine/ bindings/ocaml/llvm/ bindings/ocaml/target/ bindings/ocaml/transforms/scalar/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ lib/Target/MSP430/InstPrinter/ test/Analysis/TypeBasedAliasAnalysis/ test/MC/ELF/ test/Transforms/CorrelatedValuePropagation/ Message-ID: <20101108105243.40A9A2A6C12C@llvm.org> Author: d0k Date: Mon Nov 8 04:52:42 2010 New Revision: 118405 URL: http://llvm.org/viewvc/llvm-project?rev=118405&view=rev Log: svn:ignore Modified: llvm/trunk/bindings/ocaml/analysis/ (props changed) llvm/trunk/bindings/ocaml/bitreader/ (props changed) llvm/trunk/bindings/ocaml/bitwriter/ (props changed) llvm/trunk/bindings/ocaml/executionengine/ (props changed) llvm/trunk/bindings/ocaml/llvm/ (props changed) llvm/trunk/bindings/ocaml/target/ (props changed) llvm/trunk/bindings/ocaml/transforms/scalar/ (props changed) llvm/trunk/lib/Target/MBlaze/AsmParser/ (props changed) llvm/trunk/lib/Target/MBlaze/Disassembler/ (props changed) llvm/trunk/lib/Target/MBlaze/InstPrinter/ (props changed) llvm/trunk/lib/Target/MSP430/InstPrinter/ (props changed) llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/ (props changed) llvm/trunk/test/MC/ELF/ (props changed) llvm/trunk/test/Transforms/CorrelatedValuePropagation/ (props changed) Propchange: llvm/trunk/bindings/ocaml/analysis/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ Debug +Debug+Asserts Release -Release-Asserts +Release+Asserts Propchange: llvm/trunk/bindings/ocaml/bitreader/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ Debug +Debug+Asserts Release -Release-Asserts +Release+Asserts Propchange: llvm/trunk/bindings/ocaml/bitwriter/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ Debug +Debug+Asserts Release -Release-Asserts +Release+Asserts Propchange: llvm/trunk/bindings/ocaml/executionengine/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ Debug +Debug+Asserts Release -Release-Asserts +Release+Asserts Propchange: llvm/trunk/bindings/ocaml/llvm/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ Debug +Debug+Asserts Release -Release-Asserts +Release+Asserts Propchange: llvm/trunk/bindings/ocaml/target/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ -Release Debug -Release-Asserts +Debug+Asserts +Release +Release+Asserts Propchange: llvm/trunk/bindings/ocaml/transforms/scalar/ ------------------------------------------------------------------------------ --- svn:ignore (original) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -1,3 +1,4 @@ Debug +Debug+Asserts Release -Release-Asserts +Release+Asserts Propchange: llvm/trunk/lib/Target/MBlaze/AsmParser/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1,8 @@ +Debug +Debug+Asserts +Debug+Checks +Debug+Coverage +Debug+Coverage-Asserts +Release +Release+Asserts +Release+Coverage Propchange: llvm/trunk/lib/Target/MBlaze/Disassembler/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1,8 @@ +Debug +Debug+Asserts +Debug+Checks +Debug+Coverage +Debug+Coverage-Asserts +Release +Release+Asserts +Release+Coverage Propchange: llvm/trunk/lib/Target/MBlaze/InstPrinter/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1,8 @@ +Debug +Debug+Asserts +Debug+Checks +Debug+Coverage +Debug+Coverage-Asserts +Release +Release+Asserts +Release+Coverage Propchange: llvm/trunk/lib/Target/MSP430/InstPrinter/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1,8 @@ +Debug +Debug+Asserts +Debug+Checks +Debug+Coverage +Debug+Coverage-Asserts +Release +Release+Asserts +Release+Coverage Propchange: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1 @@ +Output Propchange: llvm/trunk/test/MC/ELF/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1 @@ +Output Propchange: llvm/trunk/test/Transforms/CorrelatedValuePropagation/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 8 04:52:42 2010 @@ -0,0 +1 @@ +Output From baldrick at free.fr Mon Nov 8 07:38:07 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 14:38:07 +0100 Subject: [llvm-commits] [llvm] r118378 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp lib/Target/README.txt test/Transforms/InstCombine/select.ll In-Reply-To: References: <20101107161224.05FC22A6C12C@llvm.org> Message-ID: <4CD7FD3F.5050708@free.fr> Hi Benjamin, >> Author: baldrick >> Date: Sun Nov 7 10:12:23 2010 >> New Revision: 118378 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118378&view=rev >> Log: >> Fix a README item: when doing a comparison with the result >> of a select instruction, see if doing the compare with the >> true and false values of the select gives the same result. >> If so, that can be used as the value of the comparison. > > Awesome! Should we do the same thing on phi nodes where an icmp > on all incoming values yields the same result? that is a bit more tricky since you can get infinite recursion when doing this kind of analysis on phi nodes unless you protect against it. I may try to whip something up later this week. Another thing to consider is doing this "looking through select/phi" optimization for other instructions, and not just compares. For example for logical operations like "and". What do you think? Ciao, Duncan. From fvbommel at gmail.com Mon Nov 8 08:11:15 2010 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 8 Nov 2010 15:11:15 +0100 Subject: [llvm-commits] [llvm] r118378 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp lib/Target/README.txt test/Transforms/InstCombine/select.ll In-Reply-To: <4CD7FD3F.5050708@free.fr> References: <20101107161224.05FC22A6C12C@llvm.org> <4CD7FD3F.5050708@free.fr> Message-ID: On Mon, Nov 8, 2010 at 2:38 PM, Duncan Sands wrote: > Another thing to consider is doing this "looking through select/phi" > optimization for other instructions, and not just compares. ?For > example for logical operations like "and". ?What do you think? I'm pretty sure -instcombine already does things like this, at least for bitwise operations like 'and' when combined with 'select' and many other instructions (though it doesn't seem to handle 'phi' instrutions). From baldrick at free.fr Mon Nov 8 09:19:29 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 16:19:29 +0100 Subject: [llvm-commits] [llvm] r118378 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp lib/Target/README.txt test/Transforms/InstCombine/select.ll In-Reply-To: References: <20101107161224.05FC22A6C12C@llvm.org> <4CD7FD3F.5050708@free.fr> Message-ID: <4CD81501.5080902@free.fr> Hi Frits, > On Mon, Nov 8, 2010 at 2:38 PM, Duncan Sands wrote: >> Another thing to consider is doing this "looking through select/phi" >> optimization for other instructions, and not just compares. For >> example for logical operations like "and". What do you think? > > I'm pretty sure -instcombine already does things like this, at least > for bitwise operations like 'and' when combined with 'select' and many > other instructions (though it doesn't seem to handle 'phi' > instrutions). judging from FoldOpIntoSelect, instruction combine transforms select(cond, X, Y) and Constant into select(cond, X and Constant, Y and Constant) Note that it will only do this if select has exactly one use, and it only does it with a constant, which is pretty restrictive. The suggested transform would transform select(cond, X, Y) and Z into X and Z if it can prove that "X and Z" equals "Y and Z". I think this is always a win if it can be done, and I don't see any need to restrict to select instructions with only one use, Z a constant etc. That said, the way I was thinking of doing this would result in the transform only being done if both "X and Z" and "Y and Z" simplify (eg evaluate to constants), as well as being equal. Ciao, Duncan. From gohman at apple.com Mon Nov 8 09:34:42 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 15:34:42 -0000 Subject: [llvm-commits] [llvm] r118408 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101108153442.BFD732A6C12C@llvm.org> Author: djg Date: Mon Nov 8 09:34:42 2010 New Revision: 118408 URL: http://llvm.org/viewvc/llvm-project?rev=118408&view=rev Log: Add comments. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118408&r1=118407&r2=118408&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Nov 8 09:34:42 2010 @@ -86,10 +86,14 @@ struct Location { /// Ptr - The address of the start of the location. const Value *Ptr; - /// Size - The size of the location. + /// Size - The maximum size of the location, or UnknownSize if the size is + /// not known. Note that an unknown size does not mean the pointer aliases + /// the entire virtual address space, because there are restrictions on + /// stepping out of one object and into another. + /// See http://llvm.org/docs/LangRef.html#pointeraliasing uint64_t Size; /// TBAATag - The metadata node which describes the TBAA type of - /// the location, or null if there is no (unique) tag. + /// the location, or null if there is no known unique tag. const MDNode *TBAATag; explicit Location(const Value *P = 0, @@ -122,9 +126,9 @@ enum AliasResult { NoAlias = 0, MayAlias = 1, MustAlias = 2 }; /// alias - The main low level interface to the alias analysis implementation. - /// Returns a Result indicating whether the two pointers are aliased to each - /// other. This is the interface that must be implemented by specific alias - /// analysis implementations. + /// Returns an AliasResult indicating whether the two pointers are aliased to + /// each other. This is the interface that must be implemented by specific + /// alias analysis implementations. virtual AliasResult alias(const Location &LocA, const Location &LocB); /// alias - A convenience wrapper. From gohman at apple.com Mon Nov 8 10:08:43 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 16:08:43 -0000 Subject: [llvm-commits] [llvm] r118409 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <20101108160843.B1F782A6C12C@llvm.org> Author: djg Date: Mon Nov 8 10:08:43 2010 New Revision: 118409 URL: http://llvm.org/viewvc/llvm-project?rev=118409&view=rev Log: Teach BasicAliasAnalysis::getModRefBehavior(const Function *F) to analyze intrinsic functions. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=118409&r1=118408&r2=118409&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Nov 8 10:08:43 2010 @@ -553,14 +553,22 @@ /// For use when the call site is not known. AliasAnalysis::ModRefBehavior BasicAliasAnalysis::getModRefBehavior(const Function *F) { + // If the function declares it doesn't access memory, we can't do better. if (F->doesNotAccessMemory()) - // Can't do better than this. return DoesNotAccessMemory; + + // For intrinsics, we can check the table. + if (unsigned iid = F->getIntrinsicID()) { +#define GET_INTRINSIC_MODREF_BEHAVIOR +#include "llvm/Intrinsics.gen" +#undef GET_INTRINSIC_MODREF_BEHAVIOR + } + + // If the function declares it only reads memory, go with that. if (F->onlyReadsMemory()) return OnlyReadsMemory; - if (unsigned id = F->getIntrinsicID()) - return getIntrinsicModRefBehavior(id); + // Otherwise be conservative. return AliasAnalysis::getModRefBehavior(F); } From gohman at apple.com Mon Nov 8 10:10:15 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 16:10:15 -0000 Subject: [llvm-commits] [llvm] r118410 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll Message-ID: <20101108161016.02D322A6C12C@llvm.org> Author: djg Date: Mon Nov 8 10:10:15 2010 New Revision: 118410 URL: http://llvm.org/viewvc/llvm-project?rev=118410&view=rev Log: Make FunctionAttrs use AliasAnalysis::getModRefBehavior, now that it knows about intrinsic functions. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp llvm/trunk/test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118410&r1=118409&r2=118410&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Mon Nov 8 10:10:15 2010 @@ -40,7 +40,7 @@ namespace { struct FunctionAttrs : public CallGraphSCCPass { static char ID; // Pass identification, replacement for typeid - FunctionAttrs() : CallGraphSCCPass(ID) { + FunctionAttrs() : CallGraphSCCPass(ID), AA(0) { initializeFunctionAttrsPass(*PassRegistry::getPassRegistry()); } @@ -62,10 +62,14 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); + AU.addRequired(); CallGraphSCCPass::getAnalysisUsage(AU); } bool PointsToLocalOrConstantMemory(Value *V); + + private: + AliasAnalysis *AA; }; } @@ -167,26 +171,35 @@ // Some instructions can be ignored even if they read or write memory. // Detect these now, skipping to the next instruction if one is found. CallSite CS(cast(I)); - if (CS && CS.getCalledFunction()) { + if (CS) { // Ignore calls to functions in the same SCC. - if (SCCNodes.count(CS.getCalledFunction())) + if (CS.getCalledFunction() && SCCNodes.count(CS.getCalledFunction())) + continue; + switch (AA->getModRefBehavior(CS)) { + case AliasAnalysis::DoesNotAccessMemory: + // Ignore calls that don't access memory. continue; - // Ignore intrinsics that only access local memory. - if (unsigned id = CS.getCalledFunction()->getIntrinsicID()) - if (AliasAnalysis::getIntrinsicModRefBehavior(id) == - AliasAnalysis::AccessesArguments) { - // Check that all pointer arguments point to local memory. - for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); - CI != CE; ++CI) { - Value *Arg = *CI; - if (Arg->getType()->isPointerTy() && - !PointsToLocalOrConstantMemory(Arg)) - // Writes memory. Just give up. - return false; - } - // Only reads and writes local memory. - continue; + case AliasAnalysis::OnlyReadsMemory: + // Handle calls that only read from memory. + ReadsMemory = true; + continue; + case AliasAnalysis::AccessesArguments: + // Check whether all pointer arguments point to local memory, and + // ignore calls that only access local memory. + for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); + CI != CE; ++CI) { + Value *Arg = *CI; + if (Arg->getType()->isPointerTy() && + !PointsToLocalOrConstantMemory(Arg)) + // Writes memory. Just give up. + return false; } + // Only reads and writes local memory. + continue; + default: + // Otherwise, be conservative. + break; + } } else if (LoadInst *LI = dyn_cast(I)) { // Ignore non-volatile loads from local memory. if (!LI->isVolatile() && @@ -387,6 +400,8 @@ } bool FunctionAttrs::runOnSCC(CallGraphSCC &SCC) { + AA = &getAnalysis(); + bool Changed = AddReadAttrs(SCC); Changed |= AddNoCaptureAttrs(SCC); Changed |= AddNoAliasAttrs(SCC); Modified: llvm/trunk/test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll?rev=118410&r1=118409&r2=118410&view=diff ============================================================================== --- llvm/trunk/test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll (original) +++ llvm/trunk/test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll Mon Nov 8 10:10:15 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -functionattrs -S | FileCheck %s +; RUN: opt < %s -basicaa -functionattrs -S | FileCheck %s %struct.X = type { i32*, i32* } From gohman at apple.com Mon Nov 8 10:11:19 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 16:11:19 -0000 Subject: [llvm-commits] [llvm] r118411 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp Message-ID: <20101108161119.D72B92A6C12C@llvm.org> Author: djg Date: Mon Nov 8 10:11:19 2010 New Revision: 118411 URL: http://llvm.org/viewvc/llvm-project?rev=118411&view=rev Log: Delete getIntrinsicModRefBehavior. Clients can just use the normal getModRefBehavior now, since it now understands intrinsics as well as normal functions. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118411&r1=118410&r2=118411&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Nov 8 10:11:19 2010 @@ -213,11 +213,6 @@ /// For use when the call site is not known. virtual ModRefBehavior getModRefBehavior(const Function *F); - /// getIntrinsicModRefBehavior - Return the modref behavior of the intrinsic - /// with the given id. Most clients won't need this, because the regular - /// getModRefBehavior incorporates this information. - static ModRefBehavior getIntrinsicModRefBehavior(unsigned iid); - /// doesNotAccessMemory - If the specified call is known to never read or /// write memory, return true. If the call only reads from known-constant /// memory, it is also legal to return true. Calls that unwind the stack Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=118411&r1=118410&r2=118411&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Nov 8 10:11:19 2010 @@ -249,13 +249,6 @@ return ModRef; } -AliasAnalysis::ModRefBehavior -AliasAnalysis::getIntrinsicModRefBehavior(unsigned iid) { -#define GET_INTRINSIC_MODREF_BEHAVIOR -#include "llvm/Intrinsics.gen" -#undef GET_INTRINSIC_MODREF_BEHAVIOR -} - // AliasAnalysis destructor: DO NOT move this to the header file for // AliasAnalysis or else clients of the AliasAnalysis class may not depend on // the AliasAnalysis.o file in the current .a file, causing alias analysis From baldrick at free.fr Mon Nov 8 10:20:33 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 17:20:33 +0100 Subject: [llvm-commits] [llvm] r118409 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: <20101108160843.B1F782A6C12C@llvm.org> References: <20101108160843.B1F782A6C12C@llvm.org> Message-ID: <4CD82351.1010207@free.fr> Hi Dan, > Teach BasicAliasAnalysis::getModRefBehavior(const Function *F) > to analyze intrinsic functions. > + // For intrinsics, we can check the table. > + if (unsigned iid = F->getIntrinsicID()) { > +#define GET_INTRINSIC_MODREF_BEHAVIOR > +#include "llvm/Intrinsics.gen" > +#undef GET_INTRINSIC_MODREF_BEHAVIOR > + } alias analysis exports this logic as AliasAnalysis::getIntrinsicModRefBehavior. Can't you just use that? Ciao, Duncan. From baldrick at free.fr Mon Nov 8 10:31:40 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 17:31:40 +0100 Subject: [llvm-commits] [llvm] r118410 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll In-Reply-To: <20101108161016.02D322A6C12C@llvm.org> References: <20101108161016.02D322A6C12C@llvm.org> Message-ID: <4CD825EC.5040300@free.fr> Hi Dan, > Make FunctionAttrs use AliasAnalysis::getModRefBehavior, now that it > knows about intrinsic functions. I always took care to *not* have function attributes make any use of alias analysis. Partly this is to have the function attributes pass stay fast, partly from a feeling that function attributes should be layered below alias analysis not on top of it, and partly because using alias analysis doesn't (or didn't in the past) win you much. That said, I can understand the temptation to have it use alias analysis - but what is the cost/benefit ratio? > @@ -167,26 +171,35 @@ > // Some instructions can be ignored even if they read or write memory. > // Detect these now, skipping to the next instruction if one is found. > CallSite CS(cast(I)); > - if (CS&& CS.getCalledFunction()) { > + if (CS) { > // Ignore calls to functions in the same SCC. > - if (SCCNodes.count(CS.getCalledFunction())) > + if (CS.getCalledFunction()&& SCCNodes.count(CS.getCalledFunction())) > + continue; Shouldn't this be: if (!CS.getCalledFunction() || SCCNodes.count(CS.getCalledFunction())) ? Ciao, Duncan. From gohman at apple.com Mon Nov 8 10:45:26 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 16:45:26 -0000 Subject: [llvm-commits] [llvm] r118412 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/NoAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-12-29-Constant.ll Message-ID: <20101108164526.CE29F2A6C12C@llvm.org> Author: djg Date: Mon Nov 8 10:45:26 2010 New Revision: 118412 URL: http://llvm.org/viewvc/llvm-project?rev=118412&view=rev Log: Extend the AliasAnalysis::pointsToConstantMemory interface to allow it to optionally look for constant or local (alloca) memory. Teach BasicAliasAnalysis::pointsToConstantMemory to look through Select and Phi nodes, and to support looking for local memory. Remove FunctionAttrs' PointsToLocalOrConstantMemory function, now that AliasAnalysis knows all the tricks that it knew. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp llvm/trunk/lib/Analysis/AliasDebugger.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/NoAliasAnalysis.cpp llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp llvm/trunk/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Nov 8 10:45:26 2010 @@ -154,15 +154,16 @@ return isNoAlias(Location(V1, V1Size), Location(V2, V2Size)); } - /// pointsToConstantMemory - If the specified memory location is known to be - /// constant, return true. This allows disambiguation of store - /// instructions from constant pointers. - /// - virtual bool pointsToConstantMemory(const Location &Loc); + /// pointsToConstantMemory - If the specified memory location is + /// known to be constant, return true. If OrLocal is true and the + /// specified memory location is known to be "local" (derived from + /// an alloca), return true. Otherwise return false. + virtual bool pointsToConstantMemory(const Location &Loc, + bool OrLocal = false); /// pointsToConstantMemory - A convenient wrapper. - bool pointsToConstantMemory(const Value *P) { - return pointsToConstantMemory(Location(P)); + bool pointsToConstantMemory(const Value *P, bool OrLocal = false) { + return pointsToConstantMemory(Location(P), OrLocal); } //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Nov 8 10:45:26 2010 @@ -49,9 +49,10 @@ return AA->alias(LocA, LocB); } -bool AliasAnalysis::pointsToConstantMemory(const Location &Loc) { +bool AliasAnalysis::pointsToConstantMemory(const Location &Loc, + bool OrLocal) { assert(AA && "AA didn't call InitializeAliasAnalysis in its run method!"); - return AA->pointsToConstantMemory(Loc); + return AA->pointsToConstantMemory(Loc, OrLocal); } void AliasAnalysis::deleteValue(Value *V) { Modified: llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp Mon Nov 8 10:45:26 2010 @@ -95,8 +95,8 @@ } // FIXME: We could count these too... - bool pointsToConstantMemory(const Location &Loc) { - return getAnalysis().pointsToConstantMemory(Loc); + bool pointsToConstantMemory(const Location &Loc, bool OrLocal) { + return getAnalysis().pointsToConstantMemory(Loc, OrLocal); } // Forwarding functions: just delegate to a real AA implementation, counting Modified: llvm/trunk/lib/Analysis/AliasDebugger.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasDebugger.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasDebugger.cpp (original) +++ llvm/trunk/lib/Analysis/AliasDebugger.cpp Mon Nov 8 10:45:26 2010 @@ -113,9 +113,9 @@ return AliasAnalysis::getModRefInfo(CS1,CS2); } - bool pointsToConstantMemory(const Location &Loc) { + bool pointsToConstantMemory(const Location &Loc, bool OrLocal) { assert(Vals.find(Loc.Ptr) != Vals.end() && "Never seen value in AA before"); - return AliasAnalysis::pointsToConstantMemory(Loc); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); } virtual void deleteValue(Value *V) { Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Nov 8 10:45:26 2010 @@ -456,7 +456,7 @@ /// pointsToConstantMemory - Chase pointers until we find a (constant /// global) or not. - virtual bool pointsToConstantMemory(const Location &Loc); + virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal); /// getModRefBehavior - Return the behavior when calling the given /// call site. @@ -517,18 +517,61 @@ return new BasicAliasAnalysis(); } +/// pointsToConstantMemory - Returns whether the given pointer value +/// points to memory that is local to the function, with global constants being +/// considered local to all functions. +bool +BasicAliasAnalysis::pointsToConstantMemory(const Location &Loc, bool OrLocal) { + assert(Visited.empty() && "Visited must be cleared after use!"); + + SmallVector Worklist; + Worklist.push_back(Loc.Ptr); + do { + const Value *V = Worklist.pop_back_val()->getUnderlyingObject(); + if (!Visited.insert(V)) { + Visited.clear(); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); + } + + // An alloca instruction defines local memory. + if (OrLocal && isa(V)) + continue; + + // A global constant counts as local memory for our purposes. + if (const GlobalVariable *GV = dyn_cast(V)) { + // Note: this doesn't require GV to be "ODR" because it isn't legal for a + // global to be marked constant in some modules and non-constant in + // others. GV may even be a declaration, not a definition. + if (!GV->isConstant()) { + Visited.clear(); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); + } + continue; + } + + // If both select values point to local memory, then so does the select. + if (const SelectInst *SI = dyn_cast(V)) { + Worklist.push_back(SI->getTrueValue()); + Worklist.push_back(SI->getFalseValue()); + continue; + } + + // If all values incoming to a phi node point to local memory, then so does + // the phi. + if (const PHINode *PN = dyn_cast(V)) { + for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) + Worklist.push_back(PN->getIncomingValue(i)); + continue; + } + + // Otherwise be conservative. + Visited.clear(); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); -/// pointsToConstantMemory - Chase pointers until we find a (constant -/// global) or not. -bool BasicAliasAnalysis::pointsToConstantMemory(const Location &Loc) { - if (const GlobalVariable *GV = - dyn_cast(Loc.Ptr->getUnderlyingObject())) - // Note: this doesn't require GV to be "ODR" because it isn't legal for a - // global to be marked constant in some modules and non-constant in others. - // GV may even be a declaration, not a definition. - return GV->isConstant(); + } while (!Worklist.empty()); - return AliasAnalysis::pointsToConstantMemory(Loc); + Visited.clear(); + return true; } /// getModRefBehavior - Return the behavior when calling the given call site. Modified: llvm/trunk/lib/Analysis/NoAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/NoAliasAnalysis.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/NoAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/NoAliasAnalysis.cpp Mon Nov 8 10:45:26 2010 @@ -50,7 +50,10 @@ return UnknownModRefBehavior; } - virtual bool pointsToConstantMemory(const Location &Loc) { return false; } + virtual bool pointsToConstantMemory(const Location &Loc, + bool OrLocal) { + return false; + } virtual ModRefResult getModRefInfo(ImmutableCallSite CS, const Location &Loc) { return ModRef; Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Mon Nov 8 10:45:26 2010 @@ -138,7 +138,7 @@ private: virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual AliasResult alias(const Location &LocA, const Location &LocB); - virtual bool pointsToConstantMemory(const Location &Loc); + virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal); virtual ModRefResult getModRefInfo(ImmutableCallSite CS, const Location &Loc); virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, @@ -225,19 +225,20 @@ return NoAlias; } -bool TypeBasedAliasAnalysis::pointsToConstantMemory(const Location &Loc) { +bool TypeBasedAliasAnalysis::pointsToConstantMemory(const Location &Loc, + bool OrLocal) { if (!EnableTBAA) - return AliasAnalysis::pointsToConstantMemory(Loc); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); const MDNode *M = Loc.TBAATag; - if (!M) return AliasAnalysis::pointsToConstantMemory(Loc); + if (!M) return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); // If this is an "immutable" type, we can assume the pointer is pointing // to constant memory. if (TBAANode(M).TypeIsImmutable()) return true; - return AliasAnalysis::pointsToConstantMemory(Loc); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); } AliasAnalysis::ModRefResult Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Mon Nov 8 10:45:26 2010 @@ -66,8 +66,6 @@ CallGraphSCCPass::getAnalysisUsage(AU); } - bool PointsToLocalOrConstantMemory(Value *V); - private: AliasAnalysis *AA; }; @@ -83,53 +81,6 @@ Pass *llvm::createFunctionAttrsPass() { return new FunctionAttrs(); } -/// PointsToLocalOrConstantMemory - Returns whether the given pointer value -/// points to memory that is local to the function, with global constants being -/// considered local to all functions. -bool FunctionAttrs::PointsToLocalOrConstantMemory(Value *V) { - SmallVector Worklist; - unsigned MaxLookup = 8; - - Worklist.push_back(V); - - do { - V = Worklist.pop_back_val()->getUnderlyingObject(); - - // An alloca instruction defines local memory. - if (isa(V)) - continue; - - // A global constant counts as local memory for our purposes. - if (GlobalVariable *GV = dyn_cast(V)) { - if (!GV->isConstant()) - return false; - continue; - } - - // If both select values point to local memory, then so does the select. - if (SelectInst *SI = dyn_cast(V)) { - Worklist.push_back(SI->getTrueValue()); - Worklist.push_back(SI->getFalseValue()); - continue; - } - - // If all values incoming to a phi node point to local memory, then so does - // the phi. - if (PHINode *PN = dyn_cast(V)) { - // Don't bother inspecting phi nodes with many operands. - if (PN->getNumIncomingValues() > MaxLookup) - return false; - for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) - Worklist.push_back(PN->getIncomingValue(i)); - continue; - } - - return false; - } while (!Worklist.empty() && --MaxLookup); - - return Worklist.empty(); -} - /// AddReadAttrs - Deduce readonly/readnone attributes for the SCC. bool FunctionAttrs::AddReadAttrs(const CallGraphSCC &SCC) { SmallPtrSet SCCNodes; @@ -190,7 +141,7 @@ CI != CE; ++CI) { Value *Arg = *CI; if (Arg->getType()->isPointerTy() && - !PointsToLocalOrConstantMemory(Arg)) + !AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) // Writes memory. Just give up. return false; } @@ -203,12 +154,14 @@ } else if (LoadInst *LI = dyn_cast(I)) { // Ignore non-volatile loads from local memory. if (!LI->isVolatile() && - PointsToLocalOrConstantMemory(LI->getPointerOperand())) + AA->pointsToConstantMemory(LI->getPointerOperand(), + /*OrLocal=*/true)) continue; } else if (StoreInst *SI = dyn_cast(I)) { // Ignore non-volatile stores to local memory. if (!SI->isVolatile() && - PointsToLocalOrConstantMemory(SI->getPointerOperand())) + AA->pointsToConstantMemory(SI->getPointerOperand(), + /*OrLocal=*/true)) continue; } Modified: llvm/trunk/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll?rev=118412&r1=118411&r2=118412&view=diff ============================================================================== --- llvm/trunk/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll (original) +++ llvm/trunk/test/Transforms/FunctionAttrs/2008-12-29-Constant.ll Mon Nov 8 10:45:26 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -functionattrs -S | grep readnone +; RUN: opt < %s -basicaa -functionattrs -S | grep readnone @s = external constant i8 ; [#uses=1] From jason.w.kim.2009 at gmail.com Mon Nov 8 10:47:27 2010 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Mon, 08 Nov 2010 16:47:27 -0000 Subject: [llvm-commits] [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h Message-ID: <20101108164727.39B812A6C12C@llvm.org> Author: jasonwkim Date: Mon Nov 8 10:47:27 2010 New Revision: 118413 URL: http://llvm.org/viewvc/llvm-project?rev=118413&view=rev Log: Complete listing of ARM/MC/ELF relocation enums Modified: llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h?rev=118413&r1=118412&r2=118413&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h Mon Nov 8 10:47:27 2010 @@ -21,10 +21,141 @@ class ARMELFWriterInfo : public TargetELFWriterInfo { // ELF Relocation types for ARM - // FIXME: TODO(jasonwkim): [2010/09/17 14:52:25 PDT (Friday)] - // Come up with a better way to orgnize the 100+ ARM reloc types. - + // Meets 2.08 ABI Specs. Most of these are not used by the assembler. + // They are here for completeness's sake + enum ARMRelocationType { + R_ARM_NONE = 0x00, + R_ARM_PC24 = 0x01, + R_ARM_ABS32 = 0x02, + R_ARM_REL32 = 0x03, + R_ARM_LDR_PC_G0 = 0x04, + R_ARM_ABS16 = 0x05, + R_ARM_ABS12 = 0x06, + R_ARM_THM_ABS5 = 0x07, + R_ARM_ABS8 = 0x08, + R_ARM_SBREL32 = 0x09, + R_ARM_THM_CALL = 0x0a, + R_ARM_THM_PC8 = 0x0b, + R_ARM_BREL_ADJ = 0x0c, + R_ARM_TLS_DESC = 0x0d, + R_ARM_THM_SWI8 = 0x0e, + R_ARM_XPC25 = 0x0f, + R_ARM_THM_XPC22 = 0x10, + R_ARM_TLS_DTPMOD32 = 0x11, + R_ARM_TLS_DTPOFF32 = 0x12, + R_ARM_TLS_TPOFF32 = 0x13, + R_ARM_COPY = 0x14, + R_ARM_GLOB_DAT = 0x15, + R_ARM_JUMP_SLOT = 0x16, + R_ARM_RELATIVE = 0x17, + R_ARM_GOTOFF32 = 0x18, + R_ARM_BASE_PREL = 0x19, + R_ARM_GOT_BREL = 0x1a, + R_ARM_PLT32 = 0x1b, + R_ARM_CALL = 0x1c, + R_ARM_JUMP24 = 0x1d, + R_ARM_THM_JUMP24 = 0x1e, + R_ARM_BASE_ABS = 0x1f, + R_ARM_ALU_PCREL_7_0 = 0x20, + R_ARM_ALU_PCREL_15_8 = 0x21, + R_ARM_ALU_PCREL_23_15 = 0x22, + R_ARM_LDR_SBREL_11_0_NC = 0x23, + R_ARM_ALU_SBREL_19_12_NC = 0x24, + R_ARM_ALU_SBREL_27_20_CK = 0x25, + R_ARM_TARGET1 = 0x26, + R_ARM_SBREL31 = 0x27, + R_ARM_V4BX = 0x28, + R_ARM_TARGET2 = 0x29, + R_ARM_PREL31 = 0x2a, + R_ARM_MOVW_ABS_NC = 0x2b, + R_ARM_MOVT_ABS = 0x2c, + R_ARM_MOVW_PREL_NC = 0x2d, + R_ARM_MOVT_PREL = 0x2e, + R_ARM_THM_MOVW_ABS_NC = 0x2f, + R_ARM_THM_MOVT_ABS = 0x30, + R_ARM_THM_MOVW_PREL_NC = 0x31, + R_ARM_THM_MOVT_PREL = 0x32, + R_ARM_THM_JUMP19 = 0x33, + R_ARM_THM_JUMP6 = 0x34, + R_ARM_THM_ALU_PREL_11_0 = 0x35, + R_ARM_THM_PC12 = 0x36, + R_ARM_ABS32_NOI = 0x37, + R_ARM_REL32_NOI = 0x38, + R_ARM_ALU_PC_G0_NC = 0x39, + R_ARM_ALU_PC_G0 = 0x3a, + R_ARM_ALU_PC_G1_NC = 0x3b, + R_ARM_ALU_PC_G1 = 0x3c, + R_ARM_ALU_PC_G2 = 0x3d, + R_ARM_LDR_PC_G1 = 0x3e, + R_ARM_LDR_PC_G2 = 0x3f, + R_ARM_LDRS_PC_G0 = 0x40, + R_ARM_LDRS_PC_G1 = 0x41, + R_ARM_LDRS_PC_G2 = 0x42, + R_ARM_LDC_PC_G0 = 0x43, + R_ARM_LDC_PC_G1 = 0x44, + R_ARM_LDC_PC_G2 = 0x45, + R_ARM_ALU_SB_G0_NC = 0x46, + R_ARM_ALU_SB_G0 = 0x47, + R_ARM_ALU_SB_G1_NC = 0x48, + R_ARM_ALU_SB_G1 = 0x49, + R_ARM_ALU_SB_G2 = 0x4a, + R_ARM_LDR_SB_G0 = 0x4b, + R_ARM_LDR_SB_G1 = 0x4c, + R_ARM_LDR_SB_G2 = 0x4d, + R_ARM_LDRS_SB_G0 = 0x4e, + R_ARM_LDRS_SB_G1 = 0x4f, + R_ARM_LDRS_SB_G2 = 0x50, + R_ARM_LDC_SB_G0 = 0x51, + R_ARM_LDC_SB_G1 = 0x52, + R_ARM_LDC_SB_G2 = 0x53, + R_ARM_MOVW_BREL_NC = 0x54, + R_ARM_MOVT_BREL = 0x55, + R_ARM_MOVW_BREL = 0x56, + R_ARM_THM_MOVW_BREL_NC = 0x57, + R_ARM_THM_MOVT_BREL = 0x58, + R_ARM_THM_MOVW_BREL = 0x59, + R_ARM_TLS_GOTDESC = 0x5a, + R_ARM_TLS_CALL = 0x5b, + R_ARM_TLS_DESCSEQ = 0x5c, + R_ARM_THM_TLS_CALL = 0x5d, + R_ARM_PLT32_ABS = 0x5e, + R_ARM_GOT_ABS = 0x5f, + R_ARM_GOT_PREL = 0x60, + R_ARM_GOT_BREL12 = 0x61, + R_ARM_GOTOFF12 = 0x62, + R_ARM_GOTRELAX = 0x63, + R_ARM_GNU_VTENTRY = 0x64, + R_ARM_GNU_VTINHERIT = 0x65, + R_ARM_THM_JUMP11 = 0x66, + R_ARM_THM_JUMP8 = 0x67, + R_ARM_TLS_GD32 = 0x68, + R_ARM_TLS_LDM32 = 0x69, + R_ARM_TLS_LDO32 = 0x6a, + R_ARM_TLS_IE32 = 0x6b, + R_ARM_TLS_LE32 = 0x6c, + R_ARM_TLS_LDO12 = 0x6d, + R_ARM_TLS_LE12 = 0x6e, + R_ARM_TLS_IE12GP = 0x6f, + R_ARM_PRIVATE_0 = 0x70, + R_ARM_PRIVATE_1 = 0x71, + R_ARM_PRIVATE_2 = 0x72, + R_ARM_PRIVATE_3 = 0x73, + R_ARM_PRIVATE_4 = 0x74, + R_ARM_PRIVATE_5 = 0x75, + R_ARM_PRIVATE_6 = 0x76, + R_ARM_PRIVATE_7 = 0x77, + R_ARM_PRIVATE_8 = 0x78, + R_ARM_PRIVATE_9 = 0x79, + R_ARM_PRIVATE_10 = 0x7a, + R_ARM_PRIVATE_11 = 0x7b, + R_ARM_PRIVATE_12 = 0x7c, + R_ARM_PRIVATE_13 = 0x7d, + R_ARM_PRIVATE_14 = 0x7e, + R_ARM_PRIVATE_15 = 0x7f, + R_ARM_ME_TOO = 0x80, + R_ARM_THM_TLS_DESCSEQ16 = 0x81, + R_ARM_THM_TLS_DESCSEQ32 = 0x82 }; public: From gohman at apple.com Mon Nov 8 11:10:22 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 17:10:22 -0000 Subject: [llvm-commits] [llvm] r118416 - /llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Message-ID: <20101108171022.5A5172A6C12C@llvm.org> Author: djg Date: Mon Nov 8 11:10:22 2010 New Revision: 118416 URL: http://llvm.org/viewvc/llvm-project?rev=118416&view=rev Log: Implement getModRefBehavior for TypeBasedAliasAnalysis. Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=118416&r1=118415&r2=118416&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Mon Nov 8 11:10:22 2010 @@ -139,6 +139,8 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual AliasResult alias(const Location &LocA, const Location &LocB); virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal); + virtual ModRefBehavior getModRefBehavior(ImmutableCallSite CS); + virtual ModRefBehavior getModRefBehavior(const Function *F); virtual ModRefResult getModRefInfo(ImmutableCallSite CS, const Location &Loc); virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, @@ -241,6 +243,27 @@ return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); } +AliasAnalysis::ModRefBehavior +TypeBasedAliasAnalysis::getModRefBehavior(ImmutableCallSite CS) { + if (!EnableTBAA) + return AliasAnalysis::getModRefBehavior(CS); + + ModRefBehavior Min = UnknownModRefBehavior; + + // If this is an "immutable" type, we can assume the call doesn't write + // to memory. + if (const MDNode *M = CS.getInstruction()->getMetadata(LLVMContext::MD_tbaa)) + if (TBAANode(M).TypeIsImmutable()) + Min = OnlyReadsMemory; + + return std::min(AliasAnalysis::getModRefBehavior(CS), Min); +} + +AliasAnalysis::ModRefBehavior +TypeBasedAliasAnalysis::getModRefBehavior(const Function *F) { + return AliasAnalysis::getModRefBehavior(F); +} + AliasAnalysis::ModRefResult TypeBasedAliasAnalysis::getModRefInfo(ImmutableCallSite CS, const Location &Loc) { From gohman at apple.com Mon Nov 8 11:12:04 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 17:12:04 -0000 Subject: [llvm-commits] [llvm] r118417 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Message-ID: <20101108171204.51D092A6C12C@llvm.org> Author: djg Date: Mon Nov 8 11:12:04 2010 New Revision: 118417 URL: http://llvm.org/viewvc/llvm-project?rev=118417&view=rev Log: Make FunctionAttrs TBAA-aware. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118417&r1=118416&r2=118417&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Mon Nov 8 11:12:04 2010 @@ -23,6 +23,7 @@ #include "llvm/CallGraphSCCPass.h" #include "llvm/GlobalVariable.h" #include "llvm/IntrinsicInst.h" +#include "llvm/LLVMContext.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/CallGraph.h" #include "llvm/Analysis/CaptureTracking.h" @@ -140,10 +141,14 @@ for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); CI != CE; ++CI) { Value *Arg = *CI; - if (Arg->getType()->isPointerTy() && - !AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) - // Writes memory. Just give up. - return false; + if (Arg->getType()->isPointerTy()) { + AliasAnalysis::Location Loc(Arg, + AliasAnalysis::UnknownSize, + I->getMetadata(LLVMContext::MD_tbaa)); + if (!AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) + // Writes memory. Just give up. + return false; + } } // Only reads and writes local memory. continue; @@ -153,16 +158,23 @@ } } else if (LoadInst *LI = dyn_cast(I)) { // Ignore non-volatile loads from local memory. - if (!LI->isVolatile() && - AA->pointsToConstantMemory(LI->getPointerOperand(), - /*OrLocal=*/true)) - continue; + if (!LI->isVolatile()) { + AliasAnalysis::Location Loc(LI->getPointerOperand(), + AA->getTypeStoreSize(LI->getType()), + LI->getMetadata(LLVMContext::MD_tbaa)); + if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) + continue; + } } else if (StoreInst *SI = dyn_cast(I)) { // Ignore non-volatile stores to local memory. - if (!SI->isVolatile() && - AA->pointsToConstantMemory(SI->getPointerOperand(), - /*OrLocal=*/true)) - continue; + if (!SI->isVolatile()) { + const Type *StoredType = SI->getValueOperand()->getType(); + AliasAnalysis::Location Loc(SI->getPointerOperand(), + AA->getTypeStoreSize(StoredType), + SI->getMetadata(LLVMContext::MD_tbaa)); + if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) + continue; + } } // Any remaining instructions need to be taken seriously! Check if they Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll?rev=118417&view=auto ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll (added) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Mon Nov 8 11:12:04 2010 @@ -0,0 +1,37 @@ +; RUN: opt < %s -enable-tbaa -tbaa -basicaa -functionattrs -S | FileCheck %s + +; FunctionAttrs should make use of TBAA. + +; CHECK: define void @test0_yes(i32* nocapture %p) nounwind readnone { +define void @test0_yes(i32* %p) nounwind { + store i32 0, i32* %p, !tbaa !1 + ret void +} + +; CHECK: define void @test0_no(i32* nocapture %p) nounwind { +define void @test0_no(i32* %p) nounwind { + store i32 0, i32* %p, !tbaa !2 + ret void +} + +; CHECK: define void @test1_yes(i32* %p) nounwind readonly { +define void @test1_yes(i32* %p) nounwind { + call void @callee(i32* %p), !tbaa !1 + ret void +} + +; CHECK: define void @test1_no(i32* %p) nounwind { +define void @test1_no(i32* %p) nounwind { + call void @callee(i32* %p), !tbaa !2 + ret void +} + +declare void @callee(i32* %p) nounwind + +; Root note. +!0 = metadata !{ } + +; Invariant memory. +!1 = metadata !{ metadata !"foo", metadata !0, i1 1 } +; Not invariant memory. +!2 = metadata !{ metadata !"foo", metadata !0, i1 0 } From baldrick at free.fr Mon Nov 8 11:43:02 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 18:43:02 +0100 Subject: [llvm-commits] [llvm] r118412 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/NoAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-12-29-Constant.ll In-Reply-To: <20101108164526.CE29F2A6C12C@llvm.org> References: <20101108164526.CE29F2A6C12C@llvm.org> Message-ID: <4CD836A6.1070207@free.fr> Hi Dan, > +/// pointsToConstantMemory - Returns whether the given pointer value > +/// points to memory that is local to the function, with global constants being > +/// considered local to all functions. > +bool > +BasicAliasAnalysis::pointsToConstantMemory(const Location&Loc, bool OrLocal) { > + assert(Visited.empty()&& "Visited must be cleared after use!"); > + > + SmallVector Worklist; > + Worklist.push_back(Loc.Ptr); you should really put a limit on how deep you want to allow the "recursion" to go. IIRC, the reason that PointsToLocalOrConstantMemory had a limit is that it was seen to take a long time on some crazy testcase. Ciao, Duncan. From baldrick at free.fr Mon Nov 8 11:46:20 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 18:46:20 +0100 Subject: [llvm-commits] [llvm] r118417 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll In-Reply-To: <20101108171204.51D092A6C12C@llvm.org> References: <20101108171204.51D092A6C12C@llvm.org> Message-ID: <4CD8376C.6060604@free.fr> Hi Dan, > @@ -140,10 +141,14 @@ > for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); > CI != CE; ++CI) { > Value *Arg = *CI; > - if (Arg->getType()->isPointerTy()&& > - !AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) > - // Writes memory. Just give up. > - return false; > + if (Arg->getType()->isPointerTy()) { > + AliasAnalysis::Location Loc(Arg, > + AliasAnalysis::UnknownSize, > + I->getMetadata(LLVMContext::MD_tbaa)); > + if (!AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) Shouldn't it be Loc not Arg in the call to pointsToConstantMemory? Ciao, Duncan. From stoklund at 2pi.dk Mon Nov 8 11:50:06 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 08 Nov 2010 17:50:06 -0000 Subject: [llvm-commits] [zorg] r118420 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20101108175006.4B5D82A6C12C@llvm.org> Author: stoklund Date: Mon Nov 8 11:50:06 2010 New Revision: 118420 URL: http://llvm.org/viewvc/llvm-project?rev=118420&view=rev Log: Allow llvm_source_version to be None when the source directory is not a svn checkout. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=118420&r1=118419&r2=118420&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Mon Nov 8 11:50:06 2010 @@ -156,7 +156,8 @@ # Set LLVM_RELEASE_IS_PLUS_ASSERTS when appropriate, to allow testing older # LLVM source trees. - if llvm_source_version.isdigit() and int(llvm_source_version) < 107758: + if (llvm_source_version and llvm_source_version.isdigit() and + int(llvm_source_version) < 107758): make_variables['LLVM_RELEASE_IS_PLUS_ASSERTS'] = 1 # Set ARCH appropriately, based on the inferred target. From daniel at zuster.org Mon Nov 8 11:53:02 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 08 Nov 2010 17:53:02 -0000 Subject: [llvm-commits] [llvm] r118421 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20101108175302.303E52A6C12C@llvm.org> Author: ddunbar Date: Mon Nov 8 11:53:02 2010 New Revision: 118421 URL: http://llvm.org/viewvc/llvm-project?rev=118421&view=rev Log: Fix typo. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=118421&r1=118420&r2=118421&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Nov 8 11:53:02 2010 @@ -503,7 +503,7 @@ // semantics in the face of reassignment. if (Sym->isVariable() && isa(Sym->getVariableValue())) { if (Variant) - return Error(EndLoc, "unexpected modified on variable reference"); + return Error(EndLoc, "unexpected modifier on variable reference"); Res = Sym->getVariableValue(); return false; From jason.w.kim.2009 at gmail.com Mon Nov 8 11:58:07 2010 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Mon, 08 Nov 2010 17:58:07 -0000 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Message-ID: <20101108175807.8543A2A6C12C@llvm.org> Author: jasonwkim Date: Mon Nov 8 11:58:07 2010 New Revision: 118422 URL: http://llvm.org/viewvc/llvm-project?rev=118422&view=rev Log: Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118422&r1=118421&r2=118422&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Nov 8 11:58:07 2010 @@ -74,6 +74,7 @@ public: virtual void MaybeSwitchVendor(StringRef Vendor) = 0; virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0; + virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; virtual void Finish() = 0; virtual ~AttributeEmitter() {} }; @@ -90,6 +91,10 @@ Twine(Attribute) + ", " + Twine(Value)); } + void EmitTextAttribute(unsigned Attribute, StringRef String) { + assert(0 && "Unsupported use of text attribute"); + } + void Finish() { } }; @@ -123,6 +128,12 @@ Contents += Value; } + void EmitTextAttribute(unsigned Attribute, StringRef String) { + Contents += Attribute; + Contents += String; + Contents += 0; + } + void Finish() { const size_t ContentsSize = Contents.size(); @@ -598,28 +609,51 @@ if (CPUString != "generic") OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString); } else { - assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o"); - // FIXME: Why these defaults? - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); - AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1); - AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1); + if (CPUString != "generic") { + if (CPUString == "cortex-a8") { + AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "CORTEX-A8"); + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, + ARMBuildAttrs::ApplicationProfile); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, + ARMBuildAttrs::Allowed); + AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, + ARMBuildAttrs::AllowThumb32); + // Fixme: figure out when this is emitted. + //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch, + // ARMBuildAttrs::AllowWMMXv1); + } + } else { + // FIXME: Why these defaults? + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, + ARMBuildAttrs::Allowed); + AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, + ARMBuildAttrs::Allowed); + } } // FIXME: Emit FPU type if (Subtarget->hasVFP2()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2); + AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, + ARMBuildAttrs::AllowFPv2); // Signal various FP modes. if (!UnsafeFPMath) { - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1); - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, + ARMBuildAttrs::Allowed); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, + ARMBuildAttrs::Allowed); } if (NoInfsFPMath && NoNaNsFPMath) - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, + ARMBuildAttrs::Allowed); else - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, + ARMBuildAttrs::AllowIEE754); + // FIXME: add more flags to ARMBuildAttrs.h // 8-bytes alignment stuff. AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1); AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1); Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=118422&r1=118421&r2=118422&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Mon Nov 8 11:58:07 2010 @@ -92,6 +92,40 @@ v7E_M = 13 // v7_M with DSP extensions }; + enum CPUArchProfile { // (=7), uleb128 + Not_Applicable = 0, // pre v7, or cross-profile code + ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8) + RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4) + MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3) + SystemProfile = (0x53) // 'S' Application or real-time profile + }; + + // The following have a lot of common use cases + enum { + //ARMISAUse (=8), uleb128 and THUMBISAUse (=9), uleb128 + Not_Allowed = 0, + Allowed = 1, + + // FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10) + AllowFPv2 = 2, // v2 FP ISA permitted (implies use of the v1 FP ISA) + AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA) + AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31 + AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA) + AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31 + + // Tag_WMMX_arch, (=11), uleb128 + AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions) + + // Tag_WMMX_arch, (=11), uleb128 + AllowWMMXv1 = 2, // The user permitted this entity to use WMMX v2 + + // Tag_ABI_FP_denormal, (=20), uleb128 + PreserveFPSign = 2, // sign when flushed-to-zero is preserved + + // Tag_ABI_FP_number_model, (=23), uleb128 + AllowRTABI = 2, // numbers, infinities, and one quiet NaN (see [RTABI]) + AllowIEE754 = 3 // this code to use all the IEEE 754-defined FP encodings + }; } #endif // __TARGET_ARMBUILDATTRS_H__ Modified: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=118422&r1=118421&r2=118422&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Mon Nov 8 11:58:07 2010 @@ -1,18 +1,35 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s +; RUN: llc %s -march=arm -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \ +; RUN: -arm-reserve-r9 -arm-use-movt -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s + + ; This tests that the extpected ARM attributes are emitted. ; -; CHECK: .ARM.attributes -; CHECK-NEXT: 0x70000003 -; CHECK-NEXT: 0x00000000 -; CHECK-NEXT: 0x00000000 -; CHECK-NEXT: 0x0000003c -; CHECK-NEXT: 0x00000022 -; CHECK-NEXT: 0x00000000 -; CHECK-NEXT: 0x00000000 -; CHECK-NEXT: 0x00000001 -; CHECK-NEXT: 0x00000000 -; CHECK-NEXT: '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' +; BASIC: .ARM.attributes +; BASIC-NEXT: 0x70000003 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x0000003c +; BASIC-NEXT: 0x00000022 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x00000001 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' + +; CORTEXA8: .ARM.attributes +; CORTEXA8-NEXT: 0x70000003 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x0000003c +; CORTEXA8-NEXT: 0x00000031 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x00000001 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: '41300000 00616561 62690001 26000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 0119012c 01' define i32 @f(i64 %z) { ret i32 0 From atrick at apple.com Mon Nov 8 12:02:08 2010 From: atrick at apple.com (Andrew Trick) Date: Mon, 08 Nov 2010 18:02:08 -0000 Subject: [llvm-commits] [llvm] r118423 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp Message-ID: <20101108180208.E86302A6C12C@llvm.org> Author: atrick Date: Mon Nov 8 12:02:08 2010 New Revision: 118423 URL: http://llvm.org/viewvc/llvm-project?rev=118423&view=rev Log: Adds support for spilling previously allocated live intervals to handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=118423&r1=118422&r2=118423&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Mon Nov 8 12:02:08 2010 @@ -20,6 +20,44 @@ #include using namespace llvm; +// Find the first segment in the range [segBegin,segments_.end()) that +// intersects with seg. If no intersection is found, return the first segI +// such that segI.start >= seg.end +// +// This logic is tied to the underlying LiveSegments data structure. For now, we +// use set::upper_bound to find the nearest starting position, +// then reverse iterate to find the first overlap. +// +// Upon entry we have segBegin.start < seg.end +// seg |--... +// \ . +// lvr ...-| +// +// After set::upper_bound, we have segI.start >= seg.start: +// seg |--... +// / +// lvr |--... +// +// Assuming intervals are disjoint, if an intersection exists, it must be the +// segment found or the one immediately preceeding it. We continue reverse +// iterating to return the first overlapping segment. +LiveIntervalUnion::SegmentIter +LiveIntervalUnion::upperBound(SegmentIter segBegin, + const LiveSegment &seg) { + assert(seg.end > segBegin->start && "segment iterator precondition"); + // get the next LIU segment such that segI->start is not less than seg.start + // + // FIXME: Once we have a B+tree, we can make good use of segBegin as a hint to + // upper_bound. For now, we're forced to search again from the root each time. + SegmentIter segI = segments_.upper_bound(seg); + while (segI != segBegin) { + --segI; + if (seg.start >= segI->end) + return ++segI; + } + return segI; +} + // Merge a LiveInterval's segments. Guarantee no overlaps. // // Consider coalescing adjacent segments to save space, even though it makes @@ -29,7 +67,7 @@ SegmentIter segPos = segments_.begin(); for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end(); lvrI != lvrEnd; ++lvrI ) { - LiveSegment segment(lvrI->start, lvrI->end, lvr); + LiveSegment segment(lvrI->start, lvrI->end, &lvr); segPos = segments_.insert(segPos, segment); assert(*segPos == segment && "need equal val for equal key"); #ifndef NDEBUG @@ -47,40 +85,17 @@ } } -// Low-level helper to find the first segment in the range [segI,segEnd) that -// intersects with a live virtual register segment, or segI.start >= lvr.end -// -// This logic is tied to the underlying LiveSegments data structure. For now, we -// use a binary search within the vector to find the nearest starting position, -// then reverse iterate to find the first overlap. -// -// Upon entry we have segI.start < lvrSeg.end -// seg |--... -// \ . -// lvr ...-| -// -// After binary search, we have segI.start >= lvrSeg.start: -// seg |--... -// / -// lvr |--... -// -// Assuming intervals are disjoint, if an intersection exists, it must be the -// segment found or immediately behind it. We continue reverse iterating to -// return the first overlap. -typedef LiveIntervalUnion::SegmentIter SegmentIter; -static SegmentIter upperBound(SegmentIter segBegin, - SegmentIter segEnd, - const LiveRange &lvrSeg) { - assert(lvrSeg.end > segBegin->start && "segment iterator precondition"); - // get the next LIU segment such that setg.start is not less than - // lvrSeg.start - SegmentIter segI = std::upper_bound(segBegin, segEnd, lvrSeg.start); - while (segI != segBegin) { - --segI; - if (lvrSeg.start >= segI->end) - return ++segI; +// Remove a live virtual register's segments from this union. +void LiveIntervalUnion::extract(const LiveInterval &lvr) { + // Remove each of the virtual register's live segments from the map. + SegmentIter segPos = segments_.begin(); + for (LiveInterval::const_iterator lvrI = lvr.begin(), lvrEnd = lvr.end(); + lvrI != lvrEnd; ++lvrI) { + LiveSegment seg(lvrI->start, lvrI->end, const_cast(&lvr)); + segPos = upperBound(segPos, seg); + assert(segPos != segments_.end() && "missing lvr segment"); + segments_.erase(segPos++); } - return segI; } // Private interface accessed by Query. @@ -102,8 +117,8 @@ // Assumes that segments are sorted by start position in both // LiveInterval and LiveSegments. void LiveIntervalUnion::Query::findIntersection(InterferenceResult &ir) const { - LiveInterval::iterator lvrEnd = lvr_.end(); - SegmentIter liuEnd = liu_.end(); + LiveInterval::iterator lvrEnd = lvr_->end(); + SegmentIter liuEnd = liu_->end(); while (ir.liuSegI_ != liuEnd) { // Slowly advance the live virtual reg iterator until we surpass the next // segment in this union. If this is ever used for coalescing of fixed @@ -115,7 +130,8 @@ break; // lvrSegI_ may have advanced far beyond liuSegI_, // do a fast intersection test to "catch up" - ir.liuSegI_ = upperBound(ir.liuSegI_, liuEnd, *ir.lvrSegI_); + LiveSegment seg(ir.lvrSegI_->start, ir.lvrSegI_->end, lvr_); + ir.liuSegI_ = liu_->upperBound(ir.liuSegI_, seg); // Check if no liuSegI_ exists with lvrSegI_->start < liuSegI_.end if (ir.liuSegI_ == liuEnd) break; @@ -135,7 +151,7 @@ if (firstInterference_ != LiveIntervalUnion::InterferenceResult()) { return firstInterference_; } - firstInterference_ = InterferenceResult(lvr_.begin(), liu_.begin()); + firstInterference_ = InterferenceResult(lvr_->begin(), liu_->begin()); findIntersection(firstInterference_); return firstInterference_; } @@ -147,12 +163,12 @@ // Advance either the lvr or liu segment to ensure that we visit all unique // overlapping pairs. if (ir.lvrSegI_->end < ir.liuSegI_->end) { - if (++ir.lvrSegI_ == lvr_.end()) + if (++ir.lvrSegI_ == lvr_->end()) return false; } else { - if (++ir.liuSegI_ == liu_.end()) { - ir.lvrSegI_ = lvr_.end(); + if (++ir.liuSegI_ == liu_->end()) { + ir.lvrSegI_ = lvr_->end(); return false; } } Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118423&r1=118422&r2=118423&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Mon Nov 8 12:02:08 2010 @@ -38,8 +38,8 @@ SlotIndex end; LiveInterval *liveVirtReg; - LiveSegment(SlotIndex s, SlotIndex e, LiveInterval &lvr) - : start(s), end(e), liveVirtReg(&lvr) {} + LiveSegment(SlotIndex s, SlotIndex e, LiveInterval *lvr) + : start(s), end(e), liveVirtReg(lvr) {} bool operator==(const LiveSegment &ls) const { return start == ls.start && end == ls.end && liveVirtReg == ls.liveVirtReg; @@ -111,12 +111,16 @@ SegmentIter begin() { return segments_.begin(); } SegmentIter end() { return segments_.end(); } + // Return an iterator to the first segment after or including begin that + // intersects with lvrSeg. + SegmentIter upperBound(SegmentIter begin, const LiveSegment &seg); + // Add a live virtual register to this union and merge its segments. // Holds a nonconst reference to the LVR for later maniplution. void unify(LiveInterval &lvr); - // FIXME: needed by RegAllocGreedy - //void extract(const LiveInterval &li); + // Remove a live virtual register's segments from this union. + void extract(const LiveInterval &lvr); /// Cache a single interference test result in the form of two intersecting /// segments. This allows efficiently iterating over the interferences. The @@ -143,7 +147,7 @@ const LiveInterval::iterator &lvrSegPos() const { return lvrSegI_; } // Access the liu segment. - const SegmentIter &liuSeg() const { return liuSegI_; } + const SegmentIter &liuSegPos() const { return liuSegI_; } bool operator==(const InterferenceResult &ir) const { return lvrSegI_ == ir.lvrSegI_ && liuSegI_ == ir.liuSegI_; @@ -156,18 +160,40 @@ /// Query interferences between a single live virtual register and a live /// interval union. class Query { - LiveIntervalUnion &liu_; - LiveInterval &lvr_; + LiveIntervalUnion *liu_; + LiveInterval *lvr_; InterferenceResult firstInterference_; // TBD: interfering vregs public: - Query(LiveInterval &lvr, LiveIntervalUnion &liu): liu_(liu), lvr_(lvr) {} + Query(): liu_(), lvr_() {} + + Query(LiveInterval *lvr, LiveIntervalUnion *liu): liu_(liu), lvr_(lvr) {} + + void clear() { + liu_ = NULL; + lvr_ = NULL; + firstInterference_ = InterferenceResult(); + } + + void init(LiveInterval *lvr, LiveIntervalUnion *liu) { + if (lvr_ == lvr) { + // We currently allow query objects to be reused acrossed live virtual + // registers, but always for the same live interval union. + assert(liu_ == liu && "inconsistent initialization"); + // Retain cached results, e.g. firstInterference. + return; + } + liu_ = liu; + lvr_ = lvr; + // Clear cached results. + firstInterference_ = InterferenceResult(); + } - LiveInterval &lvr() const { return lvr_; } + LiveInterval &lvr() const { assert(lvr_ && "uninitialized"); return *lvr_; } bool isInterference(const InterferenceResult &ir) const { - if (ir.lvrSegI_ != lvr_.end()) { + if (ir.lvrSegI_ != lvr_->end()) { assert(overlap(*ir.lvrSegI_, *ir.liuSegI_) && "invalid segment iterators"); return true; @@ -178,7 +204,8 @@ // Does this live virtual register interfere with the union. bool checkInterference() { return isInterference(firstInterference()); } - // First pair of interfering segments, or a noninterfering result. + // Get the first pair of interfering segments, or a noninterfering result. + // This initializes the firstInterference_ cache. InterferenceResult firstInterference(); // Treat the result as an iterator and advance to the next interfering pair Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=118423&r1=118422&r2=118423&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Mon Nov 8 12:02:08 2010 @@ -94,6 +94,10 @@ LiveIntervals *lis_; LIUArray physReg2liu_; + // Current queries, one per physreg. They must be reinitialized each time we + // query on a new live virtual register. + OwningArrayPtr queries_; + RegAllocBase(): tri_(0), vrm_(0), lis_(0) {} virtual ~RegAllocBase() {} @@ -120,9 +124,15 @@ virtual void releaseMemory(); // Helper for checking interference between a live virtual register and a - // physical register, including all its register aliases. - bool checkPhysRegInterference(LiveIntervalUnion::Query &query, unsigned preg); - + // physical register, including all its register aliases. If an interference + // exists, return the interfering register, which may be preg or an alias. + unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg); + + // Helper that spills all live virtual registers currently unified under preg + // that interfere with the most recently queried lvr. + void spillInterferences(unsigned preg, + SmallVectorImpl &splitLVRs); + private: void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ); }; Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118423&r1=118422&r2=118423&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Mon Nov 8 12:02:08 2010 @@ -17,10 +17,12 @@ #include "RegAllocBase.h" #include "RenderMachineFunction.h" #include "Spiller.h" +#include "VirtRegMap.h" #include "VirtRegRewriter.h" #include "llvm/Function.h" #include "llvm/PassAnalysisSupport.h" #include "llvm/CodeGen/CalcSpillWeights.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" @@ -31,14 +33,11 @@ #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "VirtRegMap.h" -#include "llvm/CodeGen/LiveIntervalAnalysis.h" -#include "llvm/Target/TargetRegisterInfo.h" - - #include #include @@ -84,6 +83,9 @@ virtual unsigned selectOrSplit(LiveInterval &lvr, SmallVectorImpl &splitLVRs); + void spillInterferences(unsigned preg, + SmallVectorImpl &splitLVRs); + /// Perform register allocation. virtual bool runOnMachineFunction(MachineFunction &mf); @@ -170,6 +172,8 @@ vrm_ = &vrm; lis_ = &lis; physReg2liu_.init(tri_->getNumRegs()); + // Cache an interferece query for each physical reg + queries_.reset(new LiveIntervalUnion::Query[physReg2liu_.numRegs()]); } void RegAllocBase::LIUArray::clear() { @@ -238,38 +242,61 @@ LVRVec splitLVRs; unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs); if (availablePhysReg) { - assert(splitLVRs.empty() && "inconsistent splitting"); + DEBUG(dbgs() << "allocating: " << tri_->getName(availablePhysReg) << + " " << lvr << '\n'); assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions"); vrm_->assignVirt2Phys(lvr->reg, availablePhysReg); physReg2liu_[availablePhysReg].unify(*lvr); } - else { - for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end(); - lvrI != lvrEnd; ++lvrI) { - assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) && - "expect split value in virtual register"); - lvrQ.push(*lvrI); - } + for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end(); + lvrI != lvrEnd; ++lvrI) { + DEBUG(dbgs() << "queuing new interval: " << **lvrI << "\n"); + assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) && + "expect split value in virtual register"); + lvrQ.push(*lvrI); } } } // Check if this live virtual reg interferes with a physical register. If not, // then check for interference on each register that aliases with the physical -// register. -bool RegAllocBase::checkPhysRegInterference(LiveIntervalUnion::Query &query, - unsigned preg) { - if (query.checkInterference()) - return true; +// register. Return the interfering register. +unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &lvr, + unsigned preg) { + queries_[preg].init(&lvr, &physReg2liu_[preg]); + if (queries_[preg].checkInterference()) + return preg; for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) { - // We assume it's very unlikely for a register in the alias set to also be - // in the original register class. So we don't bother caching the - // interference. - LiveIntervalUnion::Query subQuery(query.lvr(), physReg2liu_[*asI] ); - if (subQuery.checkInterference()) - return true; + queries_[*asI].init(&lvr, &physReg2liu_[*asI]); + if (queries_[*asI].checkInterference()) + return *asI; } - return false; + return 0; +} + +// Spill all live virtual registers currently unified under preg that interfere +// with lvr. +void RABasic::spillInterferences(unsigned preg, + SmallVectorImpl &splitLVRs) { + SmallPtrSet spilledLVRs; + LiveIntervalUnion::Query &query = queries_[preg]; + LiveIntervalUnion::InterferenceResult ir = query.firstInterference(); + assert(query.isInterference(ir) && "expect interference"); + do { + LiveInterval *lvr = ir.liuSegPos()->liveVirtReg; + if (!spilledLVRs.insert(lvr)) continue; + // Spill the previously allocated lvr. + SmallVector spillIs; // ignored + spiller_->spill(lvr, splitLVRs, spillIs); + } while (query.nextInterference(ir)); + for (SmallPtrSetIterator lvrI = spilledLVRs.begin(), + lvrEnd = spilledLVRs.end(); + lvrI != lvrEnd; ++lvrI ) { + // Deallocate the interfering lvr by removing it from the preg union. + physReg2liu_[preg].extract(**lvrI); + } + // After extracting segments, the query's results are invalid. + query.clear(); } //===----------------------------------------------------------------------===// @@ -289,24 +316,59 @@ // minimal, there is no value in caching them. unsigned RABasic::selectOrSplit(LiveInterval &lvr, SmallVectorImpl &splitLVRs) { + // Accumulate the min spill cost among the interferences, in case we spill. + unsigned minSpillReg = 0; + unsigned minSpillAlias = 0; + float minSpillWeight = lvr.weight; + // Check for an available reg in this class. const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg); for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_), trcEnd = trc->allocation_order_end(*mf_); trcI != trcEnd; ++trcI) { unsigned preg = *trcI; - LiveIntervalUnion::Query query(lvr, physReg2liu_[preg]); - if (!checkPhysRegInterference(query, preg)) { - DEBUG(dbgs() << "\tallocating: " << tri_->getName(preg) << lvr << '\n'); + unsigned interfReg = checkPhysRegInterference(lvr, preg); + if (interfReg == 0) { return preg; } + LiveIntervalUnion::InterferenceResult interf = + queries_[interfReg].firstInterference(); + float interfWeight = interf.liuSegPos()->liveVirtReg->weight; + if (interfWeight < minSpillWeight ) { + minSpillReg = interfReg; + minSpillAlias = preg; + minSpillWeight = interfWeight; + } } - DEBUG(dbgs() << "\tspilling: " << lvr << '\n'); - SmallVector spillIs; // ignored - spiller_->spill(&lvr, splitLVRs, spillIs); + if (minSpillReg == 0) { + DEBUG(dbgs() << "spilling: " << lvr << '\n'); + SmallVector spillIs; // ignored + spiller_->spill(&lvr, splitLVRs, spillIs); + // The live virtual register requesting to be allocated was spilled. So tell + // the caller not to allocate anything for this round. + return 0; + } + // Free the cheapest physical register. + spillInterferences(minSpillReg, splitLVRs); + // Tell the caller to allocate to this newly freed physical register. + assert(minSpillAlias != 0 && "need a free register after spilling"); + // We just spilled the first register that interferes with minSpillAlias. We + // now assume minSpillAlias is free because only one register alias may + // interfere at a time. e.g. we ignore predication. + unsigned interfReg = checkPhysRegInterference(lvr, minSpillAlias); + if (interfReg != 0) { + dbgs() << "spilling cannot free " << tri_->getName(minSpillAlias) << + " for " << lvr.reg << " with interference " << + *queries_[interfReg].firstInterference().liuSegPos()->liveVirtReg << "\n"; + llvm_unreachable("Interference after spill."); + } + return minSpillAlias; +} - // FIXME: update LiveStacks - return 0; +namespace llvm { +Spiller *createInlineSpiller(MachineFunctionPass &pass, + MachineFunction &mf, + VirtRegMap &vrm); } bool RABasic::runOnMachineFunction(MachineFunction &mf) { @@ -323,6 +385,10 @@ RegAllocBase::init(*tm_->getRegisterInfo(), getAnalysis(), getAnalysis()); + // We may want to force InlineSpiller for this register allocator. For + // now we're also experimenting with the standard spiller. + // + //spiller_.reset(createInlineSpiller(*this, *mf_, *vrm_)); spiller_.reset(createSpiller(*this, *mf_, *vrm_)); allocatePhysRegs(); From dpatel at apple.com Mon Nov 8 12:28:34 2010 From: dpatel at apple.com (Devang Patel) Date: Mon, 08 Nov 2010 18:28:34 -0000 Subject: [llvm-commits] [llvm] r118424 - /llvm/trunk/include/llvm/Analysis/DIBuilder.h Message-ID: <20101108182834.A105E2A6C12C@llvm.org> Author: dpatel Date: Mon Nov 8 12:28:34 2010 New Revision: 118424 URL: http://llvm.org/viewvc/llvm-project?rev=118424&view=rev Log: Document parameters. Fix typos. Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=118424&r1=118423&r2=118424&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DIBuilder.h (original) +++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Mon Nov 8 12:28:34 2010 @@ -43,7 +43,20 @@ /// CreateCompileUnit - A CompileUnit provides an anchor for all debugging /// information generated during this instance of compilation. - void CreateCompileUnit(unsigned Lang, StringRef F, StringRef D, StringRef P, + /// @param Lang Source programming language, eg. dwarf::DW_LANG_C99 + /// @param File File name + /// @param Dir Directory + /// @param Producer String identify producer of debugging information. + /// Usuall this is a compiler version string. + /// @param isOptimized A boolean flag which indicates whether optimization + /// is ON or not. + /// @param Flags This string lists command line options. This string is + /// directly embedded in debug info output which may be used + /// by a tool analyzing generated debugging information. + /// @param RV This indicates runtime version for languages like + /// Objective-C. + void CreateCompileUnit(unsigned Lang, StringRef File, StringRef Dir, + StringRef Producer, bool isOptimized, StringRef Flags, unsigned RV); /// CreateFile - Create a file descriptor to hold debugging information @@ -54,12 +67,18 @@ DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); /// CreateBasicType - Create debugging information entry for a basic - /// type, e.g 'char'. + /// type. + /// @param Name Type name. + /// @param SizeInBits Size of the type. + /// @param AlignInBits Type alignment. + /// @param Encoding DWARF encoding code, e.g. dwarf::DW_ATE_float. DIType CreateBasicType(StringRef Name, uint64_t SizeInBits, uint64_t AlignInBits, unsigned Encoding); - /// CreateQaulifiedType - Create debugging information entry for a qualified + /// CreateQualifiedType - Create debugging information entry for a qualified /// type, e.g. 'const int'. + /// @param Tag Tag identifing type, e.g. dwarf::TAG_volatile_type + /// @param FromTy Base Type. DIType CreateQualifiedType(unsigned Tag, DIType FromTy); /// CreatePointerType - Create debugging information entry for a pointer. @@ -76,7 +95,7 @@ DIType CreateFriend(DIType Ty, DIType FriendTy); /// CreateInheritance - Create debugging information entry to establish - /// inheritnace relationship between two types. + /// inheritance relationship between two types. DIType CreateInheritance(DIType Ty, DIType BaseTy, uint64_t BaseOffset, unsigned Flags); From dpatel at apple.com Mon Nov 8 12:30:39 2010 From: dpatel at apple.com (Devang Patel) Date: Mon, 8 Nov 2010 10:30:39 -0800 Subject: [llvm-commits] [llvm] r118248 - in /llvm/trunk: include/llvm/Analysis/DIBuilder.h lib/Analysis/CMakeLists.txt lib/Analysis/DIBuilder.cpp In-Reply-To: References: <20101104150139.2385E2A6C12C@llvm.org> Message-ID: <24C0BF9D-A957-4721-AEDE-BE1A032D415F@apple.com> On Nov 4, 2010, at 10:44 AM, Frits van Bommel wrote: >> + /// CreateCompileUnit - A CompileUnit provides an anchor for all debugging >> + /// information generated during this instance of compilation. >> + void CreateCompileUnit(unsigned Lang, StringRef F, StringRef D, StringRef P, >> + bool isOptimized, StringRef Flags, unsigned RV); > > Since it's "intended to be a front-end friendly interface", maybe you > should document these parameters? Or at least give them more > meaningful names? > >> + /// CreateBasicType - Create debugging information entry for a basic >> + /// type, e.g 'char'. >> + DIType CreateBasicType(StringRef Name, uint64_t SizeInBits, >> + uint64_t AlignInBits, unsigned Encoding); > > Ditto. Especially "Encoding" -- what's that for? How is the encoding encoded? :) > (Maybe it should have an enum type instead?) > >> + /// CreateQaulifiedType - Create debugging information entry for a qualified >> + /// type, e.g. 'const int'. >> + DIType CreateQualifiedType(unsigned Tag, DIType FromTy); > > Tag is also unclear, what value is one supposed to pass here? > Also, you typo'd the function name in the comment. > >> + /// CreateInheritance - Create debugging information entry to establish >> + /// inheritnace relationship between two types. >> + DIType CreateInheritance(DIType Ty, DIType BaseTy, uint64_t BaseOffset, >> + unsigned Flags); > > typo'd inheritance. Fixed. Thanks for the feedback! - Devang From anton at korobeynikov.info Mon Nov 8 12:37:16 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 8 Nov 2010 21:37:16 +0300 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: <20101108175807.8543A2A6C12C@llvm.org> References: <20101108175807.8543A2A6C12C@llvm.org> Message-ID: Hi Jason, > + ? ?if (CPUString != "generic") { > + ? ? ?if (CPUString == "cortex-a8") { This looks pretty gross. Is it possible to generalize stuff somehow? E.g. via the mapping of CPU names => supported attributes. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From jasonwkim at google.com Mon Nov 8 12:41:05 2010 From: jasonwkim at google.com (Jason Kim) Date: Mon, 8 Nov 2010 10:41:05 -0800 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: References: <20101108175807.8543A2A6C12C@llvm.org> Message-ID: On Mon, Nov 8, 2010 at 10:37 AM, Anton Korobeynikov wrote: > Hi Jason, > >> + ? ?if (CPUString != "generic") { >> + ? ? ?if (CPUString == "cortex-a8") { > This looks pretty gross. Is it possible to generalize stuff somehow? > E.g. via the mapping of CPU names => supported attributes. I agree its very gross. I am going to be iterating over this repeatedly. I don't yet have a clear understanding of the space of cpu/attributes yet. As I get more familiarized with how GNU/as does things, I will be refactoring these. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > From echristo at apple.com Mon Nov 8 12:46:56 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 08 Nov 2010 18:46:56 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118426 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm.c arm.h Message-ID: <20101108184657.20ED02A6C12C@llvm.org> Author: echristo Date: Mon Nov 8 12:46:56 2010 New Revision: 118426 URL: http://llvm.org/viewvc/llvm-project?rev=118426&view=rev Log: Revert these changes. They need to be done in a somewhat larger way. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=118426&r1=118425&r2=118426&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Mon Nov 8 12:46:56 2010 @@ -551,10 +551,6 @@ /* The processor for which instructions should be scheduled. */ enum processor_type arm_tune = arm_none; -/* LLVM LOCAL global arch value */ -enum processor_type arm_arch = arm_none; -enum processor_type arm_cpu = arm_none; - /* APPLE LOCAL begin v7 support. Merge from mainline */ /* The default processor used if not overriden by commandline. */ static enum processor_type arm_default_cpu = arm_none; @@ -1013,8 +1009,8 @@ /* APPLE LOCAL end ARM custom frame layout */ /* APPLE LOCAL begin ARM compact switch tables */ -/* These are library functions, but calls to them are not - represented as calls in the RTL because they do not have +/* These are library functions, but calls to them are not + represented as calls in the RTL because they do not have normal function-call semantics. We generate the Mach-O stuff lazily in this case. */ @@ -1022,7 +1018,7 @@ { #if TARGET_MACHO if (switch8_libfunc == NULL) - switch8_libfunc = gen_rtx_SYMBOL_REF (Pmode, + switch8_libfunc = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string ("__switch8", sizeof ("__switch8"))); if (flag_pic || MACHO_DYNAMIC_NO_PIC_P) machopic_validate_stub_or_non_lazy_ptr @@ -1034,7 +1030,7 @@ { #if TARGET_MACHO if (switchu8_libfunc == NULL) - switchu8_libfunc = gen_rtx_SYMBOL_REF (Pmode, + switchu8_libfunc = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string ("__switchu8", sizeof ("__switchu8"))); if (flag_pic || MACHO_DYNAMIC_NO_PIC_P) machopic_validate_stub_or_non_lazy_ptr @@ -1046,7 +1042,7 @@ { #if TARGET_MACHO if (switch16_libfunc == NULL) - switch16_libfunc = gen_rtx_SYMBOL_REF (Pmode, + switch16_libfunc = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string ("__switch16", sizeof ("__switch16"))); if (flag_pic || MACHO_DYNAMIC_NO_PIC_P) machopic_validate_stub_or_non_lazy_ptr @@ -1058,7 +1054,7 @@ { #if TARGET_MACHO if (switch32_libfunc == NULL) - switch32_libfunc = gen_rtx_SYMBOL_REF (Pmode, + switch32_libfunc = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string ("__switch32", sizeof ("__switch32"))); if (flag_pic || MACHO_DYNAMIC_NO_PIC_P) machopic_validate_stub_or_non_lazy_ptr @@ -1293,13 +1289,12 @@ unsigned i; /* APPLE LOCAL v7 support. Merge from Codesourcery */ int len; - /* LLVM LOCAL global arch value */ - /* Moved arm_arch to arm.h as arm_arch and arm_cpu */ + enum processor_type target_arch_cpu = arm_none; /* Set up the flags based on the cpu/architecture selected by the user. */ for (i = ARRAY_SIZE (arm_select); i--;) { - struct arm_cpu_select * ptr = &arm_select[i]; + struct arm_cpu_select * ptr = arm_select + i; if (ptr->string != NULL && ptr->string[0] != '\0') { @@ -1330,14 +1325,8 @@ If no other option is used to set the CPU type, we'll use this to guess the most suitable tuning options. */ - if (/* -mcpu is a sensible default. */ - i == ARM_OPT_SET_CPU - /* But -march= overrides -mcpu. */ - || i == ARM_OPT_SET_ARCH) - arm_arch = (enum processor_type) (sel - ptr->processors); - - if (i == ARM_OPT_SET_CPU) - arm_cpu = (enum processor_type) (sel - ptr->processors); + if (i == ARM_OPT_SET_ARCH) + target_arch_cpu = sel->core; if (i != ARM_OPT_SET_TUNE) { @@ -1371,7 +1360,7 @@ /* Guess the tuning options from the architecture if necessary. */ if (arm_tune == arm_none) - arm_tune = arm_arch; + arm_tune = target_arch_cpu; /* If the user did not specify a processor, choose one for them. */ if (insn_flags == 0) @@ -1465,8 +1454,6 @@ arm_default_cpu = (enum processor_type) (sel - all_cores); if (arm_tune == arm_none) arm_tune = arm_default_cpu; - if (arm_cpu == arm_none) - arm_cpu = arm_default_cpu; /* APPLE LOCAL end v7 support. Merge from Codesourcery */ } @@ -2063,7 +2050,7 @@ *is_value = 1; mem = XEXP (XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 1), 0), 0); } - if (mem + if (mem && GET_CODE (XEXP (mem, 0)) == PLUS && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG && GET_CODE (XEXP (XEXP (mem, 0), 1)) == CONST_INT) @@ -2194,7 +2181,7 @@ if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) return 0; - if (flag_pic + if (flag_pic && arm_pic_register != INVALID_REGNUM && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) return 0; @@ -2275,7 +2262,7 @@ /* APPLE LOCAL begin v7 support. Merge from mainline */ /* Get the number of trailing zeros. */ lowbit = ffs((int) i) - 1; - + /* Only even shifts are allowed in ARM mode so round down to the nearest even number. */ if (TARGET_ARM) @@ -3971,15 +3958,15 @@ TYPE_ATTRIBUTES (type) = type_attr_list; } /* APPLE LOCAL begin 5946347 ms_struct support */ - /* If -mms-bitfields is active and this is a structure or union type + /* If -mms-bitfields is active and this is a structure or union type definition, then add an ms_struct attribute. */ #if TARGET_MACHO else if ((TARGET_MS_BITFIELD_LAYOUT || darwin_ms_struct) && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE)) #else - else if (TARGET_MS_BITFIELD_LAYOUT - && (TREE_CODE (type) == RECORD_TYPE + else if (TARGET_MS_BITFIELD_LAYOUT + && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE)) #endif { @@ -4544,17 +4531,17 @@ /* Thumb-2 only allows very limited access to the PC. Calculate the address in a temporary register. */ if (arm_pic_register != INVALID_REGNUM) - { + { pic_tmp = gen_rtx_REG (SImode, thumb_find_work_register (saved_regs)); } - else - { + else + { gcc_assert (!no_new_pseudos); pic_tmp = gen_reg_rtx (Pmode); - } + } - emit_insn (gen_pic_load_addr_thumb2 (cfun->machine->pic_reg, + emit_insn (gen_pic_load_addr_thumb2 (cfun->machine->pic_reg, pic_rtx, l1)); emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno)); emit_insn (gen_addsi3 (cfun->machine->pic_reg, cfun->machine->pic_reg, @@ -4720,7 +4707,7 @@ { bool use_ldrd; enum rtx_code code = GET_CODE (x); - + if (arm_address_register_rtx_p (x, strict_p)) return 1; @@ -4754,7 +4741,7 @@ offset = INTVAL(addend); if (GET_MODE_SIZE (mode) <= 4) return (offset > -256 && offset < 256); - + return (use_ldrd && offset > -1024 && offset < 1024 && (offset & 3) == 0); } @@ -4907,14 +4894,14 @@ thumb2_index_mul_operand (rtx op) { HOST_WIDE_INT val; - + if (GET_CODE(op) != CONST_INT) return false; val = INTVAL(op); return (val == 1 || val == 2 || val == 4 || val == 8); } - + /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */ static int thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) @@ -5386,7 +5373,7 @@ if (xop01 == virtual_stack_vars_rtx) { base_reg = gen_reg_rtx (SImode); - val = force_operand (gen_rtx_PLUS (SImode, xop01, xop1), + val = force_operand (gen_rtx_PLUS (SImode, xop01, xop1), NULL_RTX); emit_move_insn (base_reg, val); /* Canonical form requires some non-reg ops to be first. */ @@ -6741,7 +6728,7 @@ dep = dep; cost = cost; return 1; -#else +#else /* LLVM LOCAL end */ rtx i_pat, d_pat; @@ -7005,7 +6992,7 @@ is output and the correct instruction to use for a given constant is chosen by the assembler). The constant shown is replicated across all elements of the destination vector. - + insn elems variant constant (binary) ---- ----- ------- ----------------- vmov i32 0 00000000 00000000 00000000 abcdefgh @@ -7032,18 +7019,18 @@ For case 18, B = !b. Representable values are exactly those accepted by vfp3_const_double_index, but are output as floating-point numbers rather than indices. - + Variants 0-5 (inclusive) may also be used as immediates for the second operand of VORR/VBIC instructions. - + The INVERSE argument causes the bitwise inverse of the given operand to be recognized instead (used for recognizing legal immediates for the VAND/VORN pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be output, rather than the real insns vbic/vorr). - + INVERSE makes no difference to the recognition of float vectors. - + The return value is the variant of immediate as shown in the above table, or -1 if the given value doesn't match any of the listed patterns. */ @@ -7068,7 +7055,7 @@ unsigned char bytes[16]; int immtype = -1, matches; unsigned int invmask = inverse ? 0xff : 0; - + /* Vectors of float constants. */ if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) { @@ -7084,7 +7071,7 @@ { rtx elt = CONST_VECTOR_ELT (op, i); REAL_VALUE_TYPE re; - + REAL_VALUE_FROM_CONST_DOUBLE (re, elt); if (!REAL_VALUES_EQUAL (r0, re)) @@ -7093,13 +7080,13 @@ if (modconst) *modconst = CONST_VECTOR_ELT (op, 0); - + if (elementwidth) *elementwidth = 0; - + return 18; } - + /* Splat vector constant out into a byte vector. */ for (i = 0; i < n_elts; i++) { @@ -7119,7 +7106,7 @@ } else gcc_unreachable (); - + for (part = 0; part < parts; part++) { unsigned int byte; @@ -7132,10 +7119,10 @@ elpart = CONST_DOUBLE_HIGH (el); } } - + /* Sanity check. */ gcc_assert (idx == GET_MODE_SIZE (mode)); - + do { CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 @@ -7159,29 +7146,29 @@ CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); - + CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); - + CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); - + CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] && bytes[i + 2] == 0 && bytes[i + 3] == 0); CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); - + CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); - + CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); - + CHECK (1, 8, 16, bytes[i] == bytes[0]); CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) @@ -7194,7 +7181,7 @@ if (elementwidth) *elementwidth = elsize; - + if (modconst) { unsigned HOST_WIDE_INT imm = 0; @@ -7208,7 +7195,7 @@ { /* FIXME: Broken on 32-bit H_W_I hosts. */ gcc_assert (sizeof (HOST_WIDE_INT) == 8); - + for (i = 0; i < 8; i++) imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) << (i * BITS_PER_UNIT); @@ -7225,7 +7212,7 @@ *modconst = GEN_INT (imm); } } - + return immtype; #undef CHECK } @@ -7242,16 +7229,16 @@ rtx tmpconst; int tmpwidth; int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); - + if (retval == -1) return 0; - + if (modconst) *modconst = tmpconst; - + if (elementwidth) *elementwidth = tmpwidth; - + return 1; } @@ -7270,13 +7257,13 @@ if (retval < 0 || retval > 5) return 0; - + if (modconst) *modconst = tmpconst; - + if (elementwidth) *elementwidth = tmpwidth; - + return 1; } @@ -7289,16 +7276,16 @@ { int width, is_valid; static char templ[40]; - + is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); - + gcc_assert (is_valid != 0); - + if (quad) sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); else sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); - + return templ; } @@ -7319,7 +7306,7 @@ enum machine_mode inner = GET_MODE_INNER (mode); unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); rtx tmpsum = op1; - + for (i = parts / 2; i >= 1; i /= 2) { rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); @@ -9600,7 +9587,7 @@ /* APPLE LOCAL 7083296 Build without warnings. */ && XINT (body, 1) == VUNSPEC_POOL_STRING) { - int len = TREE_STRING_LENGTH (SYMBOL_REF_DECL + int len = TREE_STRING_LENGTH (SYMBOL_REF_DECL (XVECEXP (body, 0, 0))); len = (len + 3) & ~3; *length = len; @@ -9794,12 +9781,12 @@ rtx op1 = XEXP (body, 1); /* case 3 */ - if (GET_CODE (op0) == MEM && + if (GET_CODE (op0) == MEM && (GET_CODE (XEXP (op0, 0)) == PRE_INC || GET_CODE (XEXP (op0, 0)) == POST_INC)) *length = 2; /* case 4 */ - else if (GET_CODE (op1) == MEM && + else if (GET_CODE (op1) == MEM && (GET_CODE (XEXP (op1, 0)) == PRE_INC || GET_CODE (XEXP (op1, 0)) == POST_INC)) *length = 2; @@ -10486,7 +10473,7 @@ still put the pool after the table. */ new_cost = arm_barrier_cost (from); - if (count < max_count + if (count < max_count && (!selected || new_cost <= selected_cost)) { selected = tmp; @@ -11817,7 +11804,7 @@ dest = REGNO (operands[0]); src = REGNO (operands[1]); - + /* This seems pretty dumb, but hopefully GCC won't try to do it very often. */ if (dest < src) @@ -11836,12 +11823,12 @@ } } } - else + else { gcc_assert (MEM_P (operands[0])); gcc_assert (REG_P (operands[1])); gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); - + switch (GET_CODE (XEXP (operands[0], 0))) { case REG: @@ -11852,7 +11839,7 @@ gcc_unreachable (); } } - + return ""; } @@ -11932,12 +11919,12 @@ [e3h, e3l, e2h, e2l, e1h, e1l, e0h, e0l, e7h, e7l, e6h, e6l, e5h, e5l, e4h, e4l] - + When necessary, quadword registers (dN, dN+1) are moved to ARM registers from rN in the order: - + dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) - + So that STM/LDM can be used on vectors in ARM registers, and the same memory layout will result as if VSTM/VLDM were used. @@ -11951,12 +11938,12 @@ const char *template; char buff[50]; enum machine_mode mode; - + reg = operands[!load]; mem = operands[load]; - + mode = GET_MODE (reg); - + gcc_assert (REG_P (reg)); regno = REGNO (reg); gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) @@ -11965,13 +11952,13 @@ || VALID_NEON_QREG_MODE (mode) || VALID_NEON_STRUCT_MODE (mode)); gcc_assert (MEM_P (mem)); - + addr = XEXP (mem, 0); - + /* Strip off const from addresses like (const (plus (...))). */ if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) addr = XEXP (addr, 0); - + switch (GET_CODE (addr)) { case POST_INC: @@ -11980,7 +11967,7 @@ ops[0] = XEXP (addr, 0); ops[1] = reg; break; - + case POST_MODIFY: /* FIXME: Not currently enabled in neon_vector_mem_operand. */ gcc_unreachable (); @@ -12026,10 +12013,10 @@ ops[0] = mem; ops[1] = reg; } - + sprintf (buff, template, load ? "ld" : "st"); output_asm_insn (buff, ops); - + return ""; } @@ -13118,7 +13105,7 @@ XEXP (XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 1), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); else - XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) + XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, regno); } @@ -13132,9 +13119,9 @@ XEXP (XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 1), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); else - XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) + XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); - asm_fprintf (f, "\tldr\t%r, [%r, #%wd]\n", IP_REGNUM, + asm_fprintf (f, "\tldr\t%r, [%r, #%wd]\n", IP_REGNUM, REGNO (stack_reg), INTVAL (offset)); } } @@ -13226,7 +13213,7 @@ XEXP (XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 1), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); else - XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) + XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, regno); } @@ -13241,9 +13228,9 @@ XEXP (XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 1), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); else - XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) + XEXP (XEXP (XVECEXP (PATTERN (sibling), 0, 0), 0), 0) = gen_rtx_REG (SImode, IP_REGNUM); - asm_fprintf (f, "\tldr\t%r, [%r, #%wd]\n", IP_REGNUM, + asm_fprintf (f, "\tldr\t%r, [%r, #%wd]\n", IP_REGNUM, REGNO (stack_reg), INTVAL (offset)); } } @@ -13270,12 +13257,12 @@ and we are not saving any regs in the range R4...R11. In the latter case they are stored on the stack below the "empty" spot used for R12 and the saved values would get clobbered. */ - if (saved_regs_mask + if (saved_regs_mask & ((1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<9) | (1<<10) | (1<<11))) ip_ok = 0; if (!ip_ok) maxpopsize -= 4; - if (optimize_size + if (optimize_size && delta <= maxpopsize && delta % 4 == 0 && !TARGET_IWMMXT && really_return @@ -14200,7 +14187,7 @@ && ! frame_pointer_needed) { rtx lr = gen_rtx_REG (SImode, LR_REGNUM); - + emit_set_insn (lr, plus_constant (lr, -4)); } @@ -14454,7 +14441,7 @@ if (TARGET_UNIFIED_ASM) arm_print_condition (stream); break; - + case '.': /* The current condition code for a condition code setting instruction. Preceeded by 's' in unified syntax, otherwise followed by 's'. */ @@ -14859,21 +14846,21 @@ { int mode = GET_MODE (x); int regno; - + if ((GET_MODE_SIZE (mode) != 16 && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) { output_operand_lossage ("invalid operand for code '%c'", code); return; } - + regno = REGNO (x); if (!NEON_REGNO_OK_FOR_QUAD (regno)) { output_operand_lossage ("invalid operand for code '%c'", code); return; } - + if (GET_MODE_SIZE (mode) == 16) fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) + (code == 'f' ? 1 : 0)); @@ -15041,7 +15028,7 @@ units = CONST_VECTOR_NUNITS (x); size = GET_MODE_SIZE (GET_MODE_INNER (mode)); - + /* For big-endian Neon vectors, we must permute the vector to the form which, when loaded by a VLDR or VLDM instruction, will give a vector with the elements in the right order. */ @@ -15052,7 +15039,7 @@ support those anywhere yet. */ invmask = (parts_per_word == 0) ? 0 : (1 << (parts_per_word - 1)) - 1; } - + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) for (i = 0; i < units; i++) { @@ -15065,9 +15052,9 @@ { rtx elt = CONST_VECTOR_ELT (x, i); REAL_VALUE_TYPE rval; - + REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); - + assemble_real (rval, GET_MODE_INNER (mode), i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); @@ -15776,7 +15763,7 @@ return VFP_REGNO_OK_FOR_DOUBLE (regno); /* APPLE LOCAL end v7 support. Merge from mainline */ /* APPLE LOCAL begin v7 support. Merge from Codesourcery */ - + if (TARGET_NEON) return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) || (VALID_NEON_QREG_MODE (mode) @@ -15786,7 +15773,7 @@ || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); - + /* APPLE LOCAL end v7 support. Merge from Codesourcery */ return FALSE; } @@ -15799,7 +15786,7 @@ if (IS_IWMMXT_REGNUM (regno)) return VALID_IWMMXT_REG_MODE (mode); } - + /* APPLE LOCAL begin v7 support. Merge from Codesourcery */ /* We allow any value to be stored in the general registers. Restrict doubleword quantities to even register pairs so that we can @@ -17048,8 +17035,8 @@ tree intSI_pointer_node = build_pointer_type (neon_intSI_type_node); tree intDI_pointer_node = build_pointer_type (neon_intDI_type_node); tree float_pointer_node = build_pointer_type (neon_float_type_node); - - /* Next create constant-qualified versions of the above types. */ + + /* Next create constant-qualified versions of the above types. */ tree const_intQI_node = build_qualified_type (neon_intQI_type_node, TYPE_QUAL_CONST); tree const_intHI_node = build_qualified_type (neon_intHI_type_node, @@ -17263,13 +17250,13 @@ TYPE5 (v8hi, v8hi, v8hi, v8hi, si); TYPE5 (v4si, v4si, v4si, v4si, si); TYPE5 (v4sf, v4sf, v4sf, v4sf, si); - + /* Ternary operations, "long" operations (dest and first operand wider than second and third operands). */ TYPE5 (v8hi, v8hi, v8qi, v8qi, si); TYPE5 (v4si, v4si, v4hi, v4hi, si); TYPE5 (v2di, v2di, v2si, v2si, si); - + /* Unops, all-doubleword arithmetic. */ TYPE3 (v8qi, v8qi, si); TYPE3 (v4hi, v4hi, si); @@ -17389,7 +17376,7 @@ TYPE4 (v2sf, v2si, si, si); TYPE4 (v4si, v4sf, si, si); TYPE4 (v4sf, v4si, si, si); - + /* Multiply by scalar (lane). */ TYPE5 (v4hi, v4hi, v4hi, si, si); TYPE5 (v2si, v2si, v2si, si, si); @@ -17413,12 +17400,12 @@ /* Multiply-accumulate, etc. by scalar (lane), widening. */ TYPE6 (v4si, v4si, v4hi, v4hi, si, si); TYPE6 (v2di, v2di, v2si, v2si, si, si); - + /* Multiply by scalar. */ TYPE4 (v4hi, v4hi, hi, si); TYPE4 (v2si, v2si, si, si); TYPE4 (v2sf, v2sf, sf, si); - + TYPE4 (v8hi, v8hi, hi, si); TYPE4 (v4si, v4si, si, si); TYPE4 (v4sf, v4sf, sf, si); @@ -17519,7 +17506,7 @@ TYPE3 (v8qi, v8qi3, v8qi); TYPE3 (v8qi, v8qi4, v8qi); /* LLVM LOCAL end multi-vector types */ - + /* Extended table look-up. */ /*TYPE4 (v8qi, v8qi, v8qi, v8qi);*/ /* LLVM LOCAL begin multi-vector types */ @@ -17999,7 +17986,7 @@ "__builtin_neon_sf"); (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, "__builtin_neon_di"); - + (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, "__builtin_neon_poly8"); (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, @@ -18114,7 +18101,7 @@ qreg_types[2] = V4SI_type_node; qreg_types[3] = V4SF_type_node; qreg_types[4] = V2DI_type_node; - + for (i = 0; i < 5; i++) { int j; @@ -18145,18 +18132,18 @@ tree ftype = NULL; enum insn_code icode; enum machine_mode tmode, mode0, mode1, mode2, mode3; - + if ((d->bits & (1 << j)) == 0) continue; - + icode = d->codes[codeidx++]; - + tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; mode1 = insn_data[icode].operand[2].mode; mode2 = insn_data[icode].operand[3].mode; mode3 = insn_data[icode].operand[4].mode; - + switch (d->itype) { case NEON_UNOP: @@ -18209,7 +18196,7 @@ if (mode0 == V16QImode) ftype = v16qi_ftype_v16qi_si; break; - + case V8HImode: if (mode0 == V8HImode) ftype = v8hi_ftype_v8hi_si; @@ -18218,7 +18205,7 @@ else if (mode0 == V16QImode) ftype = v8hi_ftype_v16qi_si; break; - + case V4SImode: if (mode0 == V4SImode) ftype = v4si_ftype_v4si_si; @@ -18227,12 +18214,12 @@ else if (mode0 == V8HImode) ftype = v4si_ftype_v8hi_si; break; - + case V4SFmode: if (mode0 == V4SFmode) ftype = v4sf_ftype_v4sf_si; break; - + case V2DImode: if (mode0 == V2DImode) ftype = v2di_ftype_v2di_si; @@ -18607,7 +18594,7 @@ else if (mode0 == V4SImode) ftype = v4hi_ftype_v4si_si_si; break; - + case V2SImode: if (mode0 == V2SImode) ftype = v2si_ftype_v2si_si_si; @@ -18680,17 +18667,17 @@ if (mode0 == V8QImode && mode1 == V8QImode) ftype = v16qi_ftype_v8qi_v8qi; break; - + case V8HImode: if (mode0 == V4HImode && mode1 == V4HImode) ftype = v8hi_ftype_v4hi_v4hi; break; - + case V4SImode: if (mode0 == V2SImode && mode1 == V2SImode) ftype = v4si_ftype_v2si_v2si; break; - + case V4SFmode: if (mode0 == V2SFmode && mode1 == V2SFmode) ftype = v4sf_ftype_v2sf_v2sf; @@ -18796,7 +18783,7 @@ if (mode0 == V4SImode) ftype = v4sf_ftype_v4si_si_si; break; - + default: gcc_unreachable (); } @@ -18813,32 +18800,32 @@ if (mode0 == V4HImode && mode1 == V4HImode) ftype = v4hi_ftype_v4hi_v4hi_si_si; break; - + case V2SImode: if (mode0 == V2SImode && mode1 == V2SImode) ftype = v2si_ftype_v2si_v2si_si_si; break; - + case V2SFmode: if (mode0 == V2SFmode && mode1 == V2SFmode) ftype = v2sf_ftype_v2sf_v2sf_si_si; break; - + case V8HImode: if (mode0 == V8HImode && mode1 == V4HImode) ftype = v8hi_ftype_v8hi_v4hi_si_si; break; - + case V4SImode: if (mode0 == V4SImode && mode1 == V2SImode) ftype = v4si_ftype_v4si_v2si_si_si; break; - + case V4SFmode: if (mode0 == V4SFmode && mode1 == V2SFmode) ftype = v4sf_ftype_v4sf_v2sf_si_si; break; - + default: gcc_unreachable (); } @@ -18856,12 +18843,12 @@ if (mode0 == V4HImode && mode1 == V4HImode) ftype = v4si_ftype_v4hi_v4hi_si_si; break; - + case V2DImode: if (mode0 == V2SImode && mode1 == V2SImode) ftype = v2di_ftype_v2si_v2si_si_si; break; - + default: gcc_unreachable (); } @@ -18879,7 +18866,7 @@ if (mode0 == V4SImode && mode1 == V2SImode) ftype = v4si_ftype_v4si_v2si_si_si; break; - + case V8HImode: if (mode0 == V8HImode && mode1 == V4HImode) ftype = v8hi_ftype_v8hi_v4hi_si_si; @@ -18889,12 +18876,12 @@ if (mode0 == V2SImode && mode1 == V2SImode) ftype = v2si_ftype_v2si_v2si_si_si; break; - + case V4HImode: if (mode0 == V4HImode && mode1 == V4HImode) ftype = v4hi_ftype_v4hi_v4hi_si_si; break; - + default: gcc_unreachable (); } @@ -18915,25 +18902,25 @@ && mode2 == V4HImode) ftype = v4hi_ftype_v4hi_v4hi_v4hi_si_si; break; - + case V2SImode: if (mode0 == V2SImode && mode1 == V2SImode && mode2 == V2SImode) ftype = v2si_ftype_v2si_v2si_v2si_si_si; break; - + case V2SFmode: if (mode0 == V2SFmode && mode1 == V2SFmode && mode2 == V2SFmode) ftype = v2sf_ftype_v2sf_v2sf_v2sf_si_si; break; - + case V8HImode: if (mode0 == V8HImode && mode1 == V8HImode && mode2 == V4HImode) ftype = v8hi_ftype_v8hi_v8hi_v4hi_si_si; break; - + case V4SImode: if (mode0 == V4SImode && mode1 == V4SImode && mode2 == V2SImode) @@ -18942,19 +18929,19 @@ && mode2 == V4HImode) ftype = v4si_ftype_v4si_v4hi_v4hi_si_si; break; - + case V4SFmode: if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V2SFmode) ftype = v4sf_ftype_v4sf_v4sf_v2sf_si_si; break; - + case V2DImode: if (mode0 == V2DImode && mode1 == V2SImode && mode2 == V2SImode) ftype = v2di_ftype_v2di_v2si_v2si_si_si; break; - + default: gcc_unreachable (); } @@ -19025,7 +19012,7 @@ if (mode0 == V4SImode && mode1 == SImode) ftype = v4si_ftype_v4si_si_si; break; - + case V8HImode: if (mode0 == V8HImode && mode1 == HImode) ftype = v8hi_ftype_v8hi_hi_si; @@ -19035,12 +19022,12 @@ if (mode0 == V2SImode && mode1 == SImode) ftype = v2si_ftype_v2si_si_si; break; - + case V4HImode: if (mode0 == V4HImode && mode1 == HImode) ftype = v4hi_ftype_v4hi_hi_si; break; - + default: gcc_unreachable (); } @@ -19704,11 +19691,11 @@ default: gcc_unreachable (); } - + gcc_assert (ftype != NULL); - + sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); - + lang_hooks.builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, NULL_TREE); } @@ -19800,7 +19787,7 @@ if (TARGET_REALLY_IWMMXT) arm_init_iwmmxt_builtins (); - + if (TARGET_NEON) arm_init_neon_builtins (); @@ -19911,7 +19898,7 @@ const neon_builtin_datum *key = a; const neon_builtin_datum *memb = b; unsigned int soughtcode = key->base_fcode; - + if (soughtcode >= memb->base_fcode && soughtcode < memb->base_fcode + memb->num_vars) return 0; @@ -19930,11 +19917,11 @@ enum insn_code locate_neon_builtin_icode (int fcode, neon_itype *itype, enum neon_builtins *neon_code) -/* LLVM LOCAL end */ +/* LLVM LOCAL end */ { neon_builtin_datum key, *found; int idx; - + key.base_fcode = fcode; found = bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), sizeof (neon_builtin_data[0]), neon_builtin_compare); @@ -19973,19 +19960,19 @@ enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; int argc = 0; - + if (have_retval && (!target || GET_MODE (target) != tmode || !(*insn_data[icode].operand[0].predicate) (target, tmode))) target = gen_reg_rtx (tmode); - + va_start (ap, arglist); - + for (;;) { builtin_arg thisarg = va_arg (ap, int); - + if (thisarg == NEON_ARG_STOP) break; else @@ -20020,7 +20007,7 @@ case NEON_ARG_STOP: gcc_unreachable (); } - + argc++; } } @@ -20049,7 +20036,7 @@ case 5: pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); break; - + default: gcc_unreachable (); } @@ -20097,7 +20084,7 @@ neon_itype itype; /* LLVM LOCAL Added 0 argument to following call. */ enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, 0); - + switch (itype) { case NEON_UNOP: @@ -20105,7 +20092,7 @@ case NEON_DUPLANE: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); - + case NEON_BINOP: case NEON_SETLANE: case NEON_SCALARMUL: @@ -20116,19 +20103,19 @@ return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); - + case NEON_TERNOP: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); - + case NEON_GETLANE: case NEON_FIXCONV: case NEON_SHIFTIMM: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); - + case NEON_CREATE: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); @@ -20138,7 +20125,7 @@ case NEON_REINTERP: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); - + case NEON_COMBINE: case NEON_VTBL: return arm_expand_neon_args (target, icode, 1, arglist, @@ -20148,14 +20135,14 @@ return arm_expand_neon_args (target, icode, 0, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); - + case NEON_LANEMUL: case NEON_LANEMULL: case NEON_LANEMULH: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); - + case NEON_LANEMAC: return arm_expand_neon_args (target, icode, 1, arglist, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, @@ -20199,7 +20186,7 @@ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); } - + gcc_unreachable (); } @@ -20220,9 +20207,9 @@ rtx mem = gen_rtx_MEM (mode, destaddr); rtx tmp1 = gen_reg_rtx (mode); rtx tmp2 = gen_reg_rtx (mode); - + emit_insn (intfn (tmp1, op1, tmp2, op2)); - + emit_move_insn (mem, tmp1); mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); emit_move_insn (mem, tmp2); @@ -20239,7 +20226,7 @@ unsigned int copied = 0, opctr = 0; unsigned int done = (1 << count) - 1; unsigned int i, j; - + while (copied != done) { for (i = 0; i < count; i++) @@ -20999,7 +20986,7 @@ /* LLVM LOCAL begin */ #ifdef ENABLE_LLVM return 0; -#else +#else /* LLVM LOCAL end */ rtx insn; @@ -21886,7 +21873,7 @@ saved the LR then add it to the list of regs to push. */ if (l_mask == (1 << LR_REGNUM)) { - bytes += handle_thumb_pushpop + bytes += handle_thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), 1, &cfa_offset, real_regs_mask | (1 << LR_REGNUM), emit); @@ -22304,7 +22291,7 @@ if (flag_signaling_nans) asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n"); /* Tag_ABI_FP_number_model. */ - asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", + asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", flag_finite_math_only ? 1 : 3); /* Tag_ABI_align8_needed. */ @@ -22328,8 +22315,8 @@ } /* APPLE LOCAL 6345234 begin place text sections together */ #if TARGET_MACHO - /* Emit declarations for all code sections at the beginning of the file; - this keeps them from being separated by data sections, which can + /* Emit declarations for all code sections at the beginning of the file; + this keeps them from being separated by data sections, which can lead to out-of-range branches. */ if (flag_pic || MACHO_DYNAMIC_NO_PIC_P) { @@ -22337,10 +22324,10 @@ fprintf (asm_out_file, "\t.section __TEXT,__textcoal_nt,coalesced\n"); fprintf (asm_out_file, "\t.section __TEXT,__const_coal,coalesced\n"); if (MACHO_DYNAMIC_NO_PIC_P ) - fprintf (asm_out_file, + fprintf (asm_out_file, "\t.section __TEXT,__symbol_stub4,symbol_stubs,none,12\n"); else - fprintf (asm_out_file, + fprintf (asm_out_file, "\t.section __TEXT,__picsymbolstub4,symbol_stubs,none,16\n"); } #endif @@ -22724,7 +22711,7 @@ SYMBOL_REF_FLAGS (function_rtx), 1); bool is_indirected = false; - + /* Darwin/mach-o: use a stub for dynamic references. */ #if TARGET_MACHO @@ -22805,7 +22792,7 @@ ".word .LTHUNKn-7-.LTHUNKPCn". Otherwise, output: ".word .LTHUNKn-8-.LTHUNKPCn". - (inter-module thumbness is fixed up by the linker). + (inter-module thumbness is fixed up by the linker). If we're in a Thumb2 thunk, it's -4 and -3, respectively. */ rtx tem = gen_rtx_SYMBOL_REF (Pmode, function_name); @@ -23886,7 +23873,7 @@ else fprintf (file, "%s:\n\t.long\t%s\n", slp_label_name, lazy_ptr_name); - + switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]); fprintf (file, "%s:\n", lazy_ptr_name); fprintf (file, "\t.indirect_symbol\t%s\n", symbol_name); @@ -23907,7 +23894,7 @@ /* APPLE LOCAL end ARM MACH assembler */ /* APPLE LOCAL begin ARM darwin optimization defaults */ -/* LLVM LOCAL fix warning on non-Darwin */ +/* LLVM LOCAL fix warning on non-Darwin */ void optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) { @@ -23925,7 +23912,7 @@ flag_local_alloc = 0; /* APPLE LOCAL rerun cse after combine */ /* flag_rerun_cse_after_combine = 1; */ - + /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to make the problem with not enough registers even worse. */ /* LLVM LOCAL begin */ @@ -24020,7 +24007,7 @@ const char *shift; HOST_WIDE_INT val; char c; - + c = flag_chars[set_flags]; if (TARGET_UNIFIED_ASM) { @@ -24123,7 +24110,7 @@ directive = ".short"; else { - pack = 1; + pack = 1; directive = ".long"; } /* Alignment of table was handled by aligning its label, @@ -24142,7 +24129,7 @@ asm_fprintf (file, "\t%s\t(L%d-L%d)/%d\n", directive, CODE_LABEL_NUMBER (target_label), base_label_no, pack); - } + } /* APPLE LOCAL end 5837498 assembler expr for (L1-L2)/2 */ /* APPLE LOCAL begin 6152801 SImode thumb2 switch table dispatch */ else if (TARGET_ARM) @@ -24194,7 +24181,7 @@ Currently the true and false cases are not handled. It's surprising that there isn't already a routine somewhere that does this, but I couldn't find one. */ - + void arm_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info ATTRIBUTE_UNUSED, basic_block bb ATTRIBUTE_UNUSED, @@ -24203,7 +24190,7 @@ { /* There is a dependency here on the order of codes in rtl.def, also an assumption that none of the useful enum values will - collide with 0 or 1. + collide with 0 or 1. Order is: NE EQ GE GT LE LT GEU GTU LEU LTU */ static RTX_CODE and_codes[10][10] = { { NE, 0, GT, GT, LT, LT, GTU, GTU, LTU, LTU }, @@ -24298,7 +24285,7 @@ /* APPLE LOCAL end ARM enhance conditional insn generation */ /* APPLE LOCAL begin 5946347 ms_struct support */ -/* Handle a "ms_struct" attribute; arguments as in struct +/* Handle a "ms_struct" attribute; arguments as in struct attribute_spec.handler. */ static tree arm_handle_ms_struct_attribute (tree *node, tree name, @@ -24331,7 +24318,7 @@ return NULL_TREE; } -/* Handle a "gcc_struct" attribute; arguments as in struct +/* Handle a "gcc_struct" attribute; arguments as in struct attribute_spec.handler. */ static tree arm_handle_gcc_struct_attribute (tree *node, tree name, @@ -24369,7 +24356,7 @@ static bool arm_ms_bitfield_layout_p (tree record_type) { - return (lookup_attribute ("ms_struct", + return (lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type)) != NULL); } @@ -24386,8 +24373,8 @@ else { enum machine_mode mode; - /* For non-aggregate types of BIGGEST_ALIGNMENT bits or greater, - the alignment should be the size of the type. For arrays, it + /* For non-aggregate types of BIGGEST_ALIGNMENT bits or greater, + the alignment should be the size of the type. For arrays, it should be the alignement of the members of the array. */ mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE ? get_inner_array_type (type) : type); @@ -24459,7 +24446,7 @@ handle it. Add that code here. */ gcc_unreachable (); } - + /* Handle the cases where SECONDARY_OUTPUT_RELOAD_CLASS said that we needed a scratch register. Currently, we only handle the case where there was indexed literal addressing with an out-of-range @@ -24503,10 +24490,10 @@ call_used_regs[9] = 1; if (TARGET_THUMB) - { + { fixed_regs[THUMB_HARD_FRAME_POINTER_REGNUM] = 1; call_used_regs[THUMB_HARD_FRAME_POINTER_REGNUM] = 1; - global_regs[THUMB_HARD_FRAME_POINTER_REGNUM] = 1; + global_regs[THUMB_HARD_FRAME_POINTER_REGNUM] = 1; } } /* APPLE LOCAL end 5571707 Allow R9 as caller-saved register */ Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=118426&r1=118425&r2=118426&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Mon Nov 8 12:46:56 2010 @@ -149,10 +149,6 @@ /* The processor for which instructions should be scheduled. */ extern enum processor_type arm_tune; -/* LLVM LOCAL global arch value */ -extern enum processor_type arm_arch; -extern enum processor_type arm_cpu; - typedef enum arm_cond_code { ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, @@ -3460,7 +3456,7 @@ /* Turn -march=xx into a CPU type. */ #define LLVM_SET_SUBTARGET_FEATURES(F) \ - { switch (arm_cpu) { \ + { switch (arm_tune) { \ case arm8: F.setCPU("arm8"); break;\ case arm810: F.setCPU("arm810"); break;\ case strongarm: F.setCPU("strongarm"); break;\ From dalej at apple.com Mon Nov 8 13:17:22 2010 From: dalej at apple.com (Dale Johannesen) Date: Mon, 08 Nov 2010 19:17:22 -0000 Subject: [llvm-commits] [llvm] r118429 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Message-ID: <20101108191722.E4F872A6C12D@llvm.org> Author: johannes Date: Mon Nov 8 13:17:22 2010 New Revision: 118429 URL: http://llvm.org/viewvc/llvm-project?rev=118429&view=rev Log: Revert 118422 in search of bot verdancy. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118429&r1=118428&r2=118429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Nov 8 13:17:22 2010 @@ -74,7 +74,6 @@ public: virtual void MaybeSwitchVendor(StringRef Vendor) = 0; virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0; - virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; virtual void Finish() = 0; virtual ~AttributeEmitter() {} }; @@ -91,10 +90,6 @@ Twine(Attribute) + ", " + Twine(Value)); } - void EmitTextAttribute(unsigned Attribute, StringRef String) { - assert(0 && "Unsupported use of text attribute"); - } - void Finish() { } }; @@ -128,12 +123,6 @@ Contents += Value; } - void EmitTextAttribute(unsigned Attribute, StringRef String) { - Contents += Attribute; - Contents += String; - Contents += 0; - } - void Finish() { const size_t ContentsSize = Contents.size(); @@ -609,51 +598,28 @@ if (CPUString != "generic") OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString); } else { - if (CPUString != "generic") { - if (CPUString == "cortex-a8") { - AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "CORTEX-A8"); - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, - ARMBuildAttrs::ApplicationProfile); - AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, - ARMBuildAttrs::Allowed); - AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::AllowThumb32); - // Fixme: figure out when this is emitted. - //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch, - // ARMBuildAttrs::AllowWMMXv1); - } - } else { - // FIXME: Why these defaults? - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); - AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, - ARMBuildAttrs::Allowed); - AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::Allowed); - } + assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o"); + // FIXME: Why these defaults? + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1); + AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1); } // FIXME: Emit FPU type if (Subtarget->hasVFP2()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, - ARMBuildAttrs::AllowFPv2); + AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2); // Signal various FP modes. if (!UnsafeFPMath) { - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, - ARMBuildAttrs::Allowed); - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, - ARMBuildAttrs::Allowed); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1); } if (NoInfsFPMath && NoNaNsFPMath) - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, - ARMBuildAttrs::Allowed); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1); else - AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, - ARMBuildAttrs::AllowIEE754); + AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3); - // FIXME: add more flags to ARMBuildAttrs.h // 8-bytes alignment stuff. AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1); AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1); Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=118429&r1=118428&r2=118429&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Mon Nov 8 13:17:22 2010 @@ -92,40 +92,6 @@ v7E_M = 13 // v7_M with DSP extensions }; - enum CPUArchProfile { // (=7), uleb128 - Not_Applicable = 0, // pre v7, or cross-profile code - ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8) - RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4) - MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3) - SystemProfile = (0x53) // 'S' Application or real-time profile - }; - - // The following have a lot of common use cases - enum { - //ARMISAUse (=8), uleb128 and THUMBISAUse (=9), uleb128 - Not_Allowed = 0, - Allowed = 1, - - // FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10) - AllowFPv2 = 2, // v2 FP ISA permitted (implies use of the v1 FP ISA) - AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA) - AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31 - AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA) - AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31 - - // Tag_WMMX_arch, (=11), uleb128 - AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions) - - // Tag_WMMX_arch, (=11), uleb128 - AllowWMMXv1 = 2, // The user permitted this entity to use WMMX v2 - - // Tag_ABI_FP_denormal, (=20), uleb128 - PreserveFPSign = 2, // sign when flushed-to-zero is preserved - - // Tag_ABI_FP_number_model, (=23), uleb128 - AllowRTABI = 2, // numbers, infinities, and one quiet NaN (see [RTABI]) - AllowIEE754 = 3 // this code to use all the IEEE 754-defined FP encodings - }; } #endif // __TARGET_ARMBUILDATTRS_H__ Modified: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=118429&r1=118428&r2=118429&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Mon Nov 8 13:17:22 2010 @@ -1,35 +1,18 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s -; RUN: llc %s -march=arm -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \ -; RUN: -arm-reserve-r9 -arm-use-movt -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s - - +; RUN: elf-dump --dump-section-data | FileCheck %s ; This tests that the extpected ARM attributes are emitted. ; -; BASIC: .ARM.attributes -; BASIC-NEXT: 0x70000003 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x0000003c -; BASIC-NEXT: 0x00000022 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000001 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' - -; CORTEXA8: .ARM.attributes -; CORTEXA8-NEXT: 0x70000003 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x0000003c -; CORTEXA8-NEXT: 0x00000031 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000001 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: '41300000 00616561 62690001 26000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 0119012c 01' +; CHECK: .ARM.attributes +; CHECK-NEXT: 0x70000003 +; CHECK-NEXT: 0x00000000 +; CHECK-NEXT: 0x00000000 +; CHECK-NEXT: 0x0000003c +; CHECK-NEXT: 0x00000022 +; CHECK-NEXT: 0x00000000 +; CHECK-NEXT: 0x00000000 +; CHECK-NEXT: 0x00000001 +; CHECK-NEXT: 0x00000000 +; CHECK-NEXT: '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' define i32 @f(i64 %z) { ret i32 0 From jasonwkim at google.com Mon Nov 8 13:23:59 2010 From: jasonwkim at google.com (Jason Kim) Date: Mon, 8 Nov 2010 11:23:59 -0800 Subject: [llvm-commits] Fwd: [llvm] r118429 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: References: <20101108191722.E4F872A6C12D@llvm.org> Message-ID: ---------- Forwarded message ---------- From: Jason Kim Date: Mon, Nov 8, 2010 at 11:22 AM Subject: Re: [llvm-commits] [llvm] r118429 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll To: Dale Johannesen On Mon, Nov 8, 2010 at 11:17 AM, Dale Johannesen wrote: > Author: johannes > Date: Mon Nov ?8 13:17:22 2010 > New Revision: 118429 > > URL: http://llvm.org/viewvc/llvm-project?rev=118429&view=rev > Log: > Revert 118422 in search of bot verdancy. Hi Dale, Can you please get me an error log? (was there a build failure?) Thanks -jason > > > Modified: > ? ?llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > ? ?llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h > ? ?llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118429&r1=118428&r2=118429&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Nov ?8 13:17:22 2010 > @@ -74,7 +74,6 @@ > ? public: > ? ? virtual void MaybeSwitchVendor(StringRef Vendor) = 0; > ? ? virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0; > - ? ?virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; > ? ? virtual void Finish() = 0; > ? ? virtual ~AttributeEmitter() {} > ? }; > @@ -91,10 +90,6 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ?Twine(Attribute) + ", " + Twine(Value)); > ? ? } > > - ? ?void EmitTextAttribute(unsigned Attribute, StringRef String) { > - ? ? ?assert(0 && "Unsupported use of text attribute"); > - ? ?} > - > ? ? void Finish() { } > ? }; > > @@ -128,12 +123,6 @@ > ? ? ? Contents += Value; > ? ? } > > - ? ?void EmitTextAttribute(unsigned Attribute, StringRef String) { > - ? ? ?Contents += Attribute; > - ? ? ?Contents += String; > - ? ? ?Contents += 0; > - ? ?} > - > ? ? void Finish() { > ? ? ? const size_t ContentsSize = Contents.size(); > > @@ -609,51 +598,28 @@ > ? ? if (CPUString != "generic") > ? ? ? OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString); > ? } else { > - ? ?if (CPUString != "generic") { > - ? ? ?if (CPUString == "cortex-a8") { > - ? ? ? ?AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "CORTEX-A8"); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::ApplicationProfile); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowThumb32); > - ? ? ? ?// Fixme: figure out when this is emitted. > - ? ? ? ?//AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch, > - ? ? ? ?// ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowWMMXv1); > - ? ? ?} > - ? ?} else { > - ? ? ?// FIXME: Why these defaults? > - ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); > - ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ?} > + ? ?assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o"); > + ? ?// FIXME: Why these defaults? > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1); > ? } > > ? // FIXME: Emit FPU type > ? if (Subtarget->hasVFP2()) > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowFPv2); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2); > > ? // Signal various FP modes. > ? if (!UnsafeFPMath) { > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1); > ? } > > ? if (NoInfsFPMath && NoNaNsFPMath) > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1); > ? else > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowIEE754); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3); > > - ?// FIXME: add more flags to ARMBuildAttrs.h > ? // 8-bytes alignment stuff. > ? AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1); > ? AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1); > > Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=118429&r1=118428&r2=118429&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Mon Nov ?8 13:17:22 2010 > @@ -92,40 +92,6 @@ > ? ? v7E_M ? ?= 13 ? // v7_M with DSP extensions > ? }; > > - ?enum CPUArchProfile { // (=7), uleb128 > - ? ?Not_Applicable = 0, // pre v7, or cross-profile code > - ? ?ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8) > - ? ?RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4) > - ? ?MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3) > - ? ?SystemProfile = (0x53) // 'S' Application or real-time profile > - ?}; > - > - ?// The following have a lot of common use cases > - ?enum { > - ? ?//ARMISAUse (=8), uleb128 ?and THUMBISAUse (=9), uleb128 > - ? ?Not_Allowed = 0, > - ? ?Allowed = 1, > - > - ? ?// FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10) > - ? ?AllowFPv2 ?= 2, // v2 FP ISA permitted (implies use of the v1 FP ISA) > - ? ?AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA) > - ? ?AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31 > - ? ?AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA) > - ? ?AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31 > - > - ? ?// Tag_WMMX_arch, (=11), uleb128 > - ? ?AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions) > - > - ? ?// Tag_WMMX_arch, (=11), uleb128 > - ? ?AllowWMMXv1 = 2, ?// The user permitted this entity to use WMMX v2 > - > - ? ?// Tag_ABI_FP_denormal, (=20), uleb128 > - ? ?PreserveFPSign = 2, // sign when flushed-to-zero is preserved > - > - ? ?// Tag_ABI_FP_number_model, (=23), uleb128 > - ? ?AllowRTABI = 2, ?// numbers, infinities, and one quiet NaN (see [RTABI]) > - ? ?AllowIEE754 = 3 // this code to use all the IEEE 754-defined FP encodings > - ?}; > ?} > > ?#endif // __TARGET_ARMBUILDATTRS_H__ > > Modified: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=118429&r1=118428&r2=118429&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Mon Nov ?8 13:17:22 2010 > @@ -1,35 +1,18 @@ > ?; RUN: llc ?%s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ > -; RUN: ? ?elf-dump --dump-section-data | FileCheck ?-check-prefix=BASIC %s > -; RUN: llc ?%s -march=arm -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \ > -; RUN: ? ?-arm-reserve-r9 -arm-use-movt -filetype=obj -o - | \ > -; RUN: ? ?elf-dump --dump-section-data | FileCheck ?-check-prefix=CORTEXA8 %s > - > - > +; RUN: ? ?elf-dump --dump-section-data | FileCheck %s > ?; This tests that the extpected ARM attributes are emitted. > ?; > -; BASIC: ? ? ? ?.ARM.attributes > -; BASIC-NEXT: ? ? ? ? 0x70000003 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x0000003c > -; BASIC-NEXT: ? ? ? ? 0x00000022 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x00000001 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' > - > -; CORTEXA8: ? ? ? ?.ARM.attributes > -; CORTEXA8-NEXT: ? ? ? ? 0x70000003 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x0000003c > -; CORTEXA8-NEXT: ? ? ? ? 0x00000031 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000001 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? '41300000 00616561 62690001 26000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 0119012c 01' > +; CHECK: ? ? ? ?.ARM.attributes > +; CHECK-NEXT: ? ? ? ? 0x70000003 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x0000003c > +; CHECK-NEXT: ? ? ? ? 0x00000022 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x00000001 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' > > ?define i32 @f(i64 %z) { > ? ? ? ?ret i32 0 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Mon Nov 8 13:24:47 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 19:24:47 -0000 Subject: [llvm-commits] [llvm] r118430 - /llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20101108192447.33EAD2A6C132@llvm.org> Author: djg Date: Mon Nov 8 13:24:47 2010 New Revision: 118430 URL: http://llvm.org/viewvc/llvm-project?rev=118430&view=rev Log: Fix a thinko that Duncan spotted. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118430&r1=118429&r2=118430&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Mon Nov 8 13:24:47 2010 @@ -145,7 +145,7 @@ AliasAnalysis::Location Loc(Arg, AliasAnalysis::UnknownSize, I->getMetadata(LLVMContext::MD_tbaa)); - if (!AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) + if (!AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) // Writes memory. Just give up. return false; } From jasonwkim at google.com Mon Nov 8 13:26:29 2010 From: jasonwkim at google.com (Jason Kim) Date: Mon, 8 Nov 2010 11:26:29 -0800 Subject: [llvm-commits] [llvm] r118429 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: <20101108191722.E4F872A6C12D@llvm.org> References: <20101108191722.E4F872A6C12D@llvm.org> Message-ID: On Mon, Nov 8, 2010 at 11:17 AM, Dale Johannesen wrote: > Author: johannes > Date: Mon Nov ?8 13:17:22 2010 > New Revision: 118429 > > URL: http://llvm.org/viewvc/llvm-project?rev=118429&view=rev > Log: > Revert 118422 in search of bot verdancy. Sorry about that. I see the errors. > > > Modified: > ? ?llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > ? ?llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h > ? ?llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118429&r1=118428&r2=118429&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Nov ?8 13:17:22 2010 > @@ -74,7 +74,6 @@ > ? public: > ? ? virtual void MaybeSwitchVendor(StringRef Vendor) = 0; > ? ? virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0; > - ? ?virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; > ? ? virtual void Finish() = 0; > ? ? virtual ~AttributeEmitter() {} > ? }; > @@ -91,10 +90,6 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ?Twine(Attribute) + ", " + Twine(Value)); > ? ? } > > - ? ?void EmitTextAttribute(unsigned Attribute, StringRef String) { > - ? ? ?assert(0 && "Unsupported use of text attribute"); > - ? ?} > - > ? ? void Finish() { } > ? }; > > @@ -128,12 +123,6 @@ > ? ? ? Contents += Value; > ? ? } > > - ? ?void EmitTextAttribute(unsigned Attribute, StringRef String) { > - ? ? ?Contents += Attribute; > - ? ? ?Contents += String; > - ? ? ?Contents += 0; > - ? ?} > - > ? ? void Finish() { > ? ? ? const size_t ContentsSize = Contents.size(); > > @@ -609,51 +598,28 @@ > ? ? if (CPUString != "generic") > ? ? ? OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString); > ? } else { > - ? ?if (CPUString != "generic") { > - ? ? ?if (CPUString == "cortex-a8") { > - ? ? ? ?AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "CORTEX-A8"); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::ApplicationProfile); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowThumb32); > - ? ? ? ?// Fixme: figure out when this is emitted. > - ? ? ? ?//AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch, > - ? ? ? ?// ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowWMMXv1); > - ? ? ?} > - ? ?} else { > - ? ? ?// FIXME: Why these defaults? > - ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); > - ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ?} > + ? ?assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o"); > + ? ?// FIXME: Why these defaults? > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1); > ? } > > ? // FIXME: Emit FPU type > ? if (Subtarget->hasVFP2()) > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowFPv2); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2); > > ? // Signal various FP modes. > ? if (!UnsafeFPMath) { > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1); > ? } > > ? if (NoInfsFPMath && NoNaNsFPMath) > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::Allowed); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1); > ? else > - ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARMBuildAttrs::AllowIEE754); > + ? ?AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3); > > - ?// FIXME: add more flags to ARMBuildAttrs.h > ? // 8-bytes alignment stuff. > ? AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1); > ? AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1); > > Modified: llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h?rev=118429&r1=118428&r2=118429&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBuildAttrs.h Mon Nov ?8 13:17:22 2010 > @@ -92,40 +92,6 @@ > ? ? v7E_M ? ?= 13 ? // v7_M with DSP extensions > ? }; > > - ?enum CPUArchProfile { // (=7), uleb128 > - ? ?Not_Applicable = 0, // pre v7, or cross-profile code > - ? ?ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8) > - ? ?RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4) > - ? ?MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3) > - ? ?SystemProfile = (0x53) // 'S' Application or real-time profile > - ?}; > - > - ?// The following have a lot of common use cases > - ?enum { > - ? ?//ARMISAUse (=8), uleb128 ?and THUMBISAUse (=9), uleb128 > - ? ?Not_Allowed = 0, > - ? ?Allowed = 1, > - > - ? ?// FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10) > - ? ?AllowFPv2 ?= 2, // v2 FP ISA permitted (implies use of the v1 FP ISA) > - ? ?AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA) > - ? ?AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31 > - ? ?AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA) > - ? ?AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31 > - > - ? ?// Tag_WMMX_arch, (=11), uleb128 > - ? ?AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions) > - > - ? ?// Tag_WMMX_arch, (=11), uleb128 > - ? ?AllowWMMXv1 = 2, ?// The user permitted this entity to use WMMX v2 > - > - ? ?// Tag_ABI_FP_denormal, (=20), uleb128 > - ? ?PreserveFPSign = 2, // sign when flushed-to-zero is preserved > - > - ? ?// Tag_ABI_FP_number_model, (=23), uleb128 > - ? ?AllowRTABI = 2, ?// numbers, infinities, and one quiet NaN (see [RTABI]) > - ? ?AllowIEE754 = 3 // this code to use all the IEEE 754-defined FP encodings > - ?}; > ?} > > ?#endif // __TARGET_ARMBUILDATTRS_H__ > > Modified: llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=118429&r1=118428&r2=118429&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Mon Nov ?8 13:17:22 2010 > @@ -1,35 +1,18 @@ > ?; RUN: llc ?%s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ > -; RUN: ? ?elf-dump --dump-section-data | FileCheck ?-check-prefix=BASIC %s > -; RUN: llc ?%s -march=arm -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 \ > -; RUN: ? ?-arm-reserve-r9 -arm-use-movt -filetype=obj -o - | \ > -; RUN: ? ?elf-dump --dump-section-data | FileCheck ?-check-prefix=CORTEXA8 %s > - > - > +; RUN: ? ?elf-dump --dump-section-data | FileCheck %s > ?; This tests that the extpected ARM attributes are emitted. > ?; > -; BASIC: ? ? ? ?.ARM.attributes > -; BASIC-NEXT: ? ? ? ? 0x70000003 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x0000003c > -; BASIC-NEXT: ? ? ? ? 0x00000022 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? 0x00000001 > -; BASIC-NEXT: ? ? ? ? 0x00000000 > -; BASIC-NEXT: ? ? ? ? '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' > - > -; CORTEXA8: ? ? ? ?.ARM.attributes > -; CORTEXA8-NEXT: ? ? ? ? 0x70000003 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x0000003c > -; CORTEXA8-NEXT: ? ? ? ? 0x00000031 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000001 > -; CORTEXA8-NEXT: ? ? ? ? 0x00000000 > -; CORTEXA8-NEXT: ? ? ? ? '41300000 00616561 62690001 26000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 0119012c 01' > +; CHECK: ? ? ? ?.ARM.attributes > +; CHECK-NEXT: ? ? ? ? 0x70000003 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x0000003c > +; CHECK-NEXT: ? ? ? ? 0x00000022 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? 0x00000001 > +; CHECK-NEXT: ? ? ? ? 0x00000000 > +; CHECK-NEXT: ? ? ? ? '41210000 00616561 62690001 17000000 06020801 09011401 15011703 18011901 2c01' > > ?define i32 @f(i64 %z) { > ? ? ? ?ret i32 0 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Mon Nov 8 13:33:06 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 8 Nov 2010 11:33:06 -0800 Subject: [llvm-commits] [llvm] r118409 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: <4CD82351.1010207@free.fr> References: <20101108160843.B1F782A6C12C@llvm.org> <4CD82351.1010207@free.fr> Message-ID: <52EB9DFA-0258-4DF9-8E9F-E07CB11D8FBA@apple.com> On Nov 8, 2010, at 8:20 AM, Duncan Sands wrote: > Hi Dan, > >> Teach BasicAliasAnalysis::getModRefBehavior(const Function *F) >> to analyze intrinsic functions. > > >> + // For intrinsics, we can check the table. >> + if (unsigned iid = F->getIntrinsicID()) { >> +#define GET_INTRINSIC_MODREF_BEHAVIOR >> +#include "llvm/Intrinsics.gen" >> +#undef GET_INTRINSIC_MODREF_BEHAVIOR >> + } > > alias analysis exports this logic as AliasAnalysis::getIntrinsicModRefBehavior. > Can't you just use that? I removed that function after I updated all of its users to use the regular getModRefBehavior interface. Dan From gohman at apple.com Mon Nov 8 13:33:38 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 8 Nov 2010 11:33:38 -0800 Subject: [llvm-commits] [llvm] r118417 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll In-Reply-To: <4CD8376C.6060604@free.fr> References: <20101108171204.51D092A6C12C@llvm.org> <4CD8376C.6060604@free.fr> Message-ID: <10A6830F-42A9-4DDE-840C-26CBF99858E8@apple.com> On Nov 8, 2010, at 9:46 AM, Duncan Sands wrote: > Hi Dan, > >> @@ -140,10 +141,14 @@ >> for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); >> CI != CE; ++CI) { >> Value *Arg = *CI; >> - if (Arg->getType()->isPointerTy()&& >> - !AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) >> - // Writes memory. Just give up. >> - return false; >> + if (Arg->getType()->isPointerTy()) { >> + AliasAnalysis::Location Loc(Arg, >> + AliasAnalysis::UnknownSize, >> + I->getMetadata(LLVMContext::MD_tbaa)); >> + if (!AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) > > Shouldn't it be Loc not Arg in the call to pointsToConstantMemory? Oops, yes. Fixed. Dan From gkistanova at gmail.com Mon Nov 8 13:32:29 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 08 Nov 2010 19:32:29 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118431 - /llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Message-ID: <20101108193229.AED412A6C12D@llvm.org> Author: gkistanova Date: Mon Nov 8 13:32:29 2010 New Revision: 118431 URL: http://llvm.org/viewvc/llvm-project?rev=118431&view=rev Log: Changed script to build armeabi without using codesourcery. Modified: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Modified: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi?rev=118431&r1=118430&r2=118431&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi (original) +++ llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Mon Nov 8 13:32:29 2010 @@ -105,13 +105,15 @@ fi #------------------------------------------------------------------------------ -# Step: Copy cross-tools. +# Step: Copy cross-tools and newlib #------------------------------------------------------------------------------ if [ "$do_copy_cross_tools" == "yes" ] ; then # We need a local copy of binutils, system libraries and headers, # since we will be installing there. - cp -RL /opt/codesourcery/* ${PRIVATE_INSTALL} + cp -Ru /opt/cross-tools/* ${PRIVATE_INSTALL} + cp -Ru /opt/newlib-src/newlib/ ${BUILD_ROOT}/${LLVM_GCC_src} + cp -Ru /opt/newlib-src/libgloss/ ${BUILD_ROOT}/${LLVM_GCC_src} fi @@ -125,18 +127,10 @@ mkdir -p ${BUILD_ROOT}/${LLVM_obj} chmod a+rx ${BUILD_ROOT}/${LLVM_obj} cd ${BUILD_ROOT}/${LLVM_obj} - + ../${LLVM_src}/configure --prefix=${PRIVATE_INSTALL} \ - --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu \ - --target=arm-none-linux-gnueabi \ - --enable-shared \ - --disable-multilib \ - --disable-nls \ - --disable-bootstrap \ - --without-llvmgcc \ - --without-llvmgxx \ - --enable-optimized \ - --enable-assertions \ + --enable-optimized \ + --enable-targets=cbe,arm \ $@ # Extra args if any fi @@ -188,15 +182,18 @@ cd ${BUILD_ROOT}/${LLVM_GCC_obj} ../${LLVM_GCC_src}/configure --prefix=${PRIVATE_INSTALL} \ - --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu \ - --target=arm-none-linux-gnueabi \ - --enable-shared \ - --disable-nls \ - --disable-bootstrap \ - --with-sysroot=${PRIVATE_INSTALL}/arm-none-linux-gnueabi/libc \ - --enable-languages=c,c++ \ - --program-prefix=llvm- \ + --target=arm-eabi \ + --enable-languages=c,c++ \ + --disable-nls \ + --prefix=/opt/cross-tools \ + --program-prefix=llvm- \ + --with-newlib \ + --with-headers=yes \ --enable-llvm=${BUILD_ROOT}/${LLVM_obj} \ + --with-cpu=cortex-a8 \ + --with-fpu=neon \ + --with-float=hard \ + --with-abi=aapcs \ $@ # Extra args if any fi From anton at korobeynikov.info Mon Nov 8 13:39:46 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 8 Nov 2010 22:39:46 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r118431 - /llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi In-Reply-To: <20101108193229.AED412A6C12D@llvm.org> References: <20101108193229.AED412A6C12D@llvm.org> Message-ID: > ? ?llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi One small problem: > + ? ? ?--target=arm-eabi ? ? ? ? \ and > + ? ? ?--with-float=hard ? ? ? ? \ > + ? ? ?--with-abi=aapcs ? ? ? ? ?\ is definitely *not* gnueabi :) Otherwise - ok for me. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From peckw at wesleypeck.com Mon Nov 8 13:40:02 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Mon, 08 Nov 2010 19:40:02 -0000 Subject: [llvm-commits] [llvm] r118434 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ Message-ID: <20101108194002.618892A6C12D@llvm.org> Author: peckw Date: Mon Nov 8 13:40:01 2010 New Revision: 118434 URL: http://llvm.org/viewvc/llvm-project?rev=118434&view=rev Log: Adding working version of assembly parser for the MBlaze backend Major cleanup of whitespace and formatting issues in MBlaze backend Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeCallingConv.td llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeMCInstLower.cpp llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeSchedule.td llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetObjectFile.h llvm/trunk/lib/Target/MBlaze/TODO Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Mon Nov 8 13:40:01 2010 @@ -2,10 +2,10 @@ set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMARMInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport LLVMSystem) @@ -14,16 +14,16 @@ set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) -set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils) @@ -34,41 +34,41 @@ set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPTXAsmPrinter LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMSupport) +set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsCodeGen LLVMMipsInfo LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMPTXAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMPTXInfo LLVMSupport LLVMSystem) +set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPTXAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXCodeGen LLVMPTXInfo LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMSystem ) set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMSystemZInfo LLVMTarget) set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMSystemZInfo LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMipa) set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMX86AsmPrinter LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) -set(MSVC_LIB_DEPS_LLVMX86Info LLVMSupport) +set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMXCoreInfo) -set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMSupport) +set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Mon Nov 8 13:40:01 2010 @@ -1,4 +1,4 @@ -//===-- MBlazeAsmParser.cpp - Parse MBlaze assembly to MCInst instructions ------===// +//===-- MBlazeAsmParser.cpp - Parse MBlaze asm to MCInst instructions -----===// // // The LLVM Compiler Infrastructure // @@ -29,67 +29,25 @@ namespace { struct MBlazeOperand; -// The shift types for register controlled shifts in arm memory addressing -enum ShiftType { - Lsl, - Lsr, - Asr, - Ror, - Rrx -}; - class MBlazeAsmParser : public TargetAsmParser { MCAsmParser &Parser; TargetMachine &TM; -private: MCAsmParser &getParser() const { return Parser; } - MCAsmLexer &getLexer() const { return Parser.getLexer(); } void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } - bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } - bool MaybeParseRegister(OwningPtr &Op, bool ParseWriteBack); - - bool ParseRegisterList(OwningPtr &Op); - - bool ParseMemory(OwningPtr &Op); - - bool ParseMemoryOffsetReg(bool &Negative, - bool &OffsetRegShifted, - enum ShiftType &ShiftType, - const MCExpr *&ShiftAmount, - const MCExpr *&Offset, - bool &OffsetIsReg, - int &OffsetRegNum, - SMLoc &E); - - bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E); - - bool ParseOperand(OwningPtr &Op); - - bool ParseDirectiveWord(unsigned Size, SMLoc L); - - bool ParseDirectiveCode(SMLoc L); - - bool ParseDirectiveSyntax(SMLoc L); + MBlazeOperand *ParseMemory(SmallVectorImpl &Operands); + MBlazeOperand *ParseRegister(); + MBlazeOperand *ParseImmediate(); + MBlazeOperand *ParseFsl(); + MBlazeOperand* ParseOperand(SmallVectorImpl &Operands); bool MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, - MCStreamer &Out) { - MCInst Inst; - unsigned ErrorInfo; - if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) { - Out.EmitInstruction(Inst); - return false; - } - - // FIXME: We should give nicer diagnostics about the exact failure. - Error(IDLoc, "unrecognized instruction"); - return true; - } + MCStreamer &Out); /// @name Auto-generated Match Functions /// { @@ -109,101 +67,76 @@ virtual bool ParseDirective(AsmToken DirectiveID); }; - + /// MBlazeOperand - Instances of this class represent a parsed MBlaze machine /// instruction. struct MBlazeOperand : public MCParsedAsmOperand { -private: - MBlazeOperand() {} -public: enum KindTy { - CondCode, + Token, Immediate, - Memory, Register, - Token + Memory, + Fsl } Kind; SMLoc StartLoc, EndLoc; union { struct { - MBlazeCC::CC Val; - } CC; - - struct { const char *Data; unsigned Length; } Tok; struct { unsigned RegNum; - bool Writeback; } Reg; struct { const MCExpr *Val; } Imm; - - // This is for all forms of MBlaze address expressions + struct { - unsigned BaseRegNum; - unsigned OffsetRegNum; // used when OffsetIsReg is true - const MCExpr *Offset; // used when OffsetIsReg is false - const MCExpr *ShiftAmount; // used when OffsetRegShifted is true - enum ShiftType ShiftType; // used when OffsetRegShifted is true - unsigned - OffsetRegShifted : 1, // only used when OffsetIsReg is true - Preindexed : 1, - Postindexed : 1, - OffsetIsReg : 1, - Negative : 1, // only used when OffsetIsReg is true - Writeback : 1; + unsigned Base; + unsigned OffReg; + const MCExpr *Off; } Mem; + struct { + const MCExpr *Val; + } FslImm; }; - - //MBlazeOperand(KindTy K, SMLoc S, SMLoc E) - // : Kind(K), StartLoc(S), EndLoc(E) {} - + + MBlazeOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} +public: MBlazeOperand(const MBlazeOperand &o) : MCParsedAsmOperand() { Kind = o.Kind; StartLoc = o.StartLoc; EndLoc = o.EndLoc; switch (Kind) { - case CondCode: - CC = o.CC; - break; - case Token: - Tok = o.Tok; - break; case Register: Reg = o.Reg; break; case Immediate: Imm = o.Imm; break; + case Token: + Tok = o.Tok; + break; case Memory: Mem = o.Mem; break; + case Fsl: + FslImm = o.FslImm; + break; } } - + /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const { return StartLoc; } + /// getEndLoc - Get the location of the last token of this operand. SMLoc getEndLoc() const { return EndLoc; } - MBlazeCC::CC getCondCode() const { - assert(Kind == CondCode && "Invalid access!"); - return CC.Val; - } - - StringRef getToken() const { - assert(Kind == Token && "Invalid access!"); - return StringRef(Tok.Data, Tok.Length); - } - unsigned getReg() const { assert(Kind == Register && "Invalid access!"); return Reg.RegNum; @@ -214,29 +147,42 @@ return Imm.Val; } - bool isCondCode() const { return Kind == CondCode; } + const MCExpr *getFslImm() const { + assert(Kind == Fsl && "Invalid access!"); + return FslImm.Val; + } - bool isImm() const { return Kind == Immediate; } + unsigned getMemBase() const { + assert(Kind == Memory && "Invalid access!"); + return Mem.Base; + } - bool isReg() const { return Kind == Register; } + const MCExpr* getMemOff() const { + assert(Kind == Memory && "Invalid access!"); + return Mem.Off; + } - bool isToken() const {return Kind == Token; } + unsigned getMemOffReg() const { + assert(Kind == Memory && "Invalid access!"); + return Mem.OffReg; + } + + bool isToken() const { return Kind == Token; } + bool isImm() const { return Kind == Immediate; } + bool isMem() const { return Kind == Memory; } + bool isFsl() const { return Kind == Fsl; } + bool isReg() const { return Kind == Register; } void addExpr(MCInst &Inst, const MCExpr *Expr) const { - // Add as immediates when possible. - if (const MCConstantExpr *CE = dyn_cast(Expr)) + // Add as immediates when possible. Null MCExpr = 0. + if (Expr == 0) + Inst.addOperand(MCOperand::CreateImm(0)); + else if (const MCConstantExpr *CE = dyn_cast(Expr)) Inst.addOperand(MCOperand::CreateImm(CE->getValue())); else Inst.addOperand(MCOperand::CreateExpr(Expr)); } - void addCondCodeOperands(MCInst &Inst, unsigned N) const { - assert(N == 2 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); - // FIXME: What belongs here? - Inst.addOperand(MCOperand::CreateReg(0)); - } - void addRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(getReg())); @@ -247,71 +193,83 @@ addExpr(Inst, getImm()); } - virtual void dump(raw_ostream &OS) const; + void addFslOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getFslImm()); + } - static void CreateCondCode(OwningPtr &Op, MBlazeCC::CC CC, - SMLoc S) { - Op.reset(new MBlazeOperand); - Op->Kind = CondCode; - Op->CC.Val = CC; - Op->StartLoc = S; - Op->EndLoc = S; + void addMemOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + + unsigned RegOff = getMemOffReg(); + if (RegOff) + Inst.addOperand(MCOperand::CreateReg(RegOff)); + else + addExpr(Inst, getMemOff()); + + Inst.addOperand(MCOperand::CreateReg(getMemBase())); + } + + StringRef getToken() const { + assert(Kind == Token && "Invalid access!"); + return StringRef(Tok.Data, Tok.Length); } - static void CreateToken(OwningPtr &Op, StringRef Str, - SMLoc S) { - Op.reset(new MBlazeOperand); - Op->Kind = Token; + virtual void dump(raw_ostream &OS) const; + + static MBlazeOperand *CreateToken(StringRef Str, SMLoc S) { + MBlazeOperand *Op = new MBlazeOperand(Token); Op->Tok.Data = Str.data(); Op->Tok.Length = Str.size(); Op->StartLoc = S; Op->EndLoc = S; + return Op; } - static void CreateReg(OwningPtr &Op, unsigned RegNum, - bool Writeback, SMLoc S, SMLoc E) { - Op.reset(new MBlazeOperand); - Op->Kind = Register; + static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { + MBlazeOperand *Op = new MBlazeOperand(Register); Op->Reg.RegNum = RegNum; - Op->Reg.Writeback = Writeback; - Op->StartLoc = S; Op->EndLoc = E; + return Op; } - static void CreateImm(OwningPtr &Op, const MCExpr *Val, - SMLoc S, SMLoc E) { - Op.reset(new MBlazeOperand); - Op->Kind = Immediate; + static MBlazeOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { + MBlazeOperand *Op = new MBlazeOperand(Immediate); Op->Imm.Val = Val; - Op->StartLoc = S; Op->EndLoc = E; + return Op; } - static void CreateMem(OwningPtr &Op, - unsigned BaseRegNum, bool OffsetIsReg, - const MCExpr *Offset, unsigned OffsetRegNum, - bool OffsetRegShifted, enum ShiftType ShiftType, - const MCExpr *ShiftAmount, bool Preindexed, - bool Postindexed, bool Negative, bool Writeback, - SMLoc S, SMLoc E) { - Op.reset(new MBlazeOperand); - Op->Kind = Memory; - Op->Mem.BaseRegNum = BaseRegNum; - Op->Mem.OffsetIsReg = OffsetIsReg; - Op->Mem.Offset = Offset; - Op->Mem.OffsetRegNum = OffsetRegNum; - Op->Mem.OffsetRegShifted = OffsetRegShifted; - Op->Mem.ShiftType = ShiftType; - Op->Mem.ShiftAmount = ShiftAmount; - Op->Mem.Preindexed = Preindexed; - Op->Mem.Postindexed = Postindexed; - Op->Mem.Negative = Negative; - Op->Mem.Writeback = Writeback; - + static MBlazeOperand *CreateFslImm(const MCExpr *Val, SMLoc S, SMLoc E) { + MBlazeOperand *Op = new MBlazeOperand(Fsl); + Op->Imm.Val = Val; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; + } + + static MBlazeOperand *CreateMem(unsigned Base, const MCExpr *Off, SMLoc S, + SMLoc E) { + MBlazeOperand *Op = new MBlazeOperand(Memory); + Op->Mem.Base = Base; + Op->Mem.Off = Off; + Op->Mem.OffReg = 0; Op->StartLoc = S; Op->EndLoc = E; + return Op; + } + + static MBlazeOperand *CreateMem(unsigned Base, unsigned Off, SMLoc S, + SMLoc E) { + MBlazeOperand *Op = new MBlazeOperand(Memory); + Op->Mem.Base = Base; + Op->Mem.OffReg = Off; + Op->Mem.Off = 0; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; } }; @@ -319,21 +277,21 @@ void MBlazeOperand::dump(raw_ostream &OS) const { switch (Kind) { - case CondCode: - OS << MBlazeCCToString(getCondCode()); - break; case Immediate: getImm()->print(OS); break; - case Memory: - OS << ""; - break; case Register: OS << ""; break; case Token: OS << "'" << getToken() << "'"; break; + case Memory: + OS << "MEMORY"; + break; + case Fsl: + getFslImm()->print(OS); + break; } } @@ -343,487 +301,210 @@ static unsigned MatchRegisterName(StringRef Name); /// } +// +bool MBlazeAsmParser:: +MatchAndEmitInstruction(SMLoc IDLoc, + SmallVectorImpl &Operands, + MCStreamer &Out) { + MCInst Inst; + SMLoc ErrorLoc; + unsigned ErrorInfo; + + switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) { + case Match_Success: + Out.EmitInstruction(Inst); + return false; + case Match_MissingFeature: + return Error(IDLoc, "instruction use requires an option to be enabled"); + case Match_MnemonicFail: + return Error(IDLoc, "unrecognized instruction mnemonic"); + case Match_InvalidOperand: + ErrorLoc = IDLoc; + if (ErrorInfo != ~0U) { + if (ErrorInfo >= Operands.size()) + return Error(IDLoc, "too few operands for instruction"); -/// Try to parse a register name. The token must be an Identifier when called, -/// and if it is a register name a Reg operand is created, the token is eaten -/// and false is returned. Else true is returned and no token is eaten. -/// TODO this is likely to change to allow different register types and or to -/// parse for a specific register type. -bool MBlazeAsmParser::MaybeParseRegister - (OwningPtr &Op, bool ParseWriteBack) { - SMLoc S, E; - const AsmToken &Tok = Parser.getTok(); - assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); - - // FIXME: Validate register for the current architecture; we have to do - // validation later, so maybe there is no need for this here. - int RegNum; - - RegNum = MatchRegisterName(Tok.getString()); - if (RegNum == -1) - return true; - - S = Tok.getLoc(); - - Parser.Lex(); // Eat identifier token. - - E = Parser.getTok().getLoc(); - - bool Writeback = false; - if (ParseWriteBack) { - const AsmToken &ExclaimTok = Parser.getTok(); - if (ExclaimTok.is(AsmToken::Exclaim)) { - E = ExclaimTok.getLoc(); - Writeback = true; - Parser.Lex(); // Eat exclaim token + ErrorLoc = ((MBlazeOperand*)Operands[ErrorInfo])->getStartLoc(); + if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; } - } - MBlazeOperand::CreateReg(Op, RegNum, Writeback, S, E); + return Error(ErrorLoc, "invalid operand for instruction"); + } - return false; + llvm_unreachable("Implement any new match types added!"); + return true; } -/// Parse a register list, return false if successful else return true or an -/// error. The first token must be a '{' when called. -bool MBlazeAsmParser::ParseRegisterList(OwningPtr &Op) { - SMLoc S, E; - assert(Parser.getTok().is(AsmToken::LCurly) && - "Token is not an Left Curly Brace"); - S = Parser.getTok().getLoc(); - Parser.Lex(); // Eat left curly brace token. - - const AsmToken &RegTok = Parser.getTok(); - SMLoc RegLoc = RegTok.getLoc(); - if (RegTok.isNot(AsmToken::Identifier)) - return Error(RegLoc, "register expected"); - int RegNum = MatchRegisterName(RegTok.getString()); - if (RegNum == -1) - return Error(RegLoc, "register expected"); - Parser.Lex(); // Eat identifier token. - unsigned RegList = 1 << RegNum; - - int HighRegNum = RegNum; - // TODO ranges like "{Rn-Rm}" - while (Parser.getTok().is(AsmToken::Comma)) { - Parser.Lex(); // Eat comma token. - - const AsmToken &RegTok = Parser.getTok(); - SMLoc RegLoc = RegTok.getLoc(); - if (RegTok.isNot(AsmToken::Identifier)) - return Error(RegLoc, "register expected"); - int RegNum = MatchRegisterName(RegTok.getString()); - if (RegNum == -1) - return Error(RegLoc, "register expected"); - - if (RegList & (1 << RegNum)) - Warning(RegLoc, "register duplicated in register list"); - else if (RegNum <= HighRegNum) - Warning(RegLoc, "register not in ascending order in register list"); - RegList |= 1 << RegNum; - HighRegNum = RegNum; - - Parser.Lex(); // Eat identifier token. - } - const AsmToken &RCurlyTok = Parser.getTok(); - if (RCurlyTok.isNot(AsmToken::RCurly)) - return Error(RCurlyTok.getLoc(), "'}' expected"); - E = RCurlyTok.getLoc(); - Parser.Lex(); // Eat left curly brace token. +MBlazeOperand *MBlazeAsmParser:: +ParseMemory(SmallVectorImpl &Operands) { + if (Operands.size() != 4) + return 0; - return false; -} + MBlazeOperand &Base = *(MBlazeOperand*)Operands[2]; + MBlazeOperand &Offset = *(MBlazeOperand*)Operands[3]; -/// Parse an arm memory expression, return false if successful else return true -/// or an error. The first token must be a '[' when called. -/// TODO Only preindexing and postindexing addressing are started, unindexed -/// with option, etc are still to do. -bool MBlazeAsmParser::ParseMemory(OwningPtr &Op) { - SMLoc S, E; - assert(Parser.getTok().is(AsmToken::LBrac) && - "Token is not an Left Bracket"); - S = Parser.getTok().getLoc(); - Parser.Lex(); // Eat left bracket token. - - const AsmToken &BaseRegTok = Parser.getTok(); - if (BaseRegTok.isNot(AsmToken::Identifier)) - return Error(BaseRegTok.getLoc(), "register expected"); - if (MaybeParseRegister(Op, false)) - return Error(BaseRegTok.getLoc(), "register expected"); - int BaseRegNum = Op->getReg(); - - bool Preindexed = false; - bool Postindexed = false; - bool OffsetIsReg = false; - bool Negative = false; - bool Writeback = false; - - // First look for preindexed address forms, that is after the "[Rn" we now - // have to see if the next token is a comma. - const AsmToken &Tok = Parser.getTok(); - if (Tok.is(AsmToken::Comma)) { - Preindexed = true; - Parser.Lex(); // Eat comma token. - int OffsetRegNum; - bool OffsetRegShifted; - enum ShiftType ShiftType; - const MCExpr *ShiftAmount; - const MCExpr *Offset; - if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, - Offset, OffsetIsReg, OffsetRegNum, E)) - return true; - const AsmToken &RBracTok = Parser.getTok(); - if (RBracTok.isNot(AsmToken::RBrac)) - return Error(RBracTok.getLoc(), "']' expected"); - E = RBracTok.getLoc(); - Parser.Lex(); // Eat right bracket token. - - const AsmToken &ExclaimTok = Parser.getTok(); - if (ExclaimTok.is(AsmToken::Exclaim)) { - E = ExclaimTok.getLoc(); - Writeback = true; - Parser.Lex(); // Eat exclaim token - } - MBlazeOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum, - OffsetRegShifted, ShiftType, ShiftAmount, - Preindexed, Postindexed, Negative, Writeback, S, E); - return false; + SMLoc S = Base.getStartLoc(); + SMLoc O = Offset.getStartLoc(); + SMLoc E = Offset.getEndLoc(); + + if (!Base.isReg()) { + Error(S, "base address must be a register"); + return 0; } - // The "[Rn" we have so far was not followed by a comma. - else if (Tok.is(AsmToken::RBrac)) { - // This is a post indexing addressing forms, that is a ']' follows after - // the "[Rn". - Postindexed = true; - Writeback = true; - E = Tok.getLoc(); - Parser.Lex(); // Eat right bracket token. - - int OffsetRegNum = 0; - bool OffsetRegShifted = false; - enum ShiftType ShiftType; - const MCExpr *ShiftAmount; - const MCExpr *Offset; - - const AsmToken &NextTok = Parser.getTok(); - if (NextTok.isNot(AsmToken::EndOfStatement)) { - if (NextTok.isNot(AsmToken::Comma)) - return Error(NextTok.getLoc(), "',' expected"); - Parser.Lex(); // Eat comma token. - if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, - ShiftAmount, Offset, OffsetIsReg, OffsetRegNum, - E)) - return true; - } - MBlazeOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum, - OffsetRegShifted, ShiftType, ShiftAmount, - Preindexed, Postindexed, Negative, Writeback, S, E); - return false; + if (!Offset.isReg() && !Offset.isImm()) { + Error(O, "offset must be a register or immediate"); + return 0; } - return true; -} + MBlazeOperand *Op; + if (Offset.isReg()) + Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getReg(), S, E); + else + Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getImm(), S, E); -/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn]," -/// we will parse the following (were +/- means that a plus or minus is -/// optional): -/// +/-Rm -/// +/-Rm, shift -/// #offset -/// we return false on success or an error otherwise. -bool MBlazeAsmParser::ParseMemoryOffsetReg(bool &Negative, - bool &OffsetRegShifted, - enum ShiftType &ShiftType, - const MCExpr *&ShiftAmount, - const MCExpr *&Offset, - bool &OffsetIsReg, - int &OffsetRegNum, - SMLoc &E) { - OwningPtr Op; - Negative = false; - OffsetRegShifted = false; - OffsetIsReg = false; - OffsetRegNum = -1; - const AsmToken &NextTok = Parser.getTok(); - E = NextTok.getLoc(); - if (NextTok.is(AsmToken::Plus)) - Parser.Lex(); // Eat plus token. - else if (NextTok.is(AsmToken::Minus)) { - Negative = true; - Parser.Lex(); // Eat minus token - } - // See if there is a register following the "[Rn," or "[Rn]," we have so far. - const AsmToken &OffsetRegTok = Parser.getTok(); - if (OffsetRegTok.is(AsmToken::Identifier)) { - OffsetIsReg = !MaybeParseRegister(Op, false); - if (OffsetIsReg) { - E = Op->getEndLoc(); - OffsetRegNum = Op->getReg(); - } - } - // If we parsed a register as the offset then their can be a shift after that - if (OffsetRegNum != -1) { - // Look for a comma then a shift - const AsmToken &Tok = Parser.getTok(); - if (Tok.is(AsmToken::Comma)) { - Parser.Lex(); // Eat comma token. - - const AsmToken &Tok = Parser.getTok(); - if (ParseShift(ShiftType, ShiftAmount, E)) - return Error(Tok.getLoc(), "shift expected"); - OffsetRegShifted = true; - } - } - else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm" - // Look for #offset following the "[Rn," or "[Rn]," - const AsmToken &HashTok = Parser.getTok(); - if (HashTok.isNot(AsmToken::Hash)) - return Error(HashTok.getLoc(), "'#' expected"); - - Parser.Lex(); // Eat hash token. - - if (getParser().ParseExpression(Offset)) - return true; - E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - } - return false; + delete Operands.pop_back_val(); + delete Operands.pop_back_val(); + Operands.push_back(Op); + + return Op; } -/// ParseShift as one of these two: -/// ( lsl | lsr | asr | ror ) , # shift_amount -/// rrx -/// and returns true if it parses a shift otherwise it returns false. -bool MBlazeAsmParser::ParseShift(ShiftType &St, - const MCExpr *&ShiftAmount, - SMLoc &E) { - const AsmToken &Tok = Parser.getTok(); - if (Tok.isNot(AsmToken::Identifier)) - return true; - StringRef ShiftName = Tok.getString(); - if (ShiftName == "lsl" || ShiftName == "LSL") - St = Lsl; - else if (ShiftName == "lsr" || ShiftName == "LSR") - St = Lsr; - else if (ShiftName == "asr" || ShiftName == "ASR") - St = Asr; - else if (ShiftName == "ror" || ShiftName == "ROR") - St = Ror; - else if (ShiftName == "rrx" || ShiftName == "RRX") - St = Rrx; - else - return true; - Parser.Lex(); // Eat shift type token. +MBlazeOperand *MBlazeAsmParser::ParseRegister() { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - // Rrx stands alone. - if (St == Rrx) - return false; + switch (getLexer().getKind()) { + default: return 0; + case AsmToken::Identifier: + unsigned RegNo = MatchRegisterName(getLexer().getTok().getIdentifier()); + if (RegNo == 0) + return 0; - // Otherwise, there must be a '#' and a shift amount. - const AsmToken &HashTok = Parser.getTok(); - if (HashTok.isNot(AsmToken::Hash)) - return Error(HashTok.getLoc(), "'#' expected"); - Parser.Lex(); // Eat hash token. + return MBlazeOperand::CreateReg(RegNo, S, E); + } +} - if (getParser().ParseExpression(ShiftAmount)) - return true; +static unsigned MatchFslRegister(const StringRef &String) { + if (!String.startswith("rfsl")) + return -1; - return false; + unsigned regNum; + if (String.substr(4).getAsInteger(10,regNum)) + return -1; + + return regNum; } -/// Parse a arm instruction operand. For now this parses the operand regardless -/// of the mnemonic. -bool MBlazeAsmParser::ParseOperand(OwningPtr &Op) { - SMLoc S, E; - +MBlazeOperand *MBlazeAsmParser::ParseFsl() { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + switch (getLexer().getKind()) { + default: return 0; case AsmToken::Identifier: - if (!MaybeParseRegister(Op, true)) - return false; - // This was not a register so parse other operands that start with an - // identifier (like labels) as expressions and create them as immediates. - const MCExpr *IdVal; - S = Parser.getTok().getLoc(); - if (getParser().ParseExpression(IdVal)) - return true; - E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - MBlazeOperand::CreateImm(Op, IdVal, S, E); - return false; - case AsmToken::LBrac: - return ParseMemory(Op); - case AsmToken::LCurly: - return ParseRegisterList(Op); - case AsmToken::Hash: - // #42 -> immediate. - // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate - S = Parser.getTok().getLoc(); - Parser.Lex(); - const MCExpr *ImmVal; - if (getParser().ParseExpression(ImmVal)) - return true; - E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - MBlazeOperand::CreateImm(Op, ImmVal, S, E); - return false; - default: - return Error(Parser.getTok().getLoc(), "unexpected token in operand"); + unsigned reg = MatchFslRegister(getLexer().getTok().getIdentifier()); + if (reg >= 16) + return 0; + + const MCExpr *EVal = MCConstantExpr::Create(reg,getContext()); + return MBlazeOperand::CreateFslImm(EVal,S,E); } } -/// Parse an mblaze instruction mnemonic followed by its operands. -bool MBlazeAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, - SmallVectorImpl &Operands) { - OwningPtr Op; - - // Create the leading tokens for the mnemonic, split by '.' characters. - size_t Start = 0, Next = Name.find('.'); - StringRef Head = Name.slice(Start, Next); - - // Determine the predicate, if any. - // - // FIXME: We need a way to check whether a prefix supports predication, - // otherwise we will end up with an ambiguity for instructions that happen to - // end with a predicate name. - unsigned CC = StringSwitch(Head.substr(Head.size()-2)) - .Case("eq", MBlazeCC::EQ) - .Case("ne", MBlazeCC::NE) - .Case("gt", MBlazeCC::GT) - .Case("lt", MBlazeCC::LT) - .Case("ge", MBlazeCC::GE) - .Case("le", MBlazeCC::LE) - .Default(~0U); - if (CC != ~0U) { - Head = Head.slice(0, Head.size() - 2); - } else - CC = MBlazeCC::EQ; - - MBlazeOperand::CreateToken(Op, Head, NameLoc); - Operands.push_back(Op.take()); - - MBlazeOperand::CreateCondCode(Op, MBlazeCC::CC(CC), NameLoc); - Operands.push_back(Op.take()); - - // Add the remaining tokens in the mnemonic. - while (Next != StringRef::npos) { - Start = Next; - Next = Name.find('.', Start + 1); - Head = Name.slice(Start, Next); - - MBlazeOperand::CreateToken(Op, Head, NameLoc); - Operands.push_back(Op.take()); - } - - // Read the remaining operands. - if (getLexer().isNot(AsmToken::EndOfStatement)) { - // Read the first operand. - OwningPtr Op; - if (ParseOperand(Op)) { - Parser.EatToEndOfStatement(); - return true; - } - Operands.push_back(Op.take()); +MBlazeOperand *MBlazeAsmParser::ParseImmediate() { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - while (getLexer().is(AsmToken::Comma)) { - Parser.Lex(); // Eat the comma. + const MCExpr *EVal; + switch (getLexer().getKind()) { + default: return 0; + case AsmToken::LParen: + case AsmToken::Plus: + case AsmToken::Minus: + case AsmToken::Integer: + case AsmToken::Identifier: + if (getParser().ParseExpression(EVal)) + return 0; - // Parse and remember the operand. - if (ParseOperand(Op)) { - Parser.EatToEndOfStatement(); - return true; - } - Operands.push_back(Op.take()); - } - } - - if (getLexer().isNot(AsmToken::EndOfStatement)) { - Parser.EatToEndOfStatement(); - return TokError("unexpected token in argument list"); + return MBlazeOperand::CreateImm(EVal, S, E); } - Parser.Lex(); // Consume the EndOfStatement - return false; } -/// ParseDirective parses the arm specific directives -bool MBlazeAsmParser::ParseDirective(AsmToken DirectiveID) { - StringRef IDVal = DirectiveID.getIdentifier(); - if (IDVal == ".word") - return ParseDirectiveWord(4, DirectiveID.getLoc()); - else if (IDVal == ".code") - return ParseDirectiveCode(DirectiveID.getLoc()); - else if (IDVal == ".syntax") - return ParseDirectiveSyntax(DirectiveID.getLoc()); - return true; -} +MBlazeOperand *MBlazeAsmParser:: +ParseOperand(SmallVectorImpl &Operands) { + MBlazeOperand *Op; -/// ParseDirectiveWord -/// ::= .word [ expression (, expression)* ] -bool MBlazeAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { - if (getLexer().isNot(AsmToken::EndOfStatement)) { - for (;;) { - const MCExpr *Value; - if (getParser().ParseExpression(Value)) - return true; - - getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); - - if (getLexer().is(AsmToken::EndOfStatement)) - break; - - // FIXME: Improve diagnostic. - if (getLexer().isNot(AsmToken::Comma)) - return Error(L, "unexpected token in directive"); - Parser.Lex(); - } + // Attempt to parse the next token as a register name + Op = ParseRegister(); + + // Attempt to parse the next token as an FSL immediate + if (!Op) + Op = ParseFsl(); + + // Attempt to parse the next token as an immediate + if (!Op) + Op = ParseImmediate(); + + // Move past the parsed token in the token stream + getLexer().Lex(); + + // If the token could not be parsed then fail + if (!Op) { + Error(Parser.getTok().getLoc(), "unknown operand"); + return 0; } - Parser.Lex(); - return false; + // Push the parsed operand into the list of operands + Operands.push_back(Op); + return Op; } -/// ParseDirectiveSyntax -/// ::= .syntax unified | divided -bool MBlazeAsmParser::ParseDirectiveSyntax(SMLoc L) { - const AsmToken &Tok = Parser.getTok(); - if (Tok.isNot(AsmToken::Identifier)) - return Error(L, "unexpected token in .syntax directive"); - StringRef Mode = Tok.getString(); - if (Mode == "unified" || Mode == "UNIFIED") - Parser.Lex(); - else if (Mode == "divided" || Mode == "DIVIDED") - Parser.Lex(); - else - return Error(L, "unrecognized syntax mode in .syntax directive"); +/// Parse an mblaze instruction mnemonic followed by its operands. +bool MBlazeAsmParser:: +ParseInstruction(StringRef Name, SMLoc NameLoc, + SmallVectorImpl &Operands) { + // The first operand is the token for the instruction name + Operands.push_back(MBlazeOperand::CreateToken(Name, NameLoc)); - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(Parser.getTok().getLoc(), "unexpected token in directive"); - Parser.Lex(); + // If there are no more operands then finish + if (getLexer().is(AsmToken::EndOfStatement)) + return false; - // TODO tell the MC streamer the mode - // getParser().getStreamer().Emit???(); - return false; -} + // Parse the first operand + if (ParseOperand(Operands)) + return true; -/// ParseDirectiveCode -/// ::= .code 16 | 32 -bool MBlazeAsmParser::ParseDirectiveCode(SMLoc L) { - const AsmToken &Tok = Parser.getTok(); - if (Tok.isNot(AsmToken::Integer)) - return Error(L, "unexpected token in .code directive"); - int64_t Val = Parser.getTok().getIntVal(); - if (Val == 16) - Parser.Lex(); - else if (Val == 32) - Parser.Lex(); - else - return Error(L, "invalid operand to .code directive"); + while (getLexer().isNot(AsmToken::EndOfStatement) && + getLexer().is(AsmToken::Comma)) { + // Make sure there is a comma separating operands + // if (getLexer().isNot(AsmToken::Comma)) + // return false; + + // Consume the comma token + getLexer().Lex(); + + // Parse the next operand + if (ParseOperand(Operands)) + return true; + } - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(Parser.getTok().getLoc(), "unexpected token in directive"); - Parser.Lex(); + // If the instruction requires a memory operand then we need to + // replace the last two operands (base+offset) with a single + // memory operand. + if (Name.startswith("lw") || Name.startswith("sw") || + Name.startswith("lh") || Name.startswith("sh") || + Name.startswith("lb") || Name.startswith("sb")) + return ParseMemory(Operands); - // TODO tell the MC streamer the mode - // getParser().getStreamer().Emit???(); return false; } +/// ParseDirective parses the arm specific directives +bool MBlazeAsmParser::ParseDirective(AsmToken DirectiveID) { + return true; +} + extern "C" void LLVMInitializeMBlazeAsmLexer(); /// Force static initialization. Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Mon Nov 8 13:40:01 2010 @@ -56,38 +56,38 @@ MBlaze::SBI, MBlaze::SHI, MBlaze::SWI, UNSUPPORTED, //3C,3D,3E,3F }; -static unsigned getRD( uint32_t insn ) { - return MBlazeRegisterInfo::getRegisterFromNumbering( (insn>>21)&0x1F ); +static unsigned getRD(uint32_t insn) { + return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>21)&0x1F); } -static unsigned getRA( uint32_t insn ) { - return MBlazeRegisterInfo::getRegisterFromNumbering( (insn>>16)&0x1F ); +static unsigned getRA(uint32_t insn) { + return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>16)&0x1F); } -static unsigned getRB( uint32_t insn ) { - return MBlazeRegisterInfo::getRegisterFromNumbering( (insn>>11)&0x1F ); +static unsigned getRB(uint32_t insn) { + return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>11)&0x1F); } -static int64_t getRS( uint32_t insn ) { +static int64_t getRS(uint32_t insn) { int16_t val = (insn & 0x3FFF); return val; } -static int64_t getIMM( uint32_t insn ) { +static int64_t getIMM(uint32_t insn) { int16_t val = (insn & 0xFFFF); return val; } -static int64_t getSHT( uint32_t insn ) { +static int64_t getSHT(uint32_t insn) { int16_t val = (insn & 0x1F); return val; } -static unsigned getFLAGS( int32_t insn ) { +static unsigned getFLAGS(int32_t insn) { return (insn & 0x7FF); } -static int64_t getFSL( uint32_t insn ) { +static int64_t getFSL(uint32_t insn) { int16_t val = (insn & 0xF); return val; } @@ -412,7 +412,7 @@ } } -static unsigned getOPCODE( uint32_t insn ) { +static unsigned getOPCODE(uint32_t insn) { unsigned opcode = mblazeBinary2Opcode[ (insn>>26)&0x3F ]; switch (opcode) { case MBlaze::MUL: return decodeMUL(insn); @@ -465,102 +465,99 @@ // Get the MCInst opcode from the binary instruction and make sure // that it is a valid instruction. - unsigned opcode = getOPCODE( insn ); - if( opcode == UNSUPPORTED ) + unsigned opcode = getOPCODE(insn); + if (opcode == UNSUPPORTED) return false; instr.setOpcode(opcode); uint64_t tsFlags = MBlazeInsts[opcode].TSFlags; - switch( (tsFlags & MBlazeII::FormMask) ) { - default: - errs() << "Opcode: " << MBlazeInsts[opcode].Name << "\n"; - errs() << "Flags: "; errs().write_hex( tsFlags ); errs() << "\n"; - return false; + switch ((tsFlags & MBlazeII::FormMask)) { + default: llvm_unreachable("unknown instruction encoding"); case MBlazeII::FRRR: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRB(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateReg(getRB(insn))); break; case MBlazeII::FRRI: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateImm(getIMM(insn))); break; case MBlazeII::FCRR: - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRB(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateReg(getRB(insn))); break; case MBlazeII::FCRI: - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateImm(getIMM(insn))); break; case MBlazeII::FRCR: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRB(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateReg(getRB(insn))); break; case MBlazeII::FRCI: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateImm(getIMM(insn))); break; case MBlazeII::FCCR: - instr.addOperand( MCOperand::CreateReg( getRB(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRB(insn))); break; case MBlazeII::FCCI: - instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) ); + instr.addOperand(MCOperand::CreateImm(getIMM(insn))); break; case MBlazeII::FRRCI: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getSHT(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateImm(getSHT(insn))); break; case MBlazeII::FRRC: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); break; case MBlazeII::FRCX: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getFSL(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateImm(getFSL(insn))); break; case MBlazeII::FRCS: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getRS(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateImm(getRS(insn))); break; case MBlazeII::FCRCS: - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getRS(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateImm(getRS(insn))); break; case MBlazeII::FCRCX: - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getFSL(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); + instr.addOperand(MCOperand::CreateImm(getFSL(insn))); break; case MBlazeII::FCX: - instr.addOperand( MCOperand::CreateImm( getFSL(insn) ) ); + instr.addOperand(MCOperand::CreateImm(getFSL(insn))); break; case MBlazeII::FCR: - instr.addOperand( MCOperand::CreateReg( getRB(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRB(insn))); break; case MBlazeII::FRIR: - instr.addOperand( MCOperand::CreateReg( getRD(insn) ) ); - instr.addOperand( MCOperand::CreateImm( getIMM(insn) ) ); - instr.addOperand( MCOperand::CreateReg( getRA(insn) ) ); + instr.addOperand(MCOperand::CreateReg(getRD(insn))); + instr.addOperand(MCOperand::CreateImm(getIMM(insn))); + instr.addOperand(MCOperand::CreateReg(getRA(insn))); break; } Modified: llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp Mon Nov 8 13:40:01 2010 @@ -102,7 +102,7 @@ } void MBlazeInstPrinter::printMemOperand(const MCInst *MI, int OpNo, - raw_ostream &O, const char *Modifier ) { + raw_ostream &O, const char *Modifier) { printOperand(MI, OpNo+1, O, NULL); O << ", "; printOperand(MI, OpNo, O, NULL); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp Mon Nov 8 13:40:01 2010 @@ -70,8 +70,8 @@ if ((Count % 4) != 0) return false; - for (uint64_t i = 0; i < Count; i += 4 ) - OW->Write32( 0x00000000 ); + for (uint64_t i = 0; i < Count; i += 4) + OW->Write32(0x00000000); return true; } @@ -114,17 +114,17 @@ void ELFMBlazeAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF, uint64_t Value) const { unsigned Size = getFixupKindSize(Fixup.getKind()); - + assert(Fixup.getOffset() + Size <= DF.getContents().size() && "Invalid fixup offset!"); char *data = DF.getContents().data() + Fixup.getOffset(); switch (Size) { - default: llvm_unreachable( "Cannot fixup unknown value." ); - case 1: llvm_unreachable( "Cannot fixup 1 byte value." ); - case 8: llvm_unreachable( "Cannot fixup 8 byte value." ); + default: llvm_unreachable("Cannot fixup unknown value."); + case 1: llvm_unreachable("Cannot fixup 1 byte value."); + case 8: llvm_unreachable("Cannot fixup 8 byte value."); - case 4: + case 4: *(data+7) = uint8_t(Value); *(data+6) = uint8_t(Value >> 8); *(data+3) = uint8_t(Value >> 16); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Mon Nov 8 13:40:01 2010 @@ -69,7 +69,7 @@ void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void EmitInstruction(const MachineInstr *MI); + void EmitInstruction(const MachineInstr *MI); }; } // end of anonymous namespace Modified: llvm/trunk/lib/Target/MBlaze/MBlazeCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeCallingConv.td?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeCallingConv.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeCallingConv.td Mon Nov 8 13:40:01 2010 @@ -1,16 +1,16 @@ //===- MBlazeCallingConv.td - Calling Conventions for MBlaze -*- tablegen -*-=// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // This describes the calling conventions for MBlaze architecture. //===----------------------------------------------------------------------===// /// CCIfSubtarget - Match if the current subtarget has a feature F. -class CCIfSubtarget: +class CCIfSubtarget: CCIf().", F), A>; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp Mon Nov 8 13:40:01 2010 @@ -36,7 +36,7 @@ const TargetInstrInfo *TII; static char ID; - Filler(TargetMachine &tm) + Filler(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { } virtual const char *getPassName() const { @@ -56,44 +56,44 @@ char Filler::ID = 0; } // end of anonymous namespace -static bool hasImmInstruction( MachineBasicBlock::iterator &candidate ) { +static bool hasImmInstruction(MachineBasicBlock::iterator &candidate) { // Any instruction with an immediate mode operand greater than // 16-bits requires an implicit IMM instruction. unsigned numOper = candidate->getNumOperands(); - for( unsigned op = 0; op < numOper; ++op ) { - if( candidate->getOperand(op).isImm() && - (candidate->getOperand(op).getImm() & 0xFFFFFFFFFFFF0000LL) != 0 ) + for (unsigned op = 0; op < numOper; ++op) { + if (candidate->getOperand(op).isImm() && + (candidate->getOperand(op).getImm() & 0xFFFFFFFFFFFF0000LL) != 0) return true; // FIXME: we could probably check to see if the FP value happens // to not need an IMM instruction. For now we just always // assume that FP values always do. - if( candidate->getOperand(op).isFPImm() ) + if (candidate->getOperand(op).isFPImm()) return true; } return false; } -static bool delayHasHazard( MachineBasicBlock::iterator &candidate, - MachineBasicBlock::iterator &slot ) { +static bool delayHasHazard(MachineBasicBlock::iterator &candidate, + MachineBasicBlock::iterator &slot) { // Loop over all of the operands in the branch instruction // and make sure that none of them are defined by the // candidate instruction. unsigned numOper = slot->getNumOperands(); - for( unsigned op = 0; op < numOper; ++op ) { - if( !slot->getOperand(op).isReg() || + for (unsigned op = 0; op < numOper; ++op) { + if (!slot->getOperand(op).isReg() || !slot->getOperand(op).isUse() || - slot->getOperand(op).isImplicit() ) + slot->getOperand(op).isImplicit()) continue; unsigned cnumOper = candidate->getNumOperands(); - for( unsigned cop = 0; cop < cnumOper; ++cop ) { - if( candidate->getOperand(cop).isReg() && + for (unsigned cop = 0; cop < cnumOper; ++cop) { + if (candidate->getOperand(cop).isReg() && candidate->getOperand(cop).isDef() && - candidate->getOperand(cop).getReg() == - slot->getOperand(op).getReg() ) + candidate->getOperand(cop).getReg() == + slot->getOperand(op).getReg()) return true; } } @@ -102,20 +102,20 @@ return false; } -static bool usedBeforeDelaySlot( MachineBasicBlock::iterator &candidate, - MachineBasicBlock::iterator &slot ) { +static bool usedBeforeDelaySlot(MachineBasicBlock::iterator &candidate, + MachineBasicBlock::iterator &slot) { MachineBasicBlock::iterator I = candidate; for (++I; I != slot; ++I) { unsigned numOper = I->getNumOperands(); - for( unsigned op = 0; op < numOper; ++op ) { - if( I->getOperand(op).isReg() && - I->getOperand(op).isUse() ) { + for (unsigned op = 0; op < numOper; ++op) { + if (I->getOperand(op).isReg() && + I->getOperand(op).isUse()) { unsigned reg = I->getOperand(op).getReg(); unsigned cops = candidate->getNumOperands(); - for( unsigned cop = 0; cop < cops; ++cop ) { - if( candidate->getOperand(cop).isReg() && + for (unsigned cop = 0; cop < cops; ++cop) { + if (candidate->getOperand(cop).isReg() && candidate->getOperand(cop).isDef() && - candidate->getOperand(cop).getReg() == reg ) + candidate->getOperand(cop).getReg() == reg) return true; } } @@ -130,9 +130,9 @@ MachineBasicBlock::iterator found = MBB.end(); for (MachineBasicBlock::iterator I = MBB.begin(); I != slot; ++I) { TargetInstrDesc desc = I->getDesc(); - if( desc.hasDelaySlot() || desc.isBranch() || - desc.mayLoad() || desc. mayStore() || - hasImmInstruction(I) || delayHasHazard(I,slot) || + if (desc.hasDelaySlot() || desc.isBranch() || + desc.mayLoad() || desc. mayStore() || + hasImmInstruction(I) || delayHasHazard(I,slot) || usedBeforeDelaySlot(I,slot)) continue; found = I; @@ -155,10 +155,10 @@ ++FilledSlots; Changed = true; - if( D == MBB.end() ) + if (D == MBB.end()) BuildMI(MBB, J, I->getDebugLoc(), TII->get(MBlaze::NOP)); else - MBB.splice( J, &MBB, D ); + MBB.splice(J, &MBB, D); } return Changed; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.cpp Mon Nov 8 13:40:01 2010 @@ -32,7 +32,7 @@ MBlazeELFWriterInfo::~MBlazeELFWriterInfo() {} unsigned MBlazeELFWriterInfo::getRelocationType(unsigned MachineRelTy) const { - switch(MachineRelTy) { + switch (MachineRelTy) { case MBlaze::reloc_pcrel_word: return R_MICROBLAZE_64_PCREL; case MBlaze::reloc_absolute_word: @@ -45,7 +45,7 @@ long int MBlazeELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy, long int Modifier) const { - switch(RelTy) { + switch (RelTy) { case R_MICROBLAZE_32_PCREL: return Modifier - 4; case R_MICROBLAZE_32: @@ -58,7 +58,7 @@ unsigned MBlazeELFWriterInfo::getRelocationTySize(unsigned RelTy) const { // FIXME: Most of these sizes are guesses based on the name - switch(RelTy) { + switch (RelTy) { case R_MICROBLAZE_32: case R_MICROBLAZE_32_PCREL: case R_MICROBLAZE_32_PCREL_LO: @@ -83,7 +83,7 @@ bool MBlazeELFWriterInfo::isPCRelativeRel(unsigned RelTy) const { // FIXME: Most of these are guesses based on the name - switch(RelTy) { + switch (RelTy) { case R_MICROBLAZE_32_PCREL: case R_MICROBLAZE_64_PCREL: case R_MICROBLAZE_32_PCREL_LO: Modified: llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.h?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeELFWriterInfo.h Mon Nov 8 13:40:01 2010 @@ -31,7 +31,7 @@ R_MICROBLAZE_32_LO = 6, R_MICROBLAZE_SRO32 = 7, R_MICROBLAZE_SRW32 = 8, - R_MICROBLAZE_64_NONE = 9, + R_MICROBLAZE_64_NONE = 9, R_MICROBLAZE_32_SYM_OP_SYM = 10, R_MICROBLAZE_GNU_VTINHERIT = 11, R_MICROBLAZE_GNU_VTENTRY = 12, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Mon Nov 8 13:40:01 2010 @@ -159,7 +159,6 @@ } else { Base = N.getOperand(0); } - DEBUG( errs() << "WESLEY: Using Operand Immediate\n" ); return true; // [r+i] } } else if (ConstantSDNode *CN = dyn_cast(N)) { @@ -167,7 +166,6 @@ uint32_t Imm = CN->getZExtValue(); Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0)); Base = CurDAG->getRegister(MBlaze::R0, CN->getValueType(0)); - DEBUG( errs() << "WESLEY: Using Constant Node\n" ); return true; } @@ -192,20 +190,15 @@ unsigned Opcode = Node->getOpcode(); DebugLoc dl = Node->getDebugLoc(); - // Dump information about the Node being selected - DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); - // If we have a custom node, we already have selected! - if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + if (Node->isMachineOpcode()) return NULL; - } /// // Instruction Selection not handled by the auto-generated // tablegen selection should be handled here. /// - switch(Opcode) { + switch (Opcode) { default: break; // Get target GOT address. @@ -235,8 +228,8 @@ SDValue R20Reg = CurDAG->getRegister(MBlaze::R20, MVT::i32); SDValue InFlag(0, 0); - if ( (isa(Callee)) || - (isa(Callee)) ) + if ((isa(Callee)) || + (isa(Callee))) { /// Direct call for global addresses and external symbols SDValue GPReg = CurDAG->getRegister(MBlaze::R15, MVT::i32); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Mon Nov 8 13:40:01 2010 @@ -290,7 +290,7 @@ else if (MI->getOpcode() == MBlaze::ShiftRL) BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST); else - llvm_unreachable( "Cannot lower unknown shift instruction" ); + llvm_unreachable("Cannot lower unknown shift instruction"); BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT) .addReg(SAMT) @@ -332,7 +332,7 @@ unsigned Opc; switch (MI->getOperand(4).getImm()) { - default: llvm_unreachable( "Unknown branch condition" ); + default: llvm_unreachable("Unknown branch condition"); case MBlazeCC::EQ: Opc = MBlaze::BNEID; break; case MBlazeCC::NE: Opc = MBlaze::BEQID; break; case MBlazeCC::GT: Opc = MBlaze::BLEID; break; @@ -396,9 +396,9 @@ CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS) .getValue(1); } else { - llvm_unreachable( "Cannot lower select_cc with unknown type" ); + llvm_unreachable("Cannot lower select_cc with unknown type"); } - + return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, CompareFlag); } @@ -429,7 +429,7 @@ EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); - SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0 ); + SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0); return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI); } @@ -441,7 +441,7 @@ DebugLoc dl = Op.getDebugLoc(); SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), - N->getOffset(), 0 ); + N->getOffset(), 0); return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP); } @@ -616,10 +616,10 @@ // node so that legalize doesn't hack it. if (GlobalAddressSDNode *G = dyn_cast(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, - getPointerTy(), 0, 0 ); + getPointerTy(), 0, 0); else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) Callee = DAG.getTargetExternalSymbol(S->getSymbol(), - getPointerTy(), 0 ); + getPointerTy(), 0); // MBlazeJmpLink = #chain, #target_address, #opt_in_flags... // = Chain, Callee, Reg#1, Reg#2, ... @@ -675,7 +675,7 @@ RVLocs[i].getValVT(), InFlag).getValue(1); InFlag = Chain.getValue(2); InVals.push_back(Chain.getValue(0)); - } + } return Chain; } @@ -785,7 +785,7 @@ // To meet ABI, when VARARGS are passed on registers, the registers // must have their values written to the caller stack frame. If the last - // argument was placed in the stack, there's no need to save any register. + // argument was placed in the stack, there's no need to save any register. if ((isVarArg) && ArgRegEnd) { if (StackPtr.getNode() == 0) StackPtr = DAG.getRegister(StackReg, getPointerTy()); @@ -817,7 +817,7 @@ } } - // All stores are grouped in one node to allow the matching between + // All stores are grouped in one node to allow the matching between // the size of Ins and InVals. This only happens when on varg functions if (!OutChains.empty()) { OutChains.push_back(Chain); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td Mon Nov 8 13:40:01 2010 @@ -100,11 +100,11 @@ def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>; def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>; - def LWF : LoadFM<0x32, "lw ", load>; - def LWFI : LoadFMI<0x32, "lwi ", load>; + def LWF : LoadFM<0x32, "lw ", load>; + def LWFI : LoadFMI<0x32, "lwi ", load>; - def SWF : StoreFM<0x32, "sw ", store>; - def SWFI : StoreFMI<0x32, "swi ", store>; + def SWF : StoreFM<0x32, "sw ", store>; + def SWFI : StoreFMI<0x32, "swi ", store>; } let Predicates=[HasFPU,HasSqrt] in { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td Mon Nov 8 13:40:01 2010 @@ -58,8 +58,8 @@ bits<6> FormBits = Form.Value; // Top 6 bits are the 'opcode' field - let Inst{0-5} = opcode; - + let Inst{0-5} = opcode; + // If the instruction is marked as a pseudo, set isCodeGenOnly so that the // assembler and disassmbler ignore it. let isCodeGenOnly = !eq(!cast(form), "FPseudo"); @@ -86,15 +86,15 @@ //===----------------------------------------------------------------------===// class TA op, bits<11> flags, dag outs, dag ins, string asmstr, - list pattern, InstrItinClass itin> : - MBlazeInst + list pattern, InstrItinClass itin> : + MBlazeInst { bits<5> rd; bits<5> ra; bits<5> rb; let Inst{6-10} = rd; - let Inst{11-15} = ra; + let Inst{11-15} = ra; let Inst{16-20} = rb; let Inst{21-31} = flags; } @@ -104,15 +104,15 @@ //===----------------------------------------------------------------------===// class TB op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin> : - MBlazeInst + InstrItinClass itin> : + MBlazeInst { bits<5> rd; bits<5> ra; bits<16> imm16; let Inst{6-10} = rd; - let Inst{11-15} = ra; + let Inst{11-15} = ra; let Inst{16-31} = imm16; } @@ -121,7 +121,7 @@ // the LLVM DAG : <|opcode|rd|ra|immediate|> //===----------------------------------------------------------------------===// class TBR op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin> : + InstrItinClass itin> : TB { bits<5> rrd; bits<16> rimm16; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Mon Nov 8 13:40:01 2010 @@ -64,6 +64,16 @@ // MBlaze Operand, Complex Patterns and Transformations Definitions. //===----------------------------------------------------------------------===// +def MBlazeMemAsmOperand : AsmOperandClass { + let Name = "Mem"; + let SuperClasses = []; +} + +def MBlazeFslAsmOperand : AsmOperandClass { + let Name = "Fsl"; + let SuperClasses = []; +} + // Instruction operand types def brtarget : Operand; def calltarget : Operand; @@ -79,17 +89,20 @@ // FSL Operand def fslimm : Operand { let PrintMethod = "printFSLImm"; + let ParserMatchClass = MBlazeFslAsmOperand; } // Address operand def memri : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops simm16, GPR); + let ParserMatchClass = MBlazeMemAsmOperand; } def memrr : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR, GPR); + let ParserMatchClass = MBlazeMemAsmOperand; } // Node immediate fits as 16-bit sign extended on target immediate. @@ -490,31 +503,31 @@ hasCtrlDep=1, rd=0x10, Form=FCRI in { def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), "rtsd $target, $imm", - [], + [], IIBranch>; } let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, rd=0x11, Form=FCRI in { def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), - "rtsd $target, $imm", - [], + "rtid $target, $imm", + [], IIBranch>; } let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, rd=0x12, Form=FCRI in { def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), - "rtsd $target, $imm", - [], + "rtbd $target, $imm", + [], IIBranch>; } let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, rd=0x14, Form=FCRI in { def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), - "rtsd $target, $imm", - [], + "rted $target, $imm", + [], IIBranch>; } @@ -551,20 +564,20 @@ let rb = 0 in { def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src), - "sext16 $dst, $src", [], IIAlu>; + "sext16 $dst, $src", [], IIAlu>; def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src), - "sext8 $dst, $src", [], IIAlu>; + "sext8 $dst, $src", [], IIAlu>; def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src), - "srl $dst, $src", [], IIAlu>; + "srl $dst, $src", [], IIAlu>; def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src), - "sra $dst, $src", [], IIAlu>; + "sra $dst, $src", [], IIAlu>; def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src), - "src $dst, $src", [], IIAlu>; + "src $dst, $src", [], IIAlu>; } let opcode=0x08, isCodeGenOnly=1 in { def LEA_ADDI : TB<0x08, (outs GPR:$dst), (ins memri:$addr), - "addi $dst, ${addr:stackloc}", + "addi $dst, ${addr:stackloc}", [(set GPR:$dst, iaddr:$addr)], IIAlu>; } @@ -584,7 +597,7 @@ } let rd=0x0, Form=FCRR in { - def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), + def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), "wdc $a, $b", [], IIAlu>; def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b), "wdc.flush $a, $b", [], IIAlu>; @@ -597,7 +610,7 @@ def BRK : Branch<0x26, 0x0C, 0x000, "brk ">; def BRKI : BranchI<0x2E, 0x0C, "brki ">; -def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), +def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), "imm $imm", [], IIAlu>; //===----------------------------------------------------------------------===// @@ -633,42 +646,42 @@ // SET_CC operations def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMP GPR:$L, GPR:$R), 1)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMP GPR:$L, GPR:$R), 2)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMP GPR:$L, GPR:$R), 3)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMP GPR:$L, GPR:$R), 4)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMP GPR:$L, GPR:$R), 5)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMP GPR:$L, GPR:$R), 6)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMPU GPR:$L, GPR:$R), 3)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMPU GPR:$L, GPR:$R), 4)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMPU GPR:$L, GPR:$R), 5)>; def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), - (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), + (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (CMPU GPR:$L, GPR:$R), 6)>; // SELECT operations def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)), (Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>; -// SELECT_CC -def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), +// SELECT_CC +def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), (i32 GPR:$T), (i32 GPR:$F), SETEQ), (Select_CC GPR:$T, GPR:$F, (CMP GPR:$L, GPR:$R), 1)>; def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), Modified: llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp Mon Nov 8 13:40:01 2010 @@ -48,7 +48,7 @@ assert(!isOverloaded(IntrID) && "MBlaze intrinsics are not overloaded"); if (IntrID < Intrinsic::num_intrinsics) return 0; - assert(IntrID < mblazeIntrinsic::num_mblaze_intrinsics && + assert(IntrID < mblazeIntrinsic::num_mblaze_intrinsics && "Invalid intrinsic ID"); std::string Result(names[IntrID - Intrinsic::num_intrinsics]); @@ -94,12 +94,12 @@ const Type *ResultTy = NULL; std::vector ArgTys; bool IsVarArg = false; - + #define GET_INTRINSIC_GENERATOR #include "MBlazeGenIntrinsics.inc" #undef GET_INTRINSIC_GENERATOR - return FunctionType::get(ResultTy, ArgTys, IsVarArg); + return FunctionType::get(ResultTy, ArgTys, IsVarArg); } Function *MBlazeIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsics.td Mon Nov 8 13:40:01 2010 @@ -1,10 +1,10 @@ //===- IntrinsicsMBlaze.td - Defines MBlaze intrinsics -----*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines all of the MicroBlaze-specific intrinsics. @@ -16,7 +16,7 @@ // // MBlaze intrinsic classes. -let TargetPrefix = "mblaze", isTarget = 1 in { +let TargetPrefix = "mblaze", isTarget = 1 in { class MBFSL_Get_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>; class MBFSL_Put_Intrinsic : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h Mon Nov 8 13:40:01 2010 @@ -19,7 +19,7 @@ namespace llvm { class Target; - + class MBlazeMCAsmInfo : public MCAsmInfo { public: explicit MBlazeMCAsmInfo(); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Mon Nov 8 13:40:01 2010 @@ -94,7 +94,7 @@ void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, raw_ostream &OS) const { - assert(Size <= 8 && "size too big in emit constant" ); + assert(Size <= 8 && "size too big in emit constant"); for (unsigned i = 0; i != Size; ++i) { EmitByte(Val & 255, CurByte, OS); @@ -103,7 +103,7 @@ } void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const; - void EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte, + void EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte, raw_ostream &OS) const; void EmitImmediate(const MCInst &MI, @@ -132,7 +132,7 @@ return MBlazeRegisterInfo::getRegisterNumbering(MO.getReg()); else if (MO.isImm()) return static_cast(MO.getImm()); - else if (MO.isExpr() ) + else if (MO.isExpr()) return 0; // The relocation has already been recorded at this point. else { #ifndef NDEBUG @@ -146,7 +146,7 @@ void MBlazeMCCodeEmitter:: EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const { int32_t val = (int32_t)imm.getImm(); - if (val > 32767 || val < -32678 ) { + if (val > 32767 || val < -32678) { EmitByte(0x0D, CurByte, OS); EmitByte(0x00, CurByte, OS); EmitRawByte((val >> 24) & 0xFF, CurByte, OS); @@ -155,7 +155,7 @@ } void MBlazeMCCodeEmitter:: -EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte, +EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte, raw_ostream &OS) const { MCOperand mcop = MI.getOperand(op); if (mcop.isExpr()) { @@ -170,11 +170,11 @@ EmitImmediate(const MCInst &MI, unsigned opNo, MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, SmallVectorImpl &Fixups) const { - assert( MI.getNumOperands()>opNo && "Not enought operands for instruction" ); + assert(MI.getNumOperands()>opNo && "Not enought operands for instruction"); MCOperand oper = MI.getOperand(opNo); if (oper.isImm()) { - EmitIMM( oper, CurByte, OS ); + EmitIMM(oper, CurByte, OS); } else if (oper.isExpr()) { Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind)); } @@ -198,25 +198,25 @@ return; case MBlazeII::FRRI: - EmitImmediate( MI, 2, FK_Data_4, CurByte, OS, Fixups ); + EmitImmediate(MI, 2, FK_Data_4, CurByte, OS, Fixups); break; case MBlazeII::FRIR: - EmitImmediate( MI, 1, FK_Data_4, CurByte, OS, Fixups ); + EmitImmediate(MI, 1, FK_Data_4, CurByte, OS, Fixups); break; case MBlazeII::FCRI: - EmitImmediate( MI, 1, MCFixupKind(MBlaze::reloc_pcrel_2byte), CurByte, OS, - Fixups ); + EmitImmediate(MI, 1, MCFixupKind(MBlaze::reloc_pcrel_2byte), CurByte, OS, + Fixups); break; case MBlazeII::FRCI: - EmitImmediate( MI, 1, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS, - Fixups ); + EmitImmediate(MI, 1, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS, + Fixups); case MBlazeII::FCCI: - EmitImmediate( MI, 0, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS, - Fixups ); + EmitImmediate(MI, 0, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS, + Fixups); break; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCInstLower.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCInstLower.cpp Mon Nov 8 13:40:01 2010 @@ -32,7 +32,7 @@ MCSymbol *MBlazeMCInstLower:: GetGlobalAddressSymbol(const MachineOperand &MO) const { switch (MO.getTargetFlags()) { - default: + default: llvm_unreachable("Unknown target flag on GV operand"); case 0: break; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMachineFunction.h Mon Nov 8 13:40:01 2010 @@ -26,11 +26,11 @@ class MBlazeFunctionInfo : public MachineFunctionInfo { private: - /// Holds for each function where on the stack the Frame Pointer must be + /// Holds for each function where on the stack the Frame Pointer must be /// saved. This is used on Prologue and Epilogue to emit FP save/restore int FPStackOffset; - /// Holds for each function where on the stack the Return Address must be + /// Holds for each function where on the stack the Return Address must be /// saved. This is used on Prologue and Epilogue to emit RA save/restore int RAStackOffset; @@ -50,22 +50,22 @@ : FI(FrameIndex), SPOffset(StackPointerOffset) {} }; - /// When PIC is used the GP must be saved on the stack on the function - /// prologue and must be reloaded from this stack location after every - /// call. A reference to its stack location and frame index must be kept + /// When PIC is used the GP must be saved on the stack on the function + /// prologue and must be reloaded from this stack location after every + /// call. A reference to its stack location and frame index must be kept /// to be used on emitPrologue and processFunctionBeforeFrameFinalized. MBlazeFIHolder GPHolder; /// On LowerFormalArguments the stack size is unknown, so the Stack - /// Pointer Offset calculation of "not in register arguments" must be - /// postponed to emitPrologue. + /// Pointer Offset calculation of "not in register arguments" must be + /// postponed to emitPrologue. SmallVector FnLoadArgs; bool HasLoadArgs; - // When VarArgs, we must write registers back to caller stack, preserving - // on register arguments. Since the stack size is unknown on + // When VarArgs, we must write registers back to caller stack, preserving + // on register arguments. Since the stack size is unknown on // LowerFormalArguments, the Stack Pointer Offset calculation must be - // postponed to emitPrologue. + // postponed to emitPrologue. SmallVector FnStoreVarArgs; bool HasStoreVarArgs; @@ -83,8 +83,8 @@ int VarArgsFrameIndex; public: - MBlazeFunctionInfo(MachineFunction& MF) - : FPStackOffset(0), RAStackOffset(0), CPUTopSavedRegOff(0), + MBlazeFunctionInfo(MachineFunction& MF) + : FPStackOffset(0), RAStackOffset(0), CPUTopSavedRegOff(0), GPHolder(-1,-1), HasLoadArgs(false), HasStoreVarArgs(false), SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0) {} @@ -105,7 +105,7 @@ bool needGPSaveRestore() const { return GPHolder.SPOffset != -1; } bool hasLoadArgs() const { return HasLoadArgs; } - bool hasStoreVarArgs() const { return HasStoreVarArgs; } + bool hasStoreVarArgs() const { return HasStoreVarArgs; } void recordLoadArgsFI(int FI, int SPOffset) { if (!HasLoadArgs) HasLoadArgs=true; @@ -118,13 +118,13 @@ void adjustLoadArgsFI(MachineFrameInfo *MFI) const { if (!hasLoadArgs()) return; - for (unsigned i = 0, e = FnLoadArgs.size(); i != e; ++i) - MFI->setObjectOffset( FnLoadArgs[i].FI, FnLoadArgs[i].SPOffset ); + for (unsigned i = 0, e = FnLoadArgs.size(); i != e; ++i) + MFI->setObjectOffset(FnLoadArgs[i].FI, FnLoadArgs[i].SPOffset); } void adjustStoreVarArgsFI(MachineFrameInfo *MFI) const { - if (!hasStoreVarArgs()) return; - for (unsigned i = 0, e = FnStoreVarArgs.size(); i != e; ++i) - MFI->setObjectOffset( FnStoreVarArgs[i].FI, FnStoreVarArgs[i].SPOffset ); + if (!hasStoreVarArgs()) return; + for (unsigned i = 0, e = FnStoreVarArgs.size(); i != e; ++i) + MFI->setObjectOffset(FnStoreVarArgs[i].FI, FnStoreVarArgs[i].SPOffset); } unsigned getSRetReturnReg() const { return SRetReturnReg; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Nov 8 13:40:01 2010 @@ -25,8 +25,8 @@ class Type; namespace MBlaze { - /// SubregIndex - The index of various sized subregister classes. Note that - /// these indices must be kept in sync with the class indices in the + /// SubregIndex - The index of various sized subregister classes. Note that + /// these indices must be kept in sync with the class indices in the /// MBlazeRegisterInfo.td file. enum SubregIndex { SUBREG_FPEVEN = 1, SUBREG_FPODD = 2 @@ -36,7 +36,7 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo { const MBlazeSubtarget &Subtarget; const TargetInstrInfo &TII; - + MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget, const TargetInstrInfo &tii); @@ -70,7 +70,7 @@ void emitPrologue(MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - + /// Debug information queries. unsigned getRARegister() const; unsigned getFrameRegister(const MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSchedule.td?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSchedule.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSchedule.td Mon Nov 8 13:40:01 2010 @@ -14,7 +14,7 @@ def IMULDIV : FuncUnit; //===----------------------------------------------------------------------===// -// Instruction Itinerary classes used for MBlaze +// Instruction Itinerary classes used for MBlaze //===----------------------------------------------------------------------===// def IIAlu : InstrItinClass; def IILoad : InstrItinClass; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Mon Nov 8 13:40:01 2010 @@ -61,7 +61,7 @@ // Register the MC code emitter TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget, llvm::createMBlazeMCCodeEmitter); - + // Register the asm backend TargetRegistry::RegisterAsmBackend(TheMBlazeTarget, createMBlazeAsmBackend); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetObjectFile.h?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetObjectFile.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetObjectFile.h Mon Nov 8 13:40:01 2010 @@ -18,10 +18,9 @@ const MCSection *SmallDataSection; const MCSection *SmallBSSSection; public: - + void Initialize(MCContext &Ctx, const TargetMachine &TM); - /// IsGlobalInSmallSection - Return true if this global address should be /// placed into small data/bss section. bool IsGlobalInSmallSection(const GlobalValue *GV, @@ -29,8 +28,8 @@ SectionKind Kind) const; bool IsGlobalInSmallSection(const GlobalValue *GV, - const TargetMachine &TM) const; - + const TargetMachine &TM) const; + const MCSection *SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, Modified: llvm/trunk/lib/Target/MBlaze/TODO URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/TODO?rev=118434&r1=118433&r2=118434&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/TODO (original) +++ llvm/trunk/lib/Target/MBlaze/TODO Mon Nov 8 13:40:01 2010 @@ -1,8 +1,5 @@ * Writing out ELF files is close to working but the following needs to be examined more closely: - - ELF files are written with the wrong E_MACHINE value because - ELFObjectWriter::WriteHeader function does not yet support - target specific E_MACHINE values. - ELF relocation records are incorrect because the function ELFObjectWriter::RecordRelocation is hard coded for X86/X86-64. - Relocations use 2-byte / 4-byte to terminology in reference to @@ -32,3 +29,11 @@ and need to be updated to model the MicroBlaze correctly. - Look at the MBlazeGenFastISel.inc stuff and make use of it if appropriate. + +* A basic assembly parser is present now and seems to parse most things. + There are a few things that need to be looked at: + - There are some instructions that are not generated by the backend + and have not been tested as far as the parser is concerned. + - The assembly parser does not use any MicroBlaze specific directives. + I should investigate if there are MicroBlaze specific directive and, + if there are, add them. From gkistanova at gmail.com Mon Nov 8 13:47:01 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 8 Nov 2010 11:47:01 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r118431 - /llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi In-Reply-To: References: <20101108193229.AED412A6C12D@llvm.org> Message-ID: Thanks for correction, Anton. I will change the name. Thanks Galina On Mon, Nov 8, 2010 at 11:39 AM, Anton Korobeynikov wrote: >> ? ?llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi > One small problem: >> + ? ? ?--target=arm-eabi ? ? ? ? \ > and >> + ? ? ?--with-float=hard ? ? ? ? \ >> + ? ? ?--with-abi=aapcs ? ? ? ? ?\ > is definitely *not* gnueabi :) > > Otherwise - ok for me. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > From baldrick at free.fr Mon Nov 8 13:51:10 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 20:51:10 +0100 Subject: [llvm-commits] [llvm] r118417 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll In-Reply-To: <10A6830F-42A9-4DDE-840C-26CBF99858E8@apple.com> References: <20101108171204.51D092A6C12C@llvm.org> <4CD8376C.6060604@free.fr> <10A6830F-42A9-4DDE-840C-26CBF99858E8@apple.com> Message-ID: <4CD854AE.2000900@free.fr> Hi Dan, >>> @@ -140,10 +141,14 @@ >>> for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); >>> CI != CE; ++CI) { >>> Value *Arg = *CI; >>> - if (Arg->getType()->isPointerTy()&& >>> - !AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) >>> - // Writes memory. Just give up. >>> - return false; >>> + if (Arg->getType()->isPointerTy()) { >>> + AliasAnalysis::Location Loc(Arg, >>> + AliasAnalysis::UnknownSize, >>> + I->getMetadata(LLVMContext::MD_tbaa)); >>> + if (!AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) >> >> Shouldn't it be Loc not Arg in the call to pointsToConstantMemory? > > Oops, yes. Fixed. since the test was passing in spite of this, maybe it could do with a stronger testcase? Ciao, Duncan. From gohman at apple.com Mon Nov 8 13:52:49 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 8 Nov 2010 11:52:49 -0800 Subject: [llvm-commits] [llvm] r118410 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll In-Reply-To: <4CD825EC.5040300@free.fr> References: <20101108161016.02D322A6C12C@llvm.org> <4CD825EC.5040300@free.fr> Message-ID: On Nov 8, 2010, at 8:31 AM, Duncan Sands wrote: > Hi Dan, > >> Make FunctionAttrs use AliasAnalysis::getModRefBehavior, now that it >> knows about intrinsic functions. > > I always took care to *not* have function attributes make any use of > alias analysis. Partly this is to have the function attributes pass > stay fast, partly from a feeling that function attributes should be > layered below alias analysis not on top of it, and partly because using > alias analysis doesn't (or didn't in the past) win you much. That said, > I can understand the temptation to have it use alias analysis - but what > is the cost/benefit ratio? FunctionAttrs' PointsToLocalOrConstantMemory was basically just a slightly smarter version of BasicAliasAnalysis' pointsToConstantMemory, so I ported the additional features over (which is useful on its own). Subsequently, the FunctionAttrs code was redundant. Also, using AliasAnalysis gives FunctionAttrs the ability to take advantage of TBAA information without much extra effort. I see that there is a conceptual layering issue: FunctionAttrs uses AA, and AA uses the results of FunctionAttrs. However, it's the same problem whether FunctionAttrs duplicates BasicAliasAnalysis' code or calls it, so I don't see a strong reason to prefer duplicating. For speed, the BasicAA implementation is basically the same as the FunctionAttrs one (except the recursion check, which I'll address), and the TBAA implementation is cheap, so I don't expect there will be a big difference. >> @@ -167,26 +171,35 @@ >> // Some instructions can be ignored even if they read or write memory. >> // Detect these now, skipping to the next instruction if one is found. >> CallSite CS(cast(I)); >> - if (CS&& CS.getCalledFunction()) { >> + if (CS) { >> // Ignore calls to functions in the same SCC. >> - if (SCCNodes.count(CS.getCalledFunction())) >> + if (CS.getCalledFunction()&& SCCNodes.count(CS.getCalledFunction())) >> + continue; > > Shouldn't this be: > if (!CS.getCalledFunction() || SCCNodes.count(CS.getCalledFunction())) > ? I don't think so. Indirect calls need to be handled conservatively, since the callee may not be in the current SCC. Dan From gkistanova at gmail.com Mon Nov 8 14:06:25 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 08 Nov 2010 20:06:25 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118436 - /llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat Message-ID: <20101108200625.B79572A6C12C@llvm.org> Author: gkistanova Date: Mon Nov 8 14:06:25 2010 New Revision: 118436 URL: http://llvm.org/viewvc/llvm-project?rev=118436&view=rev Log: Added script for arm-eabi llvm-gcc cross build which will replace existing script build-x-4-gnueabi. Added: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat (with props) Added: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat?rev=118436&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat (added) +++ llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat Mon Nov 8 14:06:25 2010 @@ -0,0 +1,220 @@ +#!/bin/bash + +set -e # Terminate script at the first line that fails. +set -o pipefail # Return the first non-zero pipe command error. +set -x # Print commands as they are executed + +# This script performs an automated build on i686-pc-linux-gnu of +# cross llvm-gcc for arm-eabi-hard-float. It assumes the valid native +# compiler for i686-pc-linux-gnu is in place and available as well as +# cross libraries and headers for arm-eabi. + +# --build=i686-pc-linux-gnu +# --host=i686-pc-linux-gnu +# --target=arm-eabi +# + +# The usage: +# Run this build from the build from the build root directory as +# build-x-4-armeabi-hardfloat [] [] + +# Expected project tree structure: +# +# +-- ${LLVM_src} +# +-- ${LLVM_GCC_src} +# +-- ${LLVM_obj} +# +-- ${LLVM_GCC_obj} +# +-- ${INSTALL} + +LLVM_src=llvm.src # The LLVM source code root directory name. +LLVM_GCC_src=llvm-gcc.src # The LLVM-GCC source code root directory name. +LLVM_obj=llvm.obj # The LLVM build root directory name. +LLVM_GCC_obj=llvm-gcc.obj # The LLVM-GCC build root directory name. +INSTALL=install # Where the result will be installed. + +BUILD_ROOT=$PWD # Where build happens. +PRIVATE_INSTALL=${BUILD_ROOT}/${INSTALL} # Where the result will be installed. + +#------------------------------------------------------------------------------ +# Define build steps, parse and validate input parameters +#------------------------------------------------------------------------------ + +# This script supports the following steps: +do_clean=no # Clean up the build directory. +do_copy_cross_tools=no # Copy cross-tools. +do_configure_llvm=no # Configure LLVM. +do_make_llvm=no # Make LLVM. +do_install_llvm=no # Install LLVM-GCC. +do_test_llvm=no # Test LLVM. +do_configure_llvmgcc=no # Configure LLVM-GCC. +do_make_llvmgcc=no # Make LLVM-GCC. +do_install_llvmgcc=no # Install LLVM-GCC. +do_all=no # Runs all steps at once when requested. + +# Set step parameter +if (( $# == 0 )) ; then + do_all=yes +fi +# else +if (( ! $# == 0 )) ; then + # First check that the parameter actually defines a step. + case $1 in + clean | \ + copy_cross_tools | \ + configure_llvm | \ + make_llvm | \ + install_llvm | \ + test_llvm | \ + configure_llvmgcc | \ + make_llvmgcc | \ + install_llvmgcc | \ + all) + eval do_$1=yes # Set the flag for the requested step . + shift # Remove it since is is ours and already precessed. + ;; + + *) + # Not our parameter. Pass it as is. + esac +fi + +# Set all steps if do_all requested +if [ "$do_all" == "yes" ] ; then + # Set all steps to yes + do_clean=yes + do_copy_cross_tools=yes + do_configure_llvm=yes + do_make_llvm=yes + do_install_llvm=yes + do_test_llvm=yes + do_configure_llvmgcc=yes + do_make_llvmgcc=yes + do_install_llvmgcc=yes +fi + +#------------------------------------------------------------------------------ +# Step: Clean up. +#------------------------------------------------------------------------------ +if [ "$do_clean" == "yes" ] ; then + + # Remove everything from where we will be installing the result. + rm -rf ${PRIVATE_INSTALL} + mkdir -p ${PRIVATE_INSTALL} + chmod a+rx ${PRIVATE_INSTALL} + +fi + +#------------------------------------------------------------------------------ +# Step: Copy cross-tools and newlib +#------------------------------------------------------------------------------ +if [ "$do_copy_cross_tools" == "yes" ] ; then + + # We need a local copy of binutils, system libraries and headers, + # since we will be installing there. + cp -Ru /opt/cross-tools/* ${PRIVATE_INSTALL} + cp -Ru /opt/newlib-src/newlib/ ${BUILD_ROOT}/${LLVM_GCC_src} + cp -Ru /opt/newlib-src/libgloss/ ${BUILD_ROOT}/${LLVM_GCC_src} + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvm" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_obj} + cd ${BUILD_ROOT}/${LLVM_obj} + + ../${LLVM_src}/configure --prefix=${PRIVATE_INSTALL} \ + --enable-optimized \ + --enable-targets=cbe,arm \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM. +#------------------------------------------------------------------------------ +if [ "$do_make_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM. +#------------------------------------------------------------------------------ +if [ "$do_install_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make install VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Test LLVM. +#------------------------------------------------------------------------------ +if [ "$do_test_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + make check-lit VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvmgcc" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_GCC_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_GCC_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_GCC_obj} + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + + ../${LLVM_GCC_src}/configure --prefix=${PRIVATE_INSTALL} \ + --target=arm-eabi \ + --enable-languages=c,c++ \ + --disable-nls \ + --prefix=/opt/cross-tools \ + --program-prefix=llvm- \ + --with-newlib \ + --with-headers=yes \ + --enable-llvm=${BUILD_ROOT}/${LLVM_obj} \ + --with-cpu=cortex-a8 \ + --with-fpu=neon \ + --with-float=hard \ + --with-abi=aapcs \ + $@ # Extra args if any +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_make_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_install_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make install \ + $@ # Extra args if any + +fi Propchange: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat ------------------------------------------------------------------------------ svn:executable = * From gkistanova at gmail.com Mon Nov 8 14:16:51 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 08 Nov 2010 20:16:51 -0000 Subject: [llvm-commits] [zorg] r118437 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20101108201651.9F7722A6C12C@llvm.org> Author: gkistanova Date: Mon Nov 8 14:16:51 2010 New Revision: 118437 URL: http://llvm.org/viewvc/llvm-project?rev=118437&view=rev Log: Changed builder name for arm-eabi llvm-gcc cross build. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=118437&r1=118436&r2=118437&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov 8 14:16:51 2010 @@ -522,9 +522,9 @@ 'haltOnFailure' : True },]), 'category' : 'llvm-gcc' }, - {'name' : "llvm-gcc-i686-pc-linux-gnu-cross-gnueabi", + {'name' : "llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-hard-float", 'slavenames': [ "kistanova4" ], - 'builddir' : "llvm-gcc-i686-pc-linux-gnu-cross-gnueabi", + 'builddir' : "llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-hard-float", 'factory' : ScriptedBuilder.getScriptedBuildFactory( source_code = [SVN(name='svn-llvm', mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/', @@ -535,7 +535,7 @@ defaultBranch='trunk', workdir="llvm-gcc.src"),], launcher = 'llvm-gcc.src/extras/buildbot-launcher', - build_script = 'llvm-gcc.src/extras/build-x-4-gnueabi', + build_script = 'llvm-gcc.src/extras/build-x-4-armeabi-hardfloat', extra_args = [], build_steps = [{'name' : 'clean', 'description' : 'clean', From gohman at apple.com Mon Nov 8 14:20:11 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 20:20:11 -0000 Subject: [llvm-commits] [llvm] r118439 - /llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Message-ID: <20101108202011.9425C2A6C12C@llvm.org> Author: djg Date: Mon Nov 8 14:20:11 2010 New Revision: 118439 URL: http://llvm.org/viewvc/llvm-project?rev=118439&view=rev Log: Add a testcase for a call which BasicAA says only accesses memory through its arguments and which TBAA says doesn't write to memory. Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll?rev=118439&r1=118438&r2=118439&view=diff ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll (original) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Mon Nov 8 14:20:11 2010 @@ -2,6 +2,13 @@ ; FunctionAttrs should make use of TBAA. +; Add the readnone attribute, since the only access is a store which TBAA +; says is to constant memory. +; +; It's unusual to see a store to constant memory, but it isn't necessarily +; invalid, as it's possible that this only happens after optimization on a +; code path which isn't ever executed. + ; CHECK: define void @test0_yes(i32* nocapture %p) nounwind readnone { define void @test0_yes(i32* %p) nounwind { store i32 0, i32* %p, !tbaa !1 @@ -14,6 +21,9 @@ ret void } +; Add the readonly attribute, since there's just a call to a function which +; TBAA says doesn't modify any memory. + ; CHECK: define void @test1_yes(i32* %p) nounwind readonly { define void @test1_yes(i32* %p) nounwind { call void @callee(i32* %p), !tbaa !1 @@ -26,7 +36,27 @@ ret void } +; Add the readonly attribute, as above, but this time BasicAA will say +; that the function accesses memory through its arguments, which TBAA +; still says that the function doesn't write to memory. +; +; This is unusual, since the function is memcpy, but as above, this +; isn't necessarily invalid. + +; CHECK: define void @test2_yes(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind readnone { +define void @test2_yes(i8* %p, i8* %q, i64 %n) nounwind { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !1 + ret void +} + +; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind { +define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !2 + ret void +} + declare void @callee(i32* %p) nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) nounwind ; Root note. !0 = metadata !{ } From gohman at apple.com Mon Nov 8 14:22:42 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 8 Nov 2010 12:22:42 -0800 Subject: [llvm-commits] [llvm] r118417 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll In-Reply-To: <4CD854AE.2000900@free.fr> References: <20101108171204.51D092A6C12C@llvm.org> <4CD8376C.6060604@free.fr> <10A6830F-42A9-4DDE-840C-26CBF99858E8@apple.com> <4CD854AE.2000900@free.fr> Message-ID: On Nov 8, 2010, at 11:51 AM, Duncan Sands wrote: > Hi Dan, > >>>> @@ -140,10 +141,14 @@ >>>> for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); >>>> CI != CE; ++CI) { >>>> Value *Arg = *CI; >>>> - if (Arg->getType()->isPointerTy()&& >>>> - !AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) >>>> - // Writes memory. Just give up. >>>> - return false; >>>> + if (Arg->getType()->isPointerTy()) { >>>> + AliasAnalysis::Location Loc(Arg, >>>> + AliasAnalysis::UnknownSize, >>>> + I->getMetadata(LLVMContext::MD_tbaa)); >>>> + if (!AA->pointsToConstantMemory(Arg, /*OrLocal=*/true)) >>> >>> Shouldn't it be Loc not Arg in the call to pointsToConstantMemory? >> >> Oops, yes. Fixed. > > since the test was passing in spite of this, maybe it could do with a stronger > testcase? Makes sense. I've added one now. Dan From gohman at apple.com Mon Nov 8 14:26:19 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 20:26:19 -0000 Subject: [llvm-commits] [llvm] r118440 - /llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <20101108202619.960BB2A6C12C@llvm.org> Author: djg Date: Mon Nov 8 14:26:19 2010 New Revision: 118440 URL: http://llvm.org/viewvc/llvm-project?rev=118440&view=rev Log: Re-introduce the MaxLookup limit to BasicAliasAnalysis' pointsToConstantMemory code to guard against possible compile time slowdowns. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=118440&r1=118439&r2=118440&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Nov 8 14:26:19 2010 @@ -524,6 +524,7 @@ BasicAliasAnalysis::pointsToConstantMemory(const Location &Loc, bool OrLocal) { assert(Visited.empty() && "Visited must be cleared after use!"); + unsigned MaxLookup = 8; SmallVector Worklist; Worklist.push_back(Loc.Ptr); do { @@ -559,6 +560,11 @@ // If all values incoming to a phi node point to local memory, then so does // the phi. if (const PHINode *PN = dyn_cast(V)) { + // Don't bother inspecting phi nodes with many operands. + if (PN->getNumIncomingValues() > MaxLookup) { + Visited.clear(); + return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); + } for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) Worklist.push_back(PN->getIncomingValue(i)); continue; @@ -568,10 +574,10 @@ Visited.clear(); return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal); - } while (!Worklist.empty()); + } while (!Worklist.empty() && --MaxLookup); Visited.clear(); - return true; + return Worklist.empty(); } /// getModRefBehavior - Return the behavior when calling the given call site. From gohman at apple.com Mon Nov 8 14:29:49 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 8 Nov 2010 12:29:49 -0800 Subject: [llvm-commits] [llvm] r118412 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/AliasAnalysisCounter.cpp lib/Analysis/AliasDebugger.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/NoAliasAnalysis.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-12-29-Constant.ll In-Reply-To: <4CD836A6.1070207@free.fr> References: <20101108164526.CE29F2A6C12C@llvm.org> <4CD836A6.1070207@free.fr> Message-ID: <8E3EBC97-A1EF-4D22-A698-0346506D00CA@apple.com> On Nov 8, 2010, at 9:43 AM, Duncan Sands wrote: > Hi Dan, > >> +/// pointsToConstantMemory - Returns whether the given pointer value >> +/// points to memory that is local to the function, with global constants being >> +/// considered local to all functions. >> +bool >> +BasicAliasAnalysis::pointsToConstantMemory(const Location&Loc, bool OrLocal) { >> + assert(Visited.empty()&& "Visited must be cleared after use!"); >> + >> + SmallVector Worklist; >> + Worklist.push_back(Loc.Ptr); > > you should really put a limit on how deep you want to allow the "recursion" to > go. IIRC, the reason that PointsToLocalOrConstantMemory had a limit is that it > was seen to take a long time on some crazy testcase. Ok. Dan From gkistanova at gmail.com Mon Nov 8 14:42:12 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 8 Nov 2010 12:42:12 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r118431 - /llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi In-Reply-To: References: <20101108193229.AED412A6C12D@llvm.org> Message-ID: The existing waterfall builder llvm-gcc-i686-pc-linux-gnu-cross-gnueabi will be replaced by llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-hard-float as master pick up new configurations. It is the same builder with corrected name. Thank you Anton for your assistance. Thanks Galina On Mon, Nov 8, 2010 at 11:39 AM, Anton Korobeynikov wrote: >> ? ?llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi > One small problem: >> + ? ? ?--target=arm-eabi ? ? ? ? \ > and >> + ? ? ?--with-float=hard ? ? ? ? \ >> + ? ? ?--with-abi=aapcs ? ? ? ? ?\ > is definitely *not* gnueabi :) > > Otherwise - ok for me. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > From bigcheesegs at gmail.com Mon Nov 8 14:50:58 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Mon, 8 Nov 2010 15:50:58 -0500 Subject: [llvm-commits] [llvm] r118367 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Unix/Path.inc lib/System/Win32/Path.inc In-Reply-To: <878w14fu5p.fsf@telefonica.net> References: <20101107043650.C10C82A6C136@llvm.org> <4CD68A44.4040307@free.fr> <878w14fu5p.fsf@telefonica.net> Message-ID: On Sun, Nov 7, 2010 at 9:04 PM, ?scar Fuentes wrote: > Michael Spencer > writes: > >>>> Doesn't windows support a kind of symbolic link nowadays? >>> >>> Not sure. Michael? :-) >> >> Yes it does. I think it was added to NTFS in Vista. I'm not sure how >> to check for one, but I'll look into it. > > Something like this should do (untested): > > WIN32_FILE_ATTRIBUTE_DATA fileData; > GetFileAttributesEx("some_file", GetFileExInfoStandard, &fileData); > if( fileData.dwFileAttributes & FILE_ATTRIBUTE_REPARSE_POINT ) { > .... > } > Attached is a patch that implements it. I would like to discus one part before committing though: bool Path::isSymLink() const { DWORD attributes = GetFileAttributes(path.c_str()); if (attributes == INVALID_FILE_ATTRIBUTES) // There's no sane way to report this :(. report_fatal_error("GetFileAttributes returned INVALID_FILE_ATTRIBUTES"); // This isn't exactly what defines a NTFS symlink, but it is only true for // paths that act like a symlink. return attributes & FILE_ATTRIBUTE_REPARSE_POINT; } Most of the other code in System (for both Windows and Unix) ignores errors. This has been a big issue in bugpoint, which currently treats quite a few errors (not bugs) in System as errors in the code generator because it's currently impossible to get errors from System. I know we plan to rewrite System::Path, but that doesn't seem to be happening any time soon. So I would like to start explicitly failing instead of silently failing way down the line. My ideal world would be to use a C++03 implementation of std::error_code (which is currently already part of KillTheDoctor), but that's a much larger change. I understand the argument that errors such as "file not found" are the same as saying the path is not a symlink, however, there are other errors such as permissions, out of memory, other crazyness, etc... that are not the same. They do not tell you one way or the other if the path is a symlink (or whatever attribute is in question). - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: implement-isSymLink.patch Type: application/octet-stream Size: 1119 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101108/e803cffc/attachment.obj From baldrick at free.fr Mon Nov 8 14:56:00 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 21:56:00 +0100 Subject: [llvm-commits] [llvm] r118410 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-10-04-LocalMemory.ll In-Reply-To: References: <20101108161016.02D322A6C12C@llvm.org> <4CD825EC.5040300@free.fr> Message-ID: <4CD863E0.8000001@free.fr> Hi Dan, >>> Make FunctionAttrs use AliasAnalysis::getModRefBehavior, now that it >>> knows about intrinsic functions. >> >> I always took care to *not* have function attributes make any use of >> alias analysis. Partly this is to have the function attributes pass >> stay fast, partly from a feeling that function attributes should be >> layered below alias analysis not on top of it, and partly because using >> alias analysis doesn't (or didn't in the past) win you much. That said, >> I can understand the temptation to have it use alias analysis - but what >> is the cost/benefit ratio? > > FunctionAttrs' PointsToLocalOrConstantMemory was basically just a slightly > smarter version of BasicAliasAnalysis' pointsToConstantMemory, so I ported > the additional features over (which is useful on its own). Subsequently, the > FunctionAttrs code was redundant. Also, using AliasAnalysis gives > FunctionAttrs the ability to take advantage of TBAA information without > much extra effort. > > I see that there is a conceptual layering issue: FunctionAttrs uses AA, > and AA uses the results of FunctionAttrs. However, it's the same problem > whether FunctionAttrs duplicates BasicAliasAnalysis' code or calls it, > so I don't see a strong reason to prefer duplicating. > > For speed, the BasicAA implementation is basically the same as the > FunctionAttrs one (except the recursion check, which I'll address), and > the TBAA implementation is cheap, so I don't expect there will be a > big difference. fair enough, thanks for the explanation. >>> @@ -167,26 +171,35 @@ >>> // Some instructions can be ignored even if they read or write memory. >>> // Detect these now, skipping to the next instruction if one is found. >>> CallSite CS(cast(I)); >>> - if (CS&& CS.getCalledFunction()) { >>> + if (CS) { >>> // Ignore calls to functions in the same SCC. >>> - if (SCCNodes.count(CS.getCalledFunction())) >>> + if (CS.getCalledFunction()&& SCCNodes.count(CS.getCalledFunction())) >>> + continue; >> >> Shouldn't this be: >> if (!CS.getCalledFunction() || SCCNodes.count(CS.getCalledFunction())) >> ? > > I don't think so. Indirect calls need to be handled conservatively, > since the callee may not be in the current SCC. You are correct. I misread the effect of the change - previously this case was handled conservatively too. Ciao, Duncan. From baldrick at free.fr Mon Nov 8 14:56:28 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 08 Nov 2010 20:56:28 -0000 Subject: [llvm-commits] [llvm] r118441 - /llvm/trunk/test/Transforms/InstCombine/select.ll Message-ID: <20101108205628.30F582A6C12C@llvm.org> Author: baldrick Date: Mon Nov 8 14:56:28 2010 New Revision: 118441 URL: http://llvm.org/viewvc/llvm-project?rev=118441&view=rev Log: Add an additional test for icmp of select folding. Modified: llvm/trunk/test/Transforms/InstCombine/select.ll Modified: llvm/trunk/test/Transforms/InstCombine/select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select.ll?rev=118441&r1=118440&r2=118441&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/select.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/select.ll Mon Nov 8 14:56:28 2010 @@ -488,3 +488,14 @@ ; CHECK: @test39 ; CHECK: ret i1 true } + +define i1 @test40(i1 %cond) { + %a = alloca i32 + %b = alloca i32 + %c = alloca i32 + %s = select i1 %cond, i32* %a, i32* %b + %r = icmp eq i32* %s, %c + ret i1 %r +; CHECK: @test40 +; CHECK: ret i1 false +} From bigcheesegs at gmail.com Mon Nov 8 14:56:32 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 08 Nov 2010 20:56:32 -0000 Subject: [llvm-commits] [llvm] r118442 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20101108205632.C5A1A2A6C12D@llvm.org> Author: mspencer Date: Mon Nov 8 14:56:32 2010 New Revision: 118442 URL: http://llvm.org/viewvc/llvm-project?rev=118442&view=rev Log: Remove contributor names as per coding statndard. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118442&r1=118441&r2=118442&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Mon Nov 8 14:56:32 2010 @@ -5,9 +5,6 @@ // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -// Modified by Henrik Bach to comply with at least MinGW. -// Ported to Win32 by Jeff Cohen. -// //===----------------------------------------------------------------------===// // // This file provides the Win32 specific implementation of the Path class. From bruno.cardoso at gmail.com Mon Nov 8 15:24:59 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 08 Nov 2010 21:24:59 -0000 Subject: [llvm-commits] [llvm] r118445 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20101108212459.58EF32A6C12C@llvm.org> Author: bruno Date: Mon Nov 8 15:24:59 2010 New Revision: 118445 URL: http://llvm.org/viewvc/llvm-project?rev=118445&view=rev Log: Fix PR8211 Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=118445&r1=118444&r2=118445&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 8 15:24:59 2010 @@ -5775,6 +5775,12 @@ def : Pat<(X86Movlps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVLPSrm VR128:$src1, addr:$src2)>; +// FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem +// is during lowering, where it's not possible to recognize the load fold cause +// it has two uses through a bitcast. One use disappears at isel time and the +// fold opportunity reappears. +def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)), + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>; // Shuffle with MOVLPD def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), From isanbard at gmail.com Mon Nov 8 15:28:03 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 08 Nov 2010 21:28:03 -0000 Subject: [llvm-commits] [llvm] r118446 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Message-ID: <20101108212803.863F82A6C12C@llvm.org> Author: void Date: Mon Nov 8 15:28:03 2010 New Revision: 118446 URL: http://llvm.org/viewvc/llvm-project?rev=118446&view=rev Log: Add "write back" bit encoding. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118446&r1=118445&r2=118446&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 8 15:28:03 2010 @@ -80,14 +80,16 @@ reglist:$dsts, variable_ops), IndexModeNone, IIC_fpLoad_m, "vldm${amode}${p}\t$Rn, $dsts", "", []> { - let Inst{20} = 1; + let Inst{21} = 0; // wback = (W == '1') + let Inst{20} = 1; // Load } def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, IIC_fpLoad_m, "vldm${amode}${p}\t$Rn, $dsts", "", []> { - let Inst{20} = 1; + let Inst{21} = 0; // wback = (W == '1') + let Inst{20} = 1; // Load } def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, @@ -95,7 +97,8 @@ IndexModeUpd, IIC_fpLoad_mu, "vldm${amode}${p}\t$Rn!, $dsts", "$Rn = $wb", []> { - let Inst{20} = 1; + let Inst{21} = 1; // wback = (W == '1') + let Inst{20} = 1; // Load } def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, @@ -103,7 +106,8 @@ IndexModeUpd, IIC_fpLoad_mu, "vldm${amode}${p}\t$Rn!, $dsts", "$Rn = $wb", []> { - let Inst{20} = 1; + let Inst{21} = 1; // wback = (W == '1') + let Inst{20} = 1; // Load } } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq @@ -113,14 +117,16 @@ reglist:$srcs, variable_ops), IndexModeNone, IIC_fpStore_m, "vstm${amode}${p}\t$Rn, $srcs", "", []> { - let Inst{20} = 0; + let Inst{21} = 0; // wback = (W == '1') + let Inst{20} = 0; // Store } def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeNone, IIC_fpStore_m, "vstm${amode}${p}\t$Rn, $srcs", "", []> { - let Inst{20} = 0; + let Inst{21} = 0; // wback = (W == '1') + let Inst{20} = 0; // Store } def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, @@ -128,7 +134,8 @@ IndexModeUpd, IIC_fpStore_mu, "vstm${amode}${p}\t$Rn!, $srcs", "$Rn = $wb", []> { - let Inst{20} = 0; + let Inst{21} = 1; // wback = (W == '1') + let Inst{20} = 0; // Store } def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, @@ -136,7 +143,8 @@ IndexModeUpd, IIC_fpStore_mu, "vstm${amode}${p}\t$Rn!, $srcs", "$Rn = $wb", []> { - let Inst{20} = 0; + let Inst{21} = 1; // wback = (W == '1') + let Inst{20} = 0; // Store } } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq From jasonwkim at google.com Mon Nov 8 15:36:48 2010 From: jasonwkim at google.com (Jason Kim) Date: Mon, 8 Nov 2010 13:36:48 -0800 Subject: [llvm-commits] buildbot failure in smooshlab on llvm-gcc-i386-darwin9 In-Reply-To: <20101108184058.4D2EBB59B95D@mail-out3.apple.com> References: <20101108184058.4D2EBB59B95D@mail-out3.apple.com> Message-ID: On Mon, Nov 8, 2010 at 10:40 AM, wrote: > > Last 10 lines of '2010-10-19-mc-elf-objheader.ll': > ? ? ? ?/Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-i386-darwin9/llvm.src/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll:22:13: error: expected string not found in input > ? ? ? ?; CORTEXA8: .ARM.attributes > > Last 10 lines of '2010-10-19-mc-elf-objheader.ll': > ? ? ? ?/Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-i386-darwin9/llvm.src/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll:22:13: error: expected string not found in input > ? ? ? ?; CORTEXA8: .ARM.attributes > ? ? ? ? ? ? ? ? ? ?^ Hi everyone. Sorry about the build breakage - I haven't had a chance to reproduce it here on a local darwin machine, but I suspect that it was a case of LLC not producing ELF. (probably due to missing -mtriple=arm-linux-gnueabi on the test) I'll double check on a local mac before I recommit this. Thanks. -jason From bruno.cardoso at gmail.com Mon Nov 8 15:42:32 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 08 Nov 2010 21:42:32 -0000 Subject: [llvm-commits] [llvm] r118447 - in /llvm/trunk/lib/Target/Mips: Mips.td MipsDelaySlotFiller.cpp MipsSubtarget.h Message-ID: <20101108214233.061952A6C12C@llvm.org> Author: bruno Date: Mon Nov 8 15:42:32 2010 New Revision: 118447 URL: http://llvm.org/viewvc/llvm-project?rev=118447&view=rev Log: Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka at mips.com) Modified: llvm/trunk/lib/Target/Mips/Mips.td llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.h Modified: llvm/trunk/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=118447&r1=118446&r2=118447&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips.td (original) +++ llvm/trunk/lib/Target/Mips/Mips.td Mon Nov 8 15:42:32 2010 @@ -36,19 +36,15 @@ "Support 64-bit FP registers.">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; -def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", - "Mips1 ISA Support">; -def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", - "Mips2 ISA Support">; def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", "Enable o32 ABI">; def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", "Enable eabi ABI">; -def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", +def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true", "Enable vector FPU instructions.">; -def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", +def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", "Enable 'signext in register' instructions.">; -def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", +def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", "Enable 'conditional move' instructions.">; def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true", "Enable 'multiply add/sub' instructions.">; @@ -58,6 +54,15 @@ "Enable 'byte/half swap' instructions.">; def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", "Enable 'count leading bits' instructions.">; +def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", + "Mips1 ISA Support">; +def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", + "Mips2 ISA Support">; +def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", + "Mips32 ISA Support", [FeatureCondMov]>; +def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", + "Mips32r2", "Mips32r2 ISA Support", + [FeatureMips32, FeatureSEInReg]>; //===----------------------------------------------------------------------===// // Mips processors supported. @@ -73,10 +78,12 @@ def : Proc<"mips2", [FeatureMips2]>; def : Proc<"r6000", [FeatureMips2]>; -// Allegrex is a 32bit subset of r4000, both for interger and fp registers, -// but much more similar to Mips2 than Mips3. It also contains some of -// Mips32/Mips32r2 instructions and a custom vector fpu processor. -def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, +def : Proc<"4ke", [FeatureMips32r2]>; + +// Allegrex is a 32bit subset of r4000, both for interger and fp registers, +// but much more similar to Mips2 than Mips3. It also contains some of +// Mips32/Mips32r2 instructions and a custom vector fpu processor. +def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd, FeatureMinMax, FeatureSwap, FeatureBitCount]>; Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=118447&r1=118446&r2=118447&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Mon Nov 8 15:42:32 2010 @@ -59,7 +59,8 @@ { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) - if (I->getDesc().hasDelaySlot()) { + if (TM.getSubtarget().isMips1() && + I->getDesc().hasDelaySlot()) { MachineBasicBlock::iterator J = I; ++J; BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP)); Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=118447&r1=118446&r2=118447&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Mon Nov 8 15:42:32 2010 @@ -100,6 +100,8 @@ const std::string &CPU); bool isMips1() const { return MipsArchVersion == Mips1; } + bool isMips32() const { return MipsArchVersion == Mips32; } + bool isMips32r2() const { return MipsArchVersion == Mips32r2; } bool isLittle() const { return IsLittle; } bool isFP64bit() const { return IsFP64bit; } From gkistanova at gmail.com Mon Nov 8 15:58:03 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 08 Nov 2010 21:58:03 -0000 Subject: [llvm-commits] [zorg] r118449 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20101108215803.E2FF42A6C12C@llvm.org> Author: gkistanova Date: Mon Nov 8 15:58:03 2010 New Revision: 118449 URL: http://llvm.org/viewvc/llvm-project?rev=118449&view=rev Log: Change category for builder llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-hard-float. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=118449&r1=118448&r2=118449&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov 8 15:58:03 2010 @@ -564,7 +564,7 @@ {'name' : 'install_llvmgcc', 'description' : 'install llvm-gcc', 'haltOnFailure' : True },]), - 'category' : 'llvm-gcc.exp' }, + 'category' : 'llvm-gcc' }, {'name' : "clang-i686-linux-selfhost-rel", 'slavenames' : ["osu8"], From criswell at uiuc.edu Mon Nov 8 16:54:55 2010 From: criswell at uiuc.edu (John Criswell) Date: Mon, 08 Nov 2010 22:54:55 -0000 Subject: [llvm-commits] [poolalloc] r118452 - /poolalloc/trunk/lib/DSA/Local.cpp Message-ID: <20101108225455.B52B82A6C12C@llvm.org> Author: criswell Date: Mon Nov 8 16:54:55 2010 New Revision: 118452 URL: http://llvm.org/viewvc/llvm-project?rev=118452&view=rev Log: Removed unneeded white space. No functionality changes. Modified: poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=118452&r1=118451&r2=118452&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Mon Nov 8 16:54:55 2010 @@ -613,7 +613,7 @@ Offset = 0; break; } - } else if (const PointerType *PtrTy = dyn_cast(*I)) { + } else if (const PointerType *PtrTy = dyn_cast(*I)) { const Type *CurTy = PtrTy->getElementType(); // From resistor at mac.com Mon Nov 8 17:21:22 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 08 Nov 2010 23:21:22 -0000 Subject: [llvm-commits] [llvm] r118453 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vceq.ll test/CodeGen/ARM/vcge.ll test/CodeGen/ARM/vcgt.ll test/MC/ARM/neon-cmp-encoding.s Message-ID: <20101108232122.680622A6C12C@llvm.org> Author: resistor Date: Mon Nov 8 17:21:22 2010 New Revision: 118453 URL: http://llvm.org/viewvc/llvm-project?rev=118453&view=rev Log: Add support for ARM's specialized vector-compare-against-zero instructions. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/vceq.ll llvm/trunk/test/CodeGen/ARM/vcge.ll llvm/trunk/test/CodeGen/ARM/vcgt.ll llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 8 17:21:22 2010 @@ -3074,7 +3074,38 @@ if (Swap) std::swap(Op0, Op1); - SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); + // If one of the operands is a constant vector zero, attempt to fold the + // comparison to a specialized compare-against-zero form. + SDValue SingleOp; + if (ISD::isBuildVectorAllZeros(Op1.getNode())) + SingleOp = Op0; + else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { + if (Opc == ARMISD::VCGE) + Opc = ARMISD::VCLEZ; + else if (Opc == ARMISD::VCGT) + Opc = ARMISD::VCLTZ; + SingleOp = Op1; + } + + SDValue Result; + if (SingleOp.getNode()) { + switch (Opc) { + case ARMISD::VCEQ: + Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; + case ARMISD::VCGE: + Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; + case ARMISD::VCLEZ: + Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; + case ARMISD::VCGT: + Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; + case ARMISD::VCLTZ: + Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; + default: + Result = DAG.getNode(Opc, dl, VT, Op0, Op1); + } + } else { + Result = DAG.getNode(Opc, dl, VT, Op0, Op1); + } if (Invert) Result = DAG.getNOT(dl, Result, VT); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Nov 8 17:21:22 2010 @@ -87,9 +87,14 @@ PRELOAD, // Preload VCEQ, // Vector compare equal. + VCEQZ, // Vector compare equal to zero. VCGE, // Vector compare greater than or equal. + VCGEZ, // Vector compare greater than or equal to zero. + VCLEZ, // Vector compare less than or equal to zero. VCGEU, // Vector compare unsigned greater than or equal. VCGT, // Vector compare greater than. + VCGTZ, // Vector compare greater than zero. + VCLTZ, // Vector compare less than zero. VCGTU, // Vector compare unsigned greater than. VTST, // Vector test bits. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 8 17:21:22 2010 @@ -16,11 +16,17 @@ //===----------------------------------------------------------------------===// def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; +def SDTARMVCMPZ : SDTypeProfile<1, 1, []>; def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; +def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>; def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; +def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>; +def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>; def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; +def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>; +def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>; def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; @@ -2150,36 +2156,44 @@ // First with only element sizes of 8, 16 and 32 bits: multiclass N2V_QHS_cmp op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op4, string opc, string Dt, - string asm> { + string asm, SDNode OpNode> { // 64-bit vector types. def v8i8 : N2V; + opc, !strconcat(Dt, "8"), asm, "", + [(set DPR:$dst, (v8i8 (OpNode (v8i8 DPR:$src))))]>; def v4i16 : N2V; + opc, !strconcat(Dt, "16"), asm, "", + [(set DPR:$dst, (v4i16 (OpNode (v4i16 DPR:$src))))]>; def v2i32 : N2V; + opc, !strconcat(Dt, "32"), asm, "", + [(set DPR:$dst, (v2i32 (OpNode (v2i32 DPR:$src))))]>; def v2f32 : N2V { + opc, "f32", asm, "", + [(set DPR:$dst, (v2f32 (OpNode (v2f32 DPR:$src))))]> { let Inst{10} = 1; // overwrite F = 1 } // 128-bit vector types. def v16i8 : N2V; + opc, !strconcat(Dt, "8"), asm, "", + [(set QPR:$dst, (v16i8 (OpNode (v16i8 QPR:$src))))]>; def v8i16 : N2V; + opc, !strconcat(Dt, "16"), asm, "", + [(set QPR:$dst, (v8i16 (OpNode (v8i16 QPR:$src))))]>; def v4i32 : N2V; + opc, !strconcat(Dt, "32"), asm, "", + [(set QPR:$dst, (v4i32 (OpNode (v4i32 QPR:$src))))]>; def v4f32 : N2V { + opc, "f32", asm, "", + [(set QPR:$dst, (v4f32 (OpNode (v4f32 QPR:$src))))]> { let Inst{10} = 1; // overwrite F = 1 } } @@ -3220,9 +3234,9 @@ NEONvceq, 1>; def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, NEONvceq, 1>; -// For disassembly only. + defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i", - "$dst, $src, #0">; + "$dst, $src, #0", NEONvceqz>; // VCGE : Vector Compare Greater Than or Equal defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, @@ -3233,14 +3247,11 @@ NEONvcge, 0>; def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32, NEONvcge, 0>; -// For disassembly only. -// FIXME: This instruction's encoding MAY NOT BE correct. + defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s", - "$dst, $src, #0">; -// For disassembly only. -// FIXME: This instruction's encoding MAY NOT BE correct. + "$dst, $src, #0", NEONvcgez>; defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s", - "$dst, $src, #0">; + "$dst, $src, #0", NEONvclez>; // VCGT : Vector Compare Greater Than defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, @@ -3251,14 +3262,11 @@ NEONvcgt, 0>; def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32, NEONvcgt, 0>; -// For disassembly only. -// FIXME: This instruction's encoding MAY NOT BE correct. + defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s", - "$dst, $src, #0">; -// For disassembly only. -// FIXME: This instruction's encoding MAY NOT BE correct. + "$dst, $src, #0", NEONvcgtz>; defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s", - "$dst, $src, #0">; + "$dst, $src, #0", NEONvcltz>; // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge", Modified: llvm/trunk/test/CodeGen/ARM/vceq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vceq.ll?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vceq.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vceq.ll Mon Nov 8 17:21:22 2010 @@ -79,3 +79,14 @@ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 } + +define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind { +;CHECK: vceqi8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vceq.i8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp eq <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} Modified: llvm/trunk/test/CodeGen/ARM/vcge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcge.ll?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcge.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vcge.ll Mon Nov 8 17:21:22 2010 @@ -160,3 +160,25 @@ declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone + +define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind { +;CHECK: vcgei8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vcge.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp sge <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} + +define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind { +;CHECK: vclei8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vcle.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp sle <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} Modified: llvm/trunk/test/CodeGen/ARM/vcgt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcgt.ll?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vcgt.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vcgt.ll Mon Nov 8 17:21:22 2010 @@ -173,3 +173,25 @@ declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone + +define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { +;CHECK: vcgti8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vcgt.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp sgt <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} + +define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind { +;CHECK: vclti8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vclt.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp slt <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.s?rev=118453&r1=118452&r2=118453&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-cmp-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Mon Nov 8 17:21:22 2010 @@ -102,3 +102,14 @@ vtst.16 q8, q8, q9 @ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] vtst.32 q8, q8, q9 + +@ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3] + vceq.i8 d16, d16, #0 +@ CHECK: vcge.s8 d16, d16, #0 @ encoding: [0xa0,0x00,0xf1,0xf3] + vcge.s8 d16, d16, #0 +@ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3] + vcle.s8 d16, d16, #0 +@ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3] + vcgt.s8 d16, d16, #0 +@ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3] + vclt.s8 d16, d16, #0 From bob.wilson at apple.com Mon Nov 8 17:33:04 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 8 Nov 2010 15:33:04 -0800 Subject: [llvm-commits] [llvm] r118453 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vceq.ll test/CodeGen/ARM/vcge.ll test/CodeGen/ARM/vcgt.ll test/MC/ARM/neon-cmp-encoding.s In-Reply-To: <20101108232122.680622A6C12C@llvm.org> References: <20101108232122.680622A6C12C@llvm.org> Message-ID: <345994C0-2C4F-4F46-B464-D15617F90615@apple.com> Ooh, nice! On Nov 8, 2010, at 3:21 PM, Owen Anderson wrote: > Author: resistor > Date: Mon Nov 8 17:21:22 2010 > New Revision: 118453 > > URL: http://llvm.org/viewvc/llvm-project?rev=118453&view=rev > Log: > Add support for ARM's specialized vector-compare-against-zero instructions. > > Modified: > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.h > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/test/CodeGen/ARM/vceq.ll > llvm/trunk/test/CodeGen/ARM/vcge.ll > llvm/trunk/test/CodeGen/ARM/vcgt.ll > llvm/trunk/test/MC/ARM/neon-cmp-encoding.s > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 8 17:21:22 2010 > @@ -3074,7 +3074,38 @@ > if (Swap) > std::swap(Op0, Op1); > > - SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); > + // If one of the operands is a constant vector zero, attempt to fold the > + // comparison to a specialized compare-against-zero form. > + SDValue SingleOp; > + if (ISD::isBuildVectorAllZeros(Op1.getNode())) > + SingleOp = Op0; > + else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { > + if (Opc == ARMISD::VCGE) > + Opc = ARMISD::VCLEZ; > + else if (Opc == ARMISD::VCGT) > + Opc = ARMISD::VCLTZ; > + SingleOp = Op1; > + } > + > + SDValue Result; > + if (SingleOp.getNode()) { > + switch (Opc) { > + case ARMISD::VCEQ: > + Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; > + case ARMISD::VCGE: > + Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; > + case ARMISD::VCLEZ: > + Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; > + case ARMISD::VCGT: > + Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; > + case ARMISD::VCLTZ: > + Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; > + default: > + Result = DAG.getNode(Opc, dl, VT, Op0, Op1); > + } > + } else { > + Result = DAG.getNode(Opc, dl, VT, Op0, Op1); > + } > > if (Invert) > Result = DAG.getNOT(dl, Result, VT); > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Nov 8 17:21:22 2010 > @@ -87,9 +87,14 @@ > PRELOAD, // Preload > > VCEQ, // Vector compare equal. > + VCEQZ, // Vector compare equal to zero. > VCGE, // Vector compare greater than or equal. > + VCGEZ, // Vector compare greater than or equal to zero. > + VCLEZ, // Vector compare less than or equal to zero. > VCGEU, // Vector compare unsigned greater than or equal. > VCGT, // Vector compare greater than. > + VCGTZ, // Vector compare greater than zero. > + VCLTZ, // Vector compare less than zero. > VCGTU, // Vector compare unsigned greater than. > VTST, // Vector test bits. > > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 8 17:21:22 2010 > @@ -16,11 +16,17 @@ > //===----------------------------------------------------------------------===// > > def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; > +def SDTARMVCMPZ : SDTypeProfile<1, 1, []>; > > def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; > +def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>; > def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; > +def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>; > +def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>; > def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; > def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; > +def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>; > +def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>; > def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; > def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; > > @@ -2150,36 +2156,44 @@ > // First with only element sizes of 8, 16 and 32 bits: > multiclass N2V_QHS_cmp op24_23, bits<2> op21_20, bits<2> op17_16, > bits<5> op11_7, bit op4, string opc, string Dt, > - string asm> { > + string asm, SDNode OpNode> { > // 64-bit vector types. > def v8i8 : N2V (outs DPR:$dst), (ins DPR:$src), NoItinerary, > - opc, !strconcat(Dt, "8"), asm, "", []>; > + opc, !strconcat(Dt, "8"), asm, "", > + [(set DPR:$dst, (v8i8 (OpNode (v8i8 DPR:$src))))]>; > def v4i16 : N2V (outs DPR:$dst), (ins DPR:$src), NoItinerary, > - opc, !strconcat(Dt, "16"), asm, "", []>; > + opc, !strconcat(Dt, "16"), asm, "", > + [(set DPR:$dst, (v4i16 (OpNode (v4i16 DPR:$src))))]>; > def v2i32 : N2V (outs DPR:$dst), (ins DPR:$src), NoItinerary, > - opc, !strconcat(Dt, "32"), asm, "", []>; > + opc, !strconcat(Dt, "32"), asm, "", > + [(set DPR:$dst, (v2i32 (OpNode (v2i32 DPR:$src))))]>; > def v2f32 : N2V (outs DPR:$dst), (ins DPR:$src), NoItinerary, > - opc, "f32", asm, "", []> { > + opc, "f32", asm, "", > + [(set DPR:$dst, (v2f32 (OpNode (v2f32 DPR:$src))))]> { > let Inst{10} = 1; // overwrite F = 1 > } > > // 128-bit vector types. > def v16i8 : N2V (outs QPR:$dst), (ins QPR:$src), NoItinerary, > - opc, !strconcat(Dt, "8"), asm, "", []>; > + opc, !strconcat(Dt, "8"), asm, "", > + [(set QPR:$dst, (v16i8 (OpNode (v16i8 QPR:$src))))]>; > def v8i16 : N2V (outs QPR:$dst), (ins QPR:$src), NoItinerary, > - opc, !strconcat(Dt, "16"), asm, "", []>; > + opc, !strconcat(Dt, "16"), asm, "", > + [(set QPR:$dst, (v8i16 (OpNode (v8i16 QPR:$src))))]>; > def v4i32 : N2V (outs QPR:$dst), (ins QPR:$src), NoItinerary, > - opc, !strconcat(Dt, "32"), asm, "", []>; > + opc, !strconcat(Dt, "32"), asm, "", > + [(set QPR:$dst, (v4i32 (OpNode (v4i32 QPR:$src))))]>; > def v4f32 : N2V (outs QPR:$dst), (ins QPR:$src), NoItinerary, > - opc, "f32", asm, "", []> { > + opc, "f32", asm, "", > + [(set QPR:$dst, (v4f32 (OpNode (v4f32 QPR:$src))))]> { > let Inst{10} = 1; // overwrite F = 1 > } > } > @@ -3220,9 +3234,9 @@ > NEONvceq, 1>; > def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, > NEONvceq, 1>; > -// For disassembly only. > + > defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i", > - "$dst, $src, #0">; > + "$dst, $src, #0", NEONvceqz>; > > // VCGE : Vector Compare Greater Than or Equal > defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, > @@ -3233,14 +3247,11 @@ > NEONvcge, 0>; > def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32, > NEONvcge, 0>; > -// For disassembly only. > -// FIXME: This instruction's encoding MAY NOT BE correct. > + > defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s", > - "$dst, $src, #0">; > -// For disassembly only. > -// FIXME: This instruction's encoding MAY NOT BE correct. > + "$dst, $src, #0", NEONvcgez>; > defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s", > - "$dst, $src, #0">; > + "$dst, $src, #0", NEONvclez>; > > // VCGT : Vector Compare Greater Than > defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, > @@ -3251,14 +3262,11 @@ > NEONvcgt, 0>; > def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32, > NEONvcgt, 0>; > -// For disassembly only. > -// FIXME: This instruction's encoding MAY NOT BE correct. > + > defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s", > - "$dst, $src, #0">; > -// For disassembly only. > -// FIXME: This instruction's encoding MAY NOT BE correct. > + "$dst, $src, #0", NEONvcgtz>; > defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s", > - "$dst, $src, #0">; > + "$dst, $src, #0", NEONvcltz>; > > // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) > def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge", > > Modified: llvm/trunk/test/CodeGen/ARM/vceq.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vceq.ll?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vceq.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vceq.ll Mon Nov 8 17:21:22 2010 > @@ -79,3 +79,14 @@ > %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> > ret <4 x i32> %tmp4 > } > + > +define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind { > +;CHECK: vceqi8Z: > +;CHECK-NOT: vmov > +;CHECK-NOT: vmvn > +;CHECK: vceq.i8 > + %tmp1 = load <8 x i8>* %A > + %tmp3 = icmp eq <8 x i8> %tmp1, > + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> > + ret <8 x i8> %tmp4 > +} > > Modified: llvm/trunk/test/CodeGen/ARM/vcge.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcge.ll?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vcge.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vcge.ll Mon Nov 8 17:21:22 2010 > @@ -160,3 +160,25 @@ > > declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone > declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone > + > +define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind { > +;CHECK: vcgei8Z: > +;CHECK-NOT: vmov > +;CHECK-NOT: vmvn > +;CHECK: vcge.s8 > + %tmp1 = load <8 x i8>* %A > + %tmp3 = icmp sge <8 x i8> %tmp1, > + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> > + ret <8 x i8> %tmp4 > +} > + > +define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind { > +;CHECK: vclei8Z: > +;CHECK-NOT: vmov > +;CHECK-NOT: vmvn > +;CHECK: vcle.s8 > + %tmp1 = load <8 x i8>* %A > + %tmp3 = icmp sle <8 x i8> %tmp1, > + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> > + ret <8 x i8> %tmp4 > +} > > Modified: llvm/trunk/test/CodeGen/ARM/vcgt.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcgt.ll?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vcgt.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vcgt.ll Mon Nov 8 17:21:22 2010 > @@ -173,3 +173,25 @@ > > declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone > declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone > + > +define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { > +;CHECK: vcgti8Z: > +;CHECK-NOT: vmov > +;CHECK-NOT: vmvn > +;CHECK: vcgt.s8 > + %tmp1 = load <8 x i8>* %A > + %tmp3 = icmp sgt <8 x i8> %tmp1, > + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> > + ret <8 x i8> %tmp4 > +} > + > +define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind { > +;CHECK: vclti8Z: > +;CHECK-NOT: vmov > +;CHECK-NOT: vmvn > +;CHECK: vclt.s8 > + %tmp1 = load <8 x i8>* %A > + %tmp3 = icmp slt <8 x i8> %tmp1, > + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> > + ret <8 x i8> %tmp4 > +} > > Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.s?rev=118453&r1=118452&r2=118453&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/neon-cmp-encoding.s (original) > +++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Mon Nov 8 17:21:22 2010 > @@ -102,3 +102,14 @@ > vtst.16 q8, q8, q9 > @ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] > vtst.32 q8, q8, q9 > + > +@ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3] > + vceq.i8 d16, d16, #0 > +@ CHECK: vcge.s8 d16, d16, #0 @ encoding: [0xa0,0x00,0xf1,0xf3] > + vcge.s8 d16, d16, #0 > +@ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3] > + vcle.s8 d16, d16, #0 > +@ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3] > + vcgt.s8 d16, d16, #0 > +@ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3] > + vclt.s8 d16, d16, #0 > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Nov 8 17:41:36 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 8 Nov 2010 15:41:36 -0800 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: References: <20101108175807.8543A2A6C12C@llvm.org> Message-ID: <15B2412D-4A1A-4831-817E-53C4B598420A@apple.com> On Nov 8, 2010, at 10:41 AM, Jason Kim wrote: > On Mon, Nov 8, 2010 at 10:37 AM, Anton Korobeynikov > wrote: >> Hi Jason, >> >>> + if (CPUString != "generic") { >>> + if (CPUString == "cortex-a8") { >> This looks pretty gross. Is it possible to generalize stuff somehow? >> E.g. via the mapping of CPU names => supported attributes. > > I agree its very gross. I am going to be iterating over this repeatedly. > I don't yet have a clear understanding of the space of cpu/attributes yet. > As I get more familiarized with how GNU/as does things, I will be > refactoring these. > it's also wrong. What about other cpu's which are cortex-a8 variants and later? Do we have to get this patch in now? Can you table it until you have figured out how to match these to subtarget attributes? Evan > >> >> -- >> With best regards, Anton Korobeynikov >> Faculty of Mathematics and Mechanics, Saint Petersburg State University >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Nov 8 17:46:03 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 08 Nov 2010 23:46:03 -0000 Subject: [llvm-commits] [llvm] r118455 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101108234603.0AF2A2A6C12C@llvm.org> Author: djg Date: Mon Nov 8 17:46:02 2010 New Revision: 118455 URL: http://llvm.org/viewvc/llvm-project?rev=118455&view=rev Log: Add some comments noting some correspondences between ModRefBehavior values, LLVM IR function attributes, and LLVM intrinsic attributes. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118455&r1=118454&r2=118455&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Nov 8 17:46:02 2010 @@ -185,10 +185,14 @@ // or stores to memory. // // This property corresponds to the GCC 'const' attribute. + // This property corresponds to the LLVM IR 'readnone' attribute. + // This property corresponds to the IntrNoMem LLVM intrinsic flag. DoesNotAccessMemory, // AccessesArguments - This function accesses function arguments in well // known (possibly volatile) ways, but does not access any other memory. + // + // This property corresponds to the IntrReadWriteArgMem LLVM intrinsic flag. AccessesArguments, // AccessesArgumentsAndGlobals - This function has accesses function @@ -200,6 +204,8 @@ // volatile loads, but may read from any memory location. // // This property corresponds to the GCC 'pure' attribute. + // This property corresponds to the LLVM IR 'readonly' attribute. + // This property corresponds to the IntrReadMem LLVM intrinsic flag. OnlyReadsMemory, // UnknownModRefBehavior - This indicates that the function could not be From geek4civic at gmail.com Mon Nov 8 17:48:47 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 9 Nov 2010 08:48:47 +0900 Subject: [llvm-commits] [PATCH] Add some options to configure for Cygming In-Reply-To: References: Message-ID: Ping. 2010/10/23 NAKAMURA Takumi : > Good evening, guys! > > I would like to add a few options to configure for tweaking cygming build. > Please take a look into them. > > I don't have suitable version of autoconf. > When patches would be applicable, please feel free to commit one > with regenerating configure, thank you. > > ...Takumi > > * 0001-Autoconf-2.63.patch (local patch) > > ?It is attached for consistency. It should not be committed. > > * 0002-autoconf-Add-enable-docs-to-enable-disable-buiding-a.patch > > ?--enable-docs=yes by default. > ?Some MSYS distros have incomplete pod2html, and "make install" fails. > ?with --disable-docs, building and installing docs is suppressed. > > * 0003-autoconf-PR7874-Add-disable-pthreads-to-suppress-det.patch > > ?--enable-pthreads=yes by default. > ?It would be needed to build pthread*.dll-free binaries on mingw. > ?Without this patch, it would be impossible to build with > ENABLE_THREADS=1 without pthread.h > ?[PR7874] > > * 0004-autoconf-Add-disable-embed-stdcxx-to-suppress-linkin.patch > > ?--enable-embed-stdcxx=yes by default. Use with --enable-shared. > ?Some cygming distros have it's own stdc++.dll. > ?By default, tools/llvm-shlib does not use stdc++.dll but link > stdc++.a included for kludge. > ?Cygwin-1.7's gcc-4.4 has its own stdc++.dll and is applicable. > ?With --disable-embed-stdcxx, tools/llvm-shlib uses cygwin's stdc++.dll. > From geek4civic at gmail.com Mon Nov 8 17:51:03 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 9 Nov 2010 08:51:03 +0900 Subject: [llvm-commits] [Review request] test: Add the new feature "loadable_module" In-Reply-To: References: Message-ID: Ping. 2010/10/21 NAKAMURA Takumi : > Hello. > > Cygming can build Module.dll for Opt and Bugpoint with autoconf. > > I will propose two patches attached. Please give me comments. > > > * 0001 - Add the feature "loadable_module" > > By default, "loadable_module" is 1. > On cygwin and win32(s), it obeys ENABLE_SHARED. > > It should not have any sideeffects, I believe. > > > * 0002 - patches for 4 tests > > Without "loadable_module", all of 4 tests marks as "UNSUPPORTED". > > I have confirmed (both enable_shared) on CentOS5, Cygwin and Mingw. > > I have confirmed with cmake on Mingw. > IIRC, cmake/mingw and cmake/msvc set ENABLE_SHARED as '0'. > I believe it might not affect msvc buildbots. > > > ps. LLVMHello.dll can be built manually :) > (or seek llvmdev or here with "llvmhello") > > > Enjoy happy testing, ...Takumi > From isanbard at gmail.com Mon Nov 8 17:49:57 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 08 Nov 2010 23:49:57 -0000 Subject: [llvm-commits] [llvm] r118456 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101108234957.6C2442A6C12C@llvm.org> Author: void Date: Mon Nov 8 17:49:57 2010 New Revision: 118456 URL: http://llvm.org/viewvc/llvm-project?rev=118456&view=rev Log: The "addRegListOperands()" function returns the start register and the total number of registers in the list. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118456&r1=118455&r2=118456&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Nov 8 17:49:57 2010 @@ -221,6 +221,20 @@ bool isRegList() const { return Kind == RegisterList; } bool isToken() const { return Kind == Token; } bool isMemory() const { return Kind == Memory; } + bool isMemMode5() const { + if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted || + Mem.Writeback || Mem.Negative) + return false; + // If there is an offset expression, make sure it's valid. + if (!Mem.Offset) + return true; + const MCConstantExpr *CE = dyn_cast(Mem.Offset); + if (!CE) + return false; + // The offset must be a multiple of 4 in the range 0-1020. + int64_t Value = CE->getValue(); + return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020); + } void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. @@ -244,26 +258,18 @@ Inst.addOperand(MCOperand::CreateReg(getReg())); } + void addRegListOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + std::pair RegList = getRegList(); + Inst.addOperand(MCOperand::CreateReg(RegList.first)); + Inst.addOperand(MCOperand::CreateImm(RegList.second)); + } + void addImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); } - bool isMemMode5() const { - if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted || - Mem.Writeback || Mem.Negative) - return false; - // If there is an offset expression, make sure it's valid. - if (!Mem.Offset) - return true; - const MCConstantExpr *CE = dyn_cast(Mem.Offset); - if (!CE) - return false; - // The offset must be a multiple of 4 in the range 0-1020. - int64_t Value = CE->getValue(); - return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020); - } - void addMemMode5Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && isMemMode5() && "Invalid number of operands!"); From isanbard at gmail.com Mon Nov 8 17:50:20 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 08 Nov 2010 23:50:20 -0000 Subject: [llvm-commits] [llvm] r118457 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20101108235020.B5DB62A6C12C@llvm.org> Author: void Date: Mon Nov 8 17:50:20 2010 New Revision: 118457 URL: http://llvm.org/viewvc/llvm-project?rev=118457&view=rev Log: reglist has two operands. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118457&r1=118456&r2=118457&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 8 17:50:20 2010 @@ -278,6 +278,7 @@ // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand { + int NumOperands = 2; string EncoderMethod = "getRegisterListOpValue"; let PrintMethod = "printRegisterList"; } From isanbard at gmail.com Mon Nov 8 17:51:21 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 08 Nov 2010 23:51:21 -0000 Subject: [llvm-commits] [llvm] r118458 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101108235121.0CD602A6C12C@llvm.org> Author: void Date: Mon Nov 8 17:51:20 2010 New Revision: 118458 URL: http://llvm.org/viewvc/llvm-project?rev=118458&view=rev Log: Get the register and count from the register list operands. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118458&r1=118457&r2=118458&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 8 17:51:20 2010 @@ -378,14 +378,11 @@ unsigned ARMMCCodeEmitter:: getRegisterListOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { - // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each - // register in the list, set the corresponding bit. - unsigned Binary = 0; - for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) { - unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg()); - Binary |= 1 << regno; - } + SmallVectorImpl &) const { + // {12-8} = Rd + // {7-0} = count + unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8; + Binary |= MI.getOperand(Op + 1).getImm() & 0xFF; return Binary; } From resistor at mac.com Mon Nov 8 18:27:03 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 09 Nov 2010 00:27:03 -0000 Subject: [llvm-commits] [llvm] r118461 - /llvm/trunk/lib/VMCore/Attributes.cpp Message-ID: <20101109002703.D3B3A2A6C12C@llvm.org> Author: resistor Date: Mon Nov 8 18:27:03 2010 New Revision: 118461 URL: http://llvm.org/viewvc/llvm-project?rev=118461&view=rev Log: Fix PR8441, a race condition in the static attributes list. While the reference counting was itself threadsafe, the implicit removal of each object from the global list was not. Make this operation atomic. Modified: llvm/trunk/lib/VMCore/Attributes.cpp Modified: llvm/trunk/lib/VMCore/Attributes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=118461&r1=118460&r2=118461&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Attributes.cpp (original) +++ llvm/trunk/lib/VMCore/Attributes.cpp Mon Nov 8 18:27:03 2010 @@ -106,7 +106,10 @@ // AttributeListImpl Definition //===----------------------------------------------------------------------===// + namespace llvm { +static ManagedStatic > ALMutex; + class AttributeListImpl : public FoldingSetNode { sys::cas_flag RefCount; @@ -122,10 +125,15 @@ RefCount = 0; } - void AddRef() { sys::AtomicIncrement(&RefCount); } + void AddRef() { + sys::SmartScopedLock Lock(*ALMutex); + ++RefCount; + } void DropRef() { - sys::cas_flag old = sys::AtomicDecrement(&RefCount); - if (old == 0) delete this; + sys::SmartScopedLock Lock(*ALMutex); + sys::cas_flag old = RefCount++; + if (old == 0) + delete this; } void Profile(FoldingSetNodeID &ID) const { @@ -139,11 +147,10 @@ }; } -static ManagedStatic > ALMutex; static ManagedStatic > AttributesLists; AttributeListImpl::~AttributeListImpl() { - sys::SmartScopedLock Lock(*ALMutex); + // NOTE: Lock must be acquired by caller. AttributesLists->RemoveNode(this); } From isanbard at gmail.com Mon Nov 8 18:30:18 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 09 Nov 2010 00:30:18 -0000 Subject: [llvm-commits] [llvm] r118462 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101109003018.B341D2A6C12C@llvm.org> Author: void Date: Mon Nov 8 18:30:18 2010 New Revision: 118462 URL: http://llvm.org/viewvc/llvm-project?rev=118462&view=rev Log: Revert r118457 and r118458. These won't hold for GPRs. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118462&r1=118461&r2=118462&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 8 18:30:18 2010 @@ -278,7 +278,6 @@ // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand { - int NumOperands = 2; string EncoderMethod = "getRegisterListOpValue"; let PrintMethod = "printRegisterList"; } Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118462&r1=118461&r2=118462&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 8 18:30:18 2010 @@ -378,11 +378,14 @@ unsigned ARMMCCodeEmitter:: getRegisterListOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &) const { - // {12-8} = Rd - // {7-0} = count - unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8; - Binary |= MI.getOperand(Op + 1).getImm() & 0xFF; + SmallVectorImpl &Fixups) const { + // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each + // register in the list, set the corresponding bit. + unsigned Binary = 0; + for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) { + unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg()); + Binary |= 1 << regno; + } return Binary; } From resistor at mac.com Mon Nov 8 18:36:06 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 09 Nov 2010 00:36:06 -0000 Subject: [llvm-commits] [llvm] r118463 - /llvm/trunk/lib/System/DynamicLibrary.cpp Message-ID: <20101109003606.EB0F42A6C12C@llvm.org> Author: resistor Date: Mon Nov 8 18:36:06 2010 New Revision: 118463 URL: http://llvm.org/viewvc/llvm-project?rev=118463&view=rev Log: Fix PR8441, a thread unsafe static variable in our dynamic library loading facilities. Modified: llvm/trunk/lib/System/DynamicLibrary.cpp Modified: llvm/trunk/lib/System/DynamicLibrary.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/DynamicLibrary.cpp?rev=118463&r1=118462&r2=118463&view=diff ============================================================================== --- llvm/trunk/lib/System/DynamicLibrary.cpp (original) +++ llvm/trunk/lib/System/DynamicLibrary.cpp Mon Nov 8 18:36:06 2010 @@ -15,6 +15,7 @@ //===----------------------------------------------------------------------===// #include "llvm/System/DynamicLibrary.h" +#include "llvm/System/Mutex.h" #include "llvm/Config/config.h" #include #include @@ -60,6 +61,7 @@ //=== independent code. //===----------------------------------------------------------------------===// +static SmartMutex HandlesMutex; static std::vector *OpenedHandles = 0; @@ -76,6 +78,7 @@ if (Filename == NULL) H = RTLD_DEFAULT; #endif + SmartScopedLock Lock(HandlesMutex); if (OpenedHandles == 0) OpenedHandles = new std::vector(); OpenedHandles->push_back(H); @@ -110,6 +113,7 @@ #if HAVE_DLFCN_H // Now search the libraries. + SmartScopedLock Lock(HandlesMutex); if (OpenedHandles) { for (std::vector::iterator I = OpenedHandles->begin(), E = OpenedHandles->end(); I != E; ++I) { From gohman at apple.com Mon Nov 8 19:13:31 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 01:13:31 -0000 Subject: [llvm-commits] [llvm] r118464 - /llvm/trunk/tools/bugpoint/ToolRunner.cpp Message-ID: <20101109011331.A24202A6C12C@llvm.org> Author: djg Date: Mon Nov 8 19:13:31 2010 New Revision: 118464 URL: http://llvm.org/viewvc/llvm-project?rev=118464&view=rev Log: Fix some places where error messages were being swallowed. Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=118464&r1=118463&r2=118464&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Mon Nov 8 19:13:31 2010 @@ -59,7 +59,8 @@ const sys::Path &StdOutFile, const sys::Path &StdErrFile, unsigned NumSeconds = 0, - unsigned MemoryLimit = 0) { + unsigned MemoryLimit = 0, + std::string *ErrMsg = 0) { const sys::Path* redirects[3]; redirects[0] = &StdInFile; redirects[1] = &StdOutFile; @@ -76,7 +77,7 @@ return sys::Program::ExecuteAndWait(ProgramPath, Args, 0, redirects, - NumSeconds, MemoryLimit); + NumSeconds, MemoryLimit, ErrMsg); } /// RunProgramRemotelyWithTimeout - This function runs the given program @@ -230,7 +231,7 @@ ); return RunProgramWithTimeout(sys::Path(LLIPath), &LLIArgs[0], sys::Path(InputFile), sys::Path(OutputFile), sys::Path(OutputFile), - Timeout, MemoryLimit); + Timeout, MemoryLimit, Error); } // LLI create method - Try to find the LLI executable @@ -301,7 +302,7 @@ return RunProgramWithTimeout( sys::Path(ExecutionCommand), &ProgramArgs[0], sys::Path(InputFile), sys::Path(OutputFile), - sys::Path(OutputFile), Timeout, MemoryLimit); + sys::Path(OutputFile), Timeout, MemoryLimit, Error); } // Custom execution environment create method, takes the execution command @@ -518,7 +519,7 @@ DEBUG(errs() << "\nSending output to " << OutputFile << "\n"); return RunProgramWithTimeout(sys::Path(LLIPath), &JITArgs[0], sys::Path(InputFile), sys::Path(OutputFile), sys::Path(OutputFile), - Timeout, MemoryLimit); + Timeout, MemoryLimit, Error); } /// createJIT - Try to find the LLI executable @@ -772,7 +773,7 @@ DEBUG(errs() << ""); return RunProgramWithTimeout(OutputBinary, &ProgramArgs[0], sys::Path(InputFile), sys::Path(OutputFile), sys::Path(OutputFile), - Timeout, MemoryLimit); + Timeout, MemoryLimit, Error); } else { outs() << ""; outs().flush(); return RunProgramRemotelyWithTimeout(sys::Path(RemoteClientPath), From dalej at apple.com Mon Nov 8 19:15:07 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 09 Nov 2010 01:15:07 -0000 Subject: [llvm-commits] [llvm] r118465 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/complex-asm.ll Message-ID: <20101109011507.AB08E2A6C12C@llvm.org> Author: johannes Date: Mon Nov 8 19:15:07 2010 New Revision: 118465 URL: http://llvm.org/viewvc/llvm-project?rev=118465&view=rev Log: Fix an inline asm pasto from 117667; was preventing {i64, i64} from matching i128. Added: llvm/trunk/test/CodeGen/X86/complex-asm.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=118465&r1=118464&r2=118465&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Nov 8 19:15:07 2010 @@ -2738,7 +2738,8 @@ case 32: case 64: case 128: - OpTy = IntegerType::get(OpTy->getContext(), BitSize); + OpInfo.ConstraintVT = + EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); break; } } else if (dyn_cast(OpTy)) { Added: llvm/trunk/test/CodeGen/X86/complex-asm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/complex-asm.ll?rev=118465&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/complex-asm.ll (added) +++ llvm/trunk/test/CodeGen/X86/complex-asm.ll Mon Nov 8 19:15:07 2010 @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin +; This formerly crashed. + +%0 = type { i64, i64 } + +define %0 @f() nounwind ssp { +entry: + %v = alloca %0, align 8 + call void asm sideeffect "", "=*r,r,r,0,~{dirflag},~{fpsr},~{flags}"(%0* %v, i32 0, i32 1, i128 undef) nounwind + %0 = getelementptr inbounds %0* %v, i64 0, i32 0 + %1 = load i64* %0, align 8 + %2 = getelementptr inbounds %0* %v, i64 0, i32 1 + %3 = load i64* %2, align 8 + %mrv4 = insertvalue %0 undef, i64 %1, 0 + %mrv5 = insertvalue %0 %mrv4, i64 %3, 1 + ret %0 %mrv5 +} From gohman at apple.com Mon Nov 8 19:37:26 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 8 Nov 2010 17:37:26 -0800 Subject: [llvm-commits] [llvm] r118367 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Unix/Path.inc lib/System/Win32/Path.inc In-Reply-To: <20101107043650.C10C82A6C136@llvm.org> References: <20101107043650.C10C82A6C136@llvm.org> Message-ID: <65559D06-9349-4839-9CD7-CE3E5EBFDDF1@apple.com> On Nov 6, 2010, at 9:36 PM, Rafael Espindola wrote: > Author: rafael > Date: Sat Nov 6 23:36:50 2010 > New Revision: 118367 > > URL: http://llvm.org/viewvc/llvm-project?rev=118367&view=rev > Log: > Add method for checking if a path is a symbolic link. Hi Rafael, What will this be used for? Dan From grosbach at apple.com Mon Nov 8 19:37:16 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 01:37:16 -0000 Subject: [llvm-commits] [llvm] r118469 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMMCCodeEmitter.cpp Message-ID: <20101109013716.112CA2A6C12C@llvm.org> Author: grosbach Date: Mon Nov 8 19:37:15 2010 New Revision: 118469 URL: http://llvm.org/viewvc/llvm-project?rev=118469&view=rev Log: Add support for a few simple fixups to the ARM Darwin asm backend. This allows constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118469&r1=118468&r2=118469&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Nov 8 19:37:15 2010 @@ -9,7 +9,7 @@ #include "llvm/Target/TargetAsmBackend.h" #include "ARM.h" -//FIXME: add #include "ARMFixupKinds.h" +#include "ARMFixupKinds.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/ELFObjectWriter.h" #include "llvm/MC/MCAssembler.h" @@ -138,9 +138,41 @@ } }; +static unsigned getFixupKindLog2Size(unsigned Kind) { + switch (Kind) { + default: llvm_unreachable("Unknown fixup kind!"); + case FK_Data_4: return 2; + case ARM::fixup_arm_pcrel_12: return 2; + case ARM::fixup_arm_vfp_pcrel_12: return 1; + } +} + +static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { + switch (Kind) { + default: + llvm_unreachable("Unknown fixup kind!"); + case FK_Data_4: + case ARM::fixup_arm_pcrel_12: + // ARM PC-relative values are offset by 8. + return Value - 8; + case ARM::fixup_arm_vfp_pcrel_12: + // The VFP ld/st immediate value doesn't encode the low two bits since + // they're always zero. Offset by 8 just as above. + return (Value - 8) >> 2; + } +} + void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF, uint64_t Value) const { - assert(0 && "DarwinARMAsmBackend::ApplyFixup() unimplemented"); + unsigned NumBytes = getFixupKindLog2Size(Fixup.getKind()); + Value = adjustFixupValue(Fixup.getKind(), Value); + + assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() && + "Invalid fixup offset!"); + // For each byte of the fragment that the fixup touches, mask in the + // bits from the fixup value. + for (unsigned i = 0; i != NumBytes; ++i) + DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8)); } } // end anonymous namespace Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118469&r1=118468&r2=118469&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 8 19:37:15 2010 @@ -234,7 +234,7 @@ // If The first operand isn't a register, we have a label reference. const MCOperand &MO = MI.getOperand(OpIdx); if (!MO.isReg()) { - Reg = ARM::PC; // Rn is PC. + Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. Imm12 = 0; assert(MO.isExpr() && "Unexpected machine operand type!"); @@ -246,9 +246,6 @@ } else isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); - if (Reg == ARM::PC) - return ARM::PC << 13; // Rn is PC; - uint32_t Binary = Imm12 & 0xfff; // Immediate is always encoded as positive. The 'U' bit controls add vs sub. if (isAdd) @@ -268,7 +265,7 @@ // If The first operand isn't a register, we have a label reference. const MCOperand &MO = MI.getOperand(OpIdx); if (!MO.isReg()) { - Reg = ARM::PC; // Rn is PC. + Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. Imm8 = 0; assert(MO.isExpr() && "Unexpected machine operand type!"); @@ -280,9 +277,6 @@ } else EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); - if (Reg == ARM::PC) - return ARM::PC << 9; // Rn is PC; - uint32_t Binary = ARM_AM::getAM5Offset(Imm8); // Immediate is always encoded as positive. The 'U' bit controls add vs sub. if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add) From bigcheesegs at gmail.com Mon Nov 8 19:49:15 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Mon, 8 Nov 2010 20:49:15 -0500 Subject: [llvm-commits] [PATCH][System/Path] Update comments to match code. Message-ID: Neither the Unix or Windows implementation include LLVM_LIB_SEARCH_PATH. I'm assuming the comments are wrong. Just making sure it's not the code that is wrong. Also, the Windows implementation is completely wrong on a multitude of levels. It should be using SHGetFolderPath instead of hard coding C:\Windows, and none of those directories contain any libraries that are actually used on modern Windows. What is the actual purpose of this function? To get libraries for link time or runtime? If it's for link time then what we really want is the platform sdk and MSVC directories, or something else on MinGW. If it's for runtime then... well... take your pick. There are quite a few directories depending on the OS version, Architecture, etc... And then there's MinGW. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: update-comments-to-match-code.patch Type: application/octet-stream Size: 977 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101108/1aef8f23/attachment.obj From gohman at apple.com Mon Nov 8 19:51:06 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 01:51:06 -0000 Subject: [llvm-commits] [llvm] r118470 - /llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll Message-ID: <20101109015106.E69782A6C12C@llvm.org> Author: djg Date: Mon Nov 8 19:51:06 2010 New Revision: 118470 URL: http://llvm.org/viewvc/llvm-project?rev=118470&view=rev Log: Delete an extraneous svn:executable property. Modified: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll (props changed) Propchange: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll ------------------------------------------------------------------------------ --- svn:executable (original) +++ svn:executable (removed) @@ -1 +0,0 @@ -* From gohman at apple.com Mon Nov 8 19:54:35 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 01:54:35 -0000 Subject: [llvm-commits] [llvm] r118471 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/narrow-shl-load.ll Message-ID: <20101109015435.9120E2A6C12C@llvm.org> Author: djg Date: Mon Nov 8 19:54:35 2010 New Revision: 118471 URL: http://llvm.org/viewvc/llvm-project?rev=118471&view=rev Log: Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl in order to fold it into a load. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=118471&r1=118470&r2=118471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Nov 8 19:54:35 2010 @@ -4120,6 +4120,7 @@ // we can fold the truncate through the shift. unsigned ShLeftAmt = 0; if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && + ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) { ShLeftAmt = N01->getZExtValue(); Modified: llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll?rev=118471&r1=118470&r2=118471&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll (original) +++ llvm/trunk/test/CodeGen/X86/narrow-shl-load.ll Mon Nov 8 19:54:35 2010 @@ -1,12 +1,11 @@ -; RUN: llc -march=x86-64 < %s - -; DAGCombiner should fold this code in finite time. - -; rdar://8606584 +; RUN: llc -march=x86-64 < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-linux-gnu" +; DAGCombiner should fold this code in finite time. +; rdar://8606584 + define void @D() nounwind readnone { bb.nph: br label %while.cond @@ -30,3 +29,37 @@ while.end: ; preds = %while.cond ret void } + + +; DAGCombiner shouldn't fold the sdiv (ashr) away. +; rdar://8636812 +; CHECK: main: +; CHECK: sarl + +define i32 @main() nounwind { +entry: + %i = alloca i32, align 4 + %j = alloca i8, align 1 + store i32 127, i32* %i, align 4 + store i8 0, i8* %j, align 1 + %tmp3 = load i32* %i, align 4 + %mul = mul nsw i32 %tmp3, 2 + %conv4 = trunc i32 %mul to i8 + %conv5 = sext i8 %conv4 to i32 + %div6 = sdiv i32 %conv5, 2 + %conv7 = trunc i32 %div6 to i8 + %conv9 = sext i8 %conv7 to i32 + %cmp = icmp eq i32 %conv9, -1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + ret i32 0 + +if.end: ; preds = %entry + call void @abort() noreturn + unreachable +} + +declare void @abort() noreturn + +declare void @exit(i32) noreturn From geek4civic at gmail.com Mon Nov 8 20:13:12 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 9 Nov 2010 11:13:12 +0900 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" Message-ID: I propose adding, for CMake, the option "LLVM_LIT_ARGS". By default LLVM_LIT_ARGS is set; MSVC or XCODE: -sv --no-progress-bar others: -sv * 0001-CMake-Add-the-new-option-LLVM_LIT_ARGS.patch for llvm tree. * 0001-test-CMakeLists.txt-Use-LLVM_LIT_ARGS-and-remove-red.patch for clang tree. it depends on the former patch. I wonder whether the name "LLVM_LIT_ARGS" would be suitable or not :) (would be better to split to new namespace LIT_**** ?) Please gimme any advices. Thank you, ...Takumi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-CMake-Add-the-new-option-LLVM_LIT_ARGS.patch Type: application/octet-stream Size: 1465 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101109/aecfd9e2/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-test-CMakeLists.txt-Use-LLVM_LIT_ARGS-and-remove-red.patch Type: application/octet-stream Size: 2634 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101109/aecfd9e2/attachment-0001.obj From dgregor at apple.com Mon Nov 8 20:41:30 2010 From: dgregor at apple.com (Douglas Gregor) Date: Mon, 8 Nov 2010 20:41:30 -0600 Subject: [llvm-commits] [cfe-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: References: Message-ID: <458C0E3F-882D-4C65-9FA1-3DDAE1AE32EC@apple.com> Looks good to me, unless ?scar objects. - Doug On Nov 8, 2010, at 8:13 PM, NAKAMURA Takumi wrote: > I propose adding, for CMake, the option "LLVM_LIT_ARGS". > > By default LLVM_LIT_ARGS is set; > > MSVC or XCODE: -sv --no-progress-bar > others: -sv > > * 0001-CMake-Add-the-new-option-LLVM_LIT_ARGS.patch > > for llvm tree. > > * 0001-test-CMakeLists.txt-Use-LLVM_LIT_ARGS-and-remove-red.patch > > for clang tree. it depends on the former patch. > > I wonder whether the name "LLVM_LIT_ARGS" would be suitable or not :) > (would be better to split to new namespace LIT_**** ?) > Please gimme any advices. > > > Thank you, ...Takumi > <0001-CMake-Add-the-new-option-LLVM_LIT_ARGS.patch><0001-test-CMakeLists.txt-Use-LLVM_LIT_ARGS-and-remove-red.patch>_______________________________________________ > cfe-commits mailing list > cfe-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits From geek4civic at gmail.com Mon Nov 8 22:35:29 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 9 Nov 2010 13:35:29 +0900 Subject: [llvm-commits] [PATCH] FileCheck.cpp: made match regex '$' for DOSish \r\n In-Reply-To: References: Message-ID: Ping. It can pass two tests below on win32. - Clang :: CodeGenCXX/dyncast.cpp - LLVM :: CodeGen/ARM/globals.ll ...Takumi 2010/10/4 NAKAMURA Takumi : > Some tests have CHECK: {{foobar$}} to cause mismatch failure on mingw. > > I took the way to eliminate \r on MemoryBuffer. > Is there any better way? > > ...Takumi > From resistor at mac.com Mon Nov 8 23:17:47 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 09 Nov 2010 05:17:47 -0000 Subject: [llvm-commits] [llvm] r118490 - /llvm/trunk/lib/VMCore/Attributes.cpp Message-ID: <20101109051747.BCA362A6C12C@llvm.org> Author: resistor Date: Mon Nov 8 23:17:47 2010 New Revision: 118490 URL: http://llvm.org/viewvc/llvm-project?rev=118490&view=rev Log: Fix leak in my recent fix for PR8442. Modified: llvm/trunk/lib/VMCore/Attributes.cpp Modified: llvm/trunk/lib/VMCore/Attributes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=118490&r1=118489&r2=118490&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Attributes.cpp (original) +++ llvm/trunk/lib/VMCore/Attributes.cpp Mon Nov 8 23:17:47 2010 @@ -132,7 +132,7 @@ void DropRef() { sys::SmartScopedLock Lock(*ALMutex); sys::cas_flag old = RefCount++; - if (old == 0) + if (old == 1) delete this; } From jasonwkim at google.com Mon Nov 8 23:24:31 2010 From: jasonwkim at google.com (Jason Kim) Date: Mon, 8 Nov 2010 21:24:31 -0800 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: <15B2412D-4A1A-4831-817E-53C4B598420A@apple.com> References: <20101108175807.8543A2A6C12C@llvm.org> <15B2412D-4A1A-4831-817E-53C4B598420A@apple.com> Message-ID: On Mon, Nov 8, 2010 at 3:41 PM, Evan Cheng wrote: > > On Nov 8, 2010, at 10:41 AM, Jason Kim wrote: > >> On Mon, Nov 8, 2010 at 10:37 AM, Anton Korobeynikov >> wrote: >>> Hi Jason, >>> >>>> + ? ?if (CPUString != "generic") { >>>> + ? ? ?if (CPUString == "cortex-a8") { >>> This looks pretty gross. Is it possible to generalize stuff somehow? >>> E.g. via the mapping of CPU names => supported attributes. >> >> I agree its very gross. I am going to be iterating over this repeatedly. >> I don't yet have a clear understanding of the space of cpu/attributes yet. >> As I get more familiarized with how GNU/as does things, I will be >> refactoring these. >> > it's also wrong. What about other cpu's which are cortex-a8 variants and later? Do we have to get this patch in now? Can you table it until you have figured out how to match these to subtarget attributes? Hi Evan, and Anton Thanks for review. This was meant as an incremental patch to get a corner subcase working. The attributes that it emitted was "correct" at least according to GNU/as for the specific subcase. I suspect that the a substantially complete table that encodes the various switches and their correspondence to .ARM.attributes might be somewhat nontrivial - as the "correctness criteria" is largely dependent upon the quirks of GNU/as (Documentation from ARM does not help much here )-: Not to mention, this is for ELF only - Does MachO care for these at all? In such cases, what ever I commit in an incremental manner will either be substantially incomplete (i.e. looks like dead code), or substantially messy looking, or both. As it turns out, there was a (trivial) bug in the test I committed, (but it was enough to cause build break on darwin) so it was rolled back :-( so its a moot point. I'll refactor and email updated patch to commits for review. Thanks again -jason > > Evan > >> >>> >>> -- >>> With best regards, Anton Korobeynikov >>> Faculty of Mathematics and Mechanics, Saint Petersburg State University >>> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From clattner at apple.com Tue Nov 9 00:07:28 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 8 Nov 2010 22:07:28 -0800 Subject: [llvm-commits] [llvm] r118463 - /llvm/trunk/lib/System/DynamicLibrary.cpp In-Reply-To: <20101109003606.EB0F42A6C12C@llvm.org> References: <20101109003606.EB0F42A6C12C@llvm.org> Message-ID: On Nov 8, 2010, at 4:36 PM, Owen Anderson wrote: > Author: resistor > Date: Mon Nov 8 18:36:06 2010 > New Revision: 118463 > > URL: http://llvm.org/viewvc/llvm-project?rev=118463&view=rev > Log: > Fix PR8441, a thread unsafe static variable in our dynamic library loading facilities. Hi Owen, Does SmartMutex cause a static constructor? -Chris > > Modified: > llvm/trunk/lib/System/DynamicLibrary.cpp > > Modified: llvm/trunk/lib/System/DynamicLibrary.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/DynamicLibrary.cpp?rev=118463&r1=118462&r2=118463&view=diff > ============================================================================== > --- llvm/trunk/lib/System/DynamicLibrary.cpp (original) > +++ llvm/trunk/lib/System/DynamicLibrary.cpp Mon Nov 8 18:36:06 2010 > @@ -15,6 +15,7 @@ > //===----------------------------------------------------------------------===// > > #include "llvm/System/DynamicLibrary.h" > +#include "llvm/System/Mutex.h" > #include "llvm/Config/config.h" > #include > #include > @@ -60,6 +61,7 @@ > //=== independent code. > //===----------------------------------------------------------------------===// > > +static SmartMutex HandlesMutex; > static std::vector *OpenedHandles = 0; > > > @@ -76,6 +78,7 @@ > if (Filename == NULL) > H = RTLD_DEFAULT; > #endif > + SmartScopedLock Lock(HandlesMutex); > if (OpenedHandles == 0) > OpenedHandles = new std::vector(); > OpenedHandles->push_back(H); > @@ -110,6 +113,7 @@ > > #if HAVE_DLFCN_H > // Now search the libraries. > + SmartScopedLock Lock(HandlesMutex); > if (OpenedHandles) { > for (std::vector::iterator I = OpenedHandles->begin(), > E = OpenedHandles->end(); I != E; ++I) { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ofv at wanadoo.es Tue Nov 9 02:05:30 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Tue, 09 Nov 2010 09:05:30 +0100 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: (NAKAMURA Takumi's message of "Tue, 9 Nov 2010 11:13:12 +0900") References: Message-ID: <87d3qezzud.fsf@telefonica.net> Hello Takumi. NAKAMURA Takumi writes: > I propose adding, for CMake, the option "LLVM_LIT_ARGS". > > By default LLVM_LIT_ARGS is set; > > MSVC or XCODE: -sv --no-progress-bar > others: -sv > > * 0001-CMake-Add-the-new-option-LLVM_LIT_ARGS.patch > > for llvm tree. > > * 0001-test-CMakeLists.txt-Use-LLVM_LIT_ARGS-and-remove-red.patch > > for clang tree. it depends on the former patch. Unless I'm missing something on how cmake processes options, there is an use-before-first-assignment problem here. LLVM_LIT_ARGS is defined in test/CMakeLists.txt, but it is used in tools/clang/test/CMakeLists.txt, which is processed before test/CMakeLists.txt. If the user sets LLVM_LIT_ARGS from the cmake command line there is no problem, but if he doesn't, the default value you set in test/CMakeLists.txt is not used for clang. You can test this by starting from a new build directory without using LLVM_LIT_ARGS on the command line, and checkig if the -sv argument is passed to lit on the clang tests. > I wonder whether the name "LLVM_LIT_ARGS" would be suitable or not :) > (would be better to split to new namespace LIT_**** ?) > Please gimme any advices. The variable is defined on a LLVM/Clang CMakeLists.txt file, so it belongs to the LLVM namespace. The LIT namespace would make sense iif LIT had its own CMakeLists.txt files. IMO. I'm wary by the use of separate_arguments. Why do you need it and why UNIX_COMMAND was chosen? On the clang part, the variable CLANG_TEST_EXTRA_ARGS is referenced by set(CLANG_TEST_EXTRA_ARGS) (which is equivalent to unsetting it) and then you + list(APPEND CLANG_TEST_EXTRA_ARGS ${LIT_ARGS}) It would be clearer if the set(CLANG_TEST_EXTRA_ARGS) were replaced by + set(CLANG_TEST_EXTRA_ARGS ${LIT_ARGS}) or replacing the occurrences of CLANG_TEST_EXTRA_ARGS by LIT_ARGS altogether, as it no longer holds the "extra args" but all the configurable lit args for clang. Also, it would be a good thing to add documentation for the LLVM_LIT_ARGS variable in docs/CMake.html. From baldrick at free.fr Tue Nov 9 07:30:26 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 09 Nov 2010 13:30:26 -0000 Subject: [llvm-commits] [dragonegg] r118499 - in /dragonegg/trunk: llvm-convert.cpp llvm-internal.h Message-ID: <20101109133026.B63D52A6C12C@llvm.org> Author: baldrick Date: Tue Nov 9 07:30:26 2010 New Revision: 118499 URL: http://llvm.org/viewvc/llvm-project?rev=118499&view=rev Log: Add support for the LFLOOR and LCEIL builtins, which represent a call to floor (resp. ceil) with the result cast to an integer type. Before, programs that performed such a cast would fail to link due to an undefined reference to __builtin_lfloor or __builtin_lceil, or a variant of these. Use some of the added infrastructure to simplify the handling of ABS_EXPR (in the floating point case) while there. Modified: dragonegg/trunk/llvm-convert.cpp dragonegg/trunk/llvm-internal.h Modified: dragonegg/trunk/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=118499&r1=118498&r2=118499&view=diff ============================================================================== --- dragonegg/trunk/llvm-convert.cpp (original) +++ dragonegg/trunk/llvm-convert.cpp Tue Nov 9 07:30:26 2010 @@ -210,6 +210,21 @@ } } +/// SelectFPName - Helper for choosing a name depending on whether a floating +/// point type is float, double or long double. +static StringRef SelectFPName(tree type, StringRef FloatName, + StringRef DoubleName, StringRef LongDoubleName) { + assert(SCALAR_FLOAT_TYPE_P(type) && "Expected a floating point type!"); + if (TYPE_MODE(type) == TYPE_MODE(float_type_node)) + return FloatName; + if (TYPE_MODE(type) == TYPE_MODE(double_type_node)) + return DoubleName; + assert(TYPE_MODE(type) == TYPE_MODE(long_double_type_node) && + "Unknown floating point type!"); + return LongDoubleName; +} + + //===----------------------------------------------------------------------===// // ... High-Level Methods ... //===----------------------------------------------------------------------===// @@ -2983,6 +2998,67 @@ return 0; } +/// EmitSimpleCall - Emit a call to the function with the given name and return +/// type, passing the provided arguments (which should all be gimple registers +/// or local constants of register type). No marshalling is done: the arguments +/// are directly passed through. +CallInst *TreeToLLVM::EmitSimpleCall(StringRef CalleeName, tree_node *ret_type, + /* arguments */ ...) { + va_list ops; + va_start(ops, ret_type); + + // Build the list of arguments. + std::vector Args; +#ifdef TARGET_ADJUST_LLVM_CC + // Build the list of GCC argument types. + tree arg_types; + tree *chainp = &arg_types; +#endif + while (tree arg = va_arg(ops, tree)) { + Args.push_back(EmitRegister(arg)); +#ifdef TARGET_ADJUST_LLVM_CC + *chainp = build_tree_list(NULL, TREE_TYPE(arg)); + chainp = &TREE_CHAIN(*chainp); +#endif + } +#ifdef TARGET_ADJUST_LLVM_CC + // Indicate that this function is not varargs. + *chainp = void_list_node; +#endif + va_end(ops); + + const Type *RetTy = TREE_CODE(ret_type) == VOID_TYPE ? + Type::getVoidTy(Context) : GetRegType(ret_type); + + // The LLVM argument types. + std::vector ArgTys; + ArgTys.reserve(Args.size()); + for (unsigned i = 0, e = Args.size(); i != e; ++i) + ArgTys.push_back(Args[i]->getType()); + + // Determine the calling convention. + CallingConv::ID CC = CallingConv::C; +#ifdef TARGET_ADJUST_LLVM_CC + // Query the target for the calling convention to use. + tree fntype = build_function_type(ret_type, arg_types); + TARGET_ADJUST_LLVM_CC(CC, fntype); +#endif + + // Get the function declaration for the callee. + const FunctionType *FTy = FunctionType::get(RetTy, ArgTys, /*isVarArg*/false); + Constant *Func = TheModule->getOrInsertFunction(CalleeName, FTy); + + // If the function already existed with the wrong prototype then don't try to + // muck with its calling convention. Otherwise, set the calling convention. + if (Function *F = dyn_cast(Func)) + F->setCallingConv(CC); + + // Finally, call the function. + CallInst *CI = Builder.CreateCall(Func, Args.begin(), Args.end()); + CI->setCallingConv(CC); + return CI; +} + //===----------------------------------------------------------------------===// // ... Inline Assembly and Register Variables ... @@ -3950,6 +4026,22 @@ Result); return true; } + case BUILT_IN_LCEIL: + case BUILT_IN_LCEILF: + case BUILT_IN_LCEILL: + case BUILT_IN_LLCEIL: + case BUILT_IN_LLCEILF: + case BUILT_IN_LLCEILL: + Result = EmitBuiltinLCEIL(stmt); + return true; + case BUILT_IN_LFLOOR: + case BUILT_IN_LFLOORF: + case BUILT_IN_LFLOORL: + case BUILT_IN_LLFLOOR: + case BUILT_IN_LLFLOORF: + case BUILT_IN_LLFLOORL: + Result = EmitBuiltinLFLOOR(stmt); + return true; //TODO case BUILT_IN_FLT_ROUNDS: { //TODO Result = //TODO Builder.CreateCall(Intrinsic::getDeclaration(TheModule, @@ -4552,6 +4644,44 @@ Args.begin(), Args.end()); } +Value *TreeToLLVM::EmitBuiltinLCEIL(gimple stmt) { + if (!validate_gimple_arglist(stmt, REAL_TYPE, VOID_TYPE)) + return 0; + + // Cast the result of "ceil" to the appropriate integer type. + // First call the appropriate version of "ceil". + tree op = gimple_call_arg(stmt, 0); + StringRef Name = SelectFPName(TREE_TYPE(op), "ceilf", "ceil", "ceill"); + CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); + Call->setDoesNotThrow(); + Call->setDoesNotAccessMemory(); + + // Then type cast the result of the "ceil" call. + tree type = gimple_call_return_type(stmt); + const Type *RetTy = GetRegType(type); + return TYPE_UNSIGNED(type) ? Builder.CreateFPToUI(Call, RetTy) : + Builder.CreateFPToSI(Call, RetTy); +} + +Value *TreeToLLVM::EmitBuiltinLFLOOR(gimple stmt) { + if (!validate_gimple_arglist(stmt, REAL_TYPE, VOID_TYPE)) + return 0; + + // Cast the result of "floor" to the appropriate integer type. + // First call the appropriate version of "floor". + tree op = gimple_call_arg(stmt, 0); + StringRef Name = SelectFPName(TREE_TYPE(op), "floorf", "floor", "floorl"); + CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); + Call->setDoesNotThrow(); + Call->setDoesNotAccessMemory(); + + // Then type cast the result of the "floor" call. + tree type = gimple_call_return_type(stmt); + const Type *RetTy = GetRegType(type); + return TYPE_UNSIGNED(type) ? Builder.CreateFPToUI(Call, RetTy) : + Builder.CreateFPToSI(Call, RetTy); +} + bool TreeToLLVM::EmitBuiltinConstantP(gimple stmt, Value *&Result) { Result = Constant::getNullValue(ConvertType(gimple_call_return_type(stmt))); return true; @@ -5926,8 +6056,8 @@ // Unary expressions. Value *TreeToLLVM::EmitReg_ABS_EXPR(tree op) { - Value *Op = EmitRegister(op); - if (!Op->getType()->isFloatingPointTy()) { + if (!FLOAT_TYPE_P(TREE_TYPE(op))) { + Value *Op = EmitRegister(op); Value *OpN = Builder.CreateNeg(Op, Op->getName()+"neg"); ICmpInst::Predicate pred = TYPE_UNSIGNED(TREE_TYPE(op)) ? ICmpInst::ICMP_UGE : ICmpInst::ICMP_SGE; @@ -5937,42 +6067,10 @@ } // Turn FP abs into fabs/fabsf. - const char *Name = 0; - - tree ArgType; - switch (Op->getType()->getTypeID()) { - default: assert(0 && "Unknown FP type!"); - case Type::FloatTyID: - Name = "fabsf"; - ArgType = float_type_node; - break; - case Type::DoubleTyID: - Name = "fabs"; - ArgType = double_type_node; - break; - case Type::X86_FP80TyID: - case Type::PPC_FP128TyID: - case Type::FP128TyID: - Name = "fabsl"; - ArgType = long_double_type_node; - break; - } - - Value *V = TheModule->getOrInsertFunction(Name, Op->getType(), Op->getType(), - NULL); - // Determine the calling convention. - CallingConv::ID CallingConvention = CallingConv::C; -#ifdef TARGET_ADJUST_LLVM_CC - tree FunctionType = build_function_type_list(ArgType, ArgType, NULL); - TARGET_ADJUST_LLVM_CC(CallingConvention, FunctionType); -#endif - - Function *F = cast(V); - F->setCallingConv(CallingConvention); - CallInst *Call = Builder.CreateCall(V, Op); + StringRef Name = SelectFPName(TREE_TYPE(op), "fabsf", "fabs", "fabsl"); + CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); Call->setDoesNotThrow(); Call->setDoesNotAccessMemory(); - Call->setCallingConv(CallingConvention); return Call; } Modified: dragonegg/trunk/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-internal.h?rev=118499&r1=118498&r2=118499&view=diff ============================================================================== --- dragonegg/trunk/llvm-internal.h (original) +++ dragonegg/trunk/llvm-internal.h Tue Nov 9 07:30:26 2010 @@ -693,6 +693,8 @@ Value *EmitADDR_EXPR(tree_node *exp); Value *EmitCallOf(Value *Callee, gimple_statement_d *stmt, const MemRef *DestLoc, const AttrListPtr &PAL); + CallInst *EmitSimpleCall(StringRef CalleeName, tree_node *ret_type, + /* arguments */ ...) END_WITH_NULL; Value *EmitFieldAnnotation(Value *FieldPtr, tree_node *FieldDecl); // Inline Assembly and Register Variables. @@ -718,6 +720,8 @@ Value *EmitBuiltinSQRT(gimple_statement_d *stmt); Value *EmitBuiltinPOWI(gimple_statement_d *stmt); Value *EmitBuiltinPOW(gimple_statement_d *stmt); + Value *EmitBuiltinLCEIL(gimple_statement_d *stmt); + Value *EmitBuiltinLFLOOR(gimple_statement_d *stmt); bool EmitBuiltinConstantP(gimple_statement_d *stmt, Value *&Result); bool EmitBuiltinAlloca(gimple_statement_d *stmt, Value *&Result); From anton at korobeynikov.info Tue Nov 9 08:45:49 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 9 Nov 2010 17:45:49 +0300 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: References: <20101108175807.8543A2A6C12C@llvm.org> <15B2412D-4A1A-4831-817E-53C4B598420A@apple.com> Message-ID: Hi Jason, > I'll refactor and email updated patch to commits for review. Thanks alot! -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From bigcheesegs at gmail.com Tue Nov 9 09:10:29 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:10:29 -0000 Subject: [llvm-commits] [llvm] r118501 - /llvm/trunk/lib/System/Win32/Win32.h Message-ID: <20101109151029.7F5D92A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:10:29 2010 New Revision: 118501 URL: http://llvm.org/viewvc/llvm-project?rev=118501&view=rev Log: Update comment. Modified: llvm/trunk/lib/System/Win32/Win32.h Modified: llvm/trunk/lib/System/Win32/Win32.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Win32.h?rev=118501&r1=118500&r2=118501&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Win32.h (original) +++ llvm/trunk/lib/System/Win32/Win32.h Tue Nov 9 09:10:29 2010 @@ -19,7 +19,7 @@ // Require at least Windows 2000 API. #define _WIN32_WINNT 0x0500 -#include "llvm/Config/config.h" // Get autoconf configuration settings +#include "llvm/Config/config.h" // Get build system configuration settings #include "windows.h" #include #include From bigcheesegs at gmail.com Tue Nov 9 09:10:45 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:10:45 -0000 Subject: [llvm-commits] [llvm] r118502 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Win32/Path.inc Message-ID: <20101109151045.50D452A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:10:45 2010 New Revision: 118502 URL: http://llvm.org/viewvc/llvm-project?rev=118502&view=rev Log: System/Path/Windows: Change GetRootDirectory to return file:/// instead of C:/. Modified: llvm/trunk/include/llvm/System/Path.h llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=118502&r1=118501&r2=118502&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Tue Nov 9 09:10:45 2010 @@ -89,7 +89,7 @@ /// Construct a path to the root directory of the file system. The root /// directory is a top level directory above which there are no more /// directories. For example, on UNIX, the root directory is /. On Windows - /// it is C:\. Other operating systems may have different notions of + /// it is file:///. Other operating systems may have different notions of /// what the root directory is or none at all. In that case, a consistent /// default root directory will be used. static Path GetRootDirectory(); Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118502&r1=118501&r2=118502&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 9 09:10:45 2010 @@ -233,9 +233,9 @@ // FIXME: the following set of functions don't map to Windows very well. Path Path::GetRootDirectory() { - Path result; - result.set("C:/"); - return result; + // This is the only notion that that Windows has of a root directory. Nothing + // is here except for drives. + return Path("file:///"); } void From bigcheesegs at gmail.com Tue Nov 9 09:10:56 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:10:56 -0000 Subject: [llvm-commits] [llvm] r118503 - /llvm/trunk/lib/System/Win32/Win32.h Message-ID: <20101109151056.B8DDF2A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:10:56 2010 New Revision: 118503 URL: http://llvm.org/viewvc/llvm-project?rev=118503&view=rev Log: System/Windows: Use normalized case and include method. Modified: llvm/trunk/lib/System/Win32/Win32.h Modified: llvm/trunk/lib/System/Win32/Win32.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Win32.h?rev=118503&r1=118502&r2=118503&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Win32.h (original) +++ llvm/trunk/lib/System/Win32/Win32.h Tue Nov 9 09:10:56 2010 @@ -20,7 +20,7 @@ #define _WIN32_WINNT 0x0500 #include "llvm/Config/config.h" // Get build system configuration settings -#include "windows.h" +#include #include #include From bigcheesegs at gmail.com Tue Nov 9 09:11:07 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:11:07 -0000 Subject: [llvm-commits] [llvm] r118504 - /llvm/trunk/lib/System/Win32/Win32.h Message-ID: <20101109151107.EFA4B2A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:11:07 2010 New Revision: 118504 URL: http://llvm.org/viewvc/llvm-project?rev=118504&view=rev Log: System/Windows: Reduce dependencies. Modified: llvm/trunk/lib/System/Win32/Win32.h Modified: llvm/trunk/lib/System/Win32/Win32.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Win32.h?rev=118504&r1=118503&r2=118504&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Win32.h (original) +++ llvm/trunk/lib/System/Win32/Win32.h Tue Nov 9 09:11:07 2010 @@ -18,6 +18,7 @@ // Require at least Windows 2000 API. #define _WIN32_WINNT 0x0500 +#define WIN32_LEAN_AND_MEAN #include "llvm/Config/config.h" // Get build system configuration settings #include From bigcheesegs at gmail.com Tue Nov 9 09:11:20 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:11:20 -0000 Subject: [llvm-commits] [llvm] r118505 - in /llvm/trunk/lib/System/Win32: Path.inc Win32.h Message-ID: <20101109151120.1C7DD2A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:11:19 2010 New Revision: 118505 URL: http://llvm.org/viewvc/llvm-project?rev=118505&view=rev Log: System/Path/Windows: Make GetSystemLibraryPaths more generic. Modified: llvm/trunk/lib/System/Win32/Path.inc llvm/trunk/lib/System/Win32/Win32.h Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118505&r1=118504&r2=118505&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 9 09:11:19 2010 @@ -240,8 +240,32 @@ void Path::GetSystemLibraryPaths(std::vector& Paths) { - Paths.push_back(sys::Path("C:/WINDOWS/SYSTEM32")); - Paths.push_back(sys::Path("C:/WINDOWS")); + char buff[MAX_PATH]; + // Generic form of C:\Windows\System32 + HRESULT res = SHGetFolderPathA(NULL, + CSIDL_FLAG_CREATE | CSIDL_SYSTEM, + NULL, + SHGFP_TYPE_CURRENT, + buff); + if (res != S_OK) { + assert(0 && "Failed to get system directory"); + return; + } + Paths.push_back(sys::Path(buff)); + + // Reset buff. + buff[0] = 0; + // Generic form of C:\Windows + res = SHGetFolderPathA(NULL, + CSIDL_FLAG_CREATE | CSIDL_WINDOWS, + NULL, + SHGFP_TYPE_CURRENT, + buff); + if (res != S_OK) { + assert(0 && "Failed to get windows directory"); + return; + } + Paths.push_back(sys::Path(buff)); } void Modified: llvm/trunk/lib/System/Win32/Win32.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Win32.h?rev=118505&r1=118504&r2=118505&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Win32.h (original) +++ llvm/trunk/lib/System/Win32/Win32.h Tue Nov 9 09:11:19 2010 @@ -18,10 +18,12 @@ // Require at least Windows 2000 API. #define _WIN32_WINNT 0x0500 +#define _WIN32_IE 0x0500 // MinGW at it again. #define WIN32_LEAN_AND_MEAN #include "llvm/Config/config.h" // Get build system configuration settings #include +#include #include #include From bigcheesegs at gmail.com Tue Nov 9 09:11:31 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:11:31 -0000 Subject: [llvm-commits] [llvm] r118506 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20101109151131.69FDF2A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:11:31 2010 New Revision: 118506 URL: http://llvm.org/viewvc/llvm-project?rev=118506&view=rev Log: System/Path/Windows: Generalize GetUserHomeDirectory. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118506&r1=118505&r2=118506&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 9 09:11:31 2010 @@ -293,14 +293,15 @@ Path Path::GetUserHomeDirectory() { - // TODO: Typical Windows setup doesn't define HOME. - const char* home = getenv("HOME"); - if (home) { - Path result; - if (result.set(home)) - return result; - } - return GetRootDirectory(); + char buff[MAX_PATH]; + HRESULT res = SHGetFolderPathA(NULL, + CSIDL_FLAG_CREATE | CSIDL_APPDATA, + NULL, + SHGFP_TYPE_CURRENT, + buff); + if (res != S_OK) + assert(0 && "Failed to get user home directory"); + return Path(buff); } Path From bigcheesegs at gmail.com Tue Nov 9 09:11:42 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 09 Nov 2010 15:11:42 -0000 Subject: [llvm-commits] [llvm] r118507 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20101109151142.AD6FD2A6C12C@llvm.org> Author: mspencer Date: Tue Nov 9 09:11:42 2010 New Revision: 118507 URL: http://llvm.org/viewvc/llvm-project?rev=118507&view=rev Log: System/Path/Windows: Implement GetLLVMDefaultConfigDir. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118507&r1=118506&r2=118507&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Nov 9 09:11:42 2010 @@ -287,8 +287,10 @@ Path Path::GetLLVMDefaultConfigDir() { - // TODO: this isn't going to fly on Windows - return Path("/etc/llvm"); + Path ret = GetUserHomeDirectory(); + if(!ret.appendComponent(".llvm")) + assert(0 && "Failed to append .llvm"); + return ret; } Path From baldrick at free.fr Tue Nov 9 10:22:27 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 09 Nov 2010 16:22:27 -0000 Subject: [llvm-commits] [llvm] r118509 - /llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll Message-ID: <20101109162227.754E22A6C12C@llvm.org> Author: baldrick Date: Tue Nov 9 10:22:27 2010 New Revision: 118509 URL: http://llvm.org/viewvc/llvm-project?rev=118509&view=rev Log: Testcase for PR8211 (llc crash at -O0). Added: llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll Added: llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll?rev=118509&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll Tue Nov 9 10:22:27 2010 @@ -0,0 +1,66 @@ +; RUN: llc < %s -march=x86-64 -O0 +; PR8211 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +module asm "\09.ident\09\22GCC: (GNU) 4.5.2 20100914 (prerelease) LLVM: 114628\22" + +%0 = type { %"int[]" } +%float = type float +%"float[]" = type [4 x float] +%int = type i32 +%"int[]" = type [4 x i32] +%"long unsigned int" = type i64 + +define void @swizzle(i8* %a, %0* %b, %0* %c) nounwind { +entry: + %a_addr = alloca i8* + %b_addr = alloca %0* + %c_addr = alloca %0* + %"alloca point" = bitcast i32 0 to i32 + store i8* %a, i8** %a_addr + store %0* %b, %0** %b_addr + store %0* %c, %0** %c_addr + %0 = load i8** %a_addr, align 64 + %1 = load %0** %b_addr, align 64 + %2 = load %0** %c_addr, align 64 + %"ssa point" = bitcast i32 0 to i32 + br label %"2" + +"2": ; preds = %entry + %3 = bitcast i8* %0 to <2 x i32>* + %4 = getelementptr inbounds %0* %1, i32 0, i32 0 + %5 = bitcast %"int[]"* %4 to <4 x float>* + %6 = load <4 x float>* %5, align 16 + %7 = bitcast <2 x i32>* %3 to <2 x float>* + %8 = bitcast <2 x float>* %7 to double* + %9 = load double* %8 + %10 = insertelement <2 x double> undef, double %9, i32 0 + %11 = insertelement <2 x double> %10, double undef, i32 1 + %12 = bitcast <2 x double> %11 to <4 x float> + %13 = shufflevector <4 x float> %6, <4 x float> %12, <4 x i32> + %14 = getelementptr inbounds %0* %1, i32 0, i32 0 + %15 = bitcast %"int[]"* %14 to <4 x float>* + store <4 x float> %13, <4 x float>* %15, align 16 + %16 = bitcast i8* %0 to <2 x i32>* + %17 = bitcast <2 x i32>* %16 to i8* + %18 = getelementptr i8* %17, i64 8 + %19 = bitcast i8* %18 to <2 x i32>* + %20 = getelementptr inbounds %0* %2, i32 0, i32 0 + %21 = bitcast %"int[]"* %20 to <4 x float>* + %22 = load <4 x float>* %21, align 16 + %23 = bitcast <2 x i32>* %19 to <2 x float>* + %24 = bitcast <2 x float>* %23 to double* + %25 = load double* %24 + %26 = insertelement <2 x double> undef, double %25, i32 0 + %27 = insertelement <2 x double> %26, double undef, i32 1 + %28 = bitcast <2 x double> %27 to <4 x float> + %29 = shufflevector <4 x float> %22, <4 x float> %28, <4 x i32> + %30 = getelementptr inbounds %0* %2, i32 0, i32 0 + %31 = bitcast %"int[]"* %30 to <4 x float>* + store <4 x float> %29, <4 x float>* %31, align 16 + br label %return + +return: ; preds = %"2" + ret void +} From bruno.cardoso at gmail.com Tue Nov 9 10:45:56 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 9 Nov 2010 14:45:56 -0200 Subject: [llvm-commits] [llvm] r118509 - /llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll In-Reply-To: <20101109162227.754E22A6C12C@llvm.org> References: <20101109162227.754E22A6C12C@llvm.org> Message-ID: Thanks Duncan! :) On Tue, Nov 9, 2010 at 2:22 PM, Duncan Sands wrote: > Author: baldrick > Date: Tue Nov ?9 10:22:27 2010 > New Revision: 118509 > > URL: http://llvm.org/viewvc/llvm-project?rev=118509&view=rev > Log: > Testcase for PR8211 (llc crash at -O0). > > Added: > ? ?llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll > > Added: llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll?rev=118509&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2010-11-09-MOVLPS.ll Tue Nov ?9 10:22:27 2010 > @@ -0,0 +1,66 @@ > +; RUN: llc < %s -march=x86-64 -O0 > +; PR8211 > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > +target triple = "x86_64-unknown-linux-gnu" > + > +module asm "\09.ident\09\22GCC: (GNU) 4.5.2 20100914 (prerelease) LLVM: 114628\22" > + > +%0 = type { %"int[]" } > +%float = type float > +%"float[]" = type [4 x float] > +%int = type i32 > +%"int[]" = type [4 x i32] > +%"long unsigned int" = type i64 > + > +define void @swizzle(i8* %a, %0* %b, %0* %c) nounwind { > +entry: > + ?%a_addr = alloca i8* > + ?%b_addr = alloca %0* > + ?%c_addr = alloca %0* > + ?%"alloca point" = bitcast i32 0 to i32 > + ?store i8* %a, i8** %a_addr > + ?store %0* %b, %0** %b_addr > + ?store %0* %c, %0** %c_addr > + ?%0 = load i8** %a_addr, align 64 > + ?%1 = load %0** %b_addr, align 64 > + ?%2 = load %0** %c_addr, align 64 > + ?%"ssa point" = bitcast i32 0 to i32 > + ?br label %"2" > + > +"2": ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry > + ?%3 = bitcast i8* %0 to <2 x i32>* > + ?%4 = getelementptr inbounds %0* %1, i32 0, i32 0 > + ?%5 = bitcast %"int[]"* %4 to <4 x float>* > + ?%6 = load <4 x float>* %5, align 16 > + ?%7 = bitcast <2 x i32>* %3 to <2 x float>* > + ?%8 = bitcast <2 x float>* %7 to double* > + ?%9 = load double* %8 > + ?%10 = insertelement <2 x double> undef, double %9, i32 0 > + ?%11 = insertelement <2 x double> %10, double undef, i32 1 > + ?%12 = bitcast <2 x double> %11 to <4 x float> > + ?%13 = shufflevector <4 x float> %6, <4 x float> %12, <4 x i32> > + ?%14 = getelementptr inbounds %0* %1, i32 0, i32 0 > + ?%15 = bitcast %"int[]"* %14 to <4 x float>* > + ?store <4 x float> %13, <4 x float>* %15, align 16 > + ?%16 = bitcast i8* %0 to <2 x i32>* > + ?%17 = bitcast <2 x i32>* %16 to i8* > + ?%18 = getelementptr i8* %17, i64 8 > + ?%19 = bitcast i8* %18 to <2 x i32>* > + ?%20 = getelementptr inbounds %0* %2, i32 0, i32 0 > + ?%21 = bitcast %"int[]"* %20 to <4 x float>* > + ?%22 = load <4 x float>* %21, align 16 > + ?%23 = bitcast <2 x i32>* %19 to <2 x float>* > + ?%24 = bitcast <2 x float>* %23 to double* > + ?%25 = load double* %24 > + ?%26 = insertelement <2 x double> undef, double %25, i32 0 > + ?%27 = insertelement <2 x double> %26, double undef, i32 1 > + ?%28 = bitcast <2 x double> %27 to <4 x float> > + ?%29 = shufflevector <4 x float> %22, <4 x float> %28, <4 x i32> > + ?%30 = getelementptr inbounds %0* %2, i32 0, i32 0 > + ?%31 = bitcast %"int[]"* %30 to <4 x float>* > + ?store <4 x float> %29, <4 x float>* %31, align 16 > + ?br label %return > + > +return: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %"2" > + ?ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From aggarwa4 at illinois.edu Tue Nov 9 11:14:22 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 09 Nov 2010 17:14:22 -0000 Subject: [llvm-commits] [poolalloc] r118512 - in /poolalloc/trunk/lib/DSA: DataStructure.cpp Local.cpp Message-ID: <20101109171422.846E32A6C12C@llvm.org> Author: aggarwa4 Date: Tue Nov 9 11:14:22 2010 New Revision: 118512 URL: http://llvm.org/viewvc/llvm-project?rev=118512&view=rev Log: Size of a node with type VOID, should be 0. Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=118512&r1=118511&r2=118512&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Tue Nov 9 11:14:22 2010 @@ -332,13 +332,12 @@ if (!NewTy || NewTy->isVoidTy()) return; if (isCollapsedNode()) return; - if (isArrayNode()) { + if (isArrayNode() && getSize() > 0) { assert (getSize() && "array node has size of zero!\n"); Offset %= getSize(); } const TargetData &TD = getParentGraph()->getTargetData(); if (Offset >= getSize()) growSize(Offset+TD.getTypeAllocSize(NewTy)); - if (Offset >= getSize() && NewTy->isVoidTy()) growSize(Offset + 1); TyMap[Offset] = getParentGraph()->getTypeSS().getOrCreate(TyMap[Offset], NewTy); @@ -374,9 +373,6 @@ if (isCollapsedNode()) return; if (isArrayNode()) Offset %= getSize(); - if (Offset >= getSize()) - growSize(Offset + 1); - if (!TyMap[Offset]) TyMap[Offset] = TyIt; if (TyIt) { @@ -525,7 +521,7 @@ } } if (CurNodeH.getNode()->isArrayNode() && NH.getNode()->isArrayNode()) { - if(NH.getNode()->getSize() != 1 && CurNodeH.getNode()->getSize() != 1 + if(NH.getNode()->getSize() != 0 && CurNodeH.getNode()->getSize() != 0 && (NH.getNode()->getSize() != CurNodeH.getNode()->getSize())){ CurNodeH.getNode()->foldNodeCompletely(); NH.getNode()->foldNodeCompletely(); @@ -789,11 +785,9 @@ DN = NH.getNode(); } #endif - } - if (DN->getSize() < SN->getSize()) - DN->growSize(SN->getSize()); + } - if ((SN->isArrayNode() && !DN->isArrayNode()) || + if ((SN->isArrayNode() && !DN->isArrayNode()) || (!SN->isArrayNode() && DN->isArrayNode())) { if(SN->getSize() != 0 && DN->getSize() != 0 && (SN->getSize() != DN->getSize())){ @@ -802,17 +796,18 @@ } } if (SN->isArrayNode() && DN->isArrayNode()) { - if((SN->getSize() != DN->getSize()) && (SN->getSize() != 1) && DN->getSize() != 1) { + if((SN->getSize() != DN->getSize()) && (SN->getSize() != 0) && DN->getSize() != 0) { DN->foldNodeCompletely(); DN = NH.getNode(); } } + if (!DN->isNodeCompletelyFolded() && DN->getSize() < SN->getSize()) + DN->growSize(SN->getSize()); // Merge the type entries of the two nodes together... if (!DN->isNodeCompletelyFolded()) DN->mergeTypeInfo(SN, NH.getOffset() - SrcNH.getOffset()); - } assert(!DN->isDeadNode()); Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=118512&r1=118511&r2=118512&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Tue Nov 9 11:14:22 2010 @@ -575,7 +575,7 @@ // increment the offset by the actual byte offset being accessed Offset += (unsigned)TD.getStructLayout(STy)->getElementOffset(FieldNo); - if(!Value.getNode()->isArrayNode() || Value.getNode()->getSize() <= 1){ + if(!Value.getNode()->isArrayNode() || Value.getNode()->getSize() <= 0){ if (TD.getTypeAllocSize(STy) + Value.getOffset() > Value.getNode()->getSize()) Value.getNode()->growSize(TD.getTypeAllocSize(STy) + Value.getOffset()); } @@ -586,19 +586,14 @@ const Type *CurTy = ATy->getElementType(); if(!isa(CurTy) && - Value.getNode()->getSize() <= 1) { + Value.getNode()->getSize() <= 0) { Value.getNode()->growSize(TD.getTypeAllocSize(CurTy)); - } else if(CurTy->isVoidTy()) { - Value.getNode()->growSize(1); - } else if(isa(CurTy) && Value.getNode()->getSize() <= 1){ + } else if(isa(CurTy) && Value.getNode()->getSize() <= 0){ const Type *ETy = (cast(CurTy))->getElementType(); while(isa(ETy)) { ETy = (cast(ETy))->getElementType(); } Value.getNode()->growSize(TD.getTypeAllocSize(ETy)); - if(ETy->isVoidTy()) { - Value.getNode()->growSize(1); - } } // indexing into an array. @@ -628,21 +623,16 @@ if (!isa(I.getOperand()) || !cast(I.getOperand())->isNullValue()) { Value.getNode()->setArrayMarker(); + - - if(!isa(CurTy) && Value.getNode()->getSize() <= 1){ + if(!isa(CurTy) && Value.getNode()->getSize() <= 0){ Value.getNode()->growSize(TD.getTypeAllocSize(CurTy)); - } else if(CurTy->isVoidTy()) { - Value.getNode()->growSize(1); - } else if(isa(CurTy) && Value.getNode()->getSize() <= 1){ + } else if(isa(CurTy) && Value.getNode()->getSize() <= 0){ const Type *ETy = (cast(CurTy))->getElementType(); while(isa(ETy)) { ETy = (cast(ETy))->getElementType(); } Value.getNode()->growSize(TD.getTypeAllocSize(ETy)); - if(ETy->isVoidTy()) { - Value.getNode()->growSize(1); - } } if(Value.getOffset() || Offset != 0 || (!isa(CurTy) From grosbach at apple.com Tue Nov 9 11:20:54 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 17:20:54 -0000 Subject: [llvm-commits] [llvm] r118513 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101109172054.20CF82A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 11:20:53 2010 New Revision: 118513 URL: http://llvm.org/viewvc/llvm-project?rev=118513&view=rev Log: Add encoder method for ARM load/store shifted register offset operands. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118513&r1=118512&r2=118513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Nov 9 11:20:53 2010 @@ -177,6 +177,8 @@ const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) + const { return 0; } unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) const { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118513&r1=118512&r2=118513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 9 11:20:53 2010 @@ -415,8 +415,8 @@ // def ldst_so_reg : Operand, ComplexPattern { + string EncoderMethod = "getLdStSORegOpValue"; // FIXME: Simplify the printer - // FIXME: Add EncoderMethod for this addressing mode let PrintMethod = "printAddrMode2Operand"; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118513&r1=118512&r2=118513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 9 11:20:53 2010 @@ -77,6 +77,11 @@ uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; + /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' + /// operand as needed by load/store instructions. + uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; @@ -254,6 +259,46 @@ return Binary; } +uint32_t ARMMCCodeEmitter:: +getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { + const MCOperand &MO = MI.getOperand(OpIdx); + const MCOperand &MO1 = MI.getOperand(OpIdx+1); + const MCOperand &MO2 = MI.getOperand(OpIdx+2); + unsigned Rn = getARMRegisterNumbering(MO.getReg()); + unsigned Rm = getARMRegisterNumbering(MO1.getReg()); + ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); + unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); + bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; + unsigned SBits; + // LSL - 00 + // LSR - 01 + // ASR - 10 + // ROR - 11 + switch (ShOp) { + default: llvm_unreachable("Unknown shift opc!"); + case ARM_AM::lsl: SBits = 0x0; break; + case ARM_AM::lsr: SBits = 0x1; break; + case ARM_AM::asr: SBits = 0x2; break; + case ARM_AM::ror: SBits = 0x3; break; + } + + // {16-13} = Rn + // {12} = isAdd + // {11-0} = shifter + // {3-0} = Rm + // {4} = 0 + // {6-5} = type + // {11-7} = imm + int64_t Binary = Rm; + Binary |= Rn << 13; + Binary |= SBits << 5; + Binary |= ShImm << 7; + if (isAdd) + Binary |= 1 << 12; + return Binary; +} + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand. uint32_t ARMMCCodeEmitter:: getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, From bruno.cardoso at gmail.com Tue Nov 9 11:25:34 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 09 Nov 2010 17:25:34 -0000 Subject: [llvm-commits] [llvm] r118515 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Message-ID: <20101109172534.CE0CA2A6C12C@llvm.org> Author: bruno Date: Tue Nov 9 11:25:34 2010 New Revision: 118515 URL: http://llvm.org/viewvc/llvm-project?rev=118515&view=rev Log: Fix trailing whitespace and style, no functionality change Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=118515&r1=118514&r2=118515&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Nov 9 11:25:34 2010 @@ -19,28 +19,28 @@ def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; -def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, +def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisInt<1>]>; -def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, +def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisInt<4>]>; def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; // Call -def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, +def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag, SDNPVariadic]>; -// Hi and Lo nodes are used to handle global addresses. Used on -// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol +// Hi and Lo nodes are used to handle global addresses. Used on +// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol // static model. (nothing to do with Mips Registers Hi and Lo) def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; // Return -def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, +def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, SDNPOptInFlag]>; // These are target-independent nodes, but have target-specific formats. @@ -126,90 +126,60 @@ let isCommutable = 1 in class ArithR op, bits<6> func, string instr_asm, SDNode OpNode, InstrItinClass itin>: - FR< op, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>; + FR; let isCommutable = 1 in class ArithOverflowR op, bits<6> func, string instr_asm>: - FR< op, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [], IIAlu>; + FR; // Arithmetic 2 register operands class ArithI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : - FI< op, - (outs CPURegs:$dst), - (ins CPURegs:$b, Od:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>; + FI; class ArithOverflowI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : - FI< op, - (outs CPURegs:$dst), - (ins CPURegs:$b, Od:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [], IIAlu>; + FI; // Arithmetic Multiply ADD/SUB let rd=0 in class MArithR func, string instr_asm> : - FR< 0x1c, - func, - (outs CPURegs:$rs), - (ins CPURegs:$rt), - !strconcat(instr_asm, "\t$rs, $rt"), - [], IIImul>; + FR<0x1c, func, (outs CPURegs:$rs), (ins CPURegs:$rt), + !strconcat(instr_asm, "\t$rs, $rt"), [], IIImul>; // Logical class LogicR func, string instr_asm, SDNode OpNode>: - FR< 0x00, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; + FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), + !strconcat(instr_asm, "\t$dst, $b, $c"), + [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; class LogicI op, string instr_asm, SDNode OpNode>: - FI< op, - (outs CPURegs:$dst), - (ins CPURegs:$b, uimm16:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>; + FI; class LogicNOR op, bits<6> func, string instr_asm>: - FR< op, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>; + FR; // Shifts let rt = 0 in class LogicR_shift_imm func, string instr_asm, SDNode OpNode>: - FR< 0x00, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, shamt:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>; + FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c), + !strconcat(instr_asm, "\t$dst, $b, $c"), + [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>; class LogicR_shift_reg func, string instr_asm, SDNode OpNode>: - FR< 0x00, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; + FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), + !strconcat(instr_asm, "\t$dst, $b, $c"), + [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; // Load Upper Imediate class LoadUpper op, string instr_asm>: @@ -222,76 +192,55 @@ // Memory Load/Store let canFoldAsLoad = 1, hasDelaySlot = 1 in class LoadM op, string instr_asm, PatFrag OpNode>: - FI< op, - (outs CPURegs:$dst), - (ins mem:$addr), - !strconcat(instr_asm, "\t$dst, $addr"), - [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>; + FI; class StoreM op, string instr_asm, PatFrag OpNode>: - FI< op, - (outs), - (ins CPURegs:$dst, mem:$addr), - !strconcat(instr_asm, "\t$dst, $addr"), - [(OpNode CPURegs:$dst, addr:$addr)], IIStore>; + FI; // Conditional Branch let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in { class CBranch op, string instr_asm, PatFrag cond_op>: - FI< op, - (outs), - (ins CPURegs:$a, CPURegs:$b, brtarget:$offset), - !strconcat(instr_asm, "\t$a, $b, $offset"), - [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)], - IIBranch>; - + FI; class CBranchZero op, string instr_asm, PatFrag cond_op>: - FI< op, - (outs), - (ins CPURegs:$src, brtarget:$offset), - !strconcat(instr_asm, "\t$src, $offset"), - [(brcond (cond_op CPURegs:$src, 0), bb:$offset)], - IIBranch>; + FI; } // SetCC class SetCC_R op, bits<6> func, string instr_asm, PatFrag cond_op>: - FR< op, - func, - (outs CPURegs:$dst), - (ins CPURegs:$b, CPURegs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))], - IIAlu>; + FR; class SetCC_I op, string instr_asm, PatFrag cond_op, Operand Od, PatLeaf imm_type>: - FI< op, - (outs CPURegs:$dst), - (ins CPURegs:$b, Od:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))], - IIAlu>; + FI; // Unconditional branch let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in class JumpFJ op, string instr_asm>: - FJ< op, - (outs), - (ins brtarget:$target), - !strconcat(instr_asm, "\t$target"), - [(br bb:$target)], IIBranch>; + FJ; let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in class JumpFR op, bits<6> func, string instr_asm>: - FR< op, - func, - (outs), - (ins CPURegs:$target), - !strconcat(instr_asm, "\t$target"), - [(brind CPURegs:$target)], IIBranch>; + FR; // Jump and Link (Call) let isCall=1, hasDelaySlot=1, @@ -299,86 +248,62 @@ Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in { class JumpLink op, string instr_asm>: - FJ< op, - (outs), - (ins calltarget:$target, variable_ops), - !strconcat(instr_asm, "\t$target"), - [(MipsJmpLink imm:$target)], IIBranch>; + FJ; let rd=31 in class JumpLinkReg op, bits<6> func, string instr_asm>: - FR< op, - func, - (outs), - (ins CPURegs:$rs, variable_ops), - !strconcat(instr_asm, "\t$rs"), - [(MipsJmpLink CPURegs:$rs)], IIBranch>; + FR; class BranchLink: - FI< 0x1, - (outs), - (ins CPURegs:$rs, brtarget:$target, variable_ops), - !strconcat(instr_asm, "\t$rs, $target"), - [], IIBranch>; + FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops), + !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>; } // Mul, Div class MulDiv func, string instr_asm, InstrItinClass itin>: - FR< 0x00, - func, - (outs), - (ins CPURegs:$a, CPURegs:$b), - !strconcat(instr_asm, "\t$a, $b"), - [], itin>; + FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b), + !strconcat(instr_asm, "\t$a, $b"), [], itin>; // Move from Hi/Lo class MoveFromLOHI func, string instr_asm>: - FR< 0x00, - func, - (outs CPURegs:$dst), - (ins), - !strconcat(instr_asm, "\t$dst"), - [], IIHiLo>; + FR<0x00, func, (outs CPURegs:$dst), (ins), + !strconcat(instr_asm, "\t$dst"), [], IIHiLo>; class MoveToLOHI func, string instr_asm>: - FR< 0x00, - func, - (outs), - (ins CPURegs:$src), - !strconcat(instr_asm, "\t$src"), - [], IIHiLo>; + FR<0x00, func, (outs), (ins CPURegs:$src), + !strconcat(instr_asm, "\t$src"), [], IIHiLo>; class EffectiveAddress : - FI<0x09, - (outs CPURegs:$dst), - (ins mem:$addr), - instr_asm, - [(set CPURegs:$dst, addr:$addr)], IIAlu>; + FI<0x09, (outs CPURegs:$dst), (ins mem:$addr), + instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>; // Count Leading Ones/Zeros in Word class CountLeading func, string instr_asm, SDNode CountOp>: - FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src), - !strconcat(instr_asm, "\t$dst, $src"), - [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>; + FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src), + !strconcat(instr_asm, "\t$dst, $src"), + [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>; // Sign Extend in Register. class SignExtInReg func, string instr_asm, ValueType vt>: - FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src), - !strconcat(instr_asm, "\t$dst, $src"), - [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>; + FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src), + !strconcat(instr_asm, "\t$dst, $src"), + [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>; // Byte Swap class ByteSwap func, string instr_asm>: - FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src), - !strconcat(instr_asm, "\t$dst, $src"), - [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>; + FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src), + !strconcat(instr_asm, "\t$dst, $src"), + [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>; // Conditional Move class CondMov func, string instr_asm, PatLeaf MovCode>: - FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T, - CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"), - [(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T, - CPURegs:$cond, MovCode))], NoItinerary>; + FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T, + CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"), + [(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T, + CPURegs:$cond, MovCode))], NoItinerary>; //===----------------------------------------------------------------------===// // Pseudo instructions @@ -408,13 +333,13 @@ def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>; def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>; -// The supported Mips ISAs dont have any instruction close to the SELECT_CC +// The supported Mips ISAs dont have any instruction close to the SELECT_CC // operation. The solution is to create a Mips pseudo SELECT_CC instruction -// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally +// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally // replace it for real supported nodes into EmitInstrWithCustomInserter let usesCustomInserter = 1 in { - class PseudoSelCC: - MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr, + class PseudoSelCC: + MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr, [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>; } @@ -493,7 +418,7 @@ def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target), "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>; -/// Multiply and Divide Instructions. +/// Multiply and Divide Instructions. let Defs = [HI, LO] in { def MULT : MulDiv<0x18, "mult", IIImul>; def MULTu : MulDiv<0x19, "multu", IIImul>; @@ -605,9 +530,9 @@ (ADDiu CPURegs:$hi, tconstpool:$lo)>; // gp_rel relocs -def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), +def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), (ADDiu CPURegs:$gp, tglobaladdr:$in)>; -def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), +def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), (ADDiu CPURegs:$gp, tconstpool:$in)>; // Mips does not have "not", so we expand our way @@ -665,7 +590,7 @@ def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F), (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>; -def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F), +def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F), (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>; // setcc patterns From baldrick at free.fr Tue Nov 9 11:25:51 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 09 Nov 2010 17:25:51 -0000 Subject: [llvm-commits] [llvm] r118516 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20101109172551.59BE62A6C12C@llvm.org> Author: baldrick Date: Tue Nov 9 11:25:51 2010 New Revision: 118516 URL: http://llvm.org/viewvc/llvm-project?rev=118516&view=rev Log: Factorize code, no functionality change. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=118516&r1=118515&r2=118516&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Nov 9 11:25:51 2010 @@ -193,6 +193,31 @@ return CmpInst::makeCmpResultType(Op->getType()); } +/// ThreadCmpOverSelect - In the case of a comparison with a select instruction, +/// try to simplify the comparison by seeing whether both branches of the select +/// result in the same value. Returns the common value if so, otherwise returns +/// null. +static Value *ThreadCmpOverSelect(CmpInst::Predicate Pred, Value *LHS, + Value *RHS, const TargetData *TD) { + // Make sure the select is on the LHS. + if (!isa(LHS)) { + std::swap(LHS, RHS); + Pred = CmpInst::getSwappedPredicate(Pred); + } + assert(isa(LHS) && "Not comparing with a select instruction!"); + SelectInst *SI = cast(LHS); + + // Now that we have "cmp select(cond, TV, FV), RHS", analyse it. + // Does "cmp TV, RHS" simplify? + if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD)) + // It does! Does "cmp FV, RHS" simplify? + if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD)) + // It does! If they simplified to the same value, then use it as the + // result of the original comparison. + if (TCmp == FCmp) + return TCmp; + return 0; +} /// SimplifyICmpInst - Given operands for an ICmpInst, see if we can /// fold the result. If not, this returns null. @@ -255,23 +280,9 @@ // If the comparison is with the result of a select instruction, check whether // comparing with either branch of the select always yields the same value. - if (isa(LHS) || isa(RHS)) { - // Make sure the select is on the LHS. - if (!isa(LHS)) { - std::swap(LHS, RHS); - Pred = CmpInst::getSwappedPredicate(Pred); - } - SelectInst *SI = cast(LHS); - // Now that we have "icmp select(cond, TV, FV), RHS", analyse it. - // Does "icmp TV, RHS" simplify? - if (Value *TCmp = SimplifyICmpInst(Pred, SI->getTrueValue(), RHS, TD)) - // It does! Does "icmp FV, RHS" simplify? - if (Value *FCmp = SimplifyICmpInst(Pred, SI->getFalseValue(), RHS, TD)) - // It does! If they simplified to the same value, then use it as the - // result of the original comparison. - if (TCmp == FCmp) - return TCmp; - } + if (isa(LHS) || isa(RHS)) + if (Value *V = ThreadCmpOverSelect(Pred, LHS, RHS, TD)) + return V; return 0; } @@ -352,23 +363,9 @@ // If the comparison is with the result of a select instruction, check whether // comparing with either branch of the select always yields the same value. - if (isa(LHS) || isa(RHS)) { - // Make sure the select is on the LHS. - if (!isa(LHS)) { - std::swap(LHS, RHS); - Pred = CmpInst::getSwappedPredicate(Pred); - } - SelectInst *SI = cast(LHS); - // Now that we have "fcmp select(cond, TV, FV), RHS", analyse it. - // Does "fcmp TV, RHS" simplify? - if (Value *TCmp = SimplifyFCmpInst(Pred, SI->getTrueValue(), RHS, TD)) - // It does! Does "fcmp FV, RHS" simplify? - if (Value *FCmp = SimplifyFCmpInst(Pred, SI->getFalseValue(), RHS, TD)) - // It does! If they simplified to the same value, then use it as the - // result of the original comparison. - if (TCmp == FCmp) - return TCmp; - } + if (isa(LHS) || isa(RHS)) + if (Value *V = ThreadCmpOverSelect(Pred, LHS, RHS, TD)) + return V; return 0; } From grosbach at apple.com Tue Nov 9 11:36:59 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 17:36:59 -0000 Subject: [llvm-commits] [llvm] r118586 - /llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Message-ID: <20101109173659.76B2C2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 11:36:59 2010 New Revision: 118586 URL: http://llvm.org/viewvc/llvm-project?rev=118586&view=rev Log: ARM .word data fixups don't need an adjustment. Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118586&r1=118585&r2=118586&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Nov 9 11:36:59 2010 @@ -152,6 +152,7 @@ default: llvm_unreachable("Unknown fixup kind!"); case FK_Data_4: + return Value; case ARM::fixup_arm_pcrel_12: // ARM PC-relative values are offset by 8. return Value - 8; From grosbach at apple.com Tue Nov 9 11:38:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 17:38:15 -0000 Subject: [llvm-commits] [llvm] r118587 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20101109173815.59DD42A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 11:38:15 2010 New Revision: 118587 URL: http://llvm.org/viewvc/llvm-project?rev=118587&view=rev Log: For ARM load/store instructions, encode [reg+reg] with no shifter immediate as a left shift by zero. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118587&r1=118586&r2=118587&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 9 11:38:15 2010 @@ -277,6 +277,9 @@ // ROR - 11 switch (ShOp) { default: llvm_unreachable("Unknown shift opc!"); + case ARM_AM::no_shift: + assert(ShImm == 0 && "Non-zero shift amount with no shift type!"); + // fall through case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x1; break; case ARM_AM::asr: SBits = 0x2; break; From benny.kra at googlemail.com Tue Nov 9 11:44:35 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 9 Nov 2010 18:44:35 +0100 Subject: [llvm-commits] [llvm] r118461 - /llvm/trunk/lib/VMCore/Attributes.cpp In-Reply-To: <20101109002703.D3B3A2A6C12C@llvm.org> References: <20101109002703.D3B3A2A6C12C@llvm.org> Message-ID: On 09.11.2010, at 01:27, Owen Anderson wrote: > Author: resistor > Date: Mon Nov 8 18:27:03 2010 > New Revision: 118461 > > URL: http://llvm.org/viewvc/llvm-project?rev=118461&view=rev > Log: > Fix PR8441, a race condition in the static attributes list. While the reference counting was itself threadsafe, > the implicit removal of each object from the global list was not. Make this operation atomic. > > Modified: > llvm/trunk/lib/VMCore/Attributes.cpp > > Modified: llvm/trunk/lib/VMCore/Attributes.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=118461&r1=118460&r2=118461&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Attributes.cpp (original) > +++ llvm/trunk/lib/VMCore/Attributes.cpp Mon Nov 8 18:27:03 2010 > @@ -106,7 +106,10 @@ > // AttributeListImpl Definition > //===----------------------------------------------------------------------===// > > + > namespace llvm { > +static ManagedStatic > ALMutex; > + > class AttributeListImpl : public FoldingSetNode { > sys::cas_flag RefCount; > > @@ -122,10 +125,15 @@ > RefCount = 0; > } > > - void AddRef() { sys::AtomicIncrement(&RefCount); } > + void AddRef() { > + sys::SmartScopedLock Lock(*ALMutex); > + ++RefCount; > + } > void DropRef() { > - sys::cas_flag old = sys::AtomicDecrement(&RefCount); > - if (old == 0) delete this; > + sys::SmartScopedLock Lock(*ALMutex); > + sys::cas_flag old = RefCount++; > + if (old == 0) > + delete this; > } Shouldn't DropRef() decrement RefCount rather than incrementing it? From resistor at mac.com Tue Nov 9 11:46:38 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 09 Nov 2010 17:46:38 -0000 Subject: [llvm-commits] [llvm] r118588 - /llvm/trunk/lib/VMCore/Attributes.cpp Message-ID: <20101109174638.F2B862A6C12C@llvm.org> Author: resistor Date: Tue Nov 9 11:46:38 2010 New Revision: 118588 URL: http://llvm.org/viewvc/llvm-project?rev=118588&view=rev Log: Really fix the leak in the attributes list. Thanks to Benjamin Kramer for pointing out how I was being stupid. Modified: llvm/trunk/lib/VMCore/Attributes.cpp Modified: llvm/trunk/lib/VMCore/Attributes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=118588&r1=118587&r2=118588&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Attributes.cpp (original) +++ llvm/trunk/lib/VMCore/Attributes.cpp Tue Nov 9 11:46:38 2010 @@ -131,8 +131,8 @@ } void DropRef() { sys::SmartScopedLock Lock(*ALMutex); - sys::cas_flag old = RefCount++; - if (old == 1) + sys::cas_flag new_val = RefCount--; + if (new_val == 0) delete this; } From resistor at mac.com Tue Nov 9 11:47:10 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 09 Nov 2010 17:47:10 -0000 Subject: [llvm-commits] [llvm] r118589 - /llvm/trunk/lib/VMCore/Attributes.cpp Message-ID: <20101109174710.65FC22A6C12C@llvm.org> Author: resistor Date: Tue Nov 9 11:47:10 2010 New Revision: 118589 URL: http://llvm.org/viewvc/llvm-project?rev=118589&view=rev Log: Last try to get this reference counting right, I swear. Modified: llvm/trunk/lib/VMCore/Attributes.cpp Modified: llvm/trunk/lib/VMCore/Attributes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=118589&r1=118588&r2=118589&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Attributes.cpp (original) +++ llvm/trunk/lib/VMCore/Attributes.cpp Tue Nov 9 11:47:10 2010 @@ -131,7 +131,7 @@ } void DropRef() { sys::SmartScopedLock Lock(*ALMutex); - sys::cas_flag new_val = RefCount--; + sys::cas_flag new_val = --RefCount; if (new_val == 0) delete this; } From resistor at mac.com Tue Nov 9 11:51:02 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 09 Nov 2010 09:51:02 -0800 Subject: [llvm-commits] [llvm] r118463 - /llvm/trunk/lib/System/DynamicLibrary.cpp In-Reply-To: References: <20101109003606.EB0F42A6C12C@llvm.org> Message-ID: <5FD84C31-B8FF-4711-87B6-0D870856A018@mac.com> On Nov 8, 2010, at 10:07 PM, Chris Lattner wrote: > > On Nov 8, 2010, at 4:36 PM, Owen Anderson wrote: > >> Author: resistor >> Date: Mon Nov 8 18:36:06 2010 >> New Revision: 118463 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118463&view=rev >> Log: >> Fix PR8441, a thread unsafe static variable in our dynamic library loading facilities. > > Hi Owen, > > Does SmartMutex cause a static constructor? Yes, as does sys::Mutex. Unfortunately, we can't use ManagedStatic here because it would introduce a circular dependency (System --> Support --> System). I feel like we tried to move ManagedStatic to System at some point in the past, and that it didn't work out, but I don't remember why. --Owen > >> >> Modified: >> llvm/trunk/lib/System/DynamicLibrary.cpp >> >> Modified: llvm/trunk/lib/System/DynamicLibrary.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/DynamicLibrary.cpp?rev=118463&r1=118462&r2=118463&view=diff >> ============================================================================== >> --- llvm/trunk/lib/System/DynamicLibrary.cpp (original) >> +++ llvm/trunk/lib/System/DynamicLibrary.cpp Mon Nov 8 18:36:06 2010 >> @@ -15,6 +15,7 @@ >> //===----------------------------------------------------------------------===// >> >> #include "llvm/System/DynamicLibrary.h" >> +#include "llvm/System/Mutex.h" >> #include "llvm/Config/config.h" >> #include >> #include >> @@ -60,6 +61,7 @@ >> //=== independent code. >> //===----------------------------------------------------------------------===// >> >> +static SmartMutex HandlesMutex; >> static std::vector *OpenedHandles = 0; >> >> >> @@ -76,6 +78,7 @@ >> if (Filename == NULL) >> H = RTLD_DEFAULT; >> #endif >> + SmartScopedLock Lock(HandlesMutex); >> if (OpenedHandles == 0) >> OpenedHandles = new std::vector(); >> OpenedHandles->push_back(H); >> @@ -110,6 +113,7 @@ >> >> #if HAVE_DLFCN_H >> // Now search the libraries. >> + SmartScopedLock Lock(HandlesMutex); >> if (OpenedHandles) { >> for (std::vector::iterator I = OpenedHandles->begin(), >> E = OpenedHandles->end(); I != E; ++I) { >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101109/e219ff4a/attachment.html From rafael.espindola at gmail.com Tue Nov 9 12:24:52 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 13:24:52 -0500 Subject: [llvm-commits] [llvm] r118367 - in /llvm/trunk: include/llvm/System/Path.h lib/System/Unix/Path.inc lib/System/Win32/Path.inc In-Reply-To: <65559D06-9349-4839-9CD7-CE3E5EBFDDF1@apple.com> References: <20101107043650.C10C82A6C136@llvm.org> <65559D06-9349-4839-9CD7-CE3E5EBFDDF1@apple.com> Message-ID: > Hi Rafael, > > What will this be used for? I used it in clang to detect the library path used when running ld on linux. > Dan > Cheers, Rafael From grosbach at apple.com Tue Nov 9 12:43:54 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 18:43:54 -0000 Subject: [llvm-commits] [llvm] r118600 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20101109184354.5D97C2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 12:43:54 2010 New Revision: 118600 URL: http://llvm.org/viewvc/llvm-project?rev=118600&view=rev Log: Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118600&r1=118599&r2=118600&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 9 12:43:54 2010 @@ -851,6 +851,7 @@ bits<17> shift; let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn + let Inst{15-12} = Rt; let Inst{11-0} = shift{11-0}; } } @@ -879,6 +880,7 @@ bits<17> shift; let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn + let Inst{15-12} = Rt; let Inst{11-0} = shift{11-0}; } } From grosbach at apple.com Tue Nov 9 12:45:04 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 18:45:04 -0000 Subject: [llvm-commits] [llvm] r118601 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101109184504.B8F1C2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 12:45:04 2010 New Revision: 118601 URL: http://llvm.org/viewvc/llvm-project?rev=118601&view=rev Log: Further MCize ARM constant pool values. This allows basic PIC references for object file emission. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118601&r1=118600&r2=118601&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Nov 9 12:45:04 2010 @@ -227,73 +227,7 @@ /// EmitMachineConstantPoolValue - Print a machine constantpool value to /// the .s file. - virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { - int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); - - ARMConstantPoolValue *ACPV = static_cast(MCPV); - SmallString<128> Str; - raw_svector_ostream OS(Str); - - if (ACPV->isLSDA()) { - OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); - } else if (ACPV->isBlockAddress()) { - OS << *GetBlockAddressSymbol(ACPV->getBlockAddress()); - } else if (ACPV->isGlobalValue()) { - const GlobalValue *GV = ACPV->getGV(); - bool isIndirect = Subtarget->isTargetDarwin() && - Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); - if (!isIndirect) - OS << *Mang->getSymbol(GV); - else { - // FIXME: Remove this when Darwin transition to @GOT like syntax. - MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); - OS << *Sym; - - MachineModuleInfoMachO &MMIMachO = - MMI->getObjFileInfo(); - MachineModuleInfoImpl::StubValueTy &StubSym = - GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) : - MMIMachO.getGVStubEntry(Sym); - if (StubSym.getPointer() == 0) - StubSym = MachineModuleInfoImpl:: - StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage()); - } - } else { - assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); - OS << *GetExternalSymbolSymbol(ACPV->getSymbol()); - } - - // Create an MCSymbol for the reference. - MCSymbol *MCSym = OutContext.GetOrCreateSymbol(OS.str()); - const MCExpr *Expr = MCSymbolRefExpr::Create(MCSym, OutContext); - - // FIXME: Model the whole expression an an MCExpr and we can get rid - // of this hasRawTextSupport() clause and just do an EmitValue(). - if (OutStreamer.hasRawTextSupport()) { - if (ACPV->hasModifier()) OS << "(" << ACPV->getModifier() << ")"; - if (ACPV->getPCAdjustment() != 0) { - OS << "-(" << MAI->getPrivateGlobalPrefix() << "PC" - << getFunctionNumber() << "_" << ACPV->getLabelId() - << "+" << (unsigned)ACPV->getPCAdjustment(); - if (ACPV->mustAddCurrentAddress()) - OS << "-."; - OS << ')'; - } - const char *DataDirective = 0; - switch (Size) { - case 1: DataDirective = MAI->getData8bitsDirective(0); break; - case 2: DataDirective = MAI->getData16bitsDirective(0); break; - case 4: DataDirective = MAI->getData32bitsDirective(0); break; - default: assert(0 && "Unknown CPV size"); - } - Twine Text(DataDirective, OS.str()); - OutStreamer.EmitRawText(Text); - } else { - assert(!ACPV->hasModifier() && ACPV->getPCAdjustment() == 0 && - "ARM binary streamer of non-trivial constant pool value!"); - OutStreamer.EmitValue(Expr, Size); - } - } + virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV); }; } // end of anonymous namespace @@ -669,6 +603,88 @@ return Label; } +void ARMAsmPrinter:: +EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { + int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); + + ARMConstantPoolValue *ACPV = static_cast(MCPV); + SmallString<128> Str; + raw_svector_ostream OS(Str); + + if (ACPV->isLSDA()) { + OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); + } else if (ACPV->isBlockAddress()) { + OS << *GetBlockAddressSymbol(ACPV->getBlockAddress()); + } else if (ACPV->isGlobalValue()) { + const GlobalValue *GV = ACPV->getGV(); + bool isIndirect = Subtarget->isTargetDarwin() && + Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); + if (!isIndirect) + OS << *Mang->getSymbol(GV); + else { + // FIXME: Remove this when Darwin transition to @GOT like syntax. + MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); + OS << *Sym; + + MachineModuleInfoMachO &MMIMachO = + MMI->getObjFileInfo(); + MachineModuleInfoImpl::StubValueTy &StubSym = + GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) : + MMIMachO.getGVStubEntry(Sym); + if (StubSym.getPointer() == 0) + StubSym = MachineModuleInfoImpl:: + StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage()); + } + } else { + assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); + OS << *GetExternalSymbolSymbol(ACPV->getSymbol()); + } + + // Create an MCSymbol for the reference. + MCSymbol *MCSym = OutContext.GetOrCreateSymbol(OS.str()); + const MCExpr *Expr = MCSymbolRefExpr::Create(MCSym, OutContext); + + // FIXME: Model the whole expression an an MCExpr and we can get rid + // of this hasRawTextSupport() clause and just do an EmitValue(). + if (OutStreamer.hasRawTextSupport()) { + if (ACPV->hasModifier()) OS << "(" << ACPV->getModifier() << ")"; + if (ACPV->getPCAdjustment() != 0) { + OS << "-(" << MAI->getPrivateGlobalPrefix() << "PC" + << getFunctionNumber() << "_" << ACPV->getLabelId() + << "+" << (unsigned)ACPV->getPCAdjustment(); + if (ACPV->mustAddCurrentAddress()) + OS << "-."; + OS << ')'; + } + const char *DataDirective = 0; + switch (Size) { + case 1: DataDirective = MAI->getData8bitsDirective(0); break; + case 2: DataDirective = MAI->getData16bitsDirective(0); break; + case 4: DataDirective = MAI->getData32bitsDirective(0); break; + default: assert(0 && "Unknown CPV size"); + } + Twine Text(DataDirective, OS.str()); + OutStreamer.EmitRawText(Text); + } else { + assert(!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress() && + "ARM binary streamer of non-trivial constant pool value!"); + if (ACPV->getPCAdjustment()) { + MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(), + getFunctionNumber(), + ACPV->getLabelId(), + OutContext); + const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext); + PCRelExpr = + MCBinaryExpr::CreateAdd(PCRelExpr, + MCConstantExpr::Create(ACPV->getPCAdjustment(), + OutContext), + OutContext); + Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext); + } + OutStreamer.EmitValue(Expr, Size); + } +} + void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) { unsigned Opcode = MI->getOpcode(); int OpNum = 1; From clattner at apple.com Tue Nov 9 12:51:42 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 9 Nov 2010 10:51:42 -0800 Subject: [llvm-commits] [llvm] r118463 - /llvm/trunk/lib/System/DynamicLibrary.cpp In-Reply-To: <5FD84C31-B8FF-4711-87B6-0D870856A018@mac.com> References: <20101109003606.EB0F42A6C12C@llvm.org> <5FD84C31-B8FF-4711-87B6-0D870856A018@mac.com> Message-ID: On Nov 9, 2010, at 9:51 AM, Owen Anderson wrote: > > On Nov 8, 2010, at 10:07 PM, Chris Lattner wrote: > >> >> On Nov 8, 2010, at 4:36 PM, Owen Anderson wrote: >> >>> Author: resistor >>> Date: Mon Nov 8 18:36:06 2010 >>> New Revision: 118463 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=118463&view=rev >>> Log: >>> Fix PR8441, a thread unsafe static variable in our dynamic library loading facilities. >> >> Hi Owen, >> >> Does SmartMutex cause a static constructor? > > Yes, as does sys::Mutex. Unfortunately, we can't use ManagedStatic here because it would introduce a circular dependency (System --> Support --> System). I feel like we tried to move ManagedStatic to System at some point in the past, and that it didn't work out, but I don't remember why. Why not just depend on threadsafe statics to handle this? Targets that don't support threadsafe statics aren't going to support threads anyway. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101109/33536220/attachment.html From atrick at apple.com Tue Nov 9 13:01:17 2010 From: atrick at apple.com (Andrew Trick) Date: Tue, 09 Nov 2010 19:01:17 -0000 Subject: [llvm-commits] [llvm] r118604 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp Message-ID: <20101109190117.89D9E2A6C12C@llvm.org> Author: atrick Date: Tue Nov 9 13:01:17 2010 New Revision: 118604 URL: http://llvm.org/viewvc/llvm-project?rev=118604&view=rev Log: Adds RABasic verification and tracing. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=118604&r1=118603&r2=118604&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Nov 9 13:01:17 2010 @@ -15,6 +15,7 @@ #define DEBUG_TYPE "regalloc" #include "LiveIntervalUnion.h" +#include "llvm/ADT/SparseBitVector.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include @@ -73,12 +74,9 @@ #ifndef NDEBUG // check for overlap (inductively) if (segPos != segments_.begin()) { - SegmentIter prevPos = segPos; - --prevPos; - assert(prevPos->end <= segment.start && "overlapping segments" ); + assert(prior(segPos)->end <= segment.start && "overlapping segments" ); } - SegmentIter nextPos = segPos; - ++nextPos; + SegmentIter nextPos = next(segPos); if (nextPos != segments_.end()) assert(segment.end <= nextPos->start && "overlapping segments" ); #endif // NDEBUG @@ -98,6 +96,49 @@ } } +raw_ostream& llvm::operator<<(raw_ostream& os, const LiveSegment &ls) { + return os << '[' << ls.start << ',' << ls.end << ':' << + ls.liveVirtReg->reg << ")"; +} + +void LiveSegment::dump() const { + dbgs() << *this << "\n"; +} + +void +LiveIntervalUnion::print(raw_ostream &os, + const AbstractRegisterDescription *rdesc) const { + os << "LIU "; + if (rdesc != NULL) + os << rdesc->getName(repReg_); + else { + os << repReg_; + } + for (SegmentIter segI = segments_.begin(), segEnd = segments_.end(); + segI != segEnd; ++segI) { + dbgs() << " " << *segI; + } + os << "\n"; +} + +void LiveIntervalUnion::dump(const AbstractRegisterDescription *rdesc) const { + print(dbgs(), rdesc); +} + +#ifndef NDEBUG +// Verify the live intervals in this union and add them to the visited set. +void LiveIntervalUnion::verify(LvrBitSet& visitedVRegs) { + SegmentIter segI = segments_.begin(); + SegmentIter segEnd = segments_.end(); + if (segI == segEnd) return; + visitedVRegs.set(segI->liveVirtReg->reg); + for (++segI; segI != segEnd; ++segI) { + visitedVRegs.set(segI->liveVirtReg->reg); + assert(prior(segI)->end <= segI->start && "overlapping segments" ); + } +} +#endif //!NDEBUG + // Private interface accessed by Query. // // Find a pair of segments that intersect, one in the live virtual register Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118604&r1=118603&r2=118604&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Nov 9 13:01:17 2010 @@ -23,6 +23,12 @@ namespace llvm { +#ifndef NDEBUG +// forward declaration +template class SparseBitVector; +typedef SparseBitVector<128> LvrBitSet; +#endif + /// A LiveSegment is a copy of a LiveRange object used within /// LiveIntervalUnion. LiveSegment additionally contains a pointer to its /// original live virtual register (LiveInterval). This allows quick lookup of @@ -51,6 +57,9 @@ // Order segments by starting point only--we expect them to be disjoint. bool operator<(const LiveSegment &ls) const { return start < ls.start; } + + void dump() const; + void print(raw_ostream &os) const; }; inline bool operator<(SlotIndex V, const LiveSegment &ls) { @@ -66,6 +75,16 @@ return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end; } +template <> struct isPodLike { static const bool value = true; }; + +raw_ostream& operator<<(raw_ostream& os, const LiveSegment &ls); + +/// Abstraction to provide info for the representative register. +class AbstractRegisterDescription { +public: + virtual const char *getName(unsigned reg) const = 0; +}; + /// Union of live intervals that are strong candidates for coalescing into a /// single register (either physical or virtual depending on the context). We /// expect the constituent live intervals to be disjoint, although we may @@ -122,6 +141,16 @@ // Remove a live virtual register's segments from this union. void extract(const LiveInterval &lvr); + void dump(const AbstractRegisterDescription *regInfo) const; + + // If tri != NULL, use it to decode repReg_ + void print(raw_ostream &os, const AbstractRegisterDescription *rdesc) const; + +#ifndef NDEBUG + // Verify the live intervals in this union and add them to the visited set. + void verify(LvrBitSet& visitedVRegs); +#endif + /// Cache a single interference test result in the form of two intersecting /// segments. This allows efficiently iterating over the interferences. The /// iteration logic is handled by LiveIntervalUnion::Query which may Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=118604&r1=118603&r2=118604&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Tue Nov 9 13:01:17 2010 @@ -128,6 +128,11 @@ // exists, return the interfering register, which may be preg or an alias. unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg); +#ifndef NDEBUG + // Verify each LiveIntervalUnion. + void verify(); +#endif + // Helper that spills all live virtual registers currently unified under preg // that interfere with the most recently queried lvr. void spillInterferences(unsigned preg, Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118604&r1=118603&r2=118604&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Nov 9 13:01:17 2010 @@ -34,6 +34,9 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" +#ifndef NDEBUG +#include "llvm/ADT/SparseBitVector.h" +#endif #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -46,6 +49,19 @@ static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator); +// Temporary verification option until we can put verification inside +// MachineVerifier. +static cl::opt +VerifyRegAlloc("verify-regalloc", + cl::desc("Verify live intervals before renaming")); + +class PhysicalRegisterDescription : public AbstractRegisterDescription { + const TargetRegisterInfo *tri_; +public: + PhysicalRegisterDescription(const TargetRegisterInfo *tri): tri_(tri) {} + virtual const char *getName(unsigned reg) const { return tri_->getName(reg); } +}; + namespace { /// RABasic provides a minimal implementation of the basic register allocation @@ -153,6 +169,40 @@ RegAllocBase::releaseMemory(); } +#ifndef NDEBUG +// Verify each LiveIntervalUnion. +void RegAllocBase::verify() { + LvrBitSet visitedVRegs; + OwningArrayPtr unionVRegs(new LvrBitSet[physReg2liu_.numRegs()]); + // Verify disjoint unions. + for (unsigned preg = 0; preg < physReg2liu_.numRegs(); ++preg) { + DEBUG(PhysicalRegisterDescription prd(tri_); physReg2liu_[preg].dump(&prd)); + LvrBitSet &vregs = unionVRegs[preg]; + physReg2liu_[preg].verify(vregs); + // Union + intersection test could be done efficiently in one pass, but + // don't add a method to SparseBitVector unless we really need it. + assert(!visitedVRegs.intersects(vregs) && "vreg in multiple unions"); + visitedVRegs |= vregs; + } + // Verify vreg coverage. + for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end(); + liItr != liEnd; ++liItr) { + unsigned reg = liItr->first; + LiveInterval &li = *liItr->second; + if (li.empty() ) continue; + if (TargetRegisterInfo::isPhysicalRegister(reg)) continue; + if (!vrm_->hasPhys(reg)) continue; // spilled? + unsigned preg = vrm_->getPhys(reg); + if (!unionVRegs[preg].test(reg)) { + dbgs() << "LiveVirtReg " << reg << " not in union " << + tri_->getName(preg) << "\n"; + llvm_unreachable("unallocated live vreg"); + } + } + // FIXME: I'm not sure how to verify spilled intervals. +} +#endif //!NDEBUG + //===----------------------------------------------------------------------===// // RegAllocBase Implementation //===----------------------------------------------------------------------===// @@ -222,6 +272,7 @@ liItr != liEnd; ++liItr) { unsigned reg = liItr->first; LiveInterval &li = *liItr->second; + if (li.empty()) continue; if (TargetRegisterInfo::isPhysicalRegister(reg)) { physReg2liu_[reg].unify(li); } @@ -243,13 +294,14 @@ unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs); if (availablePhysReg) { DEBUG(dbgs() << "allocating: " << tri_->getName(availablePhysReg) << - " " << lvr << '\n'); + " " << *lvr << '\n'); assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions"); vrm_->assignVirt2Phys(lvr->reg, availablePhysReg); physReg2liu_[availablePhysReg].unify(*lvr); } for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end(); lvrI != lvrEnd; ++lvrI) { + if ((*lvrI)->empty()) continue; DEBUG(dbgs() << "queuing new interval: " << **lvrI << "\n"); assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) && "expect split value in virtual register"); @@ -274,26 +326,32 @@ return 0; } -// Spill all live virtual registers currently unified under preg that interfere -// with lvr. +// Spill or split all live virtual registers currently unified under preg that +// interfere with lvr. The newly spilled or split live intervals are returned by +// appending them to splitLVRs. void RABasic::spillInterferences(unsigned preg, SmallVectorImpl &splitLVRs) { SmallPtrSet spilledLVRs; LiveIntervalUnion::Query &query = queries_[preg]; + // Record each interference before mutating either the union or live + // intervals. LiveIntervalUnion::InterferenceResult ir = query.firstInterference(); assert(query.isInterference(ir) && "expect interference"); do { - LiveInterval *lvr = ir.liuSegPos()->liveVirtReg; - if (!spilledLVRs.insert(lvr)) continue; - // Spill the previously allocated lvr. - SmallVector spillIs; // ignored - spiller_->spill(lvr, splitLVRs, spillIs); + spilledLVRs.insert(ir.liuSegPos()->liveVirtReg); } while (query.nextInterference(ir)); for (SmallPtrSetIterator lvrI = spilledLVRs.begin(), lvrEnd = spilledLVRs.end(); lvrI != lvrEnd; ++lvrI ) { + LiveInterval& lvr = **lvrI; + // Spill the previously allocated lvr. + DEBUG(dbgs() << "extracting from " << preg << " " << lvr << '\n'); // Deallocate the interfering lvr by removing it from the preg union. - physReg2liu_[preg].extract(**lvrI); + // Live intervals may not be in a union during modification. + physReg2liu_[preg].extract(lvr); + // Spill the extracted interval. + SmallVector spillIs; + spiller_->spill(&lvr, splitLVRs, spillIs); } // After extracting segments, the query's results are invalid. query.clear(); @@ -399,6 +457,24 @@ // optional HTML output DEBUG(rmf_->renderMachineFunction("After basic register allocation.", vrm_)); + // FIXME: Verification currently must run before VirtRegRewriter. We should + // make the rewriter a separate pass and override verifyAnalysis instead. When + // that happens, verification naturally falls under VerifyMachineCode. +#ifndef NDEBUG + if (VerifyRegAlloc) { + // Verify accuracy of LiveIntervals. The standard machine code verifier + // ensures that each LiveIntervals covers all uses of the virtual reg. + + // FIXME: MachineVerifier is currently broken when using the standard + // spiller. Enable it for InlineSpiller only. + // mf_->verify(this); + + // Verify that LiveIntervals are partitioned into unions and disjoint within + // the unions. + verify(); + } +#endif // !NDEBUG + // Run rewriter std::auto_ptr rewriter(createVirtRegRewriter()); rewriter->runOnMachineFunction(*mf_, *vrm_, lis_); From gkistanova at gmail.com Tue Nov 9 13:01:39 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 09 Nov 2010 19:01:39 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118605 - /llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Message-ID: <20101109190139.3F9B72A6C12C@llvm.org> Author: gkistanova Date: Tue Nov 9 13:01:39 2010 New Revision: 118605 URL: http://llvm.org/viewvc/llvm-project?rev=118605&view=rev Log: Removed obsolete builder's script. Removed: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi Removed: llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi?rev=118604&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi (original) +++ llvm-gcc-4.2/trunk/extras/build-x-4-gnueabi (removed) @@ -1,220 +0,0 @@ -#!/bin/bash - -set -e # Terminate script at the first line that fails. -set -o pipefail # Return the first non-zero pipe command error. -set -x # Print commands as they are executed - -# This script performs an automated build on i686-pc-linux-gnu of -# cross llvm-gcc for arm-none-linux-gnueabi. It assumes the valid native -# compiler for i686-pc-linux-gnu is in place and available as well as -# cross libraries and headers for arm-none-linux-gnueabi. - -# --build=i686-pc-linux-gnu -# --host=i686-pc-linux-gnu2 -# --target=arm-none-linux-gnueabi -# - -# The usage: -# Run this build from the build from the build root directory as -# build-self-4-mingw32 [] [] - -# Expected project tree structure: -# -# +-- ${LLVM_src} -# +-- ${LLVM_GCC_src} -# +-- ${LLVM_obj} -# +-- ${LLVM_GCC_obj} -# +-- ${INSTALL} - -LLVM_src=llvm.src # The LLVM source code root directory name. -LLVM_GCC_src=llvm-gcc.src # The LLVM-GCC source code root directory name. -LLVM_obj=llvm.obj # The LLVM build root directory name. -LLVM_GCC_obj=llvm-gcc.obj # The LLVM-GCC build root directory name. -INSTALL=install # Where the result will be installed. - -BUILD_ROOT=$PWD # Where build happens. -PRIVATE_INSTALL=${BUILD_ROOT}/${INSTALL} # Where the result will be installed. - -#------------------------------------------------------------------------------ -# Define build steps, parse and validate input parameters -#------------------------------------------------------------------------------ - -# This script supports the following steps: -do_clean=no # Clean up the build directory. -do_copy_cross_tools=no # Copy cross-tools. -do_configure_llvm=no # Configure LLVM. -do_make_llvm=no # Make LLVM. -do_install_llvm=no # Install LLVM-GCC. -do_test_llvm=no # Test LLVM. -do_configure_llvmgcc=no # Configure LLVM-GCC. -do_make_llvmgcc=no # Make LLVM-GCC. -do_install_llvmgcc=no # Install LLVM-GCC. -do_all=no # Runs all steps at once when requested. - -# Set step parameter -if (( $# == 0 )) ; then - do_all=yes -fi -# else -if (( ! $# == 0 )) ; then - # First check that the parameter actually defines a step. - case $1 in - clean | \ - copy_cross_tools | \ - configure_llvm | \ - make_llvm | \ - install_llvm | \ - test_llvm | \ - configure_llvmgcc | \ - make_llvmgcc | \ - install_llvmgcc | \ - all) - eval do_$1=yes # Set the flag for the requested step . - shift # Remove it since is is ours and already precessed. - ;; - - *) - # Not our parameter. Pass it as is. - esac -fi - -# Set all steps if do_all requested -if [ "$do_all" == "yes" ] ; then - # Set all steps to yes - do_clean=yes - do_copy_cross_tools=yes - do_configure_llvm=yes - do_make_llvm=yes - do_install_llvm=yes - do_test_llvm=yes - do_configure_llvmgcc=yes - do_make_llvmgcc=yes - do_install_llvmgcc=yes -fi - -#------------------------------------------------------------------------------ -# Step: Clean up. -#------------------------------------------------------------------------------ -if [ "$do_clean" == "yes" ] ; then - - # Remove everything from where we will be installing the result. - rm -rf ${PRIVATE_INSTALL} - mkdir -p ${PRIVATE_INSTALL} - chmod a+rx ${PRIVATE_INSTALL} - -fi - -#------------------------------------------------------------------------------ -# Step: Copy cross-tools and newlib -#------------------------------------------------------------------------------ -if [ "$do_copy_cross_tools" == "yes" ] ; then - - # We need a local copy of binutils, system libraries and headers, - # since we will be installing there. - cp -Ru /opt/cross-tools/* ${PRIVATE_INSTALL} - cp -Ru /opt/newlib-src/newlib/ ${BUILD_ROOT}/${LLVM_GCC_src} - cp -Ru /opt/newlib-src/libgloss/ ${BUILD_ROOT}/${LLVM_GCC_src} - -fi - -#------------------------------------------------------------------------------ -# Step: Configure LLVM. -#------------------------------------------------------------------------------ -if [ "$do_configure_llvm" == "yes" ] ; then - - # Remove previously build files if any. - rm -rf ${BUILD_ROOT}/${LLVM_obj} - mkdir -p ${BUILD_ROOT}/${LLVM_obj} - chmod a+rx ${BUILD_ROOT}/${LLVM_obj} - cd ${BUILD_ROOT}/${LLVM_obj} - - ../${LLVM_src}/configure --prefix=${PRIVATE_INSTALL} \ - --enable-optimized \ - --enable-targets=cbe,arm \ - $@ # Extra args if any - -fi - -#------------------------------------------------------------------------------ -# Step: Make LLVM. -#------------------------------------------------------------------------------ -if [ "$do_make_llvm" == "yes" ] ; then - - cd ${BUILD_ROOT}/${LLVM_obj} - # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. - nice -n 20 make VERBOSE=1 \ - $@ # Extra args if any, like -j16 for example. - -fi - -#------------------------------------------------------------------------------ -# Step: Install LLVM. -#------------------------------------------------------------------------------ -if [ "$do_install_llvm" == "yes" ] ; then - - cd ${BUILD_ROOT}/${LLVM_obj} - # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. - nice -n 20 make install VERBOSE=1 \ - $@ # Extra args if any, like -j16 for example. - -fi - -#------------------------------------------------------------------------------ -# Step: Test LLVM. -#------------------------------------------------------------------------------ -if [ "$do_test_llvm" == "yes" ] ; then - - cd ${BUILD_ROOT}/${LLVM_obj} - make check-lit VERBOSE=1 \ - $@ # Extra args if any, like -j16 for example. - -fi - -#------------------------------------------------------------------------------ -# Step: Configure LLVM-GCC. -#------------------------------------------------------------------------------ -if [ "$do_configure_llvmgcc" == "yes" ] ; then - - # Remove previously build files if any. - rm -rf ${BUILD_ROOT}/${LLVM_GCC_obj} - mkdir -p ${BUILD_ROOT}/${LLVM_GCC_obj} - chmod a+rx ${BUILD_ROOT}/${LLVM_GCC_obj} - cd ${BUILD_ROOT}/${LLVM_GCC_obj} - - ../${LLVM_GCC_src}/configure --prefix=${PRIVATE_INSTALL} \ - --target=arm-eabi \ - --enable-languages=c,c++ \ - --disable-nls \ - --prefix=/opt/cross-tools \ - --program-prefix=llvm- \ - --with-newlib \ - --with-headers=yes \ - --enable-llvm=${BUILD_ROOT}/${LLVM_obj} \ - --with-cpu=cortex-a8 \ - --with-fpu=neon \ - --with-float=hard \ - --with-abi=aapcs \ - $@ # Extra args if any -fi - -#------------------------------------------------------------------------------ -# Step: Make LLVM-GCC. -#------------------------------------------------------------------------------ -if [ "$do_make_llvmgcc" == "yes" ] ; then - - cd ${BUILD_ROOT}/${LLVM_GCC_obj} - nice -n 20 make \ - $@ # Extra args if any - -fi - -#------------------------------------------------------------------------------ -# Step: Install LLVM-GCC. -#------------------------------------------------------------------------------ -if [ "$do_install_llvmgcc" == "yes" ] ; then - - cd ${BUILD_ROOT}/${LLVM_GCC_obj} - nice -n 20 make install \ - $@ # Extra args if any - -fi From grosbach at apple.com Tue Nov 9 13:22:27 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 19:22:27 -0000 Subject: [llvm-commits] [llvm] r118606 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101109192227.123F12A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 13:22:26 2010 New Revision: 118606 URL: http://llvm.org/viewvc/llvm-project?rev=118606&view=rev Log: Trailing whitespace. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118606&r1=118605&r2=118606&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 9 13:22:26 2010 @@ -956,7 +956,7 @@ MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // Simple branch support. - + // If we can, avoid recomputing the compare - redoing it could lead to wonky // behavior. // TODO: Factor this out. @@ -1005,13 +1005,13 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) .addReg(Arg1).addReg(Arg2)); - + // For floating point we need to move the result to a comparison register // that we can then use for branches. if (isFloat) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::FMSTAT))); - + unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); @@ -1020,7 +1020,7 @@ return true; } } - + unsigned CmpReg = getRegForValue(BI->getCondition()); if (CmpReg == 0) return false; @@ -1826,10 +1826,10 @@ llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { // Completely untested on non-darwin. const TargetMachine &TM = funcInfo.MF->getTarget(); - + // Darwin and thumb1 only for now. const ARMSubtarget *Subtarget = &TM.getSubtarget(); - if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && + if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && !DisableARMFastISel) return new ARMFastISel(funcInfo); return 0; From criswell at uiuc.edu Tue Nov 9 13:31:26 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 09 Nov 2010 19:31:26 -0000 Subject: [llvm-commits] [poolalloc] r118607 - in /poolalloc/trunk: include/dsa/DataStructure.h lib/DSA/StdLibPass.cpp Message-ID: <20101109193126.32E5A2A6C12C@llvm.org> Author: criswell Date: Tue Nov 9 13:31:26 2010 New Revision: 118607 URL: http://llvm.org/viewvc/llvm-project?rev=118607&view=rev Log: Added support for pool_argvregister(). Added code to ensure that DSNodes are not marked External when subjected to SAFECode run-time functions. This is done by removing the DSCallSites for run-time checks. Fixed the code to merge the correct DSNodeHandles together. This ensures that the DSNodeHandle offsets are correct when merging checked pointers with run-time check return values. Modified: poolalloc/trunk/include/dsa/DataStructure.h poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=118607&r1=118606&r2=118607&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Tue Nov 9 13:31:26 2010 @@ -191,7 +191,7 @@ // functions and generates graphs for them. class StdLibDataStructures : public DataStructures { void eraseCallsTo(Function* F); - void processRuntimeCheck (Module & M, std::string name); + void processRuntimeCheck (Module & M, std::string name, unsigned arg); public: static char ID; StdLibDataStructures() : DataStructures((intptr_t)&ID, "stdlib.") {} Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=118607&r1=118606&r2=118607&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Nov 9 13:31:26 2010 @@ -160,6 +160,7 @@ {"sc.pool_unregister_global", {NRET_NARGS, NRET_NARGS, NRET_NARGS, false, false, false}}, {"sc.pool_register", {NRET_NARGS, NRET_NARGS, NRET_NARGS, false, false, false}}, {"sc.pool_unregister", {NRET_NARGS, NRET_NARGS, NRET_NARGS, false, false, false}}, + {"sc.pool_argvregister", {NRET_NARGS, NRET_NARGS, NRET_NARGS, false, false, false}}, #if 0 {"remove", {false, false, false, true, false, false, false, false, false}}, @@ -238,8 +239,16 @@ // Modify a run-time check so that its return value has the same DSNode as the // checked pointer. // +// Inputs: +// M - The module in which calls to the function live. +// name - The name of the function for which direct calls should be processed. +// arg - The argument index that contains the pointer which the run-time +// check returns. +// void -StdLibDataStructures::processRuntimeCheck (Module & M, std::string name) { +StdLibDataStructures::processRuntimeCheck (Module & M, + std::string name, + unsigned arg) { // // Get a pointer to the function. // @@ -260,12 +269,18 @@ if (CI->getOperand(0) == F) { DSGraph* Graph = getDSGraph(*CI->getParent()->getParent()); DSNodeHandle RetNode = Graph->getNodeForValue(CI); - DSNodeHandle ArgNode = Graph->getNodeForValue(CI->getOperand(2)); + DSNodeHandle ArgNode = Graph->getNodeForValue(CI->getOperand(arg)); RetNode.mergeWith(ArgNode); } } } + // + // Erase the DSCallSites for this function. This should prevent other DSA + // passes from making the DSNodes passed to/returned from the function + // from becoming Incomplete or External. + // + eraseCallsTo (F); return; } @@ -392,13 +407,16 @@ // Merge return values and checked pointer values for SAFECode run-time // checks. // - processRuntimeCheck (M, "sc.boundscheck"); - processRuntimeCheck (M, "sc.boundscheckui"); - processRuntimeCheck (M, "sc.exactcheck2"); - processRuntimeCheck (M, "sc.get_actual_val"); + processRuntimeCheck (M, "sc.boundscheck", 3); + processRuntimeCheck (M, "sc.boundscheckui", 3); + processRuntimeCheck (M, "sc.exactcheck2", 2); + processRuntimeCheck (M, "sc.get_actual_val", 2); - // In Local we marked nodes passed to/returned from 'StdLib' functions as External, because at - // that point they were. However they no longer are necessarily so, and we need to update accordingly. + // + // In the Local DSA Pass, we marked nodes passed to/returned from 'StdLib' + // functions as External because, at that point, they were. However, they no + // longer are necessarily External, and we need to update accordingly. + // GlobalsGraph->computeExternalFlags(DSGraph::ResetExternal); for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) if (!I->isDeclaration()) { From sabre at nondot.org Tue Nov 9 13:37:28 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 09 Nov 2010 19:37:28 -0000 Subject: [llvm-commits] [llvm] r118608 - /llvm/trunk/lib/Target/README.txt Message-ID: <20101109193728.40D3A2A6C12C@llvm.org> Author: lattner Date: Tue Nov 9 13:37:28 2010 New Revision: 118608 URL: http://llvm.org/viewvc/llvm-project?rev=118608&view=rev Log: add a case we fail to devirt. Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=118608&r1=118607&r2=118608&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Tue Nov 9 13:37:28 2010 @@ -1963,3 +1963,23 @@ ret i32 %b } //===---------------------------------------------------------------------===// + +clang -O3 fails to devirtualize this virtual inheritance case: (GCC PR45875) + +struct c1 {}; +struct c10 : c1{ + virtual void foo (); +}; +struct c11 : c10, c1{ + virtual void f6 (); +}; +struct c28 : virtual c11{ + void f6 (); +}; +void check_c28 () { + c28 obj; + c11 *ptr = &obj; + ptr->f6 (); +} + +//===---------------------------------------------------------------------===// From stoklund at 2pi.dk Tue Nov 9 13:41:22 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 9 Nov 2010 11:41:22 -0800 Subject: [llvm-commits] [llvm] r118604 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp In-Reply-To: <20101109190117.89D9E2A6C12C@llvm.org> References: <20101109190117.89D9E2A6C12C@llvm.org> Message-ID: <52B477E2-FFC3-4796-8661-C5BAAA10220C@2pi.dk> On Nov 9, 2010, at 11:01 AM, Andrew Trick wrote: > if (segPos != segments_.begin()) { > - SegmentIter prevPos = segPos; > - --prevPos; > - assert(prevPos->end <= segment.start && "overlapping segments" ); > + assert(prior(segPos)->end <= segment.start && "overlapping segments" ); > } > - SegmentIter nextPos = segPos; > - ++nextPos; > + SegmentIter nextPos = next(segPos); > if (nextPos != segments_.end()) > assert(segment.end <= nextPos->start && "overlapping segments" ); > #endif // NDEBUG Please spell these llvm::next() and llvm::prior(). Apparently, some C++ libraries (C++0x?) define std::next and std::prior, and Koenig lookup gets confused when our iterators derive from std::iterator. From grosbach at apple.com Tue Nov 9 13:40:22 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 19:40:22 -0000 Subject: [llvm-commits] [llvm] r118609 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101109194022.6BABD2A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 13:40:22 2010 New Revision: 118609 URL: http://llvm.org/viewvc/llvm-project?rev=118609&view=rev Log: Handle ARM constant pool values that need an explicit reference to the '.' pseudo-label. (TLS stuff). Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118609&r1=118608&r2=118609&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Nov 9 13:40:22 2010 @@ -666,7 +666,7 @@ Twine Text(DataDirective, OS.str()); OutStreamer.EmitRawText(Text); } else { - assert(!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress() && + assert(!ACPV->hasModifier() && "ARM binary streamer of non-trivial constant pool value!"); if (ACPV->getPCAdjustment()) { MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(), @@ -679,6 +679,14 @@ MCConstantExpr::Create(ACPV->getPCAdjustment(), OutContext), OutContext); + if (ACPV->mustAddCurrentAddress()) { + // We want "( - .)", but MC doesn't have a concept of the '.' + // label, so just emit a local label end reference that instead. + MCSymbol *DotSym = OutContext.CreateTempSymbol(); + OutStreamer.EmitLabel(DotSym); + const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); + Expr = MCBinaryExpr::CreateSub(Expr, DotExpr, OutContext); + } Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext); } OutStreamer.EmitValue(Expr, Size); From gohman at apple.com Tue Nov 9 13:41:37 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 19:41:37 -0000 Subject: [llvm-commits] [llvm] r118610 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101109194137.2899D2A6C12C@llvm.org> Author: djg Date: Tue Nov 9 13:41:37 2010 New Revision: 118610 URL: http://llvm.org/viewvc/llvm-project?rev=118610&view=rev Log: Delete AccessesArgumentsAndGlobals, which was unused. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118610&r1=118609&r2=118610&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 13:41:37 2010 @@ -195,11 +195,6 @@ // This property corresponds to the IntrReadWriteArgMem LLVM intrinsic flag. AccessesArguments, - // AccessesArgumentsAndGlobals - This function has accesses function - // arguments and global variables well known (possibly volatile) ways, but - // does not access any other memory. - AccessesArgumentsAndGlobals, - // OnlyReadsMemory - This function does not perform any non-local stores or // volatile loads, but may read from any memory location. // From gohman at apple.com Tue Nov 9 13:43:24 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 19:43:24 -0000 Subject: [llvm-commits] [llvm] r118611 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101109194324.945102A6C12C@llvm.org> Author: djg Date: Tue Nov 9 13:43:24 2010 New Revision: 118611 URL: http://llvm.org/viewvc/llvm-project?rev=118611&view=rev Log: Factor out the logic for onlyReadsMemory into a helper function. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118611&r1=118610&r2=118611&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 13:43:24 2010 @@ -247,8 +247,7 @@ /// This property corresponds to the GCC 'pure' attribute. /// bool onlyReadsMemory(ImmutableCallSite CS) { - ModRefBehavior MRB = getModRefBehavior(CS); - return MRB == DoesNotAccessMemory || MRB == OnlyReadsMemory; + return onlyReadsMemory(getModRefBehavior(CS)); } /// onlyReadsMemory - If the specified function is known to only read from @@ -256,7 +255,14 @@ /// when the call site is not known. /// bool onlyReadsMemory(const Function *F) { - ModRefBehavior MRB = getModRefBehavior(F); + return onlyReadsMemory(getModRefBehavior(F)); + } + + /// onlyReadsMemory - If the functions with the specified behavior are known + /// to only read from non-volatile memory (or not access memory at all), return + /// true. For use when the call site is not known. + /// + static bool onlyReadsMemory(ModRefBehavior MRB) { return MRB == DoesNotAccessMemory || MRB == OnlyReadsMemory; } From atrick at apple.com Tue Nov 9 13:47:51 2010 From: atrick at apple.com (Andrew Trick) Date: Tue, 09 Nov 2010 19:47:51 -0000 Subject: [llvm-commits] [llvm] r118613 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp Message-ID: <20101109194751.8D9242A6C12C@llvm.org> Author: atrick Date: Tue Nov 9 13:47:51 2010 New Revision: 118613 URL: http://llvm.org/viewvc/llvm-project?rev=118613&view=rev Log: Reverting r118604. Windows build broke. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=118613&r1=118612&r2=118613&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Nov 9 13:47:51 2010 @@ -15,7 +15,6 @@ #define DEBUG_TYPE "regalloc" #include "LiveIntervalUnion.h" -#include "llvm/ADT/SparseBitVector.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include @@ -74,9 +73,12 @@ #ifndef NDEBUG // check for overlap (inductively) if (segPos != segments_.begin()) { - assert(prior(segPos)->end <= segment.start && "overlapping segments" ); + SegmentIter prevPos = segPos; + --prevPos; + assert(prevPos->end <= segment.start && "overlapping segments" ); } - SegmentIter nextPos = next(segPos); + SegmentIter nextPos = segPos; + ++nextPos; if (nextPos != segments_.end()) assert(segment.end <= nextPos->start && "overlapping segments" ); #endif // NDEBUG @@ -96,49 +98,6 @@ } } -raw_ostream& llvm::operator<<(raw_ostream& os, const LiveSegment &ls) { - return os << '[' << ls.start << ',' << ls.end << ':' << - ls.liveVirtReg->reg << ")"; -} - -void LiveSegment::dump() const { - dbgs() << *this << "\n"; -} - -void -LiveIntervalUnion::print(raw_ostream &os, - const AbstractRegisterDescription *rdesc) const { - os << "LIU "; - if (rdesc != NULL) - os << rdesc->getName(repReg_); - else { - os << repReg_; - } - for (SegmentIter segI = segments_.begin(), segEnd = segments_.end(); - segI != segEnd; ++segI) { - dbgs() << " " << *segI; - } - os << "\n"; -} - -void LiveIntervalUnion::dump(const AbstractRegisterDescription *rdesc) const { - print(dbgs(), rdesc); -} - -#ifndef NDEBUG -// Verify the live intervals in this union and add them to the visited set. -void LiveIntervalUnion::verify(LvrBitSet& visitedVRegs) { - SegmentIter segI = segments_.begin(); - SegmentIter segEnd = segments_.end(); - if (segI == segEnd) return; - visitedVRegs.set(segI->liveVirtReg->reg); - for (++segI; segI != segEnd; ++segI) { - visitedVRegs.set(segI->liveVirtReg->reg); - assert(prior(segI)->end <= segI->start && "overlapping segments" ); - } -} -#endif //!NDEBUG - // Private interface accessed by Query. // // Find a pair of segments that intersect, one in the live virtual register Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118613&r1=118612&r2=118613&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Nov 9 13:47:51 2010 @@ -23,12 +23,6 @@ namespace llvm { -#ifndef NDEBUG -// forward declaration -template class SparseBitVector; -typedef SparseBitVector<128> LvrBitSet; -#endif - /// A LiveSegment is a copy of a LiveRange object used within /// LiveIntervalUnion. LiveSegment additionally contains a pointer to its /// original live virtual register (LiveInterval). This allows quick lookup of @@ -57,9 +51,6 @@ // Order segments by starting point only--we expect them to be disjoint. bool operator<(const LiveSegment &ls) const { return start < ls.start; } - - void dump() const; - void print(raw_ostream &os) const; }; inline bool operator<(SlotIndex V, const LiveSegment &ls) { @@ -75,16 +66,6 @@ return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end; } -template <> struct isPodLike { static const bool value = true; }; - -raw_ostream& operator<<(raw_ostream& os, const LiveSegment &ls); - -/// Abstraction to provide info for the representative register. -class AbstractRegisterDescription { -public: - virtual const char *getName(unsigned reg) const = 0; -}; - /// Union of live intervals that are strong candidates for coalescing into a /// single register (either physical or virtual depending on the context). We /// expect the constituent live intervals to be disjoint, although we may @@ -141,16 +122,6 @@ // Remove a live virtual register's segments from this union. void extract(const LiveInterval &lvr); - void dump(const AbstractRegisterDescription *regInfo) const; - - // If tri != NULL, use it to decode repReg_ - void print(raw_ostream &os, const AbstractRegisterDescription *rdesc) const; - -#ifndef NDEBUG - // Verify the live intervals in this union and add them to the visited set. - void verify(LvrBitSet& visitedVRegs); -#endif - /// Cache a single interference test result in the form of two intersecting /// segments. This allows efficiently iterating over the interferences. The /// iteration logic is handled by LiveIntervalUnion::Query which may Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=118613&r1=118612&r2=118613&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Tue Nov 9 13:47:51 2010 @@ -128,11 +128,6 @@ // exists, return the interfering register, which may be preg or an alias. unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg); -#ifndef NDEBUG - // Verify each LiveIntervalUnion. - void verify(); -#endif - // Helper that spills all live virtual registers currently unified under preg // that interfere with the most recently queried lvr. void spillInterferences(unsigned preg, Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118613&r1=118612&r2=118613&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Nov 9 13:47:51 2010 @@ -34,9 +34,6 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" -#ifndef NDEBUG -#include "llvm/ADT/SparseBitVector.h" -#endif #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -49,19 +46,6 @@ static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator); -// Temporary verification option until we can put verification inside -// MachineVerifier. -static cl::opt -VerifyRegAlloc("verify-regalloc", - cl::desc("Verify live intervals before renaming")); - -class PhysicalRegisterDescription : public AbstractRegisterDescription { - const TargetRegisterInfo *tri_; -public: - PhysicalRegisterDescription(const TargetRegisterInfo *tri): tri_(tri) {} - virtual const char *getName(unsigned reg) const { return tri_->getName(reg); } -}; - namespace { /// RABasic provides a minimal implementation of the basic register allocation @@ -169,40 +153,6 @@ RegAllocBase::releaseMemory(); } -#ifndef NDEBUG -// Verify each LiveIntervalUnion. -void RegAllocBase::verify() { - LvrBitSet visitedVRegs; - OwningArrayPtr unionVRegs(new LvrBitSet[physReg2liu_.numRegs()]); - // Verify disjoint unions. - for (unsigned preg = 0; preg < physReg2liu_.numRegs(); ++preg) { - DEBUG(PhysicalRegisterDescription prd(tri_); physReg2liu_[preg].dump(&prd)); - LvrBitSet &vregs = unionVRegs[preg]; - physReg2liu_[preg].verify(vregs); - // Union + intersection test could be done efficiently in one pass, but - // don't add a method to SparseBitVector unless we really need it. - assert(!visitedVRegs.intersects(vregs) && "vreg in multiple unions"); - visitedVRegs |= vregs; - } - // Verify vreg coverage. - for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end(); - liItr != liEnd; ++liItr) { - unsigned reg = liItr->first; - LiveInterval &li = *liItr->second; - if (li.empty() ) continue; - if (TargetRegisterInfo::isPhysicalRegister(reg)) continue; - if (!vrm_->hasPhys(reg)) continue; // spilled? - unsigned preg = vrm_->getPhys(reg); - if (!unionVRegs[preg].test(reg)) { - dbgs() << "LiveVirtReg " << reg << " not in union " << - tri_->getName(preg) << "\n"; - llvm_unreachable("unallocated live vreg"); - } - } - // FIXME: I'm not sure how to verify spilled intervals. -} -#endif //!NDEBUG - //===----------------------------------------------------------------------===// // RegAllocBase Implementation //===----------------------------------------------------------------------===// @@ -272,7 +222,6 @@ liItr != liEnd; ++liItr) { unsigned reg = liItr->first; LiveInterval &li = *liItr->second; - if (li.empty()) continue; if (TargetRegisterInfo::isPhysicalRegister(reg)) { physReg2liu_[reg].unify(li); } @@ -294,14 +243,13 @@ unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs); if (availablePhysReg) { DEBUG(dbgs() << "allocating: " << tri_->getName(availablePhysReg) << - " " << *lvr << '\n'); + " " << lvr << '\n'); assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions"); vrm_->assignVirt2Phys(lvr->reg, availablePhysReg); physReg2liu_[availablePhysReg].unify(*lvr); } for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end(); lvrI != lvrEnd; ++lvrI) { - if ((*lvrI)->empty()) continue; DEBUG(dbgs() << "queuing new interval: " << **lvrI << "\n"); assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) && "expect split value in virtual register"); @@ -326,32 +274,26 @@ return 0; } -// Spill or split all live virtual registers currently unified under preg that -// interfere with lvr. The newly spilled or split live intervals are returned by -// appending them to splitLVRs. +// Spill all live virtual registers currently unified under preg that interfere +// with lvr. void RABasic::spillInterferences(unsigned preg, SmallVectorImpl &splitLVRs) { SmallPtrSet spilledLVRs; LiveIntervalUnion::Query &query = queries_[preg]; - // Record each interference before mutating either the union or live - // intervals. LiveIntervalUnion::InterferenceResult ir = query.firstInterference(); assert(query.isInterference(ir) && "expect interference"); do { - spilledLVRs.insert(ir.liuSegPos()->liveVirtReg); + LiveInterval *lvr = ir.liuSegPos()->liveVirtReg; + if (!spilledLVRs.insert(lvr)) continue; + // Spill the previously allocated lvr. + SmallVector spillIs; // ignored + spiller_->spill(lvr, splitLVRs, spillIs); } while (query.nextInterference(ir)); for (SmallPtrSetIterator lvrI = spilledLVRs.begin(), lvrEnd = spilledLVRs.end(); lvrI != lvrEnd; ++lvrI ) { - LiveInterval& lvr = **lvrI; - // Spill the previously allocated lvr. - DEBUG(dbgs() << "extracting from " << preg << " " << lvr << '\n'); // Deallocate the interfering lvr by removing it from the preg union. - // Live intervals may not be in a union during modification. - physReg2liu_[preg].extract(lvr); - // Spill the extracted interval. - SmallVector spillIs; - spiller_->spill(&lvr, splitLVRs, spillIs); + physReg2liu_[preg].extract(**lvrI); } // After extracting segments, the query's results are invalid. query.clear(); @@ -457,24 +399,6 @@ // optional HTML output DEBUG(rmf_->renderMachineFunction("After basic register allocation.", vrm_)); - // FIXME: Verification currently must run before VirtRegRewriter. We should - // make the rewriter a separate pass and override verifyAnalysis instead. When - // that happens, verification naturally falls under VerifyMachineCode. -#ifndef NDEBUG - if (VerifyRegAlloc) { - // Verify accuracy of LiveIntervals. The standard machine code verifier - // ensures that each LiveIntervals covers all uses of the virtual reg. - - // FIXME: MachineVerifier is currently broken when using the standard - // spiller. Enable it for InlineSpiller only. - // mf_->verify(this); - - // Verify that LiveIntervals are partitioned into unions and disjoint within - // the unions. - verify(); - } -#endif // !NDEBUG - // Run rewriter std::auto_ptr rewriter(createVirtRegRewriter()); rewriter->runOnMachineFunction(*mf_, *vrm_, lis_); From gohman at apple.com Tue Nov 9 13:48:55 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 19:48:55 -0000 Subject: [llvm-commits] [llvm] r118614 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101109194855.35ADC2A6C12C@llvm.org> Author: djg Date: Tue Nov 9 13:48:55 2010 New Revision: 118614 URL: http://llvm.org/viewvc/llvm-project?rev=118614&view=rev Log: Add a AccessesArgumentsReadonly ModRefBehavior value, so that the intrinsic property IntrReadArgMem can be modeled. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118614&r1=118613&r2=118614&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 13:48:55 2010 @@ -189,6 +189,13 @@ // This property corresponds to the IntrNoMem LLVM intrinsic flag. DoesNotAccessMemory, + // AccessesArgumentsReadonly - This function loads through function + // arguments and does not perform any non-local stores or volatile + // loads. + // + // This property corresponds to the IntrReadArgMem LLVM intrinsic flag. + AccessesArgumentsReadonly, + // AccessesArguments - This function accesses function arguments in well // known (possibly volatile) ways, but does not access any other memory. // From gohman at apple.com Tue Nov 9 13:50:00 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 19:50:00 -0000 Subject: [llvm-commits] [llvm] r118615 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101109195000.CFE9F2A6C12C@llvm.org> Author: djg Date: Tue Nov 9 13:50:00 2010 New Revision: 118615 URL: http://llvm.org/viewvc/llvm-project?rev=118615&view=rev Log: AccessesArgumentsReadonly is read-only. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118615&r1=118614&r2=118615&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 13:50:00 2010 @@ -270,7 +270,9 @@ /// true. For use when the call site is not known. /// static bool onlyReadsMemory(ModRefBehavior MRB) { - return MRB == DoesNotAccessMemory || MRB == OnlyReadsMemory; + return MRB == DoesNotAccessMemory || + MRB == AccessesArgumentsReadonly || + MRB == OnlyReadsMemory; } From gohman at apple.com Tue Nov 9 13:58:21 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 19:58:21 -0000 Subject: [llvm-commits] [llvm] r118618 - in /llvm/trunk/lib: Analysis/AliasSetTracker.cpp Transforms/Scalar/LICM.cpp Message-ID: <20101109195821.40CAC2A6C12E@llvm.org> Author: djg Date: Tue Nov 9 13:58:21 2010 New Revision: 118618 URL: http://llvm.org/viewvc/llvm-project?rev=118618&view=rev Log: Teach LICM and AliasSetTracker about AccessesArgumentsReadonly. Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=118618&r1=118617&r2=118618&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Tue Nov 9 13:58:21 2010 @@ -124,7 +124,7 @@ AliasAnalysis::ModRefBehavior Behavior = AA.getModRefBehavior(CS); if (Behavior == AliasAnalysis::DoesNotAccessMemory) return; - else if (Behavior == AliasAnalysis::OnlyReadsMemory) { + if (AliasAnalysis::onlyReadsMemory(Behavior)) { AliasTy = MayAlias; AccessTy |= Refs; return; Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=118618&r1=118617&r2=118618&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Tue Nov 9 13:58:21 2010 @@ -412,7 +412,7 @@ AliasAnalysis::ModRefBehavior Behavior = AA->getModRefBehavior(CI); if (Behavior == AliasAnalysis::DoesNotAccessMemory) return true; - else if (Behavior == AliasAnalysis::OnlyReadsMemory) { + if (AliasAnalysis::onlyReadsMemory(Behavior)) { // If this call only reads from memory and there are no writes to memory // in the loop, we can hoist or sink the call as appropriate. bool FoundMod = false; From matthewbg at google.com Tue Nov 9 13:56:25 2010 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Tue, 09 Nov 2010 19:56:25 -0000 Subject: [llvm-commits] [llvm] r118616 - /llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Message-ID: <20101109195625.4BCC12A6C12C@llvm.org> Author: matthewbg Date: Tue Nov 9 13:56:25 2010 New Revision: 118616 URL: http://llvm.org/viewvc/llvm-project?rev=118616&view=rev Log: Add a trivial virtual dtor to AbstractRegisterDescription to appease -Wnon-virtual-dtor. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118616&r1=118615&r2=118616&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Nov 9 13:56:25 2010 @@ -66,6 +66,17 @@ return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end; } +template <> struct isPodLike { static const bool value = true; }; + +raw_ostream& operator<<(raw_ostream& os, const LiveSegment &ls); + +/// Abstraction to provide info for the representative register. +class AbstractRegisterDescription { +public: + virtual const char *getName(unsigned reg) const = 0; + virtual ~AbstractRegisterDescription() { } +}; + /// Union of live intervals that are strong candidates for coalescing into a /// single register (either physical or virtual depending on the context). We /// expect the constituent live intervals to be disjoint, although we may From gohman at apple.com Tue Nov 9 13:56:27 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 19:56:27 -0000 Subject: [llvm-commits] [llvm] r118617 - /llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20101109195627.8C02B2A6C12D@llvm.org> Author: djg Date: Tue Nov 9 13:56:27 2010 New Revision: 118617 URL: http://llvm.org/viewvc/llvm-project?rev=118617&view=rev Log: Teach FunctionAttrs about AccessesArgumentsReadonly. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118617&r1=118616&r2=118617&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Tue Nov 9 13:56:27 2010 @@ -152,6 +152,25 @@ } // Only reads and writes local memory. continue; + case AliasAnalysis::AccessesArgumentsReadonly: + // Check whether all pointer arguments point to local memory, and + // ignore calls that only access local memory. + for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); + CI != CE; ++CI) { + Value *Arg = *CI; + if (Arg->getType()->isPointerTy()) { + AliasAnalysis::Location Loc(Arg, + AliasAnalysis::UnknownSize, + I->getMetadata(LLVMContext::MD_tbaa)); + if (!AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) { + // Reads non-local memory. + ReadsMemory = true; + break; + } + } + } + // Only reads memory. + continue; default: // Otherwise, be conservative. break; From rafael.espindola at gmail.com Tue Nov 9 14:07:16 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 15:07:16 -0500 Subject: [llvm-commits] [PATCH] Add some options to configure for Cygming In-Reply-To: References: Message-ID: > I don't have suitable version of autoconf. Building autoconf is not that hard :-) You can normally omit the autogened files in code review. > When patches would be applicable, please feel free to commit one > with regenerating configure, thank you. > > ...Takumi > * 0002-autoconf-Add-enable-docs-to-enable-disable-buiding-a.patch > > ?--enable-docs=yes by default. > ?Some MSYS distros have incomplete pod2html, and "make install" fails. > ?with --disable-docs, building and installing docs is suppressed. +# When ENABLE_DOXYGEN is disabled, docs/ will not be built +ENABLE_DOCS = @ENABLE_DOCS@ Comment looks wrong. Cheers, Rafael From gohman at apple.com Tue Nov 9 14:06:55 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 20:06:55 -0000 Subject: [llvm-commits] [llvm] r118621 - /llvm/trunk/lib/Analysis/AliasAnalysis.cpp Message-ID: <20101109200655.4D02A2A6C12C@llvm.org> Author: djg Date: Tue Nov 9 14:06:55 2010 New Revision: 118621 URL: http://llvm.org/viewvc/llvm-project?rev=118621&view=rev Log: Teach AliasAnalysis about AccessesArgumentsReadonly. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=118621&r1=118620&r2=118621&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Nov 9 14:06:55 2010 @@ -75,9 +75,11 @@ return NoModRef; ModRefResult Mask = ModRef; - if (MRB == OnlyReadsMemory) + if (onlyReadsMemory(MRB)) Mask = Ref; - else if (MRB == AliasAnalysis::AccessesArguments) { + + if (MRB == AccessesArguments || + MRB == AccessesArgumentsReadonly) { bool doesAlias = false; for (ImmutableCallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); AI != AE; ++AI) @@ -115,20 +117,20 @@ if (CS2B == DoesNotAccessMemory) return NoModRef; // If they both only read from memory, there is no dependence. - if (CS1B == OnlyReadsMemory && CS2B == OnlyReadsMemory) + if (onlyReadsMemory(CS1B) && onlyReadsMemory(CS2B)) return NoModRef; AliasAnalysis::ModRefResult Mask = ModRef; // If CS1 only reads memory, the only dependence on CS2 can be // from CS1 reading memory written by CS2. - if (CS1B == OnlyReadsMemory) + if (onlyReadsMemory(CS1B)) Mask = ModRefResult(Mask & Ref); // If CS2 only access memory through arguments, accumulate the mod/ref // information from CS1's references to the memory referenced by // CS2's arguments. - if (CS2B == AccessesArguments) { + if (CS2B == AccessesArguments || CS2B == AccessesArgumentsReadonly) { AliasAnalysis::ModRefResult R = NoModRef; for (ImmutableCallSite::arg_iterator I = CS2.arg_begin(), E = CS2.arg_end(); I != E; ++I) { @@ -141,7 +143,7 @@ // If CS1 only accesses memory through arguments, check if CS2 references // any of the memory referenced by CS1's arguments. If not, return NoModRef. - if (CS1B == AccessesArguments) { + if (CS1B == AccessesArguments || CS1B == AccessesArgumentsReadonly) { AliasAnalysis::ModRefResult R = NoModRef; for (ImmutableCallSite::arg_iterator I = CS1.arg_begin(), E = CS1.arg_end(); I != E; ++I) From gohman at apple.com Tue Nov 9 14:07:21 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 20:07:21 -0000 Subject: [llvm-commits] [llvm] r118622 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <20101109200721.19CE62A6C12C@llvm.org> Author: djg Date: Tue Nov 9 14:07:20 2010 New Revision: 118622 URL: http://llvm.org/viewvc/llvm-project?rev=118622&view=rev Log: Translate IntrReadArgMem to AccessesArgumentsReadonly. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=118622&r1=118621&r2=118622&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Tue Nov 9 14:07:20 2010 @@ -573,6 +573,8 @@ OS << " return DoesNotAccessMemory;\n"; break; case CodeGenIntrinsic::ReadArgMem: + OS << " return AccessesArgumentsReadonly;\n"; + break; case CodeGenIntrinsic::ReadMem: OS << " return OnlyReadsMemory;\n"; break; From gohman at apple.com Tue Nov 9 14:09:35 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 20:09:35 -0000 Subject: [llvm-commits] [llvm] r118623 - /llvm/trunk/lib/Analysis/CaptureTracking.cpp Message-ID: <20101109200935.2C7282A6C12C@llvm.org> Author: djg Date: Tue Nov 9 14:09:35 2010 New Revision: 118623 URL: http://llvm.org/viewvc/llvm-project?rev=118623&view=rev Log: VAArg doesn't capture its operand. Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=118623&r1=118622&r2=118623&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original) +++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Tue Nov 9 14:09:35 2010 @@ -95,6 +95,9 @@ case Instruction::Load: // Loading from a pointer does not cause it to be captured. break; + case Instruction::VAArg: + // "va-arg" from a pointer does not cause it to be captured. + break; case Instruction::Ret: if (ReturnCaptures) return true; From rafael.espindola at gmail.com Tue Nov 9 14:11:35 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 15:11:35 -0500 Subject: [llvm-commits] [Review request] test: Add the new feature "loadable_module" In-Reply-To: References: Message-ID: On 21 October 2010 03:51, NAKAMURA Takumi wrote: > Hello. > > Cygming can build Module.dll for Opt and Bugpoint with autoconf. I think these patches are fine. Do the generated modules work on windows? I had the impression that on windowns plugins could not access symbols from the main executable. > I will propose two patches attached. Please give me comments. > > > * 0001 - Add the feature "loadable_module" > > By default, "loadable_module" is 1. > On cygwin and win32(s), it obeys ENABLE_SHARED. > > It should not have any sideeffects, I believe. > > > * 0002 - patches for 4 tests > > Without "loadable_module", all of 4 tests marks as "UNSUPPORTED". > > I have confirmed (both enable_shared) on CentOS5, Cygwin and Mingw. > > I have confirmed with cmake on Mingw. > IIRC, cmake/mingw and cmake/msvc set ENABLE_SHARED as '0'. > I believe it might not affect msvc buildbots. > > > ps. LLVMHello.dll can be built manually :) > (or seek llvmdev or here with "llvmhello") > > > Enjoy happy testing, ...Takumi > Cheers, Rafael From gohman at apple.com Tue Nov 9 14:13:27 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 20:13:27 -0000 Subject: [llvm-commits] [llvm] r118624 - /llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20101109201327.34F682A6C12C@llvm.org> Author: djg Date: Tue Nov 9 14:13:27 2010 New Revision: 118624 URL: http://llvm.org/viewvc/llvm-project?rev=118624&view=rev Log: Use the AliasAnalysis interface to determine how a Function accesses memory. This isn't a real improvement with present day AliasAnalysis implementations; it's mainly for consistency. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118624&r1=118623&r2=118624&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Tue Nov 9 14:13:27 2010 @@ -101,14 +101,15 @@ // External node - may write memory. Just give up. return false; - if (F->doesNotAccessMemory()) + AliasAnalysis::ModRefBehavior MRB = AA->getModRefBehavior(F); + if (MRB == AliasAnalysis::DoesNotAccessMemory) // Already perfect! continue; // Definitions with weak linkage may be overridden at linktime with // something that writes memory, so treat them like declarations. if (F->isDeclaration() || F->mayBeOverridden()) { - if (!F->onlyReadsMemory()) + if (!AliasAnalysis::onlyReadsMemory(MRB)) // May write memory. Just give up. return false; From gohman at apple.com Tue Nov 9 14:17:38 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 20:17:38 -0000 Subject: [llvm-commits] [llvm] r118627 - in /llvm/trunk: lib/Transforms/IPO/FunctionAttrs.cpp test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Message-ID: <20101109201738.7A7862A6C12D@llvm.org> Author: djg Date: Tue Nov 9 14:17:38 2010 New Revision: 118627 URL: http://llvm.org/viewvc/llvm-project?rev=118627&view=rev Log: Teach FunctionAttrs about the VAArg instruction. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118627&r1=118626&r2=118627&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Tue Nov 9 14:17:38 2010 @@ -195,6 +195,13 @@ if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) continue; } + } else if (VAArgInst *VI = dyn_cast(I)) { + // Ignore vaargs on local memory. + AliasAnalysis::Location Loc(VI->getPointerOperand(), + AliasAnalysis::UnknownSize, + VI->getMetadata(LLVMContext::MD_tbaa)); + if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) + continue; } // Any remaining instructions need to be taken seriously! Check if they Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll?rev=118627&r1=118626&r2=118627&view=diff ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll (original) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Tue Nov 9 14:17:38 2010 @@ -55,6 +55,20 @@ ret void } +; Similar to the others, va_arg only accesses memory through its operand. + +; CHECK: define i32 @test3_yes(i8* nocapture %p) nounwind readnone { +define i32 @test3_yes(i8* %p) nounwind { + %t = va_arg i8* %p, i32, !tbaa !1 + ret i32 %t +} + +; CHECK: define i32 @test3_no(i8* nocapture %p) nounwind { +define i32 @test3_no(i8* %p) nounwind { + %t = va_arg i8* %p, i32, !tbaa !2 + ret i32 %t +} + declare void @callee(i32* %p) nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) nounwind From rafael.espindola at gmail.com Tue Nov 9 14:34:52 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 15:34:52 -0500 Subject: [llvm-commits] [PATCH][System/Path] Update comments to match code. In-Reply-To: References: Message-ID: On 8 November 2010 20:49, Michael Spencer wrote: > Neither the Unix or Windows implementation include > LLVM_LIB_SEARCH_PATH. I'm assuming the comments are wrong. Just making > sure it's not the code that is wrong. Probably a cut and paste error,GetBitcodeLibraryPaths uses that variable. The only indirect user I can find is in llvm-ld. Maybe we could move this stuff there? > Also, the Windows implementation is completely wrong on a multitude of > levels. It should be using SHGetFolderPath instead of hard coding > C:\Windows, and none of those directories contain any libraries that > are actually used on modern Windows. > > What is the actual purpose of this function? To get libraries for link > time or runtime? If it's for link time then what we really want is the > platform sdk and MSVC directories, or something else on MinGW. If it's > for runtime then... well... take your pick. There are quite a few > directories depending on the OS version, Architecture, etc... And then > there's MinGW. > > - Michael Spencer Cheers, Rafael From gohman at apple.com Tue Nov 9 14:33:58 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 09 Nov 2010 20:33:58 -0000 Subject: [llvm-commits] [llvm] r118628 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101109203358.29B2F2A6C12C@llvm.org> Author: djg Date: Tue Nov 9 14:33:57 2010 New Revision: 118628 URL: http://llvm.org/viewvc/llvm-project?rev=118628&view=rev Log: Convert comments to doxygen syntax. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118628&r1=118627&r2=118628&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 14:33:57 2010 @@ -181,37 +181,37 @@ /// interface. Also, functions may freely modify stack space local to their /// invocation without having to report it through these interfaces. enum ModRefBehavior { - // DoesNotAccessMemory - This function does not perform any non-local loads - // or stores to memory. - // - // This property corresponds to the GCC 'const' attribute. - // This property corresponds to the LLVM IR 'readnone' attribute. - // This property corresponds to the IntrNoMem LLVM intrinsic flag. + /// DoesNotAccessMemory - This function does not perform any non-local loads + /// or stores to memory. + /// + /// This property corresponds to the GCC 'const' attribute. + /// This property corresponds to the LLVM IR 'readnone' attribute. + /// This property corresponds to the IntrNoMem LLVM intrinsic flag. DoesNotAccessMemory, - // AccessesArgumentsReadonly - This function loads through function - // arguments and does not perform any non-local stores or volatile - // loads. - // - // This property corresponds to the IntrReadArgMem LLVM intrinsic flag. + /// AccessesArgumentsReadonly - This function loads through function + /// arguments and does not perform any non-local stores or volatile + /// loads. + /// + /// This property corresponds to the IntrReadArgMem LLVM intrinsic flag. AccessesArgumentsReadonly, - // AccessesArguments - This function accesses function arguments in well - // known (possibly volatile) ways, but does not access any other memory. - // - // This property corresponds to the IntrReadWriteArgMem LLVM intrinsic flag. + /// AccessesArguments - This function accesses function arguments in well + /// known (possibly volatile) ways, but does not access any other memory. + /// + /// This property corresponds to the IntrReadWriteArgMem LLVM intrinsic flag. AccessesArguments, - // OnlyReadsMemory - This function does not perform any non-local stores or - // volatile loads, but may read from any memory location. - // - // This property corresponds to the GCC 'pure' attribute. - // This property corresponds to the LLVM IR 'readonly' attribute. - // This property corresponds to the IntrReadMem LLVM intrinsic flag. + /// OnlyReadsMemory - This function does not perform any non-local stores or + /// volatile loads, but may read from any memory location. + /// + /// This property corresponds to the GCC 'pure' attribute. + /// This property corresponds to the LLVM IR 'readonly' attribute. + /// This property corresponds to the IntrReadMem LLVM intrinsic flag. OnlyReadsMemory, - // UnknownModRefBehavior - This indicates that the function could not be - // classified into one of the behaviors above. + /// UnknownModRefBehavior - This indicates that the function could not be + /// classified into one of the behaviors above. UnknownModRefBehavior }; From rafael.espindola at gmail.com Tue Nov 9 15:03:48 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 16:03:48 -0500 Subject: [llvm-commits] [PATCH] ARM/MC/ELF Relocation Stubs/Refactoring In-Reply-To: References: Message-ID: > The rationale for these is to support the various non-simple (i.e. not > just a 32/64bit sequential blob) - relocation types mandated by the > ARM architecture manual. There are over 100 of these relocation types, > and selecting the actual ELF32_R_TYPE() field depends on the actual > instruction sequence - and the most obvious way to do this is to > examine the ELFSection& object directly. Are they used? I am sure we haven't implement all the x86 relocations, but elf writer is already fairly functional there. I would suggest doing this one relocation at a time. And start with the simple ones :-) For example, first add support for a function that just calls an external one: ------ f: bl g ------ Also, if only ARM needs support for fancier relocations, we should try to avoid modifying other targets. > Thanks! > -jason > Cheers, Rafael From atrick at apple.com Tue Nov 9 15:04:34 2010 From: atrick at apple.com (Andrew Trick) Date: Tue, 09 Nov 2010 21:04:34 -0000 Subject: [llvm-commits] [llvm] r118630 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp Message-ID: <20101109210434.5162D2A6C12C@llvm.org> Author: atrick Date: Tue Nov 9 15:04:34 2010 New Revision: 118630 URL: http://llvm.org/viewvc/llvm-project?rev=118630&view=rev Log: Adds RABasic verification and tracing. (retry now that the windows build is green) Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=118630&r1=118629&r2=118630&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Nov 9 15:04:34 2010 @@ -15,6 +15,7 @@ #define DEBUG_TYPE "regalloc" #include "LiveIntervalUnion.h" +#include "llvm/ADT/SparseBitVector.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include @@ -73,12 +74,10 @@ #ifndef NDEBUG // check for overlap (inductively) if (segPos != segments_.begin()) { - SegmentIter prevPos = segPos; - --prevPos; - assert(prevPos->end <= segment.start && "overlapping segments" ); + assert(llvm::prior(segPos)->end <= segment.start && + "overlapping segments" ); } - SegmentIter nextPos = segPos; - ++nextPos; + SegmentIter nextPos = llvm::next(segPos); if (nextPos != segments_.end()) assert(segment.end <= nextPos->start && "overlapping segments" ); #endif // NDEBUG @@ -98,6 +97,49 @@ } } +raw_ostream& llvm::operator<<(raw_ostream& os, const LiveSegment &ls) { + return os << '[' << ls.start << ',' << ls.end << ':' << + ls.liveVirtReg->reg << ")"; +} + +void LiveSegment::dump() const { + dbgs() << *this << "\n"; +} + +void +LiveIntervalUnion::print(raw_ostream &os, + const AbstractRegisterDescription *rdesc) const { + os << "LIU "; + if (rdesc != NULL) + os << rdesc->getName(repReg_); + else { + os << repReg_; + } + for (LiveSegments::const_iterator segI = segments_.begin(), + segEnd = segments_.end(); segI != segEnd; ++segI) { + dbgs() << " " << *segI; + } + os << "\n"; +} + +void LiveIntervalUnion::dump(const AbstractRegisterDescription *rdesc) const { + print(dbgs(), rdesc); +} + +#ifndef NDEBUG +// Verify the live intervals in this union and add them to the visited set. +void LiveIntervalUnion::verify(LvrBitSet& visitedVRegs) { + SegmentIter segI = segments_.begin(); + SegmentIter segEnd = segments_.end(); + if (segI == segEnd) return; + visitedVRegs.set(segI->liveVirtReg->reg); + for (++segI; segI != segEnd; ++segI) { + visitedVRegs.set(segI->liveVirtReg->reg); + assert(llvm::prior(segI)->end <= segI->start && "overlapping segments" ); + } +} +#endif //!NDEBUG + // Private interface accessed by Query. // // Find a pair of segments that intersect, one in the live virtual register Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118630&r1=118629&r2=118630&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Nov 9 15:04:34 2010 @@ -23,6 +23,12 @@ namespace llvm { +#ifndef NDEBUG +// forward declaration +template class SparseBitVector; +typedef SparseBitVector<128> LvrBitSet; +#endif + /// A LiveSegment is a copy of a LiveRange object used within /// LiveIntervalUnion. LiveSegment additionally contains a pointer to its /// original live virtual register (LiveInterval). This allows quick lookup of @@ -51,6 +57,9 @@ // Order segments by starting point only--we expect them to be disjoint. bool operator<(const LiveSegment &ls) const { return start < ls.start; } + + void dump() const; + void print(raw_ostream &os) const; }; inline bool operator<(SlotIndex V, const LiveSegment &ls) { @@ -74,9 +83,9 @@ class AbstractRegisterDescription { public: virtual const char *getName(unsigned reg) const = 0; - virtual ~AbstractRegisterDescription() { } + virtual ~AbstractRegisterDescription() {} }; - + /// Union of live intervals that are strong candidates for coalescing into a /// single register (either physical or virtual depending on the context). We /// expect the constituent live intervals to be disjoint, although we may @@ -133,6 +142,16 @@ // Remove a live virtual register's segments from this union. void extract(const LiveInterval &lvr); + void dump(const AbstractRegisterDescription *regInfo) const; + + // If tri != NULL, use it to decode repReg_ + void print(raw_ostream &os, const AbstractRegisterDescription *rdesc) const; + +#ifndef NDEBUG + // Verify the live intervals in this union and add them to the visited set. + void verify(LvrBitSet& visitedVRegs); +#endif + /// Cache a single interference test result in the form of two intersecting /// segments. This allows efficiently iterating over the interferences. The /// iteration logic is handled by LiveIntervalUnion::Query which may Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=118630&r1=118629&r2=118630&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Tue Nov 9 15:04:34 2010 @@ -128,6 +128,11 @@ // exists, return the interfering register, which may be preg or an alias. unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg); +#ifndef NDEBUG + // Verify each LiveIntervalUnion. + void verify(); +#endif + // Helper that spills all live virtual registers currently unified under preg // that interfere with the most recently queried lvr. void spillInterferences(unsigned preg, Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118630&r1=118629&r2=118630&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Nov 9 15:04:34 2010 @@ -34,6 +34,9 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" +#ifndef NDEBUG +#include "llvm/ADT/SparseBitVector.h" +#endif #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -46,6 +49,19 @@ static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator); +// Temporary verification option until we can put verification inside +// MachineVerifier. +static cl::opt +VerifyRegAlloc("verify-regalloc", + cl::desc("Verify live intervals before renaming")); + +class PhysicalRegisterDescription : public AbstractRegisterDescription { + const TargetRegisterInfo *tri_; +public: + PhysicalRegisterDescription(const TargetRegisterInfo *tri): tri_(tri) {} + virtual const char *getName(unsigned reg) const { return tri_->getName(reg); } +}; + namespace { /// RABasic provides a minimal implementation of the basic register allocation @@ -153,6 +169,40 @@ RegAllocBase::releaseMemory(); } +#ifndef NDEBUG +// Verify each LiveIntervalUnion. +void RegAllocBase::verify() { + LvrBitSet visitedVRegs; + OwningArrayPtr unionVRegs(new LvrBitSet[physReg2liu_.numRegs()]); + // Verify disjoint unions. + for (unsigned preg = 0; preg < physReg2liu_.numRegs(); ++preg) { + DEBUG(PhysicalRegisterDescription prd(tri_); physReg2liu_[preg].dump(&prd)); + LvrBitSet &vregs = unionVRegs[preg]; + physReg2liu_[preg].verify(vregs); + // Union + intersection test could be done efficiently in one pass, but + // don't add a method to SparseBitVector unless we really need it. + assert(!visitedVRegs.intersects(vregs) && "vreg in multiple unions"); + visitedVRegs |= vregs; + } + // Verify vreg coverage. + for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end(); + liItr != liEnd; ++liItr) { + unsigned reg = liItr->first; + LiveInterval &li = *liItr->second; + if (li.empty() ) continue; + if (TargetRegisterInfo::isPhysicalRegister(reg)) continue; + if (!vrm_->hasPhys(reg)) continue; // spilled? + unsigned preg = vrm_->getPhys(reg); + if (!unionVRegs[preg].test(reg)) { + dbgs() << "LiveVirtReg " << reg << " not in union " << + tri_->getName(preg) << "\n"; + llvm_unreachable("unallocated live vreg"); + } + } + // FIXME: I'm not sure how to verify spilled intervals. +} +#endif //!NDEBUG + //===----------------------------------------------------------------------===// // RegAllocBase Implementation //===----------------------------------------------------------------------===// @@ -222,6 +272,7 @@ liItr != liEnd; ++liItr) { unsigned reg = liItr->first; LiveInterval &li = *liItr->second; + if (li.empty()) continue; if (TargetRegisterInfo::isPhysicalRegister(reg)) { physReg2liu_[reg].unify(li); } @@ -243,13 +294,14 @@ unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs); if (availablePhysReg) { DEBUG(dbgs() << "allocating: " << tri_->getName(availablePhysReg) << - " " << lvr << '\n'); + " " << *lvr << '\n'); assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions"); vrm_->assignVirt2Phys(lvr->reg, availablePhysReg); physReg2liu_[availablePhysReg].unify(*lvr); } for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end(); lvrI != lvrEnd; ++lvrI) { + if ((*lvrI)->empty()) continue; DEBUG(dbgs() << "queuing new interval: " << **lvrI << "\n"); assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) && "expect split value in virtual register"); @@ -274,26 +326,32 @@ return 0; } -// Spill all live virtual registers currently unified under preg that interfere -// with lvr. +// Spill or split all live virtual registers currently unified under preg that +// interfere with lvr. The newly spilled or split live intervals are returned by +// appending them to splitLVRs. void RABasic::spillInterferences(unsigned preg, SmallVectorImpl &splitLVRs) { SmallPtrSet spilledLVRs; LiveIntervalUnion::Query &query = queries_[preg]; + // Record each interference before mutating either the union or live + // intervals. LiveIntervalUnion::InterferenceResult ir = query.firstInterference(); assert(query.isInterference(ir) && "expect interference"); do { - LiveInterval *lvr = ir.liuSegPos()->liveVirtReg; - if (!spilledLVRs.insert(lvr)) continue; - // Spill the previously allocated lvr. - SmallVector spillIs; // ignored - spiller_->spill(lvr, splitLVRs, spillIs); + spilledLVRs.insert(ir.liuSegPos()->liveVirtReg); } while (query.nextInterference(ir)); for (SmallPtrSetIterator lvrI = spilledLVRs.begin(), lvrEnd = spilledLVRs.end(); lvrI != lvrEnd; ++lvrI ) { + LiveInterval& lvr = **lvrI; + // Spill the previously allocated lvr. + DEBUG(dbgs() << "extracting from " << preg << " " << lvr << '\n'); // Deallocate the interfering lvr by removing it from the preg union. - physReg2liu_[preg].extract(**lvrI); + // Live intervals may not be in a union during modification. + physReg2liu_[preg].extract(lvr); + // Spill the extracted interval. + SmallVector spillIs; + spiller_->spill(&lvr, splitLVRs, spillIs); } // After extracting segments, the query's results are invalid. query.clear(); @@ -399,6 +457,24 @@ // optional HTML output DEBUG(rmf_->renderMachineFunction("After basic register allocation.", vrm_)); + // FIXME: Verification currently must run before VirtRegRewriter. We should + // make the rewriter a separate pass and override verifyAnalysis instead. When + // that happens, verification naturally falls under VerifyMachineCode. +#ifndef NDEBUG + if (VerifyRegAlloc) { + // Verify accuracy of LiveIntervals. The standard machine code verifier + // ensures that each LiveIntervals covers all uses of the virtual reg. + + // FIXME: MachineVerifier is currently broken when using the standard + // spiller. Enable it for InlineSpiller only. + // mf_->verify(this); + + // Verify that LiveIntervals are partitioned into unions and disjoint within + // the unions. + verify(); + } +#endif // !NDEBUG + // Run rewriter std::auto_ptr rewriter(createVirtRegRewriter()); rewriter->runOnMachineFunction(*mf_, *vrm_, lis_); From rafael.espindola at gmail.com Tue Nov 9 15:07:48 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 16:07:48 -0500 Subject: [llvm-commits] [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: <20101108164727.39B812A6C12C@llvm.org> References: <20101108164727.39B812A6C12C@llvm.org> Message-ID: > + ? ? ?R_ARM_THM_CALL ? ? ? ? ? ? ?= 0x0a, The names don't match what I have on a linux system. For example #define R_ARM_THM_PC22 10 Are there two independent naming conventions for ARM relocations? Cheers, Rafael From rafael.espindola at gmail.com Tue Nov 9 15:11:16 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Tue, 9 Nov 2010 16:11:16 -0500 Subject: [llvm-commits] [llvm] r118422 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBuildAttrs.h test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll In-Reply-To: <20101108175807.8543A2A6C12C@llvm.org> References: <20101108175807.8543A2A6C12C@llvm.org> Message-ID: > + ? ?virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0; This is wrong. The purpose of this class is to represent the low level attributes. Something like a ".cpu" is *not* an attribute, it is an alias that produces many of them. Cheers, Rafael From grosbach at apple.com Tue Nov 9 15:36:17 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 09 Nov 2010 21:36:17 -0000 Subject: [llvm-commits] [llvm] r118633 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMConstantPoolValue.cpp ARMConstantPoolValue.h ARMISelLowering.cpp Message-ID: <20101109213617.E42B72A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 15:36:17 2010 New Revision: 118633 URL: http://llvm.org/viewvc/llvm-project?rev=118633&view=rev Log: Change the ARMConstantPoolValue modifier string to an enumeration. This will help in MC'izing the references that use them. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118633&r1=118632&r2=118633&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Nov 9 15:36:17 2010 @@ -647,7 +647,7 @@ // FIXME: Model the whole expression an an MCExpr and we can get rid // of this hasRawTextSupport() clause and just do an EmitValue(). if (OutStreamer.hasRawTextSupport()) { - if (ACPV->hasModifier()) OS << "(" << ACPV->getModifier() << ")"; + if (ACPV->hasModifier()) OS << "(" << ACPV->getModifierText() << ")"; if (ACPV->getPCAdjustment() != 0) { OS << "-(" << MAI->getPrivateGlobalPrefix() << "PC" << getFunctionNumber() << "_" << ACPV->getLabelId() Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp?rev=118633&r1=118632&r2=118633&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp Tue Nov 9 15:36:17 2010 @@ -24,7 +24,7 @@ ARMConstantPoolValue::ARMConstantPoolValue(const Constant *cval, unsigned id, ARMCP::ARMCPKind K, unsigned char PCAdj, - const char *Modif, + ARMCP::ARMCPModifier Modif, bool AddCA) : MachineConstantPoolValue((const Type*)cval->getType()), CVal(cval), S(NULL), LabelId(id), Kind(K), PCAdjust(PCAdj), @@ -33,14 +33,14 @@ ARMConstantPoolValue::ARMConstantPoolValue(LLVMContext &C, const char *s, unsigned id, unsigned char PCAdj, - const char *Modif, + ARMCP::ARMCPModifier Modif, bool AddCA) : MachineConstantPoolValue((const Type*)Type::getInt32Ty(C)), CVal(NULL), S(strdup(s)), LabelId(id), Kind(ARMCP::CPExtSymbol), PCAdjust(PCAdj), Modifier(Modif), AddCurrentAddress(AddCA) {} ARMConstantPoolValue::ARMConstantPoolValue(const GlobalValue *gv, - const char *Modif) + ARMCP::ARMCPModifier Modif) : MachineConstantPoolValue((const Type*)Type::getInt32Ty(gv->getContext())), CVal(gv), S(NULL), LabelId(0), Kind(ARMCP::CPValue), PCAdjust(0), Modifier(Modif) {} @@ -74,7 +74,7 @@ CPV->LabelId == LabelId && CPV->PCAdjust == PCAdjust && CPV_streq(CPV->S, S) && - CPV_streq(CPV->Modifier, Modifier)) + CPV->Modifier == Modifier) return i; } } @@ -100,7 +100,7 @@ ACPV->CVal == CVal && ACPV->PCAdjust == PCAdjust && CPV_streq(ACPV->S, S) && - CPV_streq(ACPV->Modifier, Modifier)) { + ACPV->Modifier == Modifier) { if (ACPV->LabelId == LabelId) return true; // Two PC relative constpool entries containing the same GV address or @@ -121,7 +121,7 @@ O << CVal->getName(); else O << S; - if (Modifier) O << "(" << Modifier << ")"; + if (Modifier) O << "(" << getModifierText() << ")"; if (PCAdjust != 0) { O << "-(LPC" << LabelId << "+" << (unsigned)PCAdjust; if (AddCurrentAddress) O << "-."; Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h?rev=118633&r1=118632&r2=118633&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Tue Nov 9 15:36:17 2010 @@ -15,6 +15,7 @@ #define LLVM_TARGET_ARM_CONSTANTPOOLVALUE_H #include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/Support/ErrorHandling.h" #include namespace llvm { @@ -31,6 +32,15 @@ CPBlockAddress, CPLSDA }; + + enum ARMCPModifier { + no_modifier, + TLSGD, + GOT, + GOTOFF, + GOTTPOFF, + TPOFF + }; } /// ARMConstantPoolValue - ARM specific constantpool value. This is used to @@ -43,26 +53,41 @@ ARMCP::ARMCPKind Kind; // Kind of constant. unsigned char PCAdjust; // Extra adjustment if constantpool is pc-relative. // 8 for ARM, 4 for Thumb. - const char *Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8)) + ARMCP::ARMCPModifier Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8)) bool AddCurrentAddress; public: ARMConstantPoolValue(const Constant *cval, unsigned id, ARMCP::ARMCPKind Kind = ARMCP::CPValue, - unsigned char PCAdj = 0, const char *Modifier = NULL, + unsigned char PCAdj = 0, + ARMCP::ARMCPModifier Modifier = ARMCP::no_modifier, bool AddCurrentAddress = false); ARMConstantPoolValue(LLVMContext &C, const char *s, unsigned id, - unsigned char PCAdj = 0, const char *Modifier = NULL, + unsigned char PCAdj = 0, + ARMCP::ARMCPModifier Modifier = ARMCP::no_modifier, bool AddCurrentAddress = false); - ARMConstantPoolValue(const GlobalValue *GV, const char *Modifier); + ARMConstantPoolValue(const GlobalValue *GV, ARMCP::ARMCPModifier Modifier); ARMConstantPoolValue(); ~ARMConstantPoolValue(); const GlobalValue *getGV() const; const char *getSymbol() const { return S; } const BlockAddress *getBlockAddress() const; - const char *getModifier() const { return Modifier; } - bool hasModifier() const { return Modifier != NULL; } + ARMCP::ARMCPModifier getModifier() const { return Modifier; } + const char *getModifierText() const { + switch (Modifier) { + default: llvm_unreachable("Unknown modifier!"); + // FIXME: Are these case sensitive? It'd be nice to lower-case all the + // strings if that's legal. + case ARMCP::no_modifier: return "none"; + case ARMCP::TLSGD: return "tlsgd"; + case ARMCP::GOT: return "GOT"; + case ARMCP::GOTOFF: return "GOTOFF"; + case ARMCP::GOTTPOFF: return "gottpoff"; + case ARMCP::TPOFF: return "tpoff"; + } + } + bool hasModifier() const { return Modifier != ARMCP::no_modifier; } bool mustAddCurrentAddress() const { return AddCurrentAddress; } unsigned getLabelId() const { return LabelId; } unsigned char getPCAdjustment() const { return PCAdjust; } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118633&r1=118632&r2=118633&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 9 15:36:17 2010 @@ -1781,7 +1781,7 @@ unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, - ARMCP::CPValue, PCAdj, "tlsgd", true); + ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, @@ -1828,7 +1828,7 @@ unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, - ARMCP::CPValue, PCAdj, "gottpoff", true); + ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, @@ -1844,7 +1844,7 @@ false, false, 0); } else { // local exec model - ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff"); + ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, @@ -1880,7 +1880,7 @@ if (RelocM == Reloc::PIC_) { bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); ARMConstantPoolValue *CPV = - new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT"); + new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), From bigcheesegs at gmail.com Tue Nov 9 16:13:00 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 9 Nov 2010 17:13:00 -0500 Subject: [llvm-commits] [PATCH][System/Path] Update comments to match code. In-Reply-To: References: Message-ID: 2010/11/9 Rafael Esp?ndola : > On 8 November 2010 20:49, Michael Spencer wrote: >> Neither the Unix or Windows implementation include >> LLVM_LIB_SEARCH_PATH. I'm assuming the comments are wrong. Just making >> sure it's not the code that is wrong. > > Probably a cut and paste error,GetBitcodeLibraryPaths uses that variable. > The only indirect user I can find is in llvm-ld. Maybe we could move > this stuff there? I think it's fine where it is for the bitcode. If anyone else uses it in the future it would be better for LLVM_LIB_SEARCH_PATH to work correctly. I'll update the comment for the system libs. - Michael Spencer >> Also, the Windows implementation is completely wrong on a multitude of >> levels. It should be using SHGetFolderPath instead of hard coding >> C:\Windows, and none of those directories contain any libraries that >> are actually used on modern Windows. >> >> What is the actual purpose of this function? To get libraries for link >> time or runtime? If it's for link time then what we really want is the >> platform sdk and MSVC directories, or something else on MinGW. If it's >> for runtime then... well... take your pick. There are quite a few >> directories depending on the OS version, Architecture, etc... And then >> there's MinGW. >> >> - Michael Spencer > > > Cheers, > Rafael > From rafael.espindola at gmail.com Tue Nov 9 16:37:44 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 09 Nov 2010 22:37:44 -0000 Subject: [llvm-commits] [llvm] r118639 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCSectionELF.h lib/MC/ELFObjectWriter.cpp lib/MC/MCContext.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCSectionELF.cpp Message-ID: <20101109223744.D4B022A6C12D@llvm.org> Author: rafael Date: Tue Nov 9 16:37:44 2010 New Revision: 118639 URL: http://llvm.org/viewvc/llvm-project?rev=118639&view=rev Log: Remove IsExplicit. It was always false. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCSectionELF.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/MCSectionELF.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=118639&r1=118638&r2=118639&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Nov 9 16:37:44 2010 @@ -140,7 +140,6 @@ const MCSection *getELFSection(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind, - bool IsExplicit = false, unsigned EntrySize = 0); const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics, Modified: llvm/trunk/include/llvm/MC/MCSectionELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionELF.h?rev=118639&r1=118638&r2=118639&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionELF.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionELF.h Tue Nov 9 16:37:44 2010 @@ -32,10 +32,6 @@ /// below. unsigned Flags; - /// IsExplicit - Indicates that this section comes from globals with an - /// explicit section specified. - bool IsExplicit; - /// EntrySize - The size of each entry in this section. This size only /// makes sense for sections that contain fixed-sized entries. If a /// section does not contain fixed-sized entries 'EntrySize' will be 0. @@ -44,9 +40,9 @@ private: friend class MCContext; MCSectionELF(StringRef Section, unsigned type, unsigned flags, - SectionKind K, bool isExplicit, unsigned entrySize) + SectionKind K, unsigned entrySize) : MCSection(SV_ELF, K), SectionName(Section), Type(type), Flags(flags), - IsExplicit(isExplicit), EntrySize(entrySize) {} + EntrySize(entrySize) {} ~MCSectionELF(); public: @@ -54,9 +50,6 @@ /// should be printed before the section name bool ShouldOmitSectionDirective(StringRef Name, const MCAsmInfo &MAI) const; - /// ShouldPrintSectionType - Only prints the section type if supported - bool ShouldPrintSectionType(unsigned Ty) const; - /// HasCommonSymbols - True if this section holds common symbols, this is /// indicated on the ELF object file by a symbol with SHN_COMMON section /// header index. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118639&r1=118638&r2=118639&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Nov 9 16:37:44 2010 @@ -1065,7 +1065,7 @@ RelaSection = Ctx.getELFSection(RelaSectionName, HasRelocationAddend ? ELF::SHT_RELA : ELF::SHT_REL, 0, SectionKind::getReadOnly(), - false, EntrySize); + EntrySize); MCSectionData &RelaSD = Asm.getOrCreateSectionData(*RelaSection); RelaSD.setAlignment(Is64Bit ? 8 : 4); @@ -1164,7 +1164,7 @@ const MCSection *SymtabSection = Ctx.getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), - false, EntrySize); + EntrySize); MCSectionData &SymtabSD = Asm.getOrCreateSectionData(*SymtabSection); SymtabSD.setAlignment(Is64Bit ? 8 : 4); SymbolTableIndex = Asm.size(); @@ -1174,7 +1174,7 @@ if (NeedsSymtabShndx) { const MCSection *SymtabShndxSection = Ctx.getELFSection(".symtab_shndx", ELF::SHT_SYMTAB_SHNDX, 0, - SectionKind::getReadOnly(), false, 4); + SectionKind::getReadOnly(), 4); SymtabShndxSD = &Asm.getOrCreateSectionData(*SymtabShndxSection); SymtabShndxSD->setAlignment(4); } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=118639&r1=118638&r2=118639&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Nov 9 16:37:44 2010 @@ -151,7 +151,7 @@ const MCSection *MCContext:: getELFSection(StringRef Section, unsigned Type, unsigned Flags, - SectionKind Kind, bool IsExplicit, unsigned EntrySize) { + SectionKind Kind, unsigned EntrySize) { if (ELFUniquingMap == 0) ELFUniquingMap = new ELFUniqueMapTy(); ELFUniqueMapTy &Map = *(ELFUniqueMapTy*)ELFUniquingMap; @@ -165,7 +165,7 @@ EntrySize = MCSectionELF::DetermineEntrySize(Kind); } MCSectionELF *Result = new (*this) MCSectionELF(Entry.getKey(), Type, Flags, - Kind, IsExplicit, EntrySize); + Kind, EntrySize); Entry.setValue(Result); return Result; } Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=118639&r1=118638&r2=118639&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Tue Nov 9 16:37:44 2010 @@ -331,8 +331,7 @@ ? SectionKind::getText() : SectionKind::getDataRel(); getStreamer().SwitchSection(getContext().getELFSection(SectionName, Type, - Flags, Kind, false, - Size)); + Flags, Kind, Size)); return false; } @@ -406,7 +405,7 @@ MCSectionELF::SHF_MERGE | MCSectionELF::SHF_STRINGS, SectionKind::getReadOnly(), - false, 1); + 1); static bool First = true; Modified: llvm/trunk/lib/MC/MCSectionELF.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSectionELF.cpp?rev=118639&r1=118638&r2=118639&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSectionELF.cpp (original) +++ llvm/trunk/lib/MC/MCSectionELF.cpp Tue Nov 9 16:37:44 2010 @@ -29,14 +29,6 @@ return false; } -// ShouldPrintSectionType - Only prints the section type if supported -bool MCSectionELF::ShouldPrintSectionType(unsigned Ty) const { - if (IsExplicit && !(Ty == SHT_NOBITS || Ty == SHT_PROGBITS)) - return false; - - return true; -} - void MCSectionELF::PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const { @@ -84,31 +76,29 @@ OS << '"'; - if (ShouldPrintSectionType(Type)) { - OS << ','; - - // If comment string is '@', e.g. as on ARM - use '%' instead - if (MAI.getCommentString()[0] == '@') - OS << '%'; - else - OS << '@'; - - if (Type == MCSectionELF::SHT_INIT_ARRAY) - OS << "init_array"; - else if (Type == MCSectionELF::SHT_FINI_ARRAY) - OS << "fini_array"; - else if (Type == MCSectionELF::SHT_PREINIT_ARRAY) - OS << "preinit_array"; - else if (Type == MCSectionELF::SHT_NOBITS) - OS << "nobits"; - else if (Type == MCSectionELF::SHT_PROGBITS) - OS << "progbits"; - - if (EntrySize) { - OS << "," << EntrySize; - } + OS << ','; + + // If comment string is '@', e.g. as on ARM - use '%' instead + if (MAI.getCommentString()[0] == '@') + OS << '%'; + else + OS << '@'; + + if (Type == MCSectionELF::SHT_INIT_ARRAY) + OS << "init_array"; + else if (Type == MCSectionELF::SHT_FINI_ARRAY) + OS << "fini_array"; + else if (Type == MCSectionELF::SHT_PREINIT_ARRAY) + OS << "preinit_array"; + else if (Type == MCSectionELF::SHT_NOBITS) + OS << "nobits"; + else if (Type == MCSectionELF::SHT_PROGBITS) + OS << "progbits"; + + if (EntrySize) { + OS << "," << EntrySize; } - + OS << '\n'; } From isanbard at gmail.com Tue Nov 9 16:44:22 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 09 Nov 2010 22:44:22 -0000 Subject: [llvm-commits] [llvm] r118640 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101109224422.878C42A6C12D@llvm.org> Author: void Date: Tue Nov 9 16:44:22 2010 New Revision: 118640 URL: http://llvm.org/viewvc/llvm-project?rev=118640&view=rev Log: Two types of instructions have register lists: * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118640&r1=118639&r2=118640&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 16:44:22 2010 @@ -128,8 +128,7 @@ } Reg; struct { - unsigned RegStart; - unsigned Number; + std::vector *Registers; } RegList; struct { @@ -196,18 +195,13 @@ } unsigned getReg() const { - assert((Kind == Register || Kind == RegisterList) && "Invalid access!"); - unsigned RegNum = 0; - if (Kind == Register) - RegNum = Reg.RegNum; - else - RegNum = RegList.RegStart; - return RegNum; + assert(Kind == Register && "Invalid access!"); + return Reg.RegNum; } - std::pair getRegList() const { + const std::vector &getRegList() const { assert(Kind == RegisterList && "Invalid access!"); - return std::make_pair(RegList.RegStart, RegList.Number); + return *RegList.Registers; } const MCExpr *getImm() const { @@ -259,10 +253,11 @@ } void addRegListOperands(MCInst &Inst, unsigned N) const { - assert(N == 2 && "Invalid number of operands!"); - std::pair RegList = getRegList(); - Inst.addOperand(MCOperand::CreateReg(RegList.first)); - Inst.addOperand(MCOperand::CreateImm(RegList.second)); + assert(N == 1 && "Invalid number of operands!"); + const std::vector &RegList = getRegList(); + for (std::vector::const_iterator + I = RegList.begin(), E = RegList.end(); I != E; ++I) + Inst.addOperand(MCOperand::CreateReg(*I)); } void addImmOperands(MCInst &Inst, unsigned N) const { @@ -325,11 +320,15 @@ return Op; } - static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number, - SMLoc S, SMLoc E) { + static ARMOperand * + CreateRegList(std::vector > &Regs, + SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(RegisterList); - Op->RegList.RegStart = RegStart; - Op->RegList.Number = Number; + Op->RegList.Registers = new std::vector(); + for (std::vector >::iterator + I = Regs.begin(), E = Regs.end(); I != E; ++I) + Op->RegList.Registers->push_back(I->first); + std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end()); Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -386,12 +385,12 @@ break; case RegisterList: { OS << " List = getRegList(); - unsigned RegEnd = List.first + List.second; - for (unsigned Idx = List.first; Idx < RegEnd; ) { - OS << Idx; - if (++Idx < RegEnd) OS << ", "; + const std::vector &RegList = getRegList(); + for (std::vector::const_iterator + I = RegList.begin(), E = RegList.end(); I != E; ) { + OS << *I; + if (++I < E) OS << ", "; } OS << ">"; @@ -459,30 +458,15 @@ assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Curly Brace"); SMLoc S = Parser.getTok().getLoc(); - Parser.Lex(); // Eat left curly brace token. - - const AsmToken &RegTok = Parser.getTok(); - SMLoc RegLoc = RegTok.getLoc(); - if (RegTok.isNot(AsmToken::Identifier)) { - Error(RegLoc, "register expected"); - return 0; - } - - int RegNum = TryParseRegister(); - if (RegNum == -1) { - Error(RegLoc, "register expected"); - return 0; - } - unsigned PrevRegNum = RegNum; + // Read the rest of the registers in the list. + unsigned PrevRegNum = 0; std::vector > Registers; Registers.reserve(32); - Registers.push_back(std::make_pair(RegNum, RegLoc)); - while (Parser.getTok().is(AsmToken::Comma) || - Parser.getTok().is(AsmToken::Minus)) { + do { bool IsRange = Parser.getTok().is(AsmToken::Minus); - Parser.Lex(); // Eat comma or minus token. + Parser.Lex(); // Eat non-identifier token. const AsmToken &RegTok = Parser.getTok(); SMLoc RegLoc = RegTok.getLoc(); @@ -508,7 +492,8 @@ } PrevRegNum = RegNum; - } + } while (Parser.getTok().is(AsmToken::Comma) || + Parser.getTok().is(AsmToken::Minus)); // Process the right curly brace of the list. const AsmToken &RCurlyTok = Parser.getTok(); @@ -521,18 +506,15 @@ Parser.Lex(); // Eat right curly brace token. // Verify the register list. - std::vector >::iterator + std::vector >::const_iterator RI = Registers.begin(), RE = Registers.end(); - unsigned Number = Registers.size(); unsigned HighRegNum = RI->first; - unsigned RegStart = RI->first; - DenseMap RegMap; RegMap[RI->first] = true; for (++RI; RI != RE; ++RI) { - std::pair &RegInfo = *RI; + const std::pair &RegInfo = *RI; if (RegMap[RegInfo.first]) { Error(RegInfo.second, "register duplicated in register list"); @@ -545,15 +527,9 @@ RegMap[RegInfo.first] = true; HighRegNum = std::max(RegInfo.first, HighRegNum); - RegStart = std::min(RegInfo.first, RegStart); - } - - if (RegStart + Number - 1 != HighRegNum) { - Error(RegLoc, "non-contiguous register range"); - return 0; } - return ARMOperand::CreateRegList(RegStart, Number, S, E); + return ARMOperand::CreateRegList(Registers, S, E); } /// Parse an ARM memory expression, return false if successful else return true From bob.wilson at apple.com Tue Nov 9 16:50:44 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 09 Nov 2010 22:50:44 -0000 Subject: [llvm-commits] [llvm] r118642 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/Thumb/barrier.ll Message-ID: <20101109225044.9D5592A6C12D@llvm.org> Author: bwilson Date: Tue Nov 9 16:50:44 2010 New Revision: 118642 URL: http://llvm.org/viewvc/llvm-project?rev=118642&view=rev Log: Do not use MEMBARRIER_MCR for any Thumb code. It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/Thumb/barrier.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118642&r1=118641&r2=118642&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 9 16:50:44 2010 @@ -553,7 +553,7 @@ // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use // the default expansion. if (Subtarget->hasDataBarrier() || - (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) { + (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { // membarrier needs custom lowering; the rest are legal and handled // normally. setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); @@ -2040,7 +2040,7 @@ // Some ARMv6 cpus can support data barriers with an mcr instruction. // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get // here. - assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() && + assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), DAG.getConstant(0, MVT::i32)); Modified: llvm/trunk/test/CodeGen/Thumb/barrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/barrier.ll?rev=118642&r1=118641&r2=118642&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/barrier.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/barrier.ll Tue Nov 9 16:50:44 2010 @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6 ; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) From bob.wilson at apple.com Tue Nov 9 16:50:48 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 09 Nov 2010 22:50:48 -0000 Subject: [llvm-commits] [llvm] r118643 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Message-ID: <20101109225048.1724E2A6C12F@llvm.org> Author: bwilson Date: Tue Nov 9 16:50:47 2010 New Revision: 118643 URL: http://llvm.org/viewvc/llvm-project?rev=118643&view=rev Log: Define the subtarget feature for the architecture version, as derived from the target triple. This is important for enabling features that are implied based on the architecture version. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=118643&r1=118642&r2=118643&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Nov 9 16:50:47 2010 @@ -64,13 +64,13 @@ // Determine default and user specified characteristics - // Parse features string. - CPUString = ParseSubtargetFeatures(FS, CPUString); - // When no arch is specified either by CPU or by attributes, make the default // ARMv4T. - if (CPUString == "generic" && (FS.empty() || FS == "generic")) + const char *ARMArchFeature = ""; + if (CPUString == "generic" && (FS.empty() || FS == "generic")) { ARMArchVersion = V4T; + ARMArchFeature = ",+v4t"; + } // Set the boolean corresponding to the current target triple, or the default // if one cannot be determined, to true. @@ -88,30 +88,36 @@ unsigned SubVer = TT[Idx]; if (SubVer >= '7' && SubVer <= '9') { ARMArchVersion = V7A; - if (Len >= Idx+2 && TT[Idx+1] == 'm') + ARMArchFeature = ",+v7a"; + if (Len >= Idx+2 && TT[Idx+1] == 'm') { ARMArchVersion = V7M; + ARMArchFeature = ",+v7m"; + } } else if (SubVer == '6') { ARMArchVersion = V6; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') + ARMArchFeature = ",+v6"; + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { ARMArchVersion = V6T2; + ARMArchFeature = ",+v6t2"; + } } else if (SubVer == '5') { ARMArchVersion = V5T; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') + ARMArchFeature = ",+v5t"; + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { ARMArchVersion = V5TE; + ARMArchFeature = ",+v5te"; + } } else if (SubVer == '4') { - if (Len >= Idx+2 && TT[Idx+1] == 't') + if (Len >= Idx+2 && TT[Idx+1] == 't') { ARMArchVersion = V4T; - else + ARMArchFeature = ",+v4t"; + } else { ARMArchVersion = V4; + ARMArchFeature = ""; + } } } - // Thumb2 implies at least V6T2. - if (ARMArchVersion >= V6T2) - ThumbMode = Thumb2; - else if (ThumbMode >= Thumb2) - ARMArchVersion = V6T2; - if (Len >= 10) { if (TT.find("-darwin") != std::string::npos) // arm-darwin @@ -121,6 +127,25 @@ if (TT.find("eabi") != std::string::npos) TargetABI = ARM_ABI_AAPCS; + // Parse features string. If the first entry in FS (the CPU) is missing, + // insert the architecture feature derived from the target triple. This is + // important for setting features that are implied based on the architecture + // version. + std::string FSWithArch; + if (FS.empty()) + FSWithArch = std::string(ARMArchFeature); + else if (FS.find(',') == 0) + FSWithArch = std::string(ARMArchFeature) + FS; + else + FSWithArch = FS; + CPUString = ParseSubtargetFeatures(FSWithArch, CPUString); + + // Thumb2 implies at least V6T2. + if (ARMArchVersion >= V6T2) + ThumbMode = Thumb2; + else if (ThumbMode >= Thumb2) + ARMArchVersion = V6T2; + if (isAAPCS_ABI()) stackAlignment = 8; From isanbard at gmail.com Tue Nov 9 16:51:42 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 09 Nov 2010 22:51:42 -0000 Subject: [llvm-commits] [llvm] r118644 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101109225142.A371F2A6C12D@llvm.org> Author: void Date: Tue Nov 9 16:51:42 2010 New Revision: 118644 URL: http://llvm.org/viewvc/llvm-project?rev=118644&view=rev Log: Delete the allocated vector. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118644&r1=118643&r2=118644&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 16:51:42 2010 @@ -178,6 +178,10 @@ break; } } + ~ARMOperand() { + if (isRegList()) + delete RegList.Registers; + } /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const { return StartLoc; } From rafael.espindola at gmail.com Tue Nov 9 16:54:38 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 09 Nov 2010 22:54:38 -0000 Subject: [llvm-commits] [llvm] r118645 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCSectionELF.h lib/MC/ELFObjectWriter.cpp lib/MC/MCContext.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCSectionELF.cpp Message-ID: <20101109225439.0F4972A6C12C@llvm.org> Author: rafael Date: Tue Nov 9 16:54:38 2010 New Revision: 118645 URL: http://llvm.org/viewvc/llvm-project?rev=118645&view=rev Log: Revert previous patch. Missed a case. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCSectionELF.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/MCSectionELF.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=118645&r1=118644&r2=118645&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Nov 9 16:54:38 2010 @@ -140,6 +140,7 @@ const MCSection *getELFSection(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind, + bool IsExplicit = false, unsigned EntrySize = 0); const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics, Modified: llvm/trunk/include/llvm/MC/MCSectionELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionELF.h?rev=118645&r1=118644&r2=118645&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionELF.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionELF.h Tue Nov 9 16:54:38 2010 @@ -32,6 +32,10 @@ /// below. unsigned Flags; + /// IsExplicit - Indicates that this section comes from globals with an + /// explicit section specified. + bool IsExplicit; + /// EntrySize - The size of each entry in this section. This size only /// makes sense for sections that contain fixed-sized entries. If a /// section does not contain fixed-sized entries 'EntrySize' will be 0. @@ -40,9 +44,9 @@ private: friend class MCContext; MCSectionELF(StringRef Section, unsigned type, unsigned flags, - SectionKind K, unsigned entrySize) + SectionKind K, bool isExplicit, unsigned entrySize) : MCSection(SV_ELF, K), SectionName(Section), Type(type), Flags(flags), - EntrySize(entrySize) {} + IsExplicit(isExplicit), EntrySize(entrySize) {} ~MCSectionELF(); public: @@ -50,6 +54,9 @@ /// should be printed before the section name bool ShouldOmitSectionDirective(StringRef Name, const MCAsmInfo &MAI) const; + /// ShouldPrintSectionType - Only prints the section type if supported + bool ShouldPrintSectionType(unsigned Ty) const; + /// HasCommonSymbols - True if this section holds common symbols, this is /// indicated on the ELF object file by a symbol with SHN_COMMON section /// header index. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118645&r1=118644&r2=118645&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Nov 9 16:54:38 2010 @@ -1065,7 +1065,7 @@ RelaSection = Ctx.getELFSection(RelaSectionName, HasRelocationAddend ? ELF::SHT_RELA : ELF::SHT_REL, 0, SectionKind::getReadOnly(), - EntrySize); + false, EntrySize); MCSectionData &RelaSD = Asm.getOrCreateSectionData(*RelaSection); RelaSD.setAlignment(Is64Bit ? 8 : 4); @@ -1164,7 +1164,7 @@ const MCSection *SymtabSection = Ctx.getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), - EntrySize); + false, EntrySize); MCSectionData &SymtabSD = Asm.getOrCreateSectionData(*SymtabSection); SymtabSD.setAlignment(Is64Bit ? 8 : 4); SymbolTableIndex = Asm.size(); @@ -1174,7 +1174,7 @@ if (NeedsSymtabShndx) { const MCSection *SymtabShndxSection = Ctx.getELFSection(".symtab_shndx", ELF::SHT_SYMTAB_SHNDX, 0, - SectionKind::getReadOnly(), 4); + SectionKind::getReadOnly(), false, 4); SymtabShndxSD = &Asm.getOrCreateSectionData(*SymtabShndxSection); SymtabShndxSD->setAlignment(4); } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=118645&r1=118644&r2=118645&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Nov 9 16:54:38 2010 @@ -151,7 +151,7 @@ const MCSection *MCContext:: getELFSection(StringRef Section, unsigned Type, unsigned Flags, - SectionKind Kind, unsigned EntrySize) { + SectionKind Kind, bool IsExplicit, unsigned EntrySize) { if (ELFUniquingMap == 0) ELFUniquingMap = new ELFUniqueMapTy(); ELFUniqueMapTy &Map = *(ELFUniqueMapTy*)ELFUniquingMap; @@ -165,7 +165,7 @@ EntrySize = MCSectionELF::DetermineEntrySize(Kind); } MCSectionELF *Result = new (*this) MCSectionELF(Entry.getKey(), Type, Flags, - Kind, EntrySize); + Kind, IsExplicit, EntrySize); Entry.setValue(Result); return Result; } Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=118645&r1=118644&r2=118645&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Tue Nov 9 16:54:38 2010 @@ -331,7 +331,8 @@ ? SectionKind::getText() : SectionKind::getDataRel(); getStreamer().SwitchSection(getContext().getELFSection(SectionName, Type, - Flags, Kind, Size)); + Flags, Kind, false, + Size)); return false; } @@ -405,7 +406,7 @@ MCSectionELF::SHF_MERGE | MCSectionELF::SHF_STRINGS, SectionKind::getReadOnly(), - 1); + false, 1); static bool First = true; Modified: llvm/trunk/lib/MC/MCSectionELF.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSectionELF.cpp?rev=118645&r1=118644&r2=118645&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSectionELF.cpp (original) +++ llvm/trunk/lib/MC/MCSectionELF.cpp Tue Nov 9 16:54:38 2010 @@ -29,6 +29,14 @@ return false; } +// ShouldPrintSectionType - Only prints the section type if supported +bool MCSectionELF::ShouldPrintSectionType(unsigned Ty) const { + if (IsExplicit && !(Ty == SHT_NOBITS || Ty == SHT_PROGBITS)) + return false; + + return true; +} + void MCSectionELF::PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const { @@ -76,29 +84,31 @@ OS << '"'; - OS << ','; - - // If comment string is '@', e.g. as on ARM - use '%' instead - if (MAI.getCommentString()[0] == '@') - OS << '%'; - else - OS << '@'; - - if (Type == MCSectionELF::SHT_INIT_ARRAY) - OS << "init_array"; - else if (Type == MCSectionELF::SHT_FINI_ARRAY) - OS << "fini_array"; - else if (Type == MCSectionELF::SHT_PREINIT_ARRAY) - OS << "preinit_array"; - else if (Type == MCSectionELF::SHT_NOBITS) - OS << "nobits"; - else if (Type == MCSectionELF::SHT_PROGBITS) - OS << "progbits"; - - if (EntrySize) { - OS << "," << EntrySize; + if (ShouldPrintSectionType(Type)) { + OS << ','; + + // If comment string is '@', e.g. as on ARM - use '%' instead + if (MAI.getCommentString()[0] == '@') + OS << '%'; + else + OS << '@'; + + if (Type == MCSectionELF::SHT_INIT_ARRAY) + OS << "init_array"; + else if (Type == MCSectionELF::SHT_FINI_ARRAY) + OS << "fini_array"; + else if (Type == MCSectionELF::SHT_PREINIT_ARRAY) + OS << "preinit_array"; + else if (Type == MCSectionELF::SHT_NOBITS) + OS << "nobits"; + else if (Type == MCSectionELF::SHT_PROGBITS) + OS << "progbits"; + + if (EntrySize) { + OS << "," << EntrySize; + } } - + OS << '\n'; } From grosbach at apple.com Tue Nov 9 17:25:20 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 9 Nov 2010 15:25:20 -0800 Subject: [llvm-commits] [llvm] r118640 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: <20101109224422.878C42A6C12D@llvm.org> References: <20101109224422.878C42A6C12D@llvm.org> Message-ID: Hi Bill, Looking good. How close are we to parsing LDM instructions with this in place? A few nits inline. -Jim On Nov 9, 2010, at 2:44 PM, Bill Wendling wrote: > Author: void > Date: Tue Nov 9 16:44:22 2010 > New Revision: 118640 > > URL: http://llvm.org/viewvc/llvm-project?rev=118640&view=rev > Log: > Two types of instructions have register lists: > > * LDM, et al, uses a bit mask to indicate the register list. > * VLDM, et al, uses a base register plus number. > > The LDM instructions may be non-contiguous, but the VLDM ones must be > contiguous. Those are semantic checks that should be done later in the > compiler. Also postpone the creation of the bit mask until it's needed. > > Modified: > llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118640&r1=118639&r2=118640&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 16:44:22 2010 > @@ -128,8 +128,7 @@ > } Reg; > > struct { > - unsigned RegStart; > - unsigned Number; > + std::vector *Registers; > } RegList; SmallVector. Also, no need for the struct container. > > struct { > @@ -196,18 +195,13 @@ > } > > unsigned getReg() const { > - assert((Kind == Register || Kind == RegisterList) && "Invalid access!"); > - unsigned RegNum = 0; > - if (Kind == Register) > - RegNum = Reg.RegNum; > - else > - RegNum = RegList.RegStart; > - return RegNum; > + assert(Kind == Register && "Invalid access!"); > + return Reg.RegNum; > } > > - std::pair getRegList() const { > + const std::vector &getRegList() const { > assert(Kind == RegisterList && "Invalid access!"); > - return std::make_pair(RegList.RegStart, RegList.Number); > + return *RegList.Registers; > } > > const MCExpr *getImm() const { > @@ -259,10 +253,11 @@ > } > > void addRegListOperands(MCInst &Inst, unsigned N) const { > - assert(N == 2 && "Invalid number of operands!"); > - std::pair RegList = getRegList(); > - Inst.addOperand(MCOperand::CreateReg(RegList.first)); > - Inst.addOperand(MCOperand::CreateImm(RegList.second)); > + assert(N == 1 && "Invalid number of operands!"); > + const std::vector &RegList = getRegList(); > + for (std::vector::const_iterator > + I = RegList.begin(), E = RegList.end(); I != E; ++I) > + Inst.addOperand(MCOperand::CreateReg(*I)); > } > > void addImmOperands(MCInst &Inst, unsigned N) const { > @@ -325,11 +320,15 @@ > return Op; > } > > - static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number, > - SMLoc S, SMLoc E) { > + static ARMOperand * > + CreateRegList(std::vector > &Regs, > + SMLoc S, SMLoc E) { > ARMOperand *Op = new ARMOperand(RegisterList); > - Op->RegList.RegStart = RegStart; > - Op->RegList.Number = Number; > + Op->RegList.Registers = new std::vector(); > + for (std::vector >::iterator > + I = Regs.begin(), E = Regs.end(); I != E; ++I) > + Op->RegList.Registers->push_back(I->first); > + std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end()); > Op->StartLoc = S; > Op->EndLoc = E; > return Op; > @@ -386,12 +385,12 @@ > break; > case RegisterList: { > OS << " - std::pair List = getRegList(); > - unsigned RegEnd = List.first + List.second; > > - for (unsigned Idx = List.first; Idx < RegEnd; ) { > - OS << Idx; > - if (++Idx < RegEnd) OS << ", "; > + const std::vector &RegList = getRegList(); > + for (std::vector::const_iterator > + I = RegList.begin(), E = RegList.end(); I != E; ) { > + OS << *I; > + if (++I < E) OS << ", "; > } > > OS << ">"; > @@ -459,30 +458,15 @@ > assert(Parser.getTok().is(AsmToken::LCurly) && > "Token is not a Left Curly Brace"); > SMLoc S = Parser.getTok().getLoc(); > - Parser.Lex(); // Eat left curly brace token. > - > - const AsmToken &RegTok = Parser.getTok(); > - SMLoc RegLoc = RegTok.getLoc(); > - if (RegTok.isNot(AsmToken::Identifier)) { > - Error(RegLoc, "register expected"); > - return 0; > - } > - > - int RegNum = TryParseRegister(); > - if (RegNum == -1) { > - Error(RegLoc, "register expected"); > - return 0; > - } > > - unsigned PrevRegNum = RegNum; > + // Read the rest of the registers in the list. > + unsigned PrevRegNum = 0; > std::vector > Registers; SmallVector. > Registers.reserve(32); > - Registers.push_back(std::make_pair(RegNum, RegLoc)); > > - while (Parser.getTok().is(AsmToken::Comma) || > - Parser.getTok().is(AsmToken::Minus)) { > + do { > bool IsRange = Parser.getTok().is(AsmToken::Minus); > - Parser.Lex(); // Eat comma or minus token. > + Parser.Lex(); // Eat non-identifier token. > > const AsmToken &RegTok = Parser.getTok(); > SMLoc RegLoc = RegTok.getLoc(); > @@ -508,7 +492,8 @@ > } > > PrevRegNum = RegNum; > - } > + } while (Parser.getTok().is(AsmToken::Comma) || > + Parser.getTok().is(AsmToken::Minus)); > > // Process the right curly brace of the list. > const AsmToken &RCurlyTok = Parser.getTok(); > @@ -521,18 +506,15 @@ > Parser.Lex(); // Eat right curly brace token. > > // Verify the register list. > - std::vector >::iterator > + std::vector >::const_iterator > RI = Registers.begin(), RE = Registers.end(); > > - unsigned Number = Registers.size(); > unsigned HighRegNum = RI->first; > - unsigned RegStart = RI->first; > - > DenseMap RegMap; > RegMap[RI->first] = true; > > for (++RI; RI != RE; ++RI) { > - std::pair &RegInfo = *RI; > + const std::pair &RegInfo = *RI; > > if (RegMap[RegInfo.first]) { > Error(RegInfo.second, "register duplicated in register list"); > @@ -545,15 +527,9 @@ > > RegMap[RegInfo.first] = true; > HighRegNum = std::max(RegInfo.first, HighRegNum); > - RegStart = std::min(RegInfo.first, RegStart); > - } > - > - if (RegStart + Number - 1 != HighRegNum) { > - Error(RegLoc, "non-contiguous register range"); > - return 0; > } > > - return ARMOperand::CreateRegList(RegStart, Number, S, E); > + return ARMOperand::CreateRegList(Registers, S, E); > } > > /// Parse an ARM memory expression, return false if successful else return true > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From anton at korobeynikov.info Tue Nov 9 17:29:52 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 10 Nov 2010 02:29:52 +0300 Subject: [llvm-commits] RFC: TargetRegisterInfo refactoring Message-ID: Hello Everyone, Right now TargetRegisterInfo class looks pretty much overweighted and definitely not a "register info" anymore. In particular, it contains various stuff to handle function stack frames, e.g. emitPrologue / emitEpilogue and around. These methods looks much better if located in the TargetFrameInfo. I'd like to move them there and collect all frame-related stuff in the same place. Any objections / comments / thoughts? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From isanbard at gmail.com Tue Nov 9 17:28:45 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 09 Nov 2010 23:28:45 -0000 Subject: [llvm-commits] [llvm] r118648 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101109232845.0B0D92A6C12C@llvm.org> Author: void Date: Tue Nov 9 17:28:44 2010 New Revision: 118648 URL: http://llvm.org/viewvc/llvm-project?rev=118648&view=rev Log: s/std::vector/SmallVector/ Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118648&r1=118647&r2=118648&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 17:28:44 2010 @@ -128,7 +128,7 @@ } Reg; struct { - std::vector *Registers; + SmallVector *Registers; } RegList; struct { @@ -203,7 +203,7 @@ return Reg.RegNum; } - const std::vector &getRegList() const { + const SmallVectorImpl &getRegList() const { assert(Kind == RegisterList && "Invalid access!"); return *RegList.Registers; } @@ -258,8 +258,8 @@ void addRegListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); - const std::vector &RegList = getRegList(); - for (std::vector::const_iterator + const SmallVectorImpl &RegList = getRegList(); + for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ++I) Inst.addOperand(MCOperand::CreateReg(*I)); } @@ -325,11 +325,11 @@ } static ARMOperand * - CreateRegList(std::vector > &Regs, + CreateRegList(const SmallVectorImpl > &Regs, SMLoc S, SMLoc E) { ARMOperand *Op = new ARMOperand(RegisterList); - Op->RegList.Registers = new std::vector(); - for (std::vector >::iterator + Op->RegList.Registers = new SmallVector(); + for (SmallVectorImpl >::const_iterator I = Regs.begin(), E = Regs.end(); I != E; ++I) Op->RegList.Registers->push_back(I->first); std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end()); @@ -390,8 +390,8 @@ case RegisterList: { OS << " &RegList = getRegList(); - for (std::vector::const_iterator + const SmallVectorImpl &RegList = getRegList(); + for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ) { OS << *I; if (++I < E) OS << ", "; @@ -465,8 +465,7 @@ // Read the rest of the registers in the list. unsigned PrevRegNum = 0; - std::vector > Registers; - Registers.reserve(32); + SmallVector, 32> Registers; do { bool IsRange = Parser.getTok().is(AsmToken::Minus); @@ -510,7 +509,7 @@ Parser.Lex(); // Eat right curly brace token. // Verify the register list. - std::vector >::const_iterator + SmallVectorImpl >::const_iterator RI = Registers.begin(), RE = Registers.end(); unsigned HighRegNum = RI->first; From isanbard at gmail.com Tue Nov 9 17:32:37 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 9 Nov 2010 15:32:37 -0800 Subject: [llvm-commits] [llvm] r118640 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: References: <20101109224422.878C42A6C12D@llvm.org> Message-ID: On Nov 9, 2010, at 3:25 PM, Jim Grosbach wrote: > Hi Bill, > > Looking good. How close are we to parsing LDM instructions with this in place? > Pretty close. I need to look up-stream from here. We can *parse* them, but can't do much with the information at this point. :) > On Nov 9, 2010, at 2:44 PM, Bill Wendling wrote: > >> struct { >> - unsigned RegStart; >> - unsigned Number; >> + std::vector *Registers; >> } RegList; > > SmallVector. Done. > Also, no need for the struct container. > No, but containers are used in all of the other structures in this union, even if they have only one field. At least it's consistent. :-) -bw From rafael.espindola at gmail.com Tue Nov 9 17:42:07 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 09 Nov 2010 23:42:07 -0000 Subject: [llvm-commits] [llvm] r118651 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCSectionELF.h lib/CodeGen/TargetLoweringObjectFileImpl.cpp lib/MC/ELFObjectWriter.cpp lib/MC/MCContext.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCSectionELF.cpp Message-ID: <20101109234207.517812A6C12D@llvm.org> Author: rafael Date: Tue Nov 9 17:42:07 2010 New Revision: 118651 URL: http://llvm.org/viewvc/llvm-project?rev=118651&view=rev Log: Fixed version of 118639 with an extra assert to catch similar problems earlier. Implicit bool -> int conversions are evil! Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCSectionELF.h llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/MCSectionELF.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Nov 9 17:42:07 2010 @@ -140,7 +140,6 @@ const MCSection *getELFSection(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind, - bool IsExplicit = false, unsigned EntrySize = 0); const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics, Modified: llvm/trunk/include/llvm/MC/MCSectionELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionELF.h?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionELF.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionELF.h Tue Nov 9 17:42:07 2010 @@ -32,10 +32,6 @@ /// below. unsigned Flags; - /// IsExplicit - Indicates that this section comes from globals with an - /// explicit section specified. - bool IsExplicit; - /// EntrySize - The size of each entry in this section. This size only /// makes sense for sections that contain fixed-sized entries. If a /// section does not contain fixed-sized entries 'EntrySize' will be 0. @@ -44,9 +40,9 @@ private: friend class MCContext; MCSectionELF(StringRef Section, unsigned type, unsigned flags, - SectionKind K, bool isExplicit, unsigned entrySize) + SectionKind K, unsigned entrySize) : MCSection(SV_ELF, K), SectionName(Section), Type(type), Flags(flags), - IsExplicit(isExplicit), EntrySize(entrySize) {} + EntrySize(entrySize) {} ~MCSectionELF(); public: @@ -54,9 +50,6 @@ /// should be printed before the section name bool ShouldOmitSectionDirective(StringRef Name, const MCAsmInfo &MAI) const; - /// ShouldPrintSectionType - Only prints the section type if supported - bool ShouldPrintSectionType(unsigned Ty) const; - /// HasCommonSymbols - True if this section holds common symbols, this is /// indicated on the ELF object file by a symbol with SHN_COMMON section /// header index. Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Nov 9 17:42:07 2010 @@ -262,7 +262,7 @@ return getContext().getELFSection(SectionName, getELFSectionType(SectionName, Kind), - getELFSectionFlags(Kind), Kind, true); + getELFSectionFlags(Kind), Kind); } static const char *getSectionPrefixForUniqueGlobal(SectionKind Kind) { Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Nov 9 17:42:07 2010 @@ -1065,7 +1065,7 @@ RelaSection = Ctx.getELFSection(RelaSectionName, HasRelocationAddend ? ELF::SHT_RELA : ELF::SHT_REL, 0, SectionKind::getReadOnly(), - false, EntrySize); + EntrySize); MCSectionData &RelaSD = Asm.getOrCreateSectionData(*RelaSection); RelaSD.setAlignment(Is64Bit ? 8 : 4); @@ -1164,7 +1164,7 @@ const MCSection *SymtabSection = Ctx.getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), - false, EntrySize); + EntrySize); MCSectionData &SymtabSD = Asm.getOrCreateSectionData(*SymtabSection); SymtabSD.setAlignment(Is64Bit ? 8 : 4); SymbolTableIndex = Asm.size(); @@ -1174,7 +1174,7 @@ if (NeedsSymtabShndx) { const MCSection *SymtabShndxSection = Ctx.getELFSection(".symtab_shndx", ELF::SHT_SYMTAB_SHNDX, 0, - SectionKind::getReadOnly(), false, 4); + SectionKind::getReadOnly(), 4); SymtabShndxSD = &Asm.getOrCreateSectionData(*SymtabShndxSection); SymtabShndxSD->setAlignment(4); } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Nov 9 17:42:07 2010 @@ -151,7 +151,7 @@ const MCSection *MCContext:: getELFSection(StringRef Section, unsigned Type, unsigned Flags, - SectionKind Kind, bool IsExplicit, unsigned EntrySize) { + SectionKind Kind, unsigned EntrySize) { if (ELFUniquingMap == 0) ELFUniquingMap = new ELFUniqueMapTy(); ELFUniqueMapTy &Map = *(ELFUniqueMapTy*)ELFUniquingMap; @@ -165,7 +165,7 @@ EntrySize = MCSectionELF::DetermineEntrySize(Kind); } MCSectionELF *Result = new (*this) MCSectionELF(Entry.getKey(), Type, Flags, - Kind, IsExplicit, EntrySize); + Kind, EntrySize); Entry.setValue(Result); return Result; } Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Tue Nov 9 17:42:07 2010 @@ -331,8 +331,7 @@ ? SectionKind::getText() : SectionKind::getDataRel(); getStreamer().SwitchSection(getContext().getELFSection(SectionName, Type, - Flags, Kind, false, - Size)); + Flags, Kind, Size)); return false; } @@ -406,7 +405,7 @@ MCSectionELF::SHF_MERGE | MCSectionELF::SHF_STRINGS, SectionKind::getReadOnly(), - false, 1); + 1); static bool First = true; Modified: llvm/trunk/lib/MC/MCSectionELF.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSectionELF.cpp?rev=118651&r1=118650&r2=118651&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCSectionELF.cpp (original) +++ llvm/trunk/lib/MC/MCSectionELF.cpp Tue Nov 9 17:42:07 2010 @@ -29,14 +29,6 @@ return false; } -// ShouldPrintSectionType - Only prints the section type if supported -bool MCSectionELF::ShouldPrintSectionType(unsigned Ty) const { - if (IsExplicit && !(Ty == SHT_NOBITS || Ty == SHT_PROGBITS)) - return false; - - return true; -} - void MCSectionELF::PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const { @@ -84,31 +76,30 @@ OS << '"'; - if (ShouldPrintSectionType(Type)) { - OS << ','; - - // If comment string is '@', e.g. as on ARM - use '%' instead - if (MAI.getCommentString()[0] == '@') - OS << '%'; - else - OS << '@'; - - if (Type == MCSectionELF::SHT_INIT_ARRAY) - OS << "init_array"; - else if (Type == MCSectionELF::SHT_FINI_ARRAY) - OS << "fini_array"; - else if (Type == MCSectionELF::SHT_PREINIT_ARRAY) - OS << "preinit_array"; - else if (Type == MCSectionELF::SHT_NOBITS) - OS << "nobits"; - else if (Type == MCSectionELF::SHT_PROGBITS) - OS << "progbits"; - - if (EntrySize) { - OS << "," << EntrySize; - } + OS << ','; + + // If comment string is '@', e.g. as on ARM - use '%' instead + if (MAI.getCommentString()[0] == '@') + OS << '%'; + else + OS << '@'; + + if (Type == MCSectionELF::SHT_INIT_ARRAY) + OS << "init_array"; + else if (Type == MCSectionELF::SHT_FINI_ARRAY) + OS << "fini_array"; + else if (Type == MCSectionELF::SHT_PREINIT_ARRAY) + OS << "preinit_array"; + else if (Type == MCSectionELF::SHT_NOBITS) + OS << "nobits"; + else if (Type == MCSectionELF::SHT_PROGBITS) + OS << "progbits"; + + if (EntrySize) { + assert(Flags & MCSectionELF::SHF_MERGE); + OS << "," << EntrySize; } - + OS << '\n'; } From dalej at apple.com Tue Nov 9 17:43:34 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 09 Nov 2010 23:43:34 -0000 Subject: [llvm-commits] [llvm] r118652 - in /llvm/trunk/test/ExecutionEngine: 2003-08-23-RegisterAllocatePhysReg.ll test-loadstore.ll Message-ID: <20101109234334.C115F2A6C12C@llvm.org> Author: johannes Date: Tue Nov 9 17:43:34 2010 New Revision: 118652 URL: http://llvm.org/viewvc/llvm-project?rev=118652&view=rev Log: Jim's recent fixes 118600, 118587, 118513 have made these work. Modified: llvm/trunk/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll llvm/trunk/test/ExecutionEngine/test-loadstore.ll Modified: llvm/trunk/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll?rev=118652&r1=118651&r2=118652&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll Tue Nov 9 17:43:34 2010 @@ -1,6 +1,5 @@ ; RUN: llvm-as %s -o %t.bc ; RUN: lli %t.bc > /dev/null -; XFAIL: arm ; This testcase exposes a bug in the local register allocator where it runs out ; of registers (due to too many overlapping live ranges), but then attempts to Modified: llvm/trunk/test/ExecutionEngine/test-loadstore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/test-loadstore.ll?rev=118652&r1=118651&r2=118652&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/test-loadstore.ll (original) +++ llvm/trunk/test/ExecutionEngine/test-loadstore.ll Tue Nov 9 17:43:34 2010 @@ -1,6 +1,5 @@ ; RUN: llvm-as %s -o %t.bc ; RUN: lli %t.bc > /dev/null -; XFAIL: arm define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) { %V = load i8* %P ; [#uses=1] From isanbard at gmail.com Tue Nov 9 17:45:59 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 09 Nov 2010 23:45:59 -0000 Subject: [llvm-commits] [llvm] r118653 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101109234559.AC7852A6C12C@llvm.org> Author: void Date: Tue Nov 9 17:45:59 2010 New Revision: 118653 URL: http://llvm.org/viewvc/llvm-project?rev=118653&view=rev Log: Emit the warning about the register list not being in ascending order only once. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118653&r1=118652&r2=118653&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 17:45:59 2010 @@ -512,24 +512,27 @@ SmallVectorImpl >::const_iterator RI = Registers.begin(), RE = Registers.end(); - unsigned HighRegNum = RI->first; DenseMap RegMap; RegMap[RI->first] = true; + unsigned HighRegNum = RI->first; + bool EmittedWarning = false; + for (++RI; RI != RE; ++RI) { const std::pair &RegInfo = *RI; + unsigned Reg = RegInfo.first; - if (RegMap[RegInfo.first]) { + if (RegMap[Reg]) { Error(RegInfo.second, "register duplicated in register list"); return 0; } - if (RegInfo.first < HighRegNum) + if (!EmittedWarning && Reg < HighRegNum) Warning(RegInfo.second, "register not in ascending order in register list"); - RegMap[RegInfo.first] = true; - HighRegNum = std::max(RegInfo.first, HighRegNum); + RegMap[Reg] = true; + HighRegNum = std::max(Reg, HighRegNum); } return ARMOperand::CreateRegList(Registers, S, E); From grosbach at apple.com Tue Nov 9 17:49:30 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 9 Nov 2010 15:49:30 -0800 Subject: [llvm-commits] [llvm] r118640 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: References: <20101109224422.878C42A6C12D@llvm.org> Message-ID: On Nov 9, 2010, at 3:32 PM, Bill Wendling wrote: >> Also, no need for the struct container. >> > No, but containers are used in all of the other structures in this union, even if they have only one field. At least it's consistent. :-) Ah, Ok. Would it be better then to keep them as separate operands rather than bundling them up as a list? That's how the MCInst will expect them anyway, so it seems to make sense. The encoder methods can then pack them up into a bitmask, start+length pair, or whatever else is needed. I think that'll make is easier for you to construct the MCInsts from the parsed operand list. Having a non-trivial destructor on ARMOperand worries me. Making the reglist not a pointer will increase the size of ARMOperand quite a bit, which isn't good either. -Jim From grosser at fim.uni-passau.de Tue Nov 9 18:05:46 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 09 Nov 2010 19:05:46 -0500 Subject: [llvm-commits] [PATCH] Add dragonegg support as llvm-gcc frontend in llvm-core and test-suite Message-ID: <4CD9E1DA.1070001@fim.uni-passau.de> Hi, this patch set based on work of Duncan adds support for a dragonegg based llvm-gcc frontend to llvm-core and the test suite. This patch set is a step to set up automatic test-suite runs for dragonegg as well as to add dragonegg-fortran support to the test suite. OK to commit those patches? Cheers Tobi -------------- next part -------------- A non-text attachment was scrubbed... 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Name: 0002-Update-configure.patch Type: text/x-diff Size: 5770 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101109/50b96226/attachment-0002.bin From matthewbg at google.com Tue Nov 9 18:08:58 2010 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Wed, 10 Nov 2010 00:08:58 -0000 Subject: [llvm-commits] [llvm] r118656 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101110000858.8589A2A6C12C@llvm.org> Author: matthewbg Date: Tue Nov 9 18:08:58 2010 New Revision: 118656 URL: http://llvm.org/viewvc/llvm-project?rev=118656&view=rev Log: Rename a parameter to avoid confusion with a local variable Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118656&r1=118655&r2=118656&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 18:08:58 2010 @@ -326,15 +326,15 @@ static ARMOperand * CreateRegList(const SmallVectorImpl > &Regs, - SMLoc S, SMLoc E) { + SMLoc StartLoc, SMLoc EndLoc) { ARMOperand *Op = new ARMOperand(RegisterList); Op->RegList.Registers = new SmallVector(); for (SmallVectorImpl >::const_iterator I = Regs.begin(), E = Regs.end(); I != E; ++I) Op->RegList.Registers->push_back(I->first); std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end()); - Op->StartLoc = S; - Op->EndLoc = E; + Op->StartLoc = StartLoc; + Op->EndLoc = EndLoc; return Op; } From wendling at apple.com Tue Nov 9 18:14:42 2010 From: wendling at apple.com (Bill Wendling) Date: Tue, 9 Nov 2010 16:14:42 -0800 Subject: [llvm-commits] [llvm] r118656 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: <20101110000858.8589A2A6C12C@llvm.org> References: <20101110000858.8589A2A6C12C@llvm.org> Message-ID: On Nov 9, 2010, at 4:08 PM, Matt Beaumont-Gay wrote: > Author: matthewbg > Date: Tue Nov 9 18:08:58 2010 > New Revision: 118656 > > URL: http://llvm.org/viewvc/llvm-project?rev=118656&view=rev > Log: > Rename a parameter to avoid confusion with a local variable > Thanks, Matt. :-) In the future, if there's something wrong with a patch, you can reply and I will fix it. (Not meaning this to sound like a sarcastic statement.) -bw From matthewbg at google.com Tue Nov 9 18:21:56 2010 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Tue, 9 Nov 2010 16:21:56 -0800 Subject: [llvm-commits] [llvm] r118656 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp In-Reply-To: References: <20101110000858.8589A2A6C12C@llvm.org> Message-ID: On Tue, Nov 9, 2010 at 16:14, Bill Wendling wrote: > On Nov 9, 2010, at 4:08 PM, Matt Beaumont-Gay wrote: > >> Author: matthewbg >> Date: Tue Nov ?9 18:08:58 2010 >> New Revision: 118656 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118656&view=rev >> Log: >> Rename a parameter to avoid confusion with a local variable >> > Thanks, Matt. :-) > > In the future, if there's something wrong with a patch, you can reply and I will fix it. (Not meaning this to sound like a sarcastic statement.) Sure, no problem. I fixed it myself largely because (A) it was a trivial fix and (B) it only materially affects those of us who build with -Wall -Werror :) -Matt From stoklund at 2pi.dk Tue Nov 9 18:31:09 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 9 Nov 2010 16:31:09 -0800 Subject: [llvm-commits] RFC: TargetRegisterInfo refactoring In-Reply-To: References: Message-ID: <15FA6D6F-898A-4B35-9616-B4470854336A@2pi.dk> On Nov 9, 2010, at 3:29 PM, Anton Korobeynikov wrote: > Hello Everyone, > > Right now TargetRegisterInfo class looks pretty much overweighted and > definitely not a "register info" anymore. In particular, it contains > various stuff to handle function stack frames, e.g. emitPrologue / > emitEpilogue and around. These methods looks much better if located in > the TargetFrameInfo. I'd like to move them there and collect all > frame-related stuff in the same place. > > Any objections / comments / thoughts? That makes sense to me. It is a lot of code to move around, though. Is it worth the churn? /jakob From anton at korobeynikov.info Tue Nov 9 18:44:30 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 10 Nov 2010 03:44:30 +0300 Subject: [llvm-commits] RFC: TargetRegisterInfo refactoring In-Reply-To: <15FA6D6F-898A-4B35-9616-B4470854336A@2pi.dk> References: <15FA6D6F-898A-4B35-9616-B4470854336A@2pi.dk> Message-ID: > That makes sense to me. > It is a lot of code to move around, though. Is it worth the churn? Well, I have a feeling that this should be done sooner or later. I'd take "sooner" way :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From stoklund at 2pi.dk Tue Nov 9 18:51:18 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 9 Nov 2010 16:51:18 -0800 Subject: [llvm-commits] RFC: TargetRegisterInfo refactoring In-Reply-To: References: <15FA6D6F-898A-4B35-9616-B4470854336A@2pi.dk> Message-ID: <9A8D8FD7-22D8-4037-99C0-3EC88D2D5594@2pi.dk> On Nov 9, 2010, at 4:44 PM, Anton Korobeynikov wrote: >> That makes sense to me. >> It is a lot of code to move around, though. Is it worth the churn? > Well, I have a feeling that this should be done sooner or later. I'd > take "sooner" way :) I say, go for it. /jakob From gohman at apple.com Tue Nov 9 19:02:18 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 01:02:18 -0000 Subject: [llvm-commits] [llvm] r118660 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll Message-ID: <20101110010218.BC1E62A6C12C@llvm.org> Author: djg Date: Tue Nov 9 19:02:18 2010 New Revision: 118660 URL: http://llvm.org/viewvc/llvm-project?rev=118660&view=rev Log: Make ModRefBehavior a lattice. Use this to clean up AliasAnalysis chaining and simplify FunctionAttrs' GetModRefBehavior logic. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 19:02:18 2010 @@ -175,6 +175,9 @@ /// enum ModRefResult { NoModRef = 0, Ref = 1, Mod = 2, ModRef = 3 }; + /// These values define additional bits used to define the + /// ModRefBehavior values. + enum { Nowhere = 0, ArgumentPointees = 4, Anywhere = 8 | ArgumentPointees }; /// ModRefBehavior - Summary of how a function affects memory in the program. /// Loads from constant globals are not considered memory accesses for this @@ -187,20 +190,20 @@ /// This property corresponds to the GCC 'const' attribute. /// This property corresponds to the LLVM IR 'readnone' attribute. /// This property corresponds to the IntrNoMem LLVM intrinsic flag. - DoesNotAccessMemory, + DoesNotAccessMemory = Nowhere | NoModRef, /// AccessesArgumentsReadonly - This function loads through function /// arguments and does not perform any non-local stores or volatile /// loads. /// /// This property corresponds to the IntrReadArgMem LLVM intrinsic flag. - AccessesArgumentsReadonly, + AccessesArgumentsReadonly = ArgumentPointees | Ref, /// AccessesArguments - This function accesses function arguments in well /// known (possibly volatile) ways, but does not access any other memory. /// /// This property corresponds to the IntrReadWriteArgMem LLVM intrinsic flag. - AccessesArguments, + AccessesArguments = ArgumentPointees | ModRef, /// OnlyReadsMemory - This function does not perform any non-local stores or /// volatile loads, but may read from any memory location. @@ -208,11 +211,11 @@ /// This property corresponds to the GCC 'pure' attribute. /// This property corresponds to the LLVM IR 'readonly' attribute. /// This property corresponds to the IntrReadMem LLVM intrinsic flag. - OnlyReadsMemory, + OnlyReadsMemory = Anywhere | Ref, /// UnknownModRefBehavior - This indicates that the function could not be /// classified into one of the behaviors above. - UnknownModRefBehavior + UnknownModRefBehavior = Anywhere | ModRef }; /// getModRefBehavior - Return the behavior when calling the given call site. @@ -270,12 +273,9 @@ /// true. For use when the call site is not known. /// static bool onlyReadsMemory(ModRefBehavior MRB) { - return MRB == DoesNotAccessMemory || - MRB == AccessesArgumentsReadonly || - MRB == OnlyReadsMemory; + return !(MRB & Mod); } - /// getModRefInfo - Return information about whether or not an instruction may /// read or write the specified memory location. An instruction /// that doesn't read or write memory may be trivially LICM'd for example. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Nov 9 19:02:18 2010 @@ -179,7 +179,7 @@ // Otherwise, fall back to the next AA in the chain. But we can merge // in any result we've managed to compute. - return std::min(AA->getModRefBehavior(CS), Min); + return ModRefBehavior(AA->getModRefBehavior(CS) & Min); } AliasAnalysis::ModRefBehavior Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Nov 9 19:02:18 2010 @@ -595,7 +595,7 @@ Min = OnlyReadsMemory; // The AliasAnalysis base class has some smarts, lets use them. - return std::min(AliasAnalysis::getModRefBehavior(CS), Min); + return ModRefBehavior(AliasAnalysis::getModRefBehavior(CS) & Min); } /// getModRefBehavior - Return the behavior when calling the given function. @@ -613,12 +613,14 @@ #undef GET_INTRINSIC_MODREF_BEHAVIOR } + ModRefBehavior Min = UnknownModRefBehavior; + // If the function declares it only reads memory, go with that. if (F->onlyReadsMemory()) - return OnlyReadsMemory; + Min = OnlyReadsMemory; // Otherwise be conservative. - return AliasAnalysis::getModRefBehavior(F); + return ModRefBehavior(AliasAnalysis::getModRefBehavior(F) & Min); } /// getModRefInfo - Check to see if the specified callsite can clobber the @@ -671,6 +673,8 @@ return NoModRef; } + ModRefResult Min = ModRef; + // Finally, handle specific knowledge of intrinsics. const IntrinsicInst *II = dyn_cast(CS.getInstruction()); if (II != 0) @@ -686,7 +690,7 @@ if (isNoAlias(Location(Dest, Len), Loc)) { if (isNoAlias(Location(Src, Len), Loc)) return NoModRef; - return Ref; + Min = Ref; } break; } @@ -745,7 +749,7 @@ } // The AliasAnalysis base class has some smarts, lets use them. - return AliasAnalysis::getModRefInfo(CS, Loc); + return ModRefResult(AliasAnalysis::getModRefInfo(CS, Loc) & Min); } /// aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP instruction Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Tue Nov 9 19:02:18 2010 @@ -120,28 +120,33 @@ /// called from the specified call site. The call site may be null in which /// case the most generic behavior of this function should be returned. ModRefBehavior getModRefBehavior(const Function *F) { + ModRefBehavior Min = UnknownModRefBehavior; + if (FunctionRecord *FR = getFunctionInfo(F)) { if (FR->FunctionEffect == 0) - return DoesNotAccessMemory; + Min = DoesNotAccessMemory; else if ((FR->FunctionEffect & Mod) == 0) - return OnlyReadsMemory; + Min = OnlyReadsMemory; } - return AliasAnalysis::getModRefBehavior(F); + + return ModRefBehavior(AliasAnalysis::getModRefBehavior(F) & Min); } /// getModRefBehavior - Return the behavior of the specified function if /// called from the specified call site. The call site may be null in which /// case the most generic behavior of this function should be returned. ModRefBehavior getModRefBehavior(ImmutableCallSite CS) { - const Function* F = CS.getCalledFunction(); - if (!F) return AliasAnalysis::getModRefBehavior(CS); - if (FunctionRecord *FR = getFunctionInfo(F)) { - if (FR->FunctionEffect == 0) - return DoesNotAccessMemory; - else if ((FR->FunctionEffect & Mod) == 0) - return OnlyReadsMemory; - } - return AliasAnalysis::getModRefBehavior(CS); + ModRefBehavior Min = UnknownModRefBehavior; + + if (const Function* F = CS.getCalledFunction()) + if (FunctionRecord *FR = getFunctionInfo(F)) { + if (FR->FunctionEffect == 0) + Min = DoesNotAccessMemory; + else if ((FR->FunctionEffect & Mod) == 0) + Min = OnlyReadsMemory; + } + + return ModRefBehavior(AliasAnalysis::getModRefBehavior(CS) & Min); } virtual void deleteValue(Value *V); Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Tue Nov 9 19:02:18 2010 @@ -256,11 +256,12 @@ if (TBAANode(M).TypeIsImmutable()) Min = OnlyReadsMemory; - return std::min(AliasAnalysis::getModRefBehavior(CS), Min); + return ModRefBehavior(AliasAnalysis::getModRefBehavior(CS) & Min); } AliasAnalysis::ModRefBehavior TypeBasedAliasAnalysis::getModRefBehavior(const Function *F) { + // Functions don't have metadata. Just chain to the next implementation. return AliasAnalysis::getModRefBehavior(F); } Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Tue Nov 9 19:02:18 2010 @@ -128,54 +128,41 @@ // Ignore calls to functions in the same SCC. if (CS.getCalledFunction() && SCCNodes.count(CS.getCalledFunction())) continue; - switch (AA->getModRefBehavior(CS)) { - case AliasAnalysis::DoesNotAccessMemory: - // Ignore calls that don't access memory. - continue; - case AliasAnalysis::OnlyReadsMemory: - // Handle calls that only read from memory. - ReadsMemory = true; - continue; - case AliasAnalysis::AccessesArguments: - // Check whether all pointer arguments point to local memory, and - // ignore calls that only access local memory. - for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); - CI != CE; ++CI) { - Value *Arg = *CI; - if (Arg->getType()->isPointerTy()) { - AliasAnalysis::Location Loc(Arg, - AliasAnalysis::UnknownSize, - I->getMetadata(LLVMContext::MD_tbaa)); - if (!AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) - // Writes memory. Just give up. - return false; - } - } - // Only reads and writes local memory. - continue; - case AliasAnalysis::AccessesArgumentsReadonly: - // Check whether all pointer arguments point to local memory, and - // ignore calls that only access local memory. - for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); - CI != CE; ++CI) { - Value *Arg = *CI; - if (Arg->getType()->isPointerTy()) { - AliasAnalysis::Location Loc(Arg, - AliasAnalysis::UnknownSize, - I->getMetadata(LLVMContext::MD_tbaa)); - if (!AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) { - // Reads non-local memory. - ReadsMemory = true; - break; + AliasAnalysis::ModRefBehavior MRB = AA->getModRefBehavior(CS); + // If the call doesn't access arbitrary memory, we may be able to + // figure out something. + if (!(MRB & AliasAnalysis::Anywhere & + ~AliasAnalysis::ArgumentPointees)) { + // If the call accesses argument pointees, check each argument. + if (MRB & AliasAnalysis::AccessesArguments) + // Check whether all pointer arguments point to local memory, and + // ignore calls that only access local memory. + for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); + CI != CE; ++CI) { + Value *Arg = *CI; + if (Arg->getType()->isPointerTy()) { + AliasAnalysis::Location Loc(Arg, + AliasAnalysis::UnknownSize, + I->getMetadata(LLVMContext::MD_tbaa)); + if (!AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) { + if (MRB & AliasAnalysis::Mod) + // Writes non-local memory. Give up. + return false; + if (MRB & AliasAnalysis::Ref) + // Ok, it reads non-local memory. + ReadsMemory = true; + } } } - } - // Only reads memory. continue; - default: - // Otherwise, be conservative. - break; } + // The call could access any memory. If that includes writes, give up. + if (MRB & AliasAnalysis::Mod) + return false; + // If it reads, note it. + if (MRB & AliasAnalysis::Ref) + ReadsMemory = true; + continue; } else if (LoadInst *LI = dyn_cast(I)) { // Ignore non-volatile loads from local memory. if (!LI->isVolatile()) { Modified: llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll (original) +++ llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll Tue Nov 9 19:02:18 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -functionattrs -S | grep readnone | count 4 +; RUN: opt < %s -basicaa -functionattrs -S | grep readnone | count 4 @x = global i32 0 declare i32 @e() readnone Modified: llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll?rev=118660&r1=118659&r2=118660&view=diff ============================================================================== --- llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll (original) +++ llvm/trunk/test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll Tue Nov 9 19:02:18 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -functionattrs -S | grep readonly | count 2 +; RUN: opt < %s -basicaa -functionattrs -S | grep readonly | count 2 define i32 @f() { entry: From stoklund at 2pi.dk Tue Nov 9 19:05:12 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 01:05:12 -0000 Subject: [llvm-commits] [llvm] r118661 - in /llvm/trunk/lib/CodeGen: InlineSpiller.cpp LiveRangeEdit.cpp LiveRangeEdit.h Message-ID: <20101110010512.E2FB22A6C12C@llvm.org> Author: stoklund Date: Tue Nov 9 19:05:12 2010 New Revision: 118661 URL: http://llvm.org/viewvc/llvm-project?rev=118661&view=rev Log: Simplify the LiveRangeEdit::canRematerializeAt() interface a bit. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp llvm/trunk/lib/CodeGen/LiveRangeEdit.h Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=118661&r1=118660&r2=118661&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Nov 9 19:05:12 2010 @@ -167,9 +167,8 @@ return true; } - LiveRangeEdit::Remat RM = edit_->canRematerializeAt(OrigVNI, UseIdx, false, - lis_); - if (!RM) { + LiveRangeEdit::Remat RM(OrigVNI); + if (!edit_->canRematerializeAt(RM, UseIdx, false, lis_)) { usedValues_.insert(OrigVNI); DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); return false; Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=118661&r1=118660&r2=118661&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Tue Nov 9 19:05:12 2010 @@ -88,36 +88,29 @@ return true; } -LiveRangeEdit::Remat LiveRangeEdit::canRematerializeAt(VNInfo *ParentVNI, - SlotIndex UseIdx, - bool cheapAsAMove, - LiveIntervals &lis) { +bool LiveRangeEdit::canRematerializeAt(Remat &RM, + SlotIndex UseIdx, + bool cheapAsAMove, + LiveIntervals &lis) { assert(scannedRemattable_ && "Call anyRematerializable first"); - Remat RM = { 0, 0 }; - - // We could remat an undefined value as IMPLICIT_DEF, but all that should have - // been taken care of earlier. - if (!(RM.ParentVNI = parent_.getVNInfoAt(UseIdx))) - return RM; // Use scanRemattable info. if (!remattable_.count(RM.ParentVNI)) - return RM; + return false; // No defining instruction. - MachineInstr *OrigMI = lis.getInstructionFromIndex(RM.ParentVNI->def); - assert(OrigMI && "Defining instruction for remattable value disappeared"); + RM.OrigMI = lis.getInstructionFromIndex(RM.ParentVNI->def); + assert(RM.OrigMI && "Defining instruction for remattable value disappeared"); // If only cheap remats were requested, bail out early. - if (cheapAsAMove && !OrigMI->getDesc().isAsCheapAsAMove()) - return RM; + if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove()) + return false; // Verify that all used registers are available with the same values. - if (!allUsesAvailableAt(OrigMI, RM.ParentVNI->def, UseIdx, lis)) - return RM; + if (!allUsesAvailableAt(RM.OrigMI, RM.ParentVNI->def, UseIdx, lis)) + return false; - RM.OrigMI = OrigMI; - return RM; + return true; } SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB, Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.h?rev=118661&r1=118660&r2=118661&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.h (original) +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.h Tue Nov 9 19:05:12 2010 @@ -94,16 +94,16 @@ struct Remat { VNInfo *ParentVNI; // parent_'s value at the remat location. MachineInstr *OrigMI; // Instruction defining ParentVNI. - operator bool() const { return OrigMI; } + explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {} }; /// canRematerializeAt - Determine if ParentVNI can be rematerialized at /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. /// When cheapAsAMove is set, only cheap remats are allowed. - Remat canRematerializeAt(VNInfo *ParentVNI, - SlotIndex UseIdx, - bool cheapAsAMove, - LiveIntervals &lis); + bool canRematerializeAt(Remat &RM, + SlotIndex UseIdx, + bool cheapAsAMove, + LiveIntervals &lis); /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an /// instruction into MBB before MI. The new instruction is mapped, but From isanbard at gmail.com Tue Nov 9 19:07:54 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 10 Nov 2010 01:07:54 -0000 Subject: [llvm-commits] [llvm] r118662 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20101110010755.05ECD2A6C12C@llvm.org> Author: void Date: Tue Nov 9 19:07:54 2010 New Revision: 118662 URL: http://llvm.org/viewvc/llvm-project?rev=118662&view=rev Log: Emit a '!' if this is a "writeback" register or memory address. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118662&r1=118661&r2=118662&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 19:07:54 2010 @@ -382,10 +382,10 @@ getImm()->print(OS); break; case Memory: - OS << ""; + OS << "" : "!>"); break; case Register: - OS << ""; + OS << "" : "!>"); break; case RegisterList: { OS << " Author: aggarwa4 Date: Tue Nov 9 19:17:59 2010 New Revision: 118663 URL: http://llvm.org/viewvc/llvm-project?rev=118663&view=rev Log: More testcases. Must fix td to handle these. Added: poolalloc/trunk/test/dsa/td/checkIncomplete.ll poolalloc/trunk/test/dsa/td/checkIncomplete1.ll Added: poolalloc/trunk/test/dsa/td/checkIncomplete.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/checkIncomplete.ll?rev=118663&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/checkIncomplete.ll (added) +++ poolalloc/trunk/test/dsa/td/checkIncomplete.ll Tue Nov 9 19:17:59 2010 @@ -0,0 +1,39 @@ +;RUN: dsaopt %s -dsa-stdlib -analyze -verify-flags "print:buffer+I" +;RUN: dsaopt %s -dsa-stdlib -analyze -verify-flags "@buf+I" + +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "print:buffer+I" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "@buf-I" + +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "print:buffer-I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "@buf-I" + +; global buf, is passed as argument to print. It should not be marked incomplete after td + +; ModuleID = 'checkIncomplete.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + + at buf = internal global [30 x i8] zeroinitializer, align 16 ; <[30 x i8]*> [#uses=1] + +define internal void @print(i8* %buffer) nounwind { +entry: + %buffer_addr = alloca i8* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i8* %buffer, i8** %buffer_addr + %0 = load i8** %buffer_addr, align 8 ; [#uses=1] + %1 = getelementptr inbounds i8* %0, i64 0 ; [#uses=1] + store i8 97, i8* %1, align 1 + br label %return + +return: ; preds = %entry + ret void +} + +define void @main() nounwind { +entry: + call void @print(i8* getelementptr inbounds ([30 x i8]* @buf, i64 0, i64 0)) nounwind + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/td/checkIncomplete1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/checkIncomplete1.ll?rev=118663&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/checkIncomplete1.ll (added) +++ poolalloc/trunk/test/dsa/td/checkIncomplete1.ll Tue Nov 9 19:17:59 2010 @@ -0,0 +1,64 @@ +;RUN: dsaopt %s -dsa-stdlib -analyze -verify-flags "testfunc:f+I" +;RUN: dsaopt %s -dsa-stdlib -analyze -verify-flags "main:F+I" + +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "testfunc:f+I" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:F+I" + +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "testfunc:f+IE" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:F+IE" + +; ModuleID = 'fptr.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +; F is passes as argument to testfunc. But since F is incomplete, f should remain incomplete after td. +define internal void @A(void (i8*)** %f) nounwind { +entry: + %f_addr = alloca void (i8*)** ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store void (i8*)** %f, void (i8*)*** %f_addr + br label %return + +return: ; preds = %entry + ret void +} + +define internal void @B(void (i8*)** %f) nounwind { +entry: + %f_addr = alloca void (i8*)** ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store void (i8*)** %f, void (i8*)*** %f_addr + br label %return + +return: ; preds = %entry + ret void +} + +define internal void @testfunc(void (i8*)** %f) nounwind { +entry: + %f_addr = alloca void (i8*)** ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store void (i8*)** %f, void (i8*)*** %f_addr + store void (i8*)** bitcast (void (void (i8*)**)* @B to void (i8*)**), void (i8*)*** %f_addr, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=1] + %F = alloca void (i8*)* ; [#uses=4] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store void (i8*)* bitcast (void (void (i8*)**)* @A to void (i8*)*), void (i8*)** %F, align 8 + %0 = load void (i8*)** %F, align 8 ; [#uses=1] + %F1 = bitcast void (i8*)** %F to i8* ; [#uses=1] + call void %0(i8* %F1) nounwind + call void @testfunc(void (i8*)** %F) nounwind + br label %return + +return: ; preds = %entry + %retval2 = load i32* %retval ; [#uses=1] + ret i32 %retval2 +} From aggarwa4 at illinois.edu Tue Nov 9 19:20:05 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 10 Nov 2010 01:20:05 -0000 Subject: [llvm-commits] [poolalloc] r118664 - /poolalloc/trunk/lib/DSA/TopDownClosure.cpp Message-ID: <20101110012005.668742A6C12C@llvm.org> Author: aggarwa4 Date: Tue Nov 9 19:20:05 2010 New Revision: 118664 URL: http://llvm.org/viewvc/llvm-project?rev=118664&view=rev Log: Move the code that propogates information to the globals graph to be after the Incomplete/External flag calculation. This ensures that the globals graph does not get I, in the cases when the graph itself does not mark I on the same node in its graph. This was happening when a global was merged with a formal parameter to the function, which was I till the end of TD for that graph. Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=118664&r1=118663&r2=118664&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Tue Nov 9 19:20:05 2010 @@ -86,7 +86,6 @@ init(useEQBU ? &getAnalysis() : &getAnalysis(), true, true, true, false); - // Figure out which functions must not mark their arguments complete because // they are accessible outside this compilation unit. Currently, these // arguments are functions which are reachable by incomplete or external @@ -249,6 +248,7 @@ DEBUG(errs() << "[TD] Inlining callers into '" << DSG->getFunctionNames() << "'\n"); + DSG->maskIncompleteMarkers(); // Iteratively inline caller graphs into this graph. while (!EdgesFromCaller.empty()) { DSGraph* CallerGraph = EdgesFromCaller.back().CallerGraph; @@ -286,20 +286,9 @@ } - { - DSGraph* GG = DSG->getGlobalsGraph(); - ReachabilityCloner RC(GG, DSG, - DSGraph::DontCloneCallNodes | - DSGraph::DontCloneAuxCallNodes); - for (DSScalarMap::global_iterator - GI = DSG->getScalarMap().global_begin(), - E = DSG->getScalarMap().global_end(); GI != E; ++GI) - RC.getClonedNH(DSG->getNodeForValue(*GI)); - } // Next, now that this graph is finalized, we need to recompute the // incompleteness markers for this graph and remove unreachable nodes. - DSG->maskIncompleteMarkers(); // If any of the functions is externally callable, treat everything in its // SCC as externally callable. @@ -323,6 +312,17 @@ = isExternallyCallable ? DSGraph::MarkFormalsExternal : DSGraph::DontMarkFormalsExternal; DSG->computeExternalFlags(ExtFlags); + { + DSGraph* GG = DSG->getGlobalsGraph(); + ReachabilityCloner RC(GG, DSG, + DSGraph::DontCloneCallNodes | + DSGraph::DontCloneAuxCallNodes); + for (DSScalarMap::global_iterator + GI = DSG->getScalarMap().global_begin(), + E = DSG->getScalarMap().global_end(); GI != E; ++GI) + RC.getClonedNH(DSG->getNodeForValue(*GI)); + } + // // Delete dead nodes. Treat globals that are unreachable as dead also. // From dalej at apple.com Tue Nov 9 19:30:56 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 10 Nov 2010 01:30:56 -0000 Subject: [llvm-commits] [llvm] r118665 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineShifts.cpp test/Transforms/InstCombine/pr8547.ll Message-ID: <20101110013057.040B82A6C12C@llvm.org> Author: johannes Date: Tue Nov 9 19:30:56 2010 New Revision: 118665 URL: http://llvm.org/viewvc/llvm-project?rev=118665&view=rev Log: When checking that the necessary bits are zero in order to reduce ((x<<30)>>24) to x<<6, check the correct bits. PR 8547. Added: llvm/trunk/test/Transforms/InstCombine/pr8547.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=118665&r1=118664&r2=118665&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Tue Nov 9 19:30:56 2010 @@ -131,9 +131,9 @@ // We can turn shl(c1)+shr(c2) -> shl(c3)+and(c4), but it isn't // profitable unless we know the and'd out bits are already zero. if (CI->getZExtValue() > NumBits) { - unsigned HighBits = CI->getZExtValue() - NumBits; + unsigned LowBits = TypeWidth - CI->getZExtValue(); if (MaskedValueIsZero(I->getOperand(0), - APInt::getHighBitsSet(TypeWidth, HighBits))) + APInt::getLowBitsSet(TypeWidth, NumBits) << LowBits)) return true; } Added: llvm/trunk/test/Transforms/InstCombine/pr8547.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/pr8547.ll?rev=118665&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/pr8547.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/pr8547.ll Tue Nov 9 19:30:56 2010 @@ -0,0 +1,26 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +; Converting the 2 shifts to SHL 6 without the AND is wrong. PR 8547. + + at g_2 = global i32 0, align 4 + at .str = constant [10 x i8] c"g_2 = %d\0A\00" + +declare i32 @printf(i8*, ...) + +define i32 @main() nounwind { +codeRepl: + br label %for.cond + +for.cond: ; preds = %for.cond, %codeRepl + %storemerge = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ] + store i32 %storemerge, i32* @g_2, align 4 + %shl = shl i32 %storemerge, 30 + %conv2 = lshr i32 %shl, 24 +; CHECK: %0 = shl i32 %storemerge, 6 +; CHECK: %conv2 = and i32 %0, 64 + %tobool = icmp eq i32 %conv2, 0 + br i1 %tobool, label %for.cond, label %codeRepl2 + +codeRepl2: ; preds = %for.cond + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i32 %conv2) nounwind + ret i32 0 +} \ No newline at end of file From geek4civic at gmail.com Tue Nov 9 20:02:20 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 10 Nov 2010 11:02:20 +0900 Subject: [llvm-commits] [Review request] test: Add the new feature "loadable_module" In-Reply-To: References: Message-ID: Good morning, Rafael. Thank you to give me comments. 2010/11/10 Rafael Esp?ndola : > I think these patches are fine. Do the generated modules work on > windows? I had the impression that on windowns plugins could not > access symbols from the main executable. "bugpoint -load BugpointPasses" works fine on Cygming. And I used to build and test my passes as DLL, they worked ;) Win32 DLL has restrictions (against elf.so) - "Undefined" symbols are prohibited. - To import entries, exporter's name (eg. bugpoint.exe) should be known. In theory, PECOFF executable can export entries. (unittests/JITTests.exe should do). Consider bugpoint.exe exported some entries for BugpointPasses.dll. BugpointPasses.dll would rely on bugpoint.exe and would not unavailable with opt.exe. Who would be happy? :) Usually, when "loadable module" capability is needed on win32, we can split exporter to the big DLL. eg. perl5*.dll, python2*.dll, llvm*.dll, &c. "loadable modules" can depend on those DLLs, not on main executables. It is why ENABLE_SHARED is needed on win32 to be capable of loadable module. ps. a few patches will be needed to pass test/bugpoint. llvm*.dll is not on lib/ but on bin/. for convenience. ...Takumi From bruno.cardoso at gmail.com Tue Nov 9 20:13:22 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 10 Nov 2010 02:13:22 -0000 Subject: [llvm-commits] [llvm] r118667 - in /llvm/trunk/lib/Target/Mips: Mips.td MipsInstrInfo.td Message-ID: <20101110021322.F30CA2A6C12C@llvm.org> Author: bruno Date: Tue Nov 9 20:13:22 2010 New Revision: 118667 URL: http://llvm.org/viewvc/llvm-project?rev=118667&view=rev Log: Add clo instruction. Patch by Akira Hatanaka (ahatanaka at mips.com) with some minor tweaks Modified: llvm/trunk/lib/Target/Mips/Mips.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=118667&r1=118666&r2=118667&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips.td (original) +++ llvm/trunk/lib/Target/Mips/Mips.td Tue Nov 9 20:13:22 2010 @@ -59,7 +59,8 @@ def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", "Mips2 ISA Support">; def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", - "Mips32 ISA Support", [FeatureCondMov]>; + "Mips32 ISA Support", + [FeatureCondMov, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", [FeatureMips32, FeatureSEInReg]>; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=118667&r1=118666&r2=118667&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Nov 9 20:13:22 2010 @@ -281,10 +281,13 @@ instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>; // Count Leading Ones/Zeros in Word -class CountLeading func, string instr_asm, SDNode CountOp>: +class CountLeading func, string instr_asm, list pattern>: FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src), - !strconcat(instr_asm, "\t$dst, $src"), - [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>; + !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>, + Requires<[HasBitCount]> { + let shamt = 0; + let rt = rd; +} // Sign Extend in Register. class SignExtInReg func, string instr_asm, ValueType vt>: @@ -446,10 +449,10 @@ } /// Count Leading -let Predicates = [HasBitCount] in { - let rt = 0 in - def CLZ : CountLeading<0b010110, "clz", ctlz>; -} +def CLZ : CountLeading<0b100000, "clz", + [(set CPURegs:$dst, (ctlz CPURegs:$src))]>; +def CLO : CountLeading<0b100001, "clo", + [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>; /// Byte Swap let Predicates = [HasSwap] in { From bruno.cardoso at gmail.com Tue Nov 9 20:22:44 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 10 Nov 2010 02:22:44 -0000 Subject: [llvm-commits] [llvm] r118668 - /llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll Message-ID: <20101110022244.917DC2A6C12C@llvm.org> Author: bruno Date: Tue Nov 9 20:22:44 2010 New Revision: 118668 URL: http://llvm.org/viewvc/llvm-project?rev=118668&view=rev Log: Add a test to the previous added clo instruction. Patch by Akira again Added: llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll Added: llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll?rev=118668&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll (added) +++ llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll Tue Nov 9 20:22:44 2010 @@ -0,0 +1,33 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: clz $2, $4 +define i32 @t1(i32 %X) nounwind readnone { +entry: + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X) + ret i32 %tmp1 +} + +declare i32 @llvm.ctlz.i32(i32) nounwind readnone + +; CHECK: clz $2, $4 +define i32 @t2(i32 %X) nounwind readnone { +entry: + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X) + ret i32 %tmp1 +} + +; CHECK: clo $2, $4 +define i32 @t3(i32 %X) nounwind readnone { +entry: + %neg = xor i32 %X, -1 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg) + ret i32 %tmp1 +} + +; CHECK: clo $2, $4 +define i32 @t4(i32 %X) nounwind readnone { +entry: + %neg = xor i32 %X, -1 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg) + ret i32 %tmp1 +} From echristo at apple.com Tue Nov 9 20:53:04 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 9 Nov 2010 18:53:04 -0800 Subject: [llvm-commits] [PATCH] Add dragonegg support as llvm-gcc frontend in llvm-core and test-suite In-Reply-To: <4CD9E1DA.1070001@fim.uni-passau.de> References: <4CD9E1DA.1070001@fim.uni-passau.de> Message-ID: <6800A9D4-9722-4218-85DE-D8A865047583@apple.com> On Nov 9, 2010, at 4:05 PM, Tobias Grosser wrote: > OK to commit those patches? Sure, seems reasonable. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101109/96173a30/attachment.html From grosbach at apple.com Tue Nov 9 21:26:08 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 10 Nov 2010 03:26:08 -0000 Subject: [llvm-commits] [llvm] r118671 - in /llvm/trunk: include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101110032608.0E7C32A6C12C@llvm.org> Author: grosbach Date: Tue Nov 9 21:26:07 2010 New Revision: 118671 URL: http://llvm.org/viewvc/llvm-project?rev=118671&view=rev Log: Update ARMConstantPoolValue to not use a modifier string. Use an explicit VariantKind marker to indicate the additional information necessary. Update MC to handle the new Kinds. rdar://8647623 Modified: llvm/trunk/include/llvm/MC/MCExpr.h llvm/trunk/lib/MC/MCExpr.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/include/llvm/MC/MCExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=118671&r1=118670&r2=118671&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCExpr.h (original) +++ llvm/trunk/include/llvm/MC/MCExpr.h Tue Nov 9 21:26:07 2010 @@ -141,9 +141,15 @@ VK_TLSLDM, VK_TPOFF, VK_DTPOFF, - VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the asm file) - VK_ARM_LO16, // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the asm file) - VK_ARM_PLT, // ARM-style PLT symbol references. i.e., (PLT) instead of @PLT + VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file) + VK_ARM_LO16, // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .w file) + // FIXME: We'd really like to use the generic Kinds listed above for these. + VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT + VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF + VK_ARM_GOT, + VK_ARM_GOTOFF, + VK_ARM_TPOFF, + VK_ARM_GOTTPOFF, VK_TLVP // Mach-O thread local variable relocation }; Modified: llvm/trunk/lib/MC/MCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=118671&r1=118670&r2=118671&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCExpr.cpp (original) +++ llvm/trunk/lib/MC/MCExpr.cpp Tue Nov 9 21:26:07 2010 @@ -51,7 +51,12 @@ else OS << Sym; - if (SRE.getKind() == MCSymbolRefExpr::VK_ARM_PLT) + if (SRE.getKind() == MCSymbolRefExpr::VK_ARM_PLT || + SRE.getKind() == MCSymbolRefExpr::VK_ARM_TLSGD || + SRE.getKind() == MCSymbolRefExpr::VK_ARM_GOT || + SRE.getKind() == MCSymbolRefExpr::VK_ARM_GOTOFF || + SRE.getKind() == MCSymbolRefExpr::VK_ARM_TPOFF || + SRE.getKind() == MCSymbolRefExpr::VK_ARM_GOTTPOFF) OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); else if (SRE.getKind() != MCSymbolRefExpr::VK_None && SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 && @@ -185,6 +190,11 @@ case VK_ARM_HI16: return ":upper16:"; case VK_ARM_LO16: return ":lower16:"; case VK_ARM_PLT: return "(PLT)"; + case VK_ARM_GOT: return "(GOT)"; + case VK_ARM_GOTOFF: return "(GOTOFF)"; + case VK_ARM_TPOFF: return "(tpoff)"; + case VK_ARM_GOTTPOFF: return "(gottpoff)"; + case VK_ARM_TLSGD: return "(tldgd)"; case VK_TLVP: return "TLVP"; } } Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118671&r1=118670&r2=118671&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Nov 9 21:26:07 2010 @@ -603,6 +603,20 @@ return Label; } +static MCSymbolRefExpr::VariantKind +getModifierVariantKind(ARMCP::ARMCPModifier Modifier) { + switch (Modifier) { + default: llvm_unreachable("Unknown modifier!"); + case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None; + case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD; + case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF; + case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF; + case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT; + case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF; + } + return MCSymbolRefExpr::VK_None; +} + void ARMAsmPrinter:: EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); @@ -642,55 +656,32 @@ // Create an MCSymbol for the reference. MCSymbol *MCSym = OutContext.GetOrCreateSymbol(OS.str()); - const MCExpr *Expr = MCSymbolRefExpr::Create(MCSym, OutContext); - - // FIXME: Model the whole expression an an MCExpr and we can get rid - // of this hasRawTextSupport() clause and just do an EmitValue(). - if (OutStreamer.hasRawTextSupport()) { - if (ACPV->hasModifier()) OS << "(" << ACPV->getModifierText() << ")"; - if (ACPV->getPCAdjustment() != 0) { - OS << "-(" << MAI->getPrivateGlobalPrefix() << "PC" - << getFunctionNumber() << "_" << ACPV->getLabelId() - << "+" << (unsigned)ACPV->getPCAdjustment(); - if (ACPV->mustAddCurrentAddress()) - OS << "-."; - OS << ')'; - } - const char *DataDirective = 0; - switch (Size) { - case 1: DataDirective = MAI->getData8bitsDirective(0); break; - case 2: DataDirective = MAI->getData16bitsDirective(0); break; - case 4: DataDirective = MAI->getData32bitsDirective(0); break; - default: assert(0 && "Unknown CPV size"); - } - Twine Text(DataDirective, OS.str()); - OutStreamer.EmitRawText(Text); - } else { - assert(!ACPV->hasModifier() && - "ARM binary streamer of non-trivial constant pool value!"); - if (ACPV->getPCAdjustment()) { - MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(), - getFunctionNumber(), - ACPV->getLabelId(), - OutContext); - const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext); - PCRelExpr = - MCBinaryExpr::CreateAdd(PCRelExpr, - MCConstantExpr::Create(ACPV->getPCAdjustment(), - OutContext), - OutContext); - if (ACPV->mustAddCurrentAddress()) { - // We want "( - .)", but MC doesn't have a concept of the '.' - // label, so just emit a local label end reference that instead. - MCSymbol *DotSym = OutContext.CreateTempSymbol(); - OutStreamer.EmitLabel(DotSym); - const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); - Expr = MCBinaryExpr::CreateSub(Expr, DotExpr, OutContext); - } - Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext); + const MCExpr *Expr = + MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()), + OutContext); + + if (ACPV->getPCAdjustment()) { + MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(), + getFunctionNumber(), + ACPV->getLabelId(), + OutContext); + const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext); + PCRelExpr = + MCBinaryExpr::CreateAdd(PCRelExpr, + MCConstantExpr::Create(ACPV->getPCAdjustment(), + OutContext), + OutContext); + if (ACPV->mustAddCurrentAddress()) { + // We want "( - .)", but MC doesn't have a concept of the '.' + // label, so just emit a local label end reference that instead. + MCSymbol *DotSym = OutContext.CreateTempSymbol(); + OutStreamer.EmitLabel(DotSym); + const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); + PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext); } - OutStreamer.EmitValue(Expr, Size); + Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext); } + OutStreamer.EmitValue(Expr, Size); } void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) { From geek4civic at gmail.com Tue Nov 9 22:15:00 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 10 Nov 2010 13:15:00 +0900 Subject: [llvm-commits] [PATCH] Add some options to configure for Cygming In-Reply-To: References: Message-ID: Good afternoon, Rafael. I made and reconfirmed patches. * 0002-autoconf-Add-enable-docs-to-enable-disable-buiding-a.patch > +# When ENABLE_DOXYGEN is disabled, docs/ will not be built > +ENABLE_DOCS = @ENABLE_DOCS@ > > Comment looks wrong. Fixed. Thank you to point out. +# When ENABLE_DOCS is disabled, docs/ will not be built. +ENABLE_DOCS = @ENABLE_DOCS@ * 0004-autoconf-PR7874-Add-disable-pthreads-to-suppress-det.patch * 0006-autoconf-Add-disable-embed-stdcxx-to-suppress-linkin.patch They are as same as last. * 0001-Explicit-autotools-version.patch.gz It is not intended to commit. I installed autotools locally with suffix -x.xx. It might be dubious for libtool, but anyway, I can generate locally same configure on ToT with this patch. * 0003-configure-Regenerated-for-enable-docs.patch.gz * 0005-configure-Regenerated-for-disable-pthreads.patch.gz * 0007-configure-Regenerated-for-disable-embed-stdcxx.patch.gz They are attached for consistency. When I commit them, may I commit generated configure(s) separately or fused? ...Takumi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Explicit-autotools-version.patch.gz Type: application/x-gzip Size: 853 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment.gz -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-autoconf-Add-enable-docs-to-enable-disable-buiding-a.patch Type: application/octet-stream Size: 2078 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-configure-Regenerated-for-enable-docs.patch.gz Type: application/x-gzip Size: 1441 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment-0001.gz -------------- next part -------------- A non-text attachment was scrubbed... Name: 0004-autoconf-PR7874-Add-disable-pthreads-to-suppress-det.patch Type: application/octet-stream Size: 2257 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment-0001.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0005-configure-Regenerated-for-disable-pthreads.patch.gz Type: application/x-gzip Size: 2205 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment-0002.gz -------------- next part -------------- A non-text attachment was scrubbed... Name: 0006-autoconf-Add-disable-embed-stdcxx-to-suppress-linkin.patch Type: application/octet-stream Size: 2643 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment-0002.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0007-configure-Regenerated-for-disable-embed-stdcxx.patch.gz Type: application/x-gzip Size: 1513 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/622e9cdc/attachment-0003.gz From geek4civic at gmail.com Wed Nov 10 00:14:13 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 10 Nov 2010 15:14:13 +0900 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: <87d3qezzud.fsf@telefonica.net> References: <87d3qezzud.fsf@telefonica.net> Message-ID: Good afternoon, Oscar. I attached updated version of patches. Checked on CentOS5/2.8.2, mingw, msys, msvs8 and msvs10. 2010/11/9 ?scar Fuentes : > Unless I'm missing something on how cmake processes options, there is an > use-before-first-assignment problem here. > > LLVM_LIT_ARGS is defined in test/CMakeLists.txt, but it is used in > tools/clang/test/CMakeLists.txt, which is processed before > test/CMakeLists.txt. If the user sets LLVM_LIT_ARGS from the cmake > command line there is no problem, but if he doesn't, the default value > you set in test/CMakeLists.txt is not used for clang. > > You can test this by starting from a new build directory without using > LLVM_LIT_ARGS on the command line, and checkig if the -sv argument is > passed to lit on the clang tests. Sure. I reconfirmed what I was wrong. I have not realized that because I prefer "make edit_cache" :p > The variable is defined on a LLVM/Clang CMakeLists.txt file, so it > belongs to the LLVM namespace. The LIT namespace would make sense iif > LIT had its own CMakeLists.txt files. IMO. I see. > I'm wary by the use of separate_arguments. Why do you need it and why > UNIX_COMMAND was chosen? My intention is simply to separate simple options to list, not to separate complex arguments. It seems UNIX_COMMAND works fine. I may choose whatever works. What would be better? Without separation, we will see lit.py "-sv --no-progress-bar". > On the clang part, the variable CLANG_TEST_EXTRA_ARGS is referenced by > > set(CLANG_TEST_EXTRA_ARGS) > > (which is equivalent to unsetting it) and then you > > + ?list(APPEND CLANG_TEST_EXTRA_ARGS ${LIT_ARGS}) > > It would be clearer if the set(CLANG_TEST_EXTRA_ARGS) were replaced by > > + ?set(CLANG_TEST_EXTRA_ARGS ${LIT_ARGS}) > > or replacing the occurrences of CLANG_TEST_EXTRA_ARGS by LIT_ARGS > altogether, as it no longer holds the "extra args" but all the > configurable lit args for clang. I intended to minimize changes and append LLVM_LIT_ARGS to tail of EXTRA_ARGS. It makes sense not to use CLANG_TEST_EXTRA_ARGS. > Also, it would be a good thing to add documentation for the > LLVM_LIT_ARGS variable in docs/CMake.html. I added an entry to docs/CMake.html. Feel free to add something or rewrite whole. ...Takumi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-CMake-Add-the-new-option-LLVM_LIT_ARGS.patch Type: application/octet-stream Size: 2566 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/647cf542/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-test-CMakeLists.txt-Use-LLVM_LIT_ARGS-and-remove-red.patch Type: application/octet-stream Size: 2598 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/647cf542/attachment-0001.obj From clattner at apple.com Wed Nov 10 01:32:01 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 9 Nov 2010 23:32:01 -0800 Subject: [llvm-commits] [llvm] r118639 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCSectionELF.h lib/MC/ELFObjectWriter.cpp lib/MC/MCContext.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCSectionELF.cpp In-Reply-To: <20101109223744.D4B022A6C12D@llvm.org> References: <20101109223744.D4B022A6C12D@llvm.org> Message-ID: On Nov 9, 2010, at 2:37 PM, Rafael Espindola wrote: > Author: rafael > Date: Tue Nov 9 16:37:44 2010 > New Revision: 118639 > > URL: http://llvm.org/viewvc/llvm-project?rev=118639&view=rev > Log: > Remove IsExplicit. It was always false. Nice! One more hack dissolves away :) -Chris From baldrick at free.fr Wed Nov 10 01:46:36 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 07:46:36 -0000 Subject: [llvm-commits] [llvm] r118677 - /llvm/trunk/include/llvm/Support/MemoryBuffer.h Message-ID: <20101110074636.9E13D2A6C12C@llvm.org> Author: baldrick Date: Wed Nov 10 01:46:36 2010 New Revision: 118677 URL: http://llvm.org/viewvc/llvm-project?rev=118677&view=rev Log: There is no EndPtr anymore - reinterpret the original comment in terms of InputData. Modified: llvm/trunk/include/llvm/Support/MemoryBuffer.h Modified: llvm/trunk/include/llvm/Support/MemoryBuffer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MemoryBuffer.h?rev=118677&r1=118676&r2=118677&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/MemoryBuffer.h (original) +++ llvm/trunk/include/llvm/Support/MemoryBuffer.h Wed Nov 10 01:46:36 2010 @@ -71,13 +71,13 @@ struct stat *FileInfo = 0); /// getMemBuffer - Open the specified memory range as a MemoryBuffer. Note - /// that EndPtr[0] must be a null byte and be accessible! + /// that InputData must be null terminated. static MemoryBuffer *getMemBuffer(StringRef InputData, StringRef BufferName = ""); /// getMemBufferCopy - Open the specified memory range as a MemoryBuffer, - /// copying the contents and taking ownership of it. This has no requirements - /// on EndPtr[0]. + /// copying the contents and taking ownership of it. InputData does not + /// have to be null terminated. static MemoryBuffer *getMemBufferCopy(StringRef InputData, StringRef BufferName = ""); From baldrick at free.fr Wed Nov 10 02:07:23 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 09:07:23 +0100 Subject: [llvm-commits] [llvm] r118614 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h In-Reply-To: <20101109194855.35ADC2A6C12C@llvm.org> References: <20101109194855.35ADC2A6C12C@llvm.org> Message-ID: <4CDA52BB.8040301@free.fr> Hi Dan, > + // AccessesArgumentsReadonly - This function loads through function > + // arguments and does not perform any non-local stores or volatile > + // loads. how does this differ from OnlyReadsMemory? Is it that non-local loads are *only* via function arguments? If so, I think the description could be clearer. Ciao, Duncan. From geek4civic at gmail.com Wed Nov 10 02:21:17 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 10 Nov 2010 17:21:17 +0900 Subject: [llvm-commits] [Review request] [PR8225] Add exports to unittests/JITTests.exe on win32(s) Message-ID: Hello konbanwa. I made a patch for unittests/CMakeLists.txt to pass JITTests.exe. [ PASSED ] 25 tests. With GNU ld/PECOFF, --export-all-symbols can export all globals. For MSVC, I simply gave JITTests.def to source lists. It seems *.def is ignored on cmake/mingw/msys. Happy testing ...Takumi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-unittests-CMakeLists.txt-PR8225-Tweak-linking-JITTes.patch Type: application/octet-stream Size: 1746 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/f73c471b/attachment-0001.obj From baldrick at free.fr Wed Nov 10 02:30:40 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 09:30:40 +0100 Subject: [llvm-commits] [llvm] r118660 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/IPA/GlobalsModRef.cpp lib/Analysis/TypeBasedAliasAnalysis.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/Transforms/FunctionAttrs/2008-09-03-ReadNone.ll test/Transforms/FunctionAttrs/2008-09-03-ReadOnly.ll In-Reply-To: <20101110010218.BC1E62A6C12C@llvm.org> References: <20101110010218.BC1E62A6C12C@llvm.org> Message-ID: <4CDA5830.1090405@free.fr> Hi Dan, > --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) > +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Nov 9 19:02:18 2010 > @@ -175,6 +175,9 @@ > /// > enum ModRefResult { NoModRef = 0, Ref = 1, Mod = 2, ModRef = 3 }; > > + /// These values define additional bits used to define the > + /// ModRefBehavior values. > + enum { Nowhere = 0, ArgumentPointees = 4, Anywhere = 8 | ArgumentPointees }; how about adding some accessors for extracting the location and modref parts? > + if (!(MRB& AliasAnalysis::Anywhere& > + ~AliasAnalysis::ArgumentPointees)) { That would make this kind of thing ^ more readable. Ciao, Duncan. From geek4civic at gmail.com Wed Nov 10 02:37:47 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 10 Nov 2010 08:37:47 -0000 Subject: [llvm-commits] [llvm] r118678 - /llvm/trunk/lib/System/Win32/Process.inc Message-ID: <20101110083747.9FE722A6C12D@llvm.org> Author: chapuni Date: Wed Nov 10 02:37:47 2010 New Revision: 118678 URL: http://llvm.org/viewvc/llvm-project?rev=118678&view=rev Log: Win32/Process.inc: [PR8527] Process::FileDescriptorIsDisplayed(fd) should not check by FILE_TYPE_CHAR. It must be better to check it with Console API. The special file "NUL" is FILE_TYPE_CHAR with GetFileType(h). It was treated as display device and discarding output to NUL had failed. (eg. opt -o nul) Modified: llvm/trunk/lib/System/Win32/Process.inc Modified: llvm/trunk/lib/System/Win32/Process.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Process.inc?rev=118678&r1=118677&r2=118678&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Process.inc (original) +++ llvm/trunk/lib/System/Win32/Process.inc Wed Nov 10 02:37:47 2010 @@ -132,7 +132,8 @@ } bool Process::FileDescriptorIsDisplayed(int fd) { - return GetFileType((HANDLE)_get_osfhandle(fd)) == FILE_TYPE_CHAR; + DWORD Mode; // Unused + return (GetConsoleMode((HANDLE)_get_osfhandle(fd), &Mode) != 0); } unsigned Process::StandardOutColumns() { From baldrick at free.fr Wed Nov 10 07:00:08 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 13:00:08 -0000 Subject: [llvm-commits] [llvm] r118679 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20101110130008.AEC322A6C12C@llvm.org> Author: baldrick Date: Wed Nov 10 07:00:08 2010 New Revision: 118679 URL: http://llvm.org/viewvc/llvm-project?rev=118679&view=rev Log: Simplify binary operations where one operand is a select instruction. The simplifications performed here never create new instructions, they only return existing instructions (or a constant), and so are always a win. In theory they should transform (for example) %z = and i32 %x, %y %s = select i1 %cond, i32 %y, i32 %z %r = and i32 %x, %s into %r = and i32 %x, y but in practice they get into a fight with instcombine, and lose. Unfortunately instcombine does a poor job in this case. Nonetheless I'm committing this transform to make it easier to discuss what to do to make peace with instcombine. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=118679&r1=118678&r2=118679&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Nov 10 07:00:08 2010 @@ -21,6 +21,100 @@ using namespace llvm; using namespace llvm::PatternMatch; +/// ThreadBinOpOverSelect - In the case of a binary operation with a select +/// instruction as an operand, try to simplify the binop by seeing whether +/// evaluating it on both branches of the select results in the same value. +/// Returns the common value if so, otherwise returns null. +static Value *ThreadBinOpOverSelect(unsigned Opcode, Value *LHS, Value *RHS, + const TargetData *TD) { + SelectInst *SI; + if (isa(LHS)) { + SI = cast(LHS); + } else { + assert(isa(RHS) && "No select instruction operand!"); + SI = cast(RHS); + } + + // Evaluate the BinOp on the true and false branches of the select. + Value *TV; + Value *FV; + if (SI == LHS) { + TV = SimplifyBinOp(Opcode, SI->getTrueValue(), RHS, TD); + FV = SimplifyBinOp(Opcode, SI->getFalseValue(), RHS, TD); + } else { + TV = SimplifyBinOp(Opcode, LHS, SI->getTrueValue(), TD); + FV = SimplifyBinOp(Opcode, LHS, SI->getFalseValue(), TD); + } + + // If they simplified to the same value, then return the common value. + // If they both failed to simplify then return null. + if (TV == FV) + return TV; + + // If one branch simplified to undef, return the other one. + if (TV && isa(TV)) + return FV; + if (FV && isa(FV)) + return TV; + + // If applying the operation did not change the true and false select values, + // then the result of the binop is the select itself. + if (TV == SI->getTrueValue() && FV == SI->getFalseValue()) + return SI; + + // If one branch simplified and the other did not, and the simplified + // value is equal to the unsimplified one, return the simplified value. + // For example, select (cond, X, X & Z) & Z -> X & Z. + if ((FV && !TV) || (TV && !FV)) { + // Check that the simplified value has the form "X op Y" where "op" is the + // same as the original operation. + Instruction *Simplified = dyn_cast(FV ? FV : TV); + if (Simplified && Simplified->getOpcode() == Opcode) { + // The value that didn't simplify is "UnsimplifiedLHS op UnsimplifiedRHS". + // We already know that "op" is the same as for the simplified value. See + // if the operands match too. If so, return the simplified value. + Value *UnsimplifiedBranch = FV ? SI->getTrueValue() : SI->getFalseValue(); + Value *UnsimplifiedLHS = SI == LHS ? UnsimplifiedBranch : LHS; + Value *UnsimplifiedRHS = SI == LHS ? RHS : UnsimplifiedBranch; + if (Simplified->getOperand(0) == UnsimplifiedLHS && + Simplified->getOperand(1) == UnsimplifiedRHS) + return Simplified; + if (Simplified->isCommutative() && + Simplified->getOperand(1) == UnsimplifiedLHS && + Simplified->getOperand(0) == UnsimplifiedRHS) + return Simplified; + } + } + + return 0; +} + +/// ThreadCmpOverSelect - In the case of a comparison with a select instruction, +/// try to simplify the comparison by seeing whether both branches of the select +/// result in the same value. Returns the common value if so, otherwise returns +/// null. +static Value *ThreadCmpOverSelect(CmpInst::Predicate Pred, Value *LHS, + Value *RHS, const TargetData *TD) { + // Make sure the select is on the LHS. + if (!isa(LHS)) { + std::swap(LHS, RHS); + Pred = CmpInst::getSwappedPredicate(Pred); + } + assert(isa(LHS) && "Not comparing with a select instruction!"); + SelectInst *SI = cast(LHS); + + // Now that we have "cmp select(cond, TV, FV), RHS", analyse it. + // Does "cmp TV, RHS" simplify? + if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD)) + // It does! Does "cmp FV, RHS" simplify? + if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD)) + // It does! If they simplified to the same value, then use it as the + // result of the original comparison. + if (TCmp == FCmp) + return TCmp; + return 0; +} + /// SimplifyAddInst - Given operands for an Add, see if we can /// fold the result. If not, this returns null. Value *llvm::SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, @@ -116,6 +210,12 @@ (A == Op0 || B == Op0)) return Op1; + // If the operation is with the result of a select instruction, check whether + // operating on either branch of the select always yields the same value. + if (isa(Op0) || isa(Op1)) + if (Value *V = ThreadBinOpOverSelect(Instruction::And, Op0, Op1, TD)) + return V; + return 0; } @@ -185,6 +285,12 @@ (A == Op0 || B == Op0)) return Op1; + // If the operation is with the result of a select instruction, check whether + // operating on either branch of the select always yields the same value. + if (isa(Op0) || isa(Op1)) + if (Value *V = ThreadBinOpOverSelect(Instruction::Or, Op0, Op1, TD)) + return V; + return 0; } @@ -193,32 +299,6 @@ return CmpInst::makeCmpResultType(Op->getType()); } -/// ThreadCmpOverSelect - In the case of a comparison with a select instruction, -/// try to simplify the comparison by seeing whether both branches of the select -/// result in the same value. Returns the common value if so, otherwise returns -/// null. -static Value *ThreadCmpOverSelect(CmpInst::Predicate Pred, Value *LHS, - Value *RHS, const TargetData *TD) { - // Make sure the select is on the LHS. - if (!isa(LHS)) { - std::swap(LHS, RHS); - Pred = CmpInst::getSwappedPredicate(Pred); - } - assert(isa(LHS) && "Not comparing with a select instruction!"); - SelectInst *SI = cast(LHS); - - // Now that we have "cmp select(cond, TV, FV), RHS", analyse it. - // Does "cmp TV, RHS" simplify? - if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD)) - // It does! Does "cmp FV, RHS" simplify? - if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD)) - // It does! If they simplified to the same value, then use it as the - // result of the original comparison. - if (TCmp == FCmp) - return TCmp; - return 0; -} - /// SimplifyICmpInst - Given operands for an ICmpInst, see if we can /// fold the result. If not, this returns null. Value *llvm::SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS, @@ -393,8 +473,6 @@ return FalseVal; } - - return 0; } @@ -442,6 +520,13 @@ Constant *COps[] = {CLHS, CRHS}; return ConstantFoldInstOperands(Opcode, LHS->getType(), COps, 2, TD); } + + // If the operation is with the result of a select instruction, check whether + // operating on either branch of the select always yields the same value. + if (isa(LHS) || isa(RHS)) + if (Value *V = ThreadBinOpOverSelect(Opcode, LHS, RHS, TD)) + return V; + return 0; } } From bigcheesegs at gmail.com Wed Nov 10 08:57:14 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 10 Nov 2010 09:57:14 -0500 Subject: [llvm-commits] [Review request] [PR8225] Add exports to unittests/JITTests.exe on win32(s) In-Reply-To: References: Message-ID: On Wed, Nov 10, 2010 at 3:21 AM, NAKAMURA Takumi wrote: > Hello konbanwa. > > I made a patch for unittests/CMakeLists.txt to pass JITTests.exe. > > [ ?PASSED ?] 25 tests. > > With GNU ld/PECOFF, --export-all-symbols can export all globals. > For MSVC, I simply gave JITTests.def to source lists. > > It seems *.def is ignored on cmake/mingw/msys. > > > Happy testing ...Takumi > Looks good to me. Tested on Windows 7 x64 and MinGW. - Michael Spencer From baldrick at free.fr Wed Nov 10 09:04:08 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 15:04:08 -0000 Subject: [llvm-commits] [zorg] r118680 - in /zorg/trunk: buildbot/osuosl/master/config/builders.py zorg/buildbot/builders/ScriptedBuilder.py Message-ID: <20101110150408.9C3AF2A6C12C@llvm.org> Author: baldrick Date: Wed Nov 10 09:04:08 2010 New Revision: 118680 URL: http://llvm.org/viewvc/llvm-project?rev=118680&view=rev Log: The main reason for the dragonegg builders is to fail is a timeout, usually when compiling insn-attrtab.c (a huge file). Increase the timeout from 20 minutes to 60 minutes. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py zorg/trunk/zorg/buildbot/builders/ScriptedBuilder.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=118680&r1=118679&r2=118680&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Nov 10 09:04:08 2010 @@ -224,7 +224,8 @@ mode='update', baseURL='http://llvm.org/svn/llvm-project/dragonegg/', defaultBranch='trunk', workdir="dragonegg.src"),], - launcher = 'dragonegg.src/extras/buildbot_self_strap-32',), + launcher = 'dragonegg.src/extras/buildbot_self_strap-32', + timeout = 60), 'category' : 'dragonegg'}, {'name' : 'dragonegg-x86_64-linux', @@ -239,7 +240,8 @@ mode='update', baseURL='http://llvm.org/svn/llvm-project/dragonegg/', defaultBranch='trunk', workdir="dragonegg.src"),], - launcher = 'dragonegg.src/extras/buildbot_self_strap',), + launcher = 'dragonegg.src/extras/buildbot_self_strap', + timeout = 60), 'category' : 'dragonegg'}, ] Modified: zorg/trunk/zorg/buildbot/builders/ScriptedBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ScriptedBuilder.py?rev=118680&r1=118679&r2=118680&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/ScriptedBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/ScriptedBuilder.py Wed Nov 10 09:04:08 2010 @@ -8,7 +8,8 @@ build_script = None, # Build script name or common prefix. extra_args = [], # Extra args common for all steps. build_steps = [], # List of step commands. - env = {}): # Environmental variables for all steps. + env = {}, # Environmental variables for all steps. + timeout = 20): # Timeout if no activity seen (minutes). # Validate input parameters if not launcher: @@ -96,6 +97,7 @@ haltOnFailure = True, description = "Run build script", workdir = ".", - env = env)) + env = env, + timeout = timeout*60)) return f From bigcheesegs at gmail.com Wed Nov 10 09:05:39 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 10 Nov 2010 15:05:39 -0000 Subject: [llvm-commits] [llvm] r118681 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20101110150539.E34DA2A6C12C@llvm.org> Author: mspencer Date: Wed Nov 10 09:05:39 2010 New Revision: 118681 URL: http://llvm.org/viewvc/llvm-project?rev=118681&view=rev Log: System/Win32/Path: Implement isSymLink. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118681&r1=118680&r2=118681&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Wed Nov 10 09:05:39 2010 @@ -376,7 +376,15 @@ bool Path::isSymLink() const { - return false; + DWORD attributes = GetFileAttributes(path.c_str()); + + if (attributes == INVALID_FILE_ATTRIBUTES) + // There's no sane way to report this :(. + assert(0 && "GetFileAttributes returned INVALID_FILE_ATTRIBUTES"); + + // This isn't exactly what defines a NTFS symlink, but it is only true for + // paths that act like a symlink. + return attributes & FILE_ATTRIBUTE_REPARSE_POINT; } bool From bigcheesegs at gmail.com Wed Nov 10 09:05:50 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 10 Nov 2010 15:05:50 -0000 Subject: [llvm-commits] [llvm] r118682 - /llvm/trunk/include/llvm/System/Path.h Message-ID: <20101110150550.3AFF12A6C12C@llvm.org> Author: mspencer Date: Wed Nov 10 09:05:50 2010 New Revision: 118682 URL: http://llvm.org/viewvc/llvm-project?rev=118682&view=rev Log: System/Path: Update comments to match code. Modified: llvm/trunk/include/llvm/System/Path.h Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=118682&r1=118681&r2=118682&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Wed Nov 10 09:05:50 2010 @@ -105,9 +105,7 @@ static Path GetTemporaryDirectory(std::string* ErrMsg = 0); /// Construct a vector of sys::Path that contains the "standard" system - /// library paths suitable for linking into programs. This function *must* - /// return the value of LLVM_LIB_SEARCH_PATH as the first item in \p Paths - /// if that environment variable is set and it references a directory. + /// library paths suitable for linking into programs. /// @brief Construct a path to the system library directory static void GetSystemLibraryPaths(std::vector& Paths); From bigcheesegs at gmail.com Wed Nov 10 09:06:00 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 10 Nov 2010 15:06:00 -0000 Subject: [llvm-commits] [llvm] r118683 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20101110150600.4113A2A6C12C@llvm.org> Author: mspencer Date: Wed Nov 10 09:06:00 2010 New Revision: 118683 URL: http://llvm.org/viewvc/llvm-project?rev=118683&view=rev Log: Fix Whitespace. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=118683&r1=118682&r2=118683&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Wed Nov 10 09:06:00 2010 @@ -288,7 +288,7 @@ Path Path::GetLLVMDefaultConfigDir() { Path ret = GetUserHomeDirectory(); - if(!ret.appendComponent(".llvm")) + if (!ret.appendComponent(".llvm")) assert(0 && "Failed to append .llvm"); return ret; } @@ -296,11 +296,11 @@ Path Path::GetUserHomeDirectory() { char buff[MAX_PATH]; - HRESULT res = SHGetFolderPathA(NULL, - CSIDL_FLAG_CREATE | CSIDL_APPDATA, - NULL, - SHGFP_TYPE_CURRENT, - buff); + HRESULT res = SHGetFolderPathA(NULL, + CSIDL_FLAG_CREATE | CSIDL_APPDATA, + NULL, + SHGFP_TYPE_CURRENT, + buff); if (res != S_OK) assert(0 && "Failed to get user home directory"); return Path(buff); From cdavis at mymail.mines.edu Wed Nov 10 09:12:40 2010 From: cdavis at mymail.mines.edu (Charles Davis) Date: Wed, 10 Nov 2010 08:12:40 -0700 Subject: [llvm-commits] [llvm] r118681 - /llvm/trunk/lib/System/Win32/Path.inc In-Reply-To: <20101110150539.E34DA2A6C12C@llvm.org> References: <20101110150539.E34DA2A6C12C@llvm.org> Message-ID: <4CDAB668.9060807@mymail.mines.edu> On 11/10/10 8:05 AM, Michael J. Spencer wrote: > @@ -376,7 +376,15 @@ > > bool > Path::isSymLink() const { > - return false; > + DWORD attributes = GetFileAttributes(path.c_str()); > + > + if (attributes == INVALID_FILE_ATTRIBUTES) > + // There's no sane way to report this :(. > + assert(0 && "GetFileAttributes returned INVALID_FILE_ATTRIBUTES"); Why don't you just assert attributes != INVALID_FILE_ATTRIBUTES? Chip From bigcheesegs at gmail.com Wed Nov 10 09:20:14 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 10 Nov 2010 10:20:14 -0500 Subject: [llvm-commits] [llvm] r118681 - /llvm/trunk/lib/System/Win32/Path.inc In-Reply-To: <4CDAB668.9060807@mymail.mines.edu> References: <20101110150539.E34DA2A6C12C@llvm.org> <4CDAB668.9060807@mymail.mines.edu> Message-ID: On Wed, Nov 10, 2010 at 10:12 AM, Charles Davis wrote: > On 11/10/10 8:05 AM, Michael J. Spencer wrote: >> @@ -376,7 +376,15 @@ >> >> ?bool >> ?Path::isSymLink() const { >> - ?return false; >> + ?DWORD attributes = GetFileAttributes(path.c_str()); >> + >> + ?if (attributes == INVALID_FILE_ATTRIBUTES) >> + ? ?// There's no sane way to report this :(. >> + ? ?assert(0 && "GetFileAttributes returned INVALID_FILE_ATTRIBUTES"); > Why don't you just assert attributes != INVALID_FILE_ATTRIBUTES? > > Chip Originally it was a report_fatal_error, but that's in Support. I kept it like that because I want to replace it with some proper error handling code. - Michael Spencer From grosser at fim.uni-passau.de Wed Nov 10 10:31:34 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 10 Nov 2010 16:31:34 -0000 Subject: [llvm-commits] [llvm] r118684 - in /llvm/trunk: Makefile.config.in autoconf/configure.ac configure Message-ID: <20101110163134.C24D02A6C12C@llvm.org> Author: grosser Date: Wed Nov 10 10:31:34 2010 New Revision: 118684 URL: http://llvm.org/viewvc/llvm-project?rev=118684&view=rev Log: Detect if llvm-gcc is built on dragonegg. Store the flags needed to disable optimizations and to emit LLVM-IR depending on the version of llvm-gcc used. Modified: llvm/trunk/Makefile.config.in llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/Makefile.config.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=118684&r1=118683&r2=118684&view=diff ============================================================================== --- llvm/trunk/Makefile.config.in (original) +++ llvm/trunk/Makefile.config.in Wed Nov 10 10:31:34 2010 @@ -195,6 +195,8 @@ LLVMCC1 := @LLVMCC1@ LLVMCC1PLUS := @LLVMCC1PLUS@ LLVMGCC_LANGS := @LLVMGCC_LANGS@ +LLVMGCC_DRAGONEGG := @LLVMGCC_DRAGONEGG@ +LLVMGCC_DISABLEOPT_FLAGS := @LLVMGCC_DISABLEOPT_FLAGS@ # Information on Clang, if configured. CLANGPATH := @CLANGPATH@ @@ -204,6 +206,9 @@ # The LLVM capable compiler to use. LLVMCC_OPTION := @LLVMCC_OPTION@ +# The flag used to emit LLVM IR. +LLVMCC_EMITIR_FLAG = @LLVMCC_EMITIR_FLAG@ + # Path to directory where object files should be stored during a build. # Set OBJ_ROOT to "." if you do not want to use a separate place for # object files. Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=118684&r1=118683&r2=118684&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Wed Nov 10 10:31:34 2010 @@ -1414,12 +1414,37 @@ dnl Check, whether __dso_handle is present AC_CHECK_FUNCS([__dso_handle]) +dnl Check wether llvm-gcc is based on dragonegg +AC_CACHE_CHECK([whether llvm-gcc is dragonegg],[llvm_cv_llvmgcc_dragonegg], +[llvm_cv_llvmgcc_dragonegg="no" +if test -x "$LLVMGCC" ; then + cp /dev/null conftest.c + "$LLVMGCC" -fplugin-arg-dragonegg-emit-ir -S -o - conftest.c | \ + grep 'target datalayout =' > /dev/null 2>&1 + if test $? -eq 0 ; then + llvm_cv_llvmgcc_dragonegg="yes" + fi + rm conftest.c +fi]) + +dnl Set the flags needed to emit LLVM IR and to disable optimizations +dnl in llvmgcc +if test "$llvm_cv_llvmgcc_dragonegg" = "yes" ; then + LLVMCC_EMITIR_FLAG="-fplugin-arg-dragonegg-emit-ir" + LLVMGCC_DISABLEOPT_FLAGS="-fplugin-arg-dragonegg-disable-llvm-optzns" +else + LLVMCC_EMITIR_FLAG="-emit-llvm" + LLVMGCC_DISABLEOPT_FLAGS="-mllvm -disable-llvm-optzns" +fi + +AC_SUBST(LLVMCC_EMITIR_FLAG) + dnl See if the llvm-gcc executable can compile to LLVM assembly AC_CACHE_CHECK([whether llvm-gcc is sane],[llvm_cv_llvmgcc_sanity], [llvm_cv_llvmgcc_sanity="no" if test -x "$LLVMGCC" ; then cp /dev/null conftest.c - "$LLVMGCC" -emit-llvm -S -o - conftest.c | \ + "$LLVMGCC" "$LLVMCC_EMITIR_FLAG" -S -o - conftest.c | \ grep 'target datalayout =' > /dev/null 2>&1 if test $? -eq 0 ; then llvm_cv_llvmgcc_sanity="yes" @@ -1428,6 +1453,7 @@ fi]) dnl Since we have a sane llvm-gcc, identify it and its sub-tools +dnl Furthermore, add some information about the tools if test "$llvm_cv_llvmgcc_sanity" = "yes" ; then AC_MSG_CHECKING([llvm-gcc component support]) llvmcc1path=`"$LLVMGCC" --print-prog-name=cc1` @@ -1438,6 +1464,8 @@ AC_SUBST(LLVMGCCDIR,$llvmgccdir) llvmgcclangs=[`"$LLVMGCC" -v --help 2>&1 | grep '^Configured with:' | sed 's/^.*--enable-languages=\([^ ]*\).*/\1/'`] AC_SUBST(LLVMGCC_LANGS,$llvmgcclangs) + AC_SUBST(LLVMGCC_DRAGONEGG,$llvm_cv_llvmgcc_dragonegg) + AC_SUBST(LLVMGCC_DISABLEOPT_FLAGS) AC_MSG_RESULT([ok]) fi Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=118684&r1=118683&r2=118684&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Wed Nov 10 10:31:34 2010 @@ -771,10 +771,13 @@ HAVE_PTHREAD HUGE_VAL_SANITY MMAP_FILE +LLVMCC_EMITIR_FLAG LLVMCC1 LLVMCC1PLUS LLVMGCCDIR LLVMGCC_LANGS +LLVMGCC_DRAGONEGG +LLVMGCC_DISABLEOPT_FLAGS SHLIBEXT SHLIBPATH_VAR LLVM_PREFIX @@ -11498,7 +11501,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <&5 +echo $ECHO_N "checking whether llvm-gcc is dragonegg... $ECHO_C" >&6; } +if test "${llvm_cv_llvmgcc_dragonegg+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + llvm_cv_llvmgcc_dragonegg="no" +if test -x "$LLVMGCC" ; then + cp /dev/null conftest.c + "$LLVMGCC" -fplugin-arg-dragonegg-emit-ir -S -o - conftest.c | \ + grep 'target datalayout =' > /dev/null 2>&1 + if test $? -eq 0 ; then + llvm_cv_llvmgcc_dragonegg="yes" + fi + rm conftest.c +fi +fi +{ echo "$as_me:$LINENO: result: $llvm_cv_llvmgcc_dragonegg" >&5 +echo "${ECHO_T}$llvm_cv_llvmgcc_dragonegg" >&6; } + +if test "$llvm_cv_llvmgcc_dragonegg" = "yes" ; then + LLVMCC_EMITIR_FLAG="-fplugin-arg-dragonegg-emit-ir" + LLVMGCC_DISABLEOPT_FLAGS="-fplugin-arg-dragonegg-disable-llvm-optzns" +else + LLVMCC_EMITIR_FLAG="-emit-llvm" + LLVMGCC_DISABLEOPT_FLAGS="-mllvm -disable-llvm-optzns" +fi + + + { echo "$as_me:$LINENO: checking whether llvm-gcc is sane" >&5 echo $ECHO_N "checking whether llvm-gcc is sane... $ECHO_C" >&6; } if test "${llvm_cv_llvmgcc_sanity+set}" = set; then @@ -20568,7 +20600,7 @@ llvm_cv_llvmgcc_sanity="no" if test -x "$LLVMGCC" ; then cp /dev/null conftest.c - "$LLVMGCC" -emit-llvm -S -o - conftest.c | \ + "$LLVMGCC" "$LLVMCC_EMITIR_FLAG" -S -o - conftest.c | \ grep 'target datalayout =' > /dev/null 2>&1 if test $? -eq 0 ; then llvm_cv_llvmgcc_sanity="yes" @@ -20594,6 +20626,9 @@ llvmgcclangs=`"$LLVMGCC" -v --help 2>&1 | grep '^Configured with:' | sed 's/^.*--enable-languages=\([^ ]*\).*/\1/'` LLVMGCC_LANGS=$llvmgcclangs + LLVMGCC_DRAGONEGG=$llvm_cv_llvmgcc_dragonegg + + { echo "$as_me:$LINENO: result: ok" >&5 echo "${ECHO_T}ok" >&6; } fi @@ -21786,10 +21821,13 @@ HAVE_PTHREAD!$HAVE_PTHREAD$ac_delim HUGE_VAL_SANITY!$HUGE_VAL_SANITY$ac_delim MMAP_FILE!$MMAP_FILE$ac_delim +LLVMCC_EMITIR_FLAG!$LLVMCC_EMITIR_FLAG$ac_delim LLVMCC1!$LLVMCC1$ac_delim LLVMCC1PLUS!$LLVMCC1PLUS$ac_delim LLVMGCCDIR!$LLVMGCCDIR$ac_delim LLVMGCC_LANGS!$LLVMGCC_LANGS$ac_delim +LLVMGCC_DRAGONEGG!$LLVMGCC_DRAGONEGG$ac_delim +LLVMGCC_DISABLEOPT_FLAGS!$LLVMGCC_DISABLEOPT_FLAGS$ac_delim SHLIBEXT!$SHLIBEXT$ac_delim SHLIBPATH_VAR!$SHLIBPATH_VAR$ac_delim LLVM_PREFIX!$LLVM_PREFIX$ac_delim @@ -21808,11 +21846,9 @@ ENABLE_VISIBILITY_INLINES_HIDDEN!$ENABLE_VISIBILITY_INLINES_HIDDEN$ac_delim RPATH!$RPATH$ac_delim RDYNAMIC!$RDYNAMIC$ac_delim -LIBOBJS!$LIBOBJS$ac_delim -LTLIBOBJS!$LTLIBOBJS$ac_delim _ACEOF - if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 96; then + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 97; then break elif $ac_last_try; then { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 @@ -21848,6 +21884,51 @@ _ACEOF +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + cat >conf$$subs.sed <<_ACEOF +LIBOBJS!$LIBOBJS$ac_delim +LTLIBOBJS!$LTLIBOBJS$ac_delim +_ACEOF + + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 2; then + break + elif $ac_last_try; then + { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 +echo "$as_me: error: could not make $CONFIG_STATUS" >&2;} + { (exit 1); exit 1; }; } + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +ac_eof=`sed -n '/^CEOF[0-9]*$/s/CEOF/0/p' conf$$subs.sed` +if test -n "$ac_eof"; then + ac_eof=`echo "$ac_eof" | sort -nru | sed 1q` + ac_eof=`expr $ac_eof + 1` +fi + +cat >>$CONFIG_STATUS <<_ACEOF +cat >"\$tmp/subs-3.sed" <<\CEOF$ac_eof +/@[a-zA-Z_][a-zA-Z_0-9]*@/!b end +_ACEOF +sed ' +s/[,\\&]/\\&/g; s/@/@|#_!!_#|/g +s/^/s,@/; s/!/@,|#_!!_#|/ +:n +t n +s/'"$ac_delim"'$/,g/; t +s/$/\\/; p +N; s/^.*\n//; s/[,\\&]/\\&/g; s/@/@|#_!!_#|/g; b n +' >>$CONFIG_STATUS >$CONFIG_STATUS <<_ACEOF +:end +s/|#_!!_#|//g +CEOF$ac_eof +_ACEOF + + # VPATH may cause trouble with some makes, so we remove $(srcdir), # ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and # trailing colons and then remove the whole line if VPATH becomes empty @@ -22091,7 +22172,7 @@ s&@abs_top_builddir@&$ac_abs_top_builddir&;t t s&@INSTALL@&$ac_INSTALL&;t t $ac_datarootdir_hack -" $ac_file_inputs | sed -f "$tmp/subs-1.sed" | sed -f "$tmp/subs-2.sed" | sed 's/|#_!!_#|//g' >$tmp/out +" $ac_file_inputs | sed -f "$tmp/subs-1.sed" | sed -f "$tmp/subs-2.sed" | sed -f "$tmp/subs-3.sed" >$tmp/out test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } && From grosser at fim.uni-passau.de Wed Nov 10 11:00:55 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 10 Nov 2010 17:00:55 -0000 Subject: [llvm-commits] [test-suite] r118685 - in /test-suite/trunk: Makefile.rules Makefile.tests Message-ID: <20101110170055.5DC682A6C12C@llvm.org> Author: grosser Date: Wed Nov 10 11:00:55 2010 New Revision: 118685 URL: http://llvm.org/viewvc/llvm-project?rev=118685&view=rev Log: Add dragonegg support to the test suite. Use LLVMCC_EMITIR_FLAG and LLVMGCC_DISABLE_OPT_FLAGS to derive the flags needed to build using either the classic llvm-gcc or the dragonegg based llvm-gcc. Modified: test-suite/trunk/Makefile.rules test-suite/trunk/Makefile.tests Modified: test-suite/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.rules?rev=118685&r1=118684&r2=118685&view=diff ============================================================================== --- test-suite/trunk/Makefile.rules (original) +++ test-suite/trunk/Makefile.rules Wed Nov 10 11:00:55 2010 @@ -368,7 +368,7 @@ ifdef DISABLE_LTO LOPTFLAGS := $(OPTFLAGS) else -LOPTFLAGS := $(OPTFLAGS) -mllvm -disable-llvm-optzns +LOPTFLAGS := $(OPTFLAGS) $(LLVMGCC_DISABLEOPT_FLAGS) endif # Explicitly specify -m32 / -m64 so there is no mismatch between llvm-gcc Modified: test-suite/trunk/Makefile.tests URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.tests?rev=118685&r1=118684&r2=118685&view=diff ============================================================================== --- test-suite/trunk/Makefile.tests (original) +++ test-suite/trunk/Makefile.tests Wed Nov 10 11:00:55 2010 @@ -42,29 +42,33 @@ $(RM) -f a.out core $(RM) -rf Output/ -# Compile from X.c to Output/X.bc -Output/%.bc: %.c $(LCC_PROGRAMS) Output/.dir $(INCLUDES) - -$(LCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -c $< -o $@ -emit-llvm - -# Compile from X.cpp to Output/X.bc -Output/%.bc: %.cpp $(LCC_PROGRAMS) Output/.dir $(INCLUDES) - -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -c $< -o $@ -emit-llvm - -# Compile from X.cc to Output/X.bc -Output/%.bc: %.cc $(LCC_PROGRAMS) Output/.dir $(INCLUDES) - -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -c $< -o $@ -emit-llvm - -# Compile from X.C to Output/X.bc -Output/%.bc: %.C $(LCC_PROGRAMS) Output/.dir $(INCLUDES) - -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -c $< -o $@ -emit-llvm - -# Compile from X.m to Output/X.bc -Output/%.bc: %.m $(LCC_PROGRAMS) Output/.dir $(INCLUDES) - -$(LCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -c $< -o $@ -emit-llvm - -# Compile from X.mm to Output/X.bc -Output/%.bc: %.mm $(LCC_PROGRAMS) Output/.dir $(INCLUDES) - -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -c $< -o $@ -emit-llvm +# Compile from X.c to Output/X.ll +Output/%.ll: %.c $(LCC_PROGRAMS) Output/.dir $(INCLUDES) + -$(LCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -S $< -o $@ $(LLVMCC_EMITIR_FLAG) + +# Compile from X.cpp to Output/X.ll +Output/%.ll: %.cpp $(LCC_PROGRAMS) Output/.dir $(INCLUDES) + -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -S $< -o $@ $(LLVMCC_EMITIR_FLAG) + +# Compile from X.cc to Output/X.ll +Output/%.ll: %.cc $(LCC_PROGRAMS) Output/.dir $(INCLUDES) + -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -S $< -o $@ $(LLVMCC_EMITIR_FLAG) + +# Compile from X.C to Output/X.ll +Output/%.ll: %.C $(LCC_PROGRAMS) Output/.dir $(INCLUDES) + -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -S $< -o $@ $(LLVMCC_EMITIR_FLAG) + +# Compile from X.m to Output/X.ll +Output/%.ll: %.m $(LCC_PROGRAMS) Output/.dir $(INCLUDES) + -$(LCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -S $< -o $@ $(LLVMCC_EMITIR_FLAG) + +# Compile from X.mm to Output/X.ll +Output/%.ll: %.mm $(LCC_PROGRAMS) Output/.dir $(INCLUDES) + -$(LCXX) $(CPPFLAGS) $(CXXFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -S $< -o $@ $(LLVMCC_EMITIR_FLAG) + +# Compile from X.ll to X.bc +%.bc: %.ll $(LLVMAS) + $(LLVMAS) $< -o $@ # LLVM Assemble from X.ll to Output/X.bc. Because we are coming directly from # LLVM source, use the non-transforming assembler. From gohman at apple.com Wed Nov 10 11:15:52 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 17:15:52 -0000 Subject: [llvm-commits] [llvm] r118686 - /llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Message-ID: <20101110171552.545892A6C12C@llvm.org> Author: djg Date: Wed Nov 10 11:15:52 2010 New Revision: 118686 URL: http://llvm.org/viewvc/llvm-project?rev=118686&view=rev Log: Give NonLocalDepResult a NonLocalDepEntry member, replacing indivudal members holding the same data, to clarify the relationship between NonLocalDepResult and NonLocalDepEntry. Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=118686&r1=118685&r2=118686&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Wed Nov 10 11:15:52 2010 @@ -133,26 +133,49 @@ } }; + /// NonLocalDepEntry - This is an entry in the NonLocalDepInfo cache. For + /// each BasicBlock (the BB entry) it keeps a MemDepResult. + class NonLocalDepEntry { + BasicBlock *BB; + MemDepResult Result; + public: + NonLocalDepEntry(BasicBlock *bb, MemDepResult result) + : BB(bb), Result(result) {} + + // This is used for searches. + NonLocalDepEntry(BasicBlock *bb) : BB(bb) {} + + // BB is the sort key, it can't be changed. + BasicBlock *getBB() const { return BB; } + + void setResult(const MemDepResult &R) { Result = R; } + + const MemDepResult &getResult() const { return Result; } + + bool operator<(const NonLocalDepEntry &RHS) const { + return BB < RHS.BB; + } + }; + /// NonLocalDepResult - This is a result from a NonLocal dependence query. /// For each BasicBlock (the BB entry) it keeps a MemDepResult and the /// (potentially phi translated) address that was live in the block. class NonLocalDepResult { - BasicBlock *BB; - MemDepResult Result; + NonLocalDepEntry Entry; Value *Address; public: NonLocalDepResult(BasicBlock *bb, MemDepResult result, Value *address) - : BB(bb), Result(result), Address(address) {} + : Entry(bb, result), Address(address) {} // BB is the sort key, it can't be changed. - BasicBlock *getBB() const { return BB; } + BasicBlock *getBB() const { return Entry.getBB(); } void setResult(const MemDepResult &R, Value *Addr) { - Result = R; + Entry.setResult(R); Address = Addr; } - const MemDepResult &getResult() const { return Result; } + const MemDepResult &getResult() const { return Entry.getResult(); } /// getAddress - Return the address of this pointer in this block. This can /// be different than the address queried for the non-local result because @@ -164,30 +187,6 @@ Value *getAddress() const { return Address; } }; - /// NonLocalDepEntry - This is an entry in the NonLocalDepInfo cache. For - /// each BasicBlock (the BB entry) it keeps a MemDepResult. - class NonLocalDepEntry { - BasicBlock *BB; - MemDepResult Result; - public: - NonLocalDepEntry(BasicBlock *bb, MemDepResult result) - : BB(bb), Result(result) {} - - // This is used for searches. - NonLocalDepEntry(BasicBlock *bb) : BB(bb) {} - - // BB is the sort key, it can't be changed. - BasicBlock *getBB() const { return BB; } - - void setResult(const MemDepResult &R) { Result = R; } - - const MemDepResult &getResult() const { return Result; } - - bool operator<(const NonLocalDepEntry &RHS) const { - return BB < RHS.BB; - } - }; - /// MemoryDependenceAnalysis - This is an analysis that determines, for a /// given memory operation, what preceding memory operations it depends on. /// It builds on alias analysis information, and tries to provide a lazy, From baldrick at free.fr Wed Nov 10 11:31:25 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 18:31:25 +0100 Subject: [llvm-commits] [llvm] r118378 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp lib/Target/README.txt test/Transforms/InstCombine/select.ll In-Reply-To: References: <20101107161224.05FC22A6C12C@llvm.org> Message-ID: <4CDAD6ED.6090702@free.fr> Hi Benjamin, >> Author: baldrick >> Date: Sun Nov 7 10:12:23 2010 >> New Revision: 118378 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118378&view=rev >> Log: >> Fix a README item: when doing a comparison with the result >> of a select instruction, see if doing the compare with the >> true and false values of the select gives the same result. >> If so, that can be used as the value of the comparison. > > Awesome! Should we do the same thing on phi nodes where an icmp > on all incoming values yields the same result? how about this? Ciao, Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: phi.diff Type: text/x-patch Size: 16309 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/ec6f3ee3/attachment.bin From gohman at apple.com Wed Nov 10 11:34:04 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 17:34:04 -0000 Subject: [llvm-commits] [llvm] r118687 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20101110173404.CCF4D2A6C12C@llvm.org> Author: djg Date: Wed Nov 10 11:34:04 2010 New Revision: 118687 URL: http://llvm.org/viewvc/llvm-project?rev=118687&view=rev Log: Factor out the code for testing whether a function accesses arbitrary memory into a helper function, and adjust some comments. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118687&r1=118686&r2=118687&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Wed Nov 10 11:34:04 2010 @@ -268,14 +268,21 @@ return onlyReadsMemory(getModRefBehavior(F)); } - /// onlyReadsMemory - If the functions with the specified behavior are known - /// to only read from non-volatile memory (or not access memory at all), return - /// true. For use when the call site is not known. + /// onlyReadsMemory - Return true if functions with the specified behavior are + /// known to only read from non-volatile memory (or not access memory at all). /// static bool onlyReadsMemory(ModRefBehavior MRB) { return !(MRB & Mod); } + /// onlyAccessesArgPointees - Return true if functions with the specified + /// behavior are known to read at most from objects pointed to by their + /// pointer-typed arguments (with arbitrary offsets). + /// + static bool onlyAccessesArgPointees(ModRefBehavior MRB) { + return !(MRB & Anywhere & ~ArgumentPointees); + } + /// getModRefInfo - Return information about whether or not an instruction may /// read or write the specified memory location. An instruction /// that doesn't read or write memory may be trivially LICM'd for example. Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118687&r1=118686&r2=118687&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Wed Nov 10 11:34:04 2010 @@ -131,9 +131,8 @@ AliasAnalysis::ModRefBehavior MRB = AA->getModRefBehavior(CS); // If the call doesn't access arbitrary memory, we may be able to // figure out something. - if (!(MRB & AliasAnalysis::Anywhere & - ~AliasAnalysis::ArgumentPointees)) { - // If the call accesses argument pointees, check each argument. + if (AliasAnalysis::onlyAccessesArgPointees(MRB)) { + // If the call does access argument pointees, check each argument. if (MRB & AliasAnalysis::AccessesArguments) // Check whether all pointer arguments point to local memory, and // ignore calls that only access local memory. From jasonwkim at google.com Wed Nov 10 11:57:21 2010 From: jasonwkim at google.com (Jason Kim) Date: Wed, 10 Nov 2010 09:57:21 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) Message-ID: Refactoring the x86 dependent code from ELFObjectWriter class has repercussions among several (conflicting) axes of consideration, 1. namespace pollution - minimize pollution of the llvm: namespace 2. consistency - try to maintain as small a delta between the changes 3. linking - minimize the number of additional cross dependency between the existing libraries 4. clarity - avoid special case switching as much as possible - 5. Xfactor - how clean is the overall resulting design? The possible ways forward I see are SMALL: keep the code nearly as is - place a switch inside ELFObjectWriter::RecordRelocation and dispatch to ELFObjectWriterImpl::RecordRelocation 1. +1 no new classes 2. +1 tiny patch 3. +1 no new classes, just one additional function so far. 4. -2 need to have special case switching for every routine that needs to be tweaked. 5. -2 Terrible! So far, its just one new switch, but ... tryA: move the functionality of the ELFObjectWriterImpl class into ELFObjectWriter, and subclass ELFObjectWriter to ELFObjectWriter. Change most ELF specific routines to be virtual - except for the low level Write* routines - 1. -1 at least new classes ARMELFObjectWriter and X86ELFObjectWriter 2. -1 large patch 3. +2 Resulting special cases are isolated in their own class 4. +1 Depends upon virtual dispatch for higher level differentiation - removes unnecessary trampoline between ELFObjectWriter and ELFObjectWriterImpl 5. +2 This approach is the best in terms of the resulting design. The only drawback is the distinction between MachO and ELF tryB: subclass ELFObjectWriterImpl instead - I am still working out the details on this one - but as of right now, it is just as complex as the tryA case. The only benefit to this is approach is the superficial similarity between the ELFObjectWriter and the MachObjectWriter - in that both still trampoline into an *Impl class to do the actual work. Unfortunately, it also adds a requirement for registering a NEW ELFObjecWriterImpl class (i.e. in addition to the existing createELFObjectWriter, and without namespace pollution to llvm, creates a linkage dependency failure). I will reply to this thread with a patch as soon as I finish this variant. There are several attachments: small: small-elfwriter-cpp (application/octet-stream) 2K small-elfwriter-rename-record (application/octet-stream) 2K tryA arm-mc-elf-s07-elfwriter-tryA-combined.patch (text/x-patch) 43K - this is the combined patch - In order to make it more clear, I broke up the steps into a dozen or so smaller patches. tryA.tgz - archive of patches They are combined into a tar archive - the README is reproduced here. Thanks for reading. -jason -------------- next part -------------- A non-text attachment was scrubbed... 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Name: README Type: application/octet-stream Size: 1286 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/bf1b0e5e/attachment-0005.obj From baldrick at free.fr Wed Nov 10 12:00:05 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 19:00:05 +0100 Subject: [llvm-commits] [llvm] r118687 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Transforms/IPO/FunctionAttrs.cpp In-Reply-To: <20101110173404.CCF4D2A6C12C@llvm.org> References: <20101110173404.CCF4D2A6C12C@llvm.org> Message-ID: <4CDADDA5.5030709@free.fr> Hi Dan, > + /// onlyAccessesArgPointees - Return true if functions with the specified > + /// behavior are known to read at most from objects pointed to by their > + /// pointer-typed arguments (with arbitrary offsets). can't they also write to objects pointed to by their arguments? > + if (AliasAnalysis::onlyAccessesArgPointees(MRB)) { > + // If the call does access argument pointees, check each argument. > if (MRB& AliasAnalysis::AccessesArguments) Is this second "if" redundant? Ciao, Duncan. From grosbach at apple.com Wed Nov 10 11:59:10 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 10 Nov 2010 17:59:10 -0000 Subject: [llvm-commits] [llvm] r118688 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20101110175910.B39132A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 11:59:10 2010 New Revision: 118688 URL: http://llvm.org/viewvc/llvm-project?rev=118688&view=rev Log: Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes double quoting of ObjC symbol names in constant pool entries. rdar://8652107 Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=118688&r1=118687&r2=118688&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Nov 10 11:59:10 2010 @@ -622,40 +622,40 @@ int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); ARMConstantPoolValue *ACPV = static_cast(MCPV); - SmallString<128> Str; - raw_svector_ostream OS(Str); + MCSymbol *MCSym; if (ACPV->isLSDA()) { + SmallString<128> Str; + raw_svector_ostream OS(Str); OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); + MCSym = OutContext.GetOrCreateSymbol(OS.str()); } else if (ACPV->isBlockAddress()) { - OS << *GetBlockAddressSymbol(ACPV->getBlockAddress()); + MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress()); } else if (ACPV->isGlobalValue()) { const GlobalValue *GV = ACPV->getGV(); bool isIndirect = Subtarget->isTargetDarwin() && Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()); if (!isIndirect) - OS << *Mang->getSymbol(GV); + MCSym = Mang->getSymbol(GV); else { // FIXME: Remove this when Darwin transition to @GOT like syntax. - MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); - OS << *Sym; + MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); MachineModuleInfoMachO &MMIMachO = MMI->getObjFileInfo(); MachineModuleInfoImpl::StubValueTy &StubSym = - GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) : - MMIMachO.getGVStubEntry(Sym); + GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) : + MMIMachO.getGVStubEntry(MCSym); if (StubSym.getPointer() == 0) StubSym = MachineModuleInfoImpl:: StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage()); } } else { assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); - OS << *GetExternalSymbolSymbol(ACPV->getSymbol()); + MCSym = GetExternalSymbolSymbol(ACPV->getSymbol()); } // Create an MCSymbol for the reference. - MCSymbol *MCSym = OutContext.GetOrCreateSymbol(OS.str()); const MCExpr *Expr = MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()), OutContext); From ofv at wanadoo.es Wed Nov 10 12:03:21 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Wed, 10 Nov 2010 19:03:21 +0100 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: (NAKAMURA Takumi's message of "Wed, 10 Nov 2010 15:14:13 +0900") References: <87d3qezzud.fsf@telefonica.net> Message-ID: <877hgl3vkm.fsf@telefonica.net> NAKAMURA Takumi writes: >> I'm wary by the use of separate_arguments. Why do you need it and why >> UNIX_COMMAND was chosen? > > My intention is simply to separate simple options to list, > not to separate complex arguments. > It seems UNIX_COMMAND works fine. > I may choose whatever works. What would be better? > > Without separation, we will see lit.py "-sv --no-progress-bar". Have you checked that? As far as you add new arguments to LLMV_LIT_ARGS with set(LLMV_LIT_ARGS "${LLMV_LIT_ARGS} --another-arg") (i.e. not using the variable as a list, but as a string) there should be no problem. Please note that the cmake interpreter expands the variable's contents *before* the command is constructed. The only way of falling into the problem you mentioned would be COMMAND lit.py "${LLMV_LIT_ARGS}" instead of COMMAND lit.py ${LLMV_LIT_ARGS} (or if LLMV_LIT_ARGS contains escaped double quotes at the wrong place) [snip] Please test your change after removing `separate_arguments'. If it works, commit. Else commit the patch as posted to the mailing list. From baldrick at free.fr Wed Nov 10 12:04:30 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 19:04:30 +0100 Subject: [llvm-commits] [llvm] r118684 - in /llvm/trunk: Makefile.config.in autoconf/configure.ac configure In-Reply-To: <20101110163134.C24D02A6C12C@llvm.org> References: <20101110163134.C24D02A6C12C@llvm.org> Message-ID: <4CDADEAE.4090601@free.fr> Hi Tobias, thanks so much for doing this! > --- llvm/trunk/autoconf/configure.ac (original) > +++ llvm/trunk/autoconf/configure.ac Wed Nov 10 10:31:34 2010 > @@ -1414,12 +1414,37 @@ > dnl Check, whether __dso_handle is present > AC_CHECK_FUNCS([__dso_handle]) > > +dnl Check wether llvm-gcc is based on dragonegg > +AC_CACHE_CHECK([whether llvm-gcc is dragonegg],[llvm_cv_llvmgcc_dragonegg], > +[llvm_cv_llvmgcc_dragonegg="no" > +if test -x "$LLVMGCC" ; then > + cp /dev/null conftest.c > + "$LLVMGCC" -fplugin-arg-dragonegg-emit-ir -S -o - conftest.c | \ > + grep 'target datalayout ='> /dev/null 2>&1 The grep test shouldn't be needed, since gcc should fail to execute if it doesn't support plugins, or a plugin with name dragonegg has not been loaded. That said, it doesn't hurt. Ciao, Duncan. From baldrick at free.fr Wed Nov 10 12:05:25 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 19:05:25 +0100 Subject: [llvm-commits] [test-suite] r118685 - in /test-suite/trunk: Makefile.rules Makefile.tests In-Reply-To: <20101110170055.5DC682A6C12C@llvm.org> References: <20101110170055.5DC682A6C12C@llvm.org> Message-ID: <4CDADEE5.2070207@free.fr> Hi Tobias, > Add dragonegg support to the test suite. > > Use LLVMCC_EMITIR_FLAG and LLVMGCC_DISABLE_OPT_FLAGS to derive the flags > needed to build using either the classic llvm-gcc or the dragonegg based > llvm-gcc. great! I will try to test it tomorrow or on Friday. Best wishes, Duncan. From dpatel at apple.com Wed Nov 10 12:11:11 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 10 Nov 2010 18:11:11 -0000 Subject: [llvm-commits] [debuginfo-tests] r118690 - /debuginfo-tests/trunk/README.txt Message-ID: <20101110181111.73DDA2A6C12C@llvm.org> Author: dpatel Date: Wed Nov 10 12:11:11 2010 New Revision: 118690 URL: http://llvm.org/viewvc/llvm-project?rev=118690&view=rev Log: Zap white spaces, test commit email. Modified: debuginfo-tests/trunk/README.txt Modified: debuginfo-tests/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/README.txt?rev=118690&r1=118689&r2=118690&view=diff ============================================================================== --- debuginfo-tests/trunk/README.txt (original) +++ debuginfo-tests/trunk/README.txt Wed Nov 10 12:11:11 2010 @@ -8,10 +8,10 @@ For exmaple, define i32 @f1(i32 %i) nounwind ssp { -; DEBUGGER: break f1 -; DEBUGGER: r -; DEBUGGER: p i -; CHECK: $1 = 42 +; DEBUGGER: break f1 +; DEBUGGER: r +; DEBUGGER: p i +; CHECK: $1 = 42 entry: } From benny.kra at googlemail.com Wed Nov 10 12:18:10 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 10 Nov 2010 19:18:10 +0100 Subject: [llvm-commits] [llvm] r118378 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp lib/Target/README.txt test/Transforms/InstCombine/select.ll In-Reply-To: <4CDAD6ED.6090702@free.fr> References: <20101107161224.05FC22A6C12C@llvm.org> <4CDAD6ED.6090702@free.fr> Message-ID: On 10.11.2010, at 18:31, Duncan Sands wrote: > Hi Benjamin, > >>> Author: baldrick >>> Date: Sun Nov 7 10:12:23 2010 >>> New Revision: 118378 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=118378&view=rev >>> Log: >>> Fix a README item: when doing a comparison with the result >>> of a select instruction, see if doing the compare with the >>> true and false values of the select gives the same result. >>> If so, that can be used as the value of the comparison. >> >> Awesome! Should we do the same thing on phi nodes where an icmp >> on all incoming values yields the same result? > > how about this? Looks good to me. From gohman at apple.com Wed Nov 10 12:17:28 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 18:17:28 -0000 Subject: [llvm-commits] [llvm] r118692 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Transforms/IPO/FunctionAttrs.cpp Message-ID: <20101110181728.DB5372A6C12C@llvm.org> Author: djg Date: Wed Nov 10 12:17:28 2010 New Revision: 118692 URL: http://llvm.org/viewvc/llvm-project?rev=118692&view=rev Log: Add a doesAccessArgPointees helper function, and update code to use it, and to be consistent. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118692&r1=118691&r2=118692&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Wed Nov 10 12:17:28 2010 @@ -283,6 +283,14 @@ return !(MRB & Anywhere & ~ArgumentPointees); } + /// doesAccessArgPointees - Return true if functions with the specified + /// behavior are known to potentially read or write from objects pointed + /// to be their pointer-typed arguments (with arbitrary offsets). + /// + static bool doesAccessArgPointees(ModRefBehavior MRB) { + return (MRB & ModRef) && (MRB & ArgumentPointees); + } + /// getModRefInfo - Return information about whether or not an instruction may /// read or write the specified memory location. An instruction /// that doesn't read or write memory may be trivially LICM'd for example. Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=118692&r1=118691&r2=118692&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Wed Nov 10 12:17:28 2010 @@ -78,15 +78,15 @@ if (onlyReadsMemory(MRB)) Mask = Ref; - if (MRB == AccessesArguments || - MRB == AccessesArgumentsReadonly) { + if (onlyAccessesArgPointees(MRB)) { bool doesAlias = false; - for (ImmutableCallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); - AI != AE; ++AI) - if (!isNoAlias(Location(*AI), Loc)) { - doesAlias = true; - break; - } + if (doesAccessArgPointees(MRB)) + for (ImmutableCallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); + AI != AE; ++AI) + if (!isNoAlias(Location(*AI), Loc)) { + doesAlias = true; + break; + } if (!doesAlias) return NoModRef; @@ -130,27 +130,29 @@ // If CS2 only access memory through arguments, accumulate the mod/ref // information from CS1's references to the memory referenced by // CS2's arguments. - if (CS2B == AccessesArguments || CS2B == AccessesArgumentsReadonly) { + if (onlyAccessesArgPointees(CS2B)) { AliasAnalysis::ModRefResult R = NoModRef; - for (ImmutableCallSite::arg_iterator - I = CS2.arg_begin(), E = CS2.arg_end(); I != E; ++I) { - R = ModRefResult((R | getModRefInfo(CS1, *I, UnknownSize)) & Mask); - if (R == Mask) - break; - } + if (doesAccessArgPointees(CS2B)) + for (ImmutableCallSite::arg_iterator + I = CS2.arg_begin(), E = CS2.arg_end(); I != E; ++I) { + R = ModRefResult((R | getModRefInfo(CS1, *I, UnknownSize)) & Mask); + if (R == Mask) + break; + } return R; } // If CS1 only accesses memory through arguments, check if CS2 references // any of the memory referenced by CS1's arguments. If not, return NoModRef. - if (CS1B == AccessesArguments || CS1B == AccessesArgumentsReadonly) { + if (onlyAccessesArgPointees(CS1B)) { AliasAnalysis::ModRefResult R = NoModRef; - for (ImmutableCallSite::arg_iterator - I = CS1.arg_begin(), E = CS1.arg_end(); I != E; ++I) - if (getModRefInfo(CS2, *I, UnknownSize) != NoModRef) { - R = Mask; - break; - } + if (doesAccessArgPointees(CS1B)) + for (ImmutableCallSite::arg_iterator + I = CS1.arg_begin(), E = CS1.arg_end(); I != E; ++I) + if (getModRefInfo(CS2, *I, UnknownSize) != NoModRef) { + R = Mask; + break; + } if (R == NoModRef) return R; } Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118692&r1=118691&r2=118692&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Wed Nov 10 12:17:28 2010 @@ -133,7 +133,7 @@ // figure out something. if (AliasAnalysis::onlyAccessesArgPointees(MRB)) { // If the call does access argument pointees, check each argument. - if (MRB & AliasAnalysis::AccessesArguments) + if (AliasAnalysis::doesAccessArgPointees(MRB)) // Check whether all pointer arguments point to local memory, and // ignore calls that only access local memory. for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end(); From gohman at apple.com Wed Nov 10 12:18:23 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 18:18:23 -0000 Subject: [llvm-commits] [llvm] r118693 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101110181823.92B9B2A6C12C@llvm.org> Author: djg Date: Wed Nov 10 12:18:23 2010 New Revision: 118693 URL: http://llvm.org/viewvc/llvm-project?rev=118693&view=rev Log: Fix a copy+pasto Duncan noticed. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118693&r1=118692&r2=118693&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Wed Nov 10 12:18:23 2010 @@ -276,8 +276,8 @@ } /// onlyAccessesArgPointees - Return true if functions with the specified - /// behavior are known to read at most from objects pointed to by their - /// pointer-typed arguments (with arbitrary offsets). + /// behavior are known to read and write at most from objects pointed to by + /// their pointer-typed arguments (with arbitrary offsets). /// static bool onlyAccessesArgPointees(ModRefBehavior MRB) { return !(MRB & Anywhere & ~ArgumentPointees); From gohman at apple.com Wed Nov 10 12:22:38 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 10:22:38 -0800 Subject: [llvm-commits] [llvm] r118687 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Transforms/IPO/FunctionAttrs.cpp In-Reply-To: <4CDADDA5.5030709@free.fr> References: <20101110173404.CCF4D2A6C12C@llvm.org> <4CDADDA5.5030709@free.fr> Message-ID: <7B4B64F6-189A-457D-A355-4E3E6FBE7DDB@apple.com> On Nov 10, 2010, at 10:00 AM, Duncan Sands wrote: > Hi Dan, > >> + /// onlyAccessesArgPointees - Return true if functions with the >> specified >> + /// behavior are known to read at most from objects pointed to >> by their >> + /// pointer-typed arguments (with arbitrary offsets). > > can't they also write to objects pointed to by their arguments? Oops. Fixed. > >> + if (AliasAnalysis::onlyAccessesArgPointees(MRB)) { >> + // If the call does access argument pointees, check each >> argument. >> if (MRB& AliasAnalysis::AccessesArguments) > > Is this second "if" redundant? No; I've added another helper function for this now. Dan > From baldrick at free.fr Wed Nov 10 12:23:01 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 18:23:01 -0000 Subject: [llvm-commits] [llvm] r118694 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstCombine/select.ll Message-ID: <20101110182301.4AB762A6C12C@llvm.org> Author: baldrick Date: Wed Nov 10 12:23:01 2010 New Revision: 118694 URL: http://llvm.org/viewvc/llvm-project?rev=118694&view=rev Log: Teach InstructionSimplify how to look through PHI nodes. Since PHI nodes can be used in loops, this could result in infinite looping if there is no recursion limit, so add such a limit. It is also used for the SelectInst case because in theory there could be an infinite loop there too if the basic block is unreachable. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/test/Transforms/InstCombine/select.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=118694&r1=118693&r2=118694&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Nov 10 12:23:01 2010 @@ -21,12 +21,19 @@ using namespace llvm; using namespace llvm::PatternMatch; +#define MaxRecursionDepth 5 + +static Value *SimplifyBinOp(unsigned, Value *, Value *, const TargetData *, + unsigned); +static Value *SimplifyCmpInst(unsigned, Value *, Value *, const TargetData *, + unsigned); + /// ThreadBinOpOverSelect - In the case of a binary operation with a select /// instruction as an operand, try to simplify the binop by seeing whether /// evaluating it on both branches of the select results in the same value. /// Returns the common value if so, otherwise returns null. static Value *ThreadBinOpOverSelect(unsigned Opcode, Value *LHS, Value *RHS, - const TargetData *TD) { + const TargetData *TD, unsigned MaxRecurse) { SelectInst *SI; if (isa(LHS)) { SI = cast(LHS); @@ -39,11 +46,11 @@ Value *TV; Value *FV; if (SI == LHS) { - TV = SimplifyBinOp(Opcode, SI->getTrueValue(), RHS, TD); - FV = SimplifyBinOp(Opcode, SI->getFalseValue(), RHS, TD); + TV = SimplifyBinOp(Opcode, SI->getTrueValue(), RHS, TD, MaxRecurse); + FV = SimplifyBinOp(Opcode, SI->getFalseValue(), RHS, TD, MaxRecurse); } else { - TV = SimplifyBinOp(Opcode, LHS, SI->getTrueValue(), TD); - FV = SimplifyBinOp(Opcode, LHS, SI->getFalseValue(), TD); + TV = SimplifyBinOp(Opcode, LHS, SI->getTrueValue(), TD, MaxRecurse); + FV = SimplifyBinOp(Opcode, LHS, SI->getFalseValue(), TD, MaxRecurse); } // If they simplified to the same value, then return the common value. @@ -94,7 +101,8 @@ /// result in the same value. Returns the common value if so, otherwise returns /// null. static Value *ThreadCmpOverSelect(CmpInst::Predicate Pred, Value *LHS, - Value *RHS, const TargetData *TD) { + Value *RHS, const TargetData *TD, + unsigned MaxRecurse) { // Make sure the select is on the LHS. if (!isa(LHS)) { std::swap(LHS, RHS); @@ -105,9 +113,11 @@ // Now that we have "cmp select(cond, TV, FV), RHS", analyse it. // Does "cmp TV, RHS" simplify? - if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD)) + if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD, + MaxRecurse)) // It does! Does "cmp FV, RHS" simplify? - if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD)) + if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD, + MaxRecurse)) // It does! If they simplified to the same value, then use it as the // result of the original comparison. if (TCmp == FCmp) @@ -115,6 +125,65 @@ return 0; } +/// ThreadBinOpOverPHI - In the case of a binary operation with an operand that +/// is a PHI instruction, try to simplify the binop by seeing whether evaluating +/// it on the incoming phi values yields the same result for every value. If so +/// returns the common value, otherwise returns null. +static Value *ThreadBinOpOverPHI(unsigned Opcode, Value *LHS, Value *RHS, + const TargetData *TD, unsigned MaxRecurse) { + PHINode *PI; + if (isa(LHS)) { + PI = cast(LHS); + } else { + assert(isa(RHS) && "No PHI instruction operand!"); + PI = cast(RHS); + } + + // Evaluate the BinOp on the incoming phi values. + Value *CommonValue = 0; + for (unsigned i = 0, e = PI->getNumIncomingValues(); i != e; ++i) { + Value *V = PI == LHS ? + SimplifyBinOp(Opcode, PI->getIncomingValue(i), RHS, TD, MaxRecurse) : + SimplifyBinOp(Opcode, LHS, PI->getIncomingValue(i), TD, MaxRecurse); + // If the operation failed to simplify, or simplified to a different value + // to previously, then give up. + if (!V || (CommonValue && V != CommonValue)) + return 0; + CommonValue = V; + } + + return CommonValue; +} + +/// ThreadCmpOverPHI - In the case of a comparison with a PHI instruction, try +/// try to simplify the comparison by seeing whether comparing with all of the +/// incoming phi values yields the same result every time. If so returns the +/// common result, otherwise returns null. +static Value *ThreadCmpOverPHI(CmpInst::Predicate Pred, Value *LHS, Value *RHS, + const TargetData *TD, unsigned MaxRecurse) { + // Make sure the phi is on the LHS. + if (!isa(LHS)) { + std::swap(LHS, RHS); + Pred = CmpInst::getSwappedPredicate(Pred); + } + assert(isa(LHS) && "Not comparing with a phi instruction!"); + PHINode *PI = cast(LHS); + + // Evaluate the BinOp on the incoming phi values. + Value *CommonValue = 0; + for (unsigned i = 0, e = PI->getNumIncomingValues(); i != e; ++i) { + Value *V = SimplifyCmpInst(Pred, PI->getIncomingValue(i), RHS, TD, + MaxRecurse); + // If the operation failed to simplify, or simplified to a different value + // to previously, then give up. + if (!V || (CommonValue && V != CommonValue)) + return 0; + CommonValue = V; + } + + return CommonValue; +} + /// SimplifyAddInst - Given operands for an Add, see if we can /// fold the result. If not, this returns null. Value *llvm::SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, @@ -146,7 +215,8 @@ /// SimplifyAndInst - Given operands for an And, see if we can /// fold the result. If not, this returns null. -Value *llvm::SimplifyAndInst(Value *Op0, Value *Op1, const TargetData *TD) { +static Value *SimplifyAndInst(Value *Op0, Value *Op1, const TargetData *TD, + unsigned MaxRecurse) { if (Constant *CLHS = dyn_cast(Op0)) { if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; @@ -212,16 +282,29 @@ // If the operation is with the result of a select instruction, check whether // operating on either branch of the select always yields the same value. - if (isa(Op0) || isa(Op1)) - if (Value *V = ThreadBinOpOverSelect(Instruction::And, Op0, Op1, TD)) + if (MaxRecurse && (isa(Op0) || isa(Op1))) + if (Value *V = ThreadBinOpOverSelect(Instruction::And, Op0, Op1, TD, + MaxRecurse-1)) + return V; + + // If the operation is with the result of a phi instruction, check whether + // operating on all incoming values of the phi always yields the same value. + if (MaxRecurse && (isa(Op0) || isa(Op1))) + if (Value *V = ThreadBinOpOverPHI(Instruction::And, Op0, Op1, TD, + MaxRecurse-1)) return V; return 0; } +Value *llvm::SimplifyAndInst(Value *Op0, Value *Op1, const TargetData *TD) { + return ::SimplifyAndInst(Op0, Op1, TD, MaxRecursionDepth); +} + /// SimplifyOrInst - Given operands for an Or, see if we can /// fold the result. If not, this returns null. -Value *llvm::SimplifyOrInst(Value *Op0, Value *Op1, const TargetData *TD) { +static Value *SimplifyOrInst(Value *Op0, Value *Op1, const TargetData *TD, + unsigned MaxRecurse) { if (Constant *CLHS = dyn_cast(Op0)) { if (Constant *CRHS = dyn_cast(Op1)) { Constant *Ops[] = { CLHS, CRHS }; @@ -287,13 +370,24 @@ // If the operation is with the result of a select instruction, check whether // operating on either branch of the select always yields the same value. - if (isa(Op0) || isa(Op1)) - if (Value *V = ThreadBinOpOverSelect(Instruction::Or, Op0, Op1, TD)) + if (MaxRecurse && (isa(Op0) || isa(Op1))) + if (Value *V = ThreadBinOpOverSelect(Instruction::Or, Op0, Op1, TD, + MaxRecurse-1)) + return V; + + // If the operation is with the result of a phi instruction, check whether + // operating on all incoming values of the phi always yields the same value. + if (MaxRecurse && (isa(Op0) || isa(Op1))) + if (Value *V = ThreadBinOpOverPHI(Instruction::Or, Op0, Op1, TD, + MaxRecurse-1)) return V; return 0; } +Value *llvm::SimplifyOrInst(Value *Op0, Value *Op1, const TargetData *TD) { + return ::SimplifyOrInst(Op0, Op1, TD, MaxRecursionDepth); +} static const Type *GetCompareTy(Value *Op) { return CmpInst::makeCmpResultType(Op->getType()); @@ -301,8 +395,8 @@ /// SimplifyICmpInst - Given operands for an ICmpInst, see if we can /// fold the result. If not, this returns null. -Value *llvm::SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS, - const TargetData *TD) { +static Value *SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS, + const TargetData *TD, unsigned MaxRecurse) { CmpInst::Predicate Pred = (CmpInst::Predicate)Predicate; assert(CmpInst::isIntPredicate(Pred) && "Not an integer compare!"); @@ -360,17 +454,28 @@ // If the comparison is with the result of a select instruction, check whether // comparing with either branch of the select always yields the same value. - if (isa(LHS) || isa(RHS)) - if (Value *V = ThreadCmpOverSelect(Pred, LHS, RHS, TD)) + if (MaxRecurse && (isa(LHS) || isa(RHS))) + if (Value *V = ThreadCmpOverSelect(Pred, LHS, RHS, TD, MaxRecurse-1)) + return V; + + // If the comparison is with the result of a phi instruction, check whether + // doing the compare with each incoming phi value yields a common result. + if (MaxRecurse && (isa(LHS) || isa(RHS))) + if (Value *V = ThreadCmpOverPHI(Pred, LHS, RHS, TD, MaxRecurse-1)) return V; return 0; } +Value *llvm::SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS, + const TargetData *TD) { + return ::SimplifyICmpInst(Predicate, LHS, RHS, TD, MaxRecursionDepth); +} + /// SimplifyFCmpInst - Given operands for an FCmpInst, see if we can /// fold the result. If not, this returns null. -Value *llvm::SimplifyFCmpInst(unsigned Predicate, Value *LHS, Value *RHS, - const TargetData *TD) { +static Value *SimplifyFCmpInst(unsigned Predicate, Value *LHS, Value *RHS, + const TargetData *TD, unsigned MaxRecurse) { CmpInst::Predicate Pred = (CmpInst::Predicate)Predicate; assert(CmpInst::isFPPredicate(Pred) && "Not an FP compare!"); @@ -443,13 +548,24 @@ // If the comparison is with the result of a select instruction, check whether // comparing with either branch of the select always yields the same value. - if (isa(LHS) || isa(RHS)) - if (Value *V = ThreadCmpOverSelect(Pred, LHS, RHS, TD)) + if (MaxRecurse && (isa(LHS) || isa(RHS))) + if (Value *V = ThreadCmpOverSelect(Pred, LHS, RHS, TD, MaxRecurse-1)) + return V; + + // If the comparison is with the result of a phi instruction, check whether + // doing the compare with each incoming phi value yields a common result. + if (MaxRecurse && (isa(LHS) || isa(RHS))) + if (Value *V = ThreadCmpOverPHI(Pred, LHS, RHS, TD, MaxRecurse-1)) return V; return 0; } +Value *llvm::SimplifyFCmpInst(unsigned Predicate, Value *LHS, Value *RHS, + const TargetData *TD) { + return ::SimplifyFCmpInst(Predicate, LHS, RHS, TD, MaxRecursionDepth); +} + /// SimplifySelectInst - Given operands for a SelectInst, see if we can fold /// the result. If not, this returns null. Value *llvm::SimplifySelectInst(Value *CondVal, Value *TrueVal, Value *FalseVal, @@ -509,11 +625,11 @@ /// SimplifyBinOp - Given operands for a BinaryOperator, see if we can /// fold the result. If not, this returns null. -Value *llvm::SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, - const TargetData *TD) { +static Value *SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, + const TargetData *TD, unsigned MaxRecurse) { switch (Opcode) { - case Instruction::And: return SimplifyAndInst(LHS, RHS, TD); - case Instruction::Or: return SimplifyOrInst(LHS, RHS, TD); + case Instruction::And: return SimplifyAndInst(LHS, RHS, TD, MaxRecurse); + case Instruction::Or: return SimplifyOrInst(LHS, RHS, TD, MaxRecurse); default: if (Constant *CLHS = dyn_cast(LHS)) if (Constant *CRHS = dyn_cast(RHS)) { @@ -523,23 +639,38 @@ // If the operation is with the result of a select instruction, check whether // operating on either branch of the select always yields the same value. - if (isa(LHS) || isa(RHS)) - if (Value *V = ThreadBinOpOverSelect(Opcode, LHS, RHS, TD)) + if (MaxRecurse && (isa(LHS) || isa(RHS))) + if (Value *V = ThreadBinOpOverSelect(Opcode, LHS, RHS, TD, MaxRecurse-1)) + return V; + + // If the operation is with the result of a phi instruction, check whether + // operating on all incoming values of the phi always yields the same value. + if (MaxRecurse && (isa(LHS) || isa(RHS))) + if (Value *V = ThreadBinOpOverPHI(Opcode, LHS, RHS, TD, MaxRecurse-1)) return V; return 0; } } +Value *llvm::SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, + const TargetData *TD) { + return ::SimplifyBinOp(Opcode, LHS, RHS, TD, MaxRecursionDepth); +} + /// SimplifyCmpInst - Given operands for a CmpInst, see if we can /// fold the result. -Value *llvm::SimplifyCmpInst(unsigned Predicate, Value *LHS, Value *RHS, - const TargetData *TD) { +static Value *SimplifyCmpInst(unsigned Predicate, Value *LHS, Value *RHS, + const TargetData *TD, unsigned MaxRecurse) { if (CmpInst::isIntPredicate((CmpInst::Predicate)Predicate)) - return SimplifyICmpInst(Predicate, LHS, RHS, TD); - return SimplifyFCmpInst(Predicate, LHS, RHS, TD); + return SimplifyICmpInst(Predicate, LHS, RHS, TD, MaxRecurse); + return SimplifyFCmpInst(Predicate, LHS, RHS, TD, MaxRecurse); } +Value *llvm::SimplifyCmpInst(unsigned Predicate, Value *LHS, Value *RHS, + const TargetData *TD) { + return ::SimplifyCmpInst(Predicate, LHS, RHS, TD, MaxRecursionDepth); +} /// SimplifyInstruction - See if we can compute a simplified version of this /// instruction. If not, this returns null. Modified: llvm/trunk/test/Transforms/InstCombine/select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select.ll?rev=118694&r1=118693&r2=118694&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/select.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/select.ll Wed Nov 10 12:23:01 2010 @@ -499,3 +499,50 @@ ; CHECK: @test40 ; CHECK: ret i1 false } + +define i1 @test41(i1 %cond) { + %zero = alloca i32 + %one = alloca i32 + br i1 %cond, label %true, label %false +true: + br label %ret +false: + br label %ret +ret: + %ptr = phi i32* [ %zero, %true ] , [ %one, %false ] + %isnull = icmp eq i32* %ptr, null + ret i1 %isnull +; CHECK: @test41 +; CHECK: ret i1 false +} + +define i1 @test42(i1 %cond, double %x) { + br i1 %cond, label %true, label %false +true: + br label %ret +false: + br label %ret +ret: + %p = phi double [ %x, %true ], [ 0x7FF0000000000000, %false ]; RHS = +infty + %cmp = fcmp ule double %x, %p + ret i1 %cmp +; CHECK: @test42 +; CHECK: ret i1 true +} + +define i1 @test43(i1 %cond) { + %a = alloca i32 + %b = alloca i32 + %c = alloca i32 + br i1 %cond, label %true, label %false +true: + br label %ret +false: + br label %ret +ret: + %p = phi i32* [ %a, %true ], [ %b, %false ] + %r = icmp eq i32* %p, %c + ret i1 %r +; CHECK: @test43 +; CHECK: ret i1 false +} From gohman at apple.com Wed Nov 10 12:30:00 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 18:30:00 -0000 Subject: [llvm-commits] [llvm] r118696 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h utils/TableGen/IntrinsicEmitter.cpp Message-ID: <20101110183000.6DA682A6C12C@llvm.org> Author: djg Date: Wed Nov 10 12:30:00 2010 New Revision: 118696 URL: http://llvm.org/viewvc/llvm-project?rev=118696&view=rev Log: Rename AccessesArguments and AccessesArgumentsReadonly, and rewrite their comments. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118696&r1=118695&r2=118696&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Wed Nov 10 12:30:00 2010 @@ -192,18 +192,19 @@ /// This property corresponds to the IntrNoMem LLVM intrinsic flag. DoesNotAccessMemory = Nowhere | NoModRef, - /// AccessesArgumentsReadonly - This function loads through function - /// arguments and does not perform any non-local stores or volatile - /// loads. + /// OnlyReadsArgumentPointees - The only memory references in this function + /// (if it has any) are non-volatile loads from objects pointed to by its + /// pointer-typed arguments, with arbitrary offsets. /// /// This property corresponds to the IntrReadArgMem LLVM intrinsic flag. - AccessesArgumentsReadonly = ArgumentPointees | Ref, + OnlyReadsArgumentPointees = ArgumentPointees | Ref, - /// AccessesArguments - This function accesses function arguments in well - /// known (possibly volatile) ways, but does not access any other memory. + /// OnlyAccessesArgumentPointees - The only memory references in this + /// function (if it has any) are non-volatile loads and stores from objects + /// pointed to by its pointer-typed arguments, with arbitrary offsets. /// /// This property corresponds to the IntrReadWriteArgMem LLVM intrinsic flag. - AccessesArguments = ArgumentPointees | ModRef, + OnlyAccessesArgumentPointees = ArgumentPointees | ModRef, /// OnlyReadsMemory - This function does not perform any non-local stores or /// volatile loads, but may read from any memory location. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=118696&r1=118695&r2=118696&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Wed Nov 10 12:30:00 2010 @@ -573,13 +573,13 @@ OS << " return DoesNotAccessMemory;\n"; break; case CodeGenIntrinsic::ReadArgMem: - OS << " return AccessesArgumentsReadonly;\n"; + OS << " return OnlyReadsArgumentPointees;\n"; break; case CodeGenIntrinsic::ReadMem: OS << " return OnlyReadsMemory;\n"; break; case CodeGenIntrinsic::ReadWriteArgMem: - OS << " return AccessesArguments;\n"; + OS << " return OnlyAccessesArgumentPointees;\n"; break; } } From gohman at apple.com Wed Nov 10 13:03:33 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 19:03:33 -0000 Subject: [llvm-commits] [llvm] r118698 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20101110190333.DCF692A6C12C@llvm.org> Author: djg Date: Wed Nov 10 13:03:33 2010 New Revision: 118698 URL: http://llvm.org/viewvc/llvm-project?rev=118698&view=rev Log: Use getValueOperand() and getPointerOperand() on load and store instructions instead of hard-coding operand numbers. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=118698&r1=118697&r2=118698&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Nov 10 13:03:33 2010 @@ -1071,12 +1071,12 @@ StoreInst *DepSI, const TargetData &TD) { // Cannot handle reading from store of first-class aggregate yet. - if (DepSI->getOperand(0)->getType()->isStructTy() || - DepSI->getOperand(0)->getType()->isArrayTy()) + if (DepSI->getValueOperand()->getType()->isStructTy() || + DepSI->getValueOperand()->getType()->isArrayTy()) return -1; Value *StorePtr = DepSI->getPointerOperand(); - uint64_t StoreSize = TD.getTypeSizeInBits(DepSI->getOperand(0)->getType()); + uint64_t StoreSize =TD.getTypeSizeInBits(DepSI->getValueOperand()->getType()); return AnalyzeLoadFromClobberingWrite(LoadTy, LoadPtr, StorePtr, StoreSize, TD); } @@ -1351,7 +1351,8 @@ SmallVectorImpl &toErase) { // Find the non-local dependencies of the load. SmallVector Deps; - MD->getNonLocalPointerDependency(LI->getOperand(0), true, LI->getParent(), + MD->getNonLocalPointerDependency(LI->getPointerOperand(), true, + LI->getParent(), Deps); //DEBUG(dbgs() << "INVESTIGATING NONLOCAL LOAD: " // << Deps.size() << *LI << '\n'); @@ -1403,7 +1404,7 @@ DepSI, *TD); if (Offset != -1) { ValuesPerBlock.push_back(AvailableValueInBlock::get(DepBB, - DepSI->getOperand(0), + DepSI->getValueOperand(), Offset)); continue; } @@ -1444,13 +1445,13 @@ if (StoreInst *S = dyn_cast(DepInst)) { // Reject loads and stores that are to the same address but are of // different types if we have to. - if (S->getOperand(0)->getType() != LI->getType()) { + if (S->getValueOperand()->getType() != LI->getType()) { if (TD == 0) TD = getAnalysisIfAvailable(); // If the stored value is larger or equal to the loaded value, we can // reuse it. - if (TD == 0 || !CanCoerceMustAliasedValueToLoad(S->getOperand(0), + if (TD == 0 || !CanCoerceMustAliasedValueToLoad(S->getValueOperand(), LI->getType(), *TD)) { UnavailableBlocks.push_back(DepBB); continue; @@ -1458,7 +1459,7 @@ } ValuesPerBlock.push_back(AvailableValueInBlock::get(DepBB, - S->getOperand(0))); + S->getValueOperand())); continue; } @@ -1630,7 +1631,7 @@ // If all preds have a single successor, then we know it is safe to insert // the load on the pred (?!?), so we can insert code to materialize the // pointer if it is not available. - PHITransAddr Address(LI->getOperand(0), TD); + PHITransAddr Address(LI->getPointerOperand(), TD); Value *LoadPtr = 0; if (allSingleSucc) { LoadPtr = Address.PHITranslateWithInsertion(LoadBB, UnavailablePred, @@ -1644,7 +1645,7 @@ // we fail PRE. if (LoadPtr == 0) { DEBUG(dbgs() << "COULDN'T INSERT PHI TRANSLATED VALUE OF: " - << *LI->getOperand(0) << "\n"); + << *LI->getPointerOperand() << "\n"); CanDoPRE = false; break; } @@ -1754,7 +1755,7 @@ L->getPointerOperand(), DepSI, *TD); if (Offset != -1) - AvailVal = GetStoreValueForLoad(DepSI->getOperand(0), Offset, + AvailVal = GetStoreValueForLoad(DepSI->getValueOperand(), Offset, L->getType(), L, *TD); } @@ -1800,7 +1801,7 @@ Instruction *DepInst = Dep.getInst(); if (StoreInst *DepSI = dyn_cast(DepInst)) { - Value *StoredVal = DepSI->getOperand(0); + Value *StoredVal = DepSI->getValueOperand(); // The store and load are to a must-aliased pointer, but they may not // actually have the same type. See if we know how to reuse the stored From rafael.espindola at gmail.com Wed Nov 10 13:05:08 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 10 Nov 2010 19:05:08 -0000 Subject: [llvm-commits] [llvm] r118699 - in /llvm/trunk: include/llvm/MC/MCContext.h lib/MC/ELFObjectWriter.cpp lib/MC/MCContext.cpp Message-ID: <20101110190508.252B32A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 13:05:07 2010 New Revision: 118699 URL: http://llvm.org/viewvc/llvm-project?rev=118699&view=rev Log: Use MCSectionELF in places we know we have an ELF section. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCContext.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=118699&r1=118698&r2=118699&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Wed Nov 10 13:05:07 2010 @@ -30,6 +30,7 @@ class StringRef; class Twine; class MCSectionMachO; + class MCSectionELF; /// MCContext - Context object for machine code objects. This class owns all /// of the sections that it creates. @@ -138,9 +139,9 @@ return getMachOSection(Segment, Section, TypeAndAttributes, 0, K); } - const MCSection *getELFSection(StringRef Section, unsigned Type, - unsigned Flags, SectionKind Kind, - unsigned EntrySize = 0); + const MCSectionELF *getELFSection(StringRef Section, unsigned Type, + unsigned Flags, SectionKind Kind, + unsigned EntrySize = 0); const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics, int Selection, SectionKind Kind); Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118699&r1=118698&r2=118699&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 13:05:07 2010 @@ -1048,7 +1048,7 @@ const MCSectionData &SD) { if (!Relocations[&SD].empty()) { MCContext &Ctx = Asm.getContext(); - const MCSection *RelaSection; + const MCSectionELF *RelaSection; const MCSectionELF &Section = static_cast(SD.getSection()); @@ -1154,14 +1154,14 @@ unsigned NumRegularSections = Asm.size(); // We construct .shstrtab, .symtab and .strtab in this order to match gnu as. - const MCSection *ShstrtabSection = + const MCSectionELF *ShstrtabSection = Ctx.getELFSection(".shstrtab", ELF::SHT_STRTAB, 0, SectionKind::getReadOnly(), false); MCSectionData &ShstrtabSD = Asm.getOrCreateSectionData(*ShstrtabSection); ShstrtabSD.setAlignment(1); ShstrtabIndex = Asm.size(); - const MCSection *SymtabSection = + const MCSectionELF *SymtabSection = Ctx.getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), EntrySize); @@ -1172,7 +1172,7 @@ MCSectionData *SymtabShndxSD = NULL; if (NeedsSymtabShndx) { - const MCSection *SymtabShndxSection = + const MCSectionELF *SymtabShndxSection = Ctx.getELFSection(".symtab_shndx", ELF::SHT_SYMTAB_SHNDX, 0, SectionKind::getReadOnly(), 4); SymtabShndxSD = &Asm.getOrCreateSectionData(*SymtabShndxSection); @@ -1350,8 +1350,8 @@ case ELF::SHT_REL: case ELF::SHT_RELA: { - const MCSection *SymtabSection; - const MCSection *InfoSection; + const MCSectionELF *SymtabSection; + const MCSectionELF *InfoSection; SymtabSection = Asm.getContext().getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=118699&r1=118698&r2=118699&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Wed Nov 10 13:05:07 2010 @@ -148,8 +148,7 @@ Reserved2, Kind); } - -const MCSection *MCContext:: +const MCSectionELF *MCContext:: getELFSection(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind, unsigned EntrySize) { if (ELFUniquingMap == 0) From atrick at apple.com Wed Nov 10 13:18:47 2010 From: atrick at apple.com (Andrew Trick) Date: Wed, 10 Nov 2010 19:18:47 -0000 Subject: [llvm-commits] [llvm] r118701 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/InlineSpiller.cpp lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/LiveIntervalUnion.cpp lib/CodeGen/LiveIntervalUnion.h lib/CodeGen/RegAllocBase.h lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/Spiller.cpp lib/CodeGen/Spiller.h Message-ID: <20101110191847.433B22A6C12C@llvm.org> Author: atrick Date: Wed Nov 10 13:18:47 2010 New Revision: 118701 URL: http://llvm.org/viewvc/llvm-project?rev=118701&view=rev Log: RABasic is nearly functionally complete. There are a few remaining benchmarks hitting an assertion. Adds LiveIntervalUnion::collectInterferingVRegs. Fixes "late spilling" by checking for any unspillable live vregs among all physReg aliases. Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/lib/CodeGen/InlineSpiller.cpp llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp llvm/trunk/lib/CodeGen/Spiller.cpp llvm/trunk/lib/CodeGen/Spiller.h Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Wed Nov 10 13:18:47 2010 @@ -270,7 +270,7 @@ /// (if any is created) by reference. This is temporary. std::vector addIntervalsForSpills(const LiveInterval& i, - SmallVectorImpl &SpillIs, + const SmallVectorImpl &SpillIs, const MachineLoopInfo *loopInfo, VirtRegMap& vrm); /// spillPhysRegAroundRegDefsUses - Spill the specified physical register @@ -283,7 +283,7 @@ /// val# of the specified interval is re-materializable. Also returns true /// by reference if all of the defs are load instructions. bool isReMaterializable(const LiveInterval &li, - SmallVectorImpl &SpillIs, + const SmallVectorImpl &SpillIs, bool &isLoad); /// isReMaterializable - Returns true if the definition MI of the specified @@ -360,7 +360,7 @@ /// by reference if the def is a load. bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo, MachineInstr *MI, - SmallVectorImpl &SpillIs, + const SmallVectorImpl &SpillIs, bool &isLoad); /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Nov 10 13:18:47 2010 @@ -86,7 +86,7 @@ void spill(LiveInterval *li, SmallVectorImpl &newIntervals, - SmallVectorImpl &spillIs); + const SmallVectorImpl &spillIs); void spill(LiveRangeEdit &); @@ -352,7 +352,7 @@ void InlineSpiller::spill(LiveInterval *li, SmallVectorImpl &newIntervals, - SmallVectorImpl &spillIs) { + const SmallVectorImpl &spillIs) { LiveRangeEdit edit(*li, newIntervals, spillIs); spill(edit); if (VerifySpills) Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Nov 10 13:18:47 2010 @@ -802,10 +802,11 @@ /// isReMaterializable - Returns true if the definition MI of the specified /// val# of the specified interval is re-materializable. -bool LiveIntervals::isReMaterializable(const LiveInterval &li, - const VNInfo *ValNo, MachineInstr *MI, - SmallVectorImpl &SpillIs, - bool &isLoad) { +bool +LiveIntervals::isReMaterializable(const LiveInterval &li, + const VNInfo *ValNo, MachineInstr *MI, + const SmallVectorImpl &SpillIs, + bool &isLoad) { if (DisableReMat) return false; @@ -849,9 +850,10 @@ /// isReMaterializable - Returns true if every definition of MI of every /// val# of the specified interval is re-materializable. -bool LiveIntervals::isReMaterializable(const LiveInterval &li, - SmallVectorImpl &SpillIs, - bool &isLoad) { +bool +LiveIntervals::isReMaterializable(const LiveInterval &li, + const SmallVectorImpl &SpillIs, + bool &isLoad) { isLoad = false; for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end(); i != e; ++i) { @@ -1556,7 +1558,7 @@ std::vector LiveIntervals:: addIntervalsForSpills(const LiveInterval &li, - SmallVectorImpl &SpillIs, + const SmallVectorImpl &SpillIs, const MachineLoopInfo *loopInfo, VirtRegMap &vrm) { assert(li.isSpillable() && "attempt to spill already spilled interval!"); Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Wed Nov 10 13:18:47 2010 @@ -164,7 +164,7 @@ while (ir.liuSegI_ != liuEnd) { // Slowly advance the live virtual reg iterator until we surpass the next // segment in this union. If this is ever used for coalescing of fixed - // registers and we have a LiveInterval with thousands of segments, then use + // registers and we have a live vreg with thousands of segments, then use // upper bound instead. while (ir.lvrSegI_ != lvrEnd && ir.lvrSegI_->end <= ir.liuSegI_->start) ++ir.lvrSegI_; @@ -220,3 +220,73 @@ findIntersection(ir); return isInterference(ir); } + +// Scan the vector of interfering virtual registers in this union. Assuming it's +// quite small. +bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *lvr) const { + SmallVectorImpl::const_iterator I = + std::find(interferingVRegs_.begin(), interferingVRegs_.end(), lvr); + return I != interferingVRegs_.end(); +} + +// Count the number of virtual registers in this union that interfere with this +// query's live virtual register. +// +// The number of times that we either advance ir.lvrSegI_ or call +// liu_.upperBound() will be no more than the number of holes in +// lvr_. So each invocation of collectInterferingVirtReg() takes +// time proportional to |lvr-holes| * time(liu_.upperBound()). +// +// For comments on how to speed it up, see Query::findIntersection(). +unsigned LiveIntervalUnion::Query:: +collectInterferingVRegs(unsigned maxInterferingRegs) { + InterferenceResult ir = firstInterference(); + LiveInterval::iterator lvrEnd = lvr_->end(); + SegmentIter liuEnd = liu_->end(); + LiveInterval *recentInterferingVReg = NULL; + while (ir.liuSegI_ != liuEnd) { + // Advance the union's iterator to reach an unseen interfering vreg. + do { + if (ir.liuSegI_->liveVirtReg == recentInterferingVReg) + continue; + + if (!isSeenInterference(ir.liuSegI_->liveVirtReg)) + break; + + // Cache the most recent interfering vreg to bypass isSeenInterference. + recentInterferingVReg = ir.liuSegI_->liveVirtReg; + + } while( ++ir.liuSegI_ != liuEnd); + if (ir.liuSegI_ == liuEnd) + break; + + // Advance the live vreg reg iterator until surpassing the next + // segment in this union. If this is ever used for coalescing of fixed + // registers and we have a live vreg with thousands of segments, then use + // upper bound instead. + while (ir.lvrSegI_ != lvrEnd && ir.lvrSegI_->end <= ir.liuSegI_->start) + ++ir.lvrSegI_; + if (ir.lvrSegI_ == lvrEnd) + break; + + // Check for intersection with the union's segment. + if (overlap(*ir.lvrSegI_, *ir.liuSegI_)) { + if (!ir.liuSegI_->liveVirtReg->isSpillable()) + seenUnspillableVReg_ = true; + + interferingVRegs_.push_back(ir.liuSegI_->liveVirtReg); + if (interferingVRegs_.size() == maxInterferingRegs) + return maxInterferingRegs; + + // Cache the most recent interfering vreg to bypass isSeenInterference. + recentInterferingVReg = ir.liuSegI_->liveVirtReg; + ++ir.liuSegI_; + continue; + } + // lvrSegI_ may have advanced far beyond liuSegI_, + // do a fast intersection test to "catch up" + LiveSegment seg(ir.lvrSegI_->start, ir.lvrSegI_->end, lvr_); + ir.liuSegI_ = liu_->upperBound(ir.liuSegI_, seg); + } + return interferingVRegs_.size(); +} Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Wed Nov 10 13:18:47 2010 @@ -174,10 +174,10 @@ // result has no way to tell if it's valid to dereference them. // Access the lvr segment. - const LiveInterval::iterator &lvrSegPos() const { return lvrSegI_; } + LiveInterval::iterator lvrSegPos() const { return lvrSegI_; } // Access the liu segment. - const SegmentIter &liuSegPos() const { return liuSegI_; } + SegmentIter liuSegPos() const { return liuSegI_; } bool operator==(const InterferenceResult &ir) const { return lvrSegI_ == ir.lvrSegI_ && liuSegI_ == ir.liuSegI_; @@ -193,17 +193,21 @@ LiveIntervalUnion *liu_; LiveInterval *lvr_; InterferenceResult firstInterference_; - // TBD: interfering vregs + SmallVector interferingVRegs_; + bool seenUnspillableVReg_; public: Query(): liu_(), lvr_() {} - Query(LiveInterval *lvr, LiveIntervalUnion *liu): liu_(liu), lvr_(lvr) {} + Query(LiveInterval *lvr, LiveIntervalUnion *liu): + liu_(liu), lvr_(lvr), seenUnspillableVReg_(false) {} void clear() { liu_ = NULL; lvr_ = NULL; firstInterference_ = InterferenceResult(); + interferingVRegs_.clear(); + seenUnspillableVReg_ = false; } void init(LiveInterval *lvr, LiveIntervalUnion *liu) { @@ -218,6 +222,8 @@ lvr_ = lvr; // Clear cached results. firstInterference_ = InterferenceResult(); + interferingVRegs_.clear(); + seenUnspillableVReg_ = false; } LiveInterval &lvr() const { assert(lvr_ && "uninitialized"); return *lvr_; } @@ -242,9 +248,24 @@ // of segments. Visiting each unique interfering pairs means that the same // lvr or liu segment may be visited multiple times. bool nextInterference(InterferenceResult &ir) const; - - // TBD: bool collectInterferingVirtRegs(unsigned maxInterference) + // Count the virtual registers in this union that interfere with this + // query's live virtual register, up to maxInterferingRegs. + unsigned collectInterferingVRegs(unsigned maxInterferingRegs = UINT_MAX); + + // Was this virtual register visited during collectInterferingVRegs? + bool isSeenInterference(LiveInterval *lvr) const; + + // Did collectInterferingVRegs encounter an unspillable vreg? + bool seenUnspillableVReg() const { + return seenUnspillableVReg_; + } + + // Vector generated by collectInterferingVRegs. + const SmallVectorImpl &interferingVRegs() const { + return interferingVRegs_; + } + private: // Private interface for queries void findIntersection(InterferenceResult &ir) const; Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Wed Nov 10 13:18:47 2010 @@ -45,6 +45,7 @@ class TargetRegisterInfo; class VirtRegMap; class LiveIntervals; +class Spiller; // Heuristic that determines the priority of assigning virtual to physical // registers. The main impact of the heuristic is expected to be compile time. @@ -113,6 +114,9 @@ // LiveVirtRegQueue. void allocatePhysRegs(); + // Get a temporary reference to a Spiller instance. + virtual Spiller &spiller() = 0; + // A RegAlloc pass should override this to provide the allocation heuristics. // Each call must guarantee forward progess by returning an available PhysReg // or new set of split live virtual registers. It is up to the splitter to @@ -128,18 +132,21 @@ // exists, return the interfering register, which may be preg or an alias. unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg); + // Helper for spilling all live virtual registers currently unified under preg + // that interfere with the most recently queried lvr. Return true if spilling + // was successful, and append any new spilled/split intervals to splitLVRs. + bool spillInterferences(unsigned preg, + SmallVectorImpl &splitLVRs); + #ifndef NDEBUG // Verify each LiveIntervalUnion. void verify(); #endif - // Helper that spills all live virtual registers currently unified under preg - // that interfere with the most recently queried lvr. - void spillInterferences(unsigned preg, - SmallVectorImpl &splitLVRs); - private: void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ); + + void spillReg(unsigned reg, SmallVectorImpl &splitLVRs); }; } // end namespace llvm Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Wed Nov 10 13:18:47 2010 @@ -96,12 +96,11 @@ virtual void releaseMemory(); + virtual Spiller &spiller() { return *spiller_; } + virtual unsigned selectOrSplit(LiveInterval &lvr, SmallVectorImpl &splitLVRs); - void spillInterferences(unsigned preg, - SmallVectorImpl &splitLVRs); - /// Perform register allocation. virtual bool runOnMachineFunction(MachineFunction &mf); @@ -326,35 +325,70 @@ return 0; } +// Sort live virtual registers by their register number. +struct LessLiveVirtualReg + : public std::binary_function { + bool operator()(const LiveInterval *left, const LiveInterval *right) const { + return left->reg < right->reg; + } +}; + +// Spill all interferences currently assigned to this physical register. +void RegAllocBase::spillReg(unsigned reg, + SmallVectorImpl &splitLVRs) { + LiveIntervalUnion::Query &query = queries_[reg]; + const SmallVectorImpl &pendingSpills = + query.interferingVRegs(); + for (SmallVectorImpl::const_iterator I = pendingSpills.begin(), + E = pendingSpills.end(); I != E; ++I) { + LiveInterval &lvr = **I; + DEBUG(dbgs() << + "extracting from " << tri_->getName(reg) << " " << lvr << '\n'); + + // Deallocate the interfering vreg by removing it from the union. + // A LiveInterval instance may not be in a union during modification! + physReg2liu_[reg].extract(lvr); + + // After extracting segments, the query's results are invalid. + query.clear(); + + // Clear the vreg assignment. + vrm_->clearVirt(lvr.reg); + + // Spill the extracted interval. + spiller().spill(&lvr, splitLVRs, pendingSpills); + } +} + // Spill or split all live virtual registers currently unified under preg that // interfere with lvr. The newly spilled or split live intervals are returned by // appending them to splitLVRs. -void RABasic::spillInterferences(unsigned preg, +bool +RegAllocBase::spillInterferences(unsigned preg, SmallVectorImpl &splitLVRs) { - SmallPtrSet spilledLVRs; - LiveIntervalUnion::Query &query = queries_[preg]; - // Record each interference before mutating either the union or live - // intervals. - LiveIntervalUnion::InterferenceResult ir = query.firstInterference(); - assert(query.isInterference(ir) && "expect interference"); - do { - spilledLVRs.insert(ir.liuSegPos()->liveVirtReg); - } while (query.nextInterference(ir)); - for (SmallPtrSetIterator lvrI = spilledLVRs.begin(), - lvrEnd = spilledLVRs.end(); - lvrI != lvrEnd; ++lvrI ) { - LiveInterval& lvr = **lvrI; - // Spill the previously allocated lvr. - DEBUG(dbgs() << "extracting from " << preg << " " << lvr << '\n'); - // Deallocate the interfering lvr by removing it from the preg union. - // Live intervals may not be in a union during modification. - physReg2liu_[preg].extract(lvr); - // Spill the extracted interval. - SmallVector spillIs; - spiller_->spill(&lvr, splitLVRs, spillIs); + // Record each interference and determine if all are spillable before mutating + // either the union or live intervals. + std::vector spilledLVRs; + + unsigned numInterferences = queries_[preg].collectInterferingVRegs(); + if (queries_[preg].seenUnspillableVReg()) { + return false; + } + for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) { + numInterferences += queries_[*asI].collectInterferingVRegs(); + if (queries_[*asI].seenUnspillableVReg()) { + return false; + } } - // After extracting segments, the query's results are invalid. - query.clear(); + DEBUG(dbgs() << "spilling " << tri_->getName(preg) << + " interferences with " << queries_[preg].lvr() << "\n"); + assert(numInterferences > 0 && "expect interference"); + + // Spill each interfering vreg allocated to preg or an alias. + spillReg(preg, splitLVRs); + for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) + spillReg(*asI, splitLVRs); + return true; } //===----------------------------------------------------------------------===// @@ -374,53 +408,57 @@ // minimal, there is no value in caching them. unsigned RABasic::selectOrSplit(LiveInterval &lvr, SmallVectorImpl &splitLVRs) { - // Accumulate the min spill cost among the interferences, in case we spill. - unsigned minSpillReg = 0; - unsigned minSpillAlias = 0; - float minSpillWeight = lvr.weight; + // Populate a list of physical register spill candidates. + std::vector pregSpillCands; - // Check for an available reg in this class. + // Check for an available register in this class. const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg); for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_), trcEnd = trc->allocation_order_end(*mf_); trcI != trcEnd; ++trcI) { unsigned preg = *trcI; + // Check interference and intialize queries for this lvr as a side effect. unsigned interfReg = checkPhysRegInterference(lvr, preg); if (interfReg == 0) { + // Found an available register. return preg; } - LiveIntervalUnion::InterferenceResult interf = - queries_[interfReg].firstInterference(); - float interfWeight = interf.liuSegPos()->liveVirtReg->weight; - if (interfWeight < minSpillWeight ) { - minSpillReg = interfReg; - minSpillAlias = preg; - minSpillWeight = interfWeight; + LiveInterval *interferingVirtReg = + queries_[interfReg].firstInterference().liuSegPos()->liveVirtReg; + + // The current lvr must either spillable, or one of its interferences must + // have less spill weight. + if (interferingVirtReg->weight < lvr.weight ) { + pregSpillCands.push_back(preg); } } - if (minSpillReg == 0) { - DEBUG(dbgs() << "spilling: " << lvr << '\n'); - SmallVector spillIs; // ignored - spiller_->spill(&lvr, splitLVRs, spillIs); - // The live virtual register requesting to be allocated was spilled. So tell - // the caller not to allocate anything for this round. - return 0; - } - // Free the cheapest physical register. - spillInterferences(minSpillReg, splitLVRs); - // Tell the caller to allocate to this newly freed physical register. - assert(minSpillAlias != 0 && "need a free register after spilling"); - // We just spilled the first register that interferes with minSpillAlias. We - // now assume minSpillAlias is free because only one register alias may - // interfere at a time. e.g. we ignore predication. - unsigned interfReg = checkPhysRegInterference(lvr, minSpillAlias); - if (interfReg != 0) { - dbgs() << "spilling cannot free " << tri_->getName(minSpillAlias) << - " for " << lvr.reg << " with interference " << - *queries_[interfReg].firstInterference().liuSegPos()->liveVirtReg << "\n"; - llvm_unreachable("Interference after spill."); + // Try to spill another interfering reg with less spill weight. + // + // FIXME: RAGreedy will sort this list by spill weight. + for (std::vector::iterator pregI = pregSpillCands.begin(), + pregE = pregSpillCands.end(); pregI != pregE; ++pregI) { + + if (!spillInterferences(*pregI, splitLVRs)) continue; + + unsigned interfReg = checkPhysRegInterference(lvr, *pregI); + if (interfReg != 0) { + const LiveSegment &seg = + *queries_[interfReg].firstInterference().liuSegPos(); + dbgs() << "spilling cannot free " << tri_->getName(*pregI) << + " for " << lvr.reg << " with interference " << seg.liveVirtReg << "\n"; + llvm_unreachable("Interference after spill."); + } + // Tell the caller to allocate to this newly freed physical register. + return *pregI; } - return minSpillAlias; + // No other spill candidates were found, so spill the current lvr. + DEBUG(dbgs() << "spilling: " << lvr << '\n'); + SmallVector pendingSpills; + spiller().spill(&lvr, splitLVRs, pendingSpills); + + // The live virtual register requesting allocation was spilled, so tell + // the caller not to allocate anything during this round. + return 0; } namespace llvm { Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Nov 10 13:18:47 2010 @@ -183,7 +183,7 @@ void spill(LiveInterval *li, SmallVectorImpl &newIntervals, - SmallVectorImpl &) { + const SmallVectorImpl &) { // Ignore spillIs - we don't use it. trivialSpillEverywhere(li, newIntervals); } @@ -213,7 +213,7 @@ /// Falls back on LiveIntervals::addIntervalsForSpills. void spill(LiveInterval *li, SmallVectorImpl &newIntervals, - SmallVectorImpl &spillIs) { + const SmallVectorImpl &spillIs) { std::vector added = lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm); newIntervals.insert(newIntervals.end(), added.begin(), added.end()); @@ -250,7 +250,7 @@ void spill(LiveInterval *li, SmallVectorImpl &newIntervals, - SmallVectorImpl &spillIs) { + const SmallVectorImpl &spillIs) { if (worthTryingToSplit(li)) tryVNISplit(li); else Modified: llvm/trunk/lib/CodeGen/Spiller.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=118701&r1=118700&r2=118701&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.h (original) +++ llvm/trunk/lib/CodeGen/Spiller.h Wed Nov 10 13:18:47 2010 @@ -36,7 +36,7 @@ /// @param newIntervals The newly created intervals will be appended here. virtual void spill(LiveInterval *li, SmallVectorImpl &newIntervals, - SmallVectorImpl &spillIs) = 0; + const SmallVectorImpl &spillIs) = 0; }; From stoklund at 2pi.dk Wed Nov 10 13:31:50 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 19:31:50 -0000 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h Message-ID: <20101110193150.38A1B2A6C12C@llvm.org> Author: stoklund Date: Wed Nov 10 13:31:50 2010 New Revision: 118702 URL: http://llvm.org/viewvc/llvm-project?rev=118702&view=rev Log: Basic rematerialization during splitting. Whenever splitting wants to insert a copy, it checks if the value can be rematerialized cheaply instead. Missing features: - Delete instructions when all uses have been rematerialized. - Truncate live ranges to the remaining uses after rematerialization. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=118702&r1=118701&r2=118702&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Nov 10 13:31:50 2010 @@ -659,19 +659,6 @@ addSimpleRange(I->start, std::min(End, I->end), I->valno); } -VNInfo *LiveIntervalMap::defByCopy(const VNInfo *ParentVNI, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) { - const TargetInstrDesc &TID = MBB.getParent()->getTarget().getInstrInfo()-> - get(TargetOpcode::COPY); - MachineInstr *MI = BuildMI(MBB, I, DebugLoc(), TID, li_->reg) - .addReg(parentli_.reg); - SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex(); - VNInfo *VNI = defValue(ParentVNI, DefIdx); - VNI->setCopy(MI); - li_->addRange(LiveRange(DefIdx, DefIdx.getNextSlot(), VNI)); - return VNI; -} //===----------------------------------------------------------------------===// // Split Editor @@ -686,10 +673,14 @@ : sa_(sa), lis_(lis), vrm_(vrm), mri_(vrm.getMachineFunction().getRegInfo()), tii_(*vrm.getMachineFunction().getTarget().getInstrInfo()), + tri_(*vrm.getMachineFunction().getTarget().getRegisterInfo()), edit_(edit), dupli_(lis_, mdt, edit.getParent()), openli_(lis_, mdt, edit.getParent()) { + // We don't need an AliasAnalysis since we will only be performing + // cheap-as-a-copy remats anyway. + edit_.anyRematerializable(lis_, tii_, 0); } bool SplitEditor::intervalsLiveAt(SlotIndex Idx) const { @@ -699,10 +690,41 @@ return false; } +VNInfo *SplitEditor::defFromParent(LiveIntervalMap &Reg, + VNInfo *ParentVNI, + SlotIndex UseIdx, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) { + VNInfo *VNI = 0; + MachineInstr *CopyMI = 0; + SlotIndex Def; + + // Attempt cheap-as-a-copy rematerialization. + LiveRangeEdit::Remat RM(ParentVNI); + if (edit_.canRematerializeAt(RM, UseIdx, true, lis_)) { + Def = edit_.rematerializeAt(MBB, I, Reg.getLI()->reg, RM, + lis_, tii_, tri_); + } else { + // Can't remat, just insert a copy from parent. + CopyMI = BuildMI(MBB, I, DebugLoc(), tii_.get(TargetOpcode::COPY), + Reg.getLI()->reg).addReg(edit_.getReg()); + Def = lis_.InsertMachineInstrInMaps(CopyMI).getDefIndex(); + } + + // Define the value in Reg. + VNI = Reg.defValue(ParentVNI, Def); + VNI->setCopy(CopyMI); + + // Add minimal liveness for the new value. + if (UseIdx < Def) + UseIdx = Def; + Reg.getLI()->addRange(LiveRange(Def, UseIdx.getNextSlot(), VNI)); + return VNI; +} + /// Create a new virtual register and live interval. void SplitEditor::openIntv() { assert(!openli_.getLI() && "Previous LI not closed before openIntv"); - if (!dupli_.getLI()) dupli_.reset(&edit_.create(mri_, lis_, vrm_)); @@ -713,8 +735,9 @@ /// not live before Idx, a COPY is not inserted. void SplitEditor::enterIntvBefore(SlotIndex Idx) { assert(openli_.getLI() && "openIntv not called before enterIntvBefore"); + Idx = Idx.getUseIndex(); DEBUG(dbgs() << " enterIntvBefore " << Idx); - VNInfo *ParentVNI = edit_.getParent().getVNInfoAt(Idx.getUseIndex()); + VNInfo *ParentVNI = edit_.getParent().getVNInfoAt(Idx); if (!ParentVNI) { DEBUG(dbgs() << ": not live\n"); return; @@ -723,26 +746,28 @@ truncatedValues.insert(ParentVNI); MachineInstr *MI = lis_.getInstructionFromIndex(Idx); assert(MI && "enterIntvBefore called with invalid index"); - VNInfo *VNI = openli_.defByCopy(ParentVNI, *MI->getParent(), MI); - openli_.getLI()->addRange(LiveRange(VNI->def, Idx.getDefIndex(), VNI)); + + defFromParent(openli_, ParentVNI, Idx, *MI->getParent(), MI); + DEBUG(dbgs() << ": " << *openli_.getLI() << '\n'); } /// enterIntvAtEnd - Enter openli at the end of MBB. void SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(openli_.getLI() && "openIntv not called before enterIntvAtEnd"); - SlotIndex End = lis_.getMBBEndIdx(&MBB); + SlotIndex End = lis_.getMBBEndIdx(&MBB).getPrevSlot(); DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << End); - VNInfo *ParentVNI = edit_.getParent().getVNInfoAt(End.getPrevSlot()); + VNInfo *ParentVNI = edit_.getParent().getVNInfoAt(End); if (!ParentVNI) { DEBUG(dbgs() << ": not live\n"); return; } DEBUG(dbgs() << ": valno " << ParentVNI->id); truncatedValues.insert(ParentVNI); - VNInfo *VNI = openli_.defByCopy(ParentVNI, MBB, MBB.getFirstTerminator()); + VNInfo *VNI = defFromParent(openli_, ParentVNI, End, MBB, + MBB.getFirstTerminator()); // Make sure openli is live out of MBB. - openli_.getLI()->addRange(LiveRange(VNI->def, End, VNI)); + openli_.getLI()->addRange(LiveRange(VNI->def, End.getNextSlot(), VNI)); DEBUG(dbgs() << ": " << *openli_.getLI() << '\n'); } @@ -764,7 +789,8 @@ DEBUG(dbgs() << " leaveIntvAfter " << Idx); // The interval must be live beyond the instruction at Idx. - VNInfo *ParentVNI = edit_.getParent().getVNInfoAt(Idx.getBoundaryIndex()); + Idx = Idx.getBoundaryIndex(); + VNInfo *ParentVNI = edit_.getParent().getVNInfoAt(Idx); if (!ParentVNI) { DEBUG(dbgs() << ": not live\n"); return; @@ -772,12 +798,13 @@ DEBUG(dbgs() << ": valno " << ParentVNI->id); MachineBasicBlock::iterator MII = lis_.getInstructionFromIndex(Idx); - MachineBasicBlock *MBB = MII->getParent(); - VNInfo *VNI = dupli_.defByCopy(ParentVNI, *MBB, llvm::next(MII)); + VNInfo *VNI = defFromParent(dupli_, ParentVNI, Idx, + *MII->getParent(), llvm::next(MII)); + + // Make sure that openli is properly extended from Idx to the new copy. + // FIXME: This shouldn't be necessary for remats. + openli_.addSimpleRange(Idx, VNI->def, ParentVNI); - // Finally we must make sure that openli is properly extended from Idx to the - // new copy. - openli_.addSimpleRange(Idx.getBoundaryIndex(), VNI->def, ParentVNI); DEBUG(dbgs() << ": " << *openli_.getLI() << '\n'); } @@ -794,9 +821,8 @@ return; } - // We are going to insert a back copy, so we must have a dupli_. - VNInfo *VNI = dupli_.defByCopy(ParentVNI, MBB, - MBB.SkipPHIsAndLabels(MBB.begin())); + VNInfo *VNI = defFromParent(dupli_, ParentVNI, Start, MBB, + MBB.SkipPHIsAndLabels(MBB.begin())); // Finally we must make sure that openli is properly extended from Start to // the new copy. Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=118702&r1=118701&r2=118702&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Wed Nov 10 13:31:50 2010 @@ -26,6 +26,7 @@ class MachineLoopInfo; class MachineRegisterInfo; class TargetInstrInfo; +class TargetRegisterInfo; class VirtRegMap; class VNInfo; class raw_ostream; @@ -245,14 +246,6 @@ /// All needed values whose def is not inside [Start;End) must be defined /// beforehand so mapValue will work. void addRange(SlotIndex Start, SlotIndex End); - - /// defByCopy- Insert a copy from parentli to li, assuming that ParentVNI is - /// live at the insert location. Add a minimal live range for the new value - /// and return it. - VNInfo *defByCopy(const VNInfo *ParentVNI, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I); - }; @@ -273,6 +266,7 @@ VirtRegMap &vrm_; MachineRegisterInfo &mri_; const TargetInstrInfo &tii_; + const TargetRegisterInfo &tri_; /// edit_ - The current parent register and new intervals created. LiveRangeEdit &edit_; @@ -285,6 +279,14 @@ /// Currently open LiveInterval. LiveIntervalMap openli_; + /// defFromParent - Define Reg from ParentVNI at UseIdx using either + /// rematerialization or a COPY from parent. Return the new value. + VNInfo *defFromParent(LiveIntervalMap &Reg, + VNInfo *ParentVNI, + SlotIndex UseIdx, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I); + /// intervalsLiveAt - Return true if any member of intervals_ is live at Idx. bool intervalsLiveAt(SlotIndex Idx) const; From rafael.espindola at gmail.com Wed Nov 10 14:02:59 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 10 Nov 2010 20:02:59 -0000 Subject: [llvm-commits] [llvm] r118709 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20101110200259.312092A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 14:02:59 2010 New Revision: 118709 URL: http://llvm.org/viewvc/llvm-project?rev=118709&view=rev Log: Change the String methods to take a fragment instead of a buffer. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118709&r1=118708&r2=118709&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 14:02:59 2010 @@ -214,10 +214,6 @@ Writer->Write32(W); } - void String8(char *buf, uint8_t Value) { - buf[0] = Value; - } - void StringLE16(char *buf, uint16_t Value) { buf[0] = char(Value >> 0); buf[1] = char(Value >> 8); @@ -248,25 +244,37 @@ StringBE32(buf + 4, uint32_t(Value >> 0)); } - void String16(char *buf, uint16_t Value) { + void String8(MCDataFragment &F, uint8_t Value) { + char buf[1]; + buf[0] = Value; + F.getContents() += StringRef(buf, 1); + } + + void String16(MCDataFragment &F, uint16_t Value) { + char buf[2]; if (Writer->isLittleEndian()) StringLE16(buf, Value); else StringBE16(buf, Value); + F.getContents() += StringRef(buf, 2); } - void String32(char *buf, uint32_t Value) { + void String32(MCDataFragment &F, uint32_t Value) { + char buf[4]; if (Writer->isLittleEndian()) StringLE32(buf, Value); else StringBE32(buf, Value); + F.getContents() += StringRef(buf, 4); } - void String64(char *buf, uint64_t Value) { + void String64(MCDataFragment &F, uint64_t Value) { + char buf[8]; if (Writer->isLittleEndian()) StringLE64(buf, Value); else StringBE64(buf, Value); + F.getContents() += StringRef(buf, 8); } void WriteHeader(uint64_t SectionDataSize, unsigned NumberOfSections); @@ -407,62 +415,29 @@ uint32_t shndx, bool Reserved) { if (ShndxF) { - char buf[4]; if (shndx >= ELF::SHN_LORESERVE && !Reserved) - String32(buf, shndx); + String32(*ShndxF, shndx); else - String32(buf, 0); - ShndxF->getContents() += StringRef(buf, 4); + String32(*ShndxF, 0); } - if (Is64Bit) { - char buf[8]; - - String32(buf, name); - SymtabF->getContents() += StringRef(buf, 4); // st_name - - String8(buf, info); - SymtabF->getContents() += StringRef(buf, 1); // st_info - - String8(buf, other); - SymtabF->getContents() += StringRef(buf, 1); // st_other - - if (shndx >= ELF::SHN_LORESERVE && !Reserved) - String16(buf, ELF::SHN_XINDEX); - else - String16(buf, shndx); - - SymtabF->getContents() += StringRef(buf, 2); // st_shndx - - String64(buf, value); - SymtabF->getContents() += StringRef(buf, 8); // st_value + uint16_t Index = (shndx >= ELF::SHN_LORESERVE && !Reserved) ? + uint16_t(ELF::SHN_XINDEX) : shndx; - String64(buf, size); - SymtabF->getContents() += StringRef(buf, 8); // st_size + if (Is64Bit) { + String32(*SymtabF, name); // st_name + String8(*SymtabF, info); // st_info + String8(*SymtabF, other); // st_other + String16(*SymtabF, Index); // st_shndx + String64(*SymtabF, value); // st_value + String64(*SymtabF, size); // st_size } else { - char buf[4]; - - String32(buf, name); - SymtabF->getContents() += StringRef(buf, 4); // st_name - - String32(buf, value); - SymtabF->getContents() += StringRef(buf, 4); // st_value - - String32(buf, size); - SymtabF->getContents() += StringRef(buf, 4); // st_size - - String8(buf, info); - SymtabF->getContents() += StringRef(buf, 1); // st_info - - String8(buf, other); - SymtabF->getContents() += StringRef(buf, 1); // st_other - - if (shndx >= ELF::SHN_LORESERVE && !Reserved) - String16(buf, ELF::SHN_XINDEX); - else - String16(buf, shndx); - - SymtabF->getContents() += StringRef(buf, 2); // st_shndx + String32(*SymtabF, name); // st_name + String32(*SymtabF, value); // st_value + String32(*SymtabF, size); // st_size + String8(*SymtabF, info); // st_info + String8(*SymtabF, other); // st_other + String16(*SymtabF, Index); // st_shndx } } @@ -1111,35 +1086,23 @@ else entry.Index += LocalSymbolData.size() + 1; if (Is64Bit) { - char buf[8]; - - String64(buf, entry.r_offset); - F->getContents() += StringRef(buf, 8); + String64(*F, entry.r_offset); struct ELF::Elf64_Rela ERE64; ERE64.setSymbolAndType(entry.Index, entry.Type); - String64(buf, ERE64.r_info); - F->getContents() += StringRef(buf, 8); + String64(*F, ERE64.r_info); - if (HasRelocationAddend) { - String64(buf, entry.r_addend); - F->getContents() += StringRef(buf, 8); - } + if (HasRelocationAddend) + String64(*F, entry.r_addend); } else { - char buf[4]; - - String32(buf, entry.r_offset); - F->getContents() += StringRef(buf, 4); + String32(*F, entry.r_offset); struct ELF::Elf32_Rela ERE32; ERE32.setSymbolAndType(entry.Index, entry.Type); - String32(buf, ERE32.r_info); - F->getContents() += StringRef(buf, 4); + String32(*F, ERE32.r_info); - if (HasRelocationAddend) { - String32(buf, entry.r_addend); - F->getContents() += StringRef(buf, 4); - } + if (HasRelocationAddend) + String32(*F, entry.r_addend); } } } From evan.cheng at apple.com Wed Nov 10 14:17:13 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 10 Nov 2010 12:17:13 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: <20101110193150.38A1B2A6C12C@llvm.org> References: <20101110193150.38A1B2A6C12C@llvm.org> Message-ID: Nice. One question though: On Nov 10, 2010, at 11:31 AM, Jakob Stoklund Olesen wrote: > > + // Make sure that openli is properly extended from Idx to the new copy. > + // FIXME: This shouldn't be necessary for remats. > + openli_.addSimpleRange(Idx, VNI->def, ParentVNI); > Why the "fixme"? Are you restricting remat to instructions with no register operands? Evan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/1159b2a7/attachment.html From gohman at apple.com Wed Nov 10 14:37:15 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 20:37:15 -0000 Subject: [llvm-commits] [llvm] r118714 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/MemoryDependenceAnalysis.h lib/Analysis/MemDepPrinter.cpp lib/Analysis/MemoryDependenceAnalysis.cpp lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/non-local-offset.ll Message-ID: <20101110203715.F2A1B2A6C12C@llvm.org> Author: djg Date: Wed Nov 10 14:37:15 2010 New Revision: 118714 URL: http://llvm.org/viewvc/llvm-project?rev=118714&view=rev Log: Enhance GVN to do more precise alias queries for non-local memory references. For example, this allows gvn to eliminate the load in this example: void foo(int n, int* p, int *q) { p[0] = 0; p[1] = 1; if (n) { *q = p[0]; } } Added: llvm/trunk/test/Transforms/GVN/non-local-offset.ll Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h llvm/trunk/lib/Analysis/MemDepPrinter.cpp llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118714&r1=118713&r2=118714&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Wed Nov 10 14:37:15 2010 @@ -107,6 +107,12 @@ return Copy; } + Location getWithNewSize(uint64_t NewSize) const { + Location Copy(*this); + Copy.Size = NewSize; + return Copy; + } + Location getWithoutTBAATag() const { Location Copy(*this); Copy.TBAATag = 0; Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=118714&r1=118713&r2=118714&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Wed Nov 10 14:37:15 2010 @@ -227,11 +227,14 @@ BBSkipFirstBlockPair Pair; /// NonLocalDeps - The results of the query for each relevant block. NonLocalDepInfo NonLocalDeps; + /// Size - The maximum size of the dereferences of the + /// pointer. May be UnknownSize if the sizes are unknown. + uint64_t Size; /// TBAATag - The TBAA tag associated with dereferences of the /// pointer. May be null if there are no tags or conflicting tags. - MDNode *TBAATag; + const MDNode *TBAATag; - NonLocalPointerInfo() : TBAATag(0) {} + NonLocalPointerInfo() : Size(0), TBAATag(0) {} }; /// CachedNonLocalPointerInfo - This map stores the cached results of doing @@ -315,14 +318,6 @@ bool isLoad, BasicBlock *BB, SmallVectorImpl &Result); - /// getNonLocalPointerDependence - A convenience wrapper. - void getNonLocalPointerDependency(Value *Pointer, bool isLoad, - BasicBlock *BB, - SmallVectorImpl &Result){ - return getNonLocalPointerDependency(AliasAnalysis::Location(Pointer), - isLoad, BB, Result); - } - /// removeInstruction - Remove an instruction from the dependence analysis, /// updating the dependence of instructions that previously depended on it. void removeInstruction(Instruction *InstToRemove); Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=118714&r1=118713&r2=118714&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Wed Nov 10 14:37:15 2010 @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Analysis/MemoryDependenceAnalysis.h" +#include "llvm/LLVMContext.h" #include "llvm/Analysis/Passes.h" #include "llvm/Assembly/Writer.h" #include "llvm/Support/CallSite.h" @@ -40,7 +41,8 @@ void print(raw_ostream &OS, const Module * = 0) const; virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); + AU.addRequiredTransitive(); + AU.addRequiredTransitive(); AU.setPreservesAll(); } @@ -64,6 +66,7 @@ bool MemDepPrinter::runOnFunction(Function &F) { this->F = &F; + AliasAnalysis &AA = getAnalysis(); MemoryDependenceAnalysis &MDA = getAnalysis(); // All this code uses non-const interfaces because MemDep is not @@ -99,15 +102,23 @@ SmallVector NLDI; if (LoadInst *LI = dyn_cast(Inst)) { // FIXME: Volatile is not handled properly here. - MDA.getNonLocalPointerDependency(LI->getPointerOperand(), !LI->isVolatile(), + AliasAnalysis::Location Loc(LI->getPointerOperand(), + AA.getTypeStoreSize(LI->getType()), + LI->getMetadata(LLVMContext::MD_tbaa)); + MDA.getNonLocalPointerDependency(Loc, !LI->isVolatile(), LI->getParent(), NLDI); } else if (StoreInst *SI = dyn_cast(Inst)) { // FIXME: Volatile is not handled properly here. - MDA.getNonLocalPointerDependency(SI->getPointerOperand(), false, - SI->getParent(), NLDI); + AliasAnalysis::Location Loc(SI->getPointerOperand(), + AA.getTypeStoreSize(SI->getValueOperand() + ->getType()), + SI->getMetadata(LLVMContext::MD_tbaa)); + MDA.getNonLocalPointerDependency(Loc, false, SI->getParent(), NLDI); } else if (VAArgInst *VI = dyn_cast(Inst)) { - MDA.getNonLocalPointerDependency(VI->getPointerOperand(), false, - VI->getParent(), NLDI); + AliasAnalysis::Location Loc(SI->getPointerOperand(), + AliasAnalysis::UnknownSize, + SI->getMetadata(LLVMContext::MD_tbaa)); + MDA.getNonLocalPointerDependency(Loc, false, VI->getParent(), NLDI); } else { llvm_unreachable("Unknown memory instruction!"); } Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118714&r1=118713&r2=118714&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Nov 10 14:37:15 2010 @@ -741,16 +741,40 @@ // Look up the cached info for Pointer. ValueIsLoadPair CacheKey(Pointer.getAddr(), isLoad); - NonLocalPointerInfo *CacheInfo = &NonLocalPointerDeps[CacheKey]; - // If this query's TBAATag is inconsistent with the cached one, discard the - // tag and restart the query. - if (CacheInfo->TBAATag != Loc.TBAATag) { - CacheInfo->TBAATag = 0; - NonLocalPointerDeps.erase(CacheKey); - return getNonLocalPointerDepFromBB(Pointer, Loc.getWithoutTBAATag(), - isLoad, StartBB, Result, Visited, - SkipFirstBlock); + // Set up a temporary NLPI value. If the map doesn't yet have an entry for + // CacheKey, this value will be inserted as the associated value. Otherwise, + // it'll be ignored, and we'll have to check to see if the cached size and + // tbaa tag are consistent with the current query. + NonLocalPointerInfo InitialNLPI; + InitialNLPI.Size = Loc.Size; + InitialNLPI.TBAATag = Loc.TBAATag; + + // Get the NLPI for CacheKey, inserting one into the map if it doesn't + // already have one. + std::pair Pair = + NonLocalPointerDeps.insert(std::make_pair(CacheKey, InitialNLPI)); + NonLocalPointerInfo *CacheInfo = &Pair.first->second; + + if (!Pair.second) { + // If this query's Size is inconsistent with the cached one, take the + // maximum size and restart the query. + if (CacheInfo->Size != Loc.Size) { + CacheInfo->Size = std::max(CacheInfo->Size, Loc.Size); + return getNonLocalPointerDepFromBB(Pointer, + Loc.getWithNewSize(CacheInfo->Size), + isLoad, StartBB, Result, Visited, + SkipFirstBlock); + } + + // If this query's TBAATag is inconsistent with the cached one, discard the + // tag and restart the query. + if (CacheInfo->TBAATag != Loc.TBAATag) { + CacheInfo->TBAATag = 0; + return getNonLocalPointerDepFromBB(Pointer, Loc.getWithoutTBAATag(), + isLoad, StartBB, Result, Visited, + SkipFirstBlock); + } } NonLocalDepInfo *Cache = &CacheInfo->NonLocalDeps; @@ -796,6 +820,7 @@ CacheInfo->Pair = BBSkipFirstBlockPair(StartBB, SkipFirstBlock); else { CacheInfo->Pair = BBSkipFirstBlockPair(); + CacheInfo->Size = 0; CacheInfo->TBAATag = 0; } @@ -921,6 +946,7 @@ // cached value to do more work but not miss the phi trans failure. NonLocalPointerInfo &NLPI = NonLocalPointerDeps[CacheKey]; NLPI.Pair = BBSkipFirstBlockPair(); + NLPI.Size = 0; NLPI.TBAATag = 0; continue; } @@ -949,6 +975,7 @@ // specific block queries) but we can't do the fastpath "return all // results from the set" Clear out the indicator for this. CacheInfo->Pair = BBSkipFirstBlockPair(); + CacheInfo->Size = 0; CacheInfo->TBAATag = 0; SkipFirstBlock = false; continue; @@ -967,6 +994,7 @@ // specific block queries) but we can't do the fastpath "return all // results from the set". Clear out the indicator for this. CacheInfo->Pair = BBSkipFirstBlockPair(); + CacheInfo->Size = 0; CacheInfo->TBAATag = 0; // If *nothing* works, mark the pointer as being clobbered by the first @@ -1184,6 +1212,7 @@ // The cache is not valid for any specific block anymore. NonLocalPointerDeps[P].Pair = BBSkipFirstBlockPair(); + NonLocalPointerDeps[P].Size = 0; NonLocalPointerDeps[P].TBAATag = 0; // Update any entries for RemInst to use the instruction after it. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=118714&r1=118713&r2=118714&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Nov 10 14:37:15 2010 @@ -1351,8 +1351,10 @@ SmallVectorImpl &toErase) { // Find the non-local dependencies of the load. SmallVector Deps; - MD->getNonLocalPointerDependency(LI->getPointerOperand(), true, - LI->getParent(), + AliasAnalysis::Location Loc(LI->getPointerOperand(), + VN.getAliasAnalysis()->getTypeStoreSize(LI->getType()), + LI->getMetadata(LLVMContext::MD_tbaa)); + MD->getNonLocalPointerDependency(Loc, true, LI->getParent(), Deps); //DEBUG(dbgs() << "INVESTIGATING NONLOCAL LOAD: " // << Deps.size() << *LI << '\n'); Added: llvm/trunk/test/Transforms/GVN/non-local-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/non-local-offset.ll?rev=118714&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVN/non-local-offset.ll (added) +++ llvm/trunk/test/Transforms/GVN/non-local-offset.ll Wed Nov 10 14:37:15 2010 @@ -0,0 +1,59 @@ +; RUN: opt -basicaa -gvn -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64" + +; GVN should ignore the store to p[1] to see that the load from p[0] is +; fully redundant. + +; CHECK: @yes +; CHECK: if.then: +; CHECK-NEXT: store i32 0, i32* %q +; CHECK-NEXT: ret void + +define void @yes(i1 %c, i32* %p, i32* %q) nounwind { +entry: + store i32 0, i32* %p + %p1 = getelementptr inbounds i32* %p, i64 1 + store i32 1, i32* %p1 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p + store i32 %t, i32* %q + ret void + +if.else: + ret void +} + +; GVN should ignore the store to p[1] to see that the first load from p[0] is +; fully redundant. However, the second load is larger, so it's not a simple +; redundancy. + +; CHECK: @watch_out_for_size_change +; CHECK: if.then: +; CHECK-NEXT: store i32 0, i32* %q +; CHECK-NEXT: ret void +; CHECK: if.else: +; CHECK: load i64* %pc +; CHECK: store i64 + +define void @watch_out_for_size_change(i1 %c, i32* %p, i32* %q) nounwind { +entry: + store i32 0, i32* %p + %p1 = getelementptr inbounds i32* %p, i64 1 + store i32 1, i32* %p1 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p + store i32 %t, i32* %q + ret void + +if.else: + %pc = bitcast i32* %p to i64* + %qc = bitcast i32* %q to i64* + %t64 = load i64* %pc + store i64 %t64, i64* %qc + ret void +} From jasonwkim at google.com Wed Nov 10 14:50:22 2010 From: jasonwkim at google.com (Jason Kim) Date: Wed, 10 Nov 2010 12:50:22 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: References: Message-ID: On Wed, Nov 10, 2010 at 9:57 AM, Jason Kim wrote: > Refactoring the x86 dependent code from ELFObjectWriter class has > repercussions among several (conflicting) axes of consideration, > > 1. namespace pollution - minimize pollution of the llvm: ?namespace > 2. consistency - try to maintain as small a delta between the changes > 3. linking - minimize the number of additional cross dependency > between the existing libraries > 4. clarity - avoid special case switching as much as possible - > 5. Xfactor - how clean is the overall resulting design? > > The possible ?ways forward I see are > > SMALL: keep the code nearly as is - place a switch inside > ELFObjectWriter::RecordRelocation and dispatch to > ELFObjectWriterImpl::RecordRelocation > 1. +1 no new classes > 2. +1 tiny patch > 3. +1 no new classes, just one additional function so far. > 4. -2 need to have special case switching for every routine that needs > to be tweaked. > 5. -2 Terrible! So far, its just one new switch, but ... > > tryA: move the functionality of the ELFObjectWriterImpl class into > ELFObjectWriter, and subclass ELFObjectWriter to > ELFObjectWriter. > Change most ELF specific routines to be virtual - except for the low > level Write* routines - > 1. -1 at least new classes ARMELFObjectWriter and X86ELFObjectWriter > 2. -1 large patch > 3. +2 Resulting special cases are isolated in their own class > 4. +1 ?Depends upon virtual dispatch for higher level differentiation > - removes unnecessary trampoline between ELFObjectWriter and > ELFObjectWriterImpl > 5. +2 This approach is the best in terms of the resulting design. The > only drawback is the distinction between MachO and ELF > > tryB: subclass ELFObjectWriterImpl instead - I am still working out > the details on this one - but as of right now, it is just as complex > as the tryA case. > The only benefit to this is approach is the superficial similarity > between the ELFObjectWriter and the MachObjectWriter - in that both > still trampoline into an *Impl class to do the actual work. > Unfortunately, it also adds a requirement for registering a NEW > ELFObjecWriterImpl class (i.e. in addition to the existing > createELFObjectWriter, and without namespace pollution to llvm, > creates a linkage dependency failure). > I will reply to this thread with a patch as soon as I finish this variant. > > There are several attachments: > > small: > ?small-elfwriter-cpp (application/octet-stream) 2K > ?small-elfwriter-rename-record (application/octet-stream) 2K > > tryA > ?arm-mc-elf-s07-elfwriter-tryA-combined.patch (text/x-patch) 43K - > this is the combined patch - In order to make it more clear, I broke > up the steps into a dozen or so smaller patches. > ?tryA.tgz ?- archive of patches > ?They are combined into a tar archive - the README is reproduced here. > diffview at http://codereview.chromium.org/4703006 TryB is actually a little bit smaller than tryA, and by keeping the factory within ELFObjectWriter(), I was able to avoid the linkage issue I ran into earlier. It seems this is probably a little bit better than tryA Its smaller No switch between ELF and MachO Rest of the ELFObjectWriter is not modified - the manual trampoline is still in place. -jason > Thanks for reading. > -jason > -------------- next part -------------- A non-text attachment was scrubbed... Name: tryB-combined.patch Type: text/x-patch Size: 22131 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/add7b197/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: tryB.tgz Type: application/x-gzip Size: 5283 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/add7b197/attachment.tgz From baldrick at free.fr Wed Nov 10 14:53:24 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 20:53:24 -0000 Subject: [llvm-commits] [llvm] r118718 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20101110205324.F33A62A6C12C@llvm.org> Author: baldrick Date: Wed Nov 10 14:53:24 2010 New Revision: 118718 URL: http://llvm.org/viewvc/llvm-project?rev=118718&view=rev Log: Reduce the maximum recursion depth, 5 seems pointlessly too much. Probably it should just be 1, but compromise with 3. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=118718&r1=118717&r2=118718&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Nov 10 14:53:24 2010 @@ -21,7 +21,7 @@ using namespace llvm; using namespace llvm::PatternMatch; -#define MaxRecursionDepth 5 +#define MaxRecursionDepth 3 static Value *SimplifyBinOp(unsigned, Value *, Value *, const TargetData *, unsigned); From baldrick at free.fr Wed Nov 10 14:59:51 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 21:59:51 +0100 Subject: [llvm-commits] [llvm] r118687 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Transforms/IPO/FunctionAttrs.cpp In-Reply-To: <7B4B64F6-189A-457D-A355-4E3E6FBE7DDB@apple.com> References: <20101110173404.CCF4D2A6C12C@llvm.org> <4CDADDA5.5030709@free.fr> <7B4B64F6-189A-457D-A355-4E3E6FBE7DDB@apple.com> Message-ID: <4CDB07C7.4000504@free.fr> Hi Dan, >>> + if (AliasAnalysis::onlyAccessesArgPointees(MRB)) { >>> + // If the call does access argument pointees, check each argument. >>> if (MRB& AliasAnalysis::AccessesArguments) >> >> Is this second "if" redundant? > > No; I've added another helper function for this now. thanks. I find it confusing that in onlyAccessesArgPointees, "accesses" means read-write, while in AccessesArguments, "accesses" means read-only. How about changing AliasAnalysis::AccessesArguments to ReadsArguments? Ciao, Duncan. From stoklund at 2pi.dk Wed Nov 10 15:08:24 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 13:08:24 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: References: <20101110193150.38A1B2A6C12C@llvm.org> Message-ID: <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> On Nov 10, 2010, at 12:17 PM, Evan Cheng wrote: > Nice. One question though: > > > On Nov 10, 2010, at 11:31 AM, Jakob Stoklund Olesen wrote: > >> >> + // Make sure that openli is properly extended from Idx to the new copy. >> + // FIXME: This shouldn't be necessary for remats. >> + openli_.addSimpleRange(Idx, VNI->def, ParentVNI); >> > > Why the "fixme"? Are you restricting remat to instructions with no register operands? No, I allow register operands as much as isTriviallyReMaterializable does, but I never extend live ranges of operands to do so. I require all operands to be live with the same value at the remat location. This check is implemented in LiveRangeEdit::allUsesAvailableAt(). I think that isTriviallyReMaterializable is actually too conservative: // Only allow one virtual-register def, and that in the first operand. if (MO.isDef() != (i == 0)) return false; // For the def, it should be the only def of that register. if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() || MRI.isLiveIn(Reg))) return false; // Don't allow any virtual-register uses. Rematting an instruction with // virtual register uses would length the live ranges of the uses, which // is not necessarily a good idea, certainly not "trivial". if (MO.isUse()) return false; Given that all used virtual registers have the same value, there is no need to restrict to only one use, or single-def. I wonder if 'isTriviallyReMaterializable' means that the instruction can be rematted anywhere without further checks? If so, I should perhaps be using the basic TID::isRematerializable() flag instead? Anyway, the FIXME is an other matter entirely. When the splitter inserts copies, it needs to make sure that the COPY source register can reach the COPY instruction. When it remats the value instead of issuing a COPY, that shouldn't be necessary - in fact, the source register live range should be shortened since it is not needed for the remat. The live range extension is still necessary because the splitter is computing the live range of the last register as the complement of all the other new registers. This will go away after I figure out how to truncate live ranges after rematerialization. /jakob From baldrick at free.fr Wed Nov 10 15:20:58 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 10 Nov 2010 21:20:58 -0000 Subject: [llvm-commits] [dragonegg] r118719 - /dragonegg/trunk/www/index.html Message-ID: <20101110212058.310A82A6C12C@llvm.org> Author: baldrick Date: Wed Nov 10 15:20:58 2010 New Revision: 118719 URL: http://llvm.org/viewvc/llvm-project?rev=118719&view=rev Log: Mention a link-time failure problem with dragonegg-2.8, and the fix. Modified: dragonegg/trunk/www/index.html Modified: dragonegg/trunk/www/index.html URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/www/index.html?rev=118719&r1=118718&r2=118719&view=diff ============================================================================== --- dragonegg/trunk/www/index.html (original) +++ dragonegg/trunk/www/index.html Wed Nov 10 15:20:58 2010 @@ -83,9 +83,15 @@
  • Functions returning complex numbers are not handled in an ABI conformant way. This means for example that if code compiled with dragonegg calls a function in a system library that returns a complex - number then you get a bogus result. This was fixed in - subversion commit 117649. - That patch applies correctly to the dragonegg-2.8 source.
    • + number then you get a bogus result. The fix in + subversion commit 117649 + can be applied to the dragonegg-2.8 source to resolve the problem. +
  • Calling floor then converting the result to a long integer + type can result in link failures due to an undefined reference to + __builtin_lfloor. Likewise for ceil and variants + like floorf. The fix in + subversion commit 118499 + can be applied to the dragonegg-2.8 source to resolve the problem.

  • DragonEgg-2.7 was the first ever DragonEgg release. It works with LLVM-2.7 and From natebegeman at mac.com Wed Nov 10 15:35:42 2010 From: natebegeman at mac.com (Nate Begeman) Date: Wed, 10 Nov 2010 21:35:42 -0000 Subject: [llvm-commits] [llvm] r118720 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20101110213542.1A87D2A6C12C@llvm.org> Author: sampo Date: Wed Nov 10 15:35:41 2010 New Revision: 118720 URL: http://llvm.org/viewvc/llvm-project?rev=118720&view=rev Log: Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118720&r1=118719&r2=118720&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 10 15:35:41 2010 @@ -3546,8 +3546,8 @@ for (unsigned i = 0; i < NumElts; ++i) Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op.getOperand(i))); - SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0], - NumElts); + EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); + SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); Val = LowerBUILD_VECTOR(Val, DAG, ST); if (Val.getNode()) return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val); From gohman at apple.com Wed Nov 10 15:45:12 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 21:45:12 -0000 Subject: [llvm-commits] [llvm] r118721 - in /llvm/trunk: lib/Analysis/MemoryDependenceAnalysis.cpp test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll Message-ID: <20101110214512.201BC2A6C12C@llvm.org> Author: djg Date: Wed Nov 10 15:45:11 2010 New Revision: 118721 URL: http://llvm.org/viewvc/llvm-project?rev=118721&view=rev Log: Fully invalidate cached results when a prior query's size or type is insufficient for, or incompatible with, the current query. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118721&r1=118720&r2=118721&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Nov 10 15:45:11 2010 @@ -756,24 +756,37 @@ NonLocalPointerDeps.insert(std::make_pair(CacheKey, InitialNLPI)); NonLocalPointerInfo *CacheInfo = &Pair.first->second; + // If we already have a cache entry for this CacheKey, we may need to do some + // work to reconcile the cache entry and the current query. if (!Pair.second) { - // If this query's Size is inconsistent with the cached one, take the - // maximum size and restart the query. - if (CacheInfo->Size != Loc.Size) { - CacheInfo->Size = std::max(CacheInfo->Size, Loc.Size); + if (CacheInfo->Size < Loc.Size) { + // The query's Size is greater than the cached one. Throw out the + // cached data and procede with the query at the greater size. + CacheInfo->Pair = BBSkipFirstBlockPair(); + CacheInfo->Size = Loc.Size; + CacheInfo->NonLocalDeps.clear(); + } else if (CacheInfo->Size > Loc.Size) { + // This query's Size is less than the cached one. Conservatively restart + // the query using the greater size. return getNonLocalPointerDepFromBB(Pointer, Loc.getWithNewSize(CacheInfo->Size), isLoad, StartBB, Result, Visited, SkipFirstBlock); } - // If this query's TBAATag is inconsistent with the cached one, discard the - // tag and restart the query. + // If the query's TBAATag is inconsistent with the cached one, + // conservatively throw out the cached data and restart the query with + // no tag if needed. if (CacheInfo->TBAATag != Loc.TBAATag) { - CacheInfo->TBAATag = 0; - return getNonLocalPointerDepFromBB(Pointer, Loc.getWithoutTBAATag(), - isLoad, StartBB, Result, Visited, - SkipFirstBlock); + if (CacheInfo->TBAATag) { + CacheInfo->Pair = BBSkipFirstBlockPair(); + CacheInfo->TBAATag = 0; + CacheInfo->NonLocalDeps.clear(); + } + if (Loc.TBAATag) + return getNonLocalPointerDepFromBB(Pointer, Loc.getWithoutTBAATag(), + isLoad, StartBB, Result, Visited, + SkipFirstBlock); } } Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll?rev=118721&view=auto ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll (added) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll Wed Nov 10 15:45:11 2010 @@ -0,0 +1,91 @@ +; RUN: opt -enable-tbaa -tbaa -basicaa -gvn -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64" + +; GVN should ignore the store to p1 to see that the load from p is +; fully redundant. + +; CHECK: @yes +; CHECK: if.then: +; CHECK-NEXT: store i32 0, i32* %q +; CHECK-NEXT: ret void + +define void @yes(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind { +entry: + store i32 0, i32* %p, !tbaa !1 + store i32 1, i32* %p1, !tbaa !2 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p, !tbaa !1 + store i32 %t, i32* %q + ret void + +if.else: + ret void +} + +; GVN should ignore the store to p1 to see that the first load from p is +; fully redundant. However, the second load uses a different type. Theoretically +; the other type could be unified with the first type, however for now, GVN +; should just be conservative. + +; CHECK: @watch_out_for_type_change +; CHECK: if.then: +; CHECK: %t = load i32* %p +; CHECK: store i32 %t, i32* %q +; CHECK: ret void +; CHECK: if.else: +; CHECK: %u = load i32* %p +; CHECK: store i32 %u, i32* %q + +define void @watch_out_for_type_change(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind { +entry: + store i32 0, i32* %p, !tbaa !1 + store i32 1, i32* %p1, !tbaa !2 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p, !tbaa !4 + store i32 %t, i32* %q + ret void + +if.else: + %u = load i32* %p, !tbaa !3 + store i32 %u, i32* %q + ret void +} + +; As before, but the types are swapped. This time GVN does managed to +; eliminate one of the loads before noticing the type mismatch. + +; CHECK: @watch_out_for_another_type_change +; CHECK: if.then: +; CHECK: %t = load i32* %p +; CHECK: store i32 %t, i32* %q +; CHECK: ret void +; CHECK: if.else: +; CHECK: store i32 0, i32* %q + +define void @watch_out_for_another_type_change(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind { +entry: + store i32 0, i32* %p, !tbaa !1 + store i32 1, i32* %p1, !tbaa !2 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p, !tbaa !3 + store i32 %t, i32* %q + ret void + +if.else: + %u = load i32* %p, !tbaa !4 + store i32 %u, i32* %q + ret void +} + +!0 = metadata !{} +!1 = metadata !{metadata !"red", metadata !0} +!2 = metadata !{metadata !"blu", metadata !0} +!3 = metadata !{metadata !"outer space"} +!4 = metadata !{metadata !"brick red", metadata !1} From rafael.espindola at gmail.com Wed Nov 10 15:51:05 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 10 Nov 2010 21:51:05 -0000 Subject: [llvm-commits] [llvm] r118722 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20101110215105.B1D302A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 15:51:05 2010 New Revision: 118722 URL: http://llvm.org/viewvc/llvm-project?rev=118722&view=rev Log: Factor some code into ComputeIndexMap. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118722&r1=118721&r2=118722&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 15:51:05 2010 @@ -289,6 +289,7 @@ ELFSymbolData &MSD, const MCAsmLayout &Layout); + typedef DenseMap SectionIndexMapTy; void WriteSymbolTable(MCDataFragment *SymtabF, MCDataFragment *ShndxF, const MCAssembler &Asm, const MCAsmLayout &Layout, @@ -306,7 +307,11 @@ /// \param StringTable [out] - The string table data. /// \param StringIndexMap [out] - Map from symbol names to offsets in the /// string table. - void ComputeSymbolTable(MCAssembler &Asm); + void ComputeSymbolTable(MCAssembler &Asm, + const SectionIndexMapTy &SectionIndexMap); + + void ComputeIndexMap(MCAssembler &Asm, + SectionIndexMapTy &SectionIndexMap); void WriteRelocation(MCAssembler &Asm, MCAsmLayout &Layout, const MCSectionData &SD); @@ -919,7 +924,19 @@ return true; } -void ELFObjectWriterImpl::ComputeSymbolTable(MCAssembler &Asm) { +void ELFObjectWriterImpl::ComputeIndexMap(MCAssembler &Asm, + SectionIndexMapTy &SectionIndexMap) { + unsigned Index = 1; + for (MCAssembler::iterator it = Asm.begin(), + ie = Asm.end(); it != ie; ++it) { + const MCSectionELF &Section = + static_cast(it->getSection()); + SectionIndexMap[&Section] = Index++; + } +} + +void ELFObjectWriterImpl::ComputeSymbolTable(MCAssembler &Asm, + const SectionIndexMapTy &SectionIndexMap) { // FIXME: Is this the correct place to do this? if (NeedsGOT) { llvm::StringRef Name = "_GLOBAL_OFFSET_TABLE_"; @@ -931,11 +948,6 @@ // Build section lookup table. NumRegularSections = Asm.size(); - DenseMap SectionIndexMap; - unsigned Index = 1; - for (MCAssembler::iterator it = Asm.begin(), - ie = Asm.end(); it != ie; ++it, ++Index) - SectionIndexMap[&it->getSection()] = Index; // Index 0 is always the empty string. StringMap StringIndexMap; @@ -968,7 +980,9 @@ } else if (RefSymbol.isUndefined()) { MSD.SectionIndex = ELF::SHN_UNDEF; } else { - MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection()); + const MCSectionELF &Section = + static_cast(RefSymbol.getSection()); + MSD.SectionIndex = SectionIndexMap.lookup(&Section); if (MSD.SectionIndex >= ELF::SHN_LORESERVE) NeedsSymtabShndx = true; assert(MSD.SectionIndex && "Invalid section index!"); @@ -1010,7 +1024,7 @@ // Set the symbol indices. Local symbols must come before all other // symbols with non-local bindings. - Index = 0; + unsigned Index = 0; for (unsigned i = 0, e = LocalSymbolData.size(); i != e; ++i) LocalSymbolData[i].SymbolData->setIndex(Index++); for (unsigned i = 0, e = ExternalSymbolData.size(); i != e; ++i) @@ -1228,8 +1242,12 @@ void ELFObjectWriterImpl::WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) { + SectionIndexMapTy SectionIndexMap; + + ComputeIndexMap(Asm, SectionIndexMap); + // Compute symbol table information. - ComputeSymbolTable(Asm); + ComputeSymbolTable(Asm, SectionIndexMap); CreateMetadataSections(const_cast(Asm), const_cast(Layout)); @@ -1262,9 +1280,6 @@ // ... then all of the sections ... DenseMap SectionOffsetMap; - DenseMap SectionIndexMap; - - unsigned Index = 1; for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) { const MCSectionData &SD = *it; @@ -1275,7 +1290,6 @@ // Remember the offset into the file for this section. SectionOffsetMap[&it->getSection()] = FileOff; - SectionIndexMap[&it->getSection()] = Index++; FileOff += Layout.getSectionFileSize(&SD); From gohman at apple.com Wed Nov 10 15:51:35 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 21:51:35 -0000 Subject: [llvm-commits] [llvm] r118723 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20101110215135.A45752A6C12C@llvm.org> Author: djg Date: Wed Nov 10 15:51:35 2010 New Revision: 118723 URL: http://llvm.org/viewvc/llvm-project?rev=118723&view=rev Log: Factor out the code for computing an AliasAnalysis::Location for a given instruction into a helper function. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118723&r1=118722&r2=118723&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Nov 10 15:51:35 2010 @@ -102,6 +102,81 @@ ReverseMap.erase(InstIt); } +/// GetLocation - If the given instruction references a specific memory +/// location, fill in Loc with the details, otherwise set Loc.Ptr to null. +/// Return a ModRefInfo value describing the general behavior of the +/// instruction. +static +AliasAnalysis::ModRefResult GetLocation(const Instruction *Inst, + AliasAnalysis::Location &Loc, + AliasAnalysis *AA) { + if (const LoadInst *LI = dyn_cast(Inst)) { + if (LI->isVolatile()) { + Loc = AliasAnalysis::Location(); + return AliasAnalysis::ModRef; + } + Loc = AliasAnalysis::Location(LI->getPointerOperand(), + AA->getTypeStoreSize(LI->getType()), + LI->getMetadata(LLVMContext::MD_tbaa)); + return AliasAnalysis::Ref; + } + + if (const StoreInst *SI = dyn_cast(Inst)) { + if (SI->isVolatile()) { + Loc = AliasAnalysis::Location(); + return AliasAnalysis::ModRef; + } + Loc = AliasAnalysis::Location(SI->getPointerOperand(), + AA->getTypeStoreSize(SI->getValueOperand() + ->getType()), + SI->getMetadata(LLVMContext::MD_tbaa)); + return AliasAnalysis::Mod; + } + + if (const VAArgInst *V = dyn_cast(Inst)) { + Loc = AliasAnalysis::Location(V->getPointerOperand(), + AA->getTypeStoreSize(V->getType()), + V->getMetadata(LLVMContext::MD_tbaa)); + return AliasAnalysis::ModRef; + } + + if (const CallInst *CI = isFreeCall(Inst)) { + // calls to free() deallocate the entire structure + Loc = AliasAnalysis::Location(CI->getArgOperand(0)); + return AliasAnalysis::Mod; + } + + if (const IntrinsicInst *II = dyn_cast(Inst)) + switch (II->getIntrinsicID()) { + case Intrinsic::lifetime_start: + case Intrinsic::lifetime_end: + case Intrinsic::invariant_start: + Loc = AliasAnalysis::Location(II->getArgOperand(1), + cast(II->getArgOperand(0)) + ->getZExtValue(), + II->getMetadata(LLVMContext::MD_tbaa)); + // These intrinsics don't really modify the memory, but returning Mod + // will allow them to be handled conservatively. + return AliasAnalysis::Mod; + case Intrinsic::invariant_end: + Loc = AliasAnalysis::Location(II->getArgOperand(2), + cast(II->getArgOperand(1)) + ->getZExtValue(), + II->getMetadata(LLVMContext::MD_tbaa)); + // These intrinsics don't really modify the memory, but returning Mod + // will allow them to be handled conservatively. + return AliasAnalysis::Mod; + default: + break; + } + + // Otherwise, just do the coarse-grained thing that always works. + if (Inst->mayWriteToMemory()) + return AliasAnalysis::ModRef; + if (Inst->mayReadFromMemory()) + return AliasAnalysis::Ref; + return AliasAnalysis::NoModRef; +} /// getCallSiteDependencyFrom - Private helper for finding the local /// dependencies of a call site. @@ -114,19 +189,15 @@ // If this inst is a memory op, get the pointer it accessed AliasAnalysis::Location Loc; - if (StoreInst *S = dyn_cast(Inst)) { - Loc = AliasAnalysis::Location(S->getPointerOperand(), - AA->getTypeStoreSize(S->getValueOperand() - ->getType()), - S->getMetadata(LLVMContext::MD_tbaa)); - } else if (VAArgInst *V = dyn_cast(Inst)) { - Loc = AliasAnalysis::Location(V->getPointerOperand(), - AA->getTypeStoreSize(V->getType()), - V->getMetadata(LLVMContext::MD_tbaa)); - } else if (const CallInst *CI = isFreeCall(Inst)) { - // calls to free() erase the entire structure - Loc = AliasAnalysis::Location(CI->getArgOperand(0)); - } else if (CallSite InstCS = cast(Inst)) { + AliasAnalysis::ModRefResult MR = GetLocation(Inst, Loc, AA); + if (Loc.Ptr) { + // A simple instruction. + if (AA->getModRefInfo(CS, Loc) != AliasAnalysis::NoModRef) + return MemDepResult::getClobber(Inst); + continue; + } + + if (CallSite InstCS = cast(Inst)) { // Debug intrinsics don't cause dependences. if (isa(Inst)) continue; // If these two calls do not interfere, look past it. @@ -134,23 +205,17 @@ case AliasAnalysis::NoModRef: // If the two calls are the same, return InstCS as a Def, so that // CS can be found redundant and eliminated. - if (isReadOnlyCall && InstCS.onlyReadsMemory() && + if (isReadOnlyCall && !(MR & AliasAnalysis::Mod) && CS.getInstruction()->isIdenticalToWhenDefined(Inst)) return MemDepResult::getDef(Inst); // Otherwise if the two calls don't interact (e.g. InstCS is readnone) // keep scanning. - continue; + break; default: return MemDepResult::getClobber(Inst); } - } else { - // Non-memory instruction. - continue; } - - if (AA->getModRefInfo(CS, Loc) != AliasAnalysis::NoModRef) - return MemDepResult::getClobber(Inst); } // No dependence found. If this is the entry block of the function, it is a @@ -344,8 +409,6 @@ BasicBlock *QueryParent = QueryInst->getParent(); - AliasAnalysis::Location MemLoc; - // Do the scan. if (BasicBlock::iterator(QueryInst) == QueryParent->begin()) { // No dependence found. If this is the entry block of the function, it is a @@ -354,69 +417,25 @@ LocalCache = MemDepResult::getNonLocal(); else LocalCache = MemDepResult::getClobber(QueryInst); - } else if (StoreInst *SI = dyn_cast(QueryInst)) { - // If this is a volatile store, don't mess around with it. Just return the - // previous instruction as a clobber. - if (SI->isVolatile()) - LocalCache = MemDepResult::getClobber(--BasicBlock::iterator(ScanPos)); - else - MemLoc = AliasAnalysis::Location(SI->getPointerOperand(), - AA->getTypeStoreSize(SI->getOperand(0) - ->getType()), - SI->getMetadata(LLVMContext::MD_tbaa)); - } else if (LoadInst *LI = dyn_cast(QueryInst)) { - // If this is a volatile load, don't mess around with it. Just return the - // previous instruction as a clobber. - if (LI->isVolatile()) - LocalCache = MemDepResult::getClobber(--BasicBlock::iterator(ScanPos)); - else - MemLoc = AliasAnalysis::Location(LI->getPointerOperand(), - AA->getTypeStoreSize(LI->getType()), - LI->getMetadata(LLVMContext::MD_tbaa)); - } else if (const CallInst *CI = isFreeCall(QueryInst)) { - // calls to free() erase the entire structure, not just a field. - MemLoc = AliasAnalysis::Location(CI->getArgOperand(0)); - } else if (isa(QueryInst) || isa(QueryInst)) { - int IntrinsicID = 0; // Intrinsic IDs start at 1. - IntrinsicInst *II = dyn_cast(QueryInst); - if (II) - IntrinsicID = II->getIntrinsicID(); - - switch (IntrinsicID) { - case Intrinsic::lifetime_start: - case Intrinsic::lifetime_end: - case Intrinsic::invariant_start: - MemLoc = AliasAnalysis::Location(II->getArgOperand(1), - cast(II->getArgOperand(0)) - ->getZExtValue(), - II->getMetadata(LLVMContext::MD_tbaa)); - break; - case Intrinsic::invariant_end: - MemLoc = AliasAnalysis::Location(II->getArgOperand(2), - cast(II->getArgOperand(1)) - ->getZExtValue(), - II->getMetadata(LLVMContext::MD_tbaa)); - break; - default: + } else { + AliasAnalysis::Location MemLoc; + AliasAnalysis::ModRefResult MR = GetLocation(QueryInst, MemLoc, AA); + if (MemLoc.Ptr) { + // If we can do a pointer scan, make it happen. + bool isLoad = !(MR & AliasAnalysis::Mod); + if (IntrinsicInst *II = dyn_cast(QueryInst)) { + isLoad |= II->getIntrinsicID() == Intrinsic::lifetime_end; + } + LocalCache = getPointerDependencyFrom(MemLoc, isLoad, ScanPos, + QueryParent); + } else if (isa(QueryInst) || isa(QueryInst)) { CallSite QueryCS(QueryInst); bool isReadOnly = AA->onlyReadsMemory(QueryCS); LocalCache = getCallSiteDependencyFrom(QueryCS, isReadOnly, ScanPos, QueryParent); - break; - } - } else { - // Non-memory instruction. - LocalCache = MemDepResult::getClobber(--BasicBlock::iterator(ScanPos)); - } - - // If we need to do a pointer scan, make it happen. - if (MemLoc.Ptr) { - bool isLoad = !QueryInst->mayWriteToMemory(); - if (IntrinsicInst *II = dyn_cast(QueryInst)) { - isLoad |= II->getIntrinsicID() == Intrinsic::lifetime_end; - } - LocalCache = getPointerDependencyFrom(MemLoc, isLoad, ScanPos, - QueryParent); + } else + // Non-memory instruction. + LocalCache = MemDepResult::getClobber(--BasicBlock::iterator(ScanPos)); } // Remember the result! From gohman at apple.com Wed Nov 10 16:00:23 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 14:00:23 -0800 Subject: [llvm-commits] [llvm] r118687 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Transforms/IPO/FunctionAttrs.cpp In-Reply-To: <4CDB07C7.4000504@free.fr> References: <20101110173404.CCF4D2A6C12C@llvm.org> <4CDADDA5.5030709@free.fr> <7B4B64F6-189A-457D-A355-4E3E6FBE7DDB@apple.com> <4CDB07C7.4000504@free.fr> Message-ID: <3BFD108C-EE18-46AE-9538-EC0131F41D41@apple.com> On Nov 10, 2010, at 12:59 PM, Duncan Sands wrote: > Hi Dan, > >>>> + if (AliasAnalysis::onlyAccessesArgPointees(MRB)) { >>>> + // If the call does access argument pointees, check each >>>> argument. >>>> if (MRB& AliasAnalysis::AccessesArguments) >>> >>> Is this second "if" redundant? >> >> No; I've added another helper function for this now. > > thanks. I find it confusing that in onlyAccessesArgPointees, > "accesses" > means read-write, while in AccessesArguments, "accesses" means read- > only. "Accesses" was meant to mean read+write in both -- AccessesArguments meant loads and stores to argument pointees. > How about changing AliasAnalysis::AccessesArguments to ReadsArguments? I've renamed both and updated the comments. Let me know if the new code is unclear. Dan From rafael.espindola at gmail.com Wed Nov 10 16:16:44 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 10 Nov 2010 22:16:44 -0000 Subject: [llvm-commits] [llvm] r118725 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20101110221644.0CF602A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 16:16:43 2010 New Revision: 118725 URL: http://llvm.org/viewvc/llvm-project?rev=118725&view=rev Log: Use SectionIndexMap in WriteSymbolTable to make it a little less brittle. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118725&r1=118724&r2=118725&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 16:16:43 2010 @@ -293,7 +293,7 @@ void WriteSymbolTable(MCDataFragment *SymtabF, MCDataFragment *ShndxF, const MCAssembler &Asm, const MCAsmLayout &Layout, - unsigned NumRegularSections); + const SectionIndexMapTy &SectionIndexMap); void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, @@ -323,7 +323,8 @@ } } - void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout); + void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout, + const SectionIndexMapTy &SectionIndexMap); void ExecutePostLayoutBinding(MCAssembler &Asm); @@ -570,7 +571,7 @@ MCDataFragment *ShndxF, const MCAssembler &Asm, const MCAsmLayout &Layout, - unsigned NumRegularSections) { + const SectionIndexMapTy &SectionIndexMap) { // The string table must be emitted first because we need the index // into the string table for all the symbol names. assert(StringTable.size() && "Missing string table"); @@ -588,17 +589,17 @@ } // Write out a symbol table entry for each regular section. - unsigned Index = 1; - for (MCAssembler::const_iterator it = Asm.begin(); - Index <= NumRegularSections; ++it, ++Index) { + for (MCAssembler::const_iterator i = Asm.begin(), e = Asm.end(); i != e; + ++i) { const MCSectionELF &Section = - static_cast(it->getSection()); - // Leave out relocations so we don't have indexes within - // the relocations messed up - if (Section.getType() == ELF::SHT_RELA || Section.getType() == ELF::SHT_REL) + static_cast(i->getSection()); + if (Section.getType() == ELF::SHT_RELA || + Section.getType() == ELF::SHT_REL || + Section.getType() == ELF::SHT_STRTAB || + Section.getType() == ELF::SHT_SYMTAB) continue; WriteSymbolEntry(SymtabF, ShndxF, 0, ELF::STT_SECTION, 0, 0, - ELF::STV_DEFAULT, Index, false); + ELF::STV_DEFAULT, SectionIndexMap.lookup(&Section), false); LastLocalSymbolIndex++; } @@ -1122,14 +1123,13 @@ } void ELFObjectWriterImpl::CreateMetadataSections(MCAssembler &Asm, - MCAsmLayout &Layout) { + MCAsmLayout &Layout, + const SectionIndexMapTy &SectionIndexMap) { MCContext &Ctx = Asm.getContext(); MCDataFragment *F; unsigned EntrySize = Is64Bit ? ELF::SYMENTRY_SIZE64 : ELF::SYMENTRY_SIZE32; - unsigned NumRegularSections = Asm.size(); - // We construct .shstrtab, .symtab and .strtab in this order to match gnu as. const MCSectionELF *ShstrtabSection = Ctx.getELFSection(".shstrtab", ELF::SHT_STRTAB, 0, @@ -1172,7 +1172,7 @@ ShndxF = new MCDataFragment(SymtabShndxSD); Asm.AddSectionToTheEnd(*Writer, *SymtabShndxSD, Layout); } - WriteSymbolTable(F, ShndxF, Asm, Layout, NumRegularSections); + WriteSymbolTable(F, ShndxF, Asm, Layout, SectionIndexMap); Asm.AddSectionToTheEnd(*Writer, SymtabSD, Layout); F = new MCDataFragment(&StrtabSD); @@ -1250,7 +1250,8 @@ ComputeSymbolTable(Asm, SectionIndexMap); CreateMetadataSections(const_cast(Asm), - const_cast(Layout)); + const_cast(Layout), + SectionIndexMap); // Add 1 for the null section. unsigned NumSections = Asm.size() + 1; From dpatel at apple.com Wed Nov 10 16:19:21 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 10 Nov 2010 22:19:21 -0000 Subject: [llvm-commits] [llvm] r118726 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/Analysis/DebugInfo.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20101110221921.B9CDF2A6C12C@llvm.org> Author: dpatel Date: Wed Nov 10 16:19:21 2010 New Revision: 118726 URL: http://llvm.org/viewvc/llvm-project?rev=118726&view=rev Log: Take care of special characters while creating named MDNode name to hold function specific local variable's info. This fixes radar 8653152. I am checking in testcase as a separate check-in. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/lib/Analysis/DebugInfo.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=118726&r1=118725&r2=118726&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Nov 10 16:19:21 2010 @@ -33,6 +33,7 @@ class DbgDeclareInst; class Instruction; class MDNode; + class NamedMDNode; class LLVMContext; class raw_ostream; @@ -835,6 +836,14 @@ /// getDICompositeType - Find underlying composite type. DICompositeType getDICompositeType(DIType T); + /// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable + /// to hold function specific information. + NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, StringRef Name); + + /// getFnSpecificMDNode - Return a NameMDNode, if available, that is + /// suitable to hold function specific information. + NamedMDNode *getFnSpecificMDNode(const Module &M, StringRef Name); + class DebugInfoFinder { public: /// processModule - Process entire module and collect debug info Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=118726&r1=118725&r2=118726&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Nov 10 16:19:21 2010 @@ -1156,6 +1156,39 @@ return DIGlobalVariable(Node); } +/// fixupObjcLikeName - Replace contains special characters used +/// in a typical Objective-C names with '.' in a given string. +static void fixupObjcLikeName(std::string &Str) { + for (size_t i = 0, e = Str.size(); i < e; ++i) { + char C = Str[i]; + if (C == '[' || C == ']' || C == ' ' || C == ':') + Str[i] = '.'; + } +} + +/// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable +/// to hold function specific information. +NamedMDNode *llvm::getOrInsertFnSpecificMDNode(Module &M, StringRef FuncName) { + SmallString<32> Out; + if (FuncName.find('[') == StringRef::npos) + return M.getOrInsertNamedMetadata(Twine("llvm.dbg.lv.", FuncName) + .toStringRef(Out)); + std::string Name = FuncName; + fixupObjcLikeName(Name); + return M.getOrInsertNamedMetadata(Twine("llvm.dbg.lv.", Name) + .toStringRef(Out)); +} + +/// getFnSpecificMDNode - Return a NameMDNode, if available, that is +/// suitable to hold function specific information. +NamedMDNode *llvm::getFnSpecificMDNode(const Module &M, StringRef FuncName) { + if (FuncName.find('[') == StringRef::npos) + return M.getNamedMetadata(Twine("llvm.dbg.lv.", FuncName)); + std::string Name = FuncName; + fixupObjcLikeName(Name); + return M.getNamedMetadata(Twine("llvm.dbg.lv.", Name)); +} + /// CreateVariable - Create a new descriptor for the specified variable. DIVariable DIFactory::CreateVariable(unsigned Tag, DIDescriptor Context, StringRef Name, @@ -1185,9 +1218,8 @@ if (FName.startswith(StringRef(&One, 1))) FName = FName.substr(1); - SmallString<32> Out; - NamedMDNode *FnLocals = - M.getOrInsertNamedMetadata(Twine("llvm.dbg.lv.", FName).toStringRef(Out)); + + NamedMDNode *FnLocals = getOrInsertFnSpecificMDNode(M, FName); FnLocals->addOperand(Node); } return DIVariable(Node); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=118726&r1=118725&r2=118726&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Nov 10 16:19:21 2010 @@ -2128,8 +2128,7 @@ StringRef FName = SP.getLinkageName(); if (FName.empty()) FName = SP.getName(); - NamedMDNode *NMD = - M->getNamedMetadata(Twine("llvm.dbg.lv.", getRealLinkageName(FName))); + NamedMDNode *NMD = getFnSpecificMDNode(*(MMI->getModule()), FName); if (!NMD) continue; unsigned E = NMD->getNumOperands(); if (!E) continue; @@ -2422,10 +2421,7 @@ // Collect info for variables that were optimized out. const Function *F = MF->getFunction(); - const Module *M = F->getParent(); - if (NamedMDNode *NMD = - M->getNamedMetadata(Twine("llvm.dbg.lv.", - getRealLinkageName(F->getName())))) { + if (NamedMDNode *NMD = getFnSpecificMDNode(*(F->getParent()), F->getName())) { for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { DIVariable DV(cast(NMD->getOperand(i))); if (!DV || !Processed.insert(DV)) @@ -2912,10 +2908,8 @@ StringRef FName = SP.getLinkageName(); if (FName.empty()) FName = SP.getName(); - const Module *M = MF->getFunction()->getParent(); - if (NamedMDNode *NMD = - M->getNamedMetadata(Twine("llvm.dbg.lv.", - getRealLinkageName(FName)))) { + if (NamedMDNode *NMD = + getFnSpecificMDNode(*(MF->getFunction()->getParent()), FName)) { for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { DIVariable DV(cast(NMD->getOperand(i))); if (!DV || !ProcessedVars.insert(DV)) From rafael.espindola at gmail.com Wed Nov 10 16:34:07 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 10 Nov 2010 22:34:07 -0000 Subject: [llvm-commits] [llvm] r118728 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20101110223407.B0C192A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 16:34:07 2010 New Revision: 118728 URL: http://llvm.org/viewvc/llvm-project?rev=118728&view=rev Log: Update the section index map after we add the medatada sections. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118728&r1=118727&r2=118728&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 16:34:07 2010 @@ -1253,6 +1253,9 @@ const_cast(Layout), SectionIndexMap); + // Update to include the metadata sections. + ComputeIndexMap(Asm, SectionIndexMap); + // Add 1 for the null section. unsigned NumSections = Asm.size() + 1; uint64_t NaturalAlignment = Is64Bit ? 8 : 4; @@ -1335,6 +1338,7 @@ SectionKind::getReadOnly(), false); sh_link = SectionIndexMap[SymtabSection]; + assert(sh_link && ".symtab not found"); // Remove ".rel" and ".rela" prefixes. unsigned SecNameLen = (Section.getType() == ELF::SHT_REL) ? 4 : 5; From gohman at apple.com Wed Nov 10 16:35:02 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 22:35:02 -0000 Subject: [llvm-commits] [llvm] r118729 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20101110223502.821D32A6C12C@llvm.org> Author: djg Date: Wed Nov 10 16:35:02 2010 New Revision: 118729 URL: http://llvm.org/viewvc/llvm-project?rev=118729&view=rev Log: When clearing a non-local pointer dependency cache entry, clear the reverse map too. This fixes seflhost build errors. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118729&r1=118728&r2=118729&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Nov 10 16:35:02 2010 @@ -783,6 +783,10 @@ // cached data and procede with the query at the greater size. CacheInfo->Pair = BBSkipFirstBlockPair(); CacheInfo->Size = Loc.Size; + for (NonLocalDepInfo::iterator DI = CacheInfo->NonLocalDeps.begin(), + DE = CacheInfo->NonLocalDeps.end(); DI != DE; ++DI) + if (Instruction *Inst = DI->getResult().getInst()) + RemoveFromReverseMap(ReverseNonLocalPtrDeps, Inst, CacheKey); CacheInfo->NonLocalDeps.clear(); } else if (CacheInfo->Size > Loc.Size) { // This query's Size is less than the cached one. Conservatively restart @@ -800,6 +804,10 @@ if (CacheInfo->TBAATag) { CacheInfo->Pair = BBSkipFirstBlockPair(); CacheInfo->TBAATag = 0; + for (NonLocalDepInfo::iterator DI = CacheInfo->NonLocalDeps.begin(), + DE = CacheInfo->NonLocalDeps.end(); DI != DE; ++DI) + if (Instruction *Inst = DI->getResult().getInst()) + RemoveFromReverseMap(ReverseNonLocalPtrDeps, Inst, CacheKey); CacheInfo->NonLocalDeps.clear(); } if (Loc.TBAATag) From jasonwkim at google.com Wed Nov 10 17:00:55 2010 From: jasonwkim at google.com (Jason Kim) Date: Wed, 10 Nov 2010 15:00:55 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: References: Message-ID: Hi everyone. Just a heads up: Recent commits broke my patches. Please apply to -r118656 to examine. Thanks -jason On Wed, Nov 10, 2010 at 12:50 PM, Jason Kim wrote: > On Wed, Nov 10, 2010 at 9:57 AM, Jason Kim wrote: >> Refactoring the x86 dependent code from ELFObjectWriter class has >> repercussions among several (conflicting) axes of consideration, >> >> 1. namespace pollution - minimize pollution of the llvm: ?namespace >> 2. consistency - try to maintain as small a delta between the changes >> 3. linking - minimize the number of additional cross dependency >> between the existing libraries >> 4. clarity - avoid special case switching as much as possible - >> 5. Xfactor - how clean is the overall resulting design? >> >> The possible ?ways forward I see are >> >> SMALL: keep the code nearly as is - place a switch inside >> ELFObjectWriter::RecordRelocation and dispatch to >> ELFObjectWriterImpl::RecordRelocation >> 1. +1 no new classes >> 2. +1 tiny patch >> 3. +1 no new classes, just one additional function so far. >> 4. -2 need to have special case switching for every routine that needs >> to be tweaked. >> 5. -2 Terrible! So far, its just one new switch, but ... >> >> tryA: move the functionality of the ELFObjectWriterImpl class into >> ELFObjectWriter, and subclass ELFObjectWriter to >> ELFObjectWriter. >> Change most ELF specific routines to be virtual - except for the low >> level Write* routines - >> 1. -1 at least new classes ARMELFObjectWriter and X86ELFObjectWriter >> 2. -1 large patch >> 3. +2 Resulting special cases are isolated in their own class >> 4. +1 ?Depends upon virtual dispatch for higher level differentiation >> - removes unnecessary trampoline between ELFObjectWriter and >> ELFObjectWriterImpl >> 5. +2 This approach is the best in terms of the resulting design. The >> only drawback is the distinction between MachO and ELF >> >> tryB: subclass ELFObjectWriterImpl instead - I am still working out >> the details on this one - but as of right now, it is just as complex >> as the tryA case. >> The only benefit to this is approach is the superficial similarity >> between the ELFObjectWriter and the MachObjectWriter - in that both >> still trampoline into an *Impl class to do the actual work. >> Unfortunately, it also adds a requirement for registering a NEW >> ELFObjecWriterImpl class (i.e. in addition to the existing >> createELFObjectWriter, and without namespace pollution to llvm, >> creates a linkage dependency failure). >> I will reply to this thread with a patch as soon as I finish this variant. >> >> There are several attachments: >> >> small: >> ?small-elfwriter-cpp (application/octet-stream) 2K >> ?small-elfwriter-rename-record (application/octet-stream) 2K >> >> tryA >> ?arm-mc-elf-s07-elfwriter-tryA-combined.patch (text/x-patch) 43K - >> this is the combined patch - In order to make it more clear, I broke >> up the steps into a dozen or so smaller patches. >> ?tryA.tgz ?- archive of patches >> ?They are combined into a tar archive - the README is reproduced here. >> > > > diffview at http://codereview.chromium.org/4703006 > > TryB is actually a little bit smaller than tryA, and by keeping the > factory within ELFObjectWriter(), I was able to avoid the linkage > issue I ran into earlier. > It seems this is probably a little bit better than tryA > > Its smaller > No switch between ELF and MachO > Rest of the ELFObjectWriter is not modified - the manual trampoline is > still in place. > > -jason > >> Thanks for reading. >> -jason >> > From pdox at google.com Wed Nov 10 16:31:52 2010 From: pdox at google.com (David Meyer) Date: Wed, 10 Nov 2010 14:31:52 -0800 Subject: [llvm-commits] [PATCH] MCFragments Clean Up In-Reply-To: References: Message-ID: Hi Dan, I'm not sure what you mean by vtable construction cost. Do you mean the additional memory to store the vptr? I can't deny that a switch-based implementation uses a little less memory and is probably slightly faster (one less memory read & a closer jump on dispatch). However, I think the resulting code could be significantly cleaner and more extensible. As you can probably tell, I've been working on adding native-client instruction bundling to the MC assembler. The modifications are almost finished. Unfortunately, it has been quite an unpleasant experience. One of the things I did was to add a new fragment type which can store multiple instructions (usually about 3), each with its own fixups and (possibly) each needing relaxation separately. The existing relaxation and lowering mechanism assumes that only MCInstFragment needs relaxation and lowering. I had to copy & paste & modify most of the relaxation code in order to make it relax my new fragment type. If there were instead virtual methods NeedRelaxation() and PerformRelaxation() and LowerFragment() on fragments, this would not have been necessary. I also needed to control the creation of fragments. With bundling enabled, the creation of a fragment sometimes needs to trigger the substitution for a different type of fragment. Unfortunately, the creation of fragments (e.g. "new MCAlignFragment(...)") is sprinkled all over the MCObjectStreamer subclasses instead of being private to MCAssembler. This made the required changes messy and spread out. I'm curious as to why the the assembler doesn't keep fragments as private data. Instead, they get passed and manipulated all over the place. Fragments even get passed directly to the TargetAsmBackend! The number of places in the code that "knows" about a fragments is alarming. I think that ideally, fragment creation could have been hidden behind functions like: // Emits into MCInstFragment or into the current MCDataFragment MCAssembler::EmitInstruction(MCSectionData *Parent, const MCInst &Inst); MCAssembler::EmitValueToAlignment(...); MCAssember::EmitCodeAlignment(...); MCAssembler::EmitOrg(...); MCAssembler::EmitDwarf(...); I'd like to talk more about this. I'd like to get the bundling feature clean enough to be added to mainstream LLVM MC. The changes are mostly innocuous, but little things are getting in the way of making the implementation compact. Unfortunately, I'm under intense pressure to get this stuff working a week ago (in our local branch). I can't focus on refactoring at the moment. When I'm finished, I'll send you a ping. Thanks, David M On Fri, Nov 5, 2010 at 11:09 AM, Daniel Dunbar wrote: > Hi David, > > MCFragment actually used to be virtual. > > I eventually killed this because in practice I felt like the number of > interesting fragments was likely to be small, and the vtable > construction cost wasn't worth it. > > I would propose making an extensible MCFragment subclass to cover the > case of wanting to add plugable MCFragments, instead of imposing a > vtable construction cost on the core classes (which was construct many > hundreds of, and don't actually dispatch on much). > > - Daniel > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/4e2059c5/attachment.html From grosbach at apple.com Wed Nov 10 17:12:48 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 10 Nov 2010 23:12:48 -0000 Subject: [llvm-commits] [llvm] r118730 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td Message-ID: <20101110231248.8609B2A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 17:12:48 2010 New Revision: 118730 URL: http://llvm.org/viewvc/llvm-project?rev=118730&view=rev Log: Fix ARM encoding of LDM+Return instruction. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118730&r1=118729&r2=118730&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 17:12:48 2010 @@ -941,9 +941,11 @@ : XI { bits<16> dsts; - let Inst{20} = 1; // L bit - let Inst{22} = 0; // S bit + bits<4> Rn; let Inst{27-25} = 0b100; + let Inst{22} = 0; // S bit + let Inst{20} = 1; // L bit + let Inst{19-16} = Rn; let Inst{15-0} = dsts; } class AXI4st; + "$Rn = $wb", []> { + bits<4> p; + let Inst{31-28} = p; + let Inst{24-23} = 0b01; + let Inst{21} = 1; +} // On non-Darwin platforms R9 is callee-saved. let isCall = 1, From grosbach at apple.com Wed Nov 10 17:18:50 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 10 Nov 2010 23:18:50 -0000 Subject: [llvm-commits] [llvm] r118732 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td Message-ID: <20101110231850.179F72A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 17:18:49 2010 New Revision: 118732 URL: http://llvm.org/viewvc/llvm-project?rev=118732&view=rev Log: Fix ARM encoding of non-return LDM instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118732&r1=118731&r2=118732&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 17:18:49 2010 @@ -943,7 +943,7 @@ bits<16> dsts; bits<4> Rn; let Inst{27-25} = 0b100; - let Inst{22} = 0; // S bit + let Inst{24-22} = 0b010; let Inst{20} = 1; // L bit let Inst{19-16} = Rn; let Inst{15-0} = dsts; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118732&r1=118731&r2=118732&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 17:18:49 2010 @@ -1186,7 +1186,6 @@ "$Rn = $wb", []> { bits<4> p; let Inst{31-28} = p; - let Inst{24-23} = 0b01; let Inst{21} = 1; } @@ -1709,13 +1708,21 @@ def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, LdStMulFrm, IIC_iLoad_m, - "ldm${amode}${p}\t$Rn, $dsts", "", []>; + "ldm${amode}${p}\t$Rn, $dsts", "", []> { + bits<4> p; + let Inst{31-28} = p; + let Inst{21} = 0; +} def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, "ldm${amode}${p}\t$Rn!, $dsts", - "$Rn = $wb", []>; + "$Rn = $wb", []> { + bits<4> p; + let Inst{31-28} = p; + let Inst{21} = 1; +} } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, From rafael.espindola at gmail.com Wed Nov 10 17:36:59 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 10 Nov 2010 23:36:59 -0000 Subject: [llvm-commits] [llvm] r118733 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20101110233659.CC29B2A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 17:36:59 2010 New Revision: 118733 URL: http://llvm.org/viewvc/llvm-project?rev=118733&view=rev Log: Factor some code into WriteSection. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118733&r1=118732&r2=118733&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 17:36:59 2010 @@ -342,6 +342,10 @@ const MCFragment *DF) const; void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); + void WriteSection(MCAssembler &Asm, + const SectionIndexMapTy &SectionIndexMap, + uint64_t Offset, uint64_t Size, uint64_t Alignment, + const MCSectionELF &Section); }; } @@ -1240,6 +1244,71 @@ return !SectionB && BaseSection == SectionA; } +void ELFObjectWriterImpl::WriteSection(MCAssembler &Asm, + const SectionIndexMapTy &SectionIndexMap, + uint64_t Offset, uint64_t Size, + uint64_t Alignment, + const MCSectionELF &Section) { + uint64_t sh_link = 0; + uint64_t sh_info = 0; + + switch(Section.getType()) { + case ELF::SHT_DYNAMIC: + sh_link = SectionStringTableIndex[&Section]; + sh_info = 0; + break; + + case ELF::SHT_REL: + case ELF::SHT_RELA: { + const MCSectionELF *SymtabSection; + const MCSectionELF *InfoSection; + SymtabSection = Asm.getContext().getELFSection(".symtab", ELF::SHT_SYMTAB, + 0, + SectionKind::getReadOnly(), + false); + sh_link = SectionIndexMap.lookup(SymtabSection); + assert(sh_link && ".symtab not found"); + + // Remove ".rel" and ".rela" prefixes. + unsigned SecNameLen = (Section.getType() == ELF::SHT_REL) ? 4 : 5; + StringRef SectionName = Section.getSectionName().substr(SecNameLen); + + InfoSection = Asm.getContext().getELFSection(SectionName, + ELF::SHT_PROGBITS, 0, + SectionKind::getReadOnly(), + false); + sh_info = SectionIndexMap.lookup(InfoSection); + break; + } + + case ELF::SHT_SYMTAB: + case ELF::SHT_DYNSYM: + sh_link = StringTableIndex; + sh_info = LastLocalSymbolIndex; + break; + + case ELF::SHT_SYMTAB_SHNDX: + sh_link = SymbolTableIndex; + break; + + case ELF::SHT_PROGBITS: + case ELF::SHT_STRTAB: + case ELF::SHT_NOBITS: + case ELF::SHT_NULL: + case ELF::SHT_ARM_ATTRIBUTES: + // Nothing to do. + break; + + default: + assert(0 && "FIXME: sh_type value not supported!"); + break; + } + + WriteSecHdrEntry(SectionStringTableIndex[&Section], Section.getType(), + Section.getFlags(), 0, Offset, Size, sh_link, sh_info, + Alignment, Section.getEntrySize()); +} + void ELFObjectWriterImpl::WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) { SectionIndexMapTy SectionIndexMap; @@ -1320,68 +1389,9 @@ const MCSectionELF &Section = static_cast(SD.getSection()); - uint64_t sh_link = 0; - uint64_t sh_info = 0; - - switch(Section.getType()) { - case ELF::SHT_DYNAMIC: - sh_link = SectionStringTableIndex[&it->getSection()]; - sh_info = 0; - break; - - case ELF::SHT_REL: - case ELF::SHT_RELA: { - const MCSectionELF *SymtabSection; - const MCSectionELF *InfoSection; - - SymtabSection = Asm.getContext().getELFSection(".symtab", ELF::SHT_SYMTAB, 0, - SectionKind::getReadOnly(), - false); - sh_link = SectionIndexMap[SymtabSection]; - assert(sh_link && ".symtab not found"); - - // Remove ".rel" and ".rela" prefixes. - unsigned SecNameLen = (Section.getType() == ELF::SHT_REL) ? 4 : 5; - StringRef SectionName = Section.getSectionName().substr(SecNameLen); - - InfoSection = Asm.getContext().getELFSection(SectionName, - ELF::SHT_PROGBITS, 0, - SectionKind::getReadOnly(), - false); - sh_info = SectionIndexMap[InfoSection]; - break; - } - - case ELF::SHT_SYMTAB: - case ELF::SHT_DYNSYM: - sh_link = StringTableIndex; - sh_info = LastLocalSymbolIndex; - break; - - case ELF::SHT_SYMTAB_SHNDX: - sh_link = SymbolTableIndex; - break; - - case ELF::SHT_PROGBITS: - case ELF::SHT_STRTAB: - case ELF::SHT_NOBITS: - case ELF::SHT_NULL: - case ELF::SHT_ARM_ATTRIBUTES: - // Nothing to do. - break; - - default: - assert(0 && "FIXME: sh_type value not supported!"); - break; - } - - WriteSecHdrEntry(SectionStringTableIndex[&it->getSection()], - Section.getType(), Section.getFlags(), - 0, - SectionOffsetMap.lookup(&SD.getSection()), - Layout.getSectionSize(&SD), sh_link, - sh_info, SD.getAlignment(), - Section.getEntrySize()); + WriteSection(Asm, SectionIndexMap, SectionOffsetMap[&Section], + Layout.getSectionSize(&SD), + SD.getAlignment(), Section); } } From grosbach at apple.com Wed Nov 10 17:38:36 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 10 Nov 2010 23:38:36 -0000 Subject: [llvm-commits] [llvm] r118736 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101110233836.40B952A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 17:38:36 2010 New Revision: 118736 URL: http://llvm.org/viewvc/llvm-project?rev=118736&view=rev Log: ARM LDM encoding for the mode (ia, ib, da, db) operand. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118736&r1=118735&r2=118736&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 10 17:38:36 2010 @@ -177,6 +177,8 @@ const { return 0; } unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) + const {return 0; } uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) const { return 0; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118736&r1=118735&r2=118736&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 17:38:36 2010 @@ -942,8 +942,10 @@ asm, cstr, pattern> { bits<16> dsts; bits<4> Rn; + bits<2> amode; let Inst{27-25} = 0b100; - let Inst{24-22} = 0b010; + let Inst{24-23} = amode; + let Inst{22} = 0; // S bit let Inst{20} = 1; // L bit let Inst{19-16} = Rn; let Inst{15-0} = dsts; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118736&r1=118735&r2=118736&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 17:38:36 2010 @@ -456,6 +456,7 @@ // ldstm_mode := {ia, ib, da, db} // def ldstm_mode : OptionalDefOperand { + string EncoderMethod = "getLdStmModeOpValue"; let PrintMethod = "printLdStmModeOperand"; } Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118736&r1=118735&r2=118736&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Nov 10 17:38:36 2010 @@ -82,6 +82,19 @@ uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; + /// getLdStmModeOpValue - Return encoding for load/store multiple mode. + uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { + ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); + switch (Mode) { + default: assert(0 && "Unknown addressing sub-mode!"); + case ARM_AM::da: return 0; + case ARM_AM::ia: return 1; + case ARM_AM::db: return 2; + case ARM_AM::ib: return 3; + } + } + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; From grosbach at apple.com Wed Nov 10 17:44:32 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 10 Nov 2010 23:44:32 -0000 Subject: [llvm-commits] [llvm] r118738 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td Message-ID: <20101110234432.56E0D2A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 17:44:32 2010 New Revision: 118738 URL: http://llvm.org/viewvc/llvm-project?rev=118738&view=rev Log: Move LDM predicate operand encoding into base clase. Add STM missing STM encoding bits. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118738&r1=118737&r2=118738&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 17:44:32 2010 @@ -940,9 +940,11 @@ string asm, string cstr, list pattern> : XI { + bits<4> p; bits<16> dsts; bits<4> Rn; bits<2> amode; + let Inst{31-28} = p; let Inst{27-25} = 0b100; let Inst{24-23} = amode; let Inst{22} = 0; // S bit @@ -954,10 +956,16 @@ string asm, string cstr, list pattern> : XI { + bits<4> p; bits<16> srcs; - let Inst{20} = 0; // L bit - let Inst{22} = 0; // S bit + bits<4> Rn; + bits<2> amode; + let Inst{31-28} = p; let Inst{27-25} = 0b100; + let Inst{24-23} = amode; + let Inst{22} = 0; // S bit + let Inst{20} = 0; // L bit + let Inst{19-16} = Rn; let Inst{15-0} = srcs; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118738&r1=118737&r2=118738&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 17:44:32 2010 @@ -1185,8 +1185,6 @@ IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, "ldm${mode}${p}\t$Rn!, $dsts", "$Rn = $wb", []> { - bits<4> p; - let Inst{31-28} = p; let Inst{21} = 1; } @@ -1710,8 +1708,6 @@ reglist:$dsts, variable_ops), IndexModeNone, LdStMulFrm, IIC_iLoad_m, "ldm${amode}${p}\t$Rn, $dsts", "", []> { - bits<4> p; - let Inst{31-28} = p; let Inst{21} = 0; } @@ -1720,8 +1716,6 @@ IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, "ldm${amode}${p}\t$Rn!, $dsts", "$Rn = $wb", []> { - bits<4> p; - let Inst{31-28} = p; let Inst{21} = 1; } } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq @@ -1731,13 +1725,19 @@ def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeNone, LdStMulFrm, IIC_iStore_m, - "stm${amode}${p}\t$Rn, $srcs", "", []>; + "stm${amode}${p}\t$Rn, $srcs", "", []> { + let Inst{21} = 0; +} def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iStore_mu, "stm${amode}${p}\t$Rn!, $srcs", - "$Rn = $wb", []>; + "$Rn = $wb", []> { + bits<4> p; + let Inst{31-28} = p; + let Inst{21} = 1; +} } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq //===----------------------------------------------------------------------===// From stoklund at 2pi.dk Wed Nov 10 17:55:57 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 23:55:57 -0000 Subject: [llvm-commits] [llvm] r118741 - in /llvm/trunk/lib/CodeGen: InlineSpiller.cpp RegAllocLinearScan.cpp Message-ID: <20101110235557.1EA772A6C12C@llvm.org> Author: stoklund Date: Wed Nov 10 17:55:56 2010 New Revision: 118741 URL: http://llvm.org/viewvc/llvm-project?rev=118741&view=rev Log: Hook up AliasAnalysis in InlineSpiller. This is used for rematerializing constant loads. Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=118741&r1=118740&r2=118741&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Nov 10 17:55:56 2010 @@ -17,6 +17,7 @@ #include "LiveRangeEdit.h" #include "SplitKit.h" #include "VirtRegMap.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/MachineDominators.h" @@ -47,6 +48,7 @@ LiveStacks &lss_; MachineDominatorTree &mdt_; MachineLoopInfo &loops_; + AliasAnalysis *aa_; VirtRegMap &vrm_; MachineFrameInfo &mfi_; MachineRegisterInfo &mri_; @@ -76,6 +78,7 @@ lss_(pass.getAnalysis()), mdt_(pass.getAnalysis()), loops_(pass.getAnalysis()), + aa_(&pass.getAnalysis()), vrm_(vrm), mfi_(*mf.getFrameInfo()), mri_(mf.getRegInfo()), @@ -219,7 +222,7 @@ /// and trim the live ranges after. void InlineSpiller::reMaterializeAll() { // Do a quick scan of the interval values to find if any are remattable. - if (!edit_->anyRematerializable(lis_, tii_, 0)) + if (!edit_->anyRematerializable(lis_, tii_, aa_)) return; usedValues_.clear(); Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=118741&r1=118740&r2=118741&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Nov 10 17:55:56 2010 @@ -15,6 +15,7 @@ #include "VirtRegMap.h" #include "VirtRegRewriter.h" #include "Spiller.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Function.h" #include "llvm/CodeGen/CalcSpillWeights.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" @@ -193,6 +194,8 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); if (StrongPHIElim) @@ -391,6 +394,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(VirtRegMap) INITIALIZE_AG_DEPENDENCY(RegisterCoalescer) +INITIALIZE_AG_DEPENDENCY(AliasAnalysis) INITIALIZE_PASS_END(RALinScan, "linearscan-regalloc", "Linear Scan Register Allocator", false, false) From stoklund at 2pi.dk Wed Nov 10 17:56:00 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 23:56:00 -0000 Subject: [llvm-commits] [llvm] r118742 - /llvm/trunk/lib/CodeGen/SplitKit.cpp Message-ID: <20101110235600.B2C1B2A6C12D@llvm.org> Author: stoklund Date: Wed Nov 10 17:56:00 2010 New Revision: 118742 URL: http://llvm.org/viewvc/llvm-project?rev=118742&view=rev Log: No need to add liveness that's already there. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=118742&r1=118741&r2=118742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Nov 10 17:56:00 2010 @@ -764,10 +764,7 @@ } DEBUG(dbgs() << ": valno " << ParentVNI->id); truncatedValues.insert(ParentVNI); - VNInfo *VNI = defFromParent(openli_, ParentVNI, End, MBB, - MBB.getFirstTerminator()); - // Make sure openli is live out of MBB. - openli_.getLI()->addRange(LiveRange(VNI->def, End.getNextSlot(), VNI)); + defFromParent(openli_, ParentVNI, End, MBB, MBB.getFirstTerminator()); DEBUG(dbgs() << ": " << *openli_.getLI() << '\n'); } From stoklund at 2pi.dk Wed Nov 10 17:56:03 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 23:56:03 -0000 Subject: [llvm-commits] [llvm] r118743 - /llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Message-ID: <20101110235603.13D092A6C12E@llvm.org> Author: stoklund Date: Wed Nov 10 17:56:02 2010 New Revision: 118743 URL: http://llvm.org/viewvc/llvm-project?rev=118743&view=rev Log: Delete unused function. Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=118743&r1=118742&r2=118743&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Wed Nov 10 17:56:02 2010 @@ -590,29 +590,6 @@ return resVal; } - /// Return a list of MBBs that can be reach via any branches or - /// fall-throughs. - bool findReachableMBBs(SlotIndex start, SlotIndex end, - SmallVectorImpl &mbbs) const { - std::vector::const_iterator itr = - std::lower_bound(idx2MBBMap.begin(), idx2MBBMap.end(), start); - - bool resVal = false; - while (itr != idx2MBBMap.end()) { - if (itr->first > end) - break; - MachineBasicBlock *mbb = itr->second; - if (getMBBEndIdx(mbb) > end) - break; - for (MachineBasicBlock::succ_iterator si = mbb->succ_begin(), - se = mbb->succ_end(); si != se; ++si) - mbbs.push_back(*si); - resVal = true; - ++itr; - } - return resVal; - } - /// Returns the MBB covering the given range, or null if the range covers /// more than one basic block. MachineBasicBlock* getMBBCoveringRange(SlotIndex start, SlotIndex end) const { From gkistanova at gmail.com Wed Nov 10 18:07:07 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Thu, 11 Nov 2010 00:07:07 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118744 - in /llvm-gcc-4.2/trunk/extras: build-x-4-armeabi-hardfloat build-x-4-armeabi-softfloat Message-ID: <20101111000707.B38EE2A6C12C@llvm.org> Author: gkistanova Date: Wed Nov 10 18:07:07 2010 New Revision: 118744 URL: http://llvm.org/viewvc/llvm-project?rev=118744&view=rev Log: Added script for new arm-softfloat-eabi builder. Fixed existing arm-eabi script. Added: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-softfloat (with props) Modified: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat Modified: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat?rev=118744&r1=118743&r2=118744&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat (original) +++ llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-hardfloat Wed Nov 10 18:07:07 2010 @@ -185,7 +185,6 @@ --target=arm-eabi \ --enable-languages=c,c++ \ --disable-nls \ - --prefix=/opt/cross-tools \ --program-prefix=llvm- \ --with-newlib \ --with-headers=yes \ Added: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-softfloat URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-softfloat?rev=118744&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-softfloat (added) +++ llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-softfloat Wed Nov 10 18:07:07 2010 @@ -0,0 +1,219 @@ +#!/bin/bash + +set -e # Terminate script at the first line that fails. +set -o pipefail # Return the first non-zero pipe command error. +set -x # Print commands as they are executed + +# This script performs an automated build on i686-pc-linux-gnu of +# cross llvm-gcc for arm-eabi-soft-float. It assumes the valid native +# compiler for i686-pc-linux-gnu is in place and available as well as +# cross libraries and headers for arm-softfloat-eabi. + +# --build=i686-pc-linux-gnu +# --host=i686-pc-linux-gnu +# --target=arm-softfloat-eabi +# + +# The usage: +# Run this build from the build from the build root directory as +# build-x-4-armeabi-softfloat [] [] + +# Expected project tree structure: +# +# +-- ${LLVM_src} +# +-- ${LLVM_GCC_src} +# +-- ${LLVM_obj} +# +-- ${LLVM_GCC_obj} +# +-- ${INSTALL} + +LLVM_src=llvm.src # The LLVM source code root directory name. +LLVM_GCC_src=llvm-gcc.src # The LLVM-GCC source code root directory name. +LLVM_obj=llvm.obj # The LLVM build root directory name. +LLVM_GCC_obj=llvm-gcc.obj # The LLVM-GCC build root directory name. +INSTALL=install # Where the result will be installed. + +BUILD_ROOT=$PWD # Where build happens. +PRIVATE_INSTALL=${BUILD_ROOT}/${INSTALL} # Where the result will be installed. + +#------------------------------------------------------------------------------ +# Define build steps, parse and validate input parameters +#------------------------------------------------------------------------------ + +# This script supports the following steps: +do_clean=no # Clean up the build directory. +do_copy_cross_tools=no # Copy cross-tools. +do_configure_llvm=no # Configure LLVM. +do_make_llvm=no # Make LLVM. +do_install_llvm=no # Install LLVM-GCC. +do_test_llvm=no # Test LLVM. +do_configure_llvmgcc=no # Configure LLVM-GCC. +do_make_llvmgcc=no # Make LLVM-GCC. +do_install_llvmgcc=no # Install LLVM-GCC. +do_all=no # Runs all steps at once when requested. + +# Set step parameter +if (( $# == 0 )) ; then + do_all=yes +fi +# else +if (( ! $# == 0 )) ; then + # First check that the parameter actually defines a step. + case $1 in + clean | \ + copy_cross_tools | \ + configure_llvm | \ + make_llvm | \ + install_llvm | \ + test_llvm | \ + configure_llvmgcc | \ + make_llvmgcc | \ + install_llvmgcc | \ + all) + eval do_$1=yes # Set the flag for the requested step . + shift # Remove it since is is ours and already precessed. + ;; + + *) + # Not our parameter. Pass it as is. + esac +fi + +# Set all steps if do_all requested +if [ "$do_all" == "yes" ] ; then + # Set all steps to yes + do_clean=yes + do_copy_cross_tools=yes + do_configure_llvm=yes + do_make_llvm=yes + do_install_llvm=yes + do_test_llvm=yes + do_configure_llvmgcc=yes + do_make_llvmgcc=yes + do_install_llvmgcc=yes +fi + +#------------------------------------------------------------------------------ +# Step: Clean up. +#------------------------------------------------------------------------------ +if [ "$do_clean" == "yes" ] ; then + + # Remove everything from where we will be installing the result. + rm -rf ${PRIVATE_INSTALL} + mkdir -p ${PRIVATE_INSTALL} + chmod a+rx ${PRIVATE_INSTALL} + +fi + +#------------------------------------------------------------------------------ +# Step: Copy cross-tools and newlib +#------------------------------------------------------------------------------ +if [ "$do_copy_cross_tools" == "yes" ] ; then + + # We need a local copy of binutils, system libraries and headers, + # since we will be installing there. + cp -Ru /opt/cross-tools/* ${PRIVATE_INSTALL} + cp -Ru /opt/newlib-src/newlib/ ${BUILD_ROOT}/${LLVM_GCC_src} + cp -Ru /opt/newlib-src/libgloss/ ${BUILD_ROOT}/${LLVM_GCC_src} + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvm" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_obj} + cd ${BUILD_ROOT}/${LLVM_obj} + + ../${LLVM_src}/configure --prefix=${PRIVATE_INSTALL} \ + --enable-optimized \ + --enable-targets=cbe,arm \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM. +#------------------------------------------------------------------------------ +if [ "$do_make_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM. +#------------------------------------------------------------------------------ +if [ "$do_install_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make install VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Test LLVM. +#------------------------------------------------------------------------------ +if [ "$do_test_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + make check-lit VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvmgcc" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_GCC_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_GCC_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_GCC_obj} + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + + ../${LLVM_GCC_src}/configure --prefix=${PRIVATE_INSTALL} \ + --target=arm-softfloat-eabi \ + --enable-languages=c,c++ \ + --disable-nls \ + --program-prefix=llvm- \ + --with-newlib \ + --with-headers=yes \ + --enable-llvm=${BUILD_ROOT}/${LLVM_obj} \ + --with-cpu=cortex-a8 \ + --with-fpu=neon \ + --with-float=soft \ + --with-abi=aapcs \ + $@ # Extra args if any +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_make_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_install_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make install \ + $@ # Extra args if any + +fi Propchange: llvm-gcc-4.2/trunk/extras/build-x-4-armeabi-softfloat ------------------------------------------------------------------------------ svn:executable = * From dpatel at apple.com Wed Nov 10 18:13:40 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 11 Nov 2010 00:13:40 -0000 Subject: [llvm-commits] [llvm] r118746 - /llvm/trunk/docs/TestingGuide.html Message-ID: <20101111001340.2D3142A6C12C@llvm.org> Author: dpatel Date: Wed Nov 10 18:13:39 2010 New Revision: 118746 URL: http://llvm.org/viewvc/llvm-project?rev=118746&view=rev Log: Document debuginfo-tests. Modified: llvm/trunk/docs/TestingGuide.html Modified: llvm/trunk/docs/TestingGuide.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TestingGuide.html?rev=118746&r1=118745&r2=118746&view=diff ============================================================================== --- llvm/trunk/docs/TestingGuide.html (original) +++ llvm/trunk/docs/TestingGuide.html Wed Nov 10 18:13:39 2010 @@ -18,12 +18,14 @@

  • Quick start
  • Regression test structure @@ -141,6 +143,23 @@ + +
    Debugging Information +tests
    + + +
    + +

    The test suite contains tests to check quality of debugging information. +The test are written in C based languages or in LLVM assembly language.

    + +

    These tests are compiled and run under a debugger. The debugger output +is checked to validate of debugging information. See README.txt in the +test suite for more information . This test suite is located in the +debuginfo-tests Subversion module.

    + +
    +
    Quick start
    @@ -272,6 +291,25 @@ + +
    Debugging Information +tests
    + + +

    To run debugging information tests simply checkout the tests inside +clang/test directory.

    + +
    +
    +%cd clang/test
+% svn co http://llvm.org/svn/llvm-project/debuginfo-tests/trunk debuginfo-tests
+
    +
    + +

    These tests are already set up to run as part of clang regression tests.

    + + +
    Regression test structure
    From stoklund at 2pi.dk Wed Nov 10 18:19:20 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 11 Nov 2010 00:19:20 -0000 Subject: [llvm-commits] [llvm] r118747 - in /llvm/trunk: include/llvm/CodeGen/SlotIndexes.h lib/CodeGen/SlotIndexes.cpp Message-ID: <20101111001920.919222A6C12C@llvm.org> Author: stoklund Date: Wed Nov 10 18:19:20 2010 New Revision: 118747 URL: http://llvm.org/viewvc/llvm-project?rev=118747&view=rev Log: Insert two blank SlotIndexes between basic blocks instead of just one. This is the first small step towards using closed intervals for liveness instead of the half-open intervals we're using now. We want to be able to distinguish between a SlotIndex that represents a variable being live-out of a basic block, and an index representing a variable live-in to its successor. That requires two separate indexes between blocks. One for live-outs and one for live-ins. With this change, getMBBEndIdx(MBB).getPrevSlot() becomes stable so it stays greater than any instructions inserted at the end of MBB. Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h llvm/trunk/lib/CodeGen/SlotIndexes.cpp Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=118747&r1=118746&r2=118747&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Wed Nov 10 18:19:20 2010 @@ -738,6 +738,7 @@ MachineFunction::iterator nextMBB = llvm::next(MachineFunction::iterator(mbb)); IndexListEntry *startEntry = createEntry(0, 0); + IndexListEntry *stopEntry = createEntry(0, 0); IndexListEntry *nextEntry = 0; if (nextMBB == mbb->getParent()->end()) { @@ -747,6 +748,7 @@ } insert(nextEntry, startEntry); + insert(nextEntry, stopEntry); SlotIndex startIdx(startEntry, SlotIndex::LOAD); SlotIndex endIdx(nextEntry, SlotIndex::LOAD); Modified: llvm/trunk/lib/CodeGen/SlotIndexes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SlotIndexes.cpp?rev=118747&r1=118746&r2=118747&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SlotIndexes.cpp (original) +++ llvm/trunk/lib/CodeGen/SlotIndexes.cpp Wed Nov 10 18:19:20 2010 @@ -127,8 +127,12 @@ index += (Slots + 1) * SlotIndex::NUM; } - // One blank instruction at the end. - push_back(createEntry(0, index)); + // We insert two blank instructions between basic blocks. + // One to represent live-out registers and one to represent live-ins. + push_back(createEntry(0, index)); + index += SlotIndex::NUM; + + push_back(createEntry(0, index)); SlotIndex blockEndIndex(back(), SlotIndex::LOAD); mbb2IdxMap.insert( From gohman at apple.com Wed Nov 10 18:20:27 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 00:20:27 -0000 Subject: [llvm-commits] [llvm] r118748 - in /llvm/trunk: include/llvm/Analysis/MemoryDependenceAnalysis.h lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20101111002027.C9D562A6C12C@llvm.org> Author: djg Date: Wed Nov 10 18:20:27 2010 New Revision: 118748 URL: http://llvm.org/viewvc/llvm-project?rev=118748&view=rev Log: Set NonLocalDepInfo's Size field to UnknownSize when invalidating it, so that it doesn't appear to be a known size. Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=118748&r1=118747&r2=118748&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Wed Nov 10 18:20:27 2010 @@ -234,7 +234,7 @@ /// pointer. May be null if there are no tags or conflicting tags. const MDNode *TBAATag; - NonLocalPointerInfo() : Size(0), TBAATag(0) {} + NonLocalPointerInfo() : Size(AliasAnalysis::UnknownSize), TBAATag(0) {} }; /// CachedNonLocalPointerInfo - This map stores the cached results of doing Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118748&r1=118747&r2=118748&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Nov 10 18:20:27 2010 @@ -860,7 +860,7 @@ CacheInfo->Pair = BBSkipFirstBlockPair(StartBB, SkipFirstBlock); else { CacheInfo->Pair = BBSkipFirstBlockPair(); - CacheInfo->Size = 0; + CacheInfo->Size = AliasAnalysis::UnknownSize; CacheInfo->TBAATag = 0; } @@ -986,7 +986,7 @@ // cached value to do more work but not miss the phi trans failure. NonLocalPointerInfo &NLPI = NonLocalPointerDeps[CacheKey]; NLPI.Pair = BBSkipFirstBlockPair(); - NLPI.Size = 0; + NLPI.Size = AliasAnalysis::UnknownSize; NLPI.TBAATag = 0; continue; } @@ -1015,7 +1015,7 @@ // specific block queries) but we can't do the fastpath "return all // results from the set" Clear out the indicator for this. CacheInfo->Pair = BBSkipFirstBlockPair(); - CacheInfo->Size = 0; + CacheInfo->Size = AliasAnalysis::UnknownSize; CacheInfo->TBAATag = 0; SkipFirstBlock = false; continue; @@ -1034,7 +1034,7 @@ // specific block queries) but we can't do the fastpath "return all // results from the set". Clear out the indicator for this. CacheInfo->Pair = BBSkipFirstBlockPair(); - CacheInfo->Size = 0; + CacheInfo->Size = AliasAnalysis::UnknownSize; CacheInfo->TBAATag = 0; // If *nothing* works, mark the pointer as being clobbered by the first @@ -1252,7 +1252,7 @@ // The cache is not valid for any specific block anymore. NonLocalPointerDeps[P].Pair = BBSkipFirstBlockPair(); - NonLocalPointerDeps[P].Size = 0; + NonLocalPointerDeps[P].Size = AliasAnalysis::UnknownSize; NonLocalPointerDeps[P].TBAATag = 0; // Update any entries for RemInst to use the instruction after it. From stuart at apple.com Wed Nov 10 18:33:13 2010 From: stuart at apple.com (Stuart Hastings) Date: Thu, 11 Nov 2010 00:33:13 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118749 - /llvm-gcc-4.2/trunk/gcc/c-typeck.c Message-ID: <20101111003313.67B4E2A6C12C@llvm.org> Author: stuart Date: Wed Nov 10 18:33:13 2010 New Revision: 118749 URL: http://llvm.org/viewvc/llvm-project?rev=118749&view=rev Log: Support taking the address of a block function within a block. Radar 8521187. Needs a test case. Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-typeck.c?rev=118749&r1=118748&r2=118749&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-typeck.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-typeck.c Wed Nov 10 18:33:13 2010 @@ -4976,7 +4976,27 @@ warning (OPT_Wtraditional, "traditional C rejects automatic " "aggregate initialization"); - DECL_INITIAL (decl) = value; + /* LLVM LOCAL begin 8521187 */ + { + bool was_error_mark = (DECL_INITIAL(decl) == error_mark_node); + extern void * TheTreeToLLVM; /* llvm-internal.h is not available here. Ugh. */ + + DECL_INITIAL (decl) = value; + + /* + * If we're updating the initialization of a variable or function decl, + * and we're inside a function body (not initializing a global or static), + * and the previous value was the placeholder 'error_mark_node', + * then tell LLVM we updated the initialization. + */ + if ((TREE_CODE(decl) == VAR_DECL || TREE_CODE(decl) == FUNCTION_DECL) + && TREE_STATIC(decl) && was_error_mark && TheTreeToLLVM) + { + extern void reset_type_and_initializer_llvm(tree); + reset_type_and_initializer_llvm(decl); + } + } + /* LLVM LOCAL end 8521187 */ /* ANSI wants warnings about out-of-range constant initializers. */ STRIP_TYPE_NOPS (value); From stuart at apple.com Wed Nov 10 18:37:14 2010 From: stuart at apple.com (Stuart Hastings) Date: Thu, 11 Nov 2010 00:37:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118750 - in /llvm-gcc-4.2/trunk/gcc: c-opts.c calls.c common.opt config/arm/darwin.h config/darwin.h cp/decl.c cp/init.c dwarf2out.c function.c opts.c tree-eh.c tree-ssa-math-opts.c Message-ID: <20101111003715.34D3F2A6C12C@llvm.org> Author: stuart Date: Wed Nov 10 18:37:14 2010 New Revision: 118750 URL: http://llvm.org/viewvc/llvm-project?rev=118750&view=rev Log: Support -fno-exceptions in Objective-C++. Tweaked flag_exceptions from a binary into a trinary variable. Modified: llvm-gcc-4.2/trunk/gcc/c-opts.c llvm-gcc-4.2/trunk/gcc/calls.c llvm-gcc-4.2/trunk/gcc/common.opt llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/cp/decl.c llvm-gcc-4.2/trunk/gcc/cp/init.c llvm-gcc-4.2/trunk/gcc/dwarf2out.c llvm-gcc-4.2/trunk/gcc/function.c llvm-gcc-4.2/trunk/gcc/opts.c llvm-gcc-4.2/trunk/gcc/tree-eh.c llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c Modified: llvm-gcc-4.2/trunk/gcc/c-opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-opts.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-opts.c Wed Nov 10 18:37:14 2010 @@ -237,7 +237,10 @@ #endif /* APPLE LOCAL end -Wfour-char-constants */ - flag_exceptions = c_dialect_cxx (); + /* LLVM LOCAL begin 6635085 */ + if (c_dialect_cxx() && flag_exceptions < 0) + flag_exceptions = 1; + /* LLVM LOCAL end 6635085 */ /* LLVM local begin One Definition Rule */ #ifdef ENABLE_LLVM flag_odr = c_dialect_cxx (); @@ -1153,7 +1156,10 @@ /* Default to ObjC sjlj exception handling if NeXT runtime. */ if (flag_objc_sjlj_exceptions < 0) flag_objc_sjlj_exceptions = flag_next_runtime; - if (flag_objc_exceptions && !flag_objc_sjlj_exceptions) + /* LLVM LOCAL begin 6635085 */ + if ((flag_objc_exceptions && !flag_objc_sjlj_exceptions) + || flag_exceptions < 0) + /* LLVM LOCAL end 6635085 */ flag_exceptions = 1; /* -Wextra implies -Wsign-compare, -Wmissing-field-initializers and Modified: llvm-gcc-4.2/trunk/gcc/calls.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/calls.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/calls.c (original) +++ llvm-gcc-4.2/trunk/gcc/calls.c Wed Nov 10 18:37:14 2010 @@ -2384,6 +2384,8 @@ with stack pointer depressed. Also do the adjustments before a throwing call, otherwise exception handling can fail; PR 19225. */ + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions > 0); if (pending_stack_adjust >= 32 || (pending_stack_adjust > 0 && (flags & (ECF_MAY_BE_ALLOCA | ECF_SP_DEPRESSED))) Modified: llvm-gcc-4.2/trunk/gcc/common.opt URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/common.opt?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/common.opt (original) +++ llvm-gcc-4.2/trunk/gcc/common.opt Wed Nov 10 18:37:14 2010 @@ -519,7 +519,7 @@ Do not suppress C++ class debug information. fexceptions -Common Report Var(flag_exceptions) +Common Report Var(flag_exceptions) Init(-1) Enable exception handling ; APPLE LOCAL begin optimization pragmas 3124235/3420242 Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Wed Nov 10 18:37:14 2010 @@ -382,7 +382,9 @@ #define OBJC_TARGET_FLAG_OBJC_ABI \ do { \ - if (flag_objc_abi == -1) \ + /* LLVM LOCAL 6635085 */ \ + if (flag_objc_abi == -1 \ + && flag_exceptions == -1) \ flag_objc_abi = 2; \ if (flag_objc_legacy_dispatch == -1) \ flag_objc_legacy_dispatch = 1; \ Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Wed Nov 10 18:37:14 2010 @@ -863,7 +863,10 @@ flag_objc_zerocost_exceptions = 1; \ if (flag_objc_zerocost_exceptions) \ { \ - flag_exceptions = 1; \ + /* APPLE LOCAL begin 6635085 */ \ + if (flag_exceptions == -1) \ + flag_exceptions = 1; \ + /* APPLE LOCAL end 6635085 */ \ flag_objc_sjlj_exceptions = 0; \ } \ /* APPLE LOCAL end radar 5023725 */ \ Modified: llvm-gcc-4.2/trunk/gcc/cp/decl.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/decl.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/cp/decl.c (original) +++ llvm-gcc-4.2/trunk/gcc/cp/decl.c Wed Nov 10 18:37:14 2010 @@ -1104,6 +1104,8 @@ all declarations, including the definition and an explicit specialization, of that function shall have an exception-specification with the same set of type-ids. */ + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); if ((pedantic || ! DECL_IN_SYSTEM_HEADER (old_decl)) && ! DECL_IS_BUILTIN (old_decl) && flag_exceptions @@ -3393,7 +3395,8 @@ init_class_processing (); init_rtti_processing (); - if (flag_exceptions) + /* LLVM LOCAL 6635085 */ + if (flag_exceptions > 0) init_exception_processing (); if (! supports_one_only ()) @@ -11736,6 +11739,8 @@ static bool use_eh_spec_block (tree fn) { + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); return (flag_exceptions && flag_enforce_eh_specs && !processing_template_decl && TYPE_RAISES_EXCEPTIONS (TREE_TYPE (fn)) Modified: llvm-gcc-4.2/trunk/gcc/cp/init.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/init.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/cp/init.c (original) +++ llvm-gcc-4.2/trunk/gcc/cp/init.c Wed Nov 10 18:37:14 2010 @@ -1957,6 +1957,8 @@ unambiguous matching deallocation function can be found, propagating the exception does not cause the object's memory to be freed. */ + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); if (flag_exceptions && ! use_java_new) { enum tree_code dcode = array_p ? VEC_DELETE_EXPR : DELETE_EXPR; @@ -2495,6 +2497,8 @@ /* Protect the entire array initialization so that we can destroy the partially constructed array if an exception is thrown. But don't do this if we're assigning. */ + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); if (flag_exceptions && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (type) && from_array != 2) { @@ -2629,6 +2633,8 @@ } /* Make sure to cleanup any partially constructed elements. */ + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); if (flag_exceptions && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (type) && from_array != 2) { Modified: llvm-gcc-4.2/trunk/gcc/dwarf2out.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/dwarf2out.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/dwarf2out.c (original) +++ llvm-gcc-4.2/trunk/gcc/dwarf2out.c Wed Nov 10 18:37:14 2010 @@ -123,7 +123,8 @@ #ifdef DWARF2_UNWIND_INFO || (DWARF2_UNWIND_INFO && (flag_unwind_tables - || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))) + /* LLVM LOCAL 6635085 */ + || (flag_exceptions > 0 && ! USING_SJLJ_EXCEPTIONS))) #endif ); } @@ -2207,6 +2208,8 @@ discarded. Example where this matters: a primary function template in C++ requires EH information, but an explicit specialization doesn't. */ + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); if (TARGET_USES_WEAK_UNWIND_INFO && ! flag_asynchronous_unwind_tables /* APPLE LOCAL begin for-fsf-4_4 5480287 */ \ @@ -2380,6 +2383,8 @@ floor_log2 (for_eh ? PTR_SIZE : DWARF2_ADDR_SIZE)); ASM_OUTPUT_LABEL (asm_out_file, l2); + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); /* Loop through all of the FDE's. */ for (i = 0; i < fde_table_in_use; i++) { @@ -2664,7 +2669,8 @@ #ifndef TARGET_UNWIND_INFO /* Output another copy for the unwinder. */ - if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions)) + /* LLVM LOCAL 6635085 */ + if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions > 0)) output_call_frame_info (1); #endif } Modified: llvm-gcc-4.2/trunk/gcc/function.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/function.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/function.c (original) +++ llvm-gcc-4.2/trunk/gcc/function.c Wed Nov 10 18:37:14 2010 @@ -4475,6 +4475,8 @@ /* Output the label for the actual return from the function. */ emit_label (return_label); + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions > 0); if (USING_SJLJ_EXCEPTIONS) { /* Let except.c know where it should emit the call to unregister Modified: llvm-gcc-4.2/trunk/gcc/opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/opts.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/opts.c Wed Nov 10 18:37:14 2010 @@ -736,7 +736,8 @@ generating unwind info. If flag_exceptions is turned on we need to turn off the partitioning optimization. */ - if (flag_exceptions && flag_reorder_blocks_and_partition) + /* LLVM LOCAL 6635085 */ + if (flag_exceptions > 0 && flag_reorder_blocks_and_partition) { inform ("-freorder-blocks-and-partition does not work with exceptions"); Modified: llvm-gcc-4.2/trunk/gcc/tree-eh.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-eh.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-eh.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-eh.c Wed Nov 10 18:37:14 2010 @@ -1355,6 +1355,11 @@ struct leh_state this_state; int ndests; + /* LLVM LOCAL begin 6635085 */ + /* if ( ! flag_exceptions) + fatal_error("try/catch constructs require -fexceptions"); */ + /* LLVM LOCAL end 6635085 */ + /* Process the try block. */ memset (&this_tf, 0, sizeof (this_tf)); Modified: llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c?rev=118750&r1=118749&r2=118750&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c Wed Nov 10 18:37:14 2010 @@ -259,6 +259,8 @@ if (occ_child->children) compute_merit (occ_child); + /* LLVM LOCAL 6635085 */ + gcc_assert(flag_exceptions >= 0); if (flag_exceptions) bb = single_noncomplex_succ (dom); else From gohman at apple.com Wed Nov 10 18:42:22 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 00:42:22 -0000 Subject: [llvm-commits] [llvm] r118752 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20101111004222.7BEAD2A6C12C@llvm.org> Author: djg Date: Wed Nov 10 18:42:22 2010 New Revision: 118752 URL: http://llvm.org/viewvc/llvm-project?rev=118752&view=rev Log: It's not necessary to clear out the Size and TBAATag at each of these points. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118752&r1=118751&r2=118752&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Nov 10 18:42:22 2010 @@ -858,11 +858,8 @@ // otherwise it isn't. if (Cache->empty()) CacheInfo->Pair = BBSkipFirstBlockPair(StartBB, SkipFirstBlock); - else { + else CacheInfo->Pair = BBSkipFirstBlockPair(); - CacheInfo->Size = AliasAnalysis::UnknownSize; - CacheInfo->TBAATag = 0; - } SmallVector Worklist; Worklist.push_back(StartBB); @@ -986,8 +983,6 @@ // cached value to do more work but not miss the phi trans failure. NonLocalPointerInfo &NLPI = NonLocalPointerDeps[CacheKey]; NLPI.Pair = BBSkipFirstBlockPair(); - NLPI.Size = AliasAnalysis::UnknownSize; - NLPI.TBAATag = 0; continue; } @@ -1015,8 +1010,6 @@ // specific block queries) but we can't do the fastpath "return all // results from the set" Clear out the indicator for this. CacheInfo->Pair = BBSkipFirstBlockPair(); - CacheInfo->Size = AliasAnalysis::UnknownSize; - CacheInfo->TBAATag = 0; SkipFirstBlock = false; continue; @@ -1034,8 +1027,6 @@ // specific block queries) but we can't do the fastpath "return all // results from the set". Clear out the indicator for this. CacheInfo->Pair = BBSkipFirstBlockPair(); - CacheInfo->Size = AliasAnalysis::UnknownSize; - CacheInfo->TBAATag = 0; // If *nothing* works, mark the pointer as being clobbered by the first // instruction in this block. @@ -1252,8 +1243,6 @@ // The cache is not valid for any specific block anymore. NonLocalPointerDeps[P].Pair = BBSkipFirstBlockPair(); - NonLocalPointerDeps[P].Size = AliasAnalysis::UnknownSize; - NonLocalPointerDeps[P].TBAATag = 0; // Update any entries for RemInst to use the instruction after it. for (NonLocalDepInfo::iterator DI = NLPDI.begin(), DE = NLPDI.end(); From stoklund at 2pi.dk Wed Nov 10 18:52:44 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 11 Nov 2010 00:52:44 -0000 Subject: [llvm-commits] [llvm] r118754 - /llvm/trunk/lib/CodeGen/Spiller.cpp Message-ID: <20101111005244.E1E792A6C12C@llvm.org> Author: stoklund Date: Wed Nov 10 18:52:44 2010 New Revision: 118754 URL: http://llvm.org/viewvc/llvm-project?rev=118754&view=rev Log: Delete SplittingSpiller. It was not being used by anyone, and it is being superceded by SplitKit. Modified: llvm/trunk/lib/CodeGen/Spiller.cpp Modified: llvm/trunk/lib/CodeGen/Spiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=118754&r1=118753&r2=118754&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Spiller.cpp (original) +++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Nov 10 18:52:44 2010 @@ -29,7 +29,7 @@ using namespace llvm; namespace { - enum SpillerName { trivial, standard, splitting, inline_ }; + enum SpillerName { trivial, standard, inline_ }; } static cl::opt @@ -38,7 +38,6 @@ cl::Prefix, cl::values(clEnumVal(trivial, "trivial spiller"), clEnumVal(standard, "default spiller"), - clEnumVal(splitting, "splitting spiller"), clEnumValN(inline_, "inline", "inline spiller"), clEnumValEnd), cl::init(standard)); @@ -232,289 +231,6 @@ } // end anonymous namespace -namespace { - -/// When a call to spill is placed this spiller will first try to break the -/// interval up into its component values (one new interval per value). -/// If this fails, or if a call is placed to spill a previously split interval -/// then the spiller falls back on the standard spilling mechanism. -class SplittingSpiller : public StandardSpiller { -public: - SplittingSpiller(MachineFunctionPass &pass, MachineFunction &mf, - VirtRegMap &vrm) - : StandardSpiller(pass, mf, vrm) { - mri = &mf.getRegInfo(); - tii = mf.getTarget().getInstrInfo(); - tri = mf.getTarget().getRegisterInfo(); - } - - void spill(LiveInterval *li, - SmallVectorImpl &newIntervals, - const SmallVectorImpl &spillIs) { - if (worthTryingToSplit(li)) - tryVNISplit(li); - else - StandardSpiller::spill(li, newIntervals, spillIs); - } - -private: - - MachineRegisterInfo *mri; - const TargetInstrInfo *tii; - const TargetRegisterInfo *tri; - DenseSet alreadySplit; - - bool worthTryingToSplit(LiveInterval *li) const { - return (!alreadySplit.count(li) && li->getNumValNums() > 1); - } - - /// Try to break a LiveInterval into its component values. - std::vector tryVNISplit(LiveInterval *li) { - - DEBUG(dbgs() << "Trying VNI split of %reg" << *li << "\n"); - - std::vector added; - SmallVector vnis; - - std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis)); - - for (SmallVectorImpl::iterator vniItr = vnis.begin(), - vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) { - VNInfo *vni = *vniItr; - - // Skip unused VNIs. - if (vni->isUnused()) - continue; - - DEBUG(dbgs() << " Extracted Val #" << vni->id << " as "); - LiveInterval *splitInterval = extractVNI(li, vni); - - if (splitInterval != 0) { - DEBUG(dbgs() << *splitInterval << "\n"); - added.push_back(splitInterval); - alreadySplit.insert(splitInterval); - } else { - DEBUG(dbgs() << "0\n"); - } - } - - DEBUG(dbgs() << "Original LI: " << *li << "\n"); - - // If there original interval still contains some live ranges - // add it to added and alreadySplit. - if (!li->empty()) { - added.push_back(li); - alreadySplit.insert(li); - } - - return added; - } - - /// Extract the given value number from the interval. - LiveInterval* extractVNI(LiveInterval *li, VNInfo *vni) const { - assert((lis->getInstructionFromIndex(vni->def) != 0 || vni->isPHIDef()) && - "Def index not sane?"); - - // Create a new vreg and live interval, copy VNI ranges over. - const TargetRegisterClass *trc = mri->getRegClass(li->reg); - unsigned newVReg = mri->createVirtualRegister(trc); - vrm->grow(); - LiveInterval *newLI = &lis->getOrCreateInterval(newVReg); - VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator()); - - // Start by copying all live ranges in the VN to the new interval. - for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end(); - rItr != rEnd; ++rItr) { - if (rItr->valno == vni) { - newLI->addRange(LiveRange(rItr->start, rItr->end, newVNI)); - } - } - - // Erase the old VNI & ranges. - li->removeValNo(vni); - - // Collect all current uses of the register belonging to the given VNI. - // We'll use this to rename the register after we've dealt with the def. - std::set uses; - for (MachineRegisterInfo::use_iterator - useItr = mri->use_begin(li->reg), useEnd = mri->use_end(); - useItr != useEnd; ++useItr) { - uses.insert(&*useItr); - } - - // Process the def instruction for this VNI. - if (newVNI->isPHIDef()) { - // Insert a copy at the start of the MBB. The range proceeding the - // copy will be attached to the original LiveInterval. - MachineBasicBlock *defMBB = lis->getMBBFromIndex(newVNI->def); - MachineInstr *copyMI = BuildMI(*defMBB, defMBB->begin(), DebugLoc(), - tii->get(TargetOpcode::COPY), newVReg) - .addReg(li->reg, RegState::Kill); - SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI); - SlotIndex phiDefIdx = lis->getMBBStartIdx(defMBB); - assert(lis->getInstructionFromIndex(phiDefIdx) == 0 && - "PHI def index points at actual instruction."); - VNInfo *phiDefVNI = li->getNextValue(phiDefIdx, - 0, lis->getVNInfoAllocator()); - phiDefVNI->setIsPHIDef(true); - li->addRange(LiveRange(phiDefVNI->def, copyIdx.getDefIndex(), phiDefVNI)); - LiveRange *oldPHIDefRange = - newLI->getLiveRangeContaining(lis->getMBBStartIdx(defMBB)); - - // If the old phi def starts in the middle of the range chop it up. - if (oldPHIDefRange->start < lis->getMBBStartIdx(defMBB)) { - LiveRange oldPHIDefRange2(copyIdx.getDefIndex(), oldPHIDefRange->end, - oldPHIDefRange->valno); - oldPHIDefRange->end = lis->getMBBStartIdx(defMBB); - newLI->addRange(oldPHIDefRange2); - } else if (oldPHIDefRange->start == lis->getMBBStartIdx(defMBB)) { - // Otherwise if it's at the start of the range just trim it. - oldPHIDefRange->start = copyIdx.getDefIndex(); - } else { - assert(false && "PHI def range doesn't cover PHI def?"); - } - - newVNI->def = copyIdx.getDefIndex(); - newVNI->setCopy(copyMI); - newVNI->setIsPHIDef(false); // not a PHI def anymore. - } else { - // non-PHI def. Rename the def. If it's two-addr that means renaming the - // use and inserting a new copy too. - MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def); - // We'll rename this now, so we can remove it from uses. - uses.erase(defInst); - unsigned defOpIdx = defInst->findRegisterDefOperandIdx(li->reg); - bool isTwoAddr = defInst->isRegTiedToUseOperand(defOpIdx), - twoAddrUseIsUndef = false; - - for (unsigned i = 0; i < defInst->getNumOperands(); ++i) { - MachineOperand &mo = defInst->getOperand(i); - if (mo.isReg() && (mo.isDef() || isTwoAddr) && (mo.getReg()==li->reg)) { - mo.setReg(newVReg); - if (isTwoAddr && mo.isUse() && mo.isUndef()) - twoAddrUseIsUndef = true; - } - } - - SlotIndex defIdx = lis->getInstructionIndex(defInst); - newVNI->def = defIdx.getDefIndex(); - - if (isTwoAddr && !twoAddrUseIsUndef) { - MachineBasicBlock *defMBB = defInst->getParent(); - MachineInstr *copyMI = BuildMI(*defMBB, defInst, DebugLoc(), - tii->get(TargetOpcode::COPY), newVReg) - .addReg(li->reg, RegState::Kill); - SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI); - LiveRange *origUseRange = - li->getLiveRangeContaining(newVNI->def.getUseIndex()); - origUseRange->end = copyIdx.getDefIndex(); - VNInfo *copyVNI = newLI->getNextValue(copyIdx.getDefIndex(), copyMI, - lis->getVNInfoAllocator()); - LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI); - newLI->addRange(copyRange); - } - } - - for (std::set::iterator - usesItr = uses.begin(), usesEnd = uses.end(); - usesItr != usesEnd; ++usesItr) { - MachineInstr *useInst = *usesItr; - SlotIndex useIdx = lis->getInstructionIndex(useInst); - LiveRange *useRange = - newLI->getLiveRangeContaining(useIdx.getUseIndex()); - - // If this use doesn't belong to the new interval skip it. - if (useRange == 0) - continue; - - // This use doesn't belong to the VNI, skip it. - if (useRange->valno != newVNI) - continue; - - // Check if this instr is two address. - unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg); - bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx); - - // Rename uses (and defs for two-address instrs). - for (unsigned i = 0; i < useInst->getNumOperands(); ++i) { - MachineOperand &mo = useInst->getOperand(i); - if (mo.isReg() && (mo.isUse() || isTwoAddress) && - (mo.getReg() == li->reg)) { - mo.setReg(newVReg); - } - } - - // If this is a two address instruction we've got some extra work to do. - if (isTwoAddress) { - // We modified the def operand, so we need to copy back to the original - // reg. - MachineBasicBlock *useMBB = useInst->getParent(); - MachineBasicBlock::iterator useItr(useInst); - MachineInstr *copyMI = BuildMI(*useMBB, llvm::next(useItr), DebugLoc(), - tii->get(TargetOpcode::COPY), newVReg) - .addReg(li->reg, RegState::Kill); - SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI); - - // Change the old two-address defined range & vni to start at - // (and be defined by) the copy. - LiveRange *origDefRange = - li->getLiveRangeContaining(useIdx.getDefIndex()); - origDefRange->start = copyIdx.getDefIndex(); - origDefRange->valno->def = copyIdx.getDefIndex(); - origDefRange->valno->setCopy(copyMI); - - // Insert a new range & vni for the two-address-to-copy value. This - // will be attached to the new live interval. - VNInfo *copyVNI = - newLI->getNextValue(useIdx.getDefIndex(), 0, - lis->getVNInfoAllocator()); - LiveRange copyRange(useIdx.getDefIndex(),copyIdx.getDefIndex(),copyVNI); - newLI->addRange(copyRange); - } - } - - // Iterate over any PHI kills - we'll need to insert new copies for them. - for (LiveInterval::iterator LRI = newLI->begin(), LRE = newLI->end(); - LRI != LRE; ++LRI) { - if (LRI->valno != newVNI) - continue; - SlotIndex killIdx = LRI->end; - MachineBasicBlock *killMBB = lis->getMBBFromIndex(killIdx); - MachineInstr *copyMI = BuildMI(*killMBB, killMBB->getFirstTerminator(), - DebugLoc(), tii->get(TargetOpcode::COPY), - li->reg) - .addReg(newVReg, RegState::Kill); - SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI); - - // Save the current end. We may need it to add a new range if the - // current range runs of the end of the MBB. - SlotIndex newKillRangeEnd = LRI->end; - LRI->end = copyIdx.getDefIndex(); - - if (newKillRangeEnd != lis->getMBBEndIdx(killMBB)) { - assert(newKillRangeEnd > lis->getMBBEndIdx(killMBB) && - "PHI kill range doesn't reach kill-block end. Not sane."); - newLI->addRange(LiveRange(lis->getMBBEndIdx(killMBB), - newKillRangeEnd, newVNI)); - } - - VNInfo *newKillVNI = li->getNextValue(copyIdx.getDefIndex(), - copyMI, lis->getVNInfoAllocator()); - newKillVNI->setHasPHIKill(true); - li->addRange(LiveRange(copyIdx.getDefIndex(), - lis->getMBBEndIdx(killMBB), - newKillVNI)); - } - newVNI->setHasPHIKill(false); - - return newLI; - } - -}; - -} // end anonymous namespace - - namespace llvm { Spiller *createInlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, @@ -528,7 +244,6 @@ default: assert(0 && "unknown spiller"); case trivial: return new TrivialSpiller(pass, mf, vrm); case standard: return new StandardSpiller(pass, mf, vrm); - case splitting: return new SplittingSpiller(pass, mf, vrm); case inline_: return createInlineSpiller(pass, mf, vrm); } } From gohman at apple.com Wed Nov 10 19:03:30 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 01:03:30 -0000 Subject: [llvm-commits] [llvm] r118755 - /llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Message-ID: <20101111010330.B36332A6C12C@llvm.org> Author: djg Date: Wed Nov 10 19:03:30 2010 New Revision: 118755 URL: http://llvm.org/viewvc/llvm-project?rev=118755&view=rev Log: Add a testcase which demonstrates alias analysis pass precedence. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll?rev=118755&view=auto ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll (added) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Wed Nov 10 19:03:30 2010 @@ -0,0 +1,21 @@ +; RUN: opt -enable-tbaa -basicaa -tbaa -gvn -instcombine -S < %s | grep {ret i32 0} +; RUN: opt -enable-tbaa -tbaa -basicaa -gvn -instcombine -S < %s | grep {ret i32 1075000115} + +; According to the TBAA metadata the load and store don't alias. However, +; according to the actual code, they do. The order of the alias analysis +; passes should determine which of these takes precedence. + +target datalayout = "e-p:64:64:64" + +define i32 @trouble(i32* %x) nounwind ssp { +entry: + store i32 0, i32* %x, !tbaa !0 + %0 = bitcast i32* %x to float* + store float 0x4002666660000000, float* %0, !tbaa !3 + %tmp3 = load i32* %x, !tbaa !0 + ret i32 %tmp3 +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"simple"} +!3 = metadata !{metadata !"float", metadata !1} From grosbach at apple.com Wed Nov 10 19:09:40 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 01:09:40 -0000 Subject: [llvm-commits] [llvm] r118757 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101111010940.E3AB12A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 19:09:40 2010 New Revision: 118757 URL: http://llvm.org/viewvc/llvm-project?rev=118757&view=rev Log: ARM STRH encoding information. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118757&r1=118756&r2=118757&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Wed Nov 10 19:09:40 2010 @@ -202,6 +202,8 @@ Binary |= (Reg << 13); return Binary; } + uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const + { return 0; } uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { // {12-9} = reg // {8} = (U)nsigned (add == '1', sub == '0') Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118757&r1=118756&r2=118757&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 19:09:40 2010 @@ -735,14 +735,19 @@ string opc, string asm, list pattern> : I { - let Inst{4} = 1; - let Inst{5} = 1; // H bit - let Inst{6} = 0; // S bit - let Inst{7} = 1; - let Inst{20} = 0; // L bit - let Inst{21} = 0; // W bit - let Inst{24} = 1; // P bit + bits<14> addr; + bits<4> Rt; let Inst{27-25} = 0b000; + let Inst{24} = 1; // P bit + let Inst{23} = addr{8}; // U bit + let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm + let Inst{21} = 0; // W bit + let Inst{20} = 0; // L bit + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Rt; // Rt + let Inst{11-8} = addr{7-4}; // imm7_4/zero + let Inst{7-4} = 0b1011; + let Inst{3-0} = addr{3-0}; // imm3_0/Rm } class AXI3sth pattern> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118757&r1=118756&r2=118757&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 19:09:40 2010 @@ -442,6 +442,7 @@ // def addrmode3 : Operand, ComplexPattern { + string EncoderMethod = "getAddrMode3OpValue"; let PrintMethod = "printAddrMode3Operand"; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } @@ -1604,9 +1605,9 @@ // Store // Stores with truncate -def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, - IIC_iStore_bh_r, "strh", "\t$src, $addr", - [(truncstorei16 GPR:$src, addrmode3:$addr)]>; +def STRH : AI3sth<(outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, + IIC_iStore_bh_r, "strh", "\t$Rt, $addr", + [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; // Store doubleword let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118757&r1=118756&r2=118757&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Nov 10 19:09:40 2010 @@ -94,6 +94,9 @@ case ARM_AM::ib: return 3; } } + /// getAddrMode3OpValue - Return encoding for addrmode3 operands. + uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, @@ -306,7 +309,7 @@ // {4} = 0 // {6-5} = type // {11-7} = imm - int64_t Binary = Rm; + uint32_t Binary = Rm; Binary |= Rn << 13; Binary |= SBits << 5; Binary |= ShImm << 7; @@ -315,6 +318,28 @@ return Binary; } +uint32_t ARMMCCodeEmitter:: +getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { + // {13} 1 == imm8, 0 == Rm + // {12-9} Rn + // {8} isAdd + // {7-4} imm7_4/zero + // {3-0} imm3_0/Rm + const MCOperand &MO = MI.getOperand(OpIdx); + const MCOperand &MO1 = MI.getOperand(OpIdx+1); + const MCOperand &MO2 = MI.getOperand(OpIdx+2); + unsigned Rn = getARMRegisterNumbering(MO.getReg()); + unsigned Imm = MO2.getImm(); + bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; + bool isImm = MO1.getReg() == 0; + uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); + // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 + if (!isImm) + Imm8 = getARMRegisterNumbering(MO1.getReg()); + return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); +} + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand. uint32_t ARMMCCodeEmitter:: getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, From resistor at mac.com Wed Nov 10 19:19:24 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 11 Nov 2010 01:19:24 -0000 Subject: [llvm-commits] [llvm] r118759 - /llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Message-ID: <20101111011924.D9B8F2A6C12C@llvm.org> Author: resistor Date: Wed Nov 10 19:19:24 2010 New Revision: 118759 URL: http://llvm.org/viewvc/llvm-project?rev=118759&view=rev Log: Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction. Not yet used. Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=118759&r1=118758&r2=118759&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Wed Nov 10 19:19:24 2010 @@ -230,6 +230,10 @@ } } + if (R->getValue("PostEncoderMethod")) + Case += " Value = " + + R->getValueAsString("PostEncoderMethod") + "(MI, Value);\n"; + std::vector &InstList = CaseMap[Case]; InstList.push_back(InstName); } From grosbach at apple.com Wed Nov 10 19:27:41 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 01:27:41 -0000 Subject: [llvm-commits] [llvm] r118761 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20101111012741.B5CD02A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 19:27:41 2010 New Revision: 118761 URL: http://llvm.org/viewvc/llvm-project?rev=118761&view=rev Log: Fix encoding of Ra register for ARM smla* instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118761&r1=118760&r2=118761&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 19:27:41 2010 @@ -2533,7 +2533,7 @@ multiclass AI_smla { - def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd), + def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, @@ -2541,35 +2541,35 @@ (sext_inreg GPR:$Rm, i16))))]>, Requires<[IsARM, HasV5TE]>; - def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd), + def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16), (sra GPR:$Rm, (i32 16)))))]>, Requires<[IsARM, HasV5TE]>; - def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd), + def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), (sext_inreg GPR:$Rm, i16))))]>, Requires<[IsARM, HasV5TE]>; - def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd), + def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), (sra GPR:$Rm, (i32 16)))))]>, Requires<[IsARM, HasV5TE]>; - def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd), + def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, (sext_inreg GPR:$Rm, i16)), (i32 16))))]>, Requires<[IsARM, HasV5TE]>; - def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd), + def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, From evan.cheng at apple.com Wed Nov 10 19:52:09 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 10 Nov 2010 17:52:09 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> Message-ID: On Nov 10, 2010, at 1:08 PM, Jakob Stoklund Olesen wrote: > > On Nov 10, 2010, at 12:17 PM, Evan Cheng wrote: > >> Nice. One question though: >> >> >> On Nov 10, 2010, at 11:31 AM, Jakob Stoklund Olesen wrote: >> >>> >>> + // Make sure that openli is properly extended from Idx to the new copy. >>> + // FIXME: This shouldn't be necessary for remats. >>> + openli_.addSimpleRange(Idx, VNI->def, ParentVNI); >>> >> >> Why the "fixme"? Are you restricting remat to instructions with no register operands? > > No, I allow register operands as much as isTriviallyReMaterializable does, but I never extend live ranges of operands to do so. I require all operands to be live with the same value at the remat location. This check is implemented in LiveRangeEdit::allUsesAvailableAt(). Ah ok. We can potentially allow more remat by extending live ranges with more analysis. But that's later. > > I think that isTriviallyReMaterializable is actually too conservative: > > // Only allow one virtual-register def, and that in the first operand. > if (MO.isDef() != (i == 0)) > return false; > > // For the def, it should be the only def of that register. > if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() || > MRI.isLiveIn(Reg))) > return false; > > // Don't allow any virtual-register uses. Rematting an instruction with > // virtual register uses would length the live ranges of the uses, which > // is not necessarily a good idea, certainly not "trivial". > if (MO.isUse()) > return false; > > Given that all used virtual registers have the same value, there is no need to restrict to only one use, or single-def. > > I wonder if 'isTriviallyReMaterializable' means that the instruction can be rematted anywhere without further checks? If so, I should perhaps be using the basic TID::isRematerializable() flag instead? Right. It's only meant for the existing brain dead remat. > > > Anyway, the FIXME is an other matter entirely. When the splitter inserts copies, it needs to make sure that the COPY source register can reach the COPY instruction. When it remats the value instead of issuing a COPY, that shouldn't be necessary - in fact, the source register live range should be shortened since it is not needed for the remat. > > The live range extension is still necessary because the splitter is computing the live range of the last register as the complement of all the other new registers. This will go away after I figure out how to truncate live ranges after rematerialization. Ok, thanks. Evan > > /jakob > From grosbach at apple.com Wed Nov 10 19:55:59 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 01:55:59 -0000 Subject: [llvm-commits] [llvm] r118767 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td Message-ID: <20101111015559.B154C2A6C12C@llvm.org> Author: grosbach Date: Wed Nov 10 19:55:59 2010 New Revision: 118767 URL: http://llvm.org/viewvc/llvm-project?rev=118767&view=rev Log: Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118767&r1=118766&r2=118767&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 19:55:59 2010 @@ -670,14 +670,19 @@ string opc, string asm, list pattern> : I { - let Inst{4} = 1; - let Inst{5} = 1; // H bit - let Inst{6} = 1; // S bit - let Inst{7} = 1; - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{24} = 1; // P bit + bits<14> addr; + bits<4> Rt; let Inst{27-25} = 0b000; + let Inst{24} = 1; // P bit + let Inst{23} = addr{8}; // U bit + let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm + let Inst{21} = 0; // W bit + let Inst{20} = 1; // L bit + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Rt; // Rt + let Inst{11-8} = addr{7-4}; // imm7_4/zero + let Inst{7-4} = 0b1111; + let Inst{3-0} = addr{3-0}; // imm3_0/Rm } class AXI3ldsh pattern> @@ -793,14 +798,19 @@ string opc, string asm, string cstr, list pattern> : I { - let Inst{4} = 1; - let Inst{5} = 1; // H bit - let Inst{6} = 1; // S bit - let Inst{7} = 1; - let Inst{20} = 1; // L bit - let Inst{21} = 1; // W bit - let Inst{24} = 1; // P bit + bits<14> addr; + bits<4> Rt; let Inst{27-25} = 0b000; + let Inst{24} = 1; // P bit + let Inst{23} = addr{8}; // U bit + let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm + let Inst{21} = 1; // W bit + let Inst{20} = 1; // L bit + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Rt; // Rt + let Inst{11-8} = addr{7-4}; // imm7_4/zero + let Inst{7-4} = 0b1111; + let Inst{3-0} = addr{3-0}; // imm3_0/Rm } class AI3ldsbpr pattern> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118767&r1=118766&r2=118767&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 19:55:59 2010 @@ -1516,45 +1516,45 @@ []>, Requires<[IsARM, HasV5TE]>; // Indexed loads -def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), +def LDR_PRE : AI2ldwpr<(outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru, - "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>; + "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, - "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>; +def LDR_POST : AI2ldwpo<(outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru, + "ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; -def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), +def LDRH_PRE : AI3ldhpr<(outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, - "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; + "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, - "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; +def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, + "ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; -def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), +def LDRB_PRE : AI2ldbpr<(outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru, - "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; + "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, - "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; +def LDRB_POST : AI2ldbpo<(outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, + "ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; -def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), +def LDRSH_PRE : AI3ldshpr<(outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, - "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; + "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, - "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; +def LDRSH_POST: AI3ldshpo<(outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, + "ldrsh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; -def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), +def LDRSB_PRE : AI3ldsbpr<(outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, - "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; + "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru, - "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; +def LDRSB_POST: AI3ldsbpo<(outs GPR:$Rt, GPR:$Rn_wb), + (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru, + "ldrsb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; // For disassembly only def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), From dalej at apple.com Wed Nov 10 19:59:08 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 11 Nov 2010 01:59:08 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r118768 - in /llvm-gcc-4.2/trunk/gcc: c-opts.c calls.c common.opt config/arm/darwin.h config/darwin.h cp/decl.c cp/init.c dwarf2out.c function.c opts.c tree-eh.c tree-ssa-math-opts.c Message-ID: <20101111015909.089E42A6C12C@llvm.org> Author: johannes Date: Wed Nov 10 19:59:08 2010 New Revision: 118768 URL: http://llvm.org/viewvc/llvm-project?rev=118768&view=rev Log: Revert 118750, which broke FrontendC/2008-04-08-NoExceptions.c. As I understand the point of the patch this test should continue to work. Modified: llvm-gcc-4.2/trunk/gcc/c-opts.c llvm-gcc-4.2/trunk/gcc/calls.c llvm-gcc-4.2/trunk/gcc/common.opt llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/cp/decl.c llvm-gcc-4.2/trunk/gcc/cp/init.c llvm-gcc-4.2/trunk/gcc/dwarf2out.c llvm-gcc-4.2/trunk/gcc/function.c llvm-gcc-4.2/trunk/gcc/opts.c llvm-gcc-4.2/trunk/gcc/tree-eh.c llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c Modified: llvm-gcc-4.2/trunk/gcc/c-opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-opts.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-opts.c Wed Nov 10 19:59:08 2010 @@ -237,10 +237,7 @@ #endif /* APPLE LOCAL end -Wfour-char-constants */ - /* LLVM LOCAL begin 6635085 */ - if (c_dialect_cxx() && flag_exceptions < 0) - flag_exceptions = 1; - /* LLVM LOCAL end 6635085 */ + flag_exceptions = c_dialect_cxx (); /* LLVM local begin One Definition Rule */ #ifdef ENABLE_LLVM flag_odr = c_dialect_cxx (); @@ -1156,10 +1153,7 @@ /* Default to ObjC sjlj exception handling if NeXT runtime. */ if (flag_objc_sjlj_exceptions < 0) flag_objc_sjlj_exceptions = flag_next_runtime; - /* LLVM LOCAL begin 6635085 */ - if ((flag_objc_exceptions && !flag_objc_sjlj_exceptions) - || flag_exceptions < 0) - /* LLVM LOCAL end 6635085 */ + if (flag_objc_exceptions && !flag_objc_sjlj_exceptions) flag_exceptions = 1; /* -Wextra implies -Wsign-compare, -Wmissing-field-initializers and Modified: llvm-gcc-4.2/trunk/gcc/calls.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/calls.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/calls.c (original) +++ llvm-gcc-4.2/trunk/gcc/calls.c Wed Nov 10 19:59:08 2010 @@ -2384,8 +2384,6 @@ with stack pointer depressed. Also do the adjustments before a throwing call, otherwise exception handling can fail; PR 19225. */ - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions > 0); if (pending_stack_adjust >= 32 || (pending_stack_adjust > 0 && (flags & (ECF_MAY_BE_ALLOCA | ECF_SP_DEPRESSED))) Modified: llvm-gcc-4.2/trunk/gcc/common.opt URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/common.opt?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/common.opt (original) +++ llvm-gcc-4.2/trunk/gcc/common.opt Wed Nov 10 19:59:08 2010 @@ -519,7 +519,7 @@ Do not suppress C++ class debug information. fexceptions -Common Report Var(flag_exceptions) Init(-1) +Common Report Var(flag_exceptions) Enable exception handling ; APPLE LOCAL begin optimization pragmas 3124235/3420242 Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Wed Nov 10 19:59:08 2010 @@ -382,9 +382,7 @@ #define OBJC_TARGET_FLAG_OBJC_ABI \ do { \ - /* LLVM LOCAL 6635085 */ \ - if (flag_objc_abi == -1 \ - && flag_exceptions == -1) \ + if (flag_objc_abi == -1) \ flag_objc_abi = 2; \ if (flag_objc_legacy_dispatch == -1) \ flag_objc_legacy_dispatch = 1; \ Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Wed Nov 10 19:59:08 2010 @@ -863,10 +863,7 @@ flag_objc_zerocost_exceptions = 1; \ if (flag_objc_zerocost_exceptions) \ { \ - /* APPLE LOCAL begin 6635085 */ \ - if (flag_exceptions == -1) \ - flag_exceptions = 1; \ - /* APPLE LOCAL end 6635085 */ \ + flag_exceptions = 1; \ flag_objc_sjlj_exceptions = 0; \ } \ /* APPLE LOCAL end radar 5023725 */ \ Modified: llvm-gcc-4.2/trunk/gcc/cp/decl.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/decl.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/cp/decl.c (original) +++ llvm-gcc-4.2/trunk/gcc/cp/decl.c Wed Nov 10 19:59:08 2010 @@ -1104,8 +1104,6 @@ all declarations, including the definition and an explicit specialization, of that function shall have an exception-specification with the same set of type-ids. */ - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); if ((pedantic || ! DECL_IN_SYSTEM_HEADER (old_decl)) && ! DECL_IS_BUILTIN (old_decl) && flag_exceptions @@ -3395,8 +3393,7 @@ init_class_processing (); init_rtti_processing (); - /* LLVM LOCAL 6635085 */ - if (flag_exceptions > 0) + if (flag_exceptions) init_exception_processing (); if (! supports_one_only ()) @@ -11739,8 +11736,6 @@ static bool use_eh_spec_block (tree fn) { - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); return (flag_exceptions && flag_enforce_eh_specs && !processing_template_decl && TYPE_RAISES_EXCEPTIONS (TREE_TYPE (fn)) Modified: llvm-gcc-4.2/trunk/gcc/cp/init.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/cp/init.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/cp/init.c (original) +++ llvm-gcc-4.2/trunk/gcc/cp/init.c Wed Nov 10 19:59:08 2010 @@ -1957,8 +1957,6 @@ unambiguous matching deallocation function can be found, propagating the exception does not cause the object's memory to be freed. */ - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); if (flag_exceptions && ! use_java_new) { enum tree_code dcode = array_p ? VEC_DELETE_EXPR : DELETE_EXPR; @@ -2497,8 +2495,6 @@ /* Protect the entire array initialization so that we can destroy the partially constructed array if an exception is thrown. But don't do this if we're assigning. */ - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); if (flag_exceptions && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (type) && from_array != 2) { @@ -2633,8 +2629,6 @@ } /* Make sure to cleanup any partially constructed elements. */ - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); if (flag_exceptions && TYPE_HAS_NONTRIVIAL_DESTRUCTOR (type) && from_array != 2) { Modified: llvm-gcc-4.2/trunk/gcc/dwarf2out.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/dwarf2out.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/dwarf2out.c (original) +++ llvm-gcc-4.2/trunk/gcc/dwarf2out.c Wed Nov 10 19:59:08 2010 @@ -123,8 +123,7 @@ #ifdef DWARF2_UNWIND_INFO || (DWARF2_UNWIND_INFO && (flag_unwind_tables - /* LLVM LOCAL 6635085 */ - || (flag_exceptions > 0 && ! USING_SJLJ_EXCEPTIONS))) + || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))) #endif ); } @@ -2208,8 +2207,6 @@ discarded. Example where this matters: a primary function template in C++ requires EH information, but an explicit specialization doesn't. */ - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); if (TARGET_USES_WEAK_UNWIND_INFO && ! flag_asynchronous_unwind_tables /* APPLE LOCAL begin for-fsf-4_4 5480287 */ \ @@ -2383,8 +2380,6 @@ floor_log2 (for_eh ? PTR_SIZE : DWARF2_ADDR_SIZE)); ASM_OUTPUT_LABEL (asm_out_file, l2); - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); /* Loop through all of the FDE's. */ for (i = 0; i < fde_table_in_use; i++) { @@ -2669,8 +2664,7 @@ #ifndef TARGET_UNWIND_INFO /* Output another copy for the unwinder. */ - /* LLVM LOCAL 6635085 */ - if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions > 0)) + if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions)) output_call_frame_info (1); #endif } Modified: llvm-gcc-4.2/trunk/gcc/function.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/function.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/function.c (original) +++ llvm-gcc-4.2/trunk/gcc/function.c Wed Nov 10 19:59:08 2010 @@ -4475,8 +4475,6 @@ /* Output the label for the actual return from the function. */ emit_label (return_label); - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions > 0); if (USING_SJLJ_EXCEPTIONS) { /* Let except.c know where it should emit the call to unregister Modified: llvm-gcc-4.2/trunk/gcc/opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/opts.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/opts.c Wed Nov 10 19:59:08 2010 @@ -736,8 +736,7 @@ generating unwind info. If flag_exceptions is turned on we need to turn off the partitioning optimization. */ - /* LLVM LOCAL 6635085 */ - if (flag_exceptions > 0 && flag_reorder_blocks_and_partition) + if (flag_exceptions && flag_reorder_blocks_and_partition) { inform ("-freorder-blocks-and-partition does not work with exceptions"); Modified: llvm-gcc-4.2/trunk/gcc/tree-eh.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-eh.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-eh.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-eh.c Wed Nov 10 19:59:08 2010 @@ -1355,11 +1355,6 @@ struct leh_state this_state; int ndests; - /* LLVM LOCAL begin 6635085 */ - /* if ( ! flag_exceptions) - fatal_error("try/catch constructs require -fexceptions"); */ - /* LLVM LOCAL end 6635085 */ - /* Process the try block. */ memset (&this_tf, 0, sizeof (this_tf)); Modified: llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c?rev=118768&r1=118767&r2=118768&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-ssa-math-opts.c Wed Nov 10 19:59:08 2010 @@ -259,8 +259,6 @@ if (occ_child->children) compute_merit (occ_child); - /* LLVM LOCAL 6635085 */ - gcc_assert(flag_exceptions >= 0); if (flag_exceptions) bb = single_noncomplex_succ (dom); else From stoklund at 2pi.dk Wed Nov 10 20:19:14 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 10 Nov 2010 18:19:14 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> Message-ID: <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> On Nov 10, 2010, at 5:52 PM, Evan Cheng wrote: > > On Nov 10, 2010, at 1:08 PM, Jakob Stoklund Olesen wrote: > >> >> On Nov 10, 2010, at 12:17 PM, Evan Cheng wrote: >> >>> Are you restricting remat to instructions with no register operands? >> >> No, I allow register operands as much as isTriviallyReMaterializable does, but I never extend live ranges of operands to do so. I require all operands to be live with the same value at the remat location. This check is implemented in LiveRangeEdit::allUsesAvailableAt(). > > Ah ok. We can potentially allow more remat by extending live ranges with more analysis. But that's later. Yes, that is tricky. The extended live range must be useful for more than one remat. Otherwise register pressure stays the same. >> I wonder if 'isTriviallyReMaterializable' means that the instruction can be rematted anywhere without further checks? If so, I should perhaps be using the basic TID::isRematerializable() flag instead? > > Right. It's only meant for the existing brain dead remat. I see. X86InstrInfo::isReallyTriviallyReMaterializable in particular has many arbitrary restrictions. I'll look into something more generic. I would be useful to be able to remat loads that have been hoisted by early optimizations. Is there any way AliasAnalysis can be rigged to provide more information than AA->pointsToConstantMemory? -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101110/ce8c9994/attachment.bin From evan.cheng at apple.com Wed Nov 10 20:38:48 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 10 Nov 2010 18:38:48 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> Message-ID: <1D46230B-F666-4B99-9C72-7D17BB709EEA@apple.com> On Nov 10, 2010, at 6:19 PM, Jakob Stoklund Olesen wrote: > > On Nov 10, 2010, at 5:52 PM, Evan Cheng wrote: > >> >> On Nov 10, 2010, at 1:08 PM, Jakob Stoklund Olesen wrote: >> >>> >>> On Nov 10, 2010, at 12:17 PM, Evan Cheng wrote: >>> >>>> Are you restricting remat to instructions with no register operands? >>> >>> No, I allow register operands as much as isTriviallyReMaterializable does, but I never extend live ranges of operands to do so. I require all operands to be live with the same value at the remat location. This check is implemented in LiveRangeEdit::allUsesAvailableAt(). >> >> Ah ok. We can potentially allow more remat by extending live ranges with more analysis. But that's later. > > Yes, that is tricky. The extended live range must be useful for more than one remat. Otherwise register pressure stays the same. > >>> I wonder if 'isTriviallyReMaterializable' means that the instruction can be rematted anywhere without further checks? If so, I should perhaps be using the basic TID::isRematerializable() flag instead? >> >> Right. It's only meant for the existing brain dead remat. > > I see. X86InstrInfo::isReallyTriviallyReMaterializable in particular has many arbitrary restrictions. I'll look into something more generic. > > I would be useful to be able to remat loads that have been hoisted by early optimizations. Is there any way AliasAnalysis can be rigged to provide more information than AA->pointsToConstantMemory? Dan? Evan > > From rafael.espindola at gmail.com Wed Nov 10 20:36:20 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Wed, 10 Nov 2010 21:36:20 -0500 Subject: [llvm-commits] [PATCH] MCFragments Clean Up In-Reply-To: References: Message-ID: On 10 November 2010 17:31, David Meyer wrote: > Hi Dan, > I'm not sure what you mean by vtable construction cost. Do you mean the > additional memory to store the vptr??I can't deny that a switch-based > implementation?uses a little less memory and is probably slightly faster > (one less memory read & a closer jump on dispatch). However, I think the > resulting code could be significantly cleaner and more extensible. > As you can probably tell, I've been working on adding native-client > instruction bundling to the MC assembler. The modifications are almost > finished. Unfortunately, it has been quite an unpleasant experience. > One of the things I did was to add a new fragment type which can store > multiple instructions (usually about 3), each with its own fixups and > (possibly) each needing relaxation separately. The existing relaxation and > lowering mechanism assumes that only MCInstFragment needs relaxation and > lowering. I changed that when I implemented uleb128 with expressions, but it is not pretty. One of the things I was planning to do with your refactoring was add a base class for all classes that are relaxed. > I had to copy & paste & modify most of the relaxation code in > order to make it relax my new fragment type. If there were instead virtual > methods NeedRelaxation() and PerformRelaxation() and LowerFragment() on > fragments, this would not have been necessary. > I also needed to control the creation of fragments. With bundling enabled, > the creation of a fragment sometimes needs to trigger the substitution for a > different type of fragment. Unfortunately, the creation of fragments (e.g. > "new MCAlignFragment(...)") is sprinkled all over the MCObjectStreamer > subclasses instead of being private to MCAssembler. This made the required > changes messy and spread out. > I'm curious as to why the the assembler doesn't keep fragments as private > data. Instead, they get passed and manipulated all over the place. Fragments > even get passed directly to the TargetAsmBackend! The number of places in > the code that "knows" about a fragments is alarming. Yes, I haven't put a lot of thought on how to improve this, but it does look like that areas of the code that just need to append data are handling fragments just because that is the alternative they have for when the streamer is not available. The ELFObjectWritter for example would probably be more than happy with any API that lets it push data to the end of a given section. > I think that ideally, fragment creation could have been hidden behind > functions like: > // Emits into MCInstFragment or into the current MCDataFragment > MCAssembler::EmitInstruction(MCSectionData *Parent, const MCInst &Inst); > MCAssembler::EmitValueToAlignment(...); > MCAssember::EmitCodeAlignment(...); > MCAssembler::EmitOrg(...); > MCAssembler::EmitDwarf(...); This looks a lot like the MCStreamer class. Maybe it should just be available in more places? > I'd like to talk more about this. I'd like to get the bundling feature clean > enough to be added to mainstream LLVM MC. The changes are mostly innocuous, > but little things are getting in the way of making the implementation > compact. Unfortunately, I'm under intense pressure to get this stuff working > a week ago (in our local branch). I can't focus on refactoring at the > moment. > When I'm finished, I'll send you a ping. Thanks a lot! > Thanks, > ??David M Cheers, Rafael From geek4civic at gmail.com Wed Nov 10 21:04:04 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 11 Nov 2010 12:04:04 +0900 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: <877hgl3vkm.fsf@telefonica.net> References: <87d3qezzud.fsf@telefonica.net> <877hgl3vkm.fsf@telefonica.net> Message-ID: Good morning, Oscar. I have tried your advices, thank you, but I gave up. :( I am convinced there might be no way for CMake to expand whitespace-separated-STRING to COMMAND without quote. At now, I have two-way patches. * 0001-llvm-LLVM_LIT_ARGS.patch * 0001-clang-LLVM_LIT_ARGS.patch I got rid of separate_arguments(UNIX_COMMAND) but still I take separate_arguments() to split whitespace-separated-STRING. It simply must substitute space to semicolon. * 0001-llvm-LLVM_LIT_ARGS-semicolon.patch * 0001-clang-LLVM_LIT_ARGS-semicolon.patch These patches might be suitable to CMake's philosophy. LLVM_LIT_ARGS should have semicolon-separated list. (eg. "-s;-v;--no-progress-bar") I wonder it might be unusual way against shell/make's sense. ps. I saw '-s -v' was expanded to '-s\ -v'. ...Takumi -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-llvm-LLVM_LIT_ARGS.patch Type: application/octet-stream Size: 2571 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/e1b3c2ba/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-clang-LLVM_LIT_ARGS.patch Type: application/octet-stream Size: 2573 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/e1b3c2ba/attachment-0001.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-llvm-LLVM_LIT_ARGS-semicolon.patch Type: application/octet-stream Size: 2342 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/e1b3c2ba/attachment-0002.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-clang-LLVM_LIT_ARGS-semicolon.patch Type: application/octet-stream Size: 2399 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/e1b3c2ba/attachment-0003.obj From rafael.espindola at gmail.com Wed Nov 10 21:40:25 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 11 Nov 2010 03:40:25 -0000 Subject: [llvm-commits] [llvm] r118774 - in /llvm/trunk/lib: MC/ELFObjectWriter.cpp Target/SystemZ/SystemZMCAsmInfo.cpp Target/X86/X86MCAsmInfo.cpp Target/XCore/XCoreTargetObjectFile.cpp Message-ID: <20101111034025.6D3162A6C12C@llvm.org> Author: rafael Date: Wed Nov 10 21:40:25 2010 New Revision: 118774 URL: http://llvm.org/viewvc/llvm-project?rev=118774&view=rev Log: Remove some explicit arguments to getELFSection. This is a leftover from the removal of isExplicit. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118774&r1=118773&r2=118774&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Nov 10 21:40:25 2010 @@ -1137,7 +1137,7 @@ // We construct .shstrtab, .symtab and .strtab in this order to match gnu as. const MCSectionELF *ShstrtabSection = Ctx.getELFSection(".shstrtab", ELF::SHT_STRTAB, 0, - SectionKind::getReadOnly(), false); + SectionKind::getReadOnly()); MCSectionData &ShstrtabSD = Asm.getOrCreateSectionData(*ShstrtabSection); ShstrtabSD.setAlignment(1); ShstrtabIndex = Asm.size(); @@ -1162,7 +1162,7 @@ const MCSection *StrtabSection; StrtabSection = Ctx.getELFSection(".strtab", ELF::SHT_STRTAB, 0, - SectionKind::getReadOnly(), false); + SectionKind::getReadOnly()); MCSectionData &StrtabSD = Asm.getOrCreateSectionData(*StrtabSection); StrtabSD.setAlignment(1); StringTableIndex = Asm.size(); @@ -1264,8 +1264,7 @@ const MCSectionELF *InfoSection; SymtabSection = Asm.getContext().getELFSection(".symtab", ELF::SHT_SYMTAB, 0, - SectionKind::getReadOnly(), - false); + SectionKind::getReadOnly()); sh_link = SectionIndexMap.lookup(SymtabSection); assert(sh_link && ".symtab not found"); @@ -1275,8 +1274,7 @@ InfoSection = Asm.getContext().getELFSection(SectionName, ELF::SHT_PROGBITS, 0, - SectionKind::getReadOnly(), - false); + SectionKind::getReadOnly()); sh_info = SectionIndexMap.lookup(InfoSection); break; } Modified: llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp?rev=118774&r1=118773&r2=118774&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp Wed Nov 10 21:40:25 2010 @@ -25,5 +25,5 @@ const MCSection *SystemZMCAsmInfo:: getNonexecutableStackSection(MCContext &Ctx) const{ return Ctx.getELFSection(".note.GNU-stack", MCSectionELF::SHT_PROGBITS, - 0, SectionKind::getMetadata(), false); + 0, SectionKind::getMetadata()); } Modified: llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp?rev=118774&r1=118773&r2=118774&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCAsmInfo.cpp Wed Nov 10 21:40:25 2010 @@ -99,7 +99,7 @@ const MCSection *X86ELFMCAsmInfo:: getNonexecutableStackSection(MCContext &Ctx) const { return Ctx.getELFSection(".note.GNU-stack", MCSectionELF::SHT_PROGBITS, - 0, SectionKind::getMetadata(), false); + 0, SectionKind::getMetadata()); } X86MCAsmInfoCOFF::X86MCAsmInfoCOFF(const Triple &Triple) { Modified: llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp?rev=118774&r1=118773&r2=118774&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetObjectFile.cpp Wed Nov 10 21:40:25 2010 @@ -22,28 +22,28 @@ Ctx.getELFSection(".dp.data", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE | MCSectionELF::XCORE_SHF_DP_SECTION, - SectionKind::getDataRel(), false); + SectionKind::getDataRel()); BSSSection = Ctx.getELFSection(".dp.bss", MCSectionELF::SHT_NOBITS, MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE | MCSectionELF::XCORE_SHF_DP_SECTION, - SectionKind::getBSS(), false); + SectionKind::getBSS()); MergeableConst4Section = Ctx.getELFSection(".cp.rodata.cst4", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE | MCSectionELF::XCORE_SHF_CP_SECTION, - SectionKind::getMergeableConst4(), false); + SectionKind::getMergeableConst4()); MergeableConst8Section = Ctx.getELFSection(".cp.rodata.cst8", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE | MCSectionELF::XCORE_SHF_CP_SECTION, - SectionKind::getMergeableConst8(), false); + SectionKind::getMergeableConst8()); MergeableConst16Section = Ctx.getELFSection(".cp.rodata.cst16", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_MERGE | MCSectionELF::XCORE_SHF_CP_SECTION, - SectionKind::getMergeableConst16(), false); + SectionKind::getMergeableConst16()); // TLS globals are lowered in the backend to arrays indexed by the current // thread id. After lowering they require no special handling by the linker @@ -55,7 +55,7 @@ Ctx.getELFSection(".cp.rodata", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_ALLOC | MCSectionELF::XCORE_SHF_CP_SECTION, - SectionKind::getReadOnlyWithRel(), false); + SectionKind::getReadOnlyWithRel()); // Dynamic linking is not supported. Data with relocations is placed in the // same section as data without relocations. From ofv at wanadoo.es Wed Nov 10 21:57:13 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Thu, 11 Nov 2010 04:57:13 +0100 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: (NAKAMURA Takumi's message of "Thu, 11 Nov 2010 12:04:04 +0900") References: <87d3qezzud.fsf@telefonica.net> <877hgl3vkm.fsf@telefonica.net> Message-ID: <87tyjo342u.fsf@telefonica.net> NAKAMURA Takumi writes: > Good morning, Oscar. > > I have tried your advices, thank you, but I gave up. :( > I am convinced there might be no way for CMake to expand > whitespace-separated-STRING to COMMAND without quote. > > At now, I have two-way patches. > > * 0001-llvm-LLVM_LIT_ARGS.patch > * 0001-clang-LLVM_LIT_ARGS.patch > > I got rid of separate_arguments(UNIX_COMMAND) but still I take > separate_arguments() to split whitespace-separated-STRING. It simply > must substitute space to semicolon. > > * 0001-llvm-LLVM_LIT_ARGS-semicolon.patch > * 0001-clang-LLVM_LIT_ARGS-semicolon.patch > > These patches might be suitable to CMake's philosophy. LLVM_LIT_ARGS > should have semicolon-separated list. > (eg. "-s;-v;--no-progress-bar") > I wonder it might be unusual way against shell/make's sense. > > ps. I saw '-s -v' was expanded to '-s\ -v'. I see. AFAIK CMake's evaluation model is loosely inspired by Tcl's and it brings in its own incarnation of quoting hell. Okay, commit the version that uses the usual shell syntax (-DLLVM_LIT_ARGS="-s -v") Those parameters are for lit, not for cmake, and hence it is reasonable to use the same syntax that one would use if lit were invoked directly from the shell. Thanks for trying so hard. From gohman at apple.com Wed Nov 10 22:05:20 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 10 Nov 2010 20:05:20 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: <1D46230B-F666-4B99-9C72-7D17BB709EEA@apple.com> References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> <1D46230B-F666-4B99-9C72-7D17BB709EEA@apple.com> Message-ID: On Nov 10, 2010, at 6:38 PM, Evan Cheng wrote: > >>>> I wonder if 'isTriviallyReMaterializable' means that the >>>> instruction can be rematted anywhere without further checks? If >>>> so, I should perhaps be using the basic TID::isRematerializable() >>>> flag instead? >>> >>> Right. It's only meant for the existing brain dead remat. >> >> I see. X86InstrInfo::isReallyTriviallyReMaterializable in >> particular has many arbitrary restrictions. I'll look into >> something more generic. >> >> I would be useful to be able to remat loads that have been hoisted >> by early optimizations. Is there any way AliasAnalysis can be >> rigged to provide more information than AA->pointsToConstantMemory? Yes. The Values used with pointsToConstantMemory can also be used with normal AliasAnalysis::alias queries. There's no memdep or other higher level abstraction for MachineInstrs currently though. Dan From geek4civic at gmail.com Wed Nov 10 22:09:35 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 11 Nov 2010 04:09:35 -0000 Subject: [llvm-commits] [llvm] r118776 - in /llvm/trunk: CMakeLists.txt docs/CMake.html test/CMakeLists.txt Message-ID: <20101111040935.B4F502A6C12C@llvm.org> Author: chapuni Date: Wed Nov 10 22:09:35 2010 New Revision: 118776 URL: http://llvm.org/viewvc/llvm-project?rev=118776&view=rev Log: CMake: Add the new option "LLVM_LIT_ARGS". Defaults: if (MSVC OR XCODE): "-sv --no-progress-bar" else: "-sv" Modified: llvm/trunk/CMakeLists.txt llvm/trunk/docs/CMake.html llvm/trunk/test/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=118776&r1=118775&r2=118776&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Wed Nov 10 22:09:35 2010 @@ -89,6 +89,13 @@ set(LLVM_TARGET_ARCH "host" CACHE STRING "Set target to use for LLVM JIT or use \"host\" for automatic detection.") +set(LIT_ARGS_DEFAULT "-sv") +if (MSVC OR XCODE) + set(LIT_ARGS_DEFAULT "${LIT_ARGS_DEFAULT} --no-progress-bar") +endif() +set(LLVM_LIT_ARGS "${LIT_ARGS_DEFAULT}" + CACHE STRING "Default options for lit") + option(LLVM_ENABLE_THREADS "Use threads if available." ON) if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" ) Modified: llvm/trunk/docs/CMake.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=118776&r1=118775&r2=118776&view=diff ============================================================================== --- llvm/trunk/docs/CMake.html (original) +++ llvm/trunk/docs/CMake.html Wed Nov 10 22:09:35 2010 @@ -325,6 +325,13 @@
    Full path to a native TableGen executable (usually named tblgen). This is intented for cross-compiling: if the user sets this variable, no native TableGen will be created.
    + +
    LLVM_LIT_ARGS:STRING
    +
    Arguments given to lit. + make check and make clang-test are affected. + By default, "-sv --no-progress-bar" + on Visual C++ and Xcode, + "-sv" on others.
    Modified: llvm/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=118776&r1=118775&r2=118776&view=diff ============================================================================== --- llvm/trunk/test/CMakeLists.txt (original) +++ llvm/trunk/test/CMakeLists.txt Wed Nov 10 22:09:35 2010 @@ -24,6 +24,9 @@ include(FindPythonInterp) if(PYTHONINTERP_FOUND) + set(LIT_ARGS "${LLVM_LIT_ARGS}") + separate_arguments(LIT_ARGS) + get_directory_property(DEFINITIONS COMPILE_DEFINITIONS) foreach(DEF ${DEFINITIONS}) set(DEFS "${DEFS} -D${DEF}") @@ -78,7 +81,7 @@ ${LLVM_SOURCE_DIR}/utils/lit/lit.py --param llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg --param llvm_unit_site_config=${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg - -sv + ${LIT_ARGS} ${CMAKE_CURRENT_BINARY_DIR} DEPENDS COMMENT "Running LLVM regression tests") From geek4civic at gmail.com Wed Nov 10 22:13:12 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 11 Nov 2010 13:13:12 +0900 Subject: [llvm-commits] [Review request] CMake: Add the new option "LLVM_LIT_ARGS" In-Reply-To: <87tyjo342u.fsf@telefonica.net> References: <87d3qezzud.fsf@telefonica.net> <877hgl3vkm.fsf@telefonica.net> <87tyjo342u.fsf@telefonica.net> Message-ID: 2010/11/11 ?scar Fuentes : >> At now, I have two-way patches. >> >> * 0001-llvm-LLVM_LIT_ARGS.patch >> * 0001-clang-LLVM_LIT_ARGS.patch >> >> I got rid of separate_arguments(UNIX_COMMAND) but still I take >> separate_arguments() to split whitespace-separated-STRING. It simply >> must substitute space to semicolon. > Okay, commit the version that uses the usual shell syntax > (-DLLVM_LIT_ARGS="-s -v") Those parameters are for lit, not for cmake, > and hence it is reasonable to use the same syntax that one would use if > lit were invoked directly from the shell. Committed in r118776 and r118777, thank you to advice me! From sabre at nondot.org Thu Nov 11 01:16:18 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 07:16:18 -0000 Subject: [llvm-commits] [www-pubs] r118779 - in /www-pubs/trunk: 2010-07-CAV-LazyAnnot.html 2010-07-CAV-LazyAnnot.pdf pubs.js Message-ID: <20101111071618.419B32A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 01:16:18 2010 New Revision: 118779 URL: http://llvm.org/viewvc/llvm-project?rev=118779&view=rev Log: add a paper nuno pointed me at Added: www-pubs/trunk/2010-07-CAV-LazyAnnot.html www-pubs/trunk/2010-07-CAV-LazyAnnot.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-07-CAV-LazyAnnot.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-07-CAV-LazyAnnot.html?rev=118779&view=auto ============================================================================== --- www-pubs/trunk/2010-07-CAV-LazyAnnot.html (added) +++ www-pubs/trunk/2010-07-CAV-LazyAnnot.html Thu Nov 11 01:16:18 2010 @@ -0,0 +1,69 @@ + + + + + + Lazy Annotation for Program Testing and Verification + + + +
    + Lazy Annotation for Program Testing and Verification +
    +
    + Kenneth McMillan +
    + +

    Abstract:

    +
    +

    +We describe an interpolant-based approach to test generation and model checking for sequential programs. The method generates Floyd/Hoare style annotations of the program on demand, as a result of failure to achieve goals, in a manner analogous to conflict clause learning in a DPLL style SAT solver. +

    +
    + +

    Published:

    +
    + "Lazy Annotation for Program Testing and Verification"
    + Kenneth McMillan
    +In Proceedings of Computer Aided Verification, +Edinburgh, UK, July 15-19, 2010. +
    + +

    Download:

    +

    Paper:

    + + +

    BibTeX Entry:

    +
    + at incollection {springerlink:10.1007/978-3-642-14295-6_10,
+   author = {McMillan, Kenneth},
+   affiliation = {Cadence Berkeley Labs},
+   title = {Lazy Annotation for Program Testing and Verification},
+   booktitle = {Computer Aided Verification},
+   series = {Lecture Notes in Computer Science},
+   editor = {Touili, Tayssir and Cook, Byron and Jackson, Paul},
+   publisher = {Springer Berlin / Heidelberg},
+   isbn = {},
+   pages = {104-118},
+   volume = {6174},
+   url = {http://dx.doi.org/10.1007/978-3-642-14295-6_10},
+   note = {10.1007/978-3-642-14295-6_10},
+   abstract = {We describe an interpolant-based approach to test generation and model checking for sequential programs. The method generates Floyd/Hoare style annotations of the program on demand, as a result of failure to achieve goals, in a manner analogous to conflict clause learning in a DPLL style SAT solver.},
+   year = {2010}
+}
+
    + + + +
    + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-07-CAV-LazyAnnot.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-07-CAV-LazyAnnot.pdf?rev=118779&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-07-CAV-LazyAnnot.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=118779&r1=118778&r2=118779&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Thu Nov 11 01:16:18 2010 @@ -15,6 +15,18 @@ author: "André Tavares, Fernando Magno Pereira, Mariza Bigonha and Roberto Bigonha", month: 9, year: 2010}, + + { + url: "2010-07-CAV-LazyAnnot.html", + title: "Lazy Annotation for Program Testing and Verification", + published: "In Proceedings of Computer Aided Verification (CAV 2010)", + author: "Kenneth McMillan", + location: "Edinburgh, UK", + month: 7, + year: 2010 + }, + + {url: "2010-06-ISCA-Relax.html", title: "Relax: An Architectural Framework for Software Recovery of Hardware Faults", published: "ISCA '10: International Symposium on Computer Architecture", From sabre at nondot.org Thu Nov 11 01:49:29 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 07:49:29 -0000 Subject: [llvm-commits] [www-pubs] r118781 - in /www-pubs/trunk: 2010-09-ESORICS-FixOverflows.html 2010-09-ESORICS-FixOverflows.pdf pubs.js Message-ID: <20101111074929.DDB132A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 01:49:29 2010 New Revision: 118781 URL: http://llvm.org/viewvc/llvm-project?rev=118781&view=rev Log: add another paper Added: www-pubs/trunk/2010-09-ESORICS-FixOverflows.html www-pubs/trunk/2010-09-ESORICS-FixOverflows.pdf Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-09-ESORICS-FixOverflows.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-09-ESORICS-FixOverflows.html?rev=118781&view=auto ============================================================================== --- www-pubs/trunk/2010-09-ESORICS-FixOverflows.html (added) +++ www-pubs/trunk/2010-09-ESORICS-FixOverflows.html Thu Nov 11 01:49:29 2010 @@ -0,0 +1,49 @@ + + + + + + IntPatch: Automatically Fix Integer-Overflow-to-Buffer-Overflow Vulnerability at Compile-Time + + + +
    + IntPatch: Automatically Fix Integer-Overflow-to-Buffer-Overflow Vulnerability at Compile-Time +
    +
    + Chao Zhang, Tielei Wang, Tao Wei, Yu Chen, and Wei Zou +
    + +

    Abstract:

    +
    +

    +The Integer-Overflow-to-Buffer-Overflow (IO2BO) vulnerability is an underestimated threat. Automatically identifying and fixing this kind of vulnerability are critical for software security. In this paper, we present the design and implementation of IntPatch, a compiler extension for automatically fixing IO2BO vulnerabilities in C/C++ programs at compile time. IntPatch utilizes classic type theory and dataflow analysis framework to identify potential IO2BO vulnerabilities, and then instruments programs with runtime checks. Moreover, IntPatch provides an interface for programmers to facilitate checking integer overflows. We evaluate IntPatch on a number of real-world applications. It has caught all 46 previously known IO2BO vulnerabilities in our test suite and found 21 new bugs. Applications patched by IntPatch have a negligible runtime performance loss which is averaging about 1%. +

    +
    + +

    Published:

    +
    + "IntPatch: Automatically Fix Integer-Overflow-to-Buffer-Overflow Vulnerability at Compile-Time"
    + Chao Zhang, Tielei Wang, Tao Wei, Yu Chen, and Wei Zou
    +Proc. of the 15th European Symposium on Research in Computer Security (ESORICS 2010), +Athen, Greece, Sep. 2010 +
    + +

    Download:

    +

    Paper:

    + + + + +
    + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-09-ESORICS-FixOverflows.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-09-ESORICS-FixOverflows.pdf?rev=118781&view=auto ============================================================================== Binary files www-pubs/trunk/2010-09-ESORICS-FixOverflows.pdf (added) and www-pubs/trunk/2010-09-ESORICS-FixOverflows.pdf Thu Nov 11 01:49:29 2010 differ Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=118781&r1=118780&r2=118781&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Thu Nov 11 01:49:29 2010 @@ -8,6 +8,15 @@ author: "David A. Terei and Manuel M. T. Chakravarty", month: 9, year: 2010}, + { + url: "2010-09-ESORICS-FixOverflows.html", + title: "IntPatch: Automatically Fix Integer-Overflow-to-Buffer-Overflow Vulnerability at Compile-Time", + published: "Proc. of the 15th European Symposium on Research in Computer Security (ESORICS 2010)", + location: "Athen, Greece", + author: "Chao Zhang, Tielei Wang, Tao Wei, Yu Chen, and Wei Zou", + month: 9, + year: 2010 + }, {url: "2010-08-SBLP-SSI.html", title: "Efficient SSI Conversion", published: "Brazilian Symposium on Programming Languages 2010", From nicholas at mxc.ca Thu Nov 11 03:28:21 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 11 Nov 2010 01:28:21 -0800 Subject: [llvm-commits] [llvm] r118608 - /llvm/trunk/lib/Target/README.txt In-Reply-To: <20101109193728.40D3A2A6C12C@llvm.org> References: <20101109193728.40D3A2A6C12C@llvm.org> Message-ID: <4CDBB735.3020306@mxc.ca> Hi Chris, why did this go into README.txt? It looks like the problem is that we aren't emitting a vtable for c28, making this another testcase for PR3100? Chris Lattner wrote: > Author: lattner > Date: Tue Nov 9 13:37:28 2010 > New Revision: 118608 > > URL: http://llvm.org/viewvc/llvm-project?rev=118608&view=rev > Log: > add a case we fail to devirt. > > Modified: > llvm/trunk/lib/Target/README.txt > > Modified: llvm/trunk/lib/Target/README.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=118608&r1=118607&r2=118608&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/README.txt (original) > +++ llvm/trunk/lib/Target/README.txt Tue Nov 9 13:37:28 2010 > @@ -1963,3 +1963,23 @@ > ret i32 %b > } > //===---------------------------------------------------------------------===// > + > +clang -O3 fails to devirtualize this virtual inheritance case: (GCC PR45875) > + > +struct c1 {}; > +struct c10 : c1{ > + virtual void foo (); > +}; > +struct c11 : c10, c1{ > + virtual void f6 (); > +}; > +struct c28 : virtual c11{ > + void f6 (); > +}; > +void check_c28 () { > + c28 obj; > + c11 *ptr =&obj; > + ptr->f6 (); > +} > + > +//===---------------------------------------------------------------------===// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Thu Nov 11 10:20:28 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 16:20:28 -0000 Subject: [llvm-commits] [llvm] r118787 - /llvm/trunk/lib/Transforms/Scalar/Sink.cpp Message-ID: <20101111162028.E21922A6C12C@llvm.org> Author: djg Date: Thu Nov 11 10:20:28 2010 New Revision: 118787 URL: http://llvm.org/viewvc/llvm-project?rev=118787&view=rev Log: It's safe to sink some instructions which are not safe to speculatively execute. Make Sink's predicate more precise. Modified: llvm/trunk/lib/Transforms/Scalar/Sink.cpp Modified: llvm/trunk/lib/Transforms/Scalar/Sink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Sink.cpp?rev=118787&r1=118786&r2=118787&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Sink.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Sink.cpp Thu Nov 11 10:20:28 2010 @@ -169,7 +169,10 @@ return false; } - return Inst->isSafeToSpeculativelyExecute(); + if (isa(Inst) || isa(Inst)) + return false; + + return true; } /// SinkInstruction - Determine whether it is safe to sink the specified machine From gohman at apple.com Thu Nov 11 10:21:48 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 16:21:48 -0000 Subject: [llvm-commits] [llvm] r118788 - in /llvm/trunk: lib/Transforms/Scalar/Sink.cpp test/Analysis/TypeBasedAliasAnalysis/sink.ll Message-ID: <20101111162148.1B7A22A6C12C@llvm.org> Author: djg Date: Thu Nov 11 10:21:47 2010 New Revision: 118788 URL: http://llvm.org/viewvc/llvm-project?rev=118788&view=rev Log: Make Sink tbaa-aware. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll Modified: llvm/trunk/lib/Transforms/Scalar/Sink.cpp Modified: llvm/trunk/lib/Transforms/Scalar/Sink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Sink.cpp?rev=118788&r1=118787&r2=118788&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Sink.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Sink.cpp Thu Nov 11 10:21:47 2010 @@ -15,6 +15,7 @@ #define DEBUG_TYPE "sink" #include "llvm/Transforms/Scalar.h" #include "llvm/IntrinsicInst.h" +#include "llvm/LLVMContext.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -158,9 +159,11 @@ Value *Ptr = L->getPointerOperand(); uint64_t Size = AA->getTypeStoreSize(L->getType()); + const MDNode *TBAAInfo = L->getMetadata(LLVMContext::MD_tbaa); + AliasAnalysis::Location Loc(Ptr, Size, TBAAInfo); for (SmallPtrSet::iterator I = Stores.begin(), E = Stores.end(); I != E; ++I) - if (AA->getModRefInfo(*I, Ptr, Size) & AliasAnalysis::Mod) + if (AA->getModRefInfo(*I, Loc) & AliasAnalysis::Mod) return false; } Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll?rev=118788&view=auto ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll (added) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll Thu Nov 11 10:21:47 2010 @@ -0,0 +1,20 @@ +; RUN: opt -tbaa -enable-tbaa -sink -S < %s | FileCheck %s + +; CHECK: a: +; CHECK: %f = load float* %p, !tbaa !2 +; CHECK: store float %f, float* %q + +define void @foo(float* %p, i1 %c, float* %q, float* %r) { + %f = load float* %p, !tbaa !0 + store float 0.0, float* %r, !tbaa !1 + br i1 %c, label %a, label %b +a: + store float %f, float* %q + br label %b +b: + ret void +} + +!0 = metadata !{metadata !"A", metadata !2} +!1 = metadata !{metadata !"B", metadata !2} +!2 = metadata !{metadata !"test"} From gohman at apple.com Thu Nov 11 10:24:49 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 16:24:49 -0000 Subject: [llvm-commits] [llvm] r118789 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/X86/memmove-0.ll test/CodeGen/X86/memmove-1.ll test/CodeGen/X86/memmove-2.ll test/CodeGen/X86/memmove-3.ll Message-ID: <20101111162449.F071E2A6C12C@llvm.org> Author: djg Date: Thu Nov 11 10:24:49 2010 New Revision: 118789 URL: http://llvm.org/viewvc/llvm-project?rev=118789&view=rev Log: Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this. Removed: llvm/trunk/test/CodeGen/X86/memmove-0.ll llvm/trunk/test/CodeGen/X86/memmove-1.ll llvm/trunk/test/CodeGen/X86/memmove-2.ll llvm/trunk/test/CodeGen/X86/memmove-3.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118789&r1=118788&r2=118789&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Nov 11 10:24:49 2010 @@ -4086,20 +4086,6 @@ SDValue Op3 = getValue(I.getArgOperand(2)); unsigned Align = cast(I.getArgOperand(3))->getZExtValue(); bool isVol = cast(I.getArgOperand(4))->getZExtValue(); - - // If the source and destination are known to not be aliases, we can - // lower memmove as memcpy. - uint64_t Size = -1ULL; - if (ConstantSDNode *C = dyn_cast(Op3)) - Size = C->getZExtValue(); - if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == - AliasAnalysis::NoAlias) { - DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, - false, MachinePointerInfo(I.getArgOperand(0)), - MachinePointerInfo(I.getArgOperand(1)))); - return 0; - } - DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, MachinePointerInfo(I.getArgOperand(0)), MachinePointerInfo(I.getArgOperand(1)))); Removed: llvm/trunk/test/CodeGen/X86/memmove-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-0.ll?rev=118788&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/memmove-0.ll (original) +++ llvm/trunk/test/CodeGen/X86/memmove-0.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {calll memcpy} - -declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a) - -define void @foo(i8* noalias %d, i8* noalias %s, i64 %l) -{ - call void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 1) - ret void -} Removed: llvm/trunk/test/CodeGen/X86/memmove-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-1.ll?rev=118788&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/memmove-1.ll (original) +++ llvm/trunk/test/CodeGen/X86/memmove-1.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {calll memmove} - -declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a) - -define void @foo(i8* %d, i8* %s, i64 %l) -{ - call void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 1) - ret void -} Removed: llvm/trunk/test/CodeGen/X86/memmove-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-2.ll?rev=118788&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/memmove-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/memmove-2.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | not grep call - -declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a) - -define void @foo(i8* noalias %d, i8* noalias %s) -{ - call void @llvm.memmove.i64(i8* %d, i8* %s, i64 32, i32 1) - ret void -} Removed: llvm/trunk/test/CodeGen/X86/memmove-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-3.ll?rev=118788&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/memmove-3.ll (original) +++ llvm/trunk/test/CodeGen/X86/memmove-3.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {calll memmove} - -declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a) - -define void @foo(i8* %d, i8* %s) -{ - call void @llvm.memmove.i64(i8* %d, i8* %s, i64 32, i32 1) - ret void -} From gohman at apple.com Thu Nov 11 10:32:17 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 16:32:17 -0000 Subject: [llvm-commits] [llvm] r118790 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <20101111163217.AC0E42A6C12C@llvm.org> Author: djg Date: Thu Nov 11 10:32:17 2010 New Revision: 118790 URL: http://llvm.org/viewvc/llvm-project?rev=118790&view=rev Log: Include ImmutablePass passes in -debug-pass=Arguments. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=118790&r1=118789&r2=118790&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Thu Nov 11 10:32:17 2010 @@ -675,6 +675,12 @@ return; dbgs() << "Pass Arguments: "; + for (SmallVector::const_iterator I = + ImmutablePasses.begin(), E = ImmutablePasses.end(); I != E; ++I) + if (const PassInfo *PI = + PassRegistry::getPassRegistry()->getPassInfo((*I)->getPassID())) + if (!PI->isAnalysisGroup()) + dbgs() << " -" << PI->getPassArgument(); for (SmallVector::const_iterator I = PassManagers.begin(), E = PassManagers.end(); I != E; ++I) (*I)->dumpPassArguments(); From gohman at apple.com Thu Nov 11 10:37:38 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 16:37:38 -0000 Subject: [llvm-commits] [llvm] r118792 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101111163739.048032A6C12C@llvm.org> Author: djg Date: Thu Nov 11 10:37:38 2010 New Revision: 118792 URL: http://llvm.org/viewvc/llvm-project?rev=118792&view=rev Log: Add brief doxygen comments for AliasResult enum values. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118792&r1=118791&r2=118792&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Nov 11 10:37:38 2010 @@ -129,7 +129,11 @@ /// See docs/AliasAnalysis.html for more information on the specific meanings /// of these values. /// - enum AliasResult { NoAlias = 0, MayAlias = 1, MustAlias = 2 }; + enum AliasResult { + NoAlias = 0, ///< No dependencies. + MayAlias = 1, ///< Anything goes. + MustAlias = 2 ///< Pointers are equal. + }; /// alias - The main low level interface to the alias analysis implementation. /// Returns an AliasResult indicating whether the two pointers are aliased to From rafael.espindola at gmail.com Thu Nov 11 10:48:11 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 11 Nov 2010 16:48:11 -0000 Subject: [llvm-commits] [llvm] r118793 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp test/MC/ELF/weakref-reloc.s Message-ID: <20101111164811.CD37D2A6C12C@llvm.org> Author: rafael Date: Thu Nov 11 10:48:11 2010 New Revision: 118793 URL: http://llvm.org/viewvc/llvm-project?rev=118793&view=rev Log: Fix the symbol index of weak references. Also make RecordRelocation a bit easier to read by having const references to the symbol, aliased symbol and renamed symbol. Added: llvm/trunk/test/MC/ELF/weakref-reloc.s Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118793&r1=118792&r2=118793&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Nov 11 10:48:11 2010 @@ -669,16 +669,16 @@ int64_t Addend = 0; int Index = 0; int64_t Value = Target.getConstant(); - const MCSymbol *Symbol = 0; - const MCSymbol *Renamed = 0; + const MCSymbol &Symbol = Target.getSymA()->getSymbol(); + const MCSymbol &ASymbol = AliasedSymbol(Symbol); + const MCSymbol *RenamedP = Renames.lookup(&Symbol); + if (!RenamedP) + RenamedP = &ASymbol; + const MCSymbol &Renamed = *RenamedP; bool IsPCRel = isFixupKindX86PCRel(Fixup.getKind()); if (!Target.isAbsolute()) { - Symbol = &AliasedSymbol(Target.getSymA()->getSymbol()); - Renamed = Renames.lookup(Symbol); - if (!Renamed) - Renamed = &Target.getSymA()->getSymbol(); - MCSymbolData &SD = Asm.getSymbolData(*Symbol); + MCSymbolData &SD = Asm.getSymbolData(Symbol); MCFragment *F = SD.getFragment(); if (const MCSymbolRefExpr *RefB = Target.getSymB()) { @@ -695,15 +695,6 @@ Value += b - a; } - // Check that this case has already been fully resolved before we get - // here. - if (Symbol->isDefined() && !SD.isExternal() && - IsPCRel && - &Fragment->getParent()->getSection() == &Symbol->getSection()) { - llvm_unreachable("We don't need a relocation in this case."); - return; - } - bool RelocOnSymbol = ShouldRelocOnSymbol(SD, Target, *Fragment); if (!RelocOnSymbol) { Index = F->getParent()->getOrdinal(); @@ -712,11 +703,10 @@ // Offset of the symbol in the section Value += Layout.getSymbolAddress(&SD) - Layout.getSectionAddress(FSD); } else { - UsedInReloc.insert(Renamed); - MCSymbolData &RenamedSD = Asm.getSymbolData(*Renamed); - if (RenamedSD.getFlags() & ELF_Other_Weakref) { - WeakrefUsedInReloc.insert(Symbol); - } + if (Asm.getSymbolData(Symbol).getFlags() & ELF_Other_Weakref) + WeakrefUsedInReloc.insert(&Renamed); + else + UsedInReloc.insert(&Renamed); Index = -1; } Addend = Value; @@ -864,7 +854,7 @@ ERE.Index = Index; ERE.Type = Type; - ERE.Symbol = Renamed; + ERE.Symbol = &Renamed; ERE.r_offset = Layout.getFragmentOffset(Fragment) + Fixup.getOffset(); Added: llvm/trunk/test/MC/ELF/weakref-reloc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/weakref-reloc.s?rev=118793&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/weakref-reloc.s (added) +++ llvm/trunk/test/MC/ELF/weakref-reloc.s Thu Nov 11 10:48:11 2010 @@ -0,0 +1,49 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that the relocations point to the correct symbols. We used to get the +// symbol index wrong for weakrefs when creating _GLOBAL_OFFSET_TABLE_. + + .weakref bar,foo + call zed at PLT + call bar + +// CHECK: # Symbol 0x00000004 +// CHECK-NEXT: (('st_name', 0x00000009) # '_GLOBAL_OFFSET_TABLE_' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000005 +// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' +// CHECK-NEXT: ('st_bind', 0x00000002) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000006 +// CHECK-NEXT: (('st_name', 0x00000005) # 'zed' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), + +// CHECK: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000001) +// CHECK-NEXT: ('r_sym', 0x00000006) +// CHECK-NEXT: ('r_type', 0x00000004) +// CHECK-NEXT: ('r_addend', 0xfffffffc) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 0x00000001 +// CHECK-NEXT: (('r_offset', 0x00000006) +// CHECK-NEXT: ('r_sym', 0x00000005) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0xfffffffc) +// CHECK-NEXT: ), From grosbach at apple.com Thu Nov 11 10:55:29 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 16:55:29 -0000 Subject: [llvm-commits] [llvm] r118794 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrFormats.td ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101111165529.B80232A6C12C@llvm.org> Author: grosbach Date: Thu Nov 11 10:55:29 2010 New Revision: 118794 URL: http://llvm.org/viewvc/llvm-project?rev=118794&view=rev Log: Encoding for ARM LDRSH_POST. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118794&r1=118793&r2=118794&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 11 10:55:29 2010 @@ -202,6 +202,8 @@ Binary |= (Reg << 13); return Binary; } + uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) + const { return 0;} uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const { return 0; } uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118794&r1=118793&r2=118794&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 11 10:55:29 2010 @@ -886,14 +886,20 @@ string opc, string asm, string cstr, list pattern> : I { - let Inst{4} = 1; - let Inst{5} = 1; // H bit - let Inst{6} = 1; // S bit - let Inst{7} = 1; - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{24} = 0; // P bit + bits<10> offset; + bits<4> Rt; + bits<4> Rn; let Inst{27-25} = 0b000; + let Inst{24} = 0; // P bit + let Inst{23} = offset{8}; // U bit + let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm + let Inst{21} = 0; // W bit + let Inst{20} = 1; // L bit + let Inst{19-16} = Rn; // Rn + let Inst{15-12} = Rt; // Rt + let Inst{11-8} = offset{7-4}; // imm7_4/zero + let Inst{7-4} = 0b1111; + let Inst{3-0} = offset{3-0}; // imm3_0/Rm } class AI3ldsbpo pattern> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118794&r1=118793&r2=118794&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 11 10:55:29 2010 @@ -450,6 +450,7 @@ def am3offset : Operand, ComplexPattern { + string EncoderMethod = "getAddrMode3OffsetOpValue"; let PrintMethod = "printAddrMode3OffsetOperand"; let MIOperandInfo = (ops GPR, i32imm); } Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118794&r1=118793&r2=118794&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 11 10:55:29 2010 @@ -94,6 +94,10 @@ case ARM_AM::ib: return 3; } } + /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. + uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; + /// getAddrMode3OpValue - Return encoding for addrmode3 operands. uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; @@ -319,6 +323,25 @@ } uint32_t ARMMCCodeEmitter:: +getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { + // {9} 1 == imm8, 0 == Rm + // {8} isAdd + // {7-4} imm7_4/zero + // {3-0} imm3_0/Rm + const MCOperand &MO = MI.getOperand(OpIdx); + const MCOperand &MO1 = MI.getOperand(OpIdx+1); + unsigned Imm = MO1.getImm(); + bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; + bool isImm = MO.getReg() == 0; + uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); + // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 + if (!isImm) + Imm8 = getARMRegisterNumbering(MO.getReg()); + return Imm8 | (isAdd << 8) | (isImm << 9); +} + +uint32_t ARMMCCodeEmitter:: getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { // {13} 1 == imm8, 0 == Rm From sabre at nondot.org Thu Nov 11 11:13:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 09:13:45 -0800 Subject: [llvm-commits] [llvm] r118608 - /llvm/trunk/lib/Target/README.txt In-Reply-To: <4CDBB735.3020306@mxc.ca> References: <20101109193728.40D3A2A6C12C@llvm.org> <4CDBB735.3020306@mxc.ca> Message-ID: <83F85C95-A422-4BC4-ACBC-9C0FDC7A93FF@nondot.org> On Nov 11, 2010, at 1:28 AM, Nick Lewycky wrote: > Hi Chris, why did this go into README.txt? It looks like the problem is that we aren't emitting a vtable for c28, making this another testcase for PR3100? Our general approach is to put miscellaneous missed optimizations into README files. IMO, only correctness and serious performance issues (e.g. regressions) should be in bugzilla. -Chris > > Chris Lattner wrote: >> Author: lattner >> Date: Tue Nov 9 13:37:28 2010 >> New Revision: 118608 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118608&view=rev >> Log: >> add a case we fail to devirt. >> >> Modified: >> llvm/trunk/lib/Target/README.txt >> >> Modified: llvm/trunk/lib/Target/README.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=118608&r1=118607&r2=118608&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/README.txt (original) >> +++ llvm/trunk/lib/Target/README.txt Tue Nov 9 13:37:28 2010 >> @@ -1963,3 +1963,23 @@ >> ret i32 %b >> } >> //===---------------------------------------------------------------------===// >> + >> +clang -O3 fails to devirtualize this virtual inheritance case: (GCC PR45875) >> + >> +struct c1 {}; >> +struct c10 : c1{ >> + virtual void foo (); >> +}; >> +struct c11 : c10, c1{ >> + virtual void f6 (); >> +}; >> +struct c28 : virtual c11{ >> + void f6 (); >> +}; >> +void check_c28 () { >> + c28 obj; >> + c11 *ptr =&obj; >> + ptr->f6 (); >> +} >> + >> +//===---------------------------------------------------------------------===// >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> From sabre at nondot.org Thu Nov 11 11:17:56 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 17:17:56 -0000 Subject: [llvm-commits] [llvm] r118797 - /llvm/trunk/lib/Target/README.txt Message-ID: <20101111171757.060EF2A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 11:17:56 2010 New Revision: 118797 URL: http://llvm.org/viewvc/llvm-project?rev=118797&view=rev Log: add pr# Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=118797&r1=118796&r2=118797&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Thu Nov 11 11:17:56 2010 @@ -1965,6 +1965,7 @@ //===---------------------------------------------------------------------===// clang -O3 fails to devirtualize this virtual inheritance case: (GCC PR45875) +Looks related to PR3100 struct c1 {}; struct c10 : c1{ From stoklund at 2pi.dk Thu Nov 11 11:20:39 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 11 Nov 2010 09:20:39 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> <1D46230B-F666-4B99-9C72-7D17BB709EEA@apple.com> Message-ID: <3B47EB07-D1A9-491E-A0A3-493125D0DE6F@2pi.dk> On Nov 10, 2010, at 8:05 PM, Dan Gohman wrote: > > > On Nov 10, 2010, at 6:38 PM, Evan Cheng wrote: >> >>>>> I wonder if 'isTriviallyReMaterializable' means that the instruction can be rematted anywhere without further checks? If so, I should perhaps be using the basic TID::isRematerializable() flag instead? >>>> >>>> Right. It's only meant for the existing brain dead remat. >>> >>> I see. X86InstrInfo::isReallyTriviallyReMaterializable in particular has many arbitrary restrictions. I'll look into something more generic. >>> >>> I would be useful to be able to remat loads that have been hoisted by early optimizations. Is there any way AliasAnalysis can be rigged to provide more information than AA->pointsToConstantMemory? > > Yes. The Values used with pointsToConstantMemory can also be used with normal AliasAnalysis::alias queries. There's no memdep or other higher level abstraction for MachineInstrs currently though. So because we are dealing with MachineInstrs, AliasAnalysis can't tell me if I can move a load, right? Maybe a conservative approach could look at basic blocks. I want to ask: Can I move a load from block A to block B, where A dominates B. AA could conservatively assume that I want to move the load from the top of A to the bottom of B. If all my MachineBasicBlocks are properly mapped to BasicBlocks, AA::canBasicBlockModify() is all I need, I think. /jakob From rafael.espindola at gmail.com Thu Nov 11 11:24:43 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 11 Nov 2010 17:24:43 -0000 Subject: [llvm-commits] [llvm] r118798 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp test/MC/ELF/weakref-plt.s Message-ID: <20101111172443.933372A6C12C@llvm.org> Author: rafael Date: Thu Nov 11 11:24:43 2010 New Revision: 118798 URL: http://llvm.org/viewvc/llvm-project?rev=118798&view=rev Log: Make AliasedSymbol able to handle MCTargetExpr. They can get here if a weakref is used with a VariantKind. Added: llvm/trunk/test/MC/ELF/weakref-plt.s Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118798&r1=118797&r2=118798&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Nov 11 11:24:43 2010 @@ -470,10 +470,23 @@ const MCSymbol *S = &Symbol; while (S->isVariable()) { const MCExpr *Value = S->getVariableValue(); - if (Value->getKind() != MCExpr::SymbolRef) + MCExpr::ExprKind Kind = Value->getKind(); + switch (Kind) { + case MCExpr::SymbolRef: { + const MCSymbolRefExpr *Ref = static_cast(Value); + S = &Ref->getSymbol(); + break; + } + case MCExpr::Target: { + const MCTargetExpr *TExp = static_cast(Value); + MCValue Res; + TExp->EvaluateAsRelocatableImpl(Res, NULL); + S = &Res.getSymA()->getSymbol(); + break; + } + default: return *S; - const MCSymbolRefExpr *Ref = static_cast(Value); - S = &Ref->getSymbol(); + } } return *S; } Added: llvm/trunk/test/MC/ELF/weakref-plt.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/weakref-plt.s?rev=118798&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/weakref-plt.s (added) +++ llvm/trunk/test/MC/ELF/weakref-plt.s Thu Nov 11 11:24:43 2010 @@ -0,0 +1,8 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + + .weakref bar,foo + call bar at PLT + +// CHECK: # Symbol 0x00000005 +// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' +// CHECK-NEXT: ('st_bind', 0x00000002) From gohman at apple.com Thu Nov 11 11:33:39 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 17:33:39 -0000 Subject: [llvm-commits] [llvm] r118799 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20101111173339.78D282A6C12C@llvm.org> Author: djg Date: Thu Nov 11 11:33:39 2010 New Revision: 118799 URL: http://llvm.org/viewvc/llvm-project?rev=118799&view=rev Log: Add comments. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118799&r1=118798&r2=118799&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Nov 11 11:33:39 2010 @@ -16,11 +16,21 @@ // which automatically provides functionality for the entire suite of client // APIs. // -// This API represents memory as a (Pointer, Size) pair. The Pointer component -// specifies the base memory address of the region, the Size specifies how large -// of an area is being queried, or UnknownSize if the size is not known. -// Pointers that point to two completely different objects in memory never -// alias, regardless of the value of the Size component. +// This API identifies memory regions with the Location class. The pointer +// component specifies the base memory address of the region. The Size specifies +// the maximum size (in address units) of the memory region, or UnknownSize if +// the size is not known. The TBAA tag identifies the "type" of the memory +// reference; see the TypeBasedAliasAnalysis class for details. +// +// Some non-obvious details include: +// - Pointers that point to two completely different objects in memory never +// alias, regardless of the value of the Size component. +// - NoAlias doesn't imply inequal pointers. The most obvious example of this +// is two pointers to constant memory. Even if they are equal, constant +// memory is never stored to, so there will never be any dependencies. +// In this and other situations, the pointers may be both NoAlias and +// MustAlias at the same time. The current API can only return one result, +// though this is rarely a problem in practice. // //===----------------------------------------------------------------------===// From atrick at apple.com Thu Nov 11 11:46:29 2010 From: atrick at apple.com (Andrew Trick) Date: Thu, 11 Nov 2010 17:46:29 -0000 Subject: [llvm-commits] [llvm] r118800 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp Message-ID: <20101111174629.AEAD52A6C12C@llvm.org> Author: atrick Date: Thu Nov 11 11:46:29 2010 New Revision: 118800 URL: http://llvm.org/viewvc/llvm-project?rev=118800&view=rev Log: Check TRI->getReservedRegs because other allocators do it. Even though it makes no sense for allocation_order iterators to visit reserved regs. The inline spiller depends on AliasAnalysis. Manage the Query state to avoid uninitialized or stale results. Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=118800&r1=118799&r2=118800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Thu Nov 11 11:46:29 2010 @@ -267,6 +267,9 @@ } private: + Query(const Query&); // DO NOT IMPLEMENT + void operator=(const Query&); // DO NOT IMPLEMENT + // Private interface for queries void findIntersection(InterferenceResult &ir) const; }; Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=118800&r1=118799&r2=118800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Thu Nov 11 11:46:29 2010 @@ -106,6 +106,15 @@ // A RegAlloc pass should call this before allocatePhysRegs. void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis); + // Get an initialized query to check interferences between lvr and preg. Note + // that Query::init must be called at least once for each physical register + // before querying a new live virtual register. This ties queries_ and + // physReg2liu_ together. + LiveIntervalUnion::Query &query(LiveInterval &lvr, unsigned preg) { + queries_[preg].init(&lvr, &physReg2liu_[preg]); + return queries_[preg]; + } + // The top-level driver. The output is a VirtRegMap that us updated with // physical register assignments. // @@ -135,7 +144,7 @@ // Helper for spilling all live virtual registers currently unified under preg // that interfere with the most recently queried lvr. Return true if spilling // was successful, and append any new spilled/split intervals to splitLVRs. - bool spillInterferences(unsigned preg, + bool spillInterferences(LiveInterval &lvr, unsigned preg, SmallVectorImpl &splitLVRs); #ifndef NDEBUG @@ -146,7 +155,8 @@ private: void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ); - void spillReg(unsigned reg, SmallVectorImpl &splitLVRs); + void spillReg(LiveInterval &lvr, unsigned reg, + SmallVectorImpl &splitLVRs); }; } // end namespace llvm Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=118800&r1=118799&r2=118800&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Thu Nov 11 11:46:29 2010 @@ -19,6 +19,7 @@ #include "Spiller.h" #include "VirtRegMap.h" #include "VirtRegRewriter.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Function.h" #include "llvm/PassAnalysisSupport.h" #include "llvm/CodeGen/CalcSpillWeights.h" @@ -75,6 +76,7 @@ MachineFunction *mf_; const TargetMachine *tm_; MachineRegisterInfo *mri_; + BitVector reservedRegs_; // analyses LiveStacks *ls_; @@ -145,6 +147,8 @@ void RABasic::getAnalysisUsage(AnalysisUsage &au) const { au.setPreservesCFG(); + au.addRequired(); + au.addPreserved(); au.addRequired(); au.addPreserved(); if (StrongPHIElim) @@ -187,8 +191,6 @@ for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end(); liItr != liEnd; ++liItr) { unsigned reg = liItr->first; - LiveInterval &li = *liItr->second; - if (li.empty() ) continue; if (TargetRegisterInfo::isPhysicalRegister(reg)) continue; if (!vrm_->hasPhys(reg)) continue; // spilled? unsigned preg = vrm_->getPhys(reg); @@ -271,7 +273,6 @@ liItr != liEnd; ++liItr) { unsigned reg = liItr->first; LiveInterval &li = *liItr->second; - if (li.empty()) continue; if (TargetRegisterInfo::isPhysicalRegister(reg)) { physReg2liu_[reg].unify(li); } @@ -314,12 +315,10 @@ // register. Return the interfering register. unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &lvr, unsigned preg) { - queries_[preg].init(&lvr, &physReg2liu_[preg]); - if (queries_[preg].checkInterference()) + if (query(lvr, preg).checkInterference()) return preg; for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) { - queries_[*asI].init(&lvr, &physReg2liu_[*asI]); - if (queries_[*asI].checkInterference()) + if (query(lvr, *asI).checkInterference()) return *asI; } return 0; @@ -334,60 +333,63 @@ }; // Spill all interferences currently assigned to this physical register. -void RegAllocBase::spillReg(unsigned reg, +void RegAllocBase::spillReg(LiveInterval& lvr, unsigned reg, SmallVectorImpl &splitLVRs) { - LiveIntervalUnion::Query &query = queries_[reg]; - const SmallVectorImpl &pendingSpills = - query.interferingVRegs(); + LiveIntervalUnion::Query &Q = query(lvr, reg); + const SmallVectorImpl &pendingSpills = Q.interferingVRegs(); + for (SmallVectorImpl::const_iterator I = pendingSpills.begin(), E = pendingSpills.end(); I != E; ++I) { - LiveInterval &lvr = **I; - DEBUG(dbgs() << - "extracting from " << tri_->getName(reg) << " " << lvr << '\n'); + LiveInterval &spilledLVR = **I; + DEBUG(dbgs() << "extracting from " << + tri_->getName(reg) << " " << spilledLVR << '\n'); // Deallocate the interfering vreg by removing it from the union. // A LiveInterval instance may not be in a union during modification! - physReg2liu_[reg].extract(lvr); - - // After extracting segments, the query's results are invalid. - query.clear(); + physReg2liu_[reg].extract(spilledLVR); // Clear the vreg assignment. - vrm_->clearVirt(lvr.reg); + vrm_->clearVirt(spilledLVR.reg); // Spill the extracted interval. - spiller().spill(&lvr, splitLVRs, pendingSpills); + spiller().spill(&spilledLVR, splitLVRs, pendingSpills); } + // After extracting segments, the query's results are invalid. But keep the + // contents valid until we're done accessing pendingSpills. + Q.clear(); } // Spill or split all live virtual registers currently unified under preg that // interfere with lvr. The newly spilled or split live intervals are returned by // appending them to splitLVRs. bool -RegAllocBase::spillInterferences(unsigned preg, +RegAllocBase::spillInterferences(LiveInterval &lvr, unsigned preg, SmallVectorImpl &splitLVRs) { // Record each interference and determine if all are spillable before mutating // either the union or live intervals. - std::vector spilledLVRs; - unsigned numInterferences = queries_[preg].collectInterferingVRegs(); - if (queries_[preg].seenUnspillableVReg()) { + // Collect interferences assigned to the requested physical register. + LiveIntervalUnion::Query &QPreg = query(lvr, preg); + unsigned numInterferences = QPreg.collectInterferingVRegs(); + if (QPreg.seenUnspillableVReg()) { return false; } + // Collect interferences assigned to any alias of the physical register. for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) { - numInterferences += queries_[*asI].collectInterferingVRegs(); - if (queries_[*asI].seenUnspillableVReg()) { + LiveIntervalUnion::Query &QAlias = query(lvr, *asI); + numInterferences += QAlias.collectInterferingVRegs(); + if (QAlias.seenUnspillableVReg()) { return false; } } DEBUG(dbgs() << "spilling " << tri_->getName(preg) << - " interferences with " << queries_[preg].lvr() << "\n"); + " interferences with " << lvr << "\n"); assert(numInterferences > 0 && "expect interference"); // Spill each interfering vreg allocated to preg or an alias. - spillReg(preg, splitLVRs); + spillReg(lvr, preg, splitLVRs); for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) - spillReg(*asI, splitLVRs); + spillReg(lvr, *asI, splitLVRs); return true; } @@ -409,7 +411,7 @@ unsigned RABasic::selectOrSplit(LiveInterval &lvr, SmallVectorImpl &splitLVRs) { // Populate a list of physical register spill candidates. - std::vector pregSpillCands; + SmallVector pregSpillCands; // Check for an available register in this class. const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg); @@ -417,6 +419,8 @@ trcEnd = trc->allocation_order_end(*mf_); trcI != trcEnd; ++trcI) { unsigned preg = *trcI; + if (reservedRegs_.test(preg)) continue; + // Check interference and intialize queries for this lvr as a side effect. unsigned interfReg = checkPhysRegInterference(lvr, preg); if (interfReg == 0) { @@ -435,17 +439,17 @@ // Try to spill another interfering reg with less spill weight. // // FIXME: RAGreedy will sort this list by spill weight. - for (std::vector::iterator pregI = pregSpillCands.begin(), + for (SmallVectorImpl::iterator pregI = pregSpillCands.begin(), pregE = pregSpillCands.end(); pregI != pregE; ++pregI) { - if (!spillInterferences(*pregI, splitLVRs)) continue; + if (!spillInterferences(lvr, *pregI, splitLVRs)) continue; unsigned interfReg = checkPhysRegInterference(lvr, *pregI); if (interfReg != 0) { const LiveSegment &seg = *queries_[interfReg].firstInterference().liuSegPos(); dbgs() << "spilling cannot free " << tri_->getName(*pregI) << - " for " << lvr.reg << " with interference " << seg.liveVirtReg << "\n"; + " for " << lvr.reg << " with interference " << *seg.liveVirtReg << "\n"; llvm_unreachable("Interference after spill."); } // Tell the caller to allocate to this newly freed physical register. @@ -477,10 +481,13 @@ mri_ = &mf.getRegInfo(); DEBUG(rmf_ = &getAnalysis()); - - RegAllocBase::init(*tm_->getRegisterInfo(), getAnalysis(), + + const TargetRegisterInfo *TRI = tm_->getRegisterInfo(); + RegAllocBase::init(*TRI, getAnalysis(), getAnalysis()); + reservedRegs_ = TRI->getReservedRegs(*mf_); + // We may want to force InlineSpiller for this register allocator. For // now we're also experimenting with the standard spiller. // From clattner at apple.com Thu Nov 11 11:57:02 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 09:57:02 -0800 Subject: [llvm-commits] [llvm] r118434 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ In-Reply-To: <20101108194002.618892A6C12D@llvm.org> References: <20101108194002.618892A6C12D@llvm.org> Message-ID: On Nov 8, 2010, at 11:40 AM, Wesley Peck wrote: > Author: peckw > Date: Mon Nov 8 13:40:01 2010 > New Revision: 118434 > > URL: http://llvm.org/viewvc/llvm-project?rev=118434&view=rev > Log: > Adding working version of assembly parser for the MBlaze backend > Major cleanup of whitespace and formatting issues in MBlaze backend Very nice! Please add some testcases to test/MC/MBlaze so that it doesn't get broken in the future :) -Chris From clattner at apple.com Thu Nov 11 11:59:33 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 09:59:33 -0800 Subject: [llvm-commits] [llvm] r118788 - in /llvm/trunk: lib/Transforms/Scalar/Sink.cpp test/Analysis/TypeBasedAliasAnalysis/sink.ll In-Reply-To: <20101111162148.1B7A22A6C12C@llvm.org> References: <20101111162148.1B7A22A6C12C@llvm.org> Message-ID: <7765610D-4C6C-4671-B687-820CFCEEC217@apple.com> On Nov 11, 2010, at 8:21 AM, Dan Gohman wrote: > Author: djg > Date: Thu Nov 11 10:21:47 2010 > New Revision: 118788 > > URL: http://llvm.org/viewvc/llvm-project?rev=118788&view=rev > Log: > Make Sink tbaa-aware. Makes sense, a minor API suggestion: > +++ llvm/trunk/lib/Transforms/Scalar/Sink.cpp Thu Nov 11 10:21:47 2010 > @@ -15,6 +15,7 @@ > #define DEBUG_TYPE "sink" > #include "llvm/Transforms/Scalar.h" > #include "llvm/IntrinsicInst.h" > +#include "llvm/LLVMContext.h" > #include "llvm/Analysis/Dominators.h" > #include "llvm/Analysis/LoopInfo.h" > #include "llvm/Analysis/AliasAnalysis.h" > @@ -158,9 +159,11 @@ > > Value *Ptr = L->getPointerOperand(); > uint64_t Size = AA->getTypeStoreSize(L->getType()); > + const MDNode *TBAAInfo = L->getMetadata(LLVMContext::MD_tbaa); > + AliasAnalysis::Location Loc(Ptr, Size, TBAAInfo); How about adding a static member to Location so that you could use something like this (likewise for other mem operations): AliasAnalysis::Location Loc = AliasAnalysis::Location::getLoadLoc(L); This has the dual advantage of making the code simpler, and also not requiring an LLVMContext.h #include. -Chris From grosbach at apple.com Thu Nov 11 12:04:49 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 18:04:49 -0000 Subject: [llvm-commits] [llvm] r118801 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMCodeEmitter.cpp ARMFixupKinds.h ARMInstrInfo.td ARMMCCodeEmitter.cpp Message-ID: <20101111180449.BD3702A6C12C@llvm.org> Author: grosbach Date: Thu Nov 11 12:04:49 2010 New Revision: 118801 URL: http://llvm.org/viewvc/llvm-project?rev=118801&view=rev Log: Encoding of destination fixup for ARM branch and conditional branch instructions. Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMFixupKinds.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118801&r1=118800&r2=118801&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Nov 11 12:04:49 2010 @@ -138,12 +138,13 @@ } }; -static unsigned getFixupKindLog2Size(unsigned Kind) { +static unsigned getFixupKindNumBytes(unsigned Kind) { switch (Kind) { default: llvm_unreachable("Unknown fixup kind!"); - case FK_Data_4: return 2; + case FK_Data_4: return 4; case ARM::fixup_arm_pcrel_12: return 2; case ARM::fixup_arm_vfp_pcrel_12: return 1; + case ARM::fixup_arm_branch: return 3; } } @@ -156,16 +157,17 @@ case ARM::fixup_arm_pcrel_12: // ARM PC-relative values are offset by 8. return Value - 8; + case ARM::fixup_arm_branch: case ARM::fixup_arm_vfp_pcrel_12: - // The VFP ld/st immediate value doesn't encode the low two bits since - // they're always zero. Offset by 8 just as above. + // These values don't encode the low two bits since they're always zero. + // Offset by 8 just as above. return (Value - 8) >> 2; } } void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF, - uint64_t Value) const { - unsigned NumBytes = getFixupKindLog2Size(Fixup.getKind()); + uint64_t Value) const { + unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); Value = adjustFixupValue(Fixup.getKind(), Value); assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() && Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118801&r1=118800&r2=118801&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 11 12:04:49 2010 @@ -161,6 +161,8 @@ // are already handled elsewhere. They are placeholders to allow this // encoder to continue to function until the MC encoder is sufficiently // far along that this one can be eliminated entirely. + unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) + const { return 0; } unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=118801&r1=118800&r2=118801&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Thu Nov 11 12:04:49 2010 @@ -20,7 +20,14 @@ // fixup_arm_vfp_pcrel_12 - 12-bit PC relative relocation for symbol addresses // used in VFP instructions where the lower 2 bits are not encoded (so it's // encoded as an 8-bit immediate). - fixup_arm_vfp_pcrel_12 + fixup_arm_vfp_pcrel_12, + // fixup_arm_brnach - 24-bit PC relative relocation for direct branch + // instructions. + fixup_arm_branch, + + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118801&r1=118800&r2=118801&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 11 12:04:49 2010 @@ -274,7 +274,9 @@ // // Branch target. -def brtarget : Operand; +def brtarget : Operand { + string EncoderMethod = "getBranchTargetOpValue"; +} // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand { @@ -1363,7 +1365,10 @@ let isBarrier = 1 in { let isPredicable = 1 in def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, - "b\t$target", [(br bb:$target)]>; + "b\t$target", [(br bb:$target)]> { + bits<24> target; + let Inst{23-0} = target; + } let isNotDuplicable = 1, isIndirectBranch = 1, // FIXME: $imm field is not specified by asm string. Mark as cgonly. @@ -1406,7 +1411,10 @@ // a two-value operand where a dag node expects two operands. :( def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), IIC_Br, "b", "\t$target", - [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; + [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { + bits<24> target; + let Inst{23-0} = target; + } } // Branch and Exchange Jazelle -- for disassembly only Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118801&r1=118800&r2=118801&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 11 12:04:49 2010 @@ -41,12 +41,14 @@ ~ARMMCCodeEmitter() {} - unsigned getNumFixupKinds() const { return 2; } + unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { const static MCFixupKindInfo Infos[] = { - { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel }, + // name offset bits flags + { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, }; if (Kind < FirstTargetFixupKind) @@ -72,6 +74,11 @@ unsigned &Reg, unsigned &Imm, SmallVectorImpl &Fixups) const; + /// getBranchTargetOpValue - Return encoding info for 24-bit immediate + /// branch target. + uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; + /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' /// operand. uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, @@ -247,6 +254,24 @@ return isAdd; } +/// getBranchTargetOpValue - Return encoding info for 24-bit immediate +/// branch target. +uint32_t ARMMCCodeEmitter:: +getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { + const MCOperand &MO = MI.getOperand(OpIdx); + + // If the destination is an immediate, we have nothing to do. + if (MO.isImm()) return MO.getImm(); + assert (MO.isExpr() && "Unexpected branch target type!"); + const MCExpr *Expr = MO.getExpr(); + MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch); + Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + + // All of the information is in the fixup. + return 0; +} + /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. uint32_t ARMMCCodeEmitter:: getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, From gohman at apple.com Thu Nov 11 12:08:43 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 18:08:43 -0000 Subject: [llvm-commits] [llvm] r118803 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp Message-ID: <20101111180843.519F72A6C12C@llvm.org> Author: djg Date: Thu Nov 11 12:08:43 2010 New Revision: 118803 URL: http://llvm.org/viewvc/llvm-project?rev=118803&view=rev Log: Add a FIXME comment. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=118803&r1=118802&r2=118803&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Thu Nov 11 12:08:43 2010 @@ -944,6 +944,8 @@ // In low register pressure situation, we can be more aggressive about // hoisting. Also, favors hoisting long latency instructions even in // moderately high pressure situation. + // FIXME: If there are long latency loop-invariant instructions inside the + // loop at this point, why didn't the optimizer's LICM hoist them? DenseMap Cost; for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); From gohman at apple.com Thu Nov 11 12:09:32 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 18:09:32 -0000 Subject: [llvm-commits] [llvm] r118804 - in /llvm/trunk: lib/Transforms/IPO/ArgumentPromotion.cpp test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll Message-ID: <20101111180932.5656E2A6C12C@llvm.org> Author: djg Date: Thu Nov 11 12:09:32 2010 New Revision: 118804 URL: http://llvm.org/viewvc/llvm-project?rev=118804&view=rev Log: TBAA-enable ArgumentPromotion. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=118804&r1=118803&r2=118804&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Thu Nov 11 12:09:32 2010 @@ -39,7 +39,6 @@ #include "llvm/LLVMContext.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/CallGraph.h" -#include "llvm/Target/TargetData.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/CFG.h" #include "llvm/Support/Debug.h" @@ -440,8 +439,6 @@ SmallPtrSet TranspBlocks; AliasAnalysis &AA = getAnalysis(); - TargetData *TD = getAnalysisIfAvailable(); - if (!TD) return false; // Without TargetData, assume the worst. for (unsigned i = 0, e = Loads.size(); i != e; ++i) { // Check to see if the load is invalidated from the start of the block to @@ -449,11 +446,11 @@ LoadInst *Load = Loads[i]; BasicBlock *BB = Load->getParent(); - const PointerType *LoadTy = - cast(Load->getPointerOperand()->getType()); - uint64_t LoadSize = TD->getTypeStoreSize(LoadTy->getElementType()); + AliasAnalysis::Location Loc(Load->getPointerOperand(), + AA.getTypeStoreSize(Load->getType()), + Load->getMetadata(LLVMContext::MD_tbaa)); - if (AA.canInstructionRangeModify(BB->front(), *Load, Arg, LoadSize)) + if (AA.canInstructionRangeModify(BB->front(), *Load, Loc)) return false; // Pointer is invalidated! // Now check every path from the entry block to the load for transparency. @@ -464,7 +461,7 @@ for (idf_ext_iterator > I = idf_ext_begin(P, TranspBlocks), E = idf_ext_end(P, TranspBlocks); I != E; ++I) - if (AA.canBasicBlockModify(**I, Arg, LoadSize)) + if (AA.canBasicBlockModify(**I, Loc)) return false; } } @@ -700,6 +697,9 @@ // of the previous load. LoadInst *newLoad = new LoadInst(V, V->getName()+".val", Call); newLoad->setAlignment(OrigLoad->getAlignment()); + // Transfer the TBAA info too. + newLoad->setMetadata(LLVMContext::MD_tbaa, + OrigLoad->getMetadata(LLVMContext::MD_tbaa)); Args.push_back(newLoad); AA.copyValue(OrigLoad, Args.back()); } Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll?rev=118804&view=auto ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll (added) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll Thu Nov 11 12:09:32 2010 @@ -0,0 +1,31 @@ +; RUN: opt < %s -enable-tbaa -tbaa -basicaa -argpromotion -mem2reg -S | not grep alloca + +target datalayout = "E-p:64:64:64" + +define internal i32 @test(i32* %X, i32* %Y, i32* %Q) { + store i32 77, i32* %Q, !tbaa !2 + %A = load i32* %X, !tbaa !1 + %B = load i32* %Y, !tbaa !1 + %C = add i32 %A, %B + ret i32 %C +} + +define internal i32 @caller(i32* %B, i32* %Q) { + %A = alloca i32 + store i32 78, i32* %Q, !tbaa !2 + store i32 1, i32* %A, !tbaa !1 + %C = call i32 @test(i32* %A, i32* %B, i32* %Q) + ret i32 %C +} + +define i32 @callercaller(i32* %Q) { + %B = alloca i32 + store i32 2, i32* %B, !tbaa !1 + store i32 79, i32* %Q, !tbaa !2 + %X = call i32 @caller(i32* %B, i32* %Q) + ret i32 %X +} + +!0 = metadata !{metadata !"test"} +!1 = metadata !{metadata !"green", metadata !0} +!2 = metadata !{metadata !"blue", metadata !0} From Renato.Golin at arm.com Thu Nov 11 12:11:46 2010 From: Renato.Golin at arm.com (Renato Golin) Date: Thu, 11 Nov 2010 18:11:46 +0000 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: References: Message-ID: <4CDC31E2.3050009@arm.com> On 10/11/10 17:57, Jason Kim wrote: > tryA: move the functionality of the ELFObjectWriterImpl class into > ELFObjectWriter, and subclass ELFObjectWriter to > ELFObjectWriter. > (...) > > tryB: subclass ELFObjectWriterImpl instead - I am still working out > the details on this one - but as of right now, it is just as complex > as the tryA case. I'm not an expert in MC, but I can't see anything wrong with neither approaches. The second one seems less invasive, but has the problems you mentioned. As MachO and ELF are very different, I can't see now the big problem of conceptually separating them. As far as I could gather, you only moved things around, so no problems for ARM. In this sense, I'm happy with both patches. cheers, --renato -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From rafael.espindola at gmail.com Thu Nov 11 12:13:52 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 11 Nov 2010 18:13:52 -0000 Subject: [llvm-commits] [llvm] r118805 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCSectionELF.h include/llvm/Support/ELF.h lib/MC/ELFObjectWriter.cpp lib/MC/MCContext.cpp lib/MC/MCParser/ELFAsmParser.cpp test/MC/ELF/comdat.s test/MC/ELF/section.s Message-ID: <20101111181352.A7BBF2A6C12C@llvm.org> Author: rafael Date: Thu Nov 11 12:13:52 2010 New Revision: 118805 URL: http://llvm.org/viewvc/llvm-project?rev=118805&view=rev Log: Initial comdat implementation. Added: llvm/trunk/test/MC/ELF/comdat.s Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCSectionELF.h llvm/trunk/include/llvm/Support/ELF.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/test/MC/ELF/section.s Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Thu Nov 11 12:13:52 2010 @@ -138,10 +138,15 @@ SectionKind K) { return getMachOSection(Segment, Section, TypeAndAttributes, 0, K); } - + + const MCSectionELF *getELFSection(StringRef Section, unsigned Type, + unsigned Flags, SectionKind Kind); + const MCSectionELF *getELFSection(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind, - unsigned EntrySize = 0); + unsigned EntrySize, StringRef Group); + + const MCSectionELF *CreateELFGroupSection(); const MCSection *getCOFFSection(StringRef Section, unsigned Characteristics, int Selection, SectionKind Kind); Modified: llvm/trunk/include/llvm/MC/MCSectionELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionELF.h?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCSectionELF.h (original) +++ llvm/trunk/include/llvm/MC/MCSectionELF.h Thu Nov 11 12:13:52 2010 @@ -18,6 +18,8 @@ namespace llvm { +class MCSymbol; + /// MCSectionELF - This represents a section on linux, lots of unix variants /// and some bare metal systems. class MCSectionELF : public MCSection { @@ -37,12 +39,14 @@ /// section does not contain fixed-sized entries 'EntrySize' will be 0. unsigned EntrySize; + const MCSymbol *Group; + private: friend class MCContext; MCSectionELF(StringRef Section, unsigned type, unsigned flags, - SectionKind K, unsigned entrySize) + SectionKind K, unsigned entrySize, const MCSymbol *group) : MCSection(SV_ELF, K), SectionName(Section), Type(type), Flags(flags), - EntrySize(entrySize) {} + EntrySize(entrySize), Group(group) {} ~MCSectionELF(); public: @@ -179,6 +183,7 @@ unsigned getType() const { return Type; } unsigned getFlags() const { return Flags; } unsigned getEntrySize() const { return EntrySize; } + const MCSymbol *getGroup() const { return Group; } void PrintSwitchToSection(const MCAsmInfo &MAI, raw_ostream &OS) const; Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Thu Nov 11 12:13:52 2010 @@ -348,6 +348,13 @@ SHF_MASKPROC = 0xf0000000 // Bits indicating processor-specific flags. }; +// Section Group Flags +enum { + GRP_COMDAT = 0x1, + GRP_MASKOS = 0x0ff00000, + GRP_MASKPROC = 0xf0000000 +}; + // Symbol table entries for ELF32. struct Elf32_Sym { Elf32_Word st_name; // Symbol name (index into string table) Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Nov 11 12:13:52 2010 @@ -326,6 +326,11 @@ void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout, const SectionIndexMapTy &SectionIndexMap); + // Map from a group section to the signature symbol + typedef DenseMap GroupMapTy; + void CreateGroupSections(MCAssembler &Asm, MCAsmLayout &Layout, + GroupMapTy &GroupMap); + void ExecutePostLayoutBinding(MCAssembler &Asm); void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, @@ -344,6 +349,7 @@ void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); void WriteSection(MCAssembler &Asm, const SectionIndexMapTy &SectionIndexMap, + uint32_t GroupSymbolIndex, uint64_t Offset, uint64_t Size, uint64_t Alignment, const MCSectionELF &Section); }; @@ -939,6 +945,17 @@ ie = Asm.end(); it != ie; ++it) { const MCSectionELF &Section = static_cast(it->getSection()); + if (Section.getType() != ELF::SHT_GROUP) + continue; + SectionIndexMap[&Section] = Index++; + } + + for (MCAssembler::iterator it = Asm.begin(), + ie = Asm.end(); it != ie; ++it) { + const MCSectionELF &Section = + static_cast(it->getSection()); + if (Section.getType() == ELF::SHT_GROUP) + continue; SectionIndexMap[&Section] = Index++; } } @@ -1062,7 +1079,7 @@ RelaSection = Ctx.getELFSection(RelaSectionName, HasRelocationAddend ? ELF::SHT_RELA : ELF::SHT_REL, 0, SectionKind::getReadOnly(), - EntrySize); + EntrySize, ""); MCSectionData &RelaSD = Asm.getOrCreateSectionData(*RelaSection); RelaSD.setAlignment(Is64Bit ? 8 : 4); @@ -1148,7 +1165,7 @@ const MCSectionELF *SymtabSection = Ctx.getELFSection(".symtab", ELF::SHT_SYMTAB, 0, SectionKind::getReadOnly(), - EntrySize); + EntrySize, ""); MCSectionData &SymtabSD = Asm.getOrCreateSectionData(*SymtabSection); SymtabSD.setAlignment(Is64Bit ? 8 : 4); SymbolTableIndex = Asm.size(); @@ -1158,7 +1175,7 @@ if (NeedsSymtabShndx) { const MCSectionELF *SymtabShndxSection = Ctx.getELFSection(".symtab_shndx", ELF::SHT_SYMTAB_SHNDX, 0, - SectionKind::getReadOnly(), 4); + SectionKind::getReadOnly(), 4, ""); SymtabShndxSD = &Asm.getOrCreateSectionData(*SymtabShndxSection); SymtabShndxSD->setAlignment(4); } @@ -1195,18 +1212,25 @@ uint64_t Index = 1; F->getContents() += '\x00'; + StringMap SecStringMap; for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) { const MCSectionELF &Section = static_cast(it->getSection()); // FIXME: We could merge suffixes like in .text and .rela.text. + StringRef Name = Section.getSectionName(); + if (SecStringMap.count(Name)) { + SectionStringTableIndex[&Section] = SecStringMap[Name]; + continue; + } // Remember the index into the string table so we can write it // into the sh_name field of the section header table. - SectionStringTableIndex[&it->getSection()] = Index; + SectionStringTableIndex[&Section] = Index; + SecStringMap[Name] = Index; - Index += Section.getSectionName().size() + 1; - F->getContents() += Section.getSectionName(); + Index += Name.size() + 1; + F->getContents() += Name; F->getContents() += '\x00'; } @@ -1247,8 +1271,59 @@ return !SectionB && BaseSection == SectionA; } +void ELFObjectWriterImpl::CreateGroupSections(MCAssembler &Asm, + MCAsmLayout &Layout, + GroupMapTy &GroupMap) { + typedef DenseMap RevGroupMapTy; + // Build the groups + RevGroupMapTy Groups; + for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); + it != ie; ++it) { + const MCSectionELF &Section = + static_cast(it->getSection()); + if (!(Section.getFlags() & MCSectionELF::SHF_GROUP)) + continue; + + const MCSymbol *SignatureSymbol = Section.getGroup(); + Asm.getOrCreateSymbolData(*SignatureSymbol); + const MCSectionELF *&Group = Groups[SignatureSymbol]; + if (!Group) { + Group = Asm.getContext().CreateELFGroupSection(); + MCSectionData &Data = Asm.getOrCreateSectionData(*Group); + Data.setAlignment(4); + MCDataFragment *F = new MCDataFragment(&Data); + String32(*F, ELF::GRP_COMDAT); + } + GroupMap[Group] = SignatureSymbol; + } + + // Add sections to the groups + unsigned Index = 1; + unsigned NumGroups = Groups.size(); + for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); + it != ie; ++it, ++Index) { + const MCSectionELF &Section = + static_cast(it->getSection()); + if (!(Section.getFlags() & MCSectionELF::SHF_GROUP)) + continue; + const MCSectionELF *Group = Groups[Section.getGroup()]; + MCSectionData &Data = Asm.getOrCreateSectionData(*Group); + // FIXME: we could use the previous fragment + MCDataFragment *F = new MCDataFragment(&Data); + String32(*F, NumGroups + Index); + } + + for (RevGroupMapTy::const_iterator i = Groups.begin(), e = Groups.end(); + i != e; ++i) { + const MCSectionELF *Group = i->second; + MCSectionData &Data = Asm.getOrCreateSectionData(*Group); + Asm.AddSectionToTheEnd(*Writer, Data, Layout); + } +} + void ELFObjectWriterImpl::WriteSection(MCAssembler &Asm, const SectionIndexMapTy &SectionIndexMap, + uint32_t GroupSymbolIndex, uint64_t Offset, uint64_t Size, uint64_t Alignment, const MCSectionELF &Section) { @@ -1300,6 +1375,12 @@ // Nothing to do. break; + case ELF::SHT_GROUP: { + sh_link = SymbolTableIndex; + sh_info = GroupSymbolIndex; + break; + } + default: assert(0 && "FIXME: sh_type value not supported!"); break; @@ -1312,6 +1393,10 @@ void ELFObjectWriterImpl::WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) { + + GroupMapTy GroupMap; + CreateGroupSections(Asm, const_cast(Layout), GroupMap); + SectionIndexMapTy SectionIndexMap; ComputeIndexMap(Asm, SectionIndexMap); @@ -1332,9 +1417,18 @@ uint64_t HeaderSize = Is64Bit ? sizeof(ELF::Elf64_Ehdr) : sizeof(ELF::Elf32_Ehdr); uint64_t FileOff = HeaderSize; - for (MCAssembler::const_iterator it = Asm.begin(), - ie = Asm.end(); it != ie; ++it) { - const MCSectionData &SD = *it; + std::vector Sections; + Sections.resize(NumSections); + + for (SectionIndexMapTy::const_iterator i= + SectionIndexMap.begin(), e = SectionIndexMap.end(); i != e; ++i) { + const std::pair &p = *i; + Sections[p.second] = p.first; + } + + for (unsigned i = 1; i < NumSections; ++i) { + const MCSectionELF &Section = *Sections[i]; + const MCSectionData &SD = Asm.getOrCreateSectionData(Section); FileOff = RoundUpToAlignment(FileOff, SD.getAlignment()); @@ -1354,20 +1448,20 @@ // ... then all of the sections ... DenseMap SectionOffsetMap; - for (MCAssembler::const_iterator it = Asm.begin(), - ie = Asm.end(); it != ie; ++it) { - const MCSectionData &SD = *it; + for (unsigned i = 1; i < NumSections; ++i) { + const MCSectionELF &Section = *Sections[i]; + const MCSectionData &SD = Asm.getOrCreateSectionData(Section); uint64_t Padding = OffsetToAlignment(FileOff, SD.getAlignment()); WriteZeros(Padding); FileOff += Padding; // Remember the offset into the file for this section. - SectionOffsetMap[&it->getSection()] = FileOff; + SectionOffsetMap[&Section] = FileOff; FileOff += Layout.getSectionFileSize(&SD); - Asm.WriteSectionData(it, Layout, Writer); + Asm.WriteSectionData(&SD, Layout, Writer); } uint64_t Padding = OffsetToAlignment(FileOff, NaturalAlignment); @@ -1384,14 +1478,17 @@ ShstrtabIndex >= ELF::SHN_LORESERVE ? ShstrtabIndex : 0; WriteSecHdrEntry(0, 0, 0, 0, 0, FirstSectionSize, FirstSectionLink, 0, 0, 0); - for (MCAssembler::const_iterator it = Asm.begin(), - ie = Asm.end(); it != ie; ++it) { - const MCSectionData &SD = *it; - const MCSectionELF &Section = - static_cast(SD.getSection()); + for (unsigned i = 1; i < NumSections; ++i) { + const MCSectionELF &Section = *Sections[i]; + const MCSectionData &SD = Asm.getOrCreateSectionData(Section); + uint32_t GroupSymbolIndex; + if (Section.getType() != ELF::SHT_GROUP) + GroupSymbolIndex = 0; + else + GroupSymbolIndex = getSymbolIndexInSymbolTable(Asm, GroupMap[&Section]); - WriteSection(Asm, SectionIndexMap, SectionOffsetMap[&Section], - Layout.getSectionSize(&SD), + WriteSection(Asm, SectionIndexMap, GroupSymbolIndex, + SectionOffsetMap[&Section], Layout.getSectionSize(&SD), SD.getAlignment(), Section); } } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Thu Nov 11 12:13:52 2010 @@ -150,7 +150,13 @@ const MCSectionELF *MCContext:: getELFSection(StringRef Section, unsigned Type, unsigned Flags, - SectionKind Kind, unsigned EntrySize) { + SectionKind Kind) { + return getELFSection(Section, Type, Flags, Kind, 0, ""); +} + +const MCSectionELF *MCContext:: +getELFSection(StringRef Section, unsigned Type, unsigned Flags, + SectionKind Kind, unsigned EntrySize, StringRef Group) { if (ELFUniquingMap == 0) ELFUniquingMap = new ELFUniqueMapTy(); ELFUniqueMapTy &Map = *(ELFUniqueMapTy*)ELFUniquingMap; @@ -163,12 +169,24 @@ if (!EntrySize) { EntrySize = MCSectionELF::DetermineEntrySize(Kind); } + + MCSymbol *GroupSym = NULL; + if (!Group.empty()) + GroupSym = GetOrCreateSymbol(Group); + MCSectionELF *Result = new (*this) MCSectionELF(Entry.getKey(), Type, Flags, - Kind, EntrySize); + Kind, EntrySize, GroupSym); Entry.setValue(Result); return Result; } +const MCSectionELF *MCContext::CreateELFGroupSection() { + MCSectionELF *Result = + new (*this) MCSectionELF(".group", MCSectionELF::SHT_GROUP, 0, + SectionKind::getReadOnly(), 4, NULL); + return Result; +} + const MCSection *MCContext::getCOFFSection(StringRef Section, unsigned Characteristics, int Selection, Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Thu Nov 11 12:13:52 2010 @@ -203,6 +203,7 @@ StringRef FlagsStr; StringRef TypeName; int64_t Size = 0; + StringRef GroupName; if (getLexer().is(AsmToken::Comma)) { Lex(); @@ -249,7 +250,6 @@ if (getLexer().isNot(AsmToken::Comma)) return TokError("expected group name"); Lex(); - StringRef GroupName; if (getParser().ParseIdentifier(GroupName)) return true; if (getLexer().is(AsmToken::Comma)) { @@ -257,8 +257,8 @@ StringRef Linkage; if (getParser().ParseIdentifier(Linkage)) return true; - if (Linkage != "comdat" && Linkage != ".gnu.linkonce") - return TokError("Linkage must be 'comdat' or '.gnu.linkonce'"); + if (Linkage != "comdat") + return TokError("Linkage must be 'comdat'"); } } } @@ -306,6 +306,7 @@ Flags |= MCSectionELF::XCORE_SHF_DP_SECTION; break; case 'G': + Flags |= MCSectionELF::SHF_GROUP; break; default: return TokError("unknown flag"); @@ -331,7 +332,8 @@ ? SectionKind::getText() : SectionKind::getDataRel(); getStreamer().SwitchSection(getContext().getELFSection(SectionName, Type, - Flags, Kind, Size)); + Flags, Kind, Size, + GroupName)); return false; } @@ -405,7 +407,7 @@ MCSectionELF::SHF_MERGE | MCSectionELF::SHF_STRINGS, SectionKind::getReadOnly(), - 1); + 1, ""); static bool First = true; Added: llvm/trunk/test/MC/ELF/comdat.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/comdat.s?rev=118805&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/comdat.s (added) +++ llvm/trunk/test/MC/ELF/comdat.s Thu Nov 11 12:13:52 2010 @@ -0,0 +1,39 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that we produce the two group sections and that they are a the beginning +// of the file. + +// CHECK: # Section 0x00000001 +// CHECK-NEXT: (('sh_name', 0x00000021) # '.group' +// CHECK-NEXT: ('sh_type', 0x00000011) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000040) +// CHECK-NEXT: ('sh_size', 0x0000000c) +// CHECK-NEXT: ('sh_link', 0x0000000a) +// CHECK-NEXT: ('sh_info', 0x00000001) +// CHECK-NEXT: ('sh_addralign', 0x00000004) +// CHECK-NEXT: ('sh_entsize', 0x00000004) +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 0x00000002 +// CHECK-NEXT: (('sh_name', 0x00000021) # '.group' +// CHECK-NEXT: ('sh_type', 0x00000011) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x0000004c) +// CHECK-NEXT: ('sh_size', 0x00000008) +// CHECK-NEXT: ('sh_link', 0x0000000a) +// CHECK-NEXT: ('sh_info', 0x00000002) +// CHECK-NEXT: ('sh_addralign', 0x00000004) +// CHECK-NEXT: ('sh_entsize', 0x00000004) + + .section .foo,"axG", at progbits,g1,comdat +g1: + nop + + .section .bar,"axG", at progbits,g1,comdat + nop + + .section .zed,"axG", at progbits,g2,comdat +g2: + nop Modified: llvm/trunk/test/MC/ELF/section.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/section.s?rev=118805&r1=118804&r2=118805&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/section.s (original) +++ llvm/trunk/test/MC/ELF/section.s Thu Nov 11 12:13:52 2010 @@ -20,31 +20,31 @@ // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000040) +// CHECK-NEXT: ('sh_offset', 0x00000050) // CHECK-NEXT: ('sh_size', 0x00000000) // CHECK-NEXT: ('sh_link', 0x00000000) // CHECK-NEXT: ('sh_info', 0x00000000) // CHECK-NEXT: ('sh_addralign', 0x00000001) // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), -// CHECK-NEXT: # Section 0x00000008 +// CHECK-NEXT: # Section 0x0000000a // CHECK-NEXT: (('sh_name', 0x0000003e) # '.fini' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000040) +// CHECK-NEXT: ('sh_offset', 0x00000050) // CHECK-NEXT: ('sh_size', 0x00000000) // CHECK-NEXT: ('sh_link', 0x00000000) // CHECK-NEXT: ('sh_info', 0x00000000) // CHECK-NEXT: ('sh_addralign', 0x00000001) // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), -// CHECK-NEXT: # Section 0x00000009 +// CHECK-NEXT: # Section 0x0000000b // CHECK-NEXT: (('sh_name', 0x00000044) # '.rodata' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000040) +// CHECK-NEXT: ('sh_offset', 0x00000050) // CHECK-NEXT: ('sh_size', 0x00000000) // CHECK-NEXT: ('sh_link', 0x00000000) // CHECK-NEXT: ('sh_info', 0x00000000) @@ -53,5 +53,7 @@ // CHECK-NEXT: ), // Test that we can parse these +foo: +bar: .section .text.foo,"axG", at progbits,foo,comdat -.section .text.bar,"axMG", at progbits,42,bar,.gnu.linkonce +.section .text.bar,"axMG", at progbits,42,bar,comdat From sabre at nondot.org Thu Nov 11 12:23:57 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 18:23:57 -0000 Subject: [llvm-commits] [llvm] r118806 - /llvm/trunk/lib/Target/README.txt Message-ID: <20101111182357.C3AE02A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 12:23:57 2010 New Revision: 118806 URL: http://llvm.org/viewvc/llvm-project?rev=118806&view=rev Log: add a note Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=118806&r1=118805&r2=118806&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Thu Nov 11 12:23:57 2010 @@ -1984,3 +1984,31 @@ } //===---------------------------------------------------------------------===// + +We compile this: + +int foo(int a) { return (a & (~15)) / 16; } + +Into: + +define i32 @foo(i32 %a) nounwind readnone ssp { +entry: + %and = and i32 %a, -16 + %div = sdiv i32 %and, 16 + ret i32 %div +} + +but this code (X & -A)/A is X >> log2(A) when A is a power of 2, so this case +should be instcombined into just "a >> 4". + +We do get this at the codegen level, so something knows about it, but +instcombine should catch it earlier: + +_foo: ## @foo +## BB#0: ## %entry + movl %edi, %eax + sarl $4, %eax + ret + +//===---------------------------------------------------------------------===// + From peckw at wesleypeck.com Thu Nov 11 12:41:34 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Thu, 11 Nov 2010 18:41:34 -0000 Subject: [llvm-commits] [llvm] r118807 - /llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Message-ID: <20101111184134.1AE9D2A6C12C@llvm.org> Author: peckw Date: Thu Nov 11 12:41:33 2010 New Revision: 118807 URL: http://llvm.org/viewvc/llvm-project?rev=118807&view=rev Log: Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code. Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=118807&r1=118806&r2=118807&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Nov 11 12:41:33 2010 @@ -446,15 +446,15 @@ if (!Op) Op = ParseImmediate(); - // Move past the parsed token in the token stream - getLexer().Lex(); - // If the token could not be parsed then fail if (!Op) { Error(Parser.getTok().getLoc(), "unknown operand"); return 0; } + // Move past the parsed token in the token stream + getLexer().Lex(); + // Push the parsed operand into the list of operands Operands.push_back(Op); return Op; @@ -472,7 +472,7 @@ return false; // Parse the first operand - if (ParseOperand(Operands)) + if (!ParseOperand(Operands)) return true; while (getLexer().isNot(AsmToken::EndOfStatement) && @@ -485,7 +485,7 @@ getLexer().Lex(); // Parse the next operand - if (ParseOperand(Operands)) + if (!ParseOperand(Operands)) return true; } From gohman at apple.com Thu Nov 11 13:05:24 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 11:05:24 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: <3B47EB07-D1A9-491E-A0A3-493125D0DE6F@2pi.dk> References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> <1D46230B-F666-4B99-9C72-7D17BB709EEA@apple.com> <3B47EB07-D1A9-491E-A0A3-493125D0DE6F@2pi.dk> Message-ID: On Nov 11, 2010, at 9:20 AM, Jakob Stoklund Olesen wrote: > > On Nov 10, 2010, at 8:05 PM, Dan Gohman wrote: > >> >> >> On Nov 10, 2010, at 6:38 PM, Evan Cheng wrote: >>> >>>>>> I wonder if 'isTriviallyReMaterializable' means that the >>>>>> instruction can be rematted anywhere without further checks? If >>>>>> so, I should perhaps be using the basic TID::isRematerializable >>>>>> () flag instead? >>>>> >>>>> Right. It's only meant for the existing brain dead remat. >>>> >>>> I see. X86InstrInfo::isReallyTriviallyReMaterializable in >>>> particular has many arbitrary restrictions. I'll look into >>>> something more generic. >>>> >>>> I would be useful to be able to remat loads that have been >>>> hoisted by early optimizations. Is there any way AliasAnalysis >>>> can be rigged to provide more information than AA- >>>> >pointsToConstantMemory? >> >> Yes. The Values used with pointsToConstantMemory can also be used >> with normal AliasAnalysis::alias queries. There's no memdep or >> other higher level abstraction for MachineInstrs currently though. > > So because we are dealing with MachineInstrs, AliasAnalysis can't > tell me if I can move a load, right? Right, not by itself. AliasAnalysis is lower level. > Maybe a conservative approach could look at basic blocks. I want to > ask: Can I move a load from block A to block B, where A dominates B. > AA could conservatively assume that I want to move the load from the > top of A to the bottom of B. You also need to consider any other blocks that might be in a loop with B. > > If all my MachineBasicBlocks are properly mapped to BasicBlocks, > AA::canBasicBlockModify() is all I need, I think. This sounds risky; there is MachineInstr-level code motion, possibly incuding remat itself ;). IIRC, the only use of MachineBasicBlock's BB member right now is verbose output. A canMachineBasicBlockModify with a MachineInstr version of getModRefInfo might be worth considering. Dan > From rafael.espindola at gmail.com Thu Nov 11 13:04:55 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 11 Nov 2010 19:04:55 -0000 Subject: [llvm-commits] [llvm] r118818 - in /llvm/trunk: lib/MC/MCELFStreamer.cpp lib/MC/MCParser/AsmParser.cpp test/MC/ELF/tls.s Message-ID: <20101111190455.916012A6C12C@llvm.org> Author: rafael Date: Thu Nov 11 13:04:55 2010 New Revision: 118818 URL: http://llvm.org/viewvc/llvm-project?rev=118818&view=rev Log: Mark labels declared in tls sections as STT_TLS. This matches the behavior of gas. Added: llvm/trunk/test/MC/ELF/tls.s Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=118818&r1=118817&r2=118818&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Thu Nov 11 13:04:55 2010 @@ -35,6 +35,38 @@ namespace { +static void SetBinding(MCSymbolData &SD, unsigned Binding) { + assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL || + Binding == ELF::STB_WEAK); + uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STB_Shift); + SD.setFlags(OtherFlags | (Binding << ELF_STB_Shift)); +} + +static unsigned GetBinding(const MCSymbolData &SD) { + uint32_t Binding = (SD.getFlags() & (0xf << ELF_STB_Shift)) >> ELF_STB_Shift; + assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL || + Binding == ELF::STB_WEAK); + return Binding; +} + +static void SetType(MCSymbolData &SD, unsigned Type) { + assert(Type == ELF::STT_NOTYPE || Type == ELF::STT_OBJECT || + Type == ELF::STT_FUNC || Type == ELF::STT_SECTION || + Type == ELF::STT_FILE || Type == ELF::STT_COMMON || + Type == ELF::STT_TLS); + + uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STT_Shift); + SD.setFlags(OtherFlags | (Type << ELF_STT_Shift)); +} + +static void SetVisibility(MCSymbolData &SD, unsigned Visibility) { + assert(Visibility == ELF::STV_DEFAULT || Visibility == ELF::STV_INTERNAL || + Visibility == ELF::STV_HIDDEN || Visibility == ELF::STV_PROTECTED); + + uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STV_Shift); + SD.setFlags(OtherFlags | (Visibility << ELF_STV_Shift)); +} + class MCELFStreamer : public MCObjectStreamer { public: MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB, @@ -166,6 +198,11 @@ MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); + const MCSectionELF &Section = + static_cast(Symbol->getSection()); + if (Section.getFlags() & MCSectionELF::SHF_TLS) + SetType(SD, ELF::STT_TLS); + // FIXME: This is wasteful, we don't necessarily need to create a data // fragment. Instead, we should mark the symbol as pointing into the data // fragment if it exists, otherwise we should just queue the label and set its @@ -262,38 +299,6 @@ Alias->setVariableValue(Value); } -static void SetBinding(MCSymbolData &SD, unsigned Binding) { - assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL || - Binding == ELF::STB_WEAK); - uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STB_Shift); - SD.setFlags(OtherFlags | (Binding << ELF_STB_Shift)); -} - -static unsigned GetBinding(const MCSymbolData &SD) { - uint32_t Binding = (SD.getFlags() & (0xf << ELF_STB_Shift)) >> ELF_STB_Shift; - assert(Binding == ELF::STB_LOCAL || Binding == ELF::STB_GLOBAL || - Binding == ELF::STB_WEAK); - return Binding; -} - -static void SetType(MCSymbolData &SD, unsigned Type) { - assert(Type == ELF::STT_NOTYPE || Type == ELF::STT_OBJECT || - Type == ELF::STT_FUNC || Type == ELF::STT_SECTION || - Type == ELF::STT_FILE || Type == ELF::STT_COMMON || - Type == ELF::STT_TLS); - - uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STT_Shift); - SD.setFlags(OtherFlags | (Type << ELF_STT_Shift)); -} - -static void SetVisibility(MCSymbolData &SD, unsigned Visibility) { - assert(Visibility == ELF::STV_DEFAULT || Visibility == ELF::STV_INTERNAL || - Visibility == ELF::STV_HIDDEN || Visibility == ELF::STV_PROTECTED); - - uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STV_Shift); - SD.setFlags(OtherFlags | (Visibility << ELF_STV_Shift)); -} - void MCELFStreamer::EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) { // Indirect symbols are handled differently, to match how 'as' handles Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=118818&r1=118817&r2=118818&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Nov 11 13:04:55 2010 @@ -193,7 +193,6 @@ /// ParseDirectiveSymbolAttribute - Parse a directive like ".globl" which /// accepts a single symbol (which should be a label or an external). bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr); - bool ParseDirectiveELFType(); // ELF specific ".type" bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm" Added: llvm/trunk/test/MC/ELF/tls.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/tls.s?rev=118818&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/tls.s (added) +++ llvm/trunk/test/MC/ELF/tls.s Thu Nov 11 13:04:55 2010 @@ -0,0 +1,15 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that foobar is of type STT_TLS. + + .section .zed,"awT", at progbits +foobar: + .long 43 + +// CHECK: (('st_name', 0x00000001) # 'foobar' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000006) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000004) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) From resistor at mac.com Thu Nov 11 13:07:48 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 11 Nov 2010 19:07:48 -0000 Subject: [llvm-commits] [llvm] r118819 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neont2-abs-encoding.s test/MC/ARM/neont2-add-encoding.s Message-ID: <20101111190748.A01462A6C12C@llvm.org> Author: resistor Date: Thu Nov 11 13:07:48 2010 New Revision: 118819 URL: http://llvm.org/viewvc/llvm-project?rev=118819&view=rev Log: Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. More tests to come. Added: llvm/trunk/test/MC/ARM/neont2-abs-encoding.s llvm/trunk/test/MC/ARM/neont2-add-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118819&r1=118818&r2=118819&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 11 13:07:48 2010 @@ -161,6 +161,8 @@ // are already handled elsewhere. They are placeholders to allow this // encoder to continue to function until the MC encoder is sufficiently // far along that this one can be eliminated entirely. + unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) + const { return 0; } unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118819&r1=118818&r2=118819&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 11 13:07:48 2010 @@ -1868,6 +1868,7 @@ : NeonI { let Inst{31-25} = 0b1111001; + string PostEncoderMethod = "NEONThumb2DataIPostEncoder"; } class NDataXI &Fixups) const; + unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, + unsigned EncodedValue) const; + void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; } @@ -195,6 +198,26 @@ return new ARMMCCodeEmitter(TM, Ctx); } +/// NEONThumb2PostEncoder - Post-process encoded NEON data-processing +/// instructions, and rewrite them to their Thumb2 form if we are currently in +/// Thumb2 mode. +unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, + unsigned EncodedValue) const { + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isThumb2()) { + // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved + // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are + // set to 1111. + unsigned Bit24 = EncodedValue & 0x01000000; + unsigned Bit28 = Bit24 << 4; + EncodedValue &= 0xEFFFFFFF; + EncodedValue |= Bit28; + EncodedValue |= 0x0F000000; + } + + return EncodedValue; +} + /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned ARMMCCodeEmitter:: Added: llvm/trunk/test/MC/ARM/neont2-abs-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-abs-encoding.s?rev=118819&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-abs-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-abs-encoding.s Thu Nov 11 13:07:48 2010 @@ -0,0 +1,33 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xff] + vabs.s8 d16, d16 +@ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xff] + vabs.s16 d16, d16 +@ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xff] + vabs.s32 d16, d16 +@ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xff] + vabs.f32 d16, d16 +@ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xff] + vabs.s8 q8, q8 +@ CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xff] + vabs.s16 q8, q8 +@ CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xff] + vabs.s32 q8, q8 +@ CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xff] + vabs.f32 q8, q8 + +@ CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xff] + vqabs.s8 d16, d16 +@ CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xff] + vqabs.s16 d16, d16 +@ CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xff] + vqabs.s32 d16, d16 +@ CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xff] + vqabs.s8 q8, q8 +@ CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xff] + vqabs.s16 q8, q8 +@ CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xff] + vqabs.s32 q8, q8 Added: llvm/trunk/test/MC/ARM/neont2-add-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-add-encoding.s?rev=118819&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-add-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-add-encoding.s Thu Nov 11 13:07:48 2010 @@ -0,0 +1,138 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xef] + vadd.i8 d16, d17, d16 +@ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xef] + vadd.i16 d16, d17, d16 +@ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xef] + vadd.i64 d16, d17, d16 +@ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xef] + vadd.i32 d16, d17, d16 +@ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xef] + vadd.f32 d16, d16, d17 +@ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xef] + vadd.f32 q8, q8, q9 + +@ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xef] + vaddl.s8 q8, d17, d16 +@ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xef] + vaddl.s16 q8, d17, d16 +@ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xef] + vaddl.s32 q8, d17, d16 +@ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xff] + vaddl.u8 q8, d17, d16 +@ CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xff] + vaddl.u16 q8, d17, d16 +@ CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xff] + vaddl.u32 q8, d17, d16 + +@ CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xef] + vaddw.s8 q8, q8, d18 +@ CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xef] + vaddw.s16 q8, q8, d18 +@ CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xef] + vaddw.s32 q8, q8, d18 +@ CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xff] + vaddw.u8 q8, q8, d18 +@ CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xff] + vaddw.u16 q8, q8, d18 +@ CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xff] + vaddw.u32 q8, q8, d18 + +@ CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xef] + vhadd.s8 d16, d16, d17 +@ CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xef] + vhadd.s16 d16, d16, d17 +@ CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xef] + vhadd.s32 d16, d16, d17 +@ CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xff] + vhadd.u8 d16, d16, d17 +@ CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xff] + vhadd.u16 d16, d16, d17 +@ CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xff] + vhadd.u32 d16, d16, d17 +@ CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xef] + vhadd.s8 q8, q8, q9 +@ CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xef] + vhadd.s16 q8, q8, q9 +@ CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xef] + vhadd.s32 q8, q8, q9 + @ CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xff] + vhadd.u8 q8, q8, q9 +@ CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xff] + vhadd.u16 q8, q8, q9 +@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xff] + vhadd.u32 q8, q8, q9 + +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xef] + vrhadd.s8 d16, d16, d17 +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xef] + vrhadd.s16 d16, d16, d17 +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xef] + vrhadd.s32 d16, d16, d17 +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xff] + vrhadd.u8 d16, d16, d17 +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xff] + vrhadd.u16 d16, d16, d17 +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xff] + vrhadd.u32 d16, d16, d17 +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xef] + vrhadd.s8 q8, q8, q9 +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xef] + vrhadd.s16 q8, q8, q9 +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xef] + vrhadd.s32 q8, q8, q9 +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xff] + vrhadd.u8 q8, q8, q9 +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xff] + vrhadd.u16 q8, q8, q9 +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xff] + vrhadd.u32 q8, q8, q9 + +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xef] + vqadd.s8 d16, d16, d17 +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xef] + vqadd.s16 d16, d16, d17 +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xef] + vqadd.s32 d16, d16, d17 +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xef] + vqadd.s64 d16, d16, d17 +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xff] + vqadd.u8 d16, d16, d17 +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xff] + vqadd.u16 d16, d16, d17 +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xff] + vqadd.u32 d16, d16, d17 +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xff] + vqadd.u64 d16, d16, d17 +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xef] + vqadd.s8 q8, q8, q9 +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xef] + vqadd.s16 q8, q8, q9 +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xef] + vqadd.s32 q8, q8, q9 +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xef] + vqadd.s64 q8, q8, q9 +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xff] + vqadd.u8 q8, q8, q9 +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xff] + vqadd.u16 q8, q8, q9 +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xff] + vqadd.u32 q8, q8, q9 +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xff] + vqadd.u64 q8, q8, q9 + +@ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xef] + vaddhn.i16 d16, q8, q9 +@ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xef] + vaddhn.i32 d16, q8, q9 +@ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xef] + vaddhn.i64 d16, q8, q9 +@ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xff] + vraddhn.i16 d16, q8, q9 +@ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xff] + vraddhn.i32 d16, q8, q9 +@ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xff] + vraddhn.i64 d16, q8, q9 From stoklund at 2pi.dk Thu Nov 11 13:21:16 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 11 Nov 2010 11:21:16 -0800 Subject: [llvm-commits] [llvm] r118702 - in /llvm/trunk/lib/CodeGen: SplitKit.cpp SplitKit.h In-Reply-To: References: <20101110193150.38A1B2A6C12C@llvm.org> <0345CD1B-0433-4332-A17D-6E712DFE9FC5@2pi.dk> <050B2075-3F11-4B19-8CAB-76085992087F@2pi.dk> <1D46230B-F666-4B99-9C72-7D17BB709EEA@apple.com> <3B47EB07-D1A9-491E-A0A3-493125D0DE6F@2pi.dk> Message-ID: <5BDAC35E-4CFE-4838-9F16-BDC6BAF825AF@2pi.dk> On Nov 11, 2010, at 11:05 AM, Dan Gohman wrote: >> Maybe a conservative approach could look at basic blocks. I want to ask: Can I move a load from block A to block B, where A dominates B. AA could conservatively assume that I want to move the load from the top of A to the bottom of B. > > You also need to consider any other blocks that might be in a loop with B. Yes, any possible path from A to B. >> If all my MachineBasicBlocks are properly mapped to BasicBlocks, AA::canBasicBlockModify() is all I need, I think. > > This sounds risky; there is MachineInstr-level code motion, possibly incuding remat itself ;). IIRC, the only use of MachineBasicBlock's BB member right now is verbose output. We never remat stores, but you are right, other machine-level passes could possibly do that. > A canMachineBasicBlockModify with a MachineInstr version of getModRefInfo might be worth considering. Yes, that would actually be possible to do, using mayStore() and the memoperands. /jakob From gohman at apple.com Thu Nov 11 13:23:51 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 19:23:51 -0000 Subject: [llvm-commits] [llvm] r118822 - /llvm/trunk/lib/Analysis/Lint.cpp Message-ID: <20101111192351.4AD832A6C12C@llvm.org> Author: djg Date: Thu Nov 11 13:23:51 2010 New Revision: 118822 URL: http://llvm.org/viewvc/llvm-project?rev=118822&view=rev Log: Avoid calling alias on non-pointer values. Modified: llvm/trunk/lib/Analysis/Lint.cpp Modified: llvm/trunk/lib/Analysis/Lint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Lint.cpp?rev=118822&r1=118821&r2=118822&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Lint.cpp (original) +++ llvm/trunk/lib/Analysis/Lint.cpp Thu Nov 11 13:23:51 2010 @@ -231,10 +231,11 @@ // to do. Known partial overlap is not distinguished from the case // where nothing is known. if (Formal->hasNoAliasAttr() && Actual->getType()->isPointerTy()) - for (CallSite::arg_iterator BI = CS.arg_begin(); BI != AE; ++BI) { - Assert1(AI == BI || AA->alias(*AI, *BI) != AliasAnalysis::MustAlias, + for (CallSite::arg_iterator BI = CS.arg_begin(); BI != AE; ++BI) + Assert1(AI == BI || + !(*BI)->getType()->isPointerTy() || + AA->alias(*AI, *BI) != AliasAnalysis::MustAlias, "Unusual: noalias argument aliases another argument", &I); - } // Check that an sret argument points to valid memory. if (Formal->hasStructRetAttr() && Actual->getType()->isPointerTy()) { From echristo at apple.com Thu Nov 11 13:26:03 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 19:26:03 -0000 Subject: [llvm-commits] [llvm] r118823 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h Message-ID: <20101111192603.AEFF62A6C12C@llvm.org> Author: echristo Date: Thu Nov 11 13:26:03 2010 New Revision: 118823 URL: http://llvm.org/viewvc/llvm-project?rev=118823&view=rev Log: Change the prologue and epilogue to use push/pop for the low ARM registers. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=118823&r1=118822&r2=118823&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Nov 11 13:26:03 2010 @@ -208,8 +208,10 @@ DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); + MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); + AddDefaultPred(MIB); + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); bool isKill = true; // Add the callee-saved register as live-in unless it's LR and @@ -225,15 +227,58 @@ if (isKill) MBB.addLiveIn(Reg); - // Insert the spill to the stack frame. The register is killed at the spill - // - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - storeRegToStackSlot(MBB, MI, Reg, isKill, - CSI[i].getFrameIdx(), RC, TRI); + if (!isARMPushRegister(Reg)) { + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + storeRegToStackSlot(MBB, MI, Reg, isKill, + CSI[i-1].getFrameIdx(), RC, TRI); + } else + MIB.addReg(Reg, getKillRegState(isKill)); } return true; } +bool +ARMBaseInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI, + const TargetRegisterInfo *TRI) const { + MachineFunction &MF = *MBB.getParent(); + ARMFunctionInfo *AFI = MF.getInfo(); + if (CSI.empty()) + return false; + + bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; + DebugLoc DL = MI->getDebugLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); + AddDefaultPred(MIB); + + bool NumRegs = false; + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); + if (Reg == ARM::LR && !isVarArg) { + Reg = ARM::PC; + (*MIB).setDesc(get(ARM::tPOP_RET)); + MI = MBB.erase(MI); + } + + if (!isARMPushRegister(Reg)) { + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + loadRegFromStackSlot(MBB, MI, Reg, CSI[i-1].getFrameIdx(), RC, TRI); + } else + MIB.addReg(Reg, getDefRegState(true)); + NumRegs = true; + } + + // It's illegal to emit pop instruction without operands. + if (NumRegs) + MBB.insert(MI, &*MIB); + else + MF.DeleteMachineInstr(MIB); + + return true; +} + + // Branch analysis. bool ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, @@ -2046,7 +2091,7 @@ case ARM::VLDMQ: case ARM::VSTMQ: return 2; - } + } } bool ARMBaseInstrInfo:: Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=118823&r1=118822&r2=118823&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Nov 11 13:26:03 2010 @@ -211,6 +211,11 @@ const std::vector &CSI, const TargetRegisterInfo *TRI) const; + bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI, + const TargetRegisterInfo *TRI) const; + // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=118823&r1=118822&r2=118823&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Nov 11 13:26:03 2010 @@ -1667,9 +1667,9 @@ int Opc1, int Opc2, unsigned Area, const ARMSubtarget &STI) { while (MBBI != MBB.end() && - ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && - MBBI->getOperand(1).isFI()) { - if (Area != 0) { + ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2))) { + + if (Area == 3) { bool Done = false; unsigned Category = 0; switch (MBBI->getOperand(0).getReg()) { @@ -1759,9 +1759,7 @@ } } - // Build the new SUBri to adjust SP for integer callee-save spill area 1. - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); - movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 1, STI); // Set FP to point to the stack slot that contains the previous FP. // For Darwin, FP is R7, which has now been stored in spill area 1. @@ -1781,7 +1779,7 @@ emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); // Build the new SUBri to adjust SP for FP callee-save spill area. - movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 2, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); // Determine starting offsets of spill areas. @@ -1875,11 +1873,25 @@ static bool isCSRestore(MachineInstr *MI, const ARMBaseInstrInfo &TII, const unsigned *CSRegs) { - return ((MI->getOpcode() == (int)ARM::VLDRD || - MI->getOpcode() == (int)ARM::LDRi12 || - MI->getOpcode() == (int)ARM::t2LDRi12) && - MI->getOperand(1).isFI() && - isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); + + // Integer spill area is handled with pop. + if (MI->getOpcode() == ARM::tRestore || + MI->getOpcode() == ARM::tPOP) { + // The first two operands are predicates. The last two are + // imp-def and imp-use of SP. Check everything in between. + for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) + if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) + return false; + return true; + } + + // Or if this is a fp reg spill. + if (MI->getOpcode() == (int)ARM::VLDRD && + MI->getOperand(1).isFI() && + isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) + return true; + + return false; } void ARMBaseRegisterInfo:: @@ -1945,12 +1957,8 @@ emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); // Move SP to start of integer callee save spill area 1. - movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::tPOP, 0, 2, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); - - // Move SP to SP upon entry to the function. - movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI); - emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); } if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=118823&r1=118822&r2=118823&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Nov 11 13:26:03 2010 @@ -44,6 +44,20 @@ } } +/// isARMPushRegister - Returns true if the register is a low register (r0-r7) +/// or a stack/pc register that we should push/pop. +static inline bool isARMPushRegister(unsigned Reg) { + using namespace ARM; + switch (Reg) { + case R0: case R1: case R2: case R3: + case R4: case R5: case R6: case R7: + case LR: case SP: case PC: + return true; + default: + return false; + } +} + class ARMBaseRegisterInfo : public ARMGenRegisterInfo { protected: const ARMBaseInstrInfo &TII; From stoklund at 2pi.dk Thu Nov 11 13:46:02 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 11 Nov 2010 11:46:02 -0800 Subject: [llvm-commits] [llvm] r118800 - in /llvm/trunk/lib/CodeGen: LiveIntervalUnion.h RegAllocBase.h RegAllocBasic.cpp In-Reply-To: <20101111174629.AEAD52A6C12C@llvm.org> References: <20101111174629.AEAD52A6C12C@llvm.org> Message-ID: On Nov 11, 2010, at 9:46 AM, Andrew Trick wrote: > Author: atrick > Date: Thu Nov 11 11:46:29 2010 > New Revision: 118800 > > URL: http://llvm.org/viewvc/llvm-project?rev=118800&view=rev > Log: > Check TRI->getReservedRegs because other allocators do it. Even though > it makes no sense for allocation_order iterators to visit reserved regs. Yes, this is unfortunate, but it is the best we can do ATM. The problem is that some targets have multiple registers that may be reserved (arm), and writing the allocation_order iterators quickly becomes very difficult. /jakob From echristo at apple.com Thu Nov 11 13:47:46 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 11:47:46 -0800 Subject: [llvm-commits] [llvm] r118823 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h In-Reply-To: <20101111192603.AEFF62A6C12C@llvm.org> References: <20101111192603.AEFF62A6C12C@llvm.org> Message-ID: On Nov 11, 2010, at 11:26 AM, Eric Christopher wrote: > Change the prologue and epilogue to use push/pop for the low ARM registers. Pulling this back out. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/b7216ef4/attachment.html From echristo at apple.com Thu Nov 11 13:47:02 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 19:47:02 -0000 Subject: [llvm-commits] [llvm] r118827 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h ARMBaseRegisterInfo.cpp ARMBaseRegisterInfo.h ARMTargetMachine.cpp Message-ID: <20101111194702.6A7102A6C12C@llvm.org> Author: echristo Date: Thu Nov 11 13:47:02 2010 New Revision: 118827 URL: http://llvm.org/viewvc/llvm-project?rev=118827&view=rev Log: Revert this temporarily. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=118827&r1=118826&r2=118827&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Nov 11 13:47:02 2010 @@ -208,10 +208,8 @@ DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); - MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); - AddDefaultPred(MIB); - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); bool isKill = true; // Add the callee-saved register as live-in unless it's LR and @@ -227,58 +225,15 @@ if (isKill) MBB.addLiveIn(Reg); - if (!isARMPushRegister(Reg)) { - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - storeRegToStackSlot(MBB, MI, Reg, isKill, - CSI[i-1].getFrameIdx(), RC, TRI); - } else - MIB.addReg(Reg, getKillRegState(isKill)); + // Insert the spill to the stack frame. The register is killed at the spill + // + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + storeRegToStackSlot(MBB, MI, Reg, isKill, + CSI[i].getFrameIdx(), RC, TRI); } return true; } -bool -ARMBaseInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - if (CSI.empty()) - return false; - - bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; - DebugLoc DL = MI->getDebugLoc(); - MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); - AddDefaultPred(MIB); - - bool NumRegs = false; - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - if (Reg == ARM::LR && !isVarArg) { - Reg = ARM::PC; - (*MIB).setDesc(get(ARM::tPOP_RET)); - MI = MBB.erase(MI); - } - - if (!isARMPushRegister(Reg)) { - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - loadRegFromStackSlot(MBB, MI, Reg, CSI[i-1].getFrameIdx(), RC, TRI); - } else - MIB.addReg(Reg, getDefRegState(true)); - NumRegs = true; - } - - // It's illegal to emit pop instruction without operands. - if (NumRegs) - MBB.insert(MI, &*MIB); - else - MF.DeleteMachineInstr(MIB); - - return true; -} - - // Branch analysis. bool ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, @@ -2091,7 +2046,7 @@ case ARM::VLDMQ: case ARM::VSTMQ: return 2; - } + } } bool ARMBaseInstrInfo:: Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=118827&r1=118826&r2=118827&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Nov 11 13:47:02 2010 @@ -211,11 +211,6 @@ const std::vector &CSI, const TargetRegisterInfo *TRI) const; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=118827&r1=118826&r2=118827&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Nov 11 13:47:02 2010 @@ -1667,9 +1667,9 @@ int Opc1, int Opc2, unsigned Area, const ARMSubtarget &STI) { while (MBBI != MBB.end() && - ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2))) { - - if (Area == 3) { + ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && + MBBI->getOperand(1).isFI()) { + if (Area != 0) { bool Done = false; unsigned Category = 0; switch (MBBI->getOperand(0).getReg()) { @@ -1759,7 +1759,9 @@ } } - movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 1, STI); + // Build the new SUBri to adjust SP for integer callee-save spill area 1. + emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); + movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI); // Set FP to point to the stack slot that contains the previous FP. // For Darwin, FP is R7, which has now been stored in spill area 1. @@ -1779,7 +1781,7 @@ emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); // Build the new SUBri to adjust SP for FP callee-save spill area. - movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); // Determine starting offsets of spill areas. @@ -1873,25 +1875,11 @@ static bool isCSRestore(MachineInstr *MI, const ARMBaseInstrInfo &TII, const unsigned *CSRegs) { - - // Integer spill area is handled with pop. - if (MI->getOpcode() == ARM::tRestore || - MI->getOpcode() == ARM::tPOP) { - // The first two operands are predicates. The last two are - // imp-def and imp-use of SP. Check everything in between. - for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) - if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) - return false; - return true; - } - - // Or if this is a fp reg spill. - if (MI->getOpcode() == (int)ARM::VLDRD && - MI->getOperand(1).isFI() && - isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) - return true; - - return false; + return ((MI->getOpcode() == (int)ARM::VLDRD || + MI->getOpcode() == (int)ARM::LDRi12 || + MI->getOpcode() == (int)ARM::t2LDRi12) && + MI->getOperand(1).isFI() && + isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); } void ARMBaseRegisterInfo:: @@ -1957,8 +1945,12 @@ emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); // Move SP to start of integer callee save spill area 1. - movePastCSLoadStoreOps(MBB, MBBI, ARM::tPOP, 0, 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); + + // Move SP to SP upon entry to the function. + movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI); + emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); } if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=118827&r1=118826&r2=118827&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Nov 11 13:47:02 2010 @@ -44,20 +44,6 @@ } } -/// isARMPushRegister - Returns true if the register is a low register (r0-r7) -/// or a stack/pc register that we should push/pop. -static inline bool isARMPushRegister(unsigned Reg) { - using namespace ARM; - switch (Reg) { - case R0: case R1: case R2: case R3: - case R4: case R5: case R6: case R7: - case LR: case SP: case PC: - return true; - default: - return false; - } -} - class ARMBaseRegisterInfo : public ARMGenRegisterInfo { protected: const ARMBaseInstrInfo &TII; Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=118827&r1=118826&r2=118827&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Nov 11 13:47:02 2010 @@ -148,7 +148,7 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) + if (!Subtarget.isThumb1Only()) PM.add(createARMLoadStoreOptimizationPass(true)); return true; @@ -157,12 +157,11 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None) { - if (!Subtarget.isThumb1Only()) - PM.add(createARMLoadStoreOptimizationPass()); - if (Subtarget.hasNEON()) - PM.add(createNEONMoveFixPass()); - } + if (!Subtarget.isThumb1Only()) + PM.add(createARMLoadStoreOptimizationPass()); + + if (OptLevel != CodeGenOpt::None && Subtarget.hasNEON()) + PM.add(createNEONMoveFixPass()); // Expand some pseudo instructions into multiple instructions to allow // proper scheduling. From grosbach at apple.com Thu Nov 11 14:05:40 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 20:05:40 -0000 Subject: [llvm-commits] [llvm] r118829 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td utils/TableGen/EDEmitter.cpp Message-ID: <20101111200540.A9AE02A6C12C@llvm.org> Author: grosbach Date: Thu Nov 11 14:05:40 2010 New Revision: 118829 URL: http://llvm.org/viewvc/llvm-project?rev=118829&view=rev Log: ARM fixup encoding for direct call instructions (BL). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118829&r1=118828&r2=118829&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 11 14:05:40 2010 @@ -278,6 +278,12 @@ string EncoderMethod = "getBranchTargetOpValue"; } +// Call target. +def bltarget : Operand { + // Encoded the same as branch targets. + string EncoderMethod = "getBranchTargetOpValue"; +} + // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand { string EncoderMethod = "getRegisterListOpValue"; @@ -1198,18 +1204,22 @@ D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { - def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsNotDarwin]> { let Inst{31-28} = 0b1110; - // FIXME: Encoding info for $func. Needs fixups bits. + bits<24> func; + let Inst{23-0} = func; } - def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, - Requires<[IsARM, IsNotDarwin]>; + Requires<[IsARM, IsNotDarwin]> { + bits<24> func; + let Inst{23-0} = func; + } // ARMv5T and above def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, @@ -1249,17 +1259,21 @@ D0, D1, D2, D3, D4, D5, D6, D7, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { - def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> { let Inst{31-28} = 0b1110; - // FIXME: Encoding info for $func. Needs fixups bits. + bits<24> func; + let Inst{23-0} = func; } - def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), + def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, - Requires<[IsARM, IsDarwin]>; + Requires<[IsARM, IsDarwin]> { + bits<24> func; + let Inst{23-0} = func; + } // ARMv5T and above def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=118829&r1=118828&r2=118829&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Thu Nov 11 14:05:40 2010 @@ -322,6 +322,7 @@ PCR("offset32"); PCR("offset64"); PCR("brtarget"); + PCR("bltarget"); return 1; } @@ -584,6 +585,7 @@ IMM("neon_vcvt_imm32"); MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? + MISC("bltarget", "kOperandTypeARMBranchTarget"); // ? MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I MISC("shift_so_reg", "kOperandTypeARMSoReg"); // R, R, I MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I From grosbach at apple.com Thu Nov 11 14:16:23 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 20:16:23 -0000 Subject: [llvm-commits] [llvm] r118831 - /llvm/trunk/lib/MC/MachObjectWriter.cpp Message-ID: <20101111201623.571CA2A6C12C@llvm.org> Author: grosbach Date: Thu Nov 11 14:16:23 2010 New Revision: 118831 URL: http://llvm.org/viewvc/llvm-project?rev=118831&view=rev Log: Trailing whitespace. Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=118831&r1=118830&r2=118831&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Nov 11 14:16:23 2010 @@ -633,7 +633,7 @@ if (A_Base == B_Base && A_Base) report_fatal_error("unsupported relocation with identical base"); - Value += Layout.getSymbolAddress(&A_SD) - + Value += Layout.getSymbolAddress(&A_SD) - (A_Base == NULL ? 0 : Layout.getSymbolAddress(A_Base)); Value -= Layout.getSymbolAddress(&B_SD) - (B_Base == NULL ? 0 : Layout.getSymbolAddress(B_Base)); @@ -875,7 +875,7 @@ } else { FixedValue = 0; } - + // struct relocation_info (8 bytes) MachRelocationEntry MRE; MRE.Word0 = Value; @@ -886,7 +886,7 @@ (RIT_TLV << 28)); // Type Relocations[Fragment->getParent()].push_back(MRE); } - + void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target, uint64_t &FixedValue) { @@ -904,7 +904,7 @@ RecordTLVPRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue); return; } - + // If this is a difference or a defined symbol plus an offset, then we need // a scattered relocation entry. // Differences always require scattered relocations. @@ -988,7 +988,7 @@ // Initialize the section indirect symbol base, if necessary. if (!IndirectSymBase.count(it->SectionData)) IndirectSymBase[it->SectionData] = IndirectIndex; - + Asm.getOrCreateSymbolData(*it->Symbol); } From echristo at apple.com Thu Nov 11 14:50:14 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 20:50:14 -0000 Subject: [llvm-commits] [llvm] r118835 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Message-ID: <20101111205014.AC1EE2A6C12C@llvm.org> Author: echristo Date: Thu Nov 11 14:50:14 2010 New Revision: 118835 URL: http://llvm.org/viewvc/llvm-project?rev=118835&view=rev Log: Revert the accidental commit I made reverting the previous commit. Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=118835&r1=118834&r2=118835&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Nov 11 14:50:14 2010 @@ -148,7 +148,7 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (!Subtarget.isThumb1Only()) + if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) PM.add(createARMLoadStoreOptimizationPass(true)); return true; @@ -157,11 +157,12 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (!Subtarget.isThumb1Only()) - PM.add(createARMLoadStoreOptimizationPass()); - - if (OptLevel != CodeGenOpt::None && Subtarget.hasNEON()) - PM.add(createNEONMoveFixPass()); + if (OptLevel != CodeGenOpt::None) { + if (!Subtarget.isThumb1Only()) + PM.add(createARMLoadStoreOptimizationPass()); + if (Subtarget.hasNEON()) + PM.add(createNEONMoveFixPass()); + } // Expand some pseudo instructions into multiple instructions to allow // proper scheduling. From gohman at apple.com Thu Nov 11 15:08:46 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 21:08:46 -0000 Subject: [llvm-commits] [llvm] r118836 - in /llvm/trunk/test/Analysis: BasicAA/2009-10-13-GEP-BaseNoAlias.ll BasicAA/phi-aa.ll TypeBasedAliasAnalysis/precedence.ll Message-ID: <20101111210846.D5C782A6C12C@llvm.org> Author: djg Date: Thu Nov 11 15:08:46 2010 New Revision: 118836 URL: http://llvm.org/viewvc/llvm-project?rev=118836&view=rev Log: Delete unneeded ssp attributes. Modified: llvm/trunk/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll llvm/trunk/test/Analysis/BasicAA/phi-aa.ll llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Modified: llvm/trunk/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll?rev=118836&r1=118835&r2=118836&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll Thu Nov 11 15:08:46 2010 @@ -5,7 +5,7 @@ @Y = common global i32 0 @Z = common global i32 0 -define void @foo(i32 %cond) nounwind ssp { +define void @foo(i32 %cond) nounwind { entry: %a = alloca i32 %tmp = icmp ne i32 %cond, 0 Modified: llvm/trunk/test/Analysis/BasicAA/phi-aa.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/phi-aa.ll?rev=118836&r1=118835&r2=118836&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/phi-aa.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/phi-aa.ll Thu Nov 11 15:08:46 2010 @@ -5,7 +5,7 @@ @Y = common global i32 0 @Z = common global i32 0 -define void @foo(i32 %cond) nounwind ssp { +define void @foo(i32 %cond) nounwind { entry: %"alloca point" = bitcast i32 0 to i32 %tmp = icmp ne i32 %cond, 0 Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll?rev=118836&r1=118835&r2=118836&view=diff ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll (original) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Thu Nov 11 15:08:46 2010 @@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64" -define i32 @trouble(i32* %x) nounwind ssp { +define i32 @trouble(i32* %x) nounwind { entry: store i32 0, i32* %x, !tbaa !0 %0 = bitcast i32* %x to float* From resistor at mac.com Thu Nov 11 15:15:47 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 11 Nov 2010 21:15:47 -0000 Subject: [llvm-commits] [llvm] r118837 - in /llvm/trunk/test/MC/ARM: neont2-cmp-encoding.s neont2-minmax-encoding.s neont2-mul-encoding.s neont2-neg-encoding.s neont2-reciprocal-encoding.s neont2-reverse-encoding.s neont2-satshift-encoding.s neont2-shift-encoding.s neont2-shiftaccum-encoding.s neont2-shuffle-encoding.s neont2-sub-encoding.s Message-ID: <20101111211547.96FE42A6C12C@llvm.org> Author: resistor Date: Thu Nov 11 15:15:47 2010 New Revision: 118837 URL: http://llvm.org/viewvc/llvm-project?rev=118837&view=rev Log: Flesh out tests for Thumb2 encodings of NEON instructions. Added: llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s llvm/trunk/test/MC/ARM/neont2-mul-encoding.s llvm/trunk/test/MC/ARM/neont2-neg-encoding.s llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s llvm/trunk/test/MC/ARM/neont2-shift-encoding.s llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s llvm/trunk/test/MC/ARM/neont2-sub-encoding.s Added: llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,36 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xff] + vcvt.s32.f32 d16, d16 +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xff] + vcvt.u32.f32 d16, d16 +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xff] + vcvt.f32.s32 d16, d16 +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xff] + vcvt.f32.u32 d16, d16 +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xff] + vcvt.s32.f32 q8, q8 +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xff] + vcvt.u32.f32 q8, q8 +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xff] + vcvt.f32.s32 q8, q8 +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xff] + vcvt.f32.u32 q8, q8 +@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xef] + vcvt.s32.f32 d16, d16, #1 +@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xff] + vcvt.u32.f32 d16, d16, #1 +@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xef] + vcvt.f32.s32 d16, d16, #1 +@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xff] + vcvt.f32.u32 d16, d16, #1 +@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xef] + vcvt.s32.f32 q8, q8, #1 +@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xff] + vcvt.u32.f32 q8, q8, #1 +@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xef] + vcvt.f32.s32 q8, q8, #1 +@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xff] + vcvt.f32.u32 q8, q8, #1 Added: llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,60 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xef] + vmin.s8 d16, d16, d17 +@ CHECK: vmin.s16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xef] + vmin.s16 d16, d16, d17 +@ CHECK: vmin.s32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xef] + vmin.s32 d16, d16, d17 +@ CHECK: vmin.u8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xff] + vmin.u8 d16, d16, d17 +@ CHECK: vmin.u16 d16, d16, d17 @ encoding: [0xb1,0x06,0x50,0xff] + vmin.u16 d16, d16, d17 +@ CHECK: vmin.u32 d16, d16, d17 @ encoding: [0xb1,0x06,0x60,0xff] + vmin.u32 d16, d16, d17 +@ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xef] + vmin.f32 d16, d16, d17 +@ CHECK: vmin.s8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xef] + vmin.s8 q8, q8, q9 +@ CHECK: vmin.s16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xef] + vmin.s16 q8, q8, q9 +@ CHECK: vmin.s32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xef] + vmin.s32 q8, q8, q9 +@ CHECK: vmin.u8 q8, q8, q9 @ encoding: [0xf2,0x06,0x40,0xff] + vmin.u8 q8, q8, q9 +@ CHECK: vmin.u16 q8, q8, q9 @ encoding: [0xf2,0x06,0x50,0xff] + vmin.u16 q8, q8, q9 +@ CHECK: vmin.u32 q8, q8, q9 @ encoding: [0xf2,0x06,0x60,0xff] + vmin.u32 q8, q8, q9 +@ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xef] + vmin.f32 q8, q8, q9 +@ CHECK: vmax.s8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xef] + vmax.s8 d16, d16, d17 +@ CHECK: vmax.s16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xef] + vmax.s16 d16, d16, d17 +@ CHECK: vmax.s32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xef] + vmax.s32 d16, d16, d17 +@ CHECK: vmax.u8 d16, d16, d17 @ encoding: [0xa1,0x06,0x40,0xff] + vmax.u8 d16, d16, d17 +@ CHECK: vmax.u16 d16, d16, d17 @ encoding: [0xa1,0x06,0x50,0xff] + vmax.u16 d16, d16, d17 +@ CHECK: vmax.u32 d16, d16, d17 @ encoding: [0xa1,0x06,0x60,0xff] + vmax.u32 d16, d16, d17 +@ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xef] + vmax.f32 d16, d16, d17 +@ CHECK: vmax.s8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xef] + vmax.s8 q8, q8, q9 +@ CHECK: vmax.s16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xef] + vmax.s16 q8, q8, q9 +@ CHECK: vmax.s32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xef] + vmax.s32 q8, q8, q9 +@ CHECK: vmax.u8 q8, q8, q9 @ encoding: [0xe2,0x06,0x40,0xff] + vmax.u8 q8, q8, q9 +@ CHECK: vmax.u16 q8, q8, q9 @ encoding: [0xe2,0x06,0x50,0xff] + vmax.u16 q8, q8, q9 +@ CHECK: vmax.u32 q8, q8, q9 @ encoding: [0xe2,0x06,0x60,0xff] + vmax.u32 q8, q8, q9 +@ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xef] + vmax.f32 q8, q8, q9 Added: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,58 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xef] + vmul.i8 d16, d16, d17 +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xef] + vmul.i16 d16, d16, d17 +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xef] + vmul.i32 d16, d16, d17 +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xff] + vmul.f32 d16, d16, d17 +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xef] + vmul.i8 q8, q8, q9 +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xef] + vmul.i16 q8, q8, q9 +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xef] + vmul.i32 q8, q8, q9 +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xff] + vmul.f32 q8, q8, q9 +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xff] + vmul.p8 d16, d16, d17 +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xff] + vmul.p8 q8, q8, q9 +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xef] + vqdmulh.s16 d16, d16, d17 +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xef] + vqdmulh.s32 d16, d16, d17 +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xef] + vqdmulh.s16 q8, q8, q9 +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xef] + vqdmulh.s32 q8, q8, q9 +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xff] + vqrdmulh.s16 d16, d16, d17 +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xff] + vqrdmulh.s32 d16, d16, d17 +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xff] + vqrdmulh.s16 q8, q8, q9 +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xff] + vqrdmulh.s32 q8, q8, q9 +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xef] + vmull.s8 q8, d16, d17 +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xef] + vmull.s16 q8, d16, d17 +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xef] + vmull.s32 q8, d16, d17 +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xff] + vmull.u8 q8, d16, d17 +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xff] + vmull.u16 q8, d16, d17 +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xff] + vmull.u32 q8, d16, d17 +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xef] + vmull.p8 q8, d16, d17 +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xef] + vqdmull.s16 q8, d16, d17 +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xef] + vqdmull.s32 q8, d16, d17 Added: llvm/trunk/test/MC/ARM/neont2-neg-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-neg-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-neg-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-neg-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,32 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xff] + vneg.s8 d16, d16 +@ CHECK: vneg.s16 d16, d16 @ encoding: [0xa0,0x03,0xf5,0xff] + vneg.s16 d16, d16 +@ CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xff] + vneg.s32 d16, d16 +@ CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xff] + vneg.f32 d16, d16 +@ CHECK: vneg.s8 q8, q8 @ encoding: [0xe0,0x03,0xf1,0xff] + vneg.s8 q8, q8 +@ CHECK: vneg.s16 q8, q8 @ encoding: [0xe0,0x03,0xf5,0xff] + vneg.s16 q8, q8 +@ CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xff] + vneg.s32 q8, q8 +@ CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xff] + vneg.f32 q8, q8 +@ CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xff] + vqneg.s8 d16, d16 +@ CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xff] + vqneg.s16 d16, d16 +@ CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xff] + vqneg.s32 d16, d16 +@ CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xff] + vqneg.s8 q8, q8 +@ CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xff] + vqneg.s16 q8, q8 +@ CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xff] + vqneg.s32 q8, q8 Added: llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,28 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xff] + vrecpe.u32 d16, d16 +@ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xff] + vrecpe.u32 q8, q8 +@ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xff] + vrecpe.f32 d16, d16 +@ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xff] + vrecpe.f32 q8, q8 +@ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xef] + vrecps.f32 d16, d16, d17 +@ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xef] + vrecps.f32 q8, q8, q9 +@ CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xff] + vrsqrte.u32 d16, d16 +@ CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xff] + vrsqrte.u32 q8, q8 +@ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xff] + vrsqrte.f32 d16, d16 +@ CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xff] + vrsqrte.f32 q8, q8 +@ CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xef] + vrsqrts.f32 d16, d16, d17 +@ CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xef] + vrsqrts.f32 q8, q8, q9 Added: llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,26 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +@ CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xff] + vrev64.8 d16, d16 +@ CHECK: vrev64.16 d16, d16 @ encoding: [0x20,0x00,0xf4,0xff] + vrev64.16 d16, d16 +@ CHECK: vrev64.32 d16, d16 @ encoding: [0x20,0x00,0xf8,0xff] + vrev64.32 d16, d16 +@ CHECK: vrev64.8 q8, q8 @ encoding: [0x60,0x00,0xf0,0xff] + vrev64.8 q8, q8 +@ CHECK: vrev64.16 q8, q8 @ encoding: [0x60,0x00,0xf4,0xff] + vrev64.16 q8, q8 +@ CHECK: vrev64.32 q8, q8 @ encoding: [0x60,0x00,0xf8,0xff] + vrev64.32 q8, q8 +@ CHECK: vrev32.8 d16, d16 @ encoding: [0xa0,0x00,0xf0,0xff] + vrev32.8 d16, d16 +@ CHECK: vrev32.16 d16, d16 @ encoding: [0xa0,0x00,0xf4,0xff] + vrev32.16 d16, d16 +@ CHECK: vrev32.8 q8, q8 @ encoding: [0xe0,0x00,0xf0,0xff] + vrev32.8 q8, q8 +@ CHECK: vrev32.16 q8, q8 @ encoding: [0xe0,0x00,0xf4,0xff] + vrev32.16 q8, q8 +@ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xff] + vrev16.8 d16, d16 +@ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xff] + vrev16.8 q8, q8 Added: llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,152 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xef] + vqshl.s8 d16, d16, d17 +@ CHECK: vqshl.s16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xef] + vqshl.s16 d16, d16, d17 +@ CHECK: vqshl.s32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xef] + vqshl.s32 d16, d16, d17 +@ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xef] + vqshl.s64 d16, d16, d17 +@ CHECK: vqshl.u8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xff] + vqshl.u8 d16, d16, d17 +@ CHECK: vqshl.u16 d16, d16, d17 @ encoding: [0xb0,0x04,0x51,0xff] + vqshl.u16 d16, d16, d17 +@ CHECK: vqshl.u32 d16, d16, d17 @ encoding: [0xb0,0x04,0x61,0xff] + vqshl.u32 d16, d16, d17 +@ CHECK: vqshl.u64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xff] + vqshl.u64 d16, d16, d17 +@ CHECK: vqshl.s8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xef] + vqshl.s8 q8, q8, q9 +@ CHECK: vqshl.s16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xef] + vqshl.s16 q8, q8, q9 +@ CHECK: vqshl.s32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xef] + vqshl.s32 q8, q8, q9 +@ CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xef] + vqshl.s64 q8, q8, q9 +@ CHECK: vqshl.u8 q8, q8, q9 @ encoding: [0xf0,0x04,0x42,0xff] + vqshl.u8 q8, q8, q9 +@ CHECK: vqshl.u16 q8, q8, q9 @ encoding: [0xf0,0x04,0x52,0xff] + vqshl.u16 q8, q8, q9 +@ CHECK: vqshl.u32 q8, q8, q9 @ encoding: [0xf0,0x04,0x62,0xff] + vqshl.u32 q8, q8, q9 +@ CHECK: vqshl.u64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xff] + vqshl.u64 q8, q8, q9 +@ CHECK: vqshl.s8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xef] + vqshl.s8 d16, d16, #7 +@ CHECK: vqshl.s16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xef] + vqshl.s16 d16, d16, #15 +@ CHECK: vqshl.s32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xef] + vqshl.s32 d16, d16, #31 +@ CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xef] + vqshl.s64 d16, d16, #63 +@ CHECK: vqshl.u8 d16, d16, #7 @ encoding: [0x30,0x07,0xcf,0xff] + vqshl.u8 d16, d16, #7 +@ CHECK: vqshl.u16 d16, d16, #15 @ encoding: [0x30,0x07,0xdf,0xff] + vqshl.u16 d16, d16, #15 +@ CHECK: vqshl.u32 d16, d16, #31 @ encoding: [0x30,0x07,0xff,0xff] + vqshl.u32 d16, d16, #31 +@ CHECK: vqshl.u64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xff] + vqshl.u64 d16, d16, #63 +@ CHECK: vqshlu.s8 d16, d16, #7 @ encoding: [0x30,0x06,0xcf,0xff] + vqshlu.s8 d16, d16, #7 +@ CHECK: vqshlu.s16 d16, d16, #15 @ encoding: [0x30,0x06,0xdf,0xff] + vqshlu.s16 d16, d16, #15 +@ CHECK: vqshlu.s32 d16, d16, #31 @ encoding: [0x30,0x06,0xff,0xff] + vqshlu.s32 d16, d16, #31 +@ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xff] + vqshlu.s64 d16, d16, #63 +@ CHECK: vqshl.s8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xef] + vqshl.s8 q8, q8, #7 +@ CHECK: vqshl.s16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xef] + vqshl.s16 q8, q8, #15 +@ CHECK: vqshl.s32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xef] + vqshl.s32 q8, q8, #31 +@ CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xef] + vqshl.s64 q8, q8, #63 +@ CHECK: vqshl.u8 q8, q8, #7 @ encoding: [0x70,0x07,0xcf,0xff] + vqshl.u8 q8, q8, #7 +@ CHECK: vqshl.u16 q8, q8, #15 @ encoding: [0x70,0x07,0xdf,0xff] + vqshl.u16 q8, q8, #15 +@ CHECK: vqshl.u32 q8, q8, #31 @ encoding: [0x70,0x07,0xff,0xff] + vqshl.u32 q8, q8, #31 +@ CHECK: vqshl.u64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xff] + vqshl.u64 q8, q8, #63 +@ CHECK: vqshlu.s8 q8, q8, #7 @ encoding: [0x70,0x06,0xcf,0xff] + vqshlu.s8 q8, q8, #7 +@ CHECK: vqshlu.s16 q8, q8, #15 @ encoding: [0x70,0x06,0xdf,0xff] + vqshlu.s16 q8, q8, #15 +@ CHECK: vqshlu.s32 q8, q8, #31 @ encoding: [0x70,0x06,0xff,0xff] + vqshlu.s32 q8, q8, #31 +@ CHECK: vqshlu.s64 q8, q8, #63 @ encoding: [0xf0,0x06,0xff,0xff] + vqshlu.s64 q8, q8, #63 +@ CHECK: vqrshl.s8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xef] + vqrshl.s8 d16, d16, d17 +@ CHECK: vqrshl.s16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xef] + vqrshl.s16 d16, d16, d17 +@ CHECK: vqrshl.s32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xef] + vqrshl.s32 d16, d16, d17 +@ CHECK: vqrshl.s64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xef] + vqrshl.s64 d16, d16, d17 +@ CHECK: vqrshl.u8 d16, d16, d17 @ encoding: [0xb0,0x05,0x41,0xff] + vqrshl.u8 d16, d16, d17 +@ CHECK: vqrshl.u16 d16, d16, d17 @ encoding: [0xb0,0x05,0x51,0xff] + vqrshl.u16 d16, d16, d17 +@ CHECK: vqrshl.u32 d16, d16, d17 @ encoding: [0xb0,0x05,0x61,0xff] + vqrshl.u32 d16, d16, d17 +@ CHECK: vqrshl.u64 d16, d16, d17 @ encoding: [0xb0,0x05,0x71,0xff] + vqrshl.u64 d16, d16, d17 +@ CHECK: vqrshl.s8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xef] + vqrshl.s8 q8, q8, q9 +@ CHECK: vqrshl.s16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xef] + vqrshl.s16 q8, q8, q9 +@ CHECK: vqrshl.s32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xef] + vqrshl.s32 q8, q8, q9 +@ CHECK: vqrshl.s64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xef] + vqrshl.s64 q8, q8, q9 +@ CHECK: vqrshl.u8 q8, q8, q9 @ encoding: [0xf0,0x05,0x42,0xff] + vqrshl.u8 q8, q8, q9 +@ CHECK: vqrshl.u16 q8, q8, q9 @ encoding: [0xf0,0x05,0x52,0xff] + vqrshl.u16 q8, q8, q9 +@ CHECK: vqrshl.u32 q8, q8, q9 @ encoding: [0xf0,0x05,0x62,0xff] + vqrshl.u32 q8, q8, q9 +@ CHECK: vqrshl.u64 q8, q8, q9 @ encoding: [0xf0,0x05,0x72,0xff] + vqrshl.u64 q8, q8, q9 +@ CHECK: vqshrn.s16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xef] + vqshrn.s16 d16, q8, #8 +@ CHECK: vqshrn.s32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xef] + vqshrn.s32 d16, q8, #16 +@ CHECK: vqshrn.s64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xef] + vqshrn.s64 d16, q8, #32 +@ CHECK: vqshrn.u16 d16, q8, #8 @ encoding: [0x30,0x09,0xc8,0xff] + vqshrn.u16 d16, q8, #8 +@ CHECK: vqshrn.u32 d16, q8, #16 @ encoding: [0x30,0x09,0xd0,0xff] + vqshrn.u32 d16, q8, #16 +@ CHECK: vqshrn.u64 d16, q8, #32 @ encoding: [0x30,0x09,0xe0,0xff] + vqshrn.u64 d16, q8, #32 +@ CHECK: vqshrun.s16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xff] + vqshrun.s16 d16, q8, #8 +@ CHECK: vqshrun.s32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xff] + vqshrun.s32 d16, q8, #16 +@ CHECK: vqshrun.s64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xff] + vqshrun.s64 d16, q8, #32 +@ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xef] + vqrshrn.s16 d16, q8, #8 +@ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xef] + vqrshrn.s32 d16, q8, #16 +@ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xef] + vqrshrn.s64 d16, q8, #32 +@ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xff] + vqrshrn.u16 d16, q8, #8 +@ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xff] + vqrshrn.u32 d16, q8, #16 +@ CHECK: vqrshrn.u64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xff] + vqrshrn.u64 d16, q8, #32 +@ CHECK: vqrshrun.s16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xff] + vqrshrun.s16 d16, q8, #8 +@ CHECK: vqrshrun.s32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xff] + vqrshrun.s32 d16, q8, #16 +@ CHECK: vqrshrun.s64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xff] + vqrshrun.s64 d16, q8, #32 Added: llvm/trunk/test/MC/ARM/neont2-shift-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-shift-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-shift-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-shift-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,162 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xff] + vshl.u8 d16, d17, d16 +@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xff] + vshl.u16 d16, d17, d16 +@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xff] + vshl.u32 d16, d17, d16 +@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xff] + vshl.u64 d16, d17, d16 +@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xef] + vshl.i8 d16, d16, #7 +@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xef] + vshl.i16 d16, d16, #15 +@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xef] + vshl.i32 d16, d16, #31 +@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xef] + vshl.i64 d16, d16, #63 +@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xff] + vshl.u8 q8, q9, q8 +@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xff] + vshl.u16 q8, q9, q8 +@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xff] + vshl.u32 q8, q9, q8 +@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xff] + vshl.u64 q8, q9, q8 +@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xef] + vshl.i8 q8, q8, #7 +@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xef] + vshl.i16 q8, q8, #15 +@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xef] + vshl.i32 q8, q8, #31 +@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xef] + vshl.i64 q8, q8, #63 +@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xff] + vshr.u8 d16, d16, #8 +@ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xff] + vshr.u16 d16, d16, #16 +@ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xff] + vshr.u32 d16, d16, #32 +@ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xff] + vshr.u64 d16, d16, #64 +@ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xff] + vshr.u8 q8, q8, #8 +@ CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xff] + vshr.u16 q8, q8, #16 +@ CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xff] + vshr.u32 q8, q8, #32 +@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xff] + vshr.u64 q8, q8, #64 +@ CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xef] + vshr.s8 d16, d16, #8 +@ CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xef] + vshr.s16 d16, d16, #16 +@ CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xef] + vshr.s32 d16, d16, #32 +@ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xef] + vshr.s64 d16, d16, #64 +@ CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xef] + vshr.s8 q8, q8, #8 +@ CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xef] + vshr.s16 q8, q8, #16 +@ CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xef] + vshr.s32 q8, q8, #32 +@ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xef] + vshr.s64 q8, q8, #64 +@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xef] + vshll.s8 q8, d16, #7 +@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xef] + vshll.s16 q8, d16, #15 +@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xef] + vshll.s32 q8, d16, #31 +@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xff] + vshll.u8 q8, d16, #7 +@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xff] + vshll.u16 q8, d16, #15 +@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xff] + vshll.u32 q8, d16, #31 +@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xff] + vshll.i8 q8, d16, #8 +@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xff] + vshll.i16 q8, d16, #16 +@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xff] + vshll.i32 q8, d16, #32 +@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xef] + vshrn.i16 d16, q8, #8 +@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xef] + vshrn.i32 d16, q8, #16 +@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xef] + vshrn.i64 d16, q8, #32 +@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xef] + vrshl.s8 d16, d17, d16 +@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xef] + vrshl.s16 d16, d17, d16 +@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xef] + vrshl.s32 d16, d17, d16 +@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0 + vrshl.s64 d16, d17, d16 +@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xff] + vrshl.u8 d16, d17, d16 +@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xff] + vrshl.u16 d16, d17, d16 +@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xff] + vrshl.u32 d16, d17, d16 +@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xff] + vrshl.u64 d16, d17, d16 +@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xef] + vrshl.s8 q8, q9, q8 +@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xef] + vrshl.s16 q8, q9, q8 +@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xef] + vrshl.s32 q8, q9, q8 +@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xef] + vrshl.s64 q8, q9, q8 +@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xff] + vrshl.u8 q8, q9, q8 +@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xff] + vrshl.u16 q8, q9, q8 +@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xff] + vrshl.u32 q8, q9, q8 +@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xff] + vrshl.u64 q8, q9, q8 +@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xef] + vrshr.s8 d16, d16, #8 +@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xef] + vrshr.s16 d16, d16, #16 +@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xef] + vrshr.s32 d16, d16, #32 +@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xef] + vrshr.s64 d16, d16, #64 +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xff] + vrshr.u8 d16, d16, #8 +@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xff] + vrshr.u16 d16, d16, #16 +@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xff] + vrshr.u32 d16, d16, #32 +@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xff] + vrshr.u64 d16, d16, #64 +@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xef] + vrshr.s8 q8, q8, #8 +@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xef] + vrshr.s16 q8, q8, #16 +@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xef] + vrshr.s32 q8, q8, #32 +@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xef] + vrshr.s64 q8, q8, #64 +@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xff] + vrshr.u8 q8, q8, #8 +@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xff] + vrshr.u16 q8, q8, #16 +@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xff] + vrshr.u32 q8, q8, #32 +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xff] + vrshr.u64 q8, q8, #64 +@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xef] + vrshrn.i16 d16, q8, #8 +@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xef] + vrshrn.i32 d16, q8, #16 +@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xef] + vrshrn.i64 d16, q8, #32 Added: llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,100 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vsra.s8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xef] + vsra.s8 d17, d16, #8 +@ CHECK: vsra.s16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xef] + vsra.s16 d17, d16, #16 +@ CHECK: vsra.s32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xef] + vsra.s32 d17, d16, #32 +@ CHECK: vsra.s64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xef] + vsra.s64 d17, d16, #64 +@ CHECK: vsra.s8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xef] + vsra.s8 q8, q9, #8 +@ CHECK: vsra.s16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xef] + vsra.s16 q8, q9, #16 +@ CHECK: vsra.s32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xef] + vsra.s32 q8, q9, #32 +@ CHECK: vsra.s64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xef] + vsra.s64 q8, q9, #64 +@ CHECK: vsra.u8 d17, d16, #8 @ encoding: [0x30,0x11,0xc8,0xff] + vsra.u8 d17, d16, #8 +@ CHECK: vsra.u16 d17, d16, #16 @ encoding: [0x30,0x11,0xd0,0xff] + vsra.u16 d17, d16, #16 +@ CHECK: vsra.u32 d17, d16, #32 @ encoding: [0x30,0x11,0xe0,0xff] + vsra.u32 d17, d16, #32 +@ CHECK: vsra.u64 d17, d16, #64 @ encoding: [0xb0,0x11,0xc0,0xff] + vsra.u64 d17, d16, #64 +@ CHECK: vsra.u8 q8, q9, #8 @ encoding: [0x72,0x01,0xc8,0xff] + vsra.u8 q8, q9, #8 +@ CHECK: vsra.u16 q8, q9, #16 @ encoding: [0x72,0x01,0xd0,0xff] + vsra.u16 q8, q9, #16 +@ CHECK: vsra.u32 q8, q9, #32 @ encoding: [0x72,0x01,0xe0,0xff] + vsra.u32 q8, q9, #32 +@ CHECK: vsra.u64 q8, q9, #64 @ encoding: [0xf2,0x01,0xc0,0xff] + vsra.u64 q8, q9, #64 +@ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xef] + vrsra.s8 d17, d16, #8 +@ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xef] + vrsra.s16 d17, d16, #16 +@ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xef] + vrsra.s32 d17, d16, #32 +@ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xef] + vrsra.s64 d17, d16, #64 +@ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xff] + vrsra.u8 d17, d16, #8 +@ CHECK: vrsra.u16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xff] + vrsra.u16 d17, d16, #16 +@ CHECK: vrsra.u32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xff] + vrsra.u32 d17, d16, #32 +@ CHECK: vrsra.u64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xff] + vrsra.u64 d17, d16, #64 +@ CHECK: vrsra.s8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xef] + vrsra.s8 q8, q9, #8 +@ CHECK: vrsra.s16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xef] + vrsra.s16 q8, q9, #16 +@ CHECK: vrsra.s32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xef] + vrsra.s32 q8, q9, #32 +@ CHECK: vrsra.s64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xef] + vrsra.s64 q8, q9, #64 +@ CHECK: vrsra.u8 q8, q9, #8 @ encoding: [0x72,0x03,0xc8,0xff] + vrsra.u8 q8, q9, #8 +@ CHECK: vrsra.u16 q8, q9, #16 @ encoding: [0x72,0x03,0xd0,0xff] + vrsra.u16 q8, q9, #16 +@ CHECK: vrsra.u32 q8, q9, #32 @ encoding: [0x72,0x03,0xe0,0xff] + vrsra.u32 q8, q9, #32 +@ CHECK: vrsra.u64 q8, q9, #64 @ encoding: [0xf2,0x03,0xc0,0xff] + vrsra.u64 q8, q9, #64 +@ CHECK: vsli.8 d17, d16, #7 @ encoding: [0x30,0x15,0xcf,0xff] + vsli.8 d17, d16, #7 +@ CHECK: vsli.16 d17, d16, #15 @ encoding: [0x30,0x15,0xdf,0xff] + vsli.16 d17, d16, #15 +@ CHECK: vsli.32 d17, d16, #31 @ encoding: [0x30,0x15,0xff,0xff] + vsli.32 d17, d16, #31 +@ CHECK: vsli.64 d17, d16, #63 @ encoding: [0xb0,0x15,0xff,0xff] + vsli.64 d17, d16, #63 +@ CHECK: vsli.8 q9, q8, #7 @ encoding: [0x70,0x25,0xcf,0xff] + vsli.8 q9, q8, #7 +@ CHECK: vsli.16 q9, q8, #15 @ encoding: [0x70,0x25,0xdf,0xff] + vsli.16 q9, q8, #15 +@ CHECK: vsli.32 q9, q8, #31 @ encoding: [0x70,0x25,0xff,0xff] + vsli.32 q9, q8, #31 +@ CHECK: vsli.64 q9, q8, #63 @ encoding: [0xf0,0x25,0xff,0xff] + vsli.64 q9, q8, #63 +@ CHECK: vsri.8 d17, d16, #8 @ encoding: [0x30,0x14,0xc8,0xff] + vsri.8 d17, d16, #8 +@ CHECK: vsri.16 d17, d16, #16 @ encoding: [0x30,0x14,0xd0,0xff] + vsri.16 d17, d16, #16 +@ CHECK: vsri.32 d17, d16, #32 @ encoding: [0x30,0x14,0xe0,0xff] + vsri.32 d17, d16, #32 +@ CHECK: vsri.64 d17, d16, #64 @ encoding: [0xb0,0x14,0xc0,0xff] + vsri.64 d17, d16, #64 +@ CHECK: vsri.8 q9, q8, #8 @ encoding: [0x70,0x24,0xc8,0xff] + vsri.8 q9, q8, #8 +@ CHECK: vsri.16 q9, q8, #16 @ encoding: [0x70,0x24,0xd0,0xff] + vsri.16 q9, q8, #16 +@ CHECK: vsri.32 q9, q8, #32 @ encoding: [0x70,0x24,0xe0,0xff] + vsri.32 q9, q8, #32 +@ CHECK: vsri.64 q9, q8, #64 @ encoding: [0xf0,0x24,0xc0,0xff] + vsri.64 q9, q8, #64 Added: llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,48 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xef] + vext.8 d16, d17, d16, #3 +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xef] + vext.8 d16, d17, d16, #5 +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xef] + vext.8 q8, q9, q8, #3 +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xef] + vext.8 q8, q9, q8, #7 +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xef] + vext.16 d16, d17, d16, #3 +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xef] + vext.32 q8, q9, q8, #3 +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xff] + vtrn.8 d17, d16 +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xff] + vtrn.16 d17, d16 +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xff] + vtrn.32 d17, d16 +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xe0,0x20,0xf2,0xff] + vtrn.8 q9, q8 +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xe0,0x20,0xf6,0xff] + vtrn.16 q9, q8 +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xff] + vtrn.32 q9, q8 +@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xff] + vuzp.8 d17, d16 +@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xff] + vuzp.16 d17, d16 +@ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xff] + vuzp.8 q9, q8 +@ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xff] + vuzp.16 q9, q8 +@ CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xff] + vuzp.32 q9, q8 +@ CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xff] + vzip.8 d17, d16 +@ CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xff] + vzip.16 d17, d16 +@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xff] + vzip.8 q9, q8 +@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xff] + vzip.16 q9, q8 +@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xff] + vzip.32 q9, q8 Added: llvm/trunk/test/MC/ARM/neont2-sub-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-sub-encoding.s?rev=118837&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-sub-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-sub-encoding.s Thu Nov 11 15:15:47 2010 @@ -0,0 +1,46 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xef] + vext.8 d16, d17, d16, #3 +@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xef] + vext.8 d16, d17, d16, #5 +@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xef] + vext.8 q8, q9, q8, #3 +@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xef] + vext.8 q8, q9, q8, #7 +@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xef] + vext.16 d16, d17, d16, #3 +@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xef] + vext.32 q8, q9, q8, #3 +@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xff] + vtrn.8 d17, d16 +@ CHECK: vtrn.16 d17, d16 @ encoding: [0xa0,0x10,0xf6,0xff] + vtrn.16 d17, d16 +@ CHECK: vtrn.32 d17, d16 @ encoding: [0xa0,0x10,0xfa,0xff] + vtrn.32 d17, d16 +@ CHECK: vtrn.8 q9, q8 @ encoding: [0xe0,0x20,0xf2,0xff] + vtrn.8 q9, q8 +@ CHECK: vtrn.16 q9, q8 @ encoding: [0xe0,0x20,0xf6,0xff] + vtrn.16 q9, q8 +@ CHECK: vtrn.32 q9, q8 @ encoding: [0xe0,0x20,0xfa,0xff] + vtrn.32 q9, q8 +@ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xff] + vuzp.8 d17, d16 +@ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xff] + vuzp.16 d17, d16 +@ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xff] + vuzp.8 q9, q8 +@ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xff] + vuzp.16 q9, q8 +@ CHECK: vuzp.32 q9, q8 @ encoding: [0x60,0x21,0xfa,0xff] + vuzp.32 q9, q8 +@ CHECK: vzip.8 d17, d16 @ encoding: [0xa0,0x11,0xf2,0xff] + vzip.8 d17, d16 +@ CHECK: vzip.16 d17, d16 @ encoding: [0xa0,0x11,0xf6,0xff] + vzip.16 d17, d16 +@ CHECK: vzip.8 q9, q8 @ encoding: [0xe0,0x21,0xf2,0xff] + vzip.8 q9, q8 +@ CHECK: vzip.16 q9, q8 @ encoding: [0xe0,0x21,0xf6,0xff] + vzip.16 q9, q8 +@ CHECK: vzip.32 q9, q8 @ encoding: [0xe0,0x21,0xfa,0xff] + vzip.32 q9, q8 From gohman at apple.com Thu Nov 11 15:23:25 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 21:23:25 -0000 Subject: [llvm-commits] [llvm] r118840 - in /llvm/trunk: include/llvm/Value.h lib/Transforms/IPO/ArgumentPromotion.cpp lib/VMCore/Instruction.cpp lib/VMCore/Value.cpp test/Transforms/SimplifyCFG/speculate-with-offset.ll Message-ID: <20101111212325.ED0082A6C12C@llvm.org> Author: djg Date: Thu Nov 11 15:23:25 2010 New Revision: 118840 URL: http://llvm.org/viewvc/llvm-project?rev=118840&view=rev Log: Factor out Instruction::isSafeToSpeculativelyExecute's code for testing for dereferenceable pointers into a helper function, isDereferenceablePointer. Teach it how to reason about GEPs with simple non-zero indices. Also eliminate ArgumentPromtion's IsAlwaysValidPointer, which didn't check for weak externals or out of range gep indices. Added: llvm/trunk/test/Transforms/SimplifyCFG/speculate-with-offset.ll Modified: llvm/trunk/include/llvm/Value.h llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp llvm/trunk/lib/VMCore/Instruction.cpp llvm/trunk/lib/VMCore/Value.cpp Modified: llvm/trunk/include/llvm/Value.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=118840&r1=118839&r2=118840&view=diff ============================================================================== --- llvm/trunk/include/llvm/Value.h (original) +++ llvm/trunk/include/llvm/Value.h Thu Nov 11 15:23:25 2010 @@ -294,6 +294,10 @@ const Value *getUnderlyingObject(unsigned MaxLookup = 6) const { return const_cast(this)->getUnderlyingObject(MaxLookup); } + + /// isDereferenceablePointer - Test if this value is always a pointer to + /// allocated and suitably aligned memory for a simple load or store. + bool isDereferenceablePointer() const; /// DoPHITranslation - If this value is a PHI node with CurBB as its parent, /// return the value in the PHI node corresponding to PredBB. If not, return Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=118840&r1=118839&r2=118840&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Thu Nov 11 15:23:25 2010 @@ -188,19 +188,6 @@ return DoPromotion(F, ArgsToPromote, ByValArgsToTransform); } -/// IsAlwaysValidPointer - Return true if the specified pointer is always legal -/// to load. -static bool IsAlwaysValidPointer(Value *V) { - if (isa(V) || isa(V)) return true; - if (GetElementPtrInst *GEP = dyn_cast(V)) - return IsAlwaysValidPointer(GEP->getOperand(0)); - if (ConstantExpr *CE = dyn_cast(V)) - if (CE->getOpcode() == Instruction::GetElementPtr) - return IsAlwaysValidPointer(CE->getOperand(0)); - - return false; -} - /// AllCalleesPassInValidPointerForArgument - Return true if we can prove that /// all callees pass in a valid pointer for the specified function argument. static bool AllCalleesPassInValidPointerForArgument(Argument *Arg) { @@ -216,7 +203,7 @@ CallSite CS(*UI); assert(CS && "Should only have direct calls!"); - if (!IsAlwaysValidPointer(CS.getArgument(ArgNo))) + if (!CS.getArgument(ArgNo)->isDereferenceablePointer()) return false; } return true; Modified: llvm/trunk/lib/VMCore/Instruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=118840&r1=118839&r2=118840&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instruction.cpp (original) +++ llvm/trunk/lib/VMCore/Instruction.cpp Thu Nov 11 15:23:25 2010 @@ -398,25 +398,10 @@ return Op && !Op->isNullValue() && !Op->isAllOnesValue(); } case Load: { - if (cast(this)->isVolatile()) + const LoadInst *LI = cast(this); + if (LI->isVolatile()) return false; - // Note that it is not safe to speculate into a malloc'd region because - // malloc may return null. - // It's also not safe to follow a bitcast, for example: - // bitcast i8* (alloca i8) to i32* - // would result in a 4-byte load from a 1-byte alloca. - Value *Op0 = getOperand(0); - if (GEPOperator *GEP = dyn_cast(Op0)) { - // TODO: it's safe to do this for any GEP with constant indices that - // compute inside the allocated type, but not for any inbounds gep. - if (GEP->hasAllZeroIndices()) - Op0 = GEP->getPointerOperand(); - } - if (isa(Op0)) - return true; - if (GlobalVariable *GV = dyn_cast(getOperand(0))) - return !GV->hasExternalWeakLinkage(); - return false; + return LI->getPointerOperand()->isDereferenceablePointer(); } case Call: return false; // The called function could have undefined behavior or Modified: llvm/trunk/lib/VMCore/Value.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=118840&r1=118839&r2=118840&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Value.cpp (original) +++ llvm/trunk/lib/VMCore/Value.cpp Thu Nov 11 15:23:25 2010 @@ -22,6 +22,7 @@ #include "llvm/ValueSymbolTable.h" #include "llvm/ADT/SmallString.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/LeakDetector.h" #include "llvm/Support/ManagedStatic.h" @@ -366,6 +367,60 @@ return V; } +/// isDereferenceablePointer - Test if this value is always a pointer to +// allocated and suitably aligned memory for a simple load or store. +bool Value::isDereferenceablePointer() const { + // Note that it is not safe to speculate into a malloc'd region because + // malloc may return null. + // It's also not always safe to follow a bitcast, for example: + // bitcast i8* (alloca i8) to i32* + // would result in a 4-byte load from a 1-byte alloca. Some cases could + // be handled using TargetData to check sizes and alignments though. + + // These are obviously ok. + if (isa(this)) return true; + + // Global variables which can't collapse to null are ok. + if (const GlobalVariable *GV = dyn_cast(this)) + return !GV->hasExternalWeakLinkage(); + + // For GEPs, determine if the indexing lands within the allocated object. + if (const GEPOperator *GEP = dyn_cast(this)) { + // Conservatively require that the base pointer be fully dereferenceable. + if (!GEP->getOperand(0)->isDereferenceablePointer()) + return false; + // Check the indices. + gep_type_iterator GTI = gep_type_begin(GEP); + for (User::const_op_iterator I = GEP->op_begin()+1, + E = GEP->op_end(); I != E; ++I) { + Value *Index = *I; + const Type *Ty = *GTI++; + // Struct indices can't be out of bounds. + if (isa(Ty)) + continue; + ConstantInt *CI = dyn_cast(Index); + if (!CI) + return false; + // Zero is always ok. + if (CI->isZero()) + continue; + // Check to see that it's within the bounds of an array. + const ArrayType *ATy = dyn_cast(Ty); + if (!ATy) + return false; + if (CI->getValue().getActiveBits() > 64) + return false; + if (CI->getZExtValue() >= ATy->getNumElements()) + return false; + } + // Indices check out; this is dereferenceable. + return true; + } + + // If we don't know, assume the worst. + return false; +} + /// DoPHITranslation - If this value is a PHI node with CurBB as its parent, /// return the value in the PHI node corresponding to PredBB. If not, return /// ourself. This is useful if you want to know the value something has in a Added: llvm/trunk/test/Transforms/SimplifyCFG/speculate-with-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/speculate-with-offset.ll?rev=118840&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/speculate-with-offset.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/speculate-with-offset.ll Thu Nov 11 15:23:25 2010 @@ -0,0 +1,94 @@ +; RUN: opt -simplifycfg -S < %s | FileCheck %s + +; This load is safe to speculate, as it's from a safe offset +; within an alloca. + +; CHECK: @yes +; CHECK-NOT: br + +define void @yes(i1 %c) nounwind { +entry: + %a = alloca [4 x i64*], align 8 + %__a.addr = getelementptr [4 x i64*]* %a, i64 0, i64 3 + call void @frob(i64** %__a.addr) + br i1 %c, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %return + +if.end: ; preds = %entry + %tmp5 = load i64** %__a.addr, align 8 + br label %return + +return: ; preds = %if.end, %if.then + %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ] + ret void +} + +; CHECK: @no0 +; CHECK: br i1 %c + +define void @no0(i1 %c) nounwind { +entry: + %a = alloca [4 x i64*], align 8 + %__a.addr = getelementptr [4 x i64*]* %a, i64 0, i64 4 + call void @frob(i64** %__a.addr) + br i1 %c, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %return + +if.end: ; preds = %entry + %tmp5 = load i64** %__a.addr, align 8 + br label %return + +return: ; preds = %if.end, %if.then + %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ] + ret void +} + +; CHECK: @no1 +; CHECK: br i1 %c + +define void @no1(i1 %c, i64 %n) nounwind { +entry: + %a = alloca [4 x i64*], align 8 + %__a.addr = getelementptr [4 x i64*]* %a, i64 0, i64 %n + call void @frob(i64** %__a.addr) + br i1 %c, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %return + +if.end: ; preds = %entry + %tmp5 = load i64** %__a.addr, align 8 + br label %return + +return: ; preds = %if.end, %if.then + %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ] + ret void +} + +; CHECK: @no2 +; CHECK: br i1 %c + +define void @no2(i1 %c, i64 %n) nounwind { +entry: + %a = alloca [4 x i64*], align 8 + %__a.addr = getelementptr [4 x i64*]* %a, i64 1, i64 0 + call void @frob(i64** %__a.addr) + br i1 %c, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %return + +if.end: ; preds = %entry + %tmp5 = load i64** %__a.addr, align 8 + br label %return + +return: ; preds = %if.end, %if.then + %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ] + ret void +} + +declare void @frob(i64** nocapture %p) From gohman at apple.com Thu Nov 11 15:27:26 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 21:27:26 -0000 Subject: [llvm-commits] [llvm] r118842 - /llvm/trunk/lib/Analysis/AliasSetTracker.cpp Message-ID: <20101111212726.6BFA12A6C12C@llvm.org> Author: djg Date: Thu Nov 11 15:27:26 2010 New Revision: 118842 URL: http://llvm.org/viewvc/llvm-project?rev=118842&view=rev Log: Don't forget the TBAA info, if available. Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=118842&r1=118841&r2=118842&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Thu Nov 11 15:27:26 2010 @@ -46,7 +46,12 @@ PointerRec *R = AS.getSomePointer(); // If the pointers are not a must-alias pair, this set becomes a may alias. - if (AA.alias(L->getValue(), L->getSize(), R->getValue(), R->getSize()) + if (AA.alias(AliasAnalysis::Location(L->getValue(), + L->getSize(), + L->getTBAAInfo()), + AliasAnalysis::Location(R->getValue(), + R->getSize(), + R->getTBAAInfo())) != AliasAnalysis::MustAlias) AliasTy = MayAlias; } From resistor at mac.com Thu Nov 11 15:36:43 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 11 Nov 2010 21:36:43 -0000 Subject: [llvm-commits] [llvm] r118843 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neont2-vld-encoding.s test/MC/ARM/neont2-vst-encoding.s Message-ID: <20101111213643.9AC2B2A6C12C@llvm.org> Author: resistor Date: Thu Nov 11 15:36:43 2010 New Revision: 118843 URL: http://llvm.org/viewvc/llvm-project?rev=118843&view=rev Log: Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. Added: llvm/trunk/test/MC/ARM/neont2-vld-encoding.s llvm/trunk/test/MC/ARM/neont2-vst-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118843&r1=118842&r2=118843&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 11 15:36:43 2010 @@ -163,6 +163,8 @@ // far along that this one can be eliminated entirely. unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) const { return 0; } + unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) + const { return 0; } unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118843&r1=118842&r2=118843&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 11 15:36:43 2010 @@ -1827,6 +1827,8 @@ let Inst{11-8} = op11_8; let Inst{7-4} = op7_4; + string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; + bits<5> Vd; bits<6> Rn; bits<4> Rm; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118843&r1=118842&r2=118843&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 11 15:36:43 2010 @@ -174,6 +174,8 @@ unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue) const; + unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, + unsigned EncodedValue) const; void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; @@ -198,7 +200,7 @@ return new ARMMCCodeEmitter(TM, Ctx); } -/// NEONThumb2PostEncoder - Post-process encoded NEON data-processing +/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing /// instructions, and rewrite them to their Thumb2 form if we are currently in /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, @@ -218,6 +220,21 @@ return EncodedValue; } +/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store +/// instructions, and rewrite them to their Thumb2 form if we are currently in +/// Thumb2 mode. +unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, + unsigned EncodedValue) const { + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isThumb2()) { + EncodedValue &= 0xF0FFFFFF; + EncodedValue |= 0x09000000; + } + + return EncodedValue; +} + + /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned ARMMCCodeEmitter:: Added: llvm/trunk/test/MC/ARM/neont2-vld-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-vld-encoding.s?rev=118843&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-vld-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-vld-encoding.s Thu Nov 11 15:36:43 2010 @@ -0,0 +1,112 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf9] + vld1.8 {d16}, [r0, :64] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf9] + vld1.16 {d16}, [r0] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf9] + vld1.32 {d16}, [r0] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf9] + vld1.64 {d16}, [r0] +@ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf9] + vld1.8 {d16, d17}, [r0, :64] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf9] + vld1.16 {d16, d17}, [r0, :128] +@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf9] + vld1.32 {d16, d17}, [r0] +@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf9] + vld1.64 {d16, d17}, [r0] + +@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf9] + vld2.8 {d16, d17}, [r0, :64] +@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf9] + vld2.16 {d16, d17}, [r0, :128] +@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf9] + vld2.32 {d16, d17}, [r0] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf9] + vld2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf9] + vld2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf9] + vld2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf9] + vld3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf9] + vld3.16 {d16, d17, d18}, [r0] +@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf9] + vld3.32 {d16, d17, d18}, [r0] +@ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf9] + vld3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf9] + vld3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf9] + vld3.16 {d16, d18, d20}, [r0]! +@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf9] + vld3.16 {d17, d19, d21}, [r0]! +@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf9] + vld3.32 {d16, d18, d20}, [r0]! +@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf9] + vld3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf9] + vld4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf9] + vld4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf9] + vld4.32 {d16, d17, d18, d19}, [r0, :256] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf9] + vld4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf9] + vld4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf9] + vld4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf9] + vld4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf9] + vld4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf9] + vld4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf9] + vld1.8 {d16[3]}, [r0] +@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf9] + vld1.16 {d16[2]}, [r0, :16] +@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf9] + vld1.32 {d16[1]}, [r0, :32] + +@ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf9] + vld2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf9] + vld2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf9] + vld2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf9] + vld2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf9] + vld2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf9] + vld3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xe0,0xf9] + vld3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xe0,0xf9] + vld3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] @ encoding: [0x6f,0x06,0xe0,0xf9] + vld3.16 {d16[1], d18[1], d20[1]}, [r0] +@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf9] + vld3.32 {d17[1], d19[1], d21[1]}, [r0] + +@ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf9] + vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf9] + vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf9] + vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf9] + vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf9] + vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] Added: llvm/trunk/test/MC/ARM/neont2-vst-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-vst-encoding.s?rev=118843&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-vst-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-vst-encoding.s Thu Nov 11 15:36:43 2010 @@ -0,0 +1,103 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf9] + vst1.8 {d16}, [r0, :64] +@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf9] + vst1.16 {d16}, [r0] +@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf9] + vst1.32 {d16}, [r0] +@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf9] + vst1.64 {d16}, [r0] +@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf9] + vst1.8 {d16, d17}, [r0, :64] +@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf9] + vst1.16 {d16, d17}, [r0, :128] +@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf9] + vst1.32 {d16, d17}, [r0] +@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf9] + vst1.64 {d16, d17}, [r0] + +@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf9] + vst2.8 {d16, d17}, [r0, :64] +@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf9] + vst2.16 {d16, d17}, [r0, :128] +@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf9] + vst2.32 {d16, d17}, [r0] +@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf9] + vst2.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf9] + vst2.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf9] + vst2.32 {d16, d17, d18, d19}, [r0, :256] + +@ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf9] + vst3.8 {d16, d17, d18}, [r0, :64] +@ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf9] + vst3.16 {d16, d17, d18}, [r0] +@ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf9] + vst3.32 {d16, d17, d18}, [r0] +@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf9] + vst3.8 {d16, d18, d20}, [r0, :64]! +@ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf9] + vst3.8 {d17, d19, d21}, [r0, :64]! +@ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf9] + vst3.16 {d16, d18, d20}, [r0]! +@ CHECK: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf9] + vst3.16 {d17, d19, d21}, [r0]! +@ CHECK: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf9] + vst3.32 {d16, d18, d20}, [r0]! +@ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf9] + vst3.32 {d17, d19, d21}, [r0]! + +@ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf9] + vst4.8 {d16, d17, d18, d19}, [r0, :64] +@ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf9] + vst4.16 {d16, d17, d18, d19}, [r0, :128] +@ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf9] + vst4.8 {d16, d18, d20, d22}, [r0, :256]! +@ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf9] + vst4.8 {d17, d19, d21, d23}, [r0, :256]! +@ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf9] + vst4.16 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf9] + vst4.16 {d17, d19, d21, d23}, [r0]! +@ CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf9] + vst4.32 {d16, d18, d20, d22}, [r0]! +@ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf9] + vst4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf9] + vst2.8 {d16[1], d17[1]}, [r0, :16] +@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf9] + vst2.16 {d16[1], d17[1]}, [r0, :32] +@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf9] + vst2.32 {d16[1], d17[1]}, [r0] +@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf9] + vst2.16 {d17[1], d19[1]}, [r0] +@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf9] + vst2.32 {d17[0], d19[0]}, [r0, :64] + +@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf9] + vst3.8 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xc0,0xf9] + vst3.16 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xc0,0xf9] + vst3.32 {d16[1], d17[1], d18[1]}, [r0] +@ CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] @ encoding: [0xaf,0x16,0xc0,0xf9] + vst3.16 {d17[2], d19[2], d21[2]}, [r0] +@ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf9] + vst3.32 {d16[0], d18[0], d20[0]}, [r0] + +@ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf9] + vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +@ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf9] + vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +@ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf9] + vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +@ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf9] + vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] + vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] From peckw at wesleypeck.com Thu Nov 11 15:40:53 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Thu, 11 Nov 2010 21:40:53 -0000 Subject: [llvm-commits] [llvm] r118844 - in /llvm/trunk: lib/Target/MBlaze/MBlazeInstrInfo.td lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp test/MC/MBlaze/ test/MC/MBlaze/dg.exp test/MC/MBlaze/mblaze_fsl.s test/MC/MBlaze/mblaze_imm.s test/MC/MBlaze/mblaze_operands.s test/MC/MBlaze/mblaze_typea.s test/MC/MBlaze/mblaze_typeb.s Message-ID: <20101111214054.0C2572A6C12C@llvm.org> Author: peckw Date: Thu Nov 11 15:40:53 2010 New Revision: 118844 URL: http://llvm.org/viewvc/llvm-project?rev=118844&view=rev Log: Fix tblgen instruction errors exposed by MC asm parser tests Fix minimum 16-bit signed value error exposed by MC asm parser tests Add initial MC asm parser tests for the MBlaze backend Added: llvm/trunk/test/MC/MBlaze/ llvm/trunk/test/MC/MBlaze/dg.exp llvm/trunk/test/MC/MBlaze/mblaze_fsl.s llvm/trunk/test/MC/MBlaze/mblaze_imm.s llvm/trunk/test/MC/MBlaze/mblaze_operands.s llvm/trunk/test/MC/MBlaze/mblaze_typea.s llvm/trunk/test/MC/MBlaze/mblaze_typeb.s Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118844&r1=118843&r2=118844&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Thu Nov 11 15:40:53 2010 @@ -297,17 +297,16 @@ //===----------------------------------------------------------------------===// // Conditional Branch Instructions //===----------------------------------------------------------------------===// -class BranchC op, bits<5> br, bits<11> flags, string instr_asm, - PatFrag cond_op> : +class BranchC op, bits<5> br, bits<11> flags, string instr_asm> : TA { let rd = br; let Form = FCRR; } -class BranchCI op, bits<5> br, string instr_asm, PatFrag cond_op> : +class BranchCI op, bits<5> br, string instr_asm> : TB { @@ -430,12 +429,12 @@ } let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { - def BEQI : BranchCI<0x2F, 0x00, "beqi ", seteq>; - def BNEI : BranchCI<0x2F, 0x01, "bnei ", setne>; - def BLTI : BranchCI<0x2F, 0x02, "blti ", setlt>; - def BLEI : BranchCI<0x2F, 0x03, "blei ", setle>; - def BGTI : BranchCI<0x2F, 0x04, "bgti ", setgt>; - def BGEI : BranchCI<0x2F, 0x05, "bgei ", setge>; + def BEQI : BranchCI<0x2F, 0x00, "beqi ">; + def BNEI : BranchCI<0x2F, 0x01, "bnei ">; + def BLTI : BranchCI<0x2F, 0x02, "blti ">; + def BLEI : BranchCI<0x2F, 0x03, "blei ">; + def BGTI : BranchCI<0x2F, 0x04, "bgti ">; + def BGEI : BranchCI<0x2F, 0x05, "bgei ">; } let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1, @@ -445,12 +444,12 @@ } let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { - def BEQ : BranchC<0x27, 0x00, 0x000, "beq ", seteq>; - def BNE : BranchC<0x27, 0x01, 0x000, "bne ", setne>; - def BLT : BranchC<0x27, 0x02, 0x000, "blt ", setlt>; - def BLE : BranchC<0x27, 0x03, 0x000, "ble ", setle>; - def BGT : BranchC<0x27, 0x04, 0x000, "bgt ", setgt>; - def BGE : BranchC<0x27, 0x05, 0x000, "bge ", setge>; + def BEQ : BranchC<0x27, 0x00, 0x000, "beq ">; + def BNE : BranchC<0x27, 0x01, 0x000, "bne ">; + def BLT : BranchC<0x27, 0x02, 0x000, "blt ">; + def BLE : BranchC<0x27, 0x03, 0x000, "ble ">; + def BGT : BranchC<0x27, 0x04, 0x000, "bgt ">; + def BGE : BranchC<0x27, 0x05, 0x000, "bge ">; } let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1, @@ -460,12 +459,12 @@ } let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in { - def BEQID : BranchCI<0x2F, 0x10, "beqid ", seteq>; - def BNEID : BranchCI<0x2F, 0x11, "bneid ", setne>; - def BLTID : BranchCI<0x2F, 0x12, "bltid ", setlt>; - def BLEID : BranchCI<0x2F, 0x13, "bleid ", setle>; - def BGTID : BranchCI<0x2F, 0x14, "bgtid ", setgt>; - def BGEID : BranchCI<0x2F, 0x15, "bgeid ", setge>; + def BEQID : BranchCI<0x2F, 0x10, "beqid ">; + def BNEID : BranchCI<0x2F, 0x11, "bneid ">; + def BLTID : BranchCI<0x2F, 0x12, "bltid ">; + def BLEID : BranchCI<0x2F, 0x13, "bleid ">; + def BGTID : BranchCI<0x2F, 0x14, "bgtid ">; + def BGEID : BranchCI<0x2F, 0x15, "bgeid ">; } let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, @@ -476,12 +475,12 @@ let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in { - def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ", seteq>; - def BNED : BranchC<0x27, 0x11, 0x000, "bned ", setne>; - def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ", setlt>; - def BLED : BranchC<0x27, 0x13, 0x000, "bled ", setle>; - def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ", setgt>; - def BGED : BranchC<0x27, 0x15, 0x000, "bged ", setge>; + def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ">; + def BNED : BranchC<0x27, 0x11, 0x000, "bned ">; + def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ">; + def BLED : BranchC<0x27, 0x13, 0x000, "bled ">; + def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ">; + def BGED : BranchC<0x27, 0x15, 0x000, "bged ">; } let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=118844&r1=118843&r2=118844&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Thu Nov 11 15:40:53 2010 @@ -146,7 +146,7 @@ void MBlazeMCCodeEmitter:: EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const { int32_t val = (int32_t)imm.getImm(); - if (val > 32767 || val < -32678) { + if (val > 32767 || val < -32768) { EmitByte(0x0D, CurByte, OS); EmitByte(0x00, CurByte, OS); EmitRawByte((val >> 24) & 0xFF, CurByte, OS); Added: llvm/trunk/test/MC/MBlaze/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/dg.exp?rev=118844&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/dg.exp (added) +++ llvm/trunk/test/MC/MBlaze/dg.exp Thu Nov 11 15:40:53 2010 @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target MBlaze] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] +} Added: llvm/trunk/test/MC/MBlaze/mblaze_fsl.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_fsl.s?rev=118844&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_fsl.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_fsl.s Thu Nov 11 15:40:53 2010 @@ -0,0 +1,245 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to ensure that all FSL immediate operands and FSL instructions +# can be parsed by the assembly parser correctly. + +# TYPE F: OPCODE RD NCTAE FSL +# BINARY: 011011 00000 000000 00000 000000 0000 + +# TYPE FD: OPCODE RD RB NCTAE +# BINARY: 011011 00000 00000 00000 0 00000 00000 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x00,0x00] + get r0, rfsl0 + +# CHECK: nget +# BINARY: 011011 00000 000000 10000 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x40,0x00] + nget r0, rfsl0 + +# CHECK: cget +# BINARY: 011011 00000 000000 01000 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x20,0x00] + cget r0, rfsl0 + +# CHECK: ncget +# BINARY: 011011 00000 000000 11000 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x60,0x00] + ncget r0, rfsl0 + +# CHECK: tget +# BINARY: 011011 00000 000000 00100 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x10,0x00] + tget r0, rfsl0 + +# CHECK: tnget +# BINARY: 011011 00000 000000 10100 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x50,0x00] + tnget r0, rfsl0 + +# CHECK: tcget +# BINARY: 011011 00000 000000 01100 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x30,0x00] + tcget r0, rfsl0 + +# CHECK: tncget +# BINARY: 011011 00000 000000 11100 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x70,0x00] + tncget r0, rfsl0 + +# CHECK: aget +# BINARY: 011011 00000 000000 00010 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x08,0x00] + aget r0, rfsl0 + +# CHECK: naget +# BINARY: 011011 00000 000000 10010 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x48,0x00] + naget r0, rfsl0 + +# CHECK: caget +# BINARY: 011011 00000 000000 01010 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x28,0x00] + caget r0, rfsl0 + +# CHECK: ncaget +# BINARY: 011011 00000 000000 11010 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x68,0x00] + ncaget r0, rfsl0 + +# CHECK: taget +# BINARY: 011011 00000 000000 00110 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x18,0x00] + taget r0, rfsl0 + +# CHECK: tnaget +# BINARY: 011011 00000 000000 10110 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x58,0x00] + tnaget r0, rfsl0 + +# CHECK: tcaget +# BINARY: 011011 00000 000000 01110 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x38,0x00] + tcaget r0, rfsl0 + +# CHECK: tncaget +# BINARY: 011011 00000 000000 11110 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x78,0x00] + tncaget r0, rfsl0 + +# CHECK: eget +# BINARY: 011011 00000 000000 00001 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x04,0x00] + eget r0, rfsl0 + +# CHECK: neget +# BINARY: 011011 00000 000000 10001 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x44,0x00] + neget r0, rfsl0 + +# CHECK: ecget +# BINARY: 011011 00000 000000 01001 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x24,0x00] + ecget r0, rfsl0 + +# CHECK: necget +# BINARY: 011011 00000 000000 11001 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x64,0x00] + necget r0, rfsl0 + +# CHECK: teget +# BINARY: 011011 00000 000000 00101 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x14,0x00] + teget r0, rfsl0 + +# CHECK: tneget +# BINARY: 011011 00000 000000 10101 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x54,0x00] + tneget r0, rfsl0 + +# CHECK: tecget +# BINARY: 011011 00000 000000 01101 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x34,0x00] + tecget r0, rfsl0 + +# CHECK: tnecget +# BINARY: 011011 00000 000000 11101 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x74,0x00] + tnecget r0, rfsl0 + +# CHECK: eaget +# BINARY: 011011 00000 000000 00011 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x0c,0x00] + eaget r0, rfsl0 + +# CHECK: neaget +# BINARY: 011011 00000 000000 10011 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x4c,0x00] + neaget r0, rfsl0 + +# CHECK: ecaget +# BINARY: 011011 00000 000000 01011 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x2c,0x00] + ecaget r0, rfsl0 + +# CHECK: necaget +# BINARY: 011011 00000 000000 11011 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x6c,0x00] + necaget r0, rfsl0 + +# CHECK: teaget +# BINARY: 011011 00000 000000 00111 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x1c,0x00] + teaget r0, rfsl0 + +# CHECK: tneaget +# BINARY: 011011 00000 000000 10111 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x5c,0x00] + tneaget r0, rfsl0 + +# CHECK: tecaget +# BINARY: 011011 00000 000000 01111 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x3c,0x00] + tecaget r0, rfsl0 + +# CHECK: tnecaget +# BINARY: 011011 00000 000000 11111 000000 0000 +# CHECK: encoding: [0x6c,0x00,0x7c,0x00] + tnecaget r0, rfsl0 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0001 +# CHECK: encoding: [0x6c,0x00,0x00,0x01] + get r0, rfsl1 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0010 +# CHECK: encoding: [0x6c,0x00,0x00,0x02] + get r0, rfsl2 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0011 +# CHECK: encoding: [0x6c,0x00,0x00,0x03] + get r0, rfsl3 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0100 +# CHECK: encoding: [0x6c,0x00,0x00,0x04] + get r0, rfsl4 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0101 +# CHECK: encoding: [0x6c,0x00,0x00,0x05] + get r0, rfsl5 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0110 +# CHECK: encoding: [0x6c,0x00,0x00,0x06] + get r0, rfsl6 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 0111 +# CHECK: encoding: [0x6c,0x00,0x00,0x07] + get r0, rfsl7 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1000 +# CHECK: encoding: [0x6c,0x00,0x00,0x08] + get r0, rfsl8 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1001 +# CHECK: encoding: [0x6c,0x00,0x00,0x09] + get r0, rfsl9 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1010 +# CHECK: encoding: [0x6c,0x00,0x00,0x0a] + get r0, rfsl10 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1011 +# CHECK: encoding: [0x6c,0x00,0x00,0x0b] + get r0, rfsl11 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1100 +# CHECK: encoding: [0x6c,0x00,0x00,0x0c] + get r0, rfsl12 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1101 +# CHECK: encoding: [0x6c,0x00,0x00,0x0d] + get r0, rfsl13 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1110 +# CHECK: encoding: [0x6c,0x00,0x00,0x0e] + get r0, rfsl14 + +# CHECK: get +# BINARY: 011011 00000 000000 00000 000000 1111 +# CHECK: encoding: [0x6c,0x00,0x00,0x0f] + get r0, rfsl15 Added: llvm/trunk/test/MC/MBlaze/mblaze_imm.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_imm.s?rev=118844&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_imm.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_imm.s Thu Nov 11 15:40:53 2010 @@ -0,0 +1,194 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# In the microblaze instruction set, any TYPE-B instruction with a +# signed immediate value requiring more than 16-bits must be prefixed +# with an IMM instruction that contains the high 16-bits. The higher +# 16-bits are then combined with the lower 16-bits in the original +# instruction to form a 32-bit immediate value. +# +# The generation of IMM instructions is handled automatically by the +# code emitter. Test to ensure that IMM instructions are generated +# when they are suppose to and are not generated when they are not +# needed. + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0x20,0x00,0x00,0x00] + addi r0, r0, 0x00000000 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000001 +# CHECK: encoding: [0x20,0x00,0x00,0x01] + addi r0, r0, 0x00000001 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000010 +# CHECK: encoding: [0x20,0x00,0x00,0x02] + addi r0, r0, 0x00000002 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000100 +# CHECK: encoding: [0x20,0x00,0x00,0x04] + addi r0, r0, 0x00000004 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000001000 +# CHECK: encoding: [0x20,0x00,0x00,0x08] + addi r0, r0, 0x00000008 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000010000 +# CHECK: encoding: [0x20,0x00,0x00,0x10] + addi r0, r0, 0x00000010 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000100000 +# CHECK: encoding: [0x20,0x00,0x00,0x20] + addi r0, r0, 0x00000020 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000001000000 +# CHECK: encoding: [0x20,0x00,0x00,0x40] + addi r0, r0, 0x00000040 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000010000000 +# CHECK: encoding: [0x20,0x00,0x00,0x80] + addi r0, r0, 0x00000080 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000100000000 +# CHECK: encoding: [0x20,0x00,0x01,0x00] + addi r0, r0, 0x00000100 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000001000000000 +# CHECK: encoding: [0x20,0x00,0x02,0x00] + addi r0, r0, 0x00000200 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000010000000000 +# CHECK: encoding: [0x20,0x00,0x04,0x00] + addi r0, r0, 0x00000400 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000100000000000 +# CHECK: encoding: [0x20,0x00,0x08,0x00] + addi r0, r0, 0x00000800 + +# CHECK: addi +# BINARY: 001000 00000 00000 0001000000000000 +# CHECK: encoding: [0x20,0x00,0x10,0x00] + addi r0, r0, 0x00001000 + +# CHECK: addi +# BINARY: 001000 00000 00000 0010000000000000 +# CHECK: encoding: [0x20,0x00,0x20,0x00] + addi r0, r0, 0x00002000 + +# CHECK: addi +# BINARY: 001000 00000 00000 0100000000000000 +# CHECK: encoding: [0x20,0x00,0x40,0x00] + addi r0, r0, 0x00004000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000000000 +# BINARY: 001000 00000 00000 1000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x00,0x20,0x00,0x80,0x00] + addi r0, r0, 0x00008000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000000001 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x01,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00010000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000000010 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x02,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00020000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000000100 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x04,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00040000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000001000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x08,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00080000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000010000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x10,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00100000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000000100000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x20,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00200000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000001000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x40,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00400000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000010000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x00,0x80,0x20,0x00,0x00,0x00] + addi r0, r0, 0x00800000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000000100000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x01,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x01000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000001000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x02,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x02000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000010000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x04,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x04000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0000100000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x08,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x08000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0001000000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x10,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x10000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0010000000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x20,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x20000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 0100000000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x40,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x40000000 + +# CHECK: addi +# BINARY: 101100 00000 00000 1000000000000000 +# 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0xb0,0x00,0x80,0x00,0x20,0x00,0x00,0x00] + addi r0, r0, 0x80000000 Added: llvm/trunk/test/MC/MBlaze/mblaze_operands.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_operands.s?rev=118844&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_operands.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_operands.s Thu Nov 11 15:40:53 2010 @@ -0,0 +1,328 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to ensure that all register and immediate operands can be parsed by +# the assembly parser correctly. Testing the parsing of FSL immediate +# values is done in a different test. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 000000 00000 00000 00000 00000000000 + +# CHECK: add +# BINARY: 000000 00000 00000 00000 00000000000 +# CHECK: encoding: [0x00,0x00,0x00,0x00] + add r0, r0, r0 + +# CHECK: add +# BINARY: 000000 00001 00001 00001 00000000000 +# CHECK: encoding: [0x00,0x21,0x08,0x00] + add r1, r1, r1 + +# CHECK: add +# BINARY: 000000 00010 00010 00010 00000000000 +# CHECK: encoding: [0x00,0x42,0x10,0x00] + add r2, r2, r2 + +# CHECK: add +# BINARY: 000000 00011 00011 00011 00000000000 +# CHECK: encoding: [0x00,0x63,0x18,0x00] + add r3, r3, r3 + +# CHECK: add +# BINARY: 000000 00100 00100 00100 00000000000 +# CHECK: encoding: [0x00,0x84,0x20,0x00] + add r4, r4, r4 + +# CHECK: add +# BINARY: 000000 00101 00101 00101 00000000000 +# CHECK: encoding: [0x00,0xa5,0x28,0x00] + add r5, r5, r5 + +# CHECK: add +# BINARY: 000000 00110 00110 00110 00000000000 +# CHECK: encoding: [0x00,0xc6,0x30,0x00] + add r6, r6, r6 + +# CHECK: add +# BINARY: 000000 00111 00111 00111 00000000000 +# CHECK: encoding: [0x00,0xe7,0x38,0x00] + add r7, r7, r7 + +# CHECK: add +# BINARY: 000000 01000 01000 01000 00000000000 +# CHECK: encoding: [0x01,0x08,0x40,0x00] + add r8, r8, r8 + +# CHECK: add +# BINARY: 000000 01001 01001 01001 00000000000 +# CHECK: encoding: [0x01,0x29,0x48,0x00] + add r9, r9, r9 + +# CHECK: add +# BINARY: 000000 01010 01010 01010 00000000000 +# CHECK: encoding: [0x01,0x4a,0x50,0x00] + add r10, r10, r10 + +# CHECK: add +# BINARY: 000000 01011 01011 01011 00000000000 +# CHECK: encoding: [0x01,0x6b,0x58,0x00] + add r11, r11, r11 + +# CHECK: add +# BINARY: 000000 01100 01100 01100 00000000000 +# CHECK: encoding: [0x01,0x8c,0x60,0x00] + add r12, r12, r12 + +# CHECK: add +# BINARY: 000000 01101 01101 01101 00000000000 +# CHECK: encoding: [0x01,0xad,0x68,0x00] + add r13, r13, r13 + +# CHECK: add +# BINARY: 000000 01110 01110 01110 00000000000 +# CHECK: encoding: [0x01,0xce,0x70,0x00] + add r14, r14, r14 + +# CHECK: add +# BINARY: 000000 01111 01111 01111 00000000000 +# CHECK: encoding: [0x01,0xef,0x78,0x00] + add r15, r15, r15 + +# CHECK: add +# BINARY: 000000 10000 10000 10000 00000000000 +# CHECK: encoding: [0x02,0x10,0x80,0x00] + add r16, r16, r16 + +# CHECK: add +# BINARY: 000000 10001 10001 10001 00000000000 +# CHECK: encoding: [0x02,0x31,0x88,0x00] + add r17, r17, r17 + +# CHECK: add +# BINARY: 000000 10010 10010 10010 00000000000 +# CHECK: encoding: [0x02,0x52,0x90,0x00] + add r18, r18, r18 + +# CHECK: add +# BINARY: 000000 10011 10011 10011 00000000000 +# CHECK: encoding: [0x02,0x73,0x98,0x00] + add r19, r19, r19 + +# CHECK: add +# BINARY: 000000 10100 10100 10100 00000000000 +# CHECK: encoding: [0x02,0x94,0xa0,0x00] + add r20, r20, r20 + +# CHECK: add +# BINARY: 000000 10101 10101 10101 00000000000 +# CHECK: encoding: [0x02,0xb5,0xa8,0x00] + add r21, r21, r21 + +# CHECK: add +# BINARY: 000000 10110 10110 10110 00000000000 +# CHECK: encoding: [0x02,0xd6,0xb0,0x00] + add r22, r22, r22 + +# CHECK: add +# BINARY: 000000 10111 10111 10111 00000000000 +# CHECK: encoding: [0x02,0xf7,0xb8,0x00] + add r23, r23, r23 + +# CHECK: add +# BINARY: 000000 11000 11000 11000 00000000000 +# CHECK: encoding: [0x03,0x18,0xc0,0x00] + add r24, r24, r24 + +# CHECK: add +# BINARY: 000000 11001 11001 11001 00000000000 +# CHECK: encoding: [0x03,0x39,0xc8,0x00] + add r25, r25, r25 + +# CHECK: add +# BINARY: 000000 11010 11010 11010 00000000000 +# CHECK: encoding: [0x03,0x5a,0xd0,0x00] + add r26, r26, r26 + +# CHECK: add +# BINARY: 000000 11011 11011 11011 00000000000 +# CHECK: encoding: [0x03,0x7b,0xd8,0x00] + add r27, r27, r27 + +# CHECK: add +# BINARY: 000000 11100 11100 11100 00000000000 +# CHECK: encoding: [0x03,0x9c,0xe0,0x00] + add r28, r28, r28 + +# CHECK: add +# BINARY: 000000 11101 11101 11101 00000000000 +# CHECK: encoding: [0x03,0xbd,0xe8,0x00] + add r29, r29, r29 + +# CHECK: add +# BINARY: 000000 11110 11110 11110 00000000000 +# CHECK: encoding: [0x03,0xde,0xf0,0x00] + add r30, r30, r30 + +# CHECK: add +# BINARY: 000000 11111 11111 11111 00000000000 +# CHECK: encoding: [0x03,0xff,0xf8,0x00] + add r31, r31, r31 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000000 +# CHECK: encoding: [0x20,0x00,0x00,0x00] + addi r0, r0, 0 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000001 +# CHECK: encoding: [0x20,0x00,0x00,0x01] + addi r0, r0, 1 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000010 +# CHECK: encoding: [0x20,0x00,0x00,0x02] + addi r0, r0, 2 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000000100 +# CHECK: encoding: [0x20,0x00,0x00,0x04] + addi r0, r0, 4 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000001000 +# CHECK: encoding: [0x20,0x00,0x00,0x08] + addi r0, r0, 8 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000010000 +# CHECK: encoding: [0x20,0x00,0x00,0x10] + addi r0, r0, 16 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000000100000 +# CHECK: encoding: [0x20,0x00,0x00,0x20] + addi r0, r0, 32 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000001000000 +# CHECK: encoding: [0x20,0x00,0x00,0x40] + addi r0, r0, 64 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000010000000 +# CHECK: encoding: [0x20,0x00,0x00,0x80] + addi r0, r0, 128 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000000100000000 +# CHECK: encoding: [0x20,0x00,0x01,0x00] + addi r0, r0, 256 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000001000000000 +# CHECK: encoding: [0x20,0x00,0x02,0x00] + addi r0, r0, 512 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000010000000000 +# CHECK: encoding: [0x20,0x00,0x04,0x00] + addi r0, r0, 1024 + +# CHECK: addi +# BINARY: 001000 00000 00000 0000100000000000 +# CHECK: encoding: [0x20,0x00,0x08,0x00] + addi r0, r0, 2048 + +# CHECK: addi +# BINARY: 001000 00000 00000 0001000000000000 +# CHECK: encoding: [0x20,0x00,0x10,0x00] + addi r0, r0, 4096 + +# CHECK: addi +# BINARY: 001000 00000 00000 0010000000000000 +# CHECK: encoding: [0x20,0x00,0x20,0x00] + addi r0, r0, 8192 + +# CHECK: addi +# BINARY: 001000 00000 00000 0100000000000000 +# CHECK: encoding: [0x20,0x00,0x40,0x00] + addi r0, r0, 16384 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111111111 +# CHECK: encoding: [0x20,0x00,0xff,0xff] + addi r0, r0, -1 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111111110 +# CHECK: encoding: [0x20,0x00,0xff,0xfe] + addi r0, r0, -2 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111111100 +# CHECK: encoding: [0x20,0x00,0xff,0xfc] + addi r0, r0, -4 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111111000 +# CHECK: encoding: [0x20,0x00,0xff,0xf8] + addi r0, r0, -8 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111110000 +# CHECK: encoding: [0x20,0x00,0xff,0xf0] + addi r0, r0, -16 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111100000 +# CHECK: encoding: [0x20,0x00,0xff,0xe0] + addi r0, r0, -32 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111111000000 +# CHECK: encoding: [0x20,0x00,0xff,0xc0] + addi r0, r0, -64 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111110000000 +# CHECK: encoding: [0x20,0x00,0xff,0x80] + addi r0, r0, -128 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111100000000 +# CHECK: encoding: [0x20,0x00,0xff,0x00] + addi r0, r0, -256 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111111000000000 +# CHECK: encoding: [0x20,0x00,0xfe,0x00] + addi r0, r0, -512 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111110000000000 +# CHECK: encoding: [0x20,0x00,0xfc,0x00] + addi r0, r0, -1024 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111100000000000 +# CHECK: encoding: [0x20,0x00,0xf8,0x00] + addi r0, r0, -2048 + +# CHECK: addi +# BINARY: 001000 00000 00000 1111000000000000 +# CHECK: encoding: [0x20,0x00,0xf0,0x00] + addi r0, r0, -4096 + +# CHECK: addi +# BINARY: 001000 00000 00000 1110000000000000 +# CHECK: encoding: [0x20,0x00,0xe0,0x00] + addi r0, r0, -8192 + +# CHECK: addi +# BINARY: 001000 00000 00000 1100000000000000 +# CHECK: encoding: [0x20,0x00,0xc0,0x00] + addi r0, r0, -16384 + +# CHECK: addi +# BINARY: 001000 00000 00000 1000000000000000 +# CHECK: encoding: [0x20,0x00,0x80,0x00] + addi r0, r0, -32768 Added: llvm/trunk/test/MC/MBlaze/mblaze_typea.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_typea.s?rev=118844&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_typea.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_typea.s Thu Nov 11 15:40:53 2010 @@ -0,0 +1,72 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to make sure that all of the TYPE-A instructions supported by +# the Microblaze can be parsed by the assembly parser. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 000000 00000 00000 00000 00000000000 + +# CHECK: add +# BINARY: 000000 00001 00010 00011 00000000000 +# CHECK: encoding: [0x00,0x22,0x18,0x00] + add r1, r2, r3 + +# CHECK: addc +# BINARY: 000010 00001 00010 00011 00000000000 +# CHECK: encoding: [0x08,0x22,0x18,0x00] + addc r1, r2, r3 + +# CHECK: addk +# BINARY: 000100 00001 00010 00011 00000000000 +# CHECK: encoding: [0x10,0x22,0x18,0x00] + addk r1, r2, r3 + +# CHECK: addkc +# BINARY: 000110 00001 00010 00011 00000000000 +# CHECK: encoding: [0x18,0x22,0x18,0x00] + addkc r1, r2, r3 + +# CHECK: and +# BINARY: 100001 00001 00010 00011 00000000000 +# CHECK: encoding: [0x84,0x22,0x18,0x00] + and r1, r2, r3 + +# CHECK: andn +# BINARY: 100011 00001 00010 00011 00000000000 +# CHECK: encoding: [0x8c,0x22,0x18,0x00] + andn r1, r2, r3 + +# CHECK: beq +# BINARY: 100111 00000 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x02,0x18,0x00] + beq r2, r3 + +# CHECK: bge +# BINARY: 100111 00101 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0xa2,0x18,0x00] + bge r2, r3 + +# CHECK: bgt +# BINARY: 100111 00100 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x82,0x18,0x00] + bgt r2, r3 + +# CHECK: ble +# BINARY: 100111 00011 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x62,0x18,0x00] + ble r2, r3 + +# CHECK: blt +# BINARY: 100111 00010 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x42,0x18,0x00] + blt r2, r3 + +# CHECK: bne +# BINARY: 100111 00001 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x22,0x18,0x00] + bne r2, r3 + +# CHECK: nop +# BINARY: 100000 00000 00000 00000 00000000000 +# CHECK: encoding: [0x80,0x00,0x00,0x00] + nop Added: llvm/trunk/test/MC/MBlaze/mblaze_typeb.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_typeb.s?rev=118844&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_typeb.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_typeb.s Thu Nov 11 15:40:53 2010 @@ -0,0 +1,37 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to make sure that all of the TYPE-B instructions supported by +# the Microblaze can be parsed by the assembly parser. + +# TYPE B: OPCODE RD RA IMMEDIATE +# 000000 00000 00000 0000000000000000 + +# CHECK: addi +# BINARY: 001000 00001 00010 0000000000001111 +# CHECK: encoding: [0x20,0x22,0x00,0x0f] + addi r1, r2, 0x000F + +# CHECK: addic +# BINARY: 001010 00001 00010 0000000000001111 +# CHECK: encoding: [0x28,0x22,0x00,0x0f] + addic r1, r2, 0x000F + +# CHECK: addik +# BINARY: 001100 00001 00010 0000000000001111 +# CHECK: encoding: [0x30,0x22,0x00,0x0f] + addik r1, r2, 0x000F + +# CHECK: addikc +# BINARY: 001110 00001 00010 0000000000001111 +# CHECK: encoding: [0x38,0x22,0x00,0x0f] + addikc r1, r2, 0x000F + +# CHECK: andi +# BINARY: 101001 00001 00010 0000000000001111 +# CHECK: encoding: [0xa4,0x22,0x00,0x0f] + andi r1, r2, 0x000F + +# CHECK: andni +# BINARY: 101011 00001 00010 0000000000001111 +# CHECK: encoding: [0xac,0x22,0x00,0x0f] + andni r1, r2, 0x000F From peckw at wesleypeck.com Thu Nov 11 15:52:13 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Thu, 11 Nov 2010 15:52:13 -0600 Subject: [llvm-commits] [llvm] r118434 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/MBlaze/InstPrinter/ In-Reply-To: References: <20101108194002.618892A6C12D@llvm.org> Message-ID: <55241214-D6B2-44B2-AB61-56EE83D7D75A@wesleypeck.com> I have committed some initial MC asm parser tests for the MBlaze backend in 118844. Also, thanks for taking a look at the code. -- Wesley Peck On Nov 11, 2010, at 11:57 AM, Chris Lattner wrote: > > On Nov 8, 2010, at 11:40 AM, Wesley Peck wrote: > >> Author: peckw >> Date: Mon Nov 8 13:40:01 2010 >> New Revision: 118434 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118434&view=rev >> Log: >> Adding working version of assembly parser for the MBlaze backend >> Major cleanup of whitespace and formatting issues in MBlaze backend > > Very nice! Please add some testcases to test/MC/MBlaze so that it doesn't get broken in the future :) > > -Chris From gohman at apple.com Thu Nov 11 15:50:20 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 11 Nov 2010 21:50:20 -0000 Subject: [llvm-commits] [llvm] r118845 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/MemDepPrinter.cpp lib/Analysis/MemoryDependenceAnalysis.cpp lib/Transforms/IPO/ArgumentPromotion.cpp lib/Transforms/IPO/FunctionAttrs.cpp lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/Sink.cpp Message-ID: <20101111215020.376202A6C12C@llvm.org> Author: djg Date: Thu Nov 11 15:50:19 2010 New Revision: 118845 URL: http://llvm.org/viewvc/llvm-project?rev=118845&view=rev Log: Add helper functions for computing the Location of load, store, and vaarg instructions. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/MemDepPrinter.cpp llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Scalar/Sink.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Nov 11 15:50:19 2010 @@ -130,6 +130,12 @@ } }; + /// getLocation - Fill in Loc with information about the memory reference by + /// the given instruction. + Location getLocation(const LoadInst *LI); + Location getLocation(const StoreInst *SI); + Location getLocation(const VAArgInst *VI); + /// Alias analysis result - Either we know for sure that it does not alias, we /// know for sure it must alias, or we don't know anything: The two pointers /// _might_ alias. This enum is designed so you can do things like: Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Thu Nov 11 15:50:19 2010 @@ -194,6 +194,24 @@ // AliasAnalysis non-virtual helper method implementation //===----------------------------------------------------------------------===// +AliasAnalysis::Location AliasAnalysis::getLocation(const LoadInst *LI) { + return Location(LI->getPointerOperand(), + getTypeStoreSize(LI->getType()), + LI->getMetadata(LLVMContext::MD_tbaa)); +} + +AliasAnalysis::Location AliasAnalysis::getLocation(const StoreInst *SI) { + return Location(SI->getPointerOperand(), + getTypeStoreSize(SI->getValueOperand()->getType()), + SI->getMetadata(LLVMContext::MD_tbaa)); +} + +AliasAnalysis::Location AliasAnalysis::getLocation(const VAArgInst *VI) { + return Location(VI->getPointerOperand(), + UnknownSize, + VI->getMetadata(LLVMContext::MD_tbaa)); +} + AliasAnalysis::ModRefResult AliasAnalysis::getModRefInfo(const LoadInst *L, const Location &Loc) { // Be conservative in the face of volatile. @@ -202,10 +220,7 @@ // If the load address doesn't alias the given address, it doesn't read // or write the specified memory. - if (!alias(Location(L->getOperand(0), - getTypeStoreSize(L->getType()), - L->getMetadata(LLVMContext::MD_tbaa)), - Loc)) + if (!alias(getLocation(L), Loc)) return NoModRef; // Otherwise, a load just reads. @@ -220,10 +235,7 @@ // If the store address cannot alias the pointer in question, then the // specified memory cannot be modified by the store. - if (!alias(Location(S->getOperand(1), - getTypeStoreSize(S->getOperand(0)->getType()), - S->getMetadata(LLVMContext::MD_tbaa)), - Loc)) + if (!alias(getLocation(S), Loc)) return NoModRef; // If the pointer is a pointer to constant memory, then it could not have been @@ -239,10 +251,7 @@ AliasAnalysis::getModRefInfo(const VAArgInst *V, const Location &Loc) { // If the va_arg address cannot alias the pointer in question, then the // specified memory cannot be accessed by the va_arg. - if (!alias(Location(V->getOperand(0), - UnknownSize, - V->getMetadata(LLVMContext::MD_tbaa)), - Loc)) + if (!alias(getLocation(V), Loc)) return NoModRef; // If the pointer is a pointer to constant memory, then it could not have been Modified: llvm/trunk/lib/Analysis/MemDepPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemDepPrinter.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemDepPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/MemDepPrinter.cpp Thu Nov 11 15:50:19 2010 @@ -102,22 +102,15 @@ SmallVector NLDI; if (LoadInst *LI = dyn_cast(Inst)) { // FIXME: Volatile is not handled properly here. - AliasAnalysis::Location Loc(LI->getPointerOperand(), - AA.getTypeStoreSize(LI->getType()), - LI->getMetadata(LLVMContext::MD_tbaa)); + AliasAnalysis::Location Loc = AA.getLocation(LI); MDA.getNonLocalPointerDependency(Loc, !LI->isVolatile(), LI->getParent(), NLDI); } else if (StoreInst *SI = dyn_cast(Inst)) { // FIXME: Volatile is not handled properly here. - AliasAnalysis::Location Loc(SI->getPointerOperand(), - AA.getTypeStoreSize(SI->getValueOperand() - ->getType()), - SI->getMetadata(LLVMContext::MD_tbaa)); + AliasAnalysis::Location Loc = AA.getLocation(SI); MDA.getNonLocalPointerDependency(Loc, false, SI->getParent(), NLDI); } else if (VAArgInst *VI = dyn_cast(Inst)) { - AliasAnalysis::Location Loc(SI->getPointerOperand(), - AliasAnalysis::UnknownSize, - SI->getMetadata(LLVMContext::MD_tbaa)); + AliasAnalysis::Location Loc = AA.getLocation(VI); MDA.getNonLocalPointerDependency(Loc, false, VI->getParent(), NLDI); } else { llvm_unreachable("Unknown memory instruction!"); Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Thu Nov 11 15:50:19 2010 @@ -115,9 +115,7 @@ Loc = AliasAnalysis::Location(); return AliasAnalysis::ModRef; } - Loc = AliasAnalysis::Location(LI->getPointerOperand(), - AA->getTypeStoreSize(LI->getType()), - LI->getMetadata(LLVMContext::MD_tbaa)); + Loc = AA->getLocation(LI); return AliasAnalysis::Ref; } @@ -126,17 +124,12 @@ Loc = AliasAnalysis::Location(); return AliasAnalysis::ModRef; } - Loc = AliasAnalysis::Location(SI->getPointerOperand(), - AA->getTypeStoreSize(SI->getValueOperand() - ->getType()), - SI->getMetadata(LLVMContext::MD_tbaa)); + Loc = AA->getLocation(SI); return AliasAnalysis::Mod; } if (const VAArgInst *V = dyn_cast(Inst)) { - Loc = AliasAnalysis::Location(V->getPointerOperand(), - AA->getTypeStoreSize(V->getType()), - V->getMetadata(LLVMContext::MD_tbaa)); + Loc = AA->getLocation(V); return AliasAnalysis::ModRef; } @@ -288,10 +281,7 @@ // Values depend on loads if the pointers are must aliased. This means that // a load depends on another must aliased load from the same value. if (LoadInst *LI = dyn_cast(Inst)) { - Value *Pointer = LI->getPointerOperand(); - uint64_t PointerSize = AA->getTypeStoreSize(LI->getType()); - MDNode *TBAATag = LI->getMetadata(LLVMContext::MD_tbaa); - AliasAnalysis::Location LoadLoc(Pointer, PointerSize, TBAATag); + AliasAnalysis::Location LoadLoc = AA->getLocation(LI); // If we found a pointer, check if it could be the same as our pointer. AliasAnalysis::AliasResult R = AA->alias(LoadLoc, MemLoc); @@ -324,14 +314,10 @@ // Ok, this store might clobber the query pointer. Check to see if it is // a must alias: in this case, we want to return this as a def. - Value *Pointer = SI->getPointerOperand(); - uint64_t PointerSize = AA->getTypeStoreSize(SI->getOperand(0)->getType()); - MDNode *TBAATag = SI->getMetadata(LLVMContext::MD_tbaa); + AliasAnalysis::Location StoreLoc = AA->getLocation(SI); // If we found a pointer, check if it could be the same as our pointer. - AliasAnalysis::AliasResult R = - AA->alias(AliasAnalysis::Location(Pointer, PointerSize, TBAATag), - MemLoc); + AliasAnalysis::AliasResult R = AA->alias(StoreLoc, MemLoc); if (R == AliasAnalysis::NoAlias) continue; Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Thu Nov 11 15:50:19 2010 @@ -433,10 +433,7 @@ LoadInst *Load = Loads[i]; BasicBlock *BB = Load->getParent(); - AliasAnalysis::Location Loc(Load->getPointerOperand(), - AA.getTypeStoreSize(Load->getType()), - Load->getMetadata(LLVMContext::MD_tbaa)); - + AliasAnalysis::Location Loc = AA.getLocation(Load); if (AA.canInstructionRangeModify(BB->front(), *Load, Loc)) return false; // Pointer is invalidated! Modified: llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp Thu Nov 11 15:50:19 2010 @@ -165,27 +165,20 @@ } else if (LoadInst *LI = dyn_cast(I)) { // Ignore non-volatile loads from local memory. if (!LI->isVolatile()) { - AliasAnalysis::Location Loc(LI->getPointerOperand(), - AA->getTypeStoreSize(LI->getType()), - LI->getMetadata(LLVMContext::MD_tbaa)); + AliasAnalysis::Location Loc = AA->getLocation(LI); if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) continue; } } else if (StoreInst *SI = dyn_cast(I)) { // Ignore non-volatile stores to local memory. if (!SI->isVolatile()) { - const Type *StoredType = SI->getValueOperand()->getType(); - AliasAnalysis::Location Loc(SI->getPointerOperand(), - AA->getTypeStoreSize(StoredType), - SI->getMetadata(LLVMContext::MD_tbaa)); + AliasAnalysis::Location Loc = AA->getLocation(SI); if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) continue; } } else if (VAArgInst *VI = dyn_cast(I)) { // Ignore vaargs on local memory. - AliasAnalysis::Location Loc(VI->getPointerOperand(), - AliasAnalysis::UnknownSize, - VI->getMetadata(LLVMContext::MD_tbaa)); + AliasAnalysis::Location Loc = AA->getLocation(VI); if (AA->pointsToConstantMemory(Loc, /*OrLocal=*/true)) continue; } Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Nov 11 15:50:19 2010 @@ -1351,11 +1351,8 @@ SmallVectorImpl &toErase) { // Find the non-local dependencies of the load. SmallVector Deps; - AliasAnalysis::Location Loc(LI->getPointerOperand(), - VN.getAliasAnalysis()->getTypeStoreSize(LI->getType()), - LI->getMetadata(LLVMContext::MD_tbaa)); - MD->getNonLocalPointerDependency(Loc, true, LI->getParent(), - Deps); + AliasAnalysis::Location Loc = VN.getAliasAnalysis()->getLocation(LI); + MD->getNonLocalPointerDependency(Loc, true, LI->getParent(), Deps); //DEBUG(dbgs() << "INVESTIGATING NONLOCAL LOAD: " // << Deps.size() << *LI << '\n'); Modified: llvm/trunk/lib/Transforms/Scalar/Sink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Sink.cpp?rev=118845&r1=118844&r2=118845&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Sink.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Sink.cpp Thu Nov 11 15:50:19 2010 @@ -15,7 +15,6 @@ #define DEBUG_TYPE "sink" #include "llvm/Transforms/Scalar.h" #include "llvm/IntrinsicInst.h" -#include "llvm/LLVMContext.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -157,10 +156,7 @@ if (LoadInst *L = dyn_cast(Inst)) { if (L->isVolatile()) return false; - Value *Ptr = L->getPointerOperand(); - uint64_t Size = AA->getTypeStoreSize(L->getType()); - const MDNode *TBAAInfo = L->getMetadata(LLVMContext::MD_tbaa); - AliasAnalysis::Location Loc(Ptr, Size, TBAAInfo); + AliasAnalysis::Location Loc = AA->getLocation(L); for (SmallPtrSet::iterator I = Stores.begin(), E = Stores.end(); I != E; ++I) if (AA->getModRefInfo(*I, Loc) & AliasAnalysis::Mod) From nicholas at mxc.ca Thu Nov 11 15:51:44 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 11 Nov 2010 21:51:44 -0000 Subject: [llvm-commits] [llvm] r118846 - /llvm/trunk/lib/VMCore/Value.cpp Message-ID: <20101111215144.7463E2A6C12C@llvm.org> Author: nicholas Date: Thu Nov 11 15:51:44 2010 New Revision: 118846 URL: http://llvm.org/viewvc/llvm-project?rev=118846&view=rev Log: Doxygenify Modified: llvm/trunk/lib/VMCore/Value.cpp Modified: llvm/trunk/lib/VMCore/Value.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=118846&r1=118845&r2=118846&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Value.cpp (original) +++ llvm/trunk/lib/VMCore/Value.cpp Thu Nov 11 15:51:44 2010 @@ -368,7 +368,7 @@ } /// isDereferenceablePointer - Test if this value is always a pointer to -// allocated and suitably aligned memory for a simple load or store. +/// allocated and suitably aligned memory for a simple load or store. bool Value::isDereferenceablePointer() const { // Note that it is not safe to speculate into a malloc'd region because // malloc may return null. From jasonwkim at google.com Thu Nov 11 16:07:52 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 14:07:52 -0800 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: References: <20101108164727.39B812A6C12C@llvm.org> Message-ID: ---------- Forwarded message ---------- From: Jason Kim Date: Thu, Nov 11, 2010 at 2:07 PM Subject: Re: [llvm-commits] [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h To: Rafael Esp?ndola On Tue, Nov 9, 2010 at 1:07 PM, Rafael Esp?ndola wrote: >> + ? ? ?R_ARM_THM_CALL ? ? ? ? ? ? ?= 0x0a, > > The names don't match what I have on a linux system. For example > > #define R_ARM_THM_PC22 ? ? ? ? ?10 > > Are there two independent naming conventions for ARM relocations? The names are from the 2.08 ABI manual from ARM (aaelf) ARM IHI 0044D, current through ABI release 2.08 I don't know where linux gets its names from. Thanks -jason > > Cheers, > Rafael > From jasonwkim at google.com Thu Nov 11 16:21:42 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 14:21:42 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: <4CDC31E2.3050009@arm.com> References: <4CDC31E2.3050009@arm.com> Message-ID: On Thu, Nov 11, 2010 at 10:11 AM, Renato Golin wrote: > On 10/11/10 17:57, Jason Kim wrote: >> tryA: move the functionality of the ELFObjectWriterImpl class into >> ELFObjectWriter, and subclass ELFObjectWriter to >> ELFObjectWriter. > ?> > (...) >> >> tryB: subclass ELFObjectWriterImpl instead - I am still working out >> the details on this one - but as of right now, it is just as complex >> as the tryA case. > > I'm not an expert in MC, but I can't see anything wrong with neither > approaches. The second one seems less invasive, but has the problems you > mentioned. > > As MachO and ELF are very different, I can't see now the big problem of > conceptually separating them. > > As far as I could gather, you only moved things around, so no problems > for ARM. In this sense, I'm happy with both patches. Hi Everyone, tryB *is* less invasive, but tryA1 (included) is still the better approach IMO tryA1 has 1 new class total, and two fewer slots, and no trampolines (a plus IMO), and requires 4 changes to the places where ELFObjectWriter is created, but given that this is already in a arch-specific factory function, its not a big deal. tryB has 2 new classes total, and has the trampolines (a PLUS if you think ELF should be implemented in a similar fashion to the MachO code) I'd like to push in tryA - as I need this refactoring to proceed further in ARM/MC/ELF work. combined.patch is just a straight cat of all subpatches in sequence, so its larger than the svn diff ( arm-mc-elf-s07-elfwriter-tryA-combined.patch) http://codereview.chromium.org/4828001 -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf-s07-elfwriter-tryA-combined.patch Type: text/x-patch Size: 43385 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/7d10c638/attachment-0002.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: combined.patch Type: text/x-patch Size: 81121 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/7d10c638/attachment-0003.bin From peckw at wesleypeck.com Thu Nov 11 16:21:08 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Thu, 11 Nov 2010 22:21:08 -0000 Subject: [llvm-commits] [llvm] r118848 - /llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Message-ID: <20101111222108.D80242A6C12C@llvm.org> Author: peckw Date: Thu Nov 11 16:21:08 2010 New Revision: 118848 URL: http://llvm.org/viewvc/llvm-project?rev=118848&view=rev Log: The BRK instruction in the MicroBlaze is a branch-and-link. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118848&r1=118847&r2=118848&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Thu Nov 11 16:21:08 2010 @@ -606,8 +606,8 @@ "wic $a, $b", [], IIAlu>; } -def BRK : Branch<0x26, 0x0C, 0x000, "brk ">; -def BRKI : BranchI<0x2E, 0x0C, "brki ">; +def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">; +def BRKI : BranchLI<0x2E, 0x0C, "brki ">; def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), "imm $imm", [], IIAlu>; From jasonwkim at google.com Thu Nov 11 16:22:48 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 14:22:48 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: References: <4CDC31E2.3050009@arm.com> Message-ID: On Thu, Nov 11, 2010 at 2:21 PM, Jason Kim wrote: > On Thu, Nov 11, 2010 at 10:11 AM, Renato Golin wrote: >> On 10/11/10 17:57, Jason Kim wrote: >>> tryA: move the functionality of the ELFObjectWriterImpl class into >>> ELFObjectWriter, and subclass ELFObjectWriter to >>> ELFObjectWriter. >> ?> >> (...) >>> >>> tryB: subclass ELFObjectWriterImpl instead - I am still working out >>> the details on this one - but as of right now, it is just as complex >>> as the tryA case. >> >> I'm not an expert in MC, but I can't see anything wrong with neither >> approaches. The second one seems less invasive, but has the problems you >> mentioned. >> >> As MachO and ELF are very different, I can't see now the big problem of >> conceptually separating them. >> >> As far as I could gather, you only moved things around, so no problems >> for ARM. In this sense, I'm happy with both patches. > > > Hi Everyone, > > tryB *is* less invasive, but tryA1 (included) is still the better approach IMO > > tryA1 has 1 new class total, and two fewer slots, and no trampolines > (a plus IMO), and requires 4 changes to the places where > ELFObjectWriter is created, but given that this is already in a > arch-specific factory function, its not a big deal. > > tryB has 2 new classes total, and has the trampolines (a PLUS if you > think ELF should be implemented in a similar fashion to the MachO > code) > > I'd like to push in tryA - as I need this refactoring to proceed tryA1 oops. > further in ARM/MC/ELF work. > > combined.patch is just a straight cat of all subpatches ?in sequence, > so its larger than the svn diff ( > arm-mc-elf-s07-elfwriter-tryA-combined.patch) > > http://codereview.chromium.org/4828001 > From gkistanova at gmail.com Thu Nov 11 16:28:54 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Thu, 11 Nov 2010 22:28:54 -0000 Subject: [llvm-commits] [zorg] r118849 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20101111222854.DE1742A6C12C@llvm.org> Author: gkistanova Date: Thu Nov 11 16:28:54 2010 New Revision: 118849 URL: http://llvm.org/viewvc/llvm-project?rev=118849&view=rev Log: Added new builder llvm-gcc arm-eabi soft float. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=118849&r1=118848&r2=118849&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Nov 11 16:28:54 2010 @@ -550,18 +550,62 @@ 'haltOnFailure' : True }, {'name' : 'make_llvm', 'description' : 'make llvm', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j4'], 'haltOnFailure' : True }, {'name' : 'install_llvm', 'description' : 'install llvm', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j4'], 'haltOnFailure' : False }, {'name' : 'configure_llvmgcc', 'description' : 'configure llvm-gcc', 'haltOnFailure' : True }, {'name' : 'make_llvmgcc', 'description' : 'make llvm-gcc', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j4'], + 'haltOnFailure' : True }, + {'name' : 'install_llvmgcc', + 'description' : 'install llvm-gcc', + 'haltOnFailure' : True },]), + 'category' : 'llvm-gcc' }, + + {'name' : "llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-soft-float", + 'slavenames': [ "kistanova4" ], + 'builddir' : "llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-soft-float", + 'factory' : ScriptedBuilder.getScriptedBuildFactory( + source_code = [SVN(name='svn-llvm', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/', + defaultBranch='trunk', + workdir="llvm.src"), + SVN(name='svn-llvm-gcc', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm-gcc-4.2/', + defaultBranch='trunk', + workdir="llvm-gcc.src"),], + launcher = 'llvm-gcc.src/extras/buildbot-launcher', + build_script = 'llvm-gcc.src/extras/build-x-4-armeabi-softfloat', + extra_args = [], + build_steps = [{'name' : 'clean', + 'description' : 'clean', + 'haltOnFailure' : True }, + {'name' : 'copy_cross_tools', + 'description' : 'copy cross-tools', + 'haltOnFailure' : True }, + {'name' : 'configure_llvm', + 'description' : 'configure llvm', + 'haltOnFailure' : True }, + {'name' : 'make_llvm', + 'description' : 'make llvm', + 'extra_args' : ['-j4'], + 'haltOnFailure' : True }, + {'name' : 'install_llvm', + 'description' : 'install llvm', + 'extra_args' : ['-j4'], + 'haltOnFailure' : False }, + {'name' : 'configure_llvmgcc', + 'description' : 'configure llvm-gcc', + 'haltOnFailure' : True }, + {'name' : 'make_llvmgcc', + 'description' : 'make llvm-gcc', + 'extra_args' : ['-j4'], 'haltOnFailure' : True }, {'name' : 'install_llvmgcc', 'description' : 'install llvm-gcc', From rafael.espindola at gmail.com Thu Nov 11 16:33:37 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Thu, 11 Nov 2010 17:33:37 -0500 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: References: <20101108164727.39B812A6C12C@llvm.org> Message-ID: > The names are from the 2.08 ABI manual from ARM (aaelf) > ARM IHI 0044D, current through ABI release 2.08 > > I don't know where linux gets its names from. Yes, this is strange. binutils uses R_ARM_THM_CALL everywhere except for defining some aliases: /* Unofficial names for some of the relocs. */ FAKE_RELOC (R_ARM_GOTOFF, R_ARM_GOTOFF32) /* 32 bit offset to GOT. */ FAKE_RELOC (R_ARM_THM_PC22, R_ARM_THM_CALL) FAKE_RELOC (R_ARM_THM_PC11, R_ARM_THM_JUMP11) FAKE_RELOC (R_ARM_THM_PC9, R_ARM_THM_JUMP8) Renato, do you know where do they come from? Are they just aliases? Hopefully we can just use the "official" ones . Cheers, Rafael From aggarwa4 at illinois.edu Thu Nov 11 16:40:33 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 11 Nov 2010 22:40:33 -0000 Subject: [llvm-commits] [poolalloc] r118850 - /poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp Message-ID: <20101111224033.1AF602A6C12C@llvm.org> Author: aggarwa4 Date: Thu Nov 11 16:40:32 2010 New Revision: 118850 URL: http://llvm.org/viewvc/llvm-project?rev=118850&view=rev Log: Making the function verifyCallees to run only in DEBUG case Modified: poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp Modified: poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp?rev=118850&r1=118849&r2=118850&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp (original) +++ poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp Thu Nov 11 16:40:32 2010 @@ -45,7 +45,8 @@ //update the EQ class from indirect calls buildIndirectFunctionSets(); mergeGraphsByGlobalECs(); - verifyMerging(); + + DEBUG(verifyMerging()); bool result = runOnModuleInternal(M); // CBU contains the correct call graph. // Restore it, so that subsequent passes and clients can get it. @@ -53,6 +54,8 @@ return result; } +// Verifies that all the functions in an equivalence calss have been merged. +// This is required by to be true by poolallocation. void EquivBUDataStructures::verifyMerging() { From resistor at mac.com Thu Nov 11 17:12:55 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 11 Nov 2010 23:12:55 -0000 Subject: [llvm-commits] [llvm] r118854 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/neont2-absdiff-encoding.s test/MC/ARM/neont2-bitcount-encoding.s test/MC/ARM/neont2-bitwise-encoding.s test/MC/ARM/neont2-convert-encoding.s test/MC/ARM/neont2-dup-encoding.s test/MC/ARM/neont2-mov-encoding.s test/MC/ARM/neont2-mul-accum-encoding.s test/MC/ARM/neont2-pairwise-encoding.s test/MC/ARM/neont2-table-encoding.s Message-ID: <20101111231255.7F2882A6C12C@llvm.org> Author: resistor Date: Thu Nov 11 17:12:55 2010 New Revision: 118854 URL: http://llvm.org/viewvc/llvm-project?rev=118854&view=rev Log: Fill out support for Thumb2 encodings of NEON instructions. Added: llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s llvm/trunk/test/MC/ARM/neont2-convert-encoding.s llvm/trunk/test/MC/ARM/neont2-dup-encoding.s llvm/trunk/test/MC/ARM/neont2-mov-encoding.s llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s llvm/trunk/test/MC/ARM/neont2-table-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118854&r1=118853&r2=118854&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 11 17:12:55 2010 @@ -165,6 +165,8 @@ const { return 0; } unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) const { return 0; } + unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) + const { return 0; } unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118854&r1=118853&r2=118854&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 11 17:12:55 2010 @@ -2046,6 +2046,8 @@ let Pattern = pattern; list Predicates = [HasNEON]; + string PostEncoderMethod = "NEONThumb2DupPostEncoder"; + bits<5> V; bits<4> R; bits<4> p; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118854&r1=118853&r2=118854&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 11 17:12:55 2010 @@ -176,6 +176,8 @@ unsigned EncodedValue) const; unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned EncodedValue) const; + unsigned NEONThumb2DupPostEncoder(const MCInst &MI, + unsigned EncodedValue) const; void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; @@ -234,6 +236,21 @@ return EncodedValue; } +/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup +/// instructions, and rewrite them to their Thumb2 form if we are currently in +/// Thumb2 mode. +unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, + unsigned EncodedValue) const { + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isThumb2()) { + EncodedValue &= 0x00FFFFFF; + EncodedValue |= 0xEE000000; + } + + return EncodedValue; +} + + /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. Added: llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,86 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * +@ NOTE: This currently fails because the ASM parser doesn't parse vabal. + +.code 16 + +@ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xef] + vabd.s8 d16, d16, d17 +@ CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xef] + vabd.s16 d16, d16, d17 +@ CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xef] + vabd.s32 d16, d16, d17 +@ CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xff] + vabd.u8 d16, d16, d17 +@ CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xff] + vabd.u16 d16, d16, d17 + @ CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xff] + vabd.u32 d16, d16, d17 +@ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xff] + vabd.f32 d16, d16, d17 +@ CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xef] + vabd.s8 q8, q8, q9 +@ CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xef] + vabd.s16 q8, q8, q9 +@ CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xef] + vabd.s32 q8, q8, q9 +@ CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xff] + vabd.u8 q8, q8, q9 +@ CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xff] + vabd.u16 q8, q8, q9 +@ CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xff] + vabd.u32 q8, q8, q9 +@ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xff] + vabd.f32 q8, q8, q9 + +@ CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xef] + vabdl.s8 q8, d16, d17 +@ CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xef] + vabdl.s16 q8, d16, d17 +@ CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xef] + vabdl.s32 q8, d16, d17 +@ CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xff] + vabdl.u8 q8, d16, d17 +@ CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xff] + vabdl.u16 q8, d16, d17 +@ CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xff] + vabdl.u32 q8, d16, d17 + +@ CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xef] + vaba.s8 d16, d18, d17 +@ CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xef] + vaba.s16 d16, d18, d17 +@ CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xef] + vaba.s32 d16, d18, d17 +@ CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xff] + vaba.u8 d16, d18, d17 +@ CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xff] + vaba.u16 d16, d18, d17 +@ CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xff] + vaba.u32 d16, d18, d17 +@ CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xef] + vaba.s8 q9, q8, q10 +@ CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xef] + vaba.s16 q9, q8, q10 +@ CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xef] + vaba.s32 q9, q8, q10 +@ CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xff] + vaba.u8 q9, q8, q10 +@ CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xff] + vaba.u16 q9, q8, q10 +@ CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xff] + vaba.u32 q9, q8, q10 + +@ CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xef] + vabal.s8 q8, d19, d18 +@ CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xef] + vabal.s16 q8, d19, d18 +@ CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xef] + vabal.s32 q8, d19, d18 +@ CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xff] + vabal.u8 q8, d19, d18 +@ CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xff] + vabal.u16 q8, d19, d18 +@ CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xff] + vabal.u32 q8, d19, d18 + Added: llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,34 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xff] + vcnt.8 d16, d16 +@ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xff] + vcnt.8 q8, q8 +@ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xff] + vclz.i8 d16, d16 +@ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xff] + vclz.i16 d16, d16 +@ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xff] + vclz.i32 d16, d16 +@ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xff] + vclz.i8 q8, q8 +@ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xff] + vclz.i16 q8, q8 +@ CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xff] + vclz.i32 q8, q8 +@ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xff] + vcls.s8 d16, d16 +@ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xff] + vcls.s16 d16, d16 +@ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xff] + vcls.s32 d16, d16 +@ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xff] + vcls.s8 q8, q8 +@ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xff] + vcls.s16 q8, q8 +@ CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xff] + vcls.s32 q8, q8 + Added: llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,49 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xef] + vand d16, d17, d16 +@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xef] + vand q8, q8, q9 + +@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xff] + veor d16, d17, d16 +@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xff] + veor q8, q8, q9 + +@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xef] + vorr d16, d17, d16 +@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xef] + vorr q8, q8, q9 +@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xef] + vorr.i32 d16, #0x1000000 +@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xef] + vorr.i32 q8, #0x1000000 +@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xef] + vorr.i32 q8, #0x0 + +@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xef] + vbic d16, d17, d16 +@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xef] + vbic q8, q8, q9 +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xff] + vbic.i32 d16, #0xFF000000 +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xff] + vbic.i32 q8, #0xFF000000 + +@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xef] + vorn d16, d17, d16 +@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xef] + vorn q8, q8, q9 + +@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xff] + vmvn d16, d16 +@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xff] + vmvn q8, q8 + +@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xff] + vbsl d18, d17, d16 +@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xff] + vbsl q8, q10, q9 Added: llvm/trunk/test/MC/ARM/neont2-convert-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-convert-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-convert-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-convert-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,36 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xff] + vcvt.s32.f32 d16, d16 +@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xff] + vcvt.u32.f32 d16, d16 +@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xff] + vcvt.f32.s32 d16, d16 +@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xff] + vcvt.f32.u32 d16, d16 +@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xff] + vcvt.s32.f32 q8, q8 +@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xff] + vcvt.u32.f32 q8, q8 +@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xff] + vcvt.f32.s32 q8, q8 +@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xff] + vcvt.f32.u32 q8, q8 +@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xef] + vcvt.s32.f32 d16, d16, #1 +@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xff] + vcvt.u32.f32 d16, d16, #1 +@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xef] + vcvt.f32.s32 d16, d16, #1 +@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xff] + vcvt.f32.u32 d16, d16, #1 +@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xef] + vcvt.s32.f32 q8, q8, #1 +@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xff] + vcvt.u32.f32 q8, q8, #1 +@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xef] + vcvt.f32.s32 q8, q8, #1 +@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xff] + vcvt.f32.u32 q8, q8, #1 Added: llvm/trunk/test/MC/ARM/neont2-dup-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-dup-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-dup-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-dup-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,29 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] + vdup.8 d16, r0 +@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] + vdup.16 d16, r0 +@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] + vdup.32 d16, r0 +@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] + vdup.8 q8, r0 +@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] + vdup.16 q8, r0 +@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] + vdup.32 q8, r0 +@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xff] + vdup.8 d16, d16[1] +@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xff] + vdup.16 d16, d16[1] +@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xff] + vdup.32 d16, d16[1] +@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xff] + vdup.8 q8, d16[1] +@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xff] + vdup.16 q8, d16[1] +@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xff] + vdup.32 q8, d16[1] Added: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,119 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xef] + vmov.i8 d16, #0x8 +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xef] + vmov.i16 d16, #0x10 +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xef] + vmov.i16 d16, #0x1000 +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xef] + vmov.i32 d16, #0x20 +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xef] + vmov.i32 d16, #0x2000 +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xef] + vmov.i32 d16, #0x200000 +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xef] + vmov.i32 d16, #0x20000000 +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xef] + vmov.i32 d16, #0x20FF +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xef] + vmov.i32 d16, #0x20FFFF +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xff] + vmov.i64 d16, #0xFF0000FF0000FFFF +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xef] + vmov.i8 q8, #0x8 +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xef] + vmov.i16 q8, #0x10 +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xef] + vmov.i16 q8, #0x1000 +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xef] + vmov.i32 q8, #0x20 +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xef] + vmov.i32 q8, #0x2000 +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xef] + vmov.i32 q8, #0x200000 +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xef] + vmov.i32 q8, #0x20000000 +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xef] + vmov.i32 q8, #0x20FF +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xef] + vmov.i32 q8, #0x20FFFF +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xff] + vmov.i64 q8, #0xFF0000FF0000FFFF +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xef] + vmvn.i16 d16, #0x10 +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xef] + vmvn.i16 d16, #0x1000 +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xef] + vmvn.i32 d16, #0x20 +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xef] + vmvn.i32 d16, #0x2000 +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xef] + vmvn.i32 d16, #0x200000 +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xef] + vmvn.i32 d16, #0x20000000 +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xef] + vmvn.i32 d16, #0x20FF +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xef] + vmvn.i32 d16, #0x20FFFF +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xef] + vmovl.s8 q8, d16 +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xef] + vmovl.s16 q8, d16 +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xef] + vmovl.s32 q8, d16 +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xff] + vmovl.u8 q8, d16 +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xff] + vmovl.u16 q8, d16 +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xff] + vmovl.u32 q8, d16 +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xff] + vmovn.i16 d16, q8 +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xff] + vmovn.i32 d16, q8 +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xff] + vmovn.i64 d16, q8 +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xff] + vqmovn.s16 d16, q8 +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xff] + vqmovn.s32 d16, q8 +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xff] + vqmovn.s64 d16, q8 +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xff] + vqmovn.u16 d16, q8 +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xff] + vqmovn.u32 d16, q8 +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xff] + vqmovn.u64 d16, q8 +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xff] + vqmovun.s16 d16, q8 +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xff] + vqmovun.s32 d16, q8 +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xff] + vqmovun.s64 d16, q8 +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] + vmov.s8 r0, d16[1] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] + vmov.s16 r0, d16[1] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] + vmov.u8 r0, d16[1] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] + vmov.u16 r0, d16[1] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] + vmov.32 r0, d16[1] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] + vmov.8 d16[1], r1 +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] + vmov.16 d16[1], r1 +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] + vmov.32 d16[1], r1 +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] + vmov.8 d18[1], r1 +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] + vmov.16 d18[1], r1 +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] + vmov.32 d18[1], r1 Added: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,69 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xef] + vmla.i8 d16, d18, d17 +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xef] + vmla.i16 d16, d18, d17 +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xef] + vmla.i32 d16, d18, d17 +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xef] + vmla.f32 d16, d18, d17 +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xef] + vmla.i8 q9, q8, q10 +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xef] + vmla.i16 q9, q8, q10 +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xef] + vmla.i32 q9, q8, q10 +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xef] + vmla.f32 q9, q8, q10 +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xef] + vmlal.s8 q8, d19, d18 +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xef] + vmlal.s16 q8, d19, d18 +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xef] + vmlal.s32 q8, d19, d18 +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xff] + vmlal.u8 q8, d19, d18 +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xff] + vmlal.u16 q8, d19, d18 +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xff] + vmlal.u32 q8, d19, d18 +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xef] + vqdmlal.s16 q8, d19, d18 +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xef] + vqdmlal.s32 q8, d19, d18 +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xff] + vmls.i8 d16, d18, d17 +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xff] + vmls.i16 d16, d18, d17 +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xff] + vmls.i32 d16, d18, d17 +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xef] + vmls.f32 d16, d18, d17 +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xff] + vmls.i8 q9, q8, q10 +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xff] + vmls.i16 q9, q8, q10 +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xff] + vmls.i32 q9, q8, q10 +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xef] + vmls.f32 q9, q8, q10 +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xef] + vmlsl.s8 q8, d19, d18 +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xef] + vmlsl.s16 q8, d19, d18 +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xef] + vmlsl.s32 q8, d19, d18 +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xff] + vmlsl.u8 q8, d19, d18 +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xff] + vmlsl.u16 q8, d19, d18 +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xff] + vmlsl.u32 q8, d19, d18 +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xef] + vqdmlsl.s16 q8, d19, d18 +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xef] + vqdmlsl.s32 q8, d19, d18 Added: llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,89 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xef] + vpadd.i8 d16, d17, d16 +@ CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xef] + vpadd.i16 d16, d17, d16 +@ CHECK: vpadd.i32 d16, d17, d16 @ encoding: [0xb0,0x0b,0x61,0xef] + vpadd.i32 d16, d17, d16 +@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xff] + vpadd.f32 d16, d16, d17 +@ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xff] + vpaddl.s8 d16, d16 +@ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xff] + vpaddl.s16 d16, d16 +@ CHECK: vpaddl.s32 d16, d16 @ encoding: [0x20,0x02,0xf8,0xff] + vpaddl.s32 d16, d16 +@ CHECK: vpaddl.u8 d16, d16 @ encoding: [0xa0,0x02,0xf0,0xff] + vpaddl.u8 d16, d16 +@ CHECK: vpaddl.u16 d16, d16 @ encoding: [0xa0,0x02,0xf4,0xff] + vpaddl.u16 d16, d16 +@ CHECK: vpaddl.u32 d16, d16 @ encoding: [0xa0,0x02,0xf8,0xff] + vpaddl.u32 d16, d16 +@ CHECK: vpaddl.s8 q8, q8 @ encoding: [0x60,0x02,0xf0,0xff] + vpaddl.s8 q8, q8 +@ CHECK: vpaddl.s16 q8, q8 @ encoding: [0x60,0x02,0xf4,0xff] + vpaddl.s16 q8, q8 +@ CHECK: vpaddl.s32 q8, q8 @ encoding: [0x60,0x02,0xf8,0xff] + vpaddl.s32 q8, q8 +@ CHECK: vpaddl.u8 q8, q8 @ encoding: [0xe0,0x02,0xf0,0xff] + vpaddl.u8 q8, q8 +@ CHECK: vpaddl.u16 q8, q8 @ encoding: [0xe0,0x02,0xf4,0xff] + vpaddl.u16 q8, q8 +@ CHECK: vpaddl.u32 q8, q8 @ encoding: [0xe0,0x02,0xf8,0xff] + vpaddl.u32 q8, q8 +@ CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xff] + vpadal.s8 d16, d17 +@ CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xff] + vpadal.s16 d16, d17 +@ CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xff] + vpadal.s32 d16, d17 +@ CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xff] + vpadal.u8 d16, d17 +@ CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xff] + vpadal.u16 d16, d17 +@ CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xff] + vpadal.u32 d16, d17 +@ CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xff] + vpadal.s8 q9, q8 +@ CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xff] + vpadal.s16 q9, q8 +@ CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xff] + vpadal.s32 q9, q8 +@ CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xff] + vpadal.u8 q9, q8 +@ CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xff] + vpadal.u16 q9, q8 +@ CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xff] + vpadal.u32 q9, q8 +@ CHECK: vpmin.s8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xef] + vpmin.s8 d16, d16, d17 +@ CHECK: vpmin.s16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xef] + vpmin.s16 d16, d16, d17 +@ CHECK: vpmin.s32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xef] + vpmin.s32 d16, d16, d17 +@ CHECK: vpmin.u8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xff] + vpmin.u8 d16, d16, d17 +@ CHECK: vpmin.u16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xff] + vpmin.u16 d16, d16, d17 +@ CHECK: vpmin.u32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xff] + vpmin.u32 d16, d16, d17 +@ CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xff] + vpmin.f32 d16, d16, d17 +@ CHECK: vpmax.s8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xef] + vpmax.s8 d16, d16, d17 +@ CHECK: vpmax.s16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xef] + vpmax.s16 d16, d16, d17 +@ CHECK: vpmax.s32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xef] + vpmax.s32 d16, d16, d17 +@ CHECK: vpmax.u8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xff] + vpmax.u8 d16, d16, d17 +@ CHECK: vpmax.u16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xff] + vpmax.u16 d16, d16, d17 +@ CHECK: vpmax.u32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xff] + vpmax.u32 d16, d16, d17 +@ CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xff] + vpmax.f32 d16, d16, d17 Added: llvm/trunk/test/MC/ARM/neont2-table-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-table-encoding.s?rev=118854&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-table-encoding.s (added) +++ llvm/trunk/test/MC/ARM/neont2-table-encoding.s Thu Nov 11 17:12:55 2010 @@ -0,0 +1,21 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s +@ XFAIL: * + +.code 16 + +@ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xff] + vtbl.8 d16, {d17}, d16 +@ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xff] + vtbl.8 d16, {d16, d17}, d18 +@ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xff] + vtbl.8 d16, {d16, d17, d18}, d20 +@ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xff] + vtbl.8 d16, {d16, d17, d18, d19}, d20 +@ CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xff] + vtbx.8 d18, {d16}, d17 +@ CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xff] + vtbx.8 d19, {d16, d17}, d18 +@ CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xff] + vtbx.8 d20, {d16, d17, d18}, d21 +@ CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xff] + vtbx.8 d20, {d16, d17, d18, d19}, d21 From jasonwkim at google.com Thu Nov 11 17:21:50 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 15:21:50 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: References: <4CDC31E2.3050009@arm.com> Message-ID: On Thu, Nov 11, 2010 at 2:22 PM, Jason Kim wrote: > On Thu, Nov 11, 2010 at 2:21 PM, Jason Kim wrote: >> On Thu, Nov 11, 2010 at 10:11 AM, Renato Golin wrote: >>> On 10/11/10 17:57, Jason Kim wrote: >>>> tryA: move the functionality of the ELFObjectWriterImpl class into >>>> ELFObjectWriter, and subclass ELFObjectWriter to >>>> ELFObjectWriter. >>> ?> >>> (...) >>>> >>>> tryB: subclass ELFObjectWriterImpl instead - I am still working out >>>> the details on this one - but as of right now, it is just as complex >>>> as the tryA case. >>> >>> I'm not an expert in MC, but I can't see anything wrong with neither >>> approaches. The second one seems less invasive, but has the problems you >>> mentioned. >>> >>> As MachO and ELF are very different, I can't see now the big problem of >>> conceptually separating them. >>> >>> As far as I could gather, you only moved things around, so no problems >>> for ARM. In this sense, I'm happy with both patches. >> >> >> Hi Everyone, >> >> tryB *is* less invasive, but tryA1 (included) is still the better approach IMO >> >> tryA1 has 1 new class total, and two fewer slots, and no trampolines >> (a plus IMO), and requires 4 changes to the places where >> ELFObjectWriter is created, but given that this is already in a >> arch-specific factory function, its not a big deal. >> >> tryB has 2 new classes total, and has the trampolines (a PLUS if you >> think ELF should be implemented in a similar fashion to the MachO >> code) >> >> I'd like to push in tryA - as I need this refactoring to proceed > tryA1 oops. > >> further in ARM/MC/ELF work. >> >> combined.patch is just a straight cat of all subpatches ?in sequence, >> so its larger than the svn diff ( >> arm-mc-elf-s07-elfwriter-tryA-combined.patch) oops. I resent the older tryA patch by mistake :-( Sorry for the noise The differences between A and A1 are minimal - tryA1 is a rebased version of tryA at -r118813 rior included combined.patch is the A1 sequence of sub-patches. The diffview URL shows the correct rebased combined diff. -jason >> >> http://codereview.chromium.org/4828001 >> > -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf-s07-tryA1.patch Type: text/x-patch Size: 46272 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/46514d93/attachment-0001.bin From sabre at nondot.org Thu Nov 11 17:28:11 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 23:28:11 -0000 Subject: [llvm-commits] [www-pubs] r118855 - in /www-pubs/trunk: 2010-10-HotDep-CrashRecovery.html 2010-10-HotDep-CrashRecovery.pdf pubs.js Message-ID: <20101111232811.AC6332A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 17:28:11 2010 New Revision: 118855 URL: http://llvm.org/viewvc/llvm-project?rev=118855&view=rev Log: add another new paper Added: www-pubs/trunk/2010-10-HotDep-CrashRecovery.html www-pubs/trunk/2010-10-HotDep-CrashRecovery.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-10-HotDep-CrashRecovery.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-10-HotDep-CrashRecovery.html?rev=118855&view=auto ============================================================================== --- www-pubs/trunk/2010-10-HotDep-CrashRecovery.html (added) +++ www-pubs/trunk/2010-10-HotDep-CrashRecovery.html Thu Nov 11 17:28:11 2010 @@ -0,0 +1,58 @@ + + + + + + We Crashed, Now What? + + + +
    + We Crashed, Now What? +
    +
    + Cristiano Giuffrida, Lorenzo Cavallaro, and Andrew S. Tanenbaum +
    + +

    Abstract:

    +
    +

    +We present an in-depth analysis of the crash-recovery +problem and propose a novel approach to recover from +otherwise fatal operating system (OS) crashes. We show +how an unconventional, but careful, OS design, aided by +automatic compiler-based code instrumentation, offers a +practical solution towards the survivability of the entire +system. Current results are encouraging and show that +our approach is able to recover even the most critical OS +subsystems without exposing the failure to user applications +or hampering the scalability of the system. +

    +
    + +

    Published:

    +
    + "We Crashed, Now What?"
    + Cristiano Giuffrida, Lorenzo Cavallaro, and Andrew S. Tanenbaum
    +In the Proceedings of the 6th Workshop on Hot Topics in System Dependability + (HotDep '10), +October 3, 2010, Vancouver, BC, Canada +
    + +

    Download:

    +

    Paper:

    + + + +
    + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-10-HotDep-CrashRecovery.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-10-HotDep-CrashRecovery.pdf?rev=118855&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-10-HotDep-CrashRecovery.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=118855&r1=118854&r2=118855&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Thu Nov 11 17:28:11 2010 @@ -1,6 +1,15 @@ // The array should be sorted reverse-chronologically, and will be displayed on // the page in the order listed. -var PUBS = [ +var PUBS = +[{ url: "2010-10-HotDep-CrashRecovery.html", + title: "We Crashed, Now What?", +published: "Proc. of the 6th Workshop on Hot Topics in System Dependability (HotDep '10)", +location: "Vancouver, BC, Canada", +author: "Cristiano Giuffrida, Lorenzo Cavallaro, and Andrew S. Tanenbaum", + month: 10, + year: 2010 + }, + {url: "2010-09-HASKELLSYM-LLVM-GHC.html", title: "An LLVM Backend for GHC", published: "ACM SIGPLAN Haskell Symposium 2010", From sabre at nondot.org Thu Nov 11 17:38:49 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 23:38:49 -0000 Subject: [llvm-commits] [www-pubs] r118857 - in /www-pubs/trunk: 2010-10-OSDI-BypassingRaces.html 2010-10-OSDI-BypassingRaces.pdf 2010-10-OSDI-DeterministicMT.html 2010-10-OSDI-DeterministicMT.pdf pubs.js Message-ID: <20101111233849.EF9162A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 17:38:49 2010 New Revision: 118857 URL: http://llvm.org/viewvc/llvm-project?rev=118857&view=rev Log: add two more OSDI papers using LLVM. Added: www-pubs/trunk/2010-10-OSDI-BypassingRaces.html www-pubs/trunk/2010-10-OSDI-BypassingRaces.pdf (with props) www-pubs/trunk/2010-10-OSDI-DeterministicMT.html www-pubs/trunk/2010-10-OSDI-DeterministicMT.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-10-OSDI-BypassingRaces.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-10-OSDI-BypassingRaces.html?rev=118857&view=auto ============================================================================== --- www-pubs/trunk/2010-10-OSDI-BypassingRaces.html (added) +++ www-pubs/trunk/2010-10-OSDI-BypassingRaces.html Thu Nov 11 17:38:49 2010 @@ -0,0 +1,52 @@ + + + + + + Bypassing Races in Live Applications with Execution Filters + + + +
    + Bypassing Races in Live Applications with Execution Filters +
    +
    + Jingyue Wu, Heming Cui, Junfeng Yang +
    + +

    Abstract:

    +
    +

    +Deployed multithreaded applications contain many races because these applications are difficult to write, test, and debug. Worse, the number of races in deployed applications may drastically increase due to the rise of multicore hardware and the immaturity of current race detectors.

    + +

    LOOM is a "live-workaround" system designed to quickly and safely bypass application races at runtime. LOOM provides a flexible and safe language for developers to write execution filters that explicitly synchronize code. It then uses an evacuation algorithm to safely install the filters to live applications to avoid races. It reduces its performance overhead using hybrid instrumentation that combines static and dynamic instrumentation.

    + +

    We evaluated LOOM on nine real races from a diverse set of six applications, including MySQL and Apache. Our results show that (1) LOOM can safely fix all evaluated races in a timely manner, thereby increasing application availability; (2) LOOM incurs little performance overhead; (3) LOOM scales well with the number of application threads; and (4) LOOM is easy to use. +

    +
    + +

    Published:

    +
    + "Bypassing Races in Live Applications with Execution Filters"
    + Jingyue Wu, Heming Cui, Junfeng Yang
    +In Proceedings of the Ninth Symposium on Operating Systems Design and Implementation (OSDI '10), +Vancouver, BC, Canada, Oct 2010 +
    + +

    Download:

    +

    Paper:

    + + + +
    + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-10-OSDI-BypassingRaces.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-10-OSDI-BypassingRaces.pdf?rev=118857&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-10-OSDI-BypassingRaces.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Added: www-pubs/trunk/2010-10-OSDI-DeterministicMT.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-10-OSDI-DeterministicMT.html?rev=118857&view=auto ============================================================================== --- www-pubs/trunk/2010-10-OSDI-DeterministicMT.html (added) +++ www-pubs/trunk/2010-10-OSDI-DeterministicMT.html Thu Nov 11 17:38:49 2010 @@ -0,0 +1,50 @@ + + + + + + Stable Deterministic Multithreading through Schedule Memoization + + + +
    + Stable Deterministic Multithreading through Schedule Memoization +
    +
    + Heming Cui, Jingyue Wu, Chia-che Tsai, Junfeng Yang +
    + +

    Abstract:

    +
    +

    +A deterministic multithreading (DMT) system eliminates nondeterminism in thread scheduling, simplifying the development of multithreaded programs. However, existing DMT systems are unstable; they may force a program to (ad)venture into vastly different schedules even for slightly different inputs or execution environments, defeating many benefits of determinism. Moreover, few existing DMT systems work with server programs whose inputs arrive continuously and nondeterministically.

    + +

    TERN is a stable DMT system. The key novelty in TERN is the idea of schedule memoization that memoizes past working schedules and reuses them on future inputs, making program behaviors stable across different inputs. A second novelty in TERN is the idea of windowing that extends schedule memoization to server programs by splitting continuous request streams into windows of requests. Our TERN implementation runs on Linux. It operates as user-space schedulers, requiring no changes to the OS and only a few lines of changes to the application programs. We evaluated TERN on a diverse set of 14 programs (e.g., Apache and MySQL) with real and synthetic workloads. Our results show that TERN is easy to use, makes programs more deterministic and stable, and has reasonable overhead. +

    +
    + +

    Published:

    +
    + "Stable Deterministic Multithreading through Schedule Memoization"
    + Heming Cui, Jingyue Wu, Chia-che Tsai, Junfeng Yang
    +In Proceedings of the Ninth Symposium on Operating Systems Design and Implementation (OSDI '10), +Vancouver, BC, Canada, Oct 2010 +
    + +

    Download:

    +

    Paper:

    + + + +
    + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-10-OSDI-DeterministicMT.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-10-OSDI-DeterministicMT.pdf?rev=118857&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-10-OSDI-DeterministicMT.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=118857&r1=118856&r2=118857&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Thu Nov 11 17:38:49 2010 @@ -9,6 +9,24 @@ month: 10, year: 2010 }, + + [{ url: "2010-10-OSDI-DeterministicMT.html", + title: "Stable Deterministic Multithreading through Schedule Memoization", +published: "Proc. of the Ninth Symposium on Operating Systems Design and Implementation (OSDI '10)", +location: "Vancouver, BC, Canada", + author: "Heming Cui and Jingyue Wu and Chia-che Tsai and Junfeng Yang", + month: 10, + year: 2010 + }, + + [{ url: "2010-10-OSDI-BypassingRaces.html", + title: "Bypassing Races in Live Applications with Execution Filters", +published: "Proc. of the Ninth Symposium on Operating Systems Design and Implementation (OSDI '10)", +location: "Vancouver, BC, Canada", + author: "Jingyue Wu, Heming Cui, Junfeng Yang", + month: 10, + year: 2010 + }, {url: "2010-09-HASKELLSYM-LLVM-GHC.html", title: "An LLVM Backend for GHC", From sabre at nondot.org Thu Nov 11 17:39:56 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 11 Nov 2010 23:39:56 -0000 Subject: [llvm-commits] [www-pubs] r118858 - /www-pubs/trunk/pubs.js Message-ID: <20101111233956.B89912A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 17:39:56 2010 New Revision: 118858 URL: http://llvm.org/viewvc/llvm-project?rev=118858&view=rev Log: unbreak the web page. Modified: www-pubs/trunk/pubs.js Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=118858&r1=118857&r2=118858&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Thu Nov 11 17:39:56 2010 @@ -10,7 +10,7 @@ year: 2010 }, - [{ url: "2010-10-OSDI-DeterministicMT.html", + { url: "2010-10-OSDI-DeterministicMT.html", title: "Stable Deterministic Multithreading through Schedule Memoization", published: "Proc. of the Ninth Symposium on Operating Systems Design and Implementation (OSDI '10)", location: "Vancouver, BC, Canada", @@ -19,7 +19,7 @@ year: 2010 }, - [{ url: "2010-10-OSDI-BypassingRaces.html", + { url: "2010-10-OSDI-BypassingRaces.html", title: "Bypassing Races in Live Applications with Execution Filters", published: "Proc. of the Ninth Symposium on Operating Systems Design and Implementation (OSDI '10)", location: "Vancouver, BC, Canada", From grosbach at apple.com Thu Nov 11 17:41:09 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 11 Nov 2010 23:41:09 -0000 Subject: [llvm-commits] [llvm] r118859 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMMCCodeEmitter.cpp Message-ID: <20101111234109.5622E2A6C12C@llvm.org> Author: grosbach Date: Thu Nov 11 17:41:09 2010 New Revision: 118859 URL: http://llvm.org/viewvc/llvm-project?rev=118859&view=rev Log: Start of support for binary emit of 16-it Thumb instructions. Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118859&r1=118858&r2=118859&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Nov 11 17:41:09 2010 @@ -56,10 +56,14 @@ } bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { - if ((Count % 4) != 0) { - // Fixme: % 2 for Thumb? - return false; - } +// if ((Count % 4) != 0) { +// // Fixme: % 2 for Thumb? +// return false; +// } + // FIXME: Zero fill for now. That's not right, but at least will get the + // section size right. + for (uint64_t i = 0; i != Count; ++i) + OW->Write8(0); return true; } } // end anonymous namespace Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118859&r1=118858&r2=118859&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 11 17:41:09 2010 @@ -608,10 +608,17 @@ SmallVectorImpl &Fixups) const { // Pseudo instructions don't get encoded. const TargetInstrDesc &Desc = TII.get(MI.getOpcode()); - if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo) + uint64_t TSFlags = Desc.TSFlags; + if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) return; - - EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS); + int Size; + // Basic size info comes from the TSFlags field. + switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { + default: llvm_unreachable("Unexpected instruction size!"); + case ARMII::Size2Bytes: Size = 2; break; + case ARMII::Size4Bytes: Size = 4; break; + } + EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS); ++MCNumEmitted; // Keep track of the # of mi's emitted. } From clattner at apple.com Thu Nov 11 18:00:24 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 16:00:24 -0800 Subject: [llvm-commits] [PATCH] FileCheck.cpp: made match regex '$' for DOSish \r\n In-Reply-To: References: Message-ID: <3130D98D-B795-4261-9FAF-7BE5E6CBC218@apple.com> Patch looks good to me, please commit, thanks! -Chris On Nov 8, 2010, at 8:35 PM, NAKAMURA Takumi wrote: > Ping. It can pass two tests below on win32. > - Clang :: CodeGenCXX/dyncast.cpp > - LLVM :: CodeGen/ARM/globals.ll > > ...Takumi > > 2010/10/4 NAKAMURA Takumi : >> Some tests have CHECK: {{foobar$}} to cause mismatch failure on mingw. >> >> I took the way to eliminate \r on MemoryBuffer. >> Is there any better way? >> >> ...Takumi >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Thu Nov 11 18:00:21 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 12 Nov 2010 00:00:21 -0000 Subject: [llvm-commits] [llvm] r118862 - /llvm/trunk/include/llvm/CodeGen/MachineInstr.h Message-ID: <20101112000021.402DA2A6C12D@llvm.org> Author: lattner Date: Thu Nov 11 18:00:21 2010 New Revision: 118862 URL: http://llvm.org/viewvc/llvm-project?rev=118862&view=rev Log: add operand iterator apis to MachineInstr, patch by ether zhhb. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=118862&r1=118861&r2=118862&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Nov 11 18:00:21 2010 @@ -167,7 +167,17 @@ /// getNumExplicitOperands - Returns the number of non-implicit operands. /// unsigned getNumExplicitOperands() const; - + + /// iterator/begin/end - Iterate over all operands of a machine instruction. + typedef std::vector::iterator mop_iterator; + typedef std::vector::const_iterator const_mop_iterator; + + mop_iterator operands_begin() { return Operands.begin(); } + mop_iterator operands_end() { return Operands.end(); } + + const_mop_iterator operands_begin() const { return Operands.begin(); } + const_mop_iterator operands_end() const { return Operands.end(); } + /// Access to memory operands of the instruction mmo_iterator memoperands_begin() const { return MemRefs; } mmo_iterator memoperands_end() const { return MemRefsEnd; } From clattner at apple.com Thu Nov 11 18:02:38 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 16:02:38 -0800 Subject: [llvm-commits] Add operand iterator for machine instruction. In-Reply-To: References: <4B360CA0-C20B-4DC5-9D82-9BDE953F19FB@apple.com> Message-ID: On Oct 30, 2010, at 7:54 PM, ether zhhb wrote: > From 2b00490b46f8ba46fafffa327f7998e83f180f55 Mon Sep 17 00:00:00 2001 > From: ether > Date: Sun, 31 Oct 2010 10:42:10 +0800 > Subject: [PATCH] Add operand iterator to machine instruction. > hi > > sorry for the trivial mistake, this is the correct patch: Applied in r118862, thanks. -Chris > > --- > include/llvm/CodeGen/MachineInstr.h | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/include/llvm/CodeGen/MachineInstr.h > b/include/llvm/CodeGen/MachineInstr.h > index fc84f8c..d1f17d3 100644 > --- a/include/llvm/CodeGen/MachineInstr.h > +++ b/include/llvm/CodeGen/MachineInstr.h > @@ -167,7 +167,17 @@ public: > /// getNumExplicitOperands - Returns the number of non-implicit operands. > /// > unsigned getNumExplicitOperands() const; > - > + > + /// iterator/begin/end - Iterate over all operands of a machine instruction. > + typedef std::vector::iterator mop_iterator; > + typedef std::vector::const_iterator const_mop_iterator; > + > + mop_iterator operands_begin() { return Operands.begin(); } > + mop_iterator operands_end() { return Operands.end(); } > + > + const_mop_iterator operands_begin() const { return Operands.begin(); } > + const_mop_iterator operands_end() const { return Operands.end(); } > + > /// Access to memory operands of the instruction > mmo_iterator memoperands_begin() const { return MemRefs; } > mmo_iterator memoperands_end() const { return MemRefsEnd; } > -- > 1.7.1 > <0001-Add-operand-iterator-to-machine-instruction.patch> From clattner at apple.com Thu Nov 11 18:07:11 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 16:07:11 -0800 Subject: [llvm-commits] [llvm] r117420 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ In-Reply-To: <20101027002302.2AE5F2A6C12C@llvm.org> References: <20101027002302.2AE5F2A6C12C@llvm.org> Message-ID: <152DDF75-3BA5-49AA-BC28-95A4A2B8FC28@apple.com> On Oct 26, 2010, at 5:23 PM, Wesley Peck wrote: > Author: peckw > Date: Tue Oct 26 19:23:01 2010 > New Revision: 117420 > > URL: http://llvm.org/viewvc/llvm-project?rev=117420&view=rev > Log: > Adding disassembler to the MicroBlaze backend. Ok, cool. Please add some simple testcases for these as well. Our ultimate goal is to have the disassembler be autogenerated from the encoding info in the .td files (for targets with 16 or 32-bit encodings) so that you don't have to write so much rote code, but in the meantime this is the right way to go. -Chris From clattner at apple.com Thu Nov 11 18:12:35 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 16:12:35 -0800 Subject: [llvm-commits] [llvm] r117322 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/stdcall-notailcall.ll In-Reply-To: <4CC68CC2.5030402@free.fr> References: <20101025221705.C4B602A6C12C@llvm.org> <4CC68CC2.5030402@free.fr> Message-ID: On Oct 26, 2010, at 1:09 AM, Duncan Sands wrote: > Hi Dale, > >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 25 17:17:05 2010 >> @@ -2532,6 +2532,11 @@ >> } >> } >> >> + // An stdcall caller is expected to clean up its arguments; the callee >> + // isn't going to do that. PR 8461. > > I think there's some rule saying that PR numbers should not be mentioned in > code comments (not sure why, but I recall Chris saying this once). PR #'s should not be used as a substitute for good comments, please make the code be self contained. Thanks Dale, -Chris From dalej at apple.com Thu Nov 11 18:20:46 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 11 Nov 2010 16:20:46 -0800 Subject: [llvm-commits] [llvm] r117322 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/stdcall-notailcall.ll In-Reply-To: References: <20101025221705.C4B602A6C12C@llvm.org> <4CC68CC2.5030402@free.fr> Message-ID: On Nov 11, 2010, at 4:12 PMPST, Chris Lattner wrote: > > On Oct 26, 2010, at 1:09 AM, Duncan Sands wrote: > >> Hi Dale, >> >>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 25 17:17:05 2010 >>> @@ -2532,6 +2532,11 @@ >>> } >>> } >>> >>> + // An stdcall caller is expected to clean up its arguments; the callee >>> + // isn't going to do that. PR 8461. >> >> I think there's some rule saying that PR numbers should not be mentioned in >> code comments (not sure why, but I recall Chris saying this once). > > PR #'s should not be used as a substitute for good comments, please make the code be self contained. Thanks Dale, This is not a substitute for comments, as you can see; it is a reference to an example, which I think is useful. However I'll remove it if you prefer. From sabre at nondot.org Thu Nov 11 18:19:41 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 12 Nov 2010 00:19:41 -0000 Subject: [llvm-commits] [llvm] r118863 - /llvm/trunk/docs/CodingStandards.html Message-ID: <20101112001941.7D5B42A6C12C@llvm.org> Author: lattner Date: Thu Nov 11 18:19:41 2010 New Revision: 118863 URL: http://llvm.org/viewvc/llvm-project?rev=118863&view=rev Log: describe the preferred approach to silencing 'unused variable warnings' due to asserts. Modified: llvm/trunk/docs/CodingStandards.html Modified: llvm/trunk/docs/CodingStandards.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodingStandards.html?rev=118863&r1=118862&r2=118863&view=diff ============================================================================== --- llvm/trunk/docs/CodingStandards.html (original) +++ llvm/trunk/docs/CodingStandards.html Thu Nov 11 18:19:41 2010 @@ -851,6 +851,38 @@ +

    Another issue is that values used only by assertions will produce an "unused + value" warning when assertions are disabled. For example, this code will warn: +

    + +
    +
    +  unsigned Size = V.size(); 
+  assert(Size > 42 && "Vector smaller than it should be");
+
+  bool NewToSet = Myset.insert(Value);
+  assert(NewToSet && "The value shouldn't be in the set yet");  
+
    +
    + +

    These are two interesting different cases: in the first case, the call to +V.size() is only useful for the assert, and we don't want it executed when +assertions are disabled. Code like this should move the call into the assert +itself. In the second case, the side effects of the call must happen whether +the assert is enabled or not. In this case, the value should be cast to void +to disable the warning. To be specific, it is preferred to write the code +like this:

    + +
    +
    +  assert(V.size() > 42 && "Vector smaller than it should be");
+
+  bool NewToSet = Myset.insert(Value); (void)NewToSet;
+  assert(NewToSet && "The value shouldn't be in the set yet");  
+
    +
    + + From clattner at apple.com Thu Nov 11 18:22:18 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 16:22:18 -0800 Subject: [llvm-commits] [llvm] r116920 - /llvm/trunk/include/llvm/Support/Compiler.h In-Reply-To: References: <20101020084427.BD15C2A6C12C@llvm.org> Message-ID: On Oct 23, 2010, at 2:20 AM, Chandler Carruth wrote: > On Wed, Oct 20, 2010 at 5:38 PM, Bill Wendling wrote: > On Oct 20, 2010, at 1:44 AM, Chandler Carruth wrote: > >> Author: chandlerc >> Date: Wed Oct 20 03:44:27 2010 >> New Revision: 116920 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=116920&view=rev >> Log: >> Add a comment about ATTRIBUTE_UNUSED to avoid further confusion over when to >> use it. >> > > There's no reason not to use this for variables. And it avoids the void-casting hack. > > Chris expressly asked for the void-cast for variables: http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20100705/032066.html > > The comment I added was intended to help document this preference. I'll happily change it if you change Chris's mind. ;] Yep, Chandler is right. I documented this in the CodingStandards.html file in r118863. Thanks! -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/0a7fdbba/attachment.html From clattner at apple.com Thu Nov 11 18:24:30 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 11 Nov 2010 16:24:30 -0800 Subject: [llvm-commits] [llvm] r117322 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/stdcall-notailcall.ll In-Reply-To: References: <20101025221705.C4B602A6C12C@llvm.org> <4CC68CC2.5030402@free.fr> Message-ID: On Nov 11, 2010, at 4:20 PM, Dale Johannesen wrote: > > On Nov 11, 2010, at 4:12 PMPST, Chris Lattner wrote: > >> >> On Oct 26, 2010, at 1:09 AM, Duncan Sands wrote: >> >>> Hi Dale, >>> >>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) >>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Oct 25 17:17:05 2010 >>>> @@ -2532,6 +2532,11 @@ >>>> } >>>> } >>>> >>>> + // An stdcall caller is expected to clean up its arguments; the callee >>>> + // isn't going to do that. PR 8461. >>> >>> I think there's some rule saying that PR numbers should not be mentioned in >>> code comments (not sure why, but I recall Chris saying this once). >> >> PR #'s should not be used as a substitute for good comments, please make the code be self contained. Thanks Dale, > > This is not a substitute for comments, as you can see; it is a reference to an example, which I think is useful. However I'll remove it if you prefer. Yes please do, so long as there is a testcase in llvm/test that covers this, we should be good. Thanks! -Chris From Renato.Golin at arm.com Thu Nov 11 18:35:14 2010 From: Renato.Golin at arm.com (Renato Golin) Date: Fri, 12 Nov 2010 00:35:14 +0000 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: References: <20101108164727.39B812A6C12C@llvm.org> , Message-ID: > Renato, do you know where do they come from? Are they just aliases? Good question. Never seen them, but surely looks that way. Will check some internal sources (people that know binutils better) and will come back to you tomorrow. > Hopefully we can just use the "official" ones . If you use CodeSourcery's GCC you should be perfectly fine. As far as I know they offer full compatibility with the ARM toolkit, so even though it might not use it internally all the time, it sure understands ARM ABI. If it doesn't, it's a bug. ;) cheers, --renato -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From bruno.cardoso at gmail.com Thu Nov 11 18:38:32 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 12 Nov 2010 00:38:32 -0000 Subject: [llvm-commits] [llvm] r118864 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.h test/CodeGen/Mips/2010-11-09-Mul.ll Message-ID: <20101112003832.5E6722A6C12C@llvm.org> Author: bruno Date: Thu Nov 11 18:38:32 2010 New Revision: 118864 URL: http://llvm.org/viewvc/llvm-project?rev=118864&view=rev Log: Enable mips32 mul instruction. Patch by Akira Hatanaka Added: llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsSubtarget.h Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=118864&r1=118863&r2=118864&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Nov 11 18:38:32 2010 @@ -386,6 +386,8 @@ /// Special Muls case ISD::MUL: + if (Subtarget.isMips32()) + break; case ISD::MULHS: case ISD::MULHU: { SDValue MulOp1 = Node->getOperand(0); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=118864&r1=118863&r2=118864&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Nov 11 18:38:32 2010 @@ -62,6 +62,7 @@ def HasBitCount : Predicate<"Subtarget.hasBitCount()">; def HasSwap : Predicate<"Subtarget.hasSwap()">; def HasCondMov : Predicate<"Subtarget.hasCondMov()">; +def IsMips32 : Predicate<"Subtarget.isMips32()">; //===----------------------------------------------------------------------===// // Mips Operand, Complex Patterns and Transformations Definitions. @@ -487,7 +488,7 @@ // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. -//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; +def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=118864&r1=118863&r2=118864&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Thu Nov 11 18:38:32 2010 @@ -31,7 +31,7 @@ protected: enum MipsArchEnum { - Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2 + Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2 }; // Mips architecture version @@ -100,7 +100,7 @@ const std::string &CPU); bool isMips1() const { return MipsArchVersion == Mips1; } - bool isMips32() const { return MipsArchVersion == Mips32; } + bool isMips32() const { return MipsArchVersion >= Mips32; } bool isMips32r2() const { return MipsArchVersion == Mips32r2; } bool isLittle() const { return IsLittle; } Added: llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll?rev=118864&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll (added) +++ llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll Thu Nov 11 18:38:32 2010 @@ -0,0 +1,15 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: mul $2, $5, $4 +define i32 @mul1(i32 %a, i32 %b) nounwind readnone { +entry: + %mul = mul i32 %b, %a + ret i32 %mul +} + +; CHECK: mul $2, $5, $4 +define i32 @mul2(i32 %a, i32 %b) nounwind readnone { +entry: + %mul = mul nsw i32 %b, %a + ret i32 %mul +} From echristo at apple.com Thu Nov 11 18:44:14 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 16:44:14 -0800 Subject: [llvm-commits] [llvm] r118864 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.h test/CodeGen/Mips/2010-11-09-Mul.ll In-Reply-To: <20101112003832.5E6722A6C12C@llvm.org> References: <20101112003832.5E6722A6C12C@llvm.org> Message-ID: <7259CCEE-B56C-41A3-B237-77A1CD3218EE@apple.com> On Nov 11, 2010, at 4:38 PM, Bruno Cardoso Lopes wrote: > enum MipsArchEnum { > - Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2 > + Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2 > }; Abandoning mips64 support? -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/43d9df59/attachment.html From dalej at apple.com Thu Nov 11 18:43:18 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 12 Nov 2010 00:43:18 -0000 Subject: [llvm-commits] [llvm] r118865 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20101112004318.40A6D2A6C12C@llvm.org> Author: johannes Date: Thu Nov 11 18:43:18 2010 New Revision: 118865 URL: http://llvm.org/viewvc/llvm-project?rev=118865&view=rev Log: Remove possibly useful info from comment, per Chris. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=118865&r1=118864&r2=118865&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Nov 11 18:43:18 2010 @@ -2509,7 +2509,7 @@ } // An stdcall caller is expected to clean up its arguments; the callee - // isn't going to do that. PR 8461. + // isn't going to do that. if (!CCMatch && CallerCC==CallingConv::X86_StdCall) return false; From bruno.cardoso at gmail.com Thu Nov 11 18:48:59 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 11 Nov 2010 22:48:59 -0200 Subject: [llvm-commits] [llvm] r118864 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.h test/CodeGen/Mips/2010-11-09-Mul.ll In-Reply-To: <7259CCEE-B56C-41A3-B237-77A1CD3218EE@apple.com> References: <20101112003832.5E6722A6C12C@llvm.org> <7259CCEE-B56C-41A3-B237-77A1CD3218EE@apple.com> Message-ID: Hi Eric, On Thu, Nov 11, 2010 at 10:44 PM, Eric Christopher wrote: > > On Nov 11, 2010, at 4:38 PM, Bruno Cardoso Lopes wrote: > > ??enum MipsArchEnum { > - ???Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2 > + ???Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2 > ??}; > > Abandoning mips64 support? > -eric Forgot to mention. Since we have not support for this anyway, remove it until someone cares enough to put it there again! -- Bruno Cardoso Lopes http://www.brunocardoso.cc From echristo at apple.com Thu Nov 11 18:49:38 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 16:49:38 -0800 Subject: [llvm-commits] [llvm] r118864 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.h test/CodeGen/Mips/2010-11-09-Mul.ll In-Reply-To: References: <20101112003832.5E6722A6C12C@llvm.org> <7259CCEE-B56C-41A3-B237-77A1CD3218EE@apple.com> Message-ID: On Nov 11, 2010, at 4:48 PM, Bruno Cardoso Lopes wrote: > Hi Eric, > > On Thu, Nov 11, 2010 at 10:44 PM, Eric Christopher wrote: >> >> On Nov 11, 2010, at 4:38 PM, Bruno Cardoso Lopes wrote: >> >> enum MipsArchEnum { >> - Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2 >> + Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2 >> }; >> >> Abandoning mips64 support? >> -eric > > Forgot to mention. Since we have not support for this anyway, remove > it until someone > cares enough to put it there again! Cool deal. :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/23b9eeca/attachment.html From peckw at wesleypeck.com Thu Nov 11 18:50:26 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Thu, 11 Nov 2010 18:50:26 -0600 Subject: [llvm-commits] [llvm] r117420 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ In-Reply-To: <152DDF75-3BA5-49AA-BC28-95A4A2B8FC28@apple.com> References: <20101027002302.2AE5F2A6C12C@llvm.org> <152DDF75-3BA5-49AA-BC28-95A4A2B8FC28@apple.com> Message-ID: <6B65D64D-12B0-40BF-B585-C770EDCACF66@wesleypeck.com> Yeah, from what I saw the ARM and x86 backends had some custom tblgen stuff to do a lot of this. I'm unfamiliar with adding stuff to tblgen so I decided to just hand code some of the tables for now. When the auto-generation from .td files is working then I'll convert the MBlaze backend over to that. I'll add some test cases in the next few days. Again, thanks for taking a look at the code. -- Wesley Peck On Nov 11, 2010, at 6:07 PM, Chris Lattner wrote: > > On Oct 26, 2010, at 5:23 PM, Wesley Peck wrote: > >> Author: peckw >> Date: Tue Oct 26 19:23:01 2010 >> New Revision: 117420 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=117420&view=rev >> Log: >> Adding disassembler to the MicroBlaze backend. > > Ok, cool. Please add some simple testcases for these as well. Our ultimate goal is to have the disassembler be autogenerated from the encoding info in the .td files (for targets with 16 or 32-bit encodings) so that you don't have to write so much rote code, but in the meantime this is the right way to go. > > -Chris From jasonwkim at google.com Thu Nov 11 19:09:29 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 17:09:29 -0800 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: References: <20101108164727.39B812A6C12C@llvm.org> Message-ID: On Thu, Nov 11, 2010 at 4:35 PM, Renato Golin wrote: >> Renato, do you know where do they come from? Are they just aliases? > > Good question. Never seen them, but surely looks that way. > > Will check some internal sources (people that know binutils better) and will come back to you tomorrow. > > >> Hopefully we can just use the "official" ones . > > If you use CodeSourcery's GCC you should be perfectly fine. > > As far as I know they offer full compatibility with the ARM toolkit, so even though it might not use it internally all the time, it sure understands ARM ABI. > > If it doesn't, it's a bug. ;) > The names for the enums are internal to LLVM anyways, only the values matter to the outside world. If some other toolchain uses their own flavor for the value names, no harm done - right? -jason > cheers, > --renato > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. ?Thank you. > From aggarwa4 at illinois.edu Thu Nov 11 19:08:09 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 12 Nov 2010 01:08:09 -0000 Subject: [llvm-commits] [poolalloc] r118870 - /poolalloc/trunk/lib/DSA/DataStructureStats.cpp Message-ID: <20101112010809.E7F7F2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Nov 11 19:08:09 2010 New Revision: 118870 URL: http://llvm.org/viewvc/llvm-project?rev=118870&view=rev Log: Fixes some failures while running DSA tests. Modified: poolalloc/trunk/lib/DSA/DataStructureStats.cpp Modified: poolalloc/trunk/lib/DSA/DataStructureStats.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureStats.cpp?rev=118870&r1=118869&r2=118870&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructureStats.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructureStats.cpp Thu Nov 11 19:08:09 2010 @@ -78,6 +78,11 @@ if (CastInst *CI = dyn_cast(V)) return isIndirectCallee(CI->getOperand(0)); + + if (ConstantExpr *CE = dyn_cast(V)) + if (CE->isCast()) + return isIndirectCallee(CE->getOperand(0)); + return true; } From echristo at apple.com Thu Nov 11 19:12:46 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 11 Nov 2010 17:12:46 -0800 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: References: <20101108164727.39B812A6C12C@llvm.org> Message-ID: <3F99DCBF-087A-49D1-8E7E-A9E4DC6B093B@apple.com> On Nov 11, 2010, at 5:09 PM, Jason Kim wrote: > On Thu, Nov 11, 2010 at 4:35 PM, Renato Golin wrote: >>> Renato, do you know where do they come from? Are they just aliases? >> >> Good question. Never seen them, but surely looks that way. >> >> Will check some internal sources (people that know binutils better) and will come back to you tomorrow. >> >> >>> Hopefully we can just use the "official" ones . >> >> If you use CodeSourcery's GCC you should be perfectly fine. >> >> As far as I know they offer full compatibility with the ARM toolkit, so even though it might not use it internally all the time, it sure understands ARM ABI. >> >> If it doesn't, it's a bug. ;) >> > > The names for the enums are internal to LLVM anyways, only the values > matter to the outside world. If some other toolchain uses their own > flavor for the value names, no harm done - right? It's definitely easiest to go ahead and use the same names if you know what they are :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/361c50ba/attachment-0001.html From gohman at apple.com Thu Nov 11 20:02:39 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 12 Nov 2010 02:02:39 -0000 Subject: [llvm-commits] [llvm] r118874 - /llvm/trunk/test/Transforms/DeadStoreElimination/free.ll Message-ID: <20101112020239.32CCB2A6C12C@llvm.org> Author: djg Date: Thu Nov 11 20:02:39 2010 New Revision: 118874 URL: http://llvm.org/viewvc/llvm-project?rev=118874&view=rev Log: Filecheckize. Modified: llvm/trunk/test/Transforms/DeadStoreElimination/free.ll Modified: llvm/trunk/test/Transforms/DeadStoreElimination/free.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/free.ll?rev=118874&r1=118873&r2=118874&view=diff ============================================================================== --- llvm/trunk/test/Transforms/DeadStoreElimination/free.ll (original) +++ llvm/trunk/test/Transforms/DeadStoreElimination/free.ll Thu Nov 11 20:02:39 2010 @@ -1,5 +1,11 @@ -; RUN: opt < %s -basicaa -dse -S | not grep DEAD +; RUN: opt < %s -basicaa -dse -S | FileCheck %s +target datalayout = "e-p:64:64:64" + +; CHECK: @test +; CHECK-NEXT: bitcast +; CHECK-NEXT: @free +; CHECK-NEXT: ret void define void @test(i32* %Q, i32* %P) { %DEAD = load i32* %Q ; [#uses=1] store i32 %DEAD, i32* %P @@ -7,9 +13,14 @@ ret void } +; CHECK: @test2 +; CHECK-NEXT: bitcast +; CHECK-NEXT: @free +; CHECK-NEXT: ret void define void @test2({i32, i32}* %P) { %Q = getelementptr {i32, i32} *%P, i32 0, i32 1 store i32 4, i32* %Q free {i32,i32}* %P ret void } + From gohman at apple.com Thu Nov 11 20:19:17 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 12 Nov 2010 02:19:17 -0000 Subject: [llvm-commits] [llvm] r118875 - in /llvm/trunk: lib/Transforms/Scalar/DeadStoreElimination.cpp test/Transforms/DeadStoreElimination/free.ll Message-ID: <20101112021917.963612A6C12C@llvm.org> Author: djg Date: Thu Nov 11 20:19:17 2010 New Revision: 118875 URL: http://llvm.org/viewvc/llvm-project?rev=118875&view=rev Log: Enhance DSE to handle the case where a free call makes more than one store dead. This is especially noticeable in SingleSource/Benchmarks/Shootout/objinst. Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp llvm/trunk/test/Transforms/DeadStoreElimination/free.ll Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=118875&r1=118874&r2=118875&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Thu Nov 11 20:19:17 2010 @@ -59,6 +59,7 @@ bool runOnBasicBlock(BasicBlock &BB); bool handleFreeWithNonTrivialDependency(const CallInst *F, + Instruction *Inst, MemDepResult Dep); bool handleEndBlock(BasicBlock &BB); bool RemoveUndeadPointers(Value *Ptr, uint64_t killPointerSize, @@ -212,7 +213,7 @@ // Handle frees whose dependencies are non-trivial. if (const CallInst *F = isFreeCall(Inst)) { - MadeChange |= handleFreeWithNonTrivialDependency(F, InstDep); + MadeChange |= handleFreeWithNonTrivialDependency(F, Inst, InstDep); continue; } @@ -298,23 +299,34 @@ /// handleFreeWithNonTrivialDependency - Handle frees of entire structures whose /// dependency is a store to a field of that structure. bool DSE::handleFreeWithNonTrivialDependency(const CallInst *F, + Instruction *Inst, MemDepResult Dep) { AliasAnalysis &AA = getAnalysis(); + MemoryDependenceAnalysis &MD = getAnalysis(); - Instruction *Dependency = Dep.getInst(); - if (!Dependency || !doesClobberMemory(Dependency) || !isElidable(Dependency)) - return false; + do { + Instruction *Dependency = Dep.getInst(); + if (!Dependency || !doesClobberMemory(Dependency) || !isElidable(Dependency)) + return false; - Value *DepPointer = getPointerOperand(Dependency)->getUnderlyingObject(); + Value *DepPointer = getPointerOperand(Dependency)->getUnderlyingObject(); - // Check for aliasing. - if (AA.alias(F->getArgOperand(0), 1, DepPointer, 1) != - AliasAnalysis::MustAlias) - return false; + // Check for aliasing. + if (AA.alias(F->getArgOperand(0), 1, DepPointer, 1) != + AliasAnalysis::MustAlias) + return false; - // DCE instructions only used to calculate that store - DeleteDeadInstruction(Dependency); - ++NumFastStores; + // DCE instructions only used to calculate that store + DeleteDeadInstruction(Dependency); + ++NumFastStores; + + // Inst's old Dependency is now deleted. Compute the next dependency, + // which may also be dead, as in + // s[0] = 0; + // s[1] = 0; // This has just been deleted. + // free(s); + Dep = MD.getDependency(Inst); + } while (!Dep.isNonLocal()); return true; } Modified: llvm/trunk/test/Transforms/DeadStoreElimination/free.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/free.ll?rev=118875&r1=118874&r2=118875&view=diff ============================================================================== --- llvm/trunk/test/Transforms/DeadStoreElimination/free.ll (original) +++ llvm/trunk/test/Transforms/DeadStoreElimination/free.ll Thu Nov 11 20:19:17 2010 @@ -24,3 +24,17 @@ ret void } +; CHECK: @test4 +; CHECK-NOT: store +; CHECK: ret void +define void @test4() { + %m = call i8* @malloc(i64 24) + store i8 0, i8* %m + %m1 = getelementptr i8* %m, i64 1 + store i8 1, i8* %m1 + call void @free(i8* %m) + ret void +} + +declare void @free(i8*) +declare i8* @malloc(i64) From bigcheesegs at gmail.com Thu Nov 11 20:23:34 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Thu, 11 Nov 2010 21:23:34 -0500 Subject: [llvm-commits] [PATCH] Object File Library Message-ID: Attached are updated patches to be reviewed. I've split them up into the generic API, the COFF and ELF implementations, tool changes, and tests. This does not currently implement the Serialization/Normalization split that I reference in my talk. I'm going to wait to do that split until the line is firmly defined, as I still haven't figured out how exactly to represent relocation data. A current major blocker that you can see throughout the ELF implementation (and ignored in COFF (which I knew much better and didn't need debugging help)) is how invalid object file errors are handled. I currently just call report_fatal_error, which is really not how they should be handled. I've been complaining about the same problem in the System library on IRC recently too while trying to clean up the Windows impl. What I would like to do is use an error object based on the concept of std::error_code to report both system (IO, memory, syscall), and "parsing" errors from invalid object files. This should also include at least the address in the file at which the error occurred. I don't feel that we need detailed (clang style :P) diagnostics because tools generate object files, not people. At the same time I don't want to just dump "object file invalid at 0xdeadbeef" to the user. Using 'std::error_category' would allow mixing the two while proving more detailed info such as "invalid symbol name string index at 0xblahblah". Also, each object file could use a custom error_category for special errors. It also allows clients that simply don't care to just check for success and not pay for message formatting. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... 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Name: object-S0P3-llvm-nm.patch Type: application/octet-stream Size: 10871 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/b0d528a8/attachment-0009.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: object-S0P4-llvm-objdump.patch Type: application/octet-stream Size: 10547 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/b0d528a8/attachment-0010.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: object-S0P5-add-tests.patch Type: application/octet-stream Size: 10846 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/b0d528a8/attachment-0011.obj From jasonwkim at google.com Thu Nov 11 21:06:30 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 19:06:30 -0800 Subject: [llvm-commits] [patch] ARM/MC/ELF add new stub for movt/movw in ARMFixupKinds Message-ID: Is getBinaryCodeForInst the best place to place the case for supporting movt/movw fixup emission? The call stack seems to be: #0 ARMMCCodeEmitter::getBinaryCodeForInstr #1 ARMMCCodeEmitter::EncodeInstruction #2 MCELFStreamer::EmitInstToData #3 MCObjectStreamer::EmitInstruction #4 ARMAsmPrinter::EmitInstruction -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-mc-elf-s08.patch Type: text/x-patch Size: 2211 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/0000ba53/attachment.bin From jasonwkim at google.com Thu Nov 11 21:29:56 2010 From: jasonwkim at google.com (Jason Kim) Date: Thu, 11 Nov 2010 19:29:56 -0800 Subject: [llvm-commits] [patch] ARM/MC/ELF add new stub for movt/movw in ARMFixupKinds In-Reply-To: References: Message-ID: On Thu, Nov 11, 2010 at 7:06 PM, Jason Kim wrote: > Is getBinaryCodeForInst the best place to place the case for > supporting movt/movw fixup emission? > The call stack seems to be: > > #0 ARMMCCodeEmitter::getBinaryCodeForInstr > #1 ARMMCCodeEmitter::EncodeInstruction > #2 MCELFStreamer::EmitInstToData > #3 MCObjectStreamer::EmitInstruction > #4 ARMAsmPrinter::EmitInstruction > Please note that without new code (not yet committed) in RecordRelocation(), these fixups remain inactive stubs. From peter at pcc.me.uk Thu Nov 11 21:40:53 2010 From: peter at pcc.me.uk (Peter Collingbourne) Date: Fri, 12 Nov 2010 03:40:53 +0000 Subject: [llvm-commits] [PATCH] Object File Library In-Reply-To: References: Message-ID: <20101112034053.GA21724@pcc.me.uk> On Thu, Nov 11, 2010 at 09:23:34PM -0500, Michael Spencer wrote: > Attached are updated patches to be reviewed. I've split them up into > the generic API, the COFF and ELF implementations, tool changes, and > tests. A couple of fixups: 1) Fix Makefiles 2) Fix header path Thanks, -- Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Fix-Makefiles.patch Type: text/x-diff Size: 1800 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101112/4270edb7/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Fix-header-path.patch Type: text/x-diff Size: 753 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101112/4270edb7/attachment-0001.bin From peter at pcc.me.uk Thu Nov 11 22:14:48 2010 From: peter at pcc.me.uk (Peter Collingbourne) Date: Fri, 12 Nov 2010 04:14:48 +0000 Subject: [llvm-commits] [PATCH] Object File Library In-Reply-To: <20101112034053.GA21724@pcc.me.uk> References: <20101112034053.GA21724@pcc.me.uk> Message-ID: <20101112041448.GA411@pcc.me.uk> On Fri, Nov 12, 2010 at 03:40:53AM +0000, Peter Collingbourne wrote: > On Thu, Nov 11, 2010 at 09:23:34PM -0500, Michael Spencer wrote: > > Attached are updated patches to be reviewed. I've split them up into > > the generic API, the COFF and ELF implementations, tool changes, and > > tests. > > A couple of fixups: > > 1) Fix Makefiles > 2) Fix header path One more: 3) Fix Makefiles for llvm-objdump Thanks, -- Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-Fix-Makefiles-for-llvm-objdump.patch Type: text/x-diff Size: 1247 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101112/32678b58/attachment.bin From dblaikie at gmail.com Thu Nov 11 17:55:53 2010 From: dblaikie at gmail.com (David Blaikie) Date: Thu, 11 Nov 2010 15:55:53 -0800 Subject: [llvm-commits] Coding style fixups in PBQP register allocator In-Reply-To: References: Message-ID: This is just some simple coding convention/style fixups (curly braces (position & presence) and != rather than < for comparisons) in the BPQP register allocator. If someone would like to take a look, that'd be great. - David -------------- next part -------------- A non-text attachment was scrubbed... Name: pbqpstylefix.patch Type: application/octet-stream Size: 4665 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101111/d1cb3fe1/attachment.obj From lhames at gmail.com Thu Nov 11 23:47:21 2010 From: lhames at gmail.com (Lang Hames) Date: Fri, 12 Nov 2010 05:47:21 -0000 Subject: [llvm-commits] [llvm] r118883 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20101112054721.6A1ED2A6C12C@llvm.org> Author: lhames Date: Thu Nov 11 23:47:21 2010 New Revision: 118883 URL: http://llvm.org/viewvc/llvm-project?rev=118883&view=rev Log: Fix some style issues in PBQP. Patch by David Blaikie. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=118883&r1=118882&r2=118883&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Thu Nov 11 23:47:21 2010 @@ -238,11 +238,13 @@ unsigned preg = *pregItr; const LiveInterval *pregLI = &lis->getInterval(preg); - if (pregLI->empty()) + if (pregLI->empty()) { continue; + } - if (!vregLI->overlaps(*pregLI)) + if (!vregLI->overlaps(*pregLI)) { continue; + } // Remove the register from the allowed set. VRAllowed::iterator eraseItr = @@ -318,10 +320,10 @@ assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch."); assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch."); - for (unsigned i = 0; i < vr1Allowed.size(); ++i) { + for (unsigned i = 0; i != vr1Allowed.size(); ++i) { unsigned preg1 = vr1Allowed[i]; - for (unsigned j = 0; j < vr2Allowed.size(); ++j) { + for (unsigned j = 0; j != vr2Allowed.size(); ++j) { unsigned preg2 = vr2Allowed[j]; if (tri->regsOverlap(preg1, preg2)) { @@ -355,11 +357,13 @@ miItr != miEnd; ++miItr) { const MachineInstr *mi = &*miItr; - if (!cp.setRegisters(mi)) + if (!cp.setRegisters(mi)) { continue; // Not coalescable. + } - if (cp.getSrcReg() == cp.getDstReg()) + if (cp.getSrcReg() == cp.getDstReg()) { continue; // Already coalesced. + } unsigned dst = cp.getDstReg(), src = cp.getSrcReg(); @@ -372,13 +376,15 @@ loopInfo->getLoopDepth(mbb)); if (cp.isPhys()) { - if (!lis->isAllocatable(dst)) + if (!lis->isAllocatable(dst)) { continue; + } const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src); unsigned pregOpt = 0; - while (pregOpt < allowed.size() && allowed[pregOpt] != dst) + while (pregOpt < allowed.size() && allowed[pregOpt] != dst) { ++pregOpt; + } if (pregOpt < allowed.size()) { ++pregOpt; // +1 to account for spill option. PBQP::Graph::NodeItr node = p->getNodeForVReg(src); @@ -425,9 +431,9 @@ assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch."); assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch."); - for (unsigned i = 0; i < vr1Allowed.size(); ++i) { + for (unsigned i = 0; i != vr1Allowed.size(); ++i) { unsigned preg1 = vr1Allowed[i]; - for (unsigned j = 0; j < vr2Allowed.size(); ++j) { + for (unsigned j = 0; j != vr2Allowed.size(); ++j) { unsigned preg2 = vr2Allowed[j]; if (preg1 == preg2) { @@ -473,8 +479,7 @@ // finalizeAlloc. if (!li->empty()) { vregsToAlloc.insert(li->reg); - } - else { + } else { emptyIntervalVRegs.insert(li->reg); } } @@ -484,18 +489,20 @@ MachineRegisterInfo* mri) { int stackSlot = vrm->getStackSlot(spilled->reg); - if (stackSlot == VirtRegMap::NO_STACK_SLOT) + if (stackSlot == VirtRegMap::NO_STACK_SLOT) { return; + } const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC); VNInfo *vni; - if (stackInterval.getNumValNums() != 0) + if (stackInterval.getNumValNums() != 0) { vni = stackInterval.getValNumInfo(0); - else + } else { vni = stackInterval.getNextValue( SlotIndex(), 0, lss->getVNInfoAllocator()); + } LiveInterval &rhsInterval = lis->getInterval(spilled->reg); stackInterval.MergeRangesInAsValue(rhsInterval, vni); @@ -594,11 +601,9 @@ // Get the physical register for this interval if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { reg = li->reg; - } - else if (vrm->isAssignedReg(li->reg)) { + } else if (vrm->isAssignedReg(li->reg)) { reg = vrm->getPhys(li->reg); - } - else { + } else { // Ranges which are assigned a stack slot only are ignored. continue; } @@ -615,7 +620,7 @@ // Find the set of basic blocks which this range is live into... if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { // And add the physreg for this interval to their live-in sets. - for (unsigned i = 0; i < liveInMBBs.size(); ++i) { + for (unsigned i = 0; i != liveInMBBs.size(); ++i) { if (liveInMBBs[i] != entryMBB) { if (!liveInMBBs[i]->isLiveIn(reg)) { liveInMBBs[i]->addLiveIn(reg); From lhames at gmail.com Thu Nov 11 23:50:17 2010 From: lhames at gmail.com (Lang Hames) Date: Thu, 11 Nov 2010 21:50:17 -0800 Subject: [llvm-commits] Coding style fixups in PBQP register allocator In-Reply-To: References: Message-ID: Looks good. Patch applied in r118883. Thanks David! - Lang. On Thu, Nov 11, 2010 at 3:55 PM, David Blaikie wrote: > This is just some simple coding convention/style fixups (curly braces > (position & presence) and != rather than < for comparisons) in the > BPQP register allocator. If someone would like to take a look, that'd > be great. > > - David > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From gohman at apple.com Fri Nov 12 00:20:01 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 12 Nov 2010 06:20:01 -0000 Subject: [llvm-commits] [llvm] r118884 - /llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Message-ID: <20101112062001.37BAC2A6C12C@llvm.org> Author: djg Date: Fri Nov 12 00:20:01 2010 New Revision: 118884 URL: http://llvm.org/viewvc/llvm-project?rev=118884&view=rev Log: Enable TBAA. Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=118884&r1=118883&r2=118884&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Fri Nov 12 00:20:01 2010 @@ -67,7 +67,7 @@ using namespace llvm; // For testing purposes, enable TBAA only via a special option. -static cl::opt EnableTBAA("enable-tbaa"); +static cl::opt EnableTBAA("enable-tbaa", cl::init(true)); namespace { /// TBAANode - This is a simple wrapper around an MDNode which provides a From baldrick at free.fr Fri Nov 12 02:30:15 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 12 Nov 2010 09:30:15 +0100 Subject: [llvm-commits] [llvm] r118840 - in /llvm/trunk: include/llvm/Value.h lib/Transforms/IPO/ArgumentPromotion.cpp lib/VMCore/Instruction.cpp lib/VMCore/Value.cpp test/Transforms/SimplifyCFG/speculate-with-offset.ll In-Reply-To: <20101111212325.ED0082A6C12C@llvm.org> References: <20101111212325.ED0082A6C12C@llvm.org> Message-ID: <4CDCFB17.9060508@free.fr> Hi Dan, > --- llvm/trunk/lib/VMCore/Value.cpp (original) > +++ llvm/trunk/lib/VMCore/Value.cpp Thu Nov 11 15:23:25 2010 > @@ -22,6 +22,7 @@ > #include "llvm/ValueSymbolTable.h" > #include "llvm/ADT/SmallString.h" > #include "llvm/Support/Debug.h" > +#include "llvm/Support/GetElementPtrTypeIterator.h" > #include "llvm/Support/ErrorHandling.h" this header was almost but not quite added in alphabetical order, which made me think that perhaps you wanted it in alphabetical order. Ciao, Duncan. From Renato.Golin at arm.com Fri Nov 12 03:28:26 2010 From: Renato.Golin at arm.com (Renato Golin) Date: Fri, 12 Nov 2010 09:28:26 +0000 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: <3F99DCBF-087A-49D1-8E7E-A9E4DC6B093B@apple.com> References: <20101108164727.39B812A6C12C@llvm.org> <3F99DCBF-087A-49D1-8E7E-A9E4DC6B093B@apple.com> Message-ID: <4CDD08BA.8060506@arm.com> On 12/11/10 01:12, Eric Christopher wrote: >> The names for the enums are internal to LLVM anyways, only the values >> matter to the outside world. If some other toolchain uses their own >> flavor for the value names, no harm done - right? > > It's definitely easiest to go ahead and use the same names if you know > what they are :) I agree. It's best to use the correct names, unless the re-factoring is too big to do in one go (or ever), as in many parts of GCC. cheers, --renato -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From echristo at apple.com Fri Nov 12 03:48:30 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 12 Nov 2010 09:48:30 -0000 Subject: [llvm-commits] [llvm] r118888 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101112094830.A98AA2A6C12C@llvm.org> Author: echristo Date: Fri Nov 12 03:48:30 2010 New Revision: 118888 URL: http://llvm.org/viewvc/llvm-project?rev=118888&view=rev Log: Fix up a few more spots of addrmode2 (or not) changes that were missed. Update some comments accordingly. Fixes rdar://8652289 Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118888&r1=118887&r2=118888&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Nov 12 03:48:30 2010 @@ -460,7 +460,7 @@ TII.get(ARM::t2LDRpci), DestReg) .addConstantPoolIndex(Idx)); else - // The extra reg and immediate are for addrmode2. + // The extra immediate is for addrmode2. AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), DestReg) .addConstantPoolIndex(Idx) @@ -505,11 +505,11 @@ if (RelocM == Reloc::PIC_) MIB.addImm(Id); } else { - // The extra reg and immediate are for addrmode2. + // The extra immediate is for addrmode2. MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), DestReg) .addConstantPoolIndex(Idx) - .addReg(0).addImm(0); + .addImm(0); } AddOptionalDefs(MIB); return DestReg; @@ -790,9 +790,15 @@ if (isFloat) Offset /= 4; - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg) - .addReg(Base).addImm(Offset)); + // LDRH needs an additional operand. + if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Base).addReg(0).addImm(Offset)); + else + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Base).addImm(Offset)); return true; } From kalle.raiskila at nokia.com Fri Nov 12 04:14:04 2010 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Fri, 12 Nov 2010 10:14:04 -0000 Subject: [llvm-commits] [llvm] r118889 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.h lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUNodes.td test/CodeGen/CellSPU/arg_ret.ll test/CodeGen/CellSPU/loads.ll test/CodeGen/CellSPU/stores.ll Message-ID: <20101112101404.36D9F2A6C12C@llvm.org> Author: kraiskil Date: Fri Nov 12 04:14:03 2010 New Revision: 118889 URL: http://llvm.org/viewvc/llvm-project?rev=118889&view=rev Log: Fix memory access lowering on SPU, adding support for the case where alignment node_names; - //! EVT mapping to useful data for Cell SPU - struct valtype_map_s { - EVT valtype; - int prefslot_byte; - }; - - const valtype_map_s valtype_map[] = { - { MVT::i1, 3 }, - { MVT::i8, 3 }, - { MVT::i16, 2 }, - { MVT::i32, 0 }, - { MVT::f32, 0 }, - { MVT::i64, 0 }, - { MVT::f64, 0 }, - { MVT::i128, 0 } - }; - - const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]); - - const valtype_map_s *getValueTypeMapEntry(EVT VT) { - const valtype_map_s *retval = 0; - - for (size_t i = 0; i < n_valtype_map; ++i) { - if (valtype_map[i].valtype == VT) { - retval = valtype_map + i; - break; - } - } - -#ifndef NDEBUG - if (retval == 0) { - report_fatal_error("getValueTypeMapEntry returns NULL for " + - Twine(VT.getEVTString())); - } -#endif + // Byte offset of the preferred slot (counted from the MSB) + int prefslotOffset(EVT VT) { + int retval=0; + if (VT==MVT::i1) retval=3; + if (VT==MVT::i8) retval=3; + if (VT==MVT::i16) retval=2; return retval; } @@ -440,9 +411,9 @@ setOperationAction(ISD::AND, VT, Legal); setOperationAction(ISD::OR, VT, Legal); setOperationAction(ISD::XOR, VT, Legal); - setOperationAction(ISD::LOAD, VT, Legal); + setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::SELECT, VT, Legal); - setOperationAction(ISD::STORE, VT, Legal); + setOperationAction(ISD::STORE, VT, Custom); // These operations need to be expanded: setOperationAction(ISD::SDIV, VT, Expand); @@ -503,8 +474,8 @@ node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB"; node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PREFSLOT2VEC"; node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT"; - node_names[(unsigned) SPUISD::SHLQUAD_L_BITS] = "SPUISD::SHLQUAD_L_BITS"; - node_names[(unsigned) SPUISD::SHLQUAD_L_BYTES] = "SPUISD::SHLQUAD_L_BYTES"; + node_names[(unsigned) SPUISD::SHL_BITS] = "SPUISD::SHL_BITS"; + node_names[(unsigned) SPUISD::SHL_BYTES] = "SPUISD::SHL_BYTES"; node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL"; node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR"; node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT"; @@ -573,11 +544,26 @@ EVT OutVT = Op.getValueType(); ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); - const valtype_map_s *vtm = getValueTypeMapEntry(InVT); + int pso = prefslotOffset(InVT); DebugLoc dl = Op.getDebugLoc(); + EVT vecVT = InVT.isVector()? InVT: EVT::getVectorVT(*DAG.getContext(), InVT, + (128 / InVT.getSizeInBits())); + + // two sanity checks + assert( LN->getAddressingMode() == ISD::UNINDEXED + && "we should get only UNINDEXED adresses"); + // clean aligned loads can be selected as-is + if (InVT.getSizeInBits() == 128 && alignment == 16) + return SDValue(); + + // Get pointerinfos to the memory chunk(s) that contain the data to load + uint64_t mpi_offset = LN->getPointerInfo().Offset; + mpi_offset -= mpi_offset%16; + MachinePointerInfo lowMemPtr( LN->getPointerInfo().V, mpi_offset); + MachinePointerInfo highMemPtr( LN->getPointerInfo().V, mpi_offset+16); + + - switch (LN->getAddressingMode()) { - case ISD::UNINDEXED: { SDValue result; SDValue basePtr = LN->getBasePtr(); SDValue rotate; @@ -591,7 +577,7 @@ && (CN = dyn_cast (basePtr.getOperand(1))) != 0) { // Known offset into basePtr int64_t offset = CN->getSExtValue(); - int64_t rotamt = int64_t((offset & 0xf) - vtm->prefslot_byte); + int64_t rotamt = int64_t((offset & 0xf) - pso); if (rotamt < 0) rotamt += 16; @@ -611,14 +597,14 @@ && basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) { // Plain aligned a-form address: rotate into preferred slot // Same for (SPUindirect (SPUhi ...), (SPUlo ...)) - int64_t rotamt = -vtm->prefslot_byte; + int64_t rotamt = -pso; if (rotamt < 0) rotamt += 16; rotate = DAG.getConstant(rotamt, MVT::i16); } else { // Offset the rotate amount by the basePtr and the preferred slot // byte offset - int64_t rotamt = -vtm->prefslot_byte; + int64_t rotamt = -pso; if (rotamt < 0) rotamt += 16; rotate = DAG.getNode(ISD::ADD, dl, PtrVT, @@ -658,20 +644,23 @@ // byte offset rotate = DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, - DAG.getConstant(-vtm->prefslot_byte, PtrVT)); + DAG.getConstant(-pso, PtrVT)); } - // Re-emit as a v16i8 vector load - result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, - LN->getPointerInfo(), + // Do the load as a i128 to allow possible shifting + SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr, + lowMemPtr, LN->isVolatile(), LN->isNonTemporal(), 16); - + + // When the size is not greater than alignment we get all data with just + // one load + if (alignment >= InVT.getSizeInBits()/8) { // Update the chain - the_chain = result.getValue(1); + the_chain = low.getValue(1); // Rotate into the preferred slot: - result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8, - result.getValue(0), rotate); + result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::i128, + low.getValue(0), rotate); // Convert the loaded v16i8 vector to the appropriate vector type // specified by the operand: @@ -679,7 +668,56 @@ InVT, (128 / InVT.getSizeInBits())); result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result)); + } + // When alignment is less than the size, we might need (known only at + // run-time) two loads + // TODO: if the memory address is composed only from constants, we have + // extra kowledge, and might avoid the second load + else { + // storage position offset from lower 16 byte aligned memory chunk + SDValue offset = DAG.getNode( ISD::AND, dl, MVT::i32, + basePtr, DAG.getConstant( 0xf, MVT::i32 ) ); + // 16 - offset + SDValue offset_compl = DAG.getNode( ISD::SUB, dl, MVT::i32, + DAG.getConstant( 16, MVT::i32), + offset ); + // get a registerfull of ones. (this implementation is a workaround: LLVM + // cannot handle 128 bit signed int constants) + SDValue ones = DAG.getConstant( -1, MVT::v4i32 ); + ones = DAG.getNode( ISD::BIT_CONVERT, dl, MVT::i128, ones); + + SDValue high = DAG.getLoad(MVT::i128, dl, the_chain, + DAG.getNode(ISD::ADD, dl, PtrVT, + basePtr, + DAG.getConstant(16, PtrVT)), + highMemPtr, + LN->isVolatile(), LN->isNonTemporal(), 16); + + the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1), + high.getValue(1)); + + // Shift the (possible) high part right to compensate the misalignemnt. + // if there is no highpart (i.e. value is i64 and offset is 4), this + // will zero out the high value. + high = DAG.getNode( SPUISD::SRL_BYTES, dl, MVT::i128, high, + DAG.getNode( ISD::SUB, dl, MVT::i32, + DAG.getConstant( 16, MVT::i32), + offset + )); + + // Shift the low similarily + // TODO: add SPUISD::SHL_BYTES + low = DAG.getNode( SPUISD::SHL_BYTES, dl, MVT::i128, low, offset ); + + // Merge the two parts + result = DAG.getNode( ISD::BIT_CONVERT, dl, vecVT, + DAG.getNode(ISD::OR, dl, MVT::i128, low, high)); + + if (!InVT.isVector()) { + result = DAG.getNode( SPUISD::VEC2PREFSLOT, dl, InVT, result ); + } + } // Handle extending loads by extending the scalar result: if (ExtType == ISD::SEXTLOAD) { result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result); @@ -703,21 +741,6 @@ result = DAG.getNode(SPUISD::LDRESULT, dl, retvts, retops, sizeof(retops) / sizeof(retops[0])); return result; - } - case ISD::PRE_INC: - case ISD::PRE_DEC: - case ISD::POST_INC: - case ISD::POST_DEC: - case ISD::LAST_INDEXED_MODE: - { - report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other " - "than UNINDEXED\n" + - Twine((unsigned)LN->getAddressingMode())); - /*NOTREACHED*/ - } - } - - return SDValue(); } /// Custom lower stores for CellSPU @@ -735,12 +758,24 @@ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); DebugLoc dl = Op.getDebugLoc(); unsigned alignment = SN->getAlignment(); + SDValue result; + EVT vecVT = StVT.isVector()? StVT: EVT::getVectorVT(*DAG.getContext(), StVT, + (128 / StVT.getSizeInBits())); + // Get pointerinfos to the memory chunk(s) that contain the data to load + uint64_t mpi_offset = SN->getPointerInfo().Offset; + mpi_offset -= mpi_offset%16; + MachinePointerInfo lowMemPtr( SN->getPointerInfo().V, mpi_offset); + MachinePointerInfo highMemPtr( SN->getPointerInfo().V, mpi_offset+16); + + + // two sanity checks + assert( SN->getAddressingMode() == ISD::UNINDEXED + && "we should get only UNINDEXED adresses"); + // clean aligned loads can be selected as-is + if (StVT.getSizeInBits() == 128 && alignment == 16) + return SDValue(); + - switch (SN->getAddressingMode()) { - case ISD::UNINDEXED: { - // The vector type we really want to load from the 16-byte chunk. - EVT vecVT = EVT::getVectorVT(*DAG.getContext(), - VT, (128 / VT.getSizeInBits())); SDValue alignLoadVec; SDValue basePtr = SN->getBasePtr(); @@ -811,17 +846,17 @@ DAG.getConstant(0, PtrVT)); } - // Load the memory to which to store. - alignLoadVec = DAG.getLoad(vecVT, dl, the_chain, basePtr, - SN->getPointerInfo(), - SN->isVolatile(), SN->isNonTemporal(), 16); + // Load the lower part of the memory to which to store. + SDValue low = DAG.getLoad(vecVT, dl, the_chain, basePtr, + lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), 16); + // if we don't need to store over the 16 byte boundary, one store suffices + if (alignment >= StVT.getSizeInBits()/8) { // Update the chain - the_chain = alignLoadVec.getValue(1); + the_chain = low.getValue(1); - LoadSDNode *LN = cast(alignLoadVec); + LoadSDNode *LN = cast(low); SDValue theValue = SN->getValue(); - SDValue result; if (StVT != VT && (theValue.getOpcode() == ISD::AssertZext @@ -849,14 +884,14 @@ theValue); result = DAG.getNode(SPUISD::SHUFB, dl, vecVT, - vectorizeOp, alignLoadVec, + vectorizeOp, low, DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, insertEltOp)); result = DAG.getStore(the_chain, dl, result, basePtr, - LN->getPointerInfo(), + lowMemPtr, LN->isVolatile(), LN->isNonTemporal(), - LN->getAlignment()); + 16); #if 0 && !defined(NDEBUG) if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) { @@ -869,24 +904,106 @@ DAG.setRoot(currentRoot); } #endif - - return result; - /*UNREACHED*/ - } - case ISD::PRE_INC: - case ISD::PRE_DEC: - case ISD::POST_INC: - case ISD::POST_DEC: - case ISD::LAST_INDEXED_MODE: - { - report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other " - "than UNINDEXED\n" + - Twine((unsigned)SN->getAddressingMode())); - /*NOTREACHED*/ - } } + // do the store when it might cross the 16 byte memory access boundary. + else { + // TODO issue a warning if SN->isVolatile()== true? This is likely not + // what the user wanted. + + // address offset from nearest lower 16byte alinged address + SDValue offset = DAG.getNode(ISD::AND, dl, MVT::i32, + SN->getBasePtr(), + DAG.getConstant(0xf, MVT::i32)); + // 16 - offset + SDValue offset_compl = DAG.getNode(ISD::SUB, dl, MVT::i32, + DAG.getConstant( 16, MVT::i32), + offset); + SDValue hi_shift = DAG.getNode(ISD::SUB, dl, MVT::i32, + DAG.getConstant( VT.getSizeInBits()/8, + MVT::i32), + offset_compl); + // 16 - sizeof(Value) + SDValue surplus = DAG.getNode(ISD::SUB, dl, MVT::i32, + DAG.getConstant( 16, MVT::i32), + DAG.getConstant( VT.getSizeInBits()/8, + MVT::i32)); + // get a registerfull of ones + SDValue ones = DAG.getConstant(-1, MVT::v4i32); + ones = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, ones); + + // Create the 128 bit masks that have ones where the data to store is + // located. + SDValue lowmask, himask; + // if the value to store don't fill up the an entire 128 bits, zero + // out the last bits of the mask so that only the value we want to store + // is masked. + // this is e.g. in the case of store i32, align 2 + if (!VT.isVector()){ + Value = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, Value); + lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, ones, surplus); + lowmask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask, + surplus); + Value = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, Value); + Value = DAG.getNode(ISD::AND, dl, MVT::i128, Value, lowmask); + + } + else { + lowmask = ones; + Value = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, Value); + } + // this will zero, if there are no data that goes to the high quad + himask = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, lowmask, + offset_compl); + lowmask = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, lowmask, + offset); + + // Load in the old data and zero out the parts that will be overwritten with + // the new data to store. + SDValue hi = DAG.getLoad(MVT::i128, dl, the_chain, + DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, + DAG.getConstant( 16, PtrVT)), + highMemPtr, + SN->isVolatile(), SN->isNonTemporal(), 16); + the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1), + hi.getValue(1)); + + low = DAG.getNode(ISD::AND, dl, MVT::i128, + DAG.getNode( ISD::BIT_CONVERT, dl, MVT::i128, low), + DAG.getNode( ISD::XOR, dl, MVT::i128, lowmask, ones)); + hi = DAG.getNode(ISD::AND, dl, MVT::i128, + DAG.getNode( ISD::BIT_CONVERT, dl, MVT::i128, hi), + DAG.getNode( ISD::XOR, dl, MVT::i128, himask, ones)); + + // Shift the Value to store into place. rlow contains the parts that go to + // the lower memory chunk, rhi has the parts that go to the upper one. + SDValue rlow = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, Value, offset); + rlow = DAG.getNode(ISD::AND, dl, MVT::i128, rlow, lowmask); + SDValue rhi = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, Value, + offset_compl); + + // Merge the old data and the new data and store the results + // Need to convert vectors here to integer as 'OR'ing floats assert + rlow = DAG.getNode(ISD::OR, dl, MVT::i128, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, low), + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, rlow)); + rhi = DAG.getNode(ISD::OR, dl, MVT::i128, + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, hi), + DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, rhi)); + + low = DAG.getStore(the_chain, dl, rlow, basePtr, + lowMemPtr, + SN->isVolatile(), SN->isNonTemporal(), 16); + hi = DAG.getStore(the_chain, dl, rhi, + DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, + DAG.getConstant( 16, PtrVT)), + highMemPtr, + SN->isVolatile(), SN->isNonTemporal(), 16); + result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(0), + hi.getValue(0)); + } + + return result; - return SDValue(); } //! Generate the address of a constant pool entry. @@ -2002,7 +2119,7 @@ DAG.getConstant(scaleShift, MVT::i32)); } - vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt); + vecShift = DAG.getNode(SPUISD::SHL_BYTES, dl, VecVT, N, Elt); // Replicate the bytes starting at byte 0 across the entire vector (for // consistency with the notion of a unified register set) @@ -2911,8 +3028,8 @@ } break; } - case SPUISD::SHLQUAD_L_BITS: - case SPUISD::SHLQUAD_L_BYTES: + case SPUISD::SHL_BITS: + case SPUISD::SHL_BYTES: case SPUISD::ROTBYTES_LEFT: { SDValue Op1 = N->getOperand(1); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=118889&r1=118888&r2=118889&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Fri Nov 12 04:14:03 2010 @@ -41,8 +41,9 @@ CNTB, ///< Count leading ones in bytes PREFSLOT2VEC, ///< Promote scalar->vector VEC2PREFSLOT, ///< Extract element 0 - SHLQUAD_L_BITS, ///< Rotate quad left, by bits - SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes + SHL_BITS, ///< Shift quad left, by bits + SHL_BYTES, ///< Shift quad left, by bytes + SRL_BYTES, ///< Shift quad right, by bytes. Insert zeros. VEC_ROTL, ///< Vector rotate left VEC_ROTR, ///< Vector rotate right ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI) Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=118889&r1=118888&r2=118889&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Fri Nov 12 04:14:03 2010 @@ -2369,10 +2369,13 @@ RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB", RotateShift, pattern>; -class ROTQBYVecInst: - ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB), - [(set (vectype VECREG:$rT), - (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>; +class ROTQBYGenInst: + ROTQBYInst<(outs rc:$rT), (ins rc:$rA, R32C:$rB), + [(set (type rc:$rT), + (SPUrotbytes_left (type rc:$rA), R32C:$rB))]>; + +class ROTQBYVecInst: + ROTQBYGenInst; multiclass RotateQuadLeftByBytes { @@ -2382,6 +2385,7 @@ def v4f32: ROTQBYVecInst; def v2i64: ROTQBYVecInst; def v2f64: ROTQBYVecInst; + def i128: ROTQBYGenInst; } defm ROTQBY: RotateQuadLeftByBytes; @@ -2394,10 +2398,13 @@ RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val", RotateShift, pattern>; +class ROTQBYIGenInst: + ROTQBYIInst<(outs rclass:$rT), (ins rclass:$rA, u7imm:$val), + [(set (type rclass:$rT), + (SPUrotbytes_left (type rclass:$rA), (i16 uimm7:$val)))]>; + class ROTQBYIVecInst: - ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), - [(set (vectype VECREG:$rT), - (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>; + ROTQBYIGenInst; multiclass RotateQuadByBytesImm { @@ -2407,6 +2414,7 @@ def v4f32: ROTQBYIVecInst; def v2i64: ROTQBYIVecInst; def vfi64: ROTQBYIVecInst; + def i128: ROTQBYIGenInst; } defm ROTQBYI: RotateQuadByBytesImm; @@ -2661,6 +2669,10 @@ defm ROTQMBY : RotateQuadBytes; +def : Pat<(SPUsrl_bytes GPRC:$rA, R32C:$rB), + (ROTQMBYr128 GPRC:$rA, + (SFIr32 R32C:$rB, 0))>; + class ROTQMBYIInst pattern>: RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val", RotateShift, pattern>; @@ -2749,6 +2761,11 @@ defm ROTQMBI: RotateMaskQuadByBits; +def : Pat<(srl GPRC:$rA, R32C:$rB), + (ROTQMBIr128 GPRC:$rA, + (SFIr32 R32C:$rB, 0))>; + + //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // Rotate quad and mask by bits, immediate //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ Modified: llvm/trunk/lib/Target/CellSPU/SPUNodes.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUNodes.td?rev=118889&r1=118888&r2=118889&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUNodes.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUNodes.td Fri Nov 12 04:14:03 2010 @@ -83,10 +83,6 @@ // SPUISelLowering.h): def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>; -// Shift left quadword by bits and bytes -def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>; -def SPUshlquad_l_bytes: SDNode<"SPUISD::SHLQUAD_L_BYTES", SPUvecshift_type, []>; - // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only): def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>; def SPUvec_srl: SDNode<"ISD::SRL", SPUvecshift_type, []>; @@ -105,6 +101,12 @@ def SPUrotbytes_left_bits : SDNode<"SPUISD::ROTBYTES_LEFT_BITS", SPUvecshift_type>; +// Shift entire quad left by bytes/bits. Zeros are shifted in on the right +// SHL_BITS the same as SHL for i128, but ISD::SHL is not implemented for i128 +def SPUshlquad_l_bytes: SDNode<"SPUISD::SHL_BYTES", SPUvecshift_type, []>; +def SPUshlquad_l_bits: SDNode<"SPUISD::SHL_BITS", SPUvecshift_type, []>; +def SPUsrl_bytes: SDNode<"SPUISD::SRL_BYTES", SPUvecshift_type, []>; + // SPU form select mask for bytes, immediate def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>; Modified: llvm/trunk/test/CodeGen/CellSPU/arg_ret.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/arg_ret.ll?rev=118889&r1=118888&r2=118889&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/arg_ret.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/arg_ret.ll Fri Nov 12 04:14:03 2010 @@ -26,7 +26,7 @@ define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm ) { -;CHECK: lqd $75, 80($sp) +;CHECK: lqd {{\$[0-9]+}}, 80($sp) ;CHECK-NOT: ori {{\$[0-9]+, \$[0-9]+, 0}} ;CHECK: lr $3, $4 ret %paramstruct %prm Modified: llvm/trunk/test/CodeGen/CellSPU/loads.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/loads.ll?rev=118889&r1=118888&r2=118889&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/loads.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/loads.ll Fri Nov 12 04:14:03 2010 @@ -38,3 +38,15 @@ %val = load <4 x float>* undef ret <4 x float> %val } + +;check that 'misaligned' loads that may span two memory chunks +;have two loads. Don't check for the bitmanipulation, as that +;might change with improved algorithms or scheduling +define i32 @load_misaligned( i32* %ptr ){ +;CHECK: load_misaligned +;CHECK: lqd +;CHECK: lqd +;CHECK: bi $lr + %rv = load i32* %ptr, align 2 + ret i32 %rv +} Modified: llvm/trunk/test/CodeGen/CellSPU/stores.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/stores.ll?rev=118889&r1=118888&r2=118889&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/stores.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/stores.ll Fri Nov 12 04:14:03 2010 @@ -14,6 +14,7 @@ ; RUN: grep iohl %t1.s | count 8 ; RUN: grep shufb %t1.s | count 15 ; RUN: grep frds %t1.s | count 1 +; RUN: llc < %s -march=cellspu | FileCheck %s ; ModuleID = 'stores.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" @@ -149,3 +150,15 @@ store float %conv, float* %dest ret float %conv } + +;Check stores that might span two 16 byte memory blocks +define void @store_misaligned( i32 %val, i32* %ptr) { +;CHECK: store_misaligned +;CHECK: lqd +;CHECK: lqd +;CHECK: stqd +;CHECK: stqd +;CHECK: bi $lr + store i32 %val, i32*%ptr, align 2 + ret void +} From gohman at apple.com Fri Nov 12 05:21:09 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 12 Nov 2010 11:21:09 -0000 Subject: [llvm-commits] [llvm] r118890 - /llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Message-ID: <20101112112109.20F4E2A6C12C@llvm.org> Author: djg Date: Fri Nov 12 05:21:08 2010 New Revision: 118890 URL: http://llvm.org/viewvc/llvm-project?rev=118890&view=rev Log: Re-disable TBAA for now; it broke MultiSource/Applications/JM/lencod, at least. Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=118890&r1=118889&r2=118890&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Fri Nov 12 05:21:08 2010 @@ -67,7 +67,7 @@ using namespace llvm; // For testing purposes, enable TBAA only via a special option. -static cl::opt EnableTBAA("enable-tbaa", cl::init(true)); +static cl::opt EnableTBAA("enable-tbaa", cl::init(false)); namespace { /// TBAANode - This is a simple wrapper around an MDNode which provides a From fvbommel at gmail.com Fri Nov 12 06:03:42 2010 From: fvbommel at gmail.com (Frits van Bommel) Date: Fri, 12 Nov 2010 13:03:42 +0100 Subject: [llvm-commits] [llvm] r118884 - /llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp In-Reply-To: <20101112062001.37BAC2A6C12C@llvm.org> References: <20101112062001.37BAC2A6C12C@llvm.org> Message-ID: On Fri, Nov 12, 2010 at 7:20 AM, Dan Gohman wrote: > ?// For testing purposes, enable TBAA only via a special option. > -static cl::opt EnableTBAA("enable-tbaa"); > +static cl::opt EnableTBAA("enable-tbaa", cl::init(true)); That comment is now out of date. Perhaps something like "For testing purposes, TBAA can be disabled via a special option." would now be a better description? From Renato.Golin at arm.com Fri Nov 12 06:17:21 2010 From: Renato.Golin at arm.com (Renato Golin) Date: Fri, 12 Nov 2010 12:17:21 +0000 Subject: [llvm-commits] Fwd: [llvm] r118413 - /llvm/trunk/lib/Target/ARM/ARMELFWriterInfo.h In-Reply-To: References: <20101108164727.39B812A6C12C@llvm.org> Message-ID: <4CDD3051.9090303@arm.com> On 11/11/10 22:33, Rafael Esp?ndola wrote: > Renato, do you know where do they come from? Are they just aliases? So, as we expected, those were deprecated long ago. As I found out, they're from an old ARM ABI that is not in use anymore, but for compatibility, binutils kept it as an alias. I recommend you use the new ones whenever possible. cheers, --renato -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From rafael.espindola at gmail.com Fri Nov 12 09:47:08 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 12 Nov 2010 15:47:08 -0000 Subject: [llvm-commits] [llvm] r118893 - in /llvm/trunk: lib/MC/MCParser/ELFAsmParser.cpp test/MC/ELF/section.s test/MC/ELF/type.s Message-ID: <20101112154708.329032A6C12C@llvm.org> Author: rafael Date: Fri Nov 12 09:47:08 2010 New Revision: 118893 URL: http://llvm.org/viewvc/llvm-project?rev=118893&view=rev Log: gnu as support both % and @ before types, do the same. Added: llvm/trunk/test/MC/ELF/type.s Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/test/MC/ELF/section.s Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=118893&r1=118892&r2=118893&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Fri Nov 12 09:47:08 2010 @@ -213,12 +213,6 @@ FlagsStr = getTok().getStringContents(); Lex(); - AsmToken::TokenKind TypeStartToken; - if (getContext().getAsmInfo().getCommentString()[0] == '@') - TypeStartToken = AsmToken::Percent; - else - TypeStartToken = AsmToken::At; - bool Mergeable = FlagsStr.find('M') != StringRef::npos; bool Group = FlagsStr.find('G') != StringRef::npos; @@ -229,8 +223,8 @@ return TokError("Group section must specify the type"); } else { Lex(); - if (getLexer().isNot(TypeStartToken)) - return TokError("expected the type"); + if (getLexer().isNot(AsmToken::Percent) && getLexer().isNot(AsmToken::At)) + return TokError("expected '@' or '%' before type"); Lex(); if (getParser().ParseIdentifier(TypeName)) @@ -359,8 +353,8 @@ return TokError("unexpected token in '.type' directive"); Lex(); - if (getLexer().isNot(AsmToken::At)) - return TokError("expected '@' before type"); + if (getLexer().isNot(AsmToken::Percent) && getLexer().isNot(AsmToken::At)) + return TokError("expected '@' or '%' before type"); Lex(); StringRef Type; Modified: llvm/trunk/test/MC/ELF/section.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/section.s?rev=118893&r1=118892&r2=118893&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/section.s (original) +++ llvm/trunk/test/MC/ELF/section.s Fri Nov 12 09:47:08 2010 @@ -3,12 +3,14 @@ // Test that these names are accepted. .section .note.GNU-stack,"", at progbits +.section .note.GNU-stack2,"",%progbits .section .note.GNU-,"", at progbits .section -.note.GNU,"", at progbits // CHECK: ('sh_name', 0x00000012) # '.note.GNU-stack' -// CHECK: ('sh_name', 0x00000022) # '.note.GNU-' -// CHECK: ('sh_name', 0x0000002d) # '-.note.GNU' +// CHECK: ('sh_name', 0x00000022) # '.note.GNU-stack2' +// CHECK: ('sh_name', 0x00000033) # '.note.GNU-' +// CHECK: ('sh_name', 0x0000003e) # '-.note.GNU' // Test that the dafults are used @@ -16,7 +18,7 @@ .section .fini .section .rodata -// CHECK: (('sh_name', 0x00000038) # '.init' +// CHECK: (('sh_name', 0x00000049) # '.init' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -27,8 +29,8 @@ // CHECK-NEXT: ('sh_addralign', 0x00000001) // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), -// CHECK-NEXT: # Section 0x0000000a -// CHECK-NEXT: (('sh_name', 0x0000003e) # '.fini' +// CHECK-NEXT: # Section 0x0000000b +// CHECK-NEXT: (('sh_name', 0x0000004f) # '.fini' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -39,8 +41,8 @@ // CHECK-NEXT: ('sh_addralign', 0x00000001) // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), -// CHECK-NEXT: # Section 0x0000000b -// CHECK-NEXT: (('sh_name', 0x00000044) # '.rodata' +// CHECK-NEXT: # Section 0x0000000c +// CHECK-NEXT: (('sh_name', 0x00000055) # '.rodata' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) Added: llvm/trunk/test/MC/ELF/type.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/type.s?rev=118893&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/type.s (added) +++ llvm/trunk/test/MC/ELF/type.s Fri Nov 12 09:47:08 2010 @@ -0,0 +1,29 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that both % and @ are accepted. + .global foo + .type foo,%function +foo: + + .global bar + .type bar, at object +bar: + +// CHECK: # Symbol 0x00000004 +// CHECK-NEXT: (('st_name', 0x00000005) # 'bar' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000001) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x00000005 +// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000002) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ), From grosbach at apple.com Fri Nov 12 09:57:20 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 07:57:20 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: References: Message-ID: <76C8C7AD-5BF0-40C7-87BE-7C3D00ACC8C8@apple.com> On Nov 10, 2010, at 9:57 AM, Jason Kim wrote: > Refactoring the x86 dependent code from ELFObjectWriter class has > repercussions among several (conflicting) axes of consideration, > > 1. namespace pollution - minimize pollution of the llvm: namespace > 2. consistency - try to maintain as small a delta between the changes > 3. linking - minimize the number of additional cross dependency > between the existing libraries > 4. clarity - avoid special case switching as much as possible - > 5. Xfactor - how clean is the overall resulting design? > > The possible ways forward I see are > > SMALL: keep the code nearly as is - place a switch inside > ELFObjectWriter::RecordRelocation and dispatch to > ELFObjectWriterImpl::RecordRelocation > 1. +1 no new classes > 2. +1 tiny patch > 3. +1 no new classes, just one additional function so far. > 4. -2 need to have special case switching for every routine that needs > to be tweaked. > 5. -2 Terrible! So far, its just one new switch, but ... > > tryA: move the functionality of the ELFObjectWriterImpl class into > ELFObjectWriter, and subclass ELFObjectWriter to > ELFObjectWriter. > Change most ELF specific routines to be virtual - except for the low > level Write* routines - > 1. -1 at least new classes ARMELFObjectWriter and X86ELFObjectWriter > 2. -1 large patch > 3. +2 Resulting special cases are isolated in their own class > 4. +1 Depends upon virtual dispatch for higher level differentiation > - removes unnecessary trampoline between ELFObjectWriter and > ELFObjectWriterImpl > 5. +2 This approach is the best in terms of the resulting design. The > only drawback is the distinction between MachO and ELF > This looks OK to me, and is similar to what I'm looking at for MachO. I confess I'm not completely clear on why the ELF writer is currently split into the Writer and WriterImpl classes, so that may be worth answering before proceeding too far. > tryB: subclass ELFObjectWriterImpl instead - I am still working out > the details on this one - but as of right now, it is just as complex > as the tryA case. > The only benefit to this is approach is the superficial similarity > between the ELFObjectWriter and the MachObjectWriter - in that both > still trampoline into an *Impl class to do the actual work. > Unfortunately, it also adds a requirement for registering a NEW > ELFObjecWriterImpl class (i.e. in addition to the existing > createELFObjectWriter, and without namespace pollution to llvm, > creates a linkage dependency failure). > I will reply to this thread with a patch as soon as I finish this variant. > > There are several attachments: > > small: > small-elfwriter-cpp (application/octet-stream) 2K > small-elfwriter-rename-record (application/octet-stream) 2K > > tryA > arm-mc-elf-s07-elfwriter-tryA-combined.patch (text/x-patch) 43K - > this is the combined patch - In order to make it more clear, I broke > up the steps into a dozen or so smaller patches. > tryA.tgz - archive of patches > They are combined into a tar archive - the README is reproduced here. > > Thanks for reading. > -jason > From grosbach at apple.com Fri Nov 12 10:03:35 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 08:03:35 -0800 Subject: [llvm-commits] [patch] ARM/MC/ELF add new stub for movt/movw in ARMFixupKinds In-Reply-To: References: Message-ID: <8ABAEBC3-996C-4C2E-B799-64222DAAE5C7@apple.com> Sorta. getBinaryCodeForInst() is auto-generated by tablegen, so shouldn't be modified directly. The target can register hooks for instruction operands for any special encoding needs, including registering fixups, using the EncoderMethod string. For an example, have a look at the LDRi12 instruction and how it registers a fixup for the addrmode_imm12 operand when it needs one. On Nov 11, 2010, at 7:06 PM, Jason Kim wrote: > Is getBinaryCodeForInst the best place to place the case for > supporting movt/movw fixup emission? > The call stack seems to be: > > #0 ARMMCCodeEmitter::getBinaryCodeForInstr > #1 ARMMCCodeEmitter::EncodeInstruction > #2 MCELFStreamer::EmitInstToData > #3 MCObjectStreamer::EmitInstruction > #4 ARMAsmPrinter::EmitInstruction > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Fri Nov 12 11:06:35 2010 From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=) Date: Fri, 12 Nov 2010 12:06:35 -0500 Subject: [llvm-commits] [patch] Remove what looks like dead code in the production of debug lines Message-ID: The attached patch removes what looks like dead code for the case of producing a .debug_line section with no entries. I think it is dead because we only emit these tables if we found a line directive. The gnu assembler has some strange logic on when it prints data to these sections, but if it is forced to print an "empty" .debug_line section, it stops after the header: readelf -x .debug_line test-as.o Hex dump of section '.debug_line': 0x00000000 19000000 02001300 00000101 fb0e0d00 ................ 0x00000010 01010101 00000001 00000100 00 ............. Which is exactly what we would print with this patch. Is it OK? Cheers, Rafael -------------- next part -------------- A non-text attachment was scrubbed... Name: t.patch Type: text/x-diff Size: 3911 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101112/45d817b4/attachment.bin From sabre at nondot.org Fri Nov 12 11:24:30 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 12 Nov 2010 17:24:30 -0000 Subject: [llvm-commits] [llvm] r118896 - in /llvm/trunk/lib: CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Target/X86/X86AsmPrinter.cpp Message-ID: <20101112172430.344742A6C12C@llvm.org> Author: lattner Date: Fri Nov 12 11:24:29 2010 New Revision: 118896 URL: http://llvm.org/viewvc/llvm-project?rev=118896&view=rev Log: tidy up. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118896&r1=118895&r2=118896&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Nov 12 11:24:29 2010 @@ -5030,13 +5030,11 @@ !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { const Type* T = I.getArgOperand(i)->getType(); - for (po_iterator i = po_begin(T), - e = po_end(T); - i != e; ++i) { - if (i->isFloatingPointTy()) { - MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); - break; - } + for (po_iterator i = po_begin(T), e = po_end(T); + i != e; ++i) { + if (!i->isFloatingPointTy()) continue; + MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); + break; } } } Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=118896&r1=118895&r2=118896&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Fri Nov 12 11:24:29 2010 @@ -580,9 +580,8 @@ OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); } - if (Subtarget->isTargetWindows() - && !Subtarget->isTargetCygMing() - && MMI->callsExternalVAFunctionWithFloatingPointArguments()) { + if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing() && + MMI->callsExternalVAFunctionWithFloatingPointArguments()) { StringRef SymbolName = Subtarget->is64Bit() ? "_fltused" : "__fltused"; MCSymbol *S = MMI->getContext().GetOrCreateSymbol(SymbolName); OutStreamer.EmitSymbolAttribute(S, MCSA_Global); From criswell at uiuc.edu Fri Nov 12 11:39:48 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 12 Nov 2010 17:39:48 -0000 Subject: [llvm-commits] [poolalloc] r118902 - /poolalloc/trunk/tools/WatchDog/WatchDog.cpp Message-ID: <20101112173948.6A6CC2A6C12C@llvm.org> Author: criswell Date: Fri Nov 12 11:39:48 2010 New Revision: 118902 URL: http://llvm.org/viewvc/llvm-project?rev=118902&view=rev Log: Let people know when the WatchDog barks! More clearly, print the name of the WatchDog program when it terminates a program. This makes it clear why a test case failed. Modified: poolalloc/trunk/tools/WatchDog/WatchDog.cpp Modified: poolalloc/trunk/tools/WatchDog/WatchDog.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/tools/WatchDog/WatchDog.cpp?rev=118902&r1=118901&r2=118902&view=diff ============================================================================== --- poolalloc/trunk/tools/WatchDog/WatchDog.cpp (original) +++ poolalloc/trunk/tools/WatchDog/WatchDog.cpp Fri Nov 12 11:39:48 2010 @@ -105,7 +105,7 @@ if ((fp = popen(cmd, "r")) != NULL) { if (fscanf(fp, "%d", &rss) == 1) { if (rss > rss_max_allowable) { - fprintf (stderr, "Terminating bad process %d!\n", pid_to_watch); + fprintf (stderr, "WatchDog: Terminating bad process %d!\n", pid_to_watch); kill (pid_to_watch, SIGKILL); return; } From sabre at nondot.org Fri Nov 12 11:41:20 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 12 Nov 2010 17:41:20 -0000 Subject: [llvm-commits] [llvm] r118903 - in /llvm/trunk: lib/Target/X86/X86InstrControl.td test/MC/X86/x86-64.s Message-ID: <20101112174120.D96212A6C12C@llvm.org> Author: lattner Date: Fri Nov 12 11:41:20 2010 New Revision: 118903 URL: http://llvm.org/viewvc/llvm-project?rev=118903&view=rev Log: implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=118903&r1=118902&r2=118903&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrControl.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrControl.td Fri Nov 12 11:41:20 2010 @@ -29,6 +29,8 @@ [(X86retflag timm:$amt)]>, OpSize; def LRET : I <0xCB, RawFrm, (outs), (ins), "lret", []>; + def LRETQ : RI <0xCB, RawFrm, (outs), (ins), + "lretq", []>; def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), "lret\t$amt", []>; def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118903&r1=118902&r2=118903&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Fri Nov 12 11:41:20 2010 @@ -769,6 +769,10 @@ // CHECK: encoding: [0x66,0xca,0xce,0x7a] lretw $0x7ace +// PR8592 +lretq // CHECK: lretq # encoding: [0x48,0xcb] +lret // CHECK: lret # encoding: [0xcb] + // rdar://8403907 sysret // CHECK: sysretl From atrick at apple.com Fri Nov 12 11:50:46 2010 From: atrick at apple.com (Andrew Trick) Date: Fri, 12 Nov 2010 17:50:46 -0000 Subject: [llvm-commits] [llvm] r118904 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20101112175046.B356C2A6C12C@llvm.org> Author: atrick Date: Fri Nov 12 11:50:46 2010 New Revision: 118904 URL: http://llvm.org/viewvc/llvm-project?rev=118904&view=rev Log: Fixes PR8287: SD scheduling time. The fix is a failsafe that prevents catastrophic compilation time in the event of unreasonable LLVM IR. Code quality is a separate issue--someone upstream needs to do a better job of reducing to llvm.memcpy. If the situation can be reproduced with any supported frontend, then it will be a separate bug. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118904&r1=118903&r2=118904&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Nov 12 11:50:46 2010 @@ -71,6 +71,21 @@ cl::location(LimitFloatPrecision), cl::init(0)); +// Limit the width of DAG chains. This is important in general to prevent +// prevent DAG-based analysis from blowing up. For example, alias analysis and +// load clustering may not complete in reasonable time. It is difficult to +// recognize and avoid this situation within each individual analysis, and +// future analyses are likely to have the same behavior. Limiting DAG width is +// the safe approach, and will be especially important with global DAGs. See +// 2010-11-11-ReturnBigBuffer.ll. +// +// MaxParallelChains default is arbitrarily high to avoid affecting +// optimization, but could be lowered to improve compile time. Any ld-ld-st-st +// sequence over this should have been converted to llvm.memcpy by the fronend. +static cl::opt +MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"), + cl::init(64), cl::Hidden); + static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, const SDValue *Parts, unsigned NumParts, EVT PartVT, EVT ValueVT); @@ -2945,7 +2960,7 @@ SDValue Root; bool ConstantMemory = false; - if (I.isVolatile()) + if (I.isVolatile() || NumValues > MaxParallelChains) // Serialize volatile loads with other side effects. Root = getRoot(); else if (AA->pointsToConstantMemory( @@ -2957,11 +2972,26 @@ // Do not serialize non-volatile loads against each other. Root = DAG.getRoot(); } - + SmallVector Values(NumValues); - SmallVector Chains(NumValues); + SmallVector Chains(std::min(unsigned(MaxParallelChains), + NumValues)); EVT PtrVT = Ptr.getValueType(); - for (unsigned i = 0; i != NumValues; ++i) { + unsigned ChainI = 0; + for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { + // Serializing loads here may result in excessive register pressure, and + // TokenFactor places arbitrary choke points on the scheduler. SD scheduling + // could recover a bit by hoisting nodes upward in the chain by recognizing + // they are side-effect free or do not alias. The optimizer should really + // avoid this case by converting large object/array copies to llvm.memcpy + // (MaxParallelChains should always remain as failsafe). + if (ChainI == MaxParallelChains) { + assert(PendingLoads.empty() && "PendingLoads must be serialized first"); + SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), + MVT::Other, &Chains[0], ChainI); + Root = Chain; + ChainI = 0; + } SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, DAG.getConstant(Offsets[i], PtrVT)); @@ -2970,12 +3000,12 @@ isNonTemporal, Alignment, TBAAInfo); Values[i] = L; - Chains[i] = L.getValue(1); + Chains[ChainI] = L.getValue(1); } if (!ConstantMemory) { SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), - MVT::Other, &Chains[0], NumValues); + MVT::Other, &Chains[0], ChainI); if (isVolatile) DAG.setRoot(Chain); else @@ -3005,24 +3035,34 @@ SDValue Ptr = getValue(PtrV); SDValue Root = getRoot(); - SmallVector Chains(NumValues); + SmallVector Chains(std::min(unsigned(MaxParallelChains), + NumValues)); EVT PtrVT = Ptr.getValueType(); bool isVolatile = I.isVolatile(); bool isNonTemporal = I.getMetadata("nontemporal") != 0; unsigned Alignment = I.getAlignment(); const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); - for (unsigned i = 0; i != NumValues; ++i) { + unsigned ChainI = 0; + for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { + // See visitLoad comments. + if (ChainI == MaxParallelChains) { + SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), + MVT::Other, &Chains[0], ChainI); + Root = Chain; + ChainI = 0; + } SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, DAG.getConstant(Offsets[i], PtrVT)); - Chains[i] = DAG.getStore(Root, getCurDebugLoc(), - SDValue(Src.getNode(), Src.getResNo() + i), - Add, MachinePointerInfo(PtrV, Offsets[i]), - isVolatile, isNonTemporal, Alignment, TBAAInfo); + SDValue St = DAG.getStore(Root, getCurDebugLoc(), + SDValue(Src.getNode(), Src.getResNo() + i), + Add, MachinePointerInfo(PtrV, Offsets[i]), + isVolatile, isNonTemporal, Alignment, TBAAInfo); + Chains[ChainI] = St; } SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), - MVT::Other, &Chains[0], NumValues); + MVT::Other, &Chains[0], ChainI); ++SDNodeOrder; AssignOrderingToNode(StoreNode.getNode()); DAG.setRoot(StoreNode); From grosbach at apple.com Fri Nov 12 11:53:00 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 17:53:00 -0000 Subject: [llvm-commits] [llvm] r118905 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20101112175300.2BEFF2A6C12C@llvm.org> Author: grosbach Date: Fri Nov 12 11:52:59 2010 New Revision: 118905 URL: http://llvm.org/viewvc/llvm-project?rev=118905&view=rev Log: Encoding for ARM LDRSB instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118905&r1=118904&r2=118905&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 11:52:59 2010 @@ -700,14 +700,19 @@ string opc, string asm, list pattern> : I { - let Inst{4} = 1; - let Inst{5} = 0; // H bit - let Inst{6} = 1; // S bit - let Inst{7} = 1; - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{24} = 1; // P bit + bits<14> addr; + bits<4> Rt; let Inst{27-25} = 0b000; + let Inst{24} = 1; // P bit + let Inst{23} = addr{8}; // U bit + let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm + let Inst{21} = 0; // W bit + let Inst{20} = 1; // L bit + let Inst{19-16} = addr{12-9}; // Rn + let Inst{15-12} = Rt; // Rt + let Inst{11-8} = addr{7-4}; // imm7_4/zero + let Inst{7-4} = 0b1101; + let Inst{3-0} = addr{3-0}; // imm3_0/Rm } class AXI3ldsb pattern> From clattner at apple.com Fri Nov 12 11:55:26 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 12 Nov 2010 09:55:26 -0800 Subject: [llvm-commits] [llvm] r116592 - in /llvm/trunk: docs/CommandGuide/FileCheck.pod utils/FileCheck/FileCheck.cpp In-Reply-To: <20101015174712.A5E922A6C12C@llvm.org> References: <20101015174712.A5E922A6C12C@llvm.org> Message-ID: <3FD9CDC1-8385-4969-828A-18C1EBA32B8E@apple.com> On Oct 15, 2010, at 10:47 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Oct 15 12:47:12 2010 > New Revision: 116592 > > URL: http://llvm.org/viewvc/llvm-project?rev=116592&view=rev > Log: > Teach FileCheck to handle trailing CHECK-NOT patterns. > > A CHECK-NOT pattern without a following CHECK pattern simply checks that the > pattern doesn't match before the end of the input file. > > You can even have only CHECK-NOT patterns to check that strings appear nowhere > in the input file. Cool, does this fix PR5643? -Chris > > Modified: > llvm/trunk/docs/CommandGuide/FileCheck.pod > llvm/trunk/utils/FileCheck/FileCheck.cpp > > Modified: llvm/trunk/docs/CommandGuide/FileCheck.pod > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/FileCheck.pod?rev=116592&r1=116591&r2=116592&view=diff > ============================================================================== > --- llvm/trunk/docs/CommandGuide/FileCheck.pod (original) > +++ llvm/trunk/docs/CommandGuide/FileCheck.pod Fri Oct 15 12:47:12 2010 > @@ -165,7 +165,7 @@ > =head2 The "CHECK-NOT:" directive > > The CHECK-NOT: directive is used to verify that a string doesn't occur > -between two matches (or the first match and the beginning of the file). For > +between two matches (or before the first match, or after the last match). For > example, to verify that a load is removed by a transformation, a test like this > can be used: > > > Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileCheck/FileCheck.cpp?rev=116592&r1=116591&r2=116592&view=diff > ============================================================================== > --- llvm/trunk/utils/FileCheck/FileCheck.cpp (original) > +++ llvm/trunk/utils/FileCheck/FileCheck.cpp Fri Oct 15 12:47:12 2010 > @@ -50,6 +50,10 @@ > class Pattern { > SMLoc PatternLoc; > > + /// MatchEOF - When set, this pattern only matches the end of file. This is > + /// used for trailing CHECK-NOTs. > + bool MatchEOF; > + > /// FixedStr - If non-empty, this pattern is a fixed string match with the > /// specified fixed string. > StringRef FixedStr; > @@ -71,7 +75,7 @@ > > public: > > - Pattern() { } > + Pattern(bool matchEOF = false) : MatchEOF(matchEOF) { } > > bool ParsePattern(StringRef PatternStr, SourceMgr &SM); > > @@ -271,6 +275,12 @@ > /// there is a match, the size of the matched string is returned in MatchLen. > size_t Pattern::Match(StringRef Buffer, size_t &MatchLen, > StringMap &VariableTable) const { > + // If this is the EOF pattern, match it immediately. > + if (MatchEOF) { > + MatchLen = 0; > + return Buffer.size(); > + } > + > // If this is a fixed string pattern, just match it now. > if (!FixedStr.empty()) { > MatchLen = FixedStr.size(); > @@ -565,18 +575,20 @@ > std::swap(NotMatches, CheckStrings.back().NotStrings); > } > > + // Add an EOF pattern for any trailing CHECK-NOTs. > + if (!NotMatches.empty()) { > + CheckStrings.push_back(CheckString(Pattern(true), > + SMLoc::getFromPointer(Buffer.data()), > + false)); > + std::swap(NotMatches, CheckStrings.back().NotStrings); > + } > + > if (CheckStrings.empty()) { > errs() << "error: no check strings found with prefix '" << CheckPrefix > << ":'\n"; > return true; > } > > - if (!NotMatches.empty()) { > - errs() << "error: '" << CheckPrefix > - << "-NOT:' not supported after last check line.\n"; > - return true; > - } > - > return false; > } > > @@ -662,10 +674,11 @@ > > // Find StrNo in the file. > size_t MatchLen = 0; > - Buffer = Buffer.substr(CheckStr.Pat.Match(Buffer, MatchLen, VariableTable)); > + size_t MatchPos = CheckStr.Pat.Match(Buffer, MatchLen, VariableTable); > + Buffer = Buffer.substr(MatchPos); > > // If we didn't find a match, reject the input. > - if (Buffer.empty()) { > + if (MatchPos == StringRef::npos) { > PrintCheckFailed(SM, CheckStr, SearchFrom, VariableTable); > return 1; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From atrick at apple.com Fri Nov 12 11:57:22 2010 From: atrick at apple.com (Andrew Trick) Date: Fri, 12 Nov 2010 17:57:22 -0000 Subject: [llvm-commits] [llvm] r118906 - /llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll Message-ID: <20101112175722.49CAD2A6C12C@llvm.org> Author: atrick Date: Fri Nov 12 11:57:22 2010 New Revision: 118906 URL: http://llvm.org/viewvc/llvm-project?rev=118906&view=rev Log: Test case for PR8287: SD scheduling time. Fixed in r118904. Added: llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll Added: llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll?rev=118906&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll Fri Nov 12 11:57:22 2010 @@ -0,0 +1,31 @@ +; RUN: llc < %s PR8287: SelectionDag scheduling time. +; Yes, some front end really produces this code. But that is a +; separate bug. This is more an example than a real test, because I +; don't know how give llvm-lit a timeout. + +define void @foo([4096 x i8]* %arg1, [4096 x i8]* %arg2) { + %buffer = alloca [4096 x i8] + %pbuf = alloca [4096 x i8]* + store [4096 x i8]* %buffer, [4096 x i8]** %pbuf + + %parg1 = alloca [4096 x i8]* + store [4096 x i8]* %arg1, [4096 x i8]** %parg1 + + %parg2 = alloca [4096 x i8]* + store [4096 x i8]* %arg2, [4096 x i8]** %parg2 + + ; The original test case has intermediate blocks. + ; Presumably something fills in "buffer". + + %bufferCopy1 = load [4096 x i8]** %pbuf + %dataCopy1 = load [4096 x i8]* %bufferCopy1 + %arg1Copy = load [4096 x i8]** %parg1 + store [4096 x i8] %dataCopy1, [4096 x i8]* %arg1Copy + + %bufferCopy2 = load [4096 x i8]** %pbuf + %dataCopy2 = load [4096 x i8]* %bufferCopy2 + %arg2Copy = load [4096 x i8]** %parg2 + store [4096 x i8] %dataCopy2, [4096 x i8]* %arg2Copy + + ret void +} From stoklund at 2pi.dk Fri Nov 12 11:59:17 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 12 Nov 2010 09:59:17 -0800 Subject: [llvm-commits] [llvm] r116592 - in /llvm/trunk: docs/CommandGuide/FileCheck.pod utils/FileCheck/FileCheck.cpp In-Reply-To: <3FD9CDC1-8385-4969-828A-18C1EBA32B8E@apple.com> References: <20101015174712.A5E922A6C12C@llvm.org> <3FD9CDC1-8385-4969-828A-18C1EBA32B8E@apple.com> Message-ID: On Nov 12, 2010, at 9:55 AM, Chris Lattner wrote: > > On Oct 15, 2010, at 10:47 AM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Fri Oct 15 12:47:12 2010 >> New Revision: 116592 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=116592&view=rev >> Log: >> Teach FileCheck to handle trailing CHECK-NOT patterns. >> >> A CHECK-NOT pattern without a following CHECK pattern simply checks that the >> pattern doesn't match before the end of the input file. >> >> You can even have only CHECK-NOT patterns to check that strings appear nowhere >> in the input file. > > Cool, does this fix PR5643? So it does, both cases. /jakob From grosbach at apple.com Fri Nov 12 12:13:26 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 18:13:26 -0000 Subject: [llvm-commits] [llvm] r118907 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20101112181326.F2D622A6C132@llvm.org> Author: grosbach Date: Fri Nov 12 12:13:26 2010 New Revision: 118907 URL: http://llvm.org/viewvc/llvm-project?rev=118907&view=rev Log: Fill in the default predication bits for ARM unconditional branch. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118907&r1=118906&r2=118907&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 12:13:26 2010 @@ -1381,6 +1381,7 @@ def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, "b\t$target", [(br bb:$target)]> { bits<24> target; + let Inst{31-28} = 0b1110; let Inst{23-0} = target; } From dpatel at apple.com Fri Nov 12 12:15:20 2010 From: dpatel at apple.com (Devang Patel) Date: Fri, 12 Nov 2010 10:15:20 -0800 Subject: [llvm-commits] [patch] Remove what looks like dead code in the production of debug lines In-Reply-To: References: Message-ID: On Nov 12, 2010, at 9:06 AM, Rafael Esp?ndola wrote: > The attached patch removes what looks like dead code for the case of > producing a .debug_line section with no entries. I think it is dead > because we only emit these tables if we found a line directive. > > The gnu assembler has some strange logic on when it prints data to > these sections, but if it is forced to print an "empty" .debug_line > section, it stops after the header: > > readelf -x .debug_line test-as.o > > Hex dump of section '.debug_line': > 0x00000000 19000000 02001300 00000101 fb0e0d00 ................ > 0x00000010 01010101 00000001 00000100 00 ............. > > Which is exactly what we would print with this patch. > > Is it OK? sure. - Devang From atrick at apple.com Fri Nov 12 12:17:46 2010 From: atrick at apple.com (Andrew Trick) Date: Fri, 12 Nov 2010 18:17:46 -0000 Subject: [llvm-commits] [llvm] r118908 - /llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll Message-ID: <20101112181746.961B12A6C12C@llvm.org> Author: atrick Date: Fri Nov 12 12:17:46 2010 New Revision: 118908 URL: http://llvm.org/viewvc/llvm-project?rev=118908&view=rev Log: Emacs auto-fill bug. Modified: llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll Modified: llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll?rev=118908&r1=118907&r2=118908&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2010-11-11-ReturnBigBuffer.ll Fri Nov 12 12:17:46 2010 @@ -1,4 +1,5 @@ -; RUN: llc < %s PR8287: SelectionDag scheduling time. +; RUN: llc < %s +; PR8287: SelectionDag scheduling time. ; Yes, some front end really produces this code. But that is a ; separate bug. This is more an example than a real test, because I ; don't know how give llvm-lit a timeout. From atrick at apple.com Fri Nov 12 12:36:03 2010 From: atrick at apple.com (Andrew Trick) Date: Fri, 12 Nov 2010 18:36:03 -0000 Subject: [llvm-commits] [llvm] r118913 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20101112183603.9AE272A6C12C@llvm.org> Author: atrick Date: Fri Nov 12 12:36:03 2010 New Revision: 118913 URL: http://llvm.org/viewvc/llvm-project?rev=118913&view=rev Log: typo (4th checkin for one fix) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118913&r1=118912&r2=118913&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Nov 12 12:36:03 2010 @@ -81,7 +81,7 @@ // // MaxParallelChains default is arbitrarily high to avoid affecting // optimization, but could be lowered to improve compile time. Any ld-ld-st-st -// sequence over this should have been converted to llvm.memcpy by the fronend. +// sequence over this should have been converted to llvm.memcpy by the frontend. static cl::opt MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"), cl::init(64), cl::Hidden); From rafael.espindola at gmail.com Fri Nov 12 12:41:26 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 12 Nov 2010 18:41:26 -0000 Subject: [llvm-commits] [llvm] r118914 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20101112184126.AC6652A6C12C@llvm.org> Author: rafael Date: Fri Nov 12 12:41:26 2010 New Revision: 118914 URL: http://llvm.org/viewvc/llvm-project?rev=118914&view=rev Log: Remove what looks like dead code in the production of debug lines. We only produce debug line information if we have seen a line directive, so this code is dead. Also, if we want to be bug by bug compatible with gas and sometimes produce "empty" .debug_line sections, this will match the content produced by gas. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=118914&r1=118913&r2=118914&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Fri Nov 12 12:41:26 2010 @@ -135,7 +135,7 @@ // This emits the Dwarf line table for the specified section from the entries // in the LineSection. // -static inline bool EmitDwarfLineTable(MCObjectStreamer *MCOS, +static inline void EmitDwarfLineTable(MCObjectStreamer *MCOS, const MCSection *Section, MCLineSection *LineSection, const MCSection *DwarfLineSection) { @@ -144,7 +144,6 @@ unsigned Column = 0; unsigned Flags = DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_IS_STMT : 0; unsigned Isa = 0; - bool EmittedLineTable = false; MCSymbol *LastLabel = NULL; MCSectionData &DLS = MCOS->getAssembler().getOrCreateSectionData(*DwarfLineSection); @@ -202,7 +201,6 @@ LastLine = it->getLine(); LastLabel = Label; - EmittedLineTable = true; } // Emit a DW_LNE_end_sequence for the end of the section. @@ -226,8 +224,6 @@ 0); // Create a Dwarf Line fragment for the LineDelta and AddrDelta. new MCDwarfLineAddrFragment(INT64_MAX, *AddrDelta, &DLS); - - return EmittedLineTable; } // @@ -315,56 +311,17 @@ MCOS->EmitLabel(ProEndSym); // Put out the line tables. - bool EmittedLineTable = false; DenseMap &MCLineSections = MCOS->getContext().getMCLineSections(); for (DenseMap::iterator it = MCLineSections.begin(), ie = MCLineSections.end(); it != ie; ++it) { - EmittedLineTable = EmitDwarfLineTable(MCOS, it->first, it->second, - DwarfLineSection); + EmitDwarfLineTable(MCOS, it->first, it->second, DwarfLineSection); // Now delete the MCLineSections that were created in MCLineEntry::Make() // and used to emit the line table. delete it->second; } - // If there are no line tables emited then we emit: - // The following DW_LNE_set_address sequence to set the address to zero and - // the DW_LNE_end_sequence. - if (EmittedLineTable == false) { - if (MCOS->getAssembler().getBackend().getPointerSize() == 8) { - // This is the DW_LNE_set_address sequence for 64-bit code. - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(9, 1); - MCOS->EmitIntValue(2, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - } - else { - // This is the DW_LNE_set_address sequence for 32-bit code. - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(5, 1); - MCOS->EmitIntValue(2, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - MCOS->EmitIntValue(0, 1); - } - - // Lastly emit the DW_LNE_end_sequence which consists of 3 bytes '00 01 01' - // (00 is the code for extended opcodes, followed by a ULEB128 length of the - // extended opcode (01), and the DW_LNE_end_sequence (01). - MCOS->EmitIntValue(0, 1); // DW_LNS_extended_op - MCOS->EmitIntValue(1, 1); // ULEB128 length of the extended opcode - MCOS->EmitIntValue(1, 1); // DW_LNE_end_sequence - } - // This is the end of the section, so set the value of the symbol at the end // of this section (that was used in a previous expression). MCOS->EmitLabel(LineEndSym); From evan.cheng at apple.com Fri Nov 12 12:44:17 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 10:44:17 -0800 Subject: [llvm-commits] [llvm] r118904 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp In-Reply-To: <20101112175046.B356C2A6C12C@llvm.org> References: <20101112175046.B356C2A6C12C@llvm.org> Message-ID: <11ACE3DD-E5C2-46B5-A7AA-DDA0A7B3D361@apple.com> Nice. Thanks Andy. Evan On Nov 12, 2010, at 9:50 AM, Andrew Trick wrote: > Author: atrick > Date: Fri Nov 12 11:50:46 2010 > New Revision: 118904 > > URL: http://llvm.org/viewvc/llvm-project?rev=118904&view=rev > Log: > Fixes PR8287: SD scheduling time. The fix is a failsafe that prevents > catastrophic compilation time in the event of unreasonable LLVM > IR. Code quality is a separate issue--someone upstream needs to do a > better job of reducing to llvm.memcpy. If the situation can be reproduced with > any supported frontend, then it will be a separate bug. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=118904&r1=118903&r2=118904&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Nov 12 11:50:46 2010 > @@ -71,6 +71,21 @@ > cl::location(LimitFloatPrecision), > cl::init(0)); > > +// Limit the width of DAG chains. This is important in general to prevent > +// prevent DAG-based analysis from blowing up. For example, alias analysis and > +// load clustering may not complete in reasonable time. It is difficult to > +// recognize and avoid this situation within each individual analysis, and > +// future analyses are likely to have the same behavior. Limiting DAG width is > +// the safe approach, and will be especially important with global DAGs. See > +// 2010-11-11-ReturnBigBuffer.ll. > +// > +// MaxParallelChains default is arbitrarily high to avoid affecting > +// optimization, but could be lowered to improve compile time. Any ld-ld-st-st > +// sequence over this should have been converted to llvm.memcpy by the fronend. > +static cl::opt > +MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"), > + cl::init(64), cl::Hidden); > + > static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, > const SDValue *Parts, unsigned NumParts, > EVT PartVT, EVT ValueVT); > @@ -2945,7 +2960,7 @@ > > SDValue Root; > bool ConstantMemory = false; > - if (I.isVolatile()) > + if (I.isVolatile() || NumValues > MaxParallelChains) > // Serialize volatile loads with other side effects. > Root = getRoot(); > else if (AA->pointsToConstantMemory( > @@ -2957,11 +2972,26 @@ > // Do not serialize non-volatile loads against each other. > Root = DAG.getRoot(); > } > - > + > SmallVector Values(NumValues); > - SmallVector Chains(NumValues); > + SmallVector Chains(std::min(unsigned(MaxParallelChains), > + NumValues)); > EVT PtrVT = Ptr.getValueType(); > - for (unsigned i = 0; i != NumValues; ++i) { > + unsigned ChainI = 0; > + for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { > + // Serializing loads here may result in excessive register pressure, and > + // TokenFactor places arbitrary choke points on the scheduler. SD scheduling > + // could recover a bit by hoisting nodes upward in the chain by recognizing > + // they are side-effect free or do not alias. The optimizer should really > + // avoid this case by converting large object/array copies to llvm.memcpy > + // (MaxParallelChains should always remain as failsafe). > + if (ChainI == MaxParallelChains) { > + assert(PendingLoads.empty() && "PendingLoads must be serialized first"); > + SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), > + MVT::Other, &Chains[0], ChainI); > + Root = Chain; > + ChainI = 0; > + } > SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), > PtrVT, Ptr, > DAG.getConstant(Offsets[i], PtrVT)); > @@ -2970,12 +3000,12 @@ > isNonTemporal, Alignment, TBAAInfo); > > Values[i] = L; > - Chains[i] = L.getValue(1); > + Chains[ChainI] = L.getValue(1); > } > > if (!ConstantMemory) { > SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), > - MVT::Other, &Chains[0], NumValues); > + MVT::Other, &Chains[0], ChainI); > if (isVolatile) > DAG.setRoot(Chain); > else > @@ -3005,24 +3035,34 @@ > SDValue Ptr = getValue(PtrV); > > SDValue Root = getRoot(); > - SmallVector Chains(NumValues); > + SmallVector Chains(std::min(unsigned(MaxParallelChains), > + NumValues)); > EVT PtrVT = Ptr.getValueType(); > bool isVolatile = I.isVolatile(); > bool isNonTemporal = I.getMetadata("nontemporal") != 0; > unsigned Alignment = I.getAlignment(); > const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); > > - for (unsigned i = 0; i != NumValues; ++i) { > + unsigned ChainI = 0; > + for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { > + // See visitLoad comments. > + if (ChainI == MaxParallelChains) { > + SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), > + MVT::Other, &Chains[0], ChainI); > + Root = Chain; > + ChainI = 0; > + } > SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, > DAG.getConstant(Offsets[i], PtrVT)); > - Chains[i] = DAG.getStore(Root, getCurDebugLoc(), > - SDValue(Src.getNode(), Src.getResNo() + i), > - Add, MachinePointerInfo(PtrV, Offsets[i]), > - isVolatile, isNonTemporal, Alignment, TBAAInfo); > + SDValue St = DAG.getStore(Root, getCurDebugLoc(), > + SDValue(Src.getNode(), Src.getResNo() + i), > + Add, MachinePointerInfo(PtrV, Offsets[i]), > + isVolatile, isNonTemporal, Alignment, TBAAInfo); > + Chains[ChainI] = St; > } > > SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), > - MVT::Other, &Chains[0], NumValues); > + MVT::Other, &Chains[0], ChainI); > ++SDNodeOrder; > AssignOrderingToNode(StoreNode.getNode()); > DAG.setRoot(StoreNode); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Fri Nov 12 12:54:56 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 12 Nov 2010 18:54:56 -0000 Subject: [llvm-commits] [llvm] r118916 - in /llvm/trunk: lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrInfo.td test/MC/X86/x86-64.s Message-ID: <20101112185456.F1CF22A6C12C@llvm.org> Author: lattner Date: Fri Nov 12 12:54:56 2010 New Revision: 118916 URL: http://llvm.org/viewvc/llvm-project?rev=118916&view=rev Log: accept lret as an alias for lretl, fixing the reopened part of PR8592 Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=118916&r1=118915&r2=118916&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrControl.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrControl.td Fri Nov 12 12:54:56 2010 @@ -27,8 +27,8 @@ def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), "retw\t$amt", [(X86retflag timm:$amt)]>, OpSize; - def LRET : I <0xCB, RawFrm, (outs), (ins), - "lret", []>; + def LRETL : I <0xCB, RawFrm, (outs), (ins), + "lretl", []>; def LRETQ : RI <0xCB, RawFrm, (outs), (ins), "lretq", []>; def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=118916&r1=118915&r2=118916&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Nov 12 12:54:56 2010 @@ -1264,6 +1264,9 @@ def : MnemonicAlias<"cwde", "cwtl">; def : MnemonicAlias<"cdqe", "cltq">; +// lret maps to lretl, it is not ambiguous with lretq. +def : MnemonicAlias<"lret", "lretl">; + def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>; Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=118916&r1=118915&r2=118916&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Fri Nov 12 12:54:56 2010 @@ -771,7 +771,8 @@ // PR8592 lretq // CHECK: lretq # encoding: [0x48,0xcb] -lret // CHECK: lret # encoding: [0xcb] +lretl // CHECK: lretl # encoding: [0xcb] +lret // CHECK: lretl # encoding: [0xcb] // rdar://8403907 sysret From gohman at apple.com Fri Nov 12 13:14:00 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 12 Nov 2010 19:14:00 -0000 Subject: [llvm-commits] [llvm] r118917 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp Message-ID: <20101112191400.6C7132A6C12C@llvm.org> Author: djg Date: Fri Nov 12 13:14:00 2010 New Revision: 118917 URL: http://llvm.org/viewvc/llvm-project?rev=118917&view=rev Log: When the definition of an address value is in a different block from the user of the address, fall back to just using the address in a register instead of bailing out of fast-isel altogether. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=118917&r1=118916&r2=118917&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Nov 12 13:14:00 2010 @@ -320,11 +320,11 @@ // Don't walk into other basic blocks; it's possible we haven't // visited them yet, so the instructions may not yet be assigned // virtual registers. - if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) - return false; - - Opcode = I->getOpcode(); - U = I; + if (FuncInfo.StaticAllocaMap.count(static_cast(V)) || + FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { + Opcode = I->getOpcode(); + U = I; + } } else if (const ConstantExpr *C = dyn_cast(V)) { Opcode = C->getOpcode(); U = C; From rafael.espindola at gmail.com Fri Nov 12 13:24:06 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 12 Nov 2010 19:24:06 -0000 Subject: [llvm-commits] [llvm] r118918 - in /llvm/trunk: Makefile Makefile.config.in autoconf/configure.ac configure Message-ID: <20101112192406.AC2072A6C12C@llvm.org> Author: rafael Date: Fri Nov 12 13:24:06 2010 New Revision: 118918 URL: http://llvm.org/viewvc/llvm-project?rev=118918&view=rev Log: Add --enable-docs. Patch by NAKAMURA Takumi. Modified: llvm/trunk/Makefile llvm/trunk/Makefile.config.in llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile?rev=118918&r1=118917&r2=118918&view=diff ============================================================================== --- llvm/trunk/Makefile (original) +++ llvm/trunk/Makefile Fri Nov 12 13:24:06 2010 @@ -47,6 +47,10 @@ DIRS := $(filter-out tools/llvm-shlib, $(DIRS)) endif +ifneq ($(ENABLE_DOCS),1) + DIRS := $(filter-out docs, $(DIRS)) +endif + ifeq ($(MAKECMDGOALS),libs-only) DIRS := $(filter-out tools runtime docs, $(DIRS)) OPTIONAL_DIRS := Modified: llvm/trunk/Makefile.config.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=118918&r1=118917&r2=118918&view=diff ============================================================================== --- llvm/trunk/Makefile.config.in (original) +++ llvm/trunk/Makefile.config.in Fri Nov 12 13:24:06 2010 @@ -264,6 +264,9 @@ # information to allow gprof to be used to get execution frequencies. #ENABLE_PROFILING = 1 +# When ENABLE_DOCS is disabled, docs/ will not be built. +ENABLE_DOCS = @ENABLE_DOCS@ + # When ENABLE_DOXYGEN is enabled, the doxygen documentation will be built ENABLE_DOXYGEN = @ENABLE_DOXYGEN@ Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=118918&r1=118917&r2=118918&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Fri Nov 12 13:24:06 2010 @@ -493,6 +493,18 @@ esac fi +dnl Allow enablement of building and installing docs +AC_ARG_ENABLE(docs, + AS_HELP_STRING([--enable-docs], + [Build documents (default is YES)]),, + enableval=default) +case "$enableval" in + yes) AC_SUBST(ENABLE_DOCS,[1]) ;; + no) AC_SUBST(ENABLE_DOCS,[0]) ;; + default) AC_SUBST(ENABLE_DOCS,[1]) ;; + *) AC_MSG_ERROR([Invalid setting for --enable-docs. Use "yes" or "no"]) ;; +esac + dnl Allow enablement of doxygen generated documentation AC_ARG_ENABLE(doxygen, AS_HELP_STRING([--enable-doxygen], Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=118918&r1=118917&r2=118918&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Fri Nov 12 13:24:06 2010 @@ -688,6 +688,7 @@ DEBUG_SYMBOLS JIT TARGET_HAS_JIT +ENABLE_DOCS ENABLE_DOXYGEN ENABLE_THREADS ENABLE_PIC @@ -1411,6 +1412,7 @@ --enable-debug-symbols Build compiler with debug symbols (default is NO if optimization is on and YES if it's off) --enable-jit Enable Just In Time Compiling (default is YES) + --enable-docs Build documents (default is YES) --enable-doxygen Build doxygen documentation (default is NO) --enable-threads Use threads if available (default is YES) --enable-pic Build LLVM with Position Independent Code (default @@ -4871,6 +4873,25 @@ esac fi +# Check whether --enable-docs was given. +if test "${enable_docs+set}" = set; then + enableval=$enable_docs; +else + enableval=default +fi + +case "$enableval" in + yes) ENABLE_DOCS=1 + ;; + no) ENABLE_DOCS=0 + ;; + default) ENABLE_DOCS=1 + ;; + *) { { echo "$as_me:$LINENO: error: Invalid setting for --enable-docs. Use \"yes\" or \"no\"" >&5 +echo "$as_me: error: Invalid setting for --enable-docs. Use \"yes\" or \"no\"" >&2;} + { (exit 1); exit 1; }; } ;; +esac + # Check whether --enable-doxygen was given. if test "${enable_doxygen+set}" = set; then enableval=$enable_doxygen; @@ -11501,7 +11522,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <conf$$subs.sed <<_ACEOF +ENABLE_CBE_PRINTF_A!$ENABLE_CBE_PRINTF_A$ac_delim CLANGPATH!$CLANGPATH$ac_delim CLANGXXPATH!$CLANGXXPATH$ac_delim ENABLE_BUILT_CLANG!$ENABLE_BUILT_CLANG$ac_delim @@ -21845,7 +21867,6 @@ OCAML_LIBDIR!$OCAML_LIBDIR$ac_delim ENABLE_VISIBILITY_INLINES_HIDDEN!$ENABLE_VISIBILITY_INLINES_HIDDEN$ac_delim RPATH!$RPATH$ac_delim -RDYNAMIC!$RDYNAMIC$ac_delim _ACEOF if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 97; then @@ -21887,11 +21908,12 @@ ac_delim='%!_!# ' for ac_last_try in false false false false false :; do cat >conf$$subs.sed <<_ACEOF +RDYNAMIC!$RDYNAMIC$ac_delim LIBOBJS!$LIBOBJS$ac_delim LTLIBOBJS!$LTLIBOBJS$ac_delim _ACEOF - if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 2; then + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 3; then break elif $ac_last_try; then { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 From grosbach at apple.com Fri Nov 12 13:24:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 19:24:53 -0000 Subject: [llvm-commits] [llvm] r118919 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20101112192453.511362A6C12C@llvm.org> Author: grosbach Date: Fri Nov 12 13:24:53 2010 New Revision: 118919 URL: http://llvm.org/viewvc/llvm-project?rev=118919&view=rev Log: Remove unused class. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118919&r1=118918&r2=118919&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 13:24:53 2010 @@ -417,14 +417,6 @@ opc, asm, "", pattern>; -// addrmode2 loads and stores -class AI2 pattern> - : I { - let Inst{27-26} = 0b01; -} - // loads // LDR/LDRB/STR/STRB From benny.kra at googlemail.com Fri Nov 12 13:26:04 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 12 Nov 2010 19:26:04 -0000 Subject: [llvm-commits] [llvm] r118920 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20101112192604.798AE2A6C12C@llvm.org> Author: d0k Date: Fri Nov 12 13:26:04 2010 New Revision: 118920 URL: http://llvm.org/viewvc/llvm-project?rev=118920&view=rev Log: MCELF: Copy the symbol name only if we're going to modify it. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=118920&r1=118919&r2=118920&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Fri Nov 12 13:26:04 2010 @@ -1016,21 +1016,20 @@ // The @@@ in symbol version is replaced with @ in undefined symbols and // @@ in defined ones. StringRef Name = Symbol.getName(); + SmallString<32> Buf; + size_t Pos = Name.find("@@@"); - std::string FinalName; if (Pos != StringRef::npos) { - StringRef Prefix = Name.substr(0, Pos); - unsigned n = MSD.SectionIndex == ELF::SHN_UNDEF ? 2 : 1; - StringRef Suffix = Name.substr(Pos + n); - FinalName = Prefix.str() + Suffix.str(); - } else { - FinalName = Name.str(); + Buf += Name.substr(0, Pos); + unsigned Skip = MSD.SectionIndex == ELF::SHN_UNDEF ? 2 : 1; + Buf += Name.substr(Pos + Skip); + Name = Buf; } - uint64_t &Entry = StringIndexMap[FinalName]; + uint64_t &Entry = StringIndexMap[Name]; if (!Entry) { Entry = StringTable.size(); - StringTable += FinalName; + StringTable += Name; StringTable += '\x00'; } MSD.StringIndex = Entry; From grosbach at apple.com Fri Nov 12 13:27:45 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 19:27:45 -0000 Subject: [llvm-commits] [llvm] r118921 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20101112192745.4A7DB2A6C12C@llvm.org> Author: grosbach Date: Fri Nov 12 13:27:45 2010 New Revision: 118921 URL: http://llvm.org/viewvc/llvm-project?rev=118921&view=rev Log: Kill more unused stuff. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118921&r1=118920&r2=118921&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 13:27:45 2010 @@ -448,19 +448,6 @@ let Inst{7-4} = op; } - - - -class AI2ldw pattern> - : I { - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} class AXI2ldw pattern> : XI pattern> - : I { - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 1; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} class AXI2ldb pattern> : XI pattern> - : I { - let Inst{20} = 0; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} class AXI2stw pattern> : XI pattern> - : I { - let Inst{20} = 0; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 1; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} class AXI2stb pattern> : XI References: Message-ID: > * 0001-Explicit-autotools-version.patch.gz > > It is not intended to commit. > I installed autotools locally with suffix -x.xx. > It might be dubious for libtool, but anyway, I can generate locally > same configure on ToT with this patch. I committed the --enable-docs one. > They are attached for consistency. > When I commit them, may I commit generated configure(s) separately or fused? You should commit changes to the generated files is the same commit as the source files. What I do is just have a ~/inst/auto-llvm directory with the correct versions of libtool, autoconf and automake. That way I can just export PATH=$HOME/inst/auto-llvm:$PATH ./autoconf/AutoRegen.sh > > ...Takumi > Cheers, Rafael From evan.cheng at apple.com Fri Nov 12 14:32:20 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 20:32:20 -0000 Subject: [llvm-commits] [llvm] r118922 - in /llvm/trunk: lib/Target/ARM/ARM.td lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrVFP.td test/CodeGen/ARM/fmacs.ll test/CodeGen/ARM/fmscs.ll test/CodeGen/ARM/fnmacs.ll test/CodeGen/ARM/fnmscs.ll test/CodeGen/ARM/lsr-on-unrolled-loops.ll Message-ID: <20101112203220.CAD532A6C12C@llvm.org> Author: evancheng Date: Fri Nov 12 14:32:20 2010 New Revision: 118922 URL: http://llvm.org/viewvc/llvm-project?rev=118922&view=rev Log: Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/test/CodeGen/ARM/fmacs.ll llvm/trunk/test/CodeGen/ARM/fmscs.ll llvm/trunk/test/CodeGen/ARM/fnmacs.ll llvm/trunk/test/CodeGen/ARM/fnmscs.ll llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Fri Nov 12 14:32:20 2010 @@ -168,7 +168,8 @@ [ArchV7A, ProcA8, FeatureHasSlowVMLx, FeatureT2XtPk]>; def : Processor<"cortex-a9", CortexA9Itineraries, - [ArchV7A, ProcA9, FeatureT2XtPk]>; + [ArchV7A, ProcA9, + FeatureHasSlowVMLx, FeatureT2XtPk]>; // V7M Processors. def : ProcNoItin<"cortex-m3", [ArchV7M]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 14:32:20 2010 @@ -1577,33 +1577,6 @@ let Inst{4} = op4; } -// Double precision, binary, VML[AS] (for additional predicate) -class ADbI_vmlX opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, - dag iops, InstrItinClass itin, string opc, string asm, - list pattern> - : VFPAI { - // Instruction operands. - bits<5> Dd; - bits<5> Dn; - bits<5> Dm; - - // Encode instruction operands. - let Inst{19-16} = Dn{3-0}; - let Inst{7} = Dn{4}; - let Inst{15-12} = Dd{3-0}; - let Inst{22} = Dd{4}; - let Inst{3-0} = Dm{3-0}; - let Inst{5} = Dm{4}; - - let Inst{27-23} = opcod1; - let Inst{21-20} = opcod2; - let Inst{11-9} = 0b101; - let Inst{8} = 1; // Double precision - let Inst{6} = op6; - let Inst{4} = op4; - list Predicates = [HasVFP2, UseVMLx]; -} - // Single precision, unary class ASuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Fri Nov 12 14:32:20 2010 @@ -738,80 +738,96 @@ // FP FMA Operations. // -def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VMLAD : ADbI<0b11100, 0b00, 0, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">, + Requires<[HasVFP2,UseVMLx]>; def VMLAS : ASbIn<0b11100, 0b00, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; + RegConstraint<"$Sdin = $Sd">, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))), - (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; + (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, + Requires<[HasVFP2,UseVMLx]>; def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)), - (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; + (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, + Requires<[HasVFP2,DontUseNEONForFP, UseVMLx]>; -def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VMLSD : ADbI<0b11100, 0b00, 1, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">, + Requires<[HasVFP2,UseVMLx]>; def VMLSS : ASbIn<0b11100, 0b00, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)), SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; + RegConstraint<"$Sdin = $Sd">, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))), - (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; + (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, + Requires<[HasVFP2,UseVMLx]>; def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)), - (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; + (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; -def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VNMLAD : ADbI<0b11100, 0b01, 1, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">, + Requires<[HasVFP2,UseVMLx]>; def VNMLAS : ASbI<0b11100, 0b01, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)), SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; + RegConstraint<"$Sdin = $Sd">, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin), - (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; + (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, + Requires<[HasVFP2,UseVMLx]>; def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin), - (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; + (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; -def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0, - (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), - IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", - [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm), - (f64 DPR:$Ddin)))]>, - RegConstraint<"$Ddin = $Dd">; +def VNMLSD : ADbI<0b11100, 0b01, 0, 0, + (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), + IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", + [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm), + (f64 DPR:$Ddin)))]>, + RegConstraint<"$Ddin = $Dd">, + Requires<[HasVFP2,UseVMLx]>; def VNMLSS : ASbI<0b11100, 0b01, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, - RegConstraint<"$Sdin = $Sd">; + RegConstraint<"$Sdin = $Sd">, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin), - (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>; + (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, + Requires<[HasVFP2,UseVMLx]>; def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin), - (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>; + (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, + Requires<[HasVFP2,DontUseNEONForFP,UseVMLx]>; //===----------------------------------------------------------------------===// Modified: llvm/trunk/test/CodeGen/ARM/fmacs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmacs.ll?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fmacs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fmacs.ll Fri Nov 12 14:32:20 2010 @@ -1,24 +1,51 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test(float %acc, float %a, float %b) { +define float @t1(float %acc, float %a, float %b) { entry: +; VFP2: t1: +; VFP2: vmla.f32 + +; NEON: t1: +; NEON: vmla.f32 + +; A8: t1: +; A8: vmul.f32 +; A8: vadd.f32 %0 = fmul float %a, %b %1 = fadd float %acc, %0 ret float %1 } -; VFP2: test: -; VFP2: vmla.f32 s2, s1, s0 +define double @t2(double %acc, double %a, double %b) { +entry: +; VFP2: t2: +; VFP2: vmla.f64 + +; NEON: t2: +; NEON: vmla.f64 + +; A8: t2: +; A8: vmul.f64 +; A8: vadd.f64 + %0 = fmul double %a, %b + %1 = fadd double %acc, %0 + ret double %1 +} + +define float @t3(float %acc, float %a, float %b) { +entry: +; VFP2: t3: +; VFP2: vmla.f32 + +; NEON: t3: +; NEON: vmla.f32 -; NFP1: test: -; NFP1: vmul.f32 d0, d1, d0 -; NFP0: test: -; NFP0: vmla.f32 s2, s1, s0 - -; CORTEXA8: test: -; CORTEXA8: vmul.f32 d0, d1, d0 -; CORTEXA9: test: -; CORTEXA9: vmla.f32 s2, s1, s0 +; A8: t3: +; A8: vmul.f32 +; A8: vadd.f32 + %0 = fmul float %a, %b + %1 = fadd float %0, %acc + ret float %1 +} Modified: llvm/trunk/test/CodeGen/ARM/fmscs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fmscs.ll?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fmscs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fmscs.ll Fri Nov 12 14:32:20 2010 @@ -1,24 +1,35 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test(float %acc, float %a, float %b) { +define float @t1(float %acc, float %a, float %b) { entry: +; VFP2: t1: +; VFP2: vnmls.f32 + +; NEON: t1: +; NEON: vnmls.f32 + +; A8: t1: +; A8: vmul.f32 +; A8: vsub.f32 %0 = fmul float %a, %b %1 = fsub float %0, %acc ret float %1 } -; VFP2: test: -; VFP2: vnmls.f32 s2, s1, s0 +define double @t2(double %acc, double %a, double %b) { +entry: +; VFP2: t2: +; VFP2: vnmls.f64 -; NFP1: test: -; NFP1: vnmls.f32 s2, s1, s0 -; NFP0: test: -; NFP0: vnmls.f32 s2, s1, s0 - -; CORTEXA8: test: -; CORTEXA8: vnmls.f32 s2, s1, s0 -; CORTEXA9: test: -; CORTEXA9: vnmls.f32 s2, s1, s0 +; NEON: t2: +; NEON: vnmls.f64 + +; A8: t2: +; A8: vmul.f64 +; A8: vsub.f64 + %0 = fmul double %a, %b + %1 = fsub double %0, %acc + ret double %1 +} Modified: llvm/trunk/test/CodeGen/ARM/fnmacs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmacs.ll?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fnmacs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fnmacs.ll Fri Nov 12 14:32:20 2010 @@ -1,20 +1,35 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEONFP +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test(float %acc, float %a, float %b) { +define float @t1(float %acc, float %a, float %b) { entry: +; VFP2: t1: ; VFP2: vmls.f32 -; NEON: vmls.f32 -; NEONFP-NOT: vmls -; NEONFP-NOT: vmov.f32 -; NEONFP: vmul.f32 -; NEONFP: vsub.f32 -; NEONFP: vmov +; NEON: t1: +; NEON: vmls.f32 +; A8: t1: +; A8: vmul.f32 +; A8: vsub.f32 %0 = fmul float %a, %b %1 = fsub float %acc, %0 ret float %1 } +define double @t2(double %acc, double %a, double %b) { +entry: +; VFP2: t2: +; VFP2: vmls.f64 + +; NEON: t2: +; NEON: vmls.f64 + +; A8: t2: +; A8: vmul.f64 +; A8: vsub.f64 + %0 = fmul double %a, %b + %1 = fsub double %acc, %0 + ret double %1 +} Modified: llvm/trunk/test/CodeGen/ARM/fnmscs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmscs.ll?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fnmscs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fnmscs.ll Fri Nov 12 14:32:20 2010 @@ -1,23 +1,71 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test1(float %acc, float %a, float %b) nounwind { -; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}} +define float @t1(float %acc, float %a, float %b) nounwind { entry: +; VFP2: t1: +; VFP2: vnmla.f32 + +; NEON: t1: +; NEON: vnmla.f32 + +; A8: t1: +; A8: vnmul.f32 s0, s1, s0 +; A8: vsub.f32 d0, d0, d1 %0 = fmul float %a, %b %1 = fsub float -0.0, %0 %2 = fsub float %1, %acc ret float %2 } -define float @test2(float %acc, float %a, float %b) nounwind { -; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}} +define float @t2(float %acc, float %a, float %b) nounwind { entry: +; VFP2: t2: +; VFP2: vnmla.f32 + +; NEON: t2: +; NEON: vnmla.f32 + +; A8: t2: +; A8: vnmul.f32 s0, s1, s0 +; A8: vsub.f32 d0, d0, d1 %0 = fmul float %a, %b %1 = fmul float -1.0, %0 %2 = fsub float %1, %acc ret float %2 } +define double @t3(double %acc, double %a, double %b) nounwind { +entry: +; VFP2: t3: +; VFP2: vnmla.f64 + +; NEON: t3: +; NEON: vnmla.f64 + +; A8: t3: +; A8: vnmul.f64 d16, d16, d17 +; A8: vsub.f64 d16, d16, d17 + %0 = fmul double %a, %b + %1 = fsub double -0.0, %0 + %2 = fsub double %1, %acc + ret double %2 +} + +define double @t4(double %acc, double %a, double %b) nounwind { +entry: +; VFP2: t4: +; VFP2: vnmla.f64 + +; NEON: t4: +; NEON: vnmla.f64 + +; A8: t4: +; A8: vnmul.f64 d16, d16, d17 +; A8: vsub.f64 d16, d16, d17 + %0 = fmul double %a, %b + %1 = fmul double -1.0, %0 + %2 = fsub double %1, %acc + ret double %2 +} Modified: llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=118922&r1=118921&r2=118922&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Fri Nov 12 14:32:20 2010 @@ -4,14 +4,14 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s{{.*}}, [lr, #-128] -; CHECK: vstr.32 s{{.*}}, [lr, #-96] -; CHECK: vstr.32 s{{.*}}, [lr, #-64] -; CHECK: vstr.32 s{{.*}}, [lr, #-32] -; CHECK: vstr.32 s{{.*}}, [lr] -; CHECK: vstr.32 s{{.*}}, [lr, #32] -; CHECK: vstr.32 s{{.*}}, [lr, #64] -; CHECK: vstr.32 s{{.*}}, [lr, #96] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-128] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-96] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-64] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-32] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96] target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -627,7 +627,7 @@ ; in a register. ; CHECK: @ %bb24 -; CHECK: subs{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1 +; CHECK: subs{{.*}} {{(r[0-9]+)|(lr)}}, #1 ; CHECK: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; [#uses=1] From baldrick at free.fr Fri Nov 12 15:10:24 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 12 Nov 2010 21:10:24 -0000 Subject: [llvm-commits] [llvm] r118923 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20101112211025.098D22A6C12C@llvm.org> Author: baldrick Date: Fri Nov 12 15:10:24 2010 New Revision: 118923 URL: http://llvm.org/viewvc/llvm-project?rev=118923&view=rev Log: Have GVN simplify instructions as it goes. For example, consider "%z = %x and %y". If GVN can prove that %y equals %x, then it turns this into "%z = %x and %x". With the new code, %z will be replaced with %x everywhere (and then deleted). Previously %z would be value numbered too, which is a waste of time. Also, while a clever value numbering algorithm would give %z the same value number as %x, our current one doesn't do so (at least I don't think it does). The new logic has an essentially equivalent effect to what you would get if %z was given the same value number as %x, i.e. it should make value numbering smarter. While there, get hold of target data once at the start rather than a gazillion times all over the place. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=118923&r1=118922&r2=118923&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Fri Nov 12 15:10:24 2010 @@ -35,6 +35,7 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/Dominators.h" +#include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/Loads.h" #include "llvm/Analysis/MemoryBuiltins.h" #include "llvm/Analysis/MemoryDependenceAnalysis.h" @@ -670,6 +671,7 @@ bool NoLoads; MemoryDependenceAnalysis *MD; DominatorTree *DT; + const TargetData* TD; ValueTable VN; DenseMap localAvail; @@ -1380,8 +1382,6 @@ SmallVector ValuesPerBlock; SmallVector UnavailableBlocks; - const TargetData *TD = 0; - for (unsigned i = 0, e = Deps.size(); i != e; ++i) { BasicBlock *DepBB = Deps[i].getBB(); MemDepResult DepInfo = Deps[i].getResult(); @@ -1396,8 +1396,6 @@ // read by the load, we can extract the bits we need for the load from the // stored value. if (StoreInst *DepSI = dyn_cast(DepInfo.getInst())) { - if (TD == 0) - TD = getAnalysisIfAvailable(); if (TD && Address) { int Offset = AnalyzeLoadFromClobberingStore(LI->getType(), Address, DepSI, *TD); @@ -1413,8 +1411,6 @@ // If the clobbering value is a memset/memcpy/memmove, see if we can // forward a value on from it. if (MemIntrinsic *DepMI = dyn_cast(DepInfo.getInst())) { - if (TD == 0) - TD = getAnalysisIfAvailable(); if (TD && Address) { int Offset = AnalyzeLoadFromClobberingMemInst(LI->getType(), Address, DepMI, *TD); @@ -1445,9 +1441,6 @@ // Reject loads and stores that are to the same address but are of // different types if we have to. if (S->getValueOperand()->getType() != LI->getType()) { - if (TD == 0) - TD = getAnalysisIfAvailable(); - // If the stored value is larger or equal to the loaded value, we can // reuse it. if (TD == 0 || !CanCoerceMustAliasedValueToLoad(S->getValueOperand(), @@ -1465,9 +1458,6 @@ if (LoadInst *LD = dyn_cast(DepInst)) { // If the types mismatch and we can't handle it, reject reuse of the load. if (LD->getType() != LI->getType()) { - if (TD == 0) - TD = getAnalysisIfAvailable(); - // If the stored value is larger or equal to the loaded value, we can // reuse it. if (TD == 0 || !CanCoerceMustAliasedValueToLoad(LD, LI->getType(),*TD)){ @@ -1749,7 +1739,7 @@ // access code. Value *AvailVal = 0; if (StoreInst *DepSI = dyn_cast(Dep.getInst())) - if (const TargetData *TD = getAnalysisIfAvailable()) { + if (TD) { int Offset = AnalyzeLoadFromClobberingStore(L->getType(), L->getPointerOperand(), DepSI, *TD); @@ -1761,7 +1751,7 @@ // If the clobbering value is a memset/memcpy/memmove, see if we can forward // a value on from it. if (MemIntrinsic *DepMI = dyn_cast(Dep.getInst())) { - if (const TargetData *TD = getAnalysisIfAvailable()) { + if (TD) { int Offset = AnalyzeLoadFromClobberingMemInst(L->getType(), L->getPointerOperand(), DepMI, *TD); @@ -1805,9 +1795,8 @@ // The store and load are to a must-aliased pointer, but they may not // actually have the same type. See if we know how to reuse the stored // value (depending on its type). - const TargetData *TD = 0; if (StoredVal->getType() != L->getType()) { - if ((TD = getAnalysisIfAvailable())) { + if (TD) { StoredVal = CoerceAvailableValueToLoadType(StoredVal, L->getType(), L, *TD); if (StoredVal == 0) @@ -1836,9 +1825,8 @@ // The loads are of a must-aliased pointer, but they may not actually have // the same type. See if we know how to reuse the previously loaded value // (depending on its type). - const TargetData *TD = 0; if (DepLI->getType() != L->getType()) { - if ((TD = getAnalysisIfAvailable())) { + if (TD) { AvailableVal = CoerceAvailableValueToLoadType(DepLI, L->getType(), L,*TD); if (AvailableVal == 0) return false; @@ -1911,6 +1899,19 @@ if (isa(I)) return false; + // If the instruction can be easily simplified then do so now in preference + // to value numbering it. Value numbering often exposes redundancies, for + // example if it determines that %y is equal to %x then the instruction + // "%z = and i32 %x, %y" becomes "%z = and i32 %x, %x" which we now simplify. + if (Value *V = SimplifyInstruction(I, TD)) { + I->replaceAllUsesWith(V); + if (MD && V->getType()->isPointerTy()) + MD->invalidateCachedPointerInfo(V); + VN.erase(I); + toErase.push_back(I); + return true; + } + if (LoadInst *LI = dyn_cast(I)) { bool Changed = processLoad(LI, toErase); @@ -1997,6 +1998,7 @@ if (!NoLoads) MD = &getAnalysis(); DT = &getAnalysis(); + TD = getAnalysisIfAvailable(); VN.setAliasAnalysis(&getAnalysis()); VN.setMemDep(MD); VN.setDomTree(DT); From resistor at mac.com Fri Nov 12 15:12:40 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 12 Nov 2010 21:12:40 -0000 Subject: [llvm-commits] [llvm] r118924 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/thumb2.s Message-ID: <20101112211240.B60922A6C12C@llvm.org> Author: resistor Date: Fri Nov 12 15:12:40 2010 New Revision: 118924 URL: http://llvm.org/viewvc/llvm-project?rev=118924&view=rev Log: First stab at providing correct Thumb2 encodings, start with adc. Added: llvm/trunk/test/MC/ARM/thumb2.s Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118924&r1=118923&r2=118924&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Nov 12 15:12:40 2010 @@ -173,8 +173,12 @@ const { return 0; } unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) + const { return 0; } unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) + const { return 0; } unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118924&r1=118923&r2=118924&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Nov 12 15:12:40 2010 @@ -31,6 +31,7 @@ def t2_so_reg : Operand, // reg imm ComplexPattern { + string EncoderMethod = "getT2SORegOpValue"; let PrintMethod = "printT2SOOperand"; let MIOperandInfo = (ops rGPR, i32imm); } @@ -51,7 +52,9 @@ // represented in the imm field in the same 12-bit form that they are encoded // into t2_so_imm instructions: the 8-bit immediate is the least significant // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. -def t2_so_imm : Operand, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]>; +def t2_so_imm : Operand, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> { + string EncoderMethod = "getT2SOImmOpValue"; +} // t2_so_imm_not - Match an immediate that is a complement // of a t2_so_imm. @@ -167,6 +170,47 @@ // Multiclass helpers... // +class T2TwoRegShiftedImm pattern> + : T2sI { + bits<4> Rd; + bits<4> Rn; + bits<12> imm; + + let Inst{11-8} = Rd{3-0}; + let Inst{19-16} = Rn{3-0}; + let Inst{26} = imm{11}; + let Inst{14-12} = imm{10-8}; + let Inst{7-0} = imm{7-0}; +} + +class T2ThreeReg pattern> + : T2sI { + bits<4> Rd; + bits<4> Rn; + bits<4> Rm; + + let Inst{11-8} = Rd{3-0}; + let Inst{19-16} = Rn{3-0}; + let Inst{3-0} = Rm{3-0}; +} + +class T2TwoRegShiftedReg pattern> + : T2sI { + bits<4> Rd; + bits<4> Rn; + bits<12> ShiftedRm; + + let Inst{11-8} = Rd{3-0}; + let Inst{19-16} = Rn{3-0}; + let Inst{3-0} = ShiftedRm{3-0}; + let Inst{5-4} = ShiftedRm{6-5}; + let Inst{14-12} = ShiftedRm{11-9}; + let Inst{7-6} = ShiftedRm{8-7}; +} + /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a /// unary operation that produces a value. These are predicable and can be /// changed to modify CPSR. @@ -399,9 +443,9 @@ multiclass T2I_adde_sube_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, - opc, "\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>, + def ri : T2TwoRegShiftedImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), + IIC_iALUi, opc, "\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, Requires<[IsThumb2]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; @@ -410,9 +454,9 @@ let Inst{15} = 0; } // register - def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>, + def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, + opc, ".w\t$Rd, $Rn, $Rm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, Requires<[IsThumb2]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; @@ -424,9 +468,10 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>, + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), + IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, Requires<[IsThumb2]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -440,9 +485,10 @@ multiclass T2I_adde_sube_s_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, - opc, "\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>, + def ri : T2TwoRegShiftedImm< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, + opc, "\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, Requires<[IsThumb2]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; @@ -451,9 +497,9 @@ let Inst{15} = 0; } // register - def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>, + def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, + opc, ".w\t$Rd, $Rn, $Rm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, Requires<[IsThumb2]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; @@ -465,9 +511,10 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>, + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), + IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, Requires<[IsThumb2]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118924&r1=118923&r2=118924&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Fri Nov 12 15:12:40 2010 @@ -136,10 +136,21 @@ Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); return Binary; } + + /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. + unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { + unsigned SoImm = MI.getOperand(Op).getImm(); + unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); + assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); + return Encoded; + } /// getSORegOpValue - Return an encoded so_reg shifted register value. unsigned getSORegOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const; + unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; unsigned getRotImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { @@ -549,6 +560,47 @@ } unsigned ARMMCCodeEmitter:: +getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { + // Sub-operands are [reg, imm]. The first register is Rm, the reg to be + // shifted. The second is the amount to shift by. + // + // {3-0} = Rm. + // {4} = 0 + // {6-5} = type + // {11-7} = imm + + const MCOperand &MO = MI.getOperand(OpIdx); + const MCOperand &MO1 = MI.getOperand(OpIdx + 1); + ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); + + // Encode Rm. + unsigned Binary = getARMRegisterNumbering(MO.getReg()); + + // Encode the shift opcode. + unsigned SBits = 0; + // Set shift operand (bit[6:4]). + // LSL - 000 + // LSR - 010 + // ASR - 100 + // ROR - 110 + switch (SOpc) { + default: llvm_unreachable("Unknown shift opc!"); + case ARM_AM::lsl: SBits = 0x0; break; + case ARM_AM::lsr: SBits = 0x2; break; + case ARM_AM::asr: SBits = 0x4; break; + case ARM_AM::ror: SBits = 0x6; break; + } + + Binary |= SBits << 4; + if (SOpc == ARM_AM::rrx) + return Binary; + + // Encode shift_imm bit[11:7]. + return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; +} + +unsigned ARMMCCodeEmitter:: getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the Added: llvm/trunk/test/MC/ARM/thumb2.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=118924&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2.s (added) +++ llvm/trunk/test/MC/ARM/thumb2.s Fri Nov 12 15:12:40 2010 @@ -0,0 +1,14 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ XFAIL: * +.code 16 + +@ CHECK: adc r1, r1, #171 @ encoding: [0xab,0x01,0x41,0xf1] + adc r1, r1, #171 +@ CHECK: adc r1, r1, #1179666 @ encoding: [0x12,0x11,0x41,0xf1] + adc r1, r1, #1179666 +@ CHECK: adc r1, r1, #872428544 @ encoding: [0x34,0x21,0x41,0xf1] + adc r1, r1, #872428544 +@ CHECK: adc r1, r1, #1448498774 @ encoding: [0x56,0x31,0x41,0xf1] + adc r1, r1, #1448498774 +@ CHECK: adc r1, r1, #66846720 @ encoding: [0x7f,0x71,0x41,0xf1] + adc r1, r1, #66846720 From grosbach at apple.com Fri Nov 12 15:28:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 21:28:15 -0000 Subject: [llvm-commits] [llvm] r118925 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td Message-ID: <20101112212815.9185F2A6C12C@llvm.org> Author: grosbach Date: Fri Nov 12 15:28:15 2010 New Revision: 118925 URL: http://llvm.org/viewvc/llvm-project?rev=118925&view=rev Log: Refactor to parameterize some ARM load/store encoding patterns. Preparatory to splitting the load/store pre/post indexed instructions into [r, r] and [r, imm] forms. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118925&r1=118924&r2=118925&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 15:28:15 2010 @@ -491,90 +491,28 @@ let Inst{27-26} = 0b01; } -// Pre-indexed loads -class AI2ldwpr pattern> - : I { - let Inst{20} = 1; // L bit - let Inst{21} = 1; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} -class AI2ldbpr pattern> - : I { - let Inst{20} = 1; // L bit - let Inst{21} = 1; // W bit - let Inst{22} = 1; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} - -// Pre-indexed stores -class AI2stwpr pattern> - : I { - let Inst{20} = 0; // L bit - let Inst{21} = 1; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 1; // P bit - let Inst{27-26} = 0b01; -} -class AI2stbpr pattern> +// Pre-indexed load/stores +class AI2ldstpr pattern> : I { - let Inst{20} = 0; // L bit + let Inst{20} = isLd; // L bit let Inst{21} = 1; // W bit - let Inst{22} = 1; // B bit + let Inst{22} = opc22; // B bit let Inst{24} = 1; // P bit let Inst{27-26} = 0b01; } -// Post-indexed loads -class AI2ldwpo pattern> - : I { - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 0; // P bit - let Inst{27-26} = 0b01; -} -class AI2ldbpo pattern> - : I { - let Inst{20} = 1; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 1; // B bit - let Inst{24} = 0; // P bit - let Inst{27-26} = 0b01; -} - -// Post-indexed stores -class AI2stwpo pattern> - : I { - let Inst{20} = 0; // L bit - let Inst{21} = 0; // W bit - let Inst{22} = 0; // B bit - let Inst{24} = 0; // P bit - let Inst{27-26} = 0b01; -} -class AI2stbpo pattern> +// Post-indexed load/stores +class AI2ldstpo pattern> : I { - let Inst{20} = 0; // L bit + let Inst{20} = isLd; // L bit let Inst{21} = 0; // W bit - let Inst{22} = 1; // B bit + let Inst{22} = opc22; // B bit let Inst{24} = 0; // P bit let Inst{27-26} = 0b01; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118925&r1=118924&r2=118925&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 15:28:15 2010 @@ -1540,11 +1540,11 @@ []>, Requires<[IsARM, HasV5TE]>; // Indexed loads -def LDR_PRE : AI2ldwpr<(outs GPR:$Rt, GPR:$Rn_wb), +def LDR_PRE : AI2ldstpr<1, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru, "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDR_POST : AI2ldwpo<(outs GPR:$Rt, GPR:$Rn_wb), +def LDR_POST : AI2ldstpo<1, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru, "ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; @@ -1556,11 +1556,11 @@ (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, "ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; -def LDRB_PRE : AI2ldbpr<(outs GPR:$Rt, GPR:$Rn_wb), +def LDRB_PRE : AI2ldstpr<1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru, "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>; -def LDRB_POST : AI2ldbpo<(outs GPR:$Rt, GPR:$Rn_wb), +def LDRB_POST : AI2ldstpo<1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, "ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>; @@ -1596,13 +1596,13 @@ // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only. -def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), +def LDRT : AI2ldstpo<1, 0, (outs GPR:$dst, GPR:$base_wb), (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { let Inst{21} = 1; // overwrite } -def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), +def LDRBT : AI2ldstpo<1, 1, (outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { let Inst{21} = 1; // overwrite @@ -1641,14 +1641,14 @@ "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; // Indexed stores -def STR_PRE : AI2stwpr<(outs GPR:$base_wb), +def STR_PRE : AI2ldstpr<0, 0, (outs GPR:$base_wb), (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, IIC_iStore_ru, "str", "\t$src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; -def STR_POST : AI2stwpo<(outs GPR:$base_wb), +def STR_POST : AI2ldstpo<0, 0, (outs GPR:$base_wb), (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, IIC_iStore_ru, "str", "\t$src, [$base], $offset", "$base = $base_wb", @@ -1669,14 +1669,14 @@ [(set GPR:$base_wb, (post_truncsti16 GPR:$src, GPR:$base, am3offset:$offset))]>; -def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), +def STRB_PRE : AI2ldstpr<0, 1, (outs GPR:$base_wb), (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, IIC_iStore_bh_ru, "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; -def STRB_POST: AI2stbpo<(outs GPR:$base_wb), +def STRB_POST: AI2ldstpo<0, 1, (outs GPR:$base_wb), (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, IIC_iStore_bh_ru, "strb", "\t$src, [$base], $offset", "$base = $base_wb", @@ -1699,7 +1699,7 @@ // STRT, STRBT, and STRHT are for disassembly only. -def STRT : AI2stwpo<(outs GPR:$base_wb), +def STRT : AI2ldstpo<0, 0, (outs GPR:$base_wb), (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, IIC_iStore_ru, "strt", "\t$src, [$base], $offset", "$base = $base_wb", @@ -1707,7 +1707,7 @@ let Inst{21} = 1; // overwrite } -def STRBT : AI2stbpo<(outs GPR:$base_wb), +def STRBT : AI2ldstpo<0, 1, (outs GPR:$base_wb), (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, IIC_iStore_bh_ru, "strbt", "\t$src, [$base], $offset", "$base = $base_wb", From grosbach at apple.com Fri Nov 12 15:29:10 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 12 Nov 2010 21:29:10 -0000 Subject: [llvm-commits] [llvm] r118926 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20101112212910.CE7BC2A6C12C@llvm.org> Author: grosbach Date: Fri Nov 12 15:29:10 2010 New Revision: 118926 URL: http://llvm.org/viewvc/llvm-project?rev=118926&view=rev Log: Zap a copy/paste-o bit of dead code. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118926&r1=118925&r2=118926&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 15:29:10 2010 @@ -2368,7 +2368,6 @@ IIC_iMVNsr, "mvn", "\t$Rd, $shift", [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP { bits<4> Rd; - bits<4> Rm; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = 0b0000; @@ -2380,7 +2379,6 @@ IIC_iMVNi, "mvn", "\t$Rd, $imm", [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP { bits<4> Rd; - bits<4> Rm; bits<12> imm; let Inst{25} = 1; let Inst{19-16} = 0b0000; From aggarwa4 at illinois.edu Fri Nov 12 16:17:29 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 12 Nov 2010 22:17:29 -0000 Subject: [llvm-commits] [poolalloc] r118932 - in /poolalloc/trunk: include/dsa/DSGraph.h include/dsa/DSNode.h lib/DSA/BottomUpClosure.cpp lib/DSA/DSGraph.cpp lib/DSA/DataStructure.cpp lib/DSA/Local.cpp lib/DSA/TopDownClosure.cpp test/dsa/callgraph/test1.ll test/dsa/local/struct2.ll test/dsa/local/union_P21.ll test/dsa/local/union_P2I.ll Message-ID: <20101112221729.98D272A6C12C@llvm.org> Author: aggarwa4 Date: Fri Nov 12 16:17:29 2010 New Revision: 118932 URL: http://llvm.org/viewvc/llvm-project?rev=118932&view=rev Log: 1. Correctly handle the intToPtr and PtrToInt cases where any such two types might overlap in the type record stored by DSA. The calculation of this happens at the end of each DSA Pass now, as no other flags use these flags, and it is cheaper to only walk through the type records once per node. 2. Allow merging of an array node, with a scalar node, if both are at 0 offset, and the size of the scalar node is smaller. 3. Testcase changes for the same Added: poolalloc/trunk/test/dsa/callgraph/test1.ll poolalloc/trunk/test/dsa/local/union_P21.ll Modified: poolalloc/trunk/include/dsa/DSGraph.h poolalloc/trunk/include/dsa/DSNode.h poolalloc/trunk/lib/DSA/BottomUpClosure.cpp poolalloc/trunk/lib/DSA/DSGraph.cpp poolalloc/trunk/lib/DSA/DataStructure.cpp poolalloc/trunk/lib/DSA/Local.cpp poolalloc/trunk/lib/DSA/TopDownClosure.cpp poolalloc/trunk/test/dsa/local/struct2.ll poolalloc/trunk/test/dsa/local/union_P2I.ll Modified: poolalloc/trunk/include/dsa/DSGraph.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSGraph.h (original) +++ poolalloc/trunk/include/dsa/DSGraph.h Fri Nov 12 16:17:29 2010 @@ -506,6 +506,9 @@ MarkVAStart = 4 }; void markIncompleteNodes(unsigned Flags); + + // Mark nodes that have overlapping Int and Pointer types. + void computeIntPtrFlags(); // Mark all reachable from external as external. enum ComputeExternalFlags { Modified: poolalloc/trunk/include/dsa/DSNode.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSNode.h?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSNode.h (original) +++ poolalloc/trunk/include/dsa/DSNode.h Fri Nov 12 16:17:29 2010 @@ -252,6 +252,11 @@ return true; } + /// markIntPtrFlags - If the node at any offset has overlapping int/ptr types + /// mark the P2I flags. + /// + void markIntPtrFlags(); + /// foldNodeCompletely - If we determine that this node has some funny /// behavior happening to it that we cannot represent, we fold it down to a /// single, completely pessimistic, node. This node is represented as a Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Fri Nov 12 16:17:29 2010 @@ -135,6 +135,7 @@ // Mark external globals incomplete. GlobalsGraph->markIncompleteNodes(DSGraph::IgnoreGlobals); GlobalsGraph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + GlobalsGraph->computeIntPtrFlags(); // // Create equivalence classes for aliasing globals so that we only need to @@ -155,6 +156,7 @@ Graph->markIncompleteNodes(DSGraph::MarkFormalArgs | DSGraph::IgnoreGlobals); Graph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + Graph->computeIntPtrFlags(); } } @@ -835,6 +837,7 @@ Graph->maskIncompleteMarkers(); Graph->markIncompleteNodes(DSGraph::MarkFormalArgs); Graph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + Graph->computeIntPtrFlags(); // // Update the callgraph with the new information that we have gleaned. Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSGraph.cpp Fri Nov 12 16:17:29 2010 @@ -718,6 +718,14 @@ markExternalNode(&*I, processedNodes); } } +// computeIntPtrFlags -- mark all nodes that must get P2 flags due to type overlap +void DSGraph::computeIntPtrFlags() { + DSGraph::node_iterator I = node_begin(), + E = node_end(); + for ( ; I != E; ++I ) { + I->markIntPtrFlags(); + } +} // computeExternalFlags -- mark all reachable from external as external void DSGraph::computeExternalFlags(unsigned Flags) { Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Fri Nov 12 16:17:29 2010 @@ -319,6 +319,78 @@ return; } +/// markIntPtrFlags - Mark P2 flags on node, if integer and pointer types +/// overlap at any offset. +/// +void DSNode::markIntPtrFlags() { + // check if the types merged have both int and pointer at the same offset, + + const TargetData &TD = getParentGraph()->getTargetData(); + // check all offsets for that node. + for(unsigned offset = 0; offset < getSize() ; offset++) { + // if that Node has no Type information, skip + if(TyMap.find(offset) == TyMap.end()) + continue; + + bool pointerTy = false; + bool integerTy = false; + unsigned intSize = 0; + unsigned ptrSize = 0; + + // Iterate through all the Types, at that offset, checking if we have + // found a pointer type/integer type + for (svset::const_iterator ni = TyMap[offset]->begin(), + ne = TyMap[offset]->end(); ni != ne; ++ni) { + if((*ni)->isPointerTy()) { + pointerTy = true; + ptrSize = TD.getPointerSize(); + } + if((*ni)->isIntegerTy()) { + integerTy = true; + if (TD.getTypeStoreSize(*ni) > intSize) + intSize = TD.getTypeStoreSize(*ni); + } + } + // If this offset itself contains both pointer and integer, set the + // flags and exit. + if(pointerTy && integerTy){ + setUnknownMarker()->setIntToPtrMarker()->setPtrToIntMarker(); + return; + } + if(!pointerTy && !integerTy){ + continue; + } + + // If only either integer or pointer was found, we must see if it + // overlaps with any other pointer or integer type at an offset that + // comes later. + unsigned maxOffset = offset + (pointerTy ? ptrSize:intSize); + unsigned offset2 = offset; + while(offset2 < maxOffset && offset2 < getSize()) { + if(TyMap.find(offset2) == TyMap.end()) { + offset2++; + continue; + } + for (svset::const_iterator ni = TyMap[offset2]->begin(), + ne = TyMap[offset2]->end(); ni != ne; ++ni) { + if((*ni)->isPointerTy()) { + pointerTy = true; + } + if((*ni)->isIntegerTy()) { + integerTy = true; + } + } + // whenever we have found overlapping integer and pointer types, + // we can set the flags, and exit. + if(pointerTy && integerTy){ + setUnknownMarker()->setIntToPtrMarker()->setPtrToIntMarker(); + return; + } + offset2++; + } + } +} + /// mergeTypeInfo - This method merges the specified type into the current node /// at the specified offset. This may update the current node's type record if /// this gives more information to the node, it may do nothing to the node if @@ -341,31 +413,6 @@ TyMap[Offset] = getParentGraph()->getTypeSS().getOrCreate(TyMap[Offset], NewTy); - // check if the types merged have both int and pointer at the same offset, - // If yes, the IntToPtr and PtrToInt flag must be set on the node pointed to at - // that offset. If no such node exists, it is created. - - bool pointerTy = false; - bool integerTy = false; - for (svset::const_iterator ni = TyMap[Offset]->begin(), - ne = TyMap[Offset]->end(); ni != ne; ++ni) { - if((*ni)->isPointerTy()) { - pointerTy = true; - } - if((*ni)->isIntegerTy()) { - integerTy = true; - } - } - - if(pointerTy && integerTy) { - if(!hasLink(Offset)) { - const DSNodeHandle &NH = new DSNode(getParentGraph()); - addEdgeTo(Offset, NH); - } - DSNodeHandle &Edge = getLink(Offset); - assert(!Edge.isNull()); - Edge.getNode()->setUnknownMarker()->setIntToPtrMarker()->setPtrToIntMarker(); - } assert(TyMap[Offset]); } @@ -381,32 +428,6 @@ TyMap[Offset] = getParentGraph()->getTypeSS().getOrCreate(S); } - // check if the types merged have both int and pointer at the same offset, - // If yes, the IntToPtr and PtrToInt flag must be set on the node pointed to at - // that offset. If no such node exists, it is created. - bool pointerTy = false; - bool integerTy = false; - for (svset::const_iterator ni = TyMap[Offset]->begin(), - ne = TyMap[Offset]->end(); ni != ne; ++ni) { - if((*ni)->isPointerTy()) { - pointerTy = true; - } - if((*ni)->isIntegerTy()) { - integerTy = true; - } - const TargetData &TD = getParentGraph()->getTargetData(); - if ((Offset + TD.getTypeAllocSize(*ni))>= getSize()) growSize(Offset+TD.getTypeAllocSize(*ni)); - } - if(pointerTy && integerTy) { - if(!hasLink(Offset)) { - const DSNodeHandle &NH = new DSNode(getParentGraph()); - addEdgeTo(Offset, NH); - } - DSNodeHandle &Edge = getLink(Offset); - assert(!Edge.isNull()); - Edge.getNode()->setUnknownMarker()->setIntToPtrMarker()->setPtrToIntMarker(); - } - assert(TyMap[Offset]); } @@ -436,7 +457,6 @@ } } - void DSNode::mergeGlobals(const DSNode &RHS) { Globals.insert(RHS.Globals.begin(), RHS.Globals.end()); } @@ -508,18 +528,33 @@ NOffset = NH.getOffset(); assert(NOffset == 0 && NSize == 1); } - - if((NH.getNode()->isArrayNode() && !CurNodeH.getNode()->isArrayNode()) || - (!NH.getNode()->isArrayNode() && CurNodeH.getNode()->isArrayNode())) { - if(NH.getNode()->getSize() != 0 && CurNodeH.getNode()->getSize() != 0 - && (NH.getNode()->getSize() != CurNodeH.getNode()->getSize())){ - CurNodeH.getNode()->foldNodeCompletely(); - NH.getNode()->foldNodeCompletely(); - NSize = NH.getNode()->getSize(); - // N = NH.getNode(); - NOffset = NH.getOffset(); + + // FIXME:Add comments. + if(NH.getNode()->isArrayNode() && !CurNodeH.getNode()->isArrayNode()) { + if(NH.getNode()->getSize() != 0 && CurNodeH.getNode()->getSize() != 0) { + if((NH.getNode()->getSize() != CurNodeH.getNode()->getSize() && + (NH.getOffset() != 0 || CurNodeH.getOffset() != 0) + && NH.getNode()->getSize() < CurNodeH.getNode()->getSize())) { + CurNodeH.getNode()->foldNodeCompletely(); + NH.getNode()->foldNodeCompletely(); + NSize = NH.getNode()->getSize(); + NOffset = NH.getOffset(); + } } } + if(!NH.getNode()->isArrayNode() && CurNodeH.getNode()->isArrayNode()) { + if(NH.getNode()->getSize() != 0 && CurNodeH.getNode()->getSize() != 0) { + if((NH.getNode()->getSize() != CurNodeH.getNode()->getSize() && + (NH.getOffset() != 0 || CurNodeH.getOffset() != 0) + && NH.getNode()->getSize() > CurNodeH.getNode()->getSize())) { + CurNodeH.getNode()->foldNodeCompletely(); + NH.getNode()->foldNodeCompletely(); + NSize = NH.getNode()->getSize(); + NOffset = NH.getOffset(); + } + } + } + if (CurNodeH.getNode()->isArrayNode() && NH.getNode()->isArrayNode()) { if(NH.getNode()->getSize() != 0 && CurNodeH.getNode()->getSize() != 0 && (NH.getNode()->getSize() != CurNodeH.getNode()->getSize())){ @@ -542,8 +577,6 @@ CurNodeH.getNode()->growSize(NH.getNode()->getSize() + NOffset); assert(!CurNodeH.getNode()->isDeadNode()); - - // Merge the NodeType information. CurNodeH.getNode()->NodeType |= N->NodeType; @@ -785,29 +818,45 @@ DN = NH.getNode(); } #endif - } + } + + + // FIXME:Add comments. + if(!DN->isArrayNode() && SN->isArrayNode()) { + if(DN->getSize() != 0 && SN->getSize() != 0) { + if((DN->getSize() != SN->getSize() && + (NH.getOffset() != 0 || SrcNH.getOffset() != 0) + && DN->getSize() > SN->getSize())) { + DN->foldNodeCompletely(); + DN = NH.getNode(); + } + } + } + if(!SN->isArrayNode() && DN->isArrayNode()) { + if(DN->getSize() != 0 && SN->getSize() != 0) { + if((DN->getSize() != SN->getSize() && + (NH.getOffset() != 0 || SrcNH.getOffset() != 0) + && DN->getSize() < SN->getSize())) { + DN->foldNodeCompletely(); + DN = NH.getNode(); + } + } + } - if ((SN->isArrayNode() && !DN->isArrayNode()) || - (!SN->isArrayNode() && DN->isArrayNode())) { - if(SN->getSize() != 0 && DN->getSize() != 0 - && (SN->getSize() != DN->getSize())){ - DN->foldNodeCompletely(); - DN = NH.getNode(); + if (SN->isArrayNode() && DN->isArrayNode()) { + if((SN->getSize() != DN->getSize()) && (SN->getSize() != 0) + && DN->getSize() != 0) { + DN->foldNodeCompletely(); + DN = NH.getNode(); } - } - if (SN->isArrayNode() && DN->isArrayNode()) { - if((SN->getSize() != DN->getSize()) && (SN->getSize() != 0) && DN->getSize() != 0) { - DN->foldNodeCompletely(); - DN = NH.getNode(); - } - } - if (!DN->isNodeCompletelyFolded() && DN->getSize() < SN->getSize()) - DN->growSize(SN->getSize()); + } + if (!DN->isNodeCompletelyFolded() && DN->getSize() < SN->getSize()) + DN->growSize(SN->getSize()); // Merge the type entries of the two nodes together... if (!DN->isNodeCompletelyFolded()) - DN->mergeTypeInfo(SN, NH.getOffset() - SrcNH.getOffset()); + DN->mergeTypeInfo(SN, NH.getOffset() - SrcNH.getOffset()); } assert(!DN->isDeadNode()); Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Fri Nov 12 16:17:29 2010 @@ -188,6 +188,7 @@ | DSGraph::ProcessCallSites; g.computeExternalFlags(EFlags); + g.computeIntPtrFlags(); // Remove any nodes made dead due to merging... g.removeDeadNodes(DSGraph::KeepUnreachableGlobals); Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Fri Nov 12 16:17:29 2010 @@ -165,6 +165,7 @@ ExternallyCallable.clear(); GlobalsGraph->removeTriviallyDeadNodes(); GlobalsGraph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + GlobalsGraph->computeIntPtrFlags(); // Make sure each graph has updated external information about globals // in the globals graph. @@ -184,6 +185,7 @@ Graph->removeDeadNodes(0); Graph->computeExternalFlags(DSGraph::DontMarkFormalsExternal); + Graph->computeIntPtrFlags(); } } @@ -311,6 +313,7 @@ unsigned ExtFlags = isExternallyCallable ? DSGraph::MarkFormalsExternal : DSGraph::DontMarkFormalsExternal; DSG->computeExternalFlags(ExtFlags); + DSG->computeIntPtrFlags(); { DSGraph* GG = DSG->getGlobalsGraph(); Added: poolalloc/trunk/test/dsa/callgraph/test1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/callgraph/test1.ll?rev=118932&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/callgraph/test1.ll (added) +++ poolalloc/trunk/test/dsa/callgraph/test1.ll Fri Nov 12 16:17:29 2010 @@ -0,0 +1,110 @@ +;RUN: dsaopt %s -dsa-cbu -analyze -check-callees=lreadf,f_ungetc,lreadr +;RUN: dsaopt %s -dsa-cbu -analyze -check-callees=lreadr,f_ungetc,f_getc + +; ModuleID = 'test1.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] } +%struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } +%struct.gen_readio = type { i32 (i8*)*, void (i32, i8*)*, i8* } + +define i32* @lreadr(%struct.gen_readio* %f) nounwind { +entry: + %f_addr = alloca %struct.gen_readio* ; <%struct.gen_readio**> [#uses=5] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %t = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.gen_readio* %f, %struct.gen_readio** %f_addr + %1 = load %struct.gen_readio** %f_addr, align 8 ; <%struct.gen_readio*> [#uses=1] + %2 = getelementptr inbounds %struct.gen_readio* %1, i32 0, i32 0 ; [#uses=1] + %3 = load i32 (i8*)** %2, align 8 ; [#uses=1] + %4 = load %struct.gen_readio** %f_addr, align 8 ; <%struct.gen_readio*> [#uses=1] + %5 = getelementptr inbounds %struct.gen_readio* %4, i32 0, i32 2 ; [#uses=1] + %6 = load i8** %5, align 8 ; [#uses=1] + %7 = call i32 %3(i8* %6) nounwind ; [#uses=1] + store i32 %7, i32* %t, align 4 + %8 = load %struct.gen_readio** %f_addr, align 8 ; <%struct.gen_readio*> [#uses=1] + %9 = getelementptr inbounds %struct.gen_readio* %8, i32 0, i32 1 ; [#uses=1] + %10 = load void (i32, i8*)** %9, align 8 ; [#uses=1] + %11 = load %struct.gen_readio** %f_addr, align 8 ; <%struct.gen_readio*> [#uses=1] + %12 = getelementptr inbounds %struct.gen_readio* %11, i32 0, i32 2 ; [#uses=1] + %13 = load i8** %12, align 8 ; [#uses=1] + %14 = load i32* %t, align 4 ; [#uses=1] + call void %10(i32 %14, i8* %13) nounwind + %15 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %16 = bitcast i8* %15 to i32* ; [#uses=1] + store i32* %16, i32** %0, align 8 + %17 = load i32** %0, align 8 ; [#uses=1] + store i32* %17, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +declare noalias i8* @malloc(i64) nounwind + +define void @init(%struct.gen_readio* %f, i32 (i8*)* %fcn) nounwind { +entry: + %f_addr = alloca %struct.gen_readio* ; <%struct.gen_readio**> [#uses=2] + %fcn_addr = alloca i32 (i8*)* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.gen_readio* %f, %struct.gen_readio** %f_addr + store i32 (i8*)* %fcn, i32 (i8*)** %fcn_addr + %0 = load %struct.gen_readio** %f_addr, align 8 ; <%struct.gen_readio*> [#uses=1] + %1 = getelementptr inbounds %struct.gen_readio* %0, i32 0, i32 0 ; [#uses=1] + %2 = load i32 (i8*)** %fcn_addr, align 8 ; [#uses=1] + store i32 (i8*)* %2, i32 (i8*)** %1, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +define i32* @lreadf(%struct.FILE* %f) nounwind { +entry: + %f_addr = alloca %struct.FILE* ; <%struct.FILE**> [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %s = alloca %struct.gen_readio ; <%struct.gen_readio*> [#uses=6] + %c = alloca i32 ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.FILE* %f, %struct.FILE** %f_addr + call void @init(%struct.gen_readio* %s, i32 (i8*)* bitcast (i32 (%struct.FILE*)* @f_getc to i32 (i8*)*)) nounwind + %1 = getelementptr inbounds %struct.gen_readio* %s, i32 0, i32 1 ; [#uses=1] + store void (i32, i8*)* bitcast (void (i32, %struct.FILE*)* @f_ungetc to void (i32, i8*)*), void (i32, i8*)** %1, align 8 + %2 = getelementptr inbounds %struct.gen_readio* %s, i32 0, i32 2 ; [#uses=1] + %3 = load %struct.FILE** %f_addr, align 8 ; <%struct.FILE*> [#uses=1] + %4 = bitcast %struct.FILE* %3 to i8* ; [#uses=1] + store i8* %4, i8** %2, align 8 + %5 = getelementptr inbounds %struct.gen_readio* %s, i32 0, i32 1 ; [#uses=1] + %6 = load void (i32, i8*)** %5, align 8 ; [#uses=1] + %7 = getelementptr inbounds %struct.gen_readio* %s, i32 0, i32 2 ; [#uses=1] + %8 = load i8** %7, align 8 ; [#uses=1] + %9 = load i32* %c, align 4 ; [#uses=1] + call void %6(i32 %9, i8* %8) nounwind + %10 = call i32* @lreadr(%struct.gen_readio* %s) nounwind ; [#uses=1] + store i32* %10, i32** %0, align 8 + %11 = load i32** %0, align 8 ; [#uses=1] + store i32* %11, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +declare i32 @f_getc(%struct.FILE*) + +declare void @f_ungetc(i32, %struct.FILE*) + +define void @main() nounwind { +entry: + br label %return + +return: ; preds = %entry + ret void +} Modified: poolalloc/trunk/test/dsa/local/struct2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/struct2.ll?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/local/struct2.ll (original) +++ poolalloc/trunk/test/dsa/local/struct2.ll Fri Nov 12 16:17:29 2010 @@ -2,8 +2,8 @@ ;RUN: dsaopt %s -dsa-local -analyze -check-type=main:r,0:i64|i32*::8:i32* ;RUN: dsaopt %s -dsa-local -analyze -check-same-node=main:r:0,main:x -;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:x+SUP2-MR" -;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:y+S-UP2MR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:r+SUP2" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:r1+SUP2" ; ModuleID = 'struct2.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Added: poolalloc/trunk/test/dsa/local/union_P21.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/union_P21.ll?rev=118932&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/local/union_P21.ll (added) +++ poolalloc/trunk/test/dsa/local/union_P21.ll Fri Nov 12 16:17:29 2010 @@ -0,0 +1,49 @@ +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:obj1+UP2" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:obj+UP2" +;RUN: dsaopt %s -dsa-local -analyze -check-type=main:obj,0:i32*::4:i32 +;RUN: dsaopt %s -dsa-local -analyze -check-type=main:obj1,0:i32|i32* + +; if any part of pointer overlaps with an interger, we must mark the into to ptr flag. + + +; ModuleID = 'union_P21.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.StructType = type { i32, i32 } +%union.UnionType = type { i32* } + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=1] + %obj = alloca %union.UnionType ; <%union.UnionType*> [#uses=2] + %d = alloca i32 ; [#uses=1] + %obj1 = alloca %union.UnionType ; <%union.UnionType*> [#uses=2] + %e = alloca i32 ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + %2 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; [#uses=1] + store i32* %1, i32** %2, align 8 + %3 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; [#uses=1] + %4 = bitcast i32** %3 to %struct.StructType* ; <%struct.StructType*> [#uses=1] + %5 = getelementptr inbounds %struct.StructType* %4, i32 0, i32 1 ; [#uses=1] + %6 = load i32* %5, align 4 ; [#uses=1] + store i32 %6, i32* %d, align 4 + %7 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %8 = bitcast i8* %7 to i32* ; [#uses=1] + %9 = getelementptr inbounds %union.UnionType* %obj1, i32 0, i32 0 ; [#uses=1] + store i32* %8, i32** %9, align 8 + %10 = getelementptr inbounds %union.UnionType* %obj1, i32 0, i32 0 ; [#uses=1] + %11 = bitcast i32** %10 to %struct.StructType* ; <%struct.StructType*> [#uses=1] + %12 = getelementptr inbounds %struct.StructType* %11, i32 0, i32 0 ; [#uses=1] + %13 = load i32* %12, align 8 ; [#uses=1] + store i32 %13, i32* %e, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} + +declare noalias i8* @malloc(i64) nounwind Modified: poolalloc/trunk/test/dsa/local/union_P2I.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/union_P2I.ll?rev=118932&r1=118931&r2=118932&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/local/union_P2I.ll (original) +++ poolalloc/trunk/test/dsa/local/union_P2I.ll Fri Nov 12 16:17:29 2010 @@ -1,7 +1,7 @@ ;checks that the PtrToInt and IntToPtr flag is set on unions that contain integer and pointer types ;RUN: dsaopt %s -dsa-local -analyze -check-same-node=main:ptr:0,main:obj:0 -;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:ptr:0+UP2" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:obj+UP2" ;RUN: dsaopt %s -dsa-local -analyze -check-type=main:obj,0:i32|%\struct.StructType* From evan.cheng at apple.com Fri Nov 12 16:42:47 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 22:42:47 -0000 Subject: [llvm-commits] [llvm] r118935 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/select_xform.ll Message-ID: <20101112224247.60D0C2A6C12C@llvm.org> Author: evancheng Date: Fri Nov 12 16:42:47 2010 New Revision: 118935 URL: http://llvm.org/viewvc/llvm-project?rev=118935&view=rev Log: Add conditional mvn instructions. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/CodeGen/ARM/select_xform.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=118935&r1=118934&r2=118935&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Nov 12 16:42:47 2010 @@ -142,14 +142,30 @@ bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm); + inline bool is_so_imm(unsigned Imm) const { + return ARM_AM::getSOImmVal(Imm) != -1; + } + + inline bool is_so_imm_not(unsigned Imm) const { + return ARM_AM::getSOImmVal(~Imm) != -1; + } + + inline bool is_t2_so_imm(unsigned Imm) const { + return ARM_AM::getT2SOImmVal(Imm) != -1; + } + + inline bool is_t2_so_imm_not(unsigned Imm) const { + return ARM_AM::getT2SOImmVal(~Imm) != -1; + } + inline bool Pred_so_imm(SDNode *inN) const { ConstantSDNode *N = cast(inN); - return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; + return is_so_imm(N->getZExtValue()); } inline bool Pred_t2_so_imm(SDNode *inN) const { ConstantSDNode *N = cast(inN); - return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1; + return is_t2_so_imm(N->getZExtValue()); } // Include the pieces autogenerated from the target description. @@ -1767,13 +1783,18 @@ return 0; unsigned TrueImm = T->getZExtValue(); - bool isSoImm = Pred_t2_so_imm(TrueVal.getNode()); + bool isSoImm = is_t2_so_imm(TrueImm); if (isSoImm || TrueImm <= 0xffff) { - SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); + SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16), MVT::i32, Ops, 5); + } else if (is_t2_so_imm_not(TrueImm)) { + SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32); + SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; + return CurDAG->SelectNodeTo(N, ARM::t2MVNCCi, MVT::i32, Ops, 5); } return 0; } @@ -1786,13 +1807,18 @@ return 0; unsigned TrueImm = T->getZExtValue(); - bool isSoImm = Pred_so_imm(TrueVal.getNode()); + bool isSoImm = is_so_imm(TrueImm); if (isSoImm || (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff)) { SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::MOVCCi : ARM::MOVCCi16), MVT::i32, Ops, 5); + } else if (is_so_imm_not(TrueImm)) { + SDValue True = CurDAG->getTargetConstant(~TrueImm, MVT::i32); + SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); + SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; + return CurDAG->SelectNodeTo(N, ARM::MVNCCi, MVT::i32, Ops, 5); } return 0; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118935&r1=118934&r2=118935&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 16:42:47 2010 @@ -212,12 +212,12 @@ def so_imm_neg : PatLeaf<(imm), [{ - return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; + return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1; }], so_imm_neg_XFORM>; def so_imm_not : PatLeaf<(imm), [{ - return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; + return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; }], so_imm_not_XFORM>; // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. @@ -2875,6 +2875,7 @@ // the normal MOV instructions. That would fix the dependency on // special casing them in tblgen. let neverHasSideEffects = 1 in { +let isAsCheapAsAMove = 1 in def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm, IIC_iCMOVr, "mov", "\t$Rd, $Rm", [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, @@ -2903,6 +2904,7 @@ let Inst{11-0} = shift; } +let isAsCheapAsAMove = 1 in def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm), DPFrm, IIC_iMOVi, "movw", "\t$Rd, $imm", @@ -2918,6 +2920,7 @@ let Inst{11-0} = imm{11-0}; } +let isAsCheapAsAMove = 1 in def MOVCCi : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi, "mov", "\t$Rd, $imm", @@ -2931,6 +2934,21 @@ let Inst{15-12} = Rd; let Inst{11-0} = imm; } + +let isAsCheapAsAMove = 1 in +def MVNCCi : AI1<0b1111, (outs GPR:$Rd), + (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi, + "mvn", "\t$Rd, $imm", + [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $Rd">, UnaryDP { + bits<4> Rd; + bits<12> imm; + let Inst{25} = 1; + let Inst{20} = 0; + let Inst{19-16} = 0b0000; + let Inst{15-12} = Rd; + let Inst{11-0} = imm; +} } // neverHasSideEffects //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118935&r1=118934&r2=118935&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Nov 12 16:42:47 2010 @@ -66,7 +66,7 @@ // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. def t2_so_imm_neg : Operand, PatLeaf<(imm), [{ - return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; + return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1; }], t2_so_imm_neg_XFORM>; // Break t2_so_imm's up into two pieces. This handles immediates with up to 16 @@ -2243,7 +2243,7 @@ // Conditional moves // FIXME: should be able to write a pattern for ARMcmov, but can't use // a two-value operand where a dag node expects two operands. :( -let neverHasSideEffects = 1 in { +let neverHasSideEffects = 1, isAsCheapAsAMove = 1 in { def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr, "mov", ".w\t$dst, $true", [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>, @@ -2270,7 +2270,7 @@ } def t2MOVCCi16 : T2I<(outs rGPR:$dst), (ins rGPR:$false, i32imm:$src), - IIC_iMOVi, + IIC_iCMOVi, "movw", "\t$dst, $src", []>, RegConstraint<"$false = $dst"> { let Inst{31-27} = 0b11110; @@ -2280,6 +2280,19 @@ let Inst{15} = 0; } +def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), + IIC_iCMOVi, "mvn", ".w\t$dst, $true", +[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true, + imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst"> { + let Inst{31-27} = 0b11110; + let Inst{25} = 0; + let Inst{24-21} = 0b0011; + let Inst{20} = 0; // The S bit. + let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0; +} + class T2I_movcc_sh opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : T2I { Modified: llvm/trunk/test/CodeGen/ARM/select_xform.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select_xform.ll?rev=118935&r1=118934&r2=118935&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/select_xform.ll (original) +++ llvm/trunk/test/CodeGen/ARM/select_xform.ll Fri Nov 12 16:42:47 2010 @@ -1,15 +1,59 @@ -; RUN: llc < %s -march=arm | grep mov | count 2 +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2 +; rdar://8662825 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { - %tmp1 = icmp sgt i32 %c, 10 - %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 - %tmp3 = add i32 %tmp2, %b - ret i32 %tmp3 +; ARM: t1: +; ARM: sub r0, r1, #6, 2 +; ARM: movgt r0, r1 + +; T2: t1: +; T2: sub.w r0, r1, #-2147483648 +; T2: movgt r0, r1 + %tmp1 = icmp sgt i32 %c, 10 + %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 + %tmp3 = add i32 %tmp2, %b + ret i32 %tmp3 } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { - %tmp1 = icmp sgt i32 %c, 10 - %tmp2 = select i1 %tmp1, i32 0, i32 10 - %tmp3 = sub i32 %b, %tmp2 - ret i32 %tmp3 +; ARM: t2: +; ARM: sub r0, r1, #10 +; ARM: movgt r0, r1 + +; T2: t2: +; T2: sub.w r0, r1, #10 +; T2: movgt r0, r1 + %tmp1 = icmp sgt i32 %c, 10 + %tmp2 = select i1 %tmp1, i32 0, i32 10 + %tmp3 = sub i32 %b, %tmp2 + ret i32 %tmp3 +} + +define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { +; ARM: t3: +; ARM: mvnlt r2, #0 +; ARM: and r0, r2, r3 + +; T2: t3: +; T2: movlt.w r2, #-1 +; T2: and.w r0, r2, r3 + %cond = icmp slt i32 %a, %b + %z = select i1 %cond, i32 -1, i32 %x + %s = and i32 %z, %y + ret i32 %s +} + +define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { +; ARM: t4: +; ARM: movlt r2, #0 +; ARM: orr r0, r2, r3 + +; T2: t4: +; T2: movlt r2, #0 +; T2: orr.w r0, r2, r3 + %cond = icmp slt i32 %a, %b + %z = select i1 %cond, i32 0, i32 %x + %s = or i32 %z, %y + ret i32 %s } From echristo at apple.com Fri Nov 12 16:52:32 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 12 Nov 2010 22:52:32 -0000 Subject: [llvm-commits] [llvm] r118936 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101112225232.8C2232A6C12C@llvm.org> Author: echristo Date: Fri Nov 12 16:52:32 2010 New Revision: 118936 URL: http://llvm.org/viewvc/llvm-project?rev=118936&view=rev Log: Make this happen for ARM like x86. Don't entirely bail out when an address is in a different block, get it into a register and go from there. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118936&r1=118935&r2=118936&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Nov 12 16:52:32 2010 @@ -590,10 +590,11 @@ // Don't walk into other basic blocks; it's possible we haven't // visited them yet, so the instructions may not yet be assigned // virtual registers. - if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) - return false; - Opcode = I->getOpcode(); - U = I; + if (FuncInfo.StaticAllocaMap.count(static_cast(Obj)) || + FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { + Opcode = I->getOpcode(); + U = I; + } } else if (const ConstantExpr *C = dyn_cast(Obj)) { Opcode = C->getOpcode(); U = C; From evan.cheng at apple.com Fri Nov 12 17:03:38 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 23:03:38 -0000 Subject: [llvm-commits] [llvm] r118938 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMExpandPseudoInsts.cpp ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td Message-ID: <20101112230338.7BAFA2A6C12C@llvm.org> Author: evancheng Date: Fri Nov 12 17:03:38 2010 New Revision: 118938 URL: http://llvm.org/viewvc/llvm-project?rev=118938&view=rev Log: Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118938&r1=118937&r2=118938&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Nov 12 17:03:38 2010 @@ -805,13 +805,13 @@ } case ARM::MOVi32imm: - emitMOVi32immInstruction(MI); - break; - - case ARM::MOVi2pieces: // Two instructions to materialize a constant. - emitMOVi2piecesInstruction(MI); + if (Subtarget->hasV6T2Ops()) + emitMOVi32immInstruction(MI); + else + emitMOVi2piecesInstruction(MI); break; + case ARM::LEApcrelJT: // Materialize jumptable address. emitLEApcrelJTInstruction(MI); Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=118938&r1=118937&r2=118938&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Nov 12 17:03:38 2010 @@ -36,6 +36,7 @@ const ARMBaseInstrInfo *TII; const TargetRegisterInfo *TRI; + const ARMSubtarget *STI; virtual bool runOnMachineFunction(MachineFunction &Fn); @@ -698,6 +699,28 @@ const MachineOperand &MO = MI.getOperand(1); MachineInstrBuilder LO16, HI16; + if (Opcode == ARM::MOVi32imm && !STI->hasV6T2Ops()) { + // Expand into a movi + orr. + LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); + HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) + .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) + .addReg(DstReg); + + assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); + unsigned ImmVal = (unsigned)MO.getImm(); + unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); + unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); + LO16 = LO16.addImm(SOImmValV1); + HI16 = HI16.addImm(SOImmValV2); + (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); + (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); + LO16.addImm(Pred).addReg(PredReg).addReg(0); + HI16.addImm(Pred).addReg(PredReg).addReg(0); + TransferImpOps(MI, LO16, HI16); + MI.eraseFromParent(); + break; + } + LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode == ARM::MOVi32imm ? ARM::MOVi16 : ARM::t2MOVi16), @@ -729,34 +752,6 @@ break; } - case ARM::MOVi2pieces: { - unsigned PredReg = 0; - ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); - unsigned DstReg = MI.getOperand(0).getReg(); - bool DstIsDead = MI.getOperand(0).isDead(); - const MachineOperand &MO = MI.getOperand(1); - MachineInstrBuilder LO16, HI16; - - LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); - HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) - .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) - .addReg(DstReg); - - assert (MO.isImm() && "MOVi2pieces w/ non-immediate source operand!"); - unsigned ImmVal = (unsigned)MO.getImm(); - unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); - unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); - LO16 = LO16.addImm(SOImmValV1); - HI16 = HI16.addImm(SOImmValV2); - (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); - (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); - LO16.addImm(Pred).addReg(PredReg).addReg(0); - HI16.addImm(Pred).addReg(PredReg).addReg(0); - TransferImpOps(MI, LO16, HI16); - MI.eraseFromParent(); - break; - } - case ARM::VMOVQQ: { unsigned DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); @@ -1060,6 +1055,7 @@ bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { TII = static_cast(MF.getTarget().getInstrInfo()); TRI = MF.getTarget().getRegisterInfo(); + STI = &MF.getTarget().getSubtarget(); bool Modified = false; for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=118938&r1=118937&r2=118938&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Nov 12 17:03:38 2010 @@ -59,27 +59,3 @@ return 0; } - -void ARMInstrInfo:: -reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, - const TargetRegisterInfo &TRI) const { - DebugLoc dl = Orig->getDebugLoc(); - unsigned Opcode = Orig->getOpcode(); - switch (Opcode) { - default: - break; - case ARM::MOVi2pieces: { - RI.emitLoadConstPool(MBB, I, dl, - DestReg, SubIdx, - Orig->getOperand(1).getImm(), - ARMCC::AL, 0); // Pre-if-conversion, so default pred. - MachineInstr *NewMI = prior(I); - NewMI->getOperand(0).setSubReg(SubIdx); - return; - } - } - - return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI); -} - Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=118938&r1=118937&r2=118938&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Fri Nov 12 17:03:38 2010 @@ -32,11 +32,6 @@ // if there is not such an opcode. unsigned getUnindexedOpcode(unsigned Opc) const; - void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SubIdx, - const MachineInstr *Orig, - const TargetRegisterInfo &TRI) const; - /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118938&r1=118937&r2=118938&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 17:03:38 2010 @@ -3201,14 +3201,9 @@ // Large immediate handling. -// Two piece so_imms. -// FIXME: Remove this when we can do generalized remat. -let isReMaterializable = 1 in -def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src), - IIC_iMOVix2, "", - [(set GPR:$dst, (so_imm2part:$src))]>, - Requires<[IsARM, NoV6T2]>; - +// FIXME: Folding immediates into these logical operations aren't necessary +// good ideas. If it's in a loop machine licm could have hoisted the immediate +// computation out of the loop. def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), (so_imm2part_2 imm:$RHS))>; @@ -3222,14 +3217,14 @@ (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)), (so_neg_imm2part_2 imm:$RHS))>; -// 32-bit immediate using movw + movt. +// 32-bit immediate using two piece so_imms or movw + movt. // This is a single pseudo instruction, the benefit is that it can be remat'd // as a single unit instead of having to handle reg inputs. // FIXME: Remove this when we can do generalized remat. let isReMaterializable = 1 in def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "", [(set GPR:$dst, (i32 imm:$src))]>, - Requires<[IsARM, HasV6T2]>; + Requires<[IsARM]>; // ConstantPool, GlobalAddress, and JumpTable def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, From resistor at mac.com Fri Nov 12 17:18:12 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 12 Nov 2010 23:18:12 -0000 Subject: [llvm-commits] [llvm] r118939 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20101112231812.2B8CA2A6C12C@llvm.org> Author: resistor Date: Fri Nov 12 17:18:11 2010 New Revision: 118939 URL: http://llvm.org/viewvc/llvm-project?rev=118939&view=rev Log: Attemt to provide correct encodings for Thumb2 binary operators. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118939&r1=118938&r2=118939&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Nov 12 17:18:11 2010 @@ -170,7 +170,7 @@ // Multiclass helpers... // -class T2TwoRegShiftedImm pattern> : T2sI { bits<4> Rd; @@ -262,9 +262,10 @@ InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, PatFrag opnode, bit Commutable = 0, string wide = ""> { // shifted imm - def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii, - opc, "\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> { + def ri : T2TwoRegImm< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, + opc, "\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -272,9 +273,10 @@ let Inst{15} = 0; } // register - def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir, - opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), - [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { + def rr : T2ThreeReg< + (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, + opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), + [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -285,9 +287,10 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis, - opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> { + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, + opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), + [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -307,9 +310,10 @@ /// it is equivalent to the T2I_bin_irs counterpart. multiclass T2I_rbin_irs opcod, string opc, PatFrag opnode> { // shifted imm - def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, - opc, ".w\t$dst, $rhs, $lhs", - [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { + def ri : T2TwoRegImm< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, + opc, ".w\t$Rd, $imm, $Rn", + [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -317,8 +321,8 @@ let Inst{15} = 0; } // register - def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, - opc, "\t$dst, $rhs, $lhs", + def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, + opc, "\t$Rd, $Rm, $Rn", [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -329,9 +333,10 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsir, - opc, "\t$dst, $rhs, $lhs", - [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), + IIC_iALUsir, opc, "\t$Rd, $ShiftedRm, $Rn", + [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -346,9 +351,9 @@ InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii, - !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { + def ri : T2TwoRegImm<(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, + !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -356,9 +361,9 @@ let Inst{15} = 0; } // register - def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir, - !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { + def rr : T2ThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, + !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm", + [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -369,9 +374,10 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis, - !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, + !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm", + [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -388,9 +394,10 @@ // The register-immediate version is re-materializable. This is useful // in particular for taking the address of a local. let isReMaterializable = 1 in { - def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { + def ri : T2TwoRegImm< + (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi, + opc, ".w\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24} = 1; @@ -400,9 +407,10 @@ } } // 12-bit imm - def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, - !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> { + def ri12 : T2TwoRegImm< + (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, + !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24} = 0; @@ -411,9 +419,9 @@ let Inst{15} = 0; } // register - def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { + def rr : T2ThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr, + opc, ".w\t$Rd, $Rn, $Rm", + [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -425,9 +433,10 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, - opc, ".w\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), + IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", + [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24} = 1; @@ -443,7 +452,7 @@ multiclass T2I_adde_sube_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2TwoRegShiftedImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), + def ri : T2TwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, opc, "\t$Rd, $Rn, $imm", [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, Requires<[IsThumb2]> { @@ -485,7 +494,7 @@ multiclass T2I_adde_sube_s_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2TwoRegShiftedImm< + def ri : T2TwoRegImm< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, opc, "\t$Rd, $Rn, $imm", [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, @@ -530,9 +539,10 @@ let Defs = [CPSR] in { multiclass T2I_rbin_s_is opcod, string opc, PatFrag opnode> { // shifted imm - def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, - !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs", - [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { + def ri : T2TwoRegImm< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, + !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", + [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -540,9 +550,10 @@ let Inst{15} = 0; } // shifted register - def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, - !strconcat(opc, "s"), "\t$dst, $rhs, $lhs", - [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { + def rs : T2TwoRegShiftedReg< + (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), + IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm", + [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -874,17 +885,19 @@ } // ADD r, sp, {so_imm|i12} -def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), - IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> { +def t2ADDrSPi : T2TwoRegImm< + (outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), + IIC_iALUi, "add", ".w\t$Rn, $Rn, $imm", []> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = 0b1000; let Inst{20} = ?; // The S bit. - let Inst{19-16} = 0b1101; // Rn = sp + let Inst{19-16} = 0b1101; let Inst{15} = 0; } -def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), - IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> { +def t2ADDrSPi12 : T2TwoRegImm< + (outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), + IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-21} = 0b0000; From dpatel at apple.com Fri Nov 12 17:20:42 2010 From: dpatel at apple.com (Devang Patel) Date: Fri, 12 Nov 2010 23:20:42 -0000 Subject: [llvm-commits] [llvm] r118940 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h Message-ID: <20101112232042.683922A6C12C@llvm.org> Author: dpatel Date: Fri Nov 12 17:20:42 2010 New Revision: 118940 URL: http://llvm.org/viewvc/llvm-project?rev=118940&view=rev Log: Remove DW_AT_start_scope support. It is incomplete and superseeded by location entries support. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=118940&r1=118939&r2=118940&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Nov 12 17:20:42 2010 @@ -854,35 +854,28 @@ } /// addRegisterAddress - Add register location entry in variable DIE. -bool DwarfDebug::addRegisterAddress(DIE *Die, const MCSymbol *VS, - const MachineOperand &MO) { +bool DwarfDebug::addRegisterAddress(DIE *Die, const MachineOperand &MO) { assert (MO.isReg() && "Invalid machine operand!"); if (!MO.getReg()) return false; MachineLocation Location; Location.set(MO.getReg()); addAddress(Die, dwarf::DW_AT_location, Location); - if (VS) - addLabel(Die, dwarf::DW_AT_start_scope, dwarf::DW_FORM_addr, VS); return true; } /// addConstantValue - Add constant value entry in variable DIE. -bool DwarfDebug::addConstantValue(DIE *Die, const MCSymbol *VS, - const MachineOperand &MO) { +bool DwarfDebug::addConstantValue(DIE *Die, const MachineOperand &MO) { assert (MO.isImm() && "Invalid machine operand!"); DIEBlock *Block = new (DIEValueAllocator) DIEBlock(); unsigned Imm = MO.getImm(); addUInt(Block, 0, dwarf::DW_FORM_udata, Imm); addBlock(Die, dwarf::DW_AT_const_value, 0, Block); - if (VS) - addLabel(Die, dwarf::DW_AT_start_scope, dwarf::DW_FORM_addr, VS); return true; } /// addConstantFPValue - Add constant value entry in variable DIE. -bool DwarfDebug::addConstantFPValue(DIE *Die, const MCSymbol *VS, - const MachineOperand &MO) { +bool DwarfDebug::addConstantFPValue(DIE *Die, const MachineOperand &MO) { assert (MO.isFPImm() && "Invalid machine operand!"); DIEBlock *Block = new (DIEValueAllocator) DIEBlock(); APFloat FPImm = MO.getFPImm()->getValueAPF(); @@ -903,8 +896,6 @@ (unsigned char)0xFF & FltPtr[Start]); addBlock(Die, dwarf::DW_AT_const_value, 0, Block); - if (VS) - addLabel(Die, dwarf::DW_AT_start_scope, dwarf::DW_FORM_addr, VS); return true; } @@ -1664,7 +1655,6 @@ DbgVariableToDbgInstMap.find(DV); if (DVI != DbgVariableToDbgInstMap.end()) { const MachineInstr *DVInsn = DVI->second; - const MCSymbol *DVLabel = findVariableLabel(DV); bool updated = false; // FIXME : Handle getNumOperands != 3 if (DVInsn->getNumOperands() == 3) { @@ -1676,20 +1666,17 @@ addVariableAddress(DV, VariableDie, DVInsn->getOperand(1).getImm()); updated = true; } else - updated = addRegisterAddress(VariableDie, DVLabel, RegOp); + updated = addRegisterAddress(VariableDie, RegOp); } else if (DVInsn->getOperand(0).isImm()) - updated = addConstantValue(VariableDie, DVLabel, DVInsn->getOperand(0)); + updated = addConstantValue(VariableDie, DVInsn->getOperand(0)); else if (DVInsn->getOperand(0).isFPImm()) updated = - addConstantFPValue(VariableDie, DVLabel, DVInsn->getOperand(0)); + addConstantFPValue(VariableDie, DVInsn->getOperand(0)); } else { MachineLocation Location = Asm->getDebugValueLocation(DVInsn); if (Location.getReg()) { addAddress(VariableDie, dwarf::DW_AT_location, Location); - if (DVLabel) - addLabel(VariableDie, dwarf::DW_AT_start_scope, dwarf::DW_FORM_addr, - DVLabel); updated = true; } } @@ -2363,8 +2350,6 @@ Processed.insert(DV); DbgVariable *RegVar = new DbgVariable(DV); Scope->addVariable(RegVar); - if (!CurFnArg) - DbgVariableLabelsMap[RegVar] = getLabelBeforeInsn(MInsn); if (DbgVariable *AbsVar = findAbstractVariable(DV, MInsn->getDebugLoc())) { DbgVariableToDbgInstMap[AbsVar] = MInsn; VarToAbstractVarMap[RegVar] = AbsVar; @@ -2941,7 +2926,6 @@ DbgVariableToFrameIndexMap.clear(); VarToAbstractVarMap.clear(); DbgVariableToDbgInstMap.clear(); - DbgVariableLabelsMap.clear(); DeleteContainerSeconds(DbgScopeMap); InsnsEndScopeSet.clear(); ConcreteScopes.clear(); @@ -2972,15 +2956,6 @@ return true; } -/// findVariableLabel - Find MCSymbol for the variable. -const MCSymbol *DwarfDebug::findVariableLabel(const DbgVariable *V) { - DenseMap::iterator I - = DbgVariableLabelsMap.find(V); - if (I == DbgVariableLabelsMap.end()) - return NULL; - else return I->second; -} - /// findDbgScope - Find DbgScope for the debug loc attached with an /// instruction. DbgScope *DwarfDebug::findDbgScope(const MachineInstr *MInsn) { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=118940&r1=118939&r2=118940&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Fri Nov 12 17:20:42 2010 @@ -176,9 +176,6 @@ /// machine instruction. DenseMap DbgVariableToDbgInstMap; - /// DbgVariableLabelsMap - Maps DbgVariable to corresponding MCSymbol. - DenseMap DbgVariableLabelsMap; - /// DotDebugLocEntry - This struct describes location entries emitted in /// .debug_loc section. typedef struct DotDebugLocEntry { @@ -350,13 +347,13 @@ const MachineLocation &Location); /// addRegisterAddress - Add register location entry in variable DIE. - bool addRegisterAddress(DIE *Die, const MCSymbol *VS, const MachineOperand &MO); + bool addRegisterAddress(DIE *Die, const MachineOperand &MO); /// addConstantValue - Add constant value entry in variable DIE. - bool addConstantValue(DIE *Die, const MCSymbol *VS, const MachineOperand &MO); + bool addConstantValue(DIE *Die, const MachineOperand &MO); /// addConstantFPValue - Add constant value entry in variable DIE. - bool addConstantFPValue(DIE *Die, const MCSymbol *VS, const MachineOperand &MO); + bool addConstantFPValue(DIE *Die, const MachineOperand &MO); /// addComplexAddress - Start with the address based on the location provided, /// and generate the DWARF information necessary to find the actual variable @@ -579,9 +576,6 @@ /// is found. Update FI to hold value of the index. bool findVariableFrameIndex(const DbgVariable *V, int *FI); - /// findVariableLabel - Find MCSymbol for the variable. - const MCSymbol *findVariableLabel(const DbgVariable *V); - /// findDbgScope - Find DbgScope for the debug loc attached with an /// instruction. DbgScope *findDbgScope(const MachineInstr *MI); From peckw at wesleypeck.com Fri Nov 12 17:30:18 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Fri, 12 Nov 2010 23:30:18 -0000 Subject: [llvm-commits] [llvm] r118941 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/InstPrinter/ test/MC/MBlaze/ Message-ID: <20101112233018.3E82B2A6C12C@llvm.org> Author: peckw Date: Fri Nov 12 17:30:17 2010 New Revision: 118941 URL: http://llvm.org/viewvc/llvm-project?rev=118941&view=rev Log: 1. Finishing MBlaze MC asm parser test cases 2. Parsing .word directive in MBlaze asm parser 3. Fixing hack where memory instructions reversed order of last two parameters 4. Fixing many improperly encoded instructions 5. Support parsing special instructions (MFS,MTS,etc.) 6. Removing unused functions from inst printer Added: llvm/trunk/test/MC/MBlaze/mblaze_branch.s llvm/trunk/test/MC/MBlaze/mblaze_fpu.s llvm/trunk/test/MC/MBlaze/mblaze_memory.s llvm/trunk/test/MC/MBlaze/mblaze_pattern.s llvm/trunk/test/MC/MBlaze/mblaze_shift.s llvm/trunk/test/MC/MBlaze/mblaze_special.s Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/test/MC/MBlaze/mblaze_fsl.s llvm/trunk/test/MC/MBlaze/mblaze_typea.s Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Nov 12 17:30:17 2010 @@ -30,7 +30,7 @@ set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget) +set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport LLVMSystem) set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport) Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Fri Nov 12 17:30:17 2010 @@ -9,6 +9,7 @@ #include "MBlaze.h" #include "MBlazeSubtarget.h" +#include "MBlazeRegisterInfo.h" #include "MBlazeISelLowering.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" @@ -45,6 +46,8 @@ MBlazeOperand *ParseFsl(); MBlazeOperand* ParseOperand(SmallVectorImpl &Operands); + bool ParseDirectiveWord(unsigned Size, SMLoc L); + bool MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, MCStreamer &Out); @@ -201,13 +204,13 @@ void addMemOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateReg(getMemBase())); + unsigned RegOff = getMemOffReg(); if (RegOff) Inst.addOperand(MCOperand::CreateReg(RegOff)); else addExpr(Inst, getMemOff()); - - Inst.addOperand(MCOperand::CreateReg(getMemBase())); } StringRef getToken() const { @@ -281,13 +284,24 @@ getImm()->print(OS); break; case Register: - OS << ""; + OS << ""; break; case Token: OS << "'" << getToken() << "'"; break; - case Memory: - OS << "MEMORY"; + case Memory: { + OS << ""; + } break; case Fsl: getFslImm()->print(OS); @@ -381,6 +395,7 @@ if (RegNo == 0) return 0; + getLexer().Lex(); return MBlazeOperand::CreateReg(RegNo, S, E); } } @@ -407,6 +422,7 @@ if (reg >= 16) return 0; + getLexer().Lex(); const MCExpr *EVal = MCConstantExpr::Create(reg,getContext()); return MBlazeOperand::CreateFslImm(EVal,S,E); } @@ -452,9 +468,6 @@ return 0; } - // Move past the parsed token in the token stream - getLexer().Lex(); - // Push the parsed operand into the list of operands Operands.push_back(Op); return Op; @@ -464,8 +477,11 @@ bool MBlazeAsmParser:: ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) { - // The first operand is the token for the instruction name - Operands.push_back(MBlazeOperand::CreateToken(Name, NameLoc)); + // The first operands is the token for the instruction name + size_t dotLoc = Name.find('.'); + Operands.push_back(MBlazeOperand::CreateToken(Name.substr(0,dotLoc),NameLoc)); + if (dotLoc < Name.size()) + Operands.push_back(MBlazeOperand::CreateToken(Name.substr(dotLoc),NameLoc)); // If there are no more operands then finish if (getLexer().is(AsmToken::EndOfStatement)) @@ -477,10 +493,6 @@ while (getLexer().isNot(AsmToken::EndOfStatement) && getLexer().is(AsmToken::Comma)) { - // Make sure there is a comma separating operands - // if (getLexer().isNot(AsmToken::Comma)) - // return false; - // Consume the comma token getLexer().Lex(); @@ -495,16 +507,44 @@ if (Name.startswith("lw") || Name.startswith("sw") || Name.startswith("lh") || Name.startswith("sh") || Name.startswith("lb") || Name.startswith("sb")) - return ParseMemory(Operands); + return (ParseMemory(Operands) == NULL); return false; } /// ParseDirective parses the arm specific directives bool MBlazeAsmParser::ParseDirective(AsmToken DirectiveID) { + StringRef IDVal = DirectiveID.getIdentifier(); + if (IDVal == ".word") + return ParseDirectiveWord(2, DirectiveID.getLoc()); return true; } +/// ParseDirectiveWord +/// ::= .word [ expression (, expression)* ] +bool MBlazeAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { + if (getLexer().isNot(AsmToken::EndOfStatement)) { + for (;;) { + const MCExpr *Value; + if (getParser().ParseExpression(Value)) + return true; + + getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/); + + if (getLexer().is(AsmToken::EndOfStatement)) + break; + + // FIXME: Improve diagnostic. + if (getLexer().isNot(AsmToken::Comma)) + return Error(L, "unexpected token in directive"); + Parser.Lex(); + } + } + + Parser.Lex(); + return false; +} + extern "C" void LLVMInitializeMBlazeAsmLexer(); /// Force static initialization. Modified: llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.cpp Fri Nov 12 17:30:17 2010 @@ -29,17 +29,6 @@ printInstruction(MI, O); } -void MBlazeInstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) - O << Op.getImm(); - else { - assert(Op.isExpr() && "unknown pcrel immediate operand"); - O << *Op.getExpr(); - } -} - void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier) { assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); @@ -54,35 +43,6 @@ } } -void MBlazeInstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, - const char *Modifier) { - const MCOperand &Base = MI->getOperand(OpNo); - const MCOperand &Disp = MI->getOperand(OpNo+1); - - // Print displacement first - - // If the global address expression is a part of displacement field with a - // register base, we should not emit any prefix symbol here, e.g. - // mov.w &foo, r1 - // vs - // mov.w glb(r1), r2 - // Otherwise (!) msp430-as will silently miscompile the output :( - if (!Base.getReg()) - O << '&'; - - if (Disp.isExpr()) - O << *Disp.getExpr(); - else { - assert(Disp.isImm() && "Expected immediate in displacement field"); - O << Disp.getImm(); - } - - // Print register base field - if (Base.getReg()) - O << getRegisterName(Base.getReg()); -} - void MBlazeInstPrinter::printFSLImm(const MCInst *MI, int OpNo, raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNo); @@ -103,38 +63,7 @@ void MBlazeInstPrinter::printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O, const char *Modifier) { - printOperand(MI, OpNo+1, O, NULL); - O << ", "; printOperand(MI, OpNo, O, NULL); + O << ", "; + printOperand(MI, OpNo+1, O, NULL); } - -/* -void MBlazeInstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - unsigned CC = MI->getOperand(OpNo).getImm(); - - switch (CC) { - default: - llvm_unreachable("Unsupported CC code"); - break; - case MBlazeCC::COND_E: - O << "eq"; - break; - case MBlazeCC::COND_NE: - O << "ne"; - break; - case MBlazeCC::COND_HS: - O << "hs"; - break; - case MBlazeCC::COND_LO: - O << "lo"; - break; - case MBlazeCC::COND_GE: - O << "ge"; - break; - case MBlazeCC::COND_L: - O << 'l'; - break; - } -} -*/ Modified: llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h (original) +++ llvm/trunk/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h Fri Nov 12 17:30:17 2010 @@ -33,9 +33,6 @@ void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = 0); void printFSLImm(const MCInst *MI, int OpNo, raw_ostream &O); void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O); void printMemOperand(const MCInst *MI, int OpNo,raw_ostream &O, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Fri Nov 12 17:30:17 2010 @@ -205,9 +205,9 @@ void MBlazeAsmPrinter:: printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier) { - printOperand(MI, opNum+1, O); - O << ", "; printOperand(MI, opNum, O); + O << ", "; + printOperand(MI, opNum+1, O); } static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Fri Nov 12 17:30:17 2010 @@ -133,8 +133,8 @@ N.getOperand(1).getOpcode() == ISD::TargetJumpTable) return false; // jump tables. - Base = N.getOperand(1); - Index = N.getOperand(0); + Base = N.getOperand(0); + Index = N.getOperand(1); return true; } @@ -145,9 +145,9 @@ /// a signed 32-bit displacement [r+imm], and if it is not better /// represented as reg+reg. bool MBlazeDAGToDAGISel:: -SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base) { +SelectAddrRegImm(SDValue N, SDValue &Base, SDValue &Disp) { // If this can be more profitably realized as r+r, fail. - if (SelectAddrRegReg(N, Disp, Base)) + if (SelectAddrRegReg(N, Base, Disp)) return false; if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFPU.td Fri Nov 12 17:30:17 2010 @@ -52,9 +52,9 @@ class ArithFR op, bits<11> flags, string instr_asm, SDNode OpNode, InstrItinClass itin> : - TA; + TAR; class LogicF op, string instr_asm> : TB; def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>; def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>; +} +let Predicates=[HasFPU], isCodeGenOnly=1 in { def LWF : LoadFM<0x32, "lw ", load>; - def LWFI : LoadFMI<0x32, "lwi ", load>; + def LWFI : LoadFMI<0x3A, "lwi ", load>; - def SWF : StoreFM<0x32, "sw ", store>; - def SWFI : StoreFMI<0x32, "swi ", store>; + def SWF : StoreFM<0x36, "sw ", store>; + def SWFI : StoreFMI<0x3E, "swi ", store>; } let Predicates=[HasFPU,HasSqrt] in { def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>; def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>; - def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>; + def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIAlu>; } let isAsCheapAsAMove = 1 in { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td Fri Nov 12 17:30:17 2010 @@ -15,8 +15,8 @@ } def FPseudo : Format<0>; -def FRRR : Format<1>; // ADD, RSUB, OR, etc. -def FRRI : Format<2>; // ADDI, RSUBI, ORI, etc. +def FRRR : Format<1>; // ADD, OR, etc. +def FRRI : Format<2>; // ADDI, ORI, etc. def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc. def FCRI : Format<4>; // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc. def FRCR : Format<5>; // BRLD, BRALD, GETD @@ -32,7 +32,9 @@ def FCX : Format<15>; // TPUT def FCR : Format<16>; // TPUTD def FRIR : Format<17>; // RSUBI -def FC : Format<18>; // NOP +def FRRRR : Format<18>; // RSUB, FRSUB +def FRI : Format<19>; // RSUB, FRSUB +def FC : Format<20>; // NOP //===----------------------------------------------------------------------===// // Describe MBlaze instructions format @@ -48,7 +50,7 @@ //===----------------------------------------------------------------------===// // Generic MBlaze Format -class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, +class MBlazeInst op, Format form, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin> : Instruction { let Namespace = "MBlaze"; field bits<32> Inst; @@ -63,7 +65,7 @@ // If the instruction is marked as a pseudo, set isCodeGenOnly so that the // assembler and disassmbler ignore it. let isCodeGenOnly = !eq(!cast(form), "FPseudo"); - + dag OutOperandList = outs; dag InOperandList = ins; @@ -117,6 +119,27 @@ } //===----------------------------------------------------------------------===// +// Type A instruction class in MBlaze but with the operands reversed +// in the LLVM DAG : <|opcode|rd|ra|rb|flags|> +//===----------------------------------------------------------------------===// + +class TAR op, bits<11> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst +{ + bits<5> rd; + bits<5> rb; + bits<5> ra; + + let Form = FRRRR; + + let Inst{6-10} = rd; + let Inst{11-15} = ra; + let Inst{16-20} = rb; + let Inst{21-31} = flags; +} + +//===----------------------------------------------------------------------===// // Type B instruction class in MBlaze but with the operands reversed in // the LLVM DAG : <|opcode|rd|ra|immediate|> //===----------------------------------------------------------------------===// @@ -133,3 +156,50 @@ let ra = rra; let imm16 = rimm16; } + +//===----------------------------------------------------------------------===// +// Shift immediate instruction class in MBlaze : <|opcode|rd|ra|immediate|> +//===----------------------------------------------------------------------===// +class SHT op, bits<2> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<5> ra; + bits<5> imm5; + + let Inst{6-10} = rd; + let Inst{11-15} = ra; + let Inst{16-20} = 0x0; + let Inst{21-22} = flags; + let Inst{23-26} = 0x0; + let Inst{27-31} = imm5; +} + +//===----------------------------------------------------------------------===// +// Special instruction class in MBlaze : <|opcode|rd|imm14|> +//===----------------------------------------------------------------------===// +class SPC op, bits<2> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<14> imm14; + + let Inst{6-10} = rd; + let Inst{11-15} = 0x0; + let Inst{16-17} = flags; + let Inst{18-31} = imm14; +} + +//===----------------------------------------------------------------------===// +// MSR instruction class in MBlaze : <|opcode|rd|imm15|> +//===----------------------------------------------------------------------===// +class MSR op, bits<6> flags, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin> : + MBlazeInst { + bits<5> rd; + bits<15> imm15; + + let Inst{6-10} = rd; + let Inst{11-16} = flags; + let Inst{17-31} = imm15; +} Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Fri Nov 12 17:30:17 2010 @@ -38,10 +38,10 @@ unsigned MBlazeInstrInfo:: isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == MBlaze::LWI) { - if ((MI->getOperand(2).isFI()) && // is a stack slot - (MI->getOperand(1).isImm()) && // the imm is zero - (isZeroImm(MI->getOperand(1)))) { - FrameIndex = MI->getOperand(2).getIndex(); + if ((MI->getOperand(1).isFI()) && // is a stack slot + (MI->getOperand(2).isImm()) && // the imm is zero + (isZeroImm(MI->getOperand(2)))) { + FrameIndex = MI->getOperand(1).getIndex(); return MI->getOperand(0).getReg(); } } @@ -57,10 +57,10 @@ unsigned MBlazeInstrInfo:: isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == MBlaze::SWI) { - if ((MI->getOperand(2).isFI()) && // is a stack slot - (MI->getOperand(1).isImm()) && // the imm is zero - (isZeroImm(MI->getOperand(1)))) { - FrameIndex = MI->getOperand(2).getIndex(); + if ((MI->getOperand(1).isFI()) && // is a stack slot + (MI->getOperand(2).isImm()) && // the imm is zero + (isZeroImm(MI->getOperand(2)))) { + FrameIndex = MI->getOperand(1).getIndex(); return MI->getOperand(0).getReg(); } } @@ -91,7 +91,7 @@ const TargetRegisterInfo *TRI) const { DebugLoc DL; BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI); } void MBlazeInstrInfo:: @@ -101,7 +101,7 @@ const TargetRegisterInfo *TRI) const { DebugLoc DL; BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg) - .addImm(0).addFrameIndex(FI); + .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI); } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Fri Nov 12 17:30:17 2010 @@ -156,6 +156,8 @@ FCX, FCR, FRIR, + FRRRR, + FRI, FC, FormMask = 63 Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Fri Nov 12 17:30:17 2010 @@ -79,6 +79,8 @@ def calltarget : Operand; def simm16 : Operand; def uimm5 : Operand; +def uimm14 : Operand; +def uimm15 : Operand; def fimm : Operand; // Unsigned Operand @@ -95,7 +97,7 @@ // Address operand def memri : Operand { let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops simm16, GPR); + let MIOperandInfo = (ops GPR, simm16); let ParserMatchClass = MBlazeMemAsmOperand; } @@ -167,9 +169,15 @@ !strconcat(instr_asm, " $dst, $b, $c"), [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>; +class ShiftI op, bits<2> flags, string instr_asm, SDNode OpNode, + Operand Od, PatLeaf imm_type> : + SHT; + class ArithR op, bits<11> flags, string instr_asm, SDNode OpNode, InstrItinClass itin> : - TA; @@ -192,14 +200,14 @@ class ArithRN op, bits<11> flags, string instr_asm, InstrItinClass itin> : - TA; + TAR; class ArithRNI op, string instr_asm,Operand Od, PatLeaf imm_type> : - TB; + TBR; //===----------------------------------------------------------------------===// // Misc Arithmetic Instructions @@ -224,35 +232,25 @@ //===----------------------------------------------------------------------===// // Memory Access Instructions //===----------------------------------------------------------------------===// -class LoadM op, string instr_asm, PatFrag OpNode> : - TA; - -class LoadW op, bits<11> flags, string instr_asm> : +class LoadM op, bits<11> flags, string instr_asm> : TA; class LoadMI op, string instr_asm, PatFrag OpNode> : - TBR; - -class StoreM op, string instr_asm, PatFrag OpNode> : - TA; + [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>; -class StoreW op, bits<11> flags, string instr_asm> : +class StoreM op, bits<11> flags, string instr_asm> : TA; class StoreMI op, string instr_asm, PatFrag OpNode> : - TBR; + TB; //===----------------------------------------------------------------------===// // Branch Instructions @@ -358,9 +356,9 @@ def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>; def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>; def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>; - def BSRLI : ArithI<0x11, "bsrli ", srl, uimm5, immZExt5>; - def BSRAI : ArithI<0x11, "bsrai ", sra, uimm5, immZExt5>; - def BSLLI : ArithI<0x11, "bslli ", shl, uimm5, immZExt5>; + def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>; + def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>; + def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>; } let Predicates=[HasDiv] in { @@ -396,24 +394,30 @@ //===----------------------------------------------------------------------===// let canFoldAsLoad = 1, isReMaterializable = 1 in { - def LBU : LoadM<0x30, "lbu ", zextloadi8>; - def LHU : LoadM<0x31, "lhu ", zextloadi16>; + def LBU : LoadM<0x30, 0x000, "lbu ">; + def LBUR : LoadM<0x30, 0x200, "lbur ">; - def LW : LoadW<0x32, 0x0, "lw ">; - def LWR : LoadW<0x32, 0x2, "lwr ">; - def LWX : LoadW<0x32, 0x4, "lwx ">; + def LHU : LoadM<0x31, 0x000, "lhu ">; + def LHUR : LoadM<0x31, 0x200, "lhur ">; + + def LW : LoadM<0x32, 0x000, "lw ">; + def LWR : LoadM<0x32, 0x200, "lwr ">; + def LWX : LoadM<0x32, 0x400, "lwx ">; def LBUI : LoadMI<0x38, "lbui ", zextloadi8>; def LHUI : LoadMI<0x39, "lhui ", zextloadi16>; def LWI : LoadMI<0x3A, "lwi ", load>; } - def SB : StoreM<0x34, "sb ", truncstorei8>; - def SH : StoreM<0x35, "sh ", truncstorei16>; + def SB : StoreM<0x34, 0x000, "sb ">; + def SBR : StoreM<0x34, 0x200, "sbr ">; + + def SH : StoreM<0x35, 0x000, "sh ">; + def SHR : StoreM<0x35, 0x200, "shr ">; - def SW : StoreW<0x36, 0x0, "sw ">; - def SWR : StoreW<0x36, 0x2, "swr ">; - def SWX : StoreW<0x36, 0x4, "swx ">; + def SW : StoreM<0x36, 0x000, "sw ">; + def SWR : StoreM<0x36, 0x200, "swr ">; + def SWX : StoreM<0x36, 0x400, "swx ">; def SBI : StoreMI<0x3C, "sbi ", truncstorei8>; def SHI : StoreMI<0x3D, "shi ", truncstorei16>; @@ -583,17 +587,17 @@ //===----------------------------------------------------------------------===// // Misc. instructions //===----------------------------------------------------------------------===// -def MFS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mfs", [], IIAlu> { -} +def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins uimm14:$rg), + "mfs $dst, $rg", [], IIAlu>; -def MTS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mts", [], IIAlu> { -} +def MTS : SPC<0x25, 0x3, (outs), (ins uimm14:$dst, GPR:$rg), + "mts $dst, $rg", [], IIAlu>; -def MSRSET : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrset", [], IIAlu> { -} +def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set), + "msrset $dst, $set", [], IIAlu>; -def MSRCLR : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrclr", [], IIAlu> { -} +def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr), + "msrclr $dst, $clr", [], IIAlu>; let rd=0x0, Form=FCRR in { def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), @@ -765,6 +769,14 @@ def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>; def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>; +// 16-bit load and store +def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>; +def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>; + +// 8-bit load and store +def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>; +def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>; + // Peepholes def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Fri Nov 12 17:30:17 2010 @@ -1,5 +1,5 @@ //===- MBlazeRegisterInfo.cpp - MBlaze Register Information -== -*- C++ -*-===// -// +//DJ // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source @@ -308,7 +308,7 @@ // swi R15, R1, stack_loc if (MFI->adjustsStack()) { BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI)) - .addReg(MBlaze::R15).addImm(RAOffset).addReg(MBlaze::R1); + .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset); } // if framepointer enabled, save it and set it @@ -316,7 +316,7 @@ if (hasFP(MF)) { // swi R19, R1, stack_loc BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI)) - .addReg(MBlaze::R19).addImm(FPOffset).addReg(MBlaze::R1); + .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset); // add R19, R1, R0 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19) @@ -344,14 +344,14 @@ // lwi R19, R1, stack_loc BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19) - .addImm(FPOffset).addReg(MBlaze::R1); + .addReg(MBlaze::R1).addImm(FPOffset); } // Restore the return address only if the function isnt a leaf one. // lwi R15, R1, stack_loc if (MFI->adjustsStack()) { BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15) - .addImm(RAOffset).addReg(MBlaze::R1); + .addReg(MBlaze::R1).addImm(RAOffset); } // Get the number of bytes from FrameInfo Added: llvm/trunk/test/MC/MBlaze/mblaze_branch.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_branch.s?rev=118941&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_branch.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_branch.s Fri Nov 12 17:30:17 2010 @@ -0,0 +1,197 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to make sure that all of the TYPE-A instructions supported by +# the Microblaze can be parsed by the assembly parser. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 000000 00000 00000 00000 00000000000 + +# CHECK: beq +# BINARY: 100111 00000 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x02,0x18,0x00] + beq r2, r3 + +# CHECK: bge +# BINARY: 100111 00101 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0xa2,0x18,0x00] + bge r2, r3 + +# CHECK: bgt +# BINARY: 100111 00100 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x82,0x18,0x00] + bgt r2, r3 + +# CHECK: ble +# BINARY: 100111 00011 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x62,0x18,0x00] + ble r2, r3 + +# CHECK: blt +# BINARY: 100111 00010 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x42,0x18,0x00] + blt r2, r3 + +# CHECK: bne +# BINARY: 100111 00001 00010 00011 00000000000 +# CHECK: encoding: [0x9c,0x22,0x18,0x00] + bne r2, r3 + +# CHECK: beqd +# BINARY: 100111 10000 00010 00011 00000000000 +# CHECK: encoding: [0x9e,0x02,0x18,0x00] + beqd r2, r3 + +# CHECK: bged +# BINARY: 100111 10101 00010 00011 00000000000 +# CHECK: encoding: [0x9e,0xa2,0x18,0x00] + bged r2, r3 + +# CHECK: bgtd +# BINARY: 100111 10100 00010 00011 00000000000 +# CHECK: encoding: [0x9e,0x82,0x18,0x00] + bgtd r2, r3 + +# CHECK: bled +# BINARY: 100111 10011 00010 00011 00000000000 +# CHECK: encoding: [0x9e,0x62,0x18,0x00] + bled r2, r3 + +# CHECK: bltd +# BINARY: 100111 10010 00010 00011 00000000000 +# CHECK: encoding: [0x9e,0x42,0x18,0x00] + bltd r2, r3 + +# CHECK: bned +# BINARY: 100111 10001 00010 00011 00000000000 +# CHECK: encoding: [0x9e,0x22,0x18,0x00] + bned r2, r3 + +# CHECK: br +# BINARY: 100110 00000 00000 00011 00000000000 +# CHECK: encoding: [0x98,0x00,0x18,0x00] + br r3 + +# CHECK: bra +# BINARY: 100110 00000 01000 00011 00000000000 +# CHECK: encoding: [0x98,0x08,0x18,0x00] + bra r3 + +# CHECK: brd +# BINARY: 100110 00000 10000 00011 00000000000 +# CHECK: encoding: [0x98,0x10,0x18,0x00] + brd r3 + +# CHECK: brad +# BINARY: 100110 00000 11000 00011 00000000000 +# CHECK: encoding: [0x98,0x18,0x18,0x00] + brad r3 + +# CHECK: brld +# BINARY: 100110 01111 10100 00011 00000000000 +# CHECK: encoding: [0x99,0xf4,0x18,0x00] + brld r15, r3 + +# CHECK: brald +# BINARY: 100110 01111 11100 00011 00000000000 +# CHECK: encoding: [0x99,0xfc,0x18,0x00] + brald r15, r3 + +# CHECK: brk +# BINARY: 100110 01111 01100 00011 00000000000 +# CHECK: encoding: [0x99,0xec,0x18,0x00] + brk r15, r3 + +# CHECK: beqi +# BINARY: 101111 00000 00010 0000000000000000 +# CHECK: encoding: [0xbc,0x02,0x00,0x00] + beqi r2, 0 + +# CHECK: bgei +# BINARY: 101111 00101 00010 0000000000000000 +# CHECK: encoding: [0xbc,0xa2,0x00,0x00] + bgei r2, 0 + +# CHECK: bgti +# BINARY: 101111 00100 00010 0000000000000000 +# CHECK: encoding: [0xbc,0x82,0x00,0x00] + bgti r2, 0 + +# CHECK: blei +# BINARY: 101111 00011 00010 0000000000000000 +# CHECK: encoding: [0xbc,0x62,0x00,0x00] + blei r2, 0 + +# CHECK: blti +# BINARY: 101111 00010 00010 0000000000000000 +# CHECK: encoding: [0xbc,0x42,0x00,0x00] + blti r2, 0 + +# CHECK: bnei +# BINARY: 101111 00001 00010 0000000000000000 +# CHECK: encoding: [0xbc,0x22,0x00,0x00] + bnei r2, 0 + +# CHECK: beqid +# BINARY: 101111 10000 00010 0000000000000000 +# CHECK: encoding: [0xbe,0x02,0x00,0x00] + beqid r2, 0 + +# CHECK: bgeid +# BINARY: 101111 10101 00010 0000000000000000 +# CHECK: encoding: [0xbe,0xa2,0x00,0x00] + bgeid r2, 0 + +# CHECK: bgtid +# BINARY: 101111 10100 00010 0000000000000000 +# CHECK: encoding: [0xbe,0x82,0x00,0x00] + bgtid r2, 0 + +# CHECK: bleid +# BINARY: 101111 10011 00010 0000000000000000 +# CHECK: encoding: [0xbe,0x62,0x00,0x00] + bleid r2, 0 + +# CHECK: bltid +# BINARY: 101111 10010 00010 0000000000000000 +# CHECK: encoding: [0xbe,0x42,0x00,0x00] + bltid r2, 0 + +# CHECK: bneid +# BINARY: 101111 10001 00010 0000000000000000 +# CHECK: encoding: [0xbe,0x22,0x00,0x00] + bneid r2, 0 + +# CHECK: bri +# BINARY: 101110 00000 00000 0000000000000000 +# CHECK: encoding: [0xb8,0x00,0x00,0x00] + bri 0 + +# CHECK: brai +# BINARY: 101110 00000 01000 0000000000000000 +# CHECK: encoding: [0xb8,0x08,0x00,0x00] + brai 0 + +# CHECK: brid +# BINARY: 101110 00000 10000 0000000000000000 +# CHECK: encoding: [0xb8,0x10,0x00,0x00] + brid 0 + +# CHECK: braid +# BINARY: 101110 00000 11000 0000000000000000 +# CHECK: encoding: [0xb8,0x18,0x00,0x00] + braid 0 + +# CHECK: brlid +# BINARY: 101110 01111 10100 0000000000000000 +# CHECK: encoding: [0xb9,0xf4,0x00,0x00] + brlid r15, 0 + +# CHECK: bralid +# BINARY: 101110 01111 11100 0000000000000000 +# CHECK: encoding: [0xb9,0xfc,0x00,0x00] + bralid r15, 0 + +# CHECK: brki +# BINARY: 101110 01111 01100 0000000000000000 +# CHECK: encoding: [0xb9,0xec,0x00,0x00] + brki r15, 0 Added: llvm/trunk/test/MC/MBlaze/mblaze_fpu.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_fpu.s?rev=118941&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_fpu.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_fpu.s Fri Nov 12 17:30:17 2010 @@ -0,0 +1,77 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to ensure that all FPU instructions can be parsed by the +# assembly parser correctly. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 011011 00000 00000 00000 00000000000 + +# CHECK: fadd +# BINARY: 010110 00000 00001 00010 00000000000 +# CHECK: encoding: [0x58,0x01,0x10,0x00] + fadd r0, r1, r2 + +# CHECK: frsub +# BINARY: 010110 00000 00001 00010 00010000000 +# CHECK: encoding: [0x58,0x01,0x10,0x80] + frsub r0, r1, r2 + +# CHECK: fmul +# BINARY: 010110 00000 00001 00010 00100000000 +# CHECK: encoding: [0x58,0x01,0x11,0x00] + fmul r0, r1, r2 + +# CHECK: fdiv +# BINARY: 010110 00000 00001 00010 00110000000 +# CHECK: encoding: [0x58,0x01,0x11,0x80] + fdiv r0, r1, r2 + +# CHECK: fsqrt +# BINARY: 010110 00000 00001 00000 01110000000 +# CHECK: encoding: [0x58,0x01,0x03,0x80] + fsqrt r0, r1 + +# CHECK: fint +# BINARY: 010110 00000 00001 00000 01100000000 +# CHECK: encoding: [0x58,0x01,0x03,0x00] + fint r0, r1 + +# CHECK: flt +# BINARY: 010110 00000 00001 00000 01010000000 +# CHECK: encoding: [0x58,0x01,0x02,0x80] + flt r0, r1 + +# CHECK: fcmp.un +# BINARY: 010110 00000 00001 00010 01000000000 +# CHECK: encoding: [0x58,0x01,0x12,0x00] + fcmp.un r0, r1, r2 + +# CHECK: fcmp.lt +# BINARY: 010110 00000 00001 00010 01000010000 +# CHECK: encoding: [0x58,0x01,0x12,0x10] + fcmp.lt r0, r1, r2 + +# CHECK: fcmp.eq +# BINARY: 010110 00000 00001 00010 01000100000 +# CHECK: encoding: [0x58,0x01,0x12,0x20] + fcmp.eq r0, r1, r2 + +# CHECK: fcmp.le +# BINARY: 010110 00000 00001 00010 01000110000 +# CHECK: encoding: [0x58,0x01,0x12,0x30] + fcmp.le r0, r1, r2 + +# CHECK: fcmp.gt +# BINARY: 010110 00000 00001 00010 01001000000 +# CHECK: encoding: [0x58,0x01,0x12,0x40] + fcmp.gt r0, r1, r2 + +# CHECK: fcmp.ne +# BINARY: 010110 00000 00001 00010 01001010000 +# CHECK: encoding: [0x58,0x01,0x12,0x50] + fcmp.ne r0, r1, r2 + +# CHECK: fcmp.ge +# BINARY: 010110 00000 00001 00010 01001100000 +# CHECK: encoding: [0x58,0x01,0x12,0x60] + fcmp.ge r0, r1, r2 Modified: llvm/trunk/test/MC/MBlaze/mblaze_fsl.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_fsl.s?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_fsl.s (original) +++ llvm/trunk/test/MC/MBlaze/mblaze_fsl.s Fri Nov 12 17:30:17 2010 @@ -9,6 +9,9 @@ # TYPE FD: OPCODE RD RB NCTAE # BINARY: 011011 00000 00000 00000 0 00000 00000 +# TYPE FP: OPCODE RA NCTA FSL +# 000000 00000 00000 1 0000 0000000 0000 + # CHECK: get # BINARY: 011011 00000 000000 00000 000000 0000 # CHECK: encoding: [0x6c,0x00,0x00,0x00] @@ -169,6 +172,326 @@ # CHECK: encoding: [0x6c,0x00,0x7c,0x00] tnecaget r0, rfsl0 +# CHECK: getd +# BINARY: 010011 00000 00000 00001 0 00000 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0x00] + getd r0, r1 + +# CHECK: ngetd +# BINARY: 010011 00000 00000 00001 0 10000 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0x00] + ngetd r0, r1 + +# CHECK: cgetd +# BINARY: 010011 00000 00000 00001 0 01000 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0x00] + cgetd r0, r1 + +# CHECK: ncgetd +# BINARY: 010011 00000 00000 00001 0 11000 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0x00] + ncgetd r0, r1 + +# CHECK: tgetd +# BINARY: 010011 00000 00000 00001 0 00100 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0x80] + tgetd r0, r1 + +# CHECK: tngetd +# BINARY: 010011 00000 00000 00001 0 10100 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0x80] + tngetd r0, r1 + +# CHECK: tcgetd +# BINARY: 010011 00000 00000 00001 0 01100 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0x80] + tcgetd r0, r1 + +# CHECK: tncgetd +# BINARY: 010011 00000 00000 00001 0 11100 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0x80] + tncgetd r0, r1 + +# CHECK: agetd +# BINARY: 010011 00000 00000 00001 0 00010 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0x40] + agetd r0, r1 + +# CHECK: nagetd +# BINARY: 010011 00000 00000 00001 0 10010 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0x40] + nagetd r0, r1 + +# CHECK: cagetd +# BINARY: 010011 00000 00000 00001 0 01010 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0x40] + cagetd r0, r1 + +# CHECK: ncagetd +# BINARY: 010011 00000 00000 00001 0 11010 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0x40] + ncagetd r0, r1 + +# CHECK: tagetd +# BINARY: 010011 00000 00000 00001 0 00110 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0xc0] + tagetd r0, r1 + +# CHECK: tnagetd +# BINARY: 010011 00000 00000 00001 0 10110 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0xc0] + tnagetd r0, r1 + +# CHECK: tcagetd +# BINARY: 010011 00000 00000 00001 0 01110 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0xc0] + tcagetd r0, r1 + +# CHECK: tncagetd +# BINARY: 010011 00000 00000 00001 0 11110 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0xc0] + tncagetd r0, r1 + +# CHECK: egetd +# BINARY: 010011 00000 00000 00001 0 00001 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0x20] + egetd r0, r1 + +# CHECK: negetd +# BINARY: 010011 00000 00000 00001 0 10001 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0x20] + negetd r0, r1 + +# CHECK: ecgetd +# BINARY: 010011 00000 00000 00001 0 01001 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0x20] + ecgetd r0, r1 + +# CHECK: necgetd +# BINARY: 010011 00000 00000 00001 0 11001 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0x20] + necgetd r0, r1 + +# CHECK: tegetd +# BINARY: 010011 00000 00000 00001 0 00101 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0xa0] + tegetd r0, r1 + +# CHECK: tnegetd +# BINARY: 010011 00000 00000 00001 0 10101 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0xa0] + tnegetd r0, r1 + +# CHECK: tecgetd +# BINARY: 010011 00000 00000 00001 0 01101 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0xa0] + tecgetd r0, r1 + +# CHECK: tnecgetd +# BINARY: 010011 00000 00000 00001 0 11101 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0xa0] + tnecgetd r0, r1 + +# CHECK: eagetd +# BINARY: 010011 00000 00000 00001 0 00011 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0x60] + eagetd r0, r1 + +# CHECK: neagetd +# BINARY: 010011 00000 00000 00001 0 10011 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0x60] + neagetd r0, r1 + +# CHECK: ecagetd +# BINARY: 010011 00000 00000 00001 0 01011 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0x60] + ecagetd r0, r1 + +# CHECK: necagetd +# BINARY: 010011 00000 00000 00001 0 11011 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0x60] + necagetd r0, r1 + +# CHECK: teagetd +# BINARY: 010011 00000 00000 00001 0 00111 00000 +# CHECK: encoding: [0x4c,0x00,0x08,0xe0] + teagetd r0, r1 + +# CHECK: tneagetd +# BINARY: 010011 00000 00000 00001 0 10111 00000 +# CHECK: encoding: [0x4c,0x00,0x0a,0xe0] + tneagetd r0, r1 + +# CHECK: tecagetd +# BINARY: 010011 00000 00000 00001 0 01111 00000 +# CHECK: encoding: [0x4c,0x00,0x09,0xe0] + tecagetd r0, r1 + +# CHECK: tnecagetd +# BINARY: 010011 00000 00000 00001 0 11111 00000 +# CHECK: encoding: [0x4c,0x00,0x0b,0xe0] + tnecagetd r0, r1 + +# CHECK: put +# BINARY: 011011 00000 00000 1 0000 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0x80,0x00] + put r0, rfsl0 + +# CHECK: aput +# BINARY: 011011 00000 00000 1 0001 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0x88,0x00] + aput r0, rfsl0 + +# CHECK: cput +# BINARY: 011011 00000 00000 1 0100 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xa0,0x00] + cput r0, rfsl0 + +# CHECK: caput +# BINARY: 011011 00000 00000 1 0101 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xa8,0x00] + caput r0, rfsl0 + +# CHECK: nput +# BINARY: 011011 00000 00000 1 1000 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xc0,0x00] + nput r0, rfsl0 + +# CHECK: naput +# BINARY: 011011 00000 00000 1 1001 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xc8,0x00] + naput r0, rfsl0 + +# CHECK: ncput +# BINARY: 011011 00000 00000 1 1100 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xe0,0x00] + ncput r0, rfsl0 + +# CHECK: ncaput +# BINARY: 011011 00000 00000 1 1101 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xe8,0x00] + ncaput r0, rfsl0 + +# CHECK: tput +# BINARY: 011011 00000 00000 1 0010 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0x90,0x00] + tput rfsl0 + +# CHECK: taput +# BINARY: 011011 00000 00000 1 0011 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0x98,0x00] + taput rfsl0 + +# CHECK: tcput +# BINARY: 011011 00000 00000 1 0110 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xb0,0x00] + tcput rfsl0 + +# CHECK: tcaput +# BINARY: 011011 00000 00000 1 0111 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xb8,0x00] + tcaput rfsl0 + +# CHECK: tnput +# BINARY: 011011 00000 00000 1 1010 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xd0,0x00] + tnput rfsl0 + +# CHECK: tnaput +# BINARY: 011011 00000 00000 1 1011 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xd8,0x00] + tnaput rfsl0 + +# CHECK: tncput +# BINARY: 011011 00000 00000 1 1110 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xf0,0x00] + tncput rfsl0 + +# CHECK: tncaput +# BINARY: 011011 00000 00000 1 1111 0000000 0000 +# CHECK: encoding: [0x6c,0x00,0xf8,0x00] + tncaput rfsl0 + +# CHECK: putd +# BINARY: 010011 00000 00000 00001 1 0000 000000 +# CHECK: encoding: [0x4c,0x00,0x0c,0x00] + putd r0, r1 + +# CHECK: aputd +# BINARY: 010011 00000 00000 00001 1 0001 000000 +# CHECK: encoding: [0x4c,0x00,0x0c,0x40] + aputd r0, r1 + +# CHECK: cputd +# BINARY: 010011 00000 00000 00001 1 0100 000000 +# CHECK: encoding: [0x4c,0x00,0x0d,0x00] + cputd r0, r1 + +# CHECK: caputd +# BINARY: 010011 00000 00000 00001 1 0101 000000 +# CHECK: encoding: [0x4c,0x00,0x0d,0x40] + caputd r0, r1 + +# CHECK: nputd +# BINARY: 010011 00000 00000 00001 1 1000 000000 +# CHECK: encoding: [0x4c,0x00,0x0e,0x00] + nputd r0, r1 + +# CHECK: naputd +# BINARY: 010011 00000 00000 00001 1 1001 000000 +# CHECK: encoding: [0x4c,0x00,0x0e,0x40] + naputd r0, r1 + +# CHECK: ncputd +# BINARY: 010011 00000 00000 00001 1 1100 000000 +# CHECK: encoding: [0x4c,0x00,0x0f,0x00] + ncputd r0, r1 + +# CHECK: ncaputd +# BINARY: 010011 00000 00000 00001 1 1101 000000 +# CHECK: encoding: [0x4c,0x00,0x0f,0x40] + ncaputd r0, r1 + +# CHECK: tputd +# BINARY: 010011 00000 00000 00001 1 0010 000000 +# CHECK: encoding: [0x4c,0x00,0x0c,0x80] + tputd r1 + +# CHECK: taputd +# BINARY: 010011 00000 00000 00001 1 0011 000000 +# CHECK: encoding: [0x4c,0x00,0x0c,0xc0] + taputd r1 + +# CHECK: tcputd +# BINARY: 010011 00000 00000 00001 1 0110 000000 +# CHECK: encoding: [0x4c,0x00,0x0d,0x80] + tcputd r1 + +# CHECK: tcaputd +# BINARY: 010011 00000 00000 00001 1 0111 000000 +# CHECK: encoding: [0x4c,0x00,0x0d,0xc0] + tcaputd r1 + +# CHECK: tnputd +# BINARY: 010011 00000 00000 00001 1 1010 000000 +# CHECK: encoding: [0x4c,0x00,0x0e,0x80] + tnputd r1 + +# CHECK: tnaputd +# BINARY: 010011 00000 00000 00001 1 1011 000000 +# CHECK: encoding: [0x4c,0x00,0x0e,0xc0] + tnaputd r1 + +# CHECK: tncputd +# BINARY: 010011 00000 00000 00001 1 1110 000000 +# CHECK: encoding: [0x4c,0x00,0x0f,0x80] + tncputd r1 + +# CHECK: tncaputd +# BINARY: 010011 00000 00000 00001 1 1111 000000 +# CHECK: encoding: [0x4c,0x00,0x0f,0xc0] + tncaputd r1 + # CHECK: get # BINARY: 011011 00000 000000 00000 000000 0001 # CHECK: encoding: [0x6c,0x00,0x00,0x01] Added: llvm/trunk/test/MC/MBlaze/mblaze_memory.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_memory.s?rev=118941&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_memory.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_memory.s Fri Nov 12 17:30:17 2010 @@ -0,0 +1,107 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to make sure that all of the TYPE-A instructions supported by +# the Microblaze can be parsed by the assembly parser. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 000000 00000 00000 00000 00000000000 + +# CHECK: lbu +# BINARY: 110000 00001 00010 00011 00000000000 +# CHECK: encoding: [0xc0,0x22,0x18,0x00] + lbu r1, r2, r3 + +# CHECK: lbur +# BINARY: 110000 00001 00010 00011 01000000000 +# CHECK: encoding: [0xc0,0x22,0x1a,0x00] + lbur r1, r2, r3 + +# CHECK: lbui +# BINARY: 111000 00001 00010 0000000000011100 +# CHECK: encoding: [0xe0,0x22,0x00,0x1c] + lbui r1, r2, 28 + +# CHECK: lhu +# BINARY: 110001 00001 00010 00011 00000000000 +# CHECK: encoding: [0xc4,0x22,0x18,0x00] + lhu r1, r2, r3 + +# CHECK: lhur +# BINARY: 110001 00001 00010 00011 01000000000 +# CHECK: encoding: [0xc4,0x22,0x1a,0x00] + lhur r1, r2, r3 + +# CHECK: lhui +# BINARY: 111001 00001 00010 0000000000011100 +# CHECK: encoding: [0xe4,0x22,0x00,0x1c] + lhui r1, r2, 28 + +# CHECK: lw +# BINARY: 110010 00001 00010 00011 00000000000 +# CHECK: encoding: [0xc8,0x22,0x18,0x00] + lw r1, r2, r3 + +# CHECK: lwr +# BINARY: 110010 00001 00010 00011 01000000000 +# CHECK: encoding: [0xc8,0x22,0x1a,0x00] + lwr r1, r2, r3 + +# CHECK: lwi +# BINARY: 111010 00001 00010 0000000000011100 +# CHECK: encoding: [0xe8,0x22,0x00,0x1c] + lwi r1, r2, 28 + +# CHECK: lwx +# BINARY: 110010 00001 00010 00011 10000000000 +# CHECK: encoding: [0xc8,0x22,0x1c,0x00] + lwx r1, r2, r3 + +# CHECK: sb +# BINARY: 110100 00001 00010 00011 00000000000 +# CHECK: encoding: [0xd0,0x22,0x18,0x00] + sb r1, r2, r3 + +# CHECK: sbr +# BINARY: 110100 00001 00010 00011 01000000000 +# CHECK: encoding: [0xd0,0x22,0x1a,0x00] + sbr r1, r2, r3 + +# CHECK: sbi +# BINARY: 111100 00001 00010 0000000000011100 +# CHECK: encoding: [0xf0,0x22,0x00,0x1c] + sbi r1, r2, 28 + +# CHECK: sh +# BINARY: 110101 00001 00010 00011 00000000000 +# CHECK: encoding: [0xd4,0x22,0x18,0x00] + sh r1, r2, r3 + +# CHECK: shr +# BINARY: 110101 00001 00010 00011 01000000000 +# CHECK: encoding: [0xd4,0x22,0x1a,0x00] + shr r1, r2, r3 + +# CHECK: shi +# BINARY: 111101 00001 00010 0000000000011100 +# CHECK: encoding: [0xf4,0x22,0x00,0x1c] + shi r1, r2, 28 + +# CHECK: sw +# BINARY: 110110 00001 00010 00011 00000000000 +# CHECK: encoding: [0xd8,0x22,0x18,0x00] + sw r1, r2, r3 + +# CHECK: swr +# BINARY: 110110 00001 00010 00011 01000000000 +# CHECK: encoding: [0xd8,0x22,0x1a,0x00] + swr r1, r2, r3 + +# CHECK: swi +# BINARY: 111110 00001 00010 0000000000011100 +# CHECK: encoding: [0xf8,0x22,0x00,0x1c] + swi r1, r2, 28 + +# CHECK: swx +# BINARY: 110110 00001 00010 00011 10000000000 +# CHECK: encoding: [0xd8,0x22,0x1c,0x00] + swx r1, r2, r3 Added: llvm/trunk/test/MC/MBlaze/mblaze_pattern.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_pattern.s?rev=118941&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_pattern.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_pattern.s Fri Nov 12 17:30:17 2010 @@ -0,0 +1,22 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to ensure that all FPU instructions can be parsed by the +# assembly parser correctly. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 011011 00000 00000 00000 00000000000 + +# CHECK: pcmpbf +# BINARY: 100000 00000 00001 00010 10000000000 +# CHECK: encoding: [0x80,0x01,0x14,0x00] + pcmpbf r0, r1, r2 + +# CHECK: pcmpeq +# BINARY: 100011 00000 00001 00010 10000000000 +# CHECK: encoding: [0x8c,0x01,0x14,0x00] + pcmpeq r0, r1, r2 + +# CHECK: pcmpne +# BINARY: 100010 00000 00001 00010 10000000000 +# CHECK: encoding: [0x88,0x01,0x14,0x00] + pcmpne r0, r1, r2 Added: llvm/trunk/test/MC/MBlaze/mblaze_shift.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_shift.s?rev=118941&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_shift.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_shift.s Fri Nov 12 17:30:17 2010 @@ -0,0 +1,47 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to make sure that all of the TYPE-A instructions supported by +# the Microblaze can be parsed by the assembly parser. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 000000 00000 00000 00000 00000000000 + +# CHECK: bsrl +# BINARY: 010001 00001 00010 00011 00000000000 +# CHECK: encoding: [0x44,0x22,0x18,0x00] + bsrl r1, r2, r3 + +# CHECK: bsra +# BINARY: 010001 00001 00010 00011 01000000000 +# CHECK: encoding: [0x44,0x22,0x1a,0x00] + bsra r1, r2, r3 + +# CHECK: bsll +# BINARY: 010001 00001 00010 00011 10000000000 +# CHECK: encoding: [0x44,0x22,0x1c,0x00] + bsll r1, r2, r3 + +# CHECK: bsrli +# BINARY: 011001 00001 00010 0000000000000000 +# CHECK: encoding: [0x64,0x22,0x00,0x00] + bsrli r1, r2, 0 + +# CHECK: bsrai +# BINARY: 011001 00001 00010 0000001000000000 +# CHECK: encoding: [0x64,0x22,0x02,0x00] + bsrai r1, r2, 0 + +# CHECK: bslli +# BINARY: 011001 00001 00010 0000010000000000 +# CHECK: encoding: [0x64,0x22,0x04,0x00] + bslli r1, r2, 0 + +# CHECK: sra +# BINARY: 100100 00001 00010 00000 00000000001 +# CHECK: encoding: [0x90,0x22,0x00,0x01] + sra r1, r2 + +# CHECK: srl +# BINARY: 100100 00001 00010 00000 00001000001 +# CHECK: encoding: [0x90,0x22,0x00,0x41] + srl r1, r2 Added: llvm/trunk/test/MC/MBlaze/mblaze_special.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_special.s?rev=118941&view=auto ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_special.s (added) +++ llvm/trunk/test/MC/MBlaze/mblaze_special.s Fri Nov 12 17:30:17 2010 @@ -0,0 +1,47 @@ +# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s + +# Test to ensure that all FPU instructions can be parsed by the +# assembly parser correctly. + +# TYPE A: OPCODE RD RA RB FLAGS +# BINARY: 011011 00000 00000 00000 00000000000 + +# CHECK: mfs +# BINARY: 100101 00000 00000 10000 00000000000 +# CHECK: encoding: [0x94,0x00,0x80,0x00] + mfs r0, 0x0 + +# CHECK: msrclr +# BINARY: 100101 00000 100010 000000000000000 +# CHECK: encoding: [0x94,0x11,0x00,0x00] + msrclr r0, 0x0 + +# CHECK: msrset +# BINARY: 100101 00000 100000 000000000000000 +# CHECK: encoding: [0x94,0x10,0x00,0x00] + msrset r0, 0x0 + +# CHECK: mts +# BINARY: 100101 00000 00000 11 00000000000000 +# CHECK: encoding: [0x94,0x00,0xc0,0x00] + mts 0x0 , r0 + +# CHECK: wdc +# BINARY: 100100 00000 00000 00001 00001100100 +# CHECK: encoding: [0x90,0x00,0x08,0x64] + wdc r0, r1 + +# CHECK: wdc.clear +# BINARY: 100100 00000 00000 00001 00001100110 +# CHECK: encoding: [0x90,0x00,0x08,0x66] + wdc.clear r0, r1 + +# CHECK: wdc.flush +# BINARY: 100100 00000 00000 00001 00001110100 +# CHECK: encoding: [0x90,0x00,0x08,0x74] + wdc.flush r0, r1 + +# CHECK: wic +# BINARY: 100100 00000 00000 00001 00001101000 +# CHECK: encoding: [0x90,0x00,0x08,0x68] + wic r0, r1 Modified: llvm/trunk/test/MC/MBlaze/mblaze_typea.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_typea.s?rev=118941&r1=118940&r2=118941&view=diff ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_typea.s (original) +++ llvm/trunk/test/MC/MBlaze/mblaze_typea.s Fri Nov 12 17:30:17 2010 @@ -36,35 +36,85 @@ # CHECK: encoding: [0x8c,0x22,0x18,0x00] andn r1, r2, r3 -# CHECK: beq -# BINARY: 100111 00000 00010 00011 00000000000 -# CHECK: encoding: [0x9c,0x02,0x18,0x00] - beq r2, r3 - -# CHECK: bge -# BINARY: 100111 00101 00010 00011 00000000000 -# CHECK: encoding: [0x9c,0xa2,0x18,0x00] - bge r2, r3 - -# CHECK: bgt -# BINARY: 100111 00100 00010 00011 00000000000 -# CHECK: encoding: [0x9c,0x82,0x18,0x00] - bgt r2, r3 - -# CHECK: ble -# BINARY: 100111 00011 00010 00011 00000000000 -# CHECK: encoding: [0x9c,0x62,0x18,0x00] - ble r2, r3 - -# CHECK: blt -# BINARY: 100111 00010 00010 00011 00000000000 -# CHECK: encoding: [0x9c,0x42,0x18,0x00] - blt r2, r3 - -# CHECK: bne -# BINARY: 100111 00001 00010 00011 00000000000 -# CHECK: encoding: [0x9c,0x22,0x18,0x00] - bne r2, r3 +# CHECK: cmp +# BINARY: 000101 00001 00010 00011 00000000001 +# CHECK: encoding: [0x14,0x22,0x18,0x01] + cmp r1, r2, r3 + +# CHECK: cmpu +# BINARY: 000101 00001 00010 00011 00000000011 +# CHECK: encoding: [0x14,0x22,0x18,0x03] + cmpu r1, r2, r3 + +# CHECK: idiv +# BINARY: 010010 00001 00010 00011 00000000000 +# CHECK: encoding: [0x48,0x22,0x18,0x00] + idiv r1, r2, r3 + +# CHECK: idivu +# BINARY: 010010 00001 00010 00011 00000000010 +# CHECK: encoding: [0x48,0x22,0x18,0x02] + idivu r1, r2, r3 + +# CHECK: mul +# BINARY: 010000 00001 00010 00011 00000000000 +# CHECK: encoding: [0x40,0x22,0x18,0x00] + mul r1, r2, r3 + +# CHECK: mulh +# BINARY: 010000 00001 00010 00011 00000000001 +# CHECK: encoding: [0x40,0x22,0x18,0x01] + mulh r1, r2, r3 + +# CHECK: mulhu +# BINARY: 010000 00001 00010 00011 00000000011 +# CHECK: encoding: [0x40,0x22,0x18,0x03] + mulhu r1, r2, r3 + +# CHECK: mulhsu +# BINARY: 010000 00001 00010 00011 00000000010 +# CHECK: encoding: [0x40,0x22,0x18,0x02] + mulhsu r1, r2, r3 + +# CHECK: or +# BINARY: 100000 00001 00010 00011 00000000000 +# CHECK: encoding: [0x80,0x22,0x18,0x00] + or r1, r2, r3 + +# FIXMEC: rsub +# BINARY: 000001 00001 00010 00011 00000000000 +# FIXMEC: encoding: [0x04,0x22,0x18,0x00] + rsub r1, r2, r3 + +# FIXMEC: rsubc +# BINARY: 000011 00001 00010 00011 00000000000 +# FIXMEC: encoding: [0x0c,0x22,0x18,0x00] + rsubc r1, r2, r3 + +# FIXMEC: rsubk +# BINARY: 000101 00001 00010 00011 00000000000 +# FIXMEC: encoding: [0x14,0x22,0x18,0x00] + rsubk r1, r2, r3 + +# FIXMEC: rsubkc +# BINARY: 000111 00001 00010 00011 00000000000 +# FIXMEC: encoding: [0x1c,0x22,0x18,0x00] + rsubkc r1, r2, r3 + +# CHECK: sext16 +# BINARY: 100100 00001 00010 00000 00001100001 +# CHECK: encoding: [0x90,0x22,0x00,0x61] + sext16 r1, r2 + +# CHECK: sext8 +# BINARY: 100100 00001 00010 00000 00001100000 +# CHECK: encoding: [0x90,0x22,0x00,0x60] + sext8 r1, r2 + +# CHECK: xor +# BINARY: 100010 00001 00010 00011 00000000000 +# CHECK: encoding: [0x88,0x22,0x18,0x00] + xor r1, r2, r3 # CHECK: nop # BINARY: 100000 00000 00000 00000 00000000000 From resistor at mac.com Fri Nov 12 17:36:03 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 12 Nov 2010 23:36:03 -0000 Subject: [llvm-commits] [llvm] r118942 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20101112233603.878E82A6C12C@llvm.org> Author: resistor Date: Fri Nov 12 17:36:03 2010 New Revision: 118942 URL: http://llvm.org/viewvc/llvm-project?rev=118942&view=rev Log: Revert r118939 while I work out why it broke some buildbots. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118942&r1=118941&r2=118942&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Nov 12 17:36:03 2010 @@ -170,7 +170,7 @@ // Multiclass helpers... // -class T2TwoRegImm pattern> : T2sI { bits<4> Rd; @@ -262,10 +262,9 @@ InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, PatFrag opnode, bit Commutable = 0, string wide = ""> { // shifted imm - def ri : T2TwoRegImm< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, - opc, "\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> { + def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii, + opc, "\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -273,10 +272,9 @@ let Inst{15} = 0; } // register - def rr : T2ThreeReg< - (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, - opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), - [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { + def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir, + opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), + [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -287,10 +285,9 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2TwoRegShiftedReg< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, - opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), - [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> { + def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis, + opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), + [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -310,10 +307,9 @@ /// it is equivalent to the T2I_bin_irs counterpart. multiclass T2I_rbin_irs opcod, string opc, PatFrag opnode> { // shifted imm - def ri : T2TwoRegImm< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, - opc, ".w\t$Rd, $imm, $Rn", - [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { + def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, + opc, ".w\t$dst, $rhs, $lhs", + [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -321,8 +317,8 @@ let Inst{15} = 0; } // register - def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, - opc, "\t$Rd, $Rm, $Rn", + def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, + opc, "\t$dst, $rhs, $lhs", [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -333,10 +329,9 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2TwoRegShiftedReg< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), - IIC_iALUsir, opc, "\t$Rd, $ShiftedRm, $Rn", - [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { + def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsir, + opc, "\t$dst, $rhs, $lhs", + [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -351,9 +346,9 @@ InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2TwoRegImm<(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, - !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> { + def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii, + !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -361,9 +356,9 @@ let Inst{15} = 0; } // register - def rr : T2ThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, - !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> { + def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir, + !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -374,10 +369,9 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2TwoRegShiftedReg< - (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, - !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { + def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis, + !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -394,10 +388,9 @@ // The register-immediate version is re-materializable. This is useful // in particular for taking the address of a local. let isReMaterializable = 1 in { - def ri : T2TwoRegImm< - (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi, - opc, ".w\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> { + def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, + opc, ".w\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24} = 1; @@ -407,10 +400,9 @@ } } // 12-bit imm - def ri12 : T2TwoRegImm< - (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, - !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> { + def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, + !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24} = 0; @@ -419,9 +411,9 @@ let Inst{15} = 0; } // register - def rr : T2ThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr, - opc, ".w\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> { + def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr, + opc, ".w\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { let isCommutable = Commutable; let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; @@ -433,10 +425,9 @@ let Inst{5-4} = 0b00; // type } // shifted register - def rs : T2TwoRegShiftedReg< - (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), - IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { + def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, + opc, ".w\t$dst, $lhs, $rhs", + [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24} = 1; @@ -452,7 +443,7 @@ multiclass T2I_adde_sube_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2TwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), + def ri : T2TwoRegShiftedImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, opc, "\t$Rd, $Rn, $imm", [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, Requires<[IsThumb2]> { @@ -494,7 +485,7 @@ multiclass T2I_adde_sube_s_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm - def ri : T2TwoRegImm< + def ri : T2TwoRegShiftedImm< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, opc, "\t$Rd, $Rn, $imm", [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, @@ -539,10 +530,9 @@ let Defs = [CPSR] in { multiclass T2I_rbin_s_is opcod, string opc, PatFrag opnode> { // shifted imm - def ri : T2TwoRegImm< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, - !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { + def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, + !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs", + [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = opcod; @@ -550,10 +540,9 @@ let Inst{15} = 0; } // shifted register - def rs : T2TwoRegShiftedReg< - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), - IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { + def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, + !strconcat(opc, "s"), "\t$dst, $rhs, $lhs", + [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; @@ -885,19 +874,17 @@ } // ADD r, sp, {so_imm|i12} -def t2ADDrSPi : T2TwoRegImm< - (outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), - IIC_iALUi, "add", ".w\t$Rn, $Rn, $imm", []> { +def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), + IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> { let Inst{31-27} = 0b11110; let Inst{25} = 0; let Inst{24-21} = 0b1000; let Inst{20} = ?; // The S bit. - let Inst{19-16} = 0b1101; + let Inst{19-16} = 0b1101; // Rn = sp let Inst{15} = 0; } -def t2ADDrSPi12 : T2TwoRegImm< - (outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), - IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> { +def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), + IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-21} = 0b0000; From peckw at wesleypeck.com Fri Nov 12 17:41:10 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Fri, 12 Nov 2010 23:41:10 -0000 Subject: [llvm-commits] [llvm] r118943 - in /llvm/trunk: lib/Target/MBlaze/MBlazeInstrFormats.td lib/Target/MBlaze/MBlazeInstrInfo.td test/MC/MBlaze/mblaze_typea.s Message-ID: <20101112234110.395012A6C12C@llvm.org> Author: peckw Date: Fri Nov 12 17:41:10 2010 New Revision: 118943 URL: http://llvm.org/viewvc/llvm-project?rev=118943&view=rev Log: Fixing improperly encoded reverse subtract instructions in MBlaze backend. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td llvm/trunk/test/MC/MBlaze/mblaze_typea.s Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=118943&r1=118942&r2=118943&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td Fri Nov 12 17:41:10 2010 @@ -125,18 +125,17 @@ class TAR op, bits<11> flags, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin> : - MBlazeInst + TA { - bits<5> rd; - bits<5> rb; - bits<5> ra; + bits<5> rrd; + bits<5> rrb; + bits<5> rra; let Form = FRRRR; - let Inst{6-10} = rd; - let Inst{11-15} = ra; - let Inst{16-20} = rb; - let Inst{21-31} = flags; + let rd = rrd; + let ra = rra; + let rb = rrb; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118943&r1=118942&r2=118943&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Fri Nov 12 17:41:10 2010 @@ -177,7 +177,7 @@ class ArithR op, bits<11> flags, string instr_asm, SDNode OpNode, InstrItinClass itin> : - TAR; Modified: llvm/trunk/test/MC/MBlaze/mblaze_typea.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_typea.s?rev=118943&r1=118942&r2=118943&view=diff ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_typea.s (original) +++ llvm/trunk/test/MC/MBlaze/mblaze_typea.s Fri Nov 12 17:41:10 2010 @@ -81,24 +81,24 @@ # CHECK: encoding: [0x80,0x22,0x18,0x00] or r1, r2, r3 -# FIXMEC: rsub +# CHECK: rsub # BINARY: 000001 00001 00010 00011 00000000000 -# FIXMEC: encoding: [0x04,0x22,0x18,0x00] +# CHECK: encoding: [0x04,0x22,0x18,0x00] rsub r1, r2, r3 -# FIXMEC: rsubc +# CHECK: rsubc # BINARY: 000011 00001 00010 00011 00000000000 -# FIXMEC: encoding: [0x0c,0x22,0x18,0x00] +# CHECK: encoding: [0x0c,0x22,0x18,0x00] rsubc r1, r2, r3 -# FIXMEC: rsubk +# CHECK: rsubk # BINARY: 000101 00001 00010 00011 00000000000 -# FIXMEC: encoding: [0x14,0x22,0x18,0x00] +# CHECK: encoding: [0x14,0x22,0x18,0x00] rsubk r1, r2, r3 -# FIXMEC: rsubkc +# CHECK: rsubkc # BINARY: 000111 00001 00010 00011 00000000000 -# FIXMEC: encoding: [0x1c,0x22,0x18,0x00] +# CHECK: encoding: [0x1c,0x22,0x18,0x00] rsubkc r1, r2, r3 # CHECK: sext16 From jasonwkim at google.com Fri Nov 12 17:47:28 2010 From: jasonwkim at google.com (Jason Kim) Date: Fri, 12 Nov 2010 15:47:28 -0800 Subject: [llvm-commits] [PATCH] elfobjectwriter patch (ARM/MC/ELF) In-Reply-To: <76C8C7AD-5BF0-40C7-87BE-7C3D00ACC8C8@apple.com> References: <76C8C7AD-5BF0-40C7-87BE-7C3D00ACC8C8@apple.com> Message-ID: +llvmdev On Fri, Nov 12, 2010 at 7:57 AM, Jim Grosbach wrote: > > On Nov 10, 2010, at 9:57 AM, Jason Kim wrote: > >> Refactoring the x86 dependent code from ELFObjectWriter class has >> repercussions among several (conflicting) axes of consideration, >> >> 1. namespace pollution - minimize pollution of the llvm: ?namespace >> 2. consistency - try to maintain as small a delta between the changes >> 3. linking - minimize the number of additional cross dependency >> between the existing libraries >> 4. clarity - avoid special case switching as much as possible - >> 5. Xfactor - how clean is the overall resulting design? >> >> The possible ?ways forward I see are >> >> SMALL: keep the code nearly as is - place a switch inside >> ELFObjectWriter::RecordRelocation and dispatch to >> ELFObjectWriterImpl::RecordRelocation >> 1. +1 no new classes >> 2. +1 tiny patch >> 3. +1 no new classes, just one additional function so far. >> 4. -2 need to have special case switching for every routine that needs >> to be tweaked. >> 5. -2 Terrible! So far, its just one new switch, but ... >> >> tryA: move the functionality of the ELFObjectWriterImpl class into >> ELFObjectWriter, and subclass ELFObjectWriter to >> ELFObjectWriter. >> Change most ELF specific routines to be virtual - except for the low >> level Write* routines - >> 1. -1 at least new classes ARMELFObjectWriter and X86ELFObjectWriter >> 2. -1 large patch >> 3. +2 Resulting special cases are isolated in their own class >> 4. +1 ?Depends upon virtual dispatch for higher level differentiation >> - removes unnecessary trampoline between ELFObjectWriter and >> ELFObjectWriterImpl >> 5. +2 This approach is the best in terms of the resulting design. The >> only drawback is the distinction between MachO and ELF >> > > This looks OK to me, and is similar to what I'm looking at for MachO. I confess I'm not completely clear on why the ELF writer is currently split into the Writer and WriterImpl classes, so that may be worth answering before proceeding too far. Thanks for the feedback, Jim. I'll wait a bit to see if there's an interesting answer to: Anyone have any idea why the ELFObjectWriter/ and WriterImpl classes were split? > > > >> tryB: subclass ELFObjectWriterImpl instead - I am still working out >> the details on this one - but as of right now, it is just as complex >> as the tryA case. >> The only benefit to this is approach is the superficial similarity >> between the ELFObjectWriter and the MachObjectWriter - in that both >> still trampoline into an *Impl class to do the actual work. >> Unfortunately, it also adds a requirement for registering a NEW >> ELFObjecWriterImpl class (i.e. in addition to the existing >> createELFObjectWriter, and without namespace pollution to llvm, >> creates a linkage dependency failure). >> I will reply to this thread with a patch as soon as I finish this variant. >> >> There are several attachments: >> >> small: >> small-elfwriter-cpp (application/octet-stream) 2K >> small-elfwriter-rename-record (application/octet-stream) 2K >> >> tryA >> ?arm-mc-elf-s07-elfwriter-tryA-combined.patch (text/x-patch) 43K - >> this is the combined patch - In order to make it more clear, I broke >> up the steps into a dozen or so smaller patches. >> ?tryA.tgz ?- archive of patches >> ?They are combined into a tar archive - the README is reproduced here. >> >> Thanks for reading. >> -jason >> > > From evan.cheng at apple.com Fri Nov 12 17:46:13 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 23:46:13 -0000 Subject: [llvm-commits] [llvm] r118945 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td InstPrinter/ARMInstPrinter.cpp InstPrinter/ARMInstPrinter.h Message-ID: <20101112234613.70C252A6C12C@llvm.org> Author: evancheng Date: Fri Nov 12 17:46:13 2010 New Revision: 118945 URL: http://llvm.org/viewvc/llvm-project?rev=118945&view=rev Log: For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118945&r1=118944&r2=118945&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 17:46:13 2010 @@ -359,12 +359,17 @@ // Break so_imm's up into two pieces. This handles immediates with up to 16 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to // get the first/second pieces. -def so_imm2part : Operand, - PatLeaf<(imm), [{ +def so_imm2part : PatLeaf<(imm), [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); - }]> { - let PrintMethod = "printSOImm2PartOperand"; -} +}]>; + +/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. +/// +def arm_i32imm : PatLeaf<(imm), [{ + if (Subtarget->hasV6T2Ops()) + return true; + return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); +}]>; def so_imm2part_1 : SDNodeXFormgetZExtValue()); @@ -3223,7 +3228,7 @@ // FIXME: Remove this when we can do generalized remat. let isReMaterializable = 1 in def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "", - [(set GPR:$dst, (i32 imm:$src))]>, + [(set GPR:$dst, (arm_i32imm:$src))]>, Requires<[IsARM]>; // ConstantPool, GlobalAddress, and JumpTable Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118945&r1=118944&r2=118945&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Fri Nov 12 17:46:13 2010 @@ -160,14 +160,6 @@ printSOImm(O, MO.getImm(), CommentStream, &MAI); } -/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' -/// followed by an 'orr' to materialize. -void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - // FIXME: REMOVE this method. - abort(); -} - // so_reg is a 4-operand unit corresponding to register forms of the A5.1 // "Addressing Mode 1 - Data-processing operands" forms. This includes: // REG 0 0 - e.g. R5 Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=118945&r1=118944&r2=118945&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Fri Nov 12 17:46:13 2010 @@ -36,7 +36,6 @@ void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); From evan.cheng at apple.com Fri Nov 12 17:48:44 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 15:48:44 -0800 Subject: [llvm-commits] [llvm] r118936 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <20101112225232.8C2232A6C12C@llvm.org> References: <20101112225232.8C2232A6C12C@llvm.org> Message-ID: <4A0C7A41-B6D3-49CB-90C6-3788CE650932@apple.com> Is this related to: ******************** TEST 'LLVM :: CodeGen/ARM/fast-isel.ll' FAILED ******************** Script: -- llc < /Volumes/Ebi/echeng/llvm/test/CodeGen/ARM/fast-isel.ll -O0 -fast-isel-abort -mtriple=armv7-apple-darwin llc < /Volumes/Ebi/echeng/llvm/test/CodeGen/ARM/fast-isel.ll -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin -- Exit Code: 132 Command Output (stderr): -- FastISel miss: %t8 = getelementptr i32* %t7, i32 %t6 FastISel didn't select the entire block UNREACHABLE executed at SelectionDAGISel.cpp:899! 0 llc 0x0000000106505ac5 PrintStackTrace(void*) + 53 1 llc 0x00000001065060d3 SignalHandler(int) + 371 2 libsystem_c.dylib 0x00007fff8048179a _sigtramp + 26 3 libsystem_c.dylib 0x00007fff80446725 szone_free_definite_size + 3888 4 llc 0x0000000106505d9b raise + 27 5 llc 0x0000000106505e5a abort + 26 6 llc 0x00000001064d595c llvm::llvm_unreachable_internal(char const*, char const*, unsigned int) + 220 7 llc 0x0000000105e9c0cf llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 2111 8 llc 0x0000000105e9adea llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 842 9 llc 0x0000000105ffcd21 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 97 10 llc 0x00000001063ee64f llvm::FPPassManager::runOnFunction(llvm::Function&) + 383 11 llc 0x00000001063ee9d1 llvm::FPPassManager::runOnModule(llvm::Module&) + 129 12 llc 0x00000001063eec09 llvm::MPPassManager::runOnModule(llvm::Module&) + 473 13 llc 0x00000001063ef316 llvm::PassManagerImpl::run(llvm::Module&) + 182 14 llc 0x00000001063ef76d llvm::PassManager::run(llvm::Module&) + 29 15 llc 0x00000001058c7a80 main + 3072 16 llc 0x00000001058c6e34 start + 52 Stack dump: 0. Program arguments: llc -O0 -fast-isel-abort -mtriple=armv7-apple-darwin 1. Running pass 'Function Pass Manager' on module ''. 2. Running pass 'ARM Instruction Selection' on function '@foo' Evan On Nov 12, 2010, at 2:52 PM, Eric Christopher wrote: > Author: echristo > Date: Fri Nov 12 16:52:32 2010 > New Revision: 118936 > > URL: http://llvm.org/viewvc/llvm-project?rev=118936&view=rev > Log: > Make this happen for ARM like x86. Don't entirely bail out when > an address is in a different block, get it into a register and go > from there. > > Modified: > llvm/trunk/lib/Target/ARM/ARMFastISel.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118936&r1=118935&r2=118936&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Nov 12 16:52:32 2010 > @@ -590,10 +590,11 @@ > // Don't walk into other basic blocks; it's possible we haven't > // visited them yet, so the instructions may not yet be assigned > // virtual registers. > - if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) > - return false; > - Opcode = I->getOpcode(); > - U = I; > + if (FuncInfo.StaticAllocaMap.count(static_cast(Obj)) || > + FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { > + Opcode = I->getOpcode(); > + U = I; > + } > } else if (const ConstantExpr *C = dyn_cast(Obj)) { > Opcode = C->getOpcode(); > U = C; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Fri Nov 12 17:51:32 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 12 Nov 2010 15:51:32 -0800 Subject: [llvm-commits] [llvm] r118936 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <4A0C7A41-B6D3-49CB-90C6-3788CE650932@apple.com> References: <20101112225232.8C2232A6C12C@llvm.org> <4A0C7A41-B6D3-49CB-90C6-3788CE650932@apple.com> Message-ID: On Nov 12, 2010, at 3:48 PM, Evan Cheng wrote: > Is this related to: > > ******************** TEST 'LLVM :: CodeGen/ARM/fast-isel.ll' FAILED ******************** > Script: > -- > llc < /Volumes/Ebi/echeng/llvm/test/CodeGen/ARM/fast-isel.ll -O0 -fast-isel-abort -mtriple=armv7-apple-darwin > llc < /Volumes/Ebi/echeng/llvm/test/CodeGen/ARM/fast-isel.ll -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin > -- > Exit Code: 132 > Command Output (stderr): > -- > FastISel miss: %t8 = getelementptr i32* %t7, i32 %t6 > FastISel didn't select the entire block > UNREACHABLE executed at SelectionDAGISel.cpp:899! > 0 llc 0x0000000106505ac5 PrintStackTrace(void*) + 53 > 1 llc 0x00000001065060d3 SignalHandler(int) + 371 > 2 libsystem_c.dylib 0x00007fff8048179a _sigtramp + 26 > 3 libsystem_c.dylib 0x00007fff80446725 szone_free_definite_size + 3888 > 4 llc 0x0000000106505d9b raise + 27 > 5 llc 0x0000000106505e5a abort + 26 > 6 llc 0x00000001064d595c llvm::llvm_unreachable_internal(char const*, char const*, unsigned int) + 220 > 7 llc 0x0000000105e9c0cf llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 2111 > 8 llc 0x0000000105e9adea llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 842 > 9 llc 0x0000000105ffcd21 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 97 > 10 llc 0x00000001063ee64f llvm::FPPassManager::runOnFunction(llvm::Function&) + 383 > 11 llc 0x00000001063ee9d1 llvm::FPPassManager::runOnModule(llvm::Module&) + 129 > 12 llc 0x00000001063eec09 llvm::MPPassManager::runOnModule(llvm::Module&) + 473 > 13 llc 0x00000001063ef316 llvm::PassManagerImpl::run(llvm::Module&) + 182 > 14 llc 0x00000001063ef76d llvm::PassManager::run(llvm::Module&) + 29 > 15 llc 0x00000001058c7a80 main + 3072 > 16 llc 0x00000001058c6e34 start + 52 > Stack dump: > 0. Program arguments: llc -O0 -fast-isel-abort -mtriple=armv7-apple-darwin > 1. Running pass 'Function Pass Manager' on module ''. > 2. Running pass 'ARM Instruction Selection' on function '@foo' Yes. Weird I didn't see it. Too many things in flight at once. I'll fix. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20101112/f774415b/attachment.html From echristo at apple.com Fri Nov 12 17:50:48 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 12 Nov 2010 23:50:48 -0000 Subject: [llvm-commits] [llvm] r118946 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20101112235048.797982A6C12C@llvm.org> Author: echristo Date: Fri Nov 12 17:50:48 2010 New Revision: 118946 URL: http://llvm.org/viewvc/llvm-project?rev=118946&view=rev Log: Temporarily revert this. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118946&r1=118945&r2=118946&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Nov 12 17:50:48 2010 @@ -590,11 +590,10 @@ // Don't walk into other basic blocks; it's possible we haven't // visited them yet, so the instructions may not yet be assigned // virtual registers. - if (FuncInfo.StaticAllocaMap.count(static_cast(Obj)) || - FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { - Opcode = I->getOpcode(); - U = I; - } + if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) + return false; + Opcode = I->getOpcode(); + U = I; } else if (const ConstantExpr *C = dyn_cast(Obj)) { Opcode = C->getOpcode(); U = C; From clattner at apple.com Fri Nov 12 18:04:07 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 12 Nov 2010 16:04:07 -0800 Subject: [llvm-commits] [llvm] r118938 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMExpandPseudoInsts.cpp ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td In-Reply-To: <20101112230338.7BAFA2A6C12C@llvm.org> References: <20101112230338.7BAFA2A6C12C@llvm.org> Message-ID: <14EBFC41-332C-40DF-8BBE-A7D581A393DD@apple.com> On Nov 12, 2010, at 3:03 PM, Evan Cheng wrote: > Author: evancheng > Date: Fri Nov 12 17:03:38 2010 > New Revision: 118938 > > URL: http://llvm.org/viewvc/llvm-project?rev=118938&view=rev > Log: > Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget. Ok. > + unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); > + unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); > + LO16 = LO16.addImm(SOImmValV1); > + HI16 = HI16.addImm(SOImmValV2); > + (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); > + (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); Please use x-> instead of (*x). -Chris From peckw at wesleypeck.com Fri Nov 12 18:03:46 2010 From: peckw at wesleypeck.com (Wesley Peck) Date: Sat, 13 Nov 2010 00:03:46 -0000 Subject: [llvm-commits] [llvm] r118948 - in /llvm/trunk: lib/Target/MBlaze/MBlazeInstrInfo.td test/MC/MBlaze/mblaze_typeb.s Message-ID: <20101113000346.F0E2F2A6C12C@llvm.org> Author: peckw Date: Fri Nov 12 18:03:46 2010 New Revision: 118948 URL: http://llvm.org/viewvc/llvm-project?rev=118948&view=rev Log: 1. Adding missing immediate mode asm parser test cases. 2. Fixing improper immediate mode reverse subtract. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td llvm/trunk/test/MC/MBlaze/mblaze_typeb.s Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118948&r1=118947&r2=118948&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Fri Nov 12 18:03:46 2010 @@ -376,8 +376,8 @@ def ADDIK : ArithNI<0x0C, "addik ", simm16, immSExt16>; def ADDIKC : ArithI<0x0E, "addikc ", addc, simm16, immSExt16>; def RSUBI : ArithRI<0x09, "rsubi ", sub, simm16, immSExt16>; - def RSUBIC : ArithRNI<0x0B, "rsubi ", simm16, immSExt16>; - def RSUBIK : ArithRNI<0x0E, "rsubic ", simm16, immSExt16>; + def RSUBIC : ArithRNI<0x0B, "rsubic ", simm16, immSExt16>; + def RSUBIK : ArithRNI<0x0D, "rsubik ", simm16, immSExt16>; def RSUBIKC : ArithRI<0x0F, "rsubikc", subc, simm16, immSExt16>; def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>; def ANDI : LogicI<0x29, "andi ", and>; Modified: llvm/trunk/test/MC/MBlaze/mblaze_typeb.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_typeb.s?rev=118948&r1=118947&r2=118948&view=diff ============================================================================== --- llvm/trunk/test/MC/MBlaze/mblaze_typeb.s (original) +++ llvm/trunk/test/MC/MBlaze/mblaze_typeb.s Fri Nov 12 18:03:46 2010 @@ -35,3 +35,58 @@ # BINARY: 101011 00001 00010 0000000000001111 # CHECK: encoding: [0xac,0x22,0x00,0x0f] andni r1, r2, 0x000F + +# CHECK: muli +# BINARY: 011000 00001 00010 0000000000001111 +# CHECK: encoding: [0x60,0x22,0x00,0x0f] + muli r1, r2, 0x000F + +# CHECK: ori +# BINARY: 101000 00001 00010 0000000000001111 +# CHECK: encoding: [0xa0,0x22,0x00,0x0f] + ori r1, r2, 0x000F + +# CHECK: rsubi +# BINARY: 001001 00001 00010 0000000000001111 +# CHECK: encoding: [0x24,0x22,0x00,0x0f] + rsubi r1, r2, 0x000F + +# CHECK: rsubic +# BINARY: 001011 00001 00010 0000000000001111 +# CHECK: encoding: [0x2c,0x22,0x00,0x0f] + rsubic r1, r2, 0x000F + +# CHECK: rsubik +# BINARY: 001101 00001 00010 0000000000001111 +# CHECK: encoding: [0x34,0x22,0x00,0x0f] + rsubik r1, r2, 0x000F + +# CHECK: rsubikc +# BINARY: 001111 00001 00010 0000000000001111 +# CHECK: encoding: [0x3c,0x22,0x00,0x0f] + rsubikc r1, r2, 0x000F + +# CHECK: rtbd +# BINARY: 101101 10010 01111 0000000000001111 +# CHECK: encoding: [0xb6,0x4f,0x00,0x0f] + rtbd r15, 0x000F + +# CHECK: rted +# BINARY: 101101 10001 01111 0000000000001111 +# CHECK: encoding: [0xb6,0x8f,0x00,0x0f] + rted r15, 0x000F + +# CHECK: rtid +# BINARY: 101101 10001 01111 0000000000001111 +# CHECK: encoding: [0xb6,0x2f,0x00,0x0f] + rtid r15, 0x000F + +# CHECK: rtsd +# BINARY: 101101 10000 01111 0000000000001111 +# CHECK: encoding: [0xb6,0x0f,0x00,0x0f] + rtsd r15, 0x000F + +# CHECK: xori +# BINARY: 101010 00001 00010 0000000000001111 +# CHECK: encoding: [0xa8,0x22,0x00,0x0f] + xori r1, r2, 0x000F From evan.cheng at apple.com Fri Nov 12 18:10:39 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 12 Nov 2010 16:10:39 -0800 Subject: [llvm-commits] [llvm] r118938 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMExpandPseudoInsts.cpp ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td In-Reply-To: <14EBFC41-332C-40DF-8BBE-A7D581A393DD@apple.com> References: <20101112230338.7BAFA2A6C12C@llvm.org> <14EBFC41-332C-40DF-8BBE-A7D581A393DD@apple.com> Message-ID: On Nov 12, 2010, at 4:04 PM, Chris Lattner wrote: > > On Nov 12, 2010, at 3:03 PM, Evan Cheng wrote: > >> Author: evancheng >> Date: Fri Nov 12 17:03:38 2010 >> New Revision: 118938 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=118938&view=rev >> Log: >> Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget. > > Ok. > >> + unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); >> + unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); >> + LO16 = LO16.addImm(SOImmValV1); >> + HI16 = HI16.addImm(SOImmValV2); >> + (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); >> + (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); > > Please use x-> instead of (*x). To be fixed. MachineInstrBuilder doesn't have -> operator. Evan > > -Chris From daniel at zuster.org Fri Nov 12 18:23:34 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sat, 13 Nov 2010 00:23:34 -0000 Subject: [llvm-commits] [zorg] r118949 - /zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Message-ID: <20101113002334.4F6832A6C12C@llvm.org> Author: ddunbar Date: Fri Nov 12 18:23:34 2010 New Revision: 118949 URL: http://llvm.org/viewvc/llvm-project?rev=118949&view=rev Log: buildbot: Add support for packaging/upload of stage1 compilers. Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=118949&r1=118948&r2=118949&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Fri Nov 12 18:23:34 2010 @@ -164,6 +164,27 @@ workdir=llvm_1_objdir)) if not useTwoStage: + if package_dst: + name = WithProperties( + "%(builddir)s/" + llvm_1_objdir + + "/clang-r%(got_revision)s-b%(buildnumber)s.tgz") + f.addStep(ShellCommand(name='pkg.tar', + description="tar root", + command=["tar", "zcvf", name, "./"], + workdir=llvm_1_installdir, + warnOnFailure=True, + flunkOnFailure=False, + haltOnFailure=False)) + f.addStep(ShellCommand(name='pkg.upload', + description="upload root", + command=["scp", name, + WithProperties( + package_dst + "/%(buildername)s")], + workdir=".", + warnOnFailure=True, + flunkOnFailure=False, + haltOnFailure=False)) + return f # Clean up llvm (stage 2). From echristo at apple.com Fri Nov 12 18:25:06 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 13 Nov 2010 00:25:06 -0000 Subject: [llvm-commits] [llvm] r118950 - /llvm/trunk/test/CodeGen/ARM/fast-isel.ll Message-ID: <20101113002506.697512A6C12C@llvm.org> Author: echristo Date: Fri Nov 12 18:25:06 2010 New Revision: 118950 URL: http://llvm.org/viewvc/llvm-project?rev=118950&view=rev Log: This should be still failing, but is. Disable it with the forget-me-stick for now. Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=118950&r1=118949&r2=118950&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Fri Nov 12 18:25:06 2010 @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin +; RUN: true +; RUN: true ; Very basic fast-isel functionality. From clattner at apple.com Fri Nov 12 18:27:59 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 12 Nov 2010 16:27:59 -0800 Subject: [llvm-commits] [llvm] r118923 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp In-Reply-To: <20101112211025.098D22A6C12C@llvm.org> References: <20101112211025.098D22A6C12C@llvm.org> Message-ID: <5E5AD3E7-8022-4A50-8576-BE651935B52C@apple.com> On Nov 12, 2010, at 1:10 PM, Duncan Sands wrote: > Author: baldrick > Date: Fri Nov 12 15:10:24 2010 > New Revision: 118923 > > URL: http://llvm.org/viewvc/llvm-project?rev=118923&view=rev > Log: > Have GVN simplify instructions as it goes. For example, consider > "%z = %x and %y". If GVN can prove that %y equals %x, then it turns > this into "%z = %x and %x". With the new code, %z will be replaced > with %x everywhere (and then deleted). Previously %z would be value > numbered too, which is a waste of time. Also, while a clever value > numbering algorithm would give %z the same value number as %x, our > current one doesn't do so (at least I don't think it does). The new > logic has an essentially equivalent effect to what you would get if > %z was given the same value number as %x, i.e. it should make value > numbering smarter. While there, get hold of target data once at the > start rather than a gazillion times all over the place. Awesome! Please add a testcase though, -Chris From clattner at apple.com Fri Nov 12 18:28:45 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 12 Nov 2010 16:28:45 -0800 Subject: [llvm-commits] [llvm] r117420 - in /llvm/trunk: cmake/modules/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ In-Reply-To: <6B65D64D-12B0-40BF-B585-C770EDCACF66@wesleypeck.com> References: <20101027002302.2AE5F2A6C12C@llvm.org> <152DDF75-3BA5-49AA-BC28-95A4A2B8FC28@apple.com> <6B65D64D-12B0-40BF-B585-C770EDCACF66@wesleypeck.com> Message-ID: On Nov 11, 2010, at 4:50 PM, Wesley Peck wrote: > Yeah, from what I saw the ARM and x86 backends had some custom tblgen stuff to do a lot of this. I'm unfamiliar with adding stuff to tblgen so I decided to just hand code some of the tables for now. When the auto-generation from .td files is working then I'll convert the MBlaze backend over to that. Yeah, no worries, this is a longer term infrastructure project. > I'll add some test cases in the next few days. > > Again, thanks for taking a look at the code. Cool thanks, happy to help, -Chris > > -- Wesley Peck > > On Nov 11, 2010, at 6:07 PM, Chris Lattner wrote: > >> >> On Oct 26, 2010, at 5:23 PM, Wesley Peck wrote: >> >>> Author: peckw >>> Date: Tue Oct 26 19:23:01 2010 >>> New Revision: 117420 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=117420&view=rev >>> Log: >>> Adding disassembler to the MicroBlaze backend. >> >> Ok, cool. Please add some simple testcases for these as well. Our ultimate goal is to have the disassembler be autogenerated from the encoding info in the .td files (for targets with 16 or 32-bit encodings) so that you don't have to write so much rote code, but in the meantime this is the right way to go. >> >> -Chris > From evan.cheng at apple.com Fri Nov 12 18:27:47 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 13 Nov 2010 00:27:47 -0000 Subject: [llvm-commits] [llvm] r118951 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/select-imm.ll Message-ID: <20101113002747.D26762A6C12C@llvm.org> Author: evancheng Date: Fri Nov 12 18:27:47 2010 New Revision: 118951 URL: http://llvm.org/viewvc/llvm-project?rev=118951&view=rev Log: Fix an obvious typo which inverted an immediate. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/test/CodeGen/ARM/select-imm.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=118951&r1=118950&r2=118951&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Nov 12 18:27:47 2010 @@ -1791,7 +1791,7 @@ return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16), MVT::i32, Ops, 5); } else if (is_t2_so_imm_not(TrueImm)) { - SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32); + SDValue True = CurDAG->getTargetConstant(~TrueImm, MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; return CurDAG->SelectNodeTo(N, ARM::t2MVNCCi, MVT::i32, Ops, 5); Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=118951&r1=118950&r2=118951&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Fri Nov 12 18:27:47 2010 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 +; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s --check-prefix=T2 define i32 @t1(i32 %c) nounwind readnone { entry: @@ -25,7 +25,7 @@ ; ARM: movle r0, #123 ; T2: t2: -; T2: mov r0, #123 +; T2: mov.w r0, #123 ; T2: movwgt r0, #357 %0 = icmp sgt i32 %c, 1 @@ -40,9 +40,22 @@ ; ARM: moveq r0, #1 ; T2: t3: -; T2: mov r0, #0 +; T2: mov.w r0, #0 ; T2: moveq r0, #1 %0 = icmp eq i32 %a, 160 %1 = zext i1 %0 to i32 ret i32 %1 } + +define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind { +entry: +; ARM: t4: +; ARM: ldr +; ARM: movlt + +; T2: t4: +; T2: mvnlt.w r0, #11141290 + %0 = icmp slt i32 %a, %b + %1 = select i1 %0, i32 4283826005, i32 %x + ret i32 %1 +} From daniel at zuster.org Fri Nov 12 18:28:01 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sat, 13 Nov 2010 00:28:01 -0000 Subject: [llvm-commits] [llvm] r118952 - in /llvm/trunk: test/ExecutionEngine/ tools/lli/ Message-ID: <20101113002801.E87322A6C12C@llvm.org> Author: ddunbar Date: Fri Nov 12 18:28:01 2010 New Revision: 118952 URL: http://llvm.org/viewvc/llvm-project?rev=118952&view=rev Log: lli: Switch to using ParseIRFile, for consistency with other LLVM tools. - Also, switch tests to not using llvm-as. They run 20% faster now, not that it matters. Modified: llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll llvm/trunk/test/ExecutionEngine/2003-01-04-PhiTest.ll llvm/trunk/test/ExecutionEngine/2003-01-09-SARTest.ll llvm/trunk/test/ExecutionEngine/2003-01-10-FUCOM.ll llvm/trunk/test/ExecutionEngine/2003-01-15-AlignmentTest.ll llvm/trunk/test/ExecutionEngine/2003-05-06-LivenessClobber.ll llvm/trunk/test/ExecutionEngine/2003-05-07-ArgumentTest.ll llvm/trunk/test/ExecutionEngine/2003-05-11-PHIRegAllocBug.ll llvm/trunk/test/ExecutionEngine/2003-06-04-bzip2-bug.ll llvm/trunk/test/ExecutionEngine/2003-06-05-PHIBug.ll llvm/trunk/test/ExecutionEngine/2003-08-15-AllocaAssertion.ll llvm/trunk/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll llvm/trunk/test/ExecutionEngine/2003-08-23-RegisterAllocatePhysReg.ll llvm/trunk/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll llvm/trunk/test/ExecutionEngine/2005-12-02-TailCallBug.ll llvm/trunk/test/ExecutionEngine/2007-12-10-APIntLoadStore.ll llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll llvm/trunk/test/ExecutionEngine/2010-01-15-UndefValue.ll llvm/trunk/test/ExecutionEngine/fpbitcast.ll llvm/trunk/test/ExecutionEngine/hello.ll llvm/trunk/test/ExecutionEngine/hello2.ll llvm/trunk/test/ExecutionEngine/simplesttest.ll llvm/trunk/test/ExecutionEngine/simpletest.ll llvm/trunk/test/ExecutionEngine/stubs.ll llvm/trunk/test/ExecutionEngine/test-arith.ll llvm/trunk/test/ExecutionEngine/test-branch.ll llvm/trunk/test/ExecutionEngine/test-call.ll llvm/trunk/test/ExecutionEngine/test-cast.ll llvm/trunk/test/ExecutionEngine/test-constantexpr.ll llvm/trunk/test/ExecutionEngine/test-fp.ll llvm/trunk/test/ExecutionEngine/test-loadstore.ll llvm/trunk/test/ExecutionEngine/test-logical.ll llvm/trunk/test/ExecutionEngine/test-loop.ll llvm/trunk/test/ExecutionEngine/test-malloc.ll llvm/trunk/test/ExecutionEngine/test-phi.ll llvm/trunk/test/ExecutionEngine/test-ret.ll llvm/trunk/test/ExecutionEngine/test-setcond-fp.ll llvm/trunk/test/ExecutionEngine/test-setcond-int.ll llvm/trunk/test/ExecutionEngine/test-shift.ll llvm/trunk/tools/lli/Makefile llvm/trunk/tools/lli/lli.cpp Modified: llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll?rev=118952&r1=118951&r2=118952&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll Fri Nov 12 18:28:01 2010 @@ -1,5 +1,4 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: lli %t.bc > /dev/null +; RUN: lli %s > /dev/null @.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll?rev=118952&r1=118951&r2=118952&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll Fri Nov 12 18:28:01 2010 @@ -1,5 +1,4 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: lli %t.bc > /dev/null +; RUN: lli %s > /dev/null define i32 @foo(i32 %X, i32 %Y, double %A) { %cond212 = fcmp une double %A, 1.000000e+00 ; [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll?rev=118952&r1=118951&r2=118952&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll Fri Nov 12 18:28:01 2010 @@ -1,5 +1,4 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: lli %t.bc > /dev/null +; RUN: lli %s > /dev/null define i32 @main() { call i32 @mylog( i32 4 ) ; :1 [#uses=0] Modified: llvm/trunk/test/ExecutionEngine/2003-01-04-PhiTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-01-04-PhiTest.ll?rev=118952&r1=118951&r2=118952&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-01-04-PhiTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-01-04-PhiTest.ll Fri Nov 12 18:28:01 2010 @@ -1,5 +1,4 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: lli %t.bc > /dev/null +; RUN: lli %s > /dev/null define i32 @main() { ;