From sabre at nondot.org  Mon Dec 13 00:25:44 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 06:25:44 -0000
Subject: [llvm-commits] [llvm] r121688 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101213062544.CD6372A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 00:25:44 2010
New Revision: 121688

URL: http://llvm.org/viewvc/llvm-project?rev=121688&view=rev
Log:
split all the guts of SimplifyCFGOpt::run out into one function
per terminator kind.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121688&r1=121687&r2=121688&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 00:25:44 2010
@@ -48,6 +48,14 @@
                                                      BasicBlock *Pred);
   bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI);
 
+  bool SimplifyReturn(ReturnInst *RI);
+  bool SimplifyUnwind(UnwindInst *UI);
+  bool SimplifyUnreachable(UnreachableInst *UI);
+  bool SimplifySwitch(SwitchInst *SI);
+  bool SimplifyIndirectBr(IndirectBrInst *IBI);
+  bool SimplifyUncondBranch(BranchInst *BI);
+  bool SimplifyCondBranch(BranchInst *BI);
+
 public:
   explicit SimplifyCFGOpt(const TargetData *td) : TD(td) {}
   bool run(BasicBlock *BB);
@@ -1918,8 +1926,7 @@
   }
   
   // Create the new switch instruction now.
-  SwitchInst *New =
-  SwitchInst::Create(CompVal, DefaultBB, Values.size(), BI);
+  SwitchInst *New = SwitchInst::Create(CompVal, DefaultBB, Values.size(), BI);
   
   // Add all of the 'cases' to the switch instruction.
   for (unsigned i = 0, e = Values.size(); i != e; ++i)
@@ -1941,415 +1948,475 @@
   return true;
 }
 
-bool SimplifyCFGOpt::run(BasicBlock *BB) {
-  bool Changed = false;
-  Function *Fn = BB->getParent();
-
-  assert(BB && Fn && "Block not embedded in function!");
-  assert(BB->getTerminator() && "Degenerate basic block encountered!");
-
-  // Remove basic blocks that have no predecessors (except the entry block)...
-  // or that just have themself as a predecessor.  These are unreachable.
-  if ((pred_begin(BB) == pred_end(BB) && BB != &Fn->getEntryBlock()) ||
-      BB->getSinglePredecessor() == BB) {
-    DEBUG(dbgs() << "Removing BB: \n" << *BB);
-    DeleteDeadBlock(BB);
+bool SimplifyCFGOpt::SimplifyReturn(ReturnInst *RI) {
+  BasicBlock *BB = RI->getParent();
+  if (!BB->getFirstNonPHIOrDbg()->isTerminator()) return false;
+  
+  // Find predecessors that end with branches.
+  SmallVector<BasicBlock*, 8> UncondBranchPreds;
+  SmallVector<BranchInst*, 8> CondBranchPreds;
+  for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
+    BasicBlock *P = *PI;
+    TerminatorInst *PTI = P->getTerminator();
+    if (BranchInst *BI = dyn_cast<BranchInst>(PTI)) {
+      if (BI->isUnconditional())
+        UncondBranchPreds.push_back(P);
+      else
+        CondBranchPreds.push_back(BI);
+    }
+  }
+  
+  // If we found some, do the transformation!
+  if (!UncondBranchPreds.empty()) {
+    while (!UncondBranchPreds.empty()) {
+      BasicBlock *Pred = UncondBranchPreds.pop_back_val();
+      DEBUG(dbgs() << "FOLDING: " << *BB
+            << "INTO UNCOND BRANCH PRED: " << *Pred);
+      Instruction *UncondBranch = Pred->getTerminator();
+      // Clone the return and add it to the end of the predecessor.
+      Instruction *NewRet = RI->clone();
+      Pred->getInstList().push_back(NewRet);
+      
+      // If the return instruction returns a value, and if the value was a
+      // PHI node in "BB", propagate the right value into the return.
+      for (User::op_iterator i = NewRet->op_begin(), e = NewRet->op_end();
+           i != e; ++i)
+        if (PHINode *PN = dyn_cast<PHINode>(*i))
+          if (PN->getParent() == BB)
+            *i = PN->getIncomingValueForBlock(Pred);
+      
+      // Update any PHI nodes in the returning block to realize that we no
+      // longer branch to them.
+      BB->removePredecessor(Pred);
+      Pred->getInstList().erase(UncondBranch);
+    }
+    
+    // If we eliminated all predecessors of the block, delete the block now.
+    if (pred_begin(BB) == pred_end(BB))
+      // We know there are no successors, so just nuke the block.
+      BB->eraseFromParent();
+    
     return true;
   }
+  
+  // Check out all of the conditional branches going to this return
+  // instruction.  If any of them just select between returns, change the
+  // branch itself into a select/return pair.
+  while (!CondBranchPreds.empty()) {
+    BranchInst *BI = CondBranchPreds.pop_back_val();
+    
+    // Check to see if the non-BB successor is also a return block.
+    if (isa<ReturnInst>(BI->getSuccessor(0)->getTerminator()) &&
+        isa<ReturnInst>(BI->getSuccessor(1)->getTerminator()) &&
+        SimplifyCondBranchToTwoReturns(BI))
+      return true;
+  }
+  return false;
+}
 
-  // Check to see if we can constant propagate this terminator instruction
-  // away...
-  Changed |= ConstantFoldTerminator(BB);
-
-  // Check for and eliminate duplicate PHI nodes in this block.
-  Changed |= EliminateDuplicatePHINodes(BB);
+bool SimplifyCFGOpt::SimplifyUnwind(UnwindInst *UI) {
+  // Check to see if the first instruction in this block is just an unwind.
+  // If so, replace any invoke instructions which use this as an exception
+  // destination with call instructions.
+  BasicBlock *BB = UI->getParent();
+  if (!BB->getFirstNonPHIOrDbg()->isTerminator()) return false;
 
-  // Merge basic blocks into their predecessor if there is only one distinct
-  // pred, and if there is only one distinct successor of the predecessor, and
-  // if there are no PHI nodes.
-  //
-  if (MergeBlockIntoPredecessor(BB))
+  bool Changed = false;
+  SmallVector<BasicBlock*, 8> Preds(pred_begin(BB), pred_end(BB));
+  while (!Preds.empty()) {
+    BasicBlock *Pred = Preds.back();
+    InvokeInst *II = dyn_cast<InvokeInst>(Pred->getTerminator());
+    if (II && II->getUnwindDest() == BB) {
+      // Insert a new branch instruction before the invoke, because this
+      // is now a fall through.
+      BranchInst *BI = BranchInst::Create(II->getNormalDest(), II);
+      Pred->getInstList().remove(II);   // Take out of symbol table
+      
+      // Insert the call now.
+      SmallVector<Value*,8> Args(II->op_begin(), II->op_end()-3);
+      CallInst *CI = CallInst::Create(II->getCalledValue(),
+                                      Args.begin(), Args.end(),
+                                      II->getName(), BI);
+      CI->setCallingConv(II->getCallingConv());
+      CI->setAttributes(II->getAttributes());
+      // If the invoke produced a value, the Call now does instead.
+      II->replaceAllUsesWith(CI);
+      delete II;
+      Changed = true;
+    }
+    
+    Preds.pop_back();
+  }
+  
+  // If this block is now dead (and isn't the entry block), remove it.
+  if (pred_begin(BB) == pred_end(BB) &&
+      BB != &BB->getParent()->getEntryBlock()) {
+    // We know there are no successors, so just nuke the block.
+    BB->eraseFromParent();
     return true;
+  }
   
-  // If there is a trivial two-entry PHI node in this basic block, and we can
-  // eliminate it, do so now.
-  if (PHINode *PN = dyn_cast<PHINode>(BB->begin()))
-    if (PN->getNumIncomingValues() == 2)
-      Changed |= FoldTwoEntryPHINode(PN); 
+  return Changed;  
+}
 
-  // If this is a returning block with only PHI nodes in it, fold the return
-  // instruction into any unconditional branch predecessors.
-  //
-  // If any predecessor is a conditional branch that just selects among
-  // different return values, fold the replace the branch/return with a select
-  // and return.
-  if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
-    if (BB->getFirstNonPHIOrDbg()->isTerminator()) {
-      // Find predecessors that end with branches.
-      SmallVector<BasicBlock*, 8> UncondBranchPreds;
-      SmallVector<BranchInst*, 8> CondBranchPreds;
-      for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
-        BasicBlock *P = *PI;
-        TerminatorInst *PTI = P->getTerminator();
-        if (BranchInst *BI = dyn_cast<BranchInst>(PTI)) {
-          if (BI->isUnconditional())
-            UncondBranchPreds.push_back(P);
-          else
-            CondBranchPreds.push_back(BI);
+bool SimplifyCFGOpt::SimplifyUnreachable(UnreachableInst *UI) {
+  BasicBlock *BB = UI->getParent();
+  
+  bool Changed = false;
+  
+  // If there are any instructions immediately before the unreachable that can
+  // be removed, do so.
+  while (UI != BB->begin()) {
+    BasicBlock::iterator BBI = UI;
+    --BBI;
+    // Do not delete instructions that can have side effects, like calls
+    // (which may never return) and volatile loads and stores.
+    if (isa<CallInst>(BBI) && !isa<DbgInfoIntrinsic>(BBI)) break;
+    
+    if (StoreInst *SI = dyn_cast<StoreInst>(BBI))
+      if (SI->isVolatile())
+        break;
+    
+    if (LoadInst *LI = dyn_cast<LoadInst>(BBI))
+      if (LI->isVolatile())
+        break;
+    
+    // Delete this instruction
+    BB->getInstList().erase(BBI);
+    Changed = true;
+  }
+  
+  // If the unreachable instruction is the first in the block, take a gander
+  // at all of the predecessors of this instruction, and simplify them.
+  if (&BB->front() != UI) return Changed;
+  
+  SmallVector<BasicBlock*, 8> Preds(pred_begin(BB), pred_end(BB));
+  for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
+    TerminatorInst *TI = Preds[i]->getTerminator();
+    
+    if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
+      if (BI->isUnconditional()) {
+        if (BI->getSuccessor(0) == BB) {
+          new UnreachableInst(TI->getContext(), TI);
+          TI->eraseFromParent();
+          Changed = true;
+        }
+      } else {
+        if (BI->getSuccessor(0) == BB) {
+          BranchInst::Create(BI->getSuccessor(1), BI);
+          EraseTerminatorInstAndDCECond(BI);
+        } else if (BI->getSuccessor(1) == BB) {
+          BranchInst::Create(BI->getSuccessor(0), BI);
+          EraseTerminatorInstAndDCECond(BI);
+          Changed = true;
         }
       }
-
-      // If we found some, do the transformation!
-      if (!UncondBranchPreds.empty()) {
-        while (!UncondBranchPreds.empty()) {
-          BasicBlock *Pred = UncondBranchPreds.pop_back_val();
-          DEBUG(dbgs() << "FOLDING: " << *BB
-                       << "INTO UNCOND BRANCH PRED: " << *Pred);
-          Instruction *UncondBranch = Pred->getTerminator();
-          // Clone the return and add it to the end of the predecessor.
-          Instruction *NewRet = RI->clone();
-          Pred->getInstList().push_back(NewRet);
-
-          // If the return instruction returns a value, and if the value was a
-          // PHI node in "BB", propagate the right value into the return.
-          for (User::op_iterator i = NewRet->op_begin(), e = NewRet->op_end();
-               i != e; ++i)
-            if (PHINode *PN = dyn_cast<PHINode>(*i))
-              if (PN->getParent() == BB)
-                *i = PN->getIncomingValueForBlock(Pred);
+    } else if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) {
+      for (unsigned i = 1, e = SI->getNumCases(); i != e; ++i)
+        if (SI->getSuccessor(i) == BB) {
+          BB->removePredecessor(SI->getParent());
+          SI->removeCase(i);
+          --i; --e;
+          Changed = true;
+        }
+      // If the default value is unreachable, figure out the most popular
+      // destination and make it the default.
+      if (SI->getSuccessor(0) == BB) {
+        std::map<BasicBlock*, unsigned> Popularity;
+        for (unsigned i = 1, e = SI->getNumCases(); i != e; ++i)
+          Popularity[SI->getSuccessor(i)]++;
+        
+        // Find the most popular block.
+        unsigned MaxPop = 0;
+        BasicBlock *MaxBlock = 0;
+        for (std::map<BasicBlock*, unsigned>::iterator
+             I = Popularity.begin(), E = Popularity.end(); I != E; ++I) {
+          if (I->second > MaxPop) {
+            MaxPop = I->second;
+            MaxBlock = I->first;
+          }
+        }
+        if (MaxBlock) {
+          // Make this the new default, allowing us to delete any explicit
+          // edges to it.
+          SI->setSuccessor(0, MaxBlock);
+          Changed = true;
           
-          // Update any PHI nodes in the returning block to realize that we no
-          // longer branch to them.
-          BB->removePredecessor(Pred);
-          Pred->getInstList().erase(UncondBranch);
+          // If MaxBlock has phinodes in it, remove MaxPop-1 entries from
+          // it.
+          if (isa<PHINode>(MaxBlock->begin()))
+            for (unsigned i = 0; i != MaxPop-1; ++i)
+              MaxBlock->removePredecessor(SI->getParent());
+          
+          for (unsigned i = 1, e = SI->getNumCases(); i != e; ++i)
+            if (SI->getSuccessor(i) == MaxBlock) {
+              SI->removeCase(i);
+              --i; --e;
+            }
         }
-
-        // If we eliminated all predecessors of the block, delete the block now.
-        if (pred_begin(BB) == pred_end(BB))
-          // We know there are no successors, so just nuke the block.
-          Fn->getBasicBlockList().erase(BB);
-
-        return true;
       }
-
-      // Check out all of the conditional branches going to this return
-      // instruction.  If any of them just select between returns, change the
-      // branch itself into a select/return pair.
-      while (!CondBranchPreds.empty()) {
-        BranchInst *BI = CondBranchPreds.pop_back_val();
-
-        // Check to see if the non-BB successor is also a return block.
-        if (isa<ReturnInst>(BI->getSuccessor(0)->getTerminator()) &&
-            isa<ReturnInst>(BI->getSuccessor(1)->getTerminator()) &&
-            SimplifyCondBranchToTwoReturns(BI))
-          return true;
-      }
-    }
-  } else if (isa<UnwindInst>(BB->begin())) {
-    // Check to see if the first instruction in this block is just an unwind.
-    // If so, replace any invoke instructions which use this as an exception
-    // destination with call instructions.
-    //
-    SmallVector<BasicBlock*, 8> Preds(pred_begin(BB), pred_end(BB));
-    while (!Preds.empty()) {
-      BasicBlock *Pred = Preds.back();
-      InvokeInst *II = dyn_cast<InvokeInst>(Pred->getTerminator());
-      if (II && II->getUnwindDest() == BB) {
-        // Insert a new branch instruction before the invoke, because this
-        // is now a fall through.
+    } else if (InvokeInst *II = dyn_cast<InvokeInst>(TI)) {
+      if (II->getUnwindDest() == BB) {
+        // Convert the invoke to a call instruction.  This would be a good
+        // place to note that the call does not throw though.
         BranchInst *BI = BranchInst::Create(II->getNormalDest(), II);
-        Pred->getInstList().remove(II);   // Take out of symbol table
-
-        // Insert the call now.
-        SmallVector<Value*,8> Args(II->op_begin(), II->op_end()-3);
+        II->removeFromParent();   // Take out of symbol table
+        
+        // Insert the call now...
+        SmallVector<Value*, 8> Args(II->op_begin(), II->op_end()-3);
         CallInst *CI = CallInst::Create(II->getCalledValue(),
                                         Args.begin(), Args.end(),
                                         II->getName(), BI);
         CI->setCallingConv(II->getCallingConv());
         CI->setAttributes(II->getAttributes());
-        // If the invoke produced a value, the Call now does instead.
+        // If the invoke produced a value, the call does now instead.
         II->replaceAllUsesWith(CI);
         delete II;
         Changed = true;
       }
-
-      Preds.pop_back();
     }
+  }
+  
+  // If this block is now dead, remove it.
+  if (pred_begin(BB) == pred_end(BB) &&
+      BB != &BB->getParent()->getEntryBlock()) {
+    // We know there are no successors, so just nuke the block.
+    BB->eraseFromParent();
+    return true;
+  }
 
-    // If this block is now dead (and isn't the entry block), remove it.
-    if (pred_begin(BB) == pred_end(BB) && BB != &Fn->getEntryBlock()) {
-      // We know there are no successors, so just nuke the block.
-      Fn->getBasicBlockList().erase(BB);
-      return true;
-    }
+  return Changed;
+}
 
-  } else if (SwitchInst *SI = dyn_cast<SwitchInst>(BB->getTerminator())) {
-    if (isValueEqualityComparison(SI)) {
-      // If we only have one predecessor, and if it is a branch on this value,
-      // see if that predecessor totally determines the outcome of this switch.
-      if (BasicBlock *OnlyPred = BB->getSinglePredecessor())
-        if (SimplifyEqualityComparisonWithOnlyPredecessor(SI, OnlyPred))
-          return SimplifyCFG(BB) || 1;
-
-      // If the block only contains the switch, see if we can fold the block
-      // away into any preds.
-      BasicBlock::iterator BBI = BB->begin();
-      // Ignore dbg intrinsics.
-      while (isa<DbgInfoIntrinsic>(BBI))
-        ++BBI;
-      if (SI == &*BBI)
-        if (FoldValueComparisonIntoPredecessors(SI))
-          return SimplifyCFG(BB) || 1;
-    }
-  } else if (BranchInst *BI = dyn_cast<BranchInst>(BB->getTerminator())) {
-    if (BI->isUnconditional()) {
-      // If the Terminator is the only non-phi instruction, simplify the block.
-      BasicBlock::iterator I = BB->getFirstNonPHIOrDbg();
-      if (I->isTerminator() && BB != &Fn->getEntryBlock() &&
-          TryToSimplifyUncondBranchFromEmptyBlock(BB))
-        return true;
-      
-      // If the only instruction in the block is a seteq/setne comparison
-      // against a constant, try to simplify the block.
-      if (ICmpInst *ICI = dyn_cast<ICmpInst>(I))
-        if (ICI->isEquality() && isa<ConstantInt>(ICI->getOperand(1))) {
-          for (++I; isa<DbgInfoIntrinsic>(I); ++I)
-            ;
-          if (I->isTerminator() &&
-              TryToSimplifyUncondBranchWithICmpInIt(ICI))
-            return true;
-        }
-      
-    } else {  // Conditional branch
-      if (isValueEqualityComparison(BI)) {
-        // If we only have one predecessor, and if it is a branch on this value,
-        // see if that predecessor totally determines the outcome of this
-        // switch.
-        if (BasicBlock *OnlyPred = BB->getSinglePredecessor())
-          if (SimplifyEqualityComparisonWithOnlyPredecessor(BI, OnlyPred))
-            return SimplifyCFG(BB) | true;
-
-        // This block must be empty, except for the setcond inst, if it exists.
-        // Ignore dbg intrinsics.
-        BasicBlock::iterator I = BB->begin();
-        // Ignore dbg intrinsics.
-        while (isa<DbgInfoIntrinsic>(I))
-          ++I;
-        if (&*I == BI) {
-          if (FoldValueComparisonIntoPredecessors(BI))
-            return SimplifyCFG(BB) | true;
-        } else if (&*I == cast<Instruction>(BI->getCondition())){
-          ++I;
-          // Ignore dbg intrinsics.
-          while (isa<DbgInfoIntrinsic>(I))
-            ++I;
-          if (&*I == BI && FoldValueComparisonIntoPredecessors(BI))
-            return SimplifyCFG(BB) | true;
-        }
-      }
 
-      // Try to turn "br (X == 0 | X == 1), T, F" into a switch instruction.
-      if (SimplifyBranchOnICmpChain(BI, TD))
-        return true;
-      
-      
-      // We have a conditional branch to two blocks that are only reachable
-      // from BI.  We know that the condbr dominates the two blocks, so see if
-      // there is any identical code in the "then" and "else" blocks.  If so, we
-      // can hoist it up to the branching block.
-      if (BI->getSuccessor(0)->getSinglePredecessor() != 0) {
-        if (BI->getSuccessor(1)->getSinglePredecessor() != 0) {
-          if (HoistThenElseCodeToIf(BI))
-            return SimplifyCFG(BB) | true;
-        } else {
-          // If Successor #1 has multiple preds, we may be able to conditionally
-          // execute Successor #0 if it branches to successor #1.
-          TerminatorInst *Succ0TI = BI->getSuccessor(0)->getTerminator();
-          if (Succ0TI->getNumSuccessors() == 1 &&
-              Succ0TI->getSuccessor(0) == BI->getSuccessor(1))
-            if (SpeculativelyExecuteBB(BI, BI->getSuccessor(0)))
-              return SimplifyCFG(BB) | true;
-        }
-      } else if (BI->getSuccessor(1)->getSinglePredecessor() != 0) {
-        // If Successor #0 has multiple preds, we may be able to conditionally
-        // execute Successor #1 if it branches to successor #0.
-        TerminatorInst *Succ1TI = BI->getSuccessor(1)->getTerminator();
-        if (Succ1TI->getNumSuccessors() == 1 &&
-            Succ1TI->getSuccessor(0) == BI->getSuccessor(0))
-          if (SpeculativelyExecuteBB(BI, BI->getSuccessor(1)))
-            return SimplifyCFG(BB) | true;
-      }
-      
-      // If this is a branch on a phi node in the current block, thread control
-      // through this block if any PHI node entries are constants.
-      if (PHINode *PN = dyn_cast<PHINode>(BI->getCondition()))
-        if (PN->getParent() == BI->getParent())
-          if (FoldCondBranchOnPHI(BI))
-            return SimplifyCFG(BB) | true;
-
-      // If this basic block is ONLY a setcc and a branch, and if a predecessor
-      // branches to us and one of our successors, fold the setcc into the
-      // predecessor and use logical operations to pick the right destination.
-      if (FoldBranchToCommonDest(BI))
-        return SimplifyCFG(BB) | true;
+bool SimplifyCFGOpt::SimplifySwitch(SwitchInst *SI) {
+  // If this switch is too complex to want to look at, ignore it.
+  if (!isValueEqualityComparison(SI))
+    return false;
+
+  BasicBlock *BB = SI->getParent();
 
-      // Scan predecessor blocks for conditional branches.
-      for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
-        if (BranchInst *PBI = dyn_cast<BranchInst>((*PI)->getTerminator()))
-          if (PBI != BI && PBI->isConditional())
-            if (SimplifyCondBranchToCondBranch(PBI, BI))
-              return SimplifyCFG(BB) | true;
-    }
-  } else if (isa<UnreachableInst>(BB->getTerminator())) {
-    // If there are any instructions immediately before the unreachable that can
-    // be removed, do so.
-    Instruction *Unreachable = BB->getTerminator();
-    while (Unreachable != BB->begin()) {
-      BasicBlock::iterator BBI = Unreachable;
-      --BBI;
-      // Do not delete instructions that can have side effects, like calls
-      // (which may never return) and volatile loads and stores.
-      if (isa<CallInst>(BBI) && !isa<DbgInfoIntrinsic>(BBI)) break;
-
-      if (StoreInst *SI = dyn_cast<StoreInst>(BBI))
-        if (SI->isVolatile())
-          break;
-
-      if (LoadInst *LI = dyn_cast<LoadInst>(BBI))
-        if (LI->isVolatile())
-          break;
+  // If we only have one predecessor, and if it is a branch on this value,
+  // see if that predecessor totally determines the outcome of this switch.
+  if (BasicBlock *OnlyPred = BB->getSinglePredecessor())
+    if (SimplifyEqualityComparisonWithOnlyPredecessor(SI, OnlyPred))
+      return SimplifyCFG(BB) || 1;
+  
+  // If the block only contains the switch, see if we can fold the block
+  // away into any preds.
+  BasicBlock::iterator BBI = BB->begin();
+  // Ignore dbg intrinsics.
+  while (isa<DbgInfoIntrinsic>(BBI))
+    ++BBI;
+  if (SI == &*BBI)
+    if (FoldValueComparisonIntoPredecessors(SI))
+      return SimplifyCFG(BB) || 1;
+  
+  return false;
+}
 
-      // Delete this instruction
-      BB->getInstList().erase(BBI);
+bool SimplifyCFGOpt::SimplifyIndirectBr(IndirectBrInst *IBI) {
+  BasicBlock *BB = IBI->getParent();
+  bool Changed = false;
+  
+  // Eliminate redundant destinations.
+  SmallPtrSet<Value *, 8> Succs;
+  for (unsigned i = 0, e = IBI->getNumDestinations(); i != e; ++i) {
+    BasicBlock *Dest = IBI->getDestination(i);
+    if (!Dest->hasAddressTaken() || !Succs.insert(Dest)) {
+      Dest->removePredecessor(BB);
+      IBI->removeDestination(i);
+      --i; --e;
       Changed = true;
     }
+  } 
 
-    // If the unreachable instruction is the first in the block, take a gander
-    // at all of the predecessors of this instruction, and simplify them.
-    if (&BB->front() == Unreachable) {
-      SmallVector<BasicBlock*, 8> Preds(pred_begin(BB), pred_end(BB));
-      for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
-        TerminatorInst *TI = Preds[i]->getTerminator();
-
-        if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
-          if (BI->isUnconditional()) {
-            if (BI->getSuccessor(0) == BB) {
-              new UnreachableInst(TI->getContext(), TI);
-              TI->eraseFromParent();
-              Changed = true;
-            }
-          } else {
-            if (BI->getSuccessor(0) == BB) {
-              BranchInst::Create(BI->getSuccessor(1), BI);
-              EraseTerminatorInstAndDCECond(BI);
-            } else if (BI->getSuccessor(1) == BB) {
-              BranchInst::Create(BI->getSuccessor(0), BI);
-              EraseTerminatorInstAndDCECond(BI);
-              Changed = true;
-            }
-          }
-        } else if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) {
-          for (unsigned i = 1, e = SI->getNumCases(); i != e; ++i)
-            if (SI->getSuccessor(i) == BB) {
-              BB->removePredecessor(SI->getParent());
-              SI->removeCase(i);
-              --i; --e;
-              Changed = true;
-            }
-          // If the default value is unreachable, figure out the most popular
-          // destination and make it the default.
-          if (SI->getSuccessor(0) == BB) {
-            std::map<BasicBlock*, unsigned> Popularity;
-            for (unsigned i = 1, e = SI->getNumCases(); i != e; ++i)
-              Popularity[SI->getSuccessor(i)]++;
-
-            // Find the most popular block.
-            unsigned MaxPop = 0;
-            BasicBlock *MaxBlock = 0;
-            for (std::map<BasicBlock*, unsigned>::iterator
-                   I = Popularity.begin(), E = Popularity.end(); I != E; ++I) {
-              if (I->second > MaxPop) {
-                MaxPop = I->second;
-                MaxBlock = I->first;
-              }
-            }
-            if (MaxBlock) {
-              // Make this the new default, allowing us to delete any explicit
-              // edges to it.
-              SI->setSuccessor(0, MaxBlock);
-              Changed = true;
-
-              // If MaxBlock has phinodes in it, remove MaxPop-1 entries from
-              // it.
-              if (isa<PHINode>(MaxBlock->begin()))
-                for (unsigned i = 0; i != MaxPop-1; ++i)
-                  MaxBlock->removePredecessor(SI->getParent());
-
-              for (unsigned i = 1, e = SI->getNumCases(); i != e; ++i)
-                if (SI->getSuccessor(i) == MaxBlock) {
-                  SI->removeCase(i);
-                  --i; --e;
-                }
-            }
-          }
-        } else if (InvokeInst *II = dyn_cast<InvokeInst>(TI)) {
-          if (II->getUnwindDest() == BB) {
-            // Convert the invoke to a call instruction.  This would be a good
-            // place to note that the call does not throw though.
-            BranchInst *BI = BranchInst::Create(II->getNormalDest(), II);
-            II->removeFromParent();   // Take out of symbol table
-
-            // Insert the call now...
-            SmallVector<Value*, 8> Args(II->op_begin(), II->op_end()-3);
-            CallInst *CI = CallInst::Create(II->getCalledValue(),
-                                            Args.begin(), Args.end(),
-                                            II->getName(), BI);
-            CI->setCallingConv(II->getCallingConv());
-            CI->setAttributes(II->getAttributes());
-            // If the invoke produced a value, the call does now instead.
-            II->replaceAllUsesWith(CI);
-            delete II;
-            Changed = true;
-          }
-        }
-      }
+  if (IBI->getNumDestinations() == 0) {
+    // If the indirectbr has no successors, change it to unreachable.
+    new UnreachableInst(IBI->getContext(), IBI);
+    EraseTerminatorInstAndDCECond(IBI);
+    return true;
+  }
+  
+  if (IBI->getNumDestinations() == 1) {
+    // If the indirectbr has one successor, change it to a direct branch.
+    BranchInst::Create(IBI->getDestination(0), IBI);
+    EraseTerminatorInstAndDCECond(IBI);
+    return true;
+  }
+  
+  if (SelectInst *SI = dyn_cast<SelectInst>(IBI->getAddress())) {
+    if (SimplifyIndirectBrOnSelect(IBI, SI))
+      return SimplifyCFG(BB) | true;
+  }
+  return Changed;
+}
 
-      // If this block is now dead, remove it.
-      if (pred_begin(BB) == pred_end(BB) && BB != &Fn->getEntryBlock()) {
-        // We know there are no successors, so just nuke the block.
-        Fn->getBasicBlockList().erase(BB);
+bool SimplifyCFGOpt::SimplifyUncondBranch(BranchInst *BI) {
+  BasicBlock *BB = BI->getParent();
+  
+  // If the Terminator is the only non-phi instruction, simplify the block.
+  BasicBlock::iterator I = BB->getFirstNonPHIOrDbg();
+  if (I->isTerminator() && BB != &BB->getParent()->getEntryBlock() &&
+      TryToSimplifyUncondBranchFromEmptyBlock(BB))
+    return true;
+  
+  // If the only instruction in the block is a seteq/setne comparison
+  // against a constant, try to simplify the block.
+  if (ICmpInst *ICI = dyn_cast<ICmpInst>(I))
+    if (ICI->isEquality() && isa<ConstantInt>(ICI->getOperand(1))) {
+      for (++I; isa<DbgInfoIntrinsic>(I); ++I)
+        ;
+      if (I->isTerminator() && TryToSimplifyUncondBranchWithICmpInIt(ICI))
         return true;
-      }
     }
-  } else if (IndirectBrInst *IBI =
-               dyn_cast<IndirectBrInst>(BB->getTerminator())) {
-    // Eliminate redundant destinations.
-    SmallPtrSet<Value *, 8> Succs;
-    for (unsigned i = 0, e = IBI->getNumDestinations(); i != e; ++i) {
-      BasicBlock *Dest = IBI->getDestination(i);
-      if (!Dest->hasAddressTaken() || !Succs.insert(Dest)) {
-        Dest->removePredecessor(BB);
-        IBI->removeDestination(i);
-        --i; --e;
-        Changed = true;
-      }
-    } 
+  
+  return false;
+}
 
-    if (IBI->getNumDestinations() == 0) {
-      // If the indirectbr has no successors, change it to unreachable.
-      new UnreachableInst(IBI->getContext(), IBI);
-      EraseTerminatorInstAndDCECond(IBI);
-      Changed = true;
-    } else if (IBI->getNumDestinations() == 1) {
-      // If the indirectbr has one successor, change it to a direct branch.
-      BranchInst::Create(IBI->getDestination(0), IBI);
-      EraseTerminatorInstAndDCECond(IBI);
-      Changed = true;
-    } else if (SelectInst *SI = dyn_cast<SelectInst>(IBI->getAddress())) {
-      if (SimplifyIndirectBrOnSelect(IBI, SI))
+
+bool SimplifyCFGOpt::SimplifyCondBranch(BranchInst *BI) {
+  BasicBlock *BB = BI->getParent();
+  
+  // Conditional branch
+  if (isValueEqualityComparison(BI)) {
+    // If we only have one predecessor, and if it is a branch on this value,
+    // see if that predecessor totally determines the outcome of this
+    // switch.
+    if (BasicBlock *OnlyPred = BB->getSinglePredecessor())
+      if (SimplifyEqualityComparisonWithOnlyPredecessor(BI, OnlyPred))
+        return SimplifyCFG(BB) | true;
+    
+    // This block must be empty, except for the setcond inst, if it exists.
+    // Ignore dbg intrinsics.
+    BasicBlock::iterator I = BB->begin();
+    // Ignore dbg intrinsics.
+    while (isa<DbgInfoIntrinsic>(I))
+      ++I;
+    if (&*I == BI) {
+      if (FoldValueComparisonIntoPredecessors(BI))
+        return SimplifyCFG(BB) | true;
+    } else if (&*I == cast<Instruction>(BI->getCondition())){
+      ++I;
+      // Ignore dbg intrinsics.
+      while (isa<DbgInfoIntrinsic>(I))
+        ++I;
+      if (&*I == BI && FoldValueComparisonIntoPredecessors(BI))
         return SimplifyCFG(BB) | true;
     }
   }
+  
+  // Try to turn "br (X == 0 | X == 1), T, F" into a switch instruction.
+  if (SimplifyBranchOnICmpChain(BI, TD))
+    return true;
+  
+  // We have a conditional branch to two blocks that are only reachable
+  // from BI.  We know that the condbr dominates the two blocks, so see if
+  // there is any identical code in the "then" and "else" blocks.  If so, we
+  // can hoist it up to the branching block.
+  if (BI->getSuccessor(0)->getSinglePredecessor() != 0) {
+    if (BI->getSuccessor(1)->getSinglePredecessor() != 0) {
+      if (HoistThenElseCodeToIf(BI))
+        return SimplifyCFG(BB) | true;
+    } else {
+      // If Successor #1 has multiple preds, we may be able to conditionally
+      // execute Successor #0 if it branches to successor #1.
+      TerminatorInst *Succ0TI = BI->getSuccessor(0)->getTerminator();
+      if (Succ0TI->getNumSuccessors() == 1 &&
+          Succ0TI->getSuccessor(0) == BI->getSuccessor(1))
+        if (SpeculativelyExecuteBB(BI, BI->getSuccessor(0)))
+          return SimplifyCFG(BB) | true;
+    }
+  } else if (BI->getSuccessor(1)->getSinglePredecessor() != 0) {
+    // If Successor #0 has multiple preds, we may be able to conditionally
+    // execute Successor #1 if it branches to successor #0.
+    TerminatorInst *Succ1TI = BI->getSuccessor(1)->getTerminator();
+    if (Succ1TI->getNumSuccessors() == 1 &&
+        Succ1TI->getSuccessor(0) == BI->getSuccessor(0))
+      if (SpeculativelyExecuteBB(BI, BI->getSuccessor(1)))
+        return SimplifyCFG(BB) | true;
+  }
+  
+  // If this is a branch on a phi node in the current block, thread control
+  // through this block if any PHI node entries are constants.
+  if (PHINode *PN = dyn_cast<PHINode>(BI->getCondition()))
+    if (PN->getParent() == BI->getParent())
+      if (FoldCondBranchOnPHI(BI))
+        return SimplifyCFG(BB) | true;
+  
+  // If this basic block is ONLY a setcc and a branch, and if a predecessor
+  // branches to us and one of our successors, fold the setcc into the
+  // predecessor and use logical operations to pick the right destination.
+  if (FoldBranchToCommonDest(BI))
+    return SimplifyCFG(BB) | true;
+  
+  // Scan predecessor blocks for conditional branches.
+  for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
+    if (BranchInst *PBI = dyn_cast<BranchInst>((*PI)->getTerminator()))
+      if (PBI != BI && PBI->isConditional())
+        if (SimplifyCondBranchToCondBranch(PBI, BI))
+          return SimplifyCFG(BB) | true;
+
+  return false;
+}
+
+bool SimplifyCFGOpt::run(BasicBlock *BB) {
+  bool Changed = false;
+  Function *Fn = BB->getParent();
+
+  assert(BB && Fn && "Block not embedded in function!");
+  assert(BB->getTerminator() && "Degenerate basic block encountered!");
+
+  // Remove basic blocks that have no predecessors (except the entry block)...
+  // or that just have themself as a predecessor.  These are unreachable.
+  if ((pred_begin(BB) == pred_end(BB) && BB != &Fn->getEntryBlock()) ||
+      BB->getSinglePredecessor() == BB) {
+    DEBUG(dbgs() << "Removing BB: \n" << *BB);
+    DeleteDeadBlock(BB);
+    return true;
+  }
+
+  // Check to see if we can constant propagate this terminator instruction
+  // away...
+  Changed |= ConstantFoldTerminator(BB);
+
+  // Check for and eliminate duplicate PHI nodes in this block.
+  Changed |= EliminateDuplicatePHINodes(BB);
+
+  // Merge basic blocks into their predecessor if there is only one distinct
+  // pred, and if there is only one distinct successor of the predecessor, and
+  // if there are no PHI nodes.
+  //
+  if (MergeBlockIntoPredecessor(BB))
+    return true;
+  
+  // If there is a trivial two-entry PHI node in this basic block, and we can
+  // eliminate it, do so now.
+  if (PHINode *PN = dyn_cast<PHINode>(BB->begin()))
+    if (PN->getNumIncomingValues() == 2)
+      Changed |= FoldTwoEntryPHINode(PN); 
+
+  if (BranchInst *BI = dyn_cast<BranchInst>(BB->getTerminator())) {
+    if (BI->isUnconditional())
+      return SimplifyUncondBranch(BI) | Changed;
+    
+    return SimplifyCondBranch(BI) | Changed;
+  }
+
+  if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator()))
+    return SimplifyReturn(RI) | Changed;
+  
+  if (SwitchInst *SI = dyn_cast<SwitchInst>(BB->getTerminator()))
+    return SimplifySwitch(SI) | Changed;
+  
+  if (UnreachableInst *UI = dyn_cast<UnreachableInst>(BB->getTerminator()))
+    return SimplifyUnreachable(UI) | Changed;
+  
+  if (UnwindInst *UI = dyn_cast<UnwindInst>(BB->getTerminator()))
+    return SimplifyUnwind(UI) | Changed;
+  
+  if (IndirectBrInst *IBI = dyn_cast<IndirectBrInst>(BB->getTerminator()))
+    return SimplifyIndirectBr(IBI) | Changed;
 
   return Changed;
 }



From sabre at nondot.org  Mon Dec 13 00:36:51 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 06:36:51 -0000
Subject: [llvm-commits] [llvm] r121689 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101213063651.3752F2A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 00:36:51 2010
New Revision: 121689

URL: http://llvm.org/viewvc/llvm-project?rev=121689&view=rev
Log:
make this logic a bit simpler.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121689&r1=121688&r2=121689&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 00:36:51 2010
@@ -2200,7 +2200,7 @@
   // see if that predecessor totally determines the outcome of this switch.
   if (BasicBlock *OnlyPred = BB->getSinglePredecessor())
     if (SimplifyEqualityComparisonWithOnlyPredecessor(SI, OnlyPred))
-      return SimplifyCFG(BB) || 1;
+      return SimplifyCFG(BB) | true;
   
   // If the block only contains the switch, see if we can fold the block
   // away into any preds.
@@ -2210,7 +2210,7 @@
     ++BBI;
   if (SI == &*BBI)
     if (FoldValueComparisonIntoPredecessors(SI))
-      return SimplifyCFG(BB) || 1;
+      return SimplifyCFG(BB) | true;
   
   return false;
 }
@@ -2397,27 +2397,26 @@
       Changed |= FoldTwoEntryPHINode(PN); 
 
   if (BranchInst *BI = dyn_cast<BranchInst>(BB->getTerminator())) {
-    if (BI->isUnconditional())
-      return SimplifyUncondBranch(BI) | Changed;
-    
-    return SimplifyCondBranch(BI) | Changed;
+    if (BI->isUnconditional()) {
+      if (SimplifyUncondBranch(BI)) return true;
+    } else {
+      if (SimplifyCondBranch(BI))
+        return true;
+    }
+  } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
+    if (SimplifyReturn(RI)) return true;
+  } else if (SwitchInst *SI = dyn_cast<SwitchInst>(BB->getTerminator())) {
+    if (SimplifySwitch(SI)) return true;
+  } else if (UnreachableInst *UI =
+               dyn_cast<UnreachableInst>(BB->getTerminator())) {
+    if (SimplifyUnreachable(UI)) return true;
+  } else if (UnwindInst *UI = dyn_cast<UnwindInst>(BB->getTerminator())) {
+    if (SimplifyUnwind(UI)) return true;
+  } else if (IndirectBrInst *IBI =
+               dyn_cast<IndirectBrInst>(BB->getTerminator())) {
+    if (SimplifyIndirectBr(IBI)) return true;
   }
 
-  if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator()))
-    return SimplifyReturn(RI) | Changed;
-  
-  if (SwitchInst *SI = dyn_cast<SwitchInst>(BB->getTerminator()))
-    return SimplifySwitch(SI) | Changed;
-  
-  if (UnreachableInst *UI = dyn_cast<UnreachableInst>(BB->getTerminator()))
-    return SimplifyUnreachable(UI) | Changed;
-  
-  if (UnwindInst *UI = dyn_cast<UnwindInst>(BB->getTerminator()))
-    return SimplifyUnwind(UI) | Changed;
-  
-  if (IndirectBrInst *IBI = dyn_cast<IndirectBrInst>(BB->getTerminator()))
-    return SimplifyIndirectBr(IBI) | Changed;
-
   return Changed;
 }
 



From sabre at nondot.org  Mon Dec 13 01:00:06 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 07:00:06 -0000
Subject: [llvm-commits] [llvm] r121690 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101213070006.9EA102A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 01:00:06 2010
New Revision: 121690

URL: http://llvm.org/viewvc/llvm-project?rev=121690&view=rev
Log:
Make simplifycfg reprocess newly formed "br (cond1 | cond2)" conditions
when simplifying, allowing them to be eagerly turned into switches.  This
is the last step required to get "Example 7" from this blog post:
http://blog.regehr.org/archives/320

On X86, we now generate this machine code, which (to my eye) seems better
than the ICC generated code:

_crud:                                  ## @crud
## BB#0:                                ## %entry
	cmpb	$33, %dil
	jb	LBB0_4
## BB#1:                                ## %switch.early.test
	addb	$-34, %dil
	cmpb	$58, %dil
	ja	LBB0_3
## BB#2:                                ## %switch.early.test
	movzbl	%dil, %eax
	movabsq	$288230376537592865, %rcx ## imm = 0x400000017001421
	btq	%rax, %rcx
	jb	LBB0_4
LBB0_3:                                 ## %lor.rhs
	xorl	%eax, %eax
	ret
LBB0_4:                                 ## %lor.end
	movl	$1, %eax
	ret


Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121690&r1=121689&r2=121690&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 01:00:06 2010
@@ -1357,7 +1357,7 @@
   // must be at the front of the block.
   BasicBlock::iterator FrontIt = BB->front();
   // Ignore dbg intrinsics.
-  while(isa<DbgInfoIntrinsic>(FrontIt))
+  while (isa<DbgInfoIntrinsic>(FrontIt))
     ++FrontIt;
     
   // Allow a single instruction to be hoisted in addition to the compare
@@ -1441,7 +1441,7 @@
         UsedValues.erase(Pair.first);
         if (UsedValues.empty()) break;
         
-        if (Instruction* I = dyn_cast<Instruction>(Pair.first)) {
+        if (Instruction *I = dyn_cast<Instruction>(Pair.first)) {
           for (Instruction::op_iterator OI = I->op_begin(), OE = I->op_end();
                OI != OE; ++OI)
             Worklist.push_back(std::make_pair(OI->get(), Pair.second+1));
@@ -1469,9 +1469,16 @@
     
     // If we need to invert the condition in the pred block to match, do so now.
     if (InvertPredCond) {
-      Value *NewCond =
-        BinaryOperator::CreateNot(PBI->getCondition(),
+      Value *NewCond = PBI->getCondition();
+      
+      if (NewCond->hasOneUse() && isa<CmpInst>(NewCond)) {
+        CmpInst *CI = cast<CmpInst>(NewCond);
+        CI->setPredicate(CI->getInversePredicate());
+      } else {
+        NewCond = BinaryOperator::CreateNot(NewCond,
                                   PBI->getCondition()->getName()+".not", PBI);
+      }
+      
       PBI->setCondition(NewCond);
       BasicBlock *OldTrue = PBI->getSuccessor(0);
       BasicBlock *OldFalse = PBI->getSuccessor(1);
@@ -1507,7 +1514,7 @@
       AddPredecessorToBlock(FalseDest, PredBlock, BB);
       PBI->setSuccessor(1, FalseDest);
     }
-    return true;
+    return SimplifyCFG(PBI->getParent()) | true;
   }
   return false;
 }

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121690&r1=121689&r2=121690&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 01:00:06 2010
@@ -203,5 +203,70 @@
 ; CHECK:     i8 97, label %if.then
 ; CHECK:   ]
 ; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
+}
+
+define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
+entry:
+  %cmp = icmp ult i8 %c, 33
+  br i1 %cmp, label %lor.end, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %entry
+  %cmp4 = icmp eq i8 %c, 46
+  br i1 %cmp4, label %lor.end, label %lor.lhs.false6
+
+lor.lhs.false6:                                   ; preds = %lor.lhs.false
+  %cmp9 = icmp eq i8 %c, 44
+  br i1 %cmp9, label %lor.end, label %lor.lhs.false11
+
+lor.lhs.false11:                                  ; preds = %lor.lhs.false6
+  %cmp14 = icmp eq i8 %c, 58
+  br i1 %cmp14, label %lor.end, label %lor.lhs.false16
+
+lor.lhs.false16:                                  ; preds = %lor.lhs.false11
+  %cmp19 = icmp eq i8 %c, 59
+  br i1 %cmp19, label %lor.end, label %lor.lhs.false21
+
+lor.lhs.false21:                                  ; preds = %lor.lhs.false16
+  %cmp24 = icmp eq i8 %c, 60
+  br i1 %cmp24, label %lor.end, label %lor.lhs.false26
+
+lor.lhs.false26:                                  ; preds = %lor.lhs.false21
+  %cmp29 = icmp eq i8 %c, 62
+  br i1 %cmp29, label %lor.end, label %lor.lhs.false31
 
+lor.lhs.false31:                                  ; preds = %lor.lhs.false26
+  %cmp34 = icmp eq i8 %c, 34
+  br i1 %cmp34, label %lor.end, label %lor.lhs.false36
+
+lor.lhs.false36:                                  ; preds = %lor.lhs.false31
+  %cmp39 = icmp eq i8 %c, 92
+  br i1 %cmp39, label %lor.end, label %lor.rhs
+
+lor.rhs:                                          ; preds = %lor.lhs.false36
+  %cmp43 = icmp eq i8 %c, 39
+  br label %lor.end
+
+lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
+  %0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
+  %conv46 = zext i1 %0 to i32
+  ret i32 %conv46
+  
+; CHECK: @test9
+; CHECK:   %cmp = icmp ult i8 %c, 33
+; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
+
+; CHECK: switch.early.test:
+; CHECK:   switch i8 %c, label %lor.rhs [
+; CHECK:     i8 46, label %lor.end
+; CHECK:     i8 44, label %lor.end
+; CHECK:     i8 58, label %lor.end
+; CHECK:     i8 59, label %lor.end
+; CHECK:     i8 60, label %lor.end
+; CHECK:     i8 62, label %lor.end
+; CHECK:     i8 34, label %lor.end
+; CHECK:     i8 92, label %lor.end
+; CHECK:     i8 39, label %lor.end
+; CHECK:   ]
 }
+
+



From sabre at nondot.org  Mon Dec 13 01:35:47 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 07:35:47 -0000
Subject: [llvm-commits] [llvm] r121691 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Message-ID: <20101213073547.2CEE22A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 01:35:47 2010
New Revision: 121691

URL: http://llvm.org/viewvc/llvm-project?rev=121691&view=rev
Log:
remove the verbose-asm "constant pool double" comments that we were printing
for each constant pool entry.  Using WriteTypeSymbolic here takes time
proportional to the size of the module, for each constant pool entry.

This speeds up -verbose-asm llc on 252.eon (a random testcase at my disposal)
from 4.4s to 2.137s.  llc takes 2.11s with asm-verbose off, so this is now a
pretty reasonable cost for verbose comments.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=121691&r1=121690&r2=121691&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon Dec 13 01:35:47 2010
@@ -920,14 +920,6 @@
 
       const Type *Ty = CPE.getType();
       Offset = NewOffset + TM.getTargetData()->getTypeAllocSize(Ty);
-
-      // Emit the label with a comment on it.
-      if (isVerbose()) {
-        OutStreamer.GetCommentOS() << "constant pool ";
-        WriteTypeSymbolic(OutStreamer.GetCommentOS(), CPE.getType(),
-                          MF->getFunction()->getParent());
-        OutStreamer.GetCommentOS() << '\n';
-      }
       OutStreamer.EmitLabel(GetCPISymbol(CPI));
 
       if (CPE.isMachineConstantPoolEntry())



From sabre at nondot.org  Mon Dec 13 01:41:29 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 07:41:29 -0000
Subject: [llvm-commits] [llvm] r121693 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101213074129.A15B02A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 01:41:29 2010
New Revision: 121693

URL: http://llvm.org/viewvc/llvm-project?rev=121693&view=rev
Log:
Completely disable the optimization I added in r121680 until
I can track down a miscompile.  This should bring the buildbots
back to life

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121693&r1=121692&r2=121693&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 01:41:29 2010
@@ -331,8 +331,8 @@
                                             isEQ)) {
       if (LHS == RHS)
         return LHS;
+      Vals.resize(NumVals);
     }
-    Vals.resize(NumVals);
 
     // The RHS of the or/and can't be folded in and we haven't used "Extra" yet,
     // set it and return success.
@@ -348,12 +348,13 @@
   // If the LHS can't be folded in, but Extra is available and RHS can, try to
   // use LHS as Extra.
   if (Extra == 0 || Extra == I->getOperand(0)) {
+    Value *OldExtra = Extra;
     Extra = I->getOperand(0);
     if (Value *RHS = GatherConstantCompares(I->getOperand(1), Vals, Extra, TD,
                                             isEQ))
       return RHS;
-    Vals.resize(NumValsBeforeLHS);
-    Extra = 0;
+    assert(Vals.size() == NumValsBeforeLHS);
+    Extra = OldExtra;
   }
   
   return 0;
@@ -1908,6 +1909,8 @@
   // then we evaluate them with an explicit branch first.  Split the block
   // right before the condbr to handle it.
   if (ExtraCase) {
+    return false;
+    
     BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
     // Remove the uncond branch added to the old block.
     TerminatorInst *OldTI = BB->getTerminator();

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121693&r1=121692&r2=121693&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 01:41:29 2010
@@ -168,13 +168,13 @@
   ret void
   
 ; CHECK: @test7
-; CHECK:   %cmp = icmp ult i32 %x, 32
-; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
+; HECK:   %cmp = icmp ult i32 %x, 32
+; HECK:   br i1 %cmp, label %if.then, label %switch.early.test
+; HECK: switch.early.test:
+; HECK:   switch i8 %c, label %if.end [
+; HECK:     i8 99, label %if.then
+; HECK:     i8 97, label %if.then
+; HECK:   ]
 }
 
 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
@@ -197,14 +197,15 @@
   ret i32 0
   
 ; CHECK: @test8
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %if.end [
-; CHECK:     i8 99, label %if.then
-; CHECK:     i8 97, label %if.then
-; CHECK:   ]
-; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
+; HECK: switch.early.test:
+; HECK:   switch i8 %c, label %if.end [
+; HECK:     i8 99, label %if.then
+; HECK:     i8 97, label %if.then
+; HECK:   ]
+; HECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
 }
 
+;; This is "Example 7" from http://blog.regehr.org/archives/320
 define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
 entry:
   %cmp = icmp ult i8 %c, 33
@@ -253,20 +254,20 @@
   
 ; CHECK: @test9
 ; CHECK:   %cmp = icmp ult i8 %c, 33
-; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
+; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %lor.rhs [
-; CHECK:     i8 46, label %lor.end
-; CHECK:     i8 44, label %lor.end
-; CHECK:     i8 58, label %lor.end
-; CHECK:     i8 59, label %lor.end
-; CHECK:     i8 60, label %lor.end
-; CHECK:     i8 62, label %lor.end
-; CHECK:     i8 34, label %lor.end
-; CHECK:     i8 92, label %lor.end
-; CHECK:     i8 39, label %lor.end
-; CHECK:   ]
+; HECK: switch.early.test:
+; HECK:   switch i8 %c, label %lor.rhs [
+; HECK:     i8 46, label %lor.end
+; HECK:     i8 44, label %lor.end
+; HECK:     i8 58, label %lor.end
+; HECK:     i8 59, label %lor.end
+; HECK:     i8 60, label %lor.end
+; HECK:     i8 62, label %lor.end
+; HECK:     i8 34, label %lor.end
+; HECK:     i8 92, label %lor.end
+; HECK:     i8 39, label %lor.end
+; HECK:   ]
 }
 
 



From sabre at nondot.org  Mon Dec 13 02:12:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 08:12:20 -0000
Subject: [llvm-commits] [llvm] r121695 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101213081220.3239D2A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 02:12:19 2010
New Revision: 121695

URL: http://llvm.org/viewvc/llvm-project?rev=121695&view=rev
Log:
reinstate my patch: the miscompile was caused by an inverted branch in the
'and' case.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121695&r1=121694&r2=121695&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 02:12:19 2010
@@ -1909,13 +1909,15 @@
   // then we evaluate them with an explicit branch first.  Split the block
   // right before the condbr to handle it.
   if (ExtraCase) {
-    return false;
-    
     BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
     // Remove the uncond branch added to the old block.
     TerminatorInst *OldTI = BB->getTerminator();
     
-    BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
+    if (TrueWhenEqual)
+      BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
+    else
+      BranchInst::Create(NewBB, EdgeBB, ExtraCase, OldTI);
+      
     OldTI->eraseFromParent();
     
     // If there are PHI nodes in EdgeBB, then we need to add a new entry to them
@@ -1955,6 +1957,7 @@
   
   // Erase the old branch instruction.
   EraseTerminatorInstAndDCECond(BI);
+  
   return true;
 }
 

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121695&r1=121694&r2=121695&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 02:12:19 2010
@@ -168,13 +168,13 @@
   ret void
   
 ; CHECK: @test7
-; HECK:   %cmp = icmp ult i32 %x, 32
-; HECK:   br i1 %cmp, label %if.then, label %switch.early.test
-; HECK: switch.early.test:
-; HECK:   switch i8 %c, label %if.end [
-; HECK:     i8 99, label %if.then
-; HECK:     i8 97, label %if.then
-; HECK:   ]
+; CHECK:   %cmp = icmp ult i32 %x, 32
+; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
+; CHECK: switch.early.test:
+; CHECK:   switch i8 %c, label %if.end [
+; CHECK:     i8 99, label %if.then
+; CHECK:     i8 97, label %if.then
+; CHECK:   ]
 }
 
 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
@@ -197,12 +197,12 @@
   ret i32 0
   
 ; CHECK: @test8
-; HECK: switch.early.test:
-; HECK:   switch i8 %c, label %if.end [
-; HECK:     i8 99, label %if.then
-; HECK:     i8 97, label %if.then
-; HECK:   ]
-; HECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
+; CHECK: switch.early.test:
+; CHECK:   switch i8 %c, label %if.end [
+; CHECK:     i8 99, label %if.then
+; CHECK:     i8 97, label %if.then
+; CHECK:   ]
+; CHECK:   %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
 }
 
 ;; This is "Example 7" from http://blog.regehr.org/archives/320
@@ -254,20 +254,41 @@
   
 ; CHECK: @test9
 ; CHECK:   %cmp = icmp ult i8 %c, 33
-; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
+; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
-; HECK: switch.early.test:
-; HECK:   switch i8 %c, label %lor.rhs [
-; HECK:     i8 46, label %lor.end
-; HECK:     i8 44, label %lor.end
-; HECK:     i8 58, label %lor.end
-; HECK:     i8 59, label %lor.end
-; HECK:     i8 60, label %lor.end
-; HECK:     i8 62, label %lor.end
-; HECK:     i8 34, label %lor.end
-; HECK:     i8 92, label %lor.end
-; HECK:     i8 39, label %lor.end
-; HECK:   ]
+; CHECK: switch.early.test:
+; CHECK:   switch i8 %c, label %lor.rhs [
+; CHECK:     i8 46, label %lor.end
+; CHECK:     i8 44, label %lor.end
+; CHECK:     i8 58, label %lor.end
+; CHECK:     i8 59, label %lor.end
+; CHECK:     i8 60, label %lor.end
+; CHECK:     i8 62, label %lor.end
+; CHECK:     i8 34, label %lor.end
+; CHECK:     i8 92, label %lor.end
+; CHECK:     i8 39, label %lor.end
+; CHECK:   ]
 }
 
+define i32 @test10(i32 %mode, i1 %Cond) {
+  %A = icmp ne i32 %mode, 0
+  %B = icmp ne i32 %mode, 51
+  %C = and i1 %A, %B
+  %D = and i1 %C, %Cond
+  br i1 %D, label %T, label %F
+T:
+  ret i32 123
+F:
+  ret i32 324
+
+; CHECK: @test10
+; CHECK:  br i1 %Cond, label %switch.early.test, label %F
+; CHECK:switch.early.test:
+; CHECK:  switch i32 %mode, label %T [
+; CHECK:    i32 51, label %F
+; CHECK:    i32 0, label %F
+; CHECK:  ]
+}
+
+
 



From sabre at nondot.org  Mon Dec 13 02:39:01 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 08:39:01 -0000
Subject: [llvm-commits] [llvm] r121696 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
 test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
Message-ID: <20101213083902.0392A2A6C12D@llvm.org>

Author: lattner
Date: Mon Dec 13 02:39:01 2010
New Revision: 121696

URL: http://llvm.org/viewvc/llvm-project?rev=121696&view=rev
Log:
Add a couple dag combines to transform mulhi/mullo into a wider multiply
when the wider type is legal.  This allows us to compile:

define zeroext i16 @test1(i16 zeroext %x) nounwind {
entry:
	%div = udiv i16 %x, 33
	ret i16 %div
}

into:

test1:                                  # @test1
	movzwl	4(%esp), %eax
	imull	$63551, %eax, %eax      # imm = 0xF83F
	shrl	$21, %eax
	ret

instead of:

test1:                                  # @test1
        movw    $-1985, %ax             # imm = 0xFFFFFFFFFFFFF83F
        mulw    4(%esp)
        andl    $65504, %edx            # imm = 0xFFE0
        movl    %edx, %eax
        shrl    $5, %eax
        ret

Implementing rdar://8760399 and example #4 from:
http://blog.regehr.org/archives/320

We should implement the same thing for [su]mul_hilo, but I don't
have immediate plans to do this.



Removed:
    llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=121696&r1=121695&r2=121696&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 13 02:39:01 2010
@@ -1916,6 +1916,7 @@
   SDValue N1 = N->getOperand(1);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   EVT VT = N->getValueType(0);
+  DebugLoc DL = N->getDebugLoc();
 
   // fold (mulhs x, 0) -> 0
   if (N1C && N1C->isNullValue())
@@ -1929,6 +1930,22 @@
   if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
     return DAG.getConstant(0, VT);
 
+  // If the type twice as wide is legal, transform the mulhs to a wider multiply
+  // plus a shift.
+  if (VT.isSimple() && !VT.isVector()) {
+    MVT Simple = VT.getSimpleVT();
+    unsigned SimpleSize = Simple.getSizeInBits();
+    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
+    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
+      N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
+      N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
+      N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
+      N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1,
+                       DAG.getConstant(SimpleSize, getShiftAmountTy()));
+      return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
+    }
+  }
+  
   return SDValue();
 }
 
@@ -1937,6 +1954,7 @@
   SDValue N1 = N->getOperand(1);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   EVT VT = N->getValueType(0);
+  DebugLoc DL = N->getDebugLoc();
 
   // fold (mulhu x, 0) -> 0
   if (N1C && N1C->isNullValue())
@@ -1948,6 +1966,22 @@
   if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
     return DAG.getConstant(0, VT);
 
+  // If the type twice as wide is legal, transform the mulhu to a wider multiply
+  // plus a shift.
+  if (VT.isSimple() && !VT.isVector()) {
+    MVT Simple = VT.getSimpleVT();
+    unsigned SimpleSize = Simple.getSizeInBits();
+    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
+    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
+      N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
+      N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
+      N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
+      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
+                       DAG.getConstant(SimpleSize, getShiftAmountTy()));
+      return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
+    }
+  }
+  
   return SDValue();
 }
 
@@ -2011,6 +2045,7 @@
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
   if (Res.getNode()) return Res;
 
+  // TODO: Transform smul_lohi to mul if the wider mul is legal!
   return SDValue();
 }
 
@@ -2018,6 +2053,7 @@
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
   if (Res.getNode()) return Res;
 
+  // TODO: Transform umul_lohi to mul if the wider mul is legal!
   return SDValue();
 }
 

Modified: llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll?rev=121696&r1=121695&r2=121696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll Mon Dec 13 02:39:01 2010
@@ -1,9 +1,42 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1985 | count 1
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=0 | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
 target triple = "i686-pc-linux-gnu"
 
-define zeroext i16 @a(i16 zeroext %x) nounwind {
+define zeroext i16 @test1(i16 zeroext %x) nounwind {
 entry:
-	%div = udiv i16 %x, 33		; <i32> [#uses=1]
+	%div = udiv i16 %x, 33
+	ret i16 %div
+; CHECK: test1:
+; CHECK: imull	$63551, %eax, %eax
+; CHECK-NEXT: shrl	$21, %eax
+; CHECK-NEXT: ret
+}
+
+define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) nounwind readnone ssp noredzone {
+entry:
+  %div = udiv i16 %c, 3
+  ret i16 %div
+
+; CHECK: test2:
+; CHECK: imull	$43691, %eax, %eax
+; CHECK-NEXT: shrl	$17, %eax
+; CHECK-NEXT: ret
+}
+
+define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp noredzone {
+entry:
+  %div = udiv i8 %c, 3
+  ret i8 %div
+
+; CHECK: test3:
+; CHECK: imull	$171, %eax, %eax
+; CHECK-NEXT: shrb	%ah
+; CHECK-NEXT: movzbl	%ah, %eax
+; CHECK-NEXT: ret
+}
+
+define signext i16 @test4(i16 signext %x) nounwind {
+entry:
+	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
 	ret i16 %div
 }

Removed: llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll?rev=121695&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll (removed)
@@ -1,9 +0,0 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1985
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
-target triple = "i686-pc-linux-gnu"
-
-define signext i16 @a(i16 signext %x) nounwind {
-entry:
-	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
-	ret i16 %div
-}



From sabre at nondot.org  Mon Dec 13 02:39:40 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 08:39:40 -0000
Subject: [llvm-commits] [llvm] r121697 - in /llvm/trunk/test/CodeGen/X86:
 2008-11-29-DivideConstant16bit.ll divide-by-constant.ll
Message-ID: <20101213083940.5A2552A6C12D@llvm.org>

Author: lattner
Date: Mon Dec 13 02:39:40 2010
New Revision: 121697

URL: http://llvm.org/viewvc/llvm-project?rev=121697&view=rev
Log:
rename test

Added:
    llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
      - copied unchanged from r121696, llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
Removed:
    llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll

Removed: llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll?rev=121696&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=0 | FileCheck %s
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
-target triple = "i686-pc-linux-gnu"
-
-define zeroext i16 @test1(i16 zeroext %x) nounwind {
-entry:
-	%div = udiv i16 %x, 33
-	ret i16 %div
-; CHECK: test1:
-; CHECK: imull	$63551, %eax, %eax
-; CHECK-NEXT: shrl	$21, %eax
-; CHECK-NEXT: ret
-}
-
-define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) nounwind readnone ssp noredzone {
-entry:
-  %div = udiv i16 %c, 3
-  ret i16 %div
-
-; CHECK: test2:
-; CHECK: imull	$43691, %eax, %eax
-; CHECK-NEXT: shrl	$17, %eax
-; CHECK-NEXT: ret
-}
-
-define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp noredzone {
-entry:
-  %div = udiv i8 %c, 3
-  ret i8 %div
-
-; CHECK: test3:
-; CHECK: imull	$171, %eax, %eax
-; CHECK-NEXT: shrb	%ah
-; CHECK-NEXT: movzbl	%ah, %eax
-; CHECK-NEXT: ret
-}
-
-define signext i16 @test4(i16 signext %x) nounwind {
-entry:
-	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
-	ret i16 %div
-}



From fvbommel at gmail.com  Mon Dec 13 04:34:43 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Mon, 13 Dec 2010 11:34:43 +0100
Subject: [llvm-commits] [llvm] r121674 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <20101213034357.E8F7E2A6C12C@llvm.org>
References: <20101213034357.E8F7E2A6C12C@llvm.org>
Message-ID: <AANLkTi=mv7JE90AQ32_RfBh7h9RkiCh0G4AiHEH7RHO-@mail.gmail.com>

On Mon, Dec 13, 2010 at 4:43 AM, Chris Lattner <sabre at nondot.org> wrote:
> Author: lattner
> Date: Sun Dec 12 21:43:57 2010
> New Revision: 121674
>
> URL: http://llvm.org/viewvc/llvm-project?rev=121674&view=rev
> Log:
> Fix my previous patch to handle a degenerate case that the llvm-gcc
> bootstrap buildbot tripped over.
> + ?// Ok, the block is reachable from the default dest. ?If the constant we're
> + ?// comparing exists in one of the other edges, then we can constant fold ICI
> + ?// and zap it.
> + ?if (SI->findCaseValue(Cst) != 0) {

This should probably also make sure the successor for that case isn't
equal to BB. (Yes, this is an even *more* degenerate case since BB is
the default destination of the switch, but it's valid IR...)

> + ? ?Value *V;
> + ? ?if (ICI->getPredicate() == ICmpInst::ICMP_EQ)
> + ? ? ?V = ConstantInt::getFalse(BB->getContext());
> + ? ?else
> + ? ? ?V = ConstantInt::getTrue(BB->getContext());
> +
> + ? ?ICI->replaceAllUsesWith(V);
> + ? ?ICI->eraseFromParent();
> + ? ?// BB is now empty, so it is likely to simplify away.
> + ? ?return SimplifyCFG(BB) | true;
> + ?}
> +

By the way, the "if (SI->getDefaultDest() != BB)" just before this
doesn't seem to handle the case where multiple cases jump to BB.


From fvbommel at gmail.com  Mon Dec 13 04:59:24 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Mon, 13 Dec 2010 11:59:24 +0100
Subject: [llvm-commits] [llvm] r121674 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <AANLkTi=mv7JE90AQ32_RfBh7h9RkiCh0G4AiHEH7RHO-@mail.gmail.com>
References: <20101213034357.E8F7E2A6C12C@llvm.org>
	<AANLkTi=mv7JE90AQ32_RfBh7h9RkiCh0G4AiHEH7RHO-@mail.gmail.com>
Message-ID: <AANLkTindQJ+UThxSJz6UtoVxpb2zffPJ7aaMjnEtH+Up@mail.gmail.com>

On Mon, Dec 13, 2010 at 11:34 AM, Frits van Bommel <fvbommel at gmail.com> wrote:
> On Mon, Dec 13, 2010 at 4:43 AM, Chris Lattner <sabre at nondot.org> wrote:
>> + ?// Ok, the block is reachable from the default dest. ?If the constant we're
>> + ?// comparing exists in one of the other edges, then we can constant fold ICI
>> + ?// and zap it.
>> + ?if (SI->findCaseValue(Cst) != 0) {
>
> This should probably also make sure the successor for that case isn't
> equal to BB. (Yes, this is an even *more* degenerate case since BB is
> the default destination of the switch, but it's valid IR...)

> By the way, the "if (SI->getDefaultDest() != BB)" just before this
> doesn't seem to handle the case where multiple cases jump to BB.

Never mind, none of this code is reachable if there's more than one edge.
I either overlooked the "return false if !BB->getSinglePredecessor()"
code above it or forgot that getSinglePredecessor !=
getUniquePredecessor.


From fvbommel at gmail.com  Mon Dec 13 06:29:42 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Mon, 13 Dec 2010 13:29:42 +0100
Subject: [llvm-commits] [llvm] r121671 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <20101213031854.39E3A2A6C12C@llvm.org>
References: <20101213031854.39E3A2A6C12C@llvm.org>
Message-ID: <AANLkTikygbQbx2YmcF0-FPw-kLDp8Ls4adbMUsnUnZb9@mail.gmail.com>

On Mon, Dec 13, 2010 at 4:18 AM, Chris Lattner <sabre at nondot.org> wrote:
> Author: lattner
> Date: Sun Dec 12 21:18:54 2010
> New Revision: 121671
>
> URL: http://llvm.org/viewvc/llvm-project?rev=121671&view=rev
> Log:
> fix a fairly serious oversight with switch formation from
> or'd conditions. ?Previously we'd compile something like this:
>
> int crud (unsigned char c) {
> ? return c == 62 || c == 34 || c == 92;
> }
>
> into:
>
> ?switch i8 %c, label %lor.rhs [
> ? ?i8 62, label %lor.end
> ? ?i8 34, label %lor.end
> ?]
>
> lor.rhs: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry
> ?%cmp8 = icmp eq i8 %c, 92
> ?br label %lor.end
>
> lor.end: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry, %entry, %lor.rhs
> ?%0 = phi i1 [ true, %entry ], [ %cmp8, %lor.rhs ], [ true, %entry ]
> ?%lor.ext = zext i1 %0 to i32
> ?ret i32 %lor.ext
>
> which failed to merge the compare-with-92 into the switch. ?With this patch
> we simplify this all the way to:
>
> ?switch i8 %c, label %lor.rhs [
> ? ?i8 62, label %lor.end
> ? ?i8 34, label %lor.end
> ? ?i8 92, label %lor.end
> ?]
>
> lor.rhs: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry
> ?br label %lor.end
>
> lor.end: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %entry, %entry, %entry, %lor.rhs
> ?%0 = phi i1 [ true, %entry ], [ false, %lor.rhs ], [ true, %entry ], [ true, %entry ]
> ?%lor.ext = zext i1 %0 to i32
> ?ret i32 %lor.ext
>
> which is much better for codegen's switch lowering stuff. ?This kicks in 33 times
> on 176.gcc (for example) cutting 103 instructions off the generated code.

I have some code where this doesn't work, probably due to the
requirement for the only use of the icmp to be a phi. A reduced test
case:
=====
bool foo(int x) { return x == 1; }
bool bar(int x) { return x == 2; }
bool baz(int x) { return x == 3; }

bool quux(int x) {
  return foo(x) || bar(x) || baz(x);
}
=====
The problem seems to be that the return gets duplicated into the two
branches before inlining, causing quux() to come out of clang -O3 like
this:
=====
define zeroext i1 @quux(int)(i32 %x) nounwind readnone {
entry:
  switch i32 %x, label %lor.rhs [
    i32 1, label %lor.end
    i32 2, label %lor.end
  ]

lor.rhs:                                          ; preds = %entry
  %cmp.i5 = icmp eq i32 %x, 3                     ; [#uses=1]
  ret i1 %cmp.i5

lor.end:                                          ; preds = %entry, %entry
  ret i1 true
}
=====


From geek4civic at gmail.com  Mon Dec 13 09:07:10 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 14 Dec 2010 00:07:10 +0900
Subject: [llvm-commits] [Review request][Win64] Improve allocating shadow
	area
Message-ID: <AANLkTikiPKTWtkgdmU3i80eqcimmNn6M=KeHj6k4dhaY@mail.gmail.com>

Good midnight, guys!

I tweaked Win64's calling conversion.

  - On leaf functions(do not have win64's callee), redundant shadow
area would not be emitted.
  - [PR8778] Calling parameters would be constructed properly onto
dynamic stack allocation(alloca).

This patch is not testsd widely.
I would like to point out whatever I missed.
Please take a look!

...Takumi
-------------- next part --------------
From 9b0a03ce39694d036353b7d8d4b30fefb86b3b95 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi <geek4civic at gmail.com>
Date: Mon, 13 Dec 2010 17:59:20 +0900
Subject: [PATCH] Target/X86: Allocate Win64's shadow allocation, on stack, when callee requires one.

In leaf functions, shadow area would not be allocated any more.
---
 lib/Target/X86/X86FrameInfo.cpp                    |    5 -----
 lib/Target/X86/X86ISelLowering.cpp                 |    8 ++++++--
 test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll |    4 ++--
 test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll       |    9 ++++-----
 test/CodeGen/X86/win64_params.ll                   |    4 ++--
 test/CodeGen/X86/win64_vararg.ll                   |   10 +++++-----
 6 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/lib/Target/X86/X86FrameInfo.cpp b/lib/Target/X86/X86FrameInfo.cpp
index c47b0fa..3733f6c 100644
--- a/lib/Target/X86/X86FrameInfo.cpp
+++ b/lib/Target/X86/X86FrameInfo.cpp
@@ -325,11 +325,6 @@ void X86FrameInfo::emitPrologue(MachineFunction &MF) const {
     if (HasFP) MinSize += SlotSize;
     StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
     MFI->setStackSize(StackSize);
-  } else if (IsWin64) {
-    // We need to always allocate 32 bytes as register spill area.
-    // FIXME: We might reuse these 32 bytes for leaf functions.
-    StackSize += 32;
-    MFI->setStackSize(StackSize);
   }
 
   // Insert stack pointer adjustment for later moving of return addr.  Only
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 045bb93..fd93462 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1807,8 +1807,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
                                     DebugLoc dl, SelectionDAG &DAG,
                                     const CCValAssign &VA,
                                     ISD::ArgFlagsTy Flags) const {
-  const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
-  unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
+  unsigned LocMemOffset = VA.getLocMemOffset();
   SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
   PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
   if (Flags.isByVal())
@@ -1892,6 +1891,11 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
                  ArgLocs, *DAG.getContext());
+
+  // Win64 CC requires at least 4 x 64bit of shadow allocation.
+  if (Subtarget->isTargetWin64())
+    CCInfo.AllocateStack(32, 16);
+
   CCInfo.AnalyzeCallOperands(Outs, CC_X86);
 
   // Get a count of how many bytes are to be pushed on the stack.
diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
index c598228..0413044 100644
--- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
+++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp"
-target triple = "x86_64-pc-mingw64"
+; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s
+; CHECK: subq $8, %rsp
 
 define x86_fp80 @a(i64 %x) nounwind readnone {
 entry:
diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
index 810a6f4..9833d96 100644
--- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
+++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
@@ -1,8 +1,7 @@
-; RUN: llc < %s -o %t1
-; RUN: grep "subq.*\\\$72, \\\%rsp" %t1
-; RUN: grep "movaps	\\\%xmm8, 32\\\(\\\%rsp\\\)" %t1
-; RUN: grep "movaps	\\\%xmm7, 48\\\(\\\%rsp\\\)" %t1
-target triple = "x86_64-pc-mingw64"
+; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s
+; CHECK: subq    $40, %rsp
+; CHECK: movaps  %xmm8, (%rsp)
+; CHECK: movaps  %xmm7, 16(%rsp)
 
 define i32 @a() nounwind {
 entry:
diff --git a/test/CodeGen/X86/win64_params.ll b/test/CodeGen/X86/win64_params.ll
index 0b67368..f9d4bf9 100644
--- a/test/CodeGen/X86/win64_params.ll
+++ b/test/CodeGen/X86/win64_params.ll
@@ -4,8 +4,8 @@
 ; on the stack.
 define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
 entry:
-; CHECK: movl    80(%rsp), %eax
-; CHECK: addl    72(%rsp), %eax
+; CHECK: movl    48(%rsp), %eax
+; CHECK: addl    40(%rsp), %eax
   %add = add nsw i32 %p6, %p5
   ret i32 %add
 }
diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll
index 072f36a..aa7d786 100644
--- a/test/CodeGen/X86/win64_vararg.ll
+++ b/test/CodeGen/X86/win64_vararg.ll
@@ -5,11 +5,11 @@
 ; calculated.
 define void @average_va(i32 %count, ...) nounwind {
 entry:
-; CHECK: subq	$40, %rsp
-; CHECK: movq	%r9, 72(%rsp)
-; CHECK: movq	%r8, 64(%rsp)
-; CHECK: movq	%rdx, 56(%rsp)
-; CHECK: leaq	56(%rsp), %rax
+; CHECK: subq	$8, %rsp
+; CHECK: movq	%r9, 40(%rsp)
+; CHECK: movq	%r8, 32(%rsp)
+; CHECK: movq	%rdx, 24(%rsp)
+; CHECK: leaq	24(%rsp), %rax
 
   %ap = alloca i8*, align 8                       ; <i8**> [#uses=1]
   %ap1 = bitcast i8** %ap to i8*                  ; <i8*> [#uses=1]
-- 
1.7.1.GIT

From aggarwa4 at illinois.edu  Mon Dec 13 09:55:23 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 13 Dec 2010 15:55:23 -0000
Subject: [llvm-commits] [poolalloc] r121701 - in
 /poolalloc/trunk/lib/PoolAllocate: PoolAllocate.cpp
 TransformFunctionBody.cpp
Message-ID: <20101213155523.EB9872A6C12E@llvm.org>

Author: aggarwa4
Date: Mon Dec 13 09:55:23 2010
New Revision: 121701

URL: http://llvm.org/viewvc/llvm-project?rev=121701&view=rev
Log:
While building FuncInfo for the functions, we should
look at the call graph to determine, which functions
should be in the same EQ, and hence should get the 
same number of args.
Since, we have already ensured that all targets, 
for the same call site have the same number of 
pool args, we can just choose any one to instrument
the call site.

Modified:
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
    poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=121701&r1=121700&r2=121701&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Dec 13 09:55:23 2010
@@ -658,6 +658,45 @@
   // for corresponding arguments.  Therefore, we want to process all the
   // functions in the same equivalence class once to avoid doing extra work.
   //
+  const DSCallGraph & callgraph = Graphs->getCallGraph();
+  DSGraph* G = Graphs->getGlobalsGraph();
+  DSGraph::ScalarMapTy& SM = G->getScalarMap();
+  for (DSCallGraph::callee_key_iterator ii = callgraph.key_begin(),
+       ee = callgraph.key_end(); ii != ee; ++ii) {
+    bool isIndirect = ((*ii).getCalledFunction() == NULL);
+
+    if (isIndirect) {
+      std::vector<const Function *> Functions;
+      DSCallGraph::callee_iterator csi = callgraph.callee_begin(*ii),
+                                   cse = callgraph.callee_end(*ii);
+      while(csi != cse) {
+        const Function *F = *csi;
+        DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F),
+                                sccee = callgraph.scc_end(F);
+        for(;sccii != sccee; ++sccii) {
+          DSGraph::ScalarMapTy::const_iterator I = SM.find(SM.getLeaderForGlobal(*sccii));
+          if (I != SM.end() && !((*sccii)->isDeclaration())) {
+            Functions.push_back (*sccii);
+          }
+        }
+        ++csi;
+      }
+      const Function *F1 = (*ii).getInstruction()->getParent()->getParent();
+      F1 = callgraph.sccLeader(&*F1);
+
+      DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F1),
+                                sccee = callgraph.scc_end(F1);
+      for(;sccii != sccee; ++sccii) {
+        DSGraph::ScalarMapTy::const_iterator I = SM.find(SM.getLeaderForGlobal(*sccii));
+        if (I != SM.end() && !((*sccii)->isDeclaration())) {
+          Functions.push_back (*sccii);
+        }
+      }
+    
+      FindFunctionPoolArgs (Functions);
+    }
+  }
+  /*
   EquivalenceClasses<const GlobalValue*> & GlobalECs = Graphs->getGlobalECs();
   EquivalenceClasses<const GlobalValue*>::iterator EQSI = GlobalECs.begin();
   EquivalenceClasses<const GlobalValue*>::iterator EQSE = GlobalECs.end();
@@ -691,7 +730,7 @@
     // class and construct the FuncInfo structure for each one.
     //
     FindFunctionPoolArgs (Functions);
-  }
+  }*/
 
   //
   // Make sure every function has a FuncInfo structure.

Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=121701&r1=121700&r2=121701&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Mon Dec 13 09:55:23 2010
@@ -935,12 +935,12 @@
         // If this target takes more DSNodes than the last one we found, then
         // make *this* target our canonical target.
         //
-        if (CFI->ArgNodes.size() >= maxArgsWithNodes) {
-          maxArgsWithNodes = CFI->ArgNodes.size();
-          CF = *sccii;
-        }
+        maxArgsWithNodes = CFI->ArgNodes.size();
+        CF = *sccii;
+        break;
       }
     }
+    if(!CF){
     const Function *F1 = OrigInst->getParent()->getParent();
     F1 = callGraph.sccLeader(&*F1);
 
@@ -960,10 +960,9 @@
       // If this target takes more DSNodes than the last one we found, then
       // make *this* target our canonical target.
       //
-      if (CFI->ArgNodes.size() >= maxArgsWithNodes) {
-        maxArgsWithNodes = CFI->ArgNodes.size();
-        CF = *sccii;
-      }
+      maxArgsWithNodes = CFI->ArgNodes.size();
+      CF = *sccii;
+    }
     }
     
     // Assuming the call graph is always correct. And if the call graph reports,



From benny.kra at googlemail.com  Mon Dec 13 12:20:38 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 13 Dec 2010 18:20:38 -0000
Subject: [llvm-commits] [llvm] r121705 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101213182038.37A972A6C12C@llvm.org>

Author: d0k
Date: Mon Dec 13 12:20:38 2010
New Revision: 121705

URL: http://llvm.org/viewvc/llvm-project?rev=121705&view=rev
Log:
Fix sort predicate. qsort(3)'s predicate semantics differ from std::sort's. Fixes PR 8780.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121705&r1=121704&r2=121705&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 12:20:38 2010
@@ -598,7 +598,7 @@
 static int ConstantIntSortPredicate(const void *P1, const void *P2) {
   const ConstantInt *LHS = *(const ConstantInt**)P1;
   const ConstantInt *RHS = *(const ConstantInt**)P2;
-  return LHS->getValue().ult(RHS->getValue());
+  return LHS->getValue().ult(RHS->getValue()) ? 1 : -1;
 }
 
 /// FoldValueComparisonIntoPredecessors - The specified terminator is a value

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121705&r1=121704&r2=121705&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 12:20:38 2010
@@ -290,5 +290,44 @@
 ; CHECK:  ]
 }
 
+; PR8780
+define i32 @test11(i32 %bar) nounwind {
+entry:
+  %cmp = icmp eq i32 %bar, 4
+  %cmp2 = icmp eq i32 %bar, 35
+  %or.cond = or i1 %cmp, %cmp2
+  %cmp5 = icmp eq i32 %bar, 53
+  %or.cond1 = or i1 %or.cond, %cmp5
+  %cmp8 = icmp eq i32 %bar, 24
+  %or.cond2 = or i1 %or.cond1, %cmp8
+  %cmp11 = icmp eq i32 %bar, 23
+  %or.cond3 = or i1 %or.cond2, %cmp11
+  %cmp14 = icmp eq i32 %bar, 55
+  %or.cond4 = or i1 %or.cond3, %cmp14
+  %cmp17 = icmp eq i32 %bar, 12
+  %or.cond5 = or i1 %or.cond4, %cmp17
+  %cmp20 = icmp eq i32 %bar, 35
+  %or.cond6 = or i1 %or.cond5, %cmp20
+  br i1 %or.cond6, label %if.then, label %if.end
 
+if.then:                                          ; preds = %entry
+  br label %return
 
+if.end:                                           ; preds = %entry
+  br label %return
+
+return:                                           ; preds = %if.end, %if.then
+  %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
+  ret i32 %retval.0
+
+; CHECK: @test11
+; CHECK: switch i32 %bar, label %if.end [
+; CHECK:   i32 55, label %return
+; CHECK:   i32 53, label %return
+; CHECK:   i32 35, label %return
+; CHECK:   i32 24, label %return
+; CHECK:   i32 23, label %return
+; CHECK:   i32 12, label %return
+; CHECK:   i32 4, label %return
+; CHECK: ]
+}



From aggarwa4 at illinois.edu  Mon Dec 13 13:18:02 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 13 Dec 2010 19:18:02 -0000
Subject: [llvm-commits] [poolalloc] r121707 -
	/poolalloc/trunk/lib/DSA/DSGraph.cpp
Message-ID: <20101213191802.409EE2A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Dec 13 13:18:02 2010
New Revision: 121707

URL: http://llvm.org/viewvc/llvm-project?rev=121707&view=rev
Log:
As per  getValueDest that creates DSNodes,
there is no DSNode for Constant Null Values. Perform
the same check here too.


Modified:
    poolalloc/trunk/lib/DSA/DSGraph.cpp

Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=121707&r1=121706&r2=121707&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSGraph.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSGraph.cpp Mon Dec 13 13:18:02 2010
@@ -69,6 +69,9 @@
   // Undef values, even ones of pointer type, don't get nodes.
   if (isa<UndefValue>(V)) return false;
 
+  if (isa<Constant>(V) && cast<Constant>(V)->isNullValue())
+    return false;
+
   // Use the Aliasee of GlobalAliases
   // FIXME: This check might not be required, it's here because
   // something similar is done in the Local pass.



From grosbach at apple.com  Mon Dec 13 13:18:13 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 13 Dec 2010 19:18:13 -0000
Subject: [llvm-commits] [llvm] r121708 -
	/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
Message-ID: <20101213191813.BFA822A6C12C@llvm.org>

Author: grosbach
Date: Mon Dec 13 13:18:13 2010
New Revision: 121708

URL: http://llvm.org/viewvc/llvm-project?rev=121708&view=rev
Log:
Trailing whitespace.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121708&r1=121707&r2=121708&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 13:18:13 2010
@@ -112,7 +112,7 @@
     }
     assert ((Value < 4096) && "Out of range pc-relative fixup value!");
     Value |= isAdd << 23;
-    
+
     // Same addressing mode as fixup_arm_pcrel_10,
     // but with 16-bit halfwords swapped.
     if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
@@ -120,7 +120,7 @@
       swapped |= (Value & 0x0000FFFF) << 16;
       return swapped;
     }
-    
+
     return Value;
   }
   case ARM::fixup_arm_adr_pcrel_12: {
@@ -143,14 +143,14 @@
   case ARM::fixup_t2_branch: {
     Value = Value - 4;
     Value >>= 1; // Low bit is not encoded.
-    
+
     uint64_t out = 0;
     out |= (Value & 0x80000) << 7; // S bit
     out |= (Value & 0x40000) >> 7; // J2 bit
     out |= (Value & 0x20000) >> 4; // J1 bit
     out |= (Value & 0x1F800) << 5; // imm6 field
     out |= (Value & 0x007FF);      // imm11 field
-    
+
     uint64_t swapped = (out & 0xFFFF0000) >> 16;
     swapped |= (out & 0x0000FFFF) << 16;
     return swapped;
@@ -159,9 +159,9 @@
     // The value doesn't encode the low bit (always zero) and is offset by
     // four. The value is encoded into disjoint bit positions in the destination
     // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
-    // 
+    //
     //   BL:  xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
-    // 
+    //
     // Note that the halfwords are stored high first, low second; so we need
     // to transpose the fixup value here to map properly.
     unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
@@ -177,9 +177,9 @@
     // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
     // positions in the destination opcode. x = unchanged, I = immediate value
     // bit, S = sign extension bit, 0 = zero.
-    // 
+    //
     //   BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
-    // 
+    //
     // Note that the halfwords are stored high first, low second; so we need
     // to transpose the fixup value here to map properly.
     unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;



From grosbach at apple.com  Mon Dec 13 13:25:46 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 13 Dec 2010 19:25:46 -0000
Subject: [llvm-commits] [llvm] r121709 -
	/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
Message-ID: <20101213192546.AE1BF2A6C12C@llvm.org>

Author: grosbach
Date: Mon Dec 13 13:25:46 2010
New Revision: 121709

URL: http://llvm.org/viewvc/llvm-project?rev=121709&view=rev
Log:
Use 32-bit types for 32-bit values.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121709&r1=121708&r2=121709&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 13:25:46 2010
@@ -144,14 +144,14 @@
     Value = Value - 4;
     Value >>= 1; // Low bit is not encoded.
 
-    uint64_t out = 0;
+    uint32_t out = 0;
     out |= (Value & 0x80000) << 7; // S bit
     out |= (Value & 0x40000) >> 7; // J2 bit
     out |= (Value & 0x20000) >> 4; // J1 bit
     out |= (Value & 0x1F800) << 5; // imm6 field
     out |= (Value & 0x007FF);      // imm11 field
 
-    uint64_t swapped = (out & 0xFFFF0000) >> 16;
+    uint32_t swapped = (out & 0xFFFF0000) >> 16;
     swapped |= (out & 0x0000FFFF) << 16;
     return swapped;
   }
@@ -226,7 +226,7 @@
     // Same addressing mode as fixup_arm_pcrel_10,
     // but with 16-bit halfwords swapped.
     if (Kind == ARM::fixup_t2_pcrel_10) {
-      uint64_t swapped = (Value & 0xFFFF0000) >> 16;
+      uint32_t swapped = (Value & 0xFFFF0000) >> 16;
       swapped |= (Value & 0x0000FFFF) << 16;
       return swapped;
     }



From resistor at mac.com  Mon Dec 13 13:31:11 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 13 Dec 2010 19:31:11 -0000
Subject: [llvm-commits] [llvm] r121710 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMCodeEmitter.cpp
 lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp
 utils/TableGen/EDEmitter.cpp utils/TableGen/X86RecognizableInstr.cpp
Message-ID: <20101213193111.DCC252A6C12C@llvm.org>

Author: resistor
Date: Mon Dec 13 13:31:11 2010
New Revision: 121710

URL: http://llvm.org/viewvc/llvm-project?rev=121710&view=rev
Log:
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 13:31:11 2010
@@ -140,11 +140,32 @@
     // These values don't encode the low two bits since they're always zero.
     // Offset by 8 just as above.
     return 0xffffff & ((Value - 8) >> 2);
-  case ARM::fixup_t2_branch: {
+  case ARM::fixup_t2_uncondbranch: {
     Value = Value - 4;
     Value >>= 1; // Low bit is not encoded.
 
     uint32_t out = 0;
+    bool I =  Value & 0x800000;
+    bool J1 = Value & 0x400000;
+    bool J2 = Value & 0x200000;
+    J1 ^= I;
+    J2 ^= I;
+    
+    out |= I  << 26; // S bit
+    out |= !J1 << 13; // J1 bit
+    out |= !J2 << 11; // J2 bit
+    out |= (Value & 0x1FF800)  << 5; // imm6 field
+    out |= (Value & 0x0007FF);        // imm11 field
+    
+    uint64_t swapped = (out & 0xFFFF0000) >> 16;
+    swapped |= (out & 0x0000FFFF) << 16;
+    return swapped;
+  }
+  case ARM::fixup_t2_condbranch: {
+    Value = Value - 4;
+    Value >>= 1; // Low bit is not encoded.
+    
+    uint64_t out = 0;
     out |= (Value & 0x80000) << 7; // S bit
     out |= (Value & 0x40000) >> 7; // J2 bit
     out |= (Value & 0x20000) >> 4; // J1 bit
@@ -332,7 +353,8 @@
 
   case FK_Data_4:
   case ARM::fixup_t2_ldst_pcrel_12:
-  case ARM::fixup_t2_branch:
+  case ARM::fixup_t2_condbranch:
+  case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_t2_pcrel_10:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 13:31:11 2010
@@ -183,6 +183,8 @@
       const { return 0; }
     unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
+      unsigned Op) const { return 0; }
     unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Mon Dec 13 13:31:11 2010
@@ -36,9 +36,12 @@
   // fixup_arm_branch - 24-bit PC relative relocation for direct branch
   // instructions.
   fixup_arm_branch,
-  // fixup_t2_branch - 20-bit PC relative relocation for Thumb2 direct branch
-  // instructions.
-  fixup_t2_branch,
+  // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct 
+  // uconditional branch instructions.
+  fixup_t2_condbranch,
+  // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct 
+  // branch unconditional branch instructions.
+  fixup_t2_uncondbranch,
 
   // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
   fixup_arm_thumb_br,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Dec 13 13:31:11 2010
@@ -293,6 +293,10 @@
   let EncoderMethod = "getBranchTargetOpValue";
 }
 
+def uncondbrtarget : Operand<OtherVT> {
+  let EncoderMethod = "getUnconditionalBranchTargetOpValue";
+}
+
 // Call target.
 def bltarget : Operand<i32> {
   // Encoded the same as branch targets.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec 13 13:31:11 2010
@@ -2961,7 +2961,7 @@
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 let isPredicable = 1 in
-def t2B   : T2XI<(outs), (ins brtarget:$target), IIC_Br,
+def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
                  "b.w\t$target",
                  [(br bb:$target)]> {
   let Inst{31-27} = 0b11110;

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 13:31:11 2010
@@ -57,7 +57,8 @@
                                                 MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_branch",        1,            24,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_branch",         0,            32,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_br",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_bl",      0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_blx",     7,            21,  MCFixupKindInfo::FKF_IsPCRel },
@@ -122,6 +123,12 @@
   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
                                   SmallVectorImpl<MCFixup> &Fixups) const;
 
+  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
+  /// immediate Thumb2 direct branch target.
+  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
+                                  SmallVectorImpl<MCFixup> &Fixups) const;
+  
+
   /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
   /// ADR label target.
   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
@@ -499,10 +506,34 @@
   // coupling between MC and TM anywhere we can help it.
   const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
   if (Subtarget.isThumb2())
-    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_branch, Fixups);
+    return
+      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
   return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
 }
 
+/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
+/// immediate branch target.
+uint32_t ARMMCCodeEmitter::
+getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
+                       SmallVectorImpl<MCFixup> &Fixups) const {
+  unsigned Val =
+    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
+  bool I  = (Val & 0x800000);
+  bool J1 = (Val & 0x400000);
+  bool J2 = (Val & 0x200000);
+  if (I ^ J1)
+    Val &= ~0x400000;
+  else
+    Val |= 0x400000;
+    
+  if (I ^ J2)
+    Val &= ~0x200000;
+  else
+    Val |= 0x200000;
+  
+  return Val;
+}
+
 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
 /// target.
 uint32_t ARMMCCodeEmitter::

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 13:31:11 2010
@@ -322,6 +322,7 @@
   PCR("offset32");
   PCR("offset64");
   PCR("brtarget");
+  PCR("uncondbrtarget");
   PCR("bltarget");
 
   return 1;
@@ -587,6 +588,7 @@
   IMM("neon_vcvt_imm32");
 
   MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
+  MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
   MISC("t_brtarget", "kOperandTypeARMBranchTarget");              // ?
   MISC("t_bcctarget", "kOperandTypeARMBranchTarget");             // ?
   MISC("t_cbtarget", "kOperandTypeARMBranchTarget");              // ?

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=121710&r1=121709&r2=121710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Dec 13 13:31:11 2010
@@ -857,6 +857,7 @@
   TYPE("i32imm_pcrel",        TYPE_REL32)
   TYPE("SSECC",               TYPE_IMM3)
   TYPE("brtarget",            TYPE_RELv)
+  TYPE("uncondbrtarget",      TYPE_RELv)
   TYPE("brtarget8",           TYPE_REL8)
   TYPE("f80mem",              TYPE_M80FP)
   TYPE("lea32mem",            TYPE_LEA)



From sabre at nondot.org  Mon Dec 13 13:55:30 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 19:55:30 -0000
Subject: [llvm-commits] [llvm] r121711 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101213195530.C7A922A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 13:55:30 2010
New Revision: 121711

URL: http://llvm.org/viewvc/llvm-project?rev=121711&view=rev
Log:
add some DEBUG's.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121711&r1=121710&r2=121711&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 13:55:30 2010
@@ -1905,10 +1905,16 @@
   
   BasicBlock *BB = BI->getParent();
   
+  DEBUG(dbgs() << "CONVERTING 'icmp' CHAIN with " << Values.size()
+               << " cases into SWITCH.  BB is:\n" << *BB);
+  
   // If there are any extra values that couldn't be folded into the switch
   // then we evaluate them with an explicit branch first.  Split the block
   // right before the condbr to handle it.
   if (ExtraCase) {
+    DEBUG(dbgs() << "  ** 'icmp' chain unhandled condition: " << *ExtraCase
+                 << '\n');
+    
     BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
     // Remove the uncond branch added to the old block.
     TerminatorInst *OldTI = BB->getTerminator();
@@ -2361,7 +2367,7 @@
   // branches to us and one of our successors, fold the setcc into the
   // predecessor and use logical operations to pick the right destination.
   if (FoldBranchToCommonDest(BI))
-    return SimplifyCFG(BB) | true;
+    return true;
   
   // Scan predecessor blocks for conditional branches.
   for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
@@ -2413,8 +2419,7 @@
     if (BI->isUnconditional()) {
       if (SimplifyUncondBranch(BI)) return true;
     } else {
-      if (SimplifyCondBranch(BI))
-        return true;
+      if (SimplifyCondBranch(BI)) return true;
     }
   } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
     if (SimplifyReturn(RI)) return true;



From evan.cheng at apple.com  Mon Dec 13 14:32:54 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 13 Dec 2010 20:32:54 -0000
Subject: [llvm-commits] [llvm] r121714 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20101213203254.800EF2A6C12C@llvm.org>

Author: evancheng
Date: Mon Dec 13 14:32:54 2010
New Revision: 121714

URL: http://llvm.org/viewvc/llvm-project?rev=121714&view=rev
Log:
Generalize BFI isel lowering a bit.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=121714&r1=121713&r2=121714&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Dec 13 14:32:54 2010
@@ -4713,57 +4713,43 @@
   if (VT != MVT::i32)
     return SDValue();
 
+  SDValue N00 = N0.getOperand(0);
 
   // The value and the mask need to be constants so we can verify this is
   // actually a bitfield set. If the mask is 0xffff, we can do better
   // via a movt instruction, so don't use BFI in that case.
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
-  if (!C)
+  SDValue MaskOp = N0.getOperand(1);
+  ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
+  if (!MaskC)
     return SDValue();
-  unsigned Mask = C->getZExtValue();
+  unsigned Mask = MaskC->getZExtValue();
   if (Mask == 0xffff)
     return SDValue();
   SDValue Res;
   // Case (1): or (and A, mask), val => ARMbfi A, val, mask
-  if ((C = dyn_cast<ConstantSDNode>(N1))) {
-    unsigned Val = C->getZExtValue();
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  if (N1C) {
+    unsigned Val = N1C->getZExtValue();
     if ((Val & ~Mask) != Val)
       return SDValue();
 
     if (ARM::isBitFieldInvertedMask(Mask)) {
       Val >>= CountTrailingZeros_32(~Mask);
 
-      Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
+      Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
                         DAG.getConstant(Val, MVT::i32),
                         DAG.getConstant(Mask, MVT::i32));
 
       // Do not add new nodes to DAG combiner worklist.
       DCI.CombineTo(N, Res, false);
-    } else if (N0.getOperand(0).getOpcode() == ISD::SHL &&
-               isa<ConstantSDNode>(N0.getOperand(0).getOperand(1)) &&
-               ARM::isBitFieldInvertedMask(~Mask)) {
-      // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
-      // where lsb(mask) == #shamt
-      SDValue ShAmt = N0.getOperand(0).getOperand(1);
-      unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
-      unsigned LSB = CountTrailingZeros_32(Mask);
-      if (ShAmtC != LSB)
-        return SDValue();
-      //unsigned Width = (32 - CountLeadingZeros_32(Mask)) - LSB;
-
-      Res = DAG.getNode(ARMISD::BFI, DL, VT, N1,
-                        N0.getOperand(0).getOperand(0),
-                        DAG.getConstant(~Mask, MVT::i32));
-
-      // Do not add new nodes to DAG combiner worklist.
-      DCI.CombineTo(N, Res, false);
+      return SDValue();
     }
   } else if (N1.getOpcode() == ISD::AND) {
     // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
-    C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
-    if (!C)
+    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+    if (!N11C)
       return SDValue();
-    unsigned Mask2 = C->getZExtValue();
+    unsigned Mask2 = N11C->getZExtValue();
 
     if (ARM::isBitFieldInvertedMask(Mask) &&
         ARM::isBitFieldInvertedMask(~Mask2) &&
@@ -4777,10 +4763,11 @@
       unsigned lsb = CountTrailingZeros_32(Mask2);
       Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
                         DAG.getConstant(lsb, MVT::i32));
-      Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
+      Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
                         DAG.getConstant(Mask, MVT::i32));
       // Do not add new nodes to DAG combiner worklist.
       DCI.CombineTo(N, Res, false);
+      return SDValue();
     } else if (ARM::isBitFieldInvertedMask(~Mask) &&
                ARM::isBitFieldInvertedMask(Mask2) &&
                (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
@@ -4791,15 +4778,34 @@
         return SDValue();
       // 2b
       unsigned lsb = CountTrailingZeros_32(Mask);
-      Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
+      Res = DAG.getNode(ISD::SRL, DL, VT, N00,
                         DAG.getConstant(lsb, MVT::i32));
       Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
                                 DAG.getConstant(Mask2, MVT::i32));
       // Do not add new nodes to DAG combiner worklist.
       DCI.CombineTo(N, Res, false);
+      return SDValue();
     }
   }
 
+  if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
+      N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
+      ARM::isBitFieldInvertedMask(~Mask)) {
+    // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
+    // where lsb(mask) == #shamt and masked bits of B are known zero.
+    SDValue ShAmt = N00.getOperand(1);
+    unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
+    unsigned LSB = CountTrailingZeros_32(Mask);
+    if (ShAmtC != LSB)
+      return SDValue();
+
+    Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
+                      DAG.getConstant(~Mask, MVT::i32));
+
+    // Do not add new nodes to DAG combiner worklist.
+    DCI.CombineTo(N, Res, false);
+  }
+
   return SDValue();
 }
 



From jasonwkim at google.com  Mon Dec 13 14:37:26 2010
From: jasonwkim at google.com (Jason Kim)
Date: Mon, 13 Dec 2010 12:37:26 -0800
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <nnglj3to4aw.fsf@royale.us.cray.com>
References: <nnglj3to4aw.fsf@royale.us.cray.com>
Message-ID: <AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>

Hi David.

I think the regulars want the patches posted on llvm-commits for review
However, taking a  look at the second one (lit2.patch, attached),
there's couple of utilities missing in the list - like elf-dump etc.

I'd vote getting rid of the llvm-gcc bindir being prepended as the
easiest solution to fix this.
But I don't know WHY that path was being prepended in the first place.
(Perhaps someone with a longer memory then I can comment?)

If the list of executables changes, then the explicit list of known
tools need to change as well.
Problem is, I can't immediately think of a nice way to get the list of
generated execs exported to llvm-lit,

-jason

On Mon, Dec 13, 2010 at 11:34 AM, David Greene <dag at cray.com> wrote:
> I would like to see if we can get patches posted to PR 8199 reviewed
> ASAP. ?These patches fix some problems with the lit tool and get the
> test suites working for me. ?I won't be able to contribute any code
> until this PR gets resolved.
>
> Patch #1 or Patch #3 on the PR both fix the problem. ?The difference in
> the patches is how ^ and $ are treated in substitution matching. ?Read
> the bug comments for details.
>
> Thanks!
>
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?-Dave
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu ? ? ? ? http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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From wendling at apple.com  Mon Dec 13 14:58:47 2010
From: wendling at apple.com (Bill Wendling)
Date: Mon, 13 Dec 2010 12:58:47 -0800
Subject: [llvm-commits] [llvm] r121675 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
In-Reply-To: <20101213041519.9DE9B2A6C12C@llvm.org>
References: <20101213041519.9DE9B2A6C12C@llvm.org>
Message-ID: <7635E375-1A01-4247-9B3C-85EBC21349EB@apple.com>

On Dec 12, 2010, at 8:15 PM, Chris Lattner wrote:

> Author: lattner
> Date: Sun Dec 12 22:15:19 2010
> New Revision: 121675
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121675&view=rev
> Log:
> inline a function, making the result much simpler.
> 
Chris,

This doesn't have the same semantics as the original non-inlined version. TrueWhenEqual should be "false" if the dyn_cast fails.

-bw

> Modified:
>    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
> 
> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121675&r1=121674&r2=121675&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sun Dec 12 22:15:19 2010
> @@ -347,31 +347,6 @@
>   return 0;
> }
> 
> -/// GatherValueComparisons - If the specified Cond is an 'and' or 'or' of a
> -/// bunch of comparisons of one value against constants, return the value and
> -/// the constants being compared.
> -static bool GatherValueComparisons(Value *CondV, Value *&CompVal,
> -                                   std::vector<ConstantInt*> &Values,
> -                                   const TargetData *TD) {
> -  Instruction *Cond = dyn_cast<Instruction>(CondV);
> -  if (Cond == 0) return false;
> -  
> -  if (Cond->getOpcode() == Instruction::Or) {
> -    CompVal = GatherConstantSetEQs(Cond, Values, TD);
> -
> -    // Return true to indicate that the condition is true if the CompVal is
> -    // equal to one of the constants.
> -    return true;
> -  }
> -  if (Cond->getOpcode() == Instruction::And) {
> -    CompVal = GatherConstantSetNEs(Cond, Values, TD);
> -
> -    // Return false to indicate that the condition is false if the CompVal is
> -    // equal to one of the constants.
> -    return false;
> -  }
> -  return false;
> -}
> 
> static void EraseTerminatorInstAndDCECond(TerminatorInst *TI) {
>   Instruction* Cond = 0;
> @@ -2096,8 +2071,17 @@
>       // 'setne's and'ed together, collect them.
>       Value *CompVal = 0;
>       std::vector<ConstantInt*> Values;
> -      bool TrueWhenEqual = GatherValueComparisons(BI->getCondition(), CompVal,
> -                                                  Values, TD);
> +      bool TrueWhenEqual = true;
> +      
> +      if (Instruction *Cond = dyn_cast<Instruction>(BI->getCondition())) {
> +        if (Cond->getOpcode() == Instruction::Or) {
> +          CompVal = GatherConstantSetEQs(Cond, Values, TD);
> +        } else if (Cond->getOpcode() == Instruction::And) {
> +          CompVal = GatherConstantSetNEs(Cond, Values, TD);
> +          TrueWhenEqual = false;
> +        }
> +      }
> +
>       if (CompVal) {
>         // There might be duplicate constants in the list, which the switch
>         // instruction can't handle, remove them now.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From bob.wilson at apple.com  Mon Dec 13 15:05:44 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 13 Dec 2010 21:05:44 -0000
Subject: [llvm-commits] [llvm] r121715 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20101213210544.794D82A6C12C@llvm.org>

Author: bwilson
Date: Mon Dec 13 15:05:44 2010
New Revision: 121715

URL: http://llvm.org/viewvc/llvm-project?rev=121715&view=rev
Log:
Remove unused instruction class arguments.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121715&r1=121714&r2=121715&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 13 15:05:44 2010
@@ -1670,7 +1670,7 @@
 // Basic 2-register operations: single-, double- and quad-register.
 class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
-           string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
+           string Dt>
   : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
         (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm),
         IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm", "", []>;
@@ -1744,13 +1744,10 @@
 
 // Basic 3-register operations: single-, double- and quad-register.
 class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-           string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
-           SDNode OpNode, bit Commutable>
+           string OpcodeStr, string Dt>
   : N3V<op24, op23, op21_20, op11_8, 0, op4,
         (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm,
-        IIC_VBIND, OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", []> {
-  let isCommutable = Commutable;
-}
+        IIC_VBIND, OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", []>;
 
 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
            InstrItinClass itin, string OpcodeStr, string Dt,
@@ -1923,10 +1920,8 @@
 
 // Multiply-Add/Sub operations: single-, double- and quad-register.
 class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-                InstrItinClass itin, string OpcodeStr, string Dt,
-                ValueType Ty, SDPatternOperator MulOp, SDNode OpNode>
-  : N3V<op24, op23, op21_20, op11_8, 0, op4,
-        (outs DPR_VFP2:$Vd),
+                InstrItinClass itin, string OpcodeStr, string Dt>
+  : N3V<op24, op23, op21_20, op11_8, 0, op4, (outs DPR_VFP2:$Vd),
         (ins DPR_VFP2:$src1, DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, itin,
         OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", []>;
 
@@ -4716,17 +4711,17 @@
 
 // Vector Add Operations used for single-precision FP
 let neverHasSideEffects = 1 in
-def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32", v2f32, v2f32, fadd, 1>;
+def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32">;
 def : N3VSPat<fadd, VADDfd_sfp>;
 
 // Vector Sub Operations used for single-precision FP
 let neverHasSideEffects = 1 in
-def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32", v2f32, v2f32, fsub, 0>;
+def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32">;
 def : N3VSPat<fsub, VSUBfd_sfp>;
 
 // Vector Multiply Operations used for single-precision FP
 let neverHasSideEffects = 1 in
-def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32", v2f32, v2f32, fmul, 1>;
+def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32">;
 def : N3VSPat<fmul, VMULfd_sfp>;
 
 // Vector Multiply-Accumulate/Subtract used for single-precision FP
@@ -4734,14 +4729,12 @@
 // we want to avoid them for now. e.g., alternating vmla/vadd instructions.
 
 let neverHasSideEffects = 1 in
-def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32",
-                           v2f32, fmul_su, fadd>;
+def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32">;
 def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>,
       Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
 
 let neverHasSideEffects = 1 in
-def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32",
-                           v2f32, fmul_su, fsub>;
+def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32">;
 def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>,
       Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
 
@@ -4775,23 +4768,19 @@
 
 // Vector Convert between single-precision FP and integer
 let neverHasSideEffects = 1 in
-def  VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
-                         v2i32, v2f32, fp_to_sint>;
+def  VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32">;
 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
 
 let neverHasSideEffects = 1 in
-def  VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
-                         v2i32, v2f32, fp_to_uint>;
+def  VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32">;
 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
 
 let neverHasSideEffects = 1 in
-def  VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
-                         v2f32, v2i32, sint_to_fp>;
+def  VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32">;
 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
 
 let neverHasSideEffects = 1 in
-def  VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
-                         v2f32, v2i32, uint_to_fp>;
+def  VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32">;
 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
 
 //===----------------------------------------------------------------------===//



From bob.wilson at apple.com  Mon Dec 13 15:05:52 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 13 Dec 2010 21:05:52 -0000
Subject: [llvm-commits] [llvm] r121716 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMInstrNEON.td
Message-ID: <20101213210552.862962A6C12C@llvm.org>

Author: bwilson
Date: Mon Dec 13 15:05:52 2010
New Revision: 121716

URL: http://llvm.org/viewvc/llvm-project?rev=121716&view=rev
Log:
Use pseudo instructions for 2-register Neon instructions for scalar FP.
Partial fix for Radar 8711675.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121716&r1=121715&r2=121716&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Dec 13 15:05:52 2010
@@ -54,6 +54,7 @@
     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
                     unsigned Opc, bool IsExt, unsigned NumRegs);
+    void ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI, unsigned Opc);
   };
   char ARMExpandPseudo::ID = 0;
 }
@@ -612,6 +613,21 @@
   MI.eraseFromParent();
 }
 
+/// ExpandNeonSFP2 - Translate a 2-register Neon pseudo instruction used for
+/// scalar floating-point to a real instruction.
+void ARMExpandPseudo::ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI,
+                                     unsigned Opc) {
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
+  MIB.addOperand(MI.getOperand(0)) // destination register
+    .addOperand(MI.getOperand(1))  // source register
+    .addOperand(MI.getOperand(2))  // predicate
+    .addOperand(MI.getOperand(3)); // predicate register
+  TransferImpOps(MI, MIB, MIB);
+  MI.eraseFromParent();
+}
+
 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
   bool Modified = false;
 
@@ -1145,18 +1161,19 @@
       ExpandLaneOp(MBBI);
       break;
 
-    case ARM::VTBL2Pseudo:
-      ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
-    case ARM::VTBL3Pseudo:
-      ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
-    case ARM::VTBL4Pseudo:
-      ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
-    case ARM::VTBX2Pseudo:
-      ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
-    case ARM::VTBX3Pseudo:
-      ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
-    case ARM::VTBX4Pseudo:
-      ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
+    case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
+    case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
+    case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
+    case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
+    case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
+    case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
+
+    case ARM::VABSfd_sfp:   ExpandNeonSFP2(MBBI, ARM::VABSfd); break;
+    case ARM::VNEGfd_sfp:   ExpandNeonSFP2(MBBI, ARM::VNEGfd); break;
+    case ARM::VCVTf2sd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2sd); break;
+    case ARM::VCVTf2ud_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2ud); break;
+    case ARM::VCVTs2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTs2fd); break;
+    case ARM::VCVTu2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTu2fd); break;
     }
 
     if (ModifiedOp)

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121716&r1=121715&r2=121716&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 13 15:05:52 2010
@@ -1668,12 +1668,9 @@
 //===----------------------------------------------------------------------===//
 
 // Basic 2-register operations: single-, double- and quad-register.
-class N2VS<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
-           bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
-           string Dt>
-  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
-        (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm),
-        IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm", "", []>;
+let neverHasSideEffects = 1 in
+class N2VS
+  : PseudoNeonI<(outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm), IIC_VUNAD, "", []>;
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
@@ -4681,7 +4678,7 @@
 // NEON instructions for single-precision FP math
 //===----------------------------------------------------------------------===//
 
-class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
+class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, PseudoNeonI Inst>
   : NEONFPPat<(ResTy (OpNode SPR:$a)),
               (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
                                                        SPR:$a, ssub_0))),
@@ -4739,17 +4736,11 @@
       Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
 
 // Vector Absolute used for single-precision FP
-let neverHasSideEffects = 1 in
-def  VABSfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 0,
-                      (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm), IIC_VUNAD,
-                      "vabs", "f32", "$Vd, $Vm", "", []>;
+def  VABSfd_sfp : N2VS;
 def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
 
 // Vector Negate used for single-precision FP
-let neverHasSideEffects = 1 in
-def  VNEGfd_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
-                      (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm), IIC_VUNAD,
-                      "vneg", "f32", "$Vd, $Vm", "", []>;
+def  VNEGfd_sfp : N2VS;
 def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
 
 // Vector Maximum used for single-precision FP
@@ -4767,20 +4758,16 @@
 def : N3VSPat<NEONfmin, VMINfd_sfp>;
 
 // Vector Convert between single-precision FP and integer
-let neverHasSideEffects = 1 in
-def  VCVTf2sd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32">;
+def  VCVTf2sd_sfp : N2VS;
 def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
 
-let neverHasSideEffects = 1 in
-def  VCVTf2ud_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32">;
+def  VCVTf2ud_sfp : N2VS;
 def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
 
-let neverHasSideEffects = 1 in
-def  VCVTs2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32">;
+def  VCVTs2fd_sfp : N2VS;
 def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
 
-let neverHasSideEffects = 1 in
-def  VCVTu2fd_sfp : N2VS<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32">;
+def  VCVTu2fd_sfp : N2VS;
 def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
 
 //===----------------------------------------------------------------------===//



From sabre at nondot.org  Mon Dec 13 15:31:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 13:31:20 -0800
Subject: [llvm-commits] [llvm] r121675 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
In-Reply-To: <7635E375-1A01-4247-9B3C-85EBC21349EB@apple.com>
References: <20101213041519.9DE9B2A6C12C@llvm.org>
	<7635E375-1A01-4247-9B3C-85EBC21349EB@apple.com>
Message-ID: <854385A6-A2BD-4C96-98D5-2EEBBF2F86A6@nondot.org>


On Dec 13, 2010, at 12:58 PM, Bill Wendling wrote:

>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=121675&view=rev
>> Log:
>> inline a function, making the result much simpler.
>> 
> Chris,
> 
> This doesn't have the same semantics as the original non-inlined version. TrueWhenEqual should be "false" if the dyn_cast fails.

Doesn't matter, it isn't used in that case.

-Chris
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From bob.wilson at apple.com  Mon Dec 13 15:58:05 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 13 Dec 2010 21:58:05 -0000
Subject: [llvm-commits] [llvm] r121718 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMInstrNEON.td
Message-ID: <20101213215805.DD3292A6C12C@llvm.org>

Author: bwilson
Date: Mon Dec 13 15:58:05 2010
New Revision: 121718

URL: http://llvm.org/viewvc/llvm-project?rev=121718&view=rev
Log:
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121718&r1=121717&r2=121718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Dec 13 15:58:05 2010
@@ -54,7 +54,6 @@
     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
                     unsigned Opc, bool IsExt, unsigned NumRegs);
-    void ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI, unsigned Opc);
   };
   char ARMExpandPseudo::ID = 0;
 }
@@ -613,21 +612,6 @@
   MI.eraseFromParent();
 }
 
-/// ExpandNeonSFP2 - Translate a 2-register Neon pseudo instruction used for
-/// scalar floating-point to a real instruction.
-void ARMExpandPseudo::ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI,
-                                     unsigned Opc) {
-  MachineInstr &MI = *MBBI;
-  MachineBasicBlock &MBB = *MI.getParent();
-  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
-  MIB.addOperand(MI.getOperand(0)) // destination register
-    .addOperand(MI.getOperand(1))  // source register
-    .addOperand(MI.getOperand(2))  // predicate
-    .addOperand(MI.getOperand(3)); // predicate register
-  TransferImpOps(MI, MIB, MIB);
-  MI.eraseFromParent();
-}
-
 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
   bool Modified = false;
 
@@ -1167,13 +1151,6 @@
     case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
     case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
     case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
-
-    case ARM::VABSfd_sfp:   ExpandNeonSFP2(MBBI, ARM::VABSfd); break;
-    case ARM::VNEGfd_sfp:   ExpandNeonSFP2(MBBI, ARM::VNEGfd); break;
-    case ARM::VCVTf2sd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2sd); break;
-    case ARM::VCVTf2ud_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2ud); break;
-    case ARM::VCVTs2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTs2fd); break;
-    case ARM::VCVTu2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTu2fd); break;
     }
 
     if (ModifiedOp)

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121718&r1=121717&r2=121718&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 13 15:58:05 2010
@@ -1669,8 +1669,6 @@
 
 // Basic 2-register operations: single-, double- and quad-register.
 let neverHasSideEffects = 1 in
-class N2VS
-  : PseudoNeonI<(outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vm), IIC_VUNAD, "", []>;
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
@@ -4678,11 +4676,14 @@
 // NEON instructions for single-precision FP math
 //===----------------------------------------------------------------------===//
 
-class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, PseudoNeonI Inst>
+class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
   : NEONFPPat<(ResTy (OpNode SPR:$a)),
-              (EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
-                                                       SPR:$a, ssub_0))),
-                              ssub_0)>;
+              (EXTRACT_SUBREG
+               (OpTy (COPY_TO_REGCLASS
+                (OpTy (Inst (INSERT_SUBREG
+                 (OpTy (COPY_TO_REGCLASS (OpTy (IMPLICIT_DEF)), DPR_VFP2)),
+                                           SPR:$a, ssub_0))),
+                                       DPR_VFP2)), ssub_0)>;
 
 class N3VSPat<SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
@@ -4736,12 +4737,10 @@
       Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
 
 // Vector Absolute used for single-precision FP
-def  VABSfd_sfp : N2VS;
-def : N2VSPat<fabs, f32, v2f32, VABSfd_sfp>;
+def : N2VSPat<fabs, f32, v2f32, VABSfd>;
 
 // Vector Negate used for single-precision FP
-def  VNEGfd_sfp : N2VS;
-def : N2VSPat<fneg, f32, v2f32, VNEGfd_sfp>;
+def : N2VSPat<fneg, f32, v2f32, VNEGfd>;
 
 // Vector Maximum used for single-precision FP
 let neverHasSideEffects = 1 in
@@ -4758,17 +4757,10 @@
 def : N3VSPat<NEONfmin, VMINfd_sfp>;
 
 // Vector Convert between single-precision FP and integer
-def  VCVTf2sd_sfp : N2VS;
-def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
-
-def  VCVTf2ud_sfp : N2VS;
-def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
-
-def  VCVTs2fd_sfp : N2VS;
-def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
-
-def  VCVTu2fd_sfp : N2VS;
-def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
+def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd>;
+def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud>;
+def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd>;
+def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns



From bob.wilson at apple.com  Mon Dec 13 16:05:55 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 13 Dec 2010 22:05:55 -0000
Subject: [llvm-commits] [llvm] r121719 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20101213220555.703ED2A6C12E@llvm.org>

Author: bwilson
Date: Mon Dec 13 16:05:55 2010
New Revision: 121719

URL: http://llvm.org/viewvc/llvm-project?rev=121719&view=rev
Log:
Delete a line that I forgot to revert previously.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121719&r1=121718&r2=121719&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 13 16:05:55 2010
@@ -1668,7 +1668,6 @@
 //===----------------------------------------------------------------------===//
 
 // Basic 2-register operations: single-, double- and quad-register.
-let neverHasSideEffects = 1 in
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>



From resistor at mac.com  Mon Dec 13 16:29:52 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 13 Dec 2010 22:29:52 -0000
Subject: [llvm-commits] [llvm] r121721 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMCodeEmitter.cpp
 lib/Target/ARM/ARMConstantIslandPass.cpp
 lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMFixupKinds.h
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp
 utils/TableGen/EDEmitter.cpp
Message-ID: <20101213222952.D813F2A6C12C@llvm.org>

Author: resistor
Date: Mon Dec 13 16:29:52 2010
New Revision: 121721

URL: http://llvm.org/viewvc/llvm-project?rev=121721&view=rev
Log:
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR.  Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 16:29:52 2010
@@ -136,6 +136,25 @@
     // Encode the immediate and shift the opcode into place.
     return ARM_AM::getSOImmVal(Value) | (opc << 21);
   }
+  
+  case ARM::fixup_t2_adr_pcrel_12: {
+    Value -= 4;
+    unsigned opc = 0;
+    if ((int64_t)Value < 0) {
+      Value = -Value;
+      opc = 5;
+    }
+
+    uint32_t out = (opc << 21);
+    out |= (Value & 0x800) << 14;
+    out |= (Value & 0x700) << 4;
+    out |= (Value & 0x0FF);
+    
+    uint64_t swapped = (out & 0xFFFF0000) >> 16;
+    swapped |= (out & 0x0000FFFF) << 16;
+    return swapped;
+  }
+  
   case ARM::fixup_arm_branch:
     // These values don't encode the low two bits since they're always zero.
     // Offset by 8 just as above.
@@ -356,6 +375,7 @@
   case ARM::fixup_t2_condbranch:
   case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_t2_pcrel_10:
+  case ARM::fixup_t2_adr_pcrel_12:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:
     return 4;

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 16:29:52 2010
@@ -213,6 +213,8 @@
       const { return 0; }
     unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
     unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Dec 13 16:29:52 2010
@@ -594,7 +594,7 @@
             NegOk = true;
             IsSoImm = true;
             break;
-          case ARM::t2LEApcrel:
+          case ARM::t2ADR:
             Bits = 12;
             NegOk = true;
             break;
@@ -1555,7 +1555,7 @@
     unsigned Bits = 0;
     switch (Opcode) {
     default: break;
-    case ARM::t2LEApcrel:
+    case ARM::t2ADR:
       if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
         NewOpc = ARM::tLEApcrel;
         Bits = 8;
@@ -1754,16 +1754,16 @@
       if (!OptOk)
         continue;
 
-      // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
+      // Now scan back again to find the tLEApcrel or t2ADR instruction
       // that gave us the initial base register definition.
       for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
         ;
 
-      // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
+      // The instruction should be a tLEApcrel or t2ADR; we want
       // to delete it as well.
       MachineInstr *LeaMI = PrevI;
       if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
-           LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
+           LeaMI->getOpcode() != ARM::t2ADR) ||
           LeaMI->getOperand(0).getReg() != BaseReg)
         OptOk = false;
 

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Dec 13 16:29:52 2010
@@ -763,6 +763,21 @@
       break;
     }
 
+    case ARM::t2LEApcrel:
+    case ARM::t2LEApcrelJT: {
+      bool DstIsDead = MI.getOperand(0).isDead();
+      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                                TII->get(ARM::t2ADR))
+        .addReg(MI.getOperand(0).getReg(),
+                RegState::Define | getDeadRegState(DstIsDead)) // Dst reg
+        .addOperand(MI.getOperand(1))      // Label
+        .addOperand(MI.getOperand(2))      // Pred
+        .addOperand(MI.getOperand(3));
+      TransferImpOps(MI, MIB, MIB);
+      MI.eraseFromParent();
+      return MIB;
+    }
+
     case ARM::MOVi32imm:
     case ARM::MOVCCi32imm:
     case ARM::t2MOVi32imm:

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Mon Dec 13 16:29:52 2010
@@ -33,6 +33,9 @@
   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
   // instruction.
   fixup_arm_adr_pcrel_12,
+  // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
+  // instruction.
+  fixup_t2_adr_pcrel_12,
   // fixup_arm_branch - 24-bit PC relative relocation for direct branch
   // instructions.
   fixup_arm_branch,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec 13 16:29:52 2010
@@ -131,6 +131,12 @@
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
+// ADR instruction labels.
+def t2adrlabel : Operand<i32> {
+  let EncoderMethod = "getT2AdrLabelOpValue";
+}
+
+
 // t2addrmode_imm8  := reg +/- imm8
 def t2addrmode_imm8 : Operand<i32>,
                       ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
@@ -1128,10 +1134,11 @@
 
 // LEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-let neverHasSideEffects = 1 in {
-let isReMaterializable = 1 in
-def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
-                      "adr${p}.w\t$Rd, #$label", []> {
+let neverHasSideEffects = 1, isReMaterializable = 1 in {
+
+def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
+              (ins t2adrlabel:$addr, pred:$p),
+              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25-24} = 0b10;
   // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
@@ -1139,20 +1146,22 @@
   let Inst{20} = 0;
   let Inst{19-16} = 0b1111; // Rn
   let Inst{15} = 0;
-
-
+  
+  bits<4> Rd;
+  bits<13> addr;
+  let Inst{11-8} = Rd;
+  let Inst{23}    = addr{12};
+  let Inst{21}    = addr{12};
+  let Inst{26}    = addr{11};
+  let Inst{14-12} = addr{10-8};
+  let Inst{7-0}   = addr{7-0};
 }
-} // neverHasSideEffects
-def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
+
+def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
+                            IIC_iALUi, []>;
+def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
                         (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
-                        "adr${p}.w\t$Rd, #${label}_${id}", []> {
-  let Inst{31-27} = 0b11110;
-  let Inst{25-24} = 0b10;
-  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
-  let Inst{22} = 0;
-  let Inst{20} = 0;
-  let Inst{19-16} = 0b1111; // Rn
-  let Inst{15} = 0;
+                        []>;
 }
 
 

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 16:29:52 2010
@@ -56,6 +56,8 @@
 { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
+                                                MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_branch",        1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
@@ -133,6 +135,9 @@
   /// ADR label target.
   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
                               SmallVectorImpl<MCFixup> &Fixups) const;
+  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
+  
 
   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
   /// operand.
@@ -544,6 +549,16 @@
                                   Fixups);
 }
 
+/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
+/// target.
+uint32_t ARMMCCodeEmitter::
+getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
+  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
+  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
+                                  Fixups);
+}
+
 /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
 uint32_t ARMMCCodeEmitter::
 getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121721&r1=121720&r2=121721&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 16:29:52 2010
@@ -584,6 +584,7 @@
   IMM("t_imm_s4");
   IMM("pclabel");
   IMM("adrlabel");
+  IMM("t2adrlabel");
   IMM("shift_imm");
   IMM("neon_vcvt_imm32");
 



From gohman at apple.com  Mon Dec 13 16:47:57 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 13 Dec 2010 22:47:57 -0000
Subject: [llvm-commits] [llvm] r121723 -
	/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
Message-ID: <20101213224757.374D82A6C12C@llvm.org>

Author: djg
Date: Mon Dec 13 16:47:57 2010
New Revision: 121723

URL: http://llvm.org/viewvc/llvm-project?rev=121723&view=rev
Log:
Update memdep to handle PartialAlias as MayAlias.

Modified:
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=121723&r1=121722&r2=121723&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Dec 13 16:47:57 2010
@@ -291,7 +291,7 @@
         continue;
       
       // May-alias loads don't depend on each other without a dependence.
-      if (isLoad && R == AliasAnalysis::MayAlias)
+      if (isLoad && R != AliasAnalysis::MustAlias)
         continue;
 
       // Stores don't alias loads from read-only memory.
@@ -323,9 +323,9 @@
       
       if (R == AliasAnalysis::NoAlias)
         continue;
-      if (R == AliasAnalysis::MayAlias)
-        return MemDepResult::getClobber(Inst);
-      return MemDepResult::getDef(Inst);
+      if (R == AliasAnalysis::MustAlias)
+        return MemDepResult::getDef(Inst);
+      return MemDepResult::getClobber(Inst);
     }
 
     // If this is an allocation, and if we know that the accessed pointer is to



From gohman at apple.com  Mon Dec 13 16:50:24 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 13 Dec 2010 22:50:24 -0000
Subject: [llvm-commits] [llvm] r121725 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp
 test/Analysis/TypeBasedAliasAnalysis/precedence.ll
Message-ID: <20101213225024.5F8072A6C12C@llvm.org>

Author: djg
Date: Mon Dec 13 16:50:24 2010
New Revision: 121725

URL: http://llvm.org/viewvc/llvm-project?rev=121725&view=rev
Log:
Reapply r121520, PartialAlias implementation for BasicAA, now that
memdep is updated to handle it.

Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=121725&r1=121724&r2=121725&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Dec 13 16:50:24 2010
@@ -857,6 +857,17 @@
   if (GEP1BaseOffset == 0 && GEP1VariableIndices.empty())
     return MustAlias;
 
+  // If there is a difference betwen the pointers, but the difference is
+  // less than the size of the associated memory object, then we know
+  // that the objects are partially overlapping.
+  if (GEP1BaseOffset != 0 && GEP1VariableIndices.empty()) {
+    if (GEP1BaseOffset >= 0 ?
+        (V2Size != UnknownSize && (uint64_t)GEP1BaseOffset < V2Size) :
+        (V1Size != UnknownSize && -(uint64_t)GEP1BaseOffset < V1Size &&
+         GEP1BaseOffset != INT64_MIN))
+      return PartialAlias;
+  }
+
   // If we have a known constant offset, see if this offset is larger than the
   // access size being queried.  If so, and if no variable indices can remove
   // pieces of this constant, then we know we have a no-alias.  For example,

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll?rev=121725&r1=121724&r2=121725&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Mon Dec 13 16:50:24 2010
@@ -1,5 +1,5 @@
-; RUN: opt -enable-tbaa -basicaa -tbaa -gvn -instcombine -S < %s | grep {ret i32 0}
-; RUN: opt -enable-tbaa -tbaa -basicaa -gvn -instcombine -S < %s | grep {ret i32 1075000115}
+; RUN: opt -enable-tbaa -basicaa -tbaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=TBAA
+; RUN: opt -enable-tbaa -tbaa -basicaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=BASICAA
 
 ; According to the TBAA metadata the load and store don't alias. However,
 ; according to the actual code, they do. The order of the alias analysis
@@ -7,6 +7,12 @@
 
 target datalayout = "e-p:64:64:64"
 
+; Test for simple MustAlias aliasing.
+
+; TBAA:    @trouble
+; TBAA:      ret i32 0
+; BASICAA: @trouble
+; BASICAA:   ret i32 1075000115
 define i32 @trouble(i32* %x) nounwind {
 entry:
   store i32 0, i32* %x, !tbaa !0
@@ -16,6 +22,25 @@
   ret i32 %tmp3
 }
 
+; Test for PartialAlias aliasing. GVN doesn't yet eliminate the load
+; in the BasicAA case.
+
+; TBAA:    @offset
+; TBAA:      ret i64 0
+; BASICAA: @offset
+; BASICAA:   ret i64 %tmp3
+define i64 @offset(i64* %x) nounwind {
+entry:
+  store i64 0, i64* %x, !tbaa !4
+  %0 = bitcast i64* %x to i8*
+  %1 = getelementptr i8* %0, i64 1
+  store i8 1, i8* %1, !tbaa !5
+  %tmp3 = load i64* %x, !tbaa !4
+  ret i64 %tmp3
+}
+
 !0 = metadata !{metadata !"int", metadata !1}
 !1 = metadata !{metadata !"simple"}
 !3 = metadata !{metadata !"float", metadata !1}
+!4 = metadata !{metadata !"long", metadata !1}
+!5 = metadata !{metadata !"small", metadata !1}



From resistor at mac.com  Mon Dec 13 16:51:08 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 13 Dec 2010 22:51:08 -0000
Subject: [llvm-commits] [llvm] r121726 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMCodeEmitter.cpp
 lib/Target/ARM/ARMConstantIslandPass.cpp
 lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMFixupKinds.h
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp
 utils/TableGen/EDEmitter.cpp
Message-ID: <20101213225108.C82E02A6C12C@llvm.org>

Author: resistor
Date: Mon Dec 13 16:51:08 2010
New Revision: 121726

URL: http://llvm.org/viewvc/llvm-project?rev=121726&view=rev
Log:
Revert r121721, which broke buildbots.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 16:51:08 2010
@@ -136,25 +136,6 @@
     // Encode the immediate and shift the opcode into place.
     return ARM_AM::getSOImmVal(Value) | (opc << 21);
   }
-  
-  case ARM::fixup_t2_adr_pcrel_12: {
-    Value -= 4;
-    unsigned opc = 0;
-    if ((int64_t)Value < 0) {
-      Value = -Value;
-      opc = 5;
-    }
-
-    uint32_t out = (opc << 21);
-    out |= (Value & 0x800) << 14;
-    out |= (Value & 0x700) << 4;
-    out |= (Value & 0x0FF);
-    
-    uint64_t swapped = (out & 0xFFFF0000) >> 16;
-    swapped |= (out & 0x0000FFFF) << 16;
-    return swapped;
-  }
-  
   case ARM::fixup_arm_branch:
     // These values don't encode the low two bits since they're always zero.
     // Offset by 8 just as above.
@@ -375,7 +356,6 @@
   case ARM::fixup_t2_condbranch:
   case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_t2_pcrel_10:
-  case ARM::fixup_t2_adr_pcrel_12:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:
     return 4;

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 16:51:08 2010
@@ -213,8 +213,6 @@
       const { return 0; }
     unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
-    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
-      const { return 0; }
     unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Dec 13 16:51:08 2010
@@ -594,7 +594,7 @@
             NegOk = true;
             IsSoImm = true;
             break;
-          case ARM::t2ADR:
+          case ARM::t2LEApcrel:
             Bits = 12;
             NegOk = true;
             break;
@@ -1555,7 +1555,7 @@
     unsigned Bits = 0;
     switch (Opcode) {
     default: break;
-    case ARM::t2ADR:
+    case ARM::t2LEApcrel:
       if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
         NewOpc = ARM::tLEApcrel;
         Bits = 8;
@@ -1754,16 +1754,16 @@
       if (!OptOk)
         continue;
 
-      // Now scan back again to find the tLEApcrel or t2ADR instruction
+      // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
       // that gave us the initial base register definition.
       for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
         ;
 
-      // The instruction should be a tLEApcrel or t2ADR; we want
+      // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
       // to delete it as well.
       MachineInstr *LeaMI = PrevI;
       if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
-           LeaMI->getOpcode() != ARM::t2ADR) ||
+           LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
           LeaMI->getOperand(0).getReg() != BaseReg)
         OptOk = false;
 

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Dec 13 16:51:08 2010
@@ -763,21 +763,6 @@
       break;
     }
 
-    case ARM::t2LEApcrel:
-    case ARM::t2LEApcrelJT: {
-      bool DstIsDead = MI.getOperand(0).isDead();
-      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                                TII->get(ARM::t2ADR))
-        .addReg(MI.getOperand(0).getReg(),
-                RegState::Define | getDeadRegState(DstIsDead)) // Dst reg
-        .addOperand(MI.getOperand(1))      // Label
-        .addOperand(MI.getOperand(2))      // Pred
-        .addOperand(MI.getOperand(3));
-      TransferImpOps(MI, MIB, MIB);
-      MI.eraseFromParent();
-      return MIB;
-    }
-
     case ARM::MOVi32imm:
     case ARM::MOVCCi32imm:
     case ARM::t2MOVi32imm:

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Mon Dec 13 16:51:08 2010
@@ -33,9 +33,6 @@
   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
   // instruction.
   fixup_arm_adr_pcrel_12,
-  // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
-  // instruction.
-  fixup_t2_adr_pcrel_12,
   // fixup_arm_branch - 24-bit PC relative relocation for direct branch
   // instructions.
   fixup_arm_branch,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec 13 16:51:08 2010
@@ -131,12 +131,6 @@
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
-// ADR instruction labels.
-def t2adrlabel : Operand<i32> {
-  let EncoderMethod = "getT2AdrLabelOpValue";
-}
-
-
 // t2addrmode_imm8  := reg +/- imm8
 def t2addrmode_imm8 : Operand<i32>,
                       ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
@@ -1134,11 +1128,10 @@
 
 // LEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-let neverHasSideEffects = 1, isReMaterializable = 1 in {
-
-def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
-              (ins t2adrlabel:$addr, pred:$p),
-              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
+let neverHasSideEffects = 1 in {
+let isReMaterializable = 1 in
+def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
+                      "adr${p}.w\t$Rd, #$label", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25-24} = 0b10;
   // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
@@ -1146,22 +1139,20 @@
   let Inst{20} = 0;
   let Inst{19-16} = 0b1111; // Rn
   let Inst{15} = 0;
-  
-  bits<4> Rd;
-  bits<13> addr;
-  let Inst{11-8} = Rd;
-  let Inst{23}    = addr{12};
-  let Inst{21}    = addr{12};
-  let Inst{26}    = addr{11};
-  let Inst{14-12} = addr{10-8};
-  let Inst{7-0}   = addr{7-0};
-}
 
-def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
-                            IIC_iALUi, []>;
-def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
+
+}
+} // neverHasSideEffects
+def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
                         (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
-                        []>;
+                        "adr${p}.w\t$Rd, #${label}_${id}", []> {
+  let Inst{31-27} = 0b11110;
+  let Inst{25-24} = 0b10;
+  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
+  let Inst{22} = 0;
+  let Inst{20} = 0;
+  let Inst{19-16} = 0b1111; // Rn
+  let Inst{15} = 0;
 }
 
 

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 16:51:08 2010
@@ -56,8 +56,6 @@
 { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                                MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_branch",        1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
@@ -135,9 +133,6 @@
   /// ADR label target.
   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
                               SmallVectorImpl<MCFixup> &Fixups) const;
-  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
-                              SmallVectorImpl<MCFixup> &Fixups) const;
-  
 
   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
   /// operand.
@@ -549,16 +544,6 @@
                                   Fixups);
 }
 
-/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
-/// target.
-uint32_t ARMMCCodeEmitter::
-getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
-                   SmallVectorImpl<MCFixup> &Fixups) const {
-  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
-  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
-                                  Fixups);
-}
-
 /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
 uint32_t ARMMCCodeEmitter::
 getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121726&r1=121725&r2=121726&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 16:51:08 2010
@@ -584,7 +584,6 @@
   IMM("t_imm_s4");
   IMM("pclabel");
   IMM("adrlabel");
-  IMM("t2adrlabel");
   IMM("shift_imm");
   IMM("neon_vcvt_imm32");
 



From jasonwkim at google.com  Mon Dec 13 16:53:55 2010
From: jasonwkim at google.com (Jason Kim)
Date: Mon, 13 Dec 2010 14:53:55 -0800
Subject: [llvm-commits] llvm tree busted as of -r121721.
Message-ID: <AANLkTimTnCV30gNCYHTVe4SiSB13OwM8Xj6aM0v0JK7i@mail.gmail.com>

ARM tests are failing :(
Help!

    LLVM :: CodeGen/ARM/2009-08-29-TooLongSplat.ll
    LLVM :: CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll
    LLVM :: CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
    LLVM :: CodeGen/Thumb2/buildvector-crash.ll
    LLVM :: CodeGen/Thumb2/thumb2-jtb.ll
    LLVM :: CodeGen/Thumb2/thumb2-tbb.ll
    LLVM :: CodeGen/Thumb2/thumb2-tbh.ll

Thanks!
-jason

From gohman at apple.com  Mon Dec 13 16:53:18 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 13 Dec 2010 22:53:18 -0000
Subject: [llvm-commits] [llvm] r121727 - /llvm/trunk/lib/Analysis/Lint.cpp
Message-ID: <20101213225318.B6D712A6C12C@llvm.org>

Author: djg
Date: Mon Dec 13 16:53:18 2010
New Revision: 121727

URL: http://llvm.org/viewvc/llvm-project?rev=121727&view=rev
Log:
Update a comment.

Modified:
    llvm/trunk/lib/Analysis/Lint.cpp

Modified: llvm/trunk/lib/Analysis/Lint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Lint.cpp?rev=121727&r1=121726&r2=121727&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Lint.cpp (original)
+++ llvm/trunk/lib/Analysis/Lint.cpp Mon Dec 13 16:53:18 2010
@@ -226,10 +226,9 @@
                 "Undefined behavior: Call argument type mismatches "
                 "callee parameter type", &I);
 
-        // Check that noalias arguments don't alias other arguments. The
-        // AliasAnalysis API isn't expressive enough for what we really want
-        // to do. Known partial overlap is not distinguished from the case
-        // where nothing is known.
+        // Check that noalias arguments don't alias other arguments. This is
+        // not fully precise because we don't know the sizes of the dereferenced
+        // memory regions.
         if (Formal->hasNoAliasAttr() && Actual->getType()->isPointerTy())
           for (CallSite::arg_iterator BI = CS.arg_begin(); BI != AE; ++BI)
             if (AI != BI && (*BI)->getType()->isPointerTy()) {



From sabre at nondot.org  Mon Dec 13 17:02:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 23:02:20 -0000
Subject: [llvm-commits] [llvm] r121728 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101213230220.1220D2A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 17:02:19 2010
New Revision: 121728

URL: http://llvm.org/viewvc/llvm-project?rev=121728&view=rev
Log:
temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121728&r1=121727&r2=121728&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 17:02:19 2010
@@ -1515,7 +1515,7 @@
       AddPredecessorToBlock(FalseDest, PredBlock, BB);
       PBI->setSuccessor(1, FalseDest);
     }
-    return SimplifyCFG(PBI->getParent()) | true;
+    return SimplifyCFG(BB) | true;
   }
   return false;
 }

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121728&r1=121727&r2=121728&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 17:02:19 2010
@@ -253,21 +253,21 @@
   ret i32 %conv46
   
 ; CHECK: @test9
-; CHECK:   %cmp = icmp ult i8 %c, 33
-; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
+; HECK:   %cmp = icmp ult i8 %c, 33
+; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
-; CHECK: switch.early.test:
-; CHECK:   switch i8 %c, label %lor.rhs [
-; CHECK:     i8 46, label %lor.end
-; CHECK:     i8 44, label %lor.end
-; CHECK:     i8 58, label %lor.end
-; CHECK:     i8 59, label %lor.end
-; CHECK:     i8 60, label %lor.end
-; CHECK:     i8 62, label %lor.end
-; CHECK:     i8 34, label %lor.end
-; CHECK:     i8 92, label %lor.end
-; CHECK:     i8 39, label %lor.end
-; CHECK:   ]
+; HECK: switch.early.test:
+; HECK:   switch i8 %c, label %lor.rhs [
+; HECK:     i8 46, label %lor.end
+; HECK:     i8 44, label %lor.end
+; HECK:     i8 58, label %lor.end
+; HECK:     i8 59, label %lor.end
+; HECK:     i8 60, label %lor.end
+; HECK:     i8 62, label %lor.end
+; HECK:     i8 34, label %lor.end
+; HECK:     i8 92, label %lor.end
+; HECK:     i8 39, label %lor.end
+; HECK:   ]
 }
 
 define i32 @test10(i32 %mode, i1 %Cond) {
@@ -331,3 +331,24 @@
 ; CHECK:   i32 4, label %return
 ; CHECK: ]
 }
+
+define void @test12() nounwind {
+entry:
+  br label %bb49.us.us
+
+bb49.us.us:
+  %A = icmp eq i32 undef, undef
+  br i1 %A, label %bb55.us.us, label %malformed
+
+bb48.us.us:
+  %B = icmp ugt i32 undef, undef
+  br i1 %B, label %bb55.us.us, label %bb49.us.us
+
+bb55.us.us:
+  br label %bb48.us.us
+
+malformed:
+  ret void
+; CHECK: @test12
+
+}
\ No newline at end of file



From bob.wilson at apple.com  Mon Dec 13 17:02:31 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 13 Dec 2010 23:02:31 -0000
Subject: [llvm-commits] [llvm] r121729 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20101213230231.66B232A6C12C@llvm.org>

Author: bwilson
Date: Mon Dec 13 17:02:31 2010
New Revision: 121729

URL: http://llvm.org/viewvc/llvm-project?rev=121729&view=rev
Log:
Simplify N2VSPat, removing some unnecessary type arguments.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121729&r1=121728&r2=121729&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 13 17:02:31 2010
@@ -4675,14 +4675,13 @@
 // NEON instructions for single-precision FP math
 //===----------------------------------------------------------------------===//
 
-class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
-  : NEONFPPat<(ResTy (OpNode SPR:$a)),
+class N2VSPat<SDNode OpNode, NeonI Inst>
+  : NEONFPPat<(f32 (OpNode SPR:$a)),
               (EXTRACT_SUBREG
-               (OpTy (COPY_TO_REGCLASS
-                (OpTy (Inst (INSERT_SUBREG
-                 (OpTy (COPY_TO_REGCLASS (OpTy (IMPLICIT_DEF)), DPR_VFP2)),
-                                           SPR:$a, ssub_0))),
-                                       DPR_VFP2)), ssub_0)>;
+               (v2f32 (COPY_TO_REGCLASS
+                (Inst (INSERT_SUBREG
+                 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
+                 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
 
 class N3VSPat<SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
@@ -4736,10 +4735,10 @@
       Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
 
 // Vector Absolute used for single-precision FP
-def : N2VSPat<fabs, f32, v2f32, VABSfd>;
+def : N2VSPat<fabs, VABSfd>;
 
 // Vector Negate used for single-precision FP
-def : N2VSPat<fneg, f32, v2f32, VNEGfd>;
+def : N2VSPat<fneg, VNEGfd>;
 
 // Vector Maximum used for single-precision FP
 let neverHasSideEffects = 1 in
@@ -4756,10 +4755,10 @@
 def : N3VSPat<NEONfmin, VMINfd_sfp>;
 
 // Vector Convert between single-precision FP and integer
-def : N2VSPat<arm_ftosi, f32, v2f32, VCVTf2sd>;
-def : N2VSPat<arm_ftoui, f32, v2f32, VCVTf2ud>;
-def : N2VSPat<arm_sitof, f32, v2i32, VCVTs2fd>;
-def : N2VSPat<arm_uitof, f32, v2i32, VCVTu2fd>;
+def : N2VSPat<arm_ftosi, VCVTf2sd>;
+def : N2VSPat<arm_ftoui, VCVTf2ud>;
+def : N2VSPat<arm_sitof, VCVTs2fd>;
+def : N2VSPat<arm_uitof, VCVTu2fd>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns



From bob.wilson at apple.com  Mon Dec 13 17:02:37 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 13 Dec 2010 23:02:37 -0000
Subject: [llvm-commits] [llvm] r121730 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMInstrNEON.td
 test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
 utils/TableGen/ARMDecoderEmitter.cpp
Message-ID: <20101213230237.E81992A6C12D@llvm.org>

Author: bwilson
Date: Mon Dec 13 17:02:37 2010
New Revision: 121730

URL: http://llvm.org/viewvc/llvm-project?rev=121730&view=rev
Log:
Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=121730&r1=121729&r2=121730&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Dec 13 17:02:37 2010
@@ -58,8 +58,6 @@
   { ARM::VMLSS,       ARM::VMULS,       ARM::VSUBS,      false,  false },
   { ARM::VMLAD,       ARM::VMULD,       ARM::VADDD,      false,  false },
   { ARM::VMLSD,       ARM::VMULD,       ARM::VSUBD,      false,  false },
-  { ARM::VMLAfd_sfp,  ARM::VMULfd_sfp,  ARM::VADDfd_sfp, false,  false },
-  { ARM::VMLSfd_sfp,  ARM::VMULfd_sfp,  ARM::VSUBfd_sfp, false,  false },
   { ARM::VNMLAS,      ARM::VNMULS,      ARM::VSUBS,      true,   false },
   { ARM::VNMLSS,      ARM::VMULS,       ARM::VSUBS,      true,   false },
   { ARM::VNMLAD,      ARM::VNMULD,      ARM::VSUBD,      true,   false },

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121730&r1=121729&r2=121730&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Dec 13 17:02:37 2010
@@ -1667,7 +1667,7 @@
 // Instruction Classes
 //===----------------------------------------------------------------------===//
 
-// Basic 2-register operations: single-, double- and quad-register.
+// Basic 2-register operations: double- and quad-register.
 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
            bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
            string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
@@ -1736,13 +1736,7 @@
         (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
         "$src1 = $Vd, $src2 = $Vm", []>;
 
-// Basic 3-register operations: single-, double- and quad-register.
-class N3VS<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-           string OpcodeStr, string Dt>
-  : N3V<op24, op23, op21_20, op11_8, 0, op4,
-        (outs DPR_VFP2:$Vd), (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm,
-        IIC_VBIND, OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", []>;
-
+// Basic 3-register operations: double- and quad-register.
 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
            InstrItinClass itin, string OpcodeStr, string Dt,
            ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
@@ -1912,13 +1906,7 @@
   let isCommutable = 0;
 }
 
-// Multiply-Add/Sub operations: single-, double- and quad-register.
-class N3VSMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
-                InstrItinClass itin, string OpcodeStr, string Dt>
-  : N3V<op24, op23, op21_20, op11_8, 0, op4, (outs DPR_VFP2:$Vd),
-        (ins DPR_VFP2:$src1, DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, itin,
-        OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", []>;
-
+// Multiply-Add/Sub operations: double- and quad-register.
 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
                 InstrItinClass itin, string OpcodeStr, string Dt,
                 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
@@ -4678,83 +4666,47 @@
 class N2VSPat<SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$a)),
               (EXTRACT_SUBREG
-               (v2f32 (COPY_TO_REGCLASS
-                (Inst (INSERT_SUBREG
+               (v2f32 (COPY_TO_REGCLASS (Inst
+                (INSERT_SUBREG
                  (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
                  SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
 
 class N3VSPat<SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
-              (EXTRACT_SUBREG (v2f32
-                                 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                      SPR:$a, ssub_0),
-                                       (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                      SPR:$b, ssub_0))),
-                              ssub_0)>;
+              (EXTRACT_SUBREG
+               (v2f32 (COPY_TO_REGCLASS (Inst
+                (INSERT_SUBREG
+                 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
+                 SPR:$a, ssub_0),
+                (INSERT_SUBREG
+                 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
+                 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
 
 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
   : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
-              (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$acc, ssub_0),
-                                    (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$a, ssub_0),
-                                    (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
-                                                   SPR:$b, ssub_0)),
-                              ssub_0)>;
-
-// These need separate instructions because they must use DPR_VFP2 register
-// class which have SPR sub-registers.
-
-// Vector Add Operations used for single-precision FP
-let neverHasSideEffects = 1 in
-def VADDfd_sfp : N3VS<0,0,0b00,0b1101,0, "vadd", "f32">;
-def : N3VSPat<fadd, VADDfd_sfp>;
-
-// Vector Sub Operations used for single-precision FP
-let neverHasSideEffects = 1 in
-def VSUBfd_sfp : N3VS<0,0,0b10,0b1101,0, "vsub", "f32">;
-def : N3VSPat<fsub, VSUBfd_sfp>;
-
-// Vector Multiply Operations used for single-precision FP
-let neverHasSideEffects = 1 in
-def VMULfd_sfp : N3VS<1,0,0b00,0b1101,1, "vmul", "f32">;
-def : N3VSPat<fmul, VMULfd_sfp>;
-
-// Vector Multiply-Accumulate/Subtract used for single-precision FP
-// vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
-// we want to avoid them for now. e.g., alternating vmla/vadd instructions.
-
-let neverHasSideEffects = 1 in
-def VMLAfd_sfp : N3VSMulOp<0,0,0b00,0b1101,1, IIC_VMACD, "vmla", "f32">;
-def : N3VSMulOpPat<fmul, fadd, VMLAfd_sfp>,
-      Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
+              (EXTRACT_SUBREG
+               (v2f32 (COPY_TO_REGCLASS (Inst
+                (INSERT_SUBREG
+                 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
+                 SPR:$acc, ssub_0),
+                (INSERT_SUBREG
+                 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
+                 SPR:$a, ssub_0),
+                (INSERT_SUBREG
+                 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
+                 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
 
-let neverHasSideEffects = 1 in
-def VMLSfd_sfp : N3VSMulOp<0,0,0b10,0b1101,1, IIC_VMACD, "vmls", "f32">;
-def : N3VSMulOpPat<fmul, fsub, VMLSfd_sfp>,
+def : N3VSPat<fadd, VADDfd>;
+def : N3VSPat<fsub, VSUBfd>;
+def : N3VSPat<fmul, VMULfd>;
+def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
+      Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
+def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
       Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
-
-// Vector Absolute used for single-precision FP
 def : N2VSPat<fabs, VABSfd>;
-
-// Vector Negate used for single-precision FP
 def : N2VSPat<fneg, VNEGfd>;
-
-// Vector Maximum used for single-precision FP
-let neverHasSideEffects = 1 in
-def VMAXfd_sfp : N3V<0, 0, 0b00, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
-                     (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
-                     "vmax", "f32", "$Vd, $Vn, $Vm", "", []>;
-def : N3VSPat<NEONfmax, VMAXfd_sfp>;
-
-// Vector Minimum used for single-precision FP
-let neverHasSideEffects = 1 in
-def VMINfd_sfp : N3V<0, 0, 0b10, 0b1111, 0, 0, (outs DPR_VFP2:$Vd),
-                     (ins DPR_VFP2:$Vn, DPR_VFP2:$Vm), N3RegFrm, IIC_VBIND,
-                     "vmin", "f32", "$Vd, $Vn, $Vm", "", []>;
-def : N3VSPat<NEONfmin, VMINfd_sfp>;
-
-// Vector Convert between single-precision FP and integer
+def : N3VSPat<NEONfmax, VMAXfd>;
+def : N3VSPat<NEONfmin, VMINfd>;
 def : N2VSPat<arm_ftosi, VCVTf2sd>;
 def : N2VSPat<arm_ftoui, VCVTf2ud>;
 def : N2VSPat<arm_sitof, VCVTs2fd>;

Modified: llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll?rev=121730&r1=121729&r2=121730&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll Mon Dec 13 17:02:37 2010
@@ -15,9 +15,6 @@
 
 ; Loop preheader
 ; CHECK: vmov.f32
-; CHECK: vsub.f32
-; CHECK: vadd.f32
-; CHECK: vmul.f32
 bb7:                                              ; preds = %bb9, %bb.nph
   %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3]
   %tmp79 = add i32 undef, undef                   ; <i32> [#uses=1]
@@ -73,8 +70,6 @@
   br i1 %34, label %bb8, label %bb9
 
 bb9:                                              ; preds = %bb8
-; CHECK: %bb9
-; CHECK: vmov.f32
   %35 = fadd float 0.000000e+00, undef            ; <float> [#uses=1]
   br label %bb7
 }

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=121730&r1=121729&r2=121730&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Mon Dec 13 17:02:37 2010
@@ -1613,11 +1613,6 @@
         Name == "VNEGScc")
       return false;
 
-    // Ignore the *_sfp instructions when decoding.  They are used by the
-    // compiler to implement scalar floating point operations using vector
-    // operations in order to work around some performance issues.
-    if (Name.find("_sfp") != std::string::npos) return false;
-
     // LDMIA_RET is a special case of LDM (Load Multiple) where the registers
     // loaded include the PC, causing a branch to a loaded address.  Ignore
     // the LDMIA_RET instruction when decoding.



From jason.w.kim.2009 at gmail.com  Mon Dec 13 17:16:07 2010
From: jason.w.kim.2009 at gmail.com (Jason W Kim)
Date: Mon, 13 Dec 2010 23:16:07 -0000
Subject: [llvm-commits] [llvm] r121732 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp test/CodeGen/ARM/2010-12-13-reloc-pic.ll
Message-ID: <20101213231607.8D88F2A6C12C@llvm.org>

Author: jasonwkim
Date: Mon Dec 13 17:16:07 2010
New Revision: 121732

URL: http://llvm.org/viewvc/llvm-project?rev=121732&view=rev
Log:
First cut of ARM/MC/ELF PIC relocations.
Test has fixme, to move to .s -> .o test when AsmParser works better.


Added:
    llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=121732&r1=121731&r2=121732&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Dec 13 17:16:07 2010
@@ -1535,22 +1535,40 @@
 
   unsigned Type = 0;
   if (IsPCRel) {
-    switch (Modifier) {
-    default: assert(0 && "Unimplemented Modifier");
-    case MCSymbolRefExpr::VK_None: break;
-    }
     switch ((unsigned)Fixup.getKind()) {
     default: assert(0 && "Unimplemented");
-    case ARM::fixup_arm_branch: Type = ELF::R_ARM_CALL; break;
+    case FK_Data_4:
+      switch (Modifier) {
+      default: llvm_unreachable("Unsupported Modifier");
+      case MCSymbolRefExpr::VK_None:
+        Type = ELF::R_ARM_BASE_PREL; break;
+      case MCSymbolRefExpr::VK_ARM_TLSGD:
+        assert(0 && "unimplemented"); break;
+      case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
+        Type = ELF::R_ARM_TLS_IE32;
+      } break;
+    case ARM::fixup_arm_branch:
+      switch (Modifier) {
+      case MCSymbolRefExpr::VK_ARM_PLT:
+        Type = ELF::R_ARM_PLT32; break;
+      default:
+        Type = ELF::R_ARM_CALL; break;
+      } break;
     }
   } else {
     switch ((unsigned)Fixup.getKind()) {
     default: llvm_unreachable("invalid fixup kind!");
     case FK_Data_4:
       switch (Modifier) {
-      default: llvm_unreachable("Unsupported Modifier");
+      default: llvm_unreachable("Unsupported Modifier"); break;
+      case MCSymbolRefExpr::VK_ARM_GOT:
+        Type = ELF::R_ARM_GOT_BREL; break;
+      case MCSymbolRefExpr::VK_ARM_TLSGD:
+        Type = ELF::R_ARM_TLS_GD32; break;
       case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
-        Type = ELF::R_ARM_TLS_IE32;
+        Type = ELF::R_ARM_TLS_IE32; break;
+      case MCSymbolRefExpr::VK_ARM_GOTOFF:
+        Type = ELF::R_ARM_GOTOFF32; break;
       } break;
     case ARM::fixup_arm_ldst_pcrel_12:
     case ARM::fixup_arm_pcrel_10:

Added: llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll?rev=121732&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll Mon Dec 13 17:16:07 2010
@@ -0,0 +1,100 @@
+; RUN: llc  %s -mtriple=armv7-linux-gnueabi -arm-use-movt -relocation-model=pic -filetype=obj -o - | \
+; RUN:    elf-dump --dump-section-data | FileCheck  -check-prefix=PIC01 %s
+
+;; Fixme: Reduce this test further, or even better, 
+;; redo as .s -> .o test once ARM AsmParser is working better
+
+; ModuleID = 'large2.pnacl.bc'
+target triple = "armv7-none-linux-gnueabi"
+
+%struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] }
+%struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, %struct._reent*, i8*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i32, i32)*, i32 (%struct._reent*, i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._flock_t, %struct._mbstate_t, i32 }
+%struct.__sbuf = type { i8*, i32 }
+%struct.__tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+%struct._atexit = type { %struct._atexit*, i32, [32 x void ()*], %struct._on_exit_args* }
+%struct._flock_t = type { i32, i32, i32, i32, i32 }
+%struct._glue = type { %struct._glue*, i32, %struct.__FILE* }
+%struct._mbstate_t = type { i32, %union.anon }
+%struct._misc_reent = type { i8*, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, [8 x i8], i32, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t }
+%struct._mprec = type { %struct._Bigint*, i32, %struct._Bigint*, %struct._Bigint** }
+%struct._on_exit_args = type { [32 x i8*], [32 x i8*], i32, i32 }
+%struct._rand48 = type { [3 x i16], [3 x i16], i16, i64 }
+%struct._reent = type { %struct.__FILE*, %struct.__FILE*, %struct.__FILE*, i32, i32, i8*, i32, i32, i8*, %struct._mprec*, void (%struct._reent*)*, i32, i32, i8*, %struct._rand48*, %struct.__tm*, i8*, void (i32)**, %struct._atexit*, %struct._atexit, %struct._glue, %struct.__FILE*, %struct._misc_reent*, i8* }
+%union.anon = type { i32 }
+
+ at buf = constant [2 x i8] c"x\00", align 4
+ at _impure_ptr = external thread_local global %struct._reent*
+ at .str = private constant [22 x i8] c"This should fault...\0A\00", align 4
+ at .str1 = private constant [40 x i8] c"We're still running. This is not good.\0A\00", align 4
+
+define i32 @main() nounwind {
+entry:
+  %0 = load %struct._reent** @_impure_ptr, align 4
+  %1 = getelementptr inbounds %struct._reent* %0, i32 0, i32 1
+  %2 = load %struct.__FILE** %1, align 4
+  %3 = bitcast %struct.__FILE* %2 to i8*
+  %4 = tail call i32 @fwrite(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 1, i32 21, i8* %3) nounwind
+  %5 = load %struct._reent** @_impure_ptr, align 4
+  %6 = getelementptr inbounds %struct._reent* %5, i32 0, i32 1
+  %7 = load %struct.__FILE** %6, align 4
+  %8 = tail call i32 @fflush(%struct.__FILE* %7) nounwind
+  store i8 121, i8* getelementptr inbounds ([2 x i8]* @buf, i32 0, i32 0), align 4
+  %9 = load %struct._reent** @_impure_ptr, align 4
+  %10 = getelementptr inbounds %struct._reent* %9, i32 0, i32 1
+  %11 = load %struct.__FILE** %10, align 4
+  %12 = bitcast %struct.__FILE* %11 to i8*
+  %13 = tail call i32 @fwrite(i8* getelementptr inbounds ([40 x i8]* @.str1, i32 0, i32 0), i32 1, i32 39, i8* %12) nounwind
+  ret i32 1
+}
+
+
+; PIC01:             Relocation 0x00000000
+; PIC01-NEXT:        'r_offset', 0x0000001c
+; PIC01-NEXT:          'r_sym'
+; PIC01-NEXT:          'r_type', 0x0000001b
+
+
+; PIC01:             Relocation 0x00000001
+; PIC01-NEXT:      'r_offset', 0x00000038
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x0000001b
+
+; PIC01:              Relocation 0x00000002
+; PIC01-NEXT:      'r_offset', 0x00000044
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x0000001b
+
+; PIC01:              Relocation 0x00000003
+; PIC01-NEXT:      'r_offset', 0x00000070
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x0000001b
+
+; PIC01:              Relocation 0x00000004
+; PIC01-NEXT:      'r_offset', 0x0000007c
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x00000019
+
+
+; PIC01:              Relocation 0x00000005
+; PIC01-NEXT:      'r_offset', 0x00000080
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x00000018
+
+; PIC01:              Relocation 0x00000006
+; PIC01-NEXT:      'r_offset', 0x00000084
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x00000068
+
+; PIC01:              Relocation 0x00000007
+; PIC01-NEXT:      'r_offset', 0x00000088
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x0000001a
+
+; PIC01:              Relocation 0x00000008
+; PIC01-NEXT:      'r_offset', 0x0000008c
+; PIC01-NEXT:        'r_sym'
+; PIC01-NEXT:        'r_type', 0x00000018
+
+declare i32 @fwrite(i8* nocapture, i32, i32, i8* nocapture) nounwind
+
+declare i32 @fflush(%struct.__FILE* nocapture) nounwind



From grosbach at apple.com  Mon Dec 13 17:19:53 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 13 Dec 2010 15:19:53 -0800
Subject: [llvm-commits] [llvm] r121721 - in /llvm/trunk:
	lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMCodeEmitter.cpp
	lib/Target/ARM/ARMConstantIslandPass.cpp
	lib/Target/ARM/ARMExpandPseudoInsts.cpp
	lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMInstrThumb2.td
	lib/Target/ARM/ARMMCCodeEmitter.cpp utils/TableGen/EDEmitter.cpp
In-Reply-To: <20101213222952.D813F2A6C12C@llvm.org>
References: <20101213222952.D813F2A6C12C@llvm.org>
Message-ID: <07BA5055-A490-44C1-AA98-E3538D978663@apple.com>

Hi Owen,

I don't think you're going to be able to expand these pseudos that early. Note that the label is formed differently in the asm string for LEApcrel and LEApcrelJT. That currently ends up "working" through some egregious luck at MC time even though the symbols are wrong. Better is to keep them as pseudos until MC lowering as part of ARMAsmPrinter, where the symbol can be created and properly (see the ARM versions of these insns for reference, and possibly re-use w/ some opcode tweaking).

-Jim

On Dec 13, 2010, at 2:29 PM, Owen Anderson wrote:

> Author: resistor
> Date: Mon Dec 13 16:29:52 2010
> New Revision: 121721
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121721&view=rev
> Log:
> Make Thumb2 LEA-like instruction into pseudos, which map down to ADR.  Provide correct fixups for Thumb2 ADR,
> which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
>    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
>    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
>    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>    llvm/trunk/utils/TableGen/EDEmitter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 16:29:52 2010
> @@ -136,6 +136,25 @@
>     // Encode the immediate and shift the opcode into place.
>     return ARM_AM::getSOImmVal(Value) | (opc << 21);
>   }
> +  
> +  case ARM::fixup_t2_adr_pcrel_12: {
> +    Value -= 4;
> +    unsigned opc = 0;
> +    if ((int64_t)Value < 0) {
> +      Value = -Value;
> +      opc = 5;
> +    }
> +
> +    uint32_t out = (opc << 21);
> +    out |= (Value & 0x800) << 14;
> +    out |= (Value & 0x700) << 4;
> +    out |= (Value & 0x0FF);
> +    
> +    uint64_t swapped = (out & 0xFFFF0000) >> 16;
> +    swapped |= (out & 0x0000FFFF) << 16;
> +    return swapped;
> +  }
> +  
>   case ARM::fixup_arm_branch:
>     // These values don't encode the low two bits since they're always zero.
>     // Offset by 8 just as above.
> @@ -356,6 +375,7 @@
>   case ARM::fixup_t2_condbranch:
>   case ARM::fixup_t2_uncondbranch:
>   case ARM::fixup_t2_pcrel_10:
> +  case ARM::fixup_t2_adr_pcrel_12:
>   case ARM::fixup_arm_thumb_bl:
>   case ARM::fixup_arm_thumb_blx:
>     return 4;
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 16:29:52 2010
> @@ -213,6 +213,8 @@
>       const { return 0; }
>     unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
> +    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
> +      const { return 0; }
>     unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
>     unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Mon Dec 13 16:29:52 2010
> @@ -594,7 +594,7 @@
>             NegOk = true;
>             IsSoImm = true;
>             break;
> -          case ARM::t2LEApcrel:
> +          case ARM::t2ADR:
>             Bits = 12;
>             NegOk = true;
>             break;
> @@ -1555,7 +1555,7 @@
>     unsigned Bits = 0;
>     switch (Opcode) {
>     default: break;
> -    case ARM::t2LEApcrel:
> +    case ARM::t2ADR:
>       if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
>         NewOpc = ARM::tLEApcrel;
>         Bits = 8;
> @@ -1754,16 +1754,16 @@
>       if (!OptOk)
>         continue;
> 
> -      // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
> +      // Now scan back again to find the tLEApcrel or t2ADR instruction
>       // that gave us the initial base register definition.
>       for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
>         ;
> 
> -      // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
> +      // The instruction should be a tLEApcrel or t2ADR; we want
>       // to delete it as well.
>       MachineInstr *LeaMI = PrevI;
>       if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
> -           LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
> +           LeaMI->getOpcode() != ARM::t2ADR) ||
>           LeaMI->getOperand(0).getReg() != BaseReg)
>         OptOk = false;
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Dec 13 16:29:52 2010
> @@ -763,6 +763,21 @@
>       break;
>     }
> 
> +    case ARM::t2LEApcrel:
> +    case ARM::t2LEApcrelJT: {
> +      bool DstIsDead = MI.getOperand(0).isDead();
> +      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
> +                                TII->get(ARM::t2ADR))
> +        .addReg(MI.getOperand(0).getReg(),
> +                RegState::Define | getDeadRegState(DstIsDead)) // Dst reg
> +        .addOperand(MI.getOperand(1))      // Label
> +        .addOperand(MI.getOperand(2))      // Pred
> +        .addOperand(MI.getOperand(3));
> +      TransferImpOps(MI, MIB, MIB);
> +      MI.eraseFromParent();
> +      return MIB;
> +    }
> +
>     case ARM::MOVi32imm:
>     case ARM::MOVCCi32imm:
>     case ARM::t2MOVi32imm:
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Mon Dec 13 16:29:52 2010
> @@ -33,6 +33,9 @@
>   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
>   // instruction.
>   fixup_arm_adr_pcrel_12,
> +  // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
> +  // instruction.
> +  fixup_t2_adr_pcrel_12,
>   // fixup_arm_branch - 24-bit PC relative relocation for direct branch
>   // instructions.
>   fixup_arm_branch,
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec 13 16:29:52 2010
> @@ -131,6 +131,12 @@
>   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
> }
> 
> +// ADR instruction labels.
> +def t2adrlabel : Operand<i32> {
> +  let EncoderMethod = "getT2AdrLabelOpValue";
> +}
> +
> +
> // t2addrmode_imm8  := reg +/- imm8
> def t2addrmode_imm8 : Operand<i32>,
>                       ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
> @@ -1128,10 +1134,11 @@
> 
> // LEApcrel - Load a pc-relative address into a register without offending the
> // assembler.
> -let neverHasSideEffects = 1 in {
> -let isReMaterializable = 1 in
> -def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
> -                      "adr${p}.w\t$Rd, #$label", []> {
> +let neverHasSideEffects = 1, isReMaterializable = 1 in {
> +
> +def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
> +              (ins t2adrlabel:$addr, pred:$p),
> +              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
>   let Inst{31-27} = 0b11110;
>   let Inst{25-24} = 0b10;
>   // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
> @@ -1139,20 +1146,22 @@
>   let Inst{20} = 0;
>   let Inst{19-16} = 0b1111; // Rn
>   let Inst{15} = 0;
> -
> -
> +  
> +  bits<4> Rd;
> +  bits<13> addr;
> +  let Inst{11-8} = Rd;
> +  let Inst{23}    = addr{12};
> +  let Inst{21}    = addr{12};
> +  let Inst{26}    = addr{11};
> +  let Inst{14-12} = addr{10-8};
> +  let Inst{7-0}   = addr{7-0};
> }
> -} // neverHasSideEffects
> -def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
> +
> +def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
> +                            IIC_iALUi, []>;
> +def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
>                         (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
> -                        "adr${p}.w\t$Rd, #${label}_${id}", []> {
> -  let Inst{31-27} = 0b11110;
> -  let Inst{25-24} = 0b10;
> -  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
> -  let Inst{22} = 0;
> -  let Inst{20} = 0;
> -  let Inst{19-16} = 0b1111; // Rn
> -  let Inst{15} = 0;
> +                        []>;
> }
> 
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 16:29:52 2010
> @@ -56,6 +56,8 @@
> { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
>                                                 MCFixupKindInfo::FKF_IsAligned},
> { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
> +{ "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
> +                                                MCFixupKindInfo::FKF_IsAligned},
> { "fixup_arm_branch",        1,            24,  MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
> @@ -133,6 +135,9 @@
>   /// ADR label target.
>   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
>                               SmallVectorImpl<MCFixup> &Fixups) const;
> +  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
> +                              SmallVectorImpl<MCFixup> &Fixups) const;
> +  
> 
>   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
>   /// operand.
> @@ -544,6 +549,16 @@
>                                   Fixups);
> }
> 
> +/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
> +/// target.
> +uint32_t ARMMCCodeEmitter::
> +getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
> +                   SmallVectorImpl<MCFixup> &Fixups) const {
> +  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
> +  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
> +                                  Fixups);
> +}
> +
> /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
> uint32_t ARMMCCodeEmitter::
> getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
> 
> Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121721&r1=121720&r2=121721&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 16:29:52 2010
> @@ -584,6 +584,7 @@
>   IMM("t_imm_s4");
>   IMM("pclabel");
>   IMM("adrlabel");
> +  IMM("t2adrlabel");
>   IMM("shift_imm");
>   IMM("neon_vcvt_imm32");
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From dag at cray.com  Mon Dec 13 17:27:47 2010
From: dag at cray.com (David A. Greene)
Date: Mon, 13 Dec 2010 17:27:47 -0600
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	(Jason Kim's message of "Mon, 13 Dec 2010 14:37:26 -0600")
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
Message-ID: <nng8vztntho.fsf@royale.us.cray.com>

Jason Kim <jasonwkim at google.com> writes:

> I'd vote getting rid of the llvm-gcc bindir being prepended as the
> easiest solution to fix this.

That won't fix the underlying problem.  What if the tester just happens
to have an llc, opt, etc. in her PATH?  We need to give absolute paths
to the tools we're testing, otherwise we don't know what we're testing.

> If the list of executables changes, then the explicit list of known
> tools need to change as well.
> Problem is, I can't immediately think of a nice way to get the list of
> generated execs exported to llvm-lit,

Do we create new tools all that often?

                                -Dave

From resistor at mac.com  Mon Dec 13 17:49:28 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 13 Dec 2010 23:49:28 -0000
Subject: [llvm-commits] [llvm] r121733 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101213234928.715CD2A6C12C@llvm.org>

Author: resistor
Date: Mon Dec 13 17:49:28 2010
New Revision: 121733

URL: http://llvm.org/viewvc/llvm-project?rev=121733&view=rev
Log:
Fix recent buildbot breakage by pulling SimplifyCFG back to its state as of r121694, the most recent state
where I'm confident there were no crashes or miscompilations.  XFAIL the test added since then for now.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121733&r1=121732&r2=121733&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 17:49:28 2010
@@ -1515,7 +1515,7 @@
       AddPredecessorToBlock(FalseDest, PredBlock, BB);
       PBI->setSuccessor(1, FalseDest);
     }
-    return SimplifyCFG(BB) | true;
+    return SimplifyCFG(PBI->getParent()) | true;
   }
   return false;
 }
@@ -1905,25 +1905,17 @@
   
   BasicBlock *BB = BI->getParent();
   
-  DEBUG(dbgs() << "CONVERTING 'icmp' CHAIN with " << Values.size()
-               << " cases into SWITCH.  BB is:\n" << *BB);
-  
   // If there are any extra values that couldn't be folded into the switch
   // then we evaluate them with an explicit branch first.  Split the block
   // right before the condbr to handle it.
   if (ExtraCase) {
-    DEBUG(dbgs() << "  ** 'icmp' chain unhandled condition: " << *ExtraCase
-                 << '\n');
+    return false;
     
     BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
     // Remove the uncond branch added to the old block.
     TerminatorInst *OldTI = BB->getTerminator();
     
-    if (TrueWhenEqual)
-      BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
-    else
-      BranchInst::Create(NewBB, EdgeBB, ExtraCase, OldTI);
-      
+    BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
     OldTI->eraseFromParent();
     
     // If there are PHI nodes in EdgeBB, then we need to add a new entry to them
@@ -1963,7 +1955,6 @@
   
   // Erase the old branch instruction.
   EraseTerminatorInstAndDCECond(BI);
-  
   return true;
 }
 
@@ -2367,7 +2358,7 @@
   // branches to us and one of our successors, fold the setcc into the
   // predecessor and use logical operations to pick the right destination.
   if (FoldBranchToCommonDest(BI))
-    return true;
+    return SimplifyCFG(BB) | true;
   
   // Scan predecessor blocks for conditional branches.
   for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
@@ -2419,7 +2410,8 @@
     if (BI->isUnconditional()) {
       if (SimplifyUncondBranch(BI)) return true;
     } else {
-      if (SimplifyCondBranch(BI)) return true;
+      if (SimplifyCondBranch(BI))
+        return true;
     }
   } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
     if (SimplifyReturn(RI)) return true;

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121733&r1=121732&r2=121733&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 17:49:28 2010
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -simplifycfg -S | FileCheck %s
+; XFAIL: *
 
 declare void @foo1()
 



From resistor at mac.com  Mon Dec 13 17:53:53 2010
From: resistor at mac.com (Owen Anderson)
Date: Mon, 13 Dec 2010 15:53:53 -0800
Subject: [llvm-commits] [llvm] r121728 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <20101213230220.1220D2A6C12C@llvm.org>
References: <20101213230220.1220D2A6C12C@llvm.org>
Message-ID: <240F7665-6B9C-485B-AE81-5D99D64C09B4@mac.com>

Chris,

This patch broke a number of loop tests of the buildbots.  I've pulled SimplifyCFG back to r121694, which, from your commit messages, was the last bug-free revision.  The test you added since then is still in TOT, but XFAIL'd.

--Owen


On Dec 13, 2010, at 3:02 PM, Chris Lattner wrote:

> Author: lattner
> Date: Mon Dec 13 17:02:19 2010
> New Revision: 121728
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121728&view=rev
> Log:
> temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk.
> 
> Modified:
>    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
>    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
> 
> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121728&r1=121727&r2=121728&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 17:02:19 2010
> @@ -1515,7 +1515,7 @@
>       AddPredecessorToBlock(FalseDest, PredBlock, BB);
>       PBI->setSuccessor(1, FalseDest);
>     }
> -    return SimplifyCFG(PBI->getParent()) | true;
> +    return SimplifyCFG(BB) | true;
>   }
>   return false;
> }
> 
> Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121728&r1=121727&r2=121728&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
> +++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 17:02:19 2010
> @@ -253,21 +253,21 @@
>   ret i32 %conv46
> 
> ; CHECK: @test9
> -; CHECK:   %cmp = icmp ult i8 %c, 33
> -; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
> +; HECK:   %cmp = icmp ult i8 %c, 33
> +; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
> 
> -; CHECK: switch.early.test:
> -; CHECK:   switch i8 %c, label %lor.rhs [
> -; CHECK:     i8 46, label %lor.end
> -; CHECK:     i8 44, label %lor.end
> -; CHECK:     i8 58, label %lor.end
> -; CHECK:     i8 59, label %lor.end
> -; CHECK:     i8 60, label %lor.end
> -; CHECK:     i8 62, label %lor.end
> -; CHECK:     i8 34, label %lor.end
> -; CHECK:     i8 92, label %lor.end
> -; CHECK:     i8 39, label %lor.end
> -; CHECK:   ]
> +; HECK: switch.early.test:
> +; HECK:   switch i8 %c, label %lor.rhs [
> +; HECK:     i8 46, label %lor.end
> +; HECK:     i8 44, label %lor.end
> +; HECK:     i8 58, label %lor.end
> +; HECK:     i8 59, label %lor.end
> +; HECK:     i8 60, label %lor.end
> +; HECK:     i8 62, label %lor.end
> +; HECK:     i8 34, label %lor.end
> +; HECK:     i8 92, label %lor.end
> +; HECK:     i8 39, label %lor.end
> +; HECK:   ]
> }
> 
> define i32 @test10(i32 %mode, i1 %Cond) {
> @@ -331,3 +331,24 @@
> ; CHECK:   i32 4, label %return
> ; CHECK: ]
> }
> +
> +define void @test12() nounwind {
> +entry:
> +  br label %bb49.us.us
> +
> +bb49.us.us:
> +  %A = icmp eq i32 undef, undef
> +  br i1 %A, label %bb55.us.us, label %malformed
> +
> +bb48.us.us:
> +  %B = icmp ugt i32 undef, undef
> +  br i1 %B, label %bb55.us.us, label %bb49.us.us
> +
> +bb55.us.us:
> +  br label %bb48.us.us
> +
> +malformed:
> +  ret void
> +; CHECK: @test12
> +
> +}
> \ No newline at end of file
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From sabre at nondot.org  Mon Dec 13 18:11:23 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 13 Dec 2010 16:11:23 -0800
Subject: [llvm-commits] [llvm] r121728 - in /llvm/trunk:
	lib/Transforms/Utils/SimplifyCFG.cpp
	test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <240F7665-6B9C-485B-AE81-5D99D64C09B4@mac.com>
References: <20101213230220.1220D2A6C12C@llvm.org>
	<240F7665-6B9C-485B-AE81-5D99D64C09B4@mac.com>
Message-ID: <60606E52-FBB5-45B3-946B-6AA8C8BCE25B@nondot.org>


On Dec 13, 2010, at 3:53 PM, Owen Anderson wrote:

> Chris,
> 
> This patch broke a number of loop tests of the buildbots.  I've pulled SimplifyCFG back to r121694, which, from your commit messages, was the last bug-free revision.  The test you added since then is still in TOT, but XFAIL'd.
> 

Thanks Owen, sigh sorry for the breakage.

-Chris

From wendling at apple.com  Mon Dec 13 18:24:08 2010
From: wendling at apple.com (Bill Wendling)
Date: Mon, 13 Dec 2010 16:24:08 -0800
Subject: [llvm-commits] [llvm] r121732 - in /llvm/trunk:
	lib/MC/ELFObjectWriter.cpp test/CodeGen/ARM/2010-12-13-reloc-pic.ll
In-Reply-To: <20101213231607.8D88F2A6C12C@llvm.org>
References: <20101213231607.8D88F2A6C12C@llvm.org>
Message-ID: <F02A6E12-261D-4AF3-90B3-13501982EF89@apple.com>

On Dec 13, 2010, at 3:16 PM, Jason W Kim wrote:

> Author: jasonwkim
> Date: Mon Dec 13 17:16:07 2010
> New Revision: 121732
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121732&view=rev
> Log:
> First cut of ARM/MC/ELF PIC relocations.
> Test has fixme, to move to .s -> .o test when AsmParser works better.
> 
> 
> Added: llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll?rev=121732&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll Mon Dec 13 17:16:07 2010
> @@ -0,0 +1,100 @@
> +; RUN: llc  %s -mtriple=armv7-linux-gnueabi -arm-use-movt -relocation-model=pic -filetype=obj -o - | \
> +; RUN:    elf-dump --dump-section-data | FileCheck  -check-prefix=PIC01 %s
> +
> +;; Fixme: Reduce this test further, or even better, 

Hi Jason,

Small point: could you put the "Fixme" in upper case? That's typically what people do and it makes it easy to search for with grep.

-bw

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From resistor at mac.com  Mon Dec 13 18:36:49 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 14 Dec 2010 00:36:49 -0000
Subject: [llvm-commits] [llvm] r121735 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp
 lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMFixupKinds.h
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp
 utils/TableGen/EDEmitter.cpp
Message-ID: <20101214003649.5DF1A2A6C12C@llvm.org>

Author: resistor
Date: Mon Dec 13 18:36:49 2010
New Revision: 121735

URL: http://llvm.org/viewvc/llvm-project?rev=121735&view=rev
Log:
Second attempt at make Thumb2 LEAs pseudos.  This time, perform the lowering much later, which makes the entire
process cleaner.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Dec 13 18:36:49 2010
@@ -136,6 +136,25 @@
     // Encode the immediate and shift the opcode into place.
     return ARM_AM::getSOImmVal(Value) | (opc << 21);
   }
+  
+  case ARM::fixup_t2_adr_pcrel_12: {
+    Value -= 4;
+    unsigned opc = 0;
+    if ((int64_t)Value < 0) {
+      Value = -Value;
+      opc = 5;
+    }
+
+    uint32_t out = (opc << 21);
+    out |= (Value & 0x800) << 14;
+    out |= (Value & 0x700) << 4;
+    out |= (Value & 0x0FF);
+    
+    uint64_t swapped = (out & 0xFFFF0000) >> 16;
+    swapped |= (out & 0x0000FFFF) << 16;
+    return swapped;
+  }
+  
   case ARM::fixup_arm_branch:
     // These values don't encode the low two bits since they're always zero.
     // Offset by 8 just as above.
@@ -356,6 +375,7 @@
   case ARM::fixup_t2_condbranch:
   case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_t2_pcrel_10:
+  case ARM::fixup_t2_adr_pcrel_12:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:
     return 4;

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 13 18:36:49 2010
@@ -734,6 +734,7 @@
     }
     return;
   }
+  case ARM::t2LEApcrel:
   case ARM::LEApcrel: {
     // FIXME: Need to also handle globals and externals
     assert (MI->getOperand(1).isCPI());
@@ -741,7 +742,10 @@
     MCSymbol *Sym = GetCPISymbol(LabelId);
     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Sym, OutContext);
     MCInst TmpInst;
-    TmpInst.setOpcode(ARM::ADR);
+    if (MI->getOpcode() == ARM::LEApcrel)
+      TmpInst.setOpcode(ARM::ADR);
+    else
+      TmpInst.setOpcode(ARM::t2ADR);
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
     // Add predicate operands.
@@ -750,13 +754,17 @@
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }
+  case ARM::t2LEApcrelJT:
   case ARM::LEApcrelJT: {
     unsigned JTI = MI->getOperand(1).getIndex();
     unsigned Id = MI->getOperand(2).getImm();
     MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, Id);
     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(JTISymbol, OutContext);
     MCInst TmpInst;
-    TmpInst.setOpcode(ARM::ADR);
+    if (MI->getOpcode() == ARM::LEApcrelJT)
+      TmpInst.setOpcode(ARM::ADR);
+    else
+      TmpInst.setOpcode(ARM::t2ADR);
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
     // Add predicate operands.

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 18:36:49 2010
@@ -213,6 +213,8 @@
       const { return 0; }
     unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
     unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Mon Dec 13 18:36:49 2010
@@ -33,6 +33,9 @@
   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
   // instruction.
   fixup_arm_adr_pcrel_12,
+  // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
+  // instruction.
+  fixup_t2_adr_pcrel_12,
   // fixup_arm_branch - 24-bit PC relative relocation for direct branch
   // instructions.
   fixup_arm_branch,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec 13 18:36:49 2010
@@ -131,6 +131,12 @@
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
+// ADR instruction labels.
+def t2adrlabel : Operand<i32> {
+  let EncoderMethod = "getT2AdrLabelOpValue";
+}
+
+
 // t2addrmode_imm8  := reg +/- imm8
 def t2addrmode_imm8 : Operand<i32>,
                       ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
@@ -1128,10 +1134,9 @@
 
 // LEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-let neverHasSideEffects = 1 in {
-let isReMaterializable = 1 in
-def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
-                      "adr${p}.w\t$Rd, #$label", []> {
+def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
+              (ins t2adrlabel:$addr, pred:$p),
+              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25-24} = 0b10;
   // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
@@ -1139,21 +1144,23 @@
   let Inst{20} = 0;
   let Inst{19-16} = 0b1111; // Rn
   let Inst{15} = 0;
-
-
+  
+  bits<4> Rd;
+  bits<13> addr;
+  let Inst{11-8} = Rd;
+  let Inst{23}    = addr{12};
+  let Inst{21}    = addr{12};
+  let Inst{26}    = addr{11};
+  let Inst{14-12} = addr{10-8};
+  let Inst{7-0}   = addr{7-0};
 }
-} // neverHasSideEffects
-def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
+
+let neverHasSideEffects = 1, isReMaterializable = 1 in
+def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
+                            IIC_iALUi, []>;
+def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
                         (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
-                        "adr${p}.w\t$Rd, #${label}_${id}", []> {
-  let Inst{31-27} = 0b11110;
-  let Inst{25-24} = 0b10;
-  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
-  let Inst{22} = 0;
-  let Inst{20} = 0;
-  let Inst{19-16} = 0b1111; // Rn
-  let Inst{15} = 0;
-}
+                        []>;
 
 
 // FIXME: None of these add/sub SP special instructions should be necessary

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 18:36:49 2010
@@ -56,6 +56,8 @@
 { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
+                                                MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_branch",        1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
@@ -133,6 +135,9 @@
   /// ADR label target.
   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
                               SmallVectorImpl<MCFixup> &Fixups) const;
+  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
+  
 
   /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
   /// operand.
@@ -544,6 +549,16 @@
                                   Fixups);
 }
 
+/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
+/// target.
+uint32_t ARMMCCodeEmitter::
+getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
+  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
+  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
+                                  Fixups);
+}
+
 /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
 uint32_t ARMMCCodeEmitter::
 getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121735&r1=121734&r2=121735&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 18:36:49 2010
@@ -584,6 +584,7 @@
   IMM("t_imm_s4");
   IMM("pclabel");
   IMM("adrlabel");
+  IMM("t2adrlabel");
   IMM("shift_imm");
   IMM("neon_vcvt_imm32");
 



From stoklund at 2pi.dk  Mon Dec 13 18:37:44 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 00:37:44 -0000
Subject: [llvm-commits] [llvm] r121736 -
	/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Message-ID: <20101214003744.CFCBE2A6C12C@llvm.org>

Author: stoklund
Date: Mon Dec 13 18:37:44 2010
New Revision: 121736

URL: http://llvm.org/viewvc/llvm-project?rev=121736&view=rev
Log:
Add stub for RAGreedy::trySplit.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121736&r1=121735&r2=121736&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Dec 13 18:37:44 2010
@@ -83,6 +83,9 @@
   bool checkUncachedInterference(LiveInterval &, unsigned);
   bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
   bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
+
+  unsigned trySplit(LiveInterval&, AllocationOrder&,
+                    SmallVectorImpl<LiveInterval*>&);
 };
 } // end anonymous namespace
 
@@ -222,6 +225,15 @@
   return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
 }
 
+/// trySplit - Try to split VirtReg or one of its interferences, making it
+/// assignable.
+/// @return Physreg when VirtReg may be assigned and/or new SplitVRegs.
+unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
+                            SmallVectorImpl<LiveInterval*>&SplitVRegs) {
+  NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
+  return 0;
+}
+
 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
   // Populate a list of physical register spill candidates.
@@ -266,6 +278,10 @@
   PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
                            ReassignCands.end());
 
+  unsigned PhysReg = trySplit(VirtReg, Order, SplitVRegs);
+  if (PhysReg || !SplitVRegs.empty())
+    return PhysReg;
+
   // Try to spill another interfering reg with less spill weight.
   NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
   //



From stoklund at 2pi.dk  Mon Dec 13 18:37:49 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 00:37:49 -0000
Subject: [llvm-commits] [llvm] r121737 -
	/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Message-ID: <20101214003749.B9CA32A6C12D@llvm.org>

Author: stoklund
Date: Mon Dec 13 18:37:49 2010
New Revision: 121737

URL: http://llvm.org/viewvc/llvm-project?rev=121737&view=rev
Log:
Try reassigning all virtual register interferences, not just those with lower
spill weight. Filter out fixed registers instead.

Add support for reassigning an interference that was assigned to an alias.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121737&r1=121736&r2=121737&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Dec 13 18:37:49 2010
@@ -80,10 +80,12 @@
   static char ID;
 
 private:
-  bool checkUncachedInterference(LiveInterval &, unsigned);
+  bool checkUncachedInterference(LiveInterval&, unsigned);
+  LiveInterval *getSingleInterference(LiveInterval&, unsigned);
   bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
   bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
 
+  unsigned tryReassign(LiveInterval&, AllocationOrder&);
   unsigned trySplit(LiveInterval&, AllocationOrder&,
                     SmallVectorImpl<LiveInterval*>&);
 };
@@ -163,6 +165,35 @@
   return false;
 }
 
+/// getSingleInterference - Return the single interfering virtual register
+/// assigned to PhysReg. Return 0 if more than one virtual register is
+/// interfering.
+LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
+                                              unsigned PhysReg) {
+  LiveInterval *Interference = 0;
+
+  // Check direct interferences.
+  LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
+  if (Q.checkInterference()) {
+    if (!Q.seenAllInterferences())
+      return 0;
+    Q.collectInterferingVRegs(1);
+    Interference = Q.interferingVRegs().front();
+  }
+
+  // Check aliases.
+  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
+    LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
+    if (Q.checkInterference()) {
+      if (Interference || !Q.seenAllInterferences())
+        return 0;
+      Q.collectInterferingVRegs(1);
+      Interference = Q.interferingVRegs().front();
+    }
+  }
+  return Interference;
+}
+
 // Attempt to reassign this virtual register to a different physical register.
 //
 // FIXME: we are not yet caching these "second-level" interferences discovered
@@ -173,23 +204,26 @@
 // FIXME: This may result in a lot of alias queries. We could summarize alias
 // live intervals in their parent register's live union, but it's messy.
 bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
-                            unsigned OldPhysReg) {
-  assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
+                            unsigned WantedPhysReg) {
+  assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
+         "Can only reassign virtual registers");
+  assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
          "inconsistent phys reg assigment");
 
   AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
   while (unsigned PhysReg = Order.next()) {
-    if (PhysReg == OldPhysReg)
+    // Don't reassign to a WantedPhysReg alias.
+    if (TRI->regsOverlap(PhysReg, WantedPhysReg))
       continue;
 
     if (checkUncachedInterference(InterferingVReg, PhysReg))
       continue;
 
-    DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
-          TRI->getName(OldPhysReg) << " to " << TRI->getName(PhysReg) << '\n');
-
     // Reassign the interfering virtual reg to this physical reg.
-    PhysReg2LiveUnion[OldPhysReg].extract(InterferingVReg);
+    unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
+    DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
+          TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
+    PhysReg2LiveUnion[OldAssign].extract(InterferingVReg);
     VRM->clearVirt(InterferingVReg.reg);
     VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg);
     PhysReg2LiveUnion[PhysReg].unify(InterferingVReg);
@@ -199,30 +233,32 @@
   return false;
 }
 
-// Collect all virtual regs currently assigned to PhysReg that interfere with
-// VirtReg.
-//
-// Currently, for simplicity, we only attempt to reassign a single interference
-// within the same register class.
+/// reassignInterferences - Reassign all interferences to different physical
+/// registers such that Virtreg can be assigned to PhysReg.
+/// Currently this only works with a single interference.
+/// @param  VirtReg Currently unassigned virtual register.
+/// @param  PhysReg Physical register to be cleared.
+/// @return True on success, false if nothing was changed.
 bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
-  LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
-
-  // Limit the interference search to one interference.
-  Q.collectInterferingVRegs(1);
-  assert(Q.interferingVRegs().size() == 1 &&
-         "expected at least one interference");
-
-  // Do not attempt reassignment unless we find only a single interference.
-  if (!Q.seenAllInterferences())
+  LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
+  if (!InterferingVReg)
     return false;
+  if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
+    return false;
+  return reassignVReg(*InterferingVReg, PhysReg);
+}
 
-  // Don't allow any interferences on aliases.
-  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
-    if (query(VirtReg, *AliasI).checkInterference())
-      return false;
-  }
-
-  return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
+/// tryReassign - Try to reassign interferences to different physregs.
+/// @param  VirtReg Currently unassigned virtual register.
+/// @param  Order   Physregs to try.
+/// @return         Physreg to assign VirtReg, or 0.
+unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order) {
+  NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
+  Order.rewind();
+  while (unsigned PhysReg = Order.next())
+    if (reassignInterferences(VirtReg, PhysReg))
+      return PhysReg;
+  return 0;
 }
 
 /// trySplit - Try to split VirtReg or one of its interferences, making it
@@ -255,29 +291,15 @@
 
     // The current VirtReg must either be spillable, or one of its interferences
     // must have less spill weight.
-    if (InterferingVirtReg->weight < VirtReg.weight ) {
-      // For simplicity, only consider reassigning registers in the same class.
-      if (InterfReg == PhysReg)
-        ReassignCands.push_back(PhysReg);
-      else
-        PhysRegSpillCands.push_back(PhysReg);
-    }
+    if (InterferingVirtReg->weight < VirtReg.weight )
+      PhysRegSpillCands.push_back(PhysReg);
   }
 
-  // Try to reassign interfering physical register. Priority among
-  // PhysRegSpillCands does not matter yet, because the reassigned virtual
-  // registers will still be assigned to physical registers.
-  {
-    NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
-    for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
-          PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI)
-      if (reassignInterferences(VirtReg, *PhysRegI))
-        // Reassignment successfull. Allocate now to this PhysReg.
-        return *PhysRegI;
-  }
-  PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
-                           ReassignCands.end());
+  // Try to reassign interferences.
+  if (unsigned PhysReg = tryReassign(VirtReg, Order))
+    return PhysReg;
 
+  // Try splitting VirtReg or interferences.
   unsigned PhysReg = trySplit(VirtReg, Order, SplitVRegs);
   if (PhysReg || !SplitVRegs.empty())
     return PhysReg;



From stoklund at 2pi.dk  Mon Dec 13 18:37:52 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 00:37:52 -0000
Subject: [llvm-commits] [llvm] r121738 -
	/llvm/trunk/include/llvm/ADT/IntervalMap.h
Message-ID: <20101214003752.97B762A6C12C@llvm.org>

Author: stoklund
Date: Mon Dec 13 18:37:52 2010
New Revision: 121738

URL: http://llvm.org/viewvc/llvm-project?rev=121738&view=rev
Log:
Remove debugging code.

Modified:
    llvm/trunk/include/llvm/ADT/IntervalMap.h

Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntervalMap.h?rev=121738&r1=121737&r2=121738&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/IntervalMap.h (original)
+++ llvm/trunk/include/llvm/ADT/IntervalMap.h Mon Dec 13 18:37:52 2010
@@ -105,9 +105,6 @@
 #include "llvm/Support/RecyclingAllocator.h"
 #include <iterator>
 
-// FIXME: Remove debugging code.
-#include "llvm/Support/raw_ostream.h"
-
 namespace llvm {
 
 
@@ -590,16 +587,6 @@
   }
 
   unsigned insertFrom(unsigned &Pos, unsigned Size, KeyT a, KeyT b, ValT y);
-
-#ifndef NDEBUG
-  void dump(raw_ostream &OS, unsigned Size) {
-    OS << "  N" << this << " [shape=record label=\"{ " << Size << '/' << N;
-    for (unsigned i = 0; i != Size; ++i)
-      OS << " | {" << start(i) << '-' << stop(i) << "|" << value(i) << '}';
-    OS << "}\"];\n";
-  }
-#endif
-
 };
 
 /// insertFrom - Add mapping of [a;b] to y if possible, coalescing as much as
@@ -743,19 +730,6 @@
     subtree(i) = Node;
     stop(i) = Stop;
   }
-
-#ifndef NDEBUG
-  void dump(raw_ostream &OS, unsigned Size) {
-    OS << "  N" << this << " [shape=record label=\"" << Size << '/' << N;
-    for (unsigned i = 0; i != Size; ++i)
-      OS << " | <s" << i << "> " << stop(i);
-    OS << "\"];\n";
-    for (unsigned i = 0; i != Size; ++i)
-      OS << "  N" << this << ":s" << i << " -> N"
-         << &subtree(i).template get<BranchNode>() << ";\n";
-  }
-#endif
-
 };
 
 //===----------------------------------------------------------------------===//
@@ -922,14 +896,6 @@
     moveLeft(Level);
     ++path[Level].offset;
   }
-
-#ifndef NDEBUG
-  void dump() const {
-    for (unsigned l = 0, e = path.size(); l != e; ++l)
-      errs() << l << ": " << path[l].node << ' ' << path[l].size << ' '
-             << path[l].offset << '\n';
-  }
-#endif
 };
 
 } // namespace IntervalMapImpl
@@ -1155,12 +1121,6 @@
     I.find(x);
     return I;
   }
-
-#ifndef NDEBUG
-  raw_ostream *OS;
-  void dump();
-  void dumpNode(IntervalMapImpl::NodeRef Node, unsigned Height);
-#endif
 };
 
 /// treeSafeLookup - Return the mapped value at x or NotFound, assuming a
@@ -1304,32 +1264,6 @@
   rootSize = 0;
 }
 
-#ifndef NDEBUG
-template <typename KeyT, typename ValT, unsigned N, typename Traits>
-void IntervalMap<KeyT, ValT, N, Traits>::
-dumpNode(IntervalMapImpl::NodeRef Node, unsigned Height) {
-  if (Height)
-    Node.get<Branch>().dump(*OS, Node.size());
-  else
-    Node.get<Leaf>().dump(*OS, Node.size());
-}
-
-template <typename KeyT, typename ValT, unsigned N, typename Traits>
-void IntervalMap<KeyT, ValT, N, Traits>::
-dump() {
-  std::string errors;
-  raw_fd_ostream ofs("tree.dot", errors);
-  OS = &ofs;
-  ofs << "digraph {\n";
-  if (branched())
-    rootBranch().dump(ofs, rootSize);
-  else
-    rootLeaf().dump(ofs, rootSize);
-  visitNodes(&IntervalMap::dumpNode);
-  ofs << "}\n";
-}
-#endif
-
 //===----------------------------------------------------------------------===//
 //---                   IntervalMap::const_iterator                       ----//
 //===----------------------------------------------------------------------===//



From stoklund at 2pi.dk  Mon Dec 13 18:55:51 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 00:55:51 -0000
Subject: [llvm-commits] [llvm] r121740 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20101214005551.AFB682A6C12C@llvm.org>

Author: stoklund
Date: Mon Dec 13 18:55:51 2010
New Revision: 121740

URL: http://llvm.org/viewvc/llvm-project?rev=121740&view=rev
Log:
Add IntervalMap to the Programmer's Manual.

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=121740&r1=121739&r2=121740&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Mon Dec 13 18:55:51 2010
@@ -84,6 +84,7 @@
       <li><a href="#dss_indexedmap">"llvm/ADT/IndexedMap.h"</a></li>
       <li><a href="#dss_densemap">"llvm/ADT/DenseMap.h"</a></li>
       <li><a href="#dss_valuemap">"llvm/ADT/ValueMap.h"</a></li>
+      <li><a href="#dss_intervalmap">"llvm/ADT/IntervalMap.h"</a></li>
       <li><a href="#dss_map">&lt;map&gt;</a></li>
       <li><a href="#dss_othermap">Other Map-Like Container Options</a></li>
     </ul></li>
@@ -1509,6 +1510,23 @@
 
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsubsection">
+  <a name="dss_intervalmap">"llvm/ADT/IntervalMap.h"</a>
+</div>
+
+<div class="doc_text">
+
+<p> IntervalMap is a compact map for small keys and values. It maps key
+intervals instead of single keys, and it will automatically coalesce adjacent
+intervals. When then map only contains a few intervals, they are stored in the
+map object itself to avoid allocations.</p>
+
+<p> The IntervalMap iterators are quite big, so they should not be passed around
+as STL iterators. The heavyweight iterators allow a smaller data structure.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
   <a name="dss_map">&lt;map&gt;</a>
 </div>
 



From stoklund at 2pi.dk  Mon Dec 13 18:58:47 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 00:58:47 -0000
Subject: [llvm-commits] [llvm] r121741 -
	/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Message-ID: <20101214005847.D3F102A6C12C@llvm.org>

Author: stoklund
Date: Mon Dec 13 18:58:47 2010
New Revision: 121741

URL: http://llvm.org/viewvc/llvm-project?rev=121741&view=rev
Log:
Remove unused vector.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121741&r1=121740&r2=121741&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Dec 13 18:58:47 2010
@@ -273,7 +273,7 @@
 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
   // Populate a list of physical register spill candidates.
-  SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
+  SmallVector<unsigned, 8> PhysRegSpillCands;
 
   // Check for an available register in this class.
   AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);



From jason.w.kim.2009 at gmail.com  Mon Dec 13 19:42:39 2010
From: jason.w.kim.2009 at gmail.com (Jason W Kim)
Date: Tue, 14 Dec 2010 01:42:39 -0000
Subject: [llvm-commits] [llvm] r121743 -
	/llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll
Message-ID: <20101214014239.222A42A6C12C@llvm.org>

Author: jasonwkim
Date: Mon Dec 13 19:42:38 2010
New Revision: 121743

URL: http://llvm.org/viewvc/llvm-project?rev=121743&view=rev
Log:
fix fixme case typo :-) 

Modified:
    llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll

Modified: llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll?rev=121743&r1=121742&r2=121743&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-12-13-reloc-pic.ll Mon Dec 13 19:42:38 2010
@@ -1,7 +1,7 @@
 ; RUN: llc  %s -mtriple=armv7-linux-gnueabi -arm-use-movt -relocation-model=pic -filetype=obj -o - | \
 ; RUN:    elf-dump --dump-section-data | FileCheck  -check-prefix=PIC01 %s
 
-;; Fixme: Reduce this test further, or even better, 
+;; FIXME: Reduce this test further, or even better,
 ;; redo as .s -> .o test once ARM AsmParser is working better
 
 ; ModuleID = 'large2.pnacl.bc'



From aggarwa4 at illinois.edu  Mon Dec 13 19:50:09 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 14 Dec 2010 01:50:09 -0000
Subject: [llvm-commits] [poolalloc] r121744 -
	/poolalloc/trunk/test/dsa/callgraph/scc3.c
Message-ID: <20101214015009.5EAAD2A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Dec 13 19:50:09 2010
New Revision: 121744

URL: http://llvm.org/viewvc/llvm-project?rev=121744&view=rev
Log:
Simplified test case for infinite looping in BU. 
Happens in sqlite3.

Added:
    poolalloc/trunk/test/dsa/callgraph/scc3.c

Added: poolalloc/trunk/test/dsa/callgraph/scc3.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/callgraph/scc3.c?rev=121744&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/callgraph/scc3.c (added)
+++ poolalloc/trunk/test/dsa/callgraph/scc3.c Mon Dec 13 19:50:09 2010
@@ -0,0 +1,40 @@
+// A, B, func are in an SCC
+// C is called indirectly from A/B
+// The indirect call site in C is resolved, once we process the SCC
+// But since, we never process the SCC graph again, 
+// we never inline func into the SCC graph(of A, B, and func) at that
+// call site.
+
+// when we inline the SCCGraph into D(due to call to A), the unresolved
+// call site is also inlined. As it is complete and can be resolved
+// we inline the SCC graph again, pulling in the unresolved call site
+// again. This causes an infinte looping in BU.
+
+;XFAIL:*
+;RUN: not
+
+typedef int* (*funcptr)(int *);
+
+static int* A();
+
+static int* func(int * arg) {
+  A();
+  return arg;
+}
+
+static int* C(funcptr f, int *arg) {
+  (*f)(arg);
+}
+
+static int *B() {
+  func(A());
+  return C(func, A());
+}
+
+static int* A() {
+  return func(B());
+}
+
+static int* D() {
+  return A();
+}



From evan.cheng at apple.com  Mon Dec 13 21:22:07 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 14 Dec 2010 03:22:07 -0000
Subject: [llvm-commits] [llvm] r121746 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/bfi.ll
Message-ID: <20101214032207.F060B2A6C12C@llvm.org>

Author: evancheng
Date: Mon Dec 13 21:22:07 2010
New Revision: 121746

URL: http://llvm.org/viewvc/llvm-project?rev=121746&view=rev
Log:
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/bfi.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=121746&r1=121745&r2=121746&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Dec 13 21:22:07 2010
@@ -4809,6 +4809,25 @@
   return SDValue();
 }
 
+/// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
+/// C1 & C2 == C1.
+static SDValue PerformBFICombine(SDNode *N,
+                                 TargetLowering::DAGCombinerInfo &DCI) {
+  SDValue N1 = N->getOperand(1);
+  if (N1.getOpcode() == ISD::AND) {
+    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+    if (!N11C)
+      return SDValue();
+    unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+    unsigned Mask2 = N11C->getZExtValue();
+    if ((Mask & Mask2) == Mask2)
+      return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
+                             N->getOperand(0), N1.getOperand(0),
+                             N->getOperand(2));
+  }
+  return SDValue();
+}
+
 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
 /// ARMISD::VMOVRRD.
 static SDValue PerformVMOVRRDCombine(SDNode *N,
@@ -5398,6 +5417,7 @@
   case ISD::MUL:        return PerformMULCombine(N, DCI, Subtarget);
   case ISD::OR:         return PerformORCombine(N, DCI, Subtarget);
   case ISD::AND:        return PerformANDCombine(N, DCI);
+  case ARMISD::BFI:     return PerformBFICombine(N, DCI);
   case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
   case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
   case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);

Modified: llvm/trunk/test/CodeGen/ARM/bfi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfi.ll?rev=121746&r1=121745&r2=121746&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/bfi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/bfi.ll Mon Dec 13 21:22:07 2010
@@ -49,3 +49,16 @@
   %ins12 = or i32 %ins7, 3137
   ret i32 %ins12
 }
+
+; rdar://8458663
+define i32 @f5(i32 %a, i32 %b) nounwind {
+entry:
+; CHECK: f5:
+; CHECK-NOT: bfc
+; CHECK: bfi r0, r1, #20, #4
+  %0 = and i32 %a, -15728641
+  %1 = shl i32 %b, 20
+  %2 = and i32 %1, 15728640
+  %3 = or i32 %2, %0
+  ret i32 %3
+}



From isanbard at gmail.com  Mon Dec 13 21:36:38 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 03:36:38 -0000
Subject: [llvm-commits] [llvm] r121747 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMCodeEmitter.cpp
 lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrThumb.td
 lib/Target/ARM/ARMMCCodeEmitter.cpp
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.h
 lib/Target/ARM/Thumb1RegisterInfo.cpp
 lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/EDEmitter.cpp
Message-ID: <20101214033639.1C4662A6C12C@llvm.org>

Author: void
Date: Mon Dec 13 21:36:38 2010
New Revision: 121747

URL: http://llvm.org/viewvc/llvm-project?rev=121747&view=rev
Log:
The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 13 21:36:38 2010
@@ -1129,13 +1129,12 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::tSTR);
+      TmpInst.setOpcode(ARM::tSTRi);
       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
       // The offset immediate is #4. The operand value is scaled by 4 for the
       // tSTR instruction.
       TmpInst.addOperand(MCOperand::CreateImm(1));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
       TmpInst.addOperand(MCOperand::CreateReg(0));
@@ -1312,13 +1311,12 @@
     unsigned ScratchReg = MI->getOperand(1).getReg();
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::tLDR);
+      TmpInst.setOpcode(ARM::tLDRi);
       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
       // The offset immediate is #8. The operand value is scaled by 4 for the
-      // tSTR instruction.
+      // tLDR instruction.
       TmpInst.addOperand(MCOperand::CreateImm(2));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
       TmpInst.addOperand(MCOperand::CreateReg(0));
@@ -1336,11 +1334,10 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::tLDR);
+      TmpInst.setOpcode(ARM::tLDRi);
       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
       TmpInst.addOperand(MCOperand::CreateImm(1));
-      TmpInst.addOperand(MCOperand::CreateReg(0));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
       TmpInst.addOperand(MCOperand::CreateReg(0));
@@ -1348,10 +1345,9 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::tLDR);
+      TmpInst.setOpcode(ARM::tLDRr);
       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
-      TmpInst.addOperand(MCOperand::CreateImm(0));
       TmpInst.addOperand(MCOperand::CreateReg(0));
       // Predicate.
       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 21:36:38 2010
@@ -193,7 +193,7 @@
       const { return 0; }
     unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
-    unsigned getTAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
+    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
@@ -265,6 +265,8 @@
       const { return 0; }
     uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
     uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Dec 13 21:36:38 2010
@@ -130,18 +130,24 @@
   bool SelectAddrModePC(SDValue N, SDValue &Offset,
                         SDValue &Label);
 
+  // Thumb Addressing Modes:
   bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
-  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
-                              SDValue &Base, SDValue &OffImm,
-                              SDValue &Offset);
-  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
-                             SDValue &OffImm, SDValue &Offset);
-  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
-                             SDValue &OffImm, SDValue &Offset);
-  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
-                             SDValue &OffImm, SDValue &Offset);
+  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
+                             unsigned Scale);
+  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
+  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
+  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
+  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
+                                SDValue &OffImm);
+  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
+                                 SDValue &OffImm);
+  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
+                                 SDValue &OffImm);
+  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
+                                 SDValue &OffImm);
   bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
 
+  // Thumb 2 Addressing Modes:
   bool SelectT2ShifterOperandReg(SDValue N,
                                  SDValue &BaseReg, SDValue &Opc);
   bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
@@ -872,9 +878,16 @@
                                        MVT::i32);
     return true;
   }
+
   return false;
 }
 
+
+//===----------------------------------------------------------------------===//
+//                         Thumb Addressing Modes
+//===----------------------------------------------------------------------===//
+
+
 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
                                             SDValue &Base, SDValue &Offset){
   // FIXME dl should come from the parent load or store, not the address
@@ -893,13 +906,13 @@
 }
 
 bool
-ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
-                                        unsigned Scale, SDValue &Base,
-                                        SDValue &OffImm, SDValue &Offset) {
+ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
+                                       SDValue &Offset, unsigned Scale) {
   if (Scale == 4) {
     SDValue TmpBase, TmpOffImm;
     if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
       return false;  // We want to select tLDRspi / tSTRspi instead.
+
     if (N.getOpcode() == ARMISD::Wrapper &&
         N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
       return false;  // We want to select tLDRpci instead.
@@ -907,14 +920,13 @@
 
   if (N.getOpcode() != ISD::ADD) {
     if (N.getOpcode() == ARMISD::Wrapper &&
-        !(Subtarget->useMovt() &&
-          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
+        (!Subtarget->useMovt() ||
+         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
       Base = N.getOperand(0);
-    } else
+    else
       Base = N;
 
     Offset = CurDAG->getRegister(0, MVT::i32);
-    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
     return true;
   }
 
@@ -925,6 +937,68 @@
       (RHSR && RHSR->getReg() == ARM::SP)) {
     Base = N;
     Offset = CurDAG->getRegister(0, MVT::i32);
+    return true;
+  }
+
+  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    int RHSC = (int)RHS->getZExtValue();
+
+    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
+      RHSC /= Scale;
+
+      if (RHSC >= 0 && RHSC < 32)
+        return false;
+    }
+  }
+
+  Base = N.getOperand(0);
+  Offset = N.getOperand(1);
+  return true;
+}
+
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
+                                          SDValue &Base,
+                                          SDValue &Offset) {
+  return SelectThumbAddrModeRI(N, Base, Offset, 1);
+}
+
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
+                                          SDValue &Base,
+                                          SDValue &Offset) {
+  return SelectThumbAddrModeRI(N, Base, Offset, 2);
+}
+
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
+                                          SDValue &Base,
+                                          SDValue &Offset) {
+  return SelectThumbAddrModeRI(N, Base, Offset, 4);
+}
+
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
+                                          SDValue &Base, SDValue &OffImm) {
+  if (Scale == 4) {
+    SDValue TmpBase, TmpOffImm;
+    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
+      return false;  // We want to select tLDRspi / tSTRspi instead.
+
+    if (N.getOpcode() == ARMISD::Wrapper &&
+        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
+      return false;  // We want to select tLDRpci instead.
+  }
+
+  if (N.getOpcode() != ISD::ADD) {
+    if (N.getOpcode() == ARMISD::Wrapper &&
+        !(Subtarget->useMovt() &&
+          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
+      Base = N.getOperand(0);
+    } else {
+      Base = N;
+    }
+
     OffImm = CurDAG->getTargetConstant(0, MVT::i32);
     return true;
   }
@@ -932,11 +1006,12 @@
   // If the RHS is + imm5 * scale, fold into addr mode.
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();
-    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
+
+    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
       RHSC /= Scale;
+
       if (RHSC >= 0 && RHSC < 32) {
         Base = N.getOperand(0);
-        Offset = CurDAG->getRegister(0, MVT::i32);
         OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
         return true;
       }
@@ -944,27 +1019,26 @@
   }
 
   Base = N.getOperand(0);
-  Offset = N.getOperand(1);
   OffImm = CurDAG->getTargetConstant(0, MVT::i32);
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
-                                            SDValue &Base, SDValue &OffImm,
-                                            SDValue &Offset) {
-  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
-}
-
-bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
-                                            SDValue &Base, SDValue &OffImm,
-                                            SDValue &Offset) {
-  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
-}
-
-bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
-                                            SDValue &Base, SDValue &OffImm,
-                                            SDValue &Offset) {
-  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
+                                           SDValue &OffImm) {
+  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
+}
+
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
+                                           SDValue &OffImm) {
+  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
+}
+
+bool
+ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
+                                           SDValue &OffImm) {
+  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
 }
 
 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
@@ -1003,6 +1077,12 @@
   return false;
 }
 
+
+//===----------------------------------------------------------------------===//
+//                        Thumb 2 Addressing Modes
+//===----------------------------------------------------------------------===//
+
+
 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
                                                 SDValue &Opc) {
   if (DisableShifterOp)

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Dec 13 21:36:38 2010
@@ -94,8 +94,13 @@
   let EncoderMethod = "getThumbBLXTargetOpValue";
 }
 
-def MemModeThumbAsmOperand : AsmOperandClass {
-  let Name = "MemModeThumb";
+def MemModeRegThumbAsmOperand : AsmOperandClass {
+  let Name = "MemModeRegThumb";
+  let SuperClasses = [];
+}
+
+def MemModeImmThumbAsmOperand : AsmOperandClass {
+  let Name = "MemModeImmThumb";
   let SuperClasses = [];
 }
 
@@ -103,42 +108,64 @@
 //
 def t_addrmode_rr : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
-  let EncoderMethod = "getTAddrModeRegRegOpValue";
+  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
+  let PrintMethod = "printThumbAddrModeRROperand";
+  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
+}
+
+// t_addrmode_rrs := reg + reg
+//
+def t_addrmode_rrs1 : Operand<i32>,
+                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
+  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
   let PrintMethod = "printThumbAddrModeRROperand";
   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
+  let ParserMatchClass = MemModeRegThumbAsmOperand;
 }
 
-// t_addrmode_s4 := reg + reg
-//                  reg + imm5 * 4
+def t_addrmode_rrs2 : Operand<i32>,
+                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
+  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
+  let PrintMethod = "printThumbAddrModeRROperand";
+  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
+  let ParserMatchClass = MemModeRegThumbAsmOperand;
+}
+def t_addrmode_rrs4 : Operand<i32>,
+                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
+  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
+  let PrintMethod = "printThumbAddrModeRROperand";
+  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
+  let ParserMatchClass = MemModeRegThumbAsmOperand;
+}
+
+// t_addrmode_is4 := reg + imm5 * 4
 //
-def t_addrmode_s4 : Operand<i32>,
-                    ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
-  let EncoderMethod = "getAddrModeSOpValue";
-  let PrintMethod = "printThumbAddrModeS4Operand";
-  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
-  let ParserMatchClass = MemModeThumbAsmOperand;
+def t_addrmode_is4 : Operand<i32>,
+                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
+  let EncoderMethod = "getAddrModeISOpValue";
+  let PrintMethod = "printThumbAddrModeImm5S4Operand";
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
+  let ParserMatchClass = MemModeImmThumbAsmOperand;
 }
 
-// t_addrmode_s2 := reg + reg
-//                  reg + imm5 * 2
+// t_addrmode_is2 := reg + imm5 * 2
 //
-def t_addrmode_s2 : Operand<i32>,
-                    ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
-  let EncoderMethod = "getAddrModeSOpValue";
-  let PrintMethod = "printThumbAddrModeS2Operand";
-  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
-  let ParserMatchClass = MemModeThumbAsmOperand;
+def t_addrmode_is2 : Operand<i32>,
+                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
+  let EncoderMethod = "getAddrModeISOpValue";
+  let PrintMethod = "printThumbAddrModeImm5S2Operand";
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
+  let ParserMatchClass = MemModeImmThumbAsmOperand;
 }
 
-// t_addrmode_s1 := reg + reg
-//                  reg + imm5
+// t_addrmode_is1 := reg + imm5
 //
-def t_addrmode_s1 : Operand<i32>,
-                    ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
-  let EncoderMethod = "getAddrModeSOpValue";
-  let PrintMethod = "printThumbAddrModeS1Operand";
-  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
-  let ParserMatchClass = MemModeThumbAsmOperand;
+def t_addrmode_is1 : Operand<i32>,
+                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
+  let EncoderMethod = "getAddrModeISOpValue";
+  let PrintMethod = "printThumbAddrModeImm5S1Operand";
+  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
+  let ParserMatchClass = MemModeImmThumbAsmOperand;
 }
 
 // t_addrmode_sp := sp + imm8 * 4
@@ -148,14 +175,14 @@
   let EncoderMethod = "getAddrModeThumbSPOpValue";
   let PrintMethod = "printThumbAddrModeSPOperand";
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
-  let ParserMatchClass = MemModeThumbAsmOperand;
+  let ParserMatchClass = MemModeImmThumbAsmOperand;
 }
 
 // t_addrmode_pc := <label> => pc + imm8 * 4
 //
 def t_addrmode_pc : Operand<i32> {
   let EncoderMethod = "getAddrModePCOpValue";
-  let ParserMatchClass = MemModeThumbAsmOperand;
+  let ParserMatchClass = MemModeImmThumbAsmOperand;
 }
 
 //===----------------------------------------------------------------------===//
@@ -580,41 +607,41 @@
 //
 
 let canFoldAsLoad = 1, isReMaterializable = 1 in
-def tLDR :                      // A8.6.60
-  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
+def tLDRr :                      // A8.6.60
+  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
                  AddrModeT1_4, IIC_iLoad_r,
                  "ldr", "\t$Rt, $addr",
-                 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
+                 [(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
 
 def tLDRi :                     // A8.6.57
-  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
+  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
                     AddrModeT1_4, IIC_iLoad_r,
                     "ldr", "\t$Rt, $addr",
-                    []>;
+                    [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
 
-def tLDRB :                     // A8.6.64
-  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
+def tLDRBr :                    // A8.6.64
+  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
                  AddrModeT1_1, IIC_iLoad_bh_r,
                  "ldrb", "\t$Rt, $addr",
-                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
+                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
 
 def tLDRBi :                    // A8.6.61
-  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
+  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
                     AddrModeT1_1, IIC_iLoad_bh_r,
                     "ldrb", "\t$Rt, $addr",
-                    []>;
+                    [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
 
-def tLDRH :                     // A8.6.76
-  T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
+def tLDRHr :                    // A8.6.76
+  T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
                  AddrModeT1_2, IIC_iLoad_bh_r,
-                 "ldrh", "\t$dst, $addr",
-                 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
+                 "ldrh", "\t$Rt, $addr",
+                 [(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
 
 def tLDRHi :                    // A8.6.73
-  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
+  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
                     AddrModeT1_2, IIC_iLoad_bh_r,
                     "ldrh", "\t$Rt, $addr",
-                    []>;
+                    [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
 
 let AddedComplexity = 10 in
 def tLDRSB :                    // A8.6.80
@@ -676,45 +703,45 @@
   let Inst{7-0}  = addr;
 }
 
-def tSTR :                      // A8.6.194
-  T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
+def tSTRr :                     // A8.6.194
+  T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
                  AddrModeT1_4, IIC_iStore_r,
-                 "str", "\t$src, $addr",
-                 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
+                 "str", "\t$Rt, $addr",
+                 [(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
 
 def tSTRi :                     // A8.6.192
-  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
+  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
                     AddrModeT1_4, IIC_iStore_r,
                     "str", "\t$Rt, $addr",
-                    []>;
+                    [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
 
-def tSTRB :                     // A8.6.197
-  T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
+def tSTRBr :                    // A8.6.197
+  T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
                  AddrModeT1_1, IIC_iStore_bh_r,
-                 "strb", "\t$src, $addr",
-                 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
+                 "strb", "\t$Rt, $addr",
+                 [(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
 
 def tSTRBi :                    // A8.6.195
-  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
+  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
                     AddrModeT1_1, IIC_iStore_bh_r,
                     "strb", "\t$Rt, $addr",
-                    []>;
+                    [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
 
-def tSTRH :                     // A8.6.207
-  T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
+def tSTRHr :                    // A8.6.207
+  T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
                  AddrModeT1_2, IIC_iStore_bh_r,
-                 "strh", "\t$src, $addr",
-                 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
+                 "strh", "\t$Rt, $addr",
+                 [(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
 
 def tSTRHi :                    // A8.6.205
-  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
+  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
                     AddrModeT1_2, IIC_iStore_bh_r,
                     "strh", "\t$Rt, $addr",
-                    []>;
+                    [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
 
 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
-                   "str", "\t$Rt, $addr",
-                   [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
+                    "str", "\t$Rt, $addr",
+                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
               T1LdStSP<{0,?,?}> {
   bits<3> Rt;
   bits<8> addr;
@@ -1390,27 +1417,32 @@
       Requires<[IsThumb, HasV5T, IsDarwin]>;
 
 // zextload i1 -> zextload i8
-def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
-            (tLDRB t_addrmode_s1:$addr)>;
+def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
+            (tLDRBr t_addrmode_rrs1:$addr)>;
+def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
+            (tLDRBi t_addrmode_is1:$addr)>;
 
 // extload -> zextload
-def : T1Pat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
-def : T1Pat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
-def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
+def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
+def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
+def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
+def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
+def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
+def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
 
 // If it's impossible to use [r,r] address mode for sextload, select to
 // ldr{b|h} + sxt{b|h} instead.
-def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
-            (tSXTB (tLDRB t_addrmode_s1:$addr))>,
+def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
+            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
       Requires<[IsThumb, IsThumb1Only, HasV6]>;
-def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
-            (tSXTH (tLDRH t_addrmode_s2:$addr))>,
+def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
+            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
       Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
-def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
-            (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
-def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
-            (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
+def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
+            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
+def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr),
+            (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>;
 
 // Large immediate handling.
 

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 21:36:38 2010
@@ -144,9 +144,9 @@
   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
                                    SmallVectorImpl<MCFixup> &Fixups) const;
 
-  /// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
-  uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
-                                     SmallVectorImpl<MCFixup> &Fixups) const;
+  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
+  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
+                                         SmallVectorImpl<MCFixup> &Fixups)const;
 
   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
   /// operand.
@@ -207,9 +207,9 @@
   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
                                      SmallVectorImpl<MCFixup> &Fixups) const;
 
-  /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
-  uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
-                               SmallVectorImpl<MCFixup> &) const;
+  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
+  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
+                                SmallVectorImpl<MCFixup> &) const;
 
   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
@@ -559,12 +559,16 @@
                                   Fixups);
 }
 
-/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
+/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
+/// operand.
 uint32_t ARMMCCodeEmitter::
-getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
-                        SmallVectorImpl<MCFixup> &Fixups) const {
+getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &) const {
+  // [Rn, Rm]
+  //   {5-3} = Rm
+  //   {2-0} = Rn
   const MCOperand &MO1 = MI.getOperand(OpIdx);
-  const MCOperand &MO2 = MI.getOperand(OpIdx+1);
+  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
   unsigned Rn = getARMRegisterNumbering(MO1.getReg());
   unsigned Rm = getARMRegisterNumbering(MO2.getReg());
   return (Rm << 3) | Rn;
@@ -796,27 +800,17 @@
   return MO1.getImm() & 0xff;
 }
 
-/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
+/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
 uint32_t ARMMCCodeEmitter::
-getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
-                    SmallVectorImpl<MCFixup> &) const {
-  // [Rn, Rm]
-  //   {5-3} = Rm
-  //   {2-0} = Rn
-  //
+getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
+                     SmallVectorImpl<MCFixup> &) const {
   // [Rn, #imm]
   //   {7-3} = imm5
   //   {2-0} = Rn
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
-  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
   unsigned Rn = getARMRegisterNumbering(MO.getReg());
   unsigned Imm5 = MO1.getImm();
-
-  if (MO2.getReg() != 0)
-    // Is an immediate.
-    Imm5 = getARMRegisterNumbering(MO2.getReg());
-
   return ((Imm5 & 0x1f) << 3) | Rn;
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 13 21:36:38 2010
@@ -236,11 +236,16 @@
     int64_t Value = CE->getValue();
     return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
   }
-  bool isMemModeThumb() const {
+  bool isMemModeRegThumb() const {
+    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
+      return false;
+    return !Mem.Offset || !isa<MCConstantExpr>(Mem.Offset);
+  }
+  bool isMemModeImmThumb() const {
     if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
       return false;
 
-    if (!Mem.Offset) return true;
+    if (!Mem.Offset) return false;
 
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
     if (!CE) return false;
@@ -324,19 +329,18 @@
     }
   }
 
-  void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
-    assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
+  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
+  }
 
-    if (Mem.Offset) {
-      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
-      assert(CE && "Non-constant mode offset operand!");
-      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
-      Inst.addOperand(MCOperand::CreateReg(0));
-    } else {
-      Inst.addOperand(MCOperand::CreateImm(0));
-      Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
-    }
+  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
+    assert(CE && "Non-constant mode offset operand!");
+    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
   }
 
   virtual void dump(raw_ostream &OS) const;

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Dec 13 21:36:38 2010
@@ -482,17 +482,25 @@
 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
                                                  raw_ostream &O) {
   const MCOperand &MO1 = MI->getOperand(Op);
-  const MCOperand &MO2 = MI->getOperand(Op+1);
+  const MCOperand &MO2 = MI->getOperand(Op + 1);
+
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
+    printOperand(MI, Op, O);
+    return;
+  }
+
   O << "[" << getRegisterName(MO1.getReg());
-  O << ", " << getRegisterName(MO2.getReg()) << "]";
+  if (unsigned RegNum = MO2.getReg())
+    O << ", " << getRegisterName(RegNum);
+  O << "]";
 }
 
-void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
-                                                  raw_ostream &O,
-                                                  unsigned Scale) {
+void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
+                                                    unsigned Op,
+                                                    raw_ostream &O,
+                                                    unsigned Scale) {
   const MCOperand &MO1 = MI->getOperand(Op);
-  const MCOperand &MO2 = MI->getOperand(Op+1);
-  const MCOperand &MO3 = MI->getOperand(Op+2);
+  const MCOperand &MO2 = MI->getOperand(Op + 1);
 
   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op, O);
@@ -500,36 +508,32 @@
   }
 
   O << "[" << getRegisterName(MO1.getReg());
-  if (MO3.getReg())
-    O << ", " << getRegisterName(MO3.getReg());
-  else if (unsigned ImmOffs = MO2.getImm())
+  if (unsigned ImmOffs = MO2.getImm())
     O << ", #" << ImmOffs * Scale;
   O << "]";
 }
 
-void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
-                                                 raw_ostream &O) {
-  printThumbAddrModeRI5Operand(MI, Op, O, 1);
-}
-
-void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
-                                                 raw_ostream &O) {
-  printThumbAddrModeRI5Operand(MI, Op, O, 2);
-}
-
-void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
-                                                 raw_ostream &O) {
-  printThumbAddrModeRI5Operand(MI, Op, O, 4);
+void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
+                                                     unsigned Op,
+                                                     raw_ostream &O) {
+  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
+}
+
+void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
+                                                     unsigned Op,
+                                                     raw_ostream &O) {
+  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
+}
+
+void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
+                                                     unsigned Op,
+                                                     raw_ostream &O) {
+  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
 }
 
 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
                                                  raw_ostream &O) {
-  const MCOperand &MO1 = MI->getOperand(Op);
-  const MCOperand &MO2 = MI->getOperand(Op+1);
-  O << "[" << getRegisterName(MO1.getReg());
-  if (unsigned ImmOffs = MO2.getImm())
-    O << ", #" << ImmOffs*4;
-  O << "]";
+  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
 }
 
 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Dec 13 21:36:38 2010
@@ -59,14 +59,14 @@
   void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
                                    raw_ostream &O);
-  void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,
-                                    raw_ostream &O, unsigned Scale);
-  void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum,
-                                   raw_ostream &O);
-  void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum,
-                                   raw_ostream &O);
-  void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum,
-                                   raw_ostream &O);
+  void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
+                                      raw_ostream &O, unsigned Scale);
+  void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
+                                       raw_ostream &O);
+  void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
+                                       raw_ostream &O);
+  void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
+                                       raw_ostream &O);
   void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
                                    raw_ostream &O);
 

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Dec 13 21:36:38 2010
@@ -644,13 +644,11 @@
                                 *this, dl);
     }
 
-    MI.setDesc(TII.get(ARM::tLDR));
+    MI.setDesc(TII.get(ARM::tLDRr));
     MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
     if (UseRR)
       // Use [reg, reg] addrmode.
       MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
-    else  // tLDR has an extra register operand.
-      MI.addOperand(MachineOperand::CreateReg(0, false));
   } else if (Desc.mayStore()) {
       VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
       bool UseRR = false;
@@ -666,14 +664,13 @@
       } else
         emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
                                   *this, dl);
-      MI.setDesc(TII.get(ARM::tSTR));
+      MI.setDesc(TII.get(ARM::tSTRr));
       MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
       if (UseRR)  // Use [reg, reg] addrmode.
         MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
-      else // tSTR has an extra register operand.
-        MI.addOperand(MachineOperand::CreateReg(0, false));
-  } else
+  } else {
     assert(false && "Unexpected opcode!");
+  }
 
   // Add predicate back if it's needed.
   if (MI.getDesc().isPredicable()) {

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Mon Dec 13 21:36:38 2010
@@ -105,19 +105,19 @@
     // FIXME: Clean this up after splitting each Thumb load / store opcode
     // into multiple ones.
     { ARM::t2LDRi12,ARM::tLDRi,   ARM::tLDRspi,  5,   8,    1,   0,  0,0, 1 },
-    { ARM::t2LDRs,  ARM::tLDR,    0,             0,   0,    1,   0,  0,0, 1 },
+    { ARM::t2LDRs,  ARM::tLDRr,   0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2LDRBi12,ARM::tLDRBi, 0,             5,   0,    1,   0,  0,0, 1 },
-    { ARM::t2LDRBs, ARM::tLDRB,   0,             0,   0,    1,   0,  0,0, 1 },
+    { ARM::t2LDRBs, ARM::tLDRBr,  0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2LDRHi12,ARM::tLDRHi, 0,             5,   0,    1,   0,  0,0, 1 },
-    { ARM::t2LDRHs, ARM::tLDRH,   0,             0,   0,    1,   0,  0,0, 1 },
+    { ARM::t2LDRHs, ARM::tLDRHr,  0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2LDRSBs,ARM::tLDRSB,  0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2LDRSHs,ARM::tLDRSH,  0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2STRi12,ARM::tSTRi,   ARM::tSTRspi,  5,   8,    1,   0,  0,0, 1 },
-    { ARM::t2STRs,  ARM::tSTR,    0,             0,   0,    1,   0,  0,0, 1 },
+    { ARM::t2STRs,  ARM::tSTRr,   0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2STRBi12,ARM::tSTRBi, 0,             5,   0,    1,   0,  0,0, 1 },
-    { ARM::t2STRBs, ARM::tSTRB,   0,             0,   0,    1,   0,  0,0, 1 },
+    { ARM::t2STRBs, ARM::tSTRBr,  0,             0,   0,    1,   0,  0,0, 1 },
     { ARM::t2STRHi12,ARM::tSTRHi, 0,             5,   0,    1,   0,  0,0, 1 },
-    { ARM::t2STRHs, ARM::tSTRH,   0,             0,   0,    1,   0,  0,0, 1 },
+    { ARM::t2STRHs, ARM::tSTRHr,  0,             0,   0,    1,   0,  0,0, 1 },
 
     { ARM::t2LDMIA, ARM::tLDMIA,  0,             0,   0,    1,   1,  1,1, 1 },
     { ARM::t2LDMIA_RET,0,         ARM::tPOP_RET, 0,   0,    1,   1,  1,1, 1 },
@@ -273,7 +273,6 @@
   bool HasShift = false;
   bool HasOffReg = true;
   bool isLdStMul = false;
-  bool InsertImmOffset = true;
   unsigned Opc = Entry.NarrowOpc1;
   unsigned OpNum = 3; // First 'rest' of operands.
   uint8_t  ImmLimit = Entry.Imm1Limit;
@@ -282,39 +281,41 @@
   default:
     llvm_unreachable("Unexpected Thumb2 load / store opcode!");
   case ARM::t2LDRi12:
-  case ARM::t2STRi12: {
-    unsigned BaseReg = MI->getOperand(1).getReg();
-    if (BaseReg == ARM::SP) {
+  case ARM::t2STRi12:
+    if (MI->getOperand(1).getReg() == ARM::SP) {
       Opc = Entry.NarrowOpc2;
       ImmLimit = Entry.Imm2Limit;
       HasOffReg = false;
     }
+
     Scale = 4;
-    if (MI->getOperand(2).isImm())
+
+    if (MI->getOperand(2).isImm()) {
       HasImmOffset = true;
-    else {
+      HasOffReg = false;
+    } else {
       if (Entry.WideOpc == ARM::t2LDRi12) {
         Opc = ARM::tLDRpci;
         OpNum = 2;
       }
+
       HasImmOffset = false;
-      InsertImmOffset = false;
       HasBaseReg = false;
       HasOffReg = false;
     }
     break;
-  }
   case ARM::t2LDRBi12:
   case ARM::t2STRBi12:
-    if (MI->getOperand(2).isImm())
+    if (MI->getOperand(2).isImm()) {
       HasImmOffset = true;
-    else {
+      HasOffReg = false;
+    } else {
       if (Entry.WideOpc == ARM::t2LDRBi12) {
         Opc = ARM::tLDRpci;
         OpNum = 2;
       }
+
       HasImmOffset = false;
-      InsertImmOffset = false;
       HasBaseReg = false;
       HasOffReg = false;
     }
@@ -322,15 +323,16 @@
   case ARM::t2LDRHi12:
   case ARM::t2STRHi12:
     Scale = 2;
-    if (MI->getOperand(2).isImm())
+    if (MI->getOperand(2).isImm()) {
       HasImmOffset = true;
-    else {
+      HasOffReg = false;
+    } else {
       if (Entry.WideOpc == ARM::t2LDRHi12) {
         Opc = ARM::tLDRpci;
         OpNum = 2;
       }
+
       HasImmOffset = false;
-      InsertImmOffset = false;
       HasBaseReg = false;
       HasOffReg = false;
     }
@@ -351,6 +353,7 @@
     unsigned BaseReg = MI->getOperand(0).getReg();
     if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
       return false;
+
     // For the non-writeback version (this one), the base register must be
     // one of the registers being loaded.
     bool isOK = false;
@@ -360,6 +363,7 @@
         break;
       }
     }
+
     if (!isOK)
       return false;
 
@@ -381,6 +385,7 @@
   case ARM::t2STMIA_UPD:
   case ARM::t2STMDB_UPD: {
     OpNum = 0;
+
     unsigned BaseReg = MI->getOperand(1).getReg();
     if (BaseReg == ARM::SP &&
         (Entry.WideOpc == ARM::t2LDMIA_UPD ||
@@ -392,6 +397,7 @@
                 Entry.WideOpc != ARM::t2STMIA_UPD)) {
       return false;
     }
+
     isLdStMul = true;
     break;
   }
@@ -402,6 +408,7 @@
   if (HasShift) {
     OffsetReg  = MI->getOperand(2).getReg();
     OffsetKill = MI->getOperand(2).isKill();
+
     if (MI->getOperand(3).getImm())
       // Thumb1 addressing mode doesn't support shift.
       return false;
@@ -411,24 +418,24 @@
   if (HasImmOffset) {
     OffsetImm = MI->getOperand(2).getImm();
     unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
-    if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
+
+    if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
       // Make sure the immediate field fits.
       return false;
   }
 
   // Add the 16-bit load / store instruction.
-  // FIXME: Thumb1 addressing mode encode both immediate and register offset.
   DebugLoc dl = MI->getDebugLoc();
   MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
   if (!isLdStMul) {
     MIB.addOperand(MI->getOperand(0));
-    if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
-    if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
-      // tLDRSB and tLDRSH do not have an immediate offset field. On the other
-      // hand, it must have an offset register.
-      // FIXME: Remove this special case.
-      MIB.addImm(OffsetImm/Scale);
-    }
+
+    if (HasBaseReg)
+      MIB.addOperand(MI->getOperand(1));
+
+    if (HasImmOffset)
+      MIB.addImm(OffsetImm / Scale);
+
     assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
 
     if (HasOffReg)

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 21:36:38 2010
@@ -629,9 +629,12 @@
   MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
                                                                   // R, I
   MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
-  MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1");           // R, I, R
-  MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2");           // R, I, R
-  MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4");           // R, I, R
+  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
+  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
+  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
+  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
+  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
+  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
   MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
   MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
   MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
@@ -841,9 +844,8 @@
   operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
   operandTypes.addEntry("kOperandTypeARMTBAddrMode");
   operandTypes.addEntry("kOperandTypeThumbITMask");
-  operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
-  operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
-  operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
+  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
+  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
   operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
   operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
   operandTypes.addEntry("kOperandTypeThumbAddrModePC");



From geek4civic at gmail.com  Mon Dec 13 22:08:44 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 14 Dec 2010 13:08:44 +0900
Subject: [llvm-commits] Issue with Win64 local area stack offset
In-Reply-To: <AANLkTikOHXmTk=3TCz709WhUUxtOQ51oOOCiRy-XVCJU@mail.gmail.com>
References: <489333.28347.qm@web55604.mail.re4.yahoo.com>
	<832540.73670.qm@web55606.mail.re4.yahoo.com>
	<AANLkTikOHXmTk=3TCz709WhUUxtOQ51oOOCiRy-XVCJU@mail.gmail.com>
Message-ID: <AANLkTi=3Jbc5y5fDB04vnZK6bquFpZhejjdaKaKkTYwb@mail.gmail.com>

Anton,

2010/9/3 Anton Korobeynikov <anton at korobeynikov.info>:
>> Any comments about the revised patch? Ok for someone to commit?
> The patch is invalid. First of all, make sure it does not break "make check".
> Right now it does and one of the failed tests clearly indicates the
> problem - the shadow space is allocated in the wrong place and calls
> might clobber spills of the callee which will be really hard to find
> in real-world apps.

I don't understand what would be wrong with it.
I built r112883 and got two failures.

Failing Tests (2):
    LLVM :: CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
    LLVM :: CodeGen/X86/2009-06-03-Win64SpillXMM.ll

They might be as same as what you met.
http://lists.cs.uiuc.edu/pipermail/llvm-testresults/2010-September/028878.html

I would like to know if others else two went worse.

The results themselves did emit good sequences.

# 2009-06-03-Win64DisableRedZone.ll
a:
        subq    $8, %rsp
        movq    %rcx, (%rsp)
        fildll  (%rsp)
        addq    $8, %rsp
        ret

It is a *leaf* function and broke nothing.
Shadow area would not be needed for the function "a* to allocate.
It would be better as below if we could.
a:
        movq    %rcx, 8(%rsp)
        fildll  8(%rsp)
        ret

# 2009-06-03-Win64SpillXMM.ll
a:
        subq    $40, %rsp
        movaps  %xmm8, (%rsp)           # 16-byte Spill
        movaps  %xmm7, 16(%rsp)         # 16-byte Spill
        #APP
        #NO_APP
        movaps  16(%rsp), %xmm7         # 16-byte Reload
        movaps  (%rsp), %xmm8           # 16-byte Reload
        addq    $40, %rsp
        ret

It would be reasonable and broke nothing, too.
"asm" might not be assumed to use shadow area.


Thank you, ...Takumi

From geek4civic at gmail.com  Mon Dec 13 22:09:42 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 14 Dec 2010 13:09:42 +0900
Subject: [llvm-commits] Issue with Win64 local area stack offset
In-Reply-To: <921691.29161.qm@web55608.mail.re4.yahoo.com>
References: <489333.28347.qm@web55604.mail.re4.yahoo.com>
	<832540.73670.qm@web55606.mail.re4.yahoo.com>
	<AANLkTikOHXmTk=3TCz709WhUUxtOQ51oOOCiRy-XVCJU@mail.gmail.com>
	<921691.29161.qm@web55608.mail.re4.yahoo.com>
Message-ID: <AANLkTinPqFeJKmzCR1Kg+f3WiBinptxLjmqiZ2A-20Kk@mail.gmail.com>

Jan,

I am sorry, I missed your patch and I have proposed yet another similar patch.

IMHO, r112875 was incomplete. Although it was better for two tests, I
met wrong outputs with recent tests, provided by Cameron Esfahani.

# win64_params.ll
f6:
        movl    80(%rsp), %eax
        addl    72(%rsp), %eax
        ret

The offsets +72 and +80 do not point %p5 and %p6!

"win64_vararg.ll" had been improved after that.


...Takumi

From sabre at nondot.org  Mon Dec 13 23:57:30 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 05:57:30 -0000
Subject: [llvm-commits] [llvm] r121749 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101214055730.566592A6C12C@llvm.org>

Author: lattner
Date: Mon Dec 13 23:57:30 2010
New Revision: 121749

URL: http://llvm.org/viewvc/llvm-project?rev=121749&view=rev
Log:
reapply my recent change that disables a piece of the switch formation
work, but fixes 400.perlbmk.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121749&r1=121748&r2=121749&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Dec 13 23:57:30 2010
@@ -1515,7 +1515,7 @@
       AddPredecessorToBlock(FalseDest, PredBlock, BB);
       PBI->setSuccessor(1, FalseDest);
     }
-    return SimplifyCFG(PBI->getParent()) | true;
+    return true;
   }
   return false;
 }
@@ -1905,17 +1905,25 @@
   
   BasicBlock *BB = BI->getParent();
   
+  DEBUG(dbgs() << "CONVERTING 'icmp' CHAIN with " << Values.size()
+               << " cases into SWITCH.  BB is:\n" << *BB);
+  
   // If there are any extra values that couldn't be folded into the switch
   // then we evaluate them with an explicit branch first.  Split the block
   // right before the condbr to handle it.
   if (ExtraCase) {
-    return false;
+    DEBUG(dbgs() << "  ** 'icmp' chain unhandled condition: " << *ExtraCase
+                 << '\n');
     
     BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
     // Remove the uncond branch added to the old block.
     TerminatorInst *OldTI = BB->getTerminator();
     
-    BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
+    if (TrueWhenEqual)
+      BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI);
+    else
+      BranchInst::Create(NewBB, EdgeBB, ExtraCase, OldTI);
+      
     OldTI->eraseFromParent();
     
     // If there are PHI nodes in EdgeBB, then we need to add a new entry to them
@@ -1955,6 +1963,7 @@
   
   // Erase the old branch instruction.
   EraseTerminatorInstAndDCECond(BI);
+  
   return true;
 }
 
@@ -2410,8 +2419,7 @@
     if (BI->isUnconditional()) {
       if (SimplifyUncondBranch(BI)) return true;
     } else {
-      if (SimplifyCondBranch(BI))
-        return true;
+      if (SimplifyCondBranch(BI)) return true;
     }
   } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
     if (SimplifyReturn(RI)) return true;

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121749&r1=121748&r2=121749&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Mon Dec 13 23:57:30 2010
@@ -1,5 +1,4 @@
 ; RUN: opt < %s -simplifycfg -S | FileCheck %s
-; XFAIL: *
 
 declare void @foo1()
 
@@ -257,7 +256,7 @@
 ; HECK:   %cmp = icmp ult i8 %c, 33
 ; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
-; HECK: switch.early.test:
+; CHECK: switch.early.test:
 ; HECK:   switch i8 %c, label %lor.rhs [
 ; HECK:     i8 46, label %lor.end
 ; HECK:     i8 44, label %lor.end



From sabre at nondot.org  Tue Dec 14 00:09:07 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 06:09:07 -0000
Subject: [llvm-commits] [llvm] r121750 -
	/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101214060907.DAEC22A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 00:09:07 2010
New Revision: 121750

URL: http://llvm.org/viewvc/llvm-project?rev=121750&view=rev
Log:
fix yet anohter broken line

Modified:
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121750&r1=121749&r2=121750&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Tue Dec 14 00:09:07 2010
@@ -256,7 +256,7 @@
 ; HECK:   %cmp = icmp ult i8 %c, 33
 ; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
-; CHECK: switch.early.test:
+; HECK: switch.early.test:
 ; HECK:   switch i8 %c, label %lor.rhs [
 ; HECK:     i8 46, label %lor.end
 ; HECK:     i8 44, label %lor.end
@@ -351,4 +351,4 @@
   ret void
 ; CHECK: @test12
 
-}
\ No newline at end of file
+}



From sabre at nondot.org  Tue Dec 14 00:17:25 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 06:17:25 -0000
Subject: [llvm-commits] [llvm] r121751 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214061725.E4FA92A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 00:17:25 2010
New Revision: 121751

URL: http://llvm.org/viewvc/llvm-project?rev=121751&view=rev
Log:
improve DEBUG's a bit, switch to eraseFromParent() to simplify
code a bit, switch from constant folding to instsimplify.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121751&r1=121750&r2=121751&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 00:17:25 2010
@@ -19,10 +19,7 @@
 #include "llvm/Type.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/GlobalVariable.h"
-#include "llvm/Support/CFG.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Analysis/ConstantFolding.h"
+#include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
 #include "llvm/ADT/DenseMap.h"
@@ -30,6 +27,9 @@
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/CFG.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <set>
 #include <map>
@@ -796,7 +796,7 @@
     if (!I2->use_empty())
       I2->replaceAllUsesWith(I1);
     I1->intersectOptionalDataWith(I2);
-    BB2->getInstList().erase(I2);
+    I2->eraseFromParent();
 
     I1 = BB1_Itr++;
     while (isa<DbgInfoIntrinsic>(I1))
@@ -1050,7 +1050,7 @@
 /// that is defined in the same block as the branch and if any PHI entries are
 /// constants, thread edges corresponding to that entry to be branches to their
 /// ultimate destination.
-static bool FoldCondBranchOnPHI(BranchInst *BI) {
+static bool FoldCondBranchOnPHI(BranchInst *BI, const TargetData *TD) {
   BasicBlock *BB = BI->getParent();
   PHINode *PN = dyn_cast<PHINode>(BI->getCondition());
   // NOTE: we currently cannot transform this case if the PHI node is used
@@ -1118,9 +1118,9 @@
       }
       
       // Check for trivial simplification.
-      if (Constant *C = ConstantFoldInstruction(N)) {
-        TranslateMap[BBI] = C;
-        delete N;   // Constant folded away, don't need actual inst
+      if (Value *V = SimplifyInstruction(N, TD)) {
+        TranslateMap[BBI] = V;
+        delete N;   // Instruction folded away, don't need actual inst
       } else {
         // Insert the new instruction into its new home.
         EdgeBB->getInstList().insert(InsertPt, N);
@@ -1139,7 +1139,7 @@
       }
     
     // Recurse, simplifying any other constants.
-    return FoldCondBranchOnPHI(BI) | true;
+    return FoldCondBranchOnPHI(BI, TD) | true;
   }
 
   return false;
@@ -1251,7 +1251,7 @@
     PN->replaceAllUsesWith(NV);
     NV->takeName(PN);
     
-    BB->getInstList().erase(PN);
+    PN->eraseFromParent();
   }
   return true;
 }
@@ -1779,7 +1779,8 @@
 /// 
 /// We prefer to split the edge to 'end' so that there is a true/false entry to
 /// the PHI, merging the third icmp into the switch.
-static bool TryToSimplifyUncondBranchWithICmpInIt(ICmpInst *ICI) {
+static bool TryToSimplifyUncondBranchWithICmpInIt(ICmpInst *ICI,
+                                                  const TargetData *TD) {
   BasicBlock *BB = ICI->getParent();
   // If the block has any PHIs in it or the icmp has multiple uses, it is too
   // complex.
@@ -1806,8 +1807,8 @@
     assert(VVal && "Should have a unique destination value");
     ICI->setOperand(0, VVal);
     
-    if (Constant *C = ConstantFoldInstruction(ICI)) {
-      ICI->replaceAllUsesWith(C);
+    if (Value *V = SimplifyInstruction(ICI, TD)) {
+      ICI->replaceAllUsesWith(V);
       ICI->eraseFromParent();
     }
     // BB is now empty, so it is likely to simplify away.
@@ -1905,16 +1906,13 @@
   
   BasicBlock *BB = BI->getParent();
   
-  DEBUG(dbgs() << "CONVERTING 'icmp' CHAIN with " << Values.size()
+  DEBUG(dbgs() << "Converting 'icmp' chain with " << Values.size()
                << " cases into SWITCH.  BB is:\n" << *BB);
   
   // If there are any extra values that couldn't be folded into the switch
   // then we evaluate them with an explicit branch first.  Split the block
   // right before the condbr to handle it.
   if (ExtraCase) {
-    DEBUG(dbgs() << "  ** 'icmp' chain unhandled condition: " << *ExtraCase
-                 << '\n');
-    
     BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test");
     // Remove the uncond branch added to the old block.
     TerminatorInst *OldTI = BB->getTerminator();
@@ -1931,7 +1929,10 @@
     for (BasicBlock::iterator I = EdgeBB->begin(); isa<PHINode>(I); ++I) {
       PHINode *PN = cast<PHINode>(I);
       PN->addIncoming(PN->getIncomingValueForBlock(NewBB), BB);
-    }    
+    }
+    
+    DEBUG(dbgs() << "  ** 'icmp' chain unhandled condition: " << *ExtraCase
+          << "\nEXTRABB = " << *BB);
     BB = NewBB;
   }
   
@@ -1964,6 +1965,7 @@
   // Erase the old branch instruction.
   EraseTerminatorInstAndDCECond(BI);
   
+  DEBUG(dbgs() << "  ** 'icmp' chain result is:\n" << *BB << '\n');
   return true;
 }
 
@@ -2007,7 +2009,7 @@
       // Update any PHI nodes in the returning block to realize that we no
       // longer branch to them.
       BB->removePredecessor(Pred);
-      Pred->getInstList().erase(UncondBranch);
+      UncondBranch->eraseFromParent();
     }
     
     // If we eliminated all predecessors of the block, delete the block now.
@@ -2101,7 +2103,7 @@
         break;
     
     // Delete this instruction
-    BB->getInstList().erase(BBI);
+    BBI->eraseFromParent();
     Changed = true;
   }
   
@@ -2286,7 +2288,7 @@
     if (ICI->isEquality() && isa<ConstantInt>(ICI->getOperand(1))) {
       for (++I; isa<DbgInfoIntrinsic>(I); ++I)
         ;
-      if (I->isTerminator() && TryToSimplifyUncondBranchWithICmpInIt(ICI))
+      if (I->isTerminator() && TryToSimplifyUncondBranchWithICmpInIt(ICI, TD))
         return true;
     }
   
@@ -2360,7 +2362,7 @@
   // through this block if any PHI node entries are constants.
   if (PHINode *PN = dyn_cast<PHINode>(BI->getCondition()))
     if (PN->getParent() == BI->getParent())
-      if (FoldCondBranchOnPHI(BI))
+      if (FoldCondBranchOnPHI(BI, TD))
         return SimplifyCFG(BB) | true;
   
   // If this basic block is ONLY a setcc and a branch, and if a predecessor
@@ -2381,14 +2383,14 @@
 
 bool SimplifyCFGOpt::run(BasicBlock *BB) {
   bool Changed = false;
-  Function *Fn = BB->getParent();
 
-  assert(BB && Fn && "Block not embedded in function!");
+  assert(BB && BB->getParent() && "Block not embedded in function!");
   assert(BB->getTerminator() && "Degenerate basic block encountered!");
 
   // Remove basic blocks that have no predecessors (except the entry block)...
   // or that just have themself as a predecessor.  These are unreachable.
-  if ((pred_begin(BB) == pred_end(BB) && BB != &Fn->getEntryBlock()) ||
+  if ((pred_begin(BB) == pred_end(BB) &&
+       BB != &BB->getParent()->getEntryBlock()) ||
       BB->getSinglePredecessor() == BB) {
     DEBUG(dbgs() << "Removing BB: \n" << *BB);
     DeleteDeadBlock(BB);



From evan.cheng at apple.com  Tue Dec 14 00:53:49 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 13 Dec 2010 22:53:49 -0800
Subject: [llvm-commits] [llvm] r121747 - in /llvm/trunk:
	lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMCodeEmitter.cpp
	lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrThumb.td
	lib/Target/ARM/ARMMCCodeEmitter.cpp
	lib/Target/ARM/AsmParser/ARMAsmParser.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.h
	lib/Target/ARM/Thumb1RegisterInfo.cpp
	lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/EDEmitter.cpp
In-Reply-To: <20101214033639.1C4662A6C12C@llvm.org>
References: <20101214033639.1C4662A6C12C@llvm.org>
Message-ID: <D060E5D8-3663-43A3-9EDF-4689B028A929@apple.com>

Thanks. It would be nice if we could completely split out loads / stores for ARM as well. Jim started on it but he ran out of time.

Evan

On Dec 13, 2010, at 7:36 PM, Bill Wendling wrote:

> Author: void
> Date: Mon Dec 13 21:36:38 2010
> New Revision: 121747
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121747&view=rev
> Log:
> The tLDR et al instructions were emitting either a reg/reg or reg/imm
> instruction based on the t_addrmode_s# mode and what it returned. There is some
> obvious badness to this. In particular, it's hard to do MC-encoding when the
> instruction may change out from underneath you after the t_addrmode_s# variable
> is finally resolved.
> 
> The solution is to revert a long-ago change that merged the reg/reg and reg/imm
> versions. There is the addition of several new addressing modes. They no longer
> have extraneous operands associated with them. I.e., if it's reg/reg we don't
> have to have a dummy zero immediate tacked on to the SDNode.
> 
> There are some obvious cleanups here, which will happen shortly.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>    llvm/trunk/utils/TableGen/EDEmitter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 13 21:36:38 2010
> @@ -1129,13 +1129,12 @@
>     }
>     {
>       MCInst TmpInst;
> -      TmpInst.setOpcode(ARM::tSTR);
> +      TmpInst.setOpcode(ARM::tSTRi);
>       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
>       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>       // The offset immediate is #4. The operand value is scaled by 4 for the
>       // tSTR instruction.
>       TmpInst.addOperand(MCOperand::CreateImm(1));
> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>       // Predicate.
>       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>       TmpInst.addOperand(MCOperand::CreateReg(0));
> @@ -1312,13 +1311,12 @@
>     unsigned ScratchReg = MI->getOperand(1).getReg();
>     {
>       MCInst TmpInst;
> -      TmpInst.setOpcode(ARM::tLDR);
> +      TmpInst.setOpcode(ARM::tLDRi);
>       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>       // The offset immediate is #8. The operand value is scaled by 4 for the
> -      // tSTR instruction.
> +      // tLDR instruction.
>       TmpInst.addOperand(MCOperand::CreateImm(2));
> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>       // Predicate.
>       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>       TmpInst.addOperand(MCOperand::CreateReg(0));
> @@ -1336,11 +1334,10 @@
>     }
>     {
>       MCInst TmpInst;
> -      TmpInst.setOpcode(ARM::tLDR);
> +      TmpInst.setOpcode(ARM::tLDRi);
>       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>       TmpInst.addOperand(MCOperand::CreateImm(1));
> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>       // Predicate.
>       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>       TmpInst.addOperand(MCOperand::CreateReg(0));
> @@ -1348,10 +1345,9 @@
>     }
>     {
>       MCInst TmpInst;
> -      TmpInst.setOpcode(ARM::tLDR);
> +      TmpInst.setOpcode(ARM::tLDRr);
>       TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
>       TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
> -      TmpInst.addOperand(MCOperand::CreateImm(0));
>       TmpInst.addOperand(MCOperand::CreateReg(0));
>       // Predicate.
>       TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 21:36:38 2010
> @@ -193,7 +193,7 @@
>       const { return 0; }
>     unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
> -    unsigned getTAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
> +    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
>     unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
> @@ -265,6 +265,8 @@
>       const { return 0; }
>     uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
> +    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
> +      const { return 0; }
>     uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
>       const { return 0; }
>     uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Dec 13 21:36:38 2010
> @@ -130,18 +130,24 @@
>   bool SelectAddrModePC(SDValue N, SDValue &Offset,
>                         SDValue &Label);
> 
> +  // Thumb Addressing Modes:
>   bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
> -  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
> -                              SDValue &Base, SDValue &OffImm,
> -                              SDValue &Offset);
> -  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
> -                             SDValue &OffImm, SDValue &Offset);
> -  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
> -                             SDValue &OffImm, SDValue &Offset);
> -  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
> -                             SDValue &OffImm, SDValue &Offset);
> +  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
> +                             unsigned Scale);
> +  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
> +  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
> +  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
> +  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
> +                                SDValue &OffImm);
> +  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
> +                                 SDValue &OffImm);
> +  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
> +                                 SDValue &OffImm);
> +  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
> +                                 SDValue &OffImm);
>   bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
> 
> +  // Thumb 2 Addressing Modes:
>   bool SelectT2ShifterOperandReg(SDValue N,
>                                  SDValue &BaseReg, SDValue &Opc);
>   bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
> @@ -872,9 +878,16 @@
>                                        MVT::i32);
>     return true;
>   }
> +
>   return false;
> }
> 
> +
> +//===----------------------------------------------------------------------===//
> +//                         Thumb Addressing Modes
> +//===----------------------------------------------------------------------===//
> +
> +
> bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
>                                             SDValue &Base, SDValue &Offset){
>   // FIXME dl should come from the parent load or store, not the address
> @@ -893,13 +906,13 @@
> }
> 
> bool
> -ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
> -                                        unsigned Scale, SDValue &Base,
> -                                        SDValue &OffImm, SDValue &Offset) {
> +ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
> +                                       SDValue &Offset, unsigned Scale) {
>   if (Scale == 4) {
>     SDValue TmpBase, TmpOffImm;
>     if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>       return false;  // We want to select tLDRspi / tSTRspi instead.
> +
>     if (N.getOpcode() == ARMISD::Wrapper &&
>         N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>       return false;  // We want to select tLDRpci instead.
> @@ -907,14 +920,13 @@
> 
>   if (N.getOpcode() != ISD::ADD) {
>     if (N.getOpcode() == ARMISD::Wrapper &&
> -        !(Subtarget->useMovt() &&
> -          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
> +        (!Subtarget->useMovt() ||
> +         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
>       Base = N.getOperand(0);
> -    } else
> +    else
>       Base = N;
> 
>     Offset = CurDAG->getRegister(0, MVT::i32);
> -    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>     return true;
>   }
> 
> @@ -925,6 +937,68 @@
>       (RHSR && RHSR->getReg() == ARM::SP)) {
>     Base = N;
>     Offset = CurDAG->getRegister(0, MVT::i32);
> +    return true;
> +  }
> +
> +  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
> +    int RHSC = (int)RHS->getZExtValue();
> +
> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
> +      RHSC /= Scale;
> +
> +      if (RHSC >= 0 && RHSC < 32)
> +        return false;
> +    }
> +  }
> +
> +  Base = N.getOperand(0);
> +  Offset = N.getOperand(1);
> +  return true;
> +}
> +
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
> +                                          SDValue &Base,
> +                                          SDValue &Offset) {
> +  return SelectThumbAddrModeRI(N, Base, Offset, 1);
> +}
> +
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
> +                                          SDValue &Base,
> +                                          SDValue &Offset) {
> +  return SelectThumbAddrModeRI(N, Base, Offset, 2);
> +}
> +
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
> +                                          SDValue &Base,
> +                                          SDValue &Offset) {
> +  return SelectThumbAddrModeRI(N, Base, Offset, 4);
> +}
> +
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
> +                                          SDValue &Base, SDValue &OffImm) {
> +  if (Scale == 4) {
> +    SDValue TmpBase, TmpOffImm;
> +    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
> +      return false;  // We want to select tLDRspi / tSTRspi instead.
> +
> +    if (N.getOpcode() == ARMISD::Wrapper &&
> +        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
> +      return false;  // We want to select tLDRpci instead.
> +  }
> +
> +  if (N.getOpcode() != ISD::ADD) {
> +    if (N.getOpcode() == ARMISD::Wrapper &&
> +        !(Subtarget->useMovt() &&
> +          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
> +      Base = N.getOperand(0);
> +    } else {
> +      Base = N;
> +    }
> +
>     OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>     return true;
>   }
> @@ -932,11 +1006,12 @@
>   // If the RHS is + imm5 * scale, fold into addr mode.
>   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>     int RHSC = (int)RHS->getZExtValue();
> -    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
> +
> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>       RHSC /= Scale;
> +
>       if (RHSC >= 0 && RHSC < 32) {
>         Base = N.getOperand(0);
> -        Offset = CurDAG->getRegister(0, MVT::i32);
>         OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>         return true;
>       }
> @@ -944,27 +1019,26 @@
>   }
> 
>   Base = N.getOperand(0);
> -  Offset = N.getOperand(1);
>   OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>   return true;
> }
> 
> -bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
> -                                            SDValue &Base, SDValue &OffImm,
> -                                            SDValue &Offset) {
> -  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
> -}
> -
> -bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
> -                                            SDValue &Base, SDValue &OffImm,
> -                                            SDValue &Offset) {
> -  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
> -}
> -
> -bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
> -                                            SDValue &Base, SDValue &OffImm,
> -                                            SDValue &Offset) {
> -  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
> +                                           SDValue &OffImm) {
> +  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
> +}
> +
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
> +                                           SDValue &OffImm) {
> +  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
> +}
> +
> +bool
> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
> +                                           SDValue &OffImm) {
> +  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
> }
> 
> bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
> @@ -1003,6 +1077,12 @@
>   return false;
> }
> 
> +
> +//===----------------------------------------------------------------------===//
> +//                        Thumb 2 Addressing Modes
> +//===----------------------------------------------------------------------===//
> +
> +
> bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
>                                                 SDValue &Opc) {
>   if (DisableShifterOp)
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Dec 13 21:36:38 2010
> @@ -94,8 +94,13 @@
>   let EncoderMethod = "getThumbBLXTargetOpValue";
> }
> 
> -def MemModeThumbAsmOperand : AsmOperandClass {
> -  let Name = "MemModeThumb";
> +def MemModeRegThumbAsmOperand : AsmOperandClass {
> +  let Name = "MemModeRegThumb";
> +  let SuperClasses = [];
> +}
> +
> +def MemModeImmThumbAsmOperand : AsmOperandClass {
> +  let Name = "MemModeImmThumb";
>   let SuperClasses = [];
> }
> 
> @@ -103,42 +108,64 @@
> //
> def t_addrmode_rr : Operand<i32>,
>                     ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
> -  let EncoderMethod = "getTAddrModeRegRegOpValue";
> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
> +  let PrintMethod = "printThumbAddrModeRROperand";
> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> +}
> +
> +// t_addrmode_rrs := reg + reg
> +//
> +def t_addrmode_rrs1 : Operand<i32>,
> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>   let PrintMethod = "printThumbAddrModeRROperand";
>   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
> }
> 
> -// t_addrmode_s4 := reg + reg
> -//                  reg + imm5 * 4
> +def t_addrmode_rrs2 : Operand<i32>,
> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
> +  let PrintMethod = "printThumbAddrModeRROperand";
> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
> +}
> +def t_addrmode_rrs4 : Operand<i32>,
> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
> +  let PrintMethod = "printThumbAddrModeRROperand";
> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
> +}
> +
> +// t_addrmode_is4 := reg + imm5 * 4
> //
> -def t_addrmode_s4 : Operand<i32>,
> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
> -  let EncoderMethod = "getAddrModeSOpValue";
> -  let PrintMethod = "printThumbAddrModeS4Operand";
> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
> -  let ParserMatchClass = MemModeThumbAsmOperand;
> +def t_addrmode_is4 : Operand<i32>,
> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
> +  let EncoderMethod = "getAddrModeISOpValue";
> +  let PrintMethod = "printThumbAddrModeImm5S4Operand";
> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
> }
> 
> -// t_addrmode_s2 := reg + reg
> -//                  reg + imm5 * 2
> +// t_addrmode_is2 := reg + imm5 * 2
> //
> -def t_addrmode_s2 : Operand<i32>,
> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
> -  let EncoderMethod = "getAddrModeSOpValue";
> -  let PrintMethod = "printThumbAddrModeS2Operand";
> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
> -  let ParserMatchClass = MemModeThumbAsmOperand;
> +def t_addrmode_is2 : Operand<i32>,
> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
> +  let EncoderMethod = "getAddrModeISOpValue";
> +  let PrintMethod = "printThumbAddrModeImm5S2Operand";
> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
> }
> 
> -// t_addrmode_s1 := reg + reg
> -//                  reg + imm5
> +// t_addrmode_is1 := reg + imm5
> //
> -def t_addrmode_s1 : Operand<i32>,
> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
> -  let EncoderMethod = "getAddrModeSOpValue";
> -  let PrintMethod = "printThumbAddrModeS1Operand";
> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
> -  let ParserMatchClass = MemModeThumbAsmOperand;
> +def t_addrmode_is1 : Operand<i32>,
> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
> +  let EncoderMethod = "getAddrModeISOpValue";
> +  let PrintMethod = "printThumbAddrModeImm5S1Operand";
> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
> }
> 
> // t_addrmode_sp := sp + imm8 * 4
> @@ -148,14 +175,14 @@
>   let EncoderMethod = "getAddrModeThumbSPOpValue";
>   let PrintMethod = "printThumbAddrModeSPOperand";
>   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
> -  let ParserMatchClass = MemModeThumbAsmOperand;
> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
> }
> 
> // t_addrmode_pc := <label> => pc + imm8 * 4
> //
> def t_addrmode_pc : Operand<i32> {
>   let EncoderMethod = "getAddrModePCOpValue";
> -  let ParserMatchClass = MemModeThumbAsmOperand;
> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
> }
> 
> //===----------------------------------------------------------------------===//
> @@ -580,41 +607,41 @@
> //
> 
> let canFoldAsLoad = 1, isReMaterializable = 1 in
> -def tLDR :                      // A8.6.60
> -  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
> +def tLDRr :                      // A8.6.60
> +  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
>                  AddrModeT1_4, IIC_iLoad_r,
>                  "ldr", "\t$Rt, $addr",
> -                 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
> +                 [(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
> 
> def tLDRi :                     // A8.6.57
> -  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
> +  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
>                     AddrModeT1_4, IIC_iLoad_r,
>                     "ldr", "\t$Rt, $addr",
> -                    []>;
> +                    [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
> 
> -def tLDRB :                     // A8.6.64
> -  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
> +def tLDRBr :                    // A8.6.64
> +  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
>                  AddrModeT1_1, IIC_iLoad_bh_r,
>                  "ldrb", "\t$Rt, $addr",
> -                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
> +                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
> 
> def tLDRBi :                    // A8.6.61
> -  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
> +  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
>                     AddrModeT1_1, IIC_iLoad_bh_r,
>                     "ldrb", "\t$Rt, $addr",
> -                    []>;
> +                    [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
> 
> -def tLDRH :                     // A8.6.76
> -  T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
> +def tLDRHr :                    // A8.6.76
> +  T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
>                  AddrModeT1_2, IIC_iLoad_bh_r,
> -                 "ldrh", "\t$dst, $addr",
> -                 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
> +                 "ldrh", "\t$Rt, $addr",
> +                 [(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
> 
> def tLDRHi :                    // A8.6.73
> -  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
> +  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
>                     AddrModeT1_2, IIC_iLoad_bh_r,
>                     "ldrh", "\t$Rt, $addr",
> -                    []>;
> +                    [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
> 
> let AddedComplexity = 10 in
> def tLDRSB :                    // A8.6.80
> @@ -676,45 +703,45 @@
>   let Inst{7-0}  = addr;
> }
> 
> -def tSTR :                      // A8.6.194
> -  T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
> +def tSTRr :                     // A8.6.194
> +  T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
>                  AddrModeT1_4, IIC_iStore_r,
> -                 "str", "\t$src, $addr",
> -                 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
> +                 "str", "\t$Rt, $addr",
> +                 [(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
> 
> def tSTRi :                     // A8.6.192
> -  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
> +  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
>                     AddrModeT1_4, IIC_iStore_r,
>                     "str", "\t$Rt, $addr",
> -                    []>;
> +                    [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
> 
> -def tSTRB :                     // A8.6.197
> -  T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
> +def tSTRBr :                    // A8.6.197
> +  T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
>                  AddrModeT1_1, IIC_iStore_bh_r,
> -                 "strb", "\t$src, $addr",
> -                 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
> +                 "strb", "\t$Rt, $addr",
> +                 [(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
> 
> def tSTRBi :                    // A8.6.195
> -  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
> +  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
>                     AddrModeT1_1, IIC_iStore_bh_r,
>                     "strb", "\t$Rt, $addr",
> -                    []>;
> +                    [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
> 
> -def tSTRH :                     // A8.6.207
> -  T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
> +def tSTRHr :                    // A8.6.207
> +  T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
>                  AddrModeT1_2, IIC_iStore_bh_r,
> -                 "strh", "\t$src, $addr",
> -                 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
> +                 "strh", "\t$Rt, $addr",
> +                 [(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
> 
> def tSTRHi :                    // A8.6.205
> -  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
> +  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
>                     AddrModeT1_2, IIC_iStore_bh_r,
>                     "strh", "\t$Rt, $addr",
> -                    []>;
> +                    [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
> 
> def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
> -                   "str", "\t$Rt, $addr",
> -                   [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
> +                    "str", "\t$Rt, $addr",
> +                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>               T1LdStSP<{0,?,?}> {
>   bits<3> Rt;
>   bits<8> addr;
> @@ -1390,27 +1417,32 @@
>       Requires<[IsThumb, HasV5T, IsDarwin]>;
> 
> // zextload i1 -> zextload i8
> -def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
> -            (tLDRB t_addrmode_s1:$addr)>;
> +def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
> +            (tLDRBr t_addrmode_rrs1:$addr)>;
> +def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
> +            (tLDRBi t_addrmode_is1:$addr)>;
> 
> // extload -> zextload
> -def : T1Pat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
> -def : T1Pat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
> -def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
> +def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
> +def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
> +def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
> +def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
> +def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
> +def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
> 
> // If it's impossible to use [r,r] address mode for sextload, select to
> // ldr{b|h} + sxt{b|h} instead.
> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
> -            (tSXTB (tLDRB t_addrmode_s1:$addr))>,
> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
> +            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
>       Requires<[IsThumb, IsThumb1Only, HasV6]>;
> -def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
> -            (tSXTH (tLDRH t_addrmode_s2:$addr))>,
> +def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
> +            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
>       Requires<[IsThumb, IsThumb1Only, HasV6]>;
> 
> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
> -            (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
> -def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
> -            (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
> +            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
> +def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr),
> +            (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>;
> 
> // Large immediate handling.
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 21:36:38 2010
> @@ -144,9 +144,9 @@
>   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
>                                    SmallVectorImpl<MCFixup> &Fixups) const;
> 
> -  /// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
> -  uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
> -                                     SmallVectorImpl<MCFixup> &Fixups) const;
> +  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
> +  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
> +                                         SmallVectorImpl<MCFixup> &Fixups)const;
> 
>   /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
>   /// operand.
> @@ -207,9 +207,9 @@
>   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
>                                      SmallVectorImpl<MCFixup> &Fixups) const;
> 
> -  /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
> -  uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
> -                               SmallVectorImpl<MCFixup> &) const;
> +  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
> +  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
> +                                SmallVectorImpl<MCFixup> &) const;
> 
>   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
>   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
> @@ -559,12 +559,16 @@
>                                   Fixups);
> }
> 
> -/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
> +/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
> +/// operand.
> uint32_t ARMMCCodeEmitter::
> -getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
> -                        SmallVectorImpl<MCFixup> &Fixups) const {
> +getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
> +                              SmallVectorImpl<MCFixup> &) const {
> +  // [Rn, Rm]
> +  //   {5-3} = Rm
> +  //   {2-0} = Rn
>   const MCOperand &MO1 = MI.getOperand(OpIdx);
> -  const MCOperand &MO2 = MI.getOperand(OpIdx+1);
> +  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
>   unsigned Rn = getARMRegisterNumbering(MO1.getReg());
>   unsigned Rm = getARMRegisterNumbering(MO2.getReg());
>   return (Rm << 3) | Rn;
> @@ -796,27 +800,17 @@
>   return MO1.getImm() & 0xff;
> }
> 
> -/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
> +/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
> uint32_t ARMMCCodeEmitter::
> -getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
> -                    SmallVectorImpl<MCFixup> &) const {
> -  // [Rn, Rm]
> -  //   {5-3} = Rm
> -  //   {2-0} = Rn
> -  //
> +getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
> +                     SmallVectorImpl<MCFixup> &) const {
>   // [Rn, #imm]
>   //   {7-3} = imm5
>   //   {2-0} = Rn
>   const MCOperand &MO = MI.getOperand(OpIdx);
>   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
> -  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
>   unsigned Rn = getARMRegisterNumbering(MO.getReg());
>   unsigned Imm5 = MO1.getImm();
> -
> -  if (MO2.getReg() != 0)
> -    // Is an immediate.
> -    Imm5 = getARMRegisterNumbering(MO2.getReg());
> -
>   return ((Imm5 & 0x1f) << 3) | Rn;
> }
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 13 21:36:38 2010
> @@ -236,11 +236,16 @@
>     int64_t Value = CE->getValue();
>     return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
>   }
> -  bool isMemModeThumb() const {
> +  bool isMemModeRegThumb() const {
> +    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
> +      return false;
> +    return !Mem.Offset || !isa<MCConstantExpr>(Mem.Offset);
> +  }
> +  bool isMemModeImmThumb() const {
>     if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>       return false;
> 
> -    if (!Mem.Offset) return true;
> +    if (!Mem.Offset) return false;
> 
>     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>     if (!CE) return false;
> @@ -324,19 +329,18 @@
>     }
>   }
> 
> -  void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
> -    assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
> +  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
> +    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
>     Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
> +    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
> +  }
> 
> -    if (Mem.Offset) {
> -      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
> -      assert(CE && "Non-constant mode offset operand!");
> -      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
> -      Inst.addOperand(MCOperand::CreateReg(0));
> -    } else {
> -      Inst.addOperand(MCOperand::CreateImm(0));
> -      Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
> -    }
> +  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
> +    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
> +    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
> +    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
> +    assert(CE && "Non-constant mode offset operand!");
> +    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>   }
> 
>   virtual void dump(raw_ostream &OS) const;
> 
> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Dec 13 21:36:38 2010
> @@ -482,17 +482,25 @@
> void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
>                                                  raw_ostream &O) {
>   const MCOperand &MO1 = MI->getOperand(Op);
> -  const MCOperand &MO2 = MI->getOperand(Op+1);
> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
> +
> +  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
> +    printOperand(MI, Op, O);
> +    return;
> +  }
> +
>   O << "[" << getRegisterName(MO1.getReg());
> -  O << ", " << getRegisterName(MO2.getReg()) << "]";
> +  if (unsigned RegNum = MO2.getReg())
> +    O << ", " << getRegisterName(RegNum);
> +  O << "]";
> }
> 
> -void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
> -                                                  raw_ostream &O,
> -                                                  unsigned Scale) {
> +void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
> +                                                    unsigned Op,
> +                                                    raw_ostream &O,
> +                                                    unsigned Scale) {
>   const MCOperand &MO1 = MI->getOperand(Op);
> -  const MCOperand &MO2 = MI->getOperand(Op+1);
> -  const MCOperand &MO3 = MI->getOperand(Op+2);
> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
> 
>   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>     printOperand(MI, Op, O);
> @@ -500,36 +508,32 @@
>   }
> 
>   O << "[" << getRegisterName(MO1.getReg());
> -  if (MO3.getReg())
> -    O << ", " << getRegisterName(MO3.getReg());
> -  else if (unsigned ImmOffs = MO2.getImm())
> +  if (unsigned ImmOffs = MO2.getImm())
>     O << ", #" << ImmOffs * Scale;
>   O << "]";
> }
> 
> -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
> -                                                 raw_ostream &O) {
> -  printThumbAddrModeRI5Operand(MI, Op, O, 1);
> -}
> -
> -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
> -                                                 raw_ostream &O) {
> -  printThumbAddrModeRI5Operand(MI, Op, O, 2);
> -}
> -
> -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
> -                                                 raw_ostream &O) {
> -  printThumbAddrModeRI5Operand(MI, Op, O, 4);
> +void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
> +                                                     unsigned Op,
> +                                                     raw_ostream &O) {
> +  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
> +}
> +
> +void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
> +                                                     unsigned Op,
> +                                                     raw_ostream &O) {
> +  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
> +}
> +
> +void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
> +                                                     unsigned Op,
> +                                                     raw_ostream &O) {
> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
> }
> 
> void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
>                                                  raw_ostream &O) {
> -  const MCOperand &MO1 = MI->getOperand(Op);
> -  const MCOperand &MO2 = MI->getOperand(Op+1);
> -  O << "[" << getRegisterName(MO1.getReg());
> -  if (unsigned ImmOffs = MO2.getImm())
> -    O << ", #" << ImmOffs*4;
> -  O << "]";
> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
> }
> 
> // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
> 
> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Dec 13 21:36:38 2010
> @@ -59,14 +59,14 @@
>   void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
>   void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
>                                    raw_ostream &O);
> -  void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,
> -                                    raw_ostream &O, unsigned Scale);
> -  void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum,
> -                                   raw_ostream &O);
> -  void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum,
> -                                   raw_ostream &O);
> -  void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum,
> -                                   raw_ostream &O);
> +  void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
> +                                      raw_ostream &O, unsigned Scale);
> +  void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
> +                                       raw_ostream &O);
> +  void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
> +                                       raw_ostream &O);
> +  void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
> +                                       raw_ostream &O);
>   void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
>                                    raw_ostream &O);
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Dec 13 21:36:38 2010
> @@ -644,13 +644,11 @@
>                                 *this, dl);
>     }
> 
> -    MI.setDesc(TII.get(ARM::tLDR));
> +    MI.setDesc(TII.get(ARM::tLDRr));
>     MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
>     if (UseRR)
>       // Use [reg, reg] addrmode.
>       MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
> -    else  // tLDR has an extra register operand.
> -      MI.addOperand(MachineOperand::CreateReg(0, false));
>   } else if (Desc.mayStore()) {
>       VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
>       bool UseRR = false;
> @@ -666,14 +664,13 @@
>       } else
>         emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
>                                   *this, dl);
> -      MI.setDesc(TII.get(ARM::tSTR));
> +      MI.setDesc(TII.get(ARM::tSTRr));
>       MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
>       if (UseRR)  // Use [reg, reg] addrmode.
>         MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
> -      else // tSTR has an extra register operand.
> -        MI.addOperand(MachineOperand::CreateReg(0, false));
> -  } else
> +  } else {
>     assert(false && "Unexpected opcode!");
> +  }
> 
>   // Add predicate back if it's needed.
>   if (MI.getDesc().isPredicable()) {
> 
> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Mon Dec 13 21:36:38 2010
> @@ -105,19 +105,19 @@
>     // FIXME: Clean this up after splitting each Thumb load / store opcode
>     // into multiple ones.
>     { ARM::t2LDRi12,ARM::tLDRi,   ARM::tLDRspi,  5,   8,    1,   0,  0,0, 1 },
> -    { ARM::t2LDRs,  ARM::tLDR,    0,             0,   0,    1,   0,  0,0, 1 },
> +    { ARM::t2LDRs,  ARM::tLDRr,   0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2LDRBi12,ARM::tLDRBi, 0,             5,   0,    1,   0,  0,0, 1 },
> -    { ARM::t2LDRBs, ARM::tLDRB,   0,             0,   0,    1,   0,  0,0, 1 },
> +    { ARM::t2LDRBs, ARM::tLDRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2LDRHi12,ARM::tLDRHi, 0,             5,   0,    1,   0,  0,0, 1 },
> -    { ARM::t2LDRHs, ARM::tLDRH,   0,             0,   0,    1,   0,  0,0, 1 },
> +    { ARM::t2LDRHs, ARM::tLDRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2LDRSBs,ARM::tLDRSB,  0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2LDRSHs,ARM::tLDRSH,  0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2STRi12,ARM::tSTRi,   ARM::tSTRspi,  5,   8,    1,   0,  0,0, 1 },
> -    { ARM::t2STRs,  ARM::tSTR,    0,             0,   0,    1,   0,  0,0, 1 },
> +    { ARM::t2STRs,  ARM::tSTRr,   0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2STRBi12,ARM::tSTRBi, 0,             5,   0,    1,   0,  0,0, 1 },
> -    { ARM::t2STRBs, ARM::tSTRB,   0,             0,   0,    1,   0,  0,0, 1 },
> +    { ARM::t2STRBs, ARM::tSTRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>     { ARM::t2STRHi12,ARM::tSTRHi, 0,             5,   0,    1,   0,  0,0, 1 },
> -    { ARM::t2STRHs, ARM::tSTRH,   0,             0,   0,    1,   0,  0,0, 1 },
> +    { ARM::t2STRHs, ARM::tSTRHr,  0,             0,   0,    1,   0,  0,0, 1 },
> 
>     { ARM::t2LDMIA, ARM::tLDMIA,  0,             0,   0,    1,   1,  1,1, 1 },
>     { ARM::t2LDMIA_RET,0,         ARM::tPOP_RET, 0,   0,    1,   1,  1,1, 1 },
> @@ -273,7 +273,6 @@
>   bool HasShift = false;
>   bool HasOffReg = true;
>   bool isLdStMul = false;
> -  bool InsertImmOffset = true;
>   unsigned Opc = Entry.NarrowOpc1;
>   unsigned OpNum = 3; // First 'rest' of operands.
>   uint8_t  ImmLimit = Entry.Imm1Limit;
> @@ -282,39 +281,41 @@
>   default:
>     llvm_unreachable("Unexpected Thumb2 load / store opcode!");
>   case ARM::t2LDRi12:
> -  case ARM::t2STRi12: {
> -    unsigned BaseReg = MI->getOperand(1).getReg();
> -    if (BaseReg == ARM::SP) {
> +  case ARM::t2STRi12:
> +    if (MI->getOperand(1).getReg() == ARM::SP) {
>       Opc = Entry.NarrowOpc2;
>       ImmLimit = Entry.Imm2Limit;
>       HasOffReg = false;
>     }
> +
>     Scale = 4;
> -    if (MI->getOperand(2).isImm())
> +
> +    if (MI->getOperand(2).isImm()) {
>       HasImmOffset = true;
> -    else {
> +      HasOffReg = false;
> +    } else {
>       if (Entry.WideOpc == ARM::t2LDRi12) {
>         Opc = ARM::tLDRpci;
>         OpNum = 2;
>       }
> +
>       HasImmOffset = false;
> -      InsertImmOffset = false;
>       HasBaseReg = false;
>       HasOffReg = false;
>     }
>     break;
> -  }
>   case ARM::t2LDRBi12:
>   case ARM::t2STRBi12:
> -    if (MI->getOperand(2).isImm())
> +    if (MI->getOperand(2).isImm()) {
>       HasImmOffset = true;
> -    else {
> +      HasOffReg = false;
> +    } else {
>       if (Entry.WideOpc == ARM::t2LDRBi12) {
>         Opc = ARM::tLDRpci;
>         OpNum = 2;
>       }
> +
>       HasImmOffset = false;
> -      InsertImmOffset = false;
>       HasBaseReg = false;
>       HasOffReg = false;
>     }
> @@ -322,15 +323,16 @@
>   case ARM::t2LDRHi12:
>   case ARM::t2STRHi12:
>     Scale = 2;
> -    if (MI->getOperand(2).isImm())
> +    if (MI->getOperand(2).isImm()) {
>       HasImmOffset = true;
> -    else {
> +      HasOffReg = false;
> +    } else {
>       if (Entry.WideOpc == ARM::t2LDRHi12) {
>         Opc = ARM::tLDRpci;
>         OpNum = 2;
>       }
> +
>       HasImmOffset = false;
> -      InsertImmOffset = false;
>       HasBaseReg = false;
>       HasOffReg = false;
>     }
> @@ -351,6 +353,7 @@
>     unsigned BaseReg = MI->getOperand(0).getReg();
>     if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
>       return false;
> +
>     // For the non-writeback version (this one), the base register must be
>     // one of the registers being loaded.
>     bool isOK = false;
> @@ -360,6 +363,7 @@
>         break;
>       }
>     }
> +
>     if (!isOK)
>       return false;
> 
> @@ -381,6 +385,7 @@
>   case ARM::t2STMIA_UPD:
>   case ARM::t2STMDB_UPD: {
>     OpNum = 0;
> +
>     unsigned BaseReg = MI->getOperand(1).getReg();
>     if (BaseReg == ARM::SP &&
>         (Entry.WideOpc == ARM::t2LDMIA_UPD ||
> @@ -392,6 +397,7 @@
>                 Entry.WideOpc != ARM::t2STMIA_UPD)) {
>       return false;
>     }
> +
>     isLdStMul = true;
>     break;
>   }
> @@ -402,6 +408,7 @@
>   if (HasShift) {
>     OffsetReg  = MI->getOperand(2).getReg();
>     OffsetKill = MI->getOperand(2).isKill();
> +
>     if (MI->getOperand(3).getImm())
>       // Thumb1 addressing mode doesn't support shift.
>       return false;
> @@ -411,24 +418,24 @@
>   if (HasImmOffset) {
>     OffsetImm = MI->getOperand(2).getImm();
>     unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
> -    if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
> +
> +    if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
>       // Make sure the immediate field fits.
>       return false;
>   }
> 
>   // Add the 16-bit load / store instruction.
> -  // FIXME: Thumb1 addressing mode encode both immediate and register offset.
>   DebugLoc dl = MI->getDebugLoc();
>   MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
>   if (!isLdStMul) {
>     MIB.addOperand(MI->getOperand(0));
> -    if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
> -    if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
> -      // tLDRSB and tLDRSH do not have an immediate offset field. On the other
> -      // hand, it must have an offset register.
> -      // FIXME: Remove this special case.
> -      MIB.addImm(OffsetImm/Scale);
> -    }
> +
> +    if (HasBaseReg)
> +      MIB.addOperand(MI->getOperand(1));
> +
> +    if (HasImmOffset)
> +      MIB.addImm(OffsetImm / Scale);
> +
>     assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
> 
>     if (HasOffReg)
> 
> Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 21:36:38 2010
> @@ -629,9 +629,12 @@
>   MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
>                                                                   // R, I
>   MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
> -  MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1");           // R, I, R
> -  MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2");           // R, I, R
> -  MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4");           // R, I, R
> +  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
> +  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
> +  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
> +  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
> +  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
> +  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
>   MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
>   MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
>   MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
> @@ -841,9 +844,8 @@
>   operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
>   operandTypes.addEntry("kOperandTypeARMTBAddrMode");
>   operandTypes.addEntry("kOperandTypeThumbITMask");
> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
> +  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
> +  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
>   operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
>   operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
>   operandTypes.addEntry("kOperandTypeThumbAddrModePC");
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From sabre at nondot.org  Tue Dec 14 00:51:56 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 06:51:56 -0000
Subject: [llvm-commits] [llvm] r121753 - in /llvm/trunk:
 include/llvm/Transforms/Utils/BasicBlockUtils.h
 lib/Transforms/Utils/BasicBlockUtils.cpp
Message-ID: <20101214065156.290372A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 00:51:55 2010
New Revision: 121753

URL: http://llvm.org/viewvc/llvm-project?rev=121753&view=rev
Log:
remove the dead (and terrible) llvm::RemoveSuccessor function.

Modified:
    llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp

Modified: llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h?rev=121753&r1=121752&r2=121753&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h Tue Dec 14 00:51:55 2010
@@ -75,15 +75,6 @@
       SmallVectorImpl<std::pair<const BasicBlock*,const BasicBlock*> > &Result);
   
 
-// RemoveSuccessor - Change the specified terminator instruction such that its
-// successor #SuccNum no longer exists.  Because this reduces the outgoing
-// degree of the current basic block, the actual terminator instruction itself
-// may have to be changed.  In the case where the last successor of the block is
-// deleted, a return instruction is inserted in its place which can cause a
-// suprising change in program behavior if it is not expected.
-//
-void RemoveSuccessor(TerminatorInst *TI, unsigned SuccNum);
-
 /// GetSuccessorNumber - Search for the specified successor of basic block BB
 /// and return its position in the terminator instruction's list of
 /// successors.  It is an error to call this with a block that is not a

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=121753&r1=121752&r2=121753&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Dec 14 00:51:55 2010
@@ -218,52 +218,6 @@
   ReplaceInstWithInst(From->getParent()->getInstList(), BI, To);
 }
 
-/// RemoveSuccessor - Change the specified terminator instruction such that its
-/// successor SuccNum no longer exists.  Because this reduces the outgoing
-/// degree of the current basic block, the actual terminator instruction itself
-/// may have to be changed.  In the case where the last successor of the block 
-/// is deleted, a return instruction is inserted in its place which can cause a
-/// surprising change in program behavior if it is not expected.
-///
-void llvm::RemoveSuccessor(TerminatorInst *TI, unsigned SuccNum) {
-  assert(SuccNum < TI->getNumSuccessors() &&
-         "Trying to remove a nonexistant successor!");
-
-  // If our old successor block contains any PHI nodes, remove the entry in the
-  // PHI nodes that comes from this branch...
-  //
-  BasicBlock *BB = TI->getParent();
-  TI->getSuccessor(SuccNum)->removePredecessor(BB);
-
-  TerminatorInst *NewTI = 0;
-  switch (TI->getOpcode()) {
-  case Instruction::Br:
-    // If this is a conditional branch... convert to unconditional branch.
-    if (TI->getNumSuccessors() == 2) {
-      cast<BranchInst>(TI)->setUnconditionalDest(TI->getSuccessor(1-SuccNum));
-    } else {                    // Otherwise convert to a return instruction...
-      Value *RetVal = 0;
-
-      // Create a value to return... if the function doesn't return null...
-      if (!BB->getParent()->getReturnType()->isVoidTy())
-        RetVal = Constant::getNullValue(BB->getParent()->getReturnType());
-
-      // Create the return...
-      NewTI = ReturnInst::Create(TI->getContext(), RetVal);
-    }
-    break;
-
-  case Instruction::Invoke:    // Should convert to call
-  case Instruction::Switch:    // Should remove entry
-  default:
-  case Instruction::Ret:       // Cannot happen, has no successors!
-    llvm_unreachable("Unhandled terminator inst type in RemoveSuccessor!");
-  }
-
-  if (NewTI)   // If it's a different instruction, replace.
-    ReplaceInstWithInst(TI, NewTI);
-}
-
 /// GetSuccessorNumber - Search for the specified successor of basic block BB
 /// and return its position in the terminator instruction's list of
 /// successors.  It is an error to call this with a block that is not a



From sabre at nondot.org  Tue Dec 14 01:00:00 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:00:00 -0000
Subject: [llvm-commits] [llvm] r121754 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214070000.312622A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:00:00 2010
New Revision: 121754

URL: http://llvm.org/viewvc/llvm-project?rev=121754&view=rev
Log:
make FoldTwoEntryPHINode use instsimplify a bit, make
GetIfCondition faster by avoiding pred_iterator.  No
really interesting change.


Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121754&r1=121753&r2=121754&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:00:00 2010
@@ -105,20 +105,21 @@
 }
 
 
-/// GetIfCondition - Given a basic block (BB) with two predecessors (and
-/// presumably PHI nodes in it), check to see if the merge at this block is due
+/// GetIfCondition - Given a basic block (BB) with two predecessors (and at
+/// least one PHI node in it), check to see if the merge at this block is due
 /// to an "if condition".  If so, return the boolean condition that determines
 /// which entry into BB will be taken.  Also, return by references the block
 /// that will be entered from if the condition is true, and the block that will
 /// be entered if the condition is false.
 ///
 ///
-static Value *GetIfCondition(BasicBlock *BB,
-                             BasicBlock *&IfTrue, BasicBlock *&IfFalse) {
-  assert(std::distance(pred_begin(BB), pred_end(BB)) == 2 &&
+static Value *GetIfCondition(BasicBlock *BB, BasicBlock *&IfTrue,
+                             BasicBlock *&IfFalse) {
+  PHINode *SomePHI = cast<PHINode>(BB->begin());
+  assert(SomePHI->getNumIncomingValues() == 2 &&
          "Function can only handle blocks with 2 predecessors!");
-  BasicBlock *Pred1 = *pred_begin(BB);
-  BasicBlock *Pred2 = *++pred_begin(BB);
+  BasicBlock *Pred1 = SomePHI->getIncomingBlock(0);
+  BasicBlock *Pred2 = SomePHI->getIncomingBlock(1);
 
   // We can only handle branches.  Other control flow will be lowered to
   // branches if possible anyway.
@@ -1147,14 +1148,13 @@
 
 /// FoldTwoEntryPHINode - Given a BB that starts with the specified two-entry
 /// PHI node, see if we can eliminate it.
-static bool FoldTwoEntryPHINode(PHINode *PN) {
+static bool FoldTwoEntryPHINode(PHINode *PN, const TargetData *TD) {
   // Ok, this is a two entry PHI node.  Check to see if this is a simple "if
   // statement", which has a very simple dominance structure.  Basically, we
   // are trying to find the condition that is being branched on, which
   // subsequently causes this merge to happen.  We really want control
   // dependence information for this check, but simplifycfg can't keep it up
   // to date, and this catches most of the cases we care about anyway.
-  //
   BasicBlock *BB = PN->getParent();
   BasicBlock *IfTrue, *IfFalse;
   Value *IfCond = GetIfCondition(BB, IfTrue, IfFalse);
@@ -1247,10 +1247,19 @@
     Value *TrueVal  = PN->getIncomingValue(PN->getIncomingBlock(0) == IfFalse);
     Value *FalseVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfTrue);
     
-    Value *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", AfterPHIIt);
+    Value *NV;
+    if (Value *V = SimplifySelectInst(IfCond, TrueVal, FalseVal, TD))
+      NV = V;
+    else if (TrueVal->getType()->isIntegerTy(1) && isa<ConstantInt>(TrueVal) &&
+             cast<ConstantInt>(TrueVal)->isOne()) {
+      if (Value *V = SimplifyOrInst(IfCond, FalseVal, TD))
+        NV = V;
+      else
+        NV = BinaryOperator::CreateOr(IfCond, FalseVal, "", AfterPHIIt);
+    } else
+      NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", AfterPHIIt);
     PN->replaceAllUsesWith(NV);
     NV->takeName(PN);
-    
     PN->eraseFromParent();
   }
   return true;
@@ -2415,7 +2424,7 @@
   // eliminate it, do so now.
   if (PHINode *PN = dyn_cast<PHINode>(BB->begin()))
     if (PN->getNumIncomingValues() == 2)
-      Changed |= FoldTwoEntryPHINode(PN); 
+      Changed |= FoldTwoEntryPHINode(PN, TD);
 
   if (BranchInst *BI = dyn_cast<BranchInst>(BB->getTerminator())) {
     if (BI->isUnconditional()) {



From rafael.espindola at gmail.com  Tue Dec 14 01:06:41 2010
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Mon, 13 Dec 2010 23:06:41 -0800
Subject: [llvm-commits] [llvm] r121402 -
	/llvm/trunk/lib/MC/MCStreamer.cpp
In-Reply-To: <e92c838451.Jo@hobbes.bass-software.com>
References: <20101209192621.AF9112A6C12C@llvm.org>
	<e92c838451.Jo@hobbes.bass-software.com>
Message-ID: <4D071781.2090306@gmail.com>


> This doesn't catch the Size = 1 and Value = 1UL<<63 case.  Use
> Value>  255U instead ?
>
>>     char buf[8];
>>     // FIXME: Endianness assumption.
>>     for (unsigned i = 0; i != Size; ++i)
>
> I've attached a small patch checking on more Value&  Size cases.  Please
> commit after review.

This patch would prevent us from doing EmitIntValue(-1, 1). Is that 
considered a good thing? A quick make check found just one case, so it 
is probably fine.

Maybe we should just check that the number is valid as a signed or 
unsigned value?

> John.

Cheers,
Rafael

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From sabre at nondot.org  Tue Dec 14 01:09:43 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:09:43 -0000
Subject: [llvm-commits] [llvm] r121755 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214070943.181542A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:09:42 2010
New Revision: 121755

URL: http://llvm.org/viewvc/llvm-project?rev=121755&view=rev
Log:
use AddPredecessorToBlock in 3 places instead of a manual loop.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121755&r1=121754&r2=121755&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:09:42 2010
@@ -94,8 +94,6 @@
 /// ExistPred, an existing predecessor of Succ.
 static void AddPredecessorToBlock(BasicBlock *Succ, BasicBlock *NewPred,
                                   BasicBlock *ExistPred) {
-  assert(std::find(succ_begin(ExistPred), succ_end(ExistPred), Succ) !=
-         succ_end(ExistPred) && "ExistPred is not a predecessor of Succ!");
   if (!isa<PHINode>(Succ->begin())) return; // Quick exit if nothing to do
   
   PHINode *PN;
@@ -1089,12 +1087,9 @@
                                             RealDest->getName()+".critedge",
                                             RealDest->getParent(), RealDest);
     BranchInst::Create(RealDest, EdgeBB);
-    PHINode *PN;
-    for (BasicBlock::iterator BBI = RealDest->begin();
-         (PN = dyn_cast<PHINode>(BBI)); ++BBI) {
-      Value *V = PN->getIncomingValueForBlock(BB);
-      PN->addIncoming(V, EdgeBB);
-    }
+    
+    // Update PHI nodes.
+    AddPredecessorToBlock(RealDest, EdgeBB, BB);
 
     // BB may have instructions that are being threaded over.  Clone these
     // instructions into EdgeBB.  We know that there will be no uses of the
@@ -1674,17 +1669,13 @@
   
   // OtherDest may have phi nodes.  If so, add an entry from PBI's
   // block that are identical to the entries for BI's block.
-  PHINode *PN;
-  for (BasicBlock::iterator II = OtherDest->begin();
-       (PN = dyn_cast<PHINode>(II)); ++II) {
-    Value *V = PN->getIncomingValueForBlock(BB);
-    PN->addIncoming(V, PBI->getParent());
-  }
+  AddPredecessorToBlock(OtherDest, PBI->getParent(), BB);
   
   // We know that the CommonDest already had an edge from PBI to
   // it.  If it has PHIs though, the PHIs may have different
   // entries for BB and PBI's BB.  If so, insert a select to make
   // them agree.
+  PHINode *PN;
   for (BasicBlock::iterator II = CommonDest->begin();
        (PN = dyn_cast<PHINode>(II)); ++II) {
     Value *BIV = PN->getIncomingValueForBlock(BB);
@@ -1935,10 +1926,7 @@
     
     // If there are PHI nodes in EdgeBB, then we need to add a new entry to them
     // for the edge we just added.
-    for (BasicBlock::iterator I = EdgeBB->begin(); isa<PHINode>(I); ++I) {
-      PHINode *PN = cast<PHINode>(I);
-      PN->addIncoming(PN->getIncomingValueForBlock(NewBB), BB);
-    }
+    AddPredecessorToBlock(EdgeBB, BB, NewBB);
     
     DEBUG(dbgs() << "  ** 'icmp' chain unhandled condition: " << *ExtraCase
           << "\nEXTRABB = " << *BB);



From sabre at nondot.org  Tue Dec 14 01:15:21 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:15:21 -0000
Subject: [llvm-commits] [llvm] r121756 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214071521.C73D32A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:15:21 2010
New Revision: 121756

URL: http://llvm.org/viewvc/llvm-project?rev=121756&view=rev
Log:
simplify GetIfCondition by using getSinglePredecessor.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121756&r1=121755&r2=121756&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:15:21 2010
@@ -110,7 +110,8 @@
 /// that will be entered from if the condition is true, and the block that will
 /// be entered if the condition is false.
 ///
-///
+/// This does no checking to see if the true/false blocks have large or unsavory
+/// instructions in them.
 static Value *GetIfCondition(BasicBlock *BB, BasicBlock *&IfTrue,
                              BasicBlock *&IfFalse) {
   PHINode *SomePHI = cast<PHINode>(BB->begin());
@@ -121,11 +122,10 @@
 
   // We can only handle branches.  Other control flow will be lowered to
   // branches if possible anyway.
-  if (!isa<BranchInst>(Pred1->getTerminator()) ||
-      !isa<BranchInst>(Pred2->getTerminator()))
+  BranchInst *Pred1Br = dyn_cast<BranchInst>(Pred1->getTerminator());
+  BranchInst *Pred2Br = dyn_cast<BranchInst>(Pred2->getTerminator());
+  if (Pred1Br == 0 || Pred2Br == 0)
     return 0;
-  BranchInst *Pred1Br = cast<BranchInst>(Pred1->getTerminator());
-  BranchInst *Pred2Br = cast<BranchInst>(Pred2->getTerminator());
 
   // Eliminate code duplication by ensuring that Pred1Br is conditional if
   // either are.
@@ -142,6 +142,12 @@
   }
 
   if (Pred1Br->isConditional()) {
+    // The only thing we have to watch out for here is to make sure that Pred2
+    // doesn't have incoming edges from other blocks.  If it does, the condition
+    // doesn't dominate BB.
+    if (Pred2->getSinglePredecessor() == 0)
+      return 0;
+    
     // If we found a conditional branch predecessor, make sure that it branches
     // to BB and Pred2Br.  If it doesn't, this isn't an "if statement".
     if (Pred1Br->getSuccessor(0) == BB &&
@@ -158,39 +164,29 @@
       return 0;
     }
 
-    // The only thing we have to watch out for here is to make sure that Pred2
-    // doesn't have incoming edges from other blocks.  If it does, the condition
-    // doesn't dominate BB.
-    if (++pred_begin(Pred2) != pred_end(Pred2))
-      return 0;
-
     return Pred1Br->getCondition();
   }
 
   // Ok, if we got here, both predecessors end with an unconditional branch to
   // BB.  Don't panic!  If both blocks only have a single (identical)
   // predecessor, and THAT is a conditional branch, then we're all ok!
-  if (pred_begin(Pred1) == pred_end(Pred1) ||
-      ++pred_begin(Pred1) != pred_end(Pred1) ||
-      pred_begin(Pred2) == pred_end(Pred2) ||
-      ++pred_begin(Pred2) != pred_end(Pred2) ||
-      *pred_begin(Pred1) != *pred_begin(Pred2))
+  BasicBlock *CommonPred = Pred1->getSinglePredecessor();
+  if (CommonPred == 0 || CommonPred != Pred2->getSinglePredecessor())
     return 0;
 
   // Otherwise, if this is a conditional branch, then we can use it!
-  BasicBlock *CommonPred = *pred_begin(Pred1);
-  if (BranchInst *BI = dyn_cast<BranchInst>(CommonPred->getTerminator())) {
-    assert(BI->isConditional() && "Two successors but not conditional?");
-    if (BI->getSuccessor(0) == Pred1) {
-      IfTrue = Pred1;
-      IfFalse = Pred2;
-    } else {
-      IfTrue = Pred2;
-      IfFalse = Pred1;
-    }
-    return BI->getCondition();
+  BranchInst *BI = dyn_cast<BranchInst>(CommonPred->getTerminator());
+  if (BI == 0) return 0;
+  
+  assert(BI->isConditional() && "Two successors but not conditional?");
+  if (BI->getSuccessor(0) == Pred1) {
+    IfTrue = Pred1;
+    IfFalse = Pred2;
+  } else {
+    IfTrue = Pred2;
+    IfFalse = Pred1;
   }
-  return 0;
+  return BI->getCondition();
 }
 
 /// DominatesMergePoint - If we have a merge point of an "if condition" as



From sabre at nondot.org  Tue Dec 14 01:20:29 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:20:29 -0000
Subject: [llvm-commits] [llvm] r121757 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214072029.B1DDF2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:20:29 2010
New Revision: 121757

URL: http://llvm.org/viewvc/llvm-project?rev=121757&view=rev
Log:
use SimplifyInstruction instead of reimplementing part of it.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121757&r1=121756&r2=121757&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:20:29 2010
@@ -1172,17 +1172,14 @@
   BasicBlock::iterator AfterPHIIt = BB->begin();
   while (isa<PHINode>(AfterPHIIt)) {
     PHINode *PN = cast<PHINode>(AfterPHIIt++);
-    if (PN->getIncomingValue(0) == PN->getIncomingValue(1)) {
-      if (PN->getIncomingValue(0) != PN)
-        PN->replaceAllUsesWith(PN->getIncomingValue(0));
-      else
-        PN->replaceAllUsesWith(UndefValue::get(PN->getType()));
-    } else if (!DominatesMergePoint(PN->getIncomingValue(0), BB,
-                                    &AggressiveInsts) ||
-               !DominatesMergePoint(PN->getIncomingValue(1), BB,
-                                    &AggressiveInsts)) {
-      return false;
+    if (Value *V = SimplifyInstruction(PN, TD)) {
+      PN->replaceAllUsesWith(V);
+      continue;
     }
+    
+    if (!DominatesMergePoint(PN->getIncomingValue(0), BB, &AggressiveInsts) ||
+        !DominatesMergePoint(PN->getIncomingValue(1), BB, &AggressiveInsts))
+      return false;
   }
   
   // If we all PHI nodes are promotable, check to make sure that all



From sabre at nondot.org  Tue Dec 14 01:23:10 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:23:10 -0000
Subject: [llvm-commits] [llvm] r121758 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214072310.C6F7D2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:23:10 2010
New Revision: 121758

URL: http://llvm.org/viewvc/llvm-project?rev=121758&view=rev
Log:
tidy up a bit, move DEBUG down to when we commit to doing the transform so we 
don't print it unless the xform happens.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121758&r1=121757&r2=121758&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:23:10 2010
@@ -1161,9 +1161,6 @@
     if (NumPhis > 2)
       return false;
   
-  DEBUG(dbgs() << "FOUND IF CONDITION!  " << *IfCond << "  T: "
-        << IfTrue->getName() << "  F: " << IfFalse->getName() << "\n");
-  
   // Loop over the PHI's seeing if we can promote them all to select
   // instructions.  While we are at it, keep track of the instructions
   // that need to be moved to the dominating block.
@@ -1192,8 +1189,7 @@
   if (cast<BranchInst>(Pred->getTerminator())->isUnconditional()) {
     IfBlock1 = Pred;
     DomBlock = *pred_begin(Pred);
-    for (BasicBlock::iterator I = Pred->begin();
-         !isa<TerminatorInst>(I); ++I)
+    for (BasicBlock::iterator I = Pred->begin(); !isa<TerminatorInst>(I); ++I)
       if (!AggressiveInsts.count(I) && !isa<DbgInfoIntrinsic>(I)) {
         // This is not an aggressive instruction that we can promote.
         // Because of this, we won't be able to get rid of the control
@@ -1206,8 +1202,7 @@
   if (cast<BranchInst>(Pred->getTerminator())->isUnconditional()) {
     IfBlock2 = Pred;
     DomBlock = *pred_begin(Pred);
-    for (BasicBlock::iterator I = Pred->begin();
-         !isa<TerminatorInst>(I); ++I)
+    for (BasicBlock::iterator I = Pred->begin(); !isa<TerminatorInst>(I); ++I)
       if (!AggressiveInsts.count(I) && !isa<DbgInfoIntrinsic>(I)) {
         // This is not an aggressive instruction that we can promote.
         // Because of this, we won't be able to get rid of the control
@@ -1215,6 +1210,9 @@
         return false;
       }
   }
+  
+  DEBUG(dbgs() << "FOUND IF CONDITION!  " << *IfCond << "  T: "
+        << IfTrue->getName() << "  F: " << IfFalse->getName() << "\n");
       
   // If we can still promote the PHI nodes after this gauntlet of tests,
   // do all of the PHI's now.



From sabre at nondot.org  Tue Dec 14 01:41:40 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:41:40 -0000
Subject: [llvm-commits] [llvm] r121760 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214074140.283DA2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:41:39 2010
New Revision: 121760

URL: http://llvm.org/viewvc/llvm-project?rev=121760&view=rev
Log:
clean up logic, convert std::set to SmallPtrSet, handle the case
when all 2-entry phis are simplified away.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121760&r1=121759&r2=121760&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:41:39 2010
@@ -199,7 +199,7 @@
 /// non-trapping.  If both are true, the instruction is inserted into the set
 /// and true is returned.
 static bool DominatesMergePoint(Value *V, BasicBlock *BB,
-                                std::set<Instruction*> *AggressiveInsts) {
+                                SmallPtrSet<Instruction*, 4> *AggressiveInsts) {
   Instruction *I = dyn_cast<Instruction>(V);
   if (!I) {
     // Non-instructions all dominate instructions, but not all constantexprs
@@ -217,50 +217,49 @@
 
   // If this instruction is defined in a block that contains an unconditional
   // branch to BB, then it must be in the 'conditional' part of the "if
-  // statement".
-  if (BranchInst *BI = dyn_cast<BranchInst>(PBB->getTerminator()))
-    if (BI->isUnconditional() && BI->getSuccessor(0) == BB) {
-      if (!AggressiveInsts) return false;
-      // Okay, it looks like the instruction IS in the "condition".  Check to
-      // see if it's a cheap instruction to unconditionally compute, and if it
-      // only uses stuff defined outside of the condition.  If so, hoist it out.
-      if (!I->isSafeToSpeculativelyExecute())
-        return false;
+  // statement".  If not, it definitely dominates the region.
+  BranchInst *BI = dyn_cast<BranchInst>(PBB->getTerminator());
+  if (BI == 0 || BI->isConditional() || BI->getSuccessor(0) != BB)
+    return true;
 
-      switch (I->getOpcode()) {
-      default: return false;  // Cannot hoist this out safely.
-      case Instruction::Load: {
-        // We have to check to make sure there are no instructions before the
-        // load in its basic block, as we are going to hoist the loop out to
-        // its predecessor.
-        BasicBlock::iterator IP = PBB->begin();
-        while (isa<DbgInfoIntrinsic>(IP))
-          IP++;
-        if (IP != BasicBlock::iterator(I))
-          return false;
-        break;
-      }
-      case Instruction::Add:
-      case Instruction::Sub:
-      case Instruction::And:
-      case Instruction::Or:
-      case Instruction::Xor:
-      case Instruction::Shl:
-      case Instruction::LShr:
-      case Instruction::AShr:
-      case Instruction::ICmp:
-        break;   // These are all cheap and non-trapping instructions.
-      }
+  // If we aren't allowing aggressive promotion anymore, then don't consider
+  // instructions in the 'if region'.
+  if (AggressiveInsts == 0) return false;
+  
+  // Okay, it looks like the instruction IS in the "condition".  Check to
+  // see if it's a cheap instruction to unconditionally compute, and if it
+  // only uses stuff defined outside of the condition.  If so, hoist it out.
+  if (!I->isSafeToSpeculativelyExecute())
+    return false;
 
-      // Okay, we can only really hoist these out if their operands are not
-      // defined in the conditional region.
-      for (User::op_iterator i = I->op_begin(), e = I->op_end(); i != e; ++i)
-        if (!DominatesMergePoint(*i, BB, 0))
-          return false;
-      // Okay, it's safe to do this!  Remember this instruction.
-      AggressiveInsts->insert(I);
-    }
+  switch (I->getOpcode()) {
+  default: return false;  // Cannot hoist this out safely.
+  case Instruction::Load:
+    // We have to check to make sure there are no instructions before the
+    // load in its basic block, as we are going to hoist the load out to its
+    // predecessor.
+    if (PBB->getFirstNonPHIOrDbg() != I)
+      return false;
+    break;
+  case Instruction::Add:
+  case Instruction::Sub:
+  case Instruction::And:
+  case Instruction::Or:
+  case Instruction::Xor:
+  case Instruction::Shl:
+  case Instruction::LShr:
+  case Instruction::AShr:
+  case Instruction::ICmp:
+    break;   // These are all cheap and non-trapping instructions.
+  }
 
+  // Okay, we can only really hoist these out if their operands are not
+  // defined in the conditional region.
+  for (User::op_iterator i = I->op_begin(), e = I->op_end(); i != e; ++i)
+    if (!DominatesMergePoint(*i, BB, 0))
+      return false;
+  // Okay, it's safe to do this!  Remember this instruction.
+  AggressiveInsts->insert(I);
   return true;
 }
 
@@ -1164,7 +1163,7 @@
   // Loop over the PHI's seeing if we can promote them all to select
   // instructions.  While we are at it, keep track of the instructions
   // that need to be moved to the dominating block.
-  std::set<Instruction*> AggressiveInsts;
+  SmallPtrSet<Instruction*, 4> AggressiveInsts;
   
   BasicBlock::iterator AfterPHIIt = BB->begin();
   while (isa<PHINode>(AfterPHIIt)) {
@@ -1179,17 +1178,23 @@
       return false;
   }
   
+  // If we folded the the first phi, PN dangles at this point.  Refresh it.  If
+  // we ran out of PHIs then we simplified them all.
+  PN = dyn_cast<PHINode>(BB->begin());
+  if (PN == 0) return true;
+  
   // If we all PHI nodes are promotable, check to make sure that all
   // instructions in the predecessor blocks can be promoted as well.  If
   // not, we won't be able to get rid of the control flow, so it's not
   // worth promoting to select instructions.
-  BasicBlock *DomBlock = 0, *IfBlock1 = 0, *IfBlock2 = 0;
-  PN = cast<PHINode>(BB->begin());
-  BasicBlock *Pred = PN->getIncomingBlock(0);
-  if (cast<BranchInst>(Pred->getTerminator())->isUnconditional()) {
-    IfBlock1 = Pred;
-    DomBlock = *pred_begin(Pred);
-    for (BasicBlock::iterator I = Pred->begin(); !isa<TerminatorInst>(I); ++I)
+  BasicBlock *DomBlock = 0;
+  BasicBlock *IfBlock1 = PN->getIncomingBlock(0);
+  BasicBlock *IfBlock2 = PN->getIncomingBlock(1);
+  if (cast<BranchInst>(IfBlock1->getTerminator())->isConditional()) {
+    IfBlock1 = 0;
+  } else {
+    DomBlock = *pred_begin(IfBlock1);
+    for (BasicBlock::iterator I = IfBlock1->begin();!isa<TerminatorInst>(I);++I)
       if (!AggressiveInsts.count(I) && !isa<DbgInfoIntrinsic>(I)) {
         // This is not an aggressive instruction that we can promote.
         // Because of this, we won't be able to get rid of the control
@@ -1198,11 +1203,11 @@
       }
   }
     
-  Pred = PN->getIncomingBlock(1);
-  if (cast<BranchInst>(Pred->getTerminator())->isUnconditional()) {
-    IfBlock2 = Pred;
-    DomBlock = *pred_begin(Pred);
-    for (BasicBlock::iterator I = Pred->begin(); !isa<TerminatorInst>(I); ++I)
+  if (cast<BranchInst>(IfBlock2->getTerminator())->isConditional()) {
+    IfBlock2 = 0;
+  } else {
+    DomBlock = *pred_begin(IfBlock2);
+    for (BasicBlock::iterator I = IfBlock2->begin();!isa<TerminatorInst>(I);++I)
       if (!AggressiveInsts.count(I) && !isa<DbgInfoIntrinsic>(I)) {
         // This is not an aggressive instruction that we can promote.
         // Because of this, we won't be able to get rid of the control
@@ -1212,7 +1217,7 @@
   }
   
   DEBUG(dbgs() << "FOUND IF CONDITION!  " << *IfCond << "  T: "
-        << IfTrue->getName() << "  F: " << IfFalse->getName() << "\n");
+               << IfTrue->getName() << "  F: " << IfFalse->getName() << "\n");
       
   // If we can still promote the PHI nodes after this gauntlet of tests,
   // do all of the PHI's now.



From sabre at nondot.org  Tue Dec 14 01:53:03 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 07:53:03 -0000
Subject: [llvm-commits] [llvm] r121761 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101214075303.EE7A02A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 01:53:03 2010
New Revision: 121761

URL: http://llvm.org/viewvc/llvm-project?rev=121761&view=rev
Log:
remove the instsimplify logic I added in r121754.  It is apparently
breaking the selfhost builds, though I can't fathom how.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121761&r1=121760&r2=121761&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 01:53:03 2010
@@ -1238,17 +1238,7 @@
     Value *TrueVal  = PN->getIncomingValue(PN->getIncomingBlock(0) == IfFalse);
     Value *FalseVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfTrue);
     
-    Value *NV;
-    if (Value *V = SimplifySelectInst(IfCond, TrueVal, FalseVal, TD))
-      NV = V;
-    else if (TrueVal->getType()->isIntegerTy(1) && isa<ConstantInt>(TrueVal) &&
-             cast<ConstantInt>(TrueVal)->isOne()) {
-      if (Value *V = SimplifyOrInst(IfCond, FalseVal, TD))
-        NV = V;
-      else
-        NV = BinaryOperator::CreateOr(IfCond, FalseVal, "", AfterPHIIt);
-    } else
-      NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", AfterPHIIt);
+    Value *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", AfterPHIIt);
     PN->replaceAllUsesWith(NV);
     NV->takeName(PN);
     PN->eraseFromParent();



From sabre at nondot.org  Tue Dec 14 02:01:53 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 08:01:53 -0000
Subject: [llvm-commits] [llvm] r121762 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/PhiBlockMerge.ll
Message-ID: <20101214080153.EB32D2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 02:01:53 2010
New Revision: 121762

URL: http://llvm.org/viewvc/llvm-project?rev=121762&view=rev
Log:
fix two significant issues with FoldTwoEntryPHINode:

first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.

second, it doesn't clean up the "if diamond" that it just 
eliminated away.  This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.


Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121762&r1=121761&r2=121762&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 02:01:53 2010
@@ -1148,7 +1148,10 @@
   BasicBlock *BB = PN->getParent();
   BasicBlock *IfTrue, *IfFalse;
   Value *IfCond = GetIfCondition(BB, IfTrue, IfFalse);
-  if (!IfCond) return false;
+  if (!IfCond ||
+      // Don't bother if the branch will be constant folded trivially.
+      isa<ConstantInt>(IfCond))
+    return false;
   
   // Okay, we found that we can merge this two-entry phi node into a select.
   // Doing so would require us to fold *all* two entry phi nodes in this block.
@@ -1243,6 +1246,13 @@
     NV->takeName(PN);
     PN->eraseFromParent();
   }
+  
+  // At this point, IfBlock1 and IfBlock2 are both empty, so our if statement
+  // has been flattened.  Change DomBlock to jump directly to our new block to
+  // avoid other simplifycfg's kicking in on the diamond.
+  TerminatorInst *OldTI = DomBlock->getTerminator();
+  BranchInst::Create(BB, OldTI);
+  OldTI->eraseFromParent();
   return true;
 }
 

Modified: llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll?rev=121762&r1=121761&r2=121762&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll Tue Dec 14 02:01:53 2010
@@ -1,12 +1,14 @@
 ; Test merging of blocks that only have PHI nodes in them
 ;
-; RUN: opt < %s -simplifycfg -S | not grep N:
+; RUN: opt < %s -simplifycfg -S | FileCheck %s
 ;
 
 define i32 @test(i1 %a, i1 %b) {
-; <label>:0
+; CHECK: br i1 %a
         br i1 %a, label %M, label %O
 O:              ; preds = %0
+; CHECK: select i1 %b, i32 0, i32 1
+; CHECK-NOT: phi
         br i1 %b, label %N, label %Q
 Q:              ; preds = %O
         br label %N
@@ -15,6 +17,7 @@
         %Wp = phi i32 [ 0, %O ], [ 1, %Q ]              ; <i32> [#uses=1]
         br label %M
 M:              ; preds = %N, %0
+; CHECK: %W = phi i32
         %W = phi i32 [ %Wp, %N ], [ 2, %0 ]             ; <i32> [#uses=1]
         %R = add i32 %W, 1              ; <i32> [#uses=1]
         ret i32 %R



From sabre at nondot.org  Tue Dec 14 02:46:09 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 08:46:09 -0000
Subject: [llvm-commits] [llvm] r121764 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/PhiEliminate.ll
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101214084609.363D52A6C12D@llvm.org>

Author: lattner
Date: Tue Dec 14 02:46:09 2010
New Revision: 121764

URL: http://llvm.org/viewvc/llvm-project?rev=121764&view=rev
Log:
 - Insert new instructions before DomBlock's terminator,
   which is simpler than finding a place to insert in BB.
 - Don't perform the 'if condition hoisting' xform on certain
   i1 PHIs, as it interferes with switch formation.

This re-fixes "example 7", without breaking the world hopefully.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate.ll
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121764&r1=121763&r2=121764&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 02:46:09 2010
@@ -1168,11 +1168,11 @@
   // that need to be moved to the dominating block.
   SmallPtrSet<Instruction*, 4> AggressiveInsts;
   
-  BasicBlock::iterator AfterPHIIt = BB->begin();
-  while (isa<PHINode>(AfterPHIIt)) {
-    PHINode *PN = cast<PHINode>(AfterPHIIt++);
+  for (BasicBlock::iterator II = BB->begin(); isa<PHINode>(II);) {
+    PHINode *PN = cast<PHINode>(II++);
     if (Value *V = SimplifyInstruction(PN, TD)) {
       PN->replaceAllUsesWith(V);
+      PN->eraseFromParent();
       continue;
     }
     
@@ -1186,6 +1186,14 @@
   PN = dyn_cast<PHINode>(BB->begin());
   if (PN == 0) return true;
   
+  // Don't fold i1 branches on PHIs which contain binary operators.  These can
+  // often be turned into switches and other things.
+  if (PN->getType()->isIntegerTy(1) &&
+      (isa<BinaryOperator>(PN->getIncomingValue(0)) ||
+       isa<BinaryOperator>(PN->getIncomingValue(1)) ||
+       isa<BinaryOperator>(IfCond)))
+    return false;
+  
   // If we all PHI nodes are promotable, check to make sure that all
   // instructions in the predecessor blocks can be promoted as well.  If
   // not, we won't be able to get rid of the control flow, so it's not
@@ -1224,15 +1232,16 @@
       
   // If we can still promote the PHI nodes after this gauntlet of tests,
   // do all of the PHI's now.
-
+  Instruction *InsertPt = DomBlock->getTerminator();
+  
   // Move all 'aggressive' instructions, which are defined in the
   // conditional parts of the if's up to the dominating block.
   if (IfBlock1)
-    DomBlock->getInstList().splice(DomBlock->getTerminator(),
+    DomBlock->getInstList().splice(InsertPt,
                                    IfBlock1->getInstList(), IfBlock1->begin(),
                                    IfBlock1->getTerminator());
   if (IfBlock2)
-    DomBlock->getInstList().splice(DomBlock->getTerminator(),
+    DomBlock->getInstList().splice(InsertPt,
                                    IfBlock2->getInstList(), IfBlock2->begin(),
                                    IfBlock2->getTerminator());
   
@@ -1241,7 +1250,7 @@
     Value *TrueVal  = PN->getIncomingValue(PN->getIncomingBlock(0) == IfFalse);
     Value *FalseVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfTrue);
     
-    Value *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", AfterPHIIt);
+    Value *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", InsertPt);
     PN->replaceAllUsesWith(NV);
     NV->takeName(PN);
     PN->eraseFromParent();

Modified: llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate.ll?rev=121764&r1=121763&r2=121764&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate.ll Tue Dec 14 02:46:09 2010
@@ -11,20 +11,6 @@
 
 declare void @use.upgrd.1(i32)
 
-define void @test2(i1 %c, i1 %d, i32 %V, i32 %V2) {
-; <label>:0
-        br i1 %d, label %X, label %F
-X:              ; preds = %0
-        br i1 %c, label %T, label %F
-T:              ; preds = %X
-        br label %F
-F:              ; preds = %T, %X, %0
-        %B1 = phi i1 [ true, %0 ], [ false, %T ], [ false, %X ]         ; <i1> [#uses=1]
-        %I7 = phi i32 [ %V, %0 ], [ %V2, %T ], [ %V2, %X ]              ; <i32> [#uses=1]
-        call void @use( i1 %B1 )
-        call void @use.upgrd.1( i32 %I7 )
-        ret void
-}
 
 define void @test(i1 %c, i32 %V, i32 %V2) {
 ; <label>:0

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=121764&r1=121763&r2=121764&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Tue Dec 14 02:46:09 2010
@@ -253,21 +253,21 @@
   ret i32 %conv46
   
 ; CHECK: @test9
-; HECK:   %cmp = icmp ult i8 %c, 33
-; HECK:   br i1 %cmp, label %lor.end, label %switch.early.test
+; CHECK:   %cmp = icmp ult i8 %c, 33
+; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
-; HECK: switch.early.test:
-; HECK:   switch i8 %c, label %lor.rhs [
-; HECK:     i8 46, label %lor.end
-; HECK:     i8 44, label %lor.end
-; HECK:     i8 58, label %lor.end
-; HECK:     i8 59, label %lor.end
-; HECK:     i8 60, label %lor.end
-; HECK:     i8 62, label %lor.end
-; HECK:     i8 34, label %lor.end
-; HECK:     i8 92, label %lor.end
-; HECK:     i8 39, label %lor.end
-; HECK:   ]
+; CHECK: switch.early.test:
+; CHECK:   switch i8 %c, label %lor.rhs [
+; CHECK:     i8 92, label %lor.end
+; CHECK:     i8 62, label %lor.end
+; CHECK:     i8 60, label %lor.end
+; CHECK:     i8 59, label %lor.end
+; CHECK:     i8 58, label %lor.end
+; CHECK:     i8 46, label %lor.end
+; CHECK:     i8 44, label %lor.end
+; CHECK:     i8 34, label %lor.end
+; CHECK:     i8 39, label %lor.end
+; CHECK:   ]
 }
 
 define i32 @test10(i32 %mode, i1 %Cond) {
@@ -351,4 +351,4 @@
   ret void
 ; CHECK: @test12
 
-}
+}
\ No newline at end of file



From isanbard at gmail.com  Tue Dec 14 05:36:26 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 03:36:26 -0800
Subject: [llvm-commits] [llvm] r121747 - in /llvm/trunk:
	lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMCodeEmitter.cpp
	lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrThumb.td
	lib/Target/ARM/ARMMCCodeEmitter.cpp
	lib/Target/ARM/AsmParser/ARMAsmParser.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.h
	lib/Target/ARM/Thumb1RegisterInfo.cpp
	lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/EDEmitter.cpp
In-Reply-To: <D060E5D8-3663-43A3-9EDF-4689B028A929@apple.com>
References: <20101214033639.1C4662A6C12C@llvm.org>
	<D060E5D8-3663-43A3-9EDF-4689B028A929@apple.com>
Message-ID: <4BE9BD84-20DE-4612-A959-5F6F02454021@gmail.com>

I can do that (or at least continue it) as part of the cleanup I need to do because of this patch.

-bw

On Dec 13, 2010, at 10:53 PM, Evan Cheng wrote:

> Thanks. It would be nice if we could completely split out loads / stores for ARM as well. Jim started on it but he ran out of time.
> 
> Evan
> 
> On Dec 13, 2010, at 7:36 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Mon Dec 13 21:36:38 2010
>> New Revision: 121747
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=121747&view=rev
>> Log:
>> The tLDR et al instructions were emitting either a reg/reg or reg/imm
>> instruction based on the t_addrmode_s# mode and what it returned. There is some
>> obvious badness to this. In particular, it's hard to do MC-encoding when the
>> instruction may change out from underneath you after the t_addrmode_s# variable
>> is finally resolved.
>> 
>> The solution is to revert a long-ago change that merged the reg/reg and reg/imm
>> versions. There is the addition of several new addressing modes. They no longer
>> have extraneous operands associated with them. I.e., if it's reg/reg we don't
>> have to have a dummy zero immediate tacked on to the SDNode.
>> 
>> There are some obvious cleanups here, which will happen shortly.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>>   llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>>   llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>   llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>>   llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>   llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>>   llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>>   llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>   llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>>   llvm/trunk/utils/TableGen/EDEmitter.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 13 21:36:38 2010
>> @@ -1129,13 +1129,12 @@
>>    }
>>    {
>>      MCInst TmpInst;
>> -      TmpInst.setOpcode(ARM::tSTR);
>> +      TmpInst.setOpcode(ARM::tSTRi);
>>      TmpInst.addOperand(MCOperand::CreateReg(ValReg));
>>      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>      // The offset immediate is #4. The operand value is scaled by 4 for the
>>      // tSTR instruction.
>>      TmpInst.addOperand(MCOperand::CreateImm(1));
>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>      // Predicate.
>>      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>      TmpInst.addOperand(MCOperand::CreateReg(0));
>> @@ -1312,13 +1311,12 @@
>>    unsigned ScratchReg = MI->getOperand(1).getReg();
>>    {
>>      MCInst TmpInst;
>> -      TmpInst.setOpcode(ARM::tLDR);
>> +      TmpInst.setOpcode(ARM::tLDRi);
>>      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>      // The offset immediate is #8. The operand value is scaled by 4 for the
>> -      // tSTR instruction.
>> +      // tLDR instruction.
>>      TmpInst.addOperand(MCOperand::CreateImm(2));
>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>      // Predicate.
>>      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>      TmpInst.addOperand(MCOperand::CreateReg(0));
>> @@ -1336,11 +1334,10 @@
>>    }
>>    {
>>      MCInst TmpInst;
>> -      TmpInst.setOpcode(ARM::tLDR);
>> +      TmpInst.setOpcode(ARM::tLDRi);
>>      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>      TmpInst.addOperand(MCOperand::CreateImm(1));
>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>      // Predicate.
>>      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>      TmpInst.addOperand(MCOperand::CreateReg(0));
>> @@ -1348,10 +1345,9 @@
>>    }
>>    {
>>      MCInst TmpInst;
>> -      TmpInst.setOpcode(ARM::tLDR);
>> +      TmpInst.setOpcode(ARM::tLDRr);
>>      TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
>>      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>> -      TmpInst.addOperand(MCOperand::CreateImm(0));
>>      TmpInst.addOperand(MCOperand::CreateReg(0));
>>      // Predicate.
>>      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 21:36:38 2010
>> @@ -193,7 +193,7 @@
>>      const { return 0; }
>>    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
>>      const { return 0; }
>> -    unsigned getTAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>> +    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>>      const { return 0; }
>>    unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
>>      const { return 0; }
>> @@ -265,6 +265,8 @@
>>      const { return 0; }
>>    uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
>>      const { return 0; }
>> +    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
>> +      const { return 0; }
>>    uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
>>      const { return 0; }
>>    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Dec 13 21:36:38 2010
>> @@ -130,18 +130,24 @@
>>  bool SelectAddrModePC(SDValue N, SDValue &Offset,
>>                        SDValue &Label);
>> 
>> +  // Thumb Addressing Modes:
>>  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
>> -  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
>> -                              SDValue &Base, SDValue &OffImm,
>> -                              SDValue &Offset);
>> -  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
>> -                             SDValue &OffImm, SDValue &Offset);
>> -  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
>> -                             SDValue &OffImm, SDValue &Offset);
>> -  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
>> -                             SDValue &OffImm, SDValue &Offset);
>> +  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
>> +                             unsigned Scale);
>> +  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
>> +  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
>> +  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
>> +  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
>> +                                SDValue &OffImm);
>> +  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
>> +                                 SDValue &OffImm);
>> +  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
>> +                                 SDValue &OffImm);
>> +  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
>> +                                 SDValue &OffImm);
>>  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
>> 
>> +  // Thumb 2 Addressing Modes:
>>  bool SelectT2ShifterOperandReg(SDValue N,
>>                                 SDValue &BaseReg, SDValue &Opc);
>>  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
>> @@ -872,9 +878,16 @@
>>                                       MVT::i32);
>>    return true;
>>  }
>> +
>>  return false;
>> }
>> 
>> +
>> +//===----------------------------------------------------------------------===//
>> +//                         Thumb Addressing Modes
>> +//===----------------------------------------------------------------------===//
>> +
>> +
>> bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
>>                                            SDValue &Base, SDValue &Offset){
>>  // FIXME dl should come from the parent load or store, not the address
>> @@ -893,13 +906,13 @@
>> }
>> 
>> bool
>> -ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
>> -                                        unsigned Scale, SDValue &Base,
>> -                                        SDValue &OffImm, SDValue &Offset) {
>> +ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
>> +                                       SDValue &Offset, unsigned Scale) {
>>  if (Scale == 4) {
>>    SDValue TmpBase, TmpOffImm;
>>    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>>      return false;  // We want to select tLDRspi / tSTRspi instead.
>> +
>>    if (N.getOpcode() == ARMISD::Wrapper &&
>>        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>>      return false;  // We want to select tLDRpci instead.
>> @@ -907,14 +920,13 @@
>> 
>>  if (N.getOpcode() != ISD::ADD) {
>>    if (N.getOpcode() == ARMISD::Wrapper &&
>> -        !(Subtarget->useMovt() &&
>> -          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
>> +        (!Subtarget->useMovt() ||
>> +         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
>>      Base = N.getOperand(0);
>> -    } else
>> +    else
>>      Base = N;
>> 
>>    Offset = CurDAG->getRegister(0, MVT::i32);
>> -    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>    return true;
>>  }
>> 
>> @@ -925,6 +937,68 @@
>>      (RHSR && RHSR->getReg() == ARM::SP)) {
>>    Base = N;
>>    Offset = CurDAG->getRegister(0, MVT::i32);
>> +    return true;
>> +  }
>> +
>> +  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>> +    int RHSC = (int)RHS->getZExtValue();
>> +
>> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>> +      RHSC /= Scale;
>> +
>> +      if (RHSC >= 0 && RHSC < 32)
>> +        return false;
>> +    }
>> +  }
>> +
>> +  Base = N.getOperand(0);
>> +  Offset = N.getOperand(1);
>> +  return true;
>> +}
>> +
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
>> +                                          SDValue &Base,
>> +                                          SDValue &Offset) {
>> +  return SelectThumbAddrModeRI(N, Base, Offset, 1);
>> +}
>> +
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
>> +                                          SDValue &Base,
>> +                                          SDValue &Offset) {
>> +  return SelectThumbAddrModeRI(N, Base, Offset, 2);
>> +}
>> +
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
>> +                                          SDValue &Base,
>> +                                          SDValue &Offset) {
>> +  return SelectThumbAddrModeRI(N, Base, Offset, 4);
>> +}
>> +
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
>> +                                          SDValue &Base, SDValue &OffImm) {
>> +  if (Scale == 4) {
>> +    SDValue TmpBase, TmpOffImm;
>> +    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>> +      return false;  // We want to select tLDRspi / tSTRspi instead.
>> +
>> +    if (N.getOpcode() == ARMISD::Wrapper &&
>> +        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>> +      return false;  // We want to select tLDRpci instead.
>> +  }
>> +
>> +  if (N.getOpcode() != ISD::ADD) {
>> +    if (N.getOpcode() == ARMISD::Wrapper &&
>> +        !(Subtarget->useMovt() &&
>> +          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
>> +      Base = N.getOperand(0);
>> +    } else {
>> +      Base = N;
>> +    }
>> +
>>    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>    return true;
>>  }
>> @@ -932,11 +1006,12 @@
>>  // If the RHS is + imm5 * scale, fold into addr mode.
>>  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>>    int RHSC = (int)RHS->getZExtValue();
>> -    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
>> +
>> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>>      RHSC /= Scale;
>> +
>>      if (RHSC >= 0 && RHSC < 32) {
>>        Base = N.getOperand(0);
>> -        Offset = CurDAG->getRegister(0, MVT::i32);
>>        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>>        return true;
>>      }
>> @@ -944,27 +1019,26 @@
>>  }
>> 
>>  Base = N.getOperand(0);
>> -  Offset = N.getOperand(1);
>>  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>  return true;
>> }
>> 
>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
>> -                                            SDValue &Base, SDValue &OffImm,
>> -                                            SDValue &Offset) {
>> -  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
>> -}
>> -
>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
>> -                                            SDValue &Base, SDValue &OffImm,
>> -                                            SDValue &Offset) {
>> -  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
>> -}
>> -
>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
>> -                                            SDValue &Base, SDValue &OffImm,
>> -                                            SDValue &Offset) {
>> -  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
>> +                                           SDValue &OffImm) {
>> +  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
>> +}
>> +
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
>> +                                           SDValue &OffImm) {
>> +  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
>> +}
>> +
>> +bool
>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
>> +                                           SDValue &OffImm) {
>> +  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
>> }
>> 
>> bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
>> @@ -1003,6 +1077,12 @@
>>  return false;
>> }
>> 
>> +
>> +//===----------------------------------------------------------------------===//
>> +//                        Thumb 2 Addressing Modes
>> +//===----------------------------------------------------------------------===//
>> +
>> +
>> bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
>>                                                SDValue &Opc) {
>>  if (DisableShifterOp)
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Dec 13 21:36:38 2010
>> @@ -94,8 +94,13 @@
>>  let EncoderMethod = "getThumbBLXTargetOpValue";
>> }
>> 
>> -def MemModeThumbAsmOperand : AsmOperandClass {
>> -  let Name = "MemModeThumb";
>> +def MemModeRegThumbAsmOperand : AsmOperandClass {
>> +  let Name = "MemModeRegThumb";
>> +  let SuperClasses = [];
>> +}
>> +
>> +def MemModeImmThumbAsmOperand : AsmOperandClass {
>> +  let Name = "MemModeImmThumb";
>>  let SuperClasses = [];
>> }
>> 
>> @@ -103,42 +108,64 @@
>> //
>> def t_addrmode_rr : Operand<i32>,
>>                    ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
>> -  let EncoderMethod = "getTAddrModeRegRegOpValue";
>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>> +  let PrintMethod = "printThumbAddrModeRROperand";
>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>> +}
>> +
>> +// t_addrmode_rrs := reg + reg
>> +//
>> +def t_addrmode_rrs1 : Operand<i32>,
>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>  let PrintMethod = "printThumbAddrModeRROperand";
>>  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>> }
>> 
>> -// t_addrmode_s4 := reg + reg
>> -//                  reg + imm5 * 4
>> +def t_addrmode_rrs2 : Operand<i32>,
>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>> +  let PrintMethod = "printThumbAddrModeRROperand";
>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>> +}
>> +def t_addrmode_rrs4 : Operand<i32>,
>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>> +  let PrintMethod = "printThumbAddrModeRROperand";
>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>> +}
>> +
>> +// t_addrmode_is4 := reg + imm5 * 4
>> //
>> -def t_addrmode_s4 : Operand<i32>,
>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
>> -  let EncoderMethod = "getAddrModeSOpValue";
>> -  let PrintMethod = "printThumbAddrModeS4Operand";
>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>> +def t_addrmode_is4 : Operand<i32>,
>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
>> +  let EncoderMethod = "getAddrModeISOpValue";
>> +  let PrintMethod = "printThumbAddrModeImm5S4Operand";
>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>> }
>> 
>> -// t_addrmode_s2 := reg + reg
>> -//                  reg + imm5 * 2
>> +// t_addrmode_is2 := reg + imm5 * 2
>> //
>> -def t_addrmode_s2 : Operand<i32>,
>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
>> -  let EncoderMethod = "getAddrModeSOpValue";
>> -  let PrintMethod = "printThumbAddrModeS2Operand";
>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>> +def t_addrmode_is2 : Operand<i32>,
>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
>> +  let EncoderMethod = "getAddrModeISOpValue";
>> +  let PrintMethod = "printThumbAddrModeImm5S2Operand";
>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>> }
>> 
>> -// t_addrmode_s1 := reg + reg
>> -//                  reg + imm5
>> +// t_addrmode_is1 := reg + imm5
>> //
>> -def t_addrmode_s1 : Operand<i32>,
>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
>> -  let EncoderMethod = "getAddrModeSOpValue";
>> -  let PrintMethod = "printThumbAddrModeS1Operand";
>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>> +def t_addrmode_is1 : Operand<i32>,
>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
>> +  let EncoderMethod = "getAddrModeISOpValue";
>> +  let PrintMethod = "printThumbAddrModeImm5S1Operand";
>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>> }
>> 
>> // t_addrmode_sp := sp + imm8 * 4
>> @@ -148,14 +175,14 @@
>>  let EncoderMethod = "getAddrModeThumbSPOpValue";
>>  let PrintMethod = "printThumbAddrModeSPOperand";
>>  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>> }
>> 
>> // t_addrmode_pc := <label> => pc + imm8 * 4
>> //
>> def t_addrmode_pc : Operand<i32> {
>>  let EncoderMethod = "getAddrModePCOpValue";
>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>> }
>> 
>> //===----------------------------------------------------------------------===//
>> @@ -580,41 +607,41 @@
>> //
>> 
>> let canFoldAsLoad = 1, isReMaterializable = 1 in
>> -def tLDR :                      // A8.6.60
>> -  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
>> +def tLDRr :                      // A8.6.60
>> +  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
>>                 AddrModeT1_4, IIC_iLoad_r,
>>                 "ldr", "\t$Rt, $addr",
>> -                 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
>> +                 [(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
>> 
>> def tLDRi :                     // A8.6.57
>> -  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
>> +  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
>>                    AddrModeT1_4, IIC_iLoad_r,
>>                    "ldr", "\t$Rt, $addr",
>> -                    []>;
>> +                    [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
>> 
>> -def tLDRB :                     // A8.6.64
>> -  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
>> +def tLDRBr :                    // A8.6.64
>> +  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
>>                 AddrModeT1_1, IIC_iLoad_bh_r,
>>                 "ldrb", "\t$Rt, $addr",
>> -                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
>> +                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
>> 
>> def tLDRBi :                    // A8.6.61
>> -  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
>> +  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
>>                    AddrModeT1_1, IIC_iLoad_bh_r,
>>                    "ldrb", "\t$Rt, $addr",
>> -                    []>;
>> +                    [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
>> 
>> -def tLDRH :                     // A8.6.76
>> -  T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
>> +def tLDRHr :                    // A8.6.76
>> +  T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
>>                 AddrModeT1_2, IIC_iLoad_bh_r,
>> -                 "ldrh", "\t$dst, $addr",
>> -                 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
>> +                 "ldrh", "\t$Rt, $addr",
>> +                 [(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
>> 
>> def tLDRHi :                    // A8.6.73
>> -  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
>> +  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
>>                    AddrModeT1_2, IIC_iLoad_bh_r,
>>                    "ldrh", "\t$Rt, $addr",
>> -                    []>;
>> +                    [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
>> 
>> let AddedComplexity = 10 in
>> def tLDRSB :                    // A8.6.80
>> @@ -676,45 +703,45 @@
>>  let Inst{7-0}  = addr;
>> }
>> 
>> -def tSTR :                      // A8.6.194
>> -  T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
>> +def tSTRr :                     // A8.6.194
>> +  T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
>>                 AddrModeT1_4, IIC_iStore_r,
>> -                 "str", "\t$src, $addr",
>> -                 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
>> +                 "str", "\t$Rt, $addr",
>> +                 [(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
>> 
>> def tSTRi :                     // A8.6.192
>> -  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
>> +  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
>>                    AddrModeT1_4, IIC_iStore_r,
>>                    "str", "\t$Rt, $addr",
>> -                    []>;
>> +                    [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
>> 
>> -def tSTRB :                     // A8.6.197
>> -  T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
>> +def tSTRBr :                    // A8.6.197
>> +  T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
>>                 AddrModeT1_1, IIC_iStore_bh_r,
>> -                 "strb", "\t$src, $addr",
>> -                 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
>> +                 "strb", "\t$Rt, $addr",
>> +                 [(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
>> 
>> def tSTRBi :                    // A8.6.195
>> -  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
>> +  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
>>                    AddrModeT1_1, IIC_iStore_bh_r,
>>                    "strb", "\t$Rt, $addr",
>> -                    []>;
>> +                    [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
>> 
>> -def tSTRH :                     // A8.6.207
>> -  T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
>> +def tSTRHr :                    // A8.6.207
>> +  T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
>>                 AddrModeT1_2, IIC_iStore_bh_r,
>> -                 "strh", "\t$src, $addr",
>> -                 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
>> +                 "strh", "\t$Rt, $addr",
>> +                 [(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
>> 
>> def tSTRHi :                    // A8.6.205
>> -  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
>> +  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
>>                    AddrModeT1_2, IIC_iStore_bh_r,
>>                    "strh", "\t$Rt, $addr",
>> -                    []>;
>> +                    [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
>> 
>> def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
>> -                   "str", "\t$Rt, $addr",
>> -                   [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>> +                    "str", "\t$Rt, $addr",
>> +                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>>              T1LdStSP<{0,?,?}> {
>>  bits<3> Rt;
>>  bits<8> addr;
>> @@ -1390,27 +1417,32 @@
>>      Requires<[IsThumb, HasV5T, IsDarwin]>;
>> 
>> // zextload i1 -> zextload i8
>> -def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
>> -            (tLDRB t_addrmode_s1:$addr)>;
>> +def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
>> +            (tLDRBr t_addrmode_rrs1:$addr)>;
>> +def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
>> +            (tLDRBi t_addrmode_is1:$addr)>;
>> 
>> // extload -> zextload
>> -def : T1Pat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
>> -def : T1Pat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
>> -def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
>> +def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
>> +def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
>> +def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
>> +def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
>> +def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
>> +def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
>> 
>> // If it's impossible to use [r,r] address mode for sextload, select to
>> // ldr{b|h} + sxt{b|h} instead.
>> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
>> -            (tSXTB (tLDRB t_addrmode_s1:$addr))>,
>> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
>> +            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
>>      Requires<[IsThumb, IsThumb1Only, HasV6]>;
>> -def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
>> -            (tSXTH (tLDRH t_addrmode_s2:$addr))>,
>> +def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
>> +            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
>>      Requires<[IsThumb, IsThumb1Only, HasV6]>;
>> 
>> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
>> -            (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
>> -def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
>> -            (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
>> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
>> +            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
>> +def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr),
>> +            (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>;
>> 
>> // Large immediate handling.
>> 
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 21:36:38 2010
>> @@ -144,9 +144,9 @@
>>  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
>>                                   SmallVectorImpl<MCFixup> &Fixups) const;
>> 
>> -  /// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
>> -  uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>> -                                     SmallVectorImpl<MCFixup> &Fixups) const;
>> +  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
>> +  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>> +                                         SmallVectorImpl<MCFixup> &Fixups)const;
>> 
>>  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
>>  /// operand.
>> @@ -207,9 +207,9 @@
>>  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
>>                                     SmallVectorImpl<MCFixup> &Fixups) const;
>> 
>> -  /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
>> -  uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
>> -                               SmallVectorImpl<MCFixup> &) const;
>> +  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
>> +  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
>> +                                SmallVectorImpl<MCFixup> &) const;
>> 
>>  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
>>  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
>> @@ -559,12 +559,16 @@
>>                                  Fixups);
>> }
>> 
>> -/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
>> +/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
>> +/// operand.
>> uint32_t ARMMCCodeEmitter::
>> -getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>> -                        SmallVectorImpl<MCFixup> &Fixups) const {
>> +getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>> +                              SmallVectorImpl<MCFixup> &) const {
>> +  // [Rn, Rm]
>> +  //   {5-3} = Rm
>> +  //   {2-0} = Rn
>>  const MCOperand &MO1 = MI.getOperand(OpIdx);
>> -  const MCOperand &MO2 = MI.getOperand(OpIdx+1);
>> +  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
>>  unsigned Rn = getARMRegisterNumbering(MO1.getReg());
>>  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
>>  return (Rm << 3) | Rn;
>> @@ -796,27 +800,17 @@
>>  return MO1.getImm() & 0xff;
>> }
>> 
>> -/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
>> +/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
>> uint32_t ARMMCCodeEmitter::
>> -getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
>> -                    SmallVectorImpl<MCFixup> &) const {
>> -  // [Rn, Rm]
>> -  //   {5-3} = Rm
>> -  //   {2-0} = Rn
>> -  //
>> +getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
>> +                     SmallVectorImpl<MCFixup> &) const {
>>  // [Rn, #imm]
>>  //   {7-3} = imm5
>>  //   {2-0} = Rn
>>  const MCOperand &MO = MI.getOperand(OpIdx);
>>  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
>> -  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
>>  unsigned Rn = getARMRegisterNumbering(MO.getReg());
>>  unsigned Imm5 = MO1.getImm();
>> -
>> -  if (MO2.getReg() != 0)
>> -    // Is an immediate.
>> -    Imm5 = getARMRegisterNumbering(MO2.getReg());
>> -
>>  return ((Imm5 & 0x1f) << 3) | Rn;
>> }
>> 
>> 
>> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 13 21:36:38 2010
>> @@ -236,11 +236,16 @@
>>    int64_t Value = CE->getValue();
>>    return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
>>  }
>> -  bool isMemModeThumb() const {
>> +  bool isMemModeRegThumb() const {
>> +    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>> +      return false;
>> +    return !Mem.Offset || !isa<MCConstantExpr>(Mem.Offset);
>> +  }
>> +  bool isMemModeImmThumb() const {
>>    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>>      return false;
>> 
>> -    if (!Mem.Offset) return true;
>> +    if (!Mem.Offset) return false;
>> 
>>    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>    if (!CE) return false;
>> @@ -324,19 +329,18 @@
>>    }
>>  }
>> 
>> -  void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
>> -    assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
>> +  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
>> +    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
>>    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
>> +    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
>> +  }
>> 
>> -    if (Mem.Offset) {
>> -      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>> -      assert(CE && "Non-constant mode offset operand!");
>> -      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>> -      Inst.addOperand(MCOperand::CreateReg(0));
>> -    } else {
>> -      Inst.addOperand(MCOperand::CreateImm(0));
>> -      Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
>> -    }
>> +  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
>> +    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
>> +    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
>> +    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>> +    assert(CE && "Non-constant mode offset operand!");
>> +    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>>  }
>> 
>>  virtual void dump(raw_ostream &OS) const;
>> 
>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Dec 13 21:36:38 2010
>> @@ -482,17 +482,25 @@
>> void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
>>                                                 raw_ostream &O) {
>>  const MCOperand &MO1 = MI->getOperand(Op);
>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
>> +
>> +  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>> +    printOperand(MI, Op, O);
>> +    return;
>> +  }
>> +
>>  O << "[" << getRegisterName(MO1.getReg());
>> -  O << ", " << getRegisterName(MO2.getReg()) << "]";
>> +  if (unsigned RegNum = MO2.getReg())
>> +    O << ", " << getRegisterName(RegNum);
>> +  O << "]";
>> }
>> 
>> -void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
>> -                                                  raw_ostream &O,
>> -                                                  unsigned Scale) {
>> +void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
>> +                                                    unsigned Op,
>> +                                                    raw_ostream &O,
>> +                                                    unsigned Scale) {
>>  const MCOperand &MO1 = MI->getOperand(Op);
>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>> -  const MCOperand &MO3 = MI->getOperand(Op+2);
>> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
>> 
>>  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>>    printOperand(MI, Op, O);
>> @@ -500,36 +508,32 @@
>>  }
>> 
>>  O << "[" << getRegisterName(MO1.getReg());
>> -  if (MO3.getReg())
>> -    O << ", " << getRegisterName(MO3.getReg());
>> -  else if (unsigned ImmOffs = MO2.getImm())
>> +  if (unsigned ImmOffs = MO2.getImm())
>>    O << ", #" << ImmOffs * Scale;
>>  O << "]";
>> }
>> 
>> -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
>> -                                                 raw_ostream &O) {
>> -  printThumbAddrModeRI5Operand(MI, Op, O, 1);
>> -}
>> -
>> -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
>> -                                                 raw_ostream &O) {
>> -  printThumbAddrModeRI5Operand(MI, Op, O, 2);
>> -}
>> -
>> -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
>> -                                                 raw_ostream &O) {
>> -  printThumbAddrModeRI5Operand(MI, Op, O, 4);
>> +void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
>> +                                                     unsigned Op,
>> +                                                     raw_ostream &O) {
>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
>> +}
>> +
>> +void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
>> +                                                     unsigned Op,
>> +                                                     raw_ostream &O) {
>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
>> +}
>> +
>> +void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
>> +                                                     unsigned Op,
>> +                                                     raw_ostream &O) {
>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
>> }
>> 
>> void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
>>                                                 raw_ostream &O) {
>> -  const MCOperand &MO1 = MI->getOperand(Op);
>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>> -  O << "[" << getRegisterName(MO1.getReg());
>> -  if (unsigned ImmOffs = MO2.getImm())
>> -    O << ", #" << ImmOffs*4;
>> -  O << "]";
>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
>> }
>> 
>> // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
>> 
>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Dec 13 21:36:38 2010
>> @@ -59,14 +59,14 @@
>>  void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
>>  void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
>>                                   raw_ostream &O);
>> -  void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,
>> -                                    raw_ostream &O, unsigned Scale);
>> -  void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum,
>> -                                   raw_ostream &O);
>> -  void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum,
>> -                                   raw_ostream &O);
>> -  void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum,
>> -                                   raw_ostream &O);
>> +  void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
>> +                                      raw_ostream &O, unsigned Scale);
>> +  void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
>> +                                       raw_ostream &O);
>> +  void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
>> +                                       raw_ostream &O);
>> +  void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
>> +                                       raw_ostream &O);
>>  void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
>>                                   raw_ostream &O);
>> 
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Dec 13 21:36:38 2010
>> @@ -644,13 +644,11 @@
>>                                *this, dl);
>>    }
>> 
>> -    MI.setDesc(TII.get(ARM::tLDR));
>> +    MI.setDesc(TII.get(ARM::tLDRr));
>>    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
>>    if (UseRR)
>>      // Use [reg, reg] addrmode.
>>      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>> -    else  // tLDR has an extra register operand.
>> -      MI.addOperand(MachineOperand::CreateReg(0, false));
>>  } else if (Desc.mayStore()) {
>>      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
>>      bool UseRR = false;
>> @@ -666,14 +664,13 @@
>>      } else
>>        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
>>                                  *this, dl);
>> -      MI.setDesc(TII.get(ARM::tSTR));
>> +      MI.setDesc(TII.get(ARM::tSTRr));
>>      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
>>      if (UseRR)  // Use [reg, reg] addrmode.
>>        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>> -      else // tSTR has an extra register operand.
>> -        MI.addOperand(MachineOperand::CreateReg(0, false));
>> -  } else
>> +  } else {
>>    assert(false && "Unexpected opcode!");
>> +  }
>> 
>>  // Add predicate back if it's needed.
>>  if (MI.getDesc().isPredicable()) {
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Mon Dec 13 21:36:38 2010
>> @@ -105,19 +105,19 @@
>>    // FIXME: Clean this up after splitting each Thumb load / store opcode
>>    // into multiple ones.
>>    { ARM::t2LDRi12,ARM::tLDRi,   ARM::tLDRspi,  5,   8,    1,   0,  0,0, 1 },
>> -    { ARM::t2LDRs,  ARM::tLDR,    0,             0,   0,    1,   0,  0,0, 1 },
>> +    { ARM::t2LDRs,  ARM::tLDRr,   0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2LDRBi12,ARM::tLDRBi, 0,             5,   0,    1,   0,  0,0, 1 },
>> -    { ARM::t2LDRBs, ARM::tLDRB,   0,             0,   0,    1,   0,  0,0, 1 },
>> +    { ARM::t2LDRBs, ARM::tLDRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2LDRHi12,ARM::tLDRHi, 0,             5,   0,    1,   0,  0,0, 1 },
>> -    { ARM::t2LDRHs, ARM::tLDRH,   0,             0,   0,    1,   0,  0,0, 1 },
>> +    { ARM::t2LDRHs, ARM::tLDRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2LDRSBs,ARM::tLDRSB,  0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2LDRSHs,ARM::tLDRSH,  0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2STRi12,ARM::tSTRi,   ARM::tSTRspi,  5,   8,    1,   0,  0,0, 1 },
>> -    { ARM::t2STRs,  ARM::tSTR,    0,             0,   0,    1,   0,  0,0, 1 },
>> +    { ARM::t2STRs,  ARM::tSTRr,   0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2STRBi12,ARM::tSTRBi, 0,             5,   0,    1,   0,  0,0, 1 },
>> -    { ARM::t2STRBs, ARM::tSTRB,   0,             0,   0,    1,   0,  0,0, 1 },
>> +    { ARM::t2STRBs, ARM::tSTRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>>    { ARM::t2STRHi12,ARM::tSTRHi, 0,             5,   0,    1,   0,  0,0, 1 },
>> -    { ARM::t2STRHs, ARM::tSTRH,   0,             0,   0,    1,   0,  0,0, 1 },
>> +    { ARM::t2STRHs, ARM::tSTRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>> 
>>    { ARM::t2LDMIA, ARM::tLDMIA,  0,             0,   0,    1,   1,  1,1, 1 },
>>    { ARM::t2LDMIA_RET,0,         ARM::tPOP_RET, 0,   0,    1,   1,  1,1, 1 },
>> @@ -273,7 +273,6 @@
>>  bool HasShift = false;
>>  bool HasOffReg = true;
>>  bool isLdStMul = false;
>> -  bool InsertImmOffset = true;
>>  unsigned Opc = Entry.NarrowOpc1;
>>  unsigned OpNum = 3; // First 'rest' of operands.
>>  uint8_t  ImmLimit = Entry.Imm1Limit;
>> @@ -282,39 +281,41 @@
>>  default:
>>    llvm_unreachable("Unexpected Thumb2 load / store opcode!");
>>  case ARM::t2LDRi12:
>> -  case ARM::t2STRi12: {
>> -    unsigned BaseReg = MI->getOperand(1).getReg();
>> -    if (BaseReg == ARM::SP) {
>> +  case ARM::t2STRi12:
>> +    if (MI->getOperand(1).getReg() == ARM::SP) {
>>      Opc = Entry.NarrowOpc2;
>>      ImmLimit = Entry.Imm2Limit;
>>      HasOffReg = false;
>>    }
>> +
>>    Scale = 4;
>> -    if (MI->getOperand(2).isImm())
>> +
>> +    if (MI->getOperand(2).isImm()) {
>>      HasImmOffset = true;
>> -    else {
>> +      HasOffReg = false;
>> +    } else {
>>      if (Entry.WideOpc == ARM::t2LDRi12) {
>>        Opc = ARM::tLDRpci;
>>        OpNum = 2;
>>      }
>> +
>>      HasImmOffset = false;
>> -      InsertImmOffset = false;
>>      HasBaseReg = false;
>>      HasOffReg = false;
>>    }
>>    break;
>> -  }
>>  case ARM::t2LDRBi12:
>>  case ARM::t2STRBi12:
>> -    if (MI->getOperand(2).isImm())
>> +    if (MI->getOperand(2).isImm()) {
>>      HasImmOffset = true;
>> -    else {
>> +      HasOffReg = false;
>> +    } else {
>>      if (Entry.WideOpc == ARM::t2LDRBi12) {
>>        Opc = ARM::tLDRpci;
>>        OpNum = 2;
>>      }
>> +
>>      HasImmOffset = false;
>> -      InsertImmOffset = false;
>>      HasBaseReg = false;
>>      HasOffReg = false;
>>    }
>> @@ -322,15 +323,16 @@
>>  case ARM::t2LDRHi12:
>>  case ARM::t2STRHi12:
>>    Scale = 2;
>> -    if (MI->getOperand(2).isImm())
>> +    if (MI->getOperand(2).isImm()) {
>>      HasImmOffset = true;
>> -    else {
>> +      HasOffReg = false;
>> +    } else {
>>      if (Entry.WideOpc == ARM::t2LDRHi12) {
>>        Opc = ARM::tLDRpci;
>>        OpNum = 2;
>>      }
>> +
>>      HasImmOffset = false;
>> -      InsertImmOffset = false;
>>      HasBaseReg = false;
>>      HasOffReg = false;
>>    }
>> @@ -351,6 +353,7 @@
>>    unsigned BaseReg = MI->getOperand(0).getReg();
>>    if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
>>      return false;
>> +
>>    // For the non-writeback version (this one), the base register must be
>>    // one of the registers being loaded.
>>    bool isOK = false;
>> @@ -360,6 +363,7 @@
>>        break;
>>      }
>>    }
>> +
>>    if (!isOK)
>>      return false;
>> 
>> @@ -381,6 +385,7 @@
>>  case ARM::t2STMIA_UPD:
>>  case ARM::t2STMDB_UPD: {
>>    OpNum = 0;
>> +
>>    unsigned BaseReg = MI->getOperand(1).getReg();
>>    if (BaseReg == ARM::SP &&
>>        (Entry.WideOpc == ARM::t2LDMIA_UPD ||
>> @@ -392,6 +397,7 @@
>>                Entry.WideOpc != ARM::t2STMIA_UPD)) {
>>      return false;
>>    }
>> +
>>    isLdStMul = true;
>>    break;
>>  }
>> @@ -402,6 +408,7 @@
>>  if (HasShift) {
>>    OffsetReg  = MI->getOperand(2).getReg();
>>    OffsetKill = MI->getOperand(2).isKill();
>> +
>>    if (MI->getOperand(3).getImm())
>>      // Thumb1 addressing mode doesn't support shift.
>>      return false;
>> @@ -411,24 +418,24 @@
>>  if (HasImmOffset) {
>>    OffsetImm = MI->getOperand(2).getImm();
>>    unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
>> -    if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
>> +
>> +    if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
>>      // Make sure the immediate field fits.
>>      return false;
>>  }
>> 
>>  // Add the 16-bit load / store instruction.
>> -  // FIXME: Thumb1 addressing mode encode both immediate and register offset.
>>  DebugLoc dl = MI->getDebugLoc();
>>  MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
>>  if (!isLdStMul) {
>>    MIB.addOperand(MI->getOperand(0));
>> -    if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
>> -    if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
>> -      // tLDRSB and tLDRSH do not have an immediate offset field. On the other
>> -      // hand, it must have an offset register.
>> -      // FIXME: Remove this special case.
>> -      MIB.addImm(OffsetImm/Scale);
>> -    }
>> +
>> +    if (HasBaseReg)
>> +      MIB.addOperand(MI->getOperand(1));
>> +
>> +    if (HasImmOffset)
>> +      MIB.addImm(OffsetImm / Scale);
>> +
>>    assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
>> 
>>    if (HasOffReg)
>> 
>> Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>> ==============================================================================
>> --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
>> +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 21:36:38 2010
>> @@ -629,9 +629,12 @@
>>  MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
>>                                                                  // R, I
>>  MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
>> -  MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1");           // R, I, R
>> -  MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2");           // R, I, R
>> -  MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4");           // R, I, R
>> +  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
>> +  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
>> +  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
>> +  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
>> +  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
>> +  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
>>  MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
>>  MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
>>  MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
>> @@ -841,9 +844,8 @@
>>  operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
>>  operandTypes.addEntry("kOperandTypeARMTBAddrMode");
>>  operandTypes.addEntry("kOperandTypeThumbITMask");
>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
>> +  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
>> +  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
>>  operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
>>  operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
>>  operandTypes.addEntry("kOperandTypeThumbAddrModePC");
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 



From fvbommel at gmail.com  Tue Dec 14 06:08:00 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Tue, 14 Dec 2010 13:08:00 +0100
Subject: [llvm-commits] [Review request] Jump threading and 'select'.
In-Reply-To: <AANLkTi=JO+ZgMAaz8w17qPwsO4MOC_xSPc0KwpsEG6Nf@mail.gmail.com>
References: <AANLkTi=JO+ZgMAaz8w17qPwsO4MOC_xSPc0KwpsEG6Nf@mail.gmail.com>
Message-ID: <AANLkTinwRKP6j9RD10oYAGPOzPr1nLURdKfk2PsWrrRY@mail.gmail.com>

On Thu, Dec 9, 2010 at 6:46 PM, Frits van Bommel <fvbommel at gmail.com> wrote:
> The attached patch teaches jump threading to "look through" a select
> when the branch direction of a branch/switch/indirect depends on it.
> The new code tries to figure out whether the condition of the select
> is known in any of the predecessors and if so maps the operands
> appropriately.

Ping?

From isanbard at gmail.com  Tue Dec 14 06:33:05 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 12:33:05 -0000
Subject: [llvm-commits] [llvm] r121765 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20101214123305.806082A6C12D@llvm.org>

Author: void
Date: Tue Dec 14 06:33:05 2010
New Revision: 121765

URL: http://llvm.org/viewvc/llvm-project?rev=121765&view=rev
Log:
Use the integer scheduling intrinsic for integer loads and stores.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121765&r1=121764&r2=121765&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 14 06:33:05 2010
@@ -615,7 +615,7 @@
 
 def tLDRi :                     // A8.6.57
   T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
-                    AddrModeT1_4, IIC_iLoad_r,
+                    AddrModeT1_4, IIC_iLoad_i,
                     "ldr", "\t$Rt, $addr",
                     [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
 
@@ -627,7 +627,7 @@
 
 def tLDRBi :                    // A8.6.61
   T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
-                    AddrModeT1_1, IIC_iLoad_bh_r,
+                    AddrModeT1_1, IIC_iLoad_bh_i,
                     "ldrb", "\t$Rt, $addr",
                     [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
 
@@ -639,7 +639,7 @@
 
 def tLDRHi :                    // A8.6.73
   T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
-                    AddrModeT1_2, IIC_iLoad_bh_r,
+                    AddrModeT1_2, IIC_iLoad_bh_i,
                     "ldrh", "\t$Rt, $addr",
                     [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
 
@@ -711,7 +711,7 @@
 
 def tSTRi :                     // A8.6.192
   T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
-                    AddrModeT1_4, IIC_iStore_r,
+                    AddrModeT1_4, IIC_iStore_i,
                     "str", "\t$Rt, $addr",
                     [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
 
@@ -723,7 +723,7 @@
 
 def tSTRBi :                    // A8.6.195
   T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
-                    AddrModeT1_1, IIC_iStore_bh_r,
+                    AddrModeT1_1, IIC_iStore_bh_i,
                     "strb", "\t$Rt, $addr",
                     [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
 
@@ -735,7 +735,7 @@
 
 def tSTRHi :                    // A8.6.205
   T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
-                    AddrModeT1_2, IIC_iStore_bh_r,
+                    AddrModeT1_2, IIC_iStore_bh_i,
                     "strh", "\t$Rt, $addr",
                     [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
 



From daniel at zuster.org  Tue Dec 14 08:25:17 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 14 Dec 2010 14:25:17 -0000
Subject: [llvm-commits] [zorg] r121766 -
	/zorg/trunk/lnt/lnt/viewer/GraphUtil.py
Message-ID: <20101214142517.EDE522A6C12D@llvm.org>

Author: ddunbar
Date: Tue Dec 14 08:25:17 2010
New Revision: 121766

URL: http://llvm.org/viewvc/llvm-project?rev=121766&view=rev
Log:
LNT: Protect against ZeroDivisionError in external.stats.linregress.

Modified:
    zorg/trunk/lnt/lnt/viewer/GraphUtil.py

Modified: zorg/trunk/lnt/lnt/viewer/GraphUtil.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/GraphUtil.py?rev=121766&r1=121765&r2=121766&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/viewer/GraphUtil.py (original)
+++ zorg/trunk/lnt/lnt/viewer/GraphUtil.py Tue Dec 14 08:25:17 2010
@@ -87,16 +87,24 @@
             x_min, x_max = min(xs), max(xs)
             norm_xs = [(x - x_min) / (x_max - x_min)
                        for x in xs]
-            slope, intercept,_,_,_ = ext_stats.linregress(norm_xs, ys)
 
-            reglin_col = [c*.5 for c in col]
-            pts = ','.join('[%.4f,%.4f]' % pt
-                           for pt in [(x_min, 0.0 * slope + intercept),
-                                      (x_max, 1.0 * slope + intercept)])
-            style = "new Graph2D_LinePlotStyle(4, %r)" % ([.7, .7, .7],)
-            plot_js += "    graph.addPlot([%s], %s);\n" % (pts,style)
-            style = "new Graph2D_LinePlotStyle(2, %r)" % (reglin_col,)
-            plot_js += "    graph.addPlot([%s], %s);\n" % (pts,style)
+            # FIXME: When can this raise ZeroDivisionError?
+            try:
+                info = ext_stats.linregress(norm_xs, ys)
+            except ZeroDivisionError:
+                info = None
+
+            if info is not None:
+                slope, intercept,_,_,_ = info
+
+                reglin_col = [c*.5 for c in col]
+                pts = ','.join('[%.4f,%.4f]' % pt
+                               for pt in [(x_min, 0.0 * slope + intercept),
+                                          (x_max, 1.0 * slope + intercept)])
+                style = "new Graph2D_LinePlotStyle(4, %r)" % ([.7, .7, .7],)
+                plot_js += "    graph.addPlot([%s], %s);\n" % (pts,style)
+                style = "new Graph2D_LinePlotStyle(2, %r)" % (reglin_col,)
+                plot_js += "    graph.addPlot([%s], %s);\n" % (pts,style)
 
         pts = ','.join(['[%.4f,%.4f]' % (t,v)
                         for t,v in data])



From grosbach at apple.com  Tue Dec 14 10:15:51 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 08:15:51 -0800
Subject: [llvm-commits] [llvm] r121747 - in /llvm/trunk:
	lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMCodeEmitter.cpp
	lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrThumb.td
	lib/Target/ARM/ARMMCCodeEmitter.cpp	lib/Target/ARM/AsmParser/ARMAsmParser.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.h
	lib/Target/ARM/Thumb1RegisterInfo.cpp	lib/Target/ARM/Thumb2SizeReduction.cpp
	utils/TableGen/EDEmitter.cpp
In-Reply-To: <4BE9BD84-20DE-4612-A959-5F6F02454021@gmail.com>
References: <20101214033639.1C4662A6C12C@llvm.org>
	<D060E5D8-3663-43A3-9EDF-4689B028A929@apple.com>
	<4BE9BD84-20DE-4612-A959-5F6F02454021@gmail.com>
Message-ID: <97B7F26B-6098-494F-ADBA-3034DCEE883D@apple.com>

That would be awesome. Let's talk a bit tomorrow and I'll give you the run-down on the current state of things and what's involved (there's a few more quirks in ARM mode for various reasons).

-Jim

On Dec 14, 2010, at 3:36 AM, Bill Wendling wrote:

> I can do that (or at least continue it) as part of the cleanup I need to do because of this patch.
> 
> -bw
> 
> On Dec 13, 2010, at 10:53 PM, Evan Cheng wrote:
> 
>> Thanks. It would be nice if we could completely split out loads / stores for ARM as well. Jim started on it but he ran out of time.
>> 
>> Evan
>> 
>> On Dec 13, 2010, at 7:36 PM, Bill Wendling wrote:
>> 
>>> Author: void
>>> Date: Mon Dec 13 21:36:38 2010
>>> New Revision: 121747
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=121747&view=rev
>>> Log:
>>> The tLDR et al instructions were emitting either a reg/reg or reg/imm
>>> instruction based on the t_addrmode_s# mode and what it returned. There is some
>>> obvious badness to this. In particular, it's hard to do MC-encoding when the
>>> instruction may change out from underneath you after the t_addrmode_s# variable
>>> is finally resolved.
>>> 
>>> The solution is to revert a long-ago change that merged the reg/reg and reg/imm
>>> versions. There is the addition of several new addressing modes. They no longer
>>> have extraneous operands associated with them. I.e., if it's reg/reg we don't
>>> have to have a dummy zero immediate tacked on to the SDNode.
>>> 
>>> There are some obvious cleanups here, which will happen shortly.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>>  llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>>>  llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>>  llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>>>  llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>>>  llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>>  llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>>>  llvm/trunk/utils/TableGen/EDEmitter.cpp
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -1129,13 +1129,12 @@
>>>   }
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tSTR);
>>> +      TmpInst.setOpcode(ARM::tSTRi);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ValReg));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>>     // The offset immediate is #4. The operand value is scaled by 4 for the
>>>     // tSTR instruction.
>>>     TmpInst.addOperand(MCOperand::CreateImm(1));
>>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>> @@ -1312,13 +1311,12 @@
>>>   unsigned ScratchReg = MI->getOperand(1).getReg();
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tLDR);
>>> +      TmpInst.setOpcode(ARM::tLDRi);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>>     // The offset immediate is #8. The operand value is scaled by 4 for the
>>> -      // tSTR instruction.
>>> +      // tLDR instruction.
>>>     TmpInst.addOperand(MCOperand::CreateImm(2));
>>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>> @@ -1336,11 +1334,10 @@
>>>   }
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tLDR);
>>> +      TmpInst.setOpcode(ARM::tLDRi);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>>     TmpInst.addOperand(MCOperand::CreateImm(1));
>>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>> @@ -1348,10 +1345,9 @@
>>>   }
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tLDR);
>>> +      TmpInst.setOpcode(ARM::tLDRr);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>> -      TmpInst.addOperand(MCOperand::CreateImm(0));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -193,7 +193,7 @@
>>>     const { return 0; }
>>>   unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>> -    unsigned getTAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>>> +    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>>   unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>> @@ -265,6 +265,8 @@
>>>     const { return 0; }
>>>   uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>> +    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
>>> +      const { return 0; }
>>>   uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>>   uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Dec 13 21:36:38 2010
>>> @@ -130,18 +130,24 @@
>>> bool SelectAddrModePC(SDValue N, SDValue &Offset,
>>>                       SDValue &Label);
>>> 
>>> +  // Thumb Addressing Modes:
>>> bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
>>> -  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
>>> -                              SDValue &Base, SDValue &OffImm,
>>> -                              SDValue &Offset);
>>> -  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
>>> -                             SDValue &OffImm, SDValue &Offset);
>>> -  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
>>> -                             SDValue &OffImm, SDValue &Offset);
>>> -  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
>>> -                             SDValue &OffImm, SDValue &Offset);
>>> +  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
>>> +                             unsigned Scale);
>>> +  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
>>> +  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
>>> +  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
>>> +  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
>>> +                                SDValue &OffImm);
>>> +  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
>>> +                                 SDValue &OffImm);
>>> +  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
>>> +                                 SDValue &OffImm);
>>> +  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
>>> +                                 SDValue &OffImm);
>>> bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
>>> 
>>> +  // Thumb 2 Addressing Modes:
>>> bool SelectT2ShifterOperandReg(SDValue N,
>>>                                SDValue &BaseReg, SDValue &Opc);
>>> bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
>>> @@ -872,9 +878,16 @@
>>>                                      MVT::i32);
>>>   return true;
>>> }
>>> +
>>> return false;
>>> }
>>> 
>>> +
>>> +//===----------------------------------------------------------------------===//
>>> +//                         Thumb Addressing Modes
>>> +//===----------------------------------------------------------------------===//
>>> +
>>> +
>>> bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
>>>                                           SDValue &Base, SDValue &Offset){
>>> // FIXME dl should come from the parent load or store, not the address
>>> @@ -893,13 +906,13 @@
>>> }
>>> 
>>> bool
>>> -ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
>>> -                                        unsigned Scale, SDValue &Base,
>>> -                                        SDValue &OffImm, SDValue &Offset) {
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
>>> +                                       SDValue &Offset, unsigned Scale) {
>>> if (Scale == 4) {
>>>   SDValue TmpBase, TmpOffImm;
>>>   if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>>>     return false;  // We want to select tLDRspi / tSTRspi instead.
>>> +
>>>   if (N.getOpcode() == ARMISD::Wrapper &&
>>>       N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>>>     return false;  // We want to select tLDRpci instead.
>>> @@ -907,14 +920,13 @@
>>> 
>>> if (N.getOpcode() != ISD::ADD) {
>>>   if (N.getOpcode() == ARMISD::Wrapper &&
>>> -        !(Subtarget->useMovt() &&
>>> -          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
>>> +        (!Subtarget->useMovt() ||
>>> +         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
>>>     Base = N.getOperand(0);
>>> -    } else
>>> +    else
>>>     Base = N;
>>> 
>>>   Offset = CurDAG->getRegister(0, MVT::i32);
>>> -    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>>   return true;
>>> }
>>> 
>>> @@ -925,6 +937,68 @@
>>>     (RHSR && RHSR->getReg() == ARM::SP)) {
>>>   Base = N;
>>>   Offset = CurDAG->getRegister(0, MVT::i32);
>>> +    return true;
>>> +  }
>>> +
>>> +  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>>> +    int RHSC = (int)RHS->getZExtValue();
>>> +
>>> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>>> +      RHSC /= Scale;
>>> +
>>> +      if (RHSC >= 0 && RHSC < 32)
>>> +        return false;
>>> +    }
>>> +  }
>>> +
>>> +  Base = N.getOperand(0);
>>> +  Offset = N.getOperand(1);
>>> +  return true;
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
>>> +                                          SDValue &Base,
>>> +                                          SDValue &Offset) {
>>> +  return SelectThumbAddrModeRI(N, Base, Offset, 1);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
>>> +                                          SDValue &Base,
>>> +                                          SDValue &Offset) {
>>> +  return SelectThumbAddrModeRI(N, Base, Offset, 2);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
>>> +                                          SDValue &Base,
>>> +                                          SDValue &Offset) {
>>> +  return SelectThumbAddrModeRI(N, Base, Offset, 4);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
>>> +                                          SDValue &Base, SDValue &OffImm) {
>>> +  if (Scale == 4) {
>>> +    SDValue TmpBase, TmpOffImm;
>>> +    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>>> +      return false;  // We want to select tLDRspi / tSTRspi instead.
>>> +
>>> +    if (N.getOpcode() == ARMISD::Wrapper &&
>>> +        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>>> +      return false;  // We want to select tLDRpci instead.
>>> +  }
>>> +
>>> +  if (N.getOpcode() != ISD::ADD) {
>>> +    if (N.getOpcode() == ARMISD::Wrapper &&
>>> +        !(Subtarget->useMovt() &&
>>> +          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
>>> +      Base = N.getOperand(0);
>>> +    } else {
>>> +      Base = N;
>>> +    }
>>> +
>>>   OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>>   return true;
>>> }
>>> @@ -932,11 +1006,12 @@
>>> // If the RHS is + imm5 * scale, fold into addr mode.
>>> if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>>>   int RHSC = (int)RHS->getZExtValue();
>>> -    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
>>> +
>>> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>>>     RHSC /= Scale;
>>> +
>>>     if (RHSC >= 0 && RHSC < 32) {
>>>       Base = N.getOperand(0);
>>> -        Offset = CurDAG->getRegister(0, MVT::i32);
>>>       OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>>>       return true;
>>>     }
>>> @@ -944,27 +1019,26 @@
>>> }
>>> 
>>> Base = N.getOperand(0);
>>> -  Offset = N.getOperand(1);
>>> OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>> return true;
>>> }
>>> 
>>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
>>> -                                            SDValue &Base, SDValue &OffImm,
>>> -                                            SDValue &Offset) {
>>> -  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
>>> -}
>>> -
>>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
>>> -                                            SDValue &Base, SDValue &OffImm,
>>> -                                            SDValue &Offset) {
>>> -  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
>>> -}
>>> -
>>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
>>> -                                            SDValue &Base, SDValue &OffImm,
>>> -                                            SDValue &Offset) {
>>> -  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
>>> +                                           SDValue &OffImm) {
>>> +  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
>>> +                                           SDValue &OffImm) {
>>> +  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
>>> +                                           SDValue &OffImm) {
>>> +  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
>>> }
>>> 
>>> bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
>>> @@ -1003,6 +1077,12 @@
>>> return false;
>>> }
>>> 
>>> +
>>> +//===----------------------------------------------------------------------===//
>>> +//                        Thumb 2 Addressing Modes
>>> +//===----------------------------------------------------------------------===//
>>> +
>>> +
>>> bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
>>>                                               SDValue &Opc) {
>>> if (DisableShifterOp)
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Dec 13 21:36:38 2010
>>> @@ -94,8 +94,13 @@
>>> let EncoderMethod = "getThumbBLXTargetOpValue";
>>> }
>>> 
>>> -def MemModeThumbAsmOperand : AsmOperandClass {
>>> -  let Name = "MemModeThumb";
>>> +def MemModeRegThumbAsmOperand : AsmOperandClass {
>>> +  let Name = "MemModeRegThumb";
>>> +  let SuperClasses = [];
>>> +}
>>> +
>>> +def MemModeImmThumbAsmOperand : AsmOperandClass {
>>> +  let Name = "MemModeImmThumb";
>>> let SuperClasses = [];
>>> }
>>> 
>>> @@ -103,42 +108,64 @@
>>> //
>>> def t_addrmode_rr : Operand<i32>,
>>>                   ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
>>> -  let EncoderMethod = "getTAddrModeRegRegOpValue";
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> +  let PrintMethod = "printThumbAddrModeRROperand";
>>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +}
>>> +
>>> +// t_addrmode_rrs := reg + reg
>>> +//
>>> +def t_addrmode_rrs1 : Operand<i32>,
>>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> let PrintMethod = "printThumbAddrModeRROperand";
>>> let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>>> }
>>> 
>>> -// t_addrmode_s4 := reg + reg
>>> -//                  reg + imm5 * 4
>>> +def t_addrmode_rrs2 : Operand<i32>,
>>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> +  let PrintMethod = "printThumbAddrModeRROperand";
>>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>>> +}
>>> +def t_addrmode_rrs4 : Operand<i32>,
>>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> +  let PrintMethod = "printThumbAddrModeRROperand";
>>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>>> +}
>>> +
>>> +// t_addrmode_is4 := reg + imm5 * 4
>>> //
>>> -def t_addrmode_s4 : Operand<i32>,
>>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
>>> -  let EncoderMethod = "getAddrModeSOpValue";
>>> -  let PrintMethod = "printThumbAddrModeS4Operand";
>>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +def t_addrmode_is4 : Operand<i32>,
>>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
>>> +  let EncoderMethod = "getAddrModeISOpValue";
>>> +  let PrintMethod = "printThumbAddrModeImm5S4Operand";
>>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> -// t_addrmode_s2 := reg + reg
>>> -//                  reg + imm5 * 2
>>> +// t_addrmode_is2 := reg + imm5 * 2
>>> //
>>> -def t_addrmode_s2 : Operand<i32>,
>>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
>>> -  let EncoderMethod = "getAddrModeSOpValue";
>>> -  let PrintMethod = "printThumbAddrModeS2Operand";
>>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +def t_addrmode_is2 : Operand<i32>,
>>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
>>> +  let EncoderMethod = "getAddrModeISOpValue";
>>> +  let PrintMethod = "printThumbAddrModeImm5S2Operand";
>>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> -// t_addrmode_s1 := reg + reg
>>> -//                  reg + imm5
>>> +// t_addrmode_is1 := reg + imm5
>>> //
>>> -def t_addrmode_s1 : Operand<i32>,
>>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
>>> -  let EncoderMethod = "getAddrModeSOpValue";
>>> -  let PrintMethod = "printThumbAddrModeS1Operand";
>>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +def t_addrmode_is1 : Operand<i32>,
>>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
>>> +  let EncoderMethod = "getAddrModeISOpValue";
>>> +  let PrintMethod = "printThumbAddrModeImm5S1Operand";
>>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> // t_addrmode_sp := sp + imm8 * 4
>>> @@ -148,14 +175,14 @@
>>> let EncoderMethod = "getAddrModeThumbSPOpValue";
>>> let PrintMethod = "printThumbAddrModeSPOperand";
>>> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> // t_addrmode_pc := <label> => pc + imm8 * 4
>>> //
>>> def t_addrmode_pc : Operand<i32> {
>>> let EncoderMethod = "getAddrModePCOpValue";
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> //===----------------------------------------------------------------------===//
>>> @@ -580,41 +607,41 @@
>>> //
>>> 
>>> let canFoldAsLoad = 1, isReMaterializable = 1 in
>>> -def tLDR :                      // A8.6.60
>>> -  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
>>> +def tLDRr :                      // A8.6.60
>>> +  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
>>>                AddrModeT1_4, IIC_iLoad_r,
>>>                "ldr", "\t$Rt, $addr",
>>> -                 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
>>> +                 [(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
>>> 
>>> def tLDRi :                     // A8.6.57
>>> -  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
>>> +  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
>>>                   AddrModeT1_4, IIC_iLoad_r,
>>>                   "ldr", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
>>> 
>>> -def tLDRB :                     // A8.6.64
>>> -  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
>>> +def tLDRBr :                    // A8.6.64
>>> +  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
>>>                AddrModeT1_1, IIC_iLoad_bh_r,
>>>                "ldrb", "\t$Rt, $addr",
>>> -                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
>>> +                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
>>> 
>>> def tLDRBi :                    // A8.6.61
>>> -  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
>>> +  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
>>>                   AddrModeT1_1, IIC_iLoad_bh_r,
>>>                   "ldrb", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
>>> 
>>> -def tLDRH :                     // A8.6.76
>>> -  T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
>>> +def tLDRHr :                    // A8.6.76
>>> +  T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
>>>                AddrModeT1_2, IIC_iLoad_bh_r,
>>> -                 "ldrh", "\t$dst, $addr",
>>> -                 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
>>> +                 "ldrh", "\t$Rt, $addr",
>>> +                 [(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
>>> 
>>> def tLDRHi :                    // A8.6.73
>>> -  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
>>> +  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
>>>                   AddrModeT1_2, IIC_iLoad_bh_r,
>>>                   "ldrh", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
>>> 
>>> let AddedComplexity = 10 in
>>> def tLDRSB :                    // A8.6.80
>>> @@ -676,45 +703,45 @@
>>> let Inst{7-0}  = addr;
>>> }
>>> 
>>> -def tSTR :                      // A8.6.194
>>> -  T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
>>> +def tSTRr :                     // A8.6.194
>>> +  T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
>>>                AddrModeT1_4, IIC_iStore_r,
>>> -                 "str", "\t$src, $addr",
>>> -                 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
>>> +                 "str", "\t$Rt, $addr",
>>> +                 [(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
>>> 
>>> def tSTRi :                     // A8.6.192
>>> -  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
>>> +  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
>>>                   AddrModeT1_4, IIC_iStore_r,
>>>                   "str", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
>>> 
>>> -def tSTRB :                     // A8.6.197
>>> -  T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
>>> +def tSTRBr :                    // A8.6.197
>>> +  T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
>>>                AddrModeT1_1, IIC_iStore_bh_r,
>>> -                 "strb", "\t$src, $addr",
>>> -                 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
>>> +                 "strb", "\t$Rt, $addr",
>>> +                 [(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
>>> 
>>> def tSTRBi :                    // A8.6.195
>>> -  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
>>> +  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
>>>                   AddrModeT1_1, IIC_iStore_bh_r,
>>>                   "strb", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
>>> 
>>> -def tSTRH :                     // A8.6.207
>>> -  T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
>>> +def tSTRHr :                    // A8.6.207
>>> +  T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
>>>                AddrModeT1_2, IIC_iStore_bh_r,
>>> -                 "strh", "\t$src, $addr",
>>> -                 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
>>> +                 "strh", "\t$Rt, $addr",
>>> +                 [(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
>>> 
>>> def tSTRHi :                    // A8.6.205
>>> -  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
>>> +  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
>>>                   AddrModeT1_2, IIC_iStore_bh_r,
>>>                   "strh", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
>>> 
>>> def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
>>> -                   "str", "\t$Rt, $addr",
>>> -                   [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>>> +                    "str", "\t$Rt, $addr",
>>> +                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>>>             T1LdStSP<{0,?,?}> {
>>> bits<3> Rt;
>>> bits<8> addr;
>>> @@ -1390,27 +1417,32 @@
>>>     Requires<[IsThumb, HasV5T, IsDarwin]>;
>>> 
>>> // zextload i1 -> zextload i8
>>> -def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
>>> -            (tLDRB t_addrmode_s1:$addr)>;
>>> +def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
>>> +            (tLDRBr t_addrmode_rrs1:$addr)>;
>>> +def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
>>> +            (tLDRBi t_addrmode_is1:$addr)>;
>>> 
>>> // extload -> zextload
>>> -def : T1Pat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
>>> -def : T1Pat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
>>> -def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
>>> +def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
>>> +def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
>>> +def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
>>> +def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
>>> +def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
>>> +def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
>>> 
>>> // If it's impossible to use [r,r] address mode for sextload, select to
>>> // ldr{b|h} + sxt{b|h} instead.
>>> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
>>> -            (tSXTB (tLDRB t_addrmode_s1:$addr))>,
>>> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
>>> +            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
>>>     Requires<[IsThumb, IsThumb1Only, HasV6]>;
>>> -def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
>>> -            (tSXTH (tLDRH t_addrmode_s2:$addr))>,
>>> +def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
>>> +            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
>>>     Requires<[IsThumb, IsThumb1Only, HasV6]>;
>>> 
>>> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
>>> -            (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
>>> -def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
>>> -            (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
>>> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
>>> +            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
>>> +def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr),
>>> +            (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>;
>>> 
>>> // Large immediate handling.
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -144,9 +144,9 @@
>>> uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
>>>                                  SmallVectorImpl<MCFixup> &Fixups) const;
>>> 
>>> -  /// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
>>> -  uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                                     SmallVectorImpl<MCFixup> &Fixups) const;
>>> +  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
>>> +  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                                         SmallVectorImpl<MCFixup> &Fixups)const;
>>> 
>>> /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
>>> /// operand.
>>> @@ -207,9 +207,9 @@
>>> uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
>>>                                    SmallVectorImpl<MCFixup> &Fixups) const;
>>> 
>>> -  /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
>>> -  uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                               SmallVectorImpl<MCFixup> &) const;
>>> +  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
>>> +  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                                SmallVectorImpl<MCFixup> &) const;
>>> 
>>> /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
>>> uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
>>> @@ -559,12 +559,16 @@
>>>                                 Fixups);
>>> }
>>> 
>>> -/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
>>> +/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
>>> +/// operand.
>>> uint32_t ARMMCCodeEmitter::
>>> -getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                        SmallVectorImpl<MCFixup> &Fixups) const {
>>> +getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                              SmallVectorImpl<MCFixup> &) const {
>>> +  // [Rn, Rm]
>>> +  //   {5-3} = Rm
>>> +  //   {2-0} = Rn
>>> const MCOperand &MO1 = MI.getOperand(OpIdx);
>>> -  const MCOperand &MO2 = MI.getOperand(OpIdx+1);
>>> +  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
>>> unsigned Rn = getARMRegisterNumbering(MO1.getReg());
>>> unsigned Rm = getARMRegisterNumbering(MO2.getReg());
>>> return (Rm << 3) | Rn;
>>> @@ -796,27 +800,17 @@
>>> return MO1.getImm() & 0xff;
>>> }
>>> 
>>> -/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
>>> +/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
>>> uint32_t ARMMCCodeEmitter::
>>> -getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                    SmallVectorImpl<MCFixup> &) const {
>>> -  // [Rn, Rm]
>>> -  //   {5-3} = Rm
>>> -  //   {2-0} = Rn
>>> -  //
>>> +getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                     SmallVectorImpl<MCFixup> &) const {
>>> // [Rn, #imm]
>>> //   {7-3} = imm5
>>> //   {2-0} = Rn
>>> const MCOperand &MO = MI.getOperand(OpIdx);
>>> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
>>> -  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
>>> unsigned Rn = getARMRegisterNumbering(MO.getReg());
>>> unsigned Imm5 = MO1.getImm();
>>> -
>>> -  if (MO2.getReg() != 0)
>>> -    // Is an immediate.
>>> -    Imm5 = getARMRegisterNumbering(MO2.getReg());
>>> -
>>> return ((Imm5 & 0x1f) << 3) | Rn;
>>> }
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 13 21:36:38 2010
>>> @@ -236,11 +236,16 @@
>>>   int64_t Value = CE->getValue();
>>>   return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
>>> }
>>> -  bool isMemModeThumb() const {
>>> +  bool isMemModeRegThumb() const {
>>> +    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>>> +      return false;
>>> +    return !Mem.Offset || !isa<MCConstantExpr>(Mem.Offset);
>>> +  }
>>> +  bool isMemModeImmThumb() const {
>>>   if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>>>     return false;
>>> 
>>> -    if (!Mem.Offset) return true;
>>> +    if (!Mem.Offset) return false;
>>> 
>>>   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>>   if (!CE) return false;
>>> @@ -324,19 +329,18 @@
>>>   }
>>> }
>>> 
>>> -  void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
>>> -    assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
>>> +  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
>>> +    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
>>>   Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
>>> +    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
>>> +  }
>>> 
>>> -    if (Mem.Offset) {
>>> -      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>> -      assert(CE && "Non-constant mode offset operand!");
>>> -      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>>> -      Inst.addOperand(MCOperand::CreateReg(0));
>>> -    } else {
>>> -      Inst.addOperand(MCOperand::CreateImm(0));
>>> -      Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
>>> -    }
>>> +  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
>>> +    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
>>> +    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
>>> +    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>> +    assert(CE && "Non-constant mode offset operand!");
>>> +    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>>> }
>>> 
>>> virtual void dump(raw_ostream &OS) const;
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -482,17 +482,25 @@
>>> void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
>>>                                                raw_ostream &O) {
>>> const MCOperand &MO1 = MI->getOperand(Op);
>>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>>> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
>>> +
>>> +  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>>> +    printOperand(MI, Op, O);
>>> +    return;
>>> +  }
>>> +
>>> O << "[" << getRegisterName(MO1.getReg());
>>> -  O << ", " << getRegisterName(MO2.getReg()) << "]";
>>> +  if (unsigned RegNum = MO2.getReg())
>>> +    O << ", " << getRegisterName(RegNum);
>>> +  O << "]";
>>> }
>>> 
>>> -void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
>>> -                                                  raw_ostream &O,
>>> -                                                  unsigned Scale) {
>>> +void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
>>> +                                                    unsigned Op,
>>> +                                                    raw_ostream &O,
>>> +                                                    unsigned Scale) {
>>> const MCOperand &MO1 = MI->getOperand(Op);
>>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>>> -  const MCOperand &MO3 = MI->getOperand(Op+2);
>>> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
>>> 
>>> if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>>>   printOperand(MI, Op, O);
>>> @@ -500,36 +508,32 @@
>>> }
>>> 
>>> O << "[" << getRegisterName(MO1.getReg());
>>> -  if (MO3.getReg())
>>> -    O << ", " << getRegisterName(MO3.getReg());
>>> -  else if (unsigned ImmOffs = MO2.getImm())
>>> +  if (unsigned ImmOffs = MO2.getImm())
>>>   O << ", #" << ImmOffs * Scale;
>>> O << "]";
>>> }
>>> 
>>> -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
>>> -                                                 raw_ostream &O) {
>>> -  printThumbAddrModeRI5Operand(MI, Op, O, 1);
>>> -}
>>> -
>>> -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
>>> -                                                 raw_ostream &O) {
>>> -  printThumbAddrModeRI5Operand(MI, Op, O, 2);
>>> -}
>>> -
>>> -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
>>> -                                                 raw_ostream &O) {
>>> -  printThumbAddrModeRI5Operand(MI, Op, O, 4);
>>> +void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
>>> +                                                     unsigned Op,
>>> +                                                     raw_ostream &O) {
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
>>> +}
>>> +
>>> +void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
>>> +                                                     unsigned Op,
>>> +                                                     raw_ostream &O) {
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
>>> +}
>>> +
>>> +void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
>>> +                                                     unsigned Op,
>>> +                                                     raw_ostream &O) {
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
>>> }
>>> 
>>> void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
>>>                                                raw_ostream &O) {
>>> -  const MCOperand &MO1 = MI->getOperand(Op);
>>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>>> -  O << "[" << getRegisterName(MO1.getReg());
>>> -  if (unsigned ImmOffs = MO2.getImm())
>>> -    O << ", #" << ImmOffs*4;
>>> -  O << "]";
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
>>> }
>>> 
>>> // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Dec 13 21:36:38 2010
>>> @@ -59,14 +59,14 @@
>>> void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
>>> void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
>>>                                  raw_ostream &O);
>>> -  void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,
>>> -                                    raw_ostream &O, unsigned Scale);
>>> -  void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum,
>>> -                                   raw_ostream &O);
>>> -  void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum,
>>> -                                   raw_ostream &O);
>>> -  void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum,
>>> -                                   raw_ostream &O);
>>> +  void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
>>> +                                      raw_ostream &O, unsigned Scale);
>>> +  void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
>>> +                                       raw_ostream &O);
>>> +  void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
>>> +                                       raw_ostream &O);
>>> +  void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
>>> +                                       raw_ostream &O);
>>> void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
>>>                                  raw_ostream &O);
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Dec 13 21:36:38 2010
>>> @@ -644,13 +644,11 @@
>>>                               *this, dl);
>>>   }
>>> 
>>> -    MI.setDesc(TII.get(ARM::tLDR));
>>> +    MI.setDesc(TII.get(ARM::tLDRr));
>>>   MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
>>>   if (UseRR)
>>>     // Use [reg, reg] addrmode.
>>>     MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>>> -    else  // tLDR has an extra register operand.
>>> -      MI.addOperand(MachineOperand::CreateReg(0, false));
>>> } else if (Desc.mayStore()) {
>>>     VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
>>>     bool UseRR = false;
>>> @@ -666,14 +664,13 @@
>>>     } else
>>>       emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
>>>                                 *this, dl);
>>> -      MI.setDesc(TII.get(ARM::tSTR));
>>> +      MI.setDesc(TII.get(ARM::tSTRr));
>>>     MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
>>>     if (UseRR)  // Use [reg, reg] addrmode.
>>>       MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>>> -      else // tSTR has an extra register operand.
>>> -        MI.addOperand(MachineOperand::CreateReg(0, false));
>>> -  } else
>>> +  } else {
>>>   assert(false && "Unexpected opcode!");
>>> +  }
>>> 
>>> // Add predicate back if it's needed.
>>> if (MI.getDesc().isPredicable()) {
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Mon Dec 13 21:36:38 2010
>>> @@ -105,19 +105,19 @@
>>>   // FIXME: Clean this up after splitting each Thumb load / store opcode
>>>   // into multiple ones.
>>>   { ARM::t2LDRi12,ARM::tLDRi,   ARM::tLDRspi,  5,   8,    1,   0,  0,0, 1 },
>>> -    { ARM::t2LDRs,  ARM::tLDR,    0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2LDRs,  ARM::tLDRr,   0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRBi12,ARM::tLDRBi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2LDRBs, ARM::tLDRB,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2LDRBs, ARM::tLDRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRHi12,ARM::tLDRHi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2LDRHs, ARM::tLDRH,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2LDRHs, ARM::tLDRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRSBs,ARM::tLDRSB,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRSHs,ARM::tLDRSH,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2STRi12,ARM::tSTRi,   ARM::tSTRspi,  5,   8,    1,   0,  0,0, 1 },
>>> -    { ARM::t2STRs,  ARM::tSTR,    0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2STRs,  ARM::tSTRr,   0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2STRBi12,ARM::tSTRBi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2STRBs, ARM::tSTRB,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2STRBs, ARM::tSTRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2STRHi12,ARM::tSTRHi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2STRHs, ARM::tSTRH,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2STRHs, ARM::tSTRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>>> 
>>>   { ARM::t2LDMIA, ARM::tLDMIA,  0,             0,   0,    1,   1,  1,1, 1 },
>>>   { ARM::t2LDMIA_RET,0,         ARM::tPOP_RET, 0,   0,    1,   1,  1,1, 1 },
>>> @@ -273,7 +273,6 @@
>>> bool HasShift = false;
>>> bool HasOffReg = true;
>>> bool isLdStMul = false;
>>> -  bool InsertImmOffset = true;
>>> unsigned Opc = Entry.NarrowOpc1;
>>> unsigned OpNum = 3; // First 'rest' of operands.
>>> uint8_t  ImmLimit = Entry.Imm1Limit;
>>> @@ -282,39 +281,41 @@
>>> default:
>>>   llvm_unreachable("Unexpected Thumb2 load / store opcode!");
>>> case ARM::t2LDRi12:
>>> -  case ARM::t2STRi12: {
>>> -    unsigned BaseReg = MI->getOperand(1).getReg();
>>> -    if (BaseReg == ARM::SP) {
>>> +  case ARM::t2STRi12:
>>> +    if (MI->getOperand(1).getReg() == ARM::SP) {
>>>     Opc = Entry.NarrowOpc2;
>>>     ImmLimit = Entry.Imm2Limit;
>>>     HasOffReg = false;
>>>   }
>>> +
>>>   Scale = 4;
>>> -    if (MI->getOperand(2).isImm())
>>> +
>>> +    if (MI->getOperand(2).isImm()) {
>>>     HasImmOffset = true;
>>> -    else {
>>> +      HasOffReg = false;
>>> +    } else {
>>>     if (Entry.WideOpc == ARM::t2LDRi12) {
>>>       Opc = ARM::tLDRpci;
>>>       OpNum = 2;
>>>     }
>>> +
>>>     HasImmOffset = false;
>>> -      InsertImmOffset = false;
>>>     HasBaseReg = false;
>>>     HasOffReg = false;
>>>   }
>>>   break;
>>> -  }
>>> case ARM::t2LDRBi12:
>>> case ARM::t2STRBi12:
>>> -    if (MI->getOperand(2).isImm())
>>> +    if (MI->getOperand(2).isImm()) {
>>>     HasImmOffset = true;
>>> -    else {
>>> +      HasOffReg = false;
>>> +    } else {
>>>     if (Entry.WideOpc == ARM::t2LDRBi12) {
>>>       Opc = ARM::tLDRpci;
>>>       OpNum = 2;
>>>     }
>>> +
>>>     HasImmOffset = false;
>>> -      InsertImmOffset = false;
>>>     HasBaseReg = false;
>>>     HasOffReg = false;
>>>   }
>>> @@ -322,15 +323,16 @@
>>> case ARM::t2LDRHi12:
>>> case ARM::t2STRHi12:
>>>   Scale = 2;
>>> -    if (MI->getOperand(2).isImm())
>>> +    if (MI->getOperand(2).isImm()) {
>>>     HasImmOffset = true;
>>> -    else {
>>> +      HasOffReg = false;
>>> +    } else {
>>>     if (Entry.WideOpc == ARM::t2LDRHi12) {
>>>       Opc = ARM::tLDRpci;
>>>       OpNum = 2;
>>>     }
>>> +
>>>     HasImmOffset = false;
>>> -      InsertImmOffset = false;
>>>     HasBaseReg = false;
>>>     HasOffReg = false;
>>>   }
>>> @@ -351,6 +353,7 @@
>>>   unsigned BaseReg = MI->getOperand(0).getReg();
>>>   if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
>>>     return false;
>>> +
>>>   // For the non-writeback version (this one), the base register must be
>>>   // one of the registers being loaded.
>>>   bool isOK = false;
>>> @@ -360,6 +363,7 @@
>>>       break;
>>>     }
>>>   }
>>> +
>>>   if (!isOK)
>>>     return false;
>>> 
>>> @@ -381,6 +385,7 @@
>>> case ARM::t2STMIA_UPD:
>>> case ARM::t2STMDB_UPD: {
>>>   OpNum = 0;
>>> +
>>>   unsigned BaseReg = MI->getOperand(1).getReg();
>>>   if (BaseReg == ARM::SP &&
>>>       (Entry.WideOpc == ARM::t2LDMIA_UPD ||
>>> @@ -392,6 +397,7 @@
>>>               Entry.WideOpc != ARM::t2STMIA_UPD)) {
>>>     return false;
>>>   }
>>> +
>>>   isLdStMul = true;
>>>   break;
>>> }
>>> @@ -402,6 +408,7 @@
>>> if (HasShift) {
>>>   OffsetReg  = MI->getOperand(2).getReg();
>>>   OffsetKill = MI->getOperand(2).isKill();
>>> +
>>>   if (MI->getOperand(3).getImm())
>>>     // Thumb1 addressing mode doesn't support shift.
>>>     return false;
>>> @@ -411,24 +418,24 @@
>>> if (HasImmOffset) {
>>>   OffsetImm = MI->getOperand(2).getImm();
>>>   unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
>>> -    if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
>>> +
>>> +    if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
>>>     // Make sure the immediate field fits.
>>>     return false;
>>> }
>>> 
>>> // Add the 16-bit load / store instruction.
>>> -  // FIXME: Thumb1 addressing mode encode both immediate and register offset.
>>> DebugLoc dl = MI->getDebugLoc();
>>> MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
>>> if (!isLdStMul) {
>>>   MIB.addOperand(MI->getOperand(0));
>>> -    if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
>>> -    if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
>>> -      // tLDRSB and tLDRSH do not have an immediate offset field. On the other
>>> -      // hand, it must have an offset register.
>>> -      // FIXME: Remove this special case.
>>> -      MIB.addImm(OffsetImm/Scale);
>>> -    }
>>> +
>>> +    if (HasBaseReg)
>>> +      MIB.addOperand(MI->getOperand(1));
>>> +
>>> +    if (HasImmOffset)
>>> +      MIB.addImm(OffsetImm / Scale);
>>> +
>>>   assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
>>> 
>>>   if (HasOffReg)
>>> 
>>> Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
>>> +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -629,9 +629,12 @@
>>> MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
>>>                                                                 // R, I
>>> MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
>>> -  MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1");           // R, I, R
>>> -  MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2");           // R, I, R
>>> -  MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4");           // R, I, R
>>> +  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
>>> +  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
>>> +  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
>>> +  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
>>> +  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
>>> +  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
>>> MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
>>> MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
>>> MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
>>> @@ -841,9 +844,8 @@
>>> operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
>>> operandTypes.addEntry("kOperandTypeARMTBAddrMode");
>>> operandTypes.addEntry("kOperandTypeThumbITMask");
>>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
>>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
>>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
>>> +  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
>>> +  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
>>> operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
>>> operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
>>> operandTypes.addEntry("kOperandTypeThumbAddrModePC");
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From grosbach at apple.com  Tue Dec 14 10:25:15 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 16:25:15 -0000
Subject: [llvm-commits] [llvm] r121769 -
	/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
Message-ID: <20101214162515.EE0B02A6C12D@llvm.org>

Author: grosbach
Date: Tue Dec 14 10:25:15 2010
New Revision: 121769

URL: http://llvm.org/viewvc/llvm-project?rev=121769&view=rev
Log:
Trailing whitespace

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121769&r1=121768&r2=121769&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Dec 14 10:25:15 2010
@@ -136,7 +136,7 @@
     // Encode the immediate and shift the opcode into place.
     return ARM_AM::getSOImmVal(Value) | (opc << 21);
   }
-  
+
   case ARM::fixup_t2_adr_pcrel_12: {
     Value -= 4;
     unsigned opc = 0;
@@ -149,12 +149,12 @@
     out |= (Value & 0x800) << 14;
     out |= (Value & 0x700) << 4;
     out |= (Value & 0x0FF);
-    
+
     uint64_t swapped = (out & 0xFFFF0000) >> 16;
     swapped |= (out & 0x0000FFFF) << 16;
     return swapped;
   }
-  
+
   case ARM::fixup_arm_branch:
     // These values don't encode the low two bits since they're always zero.
     // Offset by 8 just as above.
@@ -169,13 +169,13 @@
     bool J2 = Value & 0x200000;
     J1 ^= I;
     J2 ^= I;
-    
+
     out |= I  << 26; // S bit
     out |= !J1 << 13; // J1 bit
     out |= !J2 << 11; // J2 bit
     out |= (Value & 0x1FF800)  << 5; // imm6 field
     out |= (Value & 0x0007FF);        // imm11 field
-    
+
     uint64_t swapped = (out & 0xFFFF0000) >> 16;
     swapped |= (out & 0x0000FFFF) << 16;
     return swapped;
@@ -183,7 +183,7 @@
   case ARM::fixup_t2_condbranch: {
     Value = Value - 4;
     Value >>= 1; // Low bit is not encoded.
-    
+
     uint64_t out = 0;
     out |= (Value & 0x80000) << 7; // S bit
     out |= (Value & 0x40000) >> 7; // J2 bit



From pdox at google.com  Tue Dec 14 11:29:19 2010
From: pdox at google.com (David Meyer)
Date: Tue, 14 Dec 2010 09:29:19 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy invalidation
Message-ID: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>

This patch moves invalidation of the layout until after all relaxations have
occurred.

This prevents wasting time recomputing portions of the layout over and over.
Computing the layout is expensive, so we want to use as much of the
information generated each time as possible, instead of throwing it away
each  time a relaxation happens.

This removes a hidden O(n^2) runtime factor (where n is the number of
fragments) which causes terrifying performance problems when assembling
really large .s file with lots of relaxable instructions.

- David Meyer
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From daniel at zuster.org  Tue Dec 14 11:37:16 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 14 Dec 2010 17:37:16 -0000
Subject: [llvm-commits] [llvm] r121772 - in /llvm/trunk:
 lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_fixups.s
Message-ID: <20101214173716.43E442A6C12D@llvm.org>

Author: ddunbar
Date: Tue Dec 14 11:37:16 2010
New Revision: 121772

URL: http://llvm.org/viewvc/llvm-project?rev=121772&view=rev
Log:
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.

Added:
    llvm/trunk/test/MC/ARM/arm_fixups.s
Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121772&r1=121771&r2=121772&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Dec 14 11:37:16 2010
@@ -58,7 +58,7 @@
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
-{ "fixup_arm_branch",        1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_branch",        0,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_br",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },

Added: llvm/trunk/test/MC/ARM/arm_fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_fixups.s?rev=121772&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_fixups.s (added)
+++ llvm/trunk/test/MC/ARM/arm_fixups.s Tue Dec 14 11:37:16 2010
@@ -0,0 +1,7 @@
+// RUN: llvm-mc -triple arm-unknown-unknown %s --show-encoding > %t
+// RUN: FileCheck < %t %s
+
+// CHECK: bl _printf @ encoding: [A,A,A,0xeb]
+// CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_branch
+bl _printf
+        
\ No newline at end of file



From stoklund at 2pi.dk  Tue Dec 14 11:47:36 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 17:47:36 -0000
Subject: [llvm-commits] [llvm] r121774 -
	/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Message-ID: <20101214174736.42BAC2A6C12D@llvm.org>

Author: stoklund
Date: Tue Dec 14 11:47:36 2010
New Revision: 121774

URL: http://llvm.org/viewvc/llvm-project?rev=121774&view=rev
Log:
Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121774&r1=121773&r2=121774&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Dec 14 11:47:36 2010
@@ -175,9 +175,9 @@
   // Check direct interferences.
   LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
   if (Q.checkInterference()) {
+    Q.collectInterferingVRegs(1);
     if (!Q.seenAllInterferences())
       return 0;
-    Q.collectInterferingVRegs(1);
     Interference = Q.interferingVRegs().front();
   }
 
@@ -185,9 +185,11 @@
   for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
     LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
     if (Q.checkInterference()) {
-      if (Interference || !Q.seenAllInterferences())
+      if (Interference)
         return 0;
       Q.collectInterferingVRegs(1);
+      if (!Q.seenAllInterferences())
+        return 0;
       Interference = Q.interferingVRegs().front();
     }
   }



From pdox at google.com  Tue Dec 14 11:54:15 2010
From: pdox at google.com (David Meyer)
Date: Tue, 14 Dec 2010 09:54:15 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
Message-ID: <AANLkTi=Nh5-kkN9bENQYyh29RtsaRLQ_BtGXBbzCYnyK@mail.gmail.com>

I retract this patch at the moment...  I forgot to fix a problem with it.

Will submit a new one shortly.

- David Meyer


On Tue, Dec 14, 2010 at 9:29 AM, David Meyer <pdox at google.com> wrote:

> This patch moves invalidation of the layout until after all relaxations
> have occurred.
>
> This prevents wasting time recomputing portions of the layout over and
> over. Computing the layout is expensive, so we want to use as much of the
> information generated each time as possible, instead of throwing it away
> each  time a relaxation happens.
>
> This removes a hidden O(n^2) runtime factor (where n is the number of
> fragments) which causes terrifying performance problems when assembling
> really large .s file with lots of relaxable instructions.
>
> - David Meyer
>
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From rafael.espindola at gmail.com  Tue Dec 14 11:55:55 2010
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 14 Dec 2010 09:55:55 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
Message-ID: <4D07AFAB.8080907@gmail.com>

On 10-12-14 9:29 AM, David Meyer wrote:
> This patch moves invalidation of the layout until after all relaxations
> have occurred.
>
> This prevents wasting time recomputing portions of the layout over and
> over. Computing the layout is expensive, so we want to use as much of
> the information generated each time as possible, instead of throwing it
> away each  time a relaxation happens.
>
> This removes a hidden O(n^2) runtime factor (where n is the number of
> fragments) which causes terrifying performance problems when assembling
> really large .s file with lots of relaxable instructions.

You can probably remove the WasRelaxed variable now.

Do you have an example of the .s file? While working on PR8711 I tried 
something along these lines. It helped on some files, but caused more
passes on others.

One thing I tried that was unnecessary after decoupling sections but 
might help in here (and I can try it with a .s):

*) Relax align fragments. With this you can remove the EffectiveSize 
field and then invalidate should mark the last relaxed fragment as the 
last valid one (instead of the previous).

Other ideas I had but didn't implement:

*) Have a working list of fragments that might need to be relaxed, that 
way you don't revisit every fragment on every pass.
*) Have EvaluateAsAbsolute return an enum: Absolute, 
AbsoluteAfterLayout, NotAbsolute. With this you can then prune the work 
list earlier.


> - David Meyer

Cheers,
Rafael

From evan.cheng at apple.com  Tue Dec 14 12:10:30 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 14 Dec 2010 10:10:30 -0800
Subject: [llvm-commits] [llvm] r121747 - in /llvm/trunk:
	lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMCodeEmitter.cpp
	lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrThumb.td
	lib/Target/ARM/ARMMCCodeEmitter.cpp
	lib/Target/ARM/AsmParser/ARMAsmParser.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
	lib/Target/ARM/InstPrinter/ARMInstPrinter.h
	lib/Target/ARM/Thumb1RegisterInfo.cpp
	lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/EDEmitter.cpp
In-Reply-To: <4BE9BD84-20DE-4612-A959-5F6F02454021@gmail.com>
References: <20101214033639.1C4662A6C12C@llvm.org>
	<D060E5D8-3663-43A3-9EDF-4689B028A929@apple.com>
	<4BE9BD84-20DE-4612-A959-5F6F02454021@gmail.com>
Message-ID: <F3381E36-1CA0-4588-AC92-FEF644B6C286@apple.com>

Sounds great! Thanks Bill.

Evan

On Dec 14, 2010, at 3:36 AM, Bill Wendling wrote:

> I can do that (or at least continue it) as part of the cleanup I need to do because of this patch.
> 
> -bw
> 
> On Dec 13, 2010, at 10:53 PM, Evan Cheng wrote:
> 
>> Thanks. It would be nice if we could completely split out loads / stores for ARM as well. Jim started on it but he ran out of time.
>> 
>> Evan
>> 
>> On Dec 13, 2010, at 7:36 PM, Bill Wendling wrote:
>> 
>>> Author: void
>>> Date: Mon Dec 13 21:36:38 2010
>>> New Revision: 121747
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=121747&view=rev
>>> Log:
>>> The tLDR et al instructions were emitting either a reg/reg or reg/imm
>>> instruction based on the t_addrmode_s# mode and what it returned. There is some
>>> obvious badness to this. In particular, it's hard to do MC-encoding when the
>>> instruction may change out from underneath you after the t_addrmode_s# variable
>>> is finally resolved.
>>> 
>>> The solution is to revert a long-ago change that merged the reg/reg and reg/imm
>>> versions. There is the addition of several new addressing modes. They no longer
>>> have extraneous operands associated with them. I.e., if it's reg/reg we don't
>>> have to have a dummy zero immediate tacked on to the SDNode.
>>> 
>>> There are some obvious cleanups here, which will happen shortly.
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>>  llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>>>  llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>>  llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>>>  llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>>>  llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>>  llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>>>  llvm/trunk/utils/TableGen/EDEmitter.cpp
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -1129,13 +1129,12 @@
>>>   }
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tSTR);
>>> +      TmpInst.setOpcode(ARM::tSTRi);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ValReg));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>>     // The offset immediate is #4. The operand value is scaled by 4 for the
>>>     // tSTR instruction.
>>>     TmpInst.addOperand(MCOperand::CreateImm(1));
>>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>> @@ -1312,13 +1311,12 @@
>>>   unsigned ScratchReg = MI->getOperand(1).getReg();
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tLDR);
>>> +      TmpInst.setOpcode(ARM::tLDRi);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>>     // The offset immediate is #8. The operand value is scaled by 4 for the
>>> -      // tSTR instruction.
>>> +      // tLDR instruction.
>>>     TmpInst.addOperand(MCOperand::CreateImm(2));
>>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>> @@ -1336,11 +1334,10 @@
>>>   }
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tLDR);
>>> +      TmpInst.setOpcode(ARM::tLDRi);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>>     TmpInst.addOperand(MCOperand::CreateImm(1));
>>> -      TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>> @@ -1348,10 +1345,9 @@
>>>   }
>>>   {
>>>     MCInst TmpInst;
>>> -      TmpInst.setOpcode(ARM::tLDR);
>>> +      TmpInst.setOpcode(ARM::tLDRr);
>>>     TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
>>>     TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
>>> -      TmpInst.addOperand(MCOperand::CreateImm(0));
>>>     TmpInst.addOperand(MCOperand::CreateReg(0));
>>>     // Predicate.
>>>     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -193,7 +193,7 @@
>>>     const { return 0; }
>>>   unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>> -    unsigned getTAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>>> +    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>>   unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>> @@ -265,6 +265,8 @@
>>>     const { return 0; }
>>>   uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>> +    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
>>> +      const { return 0; }
>>>   uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
>>>     const { return 0; }
>>>   uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Dec 13 21:36:38 2010
>>> @@ -130,18 +130,24 @@
>>> bool SelectAddrModePC(SDValue N, SDValue &Offset,
>>>                       SDValue &Label);
>>> 
>>> +  // Thumb Addressing Modes:
>>> bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
>>> -  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
>>> -                              SDValue &Base, SDValue &OffImm,
>>> -                              SDValue &Offset);
>>> -  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
>>> -                             SDValue &OffImm, SDValue &Offset);
>>> -  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
>>> -                             SDValue &OffImm, SDValue &Offset);
>>> -  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
>>> -                             SDValue &OffImm, SDValue &Offset);
>>> +  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
>>> +                             unsigned Scale);
>>> +  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
>>> +  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
>>> +  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
>>> +  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
>>> +                                SDValue &OffImm);
>>> +  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
>>> +                                 SDValue &OffImm);
>>> +  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
>>> +                                 SDValue &OffImm);
>>> +  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
>>> +                                 SDValue &OffImm);
>>> bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
>>> 
>>> +  // Thumb 2 Addressing Modes:
>>> bool SelectT2ShifterOperandReg(SDValue N,
>>>                                SDValue &BaseReg, SDValue &Opc);
>>> bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
>>> @@ -872,9 +878,16 @@
>>>                                      MVT::i32);
>>>   return true;
>>> }
>>> +
>>> return false;
>>> }
>>> 
>>> +
>>> +//===----------------------------------------------------------------------===//
>>> +//                         Thumb Addressing Modes
>>> +//===----------------------------------------------------------------------===//
>>> +
>>> +
>>> bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
>>>                                           SDValue &Base, SDValue &Offset){
>>> // FIXME dl should come from the parent load or store, not the address
>>> @@ -893,13 +906,13 @@
>>> }
>>> 
>>> bool
>>> -ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
>>> -                                        unsigned Scale, SDValue &Base,
>>> -                                        SDValue &OffImm, SDValue &Offset) {
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
>>> +                                       SDValue &Offset, unsigned Scale) {
>>> if (Scale == 4) {
>>>   SDValue TmpBase, TmpOffImm;
>>>   if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>>>     return false;  // We want to select tLDRspi / tSTRspi instead.
>>> +
>>>   if (N.getOpcode() == ARMISD::Wrapper &&
>>>       N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>>>     return false;  // We want to select tLDRpci instead.
>>> @@ -907,14 +920,13 @@
>>> 
>>> if (N.getOpcode() != ISD::ADD) {
>>>   if (N.getOpcode() == ARMISD::Wrapper &&
>>> -        !(Subtarget->useMovt() &&
>>> -          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
>>> +        (!Subtarget->useMovt() ||
>>> +         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
>>>     Base = N.getOperand(0);
>>> -    } else
>>> +    else
>>>     Base = N;
>>> 
>>>   Offset = CurDAG->getRegister(0, MVT::i32);
>>> -    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>>   return true;
>>> }
>>> 
>>> @@ -925,6 +937,68 @@
>>>     (RHSR && RHSR->getReg() == ARM::SP)) {
>>>   Base = N;
>>>   Offset = CurDAG->getRegister(0, MVT::i32);
>>> +    return true;
>>> +  }
>>> +
>>> +  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>>> +    int RHSC = (int)RHS->getZExtValue();
>>> +
>>> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>>> +      RHSC /= Scale;
>>> +
>>> +      if (RHSC >= 0 && RHSC < 32)
>>> +        return false;
>>> +    }
>>> +  }
>>> +
>>> +  Base = N.getOperand(0);
>>> +  Offset = N.getOperand(1);
>>> +  return true;
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
>>> +                                          SDValue &Base,
>>> +                                          SDValue &Offset) {
>>> +  return SelectThumbAddrModeRI(N, Base, Offset, 1);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
>>> +                                          SDValue &Base,
>>> +                                          SDValue &Offset) {
>>> +  return SelectThumbAddrModeRI(N, Base, Offset, 2);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
>>> +                                          SDValue &Base,
>>> +                                          SDValue &Offset) {
>>> +  return SelectThumbAddrModeRI(N, Base, Offset, 4);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
>>> +                                          SDValue &Base, SDValue &OffImm) {
>>> +  if (Scale == 4) {
>>> +    SDValue TmpBase, TmpOffImm;
>>> +    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
>>> +      return false;  // We want to select tLDRspi / tSTRspi instead.
>>> +
>>> +    if (N.getOpcode() == ARMISD::Wrapper &&
>>> +        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
>>> +      return false;  // We want to select tLDRpci instead.
>>> +  }
>>> +
>>> +  if (N.getOpcode() != ISD::ADD) {
>>> +    if (N.getOpcode() == ARMISD::Wrapper &&
>>> +        !(Subtarget->useMovt() &&
>>> +          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
>>> +      Base = N.getOperand(0);
>>> +    } else {
>>> +      Base = N;
>>> +    }
>>> +
>>>   OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>>   return true;
>>> }
>>> @@ -932,11 +1006,12 @@
>>> // If the RHS is + imm5 * scale, fold into addr mode.
>>> if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
>>>   int RHSC = (int)RHS->getZExtValue();
>>> -    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
>>> +
>>> +    if ((RHSC & (Scale - 1)) == 0) { // The constant is implicitly multiplied.
>>>     RHSC /= Scale;
>>> +
>>>     if (RHSC >= 0 && RHSC < 32) {
>>>       Base = N.getOperand(0);
>>> -        Offset = CurDAG->getRegister(0, MVT::i32);
>>>       OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>>>       return true;
>>>     }
>>> @@ -944,27 +1019,26 @@
>>> }
>>> 
>>> Base = N.getOperand(0);
>>> -  Offset = N.getOperand(1);
>>> OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>> return true;
>>> }
>>> 
>>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
>>> -                                            SDValue &Base, SDValue &OffImm,
>>> -                                            SDValue &Offset) {
>>> -  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
>>> -}
>>> -
>>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
>>> -                                            SDValue &Base, SDValue &OffImm,
>>> -                                            SDValue &Offset) {
>>> -  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
>>> -}
>>> -
>>> -bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
>>> -                                            SDValue &Base, SDValue &OffImm,
>>> -                                            SDValue &Offset) {
>>> -  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
>>> +                                           SDValue &OffImm) {
>>> +  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
>>> +                                           SDValue &OffImm) {
>>> +  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
>>> +}
>>> +
>>> +bool
>>> +ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
>>> +                                           SDValue &OffImm) {
>>> +  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
>>> }
>>> 
>>> bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
>>> @@ -1003,6 +1077,12 @@
>>> return false;
>>> }
>>> 
>>> +
>>> +//===----------------------------------------------------------------------===//
>>> +//                        Thumb 2 Addressing Modes
>>> +//===----------------------------------------------------------------------===//
>>> +
>>> +
>>> bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
>>>                                               SDValue &Opc) {
>>> if (DisableShifterOp)
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Dec 13 21:36:38 2010
>>> @@ -94,8 +94,13 @@
>>> let EncoderMethod = "getThumbBLXTargetOpValue";
>>> }
>>> 
>>> -def MemModeThumbAsmOperand : AsmOperandClass {
>>> -  let Name = "MemModeThumb";
>>> +def MemModeRegThumbAsmOperand : AsmOperandClass {
>>> +  let Name = "MemModeRegThumb";
>>> +  let SuperClasses = [];
>>> +}
>>> +
>>> +def MemModeImmThumbAsmOperand : AsmOperandClass {
>>> +  let Name = "MemModeImmThumb";
>>> let SuperClasses = [];
>>> }
>>> 
>>> @@ -103,42 +108,64 @@
>>> //
>>> def t_addrmode_rr : Operand<i32>,
>>>                   ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
>>> -  let EncoderMethod = "getTAddrModeRegRegOpValue";
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> +  let PrintMethod = "printThumbAddrModeRROperand";
>>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +}
>>> +
>>> +// t_addrmode_rrs := reg + reg
>>> +//
>>> +def t_addrmode_rrs1 : Operand<i32>,
>>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> let PrintMethod = "printThumbAddrModeRROperand";
>>> let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>>> }
>>> 
>>> -// t_addrmode_s4 := reg + reg
>>> -//                  reg + imm5 * 4
>>> +def t_addrmode_rrs2 : Operand<i32>,
>>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> +  let PrintMethod = "printThumbAddrModeRROperand";
>>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>>> +}
>>> +def t_addrmode_rrs4 : Operand<i32>,
>>> +                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
>>> +  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
>>> +  let PrintMethod = "printThumbAddrModeRROperand";
>>> +  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
>>> +  let ParserMatchClass = MemModeRegThumbAsmOperand;
>>> +}
>>> +
>>> +// t_addrmode_is4 := reg + imm5 * 4
>>> //
>>> -def t_addrmode_s4 : Operand<i32>,
>>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
>>> -  let EncoderMethod = "getAddrModeSOpValue";
>>> -  let PrintMethod = "printThumbAddrModeS4Operand";
>>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +def t_addrmode_is4 : Operand<i32>,
>>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
>>> +  let EncoderMethod = "getAddrModeISOpValue";
>>> +  let PrintMethod = "printThumbAddrModeImm5S4Operand";
>>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> -// t_addrmode_s2 := reg + reg
>>> -//                  reg + imm5 * 2
>>> +// t_addrmode_is2 := reg + imm5 * 2
>>> //
>>> -def t_addrmode_s2 : Operand<i32>,
>>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
>>> -  let EncoderMethod = "getAddrModeSOpValue";
>>> -  let PrintMethod = "printThumbAddrModeS2Operand";
>>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +def t_addrmode_is2 : Operand<i32>,
>>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
>>> +  let EncoderMethod = "getAddrModeISOpValue";
>>> +  let PrintMethod = "printThumbAddrModeImm5S2Operand";
>>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> -// t_addrmode_s1 := reg + reg
>>> -//                  reg + imm5
>>> +// t_addrmode_is1 := reg + imm5
>>> //
>>> -def t_addrmode_s1 : Operand<i32>,
>>> -                    ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
>>> -  let EncoderMethod = "getAddrModeSOpValue";
>>> -  let PrintMethod = "printThumbAddrModeS1Operand";
>>> -  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +def t_addrmode_is1 : Operand<i32>,
>>> +                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
>>> +  let EncoderMethod = "getAddrModeISOpValue";
>>> +  let PrintMethod = "printThumbAddrModeImm5S1Operand";
>>> +  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> // t_addrmode_sp := sp + imm8 * 4
>>> @@ -148,14 +175,14 @@
>>> let EncoderMethod = "getAddrModeThumbSPOpValue";
>>> let PrintMethod = "printThumbAddrModeSPOperand";
>>> let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> // t_addrmode_pc := <label> => pc + imm8 * 4
>>> //
>>> def t_addrmode_pc : Operand<i32> {
>>> let EncoderMethod = "getAddrModePCOpValue";
>>> -  let ParserMatchClass = MemModeThumbAsmOperand;
>>> +  let ParserMatchClass = MemModeImmThumbAsmOperand;
>>> }
>>> 
>>> //===----------------------------------------------------------------------===//
>>> @@ -580,41 +607,41 @@
>>> //
>>> 
>>> let canFoldAsLoad = 1, isReMaterializable = 1 in
>>> -def tLDR :                      // A8.6.60
>>> -  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
>>> +def tLDRr :                      // A8.6.60
>>> +  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
>>>                AddrModeT1_4, IIC_iLoad_r,
>>>                "ldr", "\t$Rt, $addr",
>>> -                 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
>>> +                 [(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
>>> 
>>> def tLDRi :                     // A8.6.57
>>> -  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
>>> +  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
>>>                   AddrModeT1_4, IIC_iLoad_r,
>>>                   "ldr", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
>>> 
>>> -def tLDRB :                     // A8.6.64
>>> -  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
>>> +def tLDRBr :                    // A8.6.64
>>> +  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
>>>                AddrModeT1_1, IIC_iLoad_bh_r,
>>>                "ldrb", "\t$Rt, $addr",
>>> -                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
>>> +                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
>>> 
>>> def tLDRBi :                    // A8.6.61
>>> -  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
>>> +  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
>>>                   AddrModeT1_1, IIC_iLoad_bh_r,
>>>                   "ldrb", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
>>> 
>>> -def tLDRH :                     // A8.6.76
>>> -  T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
>>> +def tLDRHr :                    // A8.6.76
>>> +  T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
>>>                AddrModeT1_2, IIC_iLoad_bh_r,
>>> -                 "ldrh", "\t$dst, $addr",
>>> -                 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
>>> +                 "ldrh", "\t$Rt, $addr",
>>> +                 [(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
>>> 
>>> def tLDRHi :                    // A8.6.73
>>> -  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
>>> +  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
>>>                   AddrModeT1_2, IIC_iLoad_bh_r,
>>>                   "ldrh", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
>>> 
>>> let AddedComplexity = 10 in
>>> def tLDRSB :                    // A8.6.80
>>> @@ -676,45 +703,45 @@
>>> let Inst{7-0}  = addr;
>>> }
>>> 
>>> -def tSTR :                      // A8.6.194
>>> -  T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
>>> +def tSTRr :                     // A8.6.194
>>> +  T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
>>>                AddrModeT1_4, IIC_iStore_r,
>>> -                 "str", "\t$src, $addr",
>>> -                 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
>>> +                 "str", "\t$Rt, $addr",
>>> +                 [(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
>>> 
>>> def tSTRi :                     // A8.6.192
>>> -  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
>>> +  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
>>>                   AddrModeT1_4, IIC_iStore_r,
>>>                   "str", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
>>> 
>>> -def tSTRB :                     // A8.6.197
>>> -  T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
>>> +def tSTRBr :                    // A8.6.197
>>> +  T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
>>>                AddrModeT1_1, IIC_iStore_bh_r,
>>> -                 "strb", "\t$src, $addr",
>>> -                 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
>>> +                 "strb", "\t$Rt, $addr",
>>> +                 [(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
>>> 
>>> def tSTRBi :                    // A8.6.195
>>> -  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
>>> +  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
>>>                   AddrModeT1_1, IIC_iStore_bh_r,
>>>                   "strb", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
>>> 
>>> -def tSTRH :                     // A8.6.207
>>> -  T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
>>> +def tSTRHr :                    // A8.6.207
>>> +  T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
>>>                AddrModeT1_2, IIC_iStore_bh_r,
>>> -                 "strh", "\t$src, $addr",
>>> -                 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
>>> +                 "strh", "\t$Rt, $addr",
>>> +                 [(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
>>> 
>>> def tSTRHi :                    // A8.6.205
>>> -  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
>>> +  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
>>>                   AddrModeT1_2, IIC_iStore_bh_r,
>>>                   "strh", "\t$Rt, $addr",
>>> -                    []>;
>>> +                    [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
>>> 
>>> def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
>>> -                   "str", "\t$Rt, $addr",
>>> -                   [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>>> +                    "str", "\t$Rt, $addr",
>>> +                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
>>>             T1LdStSP<{0,?,?}> {
>>> bits<3> Rt;
>>> bits<8> addr;
>>> @@ -1390,27 +1417,32 @@
>>>     Requires<[IsThumb, HasV5T, IsDarwin]>;
>>> 
>>> // zextload i1 -> zextload i8
>>> -def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
>>> -            (tLDRB t_addrmode_s1:$addr)>;
>>> +def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
>>> +            (tLDRBr t_addrmode_rrs1:$addr)>;
>>> +def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
>>> +            (tLDRBi t_addrmode_is1:$addr)>;
>>> 
>>> // extload -> zextload
>>> -def : T1Pat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
>>> -def : T1Pat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
>>> -def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
>>> +def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
>>> +def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
>>> +def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
>>> +def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
>>> +def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
>>> +def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
>>> 
>>> // If it's impossible to use [r,r] address mode for sextload, select to
>>> // ldr{b|h} + sxt{b|h} instead.
>>> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
>>> -            (tSXTB (tLDRB t_addrmode_s1:$addr))>,
>>> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
>>> +            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
>>>     Requires<[IsThumb, IsThumb1Only, HasV6]>;
>>> -def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
>>> -            (tSXTH (tLDRH t_addrmode_s2:$addr))>,
>>> +def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
>>> +            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
>>>     Requires<[IsThumb, IsThumb1Only, HasV6]>;
>>> 
>>> -def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
>>> -            (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
>>> -def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
>>> -            (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
>>> +def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
>>> +            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
>>> +def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr),
>>> +            (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>;
>>> 
>>> // Large immediate handling.
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -144,9 +144,9 @@
>>> uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
>>>                                  SmallVectorImpl<MCFixup> &Fixups) const;
>>> 
>>> -  /// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
>>> -  uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                                     SmallVectorImpl<MCFixup> &Fixups) const;
>>> +  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
>>> +  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                                         SmallVectorImpl<MCFixup> &Fixups)const;
>>> 
>>> /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
>>> /// operand.
>>> @@ -207,9 +207,9 @@
>>> uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
>>>                                    SmallVectorImpl<MCFixup> &Fixups) const;
>>> 
>>> -  /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
>>> -  uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                               SmallVectorImpl<MCFixup> &) const;
>>> +  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
>>> +  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                                SmallVectorImpl<MCFixup> &) const;
>>> 
>>> /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
>>> uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
>>> @@ -559,12 +559,16 @@
>>>                                 Fixups);
>>> }
>>> 
>>> -/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
>>> +/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
>>> +/// operand.
>>> uint32_t ARMMCCodeEmitter::
>>> -getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                        SmallVectorImpl<MCFixup> &Fixups) const {
>>> +getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                              SmallVectorImpl<MCFixup> &) const {
>>> +  // [Rn, Rm]
>>> +  //   {5-3} = Rm
>>> +  //   {2-0} = Rn
>>> const MCOperand &MO1 = MI.getOperand(OpIdx);
>>> -  const MCOperand &MO2 = MI.getOperand(OpIdx+1);
>>> +  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
>>> unsigned Rn = getARMRegisterNumbering(MO1.getReg());
>>> unsigned Rm = getARMRegisterNumbering(MO2.getReg());
>>> return (Rm << 3) | Rn;
>>> @@ -796,27 +800,17 @@
>>> return MO1.getImm() & 0xff;
>>> }
>>> 
>>> -/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
>>> +/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
>>> uint32_t ARMMCCodeEmitter::
>>> -getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
>>> -                    SmallVectorImpl<MCFixup> &) const {
>>> -  // [Rn, Rm]
>>> -  //   {5-3} = Rm
>>> -  //   {2-0} = Rn
>>> -  //
>>> +getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
>>> +                     SmallVectorImpl<MCFixup> &) const {
>>> // [Rn, #imm]
>>> //   {7-3} = imm5
>>> //   {2-0} = Rn
>>> const MCOperand &MO = MI.getOperand(OpIdx);
>>> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
>>> -  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
>>> unsigned Rn = getARMRegisterNumbering(MO.getReg());
>>> unsigned Imm5 = MO1.getImm();
>>> -
>>> -  if (MO2.getReg() != 0)
>>> -    // Is an immediate.
>>> -    Imm5 = getARMRegisterNumbering(MO2.getReg());
>>> -
>>> return ((Imm5 & 0x1f) << 3) | Rn;
>>> }
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec 13 21:36:38 2010
>>> @@ -236,11 +236,16 @@
>>>   int64_t Value = CE->getValue();
>>>   return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
>>> }
>>> -  bool isMemModeThumb() const {
>>> +  bool isMemModeRegThumb() const {
>>> +    if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>>> +      return false;
>>> +    return !Mem.Offset || !isa<MCConstantExpr>(Mem.Offset);
>>> +  }
>>> +  bool isMemModeImmThumb() const {
>>>   if (!isMemory() || (!Mem.OffsetIsReg && !Mem.Offset) || Mem.Writeback)
>>>     return false;
>>> 
>>> -    if (!Mem.Offset) return true;
>>> +    if (!Mem.Offset) return false;
>>> 
>>>   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>>   if (!CE) return false;
>>> @@ -324,19 +329,18 @@
>>>   }
>>> }
>>> 
>>> -  void addMemModeThumbOperands(MCInst &Inst, unsigned N) const {
>>> -    assert(N == 3 && isMemModeThumb() && "Invalid number of operands!");
>>> +  void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
>>> +    assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
>>>   Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
>>> +    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
>>> +  }
>>> 
>>> -    if (Mem.Offset) {
>>> -      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>> -      assert(CE && "Non-constant mode offset operand!");
>>> -      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>>> -      Inst.addOperand(MCOperand::CreateReg(0));
>>> -    } else {
>>> -      Inst.addOperand(MCOperand::CreateImm(0));
>>> -      Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
>>> -    }
>>> +  void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
>>> +    assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
>>> +    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
>>> +    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
>>> +    assert(CE && "Non-constant mode offset operand!");
>>> +    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
>>> }
>>> 
>>> virtual void dump(raw_ostream &OS) const;
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -482,17 +482,25 @@
>>> void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
>>>                                                raw_ostream &O) {
>>> const MCOperand &MO1 = MI->getOperand(Op);
>>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>>> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
>>> +
>>> +  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>>> +    printOperand(MI, Op, O);
>>> +    return;
>>> +  }
>>> +
>>> O << "[" << getRegisterName(MO1.getReg());
>>> -  O << ", " << getRegisterName(MO2.getReg()) << "]";
>>> +  if (unsigned RegNum = MO2.getReg())
>>> +    O << ", " << getRegisterName(RegNum);
>>> +  O << "]";
>>> }
>>> 
>>> -void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
>>> -                                                  raw_ostream &O,
>>> -                                                  unsigned Scale) {
>>> +void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
>>> +                                                    unsigned Op,
>>> +                                                    raw_ostream &O,
>>> +                                                    unsigned Scale) {
>>> const MCOperand &MO1 = MI->getOperand(Op);
>>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>>> -  const MCOperand &MO3 = MI->getOperand(Op+2);
>>> +  const MCOperand &MO2 = MI->getOperand(Op + 1);
>>> 
>>> if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
>>>   printOperand(MI, Op, O);
>>> @@ -500,36 +508,32 @@
>>> }
>>> 
>>> O << "[" << getRegisterName(MO1.getReg());
>>> -  if (MO3.getReg())
>>> -    O << ", " << getRegisterName(MO3.getReg());
>>> -  else if (unsigned ImmOffs = MO2.getImm())
>>> +  if (unsigned ImmOffs = MO2.getImm())
>>>   O << ", #" << ImmOffs * Scale;
>>> O << "]";
>>> }
>>> 
>>> -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
>>> -                                                 raw_ostream &O) {
>>> -  printThumbAddrModeRI5Operand(MI, Op, O, 1);
>>> -}
>>> -
>>> -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
>>> -                                                 raw_ostream &O) {
>>> -  printThumbAddrModeRI5Operand(MI, Op, O, 2);
>>> -}
>>> -
>>> -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
>>> -                                                 raw_ostream &O) {
>>> -  printThumbAddrModeRI5Operand(MI, Op, O, 4);
>>> +void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
>>> +                                                     unsigned Op,
>>> +                                                     raw_ostream &O) {
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
>>> +}
>>> +
>>> +void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
>>> +                                                     unsigned Op,
>>> +                                                     raw_ostream &O) {
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
>>> +}
>>> +
>>> +void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
>>> +                                                     unsigned Op,
>>> +                                                     raw_ostream &O) {
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
>>> }
>>> 
>>> void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
>>>                                                raw_ostream &O) {
>>> -  const MCOperand &MO1 = MI->getOperand(Op);
>>> -  const MCOperand &MO2 = MI->getOperand(Op+1);
>>> -  O << "[" << getRegisterName(MO1.getReg());
>>> -  if (unsigned ImmOffs = MO2.getImm())
>>> -    O << ", #" << ImmOffs*4;
>>> -  O << "]";
>>> +  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
>>> }
>>> 
>>> // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Dec 13 21:36:38 2010
>>> @@ -59,14 +59,14 @@
>>> void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
>>> void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum,
>>>                                  raw_ostream &O);
>>> -  void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum,
>>> -                                    raw_ostream &O, unsigned Scale);
>>> -  void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum,
>>> -                                   raw_ostream &O);
>>> -  void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum,
>>> -                                   raw_ostream &O);
>>> -  void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum,
>>> -                                   raw_ostream &O);
>>> +  void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum,
>>> +                                      raw_ostream &O, unsigned Scale);
>>> +  void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum,
>>> +                                       raw_ostream &O);
>>> +  void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum,
>>> +                                       raw_ostream &O);
>>> +  void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum,
>>> +                                       raw_ostream &O);
>>> void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum,
>>>                                  raw_ostream &O);
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Dec 13 21:36:38 2010
>>> @@ -644,13 +644,11 @@
>>>                               *this, dl);
>>>   }
>>> 
>>> -    MI.setDesc(TII.get(ARM::tLDR));
>>> +    MI.setDesc(TII.get(ARM::tLDRr));
>>>   MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
>>>   if (UseRR)
>>>     // Use [reg, reg] addrmode.
>>>     MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>>> -    else  // tLDR has an extra register operand.
>>> -      MI.addOperand(MachineOperand::CreateReg(0, false));
>>> } else if (Desc.mayStore()) {
>>>     VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
>>>     bool UseRR = false;
>>> @@ -666,14 +664,13 @@
>>>     } else
>>>       emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
>>>                                 *this, dl);
>>> -      MI.setDesc(TII.get(ARM::tSTR));
>>> +      MI.setDesc(TII.get(ARM::tSTRr));
>>>     MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
>>>     if (UseRR)  // Use [reg, reg] addrmode.
>>>       MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
>>> -      else // tSTR has an extra register operand.
>>> -        MI.addOperand(MachineOperand::CreateReg(0, false));
>>> -  } else
>>> +  } else {
>>>   assert(false && "Unexpected opcode!");
>>> +  }
>>> 
>>> // Add predicate back if it's needed.
>>> if (MI.getDesc().isPredicable()) {
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Mon Dec 13 21:36:38 2010
>>> @@ -105,19 +105,19 @@
>>>   // FIXME: Clean this up after splitting each Thumb load / store opcode
>>>   // into multiple ones.
>>>   { ARM::t2LDRi12,ARM::tLDRi,   ARM::tLDRspi,  5,   8,    1,   0,  0,0, 1 },
>>> -    { ARM::t2LDRs,  ARM::tLDR,    0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2LDRs,  ARM::tLDRr,   0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRBi12,ARM::tLDRBi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2LDRBs, ARM::tLDRB,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2LDRBs, ARM::tLDRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRHi12,ARM::tLDRHi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2LDRHs, ARM::tLDRH,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2LDRHs, ARM::tLDRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRSBs,ARM::tLDRSB,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2LDRSHs,ARM::tLDRSH,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2STRi12,ARM::tSTRi,   ARM::tSTRspi,  5,   8,    1,   0,  0,0, 1 },
>>> -    { ARM::t2STRs,  ARM::tSTR,    0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2STRs,  ARM::tSTRr,   0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2STRBi12,ARM::tSTRBi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2STRBs, ARM::tSTRB,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2STRBs, ARM::tSTRBr,  0,             0,   0,    1,   0,  0,0, 1 },
>>>   { ARM::t2STRHi12,ARM::tSTRHi, 0,             5,   0,    1,   0,  0,0, 1 },
>>> -    { ARM::t2STRHs, ARM::tSTRH,   0,             0,   0,    1,   0,  0,0, 1 },
>>> +    { ARM::t2STRHs, ARM::tSTRHr,  0,             0,   0,    1,   0,  0,0, 1 },
>>> 
>>>   { ARM::t2LDMIA, ARM::tLDMIA,  0,             0,   0,    1,   1,  1,1, 1 },
>>>   { ARM::t2LDMIA_RET,0,         ARM::tPOP_RET, 0,   0,    1,   1,  1,1, 1 },
>>> @@ -273,7 +273,6 @@
>>> bool HasShift = false;
>>> bool HasOffReg = true;
>>> bool isLdStMul = false;
>>> -  bool InsertImmOffset = true;
>>> unsigned Opc = Entry.NarrowOpc1;
>>> unsigned OpNum = 3; // First 'rest' of operands.
>>> uint8_t  ImmLimit = Entry.Imm1Limit;
>>> @@ -282,39 +281,41 @@
>>> default:
>>>   llvm_unreachable("Unexpected Thumb2 load / store opcode!");
>>> case ARM::t2LDRi12:
>>> -  case ARM::t2STRi12: {
>>> -    unsigned BaseReg = MI->getOperand(1).getReg();
>>> -    if (BaseReg == ARM::SP) {
>>> +  case ARM::t2STRi12:
>>> +    if (MI->getOperand(1).getReg() == ARM::SP) {
>>>     Opc = Entry.NarrowOpc2;
>>>     ImmLimit = Entry.Imm2Limit;
>>>     HasOffReg = false;
>>>   }
>>> +
>>>   Scale = 4;
>>> -    if (MI->getOperand(2).isImm())
>>> +
>>> +    if (MI->getOperand(2).isImm()) {
>>>     HasImmOffset = true;
>>> -    else {
>>> +      HasOffReg = false;
>>> +    } else {
>>>     if (Entry.WideOpc == ARM::t2LDRi12) {
>>>       Opc = ARM::tLDRpci;
>>>       OpNum = 2;
>>>     }
>>> +
>>>     HasImmOffset = false;
>>> -      InsertImmOffset = false;
>>>     HasBaseReg = false;
>>>     HasOffReg = false;
>>>   }
>>>   break;
>>> -  }
>>> case ARM::t2LDRBi12:
>>> case ARM::t2STRBi12:
>>> -    if (MI->getOperand(2).isImm())
>>> +    if (MI->getOperand(2).isImm()) {
>>>     HasImmOffset = true;
>>> -    else {
>>> +      HasOffReg = false;
>>> +    } else {
>>>     if (Entry.WideOpc == ARM::t2LDRBi12) {
>>>       Opc = ARM::tLDRpci;
>>>       OpNum = 2;
>>>     }
>>> +
>>>     HasImmOffset = false;
>>> -      InsertImmOffset = false;
>>>     HasBaseReg = false;
>>>     HasOffReg = false;
>>>   }
>>> @@ -322,15 +323,16 @@
>>> case ARM::t2LDRHi12:
>>> case ARM::t2STRHi12:
>>>   Scale = 2;
>>> -    if (MI->getOperand(2).isImm())
>>> +    if (MI->getOperand(2).isImm()) {
>>>     HasImmOffset = true;
>>> -    else {
>>> +      HasOffReg = false;
>>> +    } else {
>>>     if (Entry.WideOpc == ARM::t2LDRHi12) {
>>>       Opc = ARM::tLDRpci;
>>>       OpNum = 2;
>>>     }
>>> +
>>>     HasImmOffset = false;
>>> -      InsertImmOffset = false;
>>>     HasBaseReg = false;
>>>     HasOffReg = false;
>>>   }
>>> @@ -351,6 +353,7 @@
>>>   unsigned BaseReg = MI->getOperand(0).getReg();
>>>   if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
>>>     return false;
>>> +
>>>   // For the non-writeback version (this one), the base register must be
>>>   // one of the registers being loaded.
>>>   bool isOK = false;
>>> @@ -360,6 +363,7 @@
>>>       break;
>>>     }
>>>   }
>>> +
>>>   if (!isOK)
>>>     return false;
>>> 
>>> @@ -381,6 +385,7 @@
>>> case ARM::t2STMIA_UPD:
>>> case ARM::t2STMDB_UPD: {
>>>   OpNum = 0;
>>> +
>>>   unsigned BaseReg = MI->getOperand(1).getReg();
>>>   if (BaseReg == ARM::SP &&
>>>       (Entry.WideOpc == ARM::t2LDMIA_UPD ||
>>> @@ -392,6 +397,7 @@
>>>               Entry.WideOpc != ARM::t2STMIA_UPD)) {
>>>     return false;
>>>   }
>>> +
>>>   isLdStMul = true;
>>>   break;
>>> }
>>> @@ -402,6 +408,7 @@
>>> if (HasShift) {
>>>   OffsetReg  = MI->getOperand(2).getReg();
>>>   OffsetKill = MI->getOperand(2).isKill();
>>> +
>>>   if (MI->getOperand(3).getImm())
>>>     // Thumb1 addressing mode doesn't support shift.
>>>     return false;
>>> @@ -411,24 +418,24 @@
>>> if (HasImmOffset) {
>>>   OffsetImm = MI->getOperand(2).getImm();
>>>   unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
>>> -    if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
>>> +
>>> +    if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
>>>     // Make sure the immediate field fits.
>>>     return false;
>>> }
>>> 
>>> // Add the 16-bit load / store instruction.
>>> -  // FIXME: Thumb1 addressing mode encode both immediate and register offset.
>>> DebugLoc dl = MI->getDebugLoc();
>>> MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
>>> if (!isLdStMul) {
>>>   MIB.addOperand(MI->getOperand(0));
>>> -    if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
>>> -    if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
>>> -      // tLDRSB and tLDRSH do not have an immediate offset field. On the other
>>> -      // hand, it must have an offset register.
>>> -      // FIXME: Remove this special case.
>>> -      MIB.addImm(OffsetImm/Scale);
>>> -    }
>>> +
>>> +    if (HasBaseReg)
>>> +      MIB.addOperand(MI->getOperand(1));
>>> +
>>> +    if (HasImmOffset)
>>> +      MIB.addImm(OffsetImm / Scale);
>>> +
>>>   assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
>>> 
>>>   if (HasOffReg)
>>> 
>>> Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121747&r1=121746&r2=121747&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
>>> +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Dec 13 21:36:38 2010
>>> @@ -629,9 +629,12 @@
>>> MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
>>>                                                                 // R, I
>>> MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
>>> -  MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1");           // R, I, R
>>> -  MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2");           // R, I, R
>>> -  MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4");           // R, I, R
>>> +  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
>>> +  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
>>> +  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
>>> +  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
>>> +  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
>>> +  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
>>> MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
>>> MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
>>> MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
>>> @@ -841,9 +844,8 @@
>>> operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
>>> operandTypes.addEntry("kOperandTypeARMTBAddrMode");
>>> operandTypes.addEntry("kOperandTypeThumbITMask");
>>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
>>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
>>> -  operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
>>> +  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
>>> +  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
>>> operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
>>> operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
>>> operandTypes.addEntry("kOperandTypeThumbAddrModePC");
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 



From grosbach at apple.com  Tue Dec 14 12:46:57 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 18:46:57 -0000
Subject: [llvm-commits] [llvm] r121778 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
 lib/MC/MCMachOStreamer.cpp
Message-ID: <20101214184657.40BDC2A6C12D@llvm.org>

Author: grosbach
Date: Tue Dec 14 12:46:57 2010
New Revision: 121778

URL: http://llvm.org/viewvc/llvm-project?rev=121778&view=rev
Log:
ARM Fixups relative to thumb functions need to have the low bit of the value
set for interworking to work properly. rdar://8755956

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=121778&r1=121777&r2=121778&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Tue Dec 14 12:46:57 2010
@@ -11,6 +11,7 @@
 #define LLVM_MC_MCASSEMBLER_H
 
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/ilist.h"
 #include "llvm/ADT/ilist_node.h"
@@ -662,6 +663,15 @@
 
   std::vector<IndirectSymbolData> IndirectSymbols;
 
+  /// The set of function symbols for which a .thumb_func directive has
+  /// been seen.
+  //
+  // FIXME: We really would like this in target specific code rather than
+  // here. Maybe when the relocation stuff moves to target specific,
+  // this can go with it? The streamer would need some target specific
+  // refactoring too.
+  SmallPtrSet<const MCSymbol*, 64> ThumbFuncs;
+
   unsigned RelaxAll : 1;
   unsigned SubsectionsViaSymbols : 1;
 
@@ -738,6 +748,14 @@
   void WriteSectionData(const MCSectionData *Section, const MCAsmLayout &Layout,
                         MCObjectWriter *OW) const;
 
+  /// Check whether a given symbol has been flagged with .thumb_func.
+  bool isThumbFunc(const MCSymbol *Func) const {
+    return ThumbFuncs.count(Func);
+  }
+
+  /// Flag a function symbol as the target of a .thumb_func directive.
+  void setIsThumbFunc(const MCSymbol *Func) { ThumbFuncs.insert(Func); }
+
 public:
   /// Construct a new assembler instance.
   ///

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121778&r1=121777&r2=121778&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Dec 14 12:46:57 2010
@@ -235,12 +235,15 @@
   bool IsPCRel = Emitter.getFixupKindInfo(
     Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsPCRel;
   bool IsResolved = true;
+  bool IsThumb = false;
   if (const MCSymbolRefExpr *A = Target.getSymA()) {
     const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
     if (Sym.isDefined())
       Value += Layout.getSymbolOffset(&getSymbolData(Sym));
     else
       IsResolved = false;
+    if (isThumbFunc(&Sym))
+      IsThumb = true;
   }
   if (const MCSymbolRefExpr *B = Target.getSymB()) {
     const MCSymbol &Sym = B->getSymbol().AliasedSymbol();
@@ -263,6 +266,13 @@
       Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
   }
 
+  // ARM fixups based from a thumb function address need to have the low
+  // bit set. The actual value is always at least 16-bit aligned, so the
+  // low bit is normally clear and available for use as an ISA flag for
+  // interworking.
+  if (IsThumb)
+    Value |= 1;
+
   return IsResolved;
 }
 

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=121778&r1=121777&r2=121778&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Tue Dec 14 12:46:57 2010
@@ -142,6 +142,10 @@
 
 void MCMachOStreamer::EmitThumbFunc(MCSymbol *Func) {
   // FIXME: Flag the function ISA as thumb with DW_AT_APPLE_isa.
+
+  // Remember that the function is a thumb function. Fixup and relocation
+  // values will need adjusted.
+  getAssembler().setIsThumbFunc(Func);
 }
 
 void MCMachOStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {



From stoklund at 2pi.dk  Tue Dec 14 12:53:39 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 18:53:39 -0000
Subject: [llvm-commits] [llvm] r121780 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h lib/Target/TargetRegisterInfo.cpp
Message-ID: <20101214185339.E43FA2A6C12D@llvm.org>

Author: stoklund
Date: Tue Dec 14 12:53:39 2010
New Revision: 121780

URL: http://llvm.org/viewvc/llvm-project?rev=121780&view=rev
Log:
Add TargetRegisterInfo::printReg() to pretty-print registers.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/Target/TargetRegisterInfo.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=121780&r1=121779&r2=121780&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Dec 14 12:53:39 2010
@@ -29,6 +29,7 @@
 class MachineMove;
 class RegScavenger;
 template<class T> class SmallVectorImpl;
+class raw_ostream;
 
 /// TargetRegisterDesc - This record contains all of the information known about
 /// a particular register.  The AliasSet field (if not null) contains a pointer
@@ -321,6 +322,9 @@
     return Reg >= FirstVirtualRegister;
   }
 
+  /// printReg - Print a virtual or physical register on OS.
+  void printReg(unsigned Reg, raw_ostream &OS) const;
+
   /// getMinimalPhysRegClass - Returns the Register Class of a physical
   /// register of the given type, picking the most sub register class of
   /// the right type that contains this physreg.

Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=121780&r1=121779&r2=121780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Tue Dec 14 12:53:39 2010
@@ -17,6 +17,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/ADT/BitVector.h"
+#include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
@@ -39,6 +40,13 @@
 
 TargetRegisterInfo::~TargetRegisterInfo() {}
 
+void TargetRegisterInfo::printReg(unsigned Reg, raw_ostream &OS) const {
+  if (Reg && isVirtualRegister(Reg))
+    OS << "%reg" << Reg;
+  else
+    OS << '%' << getName(Reg);
+}
+
 /// getMinimalPhysRegClass - Returns the Register Class of a physical
 /// register of the given type, picking the most sub register class of
 /// the right type that contains this physreg.



From stoklund at 2pi.dk  Tue Dec 14 12:53:47 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 18:53:47 -0000
Subject: [llvm-commits] [llvm] r121781 - in /llvm/trunk/lib/CodeGen:
 LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocBasic.cpp
Message-ID: <20101214185347.4791B2A6C12D@llvm.org>

Author: stoklund
Date: Tue Dec 14 12:53:47 2010
New Revision: 121781

URL: http://llvm.org/viewvc/llvm-project?rev=121781&view=rev
Log:
Use TRI::printReg instead of AbstractRegisterDescription when printing
LiveIntervalUnions.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=121781&r1=121780&r2=121781&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Dec 14 12:53:47 2010
@@ -18,7 +18,10 @@
 #include "llvm/ADT/SparseBitVector.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
 #include <algorithm>
+
 using namespace llvm;
 
 
@@ -66,24 +69,16 @@
 }
 
 void
-LiveIntervalUnion::print(raw_ostream &OS,
-                         const AbstractRegisterDescription *RegDesc) const {
+LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
   OS << "LIU ";
-  if (RegDesc != NULL)
-    OS << RegDesc->getName(RepReg);
-  else {
-    OS << RepReg;
+  TRI->printReg(RepReg, OS);
+  for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
+    OS << " [" << SI.start() << ' ' << SI.stop() << "):";
+    TRI->printReg(SI.value()->reg, OS);
   }
-  for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI)
-    dbgs() << " [" << SI.start() << ' ' << SI.stop() << "):%reg"
-           << SI.value()->reg;
   OS << "\n";
 }
 
-void LiveIntervalUnion::dump(const AbstractRegisterDescription *RegDesc) const {
-  print(dbgs(), RegDesc);
-}
-
 #ifndef NDEBUG
 // Verify the live intervals in this union and add them to the visited set.
 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=121781&r1=121780&r2=121781&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Dec 14 12:53:47 2010
@@ -22,19 +22,14 @@
 
 namespace llvm {
 
+class TargetRegisterInfo;
+
 #ifndef NDEBUG
 // forward declaration
 template <unsigned Element> class SparseBitVector;
 typedef SparseBitVector<128> LiveVirtRegBitSet;
 #endif
 
-/// Abstraction to provide info for the representative register.
-class AbstractRegisterDescription {
-public:
-  virtual const char *getName(unsigned Reg) const = 0;
-  virtual ~AbstractRegisterDescription() {}
-};
-
 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
 inline bool
 overlap(const LiveRange &VRSeg,
@@ -85,10 +80,8 @@
   // Remove a live virtual register's segments from this union.
   void extract(LiveInterval &VirtReg);
 
-  void dump(const AbstractRegisterDescription *RegDesc) const;
-
-  // If tri != NULL, use it to decode RepReg
-  void print(raw_ostream &OS, const AbstractRegisterDescription *RegDesc) const;
+  // Print union, using TRI to translate register names
+  void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
 
 #ifndef NDEBUG
   // Verify the live intervals in this union and add them to the visited set.

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=121781&r1=121780&r2=121781&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Dec 14 12:53:47 2010
@@ -60,14 +60,6 @@
 const char *RegAllocBase::TimerGroupName = "Register Allocation";
 
 namespace {
-
-class PhysicalRegisterDescription : public AbstractRegisterDescription {
-  const TargetRegisterInfo *TRI;
-public:
-  PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
-  virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
-};
-
 /// RABasic provides a minimal implementation of the basic register allocation
 /// algorithm. It prioritizes live virtual registers by spill weight and spills
 /// whenever a register is unavailable. This is not practical in production but
@@ -165,8 +157,7 @@
 
   // Verify disjoint unions.
   for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
-    DEBUG(PhysicalRegisterDescription PRD(TRI);
-          PhysReg2LiveUnion[PhysReg].dump(&PRD));
+    DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
     LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
     PhysReg2LiveUnion[PhysReg].verify(VRegs);
     // Union + intersection test could be done efficiently in one pass, but



From pdox at google.com  Tue Dec 14 13:02:20 2010
From: pdox at google.com (David Meyer)
Date: Tue, 14 Dec 2010 11:02:20 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <4D07AFAB.8080907@gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
	<4D07AFAB.8080907@gmail.com>
Message-ID: <AANLkTikL5ZiLKewdc+RT7pnbrk-drtYVuioLpO3GHL2+@mail.gmail.com>

New patch attached, which respects the fact that sections have been
decoupled.

I've also attached contrived.s, which assembles in 0.284 seconds with gas,
but takes hours with llvm-mc.

It is true that this patch causes code quality to reduce ever-so-slightly,
because we might not benefit from labels compressing due to aligns shrinking
after relaxation. But that hardly seems worth the sacrifice in CPU time.

This patch causes one test fail (test/MC/MachO/relax-recompute-align.s),
which needs to be altered.


Other ideas I had but didn't implement:


> *) Have a working list of fragments that might need to be relaxed, that way
> you don't revisit every fragment on every pass.
>

I've implemented this. Would you like a patch?

Thanks,
- David Meyer
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From stoklund at 2pi.dk  Tue Dec 14 13:38:49 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 19:38:49 -0000
Subject: [llvm-commits] [llvm] r121783 - in /llvm/trunk/lib/CodeGen:
 LiveIntervalUnion.cpp LiveIntervalUnion.h RegAllocGreedy.cpp
Message-ID: <20101214193849.B8A7D2A6C12D@llvm.org>

Author: stoklund
Date: Tue Dec 14 13:38:49 2010
New Revision: 121783

URL: http://llvm.org/viewvc/llvm-project?rev=121783&view=rev
Log:
Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=121783&r1=121782&r2=121783&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Tue Dec 14 13:38:49 2010
@@ -20,8 +20,6 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
-#include <algorithm>
-
 using namespace llvm;
 
 
@@ -72,11 +70,34 @@
 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
   OS << "LIU ";
   TRI->printReg(RepReg, OS);
+  if (empty()) {
+    OS << " empty\n";
+    return;
+  }
   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
     OS << " [" << SI.start() << ' ' << SI.stop() << "):";
     TRI->printReg(SI.value()->reg, OS);
   }
-  OS << "\n";
+  OS << '\n';
+}
+
+void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
+                                          const TargetRegisterInfo *TRI) const {
+  OS << '[' << start() << ';' << stop() << ")\t";
+  interference()->print(OS, TRI);
+}
+
+void LiveIntervalUnion::Query::print(raw_ostream &OS,
+                                     const TargetRegisterInfo *TRI) {
+  OS << "Interferences with ";
+  LiveUnion->print(OS, TRI);
+  InterferenceResult IR = firstInterference();
+  while (isInterference(IR)) {
+    OS << "  ";
+    IR.print(OS, TRI);
+    OS << '\n';
+    nextInterference(IR);
+  }
 }
 
 #ifndef NDEBUG

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=121783&r1=121782&r2=121783&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Tue Dec 14 13:38:49 2010
@@ -20,6 +20,8 @@
 #include "llvm/ADT/IntervalMap.h"
 #include "llvm/CodeGen/LiveInterval.h"
 
+#include <algorithm>
+
 namespace llvm {
 
 class TargetRegisterInfo;
@@ -71,8 +73,8 @@
   SegmentIter begin() { return Segments.begin(); }
   SegmentIter end() { return Segments.end(); }
   SegmentIter find(SlotIndex x) { return Segments.find(x); }
-  bool empty() { return Segments.empty(); }
-  SlotIndex startIndex() { return Segments.start(); }
+  bool empty() const { return Segments.empty(); }
+  SlotIndex startIndex() const { return Segments.start(); }
 
   // Add a live virtual register to this union and merge its segments.
   void unify(LiveInterval &VirtReg);
@@ -106,6 +108,19 @@
     // Public default ctor.
     InterferenceResult(): VirtRegI(), LiveUnionI() {}
 
+    /// start - Return the start of the current overlap.
+    SlotIndex start() const {
+      return std::max(VirtRegI->start, LiveUnionI.start());
+    }
+
+    /// stop - Return the end of the current overlap.
+    SlotIndex stop() const {
+      return std::min(VirtRegI->end, LiveUnionI.stop());
+    }
+
+    /// interference - Return the register that is interfering here.
+    LiveInterval *interference() const { return LiveUnionI.value(); }
+
     // Note: this interface provides raw access to the iterators because the
     // result has no way to tell if it's valid to dereference them.
 
@@ -121,6 +136,8 @@
     bool operator!=(const InterferenceResult &IR) const {
       return !operator==(IR);
     }
+
+    void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
   };
 
   /// Query interferences between a single live virtual register and a live
@@ -206,6 +223,7 @@
       return InterferingVRegs;
     }
 
+    void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
   private:
     Query(const Query&);          // DO NOT IMPLEMENT
     void operator=(const Query&); // DO NOT IMPLEMENT

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121783&r1=121782&r2=121783&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Dec 14 13:38:49 2010
@@ -269,6 +269,14 @@
 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
                             SmallVectorImpl<LiveInterval*>&SplitVRegs) {
   NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
+  Order.rewind();
+  while (unsigned PhysReg = Order.next()) {
+    DEBUG({
+      query(VirtReg, PhysReg).print(dbgs(), TRI);
+      for (const unsigned *AI = TRI->getAliasSet(PhysReg); *AI; ++AI)
+        query(VirtReg, *AI).print(dbgs(), TRI);
+    });
+  }
   return 0;
 }
 



From resistor at mac.com  Tue Dec 14 13:42:53 2010
From: resistor at mac.com (Owen Anderson)
Date: Tue, 14 Dec 2010 19:42:53 -0000
Subject: [llvm-commits] [llvm] r121784 -
	/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
Message-ID: <20101214194253.E41A02A6C12D@llvm.org>

Author: resistor
Date: Tue Dec 14 13:42:53 2010
New Revision: 121784

URL: http://llvm.org/viewvc/llvm-project?rev=121784&view=rev
Log:
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121784&r1=121783&r2=121784&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Dec 14 13:42:53 2010
@@ -238,7 +238,7 @@
   case ARM::fixup_arm_thumb_cb: {
     // Offset by 4 and don't encode the lower bit, which is always 0.
     uint32_t Binary = (Value - 4) >> 1;
-    return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3);
+    return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
   }
   case ARM::fixup_arm_thumb_br:
     // Offset by 4 and don't encode the lower bit, which is always 0.



From rafael.espindola at gmail.com  Tue Dec 14 14:12:57 2010
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 14 Dec 2010 12:12:57 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <AANLkTikL5ZiLKewdc+RT7pnbrk-drtYVuioLpO3GHL2+@mail.gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
	<4D07AFAB.8080907@gmail.com>
	<AANLkTikL5ZiLKewdc+RT7pnbrk-drtYVuioLpO3GHL2+@mail.gmail.com>
Message-ID: <4D07CFC9.8060601@gmail.com>

On 10-12-14 11:02 AM, David Meyer wrote:
> New patch attached, which respects the fact that sections have been
> decoupled.
>
> I've also attached contrived.s, which assembles in 0.284 seconds with
> gas, but takes hours with llvm-mc.
>
> It is true that this patch causes code quality to reduce
> ever-so-slightly, because we might not benefit from labels compressing
> due to aligns shrinking after relaxation. But that hardly seems worth
> the sacrifice in CPU time.

Looks like this just makes PR8467 a bit more likely, no? That can/should 
probably be fixed differently, so I don't think it it is a big problem.

> This patch causes one test fail (test/MC/MachO/relax-recompute-align.s),
> which needs to be altered.
>
>
>     Other ideas I had but didn't implement:
>
>
>     *) Have a working list of fragments that might need to be relaxed,
>     that way you don't revisit every fragment on every pass.
>
>
> I've implemented this. Would you like a patch?

I have it too. Would you mind including the update to 
test/MC/MachO/relax-recompute-align.s in this patch?

What I would propose is:

*) Give the other guys till the end of today to say if they have 
anything against updating test/MC/MachO/relax-recompute-align.s.

*) Can you try your patch in the .s testcase in PR8711?

*) If this patch gives you a nice speed up in the attached test and 
doesn't slow down the one in 8711, commit it.

*) I will try the "relax align" on top of it and commit if it still 
looks like an improvement.

Sounds good?

> Thanks,
> - David Meyer

Cheers,
Rafael

From grosbach at apple.com  Tue Dec 14 14:45:47 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 20:45:47 -0000
Subject: [llvm-commits] [llvm] r121788 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20101214204547.C98782A6C12D@llvm.org>

Author: grosbach
Date: Tue Dec 14 14:45:47 2010
New Revision: 121788

URL: http://llvm.org/viewvc/llvm-project?rev=121788&view=rev
Log:
Make sure to propagate the predicate operands for LEApcrel to ADR.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121788&r1=121787&r2=121788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Dec 14 14:45:47 2010
@@ -749,8 +749,8 @@
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
     // Add predicate operands.
-    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
-    TmpInst.addOperand(MCOperand::CreateReg(0));
+    TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
+    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }
@@ -768,8 +768,8 @@
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
     // Add predicate operands.
-    TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
-    TmpInst.addOperand(MCOperand::CreateReg(0));
+    TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
+    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }



From grosbach at apple.com  Tue Dec 14 14:46:39 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 20:46:39 -0000
Subject: [llvm-commits] [llvm] r121789 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20101214204639.B56AE2A6C12D@llvm.org>

Author: grosbach
Date: Tue Dec 14 14:46:39 2010
New Revision: 121789

URL: http://llvm.org/viewvc/llvm-project?rev=121789&view=rev
Log:
trailing whitespace.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121789&r1=121788&r2=121789&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Dec 14 14:46:39 2010
@@ -1144,7 +1144,7 @@
   let Inst{20} = 0;
   let Inst{19-16} = 0b1111; // Rn
   let Inst{15} = 0;
-  
+
   bits<4> Rd;
   bits<13> addr;
   let Inst{11-8} = Rd;
@@ -2831,7 +2831,7 @@
   let Inst{26-20} = 0b0000101;
   let Inst{11-8} = 0b1111;
   let Inst{7-0} = 0b00000000; // imm8 = 0
-  
+
   bits<4> Rn;
   bits<4> Rt;
   let Inst{19-16} = Rn;
@@ -2860,7 +2860,7 @@
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0000100;
   let Inst{7-0} = 0b00000000; // imm8 = 0
-  
+
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rt;
@@ -3032,7 +3032,7 @@
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
   let Inst{12} = 0;
-  
+
   bits<4> p;
   let Inst{25-22} = p;
 



From grosbach at apple.com  Tue Dec 14 15:10:47 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 21:10:47 -0000
Subject: [llvm-commits] [llvm] r121790 -
	/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <20101214211047.76ABC2A6C12D@llvm.org>

Author: grosbach
Date: Tue Dec 14 15:10:47 2010
New Revision: 121790

URL: http://llvm.org/viewvc/llvm-project?rev=121790&view=rev
Log:
Refactor a bit for legibility.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121790&r1=121789&r2=121790&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Dec 14 15:10:47 2010
@@ -713,6 +713,18 @@
   printOperand(MI, NOps-2, OS);
 }
 
+static void populateADROperands(MCInst &Inst, unsigned Dest,
+                                const MCSymbol *Label,
+                                unsigned pred, unsigned ccreg,
+                                MCContext &Ctx) {
+  const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
+  Inst.addOperand(MCOperand::CreateReg(Dest));
+  Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
+  // Add predicate operands.
+  Inst.addOperand(MCOperand::CreateImm(pred));
+  Inst.addOperand(MCOperand::CreateReg(ccreg));
+}
+
 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default: break;
@@ -734,42 +746,29 @@
     }
     return;
   }
-  case ARM::t2LEApcrel:
-  case ARM::LEApcrel: {
+  case ARM::LEApcrel:
+  case ARM::t2LEApcrel: {
     // FIXME: Need to also handle globals and externals
-    assert (MI->getOperand(1).isCPI());
-    unsigned LabelId = MI->getOperand(1).getIndex();
-    MCSymbol *Sym = GetCPISymbol(LabelId);
-    const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Sym, OutContext);
     MCInst TmpInst;
-    if (MI->getOpcode() == ARM::LEApcrel)
-      TmpInst.setOpcode(ARM::ADR);
-    else
-      TmpInst.setOpcode(ARM::t2ADR);
-    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
-    TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
-    // Add predicate operands.
-    TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
-    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
+    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel
+                      ? ARM::t2ADR : ARM::ADR);
+    populateADROperands(TmpInst, MI->getOperand(0).getReg(),
+                        GetCPISymbol(MI->getOperand(1).getIndex()),
+                        MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
+                        OutContext);
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }
   case ARM::t2LEApcrelJT:
   case ARM::LEApcrelJT: {
-    unsigned JTI = MI->getOperand(1).getIndex();
-    unsigned Id = MI->getOperand(2).getImm();
-    MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, Id);
-    const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(JTISymbol, OutContext);
     MCInst TmpInst;
-    if (MI->getOpcode() == ARM::LEApcrelJT)
-      TmpInst.setOpcode(ARM::ADR);
-    else
-      TmpInst.setOpcode(ARM::t2ADR);
-    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
-    TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
-    // Add predicate operands.
-    TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
-    TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
+    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT
+                      ? ARM::t2ADR : ARM::ADR);
+    populateADROperands(TmpInst, MI->getOperand(0).getReg(),
+                      GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
+                                                  MI->getOperand(2).getImm()),
+                      MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
+                      OutContext);
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }



From matthewbg at google.com  Tue Dec 14 15:14:56 2010
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Tue, 14 Dec 2010 21:14:56 -0000
Subject: [llvm-commits] [llvm] r121791 -
	/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Message-ID: <20101214211456.263F62A6C12E@llvm.org>

Author: matthewbg
Date: Tue Dec 14 15:14:55 2010
New Revision: 121791

URL: http://llvm.org/viewvc/llvm-project?rev=121791&view=rev
Log:
Move debugging code entirely within DEBUG(). Silences an unused variable
warning in the opt build.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121791&r1=121790&r2=121791&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Dec 14 15:14:55 2010
@@ -269,14 +269,14 @@
 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
                             SmallVectorImpl<LiveInterval*>&SplitVRegs) {
   NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
-  Order.rewind();
-  while (unsigned PhysReg = Order.next()) {
-    DEBUG({
-      query(VirtReg, PhysReg).print(dbgs(), TRI);
-      for (const unsigned *AI = TRI->getAliasSet(PhysReg); *AI; ++AI)
-        query(VirtReg, *AI).print(dbgs(), TRI);
-    });
-  }
+  DEBUG({
+    Order.rewind();
+    while (unsigned PhysReg = Order.next()) {
+        query(VirtReg, PhysReg).print(dbgs(), TRI);
+        for (const unsigned *AI = TRI->getAliasSet(PhysReg); *AI; ++AI)
+          query(VirtReg, *AI).print(dbgs(), TRI);
+    }
+  });
   return 0;
 }
 



From grosbach at apple.com  Tue Dec 14 15:28:30 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 21:28:30 -0000
Subject: [llvm-commits] [llvm] r121792 -
	/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
Message-ID: <20101214212830.19F9B2A6C12D@llvm.org>

Author: grosbach
Date: Tue Dec 14 15:28:29 2010
New Revision: 121792

URL: http://llvm.org/viewvc/llvm-project?rev=121792&view=rev
Log:
trailing whitespace

Modified:
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121792&r1=121791&r2=121792&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Dec 14 15:28:29 2010
@@ -18,11 +18,11 @@
   // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
   // addresses
   fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
-  
+
   // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
   // the 16-bit halfwords reordered.
   fixup_t2_ldst_pcrel_12,
-  
+
   // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
   // used in VFP instructions where the lower 2 bits are not encoded
   // (so it's encoded as an 8-bit immediate).
@@ -39,10 +39,10 @@
   // fixup_arm_branch - 24-bit PC relative relocation for direct branch
   // instructions.
   fixup_arm_branch,
-  // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct 
+  // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
   // uconditional branch instructions.
   fixup_t2_condbranch,
-  // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct 
+  // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
   // branch unconditional branch instructions.
   fixup_t2_uncondbranch,
 



From evan.cheng at apple.com  Tue Dec 14 15:34:53 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 14 Dec 2010 21:34:53 -0000
Subject: [llvm-commits] [llvm] r121793 - in /llvm/trunk:
 lib/CodeGen/TwoAddressInstructionPass.cpp
 test/CodeGen/X86/commute-two-addr.ll
Message-ID: <20101214213453.7619F2A6C12D@llvm.org>

Author: evancheng
Date: Tue Dec 14 15:34:53 2010
New Revision: 121793

URL: http://llvm.org/viewvc/llvm-project?rev=121793&view=rev
Log:
Fix a minor bug in two-address pass. It was missing a commute opportunity.
regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/test/CodeGen/X86/commute-two-addr.ll

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=121793&r1=121792&r2=121793&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Dec 14 15:34:53 2010
@@ -554,7 +554,8 @@
   unsigned ToRegB = getMappedReg(regB, DstRegMap);
   unsigned ToRegC = getMappedReg(regC, DstRegMap);
   if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
-      (regsAreCompatible(FromRegB, ToRegC, TRI) ||
+      ((!FromRegC && !ToRegC) ||
+       regsAreCompatible(FromRegB, ToRegC, TRI) ||
        regsAreCompatible(FromRegC, ToRegB, TRI)))
     return true;
 

Modified: llvm/trunk/test/CodeGen/X86/commute-two-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-two-addr.ll?rev=121793&r1=121792&r2=121793&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/commute-two-addr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/commute-two-addr.ll Tue Dec 14 15:34:53 2010
@@ -2,24 +2,62 @@
 ; insertion of register-register copies.
 
 ; Make sure there are only 3 mov's for each testcase
-; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   grep {\\\<mov\\\>} | count 6
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu   | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN
 
 
-target triple = "i686-pc-linux-gnu"
 @G = external global i32                ; <i32*> [#uses=2]
 
 declare void @ext(i32)
 
-define i32 @add_test(i32 %X, i32 %Y) {
+define i32 @t1(i32 %X, i32 %Y) nounwind {
+; LINUX: t1:
+; LINUX: movl 4(%esp), %eax
+; LINUX: movl 8(%esp), %ecx
+; LINUX: addl %eax, %ecx
+; LINUX: movl %ecx, G
         %Z = add i32 %X, %Y             ; <i32> [#uses=1]
         store i32 %Z, i32* @G
         ret i32 %X
 }
 
-define i32 @xor_test(i32 %X, i32 %Y) {
+define i32 @t2(i32 %X, i32 %Y) nounwind {
+; LINUX: t2:
+; LINUX: movl 4(%esp), %eax
+; LINUX: movl 8(%esp), %ecx
+; LINUX: xorl %eax, %ecx
+; LINUX: movl %ecx, G
         %Z = xor i32 %X, %Y             ; <i32> [#uses=1]
         store i32 %Z, i32* @G
         ret i32 %X
 }
 
+; rdar://8762995
+%0 = type { i64, i32 }
+
+define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
+entry:
+; DARWIN: t3:
+; DARWIN: shlq $32, %rcx
+; DARWIN-NOT: leaq
+; DARWIN: orq %rcx, %rax
+; DARWIN-NOT: mov
+; DARWIN: shll $16
+  %tmp21 = zext i32 %lb to i64
+  %tmp23 = zext i32 %ub to i64
+  %tmp24 = shl i64 %tmp23, 32
+  %ins26 = or i64 %tmp24, %tmp21
+  %tmp28 = zext i8 %has_lb to i32
+  %tmp33 = zext i8 %has_ub to i32
+  %tmp34 = shl i32 %tmp33, 8
+  %tmp38 = zext i8 %lb_inclusive to i32
+  %tmp39 = shl i32 %tmp38, 16
+  %tmp43 = zext i8 %ub_inclusive to i32
+  %tmp44 = shl i32 %tmp43, 24
+  %ins31 = or i32 %tmp39, %tmp28
+  %ins36 = or i32 %ins31, %tmp34
+  %ins46 = or i32 %ins36, %tmp44
+  %tmp16 = insertvalue %0 undef, i64 %ins26, 0
+  %tmp19 = insertvalue %0 %tmp16, i32 %ins46, 1
+  ret %0 %tmp19
+}



From greened at obbligato.org  Tue Dec 14 15:41:16 2010
From: greened at obbligato.org (David A. Greene)
Date: Tue, 14 Dec 2010 15:41:16 -0600
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	(Jason Kim's message of "Mon, 13 Dec 2010 12:37:26 -0800")
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
Message-ID: <nngy67sm3r7.fsf@royale.us.cray.com>

Jason Kim <jasonwkim at google.com> writes:

> I think the regulars want the patches posted on llvm-commits for review
> However, taking a  look at the second one (lit2.patch, attached),
> there's couple of utilities missing in the list - like elf-dump etc.

Ping?  Patch #3 on the bug is probably the one to apply.  I've copied it below.

                                  -Dave

Index: test/lit.cfg
===================================================================
--- test/lit.cfg	(revision 121488)
+++ test/lit.cfg	(working copy)
@@ -148,6 +148,35 @@
     else:
         config.substitutions.append(('%' + sub, site_exp[sub]))
 
+# NOTE: Poor man's regexp here.  Only ^ and $ are supported.
+
+# Replace command at the start of the line.
+for sub in ['^llc', '^lli', '^tblgen', '^bugpoint', '^llvmc',
+            '^llvm-ar', '^llvm-as', '^llvm-bcanalyzer', '^llvm-dis',
+            '^llvm-extract', '^llvm-ld', '^llvm-link', '^llvm-nm',
+            '^llvm-prof', '^llvm-ranlib', '^llvm-mc', '^opt',
+            '^FileCheck']:
+    config.substitutions.append((sub,
+                                 llvm_tools_dir + '/' + sub[1:]))
+
+# Replace command at the end of the line.
+for sub in [' llc$', ' lli$', ' tblgen$', ' bugpoint$', ' llvmc$',
+            ' llvm-ar$', ' llvm-as$', ' llvm-bcanalyzer$', ' llvm-dis$',
+            ' llvm-extract$', ' llvm-ld$', ' llvm-link$', ' llvm-nm$',
+            ' llvm-prof$', ' llvm-ranlib$', ' llvm-mc$', ' opt$',
+            ' FileCheck$']:
+    config.substitutions.append((sub,
+                                 ' ' + llvm_tools_dir + '/' + sub[1:-1]))
+
+# Replace command in the middle of the pipeline.
+for sub in [' llc ', ' lli ', ' tblgen ', ' bugpoint ', ' llvmc ',
+            ' llvm-ar ', ' llvm-as ', ' llvm-bcanalyzer ', ' llvm-dis ',
+            ' llvm-extract ', ' llvm-ld ', ' llvm-link ', ' llvm-nm ',
+            ' llvm-prof ', ' llvm-ranlib ', ' llvm-mc ', ' opt ',
+            ' FileCheck ']:
+    config.substitutions.append((sub,
+                                 ' ' + llvm_tools_dir + '/' + sub[1:-1] + ' '))
+
 excludes = []
 
 # Provide target_triple for use in XFAIL and XTARGET.
Index: utils/lit/lit/TestRunner.py
===================================================================
--- utils/lit/lit/TestRunner.py	(revision 121488)
+++ utils/lit/lit/TestRunner.py	(working copy)
@@ -8,6 +8,10 @@
 import platform
 import tempfile
 
+# Utility to replace a string starting from the end.
+def rreplace(s, old, new, count):
+    return (s[::-1].replace(old[::-1], new[::-1], count))[::-1]
+
 class InternalShellError(Exception):
     def __init__(self, command, message):
         self.command = command
@@ -448,7 +452,18 @@
     def processLine(ln):
         # Apply substitutions
         for a,b in substitutions:
-            ln = ln.replace(a,b)
+            # Poor man's regexp: support ^ and $.
+            if a.startswith('^') and a.endswith('$'):
+                if ln == a[1:-1]:
+                    ln = b
+            elif a.startswith('^'):
+                if ln.startswith(a[1:]):
+                    ln.replace(a[1:],b,1)
+            elif a.endswith('$'):
+                if ln.endswith(a[:-1]):
+                    ln = rreplace(ln,a[:-1],b,1)
+            else:
+                ln = ln.replace(a,b)
 
         # Strip the trailing newline and any extra whitespace.
         return ln.strip()

From isanbard at gmail.com  Tue Dec 14 16:10:49 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 22:10:49 -0000
Subject: [llvm-commits] [llvm] r121794 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20101214221049.995142A6C12D@llvm.org>

Author: void
Date: Tue Dec 14 16:10:49 2010
New Revision: 121794

URL: http://llvm.org/viewvc/llvm-project?rev=121794&view=rev
Log:
Multiclassify the LDR/STR encoding patterns. The only functionality difference
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121794&r1=121793&r2=121794&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 14 16:10:49 2010
@@ -606,42 +606,59 @@
 //  Load Store Instructions.
 //
 
+// Loads: reg/reg and reg/imm5
 let canFoldAsLoad = 1, isReMaterializable = 1 in
-def tLDRr :                      // A8.6.60
-  T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
-                 AddrModeT1_4, IIC_iLoad_r,
-                 "ldr", "\t$Rt, $addr",
-                 [(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
-
-def tLDRi :                     // A8.6.57
-  T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
-                    AddrModeT1_4, IIC_iLoad_i,
-                    "ldr", "\t$Rt, $addr",
-                    [(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
-
-def tLDRBr :                    // A8.6.64
-  T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
-                 AddrModeT1_1, IIC_iLoad_bh_r,
-                 "ldrb", "\t$Rt, $addr",
-                 [(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
-
-def tLDRBi :                    // A8.6.61
-  T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
-                    AddrModeT1_1, IIC_iLoad_bh_i,
-                    "ldrb", "\t$Rt, $addr",
-                    [(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
-
-def tLDRHr :                    // A8.6.76
-  T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
-                 AddrModeT1_2, IIC_iLoad_bh_r,
-                 "ldrh", "\t$Rt, $addr",
-                 [(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
-
-def tLDRHi :                    // A8.6.73
-  T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
-                    AddrModeT1_2, IIC_iLoad_bh_i,
-                    "ldrh", "\t$Rt, $addr",
-                    [(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
+multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
+                              Operand AddrMode_r, Operand AddrMode_i,
+                              AddrMode am, InstrItinClass itin_r,
+                              InstrItinClass itin_i, string asm,
+                              PatFrag opnode> {
+  def r :
+    T1pILdStEncode<reg_opc,
+                   (outs tGPR:$Rt), (ins AddrMode_r:$addr),
+                   am, itin_r, asm, "\t$Rt, $addr",
+                   [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
+  def i :
+    T1pILdStEncodeImm<imm_opc, 1 /* Load */,
+                      (outs tGPR:$Rt), (ins AddrMode_i:$addr),
+                      am, itin_i, asm, "\t$Rt, $addr",
+                      [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
+}
+// Stores: reg/reg and reg/imm5
+multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
+                              Operand AddrMode_r, Operand AddrMode_i,
+                              AddrMode am, InstrItinClass itin_r,
+                              InstrItinClass itin_i, string asm,
+                              PatFrag opnode> {
+  def r :
+    T1pILdStEncode<reg_opc,
+                   (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
+                   am, itin_r, asm, "\t$Rt, $addr",
+                   [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
+  def i :
+    T1pILdStEncodeImm<imm_opc, 0 /* Store */,
+                      (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
+                      am, itin_i, asm, "\t$Rt, $addr",
+                      [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
+}
+
+// A8.6.57 & A8.6.60
+defm tLDR  : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
+                                t_addrmode_is4, AddrModeT1_4,
+                                IIC_iLoad_r, IIC_iLoad_i, "ldr",
+                                UnOpFrag<(load node:$Src)>>;
+
+// A8.6.64 & A8.6.61
+defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
+                                t_addrmode_is1, AddrModeT1_1,
+                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
+                                UnOpFrag<(zextloadi8 node:$Src)>>;
+
+// A8.6.76 & A8.6.73
+defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
+                                t_addrmode_is2, AddrModeT1_2,
+                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
+                                UnOpFrag<(zextloadi16 node:$Src)>>;
 
 let AddedComplexity = 10 in
 def tLDRSB :                    // A8.6.80
@@ -703,41 +720,24 @@
   let Inst{7-0}  = addr;
 }
 
-def tSTRr :                     // A8.6.194
-  T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
-                 AddrModeT1_4, IIC_iStore_r,
-                 "str", "\t$Rt, $addr",
-                 [(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
-
-def tSTRi :                     // A8.6.192
-  T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
-                    AddrModeT1_4, IIC_iStore_i,
-                    "str", "\t$Rt, $addr",
-                    [(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
+// A8.6.194 & A8.6.192
+defm tSTR  : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
+                                t_addrmode_is4, AddrModeT1_4,
+                                IIC_iStore_r, IIC_iStore_i, "str",
+                                BinOpFrag<(store node:$LHS, node:$RHS)>>;
+
+// A8.6.197 & A8.6.195
+defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
+                                t_addrmode_is1, AddrModeT1_1,
+                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
+                                BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
+
+// A8.6.207 & A8.6.205
+defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
+                                t_addrmode_is2, AddrModeT1_2,
+                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
+                                BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
 
-def tSTRBr :                    // A8.6.197
-  T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
-                 AddrModeT1_1, IIC_iStore_bh_r,
-                 "strb", "\t$Rt, $addr",
-                 [(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
-
-def tSTRBi :                    // A8.6.195
-  T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
-                    AddrModeT1_1, IIC_iStore_bh_i,
-                    "strb", "\t$Rt, $addr",
-                    [(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
-
-def tSTRHr :                    // A8.6.207
-  T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
-                 AddrModeT1_2, IIC_iStore_bh_r,
-                 "strh", "\t$Rt, $addr",
-                 [(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
-
-def tSTRHi :                    // A8.6.205
-  T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
-                    AddrModeT1_2, IIC_iStore_bh_i,
-                    "strh", "\t$Rt, $addr",
-                    [(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
 
 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
                     "str", "\t$Rt, $addr",



From isanbard at gmail.com  Tue Dec 14 16:26:49 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 22:26:49 -0000
Subject: [llvm-commits] [llvm] r121797 -
	/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
Message-ID: <20101214222649.B275E2A6C12D@llvm.org>

Author: void
Date: Tue Dec 14 16:26:49 2010
New Revision: 121797

URL: http://llvm.org/viewvc/llvm-project?rev=121797&view=rev
Log:
Fix comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121797&r1=121796&r2=121797&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Dec 14 16:26:49 2010
@@ -61,7 +61,7 @@
   // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
   fixup_arm_thumb_cp,
 
-  // fixup_arm_thumb_bcc - Fixup for Thumb load/store from constant pool instrs.
+  // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
   fixup_arm_thumb_bcc,
 
   // The next two are for the movt/movw pair



From grosbach at apple.com  Tue Dec 14 16:28:03 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 22:28:03 -0000
Subject: [llvm-commits] [llvm] r121798 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp
 lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMFixupKinds.h
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMMCCodeEmitter.cpp
 utils/TableGen/ARMDecoderEmitter.cpp utils/TableGen/EDEmitter.cpp
Message-ID: <20101214222804.08A712A6C12F@llvm.org>

Author: grosbach
Date: Tue Dec 14 16:28:03 2010
New Revision: 121798

URL: http://llvm.org/viewvc/llvm-project?rev=121798&view=rev
Log:
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Dec 14 16:28:03 2010
@@ -123,6 +123,8 @@
 
     return Value;
   }
+  case ARM::fixup_thumb_adr_pcrel_10:
+    return ((Value - 4) >> 2) & 0xff;
   case ARM::fixup_arm_adr_pcrel_12: {
     // ARM PC-relative values are offset by 8.
     Value -= 8;
@@ -358,6 +360,7 @@
 
   case ARM::fixup_arm_thumb_bcc:
   case ARM::fixup_arm_thumb_cp:
+  case ARM::fixup_thumb_adr_pcrel_10:
     return 1;
 
   case ARM::fixup_arm_thumb_br:

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Dec 14 16:28:03 2010
@@ -747,11 +747,13 @@
     return;
   }
   case ARM::LEApcrel:
+  case ARM::tLEApcrel:
   case ARM::t2LEApcrel: {
     // FIXME: Need to also handle globals and externals
     MCInst TmpInst;
-    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel
-                      ? ARM::t2ADR : ARM::ADR);
+    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
+                      : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
+                         : ARM::ADR));
     populateADROperands(TmpInst, MI->getOperand(0).getReg(),
                         GetCPISymbol(MI->getOperand(1).getIndex()),
                         MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
@@ -759,11 +761,13 @@
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }
-  case ARM::t2LEApcrelJT:
-  case ARM::LEApcrelJT: {
+  case ARM::LEApcrelJT:
+  case ARM::tLEApcrelJT:
+  case ARM::t2LEApcrelJT: {
     MCInst TmpInst;
-    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT
-                      ? ARM::t2ADR : ARM::ADR);
+    TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
+                      : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
+                         : ARM::ADR));
     populateADROperands(TmpInst, MI->getOperand(0).getReg(),
                       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
                                                   MI->getOperand(2).getImm()),

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Dec 14 16:28:03 2010
@@ -171,6 +171,8 @@
       const { return 0; }
     unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
     unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Dec 14 16:28:03 2010
@@ -30,6 +30,10 @@
   // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
   // the short-swapped encoding of Thumb2 instructions.
   fixup_t2_pcrel_10,
+  // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
+  // addresses where the lower 2 bits are not encoded (so it's encoded as an
+  // 8-bit immediate).
+  fixup_thumb_adr_pcrel_10,
   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
   // instruction.
   fixup_arm_adr_pcrel_12,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 14 16:28:03 2010
@@ -67,6 +67,11 @@
   return CurDAG->getTargetConstant(V, MVT::i32);
 }]>;
 
+// ADR instruction labels.
+def t_adrlabel : Operand<i32> {
+  let EncoderMethod = "getThumbAdrLabelOpValue";
+}
+
 // Scaled 4 immediate.
 def t_imm_s4 : Operand<i32> {
   let PrintMethod = "printThumbS4ImmOperand";
@@ -1303,26 +1308,24 @@
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-let neverHasSideEffects = 1, isReMaterializable = 1 in
-def tLEApcrel : T1I<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
-                    "adr${p}\t$Rd, #$label", []>,
-                T1Encoding<{1,0,1,0,0,?}> {
-  // A6.2 & A8.6.10
-  bits<3> Rd;
-  let Inst{10-8} = Rd;
-  // FIXME: Add label encoding/fixup
-}
 
-def tLEApcrelJT : T1I<(outs tGPR:$Rd),
-                      (ins i32imm:$label, nohash_imm:$id, pred:$p),
-                      IIC_iALUi, "adr${p}\t$Rd, #${label}_${id}", []>,
-                  T1Encoding<{1,0,1,0,0,?}> {
-  // A6.2 & A8.6.10
+def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
+               IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
+               T1Encoding<{1,0,1,0,0,?}> {
   bits<3> Rd;
+  bits<8> addr;
   let Inst{10-8} = Rd;
-  // FIXME: Add label encoding/fixup
+  let Inst{7-0} = addr;
 }
 
+let neverHasSideEffects = 1, isReMaterializable = 1 in
+def tLEApcrel   : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
+                              Size2Bytes, IIC_iALUi, []>;
+
+def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
+                              (ins i32imm:$label, nohash_imm:$id, pred:$p),
+                              Size2Bytes, IIC_iALUi, []>;
+
 //===----------------------------------------------------------------------===//
 // TLS Instructions
 //

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Dec 14 16:28:03 2010
@@ -55,6 +55,7 @@
 { "fixup_arm_pcrel_10",      1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
+{ "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
@@ -135,6 +136,8 @@
   /// ADR label target.
   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
                               SmallVectorImpl<MCFixup> &Fixups) const;
+  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
                               SmallVectorImpl<MCFixup> &Fixups) const;
   
@@ -559,6 +562,16 @@
                                   Fixups);
 }
 
+/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
+/// target.
+uint32_t ARMMCCodeEmitter::
+getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
+  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
+  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
+                                  Fixups);
+}
+
 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
 /// operand.
 uint32_t ARMMCCodeEmitter::

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Tue Dec 14 16:28:03 2010
@@ -1679,12 +1679,8 @@
     if (Name == "tTPsoft" || Name == "t2TPsoft")
       return false;
 
-    // Ignore tLEApcrel and tLEApcrelJT, prefer tADDrPCi.
-    if (Name == "tLEApcrel" || Name == "tLEApcrelJT")
-      return false;
-
-    // Ignore t2LEApcrel, prefer the generic t2ADD* for disassembly printing.
-    if (Name == "t2LEApcrel")
+    // Ignore tADR, prefer tADDrPCi.
+    if (Name == "tADR")
       return false;
 
     // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr.
@@ -1711,13 +1707,12 @@
     //   tSpill conflicts with tSTRspi
     //   tLDRcp conflicts with tLDRspi
     //   tRestore conflicts with tLDRspi
-    //   t2LEApcrelJT conflicts with t2LEApcrel
     //   t2MOVCCi16 conflicts with tMOVi16
     if (Name == "tBfar" ||
         Name == "tPOP_RET" || Name == "t2LDMIA_RET" ||
         Name == "tMOVCCi" || Name == "tMOVCCr" ||
         Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" ||
-        Name == "t2LEApcrelJT" || Name == "t2MOVCCi16")
+        Name == "t2MOVCCi16")
       return false;
   }
 

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121798&r1=121797&r2=121798&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Dec 14 16:28:03 2010
@@ -584,6 +584,7 @@
   IMM("t_imm_s4");
   IMM("pclabel");
   IMM("adrlabel");
+  IMM("t_adrlabel");
   IMM("t2adrlabel");
   IMM("shift_imm");
   IMM("neon_vcvt_imm32");



From stoklund at 2pi.dk  Tue Dec 14 17:03:43 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 23:03:43 -0000
Subject: [llvm-commits] [llvm] r121800 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h
 utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <20101214230343.2B21B2A6C12C@llvm.org>

Author: stoklund
Date: Tue Dec 14 17:03:42 2010
New Revision: 121800

URL: http://llvm.org/viewvc/llvm-project?rev=121800&view=rev
Log:
Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=121800&r1=121799&r2=121800&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Dec 14 17:03:42 2010
@@ -32,19 +32,18 @@
 class raw_ostream;
 
 /// TargetRegisterDesc - This record contains all of the information known about
-/// a particular register.  The AliasSet field (if not null) contains a pointer
-/// to a Zero terminated array of registers that this register aliases.  This is
-/// needed for architectures like X86 which have AL alias AX alias EAX.
-/// Registers that this does not apply to simply should set this to null.
-/// The SubRegs field is a zero terminated array of registers that are
-/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
-/// The SuperRegs field is a zero terminated array of registers that are
+/// a particular register.  The Overlaps field contains a pointer to a zero
+/// terminated array of registers that this register aliases, starting with
+/// itself. This is needed for architectures like X86 which have AL alias AX
+/// alias EAX. The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
+/// AX. The SuperRegs field is a zero terminated array of registers that are
 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
 /// of AX.
 ///
 struct TargetRegisterDesc {
   const char     *Name;         // Printable name for the reg (for debugging)
-  const unsigned *AliasSet;     // Register Alias Set, described above
+  const unsigned *Overlaps;     // Overlapping registers, described above
   const unsigned *SubRegs;      // Sub-register set, described above
   const unsigned *SuperRegs;    // Super-register set, described above
 };
@@ -355,7 +354,17 @@
   /// terminated.
   ///
   const unsigned *getAliasSet(unsigned RegNo) const {
-    return get(RegNo).AliasSet;
+    // The Overlaps set always begins with Reg itself.
+    return get(RegNo).Overlaps + 1;
+  }
+
+  /// getOverlaps - Return a list of registers that overlap Reg, including
+  /// itself. This is the same as the alias set except Reg is included in the
+  /// list.
+  /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
+  ///
+  const unsigned *getOverlaps(unsigned RegNo) const {
+    return get(RegNo).Overlaps;
   }
 
   /// getSubRegisters - Return the list of registers that are sub-registers of

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=121800&r1=121799&r2=121800&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Dec 14 17:03:42 2010
@@ -777,17 +777,13 @@
   delete [] AliasesHashTable;
 
   if (!RegisterAliases.empty())
-    OS << "\n\n  // Register Alias Sets...\n";
+    OS << "\n\n  // Register Overlap Lists...\n";
 
-  // Emit the empty alias list
-  OS << "  const unsigned Empty_AliasSet[] = { 0 };\n";
-  // Loop over all of the registers which have aliases, emitting the alias list
-  // to memory.
+  // Emit an overlap list for all registers.
   for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
          I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
-    if (I->second.empty())
-      continue;
-    OS << "  const unsigned " << I->first->getName() << "_AliasSet[] = { ";
+    OS << "  const unsigned " << I->first->getName() << "_Overlaps[] = { "
+       << getQualifiedName(I->first) << ", ";
     for (std::set<Record*>::iterator ASI = I->second.begin(),
            E = I->second.end(); ASI != E; ++ASI)
       OS << getQualifiedName(*ASI) << ", ";
@@ -849,11 +845,7 @@
   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     const CodeGenRegister &Reg = Regs[i];
     OS << "    { \"";
-    OS << Reg.getName() << "\",\t";
-    if (!RegisterAliases[Reg.TheDef].empty())
-      OS << Reg.getName() << "_AliasSet,\t";
-    else
-      OS << "Empty_AliasSet,\t";
+    OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
     if (!RegisterSubRegs[Reg.TheDef].empty())
       OS << Reg.getName() << "_SubRegsSet,\t";
     else



From stoklund at 2pi.dk  Tue Dec 14 17:10:48 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 23:10:48 -0000
Subject: [llvm-commits] [llvm] r121801 -
	/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
Message-ID: <20101214231048.528852A6C12C@llvm.org>

Author: stoklund
Date: Tue Dec 14 17:10:48 2010
New Revision: 121801

URL: http://llvm.org/viewvc/llvm-project?rev=121801&view=rev
Log:
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=121801&r1=121800&r2=121801&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Dec 14 17:10:48 2010
@@ -285,12 +285,9 @@
 // physical register. Return the interfering register.
 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
                                                 unsigned PhysReg) {
-  if (query(VirtReg, PhysReg).checkInterference())
-    return PhysReg;
-  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
+  for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
     if (query(VirtReg, *AliasI).checkInterference())
       return *AliasI;
-  }
   return 0;
 }
 
@@ -331,15 +328,9 @@
                                  SmallVectorImpl<LiveInterval*> &SplitVRegs) {
   // Record each interference and determine if all are spillable before mutating
   // either the union or live intervals.
-
-  // Collect interferences assigned to the requested physical register.
-  LiveIntervalUnion::Query &QPreg = query(VirtReg, PhysReg);
-  unsigned NumInterferences = QPreg.collectInterferingVRegs();
-  if (QPreg.seenUnspillableVReg()) {
-    return false;
-  }
+  unsigned NumInterferences = 0;
   // Collect interferences assigned to any alias of the physical register.
-  for (const unsigned *asI = TRI->getAliasSet(PhysReg); *asI; ++asI) {
+  for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
     LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
     NumInterferences += QAlias.collectInterferingVRegs();
     if (QAlias.seenUnspillableVReg()) {
@@ -351,8 +342,7 @@
   assert(NumInterferences > 0 && "expect interference");
 
   // Spill each interfering vreg allocated to PhysReg or an alias.
-  spillReg(VirtReg, PhysReg, SplitVRegs);
-  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI)
+  for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
     spillReg(VirtReg, *AliasI, SplitVRegs);
   return true;
 }



From stoklund at 2pi.dk  Tue Dec 14 17:23:15 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 23:23:15 -0000
Subject: [llvm-commits] [llvm] r121805 -
	/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
Message-ID: <20101214232315.663EA2A6C12C@llvm.org>

Author: stoklund
Date: Tue Dec 14 17:23:15 2010
New Revision: 121805

URL: http://llvm.org/viewvc/llvm-project?rev=121805&view=rev
Log:
Simplify AggressiveAntiDepBreaker's use of register aliases.

Modified:
    llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=121805&r1=121804&r2=121805&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Tue Dec 14 17:23:15 2010
@@ -155,16 +155,11 @@
     // In a return block, examine the function live-out regs.
     for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
          E = MRI.liveout_end(); I != E; ++I) {
-      unsigned Reg = *I;
-      State->UnionGroups(Reg, 0);
-      KillIndices[Reg] = BB->size();
-      DefIndices[Reg] = ~0u;
-      // Repeat, for all aliases.
-      for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
-        unsigned AliasReg = *Alias;
-        State->UnionGroups(AliasReg, 0);
-        KillIndices[AliasReg] = BB->size();
-        DefIndices[AliasReg] = ~0u;
+      for (const unsigned *Alias = TRI->getOverlaps(*I);
+           unsigned Reg = *Alias; ++Alias) {
+        State->UnionGroups(Reg, 0);
+        KillIndices[Reg] = BB->size();
+        DefIndices[Reg] = ~0u;
       }
     }
   }
@@ -176,16 +171,11 @@
          SE = BB->succ_end(); SI != SE; ++SI)
     for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
            E = (*SI)->livein_end(); I != E; ++I) {
-      unsigned Reg = *I;
-      State->UnionGroups(Reg, 0);
-      KillIndices[Reg] = BB->size();
-      DefIndices[Reg] = ~0u;
-      // Repeat, for all aliases.
-      for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
-        unsigned AliasReg = *Alias;
-        State->UnionGroups(AliasReg, 0);
-        KillIndices[AliasReg] = BB->size();
-        DefIndices[AliasReg] = ~0u;
+      for (const unsigned *Alias = TRI->getOverlaps(*I);
+           unsigned Reg = *Alias; ++Alias) {
+        State->UnionGroups(Reg, 0);
+        KillIndices[Reg] = BB->size();
+        DefIndices[Reg] = ~0u;
       }
     }
 
@@ -197,12 +187,8 @@
   for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
     unsigned Reg = *I;
     if (!IsReturnBlock && !Pristine.test(Reg)) continue;
-    State->UnionGroups(Reg, 0);
-    KillIndices[Reg] = BB->size();
-    DefIndices[Reg] = ~0u;
-    // Repeat, for all aliases.
-    for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
-      unsigned AliasReg = *Alias;
+    for (const unsigned *Alias = TRI->getOverlaps(Reg);
+         unsigned AliasReg = *Alias; ++Alias) {
       State->UnionGroups(AliasReg, 0);
       KillIndices[AliasReg] = BB->size();
       DefIndices[AliasReg] = ~0u;
@@ -435,12 +421,9 @@
       continue;
 
     // Update def for Reg and aliases.
-    DefIndices[Reg] = Count;
-    for (const unsigned *Alias = TRI->getAliasSet(Reg);
-         *Alias; ++Alias) {
-      unsigned AliasReg = *Alias;
+    for (const unsigned *Alias = TRI->getOverlaps(Reg);
+         unsigned AliasReg = *Alias; ++Alias)
       DefIndices[AliasReg] = Count;
-    }
   }
 }
 



From stoklund at 2pi.dk  Tue Dec 14 17:28:01 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 23:28:01 -0000
Subject: [llvm-commits] [llvm] r121806 -
	/llvm/trunk/lib/CodeGen/CallingConvLower.cpp
Message-ID: <20101214232801.5B7BA2A6C12C@llvm.org>

Author: stoklund
Date: Tue Dec 14 17:28:01 2010
New Revision: 121806

URL: http://llvm.org/viewvc/llvm-project?rev=121806&view=rev
Log:
Simplify CCState's use of register aliases.

Modified:
    llvm/trunk/lib/CodeGen/CallingConvLower.cpp

Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=121806&r1=121805&r2=121806&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original)
+++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Tue Dec 14 17:28:01 2010
@@ -51,11 +51,9 @@
 
 /// MarkAllocated - Mark a register and all of its aliases as allocated.
 void CCState::MarkAllocated(unsigned Reg) {
-  UsedRegs[Reg/32] |= 1 << (Reg&31);
-  
-  if (const unsigned *RegAliases = TRI.getAliasSet(Reg))
-    for (; (Reg = *RegAliases); ++RegAliases)
-      UsedRegs[Reg/32] |= 1 << (Reg&31);
+  for (const unsigned *Alias = TRI.getOverlaps(Reg);
+       unsigned Reg = *Alias; ++Alias)
+    UsedRegs[Reg/32] |= 1 << (Reg&31);
 }
 
 /// AnalyzeFormalArguments - Analyze an array of argument values,



From stoklund at 2pi.dk  Tue Dec 14 17:38:19 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 23:38:19 -0000
Subject: [llvm-commits] [llvm] r121807 -
	/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Message-ID: <20101214233819.872E12A6C12C@llvm.org>

Author: stoklund
Date: Tue Dec 14 17:38:19 2010
New Revision: 121807

URL: http://llvm.org/viewvc/llvm-project?rev=121807&view=rev
Log:
Simplify RegAllocGreedy's use of register aliases.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121807&r1=121806&r2=121807&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Dec 14 17:38:19 2010
@@ -154,11 +154,8 @@
 // Check interference without using the cache.
 bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
                                          unsigned PhysReg) {
-  LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[PhysReg]);
-  if (subQ.checkInterference())
-      return true;
-  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
-    subQ.init(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
+  for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
+    LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
     if (subQ.checkInterference())
       return true;
   }
@@ -170,19 +167,9 @@
 /// interfering.
 LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
                                               unsigned PhysReg) {
+  // Check physreg and aliases.
   LiveInterval *Interference = 0;
-
-  // Check direct interferences.
-  LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
-  if (Q.checkInterference()) {
-    Q.collectInterferingVRegs(1);
-    if (!Q.seenAllInterferences())
-      return 0;
-    Interference = Q.interferingVRegs().front();
-  }
-
-  // Check aliases.
-  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
+  for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
     LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
     if (Q.checkInterference()) {
       if (Interference)



From isanbard at gmail.com  Tue Dec 14 17:40:49 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 23:40:49 -0000
Subject: [llvm-commits] [llvm] r121808 -
	/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <20101214234049.A70DA2A6C12C@llvm.org>

Author: void
Date: Tue Dec 14 17:40:49 2010
New Revision: 121808

URL: http://llvm.org/viewvc/llvm-project?rev=121808&view=rev
Log:
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]


Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121808&r1=121807&r2=121808&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Dec 14 17:40:49 2010
@@ -918,27 +918,15 @@
       return false;  // We want to select tLDRpci instead.
   }
 
-  if (N.getOpcode() != ISD::ADD) {
-    if (N.getOpcode() == ARMISD::Wrapper &&
-        (!Subtarget->useMovt() ||
-         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
-      Base = N.getOperand(0);
-    else
-      Base = N;
-
-    Offset = CurDAG->getRegister(0, MVT::i32);
-    return true;
-  }
+  if (N.getOpcode() != ISD::ADD)
+    return false;
 
   // Thumb does not have [sp, r] address mode.
   RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
   RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
   if ((LHSR && LHSR->getReg() == ARM::SP) ||
-      (RHSR && RHSR->getReg() == ARM::SP)) {
-    Base = N;
-    Offset = CurDAG->getRegister(0, MVT::i32);
-    return true;
-  }
+      (RHSR && RHSR->getReg() == ARM::SP))
+    return false;
 
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();
@@ -1003,6 +991,23 @@
     return true;
   }
 
+  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
+  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
+  if ((LHSR && LHSR->getReg() == ARM::SP) ||
+      (RHSR && RHSR->getReg() == ARM::SP)) {
+    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
+    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
+    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
+
+    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
+    if (LHSC != 0 || RHSC != 0) return false;
+
+    Base = N;
+    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+    return true;
+  }
+
   // If the RHS is + imm5 * scale, fold into addr mode.
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();



From isanbard at gmail.com  Tue Dec 14 17:42:48 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 14 Dec 2010 23:42:48 -0000
Subject: [llvm-commits] [llvm] r121809 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20101214234248.F34F82A6C12C@llvm.org>

Author: void
Date: Tue Dec 14 17:42:48 2010
New Revision: 121809

URL: http://llvm.org/viewvc/llvm-project?rev=121809&view=rev
Log:
Comments and cleaning.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121809&r1=121808&r2=121809&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 14 17:42:48 2010
@@ -26,7 +26,6 @@
   return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
 }]>;
 
-
 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
 def imm0_7 : PatLeaf<(i32 imm), [{
   return (uint32_t)N->getZExtValue() < 8;
@@ -127,7 +126,6 @@
   let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
   let ParserMatchClass = MemModeRegThumbAsmOperand;
 }
-
 def t_addrmode_rrs2 : Operand<i32>,
                       ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
   let EncoderMethod = "getThumbAddrModeRegRegOpValue";
@@ -618,12 +616,12 @@
                               AddrMode am, InstrItinClass itin_r,
                               InstrItinClass itin_i, string asm,
                               PatFrag opnode> {
-  def r :
+  def r : // reg/reg
     T1pILdStEncode<reg_opc,
                    (outs tGPR:$Rt), (ins AddrMode_r:$addr),
                    am, itin_r, asm, "\t$Rt, $addr",
                    [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
-  def i :
+  def i : // reg/imm5
     T1pILdStEncodeImm<imm_opc, 1 /* Load */,
                       (outs tGPR:$Rt), (ins AddrMode_i:$addr),
                       am, itin_i, asm, "\t$Rt, $addr",
@@ -635,12 +633,12 @@
                               AddrMode am, InstrItinClass itin_r,
                               InstrItinClass itin_i, string asm,
                               PatFrag opnode> {
-  def r :
+  def r : // reg/reg
     T1pILdStEncode<reg_opc,
                    (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
                    am, itin_r, asm, "\t$Rt, $addr",
                    [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
-  def i :
+  def i : // reg/imm5
     T1pILdStEncodeImm<imm_opc, 0 /* Store */,
                       (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
                       am, itin_i, asm, "\t$Rt, $addr",



From grosbach at apple.com  Tue Dec 14 17:47:35 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 14 Dec 2010 23:47:35 -0000
Subject: [llvm-commits] [llvm] r121812 -
	/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
Message-ID: <20101214234735.B228C2A6C12C@llvm.org>

Author: grosbach
Date: Tue Dec 14 17:47:35 2010
New Revision: 121812

URL: http://llvm.org/viewvc/llvm-project?rev=121812&view=rev
Log:
thumb adr fixup needs alignment just like the t2 version.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121812&r1=121811&r2=121812&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Dec 14 17:47:35 2010
@@ -55,7 +55,8 @@
 { "fixup_arm_pcrel_10",      1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},
-{ "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel |
+                                                MCFixupKindInfo::FKF_IsAligned},
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                                 MCFixupKindInfo::FKF_IsAligned},



From isanbard at gmail.com  Tue Dec 14 18:04:01 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 00:04:01 -0000
Subject: [llvm-commits] [llvm] r121815 -
	/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <20101215000401.0B9A02A6C12C@llvm.org>

Author: void
Date: Tue Dec 14 18:04:00 2010
New Revision: 121815

URL: http://llvm.org/viewvc/llvm-project?rev=121815&view=rev
Log:
Revert r121808 until I can fix the build.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121815&r1=121814&r2=121815&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Dec 14 18:04:00 2010
@@ -918,15 +918,27 @@
       return false;  // We want to select tLDRpci instead.
   }
 
-  if (N.getOpcode() != ISD::ADD)
-    return false;
+  if (N.getOpcode() != ISD::ADD) {
+    if (N.getOpcode() == ARMISD::Wrapper &&
+        (!Subtarget->useMovt() ||
+         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
+      Base = N.getOperand(0);
+    else
+      Base = N;
+
+    Offset = CurDAG->getRegister(0, MVT::i32);
+    return true;
+  }
 
   // Thumb does not have [sp, r] address mode.
   RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
   RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
   if ((LHSR && LHSR->getReg() == ARM::SP) ||
-      (RHSR && RHSR->getReg() == ARM::SP))
-    return false;
+      (RHSR && RHSR->getReg() == ARM::SP)) {
+    Base = N;
+    Offset = CurDAG->getRegister(0, MVT::i32);
+    return true;
+  }
 
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();
@@ -991,23 +1003,6 @@
     return true;
   }
 
-  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
-  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
-  if ((LHSR && LHSR->getReg() == ARM::SP) ||
-      (RHSR && RHSR->getReg() == ARM::SP)) {
-    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
-    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
-    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
-    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
-
-    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
-    if (LHSC != 0 || RHSC != 0) return false;
-
-    Base = N;
-    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
-    return true;
-  }
-
   // If the RHS is + imm5 * scale, fold into addr mode.
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();



From jasonwkim at google.com  Tue Dec 14 18:21:16 2010
From: jasonwkim at google.com (Jason Kim)
Date: Tue, 14 Dec 2010 16:21:16 -0800
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <nngy67sm3r7.fsf@royale.us.cray.com>
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	<nngy67sm3r7.fsf@royale.us.cray.com>
Message-ID: <AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>

Hi David.

Feedback below:

On Tue, Dec 14, 2010 at 1:41 PM, David A. Greene <greened at obbligato.org> wrote:
> Jason Kim <jasonwkim at google.com> writes:
>
>> I think the regulars want the patches posted on llvm-commits for review
>> However, taking a ?look at the second one (lit2.patch, attached),
>> there's couple of utilities missing in the list - like elf-dump etc.
>
> Ping? ?Patch #3 on the bug is probably the one to apply. ?I've copied it below.
>
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?-Dave
>
> Index: test/lit.cfg
> ===================================================================
> --- test/lit.cfg ? ? ? ?(revision 121488)
> +++ test/lit.cfg ? ? ? ?(working copy)
> @@ -148,6 +148,35 @@
> ? ? else:
> ? ? ? ? config.substitutions.append(('%' + sub, site_exp[sub]))
>
> +# NOTE: Poor man's regexp here. ?Only ^ and $ are supported.
> +
> +# Replace command at the start of the line.
> +for sub in ['^llc', '^lli', '^tblgen', '^bugpoint', '^llvmc',
> + ? ? ? ? ? ?'^llvm-ar', '^llvm-as', '^llvm-bcanalyzer', '^llvm-dis',
> + ? ? ? ? ? ?'^llvm-extract', '^llvm-ld', '^llvm-link', '^llvm-nm',
> + ? ? ? ? ? ?'^llvm-prof', '^llvm-ranlib', '^llvm-mc', '^opt',
> + ? ? ? ? ? ?'^FileCheck']:
> + ? ?config.substitutions.append((sub,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? llvm_tools_dir + '/' + sub[1:]))
> +

1. Please have one canonical list of executables (including things
like (elf/macho/coff)-dump that are used by test/ and prepend the
exact path to all of them, as having 3 sets of basically the same data
is not likely to be well received. Can you perhaps use word boundary
as a pattern check? (if you have to import re, so be it.)
2. Add verbose comment to lit.cfg and TestRunner.py
3. resend patch to llvm-commits after doublechecking test results.
4. COMMIT!
5. File a doc bug to remind the core developers about this change (or
patch the doc directly?) You can do this separately.

Steps 1,2, and 5 are to hopefully answer any objections that might
arise - as I can't say for certain why the llvm-gcc path was prepended
during config... (Tho I agree its a  bug!)

Thanks!

-jason

> +# Replace command at the end of the line.
> +for sub in [' llc$', ' lli$', ' tblgen$', ' bugpoint$', ' llvmc$',
> + ? ? ? ? ? ?' llvm-ar$', ' llvm-as$', ' llvm-bcanalyzer$', ' llvm-dis$',
> + ? ? ? ? ? ?' llvm-extract$', ' llvm-ld$', ' llvm-link$', ' llvm-nm$',
> + ? ? ? ? ? ?' llvm-prof$', ' llvm-ranlib$', ' llvm-mc$', ' opt$',
> + ? ? ? ? ? ?' FileCheck$']:
> + ? ?config.substitutions.append((sub,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ' ' + llvm_tools_dir + '/' + sub[1:-1]))
> +
> +# Replace command in the middle of the pipeline.
> +for sub in [' llc ', ' lli ', ' tblgen ', ' bugpoint ', ' llvmc ',
> + ? ? ? ? ? ?' llvm-ar ', ' llvm-as ', ' llvm-bcanalyzer ', ' llvm-dis ',
> + ? ? ? ? ? ?' llvm-extract ', ' llvm-ld ', ' llvm-link ', ' llvm-nm ',
> + ? ? ? ? ? ?' llvm-prof ', ' llvm-ranlib ', ' llvm-mc ', ' opt ',
> + ? ? ? ? ? ?' FileCheck ']:
> + ? ?config.substitutions.append((sub,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ' ' + llvm_tools_dir + '/' + sub[1:-1] + ' '))
> +
> ?excludes = []
>
> ?# Provide target_triple for use in XFAIL and XTARGET.
> Index: utils/lit/lit/TestRunner.py
> ===================================================================
> --- utils/lit/lit/TestRunner.py (revision 121488)
> +++ utils/lit/lit/TestRunner.py (working copy)
> @@ -8,6 +8,10 @@
> ?import platform
> ?import tempfile
>
> +# Utility to replace a string starting from the end.
> +def rreplace(s, old, new, count):
> + ? ?return (s[::-1].replace(old[::-1], new[::-1], count))[::-1]
> +
> ?class InternalShellError(Exception):
> ? ? def __init__(self, command, message):
> ? ? ? ? self.command = command
> @@ -448,7 +452,18 @@
> ? ? def processLine(ln):
> ? ? ? ? # Apply substitutions
> ? ? ? ? for a,b in substitutions:
> - ? ? ? ? ? ?ln = ln.replace(a,b)
> + ? ? ? ? ? ?# Poor man's regexp: support ^ and $.
> + ? ? ? ? ? ?if a.startswith('^') and a.endswith('$'):
> + ? ? ? ? ? ? ? ?if ln == a[1:-1]:
> + ? ? ? ? ? ? ? ? ? ?ln = b
> + ? ? ? ? ? ?elif a.startswith('^'):
> + ? ? ? ? ? ? ? ?if ln.startswith(a[1:]):
> + ? ? ? ? ? ? ? ? ? ?ln.replace(a[1:],b,1)
> + ? ? ? ? ? ?elif a.endswith('$'):
> + ? ? ? ? ? ? ? ?if ln.endswith(a[:-1]):
> + ? ? ? ? ? ? ? ? ? ?ln = rreplace(ln,a[:-1],b,1)
> + ? ? ? ? ? ?else:
> + ? ? ? ? ? ? ? ?ln = ln.replace(a,b)
>
> ? ? ? ? # Strip the trailing newline and any extra whitespace.
> ? ? ? ? return ln.strip()
>


From resistor at mac.com  Tue Dec 14 18:52:44 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 15 Dec 2010 00:52:44 -0000
Subject: [llvm-commits] [llvm] r121816 -
 /llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
Message-ID: <20101215005244.D3D972A6C12C@llvm.org>

Author: resistor
Date: Tue Dec 14 18:52:44 2010
New Revision: 121816

URL: http://llvm.org/viewvc/llvm-project?rev=121816&view=rev
Log:
Cleanup trailing whitespace.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=121816&r1=121815&r2=121816&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Tue Dec 14 18:52:44 2010
@@ -31,20 +31,20 @@
 namespace {
   class CorrelatedValuePropagation : public FunctionPass {
     LazyValueInfo *LVI;
-    
+
     bool processSelect(SelectInst *SI);
     bool processPHI(PHINode *P);
     bool processMemAccess(Instruction *I);
     bool processCmp(CmpInst *C);
-    
+
   public:
     static char ID;
     CorrelatedValuePropagation(): FunctionPass(ID) {
      initializeCorrelatedValuePropagationPass(*PassRegistry::getPassRegistry());
     }
-    
+
     bool runOnFunction(Function &F);
-    
+
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<LazyValueInfo>();
     }
@@ -66,34 +66,34 @@
 bool CorrelatedValuePropagation::processSelect(SelectInst *S) {
   if (S->getType()->isVectorTy()) return false;
   if (isa<Constant>(S->getOperand(0))) return false;
-  
+
   Constant *C = LVI->getConstant(S->getOperand(0), S->getParent());
   if (!C) return false;
-  
+
   ConstantInt *CI = dyn_cast<ConstantInt>(C);
   if (!CI) return false;
-  
+
   S->replaceAllUsesWith(S->getOperand(CI->isOne() ? 1 : 2));
   S->eraseFromParent();
 
   ++NumSelects;
-  
+
   return true;
 }
 
 bool CorrelatedValuePropagation::processPHI(PHINode *P) {
   bool Changed = false;
-  
+
   BasicBlock *BB = P->getParent();
   for (unsigned i = 0, e = P->getNumIncomingValues(); i < e; ++i) {
     Value *Incoming = P->getIncomingValue(i);
     if (isa<Constant>(Incoming)) continue;
-    
+
     Constant *C = LVI->getConstantOnEdge(P->getIncomingValue(i),
                                          P->getIncomingBlock(i),
                                          BB);
     if (!C) continue;
-    
+
     P->setIncomingValue(i, C);
     Changed = true;
   }
@@ -105,7 +105,7 @@
   }
 
   ++NumPhis;
-  
+
   return Changed;
 }
 
@@ -115,12 +115,12 @@
     Pointer = L->getPointerOperand();
   else
     Pointer = cast<StoreInst>(I)->getPointerOperand();
-  
+
   if (isa<Constant>(Pointer)) return false;
-  
+
   Constant *C = LVI->getConstant(Pointer, I->getParent());
   if (!C) return false;
-  
+
   ++NumMemAccess;
   I->replaceUsesOfWith(Pointer, C);
   return true;
@@ -136,32 +136,32 @@
   if (isa<Instruction>(Op0) &&
       cast<Instruction>(Op0)->getParent() == C->getParent())
     return false;
-  
+
   Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
   if (!Op1) return false;
-  
+
   pred_iterator PI = pred_begin(C->getParent()), PE = pred_end(C->getParent());
   if (PI == PE) return false;
-  
-  LazyValueInfo::Tristate Result = LVI->getPredicateOnEdge(C->getPredicate(), 
+
+  LazyValueInfo::Tristate Result = LVI->getPredicateOnEdge(C->getPredicate(),
                                     C->getOperand(0), Op1, *PI, C->getParent());
   if (Result == LazyValueInfo::Unknown) return false;
 
   ++PI;
   while (PI != PE) {
-    LazyValueInfo::Tristate Res = LVI->getPredicateOnEdge(C->getPredicate(), 
+    LazyValueInfo::Tristate Res = LVI->getPredicateOnEdge(C->getPredicate(),
                                     C->getOperand(0), Op1, *PI, C->getParent());
     if (Res != Result) return false;
     ++PI;
   }
-  
+
   ++NumCmps;
-  
+
   if (Result == LazyValueInfo::True)
     C->replaceAllUsesWith(ConstantInt::getTrue(C->getContext()));
   else
     C->replaceAllUsesWith(ConstantInt::getFalse(C->getContext()));
-  
+
   C->eraseFromParent();
 
   return true;
@@ -169,9 +169,9 @@
 
 bool CorrelatedValuePropagation::runOnFunction(Function &F) {
   LVI = &getAnalysis<LazyValueInfo>();
-  
+
   bool FnChanged = false;
-  
+
   for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) {
     bool BBChanged = false;
     for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) {
@@ -193,9 +193,9 @@
         break;
       }
     }
-    
+
     FnChanged |= BBChanged;
   }
-  
+
   return FnChanged;
 }



From resistor at mac.com  Tue Dec 14 18:55:35 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 15 Dec 2010 00:55:35 -0000
Subject: [llvm-commits] [llvm] r121817 - in /llvm/trunk:
 lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
 test/Transforms/CorrelatedValuePropagation/crash.ll
Message-ID: <20101215005535.E8A912A6C12C@llvm.org>

Author: resistor
Date: Tue Dec 14 18:55:35 2010
New Revision: 121817

URL: http://llvm.org/viewvc/llvm-project?rev=121817&view=rev
Log:
Fix PR8790, another instance where unreachable code can cause instruction simplification to fail,
this case involve a select that simplifies to itself.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
    llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll

Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=121817&r1=121816&r2=121817&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Tue Dec 14 18:55:35 2010
@@ -73,7 +73,12 @@
   ConstantInt *CI = dyn_cast<ConstantInt>(C);
   if (!CI) return false;
 
-  S->replaceAllUsesWith(S->getOperand(CI->isOne() ? 1 : 2));
+  Value *ReplaceWith = S->getOperand(1);
+  Value *Other = S->getOperand(2);
+  if (!CI->isOne()) std::swap(ReplaceWith, Other);
+  if (ReplaceWith == S) ReplaceWith = UndefValue::get(S->getType());
+
+  S->replaceAllUsesWith(ReplaceWith);
   S->eraseFromParent();
 
   ++NumSelects;

Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll?rev=121817&r1=121816&r2=121817&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll (original)
+++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/crash.ll Tue Dec 14 18:55:35 2010
@@ -18,3 +18,20 @@
 for.end:                                          ; preds = %for.cond.us, %for.cond.us.us, %entry
   ret void
 }
+
+; PR 8790
+define void @test2() nounwind ssp {
+entry:
+  br label %func_29.exit
+
+sdf.exit.i:
+  %l_44.1.mux.i = select i1 %tobool5.not.i, i8 %l_44.1.mux.i, i8 1
+  br label %srf.exit.i
+
+srf.exit.i:
+  %tobool5.not.i = icmp ne i8 undef, 0
+  br i1 %tobool5.not.i, label %sdf.exit.i, label %func_29.exit
+
+func_29.exit:
+  ret void
+}



From isanbard at gmail.com  Tue Dec 14 18:58:57 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 00:58:57 -0000
Subject: [llvm-commits] [llvm] r121819 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20101215005857.390F12A6C12C@llvm.org>

Author: void
Date: Tue Dec 14 18:58:57 2010
New Revision: 121819

URL: http://llvm.org/viewvc/llvm-project?rev=121819&view=rev
Log:
Add some missing patterns now that tLDRB and tLDRH are split into reg and
immediate versions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121819&r1=121818&r2=121819&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 14 18:58:57 2010
@@ -1433,17 +1433,27 @@
 
 // If it's impossible to use [r,r] address mode for sextload, select to
 // ldr{b|h} + sxt{b|h} instead.
+def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
+            (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
+      Requires<[IsThumb, IsThumb1Only, HasV6]>;
 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
             (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
       Requires<[IsThumb, IsThumb1Only, HasV6]>;
+def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
+            (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
+      Requires<[IsThumb, IsThumb1Only, HasV6]>;
 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
             (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
       Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
             (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
-def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr),
-            (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>;
+def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
+            (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
+def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
+            (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
+def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
+            (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
 
 // Large immediate handling.
 



From isanbard at gmail.com  Tue Dec 14 19:03:19 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 01:03:19 -0000
Subject: [llvm-commits] [llvm] r121820 -
	/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <20101215010319.A9D2F2A6C12C@llvm.org>

Author: void
Date: Tue Dec 14 19:03:19 2010
New Revision: 121820

URL: http://llvm.org/viewvc/llvm-project?rev=121820&view=rev
Log:
Reapply r121808 now that the missing patterns have been supplied.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121820&r1=121819&r2=121820&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Dec 14 19:03:19 2010
@@ -918,27 +918,15 @@
       return false;  // We want to select tLDRpci instead.
   }
 
-  if (N.getOpcode() != ISD::ADD) {
-    if (N.getOpcode() == ARMISD::Wrapper &&
-        (!Subtarget->useMovt() ||
-         N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress))
-      Base = N.getOperand(0);
-    else
-      Base = N;
-
-    Offset = CurDAG->getRegister(0, MVT::i32);
-    return true;
-  }
+  if (N.getOpcode() != ISD::ADD)
+    return false;
 
   // Thumb does not have [sp, r] address mode.
   RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
   RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
   if ((LHSR && LHSR->getReg() == ARM::SP) ||
-      (RHSR && RHSR->getReg() == ARM::SP)) {
-    Base = N;
-    Offset = CurDAG->getRegister(0, MVT::i32);
-    return true;
-  }
+      (RHSR && RHSR->getReg() == ARM::SP))
+    return false;
 
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();
@@ -1003,6 +991,23 @@
     return true;
   }
 
+  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
+  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
+  if ((LHSR && LHSR->getReg() == ARM::SP) ||
+      (RHSR && RHSR->getReg() == ARM::SP)) {
+    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
+    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
+    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
+
+    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
+    if (LHSC != 0 || RHSC != 0) return false;
+
+    Base = N;
+    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+    return true;
+  }
+
   // If the RHS is + imm5 * scale, fold into addr mode.
   if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();



From foldr at codedgers.com  Tue Dec 14 19:21:59 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:21:59 -0000
Subject: [llvm-commits] [llvm] r121822 -
	/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp
Message-ID: <20101215012159.6FEC22A6C12C@llvm.org>

Author: foldr
Date: Tue Dec 14 19:21:59 2010
New Revision: 121822

URL: http://llvm.org/viewvc/llvm-project?rev=121822&view=rev
Log:
llvmc: make switch options ZeroOrMore by default.

Modified:
    llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp

Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=121822&r1=121821&r2=121822&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Dec 14 19:21:59 2010
@@ -768,14 +768,21 @@
 
     CheckNumberOfArguments(d, 2);
 
+    // Alias option store the aliased option name in the 'Help' field and do not
+    // have any properties.
     if (OD.isAlias()) {
-      // Aliases store the aliased option name in the 'Help' field.
       OD.Help = InitPtrToString(d.getArg(1));
     }
     else {
       processOptionProperties(d, OD);
     }
 
+    // Switch options are ZeroOrMore by default.
+    if (OD.isSwitch()) {
+      if (!(OD.isOptional() || OD.isOneOrMore() || OD.isRequired()))
+        OD.setZeroOrMore();
+    }
+
     OptDescs_.InsertDescription(OD);
   }
 



From foldr at codedgers.com  Tue Dec 14 19:22:05 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:05 -0000
Subject: [llvm-commits] [llvm] r121823 -
	/llvm/trunk/tools/llvmc/src/Base.td.in
Message-ID: <20101215012205.B4D232A6C12D@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:05 2010
New Revision: 121823

URL: http://llvm.org/viewvc/llvm-project?rev=121823&view=rev
Log:
llvmc: Forward -march/-mcpu/-mtune to as & ld.

Modified:
    llvm/trunk/tools/llvmc/src/Base.td.in

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=121823&r1=121822&r2=121823&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Tue Dec 14 19:22:05 2010
@@ -276,6 +276,9 @@
           (switch_on "c"), (stop_compilation),
           (not_empty "arch"), (forward "arch"),
           (not_empty "Xassembler"), (forward "Xassembler"),
+          (not_empty "march"), (forward "march"),
+          (not_empty "mcpu"), (forward "mcpu"),
+          (not_empty "mtune"), (forward "mtune"),
           (switch_on "m32"), (forward "m32"),
           (switch_on "m64"), (forward "m64"),
           (not_empty "Wa,"), (forward "Wa,")))
@@ -321,6 +324,9 @@
           (not_empty "framework"), (forward "framework"),
           (not_empty "weak_framework"), (forward "weak_framework"),
           (not_empty "filelist"), (forward "filelist"),
+          (not_empty "march"), (forward "march"),
+          (not_empty "mcpu"), (forward "mcpu"),
+          (not_empty "mtune"), (forward "mtune"),
           (switch_on "m32"), (forward "m32"),
           (switch_on "m64"), (forward "m64"),
           (not_empty "l"), (forward "l"),



From foldr at codedgers.com  Tue Dec 14 19:22:10 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:10 -0000
Subject: [llvm-commits] [llvm] r121824 -
	/llvm/trunk/tools/llvmc/src/Base.td.in
Message-ID: <20101215012210.8B3A42A6C12C@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:10 2010
New Revision: 121824

URL: http://llvm.org/viewvc/llvm-project?rev=121824&view=rev
Log:
llvmc: Support -mabi/-mfloat-abi.

Modified:
    llvm/trunk/tools/llvmc/src/Base.td.in

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=121824&r1=121823&r2=121824&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Tue Dec 14 19:22:10 2010
@@ -50,6 +50,10 @@
     (help "Generate code for the specified machine type")),
  (parameter_option "mcpu",
     (help "A deprecated synonym for -mtune"), (hidden), (forward_not_split)),
+ (parameter_option "mabi",
+    (help "Generate code for the specified ABI"), (hidden)),
+ (parameter_option "mfloat-abi",
+    (help "Specifies which floating-point ABI to use"), (hidden)),
  (switch_option "mfix-and-continue",
     (help "Needed by gdb to load .o files dynamically"), (hidden)),
  (parameter_option "MF",
@@ -204,6 +208,8 @@
          (not_empty "march"), (forward "march"),
          (not_empty "mcpu"), (forward "mcpu"),
          (not_empty "mtune"), (forward "mtune"),
+         (not_empty "mabi"), (forward "mabi"),
+         (not_empty "mfloat-abi"), (forward "mfloat-abi"),
          (not_empty "m"), (forward "m"),
          (switch_on "mfix-and-continue"), (forward "mfix-and-continue"),
          (switch_on "m32"), (forward "m32"),
@@ -279,6 +285,8 @@
           (not_empty "march"), (forward "march"),
           (not_empty "mcpu"), (forward "mcpu"),
           (not_empty "mtune"), (forward "mtune"),
+          (not_empty "mabi"), (forward "mabi"),
+          (not_empty "mfloat-abi"), (forward "mfloat-abi"),
           (switch_on "m32"), (forward "m32"),
           (switch_on "m64"), (forward "m64"),
           (not_empty "Wa,"), (forward "Wa,")))
@@ -327,6 +335,8 @@
           (not_empty "march"), (forward "march"),
           (not_empty "mcpu"), (forward "mcpu"),
           (not_empty "mtune"), (forward "mtune"),
+          (not_empty "mabi"), (forward "mabi"),
+          (not_empty "mfloat-abi"), (forward "mfloat-abi"),
           (switch_on "m32"), (forward "m32"),
           (switch_on "m64"), (forward "m64"),
           (not_empty "l"), (forward "l"),



From foldr at codedgers.com  Tue Dec 14 19:22:15 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:15 -0000
Subject: [llvm-commits] [llvm] r121825 -
	/llvm/trunk/tools/llvmc/src/Hooks.cpp
Message-ID: <20101215012215.3FB292A6C12D@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:15 2010
New Revision: 121825

URL: http://llvm.org/viewvc/llvm-project?rev=121825&view=rev
Log:
llvmc: more complete -march table for ARM.

Modified:
    llvm/trunk/tools/llvmc/src/Hooks.cpp

Modified: llvm/trunk/tools/llvmc/src/Hooks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Hooks.cpp?rev=121825&r1=121824&r2=121825&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Hooks.cpp (original)
+++ llvm/trunk/tools/llvmc/src/Hooks.cpp Tue Dec 14 19:22:15 2010
@@ -50,8 +50,10 @@
 }
 
 // Values needed to be special-cased by ConvertMArchToMAttr.
-const char* MArchMapKeys[] = { "armv6" };
-const char* MArchMapValues[] = { "v6" };
+const char* MArchMapKeys[] = { "armv4t", "armv5t", "armv5te", "armv6",
+                               "armv6-m", "armv6t2", "armv7-a", "armv7-m" };
+const char* MArchMapValues[] = { "v4t", "v5t", "v5te", "v6", "v6m", "v6t2",
+                                 "v7a", "v7m" };
 const unsigned NumMArchMapKeys = sizeof(MArchMapKeys) / sizeof(const char*);
 
 void InitializeMArchMap(ArgMap& Args) {



From foldr at codedgers.com  Tue Dec 14 19:22:20 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:20 -0000
Subject: [llvm-commits] [llvm] r121826 - in /llvm/trunk/tools/llvmc/src:
	Base.td.in Hooks.cpp
Message-ID: <20101215012220.8E7E12A6C12C@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:20 2010
New Revision: 121826

URL: http://llvm.org/viewvc/llvm-project?rev=121826&view=rev
Log:
llvmc: Better -mfpu/-mcpu support for ARM & PPC.

Modified:
    llvm/trunk/tools/llvmc/src/Base.td.in
    llvm/trunk/tools/llvmc/src/Hooks.cpp

Modified: llvm/trunk/tools/llvmc/src/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=121826&r1=121825&r2=121826&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/src/Base.td.in Tue Dec 14 19:22:20 2010
@@ -50,6 +50,9 @@
     (help "Generate code for the specified machine type")),
  (parameter_option "mcpu",
     (help "A deprecated synonym for -mtune"), (hidden), (forward_not_split)),
+ (parameter_option "mfpu",
+    (help "Specify type of floating point unit"),
+    (hidden), (forward_not_split)),
  (parameter_option "mabi",
     (help "Generate code for the specified ABI"), (hidden)),
  (parameter_option "mfloat-abi",
@@ -208,6 +211,7 @@
          (not_empty "march"), (forward "march"),
          (not_empty "mcpu"), (forward "mcpu"),
          (not_empty "mtune"), (forward "mtune"),
+         (not_empty "mfpu"), (forward "mfpu"),
          (not_empty "mabi"), (forward "mabi"),
          (not_empty "mfloat-abi"), (forward "mfloat-abi"),
          (not_empty "m"), (forward "m"),
@@ -308,9 +312,10 @@
                      (append_cmd "-relocation-model=dynamic-no-pic"),
           (not_empty "march"), (forward_transformed_value
                                 "march", "ConvertMArchToMAttr"),
-          (not_empty "mcpu"), (forward "mcpu"),
+          (not_empty "mcpu"), (forward_transformed_value "mcpu", "ConvertMCpu"),
           (and (not_empty "mtune"), (empty "mcpu")),
                      (forward_as "mtune", "-mcpu"),
+          (not_empty "mfpu"), (forward_transformed_value "mfpu", "ConvertMFpu"),
           (not_empty "m"), (forward_transformed_value "m", "ConvertToMAttr"),
           (not_empty "Wllc,"), (forward_value "Wllc,")))
 ]>;

Modified: llvm/trunk/tools/llvmc/src/Hooks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Hooks.cpp?rev=121826&r1=121825&r2=121826&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Hooks.cpp (original)
+++ llvm/trunk/tools/llvmc/src/Hooks.cpp Tue Dec 14 19:22:20 2010
@@ -4,6 +4,21 @@
 #include <vector>
 
 namespace hooks {
+
+/// NUM_KEYS - Calculate the size of a const char* array.
+#define NUM_KEYS(Keys) sizeof(Keys) / sizeof(const char*)
+
+// See http://graphics.stanford.edu/~seander/bithacks.html#RoundUpPowerOf2
+inline unsigned NextHighestPowerOf2 (unsigned i) {
+  i |= i >> 1;
+  i |= i >> 2;
+  i |= i >> 4;
+  i |= i >> 8;
+  i |= i >> 16;
+  i++;
+  return i;
+}
+
 typedef std::vector<std::string> StrVec;
 typedef llvm::StringMap<const char*> ArgMap;
 
@@ -49,35 +64,90 @@
   return out;
 }
 
-// Values needed to be special-cased by ConvertMArchToMAttr.
-const char* MArchMapKeys[] = { "armv4t", "armv5t", "armv5te", "armv6",
+// -march values that need to be special-cased.
+const char* MArchKeysARM[] = { "armv4t", "armv5t", "armv5te", "armv6",
                                "armv6-m", "armv6t2", "armv7-a", "armv7-m" };
-const char* MArchMapValues[] = { "v4t", "v5t", "v5te", "v6", "v6m", "v6t2",
+const char* MArchValuesARM[] = { "v4t", "v5t", "v5te", "v6", "v6m", "v6t2",
                                  "v7a", "v7m" };
-const unsigned NumMArchMapKeys = sizeof(MArchMapKeys) / sizeof(const char*);
+const unsigned MArchNumKeysARM = NUM_KEYS(MArchKeysARM);
+const unsigned MArchMapSize = NextHighestPowerOf2(MArchNumKeysARM);
 
-void InitializeMArchMap(ArgMap& Args) {
-  for (unsigned i = 0; i < NumMArchMapKeys; ++i) {
+void FillInArgMap(ArgMap& Args, const char* Keys[],
+                  const char* Values[], unsigned NumKeys)
+{
+  for (unsigned i = 0; i < NumKeys; ++i) {
     // Explicit cast to StringRef here is necessary to pick up the right
     // overload.
-    Args.GetOrCreateValue(llvm::StringRef(MArchMapKeys[i]), MArchMapValues[i]);
+    Args.GetOrCreateValue(llvm::StringRef(Keys[i]), Values[i]);
   }
 }
 
-/// ConvertMArchToMAttr - Try to convert -march from the gcc dialect to
+/// ConvertMArchToMAttr - Convert -march from the gcc dialect to
 /// something llc can understand.
 std::string ConvertMArchToMAttr(const StrVec& Opts) {
-  static ArgMap MArchMap(NumMArchMapKeys);
-  static bool MArchMapInitialized = false;
+  static ArgMap MArchMap(MArchMapSize);
+  static bool StaticDataInitialized = false;
 
-  if (!MArchMapInitialized) {
-    InitializeMArchMap(MArchMap);
-    MArchMapInitialized = true;
+  if (!StaticDataInitialized) {
+    FillInArgMap(MArchMap, MArchKeysARM, MArchValuesARM, MArchNumKeysARM);
+    StaticDataInitialized = true;
   }
 
   return ConvertToMAttrImpl(Opts, &MArchMap);
 }
 
+// -mcpu values that need to be special-cased.
+const char* MCpuKeysPPC[] = { "G3", "G4", "G5", "powerpc", "powerpc64"};
+const char* MCpuValuesPPC[] = { "g3", "g4", "g5", "ppc", "ppc64"};
+const unsigned MCpuNumKeysPPC = NUM_KEYS(MCpuKeysPPC);
+const unsigned MCpuMapSize = NextHighestPowerOf2(MCpuNumKeysPPC);
+
+/// ConvertMCpu - Convert -mcpu value from the gcc to the llc dialect.
+std::string ConvertMCpu(const char* Val) {
+  static ArgMap MCpuMap(MCpuMapSize);
+  static bool StaticDataInitialized = false;
+
+  if (!StaticDataInitialized) {
+    FillInArgMap(MCpuMap, MCpuKeysPPC, MCpuValuesPPC, MCpuNumKeysPPC);
+    StaticDataInitialized = true;
+  }
+
+  std::string ret = "-mcpu=";
+  ArgMap::const_iterator I = MCpuMap.find(Val);
+  if (I != MCpuMap.end()) {
+    return ret + I->getValue();
+  }
+  return ret + Val;
+}
+
+// -mfpu values that need to be special-cased.
+const char* MFpuKeysARM[] = { "vfp", "vfpv3",
+                              "vfpv3-fp16", "vfpv3-d16", "vfpv3-d16-fp16",
+                              "neon", "neon-fp16" };
+const char* MFpuValuesARM[] = { "vfp2", "vfp3",
+                                "+vfp3,+fp16", "+vfp3,+d16", "+vfp3,+d16,+fp16",
+                                "+neon", "+neon,+neonfp" };
+const unsigned MFpuNumKeysARM = NUM_KEYS(MFpuKeysARM);
+const unsigned MFpuMapSize = NextHighestPowerOf2(MFpuNumKeysARM);
+
+/// ConvertMFpu - Convert -mfpu value from the gcc to the llc dialect.
+std::string ConvertMFpu(const char* Val) {
+  static ArgMap MFpuMap(MFpuMapSize);
+  static bool StaticDataInitialized = false;
+
+  if (!StaticDataInitialized) {
+    FillInArgMap(MFpuMap, MFpuKeysARM, MFpuValuesARM, MFpuNumKeysARM);
+    StaticDataInitialized = true;
+  }
+
+  std::string ret = "-mattr=";
+  ArgMap::const_iterator I = MFpuMap.find(Val);
+  if (I != MFpuMap.end()) {
+    return ret + I->getValue();
+  }
+  return ret + '+' + Val;
+}
+
 /// ConvertToMAttr - Convert '-mfoo' and '-mno-bar' to '-mattr=+foo,-bar'.
 std::string ConvertToMAttr(const StrVec& Opts) {
   return ConvertToMAttrImpl(Opts);



From foldr at codedgers.com  Tue Dec 14 19:22:25 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:25 -0000
Subject: [llvm-commits] [llvm] r121827 -
	/llvm/trunk/tools/llvmc/src/Hooks.cpp
Message-ID: <20101215012225.385732A6C12D@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:25 2010
New Revision: 121827

URL: http://llvm.org/viewvc/llvm-project?rev=121827&view=rev
Log:
llvmc: Support -march arguments that should be forwarded to llc as -mcpu.

Modified:
    llvm/trunk/tools/llvmc/src/Hooks.cpp

Modified: llvm/trunk/tools/llvmc/src/Hooks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Hooks.cpp?rev=121827&r1=121826&r2=121827&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Hooks.cpp (original)
+++ llvm/trunk/tools/llvmc/src/Hooks.cpp Tue Dec 14 19:22:25 2010
@@ -26,8 +26,13 @@
 /// ConvertToMAttr. The optional Args parameter contains information about how
 /// to transform special-cased values (for example, '-march=armv6' must be
 /// forwarded as '-mattr=+v6').
-std::string ConvertToMAttrImpl(const StrVec& Opts, const ArgMap* Args = 0) {
-  std::string out("-mattr=");
+std::string ConvertToMAttrImpl(const StrVec& Opts,
+                               const ArgMap* Args = 0,
+                               const ArgMap* MCpuArgs = 0) {
+  std::string mattr("-mattr=");
+  std::string mcpu("-mcpu=");
+  bool mattrTouched = false;
+  bool mcpuTouched = false;
   bool firstIter = true;
 
   for (StrVec::const_iterator B = Opts.begin(), E = Opts.end(); B!=E; ++B) {
@@ -36,31 +41,48 @@
     if (firstIter)
       firstIter = false;
     else
-      out += ",";
+      mattr += ",";
 
     // Check if the argument is a special case.
     if (Args != 0) {
       ArgMap::const_iterator I = Args->find(Arg);
 
       if (I != Args->end()) {
-        out += '+';
-        out += I->getValue();
+        mattr += '+';
+        mattr += I->getValue();
+        continue;
+      }
+    }
+
+    // Check if the argument should be forwarded to -mcpu instead of -mattr.
+    if (MCpuArgs != 0 && !mcpuTouched) {
+      ArgMap::const_iterator I = MCpuArgs->find(Arg);
+
+      if (I != MCpuArgs->end()) {
+        mcpuTouched = true;
+        mcpu += I->getValue();
         continue;
       }
     }
 
     // Convert 'no-foo' to '-foo'.
     if (Arg.find("no-") == 0 && Arg[3] != 0) {
-      out += '-';
-      out += Arg.c_str() + 3;
+      mattr += '-';
+      mattr += Arg.c_str() + 3;
     }
     // Convert 'foo' to '+foo'.
     else {
-      out += '+';
-      out += Arg;
+      mattr += '+';
+      mattr += Arg;
     }
   }
 
+  std::string out;
+  if (mattrTouched)
+    out += mattr;
+  if (mcpuTouched)
+    out += (mattrTouched ? " " : "") + mcpu;
+
   return out;
 }
 
@@ -72,6 +94,13 @@
 const unsigned MArchNumKeysARM = NUM_KEYS(MArchKeysARM);
 const unsigned MArchMapSize = NextHighestPowerOf2(MArchNumKeysARM);
 
+// -march values that should be forwarded as -mcpu
+const char* MArchMCpuKeysARM[] = { "iwmmxt", "ep9312" };
+const char* MArchMCpuValuesARM[] = { "iwmmxt", "ep9312"};
+const unsigned MArchMCpuNumKeysARM = NUM_KEYS(MArchMCpuKeysARM);
+const unsigned MArchMCpuMapSize = NextHighestPowerOf2(MArchMCpuNumKeysARM);
+
+
 void FillInArgMap(ArgMap& Args, const char* Keys[],
                   const char* Values[], unsigned NumKeys)
 {
@@ -86,14 +115,17 @@
 /// something llc can understand.
 std::string ConvertMArchToMAttr(const StrVec& Opts) {
   static ArgMap MArchMap(MArchMapSize);
+  static ArgMap MArchMCpuMap(MArchMapSize);
   static bool StaticDataInitialized = false;
 
   if (!StaticDataInitialized) {
     FillInArgMap(MArchMap, MArchKeysARM, MArchValuesARM, MArchNumKeysARM);
+    FillInArgMap(MArchMCpuMap, MArchMCpuKeysARM,
+                 MArchMCpuValuesARM, MArchMCpuNumKeysARM);
     StaticDataInitialized = true;
   }
 
-  return ConvertToMAttrImpl(Opts, &MArchMap);
+  return ConvertToMAttrImpl(Opts, &MArchMap, &MArchMCpuMap);
 }
 
 // -mcpu values that need to be special-cased.



From foldr at codedgers.com  Tue Dec 14 19:22:29 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:29 -0000
Subject: [llvm-commits] [llvm] r121828 -
	/llvm/trunk/tools/llvmc/src/Hooks.cpp
Message-ID: <20101215012229.DCFF62A6C12C@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:29 2010
New Revision: 121828

URL: http://llvm.org/viewvc/llvm-project?rev=121828&view=rev
Log:
Remove ConvertToMAttrImpl, it became too '-march'-specific.

Modified:
    llvm/trunk/tools/llvmc/src/Hooks.cpp

Modified: llvm/trunk/tools/llvmc/src/Hooks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Hooks.cpp?rev=121828&r1=121827&r2=121828&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Hooks.cpp (original)
+++ llvm/trunk/tools/llvmc/src/Hooks.cpp Tue Dec 14 19:22:29 2010
@@ -22,68 +22,17 @@
 typedef std::vector<std::string> StrVec;
 typedef llvm::StringMap<const char*> ArgMap;
 
-/// ConvertToMAttrImpl - Common implementation of ConvertMArchToMAttr and
-/// ConvertToMAttr. The optional Args parameter contains information about how
-/// to transform special-cased values (for example, '-march=armv6' must be
-/// forwarded as '-mattr=+v6').
-std::string ConvertToMAttrImpl(const StrVec& Opts,
-                               const ArgMap* Args = 0,
-                               const ArgMap* MCpuArgs = 0) {
-  std::string mattr("-mattr=");
-  std::string mcpu("-mcpu=");
-  bool mattrTouched = false;
-  bool mcpuTouched = false;
-  bool firstIter = true;
-
-  for (StrVec::const_iterator B = Opts.begin(), E = Opts.end(); B!=E; ++B) {
-    const std::string& Arg = *B;
-
-    if (firstIter)
-      firstIter = false;
-    else
-      mattr += ",";
-
-    // Check if the argument is a special case.
-    if (Args != 0) {
-      ArgMap::const_iterator I = Args->find(Arg);
-
-      if (I != Args->end()) {
-        mattr += '+';
-        mattr += I->getValue();
-        continue;
-      }
-    }
-
-    // Check if the argument should be forwarded to -mcpu instead of -mattr.
-    if (MCpuArgs != 0 && !mcpuTouched) {
-      ArgMap::const_iterator I = MCpuArgs->find(Arg);
 
-      if (I != MCpuArgs->end()) {
-        mcpuTouched = true;
-        mcpu += I->getValue();
-        continue;
-      }
-    }
-
-    // Convert 'no-foo' to '-foo'.
-    if (Arg.find("no-") == 0 && Arg[3] != 0) {
-      mattr += '-';
-      mattr += Arg.c_str() + 3;
-    }
-    // Convert 'foo' to '+foo'.
-    else {
-      mattr += '+';
-      mattr += Arg;
-    }
+/// AddPlusOrMinus - Convert 'no-foo' to '-foo' and 'foo' to '+foo'.
+void AddPlusOrMinus (const std::string& Arg, std::string& out) {
+  if (Arg.find("no-") == 0 && Arg[3] != 0) {
+    out += '-';
+    out += Arg.c_str() + 3;
+  }
+  else {
+    out += '+';
+    out += Arg;
   }
-
-  std::string out;
-  if (mattrTouched)
-    out += mattr;
-  if (mcpuTouched)
-    out += (mattrTouched ? " " : "") + mcpu;
-
-  return out;
 }
 
 // -march values that need to be special-cased.
@@ -125,7 +74,52 @@
     StaticDataInitialized = true;
   }
 
-  return ConvertToMAttrImpl(Opts, &MArchMap, &MArchMCpuMap);
+  std::string mattr("-mattr=");
+  std::string mcpu("-mcpu=");
+  bool mattrTouched = false;
+  bool mcpuTouched = false;
+  bool firstIter = true;
+
+  for (StrVec::const_iterator B = Opts.begin(), E = Opts.end(); B!=E; ++B) {
+    const std::string& Arg = *B;
+
+    if (firstIter)
+      firstIter = false;
+    else
+      mattr += ",";
+
+    // Check if the argument is a special case.
+    {
+      ArgMap::const_iterator I = MArchMap.find(Arg);
+
+      if (I != MArchMap.end()) {
+        mattr += '+';
+        mattr += I->getValue();
+        continue;
+      }
+    }
+
+    // Check if the argument should be forwarded to -mcpu instead of -mattr.
+    {
+      ArgMap::const_iterator I = MArchMCpuMap.find(Arg);
+
+      if (I != MArchMCpuMap.end()) {
+        mcpuTouched = true;
+        mcpu += I->getValue();
+        continue;
+      }
+    }
+
+    AddPlusOrMinus(Arg, mattr);
+  }
+
+  std::string out;
+  if (mattrTouched)
+    out += mattr;
+  if (mcpuTouched)
+    out += (mattrTouched ? " " : "") + mcpu;
+
+  return out;
 }
 
 // -mcpu values that need to be special-cased.
@@ -182,7 +176,21 @@
 
 /// ConvertToMAttr - Convert '-mfoo' and '-mno-bar' to '-mattr=+foo,-bar'.
 std::string ConvertToMAttr(const StrVec& Opts) {
-  return ConvertToMAttrImpl(Opts);
+  std::string out("-mattr=");
+  bool firstIter = true;
+
+  for (StrVec::const_iterator B = Opts.begin(), E = Opts.end(); B!=E; ++B) {
+    const std::string& Arg = *B;
+
+    if (firstIter)
+      firstIter = false;
+    else
+      out += ",";
+
+    AddPlusOrMinus(Arg, out);
+  }
+
+  return out;
 }
 
 }



From foldr at codedgers.com  Tue Dec 14 19:22:34 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Wed, 15 Dec 2010 01:22:34 -0000
Subject: [llvm-commits] [llvm] r121829 -
	/llvm/trunk/tools/llvmc/src/Hooks.cpp
Message-ID: <20101215012234.D92DE2A6C12D@llvm.org>

Author: foldr
Date: Tue Dec 14 19:22:34 2010
New Revision: 121829

URL: http://llvm.org/viewvc/llvm-project?rev=121829&view=rev
Log:
Copy-pastos.

Modified:
    llvm/trunk/tools/llvmc/src/Hooks.cpp

Modified: llvm/trunk/tools/llvmc/src/Hooks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Hooks.cpp?rev=121829&r1=121828&r2=121829&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/src/Hooks.cpp (original)
+++ llvm/trunk/tools/llvmc/src/Hooks.cpp Tue Dec 14 19:22:34 2010
@@ -10,19 +10,19 @@
 
 // See http://graphics.stanford.edu/~seander/bithacks.html#RoundUpPowerOf2
 inline unsigned NextHighestPowerOf2 (unsigned i) {
+  --i;
   i |= i >> 1;
   i |= i >> 2;
   i |= i >> 4;
   i |= i >> 8;
   i |= i >> 16;
-  i++;
+  ++i;
   return i;
 }
 
 typedef std::vector<std::string> StrVec;
 typedef llvm::StringMap<const char*> ArgMap;
 
-
 /// AddPlusOrMinus - Convert 'no-foo' to '-foo' and 'foo' to '+foo'.
 void AddPlusOrMinus (const std::string& Arg, std::string& out) {
   if (Arg.find("no-") == 0 && Arg[3] != 0) {
@@ -78,14 +78,22 @@
   std::string mcpu("-mcpu=");
   bool mattrTouched = false;
   bool mcpuTouched = false;
-  bool firstIter = true;
 
   for (StrVec::const_iterator B = Opts.begin(), E = Opts.end(); B!=E; ++B) {
     const std::string& Arg = *B;
 
-    if (firstIter)
-      firstIter = false;
-    else
+    // Check if the argument should be forwarded to -mcpu instead of -mattr.
+    {
+      ArgMap::const_iterator I = MArchMCpuMap.find(Arg);
+
+      if (I != MArchMCpuMap.end()) {
+        mcpuTouched = true;
+        mcpu += I->getValue();
+        continue;
+      }
+    }
+
+    if (mattrTouched)
       mattr += ",";
 
     // Check if the argument is a special case.
@@ -93,23 +101,13 @@
       ArgMap::const_iterator I = MArchMap.find(Arg);
 
       if (I != MArchMap.end()) {
+        mattrTouched = true;
         mattr += '+';
         mattr += I->getValue();
         continue;
       }
     }
 
-    // Check if the argument should be forwarded to -mcpu instead of -mattr.
-    {
-      ArgMap::const_iterator I = MArchMCpuMap.find(Arg);
-
-      if (I != MArchMCpuMap.end()) {
-        mcpuTouched = true;
-        mcpu += I->getValue();
-        continue;
-      }
-    }
-
     AddPlusOrMinus(Arg, mattr);
   }
 



From enderby at apple.com  Tue Dec 14 19:24:37 2010
From: enderby at apple.com (Kevin Enderby)
Date: Wed, 15 Dec 2010 01:24:37 -0000
Subject: [llvm-commits] [llvm] r121830 -
	/llvm/trunk/test/MC/ARM/arm_instructions.s
Message-ID: <20101215012437.299262A6C12C@llvm.org>

Author: enderby
Date: Tue Dec 14 19:24:36 2010
New Revision: 121830

URL: http://llvm.org/viewvc/llvm-project?rev=121830&view=rev
Log:
Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

Modified:
    llvm/trunk/test/MC/ARM/arm_instructions.s

Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=121830&r1=121829&r2=121830&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Dec 14 19:24:36 2010
@@ -56,11 +56,62 @@
         stmda     r2!, {r1,r3-r6,sp}
         stmdb     r2!, {r1,r3-r6,sp}
 
-@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
-        and r1, r2, r3
-@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
-        ands r1, r2, r3
-@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
-        eor r1, r2, r3
-@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
-        eors r1, r2, r3
+@ CHECK: and	r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
+        and r1,r2,r3
+
+@ CHECK: ands	r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
+        ands r1,r2,r3
+
+@ CHECK: eor	r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
+        eor r1,r2,r3
+
+@ CHECK: eors	r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
+        eors r1,r2,r3
+
+@ CHECK: sub	r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
+        sub r1,r2,r3
+
+@ CHECK: subs	r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
+        subs r1,r2,r3
+
+@ CHECK: add	r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
+        add r1,r2,r3
+
+@ CHECK: adds	r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
+        adds r1,r2,r3
+
+@ CHECK: adc	r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
+        adc r1,r2,r3
+
+@ CHECK: sbc	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0]
+        sbc r1,r2,r3
+
+@ CHECK: orr	r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1]
+        orr r1,r2,r3
+
+@ CHECK: orrs	r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1]
+        orrs r1,r2,r3
+
+@ CHECK: bic	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
+        bic r1,r2,r3
+
+@ CHECK: bics	r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
+        bics r1,r2,r3
+
+@ CHECK: mov	r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
+        mov r1,r2
+
+@ CHECK: mvn	r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
+        mvn r1,r2
+
+@ CHECK: mvns	r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
+        mvns r1,r2
+
+@ CHECK: rsb	r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0]
+        rsb r1,r2,r3
+
+@ CHECK: rsc	r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0]
+        rsc r1,r2,r3
+
+@ CHECK: mlas	r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0]
+        mlas r1,r2,r3,r4



From echristo at apple.com  Tue Dec 14 19:28:01 2010
From: echristo at apple.com (Eric Christopher)
Date: Tue, 14 Dec 2010 17:28:01 -0800
Subject: [llvm-commits] [llvm] r121829
	-	/llvm/trunk/tools/llvmc/src/Hooks.cpp
In-Reply-To: <20101215012234.D92DE2A6C12D@llvm.org>
References: <20101215012234.D92DE2A6C12D@llvm.org>
Message-ID: <3ABF5EF2-C6B2-4B4C-BC2A-3C8DFD6C42AB@apple.com>


On Dec 14, 2010, at 5:22 PM, Mikhail Glushenkov wrote:

> Author: foldr
> Date: Tue Dec 14 19:22:34 2010
> New Revision: 121829
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121829&view=rev
> Log:
> Copy-pastos.

If you are going to use git to commit, please don't commit patches like these. You already knew it was a set of bugs - merge them together.

-eric

From isanbard at gmail.com  Tue Dec 14 19:35:55 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 01:35:55 -0000
Subject: [llvm-commits] [llvm] r121832 - /llvm/trunk/docs/GettingStarted.html
Message-ID: <20101215013555.603C52A6C12C@llvm.org>

Author: void
Date: Tue Dec 14 19:35:55 2010
New Revision: 121832

URL: http://llvm.org/viewvc/llvm-project?rev=121832&view=rev
Log:
Add mention that we support FreeBSD/amd64.

Modified:
    llvm/trunk/docs/GettingStarted.html

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=121832&r1=121831&r2=121832&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Tue Dec 14 19:35:55 2010
@@ -244,6 +244,11 @@
   <td>GCC</td>
 </tr>
 <tr>
+  <td>FreeBSD</td>
+  <td>amd64</td>
+  <td>GCC</td>
+</tr>
+<tr>
   <td>MacOS X<sup><a href="#pf_2">2</a></sup></td>
   <td>PowerPC</td>
   <td>GCC</td>



From kuwerty at gmail.com  Tue Dec 14 21:25:55 2010
From: kuwerty at gmail.com (Krister Wombell)
Date: Wed, 15 Dec 2010 11:25:55 +0800
Subject: [llvm-commits] [PATCH] Linear scan allocator
Message-ID: <AANLkTik55oj_a2ferkZgq=q8F37BDBrRJO4mrPYJ-ydM@mail.gmail.com>

I've come across a bug in RALinScan::assignRegOrStackSlotAtInterval that
occurs when:

- an interval conflicts with all physical registers in it's class
- and one of the phys regs has a lower spill weight then the interval being
assigned
- and there are no active or inactive intervals (or no entries of an
overlapping reg class)

findIntervalsToSplit then runs but won't be able to find the best candidate
as it fails to find a anything suitable in the 'active_' or 'inactive_'
lists. The code asserts that there's nothing to spill.

It's a fairly obscure set of circumstances but can happen if there is a
register class with no callee saved registers and a call instruction (that
implicitly defines all registers in that class).  It (probably?) also
requires that the interval being assigned is itself the result of spilling
as both the spill weight needs to be quite high.

I've attached a fix that spills the current interval if findIntervalsToSplit
returns nothing.

e.g.
BB#1;  %reg16418 is a fresh interval resuting from a spill, no other
interval is active
... = ADD %reg16418  ; DTR:%reg16418  ; should remat here
CALL ... ; imp-def of all regs in DTR
... = SUB %reg16418  ; DTR:%reg16418  ; should remat here

Krister
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From woongsik.choi at gmail.com  Tue Dec 14 21:03:00 2010
From: woongsik.choi at gmail.com (Woongsik Choi)
Date: Wed, 15 Dec 2010 12:03:00 +0900
Subject: [llvm-commits] [PATCH] llvm-gcc-4.2/gcc/crtstuff.c : __used__
 attributes for all global static variables
Message-ID: <AANLkTi=ZXHOzJ4VFdvWoUL8x4-uZqkpwr+VnWGPEirPV@mail.gmail.com>

Relating to the article in llvm-dev list,
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-December/036982.html

attached patch assigns __used__ attributes to all global static
variables llvm-gcc/gcc/crtstuff.c so that they are not removed
as results of optimization.

The affected variables are follows:
- static func_ptr force_to_data[1]
- STATIC void *__JCR_LIST__[]
- static func_ptr __do_global_dtors_aux_fini_array_entry[]
- static func_ptr __frame_dummy_init_array_entry[]
- STATIC EH_FRAME_SECTION_CONST int32 __FRAME_END__[]
- STATIC void *__JCR_END__[1]

STATIC is defined to be 'static' if elf format is used and otherwise
defined empty. I'm not sure whether it will cause some unexpected
behavior on other formats. I think following comment in the code
might concern about this:

STATIC func_ptr __DTOR_END__[1]
/* LLVM LOCAL begin */
#ifdef __llvm__
/* FIXME: Remove when external weak linkage will be alive. */
  __attribute__((__used__, section(".dtors"), aligned(sizeof(func_ptr))))
#else
  __attribute__((unused, section(".dtors"), aligned(sizeof(func_ptr))))
#endif
/* LLVM LOCAL end */
  = { (func_ptr) 0 };
#endif

At least, the patch worked fine on armv6 target under linux.
It solved the problem that frame_dummy and
__do_global_dtors_aux were not called if .init_array and
.fini_array sections are used.

Please verify this patch and apply if it's acceptable.

Best regards,
Woongsik Choi
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From sabre at nondot.org  Tue Dec 14 22:48:22 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 04:48:22 -0000
Subject: [llvm-commits] [llvm] r121837 - in /llvm/trunk/utils/TableGen:
 AsmMatcherEmitter.cpp CodeGenTarget.cpp LLVMCConfigurationEmitter.h
 Record.h TGParser.cpp TGParser.h TableGen.cpp
Message-ID: <20101215044822.89D322A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 22:48:22 2010
New Revision: 121837

URL: http://llvm.org/viewvc/llvm-project?rev=121837&view=rev
Log:
various cleanups to tblgen, patch by Garrison Venn!

Modified:
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp
    llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.h
    llvm/trunk/utils/TableGen/Record.h
    llvm/trunk/utils/TableGen/TGParser.cpp
    llvm/trunk/utils/TableGen/TGParser.h
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Dec 14 22:48:22 2010
@@ -493,7 +493,7 @@
 class AsmMatcherInfo {
 public:
   /// Tracked Records
-  RecordKeeper& Records;
+  RecordKeeper &Records;
 
   /// The tablegen AsmParser record.
   Record *AsmParser;
@@ -551,7 +551,7 @@
 public:
   AsmMatcherInfo(Record *AsmParser, 
                  CodeGenTarget &Target, 
-                 RecordKeeper& Records);
+                 RecordKeeper &Records);
 
   /// BuildInfo - Construct the various tables used during matching.
   void BuildInfo();
@@ -565,12 +565,8 @@
     return I == SubtargetFeatures.end() ? 0 : I->second;
   }
 
-  RecordKeeper& getRecords() {
-    return(Records);
-  }
-
-  RecordKeeper& getRecords() const {
-    return(Records);
+  RecordKeeper &getRecords() const {
+    return Records;
   }
 };
 
@@ -1004,7 +1000,7 @@
 
 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, 
                                CodeGenTarget &target, 
-                               RecordKeeper& records)
+                               RecordKeeper &records)
   : Records(records), AsmParser(asmParser), Target(target),
     RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) {
 }

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Dec 14 22:48:22 2010
@@ -108,7 +108,7 @@
 
 /// getTarget - Return the current instance of the Target class.
 ///
-CodeGenTarget::CodeGenTarget(RecordKeeper& records) : Records(records) {
+CodeGenTarget::CodeGenTarget(RecordKeeper &records) : Records(records) {
   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
   if (Targets.size() == 0)
     throw std::string("ERROR: No 'Target' subclasses defined!");

Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.h?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.h (original)
+++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.h Tue Dec 14 22:48:22 2010
@@ -23,7 +23,7 @@
   class LLVMCConfigurationEmitter : public TableGenBackend {
     RecordKeeper &Records;
   public:
-    explicit LLVMCConfigurationEmitter(RecordKeeper& records) : 
+    explicit LLVMCConfigurationEmitter(RecordKeeper &records) : 
       Records(records) {}
 
     // run - Output the asmwriter, returning true on failure.

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Tue Dec 14 22:48:22 2010
@@ -1236,8 +1236,8 @@
 
 public:
 
-  // Constructs a record. See also RecordKeeper::createRecord.
-  explicit Record(const std::string &N, SMLoc loc, RecordKeeper& records) :
+  // Constructs a record.
+  explicit Record(const std::string &N, SMLoc loc, RecordKeeper &records) :
     ID(LastID++), Name(N), Loc(loc), TrackedRecords(records) {}
   ~Record() {}
 
@@ -1324,7 +1324,7 @@
   void resolveReferencesTo(const RecordVal *RV);
 
   RecordKeeper &getRecords() const {
-    return(TrackedRecords);
+    return TrackedRecords;
   }
 
   void dump() const;
@@ -1466,12 +1466,6 @@
   std::vector<Record*>
   getAllDerivedDefinitions(const std::string &ClassName) const;
 
-  // allocates and returns a record. 
-  Record *createRecord(const std::string &N, SMLoc loc) {
-    return(new Record(N, loc, *this));
-  }
-
-
   void dump() const;
 };
 

Modified: llvm/trunk/utils/TableGen/TGParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.cpp?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TGParser.cpp (original)
+++ llvm/trunk/utils/TableGen/TGParser.cpp Tue Dec 14 22:48:22 2010
@@ -1096,8 +1096,9 @@
 
     // Create the new record, set it as CurRec temporarily.
     static unsigned AnonCounter = 0;
-    Record *NewRec = Records.createRecord(
-                        "anonymous.val."+utostr(AnonCounter++),NameLoc);
+    Record *NewRec = new Record("anonymous.val."+utostr(AnonCounter++),
+                                NameLoc,
+                                Records);
     SubClassReference SCRef;
     SCRef.RefLoc = NameLoc;
     SCRef.Rec = Class;
@@ -1661,7 +1662,7 @@
   Lex.Lex();  // Eat the 'def' token.
 
   // Parse ObjectName and make a record for it.
-  Record *CurRec = Records.createRecord(ParseObjectName(), DefLoc);
+  Record *CurRec = new Record(ParseObjectName(), DefLoc, Records);
 
   if (!CurMultiClass) {
     // Top-level def definition.
@@ -1728,7 +1729,7 @@
       return TokError("Class '" + CurRec->getName() + "' already defined");
   } else {
     // If this is the first reference to this class, create and add it.
-    CurRec = Records.createRecord(Lex.getCurStrVal(), Lex.getLoc());
+    CurRec = new Record(Lex.getCurStrVal(), Lex.getLoc(), Records);
     Records.addClass(CurRec);
   }
   Lex.Lex(); // eat the name.
@@ -1975,7 +1976,7 @@
         }
       }
 
-      Record *CurRec = Records.createRecord(DefName, DefmPrefixLoc);
+      Record *CurRec = new Record(DefName, DefmPrefixLoc, Records);
 
       SubClassReference Ref;
       Ref.RefLoc = DefmPrefixLoc;

Modified: llvm/trunk/utils/TableGen/TGParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.h?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TGParser.h (original)
+++ llvm/trunk/utils/TableGen/TGParser.h Tue Dec 14 22:48:22 2010
@@ -50,9 +50,9 @@
   MultiClass *CurMultiClass;
 
   // Record tracker
-  RecordKeeper& Records;
+  RecordKeeper &Records;
 public:
-  TGParser(SourceMgr &SrcMgr, RecordKeeper& records) : 
+  TGParser(SourceMgr &SrcMgr, RecordKeeper &records) : 
     Lex(SrcMgr), CurMultiClass(0), Records(records) {}
   
   /// ParseFile - Main entrypoint for parsing a tblgen file.  These parser

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=121837&r1=121836&r2=121837&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Tue Dec 14 22:48:22 2010
@@ -186,7 +186,7 @@
 static bool ParseFile(const std::string &Filename,
                       const std::vector<std::string> &IncludeDirs,
                       SourceMgr &SrcMgr,
-                      RecordKeeper& Records) {
+                      RecordKeeper &Records) {
   error_code ec;
   MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), ec);
   if (F == 0) {



From sabre at nondot.org  Tue Dec 14 22:52:41 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 04:52:41 -0000
Subject: [llvm-commits] [llvm] r121838 -
	/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
Message-ID: <20101215045241.6E0D12A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 22:52:41 2010
New Revision: 121838

URL: http://llvm.org/viewvc/llvm-project?rev=121838&view=rev
Log:
make qsort predicate more conformant by returning 0 for equal values.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=121838&r1=121837&r2=121838&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Dec 14 22:52:41 2010
@@ -592,7 +592,11 @@
 static int ConstantIntSortPredicate(const void *P1, const void *P2) {
   const ConstantInt *LHS = *(const ConstantInt**)P1;
   const ConstantInt *RHS = *(const ConstantInt**)P2;
-  return LHS->getValue().ult(RHS->getValue()) ? 1 : -1;
+  if (LHS->getValue().ult(RHS->getValue()))
+    return 1;
+  if (LHS->getValue() == RHS->getValue())
+    return 0;
+  return -1;
 }
 
 /// FoldValueComparisonIntoPredecessors - The specified terminator is a value



From stoklund at 2pi.dk  Tue Dec 14 23:06:11 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 14 Dec 2010 21:06:11 -0800
Subject: [llvm-commits] [PATCH] Linear scan allocator
In-Reply-To: <AANLkTik55oj_a2ferkZgq=q8F37BDBrRJO4mrPYJ-ydM@mail.gmail.com>
References: <AANLkTik55oj_a2ferkZgq=q8F37BDBrRJO4mrPYJ-ydM@mail.gmail.com>
Message-ID: <A2744119-A5CF-409F-94F7-1C16CAE67C9F@2pi.dk>


On Dec 14, 2010, at 7:25 PM, Krister Wombell wrote:

> I've come across a bug in RALinScan::assignRegOrStackSlotAtInterval that occurs when:
> 
> - an interval conflicts with all physical registers in it's class
> - and one of the phys regs has a lower spill weight then the interval being assigned
> - and there are no active or inactive intervals (or no entries of an overlapping reg class)
> 
> findIntervalsToSplit then runs but won't be able to find the best candidate as it fails to find a anything suitable in the 'active_' or 'inactive_' lists. The code asserts that there's nothing to spill.
> 
> It's a fairly obscure set of circumstances but can happen if there is a register class with no callee saved registers and a call instruction (that implicitly defines all registers in that class).  It (probably?) also requires that the interval being assigned is itself the result of spilling as both the spill weight needs to be quite high.
> 
> I've attached a fix that spills the current interval if findIntervalsToSplit returns nothing.

It looks reasonable, do you have a test case?

/jakob

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From sabre at nondot.org  Tue Dec 14 23:07:16 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:07:16 -0000
Subject: [llvm-commits] [www-pubs] r121839 - in /www-pubs/trunk:
 2007-10-PekkaTTA.html 2007-10-PekkaTTA.pdf pubs.js
Message-ID: <20101215050716.E056C2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:07:16 2010
New Revision: 121839

URL: http://llvm.org/viewvc/llvm-project?rev=121839&view=rev
Log:
add pekka's thesis.

Added:
    www-pubs/trunk/2007-10-PekkaTTA.html
    www-pubs/trunk/2007-10-PekkaTTA.pdf   (with props)
Modified:
    www-pubs/trunk/pubs.js

Added: www-pubs/trunk/2007-10-PekkaTTA.html
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2007-10-PekkaTTA.html?rev=121839&view=auto
==============================================================================
--- www-pubs/trunk/2007-10-PekkaTTA.html (added)
+++ www-pubs/trunk/2007-10-PekkaTTA.html Tue Dec 14 23:07:16 2010
@@ -0,0 +1,59 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+  <link rel="stylesheet" href="../llvm.css" type="text/css" media="screen" />
+  <title>Retargetable Compiler Backend for Transport Triggered Architectures</title>
+</head>
+<body>
+
+<div class="pub_title">
+  Retargetable Compiler Backend for Transport Triggered Architectures
+</div>
+<div class="pub_author">
+  Pekka Jaaskelainen, M.S. Thesis
+</div>
+
+
+<h2>Abstract:</h2>
+<blockquote>
+Embedded computer systems can be found everywhere as the result of the
+need to develop ever more intelligent and complex electronic devices.
+To meet requirements for factors such as power consumpiton and performance
+these systems often require customized processors which are optimized for
+a specific application. However, designing an application specific processor
+can be time-consuming and costly, and therefore the toolset used for processor
+design has an important role.<p>
+
+TTA Codesign Environment (TCE) is a semi-automated toolset developed at the
+Tampere University of Technology for designing processors based on an easily
+customizable Transport Triggered Architecture (TTA) processor architecture
+template. The toolset provides a complete co-design toolchain from
+program source code to synthesizable hardware design and program binaries.<p>
+
+One of the most important tools in the toolchain is the compiler. The compiler 
+is required to adapt to customized target architectures and to utilize the 
+available processor resources as efficiently as possible and still produce 
+programs with correct behavior. The compiler is therefore the most complicated 
+and challenging tool to design in the toolset.<p>
+
+The work completed for this thesis consists of the design, implementation and
+verification of a retargetable compiler backend for the TCE project. This
+thesis describes the role of the compiler in the toolchain and presents the
+design of the implemented compiler backend. In addition, the methods and 
+benchmark results of the compiler verification are presented.
+</blockquote>
+
+<h2>Published:</h2>
+<blockquote>
+  Retargetable Compiler Backend for Transport Triggered Architectures, Pekka Jaaskelainen.<br>
+  <i>Masters Thesis</i>, Tampere University of Technology, Oct 2007.
+</blockquote>
+
+<h2>Download:</h2>
+<ul>
+  <li><a href="2007-15-PekkaTTA.pdf">Retargetable Compiler Backend for Transport Triggered Architectures</a> (PDF)</li>
+</ul>
+
+</body>
+</html>

Added: www-pubs/trunk/2007-10-PekkaTTA.pdf
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2007-10-PekkaTTA.pdf?rev=121839&view=auto
==============================================================================
Binary file - no diff available.

Propchange: www-pubs/trunk/2007-10-PekkaTTA.pdf
------------------------------------------------------------------------------
    svn:mime-type = application/octet-stream

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=121839&r1=121838&r2=121839&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Tue Dec 14 23:07:16 2010
@@ -818,6 +818,14 @@
    month: 10,
    year: 2007},
 
+ {url: '2007-15-PekkaTTA.html',
+  title: 'Retargetable Compiler Backend for Transport Triggered Architectures',
+  author: 'Pekka Jaaskelainen',
+  published: "Masters Thesis",
+  location: 'Tampere University of Technology',
+  month: 10,
+  year: 2007},
+ 
   {url: '2007-10-DLS-RPython.html',
    title: "RPython: a Step Towards Reconciling Dynamically and Statically Typed OO Languages",
    author: "Davide Ancona, Massimo Ancona, Antonio Cuni, and Nicholas D. Matsakis",



From sabre at nondot.org  Tue Dec 14 23:07:43 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:07:43 -0000
Subject: [llvm-commits] [www-pubs] r121840 - /www-pubs/trunk/pubs.js
Message-ID: <20101215050743.320432A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:07:43 2010
New Revision: 121840

URL: http://llvm.org/viewvc/llvm-project?rev=121840&view=rev
Log:
fix url

Modified:
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=121840&r1=121839&r2=121840&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Tue Dec 14 23:07:43 2010
@@ -818,7 +818,7 @@
    month: 10,
    year: 2007},
 
- {url: '2007-15-PekkaTTA.html',
+ {url: '2007-10-PekkaTTA.html',
   title: 'Retargetable Compiler Backend for Transport Triggered Architectures',
   author: 'Pekka Jaaskelainen',
   published: "Masters Thesis",



From sabre at nondot.org  Tue Dec 14 23:08:47 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:08:47 -0000
Subject: [llvm-commits] [www-pubs] r121842 -
	/www-pubs/trunk/2007-10-PekkaTTA.html
Message-ID: <20101215050847.7FF272A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:08:47 2010
New Revision: 121842

URL: http://llvm.org/viewvc/llvm-project?rev=121842&view=rev
Log:
fix url #2

Modified:
    www-pubs/trunk/2007-10-PekkaTTA.html

Modified: www-pubs/trunk/2007-10-PekkaTTA.html
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2007-10-PekkaTTA.html?rev=121842&r1=121841&r2=121842&view=diff
==============================================================================
--- www-pubs/trunk/2007-10-PekkaTTA.html (original)
+++ www-pubs/trunk/2007-10-PekkaTTA.html Tue Dec 14 23:08:47 2010
@@ -52,7 +52,7 @@
 
 <h2>Download:</h2>
 <ul>
-  <li><a href="2007-15-PekkaTTA.pdf">Retargetable Compiler Backend for Transport Triggered Architectures</a> (PDF)</li>
+  <li><a href="2007-10-PekkaTTA.pdf">Retargetable Compiler Backend for Transport Triggered Architectures</a> (PDF)</li>
 </ul>
 
 </body>



From sabre at nondot.org  Tue Dec 14 23:10:27 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:10:27 -0000
Subject: [llvm-commits] [www-pubs] r121843 - in /www-pubs/trunk:
	2007-10-PekkaTTA.html pubs.js
Message-ID: <20101215051027.32A962A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:10:27 2010
New Revision: 121843

URL: http://llvm.org/viewvc/llvm-project?rev=121843&view=rev
Log:
turns out I got the authors name wrong too, good thing there is no buildbot for pubs

Modified:
    www-pubs/trunk/2007-10-PekkaTTA.html
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/2007-10-PekkaTTA.html
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2007-10-PekkaTTA.html?rev=121843&r1=121842&r2=121843&view=diff
==============================================================================
--- www-pubs/trunk/2007-10-PekkaTTA.html (original)
+++ www-pubs/trunk/2007-10-PekkaTTA.html Tue Dec 14 23:10:27 2010
@@ -11,7 +11,7 @@
   Retargetable Compiler Backend for Transport Triggered Architectures
 </div>
 <div class="pub_author">
-  Pekka Jaaskelainen, M.S. Thesis
+  Veli-Pekka Jaaskelainen, M.S. Thesis
 </div>
 
 
@@ -46,7 +46,7 @@
 
 <h2>Published:</h2>
 <blockquote>
-  Retargetable Compiler Backend for Transport Triggered Architectures, Pekka Jaaskelainen.<br>
+  Retargetable Compiler Backend for Transport Triggered Architectures, Veli-Pekka Jaaskelainen.<br>
   <i>Masters Thesis</i>, Tampere University of Technology, Oct 2007.
 </blockquote>
 

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=121843&r1=121842&r2=121843&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Tue Dec 14 23:10:27 2010
@@ -820,7 +820,7 @@
 
  {url: '2007-10-PekkaTTA.html',
   title: 'Retargetable Compiler Backend for Transport Triggered Architectures',
-  author: 'Pekka Jaaskelainen',
+  author: 'Veli-Pekka Jaaskelainen',
   published: "Masters Thesis",
   location: 'Tampere University of Technology',
   month: 10,



From sabre at nondot.org  Tue Dec 14 23:21:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:21:20 -0000
Subject: [llvm-commits] [www-pubs] r121844 - in /www-pubs/trunk:
 2010-04-NeustifterProfiling.html 2010-04-NeustifterProfiling.pdf pubs.js
Message-ID: <20101215052120.BFE752A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:21:20 2010
New Revision: 121844

URL: http://llvm.org/viewvc/llvm-project?rev=121844&view=rev
Log:
add Andreas Neustifter's thesis

Added:
    www-pubs/trunk/2010-04-NeustifterProfiling.html
    www-pubs/trunk/2010-04-NeustifterProfiling.pdf
Modified:
    www-pubs/trunk/pubs.js

Added: www-pubs/trunk/2010-04-NeustifterProfiling.html
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-04-NeustifterProfiling.html?rev=121844&view=auto
==============================================================================
--- www-pubs/trunk/2010-04-NeustifterProfiling.html (added)
+++ www-pubs/trunk/2010-04-NeustifterProfiling.html Tue Dec 14 23:21:20 2010
@@ -0,0 +1,45 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8" />
+  <link rel="stylesheet" href="../llvm.css" type="text/css" media="screen" />
+  <title>Efficient Profiling in the LLVM Compiler Infrastructure</title>
+</head>
+<body>
+
+<div class="pub_title">
+  Efficient Profiling in the LLVM Compiler Infrastructure
+</div>
+<div class="pub_author">
+  Andreas Neustifter, M.S. Thesis
+</div>
+
+
+<h2>Abstract:</h2>
+<blockquote>
+In computer science profiling is the process of determining the execution frequencies of parts of a program. This can be done by instrumenting the program code with counters that are incremented when a part of the program is executed or by sampling the program counter at certain time intervals. From this data it is possible to calculate exact (in the case of counters) or relative (in the case of sampling) execution frequencies of all parts of the program.<p>
+
+Currently the LLVM Compiler Infrastructure supports the profiling of programs by placing counters in the code and reading the resulting profiling data during consecutive compilations. But these counters are placed with a naive and inefficient algorithm that uses more counters than necessary. Also the recorded profiling information is not used in the compiler during optimisation or in the code generating backend when recompiling the program.<p>
+
+This work tries to improve the existing profiling support in LLVM in several ways. First, the number of counters placed in the code is decreased as presented by Ball and Larus. Counters are placed only at the leaves of each functions control flow graph (CFG), which gives an incomplete profile after the program execution. This incomplete profile can be completed by propagating the values of the leaves back into the tree.<p>
+
+Secondly, the profiling information is made available to the code generating backend. The CFG modifications and instruction selection passes are modified where necessary to preserve the profiling information so that backend passes and code generation can benefit from it. For example the register allocator is one such backend pass that could benefit since the spilling decisions are based on the execution frequency information.<p>
+
+Thirdly, a compile time estimator to predict execution frequencies when no profiling information is available is implemented and evaluated as proposed by Wu et. al. This estimator is based on statistical data which is combined in order to give more accurate branch predictions as compared to methods where only a single heuristic is used for prediction.<p>
+
+The efficiency of the implemented counter placing algorithm is evaluated by measuring profiling overhead for the naive and for the improved counter placement. The improvements from having the profiling information in the code generating backend is measured by the program performance for code which was compiled without and with profiling information as well as for code that was compiled using the compile time estimator.
+</blockquote>
+
+<h2>Published:</h2>
+<blockquote>
+  Efficient Profiling in the LLVM Compiler Infrastructure, Andreas Neustifter.<br>
+  <i>Masters Thesis</i>, Vienna University of Technology, April 2010.
+</blockquote>
+
+<h2>Download:</h2>
+<ul>
+  <li><a href="2010-04-NeustifterProfiling.pdf">Efficient Profiling in the LLVM Compiler Infrastructure</a> (PDF)</li>
+</ul>
+
+</body>
+</html>

Added: www-pubs/trunk/2010-04-NeustifterProfiling.pdf
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-04-NeustifterProfiling.pdf?rev=121844&view=auto
==============================================================================
--- www-pubs/trunk/2010-04-NeustifterProfiling.pdf (added)
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+trailer
+<< /Size 1490
+/Root 1488 0 R
+/Info 1489 0 R
+/ID [<552BE4BF664AFF5BB02C641659C34CE9> <552BE4BF664AFF5BB02C641659C34CE9>] >>
+startxref
+637920
+%%EOF

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=121844&r1=121843&r2=121844&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Tue Dec 14 23:21:20 2010
@@ -130,6 +130,16 @@
    location: "Paris, France",
    month: 4,
    year: 2010},
+ 
+ 
+ {url: '2010-04-NeustifterProfiling.html',
+  title: 'Efficient Profiling in the LLVM Compiler Infrastructure',
+  author: 'Andreas Neustifter',
+  published: "Masters Thesis",
+  location: 'Vienna University of Technology',
+  month: 4,
+  year: 2007},
+ 
   {url: "2010-03-VEE-VMKit.html",
    title: "VMKit: a Substrate for Managed Runtime Environments",
    published: "Proc. of the Virtual Execution Environments Conference (VEE '10)",
@@ -179,6 +189,7 @@
    location: "Pittsburgh, PA",
    month: 3,
    year: 2010},
+ 
   {url: "2010-02-FPGA-BitLevel.html",
    title: "Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration",
    published: "Proc. of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'10)",



From sabre at nondot.org  Tue Dec 14 23:22:14 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:22:14 -0000
Subject: [llvm-commits] [www-pubs] r121845 - /www-pubs/trunk/pubs.js
Message-ID: <20101215052214.44EEF2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:22:14 2010
New Revision: 121845

URL: http://llvm.org/viewvc/llvm-project?rev=121845&view=rev
Log:
fix year

Modified:
    www-pubs/trunk/pubs.js

Modified: www-pubs/trunk/pubs.js
URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=121845&r1=121844&r2=121845&view=diff
==============================================================================
--- www-pubs/trunk/pubs.js (original)
+++ www-pubs/trunk/pubs.js Tue Dec 14 23:22:14 2010
@@ -138,7 +138,7 @@
   published: "Masters Thesis",
   location: 'Vienna University of Technology',
   month: 4,
-  year: 2007},
+  year: 2010},
  
   {url: "2010-03-VEE-VMKit.html",
    title: "VMKit: a Substrate for Managed Runtime Environments",



From pdox at google.com  Tue Dec 14 23:25:53 2010
From: pdox at google.com (David Meyer)
Date: Tue, 14 Dec 2010 21:25:53 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <4D07CFC9.8060601@gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
	<4D07AFAB.8080907@gmail.com>
	<AANLkTikL5ZiLKewdc+RT7pnbrk-drtYVuioLpO3GHL2+@mail.gmail.com>
	<4D07CFC9.8060601@gmail.com>
Message-ID: <AANLkTi=YXFUhqjxQY82HOL2X5XUJ4oHZtoktkMgh3UP7@mail.gmail.com>

>
> Looks like this just makes PR8467 a bit more likely, no? That can/should
> probably be fixed differently, so I don't think it it is a big problem.
>
>
The output of the example in PR8467 is the same. This patch makes it more
likely that we'll relax when we don't have to, but only in the edge case
where there's an align that shrinks and a relocation very near the 1-byte
boundary.


> I have it too. Would you mind including the update to
> test/MC/MachO/relax-recompute-align.s in this patch?
>
>
Attached is a new patch which includes the altered test. However, I'm not
sure the test is serving any purpose anymore... it was meant to test the
align recompute behavior, which is no longer happening.


*) Can you try your patch in the .s testcase in PR8711?
>

There is no statistically significant effect on assemble time of this
example. The output is also identical.


>
> *) If this patch gives you a nice speed up in the attached test and doesn't
> slow down the one in 8711, commit it.
>

It doesn't affect 8711. My tests show this is more of an issue on X86-32.
Have you tried to assemble contrived.s?

With the current invalidation method, the algorithm is O(n^2) in the number
of fragments. If you have only a few hundred fragments, you won't notice a
problem. But if you start having thousands or tens of thousands of
fragments, things get slow fast.

(It was taking 3 minutes to assemble spec2k-gcc-nacl with llvm-mc vs. 2.5
seconds for nacl-gcc, until I made this change. See
http://build.chromium.org/f/client/perf/nacl-lucid64-spec-x86/spec2k/report.html?history=150&rev=-1&graph=compiletime_gcc,
the rise is switching to llvm-mc, and the fall is applying this patch)

Thanks,
- David Meyer
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From clattner at apple.com  Tue Dec 14 23:51:04 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 14 Dec 2010 21:51:04 -0800
Subject: [llvm-commits] [Review request] Jump threading and 'select'.
In-Reply-To: <AANLkTi=JO+ZgMAaz8w17qPwsO4MOC_xSPc0KwpsEG6Nf@mail.gmail.com>
References: <AANLkTi=JO+ZgMAaz8w17qPwsO4MOC_xSPc0KwpsEG6Nf@mail.gmail.com>
Message-ID: <2E0F07F7-66CD-4DD9-A533-03137DE5A333@apple.com>


On Dec 9, 2010, at 9:46 AM, Frits van Bommel wrote:

> The attached patch teaches jump threading to "look through" a select
> when the branch direction of a branch/switch/indirect depends on it.
> The new code tries to figure out whether the condition of the select
> is known in any of the predecessors and if so maps the operands
> appropriately.

This looks ok to me.  Please merge this:

+    if (TrueVal || FalseVal) {
+      PredValueInfoTy Conds;
+      if (ComputeValueKnownInPredecessors(SI->getCondition(), BB, Conds,
+                                          WantInteger)) {

Into something like this to reduce indentation:

+    PredValueInfoTy Conds;
+    if ((TrueVal || FalseVal) &&
         ComputeValueKnownInPredecessors(SI->getCondition(), BB, Conds, ..

and apply.

Is it helpful to know the condition of the select in one of the predecessors?

-Chris


From sabre at nondot.org  Tue Dec 14 23:51:39 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:51:39 -0000
Subject: [llvm-commits] [llvm] r121846 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20101215055139.B843C2A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:51:39 2010
New Revision: 121846

URL: http://llvm.org/viewvc/llvm-project?rev=121846&view=rev
Log:
when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=121846&r1=121845&r2=121846&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec 14 23:51:39 2010
@@ -1940,7 +1940,7 @@
       N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
       N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
       N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
-      N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1,
+      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
                        DAG.getConstant(SimpleSize, getShiftAmountTy()));
       return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
     }



From sabre at nondot.org  Tue Dec 14 23:58:59 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 05:58:59 -0000
Subject: [llvm-commits] [llvm] r121847 - in /llvm/trunk/test/CodeGen/X86:
 div_const.ll divide-by-constant.ll
Message-ID: <20101215055859.E75F12A6C12C@llvm.org>

Author: lattner
Date: Tue Dec 14 23:58:59 2010
New Revision: 121847

URL: http://llvm.org/viewvc/llvm-project?rev=121847&view=rev
Log:
merge two tests

Removed:
    llvm/trunk/test/CodeGen/X86/div_const.ll
Modified:
    llvm/trunk/test/CodeGen/X86/divide-by-constant.ll

Removed: llvm/trunk/test/CodeGen/X86/div_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/div_const.ll?rev=121846&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/div_const.ll (original)
+++ llvm/trunk/test/CodeGen/X86/div_const.ll (removed)
@@ -1,7 +0,0 @@
-; RUN: llc < %s -march=x86 | grep 365384439
-
-define i32 @f9188_mul365384439_shift27(i32 %A) {
-        %tmp1 = udiv i32 %A, 1577682821         ; <i32> [#uses=1]
-        ret i32 %tmp1
-}
-

Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=121847&r1=121846&r2=121847&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Tue Dec 14 23:58:59 2010
@@ -39,4 +39,14 @@
 entry:
 	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
 	ret i16 %div
+; CHECK: test4:
 }
+
+define i32 @test5(i32 %A) nounwind {
+        %tmp1 = udiv i32 %A, 1577682821         ; <i32> [#uses=1]
+        ret i32 %tmp1
+; CHECK: test5:
+; CHECK: movl	$365384439, %eax
+; CHECK: mull	4(%esp)
+}
+



From sabre at nondot.org  Wed Dec 15 00:04:20 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 06:04:20 -0000
Subject: [llvm-commits] [llvm] r121848 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/X86/divide-by-constant.ll
Message-ID: <20101215060420.2CCF02A6C12C@llvm.org>

Author: lattner
Date: Wed Dec 15 00:04:19 2010
New Revision: 121848

URL: http://llvm.org/viewvc/llvm-project?rev=121848&view=rev
Log:
take care of some todos, transforming [us]mul_lohi into 
a wider mul if the wider mul is legal.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/divide-by-constant.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=121848&r1=121847&r2=121848&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 15 00:04:19 2010
@@ -2045,7 +2045,29 @@
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
   if (Res.getNode()) return Res;
 
-  // TODO: Transform smul_lohi to mul if the wider mul is legal!
+  EVT VT = N->getValueType(0);
+  DebugLoc DL = N->getDebugLoc();
+
+  // If the type twice as wide is legal, transform the mulhu to a wider multiply
+  // plus a shift.
+  if (VT.isSimple() && !VT.isVector()) {
+    MVT Simple = VT.getSimpleVT();
+    unsigned SimpleSize = Simple.getSizeInBits();
+    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
+    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
+      SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
+      SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
+      Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
+      // Compute the high part as N1.
+      Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
+                       DAG.getConstant(SimpleSize, getShiftAmountTy()));
+      Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
+      // Compute the low part as N0.
+      Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
+      return CombineTo(N, Lo, Hi);
+    }
+  }
+  
   return SDValue();
 }
 
@@ -2053,7 +2075,29 @@
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
   if (Res.getNode()) return Res;
 
-  // TODO: Transform umul_lohi to mul if the wider mul is legal!
+  EVT VT = N->getValueType(0);
+  DebugLoc DL = N->getDebugLoc();
+  
+  // If the type twice as wide is legal, transform the mulhu to a wider multiply
+  // plus a shift.
+  if (VT.isSimple() && !VT.isVector()) {
+    MVT Simple = VT.getSimpleVT();
+    unsigned SimpleSize = Simple.getSizeInBits();
+    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
+    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
+      SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
+      SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
+      Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
+      // Compute the high part as N1.
+      Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
+                       DAG.getConstant(SimpleSize, getShiftAmountTy()));
+      Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
+      // Compute the low part as N0.
+      Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
+      return CombineTo(N, Lo, Hi);
+    }
+  }
+  
   return SDValue();
 }
 

Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=121848&r1=121847&r2=121848&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Wed Dec 15 00:04:19 2010
@@ -40,6 +40,7 @@
 	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
 	ret i16 %div
 ; CHECK: test4:
+; CHECK: imull	$-1985, %ecx, %ecx 
 }
 
 define i32 @test5(i32 %A) nounwind {



From sabre at nondot.org  Wed Dec 15 00:10:51 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 14 Dec 2010 22:10:51 -0800
Subject: [llvm-commits] [llvm] r121671 - in /llvm/trunk:
	lib/Transforms/Utils/SimplifyCFG.cpp
	test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <AANLkTikygbQbx2YmcF0-FPw-kLDp8Ls4adbMUsnUnZb9@mail.gmail.com>
References: <20101213031854.39E3A2A6C12C@llvm.org>
	<AANLkTikygbQbx2YmcF0-FPw-kLDp8Ls4adbMUsnUnZb9@mail.gmail.com>
Message-ID: <1D3A4C42-0B26-4092-9CBB-0BEC6F5E1ADB@nondot.org>

On Dec 13, 2010, at 4:29 AM, Frits van Bommel wrote:
> I have some code where this doesn't work, probably due to the
> requirement for the only use of the icmp to be a phi. A reduced test
> case:
> =====
> bool foo(int x) { return x == 1; }
> bool bar(int x) { return x == 2; }
> bool baz(int x) { return x == 3; }
> 
> bool quux(int x) {
>  return foo(x) || bar(x) || baz(x);
> }
> =====
> The problem seems to be that the return gets duplicated into the two
> branches before inlining, causing quux() to come out of clang -O3 like
> this:
> =====
> define zeroext i1 @quux(int)(i32 %x) nounwind readnone {
> entry:
>  switch i32 %x, label %lor.rhs [
>    i32 1, label %lor.end
>    i32 2, label %lor.end
>  ]
> 
> lor.rhs:                                          ; preds = %entry
>  %cmp.i5 = icmp eq i32 %x, 3                     ; [#uses=1]
>  ret i1 %cmp.i5
> 
> lor.end:                                          ; preds = %entry, %entry
>  ret i1 true
> }
> =====

Yes, this is another irritating example of PR8575, which is due to us duplicating ret's instead of forcing there to be at most one.

-Chris

From rafael.espindola at gmail.com  Wed Dec 15 00:24:45 2010
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 14 Dec 2010 22:24:45 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <AANLkTi=YXFUhqjxQY82HOL2X5XUJ4oHZtoktkMgh3UP7@mail.gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>	<4D07AFAB.8080907@gmail.com>	<AANLkTikL5ZiLKewdc+RT7pnbrk-drtYVuioLpO3GHL2+@mail.gmail.com>	<4D07CFC9.8060601@gmail.com>
	<AANLkTi=YXFUhqjxQY82HOL2X5XUJ4oHZtoktkMgh3UP7@mail.gmail.com>
Message-ID: <4D085F2D.1080304@gmail.com>

On 10-12-14 9:25 PM, David Meyer wrote:
>     Looks like this just makes PR8467 a bit more likely, no? That
>     can/should probably be fixed differently, so I don't think it it is
>     a big problem.
>
>
> The output of the example in PR8467 is the same. This patch makes it
> more likely that we'll relax when we don't have to, but only in the edge
> case where there's an align that shrinks and a relocation very near the
> 1-byte boundary.

Exactly, the bug is PR8467 is that we don't consider that things can get 
better when we relax. With your patch it would just be a bit more likely 
that we would hit it. Fixing the original issue in PR8467 should fix 
this too.


>     I have it too. Would you mind including the update to
>     test/MC/MachO/relax-recompute-align.s in this patch?
>
>
> Attached is a new patch which includes the altered test. However, I'm
> not sure the test is serving any purpose anymore... it was meant to test
> the align recompute behavior, which is no longer happening.

How about adding a FIXME? Maybe add a pointer to PR8467.

>     *) Can you try your patch in the .s testcase in PR8711?
>
>
> There is no statistically significant effect on assemble time of this
> example. The output is also identical.
>
>
>     *) If this patch gives you a nice speed up in the attached test and
>     doesn't slow down the one in 8711, commit it.
>
>
> It doesn't affect 8711. My tests show this is more of an issue on
> X86-32. Have you tried to assemble contrived.s?
>
> With the current invalidation method, the algorithm is O(n^2) in the
> number of fragments. If you have only a few hundred fragments, you won't
> notice a problem. But if you start having thousands or tens of thousands
> of fragments, things get slow fast.
>
> (It was taking 3 minutes to assemble spec2k-gcc-nacl with llvm-mc vs.
> 2.5 seconds for nacl-gcc, until I made this change. See
> http://build.chromium.org/f/client/perf/nacl-lucid64-spec-x86/spec2k/report.html?history=150&rev=-1&graph=compiletime_gcc
> <http://build.chromium.org/f/client/perf/nacl-lucid64-spec-x86/spec2k/report.html?history=150&rev=-1&graph=compiletime_gcc>,
> the rise is switching to llvm-mc, and the fall is applying this patch)

Yes, I understand the problem and how your patch fixes it. I was just a 
bit afraid if it would have bad effects on other tests by causing more 
layout passes. Since it doesn't, LGTM.

> Thanks,
> - David Meyer
>
>

Cheers,
Rafael

From sabre at nondot.org  Wed Dec 15 00:38:24 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 06:38:24 -0000
Subject: [llvm-commits] [llvm] r121849 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20101215063824.CE6672A6C12C@llvm.org>

Author: lattner
Date: Wed Dec 15 00:38:24 2010
New Revision: 121849

URL: http://llvm.org/viewvc/llvm-project?rev=121849&view=rev
Log:
add a note about a SPEC hack that gcc mainline does.

Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=121849&r1=121848&r2=121849&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Wed Dec 15 00:38:24 2010
@@ -1226,6 +1226,29 @@
 
 actually a conditional increment: loadpre18.c loadpre19.c
 
+//===---------------------------------------------------------------------===//
+
+[LOAD PRE / STORE SINKING / SPEC HACK]
+
+This is a chunk of code from 456.hmmer:
+
+int f(int M, int *mc, int *mpp, int *tpmm, int *ip, int *tpim, int *dpp,
+     int *tpdm, int xmb, int *bp, int *ms) {
+ int k, sc;
+ for (k = 1; k <= M; k++) {
+     mc[k] = mpp[k-1]   + tpmm[k-1];
+     if ((sc = ip[k-1]  + tpim[k-1]) > mc[k])  mc[k] = sc;
+     if ((sc = dpp[k-1] + tpdm[k-1]) > mc[k])  mc[k] = sc;
+     if ((sc = xmb  + bp[k])         > mc[k])  mc[k] = sc;
+     mc[k] += ms[k];
+   }
+}
+
+It is very profitable for this benchmark to turn the conditional stores to mc[k]
+into a conditional move (select instr in IR) and allow the final store to do the
+store.  See GCC PR27313 for more details.  Note that this is valid to xform even
+with the new C++ memory model, since mc[k] is previously loaded and later
+stored.
 
 //===---------------------------------------------------------------------===//
 



From pdox at google.com  Wed Dec 15 01:10:04 2010
From: pdox at google.com (David Meyer)
Date: Tue, 14 Dec 2010 23:10:04 -0800
Subject: [llvm-commits] [PATCH] MCAssembler Performance: Lazy
	invalidation
In-Reply-To: <4D085F2D.1080304@gmail.com>
References: <AANLkTim+12=YUY4adM_HpxiLcHMqA9+Rz9QgNtSvuo3j@mail.gmail.com>
	<4D07AFAB.8080907@gmail.com>
	<AANLkTikL5ZiLKewdc+RT7pnbrk-drtYVuioLpO3GHL2+@mail.gmail.com>
	<4D07CFC9.8060601@gmail.com>
	<AANLkTi=YXFUhqjxQY82HOL2X5XUJ4oHZtoktkMgh3UP7@mail.gmail.com>
	<4D085F2D.1080304@gmail.com>
Message-ID: <AANLkTimdXy2ejbJdhrFKnvHu8hTYJEL_dyp1QpOLuB9Q@mail.gmail.com>

Rafael,

It may cause more layout passes, but each layout pass is cheaper. (since the
layout is computed at most once per pass).

Another data point:

For my largest organic .s file (gcc.s, 514476 instructions), the output
object is 336 bytes larger out of 2.3 MB total. There's a slight improvement
in assemble time, 2.35 sec vs 2.48 sec.

How about adding a FIXME? Maybe add a pointer to PR8467.


New patch attached.
(Note that I don't have repository access)

Thanks,
David
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From sabre at nondot.org  Wed Dec 15 01:10:43 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 07:10:43 -0000
Subject: [llvm-commits] [llvm] r121850 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20101215071043.C202A2A6C12C@llvm.org>

Author: lattner
Date: Wed Dec 15 01:10:43 2010
New Revision: 121850

URL: http://llvm.org/viewvc/llvm-project?rev=121850&view=rev
Log:
add a shift/imul missed optimization

Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=121850&r1=121849&r2=121850&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Wed Dec 15 01:10:43 2010
@@ -810,6 +810,51 @@
 
 //===---------------------------------------------------------------------===//
 
+This (and similar related idioms):
+
+unsigned int foo(unsigned char i) {
+  return i | (i<<8) | (i<<16) | (i<<24);
+} 
+
+compiles into:
+
+define i32 @foo(i8 zeroext %i) nounwind readnone ssp noredzone {
+entry:
+  %conv = zext i8 %i to i32
+  %shl = shl i32 %conv, 8
+  %shl5 = shl i32 %conv, 16
+  %shl9 = shl i32 %conv, 24
+  %or = or i32 %shl9, %conv
+  %or6 = or i32 %or, %shl5
+  %or10 = or i32 %or6, %shl
+  ret i32 %or10
+}
+
+it would be better as:
+
+unsigned int bar(unsigned char i) {
+  unsigned int j=i | (i << 8); 
+  return j | (j<<16);
+}
+
+aka:
+
+define i32 @bar(i8 zeroext %i) nounwind readnone ssp noredzone {
+entry:
+  %conv = zext i8 %i to i32
+  %shl = shl i32 %conv, 8
+  %or = or i32 %shl, %conv
+  %shl5 = shl i32 %or, 16
+  %or6 = or i32 %shl5, %or
+  ret i32 %or6
+}
+
+or even i*0x01010101, depending on the speed of the multiplier.  The best way to
+handle this is to canonicalize it to a multiply in IR and have codegen handle
+lowering multiplies to shifts on cpus where shifts are faster.
+
+//===---------------------------------------------------------------------===//
+
 We do a number of simplifications in simplify libcalls to strength reduce
 standard library functions, but we don't currently merge them together.  For
 example, it is useful to merge memcpy(a,b,strlen(b)) -> strcpy.  This can only



From rafael.espindola at gmail.com  Wed Dec 15 01:12:24 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 15 Dec 2010 07:12:24 -0000
Subject: [llvm-commits] [llvm] r121851 - in /llvm/trunk:
 include/llvm/Support/MathExtras.h lib/MC/MCStreamer.cpp
Message-ID: <20101215071224.527C52A6C12C@llvm.org>

Author: rafael
Date: Wed Dec 15 01:12:24 2010
New Revision: 121851

URL: http://llvm.org/viewvc/llvm-project?rev=121851&view=rev
Log:
Generalize an assert.

Modified:
    llvm/trunk/include/llvm/Support/MathExtras.h
    llvm/trunk/lib/MC/MCStreamer.cpp

Modified: llvm/trunk/include/llvm/Support/MathExtras.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MathExtras.h?rev=121851&r1=121850&r2=121851&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/MathExtras.h (original)
+++ llvm/trunk/include/llvm/Support/MathExtras.h Wed Dec 15 01:12:24 2010
@@ -76,6 +76,12 @@
   return x == (x & (~0ULL >> (64 - N)));
 }
 
+/// isIIntN - Checks if an signed integer fits into the given (dynamic)
+/// bit width.
+inline bool isIntN(unsigned N, int64_t x) {
+  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
+}
+
 /// isMask_32 - This function returns true if the argument is a sequence of ones
 /// starting at the least significant bit with the remainder zero (32 bit
 /// version).   Ex. isMask_32(0x0000FFFFU) == true.

Modified: llvm/trunk/lib/MC/MCStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=121851&r1=121850&r2=121851&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Dec 15 01:12:24 2010
@@ -48,7 +48,8 @@
 void MCStreamer::EmitIntValue(uint64_t Value, unsigned Size,
                               unsigned AddrSpace) {
   assert(Size <= 8 && "Invalid size");
-  assert(!(Size == 1 && (signed)Value > 255) && "Invalid size");
+  unsigned Bits = 8 * Size;
+  assert((isUIntN(Bits, Value) || isIntN(Bits, Value)) && "Invalid size");
   char buf[8];
   // FIXME: Endianness assumption.
   for (unsigned i = 0; i != Size; ++i)



From sabre at nondot.org  Wed Dec 15 01:25:55 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 07:25:55 -0000
Subject: [llvm-commits] [llvm] r121853 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20101215072555.627642A6C12C@llvm.org>

Author: lattner
Date: Wed Dec 15 01:25:55 2010
New Revision: 121853

URL: http://llvm.org/viewvc/llvm-project?rev=121853&view=rev
Log:
add a note about overflow idiom recognition.

Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=121853&r1=121852&r2=121853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Wed Dec 15 01:25:55 2010
@@ -73,7 +73,25 @@
 
 //===---------------------------------------------------------------------===//
 
-Make the PPC branch selector target independant
+We should recognized various "overflow detection" idioms and translate them into
+llvm.uadd.with.overflow and similar intrinsics.  For example, we compile this:
+
+size_t add(size_t a,size_t b) {
+ if (a+b<a)
+   exit(0);
+ return a+b;
+}
+
+into:
+
+	addq	%rdi, %rbx
+	cmpq	%rdi, %rbx
+	jae	LBB0_2
+
+when it would be better to generate:
+
+	addq	%rdi, %rbx
+	jno	LBB0_2
 
 //===---------------------------------------------------------------------===//
 



From sabre at nondot.org  Wed Dec 15 01:28:58 2010
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 15 Dec 2010 07:28:58 -0000
Subject: [llvm-commits] [llvm] r121854 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20101215072858.E2E652A6C12C@llvm.org>

Author: lattner
Date: Wed Dec 15 01:28:58 2010
New Revision: 121854

URL: http://llvm.org/viewvc/llvm-project?rev=121854&view=rev
Log:
add another overflow idiom

Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=121854&r1=121853&r2=121854&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Wed Dec 15 01:28:58 2010
@@ -93,6 +93,14 @@
 	addq	%rdi, %rbx
 	jno	LBB0_2
 
+Apparently some version of GCC knows this.  Here is a multiply idiom:
+
+unsigned int mul(unsigned int a,unsigned int b) {
+ if ((unsigned long long)a*b>0xffffffff)
+   exit(0);
+  return a*b;
+}
+
 //===---------------------------------------------------------------------===//
 
 Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and



From rafael.espindola at gmail.com  Wed Dec 15 01:39:29 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 15 Dec 2010 07:39:29 -0000
Subject: [llvm-commits] [llvm] r121856 - in /llvm/trunk:
 lib/MC/MCAssembler.cpp test/MC/MachO/relax-recompute-align.s
Message-ID: <20101215073930.013D62A6C12C@llvm.org>

Author: rafael
Date: Wed Dec 15 01:39:29 2010
New Revision: 121856

URL: http://llvm.org/viewvc/llvm-project?rev=121856&view=rev
Log:
Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.

Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/test/MC/MachO/relax-recompute-align.s

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121856&r1=121855&r2=121856&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Dec 15 01:39:29 2010
@@ -738,6 +738,7 @@
   bool WasRelaxed = false;
   for (iterator it = begin(), ie = end(); it != ie; ++it) {
     MCSectionData &SD = *it;
+    MCFragment *FirstInvalidFragment = NULL;
 
     for (MCSectionData::iterator it2 = SD.begin(),
            ie2 = SD.end(); it2 != ie2; ++it2) {
@@ -762,10 +763,12 @@
         break;
       }
       // Update the layout, and remember that we relaxed.
-      if (relaxedFrag)
-	Layout.Invalidate(it2);
+      if (relaxedFrag && !FirstInvalidFragment)
+        FirstInvalidFragment = it2;
       WasRelaxed |= relaxedFrag;
     }
+    if (FirstInvalidFragment)
+      Layout.Invalidate(FirstInvalidFragment);
   }
 
   return WasRelaxed;

Modified: llvm/trunk/test/MC/MachO/relax-recompute-align.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/relax-recompute-align.s?rev=121856&r1=121855&r2=121856&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/relax-recompute-align.s (original)
+++ llvm/trunk/test/MC/MachO/relax-recompute-align.s Wed Dec 15 01:39:29 2010
@@ -3,16 +3,16 @@
 // FIXME: This is a horrible way of checking the output, we need an llvm-mc
 // based 'otool'.
 
-// This is a case where llvm-mc computes a better layout than Darwin 'as'. This
-// issue is that after the first jmp slides, the .align size must be
-// recomputed -- otherwise the second jump will appear to be out-of-range for a
-// 1-byte jump.
+// FIXME: PR8467.
+// There is an unnecessary relaxation here. After the first jmp slides,
+// the .align size could be recomputed so that the second jump will be in range
+// for a 1-byte jump. For performance reasons, this is not currently done.
 
 // CHECK:  # Section 0
 // CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
 // CHECK:  ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
 // CHECK:  ('address', 0)
-// CHECK:  ('size', 306)
+// CHECK:  ('size', 322)
 // CHECK:  ('offset', 324)
 // CHECK:  ('alignment', 4)
 // CHECK:  ('reloc_offset', 0)



From rafael.espindola at gmail.com  Wed Dec 15 02:45:53 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 15 Dec 2010 08:45:53 -0000
Subject: [llvm-commits] [llvm] r121857 - in /llvm/trunk:
 include/llvm/MC/MCAsmLayout.h include/llvm/MC/MCAssembler.h
 lib/MC/MCAssembler.cpp test/MC/MachO/relax-recompute-align.s
Message-ID: <20101215084553.3DE902A6C12D@llvm.org>

Author: rafael
Date: Wed Dec 15 02:45:53 2010
New Revision: 121857

URL: http://llvm.org/viewvc/llvm-project?rev=121857&view=rev
Log:
Relax alignment fragments.

With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmLayout.h
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/test/MC/MachO/relax-recompute-align.s

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=121857&r1=121856&r2=121857&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Wed Dec 15 02:45:53 2010
@@ -76,10 +76,6 @@
   /// @name Fragment Layout Data
   /// @{
 
-  /// \brief Get the effective size of the given fragment, as computed in the
-  /// current layout.
-  uint64_t getFragmentEffectiveSize(const MCFragment *F) const;
-
   /// \brief Get the offset of the given fragment inside its containing section.
   uint64_t getFragmentOffset(const MCFragment *F) const;
 

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=121857&r1=121856&r2=121857&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Wed Dec 15 02:45:53 2010
@@ -75,10 +75,6 @@
   /// initialized.
   uint64_t Offset;
 
-  /// EffectiveSize - The compute size of this section. This is ~0 until
-  /// initialized.
-  uint64_t EffectiveSize;
-
   /// LayoutOrder - The layout order of this fragment.
   unsigned LayoutOrder;
 
@@ -231,6 +227,9 @@
   /// cannot be satisfied in this width then this fragment is ignored.
   unsigned MaxBytesToEmit;
 
+  /// Size - The current estimate of the size.
+  unsigned Size;
+
   /// EmitNops - Flag to indicate that (optimal) NOPs should be emitted instead
   /// of using the provided value. The exact interpretation of this flag is
   /// target dependent.
@@ -241,7 +240,7 @@
                   unsigned _MaxBytesToEmit, MCSectionData *SD = 0)
     : MCFragment(FT_Align, SD), Alignment(_Alignment),
       Value(_Value),ValueSize(_ValueSize),
-      MaxBytesToEmit(_MaxBytesToEmit), EmitNops(false) {}
+      MaxBytesToEmit(_MaxBytesToEmit), Size(0), EmitNops(false) {}
 
   /// @name Accessors
   /// @{
@@ -252,6 +251,10 @@
 
   unsigned getValueSize() const { return ValueSize; }
 
+  unsigned getSize() const { return Size; }
+
+  void setSize(unsigned Size_) { Size = Size_; }
+
   unsigned getMaxBytesToEmit() const { return MaxBytesToEmit; }
 
   bool hasEmitNops() const { return EmitNops; }
@@ -704,11 +707,6 @@
                                const MCInstFragment *IF,
                                const MCAsmLayout &Layout) const;
 
-  /// Compute the effective fragment size assuming it is layed out at the given
-  /// \arg SectionAddress and \arg FragmentOffset.
-  uint64_t ComputeFragmentSize(const MCFragment &F,
-                               uint64_t FragmentOffset) const;
-
   /// LayoutOnce - Perform one layout iteration and return true if any offsets
   /// were adjusted.
   bool LayoutOnce(const MCObjectWriter &Writer, MCAsmLayout &Layout);
@@ -725,6 +723,9 @@
   bool RelaxDwarfLineAddr(const MCObjectWriter &Writer, MCAsmLayout &Layout,
 			  MCDwarfLineAddrFragment &DF);
 
+  bool RelaxAlignment(const MCObjectWriter &Writer, MCAsmLayout &Layout,
+		      MCAlignFragment &DF);
+
   /// FinishLayout - Finalize a layout, including fragment lowering.
   void FinishLayout(MCAsmLayout &Layout);
 
@@ -732,6 +733,10 @@
                        MCFragment &F, const MCFixup &Fixup);
 
 public:
+  /// Compute the effective fragment size assuming it is layed out at the given
+  /// \arg SectionAddress and \arg FragmentOffset.
+  uint64_t ComputeFragmentSize(const MCFragment &F) const;
+
   /// Find the symbol which defines the atom containing the given symbol, or
   /// null if there is no such symbol.
   const MCSymbolData *getAtom(const MCSymbolData *Symbol) const;

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121857&r1=121856&r2=121857&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Dec 15 02:45:53 2010
@@ -74,10 +74,9 @@
   if (!isFragmentUpToDate(F))
     return;
 
-  // Otherwise, reset the last valid fragment to the predecessor of the
-  // invalidated fragment.
+  // Otherwise, reset the last valid fragment to this fragment.
   const MCSectionData &SD = *F->getParent();
-  LastValidFragment[&SD] = F->getPrevNode();
+  LastValidFragment[&SD] = F;
 }
 
 void MCAsmLayout::EnsureValid(const MCFragment *F) const {
@@ -96,12 +95,6 @@
   }
 }
 
-uint64_t MCAsmLayout::getFragmentEffectiveSize(const MCFragment *F) const {
-  EnsureValid(F);
-  assert(F->EffectiveSize != ~UINT64_C(0) && "Address not set!");
-  return F->EffectiveSize;
-}
-
 uint64_t MCAsmLayout::getFragmentOffset(const MCFragment *F) const {
   EnsureValid(F);
   assert(F->Offset != ~UINT64_C(0) && "Address not set!");
@@ -116,7 +109,7 @@
 uint64_t MCAsmLayout::getSectionAddressSize(const MCSectionData *SD) const {
   // The size is the last fragment's end offset.
   const MCFragment &F = SD->getFragmentList().back();
-  return getFragmentOffset(&F) + getFragmentEffectiveSize(&F);
+  return getFragmentOffset(&F) + getAssembler().ComputeFragmentSize(F);
 }
 
 uint64_t MCAsmLayout::getSectionFileSize(const MCSectionData *SD) const {
@@ -137,8 +130,7 @@
 }
 
 MCFragment::MCFragment(FragmentType _Kind, MCSectionData *_Parent)
-  : Kind(_Kind), Parent(_Parent), Atom(0), Offset(~UINT64_C(0)),
-    EffectiveSize(~UINT64_C(0))
+  : Kind(_Kind), Parent(_Parent), Atom(0), Offset(~UINT64_C(0))
 {
   if (Parent)
     Parent->getFragmentList().push_back(this);
@@ -276,8 +268,7 @@
   return IsResolved;
 }
 
-uint64_t MCAssembler::ComputeFragmentSize(const MCFragment &F,
-                                          uint64_t FragmentOffset) const {
+uint64_t MCAssembler::ComputeFragmentSize(const MCFragment &F) const {
   switch (F.getKind()) {
   case MCFragment::FT_Data:
     return cast<MCDataFragment>(F).getContents().size();
@@ -289,17 +280,8 @@
   case MCFragment::FT_LEB:
     return cast<MCLEBFragment>(F).getContents().size();
 
-  case MCFragment::FT_Align: {
-    const MCAlignFragment &AF = cast<MCAlignFragment>(F);
-
-    uint64_t Size = OffsetToAlignment(FragmentOffset, AF.getAlignment());
-
-    // Honor MaxBytesToEmit.
-    if (Size > AF.getMaxBytesToEmit())
-      return 0;
-
-    return Size;
-  }
+  case MCFragment::FT_Align:
+    return cast<MCAlignFragment>(F).getSize();
 
   case MCFragment::FT_Org:
     return cast<MCOrgFragment>(F).getSize();
@@ -327,10 +309,9 @@
   // Compute fragment offset and size.
   uint64_t Offset = 0;
   if (Prev)
-    Offset += Prev->Offset + Prev->EffectiveSize;
+    Offset += Prev->Offset + getAssembler().ComputeFragmentSize(*Prev);
 
   F->Offset = Offset;
-  F->EffectiveSize = getAssembler().ComputeFragmentSize(*F, F->Offset);
   LastValidFragment[F->getParent()] = F;
 }
 
@@ -343,7 +324,7 @@
   ++stats::EmittedFragments;
 
   // FIXME: Embed in fragments instead?
-  uint64_t FragmentSize = Layout.getFragmentEffectiveSize(&F);
+  uint64_t FragmentSize = Asm.ComputeFragmentSize(F);
   switch (F.getKind()) {
   case MCFragment::FT_Align: {
     MCAlignFragment &AF = cast<MCAlignFragment>(F);
@@ -730,6 +711,18 @@
   return OldSize != Data.size();
 }
 
+bool MCAssembler::RelaxAlignment(const MCObjectWriter &Writer,
+				 MCAsmLayout &Layout,
+				 MCAlignFragment &AF) {
+  unsigned Offset = Layout.getFragmentOffset(&AF);
+  unsigned Size = OffsetToAlignment(Offset, AF.getAlignment());
+  if (Size > AF.getMaxBytesToEmit())
+    Size = 0;
+  unsigned OldSize = AF.getSize();
+  AF.setSize(Size);
+  return OldSize != Size;
+}
+
 bool MCAssembler::LayoutOnce(const MCObjectWriter &Writer,
                              MCAsmLayout &Layout) {
   ++stats::RelaxationSteps;
@@ -747,6 +740,10 @@
       switch(it2->getKind()) {
       default:
         break;
+      case MCFragment::FT_Align:
+	relaxedFrag = RelaxAlignment(Writer, Layout,
+				     *cast<MCAlignFragment>(it2));
+	break;
       case MCFragment::FT_Inst:
         relaxedFrag = RelaxInstruction(Writer, Layout,
                                        *cast<MCInstFragment>(it2));
@@ -809,7 +806,7 @@
   }
 
   OS << "<MCFragment " << (void*) this << " LayoutOrder:" << LayoutOrder
-     << " Offset:" << Offset << " EffectiveSize:" << EffectiveSize << ">";
+     << " Offset:" << Offset << ">";
 
   switch (getKind()) {
   case MCFragment::FT_Align: {

Modified: llvm/trunk/test/MC/MachO/relax-recompute-align.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/relax-recompute-align.s?rev=121857&r1=121856&r2=121857&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/relax-recompute-align.s (original)
+++ llvm/trunk/test/MC/MachO/relax-recompute-align.s Wed Dec 15 02:45:53 2010
@@ -3,16 +3,16 @@
 // FIXME: This is a horrible way of checking the output, we need an llvm-mc
 // based 'otool'.
 
-// FIXME: PR8467.
-// There is an unnecessary relaxation here. After the first jmp slides,
-// the .align size could be recomputed so that the second jump will be in range
-// for a 1-byte jump. For performance reasons, this is not currently done.
+// This is a case where llvm-mc computes a better layout than Darwin 'as'. This
+// issue is that after the first jmp slides, the .align size must be
+// recomputed -- otherwise the second jump will appear to be out-of-range for a
+// 1-byte jump.
 
 // CHECK:  # Section 0
 // CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
 // CHECK:  ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
 // CHECK:  ('address', 0)
-// CHECK:  ('size', 322)
+// CHECK:  ('size', 306)
 // CHECK:  ('offset', 324)
 // CHECK:  ('alignment', 4)
 // CHECK:  ('reloc_offset', 0)



From isanbard at gmail.com  Wed Dec 15 02:51:02 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 08:51:02 -0000
Subject: [llvm-commits] [llvm] r121858 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmBackend.cpp ARMFixupKinds.h ARMMCCodeEmitter.cpp
Message-ID: <20101215085102.3A6272A6C12D@llvm.org>

Author: void
Date: Wed Dec 15 02:51:02 2010
New Revision: 121858

URL: http://llvm.org/viewvc/llvm-project?rev=121858&view=rev
Log:
Add fixups for Thumb LDR/STR instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121858&r1=121857&r2=121858&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Dec 15 02:51:02 2010
@@ -237,6 +237,9 @@
     // 'off by 4' is implicitly handled by the half-word ordering of the
     // Thumb encoding, so we only need to adjust by 2 here.
     return ((Value - 2) >> 2) & 0xff;
+  case ARM::fixup_arm_thumb_ldst:
+    // Offset by 4.
+    return ((Value - 4) & 0x1f) << 6;
   case ARM::fixup_arm_thumb_cb: {
     // Offset by 4 and don't encode the lower bit, which is always 0.
     uint32_t Binary = (Value - 4) >> 1;
@@ -365,6 +368,7 @@
 
   case ARM::fixup_arm_thumb_br:
   case ARM::fixup_arm_thumb_cb:
+  case ARM::fixup_arm_thumb_ldst:
     return 2;
 
   case ARM::fixup_arm_ldst_pcrel_12:

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121858&r1=121857&r2=121858&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Wed Dec 15 02:51:02 2010
@@ -65,6 +65,9 @@
   // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
   fixup_arm_thumb_cp,
 
+  // fixup_arm_thumb_ldst - Fixup for Thumb load/store instrs.
+  fixup_arm_thumb_ldst,
+
   // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
   fixup_arm_thumb_bcc,
 

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121858&r1=121857&r2=121858&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 15 02:51:02 2010
@@ -68,6 +68,7 @@
 { "fixup_arm_thumb_blx",     7,            21,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cb",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cp",      1,             8,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_ldst",    1,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_bcc",     1,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_movt_hi16",     0,            16,  0 },
 { "fixup_arm_movw_lo16",     0,            16,  0 },
@@ -213,7 +214,7 @@
 
   /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
-                                SmallVectorImpl<MCFixup> &) const;
+                                SmallVectorImpl<MCFixup> &Fixups) const;
 
   /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
@@ -817,14 +818,23 @@
 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
 uint32_t ARMMCCodeEmitter::
 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
-                     SmallVectorImpl<MCFixup> &) const {
+                     SmallVectorImpl<MCFixup> &Fixups) const {
   // [Rn, #imm]
   //   {7-3} = imm5
   //   {2-0} = Rn
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
   unsigned Rn = getARMRegisterNumbering(MO.getReg());
-  unsigned Imm5 = MO1.getImm();
+  unsigned Imm5 = 0;
+
+  if (MO1.isExpr()) {
+    const MCExpr *Expr = MO.getExpr();
+    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_ldst);
+    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
+  } else {
+    Imm5 = MO1.getImm();
+  }
+
   return ((Imm5 & 0x1f) << 3) | Rn;
 }
 



From kuwerty at gmail.com  Wed Dec 15 03:26:05 2010
From: kuwerty at gmail.com (Krister Wombell)
Date: Wed, 15 Dec 2010 17:26:05 +0800
Subject: [llvm-commits] [PATCH] Linear scan allocator
In-Reply-To: <A2744119-A5CF-409F-94F7-1C16CAE67C9F@2pi.dk>
References: <AANLkTik55oj_a2ferkZgq=q8F37BDBrRJO4mrPYJ-ydM@mail.gmail.com>
	<A2744119-A5CF-409F-94F7-1C16CAE67C9F@2pi.dk>
Message-ID: <AANLkTi=E-gVU8+Jp2RLbF=0GMkWxTNc8Fh26dxzfcr9K@mail.gmail.com>

Hi Jakob,

Could you please not commit this for the moment.   I've noticed that
the spill weights for some phys regs are not infinite.  If I force the
weight to be infinite (as it should always be for phys regs?) with a
debugger then it avoids findIntervalsToSpill completely.  Looks like the
root of the bug is elsewhere.

Thanks, Krister



On Wed, Dec 15, 2010 at 1:06 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:

>
> On Dec 14, 2010, at 7:25 PM, Krister Wombell wrote:
>
> > I've come across a bug in RALinScan::assignRegOrStackSlotAtInterval that
> occurs when:
> >
> > - an interval conflicts with all physical registers in it's class
> > - and one of the phys regs has a lower spill weight then the interval
> being assigned
> > - and there are no active or inactive intervals (or no entries of an
> overlapping reg class)
> >
> > findIntervalsToSplit then runs but won't be able to find the best
> candidate as it fails to find a anything suitable in the 'active_' or
> 'inactive_' lists. The code asserts that there's nothing to spill.
> >
> > It's a fairly obscure set of circumstances but can happen if there is a
> register class with no callee saved registers and a call instruction (that
> implicitly defines all registers in that class).  It (probably?) also
> requires that the interval being assigned is itself the result of spilling
> as both the spill weight needs to be quite high.
> >
> > I've attached a fix that spills the current interval if
> findIntervalsToSplit returns nothing.
>
> It looks reasonable, do you have a test case?
>
> /jakob
>
>
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From fvbommel at gmail.com  Wed Dec 15 03:51:20 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Wed, 15 Dec 2010 09:51:20 -0000
Subject: [llvm-commits] [llvm] r121859 - in /llvm/trunk:
 lib/Transforms/Scalar/JumpThreading.cpp
 test/Transforms/JumpThreading/select.ll
Message-ID: <20101215095120.E1E422A6C12C@llvm.org>

Author: fvbommel
Date: Wed Dec 15 03:51:20 2010
New Revision: 121859

URL: http://llvm.org/viewvc/llvm-project?rev=121859&view=rev
Log:
Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.

Added:
    llvm/trunk/test/Transforms/JumpThreading/select.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=121859&r1=121858&r2=121859&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Wed Dec 15 03:51:20 2010
@@ -538,6 +538,40 @@
     }
   }
 
+  if (SelectInst *SI = dyn_cast<SelectInst>(I)) {
+    // Handle select instructions where at least one operand is a known constant
+    // and we can figure out the condition value for any predecessor block.
+    Constant *TrueVal = getKnownConstant(SI->getTrueValue(), Preference);
+    Constant *FalseVal = getKnownConstant(SI->getFalseValue(), Preference);
+    PredValueInfoTy Conds;
+    if ((TrueVal || FalseVal) &&
+        ComputeValueKnownInPredecessors(SI->getCondition(), BB, Conds,
+                                        WantInteger)) {
+      for (unsigned i = 0, e = Conds.size(); i != e; ++i) {
+        Constant *Cond = Conds[i].first;
+
+        // Figure out what value to use for the condition.
+        bool KnownCond;
+        if (ConstantInt *CI = dyn_cast<ConstantInt>(Cond)) {
+          // A known boolean.
+          KnownCond = CI->isOne();
+        } else {
+          assert(isa<UndefValue>(Cond) && "Unexpected condition value");
+          // Either operand will do, so be sure to pick the one that's a known
+          // constant.
+          // FIXME: Do this more cleverly if both values are known constants?
+          KnownCond = (TrueVal != 0);
+        }
+
+        // See if the select has a known constant value for this predecessor.
+        if (Constant *Val = KnownCond ? TrueVal : FalseVal)
+          Result.push_back(std::make_pair(Val, Conds[i].second));
+      }
+
+      return !Result.empty();
+    }
+  }
+
   // If all else fails, see if LVI can figure out a constant value for us.
   Constant *CI = LVI->getConstant(V, BB);
   if (Constant *KC = getKnownConstant(CI, Preference)) {

Added: llvm/trunk/test/Transforms/JumpThreading/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/select.ll?rev=121859&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/JumpThreading/select.ll (added)
+++ llvm/trunk/test/Transforms/JumpThreading/select.ll Wed Dec 15 03:51:20 2010
@@ -0,0 +1,123 @@
+; RUN: opt -S -jump-threading < %s | FileCheck %s
+
+declare void @foo()
+declare void @bar()
+declare void @baz()
+declare void @quux()
+
+
+; Jump threading of branch with select as condition.
+; Mostly theoretical since instruction combining simplifies all selects of
+; booleans where at least one operand is true/false/undef.
+
+; CHECK: @test_br
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 %cond, label %L1,
+define void @test_br(i1 %cond, i1 %value) nounwind {
+entry:
+  br i1 %cond, label %L0, label %L3
+L0:
+  %expr = select i1 %cond, i1 true, i1 %value
+  br i1 %expr, label %L1, label %L2
+
+L1:
+  call void @foo()
+  ret void
+L2:
+  call void @bar()
+  ret void
+L3:
+  call void @baz()
+  br label %L0
+}
+
+
+; Jump threading of switch with select as condition.
+
+; CHECK: @test_switch
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 %cond, label %L1,
+define void @test_switch(i1 %cond, i8 %value) nounwind {
+entry:
+  br i1 %cond, label %L0, label %L4
+L0:
+  %expr = select i1 %cond, i8 1, i8 %value
+  switch i8 %expr, label %L3 [i8 1, label %L1 i8 2, label %L2]
+
+L1:
+  call void @foo()
+  ret void
+L2:
+  call void @bar()
+  ret void
+L3:
+  call void @baz()
+  ret void
+L4:
+  call void @quux()
+  br label %L0
+}
+
+; Make sure the blocks in the indirectbr test aren't trivially removable as
+; successors by taking their addresses.
+ at anchor = constant [3 x i8*] [
+  i8* blockaddress(@test_indirectbr, %L1),
+  i8* blockaddress(@test_indirectbr, %L2),
+  i8* blockaddress(@test_indirectbr, %L3)
+]
+
+
+; Jump threading of indirectbr with select as address.
+
+; CHECK: @test_indirectbr
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 %cond, label %L1, label %L3
+define void @test_indirectbr(i1 %cond, i8* %address) nounwind {
+entry:
+  br i1 %cond, label %L0, label %L3
+L0:
+  %indirect.goto.dest = select i1 %cond, i8* blockaddress(@test_indirectbr, %L1), i8* %address
+  indirectbr i8* %indirect.goto.dest, [label %L1, label %L2, label %L3]
+
+L1:
+  call void @foo()
+  ret void
+L2:
+  call void @bar()
+  ret void
+L3:
+  call void @baz()
+  ret void
+}
+
+
+; A more complicated case: the condition is a select based on a comparison.
+
+; CHECK: @test_switch_cmp
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 %cond, label %L0, label %[[THREADED:[A-Za-z.0-9]+]]
+; CHECK: [[THREADED]]:
+; CHECK-NEXT: call void @quux
+; CHECK-NEXT: br label %L1
+define void @test_switch_cmp(i1 %cond, i32 %val, i8 %value) nounwind {
+entry:
+  br i1 %cond, label %L0, label %L4
+L0:
+  %val.phi = phi i32 [%val, %entry], [-1, %L4]
+  %cmp = icmp slt i32 %val.phi, 0
+  %expr = select i1 %cmp, i8 1, i8 %value
+  switch i8 %expr, label %L3 [i8 1, label %L1 i8 2, label %L2]
+
+L1:
+  call void @foo()
+  ret void
+L2:
+  call void @bar()
+  ret void
+L3:
+  call void @baz()
+  ret void
+L4:
+  call void @quux()
+  br label %L0
+}



From fvbommel at gmail.com  Wed Dec 15 04:03:38 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Wed, 15 Dec 2010 11:03:38 +0100
Subject: [llvm-commits] [Review request] Jump threading and 'select'.
In-Reply-To: <2E0F07F7-66CD-4DD9-A533-03137DE5A333@apple.com>
References: <AANLkTi=JO+ZgMAaz8w17qPwsO4MOC_xSPc0KwpsEG6Nf@mail.gmail.com>
	<2E0F07F7-66CD-4DD9-A533-03137DE5A333@apple.com>
Message-ID: <AANLkTinixf2a8N+7-tYkLQkaCxmTVHb0kpL5xtHu3kQG@mail.gmail.com>

On Wed, Dec 15, 2010 at 6:51 AM, Chris Lattner <clattner at apple.com> wrote:
> This looks ok to me. ?Please merge this:
>
> + ? ?if (TrueVal || FalseVal) {
> + ? ? ?PredValueInfoTy Conds;
> + ? ? ?if (ComputeValueKnownInPredecessors(SI->getCondition(), BB, Conds,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?WantInteger)) {
>
> Into something like this to reduce indentation:
>
> + ? ?PredValueInfoTy Conds;
> + ? ?if ((TrueVal || FalseVal) &&
> ? ? ? ? ComputeValueKnownInPredecessors(SI->getCondition(), BB, Conds, ..
>
> and apply.

r121859.

> Is it helpful to know the condition of the select in one of the predecessors?

I haven't actually measured how often this fires on real code, but the
standard pass order does run -simplifycfg once before -jump-threading,
and -simplifycfg does have the tendency to turn some PHI nodes into
selects. So intuitively this might allow -jump-threading to recover
some of the "juicy" information that was previously lost by that.
On the other hand, since -scalarrepl doesn't run before that
-simplifycfg there probably won't be a lot of PHIs for it to eat yet,
so this case might only matter for PHIs inserted directly by the
frontend.

The second -jump-threading run might do better, once the code has been
optimized more.
But again, this is mostly guesswork.


From baldrick at free.fr  Wed Dec 15 05:02:22 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 15 Dec 2010 11:02:22 -0000
Subject: [llvm-commits] [llvm] r121860 -
	/llvm/trunk/lib/Analysis/InstructionSimplify.cpp
Message-ID: <20101215110223.02EC62A6C12C@llvm.org>

Author: baldrick
Date: Wed Dec 15 05:02:22 2010
New Revision: 121860

URL: http://llvm.org/viewvc/llvm-project?rev=121860&view=rev
Log:
If we detect that the instruction we are simplifying is unreachable, arrange for
it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.

Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=121860&r1=121859&r2=121860&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Dec 15 05:02:22 2010
@@ -441,7 +441,7 @@
 
   // A ^ undef -> undef
   if (isa<UndefValue>(Op1))
-    return UndefValue::get(Op0->getType());
+    return Op1;
 
   // A ^ 0 = A
   if (match(Op1, m_Zero()))
@@ -868,8 +868,8 @@
 
   /// If called on unreachable code, the above logic may report that the
   /// instruction simplified to itself.  Make life easier for users by
-  /// detecting that case here, returning null if it occurs.
-  return Result == I ? 0 : Result;
+  /// detecting that case here, returning a safe value instead.
+  return Result == I ? UndefValue::get(I->getType()) : Result;
 }
 
 /// ReplaceAndSimplifyAllUses - Perform From->replaceAllUsesWith(To) and then



From baldrick at free.fr  Wed Dec 15 08:07:39 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 15 Dec 2010 14:07:39 -0000
Subject: [llvm-commits] [llvm] r121861 - in /llvm/trunk:
 include/llvm/Analysis/InstructionSimplify.h
 lib/Analysis/InstructionSimplify.cpp
 lib/Transforms/InstCombine/InstCombineAddSub.cpp
 test/Analysis/BasicAA/modref.ll
Message-ID: <20101215140739.98AF22A6C12C@llvm.org>

Author: baldrick
Date: Wed Dec 15 08:07:39 2010
New Revision: 121861

URL: http://llvm.org/viewvc/llvm-project?rev=121861&view=rev
Log:
Move Sub simplifications and additional Add simplifications out of
instcombine and into InstructionSimplify.

Modified:
    llvm/trunk/include/llvm/Analysis/InstructionSimplify.h
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    llvm/trunk/test/Analysis/BasicAA/modref.ll

Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InstructionSimplify.h?rev=121861&r1=121860&r2=121861&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/InstructionSimplify.h (original)
+++ llvm/trunk/include/llvm/Analysis/InstructionSimplify.h Wed Dec 15 08:07:39 2010
@@ -29,6 +29,11 @@
   Value *SimplifyAddInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW,
                          const TargetData *TD = 0, const DominatorTree *DT = 0);
 
+  /// SimplifySubInst - Given operands for a Sub, see if we can
+  /// fold the result.  If not, this returns null.
+  Value *SimplifySubInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW,
+                         const TargetData *TD = 0, const DominatorTree *DT = 0);
+
   /// SimplifyAndInst - Given operands for an And, see if we can
   /// fold the result.  If not, this returns null.
   Value *SimplifyAndInst(Value *LHS, Value *RHS, const TargetData *TD = 0,

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=121861&r1=121860&r2=121861&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Dec 15 08:07:39 2010
@@ -242,17 +242,25 @@
     std::swap(Op0, Op1);
   }
 
-  if (Constant *Op1C = dyn_cast<Constant>(Op1)) {
-    // X + undef -> undef
-    if (isa<UndefValue>(Op1C))
-      return Op1C;
+  // X + undef -> undef
+  if (isa<UndefValue>(Op1))
+    return Op1;
 
-    // X + 0 --> X
-    if (Op1C->isNullValue())
-      return Op0;
-  }
+  // X + 0 -> X
+  if (match(Op1, m_Zero()))
+    return Op0;
 
-  // FIXME: Could pull several more out of instcombine.
+  // X + (Y - X) -> Y
+  // (Y - X) + X -> Y
+  Value *Y = 0;
+  if (match(Op1, m_Sub(m_Value(Y), m_Specific(Op0))) ||
+      match(Op0, m_Sub(m_Value(Y), m_Specific(Op1))))
+    return Y;
+
+  // X + ~X -> -1   since   ~X = -X-1
+  if (match(Op0, m_Not(m_Specific(Op1))) ||
+      match(Op1, m_Not(m_Specific(Op0))))
+    return Constant::getAllOnesValue(Op0->getType());
 
   // Threading Add over selects and phi nodes is pointless, so don't bother.
   // Threading over the select in "A + select(cond, B, C)" means evaluating
@@ -266,6 +274,49 @@
   return 0;
 }
 
+/// SimplifySubInst - Given operands for a Sub, see if we can
+/// fold the result.  If not, this returns null.
+Value *llvm::SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
+                             const TargetData *TD, const DominatorTree *) {
+  if (Constant *CLHS = dyn_cast<Constant>(Op0))
+    if (Constant *CRHS = dyn_cast<Constant>(Op1)) {
+      Constant *Ops[] = { CLHS, CRHS };
+      return ConstantFoldInstOperands(Instruction::Sub, CLHS->getType(),
+                                      Ops, 2, TD);
+    }
+
+  // X - undef -> undef
+  // undef - X -> undef
+  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
+    return UndefValue::get(Op0->getType());
+
+  // X - 0 -> X
+  if (match(Op1, m_Zero()))
+    return Op0;
+
+  // X - X -> 0
+  if (Op0 == Op1)
+    return Constant::getNullValue(Op0->getType());
+
+  // (X + Y) - Y -> X
+  // (Y + X) - Y -> X
+  Value *X = 0;
+  if (match(Op0, m_Add(m_Value(X), m_Specific(Op1))) ||
+      match(Op0, m_Add(m_Specific(Op1), m_Value(X))))
+    return X;
+
+  // Threading Sub over selects and phi nodes is pointless, so don't bother.
+  // Threading over the select in "A - select(cond, B, C)" means evaluating
+  // "A-B" and "A-C" and seeing if they are equal; but they are equal if and
+  // only if B and C are equal.  If B and C are equal then (since we assume
+  // that operands have already been simplified) "select(cond, B, C)" should
+  // have been simplified to the common value of B and C already.  Analysing
+  // "A-B" and "A-C" thus gains nothing, but costs compile time.  Similarly
+  // for threading over phi nodes.
+
+  return 0;
+}
+
 /// SimplifyAndInst - Given operands for an And, see if we can
 /// fold the result.  If not, this returns null.
 static Value *SimplifyAndInst(Value *Op0, Value *Op1, const TargetData *TD,
@@ -835,6 +886,12 @@
                              cast<BinaryOperator>(I)->hasNoUnsignedWrap(),
                              TD, DT);
     break;
+  case Instruction::Sub:
+    Result = SimplifySubInst(I->getOperand(0), I->getOperand(1),
+                             cast<BinaryOperator>(I)->hasNoSignedWrap(),
+                             cast<BinaryOperator>(I)->hasNoUnsignedWrap(),
+                             TD, DT);
+    break;
   case Instruction::And:
     Result = SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD, DT);
     break;

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp?rev=121861&r1=121860&r2=121861&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAddSub.cpp Wed Dec 15 08:07:39 2010
@@ -154,17 +154,6 @@
     // X + X --> X << 1
     if (LHS == RHS)
       return BinaryOperator::CreateShl(LHS, ConstantInt::get(I.getType(), 1));
-
-    if (Instruction *RHSI = dyn_cast<Instruction>(RHS)) {
-      if (RHSI->getOpcode() == Instruction::Sub)
-        if (LHS == RHSI->getOperand(1))                   // A + (B - A) --> B
-          return ReplaceInstUsesWith(I, RHSI->getOperand(0));
-    }
-    if (Instruction *LHSI = dyn_cast<Instruction>(LHS)) {
-      if (LHSI->getOpcode() == Instruction::Sub)
-        if (RHS == LHSI->getOperand(1))                   // (B - A) + A --> B
-          return ReplaceInstUsesWith(I, LHSI->getOperand(0));
-    }
   }
 
   // -A + B  -->  B - A
@@ -201,11 +190,6 @@
   if (dyn_castFoldableMul(RHS, C2) == LHS)
     return BinaryOperator::CreateMul(LHS, AddOne(C2));
 
-  // X + ~X --> -1   since   ~X = -X-1
-  if (match(LHS, m_Not(m_Specific(RHS))) ||
-      match(RHS, m_Not(m_Specific(LHS))))
-    return ReplaceInstUsesWith(I, Constant::getAllOnesValue(I.getType()));
-
   // A+B --> A|B iff A and B have no bits set in common.
   if (const IntegerType *IT = dyn_cast<IntegerType>(I.getType())) {
     APInt Mask = APInt::getAllOnesValue(IT->getBitWidth());
@@ -547,8 +531,9 @@
 Instruction *InstCombiner::visitSub(BinaryOperator &I) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
 
-  if (Op0 == Op1)                        // sub X, X  -> 0
-    return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
+  if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(),
+                                 I.hasNoUnsignedWrap(), TD))
+    return ReplaceInstUsesWith(I, V);
 
   if (Instruction *NV = SimplifyByFactorizing(I)) // (A*B)-(A*C) -> A*(B-C)
     return NV;
@@ -561,10 +546,6 @@
     return Res;
   }
 
-  if (isa<UndefValue>(Op0))
-    return ReplaceInstUsesWith(I, Op0);    // undef - X -> undef
-  if (isa<UndefValue>(Op1))
-    return ReplaceInstUsesWith(I, Op1);    // X - undef -> undef
   if (I.getType()->isIntegerTy(1))
     return BinaryOperator::CreateXor(Op0, Op1);
   
@@ -693,12 +674,7 @@
   }
 
   if (BinaryOperator *Op0I = dyn_cast<BinaryOperator>(Op0)) {
-    if (Op0I->getOpcode() == Instruction::Add) {
-      if (Op0I->getOperand(0) == Op1)             // (Y+X)-Y == X
-        return ReplaceInstUsesWith(I, Op0I->getOperand(1));
-      else if (Op0I->getOperand(1) == Op1)        // (X+Y)-Y == X
-        return ReplaceInstUsesWith(I, Op0I->getOperand(0));
-    } else if (Op0I->getOpcode() == Instruction::Sub) {
+    if (Op0I->getOpcode() == Instruction::Sub) {
       if (Op0I->getOperand(0) == Op1)             // (X-Y)-X == -Y
         return BinaryOperator::CreateNeg(Op0I->getOperand(1),
                                          I.getName());

Modified: llvm/trunk/test/Analysis/BasicAA/modref.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/modref.ll?rev=121861&r1=121860&r2=121861&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/modref.ll (original)
+++ llvm/trunk/test/Analysis/BasicAA/modref.ll Wed Dec 15 08:07:39 2010
@@ -105,7 +105,7 @@
 ; CHECK: load i32* @G
 ; CHECK: memset.p0i8.i32
 ; CHECK-NOT: load
-; CHECK: sub i32 %tmp, %tmp
+; CHECK: ret i32 0
 }
 
 ; Verify that basicaa is handling variable length memcpy, knowing it doesn't
@@ -120,7 +120,7 @@
 ; CHECK: load i32* @G
 ; CHECK: memcpy.p0i8.p0i8.i32
 ; CHECK-NOT: load
-; CHECK: sub i32 %tmp, %tmp
+; CHECK: ret i32 0
 }
 
 define i8 @test6(i8* %p, i8* noalias %a) {



From daniel at zuster.org  Wed Dec 15 10:20:54 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 15 Dec 2010 08:20:54 -0800
Subject: [llvm-commits] [llvm] r121408 - in /llvm/trunk:
 include/llvm/MC/MCCodeEmitter.h lib/MC/MCAssembler.cpp
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMMCCodeEmitter.cpp
In-Reply-To: <20101209202752.F1BEE2A6C12C@llvm.org>
References: <20101209202752.F1BEE2A6C12C@llvm.org>
Message-ID: <AANLkTinu108+Lydk5obP4F0ag41WNaRzegWf+f3Wc9KS@mail.gmail.com>

Hi Owen,

On Thu, Dec 9, 2010 at 12:27 PM, Owen Anderson <resistor at mac.com> wrote:
> Author: resistor
> Date: Thu Dec ?9 14:27:52 2010
> New Revision: 121408
>
> URL: http://llvm.org/viewvc/llvm-project?rev=121408&view=rev
> Log:
> Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
> the offset. ?Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
> this. ?It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
> adjusted accordingly.

Ok; but I have a number of concerns here...

First and most critically, please factor any MC infrastructure changes
into separate commits. I don't really care how the individual targets
work (we can fix it incrementally), but I do care about trying to get
the core MC design "right".

Subsequent comments inline...

> Modified:
> ? ?llvm/trunk/include/llvm/MC/MCCodeEmitter.h
> ? ?llvm/trunk/lib/MC/MCAssembler.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/MC/MCCodeEmitter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeEmitter.h?rev=121408&r1=121407&r2=121408&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCCodeEmitter.h (original)
> +++ llvm/trunk/include/llvm/MC/MCCodeEmitter.h Thu Dec ?9 14:27:52 2010
> @@ -25,7 +25,10 @@
> ? enum FixupKindFlags {
> ? ? /// Is this fixup kind PCrelative? This is used by the assembler backend to
> ? ? /// evaluate fixup values in a target independent manner when possible.
> - ? ?FKF_IsPCRel = (1 << 0)
> + ? ?FKF_IsPCRel = (1 << 0),
> +
> + ? ?// Should this fixup kind force a 4-byte aligned effective PC value?
> + ? ?FKF_IsAligned = (1 << 1)

Please use doxyments where appropriate.

I find the name is underspecified:
  1. IsAligned doesn't include any mention of the magic "4" number.
  2. Is there any chance any non ARM platform will use this?
  3. Calling this "aligned" is a bit of a misnomer. Aligned in most
places in the compiler means "aligned up", and this means "aligned
down".
Can we call it something like "IsAlignedDownToWord", and make the
semantics match that? Or IsAlignedDownTo32Bits?

> ? };
>
> ? /// A target specific name for the fixup kind. The names will be unique for
>
> Modified: llvm/trunk/lib/MC/MCAssembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121408&r1=121407&r2=121408&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAssembler.cpp (original)
> +++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Dec ?9 14:27:52 2010
> @@ -253,8 +253,15 @@
> ? if (IsResolved)
> ? ? IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
>
> - ?if (IsPCRel)
> - ? ?Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
> + ?if (IsPCRel) {
> + ? ?bool ShouldAlignPC = Emitter.getFixupKindInfo(
> + ? ? ? ? ? ? ? ? ? ? ? ?Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned;
> + ? ?// PC should be aligned to a 4-byte value.
> + ? ?if (ShouldAlignPC)
> + ? ? ?Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3);
> + ? ?else
> + ? ? ?Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
> + ?}

I would write this as:
--
uint32_t Offset = Fixup.getOfset()

if (ShouldAlignPC)
  Offset = Offset & ~0x3;

Value -= Layout.getFragmentOffset(DF) + Offset;
--
Which makes more sense to me (treating these as flags).

I'd also love to see an assert somewhere that this flag can't be set
without IsPCRel.

Thanks!
 - Daniel

>
> ? return IsResolved;
> ?}
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121408&r1=121407&r2=121408&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec ?9 14:27:52 2010
> @@ -100,10 +100,10 @@
> ? }
> ? case ARM::fixup_arm_ldst_pcrel_12:
> ? ? // ARM PC-relative values are offset by 8.
> - ? ?Value -= 6;
> + ? ?Value -= 4;
> ? case ARM::fixup_t2_ldst_pcrel_12: {
> ? ? // Offset by 4, adjusted by two due to the half-word ordering of thumb.
> - ? ?Value -= 2;
> + ? ?Value -= 4;
> ? ? bool isAdd = true;
> ? ? if ((int64_t)Value < 0) {
> ? ? ? Value = -Value;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121408&r1=121407&r2=121408&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Dec ?9 14:27:52 2010
> @@ -47,7 +47,8 @@
> ? ? const static MCFixupKindInfo Infos[] = {
> ? ? ? // name ? ? ? ? ? ? ? ? ? ? ? off ? bits ?flags
> ? ? ? { "fixup_arm_ldst_pcrel_12", ?1, ? ?24, ? MCFixupKindInfo::FKF_IsPCRel },
> - ? ? ?{ "fixup_t2_ldst_pcrel_12", ? 0, ? ?32, ? MCFixupKindInfo::FKF_IsPCRel },
> + ? ? ?{ "fixup_t2_ldst_pcrel_12", ? 0, ? ?32, ? MCFixupKindInfo::FKF_IsPCRel |
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCFixupKindInfo::FKF_IsAligned},
> ? ? ? { "fixup_arm_pcrel_10", ? ? ? 1, ? ?24, ? MCFixupKindInfo::FKF_IsPCRel },
> ? ? ? { "fixup_t2_pcrel_10", ? ? ? ?0, ? ?32, ? MCFixupKindInfo::FKF_IsPCRel },
> ? ? ? { "fixup_arm_adr_pcrel_12", ? 1, ? ?24, ? MCFixupKindInfo::FKF_IsPCRel },
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From jan_sjodin at yahoo.com  Wed Dec 15 10:42:48 2010
From: jan_sjodin at yahoo.com (Jan Sjodin)
Date: Wed, 15 Dec 2010 08:42:48 -0800 (PST)
Subject: [llvm-commits] Issue with Win64 local area stack offset
In-Reply-To: <AANLkTinPqFeJKmzCR1Kg+f3WiBinptxLjmqiZ2A-20Kk@mail.gmail.com>
References: <489333.28347.qm@web55604.mail.re4.yahoo.com>
	<832540.73670.qm@web55606.mail.re4.yahoo.com>
	<AANLkTikOHXmTk=3TCz709WhUUxtOQ51oOOCiRy-XVCJU@mail.gmail.com>
	<921691.29161.qm@web55608.mail.re4.yahoo.com>
	<AANLkTinPqFeJKmzCR1Kg+f3WiBinptxLjmqiZ2A-20Kk@mail.gmail.com>
Message-ID: <212727.70944.qm@web55605.mail.re4.yahoo.com>

Yes, I should have tried to finish my patch, but other things got in the way. 
Thanks for looking into it!
I explained i the previous emails what I believed was wrong with the old 
implementation.
- Jan



----- Original Message ----
> From: NAKAMURA Takumi <geek4civic at gmail.com>
> To: Jan Sjodin <jan_sjodin at yahoo.com>
> Cc: Anton Korobeynikov <anton at korobeynikov.info>; llvm-commits at cs.uiuc.edu
> Sent: Mon, December 13, 2010 11:09:42 PM
> Subject: Re: [llvm-commits] Issue with Win64 local area stack offset
> 
> Jan,
> 
> I am sorry, I missed your patch and I have proposed yet another  similar 
patch.
> 
> IMHO, r112875 was incomplete. Although it was better for  two tests, I
> met wrong outputs with recent tests, provided by Cameron  Esfahani.
> 
> # win64_params.ll
> f6:
>          movl    80(%rsp), %eax
>         addl     72(%rsp), %eax
>         ret
> 
> The offsets +72  and +80 do not point %p5 and %p6!
> 
> "win64_vararg.ll" had been improved  after that.
> 
> 
> ...Takumi
> 

From bob.wilson at apple.com  Wed Dec 15 10:58:42 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 15 Dec 2010 16:58:42 -0000
Subject: [llvm-commits] [llvm] r121867 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20101215165842.6F38B2A6C12C@llvm.org>

Author: bwilson
Date: Wed Dec 15 10:58:42 2010
New Revision: 121867

URL: http://llvm.org/viewvc/llvm-project?rev=121867&view=rev
Log:
Fix Neon intrinsic immediate range checking for some double-register operands.
Some quad-register intrinsics with lane operands only take a double-register
operand for the vector containing the lane.  The valid range of lane numbers
is then half as big as you would expect from the quad-register type.
Note: This currently has no effect because those intrinsics are now handled
entirely in the header file using __builtin_shufflevector, which does its own
range checking, but I want to use this for generating tests.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=121867&r1=121866&r2=121867&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Wed Dec 15 10:58:42 2010
@@ -1213,10 +1213,11 @@
   OS << "\n";
 }
 
-static unsigned RangeFromType(StringRef typestr) {
+static unsigned RangeFromType(const char mod, StringRef typestr) {
   // base type to get the type string for.
   bool quad = false, dummy = false;
   char type = ClassifyType(typestr, quad, dummy, dummy);
+  type = ModType(mod, type, quad, dummy, dummy, dummy, dummy, dummy);
 
   switch (type) {
     case 'c':
@@ -1359,7 +1360,8 @@
 
     // Functions which do not have an immediate do not need to have range
     // checking code emitted.
-    if (Proto.find('i') == std::string::npos)
+    size_t immPos = Proto.find('i');
+    if (immPos == std::string::npos)
       continue;
 
     SmallVector<StringRef, 16> TypeVec;
@@ -1386,7 +1388,9 @@
         }
         rangestr += "u = RFT(TV" + shiftstr + ")";
       } else {
-        rangestr = "u = " + utostr(RangeFromType(TypeVec[ti]));
+        // The immediate generally refers to a lane in the preceding argument.
+        assert(immPos > 0 && "unexpected immediate operand");
+        rangestr = "u = " + utostr(RangeFromType(Proto[immPos-1], TypeVec[ti]));
       }
       // Make sure cases appear only once by uniquing them in a string map.
       namestr = MangleName(name, TypeVec[ti], ck);



From bob.wilson at apple.com  Wed Dec 15 10:58:45 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 15 Dec 2010 16:58:45 -0000
Subject: [llvm-commits] [llvm] r121868 - in /llvm/trunk/utils/TableGen:
 NeonEmitter.cpp NeonEmitter.h TableGen.cpp
Message-ID: <20101215165845.708582A6C12D@llvm.org>

Author: bwilson
Date: Wed Dec 15 10:58:45 2010
New Revision: 121868

URL: http://llvm.org/viewvc/llvm-project?rev=121868&view=rev
Log:
Add a Neon intrinsic test generator.
This is still a WIP.  It's already good enough to expose a few bugs, though.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp
    llvm/trunk/utils/TableGen/NeonEmitter.h
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=121868&r1=121867&r2=121868&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Wed Dec 15 10:58:45 2010
@@ -18,7 +18,8 @@
 // CodeGen library.
 //
 // Additional validation code can be generated by this file when runHeader() is
-// called, rather than the normal run() entry point.
+// called, rather than the normal run() entry point.  A complete set of tests
+// for Neon intrinsics can be generated by calling the runTests() entry point.
 //
 //===----------------------------------------------------------------------===//
 
@@ -1423,3 +1424,107 @@
   }
   OS << "#endif\n\n";
 }
+
+/// GenTest - Write out a test for the intrinsic specified by the name and
+/// type strings, including the embedded patterns for FileCheck to match.
+static std::string GenTest(const std::string &name,
+                           const std::string &proto,
+                           StringRef outTypeStr, StringRef inTypeStr,
+                           bool isShift) {
+  assert(!proto.empty() && "");
+  std::string s;
+
+  // Function name with type suffix
+  std::string mangledName = MangleName(name, outTypeStr, ClassS);
+  if (outTypeStr != inTypeStr) {
+    // If the input type is different (e.g., for vreinterpret), append a suffix
+    // for the input type.  String off a "Q" (quad) prefix so that MangleName
+    // does not insert another "q" in the name.
+    unsigned typeStrOff = (inTypeStr[0] == 'Q' ? 1 : 0);
+    StringRef inTypeNoQuad = inTypeStr.substr(typeStrOff);
+    mangledName = MangleName(mangledName, inTypeNoQuad, ClassS);
+  }
+
+  // Emit the FileCheck patterns.
+  s += "// CHECK: test_" + mangledName + "\n";
+  // s += "// CHECK: \n"; // FIXME: + expected instruction opcode.
+
+  // Emit the start of the test function.
+  s += TypeString(proto[0], outTypeStr) + " test_" + mangledName + "(";
+  char arg = 'a';
+  std::string comma;
+  for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) {
+    // Do not create arguments for values that must be immediate constants.
+    if (proto[i] == 'i')
+      continue;
+    s += comma + TypeString(proto[i], inTypeStr) + " ";
+    s.push_back(arg);
+    comma = ", ";
+  }
+  s += ") { \\\n  ";
+
+  if (proto[0] != 'v')
+    s += "return ";
+  s += mangledName + "(";
+  arg = 'a';
+  for (unsigned i = 1, e = proto.size(); i != e; ++i, ++arg) {
+    if (proto[i] == 'i') {
+      // For immediate operands, test the maximum value.
+      if (isShift)
+        s += "1"; // FIXME
+      else
+        // The immediate generally refers to a lane in the preceding argument.
+        s += utostr(RangeFromType(proto[i-1], inTypeStr));
+    } else {
+      s.push_back(arg);
+    }
+    if ((i + 1) < e)
+      s += ", ";
+  }
+  s += ");\n}\n\n";
+  return s;
+}
+
+/// runTests - Write out a complete set of tests for all of the Neon
+/// intrinsics.
+void NeonEmitter::runTests(raw_ostream &OS) {
+  OS <<
+    "// RUN: %clang_cc1 -triple thumbv7-apple-darwin \\\n"
+    "// RUN:  -target-cpu cortex-a8 -ffreestanding -S -o - %s | FileCheck %s\n"
+    "\n"
+    "#include <arm_neon.h>\n"
+    "\n";
+
+  std::vector<Record*> RV = Records.getAllDerivedDefinitions("Inst");
+  for (unsigned i = 0, e = RV.size(); i != e; ++i) {
+    Record *R = RV[i];
+    std::string name = R->getValueAsString("Name");
+    std::string Proto = R->getValueAsString("Prototype");
+    std::string Types = R->getValueAsString("Types");
+    bool isShift = R->getValueAsBit("isShift");
+
+    SmallVector<StringRef, 16> TypeVec;
+    ParseTypes(R, Types, TypeVec);
+
+    OpKind kind = OpMap[R->getValueAsDef("Operand")->getName()];
+    for (unsigned ti = 0, te = TypeVec.size(); ti != te; ++ti) {
+      if (kind == OpReinterpret) {
+        bool outQuad = false;
+        bool dummy = false;
+        (void)ClassifyType(TypeVec[ti], outQuad, dummy, dummy);
+        for (unsigned srcti = 0, srcte = TypeVec.size();
+             srcti != srcte; ++srcti) {
+          bool inQuad = false;
+          (void)ClassifyType(TypeVec[srcti], inQuad, dummy, dummy);
+          if (srcti == ti || inQuad != outQuad)
+            continue;
+          OS << GenTest(name, Proto, TypeVec[ti], TypeVec[srcti], isShift);
+        }
+      } else {
+        OS << GenTest(name, Proto, TypeVec[ti], TypeVec[ti], isShift);
+      }
+    }
+    OS << "\n";
+  }
+}
+

Modified: llvm/trunk/utils/TableGen/NeonEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.h?rev=121868&r1=121867&r2=121868&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.h (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.h Wed Dec 15 10:58:45 2010
@@ -168,6 +168,9 @@
     // runHeader - Emit all the __builtin prototypes used in arm_neon.h
     void runHeader(raw_ostream &o);
 
+    // runTests - Emit tests for all the Neon intrinsics.
+    void runTests(raw_ostream &o);
+
   private:
     void emitIntrinsic(raw_ostream &OS, Record *R);
   };

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=121868&r1=121867&r2=121868&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Dec 15 10:58:45 2010
@@ -75,6 +75,7 @@
   GenEDInfo,
   GenArmNeon,
   GenArmNeonSema,
+  GenArmNeonTest,
   PrintEnums
 };
 
@@ -147,6 +148,8 @@
                                "Generate arm_neon.h for clang"),
                     clEnumValN(GenArmNeonSema, "gen-arm-neon-sema",
                                "Generate ARM NEON sema support for clang"),
+                    clEnumValN(GenArmNeonTest, "gen-arm-neon-test",
+                               "Generate ARM NEON tests for clang"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValEnd));
@@ -330,6 +333,9 @@
     case GenArmNeonSema:
       NeonEmitter(Records).runHeader(Out.os());
       break;
+    case GenArmNeonTest:
+      NeonEmitter(Records).runTests(Out.os());
+      break;
     case PrintEnums:
     {
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);



From stoklund at 2pi.dk  Wed Dec 15 11:41:20 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 15 Dec 2010 17:41:20 -0000
Subject: [llvm-commits] [llvm] r121870 - in /llvm/trunk/lib/CodeGen:
	SplitKit.cpp SplitKit.h
Message-ID: <20101215174120.2796D2A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 11:41:19 2010
New Revision: 121870

URL: http://llvm.org/viewvc/llvm-project?rev=121870&view=rev
Log:
Separate SplitAnalysis::getSplitLoops().

This method returns the set of loops with uses that are candidates for
splitting.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=121870&r1=121869&r2=121870&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Dec 15 11:41:19 2010
@@ -257,12 +257,11 @@
   analyzeUses();
 }
 
-const MachineLoop *SplitAnalysis::getBestSplitLoop() {
-  assert(curli_ && "Call analyze() before getBestSplitLoop");
+void SplitAnalysis::getSplitLoops(LoopPtrSet &Loops) {
+  assert(curli_ && "Call analyze() before getSplitLoops");
   if (usingLoops_.empty())
-    return 0;
+    return;
 
-  LoopPtrSet Loops;
   LoopBlocks Blocks;
   BlockPtrSet CriticalExits;
 
@@ -280,11 +279,11 @@
       // FIXME: We could split a live range with multiple uses in a peripheral
       // block and still make progress. However, it is possible that splitting
       // another live range will insert copies into a peripheral block, and
-      // there is a small chance we can enter an infinity loop, inserting copies
+      // there is a small chance we can enter an infinite loop, inserting copies
       // forever.
       // For safety, stick to splitting live ranges with uses outside the
       // periphery.
-      DEBUG(dbgs() << ": multiple peripheral uses\n");
+      DEBUG(dbgs() << ": multiple peripheral uses");
       break;
     case ContainedInLoop:
       DEBUG(dbgs() << ": fully contained\n");
@@ -302,9 +301,13 @@
     Loops.insert(Loop);
   }
 
-  DEBUG(dbgs() << "  getBestSplitLoop found " << Loops.size()
+  DEBUG(dbgs() << "  getSplitLoops found " << Loops.size()
                << " candidate loops.\n");
+}
 
+const MachineLoop *SplitAnalysis::getBestSplitLoop() {
+  LoopPtrSet Loops;
+  getSplitLoops(Loops);
   if (Loops.empty())
     return 0;
 

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=121870&r1=121869&r2=121870&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Wed Dec 15 11:41:19 2010
@@ -133,6 +133,10 @@
   /// these edges, but they do require special treatment.
   void getCriticalPreds(const LoopBlocks &Blocks, BlockPtrSet &CriticalPreds);
 
+  /// getSplitLoops - Get the set of loops that have curli uses and would be
+  /// profitable to split.
+  void getSplitLoops(LoopPtrSet&);
+
   /// getBestSplitLoop - Return the loop where curli may best be split to a
   /// separate register, or NULL.
   const MachineLoop *getBestSplitLoop();



From stoklund at 2pi.dk  Wed Dec 15 11:49:53 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 15 Dec 2010 17:49:53 -0000
Subject: [llvm-commits] [llvm] r121871 - in /llvm/trunk/lib/CodeGen:
	SplitKit.cpp SplitKit.h
Message-ID: <20101215174953.1CDE12A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 11:49:52 2010
New Revision: 121871

URL: http://llvm.org/viewvc/llvm-project?rev=121871&view=rev
Log:
Detect and enumerate bypass loops.

Bypass loops have the current live range live through, but contain no uses or
defs. Splitting around a bypass loop can free registers for other uses inside
the loop by spilling the split range.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=121871&r1=121870&r2=121871&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Dec 15 11:49:52 2010
@@ -325,6 +325,36 @@
   return Best;
 }
 
+/// isBypassLoop - Return true if curli is live through Loop and has no uses
+/// inside the loop. Bypass loops are candidates for splitting because it can
+/// prevent interference inside the loop.
+bool SplitAnalysis::isBypassLoop(const MachineLoop *Loop) {
+  // If curli is live into the loop header and there are no uses in the loop, it
+  // must be live in the entire loop and live on at least one exiting edge.
+  return !usingLoops_.count(Loop) &&
+         lis_.isLiveInToMBB(*curli_, Loop->getHeader());
+}
+
+/// getBypassLoops - Get all the maximal bypass loops. These are the bypass
+/// loops whose parent is not a bypass loop.
+void SplitAnalysis::getBypassLoops(LoopPtrSet &BypassLoops) {
+  SmallVector<MachineLoop*, 8> Todo(loops_.begin(), loops_.end());
+  while (!Todo.empty) {
+    MachineLoop *Loop = Todo.pop_back_val();
+    if (!usingLoops_.count(Loop)) {
+      // This is either a bypass loop or completely irrelevant.
+      if (lis_.isLiveInToMBB(*curli_, Loop->getHeader()))
+        BypassLoops.insert(Loop);
+      // Either way, skip the child loops.
+      continue;
+    }
+
+    // The child loops may be bypass loops.
+    Todo.append(Loop->begin(), Loop->end());
+  }
+}
+
+
 //===----------------------------------------------------------------------===//
 //                               LiveIntervalMap
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=121871&r1=121870&r2=121871&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Wed Dec 15 11:49:52 2010
@@ -141,6 +141,15 @@
   /// separate register, or NULL.
   const MachineLoop *getBestSplitLoop();
 
+  /// isBypassLoop - Return true if curli is live through Loop and has no uses
+  /// inside the loop. Bypass loops are candidates for splitting because it can
+  /// prevent interference inside the loop.
+  bool isBypassLoop(const MachineLoop *Loop);
+
+  /// getBypassLoops - Get all the maximal bypass loops. These are the bypass
+  /// loops whose parent is not a bypass loop.
+  void getBypassLoops(LoopPtrSet&);
+
   /// getMultiUseBlocks - Add basic blocks to Blocks that may benefit from
   /// having curli split to a new live interval. Return true if Blocks can be
   /// passed to SplitEditor::splitSingleBlocks.



From stoklund at 2pi.dk  Wed Dec 15 12:07:48 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 15 Dec 2010 18:07:48 -0000
Subject: [llvm-commits] [llvm] r121872 - /llvm/trunk/lib/CodeGen/SplitKit.cpp
Message-ID: <20101215180748.E742E2A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 12:07:48 2010
New Revision: 121872

URL: http://llvm.org/viewvc/llvm-project?rev=121872&view=rev
Log:
Fix build.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=121872&r1=121871&r2=121872&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Dec 15 12:07:48 2010
@@ -339,7 +339,7 @@
 /// loops whose parent is not a bypass loop.
 void SplitAnalysis::getBypassLoops(LoopPtrSet &BypassLoops) {
   SmallVector<MachineLoop*, 8> Todo(loops_.begin(), loops_.end());
-  while (!Todo.empty) {
+  while (!Todo.empty()) {
     MachineLoop *Loop = Todo.pop_back_val();
     if (!usingLoops_.count(Loop)) {
       // This is either a bypass loop or completely irrelevant.



From nlewycky at google.com  Wed Dec 15 12:20:02 2010
From: nlewycky at google.com (Nick Lewycky)
Date: Wed, 15 Dec 2010 10:20:02 -0800
Subject: [llvm-commits] patch: "minor" LazyValueInfo cleanup
Message-ID: <AANLkTikmxzDkzLpsZG+udfAZYZtMwkeb_rg6_qnX8_Eh@mail.gmail.com>

This patch is basically a cleanup of some of LVI, as I start hacking on it.
 * mergeIn now uses constant folding for constants that are provably
not-equal.
 * sink some sanity checks from the get*() methods into the mark*() methods,
to ensure that we never have a constant/notconstant ConstantInt
 * some textual cleanups, whitespace changes, removing "else" after return.

Please review!

Nick
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From gohman at apple.com  Wed Dec 15 12:45:20 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 18:45:20 -0000
Subject: [llvm-commits] [llvm] r121874 - /llvm/trunk/docs/AliasAnalysis.html
Message-ID: <20101215184520.5B45F2A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 12:45:20 2010
New Revision: 121874

URL: http://llvm.org/viewvc/llvm-project?rev=121874&view=rev
Log:
Document some more AliasAnalysis infrastructure limitations.

Modified:
    llvm/trunk/docs/AliasAnalysis.html

Modified: llvm/trunk/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=121874&r1=121873&r2=121874&view=diff
==============================================================================
--- llvm/trunk/docs/AliasAnalysis.html (original)
+++ llvm/trunk/docs/AliasAnalysis.html Wed Dec 15 12:45:20 2010
@@ -31,7 +31,7 @@
     <li><a href="#chaining"><tt>AliasAnalysis</tt> chaining behavior</a></li>
     <li><a href="#updating">Updating analysis results for transformations</a></li>
     <li><a href="#implefficiency">Efficiency Issues</a></li>
-    <li><a href="#passmanager">Pass Manager Issues</a></li>
+    <li><a href="#limitations">Limtations</a></li>
     </ul>
   </li>
 
@@ -523,13 +523,13 @@
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">
-  <a name="passmanager">Pass Manager Issues</a>
+  <a name="limitations">Limitations</a>
 </div>
 
 <div class="doc_text">
 
-<p>PassManager support for alternative AliasAnalysis implementation
-has some issues.</p>
+<p>The AliasAnalysis infrastructure has several limitations which make
+writing a new <tt>AliasAnalysis</tt> implementation difficult.</p>
 
 <p>There is no way to override the default alias analysis. It would
 be very useful to be able to do something like "opt -my-aa -O2" and
@@ -558,6 +558,40 @@
 passes between each pass, which prevents the use of <tt>FunctionPass</tt>
 alias analysis passes.</p>
 
+<p>The <tt>AliasAnalysis</tt> API does have functions for notifying
+implementations when values are deleted or copied, however these
+aren't sufficient. There are many other ways that LLVM IR can be
+modified which could be relevant to <tt>AliasAnalysis</tt>
+implementations which can not be expressed.</p>
+
+<p>The <tt>AliasAnalysisDebugger</tt> utility seems to suggest that
+<tt>AliasAnalysis</tt> implementations can expect that they will be
+informed of any relevant <tt>Value</tt> before it appears in an
+alias query. However, popular clients such as <tt>GVN</tt> don't
+support this, and are known to trigger errors when run with the
+<tt>AliasAnalysisDebugger</tt>.</p>
+
+<p>Due to several of the above limitations, the most obvious use for
+the <tt>AliasAnalysisCounter</tt> utility, collecting stats on all
+alias queries in a compilation, doesn't work, even if the
+<tt>AliasAnalysis</tt> implementations don't use <tt>FunctionPass</tt>.
+There's no way to set a default, much less a default sequence,
+and there's no way to preserve it.</p>
+
+<p>The <tt>AliasSetTracker</tt> class (which is used by <tt>LICM</tt>
+makes a non-deterministic number of alias queries. This can cause stats
+collected by <tt>AliasAnalysisCounter</tt> to have fluctuations among
+identical runs, for example. Another consequence is that debugging
+techniques involving pausing execution after a predetermined number
+of queries can be unreliable.</p>
+
+<p>Many alias queries can be reformulated in terms of other alias
+queries. When multiple <tt>AliasAnalysis</tt> queries are chained together,
+it would make sense to start those queries from the beginning of the chain,
+with care taken to avoid infinite looping, however currently an
+implementation which wants to do this can only start such queries
+from itself.</p>
+
 </div>
 
 <!-- *********************************************************************** -->



From resistor at mac.com  Wed Dec 15 12:48:27 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 15 Dec 2010 18:48:27 -0000
Subject: [llvm-commits] [llvm] r121875 - in /llvm/trunk:
 include/llvm/MC/MCCodeEmitter.h lib/MC/MCAssembler.cpp
 lib/Target/ARM/ARMMCCodeEmitter.cpp
Message-ID: <20101215184827.CEE162A6C12C@llvm.org>

Author: resistor
Date: Wed Dec 15 12:48:27 2010
New Revision: 121875

URL: http://llvm.org/viewvc/llvm-project?rev=121875&view=rev
Log:
Implement cleanups suggested by Daniel.

Modified:
    llvm/trunk/include/llvm/MC/MCCodeEmitter.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeEmitter.h?rev=121875&r1=121874&r2=121875&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/MC/MCCodeEmitter.h Wed Dec 15 12:48:27 2010
@@ -27,8 +27,8 @@
     /// evaluate fixup values in a target independent manner when possible.
     FKF_IsPCRel = (1 << 0),
     
-    // Should this fixup kind force a 4-byte aligned effective PC value?
-    FKF_IsAligned = (1 << 1)
+    /// Should this fixup kind force a 4-byte aligned effective PC value?
+    FKF_IsAlignedDownTo32Bits = (1 << 1)
   };
 
   /// A target specific name for the fixup kind. The names will be unique for

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121875&r1=121874&r2=121875&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Dec 15 12:48:27 2010
@@ -248,14 +248,18 @@
   if (IsResolved)
     IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
 
+  bool ShouldAlignPC = Emitter.getFixupKindInfo(Fixup.getKind()).Flags &
+                         MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
+  assert((ShouldAlignPC ? IsPCRel : true) &&
+    "FKF_IsAlignedDownTo32Bits is only allowed on PC-relative fixups!");
+
   if (IsPCRel) {
-    bool ShouldAlignPC = Emitter.getFixupKindInfo(
-                        Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned;
-    // PC should be aligned to a 4-byte value.
-    if (ShouldAlignPC)
-      Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3);
-    else
-      Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
+    uint32_t Offset = Fixup.getOffset();
+    
+    // A number of ARM fixups in Thumb mode require that the effective PC
+    // address be determined as the 32-bit aligned version of the actual offset.
+    if (ShouldAlignPC) Offset &= 0x3;
+    Value -= Layout.getFragmentOffset(DF) + Offset;
   }
 
   // ARM fixups based from a thumb function address need to have the low

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121875&r1=121874&r2=121875&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 15 12:48:27 2010
@@ -51,15 +51,15 @@
 // Name                      Offset (bits) Size (bits)     Flags
 { "fixup_arm_ldst_pcrel_12", 1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_ldst_pcrel_12",  0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                                MCFixupKindInfo::FKF_IsAligned},
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_arm_pcrel_10",      1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                                MCFixupKindInfo::FKF_IsAligned},
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel |
-                                                MCFixupKindInfo::FKF_IsAligned},
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                                MCFixupKindInfo::FKF_IsAligned},
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_arm_branch",        0,            24,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },



From grosbach at apple.com  Wed Dec 15 12:48:45 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 15 Dec 2010 18:48:45 -0000
Subject: [llvm-commits] [llvm] r121876 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrThumb2.td
Message-ID: <20101215184845.D6EC92A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec 15 12:48:45 2010
New Revision: 121876

URL: http://llvm.org/viewvc/llvm-project?rev=121876&view=rev
Log:
The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=121876&r1=121875&r2=121876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Dec 15 12:48:45 2010
@@ -266,6 +266,13 @@
   list<Predicate> Predicates = [IsThumb];
 }
 
+// PseudoInst that's Thumb2-mode only.
+class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
+                    list<dag> pattern>
+  : PseudoInst<oops, iops, itin, pattern> {
+  let SZ = sz;
+  list<Predicate> Predicates = [IsThumb2];
+}
 // Almost all ARM instructions are predicable.
 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
         IndexMode im, Format f, InstrItinClass itin,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121876&r1=121875&r2=121876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec 15 12:48:45 2010
@@ -1156,11 +1156,12 @@
 }
 
 let neverHasSideEffects = 1, isReMaterializable = 1 in
-def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
-                            IIC_iALUi, []>;
-def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
-                        (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
-                        []>;
+def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
+                                Size4Bytes, IIC_iALUi, []>;
+def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
+                                (ins i32imm:$label, nohash_imm:$id, pred:$p),
+                                Size4Bytes, IIC_iALUi,
+                                []>;
 
 
 // FIXME: None of these add/sub SP special instructions should be necessary



From nicholas at mxc.ca  Wed Dec 15 12:57:18 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 15 Dec 2010 18:57:18 -0000
Subject: [llvm-commits] [llvm] r121877 -
	/llvm/trunk/lib/Analysis/LazyValueInfo.cpp
Message-ID: <20101215185718.B4EE32A6C12C@llvm.org>

Author: nicholas
Date: Wed Dec 15 12:57:18 2010
New Revision: 121877

URL: http://llvm.org/viewvc/llvm-project?rev=121877&view=rev
Log:
Clean up some of LVI:
 * mergeIn now uses constant folding for constants that are provably not-equal.
 * sink some sanity checks from the get*() methods into the mark*() methods, to ensure that we never have a constant/notconstant ConstantInt
 * some textual cleanups, whitespace changes, removing "else" after return, that sort of thing.

Modified:
    llvm/trunk/lib/Analysis/LazyValueInfo.cpp

Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=121877&r1=121876&r2=121877&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Wed Dec 15 12:57:18 2010
@@ -52,18 +52,18 @@
 namespace {
 class LVILatticeVal {
   enum LatticeValueTy {
-    /// undefined - This LLVM Value has no known value yet.
+    /// undefined - This Value has no known value yet.
     undefined,
     
-    /// constant - This LLVM Value has a specific constant value.
+    /// constant - This Value has a specific constant value.
     constant,
-    /// notconstant - This LLVM value is known to not have the specified value.
+    /// notconstant - This Value is known to not have the specified value.
     notconstant,
     
-    /// constantrange
+    /// constantrange - The Value falls within this range.
     constantrange,
     
-    /// overdefined - This instruction is not known to be constant, and we know
+    /// overdefined - This value is not known to be constant, and we know that
     /// it has a value.
     overdefined
   };
@@ -79,17 +79,13 @@
 
   static LVILatticeVal get(Constant *C) {
     LVILatticeVal Res;
-    if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
-      Res.markConstantRange(ConstantRange(CI->getValue(), CI->getValue()+1));
-    else if (!isa<UndefValue>(C))
+    if (!isa<UndefValue>(C))
       Res.markConstant(C);
     return Res;
   }
   static LVILatticeVal getNot(Constant *C) {
     LVILatticeVal Res;
-    if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
-      Res.markConstantRange(ConstantRange(CI->getValue()+1, CI->getValue()));
-    else
+    if (!isa<UndefValue>(C))
       Res.markNotConstant(C);
     return Res;
   }
@@ -131,32 +127,34 @@
 
   /// markConstant - Return true if this is a change in status.
   bool markConstant(Constant *V) {
-    if (isConstant()) {
-      assert(getConstant() == V && "Marking constant with different value");
+    assert(V && "Marking constant with NULL");
+    if (ConstantInt *CI = dyn_cast<ConstantInt>(V))
+      return markConstantRange(ConstantRange(CI->getValue()));
+    if (isa<UndefValue>(V))
       return false;
-    }
-    
+
+    assert((!isConstant() || getConstant() == V) &&
+           "Marking constant with different value");
     assert(isUndefined());
     Tag = constant;
-    assert(V && "Marking constant with NULL");
     Val = V;
     return true;
   }
   
   /// markNotConstant - Return true if this is a change in status.
   bool markNotConstant(Constant *V) {
-    if (isNotConstant()) {
-      assert(getNotConstant() == V && "Marking !constant with different value");
+    assert(V && "Marking constant with NULL");
+    if (ConstantInt *CI = dyn_cast<ConstantInt>(V))
+      return markConstantRange(ConstantRange(CI->getValue()+1, CI->getValue()));
+    if (isa<UndefValue>(V))
       return false;
-    }
-    
-    if (isConstant())
-      assert(getConstant() != V && "Marking not constant with different value");
-    else
-      assert(isUndefined());
 
+    assert((!isConstant() || getConstant() != V) &&
+           "Marking constant !constant with same value");
+    assert((!isNotConstant() || getNotConstant() == V) &&
+           "Marking !constant with different value");
+    assert(isUndefined() || isConstant());
     Tag = notconstant;
-    assert(V && "Marking constant with NULL");
     Val = V;
     return true;
   }
@@ -187,67 +185,81 @@
     if (RHS.isUndefined() || isOverdefined()) return false;
     if (RHS.isOverdefined()) return markOverdefined();
 
-    if (RHS.isNotConstant()) {
-      if (isNotConstant()) {
-        if (getNotConstant() != RHS.getNotConstant() ||
-            isa<ConstantExpr>(getNotConstant()) ||
-            isa<ConstantExpr>(RHS.getNotConstant()))
-          return markOverdefined();
-        return false;
-      } else if (isConstant()) {
-        if (getConstant() == RHS.getNotConstant() ||
-            isa<ConstantExpr>(RHS.getNotConstant()) ||
-            isa<ConstantExpr>(getConstant()))
-          return markOverdefined();
-        return markNotConstant(RHS.getNotConstant());
-      } else if (isConstantRange()) {
-         // FIXME: This could be made more precise.
+    if (isUndefined()) {
+      Tag = RHS.Tag;
+      Val = RHS.Val;
+      Range = RHS.Range;
+      return true;
+    }
+
+    if (isConstant()) {
+      if (RHS.isConstant()) {
+        if (Val == RHS.Val)
+          return false;
         return markOverdefined();
       }
-      
-      assert(isUndefined() && "Unexpected lattice");
-      return markNotConstant(RHS.getNotConstant());
-    }
-    
-    if (RHS.isConstantRange()) {
-      if (isConstantRange()) {
-        ConstantRange NewR = Range.unionWith(RHS.getConstantRange());
-        if (NewR.isFullSet())
+
+      if (RHS.isNotConstant()) {
+        if (Val == RHS.Val)
           return markOverdefined();
-        else
-          return markConstantRange(NewR);
-      } else if (!isUndefined()) {
+
+        // Unless we can prove that the two Constants are different, we must
+        // move to overdefined.
+        // FIXME: use TargetData for smarter constant folding.
+        if (ConstantInt *Res = dyn_cast<ConstantInt>(
+                ConstantFoldCompareInstOperands(CmpInst::ICMP_NE,
+                                                getConstant(),
+                                                RHS.getNotConstant())))
+          if (Res->isOne())
+            return markNotConstant(RHS.getNotConstant());
+
         return markOverdefined();
       }
-      
-      assert(isUndefined() && "Unexpected lattice");
-      return markConstantRange(RHS.getConstantRange());
-    }
-    
-    // RHS must be a constant, we must be constantrange, 
-    // undef, constant, or notconstant.
-    if (isConstantRange()) {
-      // FIXME: This could be made more precise.
+
+      // RHS is a ConstantRange, LHS is a non-integer Constant.
+
+      // FIXME: consider the case where RHS is a range [1, 0) and LHS is
+      // a function. The correct result is to pick up RHS.
+
       return markOverdefined();
     }
-    
-    if (isUndefined())
-      return markConstant(RHS.getConstant());
-    
-    if (isConstant()) {
-      if (getConstant() != RHS.getConstant())
+
+    if (isNotConstant()) {
+      if (RHS.isConstant()) {
+        if (Val == RHS.Val)
+          return markOverdefined();
+
+        // Unless we can prove that the two Constants are different, we must
+        // move to overdefined.
+        // FIXME: use TargetData for smarter constant folding.
+        if (ConstantInt *Res = dyn_cast<ConstantInt>(
+                ConstantFoldCompareInstOperands(CmpInst::ICMP_NE,
+                                                getNotConstant(),
+                                                RHS.getConstant())))
+          if (Res->isOne())
+            return false;
+
         return markOverdefined();
-      return false;
+      }
+
+      if (RHS.isNotConstant()) {
+        if (Val == RHS.Val)
+          return false;
+        return markOverdefined();
+      }
+
+      return markOverdefined();
     }
 
-    // If we are known "!=4" and RHS is "==5", stay at "!=4".
-    if (getNotConstant() == RHS.getConstant() ||
-        isa<ConstantExpr>(getNotConstant()) ||
-        isa<ConstantExpr>(RHS.getConstant()))
+    assert(isConstantRange() && "New LVILattice type?");
+    if (!RHS.isConstantRange())
       return markOverdefined();
-    return false;
+
+    ConstantRange NewR = Range.unionWith(RHS.getConstantRange());
+    if (NewR.isFullSet())
+      return markOverdefined();
+    return markConstantRange(NewR);
   }
-  
 };
   
 } // end anonymous namespace.
@@ -292,7 +304,7 @@
         : CallbackVH(V), Parent(P) { }
       
       void deleted();
-      void allUsesReplacedWith(Value* V) {
+      void allUsesReplacedWith(Value *V) {
         deleted();
       }
     };
@@ -310,7 +322,7 @@
     LVILatticeVal getBlockValue(Value *Val, BasicBlock *BB);
     LVILatticeVal getEdgeValue(Value *V, BasicBlock *F, BasicBlock *T);
     
-    ValueCacheEntryTy  &lookup(Value *V) {
+    ValueCacheEntryTy &lookup(Value *V) {
       return ValueCache[LVIValueHandle(V, this)];
     }
     
@@ -321,7 +333,6 @@
     }
     
   public:
-    
     /// getValueInBlock - This is the query interface to determine the lattice
     /// value for the specified Value* at the end of the specified block.
     LVILatticeVal getValueInBlock(Value *V, BasicBlock *BB);
@@ -456,7 +467,7 @@
     // Loop over all of our predecessors, merging what we know from them into
     // result.
     for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
-      Value* PhiVal = PN->getIncomingValueForBlock(*PI);
+      Value *PhiVal = PN->getIncomingValueForBlock(*PI);
       Result.mergeIn(getValueOnEdge(PhiVal, *PI, BB));
       
       // If we hit overdefined, exit early.  The BlockVals entry is already set
@@ -574,8 +585,8 @@
 
 /// getEdgeValue - This method attempts to infer more complex 
 LVILatticeVal LazyValueInfoCache::getEdgeValue(Value *Val,
-                                    BasicBlock *BBFrom,
-                                     BasicBlock *BBTo) {
+                                               BasicBlock *BBFrom,
+                                               BasicBlock *BBTo) {
   // TODO: Handle more complex conditionals.  If (v == 0 || v2 < 1) is false, we
   // know that v != 0.
   if (BranchInst *BI = dyn_cast<BranchInst>(BBFrom->getTerminator())) {
@@ -725,7 +736,7 @@
     if (ToUpdate == NewSucc) continue;
     
     bool changed = false;
-    for (DenseSet<Value*>::iterator I = ClearSet.begin(),E = ClearSet.end();
+    for (DenseSet<Value*>::iterator I = ClearSet.begin(), E = ClearSet.end();
          I != E; ++I) {
       // If a value was marked overdefined in OldSucc, and is here too...
       std::set<std::pair<AssertingVH<BasicBlock>, Value*> >::iterator OI =
@@ -784,7 +795,7 @@
   
   if (Result.isConstant())
     return Result.getConstant();
-  else if (Result.isConstantRange()) {
+  if (Result.isConstantRange()) {
     ConstantRange CR = Result.getConstantRange();
     if (const APInt *SingleVal = CR.getSingleElement())
       return ConstantInt::get(V->getContext(), *SingleVal);
@@ -800,7 +811,7 @@
   
   if (Result.isConstant())
     return Result.getConstant();
-  else if (Result.isConstantRange()) {
+  if (Result.isConstantRange()) {
     ConstantRange CR = Result.getConstantRange();
     if (const APInt *SingleVal = CR.getSingleElement())
       return ConstantInt::get(V->getContext(), *SingleVal);
@@ -820,7 +831,7 @@
   Constant *Res = 0;
   if (Result.isConstant()) {
     Res = ConstantFoldCompareInstOperands(Pred, Result.getConstant(), C, TD);
-    if (ConstantInt *ResCI = dyn_cast_or_null<ConstantInt>(Res))
+    if (ConstantInt *ResCI = dyn_cast<ConstantInt>(Res))
       return ResCI->isZero() ? False : True;
     return Unknown;
   }
@@ -845,13 +856,12 @@
     }
     
     // Handle more complex predicates.
-    ConstantRange RHS(CI->getValue(), CI->getValue()+1);
-    ConstantRange TrueValues = ConstantRange::makeICmpRegion(Pred, RHS);
-    if (CR.intersectWith(TrueValues).isEmptySet())
-      return False;
-    else if (TrueValues.contains(CR))
+    ConstantRange TrueValues =
+        ICmpInst::makeConstantRange((ICmpInst::Predicate)Pred, CI->getValue());
+    if (TrueValues.contains(CR))
       return True;
-    
+    if (TrueValues.inverse().contains(CR))
+      return False;
     return Unknown;
   }
   
@@ -878,7 +888,7 @@
 }
 
 void LazyValueInfo::threadEdge(BasicBlock *PredBB, BasicBlock *OldSucc,
-                               BasicBlock* NewSucc) {
+                               BasicBlock *NewSucc) {
   if (PImpl) getCache(PImpl).threadEdge(PredBB, OldSucc, NewSucc);
 }
 



From grosbach at apple.com  Wed Dec 15 13:03:16 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 15 Dec 2010 19:03:16 -0000
Subject: [llvm-commits] [llvm] r121878 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20101215190316.6A1942A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec 15 13:03:16 2010
New Revision: 121878

URL: http://llvm.org/viewvc/llvm-project?rev=121878&view=rev
Log:
Tweak a few pseudo-inst pattern base classes.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121878&r1=121877&r2=121878&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec 15 13:03:16 2010
@@ -908,7 +908,7 @@
     let Inst{5-4}   = addr{1-0}; // imm
   }
 
-  def pci : tPseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
+  def pci : t2PseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
                       [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>;
 }
 
@@ -2985,17 +2985,17 @@
 }
 
 let isNotDuplicable = 1, isIndirectBranch = 1 in {
-def t2BR_JT : tPseudoInst<(outs),
+def t2BR_JT : t2PseudoInst<(outs),
           (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
            SizeSpecial, IIC_Br,
           [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
 
 // FIXME: Add a non-pc based case that can be predicated.
-def t2TBB_JT : tPseudoInst<(outs),
+def t2TBB_JT : t2PseudoInst<(outs),
         (ins GPR:$index, i32imm:$jt, i32imm:$id),
          SizeSpecial, IIC_Br, []>;
 
-def t2TBH_JT : tPseudoInst<(outs),
+def t2TBH_JT : t2PseudoInst<(outs),
         (ins GPR:$index, i32imm:$jt, i32imm:$id),
          SizeSpecial, IIC_Br, []>;
 



From resistor at mac.com  Wed Dec 15 13:24:24 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 15 Dec 2010 19:24:24 -0000
Subject: [llvm-commits] [llvm] r121880 - /llvm/trunk/lib/MC/MCAssembler.cpp
Message-ID: <20101215192424.EE89F2A6C12C@llvm.org>

Author: resistor
Date: Wed Dec 15 13:24:24 2010
New Revision: 121880

URL: http://llvm.org/viewvc/llvm-project?rev=121880&view=rev
Log:
Fix typo in r121875.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121880&r1=121879&r2=121880&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Dec 15 13:24:24 2010
@@ -258,7 +258,7 @@
     
     // A number of ARM fixups in Thumb mode require that the effective PC
     // address be determined as the 32-bit aligned version of the actual offset.
-    if (ShouldAlignPC) Offset &= 0x3;
+    if (ShouldAlignPC) Offset &= ~0x3;
     Value -= Layout.getFragmentOffset(DF) + Offset;
   }
 



From dalej at apple.com  Wed Dec 15 13:35:35 2010
From: dalej at apple.com (Dale Johannesen)
Date: Wed, 15 Dec 2010 19:35:35 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r121881 -
	/llvm-gcc-4.2/trunk/gcc/crtstuff.c
Message-ID: <20101215193535.AA5562A6C12C@llvm.org>

Author: johannes
Date: Wed Dec 15 13:35:35 2010
New Revision: 121881

URL: http://llvm.org/viewvc/llvm-project?rev=121881&view=rev
Log:
Add some __used__ attributes.  Patch by Woongsik Choi!
(This file is not used on Darwin so I can't really verify it
works; it looks OK, and I'm sure ELF users will report problems.)


Modified:
    llvm-gcc-4.2/trunk/gcc/crtstuff.c

Modified: llvm-gcc-4.2/trunk/gcc/crtstuff.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/crtstuff.c?rev=121881&r1=121880&r2=121881&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/crtstuff.c (original)
+++ llvm-gcc-4.2/trunk/gcc/crtstuff.c Wed Dec 15 13:35:35 2010
@@ -175,7 +175,15 @@
 #elif defined(CTORS_SECTION_ASM_OP)
 /* Hack: force cc1 to switch to .data section early, so that assembling
    __CTOR_LIST__ does not undo our behind-the-back change to .ctors.  */
-static func_ptr force_to_data[1] __attribute__ ((__unused__)) = { };
+static func_ptr force_to_data[1] 
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+__attribute__ ((__used__)) 
+#else
+__attribute__ ((__unused__)) 
+#endif
+/* LLVM LOCAL end */  
+= { };
 asm (CTORS_SECTION_ASM_OP);
 STATIC func_ptr __CTOR_LIST__[1]
 /* LLVM LOCAL begin */
@@ -241,7 +249,13 @@
 /* Stick a label at the beginning of the java class registration info
    so we can register them properly.  */
 STATIC void *__JCR_LIST__[]
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+  __attribute__ ((used, section(JCR_SECTION_NAME), aligned(sizeof(void*))))
+#else
   __attribute__ ((unused, section(JCR_SECTION_NAME), aligned(sizeof(void*))))
+#endif
+/* LLVM LOCAL end */
   = { };
 #endif /* JCR_SECTION_NAME */
 
@@ -338,7 +352,13 @@
 CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
 #else /* !defined(FINI_SECTION_ASM_OP) */
 static func_ptr __do_global_dtors_aux_fini_array_entry[]
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+  __attribute__ ((__used__, section(".fini_array")))
+#else
   __attribute__ ((__unused__, section(".fini_array")))
+#endif
+/* LLVM LOCAL end */
   = { __do_global_dtors_aux };
 #endif /* !defined(FINI_SECTION_ASM_OP) */
 
@@ -378,7 +398,13 @@
 CRT_CALL_STATIC_FUNCTION (INIT_SECTION_ASM_OP, frame_dummy)
 #else /* defined(INIT_SECTION_ASM_OP) */
 static func_ptr __frame_dummy_init_array_entry[]
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+  __attribute__ ((__used__, section(".init_array")))
+#else
   __attribute__ ((__unused__, section(".init_array")))
+#endif  
+/* LLVM LOCAL end */
   = { frame_dummy };
 #endif /* !defined(INIT_SECTION_ASM_OP) */
 #endif /* USE_EH_FRAME_REGISTRY || JCR_SECTION_NAME */
@@ -486,7 +512,16 @@
 #elif defined(CTORS_SECTION_ASM_OP)
 /* Hack: force cc1 to switch to .data section early, so that assembling
    __CTOR_LIST__ does not undo our behind-the-back change to .ctors.  */
-static func_ptr force_to_data[1] __attribute__ ((__unused__)) = { };
+static func_ptr force_to_data[1] 
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+__attribute__ ((__used__)) 
+#else
+__attribute__ ((__unused__)) 
+#endif  
+/* LLVM LOCAL end */
+= { };
+
 asm (CTORS_SECTION_ASM_OP);
 STATIC func_ptr __CTOR_END__[1]
 /* LLVM LOCAL begin */
@@ -548,16 +583,30 @@
 #  error "Missing a 4 byte integer"
 # endif
 STATIC EH_FRAME_SECTION_CONST int32 __FRAME_END__[]
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+     __attribute__ ((used, section(EH_FRAME_SECTION_NAME),
+		     aligned(sizeof(int32))))
+#else
      __attribute__ ((unused, section(EH_FRAME_SECTION_NAME),
 		     aligned(sizeof(int32))))
+#endif  
+/* LLVM LOCAL end */
      = { 0 };
 #endif /* EH_FRAME_SECTION_NAME */
 
 #ifdef JCR_SECTION_NAME
 /* Null terminate the .jcr section array.  */
 STATIC void *__JCR_END__[1] 
+/* LLVM LOCAL begin */
+#ifdef __llvm__
+   __attribute__ ((used, section(JCR_SECTION_NAME),
+		   aligned(sizeof(void *))))
+#else
    __attribute__ ((unused, section(JCR_SECTION_NAME),
 		   aligned(sizeof(void *))))
+#endif
+/* LLVM LOCAL end */  
    = { 0 };
 #endif /* JCR_SECTION_NAME */
 



From peckw at wesleypeck.com  Wed Dec 15 13:35:36 2010
From: peckw at wesleypeck.com (Wesley Peck)
Date: Wed, 15 Dec 2010 19:35:36 -0000
Subject: [llvm-commits] [llvm] r121882 -
	/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td
Message-ID: <20101215193536.C5B0A2A6C12D@llvm.org>

Author: peckw
Date: Wed Dec 15 13:35:36 2010
New Revision: 121882

URL: http://llvm.org/viewvc/llvm-project?rev=121882&view=rev
Log:
Add some special purpose register definitions to the MBlaze backend and cleanup some old, unused floating point register definitions.

Modified:
    llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td?rev=121882&r1=121881&r2=121882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.td Wed Dec 15 13:35:36 2010
@@ -17,25 +17,27 @@
   let Namespace = "MBlaze";
 }
 
-// MBlaze CPU Registers
+// Special purpose registers have 15-bit values
+class MBlazeSReg<string n> : Register<n> {
+  field bits<15> Num;
+  let Namespace = "MBlaze";
+}
+
+// MBlaze general purpose registers
 class MBlazeGPRReg<bits<5> num, string n> : MBlazeReg<n> {
   let Num = num;
 }
 
-// MBlaze 32-bit (aliased) FPU Registers
-/*
-class FPR<bits<5> num, string n, list<Register> aliases> : MBlazeReg<n> {
+// MBlaze special purpose registers
+class MBlazeSPRReg<bits<15> num, string n> : MBlazeSReg<n> {
   let Num = num;
-  let Aliases = aliases;
 }
-*/
 
 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
 let Namespace = "MBlaze" in {
-
   // General Purpose Registers
   def R0  : MBlazeGPRReg< 0,  "r0">,   DwarfRegNum<[0]>;
   def R1  : MBlazeGPRReg< 1,  "r1">,   DwarfRegNum<[1]>;
@@ -70,41 +72,31 @@
   def R30 : MBlazeGPRReg< 30, "r30">,  DwarfRegNum<[30]>;
   def R31 : MBlazeGPRReg< 31, "r31">,  DwarfRegNum<[31]>;
 
-  /// MBlaze Single point precision FPU Registers
-  /*
-  def F0  : FPR< 0,  "f0", [R0]>,  DwarfRegNum<[32]>;
-  def F1  : FPR< 1,  "f1", [R1]>,  DwarfRegNum<[33]>;
-  def F2  : FPR< 2,  "f2", [R2]>,  DwarfRegNum<[34]>;
-  def F3  : FPR< 3,  "f3", [R3]>,  DwarfRegNum<[35]>;
-  def F4  : FPR< 4,  "f4", [R4]>,  DwarfRegNum<[36]>;
-  def F5  : FPR< 5,  "f5", [R5]>,  DwarfRegNum<[37]>;
-  def F6  : FPR< 6,  "f6", [R6]>,  DwarfRegNum<[38]>;
-  def F7  : FPR< 7,  "f7", [R7]>,  DwarfRegNum<[39]>;
-  def F8  : FPR< 8,  "f8", [R8]>,  DwarfRegNum<[40]>;
-  def F9  : FPR< 9,  "f9", [R9]>,  DwarfRegNum<[41]>;
-  def F10 : FPR<10, "f10", [R10]>, DwarfRegNum<[42]>;
-  def F11 : FPR<11, "f11", [R11]>, DwarfRegNum<[43]>;
-  def F12 : FPR<12, "f12", [R12]>, DwarfRegNum<[44]>;
-  def F13 : FPR<13, "f13", [R13]>, DwarfRegNum<[45]>;
-  def F14 : FPR<14, "f14", [R14]>, DwarfRegNum<[46]>;
-  def F15 : FPR<15, "f15", [R15]>, DwarfRegNum<[47]>;
-  def F16 : FPR<16, "f16", [R16]>, DwarfRegNum<[48]>;
-  def F17 : FPR<17, "f17", [R17]>, DwarfRegNum<[49]>;
-  def F18 : FPR<18, "f18", [R18]>, DwarfRegNum<[50]>;
-  def F19 : FPR<19, "f19", [R19]>, DwarfRegNum<[51]>;
-  def F20 : FPR<20, "f20", [R20]>, DwarfRegNum<[52]>;
-  def F21 : FPR<21, "f21", [R21]>, DwarfRegNum<[53]>;
-  def F22 : FPR<22, "f22", [R22]>, DwarfRegNum<[54]>;
-  def F23 : FPR<23, "f23", [R23]>, DwarfRegNum<[55]>;
-  def F24 : FPR<24, "f24", [R24]>, DwarfRegNum<[56]>;
-  def F25 : FPR<25, "f25", [R25]>, DwarfRegNum<[57]>;
-  def F26 : FPR<26, "f26", [R26]>, DwarfRegNum<[58]>;
-  def F27 : FPR<27, "f27", [R27]>, DwarfRegNum<[59]>;
-  def F28 : FPR<28, "f28", [R28]>, DwarfRegNum<[60]>;
-  def F29 : FPR<29, "f29", [R29]>, DwarfRegNum<[61]>;
-  def F30 : FPR<30, "f30", [R30]>, DwarfRegNum<[62]>;
-  def F31 : FPR<31, "f31", [R31]>, DwarfRegNum<[63]>;
-  */
+  // Special Purpose Registers
+  def RPC    : MBlazeSPRReg<0x0000, "rpc">,    DwarfRegNum<[32]>;
+  def RMSR   : MBlazeSPRReg<0x0001, "rmsr">,   DwarfRegNum<[33]>;
+  def REAR   : MBlazeSPRReg<0x0003, "rear">,   DwarfRegNum<[34]>;
+  def RESR   : MBlazeSPRReg<0x0005, "resr">,   DwarfRegNum<[35]>;
+  def RFSR   : MBlazeSPRReg<0x0007, "rfsr">,   DwarfRegNum<[36]>;
+  def RBTR   : MBlazeSPRReg<0x000B, "rbtr">,   DwarfRegNum<[37]>;
+  def REDR   : MBlazeSPRReg<0x000D, "redr">,   DwarfRegNum<[38]>;
+  def RPID   : MBlazeSPRReg<0x1000, "rpid">,   DwarfRegNum<[39]>;
+  def RZPR   : MBlazeSPRReg<0x1001, "rzpr">,   DwarfRegNum<[40]>;
+  def RTLBX  : MBlazeSPRReg<0x0002, "rtlbx">,  DwarfRegNum<[41]>;
+  def RTLBLO : MBlazeSPRReg<0x1003, "rtlblo">, DwarfRegNum<[42]>;
+  def RTLBHI : MBlazeSPRReg<0x1004, "rtlbhi">, DwarfRegNum<[43]>;
+  def RPVR0  : MBlazeSPRReg<0x2000, "rpvr0">,  DwarfRegNum<[44]>;
+  def RPVR1  : MBlazeSPRReg<0x2001, "rpvr1">,  DwarfRegNum<[45]>;
+  def RPVR2  : MBlazeSPRReg<0x2002, "rpvr2">,  DwarfRegNum<[46]>;
+  def RPVR3  : MBlazeSPRReg<0x2003, "rpvr3">,  DwarfRegNum<[47]>;
+  def RPVR4  : MBlazeSPRReg<0x2004, "rpvr4">,  DwarfRegNum<[48]>;
+  def RPVR5  : MBlazeSPRReg<0x2005, "rpvr5">,  DwarfRegNum<[49]>;
+  def RPVR6  : MBlazeSPRReg<0x2006, "rpvr6">,  DwarfRegNum<[50]>;
+  def RPVR7  : MBlazeSPRReg<0x2007, "rpvr7">,  DwarfRegNum<[51]>;
+  def RPVR8  : MBlazeSPRReg<0x2008, "rpvr8">,  DwarfRegNum<[52]>;
+  def RPVR9  : MBlazeSPRReg<0x2009, "rpvr9">,  DwarfRegNum<[53]>;
+  def RPVR10 : MBlazeSPRReg<0x200A, "rpvr10">, DwarfRegNum<[54]>;
+  def RPVR11 : MBlazeSPRReg<0x200B, "rpvr11">, DwarfRegNum<[55]>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -146,41 +138,3 @@
     }
   }];
 }
-
-/*
-def FGR32 : RegisterClass<"MBlaze", [f32], 32,
-  [
-  // Return Values and Arguments
-  F3, F4, F5, F6, F7, F8, F9, F10,
-
-  // Not preserved across procedure calls
-  F11, F12,
-
-  // Callee save
-  F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,
-
-  // Reserved
-  F0,  // Always zero
-  F1,  // The stack pointer
-  F2,  // Read-only small data area anchor
-  F13, // Read-write small data area anchor
-  F14, // Return address for interrupts
-  F15, // Return address for sub-routines
-  F16, // Return address for trap
-  F17, // Return address for exceptions
-  F18, // Reserved for assembler
-  F19  // The frame pointer
-  ]>
-{
-  let MethodProtos = [{
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    FGR32Class::iterator
-    FGR32Class::allocation_order_end(const MachineFunction &MF) const {
-      // The last 10 registers on the list above are reserved
-      return end()-10;
-    }
-  }];
-}
-*/



From gohman at apple.com  Wed Dec 15 14:02:24 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 20:02:24 -0000
Subject: [llvm-commits] [llvm] r121885 - in /llvm/trunk: include/llvm/
 include/llvm/Analysis/ lib/Analysis/ lib/Analysis/IPA/ lib/CodeGen/
 lib/Transforms/Scalar/ lib/VMCore/
Message-ID: <20101215200224.9A0BD2A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 14:02:24 2010
New Revision: 121885

URL: http://llvm.org/viewvc/llvm-project?rev=121885&view=rev
Log:
Move Value::getUnderlyingObject to be a standalone
function so that it can live in Analysis instead of
VMCore.

Modified:
    llvm/trunk/include/llvm/Analysis/ValueTracking.h
    llvm/trunk/include/llvm/Value.h
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/lib/Analysis/ConstantFolding.cpp
    llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
    llvm/trunk/lib/Analysis/LazyValueInfo.cpp
    llvm/trunk/lib/Analysis/Lint.cpp
    llvm/trunk/lib/Analysis/Loads.cpp
    llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
    llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
    llvm/trunk/lib/VMCore/Value.cpp

Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ValueTracking.h?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/ValueTracking.h (original)
+++ llvm/trunk/include/llvm/Analysis/ValueTracking.h Wed Dec 15 14:02:24 2010
@@ -121,6 +121,18 @@
   /// GetStringLength - If we can compute the length of the string pointed to by
   /// the specified pointer, return 'len+1'.  If we can't, return 0.
   uint64_t GetStringLength(Value *V);
+
+  /// GetUnderlyingObject - This method strips off any GEP address adjustments
+  /// and pointer casts from the specified value, returning the original object
+  /// being addressed.  Note that the returned value has pointer type if the
+  /// specified value does.  If the MaxLookup value is non-zero, it limits the
+  /// number of instructions to be stripped off.
+  Value *GetUnderlyingObject(Value *V, unsigned MaxLookup = 6);
+  static inline const Value *
+  GetUnderlyingObject(const Value *V, unsigned MaxLookup = 6) {
+    return GetUnderlyingObject(const_cast<Value *>(V), MaxLookup);
+  }
+
 } // end namespace llvm
 
 #endif

Modified: llvm/trunk/include/llvm/Value.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Value.h (original)
+++ llvm/trunk/include/llvm/Value.h Wed Dec 15 14:02:24 2010
@@ -285,16 +285,6 @@
     return const_cast<Value*>(this)->stripPointerCasts();
   }
 
-  /// getUnderlyingObject - This method strips off any GEP address adjustments
-  /// and pointer casts from the specified value, returning the original object
-  /// being addressed.  Note that the returned value has pointer type if the
-  /// specified value does.  If the MaxLookup value is non-zero, it limits the
-  /// number of instructions to be stripped off.
-  Value *getUnderlyingObject(unsigned MaxLookup = 6);
-  const Value *getUnderlyingObject(unsigned MaxLookup = 6) const {
-    return const_cast<Value*>(this)->getUnderlyingObject(MaxLookup);
-  }
-
   /// isDereferenceablePointer - Test if this value is always a pointer to
   /// allocated and suitably aligned memory for a simple load or store.
   bool isDereferenceablePointer() const;

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Wed Dec 15 14:02:24 2010
@@ -233,7 +233,7 @@
 /// the gep cannot necessarily be reconstructed from its decomposed form.
 ///
 /// When TargetData is around, this function is capable of analyzing everything
-/// that Value::getUnderlyingObject() can look through.  When not, it just looks
+/// that GetUnderlyingObject can look through.  When not, it just looks
 /// through pointer casts.
 ///
 static const Value *
@@ -528,7 +528,7 @@
   SmallVector<const Value *, 16> Worklist;
   Worklist.push_back(Loc.Ptr);
   do {
-    const Value *V = Worklist.pop_back_val()->getUnderlyingObject();
+    const Value *V = GetUnderlyingObject(Worklist.pop_back_val());
     if (!Visited.insert(V)) {
       Visited.clear();
       return AliasAnalysis::pointsToConstantMemory(Loc, OrLocal);
@@ -633,7 +633,7 @@
   assert(notDifferentParent(CS.getInstruction(), Loc.Ptr) &&
          "AliasAnalysis query involving multiple functions!");
 
-  const Value *Object = Loc.Ptr->getUnderlyingObject();
+  const Value *Object = GetUnderlyingObject(Loc.Ptr);
   
   // If this is a tail call and Loc.Ptr points to a stack location, we know that
   // the tail call cannot access or modify the local stack.
@@ -761,7 +761,7 @@
 
 /// aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP instruction
 /// against another pointer.  We know that V1 is a GEP, but we don't know
-/// anything about V2.  UnderlyingV1 is GEP1->getUnderlyingObject(),
+/// anything about V2.  UnderlyingV1 is GetUnderlyingObject(GEP1),
 /// UnderlyingV2 is the same for V2.
 ///
 AliasAnalysis::AliasResult
@@ -807,7 +807,7 @@
     // to handle without it.
     if (GEP1BasePtr != UnderlyingV1 || GEP2BasePtr != UnderlyingV2) {
       assert(TD == 0 &&
-             "DecomposeGEPExpression and getUnderlyingObject disagree!");
+             "DecomposeGEPExpression and GetUnderlyingObject disagree!");
       return MayAlias;
     }
     
@@ -843,7 +843,7 @@
     // to handle without it.
     if (GEP1BasePtr != UnderlyingV1) {
       assert(TD == 0 &&
-             "DecomposeGEPExpression and getUnderlyingObject disagree!");
+             "DecomposeGEPExpression and GetUnderlyingObject disagree!");
       return MayAlias;
     }
   }
@@ -1044,8 +1044,8 @@
     return NoAlias;  // Scalars cannot alias each other
 
   // Figure out what objects these things are pointing to if we can.
-  const Value *O1 = V1->getUnderlyingObject();
-  const Value *O2 = V2->getUnderlyingObject();
+  const Value *O1 = GetUnderlyingObject(V1);
+  const Value *O2 = GetUnderlyingObject(V2);
 
   // Null values in the default address space don't point to any object, so they
   // don't alias any other pointer.

Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Wed Dec 15 14:02:24 2010
@@ -467,7 +467,7 @@
   
   // If this load comes from anywhere in a constant global, and if the global
   // is all undef or zero, we know what it loads.
-  if (GlobalVariable *GV = dyn_cast<GlobalVariable>(CE->getUnderlyingObject())){
+  if (GlobalVariable *GV = dyn_cast<GlobalVariable>(GetUnderlyingObject(CE))){
     if (GV->isConstant() && GV->hasDefinitiveInitializer()) {
       const Type *ResTy = cast<PointerType>(C->getType())->getElementType();
       if (GV->getInitializer()->isNullValue())

Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original)
+++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Wed Dec 15 14:02:24 2010
@@ -24,6 +24,7 @@
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/CallGraph.h"
 #include "llvm/Analysis/MemoryBuiltins.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/InstIterator.h"
 #include "llvm/ADT/Statistic.h"
@@ -324,7 +325,7 @@
         continue;
 
       // Check the value being stored.
-      Value *Ptr = SI->getOperand(0)->getUnderlyingObject();
+      Value *Ptr = GetUnderlyingObject(SI->getOperand(0));
 
       if (isMalloc(Ptr)) {
         // Okay, easy case.
@@ -489,8 +490,8 @@
 GlobalsModRef::alias(const Location &LocA,
                      const Location &LocB) {
   // Get the base object these pointers point to.
-  const Value *UV1 = LocA.Ptr->getUnderlyingObject();
-  const Value *UV2 = LocB.Ptr->getUnderlyingObject();
+  const Value *UV1 = GetUnderlyingObject(LocA.Ptr);
+  const Value *UV2 = GetUnderlyingObject(LocB.Ptr);
 
   // If either of the underlying values is a global, they may be non-addr-taken
   // globals, which we can answer queries about.
@@ -549,7 +550,7 @@
   // If we are asking for mod/ref info of a direct call with a pointer to a
   // global we are tracking, return information if we have it.
   if (const GlobalValue *GV =
-        dyn_cast<GlobalValue>(Loc.Ptr->getUnderlyingObject()))
+        dyn_cast<GlobalValue>(GetUnderlyingObject(Loc.Ptr)))
     if (GV->hasLocalLinkage())
       if (const Function *F = CS.getCalledFunction())
         if (NonAddressTakenGlobals.count(GV))

Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Wed Dec 15 14:02:24 2010
@@ -14,6 +14,7 @@
 
 #define DEBUG_TYPE "lazy-value-info"
 #include "llvm/Analysis/LazyValueInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Constants.h"
 #include "llvm/Instructions.h"
 #include "llvm/Analysis/ConstantFolding.h"
@@ -414,8 +415,8 @@
       for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();BI != BE;++BI){
         LoadInst *L = dyn_cast<LoadInst>(BI);
         if (L && L->getPointerAddressSpace() == 0 &&
-            L->getPointerOperand()->getUnderlyingObject() ==
-              Val->getUnderlyingObject()) {
+            GetUnderlyingObject(L->getPointerOperand()) ==
+              GetUnderlyingObject(Val)) {
           NotNull = true;
           break;
         }

Modified: llvm/trunk/lib/Analysis/Lint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Lint.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Lint.cpp (original)
+++ llvm/trunk/lib/Analysis/Lint.cpp Wed Dec 15 14:02:24 2010
@@ -567,7 +567,7 @@
   // TODO: Look through eliminable cast pairs.
   // TODO: Look through calls with unique return values.
   // TODO: Look through vector insert/extract/shuffle.
-  V = OffsetOk ? V->getUnderlyingObject() : V->stripPointerCasts();
+  V = OffsetOk ? GetUnderlyingObject(V) : V->stripPointerCasts();
   if (LoadInst *L = dyn_cast<LoadInst>(V)) {
     BasicBlock::iterator BBI = L;
     BasicBlock *BB = L->getParent();

Modified: llvm/trunk/lib/Analysis/Loads.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Loads.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Loads.cpp (original)
+++ llvm/trunk/lib/Analysis/Loads.cpp Wed Dec 15 14:02:24 2010
@@ -49,7 +49,7 @@
 /// getUnderlyingObjectWithOffset - Strip off up to MaxLookup GEPs and
 /// bitcasts to get back to the underlying object being addressed, keeping
 /// track of the offset in bytes from the GEPs relative to the result.
-/// This is closely related to Value::getUnderlyingObject but is located
+/// This is closely related to GetUnderlyingObject but is located
 /// here to avoid making VMCore depend on TargetData.
 static Value *getUnderlyingObjectWithOffset(Value *V, const TargetData *TD,
                                             uint64_t &ByteOffset,

Modified: llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopDependenceAnalysis.cpp Wed Dec 15 14:02:24 2010
@@ -27,6 +27,7 @@
 #include "llvm/Analysis/LoopPass.h"
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Instructions.h"
 #include "llvm/Operator.h"
 #include "llvm/Support/Allocator.h"
@@ -90,8 +91,8 @@
 static AliasAnalysis::AliasResult UnderlyingObjectsAlias(AliasAnalysis *AA,
                                                          const Value *A,
                                                          const Value *B) {
-  const Value *aObj = A->getUnderlyingObject();
-  const Value *bObj = B->getUnderlyingObject();
+  const Value *aObj = GetUnderlyingObject(A);
+  const Value *bObj = GetUnderlyingObject(B);
   return AA->alias(aObj, AA->getTypeStoreSize(aObj->getType()),
                    bObj, AA->getTypeStoreSize(bObj->getType()));
 }

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Dec 15 14:02:24 2010
@@ -25,6 +25,7 @@
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/MemoryBuiltins.h"
 #include "llvm/Analysis/PHITransAddr.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/PredIteratorCache.h"
@@ -338,7 +339,7 @@
     // need to continue scanning until the malloc call.
     if (isa<AllocaInst>(Inst) ||
         (isa<CallInst>(Inst) && extractMallocCall(Inst))) {
-      const Value *AccessPtr = MemLoc.Ptr->getUnderlyingObject();
+      const Value *AccessPtr = GetUnderlyingObject(MemLoc.Ptr);
       
       if (AccessPtr == Inst ||
           AA->alias(Inst, 1, AccessPtr, 1) == AliasAnalysis::MustAlias)

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Dec 15 14:02:24 2010
@@ -1426,3 +1426,23 @@
   // an empty string as a length.
   return Len == ~0ULL ? 1 : Len;
 }
+
+Value *llvm::GetUnderlyingObject(Value *V, unsigned MaxLookup) {
+  if (!V->getType()->isPointerTy())
+    return V;
+  for (unsigned Count = 0; MaxLookup == 0 || Count < MaxLookup; ++Count) {
+    if (GEPOperator *GEP = dyn_cast<GEPOperator>(V)) {
+      V = GEP->getPointerOperand();
+    } else if (Operator::getOpcode(V) == Instruction::BitCast) {
+      V = cast<Operator>(V)->getOperand(0);
+    } else if (GlobalAlias *GA = dyn_cast<GlobalAlias>(V)) {
+      if (GA->mayBeOverridden())
+        return V;
+      V = GA->getAliasee();
+    } else {
+      return V;
+    }
+    assert(V->getType()->isPointerTy() && "Unexpected operand type!");
+  }
+  return V;
+}

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Dec 15 14:02:24 2010
@@ -16,6 +16,7 @@
 #include "ScheduleDAGInstrs.h"
 #include "llvm/Operator.h"
 #include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -78,12 +79,12 @@
   } while (1);
 }
 
-/// getUnderlyingObject - This is a wrapper around Value::getUnderlyingObject
+/// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
 static const Value *getUnderlyingObject(const Value *V) {
   // First just call Value::getUnderlyingObject to let it do what it does.
   do {
-    V = V->getUnderlyingObject();
+    V = GetUnderlyingObject(V);
     // If it found an inttoptr, use special code to continue climing.
     if (Operator::getOpcode(V) != Instruction::IntToPtr)
       break;

Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Wed Dec 15 14:02:24 2010
@@ -324,7 +324,7 @@
   // other store to the same object.
   const TargetData &TD = *AA.getTargetData();
   
-  const Value *UO1 = P1->getUnderlyingObject(), *UO2 = P2->getUnderlyingObject();
+  const Value *UO1 = GetUnderlyingObject(P1), *UO2 = GetUnderlyingObject(P2);
   
   // If we can't resolve the same pointers to the same object, then we can't
   // analyze them at all.
@@ -542,7 +542,7 @@
       return false;
   
     Value *DepPointer =
-      getStoredPointerOperand(Dependency)->getUnderlyingObject();
+      GetUnderlyingObject(getStoredPointerOperand(Dependency));
 
     // Check for aliasing.
     if (!AA->isMustAlias(F->getArgOperand(0), DepPointer))
@@ -596,7 +596,7 @@
     // If we find a store, check to see if it points into a dead stack value.
     if (hasMemoryWrite(BBI) && isRemovable(BBI)) {
       // See through pointer-to-pointer bitcasts
-      Value *Pointer = getStoredPointerOperand(BBI)->getUnderlyingObject();
+      Value *Pointer = GetUnderlyingObject(getStoredPointerOperand(BBI));
 
       // Stores to stack values are valid candidates for removal.
       if (DeadStackObjects.count(Pointer)) {
@@ -703,7 +703,7 @@
 /// because the location is being loaded.
 void DSE::RemoveAccessedObjects(const AliasAnalysis::Location &LoadedLoc,
                                 SmallPtrSet<Value*, 16> &DeadStackObjects) {
-  const Value *UnderlyingPointer = LoadedLoc.Ptr->getUnderlyingObject();
+  const Value *UnderlyingPointer = GetUnderlyingObject(LoadedLoc.Ptr);
 
   // A constant can't be in the dead pointer set.
   if (isa<Constant>(UnderlyingPointer))

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Dec 15 14:02:24 2010
@@ -1076,7 +1076,7 @@
   Constant *Src = dyn_cast<Constant>(MTI->getSource());
   if (Src == 0) return -1;
   
-  GlobalVariable *GV = dyn_cast<GlobalVariable>(Src->getUnderlyingObject());
+  GlobalVariable *GV = dyn_cast<GlobalVariable>(GetUnderlyingObject(Src));
   if (GV == 0 || !GV->isConstant()) return -1;
   
   // See if the access is within the bounds of the transfer.

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Dec 15 14:02:24 2010
@@ -31,6 +31,7 @@
 #include "llvm/Module.h"
 #include "llvm/Pass.h"
 #include "llvm/Analysis/Dominators.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Transforms/Utils/PromoteMemToReg.h"
 #include "llvm/Transforms/Utils/Local.h"
@@ -490,9 +491,9 @@
       // If the source and destination are both to the same alloca, then this is
       // a noop copy-to-self, just delete it.  Otherwise, emit a load and store
       // as appropriate.
-      AllocaInst *OrigAI = cast<AllocaInst>(Ptr->getUnderlyingObject(0));
+      AllocaInst *OrigAI = cast<AllocaInst>(GetUnderlyingObject(Ptr, 0));
       
-      if (MTI->getSource()->getUnderlyingObject(0) != OrigAI) {
+      if (GetUnderlyingObject(MTI->getSource(), 0) != OrigAI) {
         // Dest must be OrigAI, change this to be a load from the original
         // pointer (bitcasted), then a store to our new alloca.
         assert(MTI->getRawDest() == Ptr && "Neither use is of pointer?");
@@ -502,7 +503,7 @@
         LoadInst *SrcVal = Builder.CreateLoad(SrcPtr, "srcval");
         SrcVal->setAlignment(MTI->getAlignment());
         Builder.CreateStore(SrcVal, NewAI);
-      } else if (MTI->getDest()->getUnderlyingObject(0) != OrigAI) {
+      } else if (GetUnderlyingObject(MTI->getDest(), 0) != OrigAI) {
         // Src must be OrigAI, change this to be a load from NewAI then a store
         // through the original dest pointer (bitcasted).
         assert(MTI->getRawSource() == Ptr && "Neither use is of pointer?");

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=121885&r1=121884&r2=121885&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Wed Dec 15 14:02:24 2010
@@ -346,27 +346,6 @@
   return V;
 }
 
-Value *Value::getUnderlyingObject(unsigned MaxLookup) {
-  if (!getType()->isPointerTy())
-    return this;
-  Value *V = this;
-  for (unsigned Count = 0; MaxLookup == 0 || Count < MaxLookup; ++Count) {
-    if (GEPOperator *GEP = dyn_cast<GEPOperator>(V)) {
-      V = GEP->getPointerOperand();
-    } else if (Operator::getOpcode(V) == Instruction::BitCast) {
-      V = cast<Operator>(V)->getOperand(0);
-    } else if (GlobalAlias *GA = dyn_cast<GlobalAlias>(V)) {
-      if (GA->mayBeOverridden())
-        return V;
-      V = GA->getAliasee();
-    } else {
-      return V;
-    }
-    assert(V->getType()->isPointerTy() && "Unexpected operand type!");
-  }
-  return V;
-}
-
 /// isDereferenceablePointer - Test if this value is always a pointer to
 /// allocated and suitably aligned memory for a simple load or store.
 bool Value::isDereferenceablePointer() const {



From gohman at apple.com  Wed Dec 15 14:10:26 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 20:10:26 -0000
Subject: [llvm-commits] [llvm] r121886 -
	/llvm/trunk/lib/Analysis/ValueTracking.cpp
Message-ID: <20101215201026.EA7142A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 14:10:26 2010
New Revision: 121886

URL: http://llvm.org/viewvc/llvm-project?rev=121886&view=rev
Log:
Strengthen GetUnderlyingObject using InstructionSimplify.

While LLVM's main design is that analysis code shouldn't
go out of its way to understand code which hasn't been
InstCombined, analysis utility routines like this can
find themselves being called in the middle of transform
passes when instcombine hasn't had a chance to run.

Modified:
    llvm/trunk/lib/Analysis/ValueTracking.cpp

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=121886&r1=121885&r2=121886&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Dec 15 14:10:26 2010
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Analysis/ValueTracking.h"
+#include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Constants.h"
 #include "llvm/Instructions.h"
 #include "llvm/GlobalVariable.h"
@@ -1440,6 +1441,14 @@
         return V;
       V = GA->getAliasee();
     } else {
+      // See if InstructionSimplify knows any relevant tricks.
+      if (Instruction *I = dyn_cast<Instruction>(V))
+        // TODO: Aquire TargetData and DominatorTree and use them.
+        if (Value *Simplified = SimplifyInstruction(I, 0, 0)) {
+          V = Simplified;
+          continue;
+        }
+
       return V;
     }
     assert(V->getType()->isPointerTy() && "Unexpected operand type!");



From peckw at wesleypeck.com  Wed Dec 15 14:14:09 2010
From: peckw at wesleypeck.com (Wesley Peck)
Date: Wed, 15 Dec 2010 20:14:09 -0000
Subject: [llvm-commits] [llvm] r121888 -
	/llvm/trunk/include/llvm/CallingConv.h
Message-ID: <20101215201409.654062A6C12C@llvm.org>

Author: peckw
Date: Wed Dec 15 14:14:09 2010
New Revision: 121888

URL: http://llvm.org/viewvc/llvm-project?rev=121888&view=rev
Log:
Adding target specific calling conventions to support the MBlaze GCC function
attributes "interrupt_handle" and "save_volatiles". Support for lowering these
correctly will be in an upcoming commit.

Modified:
    llvm/trunk/include/llvm/CallingConv.h

Modified: llvm/trunk/include/llvm/CallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallingConv.h?rev=121888&r1=121887&r2=121888&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CallingConv.h (original)
+++ llvm/trunk/include/llvm/CallingConv.h Wed Dec 15 14:14:09 2010
@@ -87,7 +87,14 @@
 
     /// PTX_Device - Call to a PTX device function.
     /// Passes all arguments in register or parameter space.
-    PTX_Device = 72
+    PTX_Device = 72,
+
+    /// MBLAZE_INTR - Calling convention used for MBlaze interrupt routines.
+    MBLAZE_INTR = 73,
+
+    /// MBLAZE_INTR - Calling convention used for MBlaze interrupt support
+    /// routines (i.e. GCC's save_volatiles attribute).
+    MBLAZE_SVOL = 74
   };
 } // End CallingConv namespace
 



From peckw at wesleypeck.com  Wed Dec 15 14:27:28 2010
From: peckw at wesleypeck.com (Wesley Peck)
Date: Wed, 15 Dec 2010 20:27:28 -0000
Subject: [llvm-commits] [llvm] r121891 - in /llvm/trunk:
 lib/Target/MBlaze/MBlazeFrameInfo.cpp
 lib/Target/MBlaze/MBlazeISelLowering.cpp
 lib/Target/MBlaze/MBlazeISelLowering.h lib/Target/MBlaze/MBlazeInstrInfo.td
 test/CodeGen/MBlaze/intr.ll test/CodeGen/MBlaze/svol.ll
Message-ID: <20101215202728.4AD1B2A6C12C@llvm.org>

Author: peckw
Date: Wed Dec 15 14:27:28 2010
New Revision: 121891

URL: http://llvm.org/viewvc/llvm-project?rev=121891&view=rev
Log:
Lower the MBlaze target specific calling conventions for "interrupt_handler"
and "save_volatiles" correctly. This completes the custom calling convention
functionality changes for the MBlaze backend that were started in 121888.

Added:
    llvm/trunk/test/CodeGen/MBlaze/intr.ll
    llvm/trunk/test/CodeGen/MBlaze/svol.ll
Modified:
    llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp?rev=121891&r1=121890&r2=121891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp Wed Dec 15 14:27:28 2010
@@ -132,6 +132,92 @@
   MBlazeFI->setStackAdjust(StackAdjust);
 }
 
+static void interruptFrameLayout(MachineFunction &MF) {
+  const Function *F = MF.getFunction();
+  llvm::CallingConv::ID CallConv = F->getCallingConv();
+
+  // If this function is not using either the interrupt_handler
+  // calling convention or the save_volatiles calling convention
+  // then we don't need to do any additional frame layout.
+  if (CallConv != llvm::CallingConv::MBLAZE_INTR &&
+      CallConv != llvm::CallingConv::MBLAZE_SVOL)
+      return;
+
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  const MBlazeInstrInfo &TII =
+    *static_cast<const MBlazeInstrInfo*>(MF.getTarget().getInstrInfo());
+
+  // Determine if the calling convention is the interrupt_handler
+  // calling convention. Some pieces of the prologue and epilogue
+  // only need to be emitted if we are lowering and interrupt handler.
+  bool isIntr = CallConv == llvm::CallingConv::MBLAZE_INTR;
+
+  // Determine where to put prologue and epilogue additions
+  MachineBasicBlock &MENT   = MF.front();
+  MachineBasicBlock &MEXT   = MF.back();
+
+  MachineBasicBlock::iterator MENTI = MENT.begin();
+  MachineBasicBlock::iterator MEXTI = prior(MEXT.end());
+
+  DebugLoc ENTDL = MENTI != MENT.end() ? MENTI->getDebugLoc() : DebugLoc();
+  DebugLoc EXTDL = MEXTI != MEXT.end() ? MEXTI->getDebugLoc() : DebugLoc();
+
+  // Store the frame indexes generated during prologue additions for use
+  // when we are generating the epilogue additions.
+  SmallVector<int, 10> VFI;
+
+  // Build the prologue SWI for R3 - R12 if needed. Note that R11 must
+  // always have a SWI because it is used when processing RMSR.
+  for (unsigned r = MBlaze::R3; r <= MBlaze::R12; ++r) {
+    if (!MRI.isPhysRegUsed(r) && !(isIntr && r == MBlaze::R11)) continue;
+    
+    int FI = MFI->CreateStackObject(4,4,false,false);
+    VFI.push_back(FI);
+
+    BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r)
+      .addFrameIndex(FI).addImm(0);
+  }
+    
+  // Build the prologue SWI for R17, R18
+  int R17FI = MFI->CreateStackObject(4,4,false,false);
+  int R18FI = MFI->CreateStackObject(4,4,false,false);
+
+  BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17)
+    .addFrameIndex(R17FI).addImm(0);
+    
+  BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18)
+    .addFrameIndex(R18FI).addImm(0);
+
+  // Buid the prologue SWI and the epilogue LWI for RMSR if needed
+  if (isIntr) {
+    int MSRFI = MFI->CreateStackObject(4,4,false,false);
+    BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
+      .addReg(MBlaze::RMSR);
+    BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
+      .addFrameIndex(MSRFI).addImm(0);
+
+    BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
+      .addFrameIndex(MSRFI).addImm(0);
+    BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR)
+      .addReg(MBlaze::R11);
+  }
+
+  // Build the epilogue LWI for R17, R18
+  BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18)
+    .addFrameIndex(R18FI).addImm(0);
+
+  BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17)
+    .addFrameIndex(R17FI).addImm(0);
+
+  // Build the epilogue LWI for R3 - R12 if needed
+  for (unsigned r = MBlaze::R12, i = VFI.size(); r >= MBlaze::R3; --r) {
+    if (!MRI.isPhysRegUsed(r)) continue;
+    BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), r)
+      .addFrameIndex(VFI[--i]).addImm(0);
+  }
+}
+
 static void determineFrameLayout(MachineFunction &MF) {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
@@ -174,6 +260,9 @@
   MachineBasicBlock::iterator MBBI = MBB.begin();
   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
 
+  llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
+  bool requiresRA = CallConv == llvm::CallingConv::MBLAZE_INTR;
+
   // Determine the correct frame layout
   determineFrameLayout(MF);
 
@@ -181,7 +270,7 @@
   unsigned StackSize = MFI->getStackSize();
 
   // No need to allocate space on the stack.
-  if (StackSize == 0 && !MFI->adjustsStack()) return;
+  if (StackSize == 0 && !MFI->adjustsStack() && !requiresRA) return;
 
   int FPOffset = MBlazeFI->getFPStackOffset();
   int RAOffset = MBlazeFI->getRAStackOffset();
@@ -191,7 +280,7 @@
       .addReg(MBlaze::R1).addImm(-StackSize);
 
   // swi  R15, R1, stack_loc
-  if (MFI->adjustsStack()) {
+  if (MFI->adjustsStack() || requiresRA) {
     BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
         .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset);
   }
@@ -217,6 +306,9 @@
 
   DebugLoc dl = MBBI->getDebugLoc();
 
+  llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
+  bool requiresRA = CallConv == llvm::CallingConv::MBLAZE_INTR;
+
   // Get the FI's where RA and FP are saved.
   int FPOffset = MBlazeFI->getFPStackOffset();
   int RAOffset = MBlazeFI->getRAStackOffset();
@@ -232,7 +324,7 @@
   }
 
   // lwi R15, R1, stack_loc
-  if (MFI->adjustsStack()) {
+  if (MFI->adjustsStack() || requiresRA) {
     BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15)
       .addReg(MBlaze::R1).addImm(RAOffset);
   }
@@ -251,8 +343,10 @@
                                                            const {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
+  llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
+  bool requiresRA = CallConv == llvm::CallingConv::MBLAZE_INTR;
 
-  if (MFI->adjustsStack()) {
+  if (MFI->adjustsStack() || requiresRA) {
     MBlazeFI->setRAStackOffset(0);
     MFI->CreateFixedObject(4,0,true);
   }
@@ -262,5 +356,6 @@
     MFI->CreateFixedObject(4,4,true);
   }
 
+  interruptFrameLayout(MF);
   analyzeFrameIndexes(MF);
 }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=121891&r1=121890&r2=121891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Wed Dec 15 14:27:28 2010
@@ -864,13 +864,18 @@
     Flag = Chain.getValue(1);
   }
 
-  // Return on MBlaze is always a "rtsd R15, 8"
+  // If this function is using the interrupt_handler calling convention
+  // then use "rtid r14, 0" otherwise use "rtsd r15, 8"
+  unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet 
+                                                              : MBlazeISD::Ret;
+  unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14 
+                                                              : MBlaze::R15;
+  SDValue DReg = DAG.getRegister(Reg, MVT::i32);
+
   if (Flag.getNode())
-    return DAG.getNode(MBlazeISD::Ret, dl, MVT::Other,
-                       Chain, DAG.getRegister(MBlaze::R15, MVT::i32), Flag);
-  else // Return Void
-    return DAG.getNode(MBlazeISD::Ret, dl, MVT::Other,
-                       Chain, DAG.getRegister(MBlaze::R15, MVT::i32));
+    return DAG.getNode(Ret, dl, MVT::Other, Chain, DReg, Flag);
+
+  return DAG.getNode(Ret, dl, MVT::Other, Chain, DReg);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h?rev=121891&r1=121890&r2=121891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h Wed Dec 15 14:27:28 2010
@@ -78,8 +78,11 @@
       // Integer Compare
       ICmp,
 
-      // Return
-      Ret
+      // Return from subroutine
+      Ret,
+
+      // Return from interrupt
+      IRet
     };
   }
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=121891&r1=121890&r2=121891&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Wed Dec 15 14:27:28 2010
@@ -18,6 +18,7 @@
 
 // def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
 def SDT_MBlazeRet     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
+def SDT_MBlazeIRet    : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
 def SDT_MBCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
@@ -28,6 +29,8 @@
 
 def MBlazeRet     : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet,
                            [SDNPHasChain, SDNPOptInFlag]>;
+def MBlazeIRet    : SDNode<"MBlazeISD::IRet", SDT_MBlazeIRet,
+                           [SDNPHasChain, SDNPOptInFlag]>;
 
 def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
                            [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
@@ -727,6 +730,7 @@
 
 // Ret instructions
 def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>;
+def : Pat<(MBlazeIRet GPR:$target), (RTID GPR:$target, 0x0)>;
 
 // BR instructions
 def : Pat<(br bb:$T), (BRID bb:$T)>;

Added: llvm/trunk/test/CodeGen/MBlaze/intr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/intr.ll?rev=121891&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/intr.ll (added)
+++ llvm/trunk/test/CodeGen/MBlaze/intr.ll Wed Dec 15 14:27:28 2010
@@ -0,0 +1,48 @@
+; Ensure that the MBlaze interrupt_handler calling convention (cc73) is handled
+; correctly correctly by the MBlaze backend.
+;
+; RUN: llc < %s -march=mblaze | FileCheck %s
+
+ at .str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
+ at _interrupt_handler = alias void ()* @myintr
+
+define cc73 void @myintr() nounwind noinline {
+  ; CHECK:        myintr:
+  ; CHECK:        swi   r3, r1
+  ; CHECK:        swi   r4, r1
+  ; CHECK:        swi   r5, r1
+  ; CHECK:        swi   r6, r1
+  ; CHECK:        swi   r7, r1
+  ; CHECK:        swi   r8, r1
+  ; CHECK:        swi   r9, r1
+  ; CHECK:        swi   r10, r1
+  ; CHECK:        swi   r11, r1
+  ; CHECK:        swi   r12, r1
+  ; CHECK:        swi   r17, r1
+  ; CHECK:        swi   r18, r1
+  ; CHECK:        mfs   r11, rmsr
+  ; CHECK:        swi   r11, r1
+  entry:
+    %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i32 0, i32 0))
+      ret void
+
+  ; CHECK:        lwi   r11, r1
+  ; CHECK:        mts   rmsr, r11
+  ; CHECK:        lwi   r18, r1
+  ; CHECK:        lwi   r17, r1
+  ; CHECK:        lwi   r12, r1
+  ; CHECK:        lwi   r11, r1
+  ; CHECK:        lwi   r10, r1
+  ; CHECK:        lwi   r9, r1
+  ; CHECK:        lwi   r8, r1
+  ; CHECK:        lwi   r7, r1
+  ; CHECK:        lwi   r6, r1
+  ; CHECK:        lwi   r5, r1
+  ; CHECK:        lwi   r4, r1
+  ; CHECK:        lwi   r3, r1
+  ; CHECK:        rtid  r14, 0
+}
+
+  ; CHECK:    .globl  _interrupt_handler
+  ; CHECK:    _interrupt_handler = myintr
+declare i32 @printf(i8*, ...)

Added: llvm/trunk/test/CodeGen/MBlaze/svol.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/svol.ll?rev=121891&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/svol.ll (added)
+++ llvm/trunk/test/CodeGen/MBlaze/svol.ll Wed Dec 15 14:27:28 2010
@@ -0,0 +1,80 @@
+; Ensure that the MBlaze save_volatiles calling convention (cc74) is handled
+; correctly correctly by the MBlaze backend.
+;
+; RUN: llc < %s -march=mblaze | FileCheck %s
+
+ at .str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
+
+define cc74 void @mysvol() nounwind noinline {
+  ; CHECK:        mysvol:
+  ; CHECK:        swi   r3, r1
+  ; CHECK:        swi   r4, r1
+  ; CHECK:        swi   r5, r1
+  ; CHECK:        swi   r6, r1
+  ; CHECK:        swi   r7, r1
+  ; CHECK:        swi   r8, r1
+  ; CHECK:        swi   r9, r1
+  ; CHECK:        swi   r10, r1
+  ; CHECK:        swi   r11, r1
+  ; CHECK:        swi   r12, r1
+  ; CHECK:        swi   r17, r1
+  ; CHECK:        swi   r18, r1
+  ; CHECK-NOT:    mfs   r11, rmsr
+  entry:
+    %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i32 0, i32 0))
+      ret void
+
+  ; CHECK-NOT:    mts   rmsr, r11
+  ; CHECK:        lwi   r18, r1
+  ; CHECK:        lwi   r17, r1
+  ; CHECK:        lwi   r12, r1
+  ; CHECK:        lwi   r11, r1
+  ; CHECK:        lwi   r10, r1
+  ; CHECK:        lwi   r9, r1
+  ; CHECK:        lwi   r8, r1
+  ; CHECK:        lwi   r7, r1
+  ; CHECK:        lwi   r6, r1
+  ; CHECK:        lwi   r5, r1
+  ; CHECK:        lwi   r4, r1
+  ; CHECK:        lwi   r3, r1
+  ; CHECK:        rtsd  r15, 8
+}
+
+define cc74 void @mysvol2() nounwind noinline {
+  ; CHECK:        mysvol2:
+  ; CHECK-NOT:    swi   r3, r1
+  ; CHECK-NOT:    swi   r4, r1
+  ; CHECK-NOT:    swi   r5, r1
+  ; CHECK-NOT:    swi   r6, r1
+  ; CHECK-NOT:    swi   r7, r1
+  ; CHECK-NOT:    swi   r8, r1
+  ; CHECK-NOT:    swi   r9, r1
+  ; CHECK-NOT:    swi   r10, r1
+  ; CHECK-NOT:    swi   r11, r1
+  ; CHECK-NOT:    swi   r12, r1
+  ; CHECK:        swi   r17, r1
+  ; CHECK:        swi   r18, r1
+  ; CHECK-NOT:    mfs   r11, rmsr
+entry:
+
+  ; CHECK-NOT:    mts   rmsr, r11
+  ; CHECK:        lwi   r18, r1
+  ; CHECK:        lwi   r17, r1
+  ; CHECK-NOT:    lwi   r12, r1
+  ; CHECK-NOT:    lwi   r11, r1
+  ; CHECK-NOT:    lwi   r10, r1
+  ; CHECK-NOT:    lwi   r9, r1
+  ; CHECK-NOT:    lwi   r8, r1
+  ; CHECK-NOT:    lwi   r7, r1
+  ; CHECK-NOT:    lwi   r6, r1
+  ; CHECK-NOT:    lwi   r5, r1
+  ; CHECK-NOT:    lwi   r4, r1
+  ; CHECK-NOT:    lwi   r3, r1
+  ; CHECK:        rtsd  r15, 8
+  ret void
+}
+
+  ; CHECK-NOT:    .globl  _interrupt_handler
+  ; CHECK-NOT:    _interrupt_handler = mysvol
+  ; CHECK-NOT:    _interrupt_handler = mysvol2
+declare i32 @printf(i8*, ...)



From gohman at apple.com  Wed Dec 15 14:39:25 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 20:39:25 -0000
Subject: [llvm-commits] [llvm] r121892 -
	/llvm/trunk/lib/Analysis/ValueTracking.cpp
Message-ID: <20101215203925.69EF02A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 14:39:25 2010
New Revision: 121892

URL: http://llvm.org/viewvc/llvm-project?rev=121892&view=rev
Log:
Revert r121886. DecomposeGEPExpression needs to be kept
in sync.

Modified:
    llvm/trunk/lib/Analysis/ValueTracking.cpp

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=121892&r1=121891&r2=121892&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Dec 15 14:39:25 2010
@@ -1441,14 +1441,6 @@
         return V;
       V = GA->getAliasee();
     } else {
-      // See if InstructionSimplify knows any relevant tricks.
-      if (Instruction *I = dyn_cast<Instruction>(V))
-        // TODO: Aquire TargetData and DominatorTree and use them.
-        if (Value *Simplified = SimplifyInstruction(I, 0, 0)) {
-          V = Simplified;
-          continue;
-        }
-
       return V;
     }
     assert(V->getType()->isPointerTy() && "Unexpected operand type!");



From stoklund at 2pi.dk  Wed Dec 15 14:40:23 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 15 Dec 2010 20:40:23 -0000
Subject: [llvm-commits] [llvm] r121893 -
	/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
Message-ID: <20101215204023.1B92E2A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 14:40:22 2010
New Revision: 121893

URL: http://llvm.org/viewvc/llvm-project?rev=121893&view=rev
Log:
Add SlotIndexes::getMBBRange() to get the range of a basic block in a single
lookup.

Modified:
    llvm/trunk/include/llvm/CodeGen/SlotIndexes.h

Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=121893&r1=121892&r2=121893&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Wed Dec 15 14:40:22 2010
@@ -545,18 +545,22 @@
       return nextNonNull;
     }
 
-    /// Returns the first index in the given basic block.
-    SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
+    /// Return the (start,end) range of the given basic block.
+    const std::pair<SlotIndex, SlotIndex> &
+    getMBBRange(const MachineBasicBlock *mbb) const {
       MBB2IdxMap::const_iterator itr = mbb2IdxMap.find(mbb);
       assert(itr != mbb2IdxMap.end() && "MBB not found in maps.");
-      return itr->second.first;
+      return itr->second;
+    }
+
+    /// Returns the first index in the given basic block.
+    SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
+      return getMBBRange(mbb).first;
     }
 
     /// Returns the last index in the given basic block.
     SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
-      MBB2IdxMap::const_iterator itr = mbb2IdxMap.find(mbb);
-      assert(itr != mbb2IdxMap.end() && "MBB not found in maps.");
-      return itr->second.second;
+      return getMBBRange(mbb).second;
     }
 
     /// Returns the basic block which the given index falls in.



From gohman at apple.com  Wed Dec 15 14:49:56 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 20:49:56 -0000
Subject: [llvm-commits] [llvm] r121895 - in /llvm/trunk/lib/Analysis:
 BasicAliasAnalysis.cpp ValueTracking.cpp
Message-ID: <20101215204956.288C12A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 14:49:55 2010
New Revision: 121895

URL: http://llvm.org/viewvc/llvm-project?rev=121895&view=rev
Log:
Reapply r121886, and also update DecomposeGEPExpression to keep
it in sync.

Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/lib/Analysis/ValueTracking.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=121895&r1=121894&r2=121895&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Wed Dec 15 14:49:55 2010
@@ -27,6 +27,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Analysis/CaptureTracking.h"
 #include "llvm/Analysis/MemoryBuiltins.h"
+#include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/ADT/SmallPtrSet.h"
@@ -262,6 +263,14 @@
       V = Op->getOperand(0);
       continue;
     }
+
+    if (const Instruction *I = dyn_cast<Instruction>(V))
+      // TODO: Get a DominatorTree and use it here.
+      if (const Value *Simplified =
+            SimplifyInstruction(const_cast<Instruction *>(I), TD)) {
+        V = Simplified;
+        continue;
+      }
     
     const GEPOperator *GEPOp = dyn_cast<GEPOperator>(Op);
     if (GEPOp == 0)

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=121895&r1=121894&r2=121895&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Dec 15 14:49:55 2010
@@ -1441,6 +1441,14 @@
         return V;
       V = GA->getAliasee();
     } else {
+      // See if InstructionSimplify knows any relevant tricks.
+      if (Instruction *I = dyn_cast<Instruction>(V))
+        // TODO: Aquire TargetData and DominatorTree and use them.
+        if (Value *Simplified = SimplifyInstruction(I, 0, 0)) {
+          V = Simplified;
+          continue;
+        }
+
       return V;
     }
     assert(V->getType()->isPointerTy() && "Unexpected operand type!");



From greened at obbligato.org  Wed Dec 15 15:10:59 2010
From: greened at obbligato.org (David A. Greene)
Date: Wed, 15 Dec 2010 15:10:59 -0600
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
	(Jason Kim's message of "Tue, 14 Dec 2010 16:21:16 -0800")
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	<nngy67sm3r7.fsf@royale.us.cray.com>
	<AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
Message-ID: <nnglj3qlp24.fsf@royale.us.cray.com>

Jason Kim <jasonwkim at google.com> writes:

> Hi David.
>
> Feedback below:

Thanks!

> 1. Please have one canonical list of executables (including things
> like (elf/macho/coff)-dump that are used by test/ and prepend the
> exact path to all of them, as having 3 sets of basically the same data
> is not likely to be well received. Can you perhaps use word boundary
> as a pattern check? (if you have to import re, so be it.)

Ok.

> 2. Add verbose comment to lit.cfg and TestRunner.py

Ok.  What kind of comment would you like to see?  I'll add something
about why we're doing the substitutions.  Anything else?

> 5. File a doc bug to remind the core developers about this change (or
> patch the doc directly?) You can do this separately.

I'll do it at the same time.  It makes sense to keep it together.

                                -Dave

From kennethuil at gmail.com  Wed Dec 15 15:12:11 2010
From: kennethuil at gmail.com (Kenneth Uildriks)
Date: Wed, 15 Dec 2010 15:12:11 -0600
Subject: [llvm-commits] [PATCH] Fix llvm.invariant support
In-Reply-To: <4CFC16E0.1050103@mxc.ca>
References: <AANLkTin-c1uSEVh=XDAxmkNyVUpaLtJ_9FVx=T8ykc=1@mail.gmail.com>
	<AANLkTiknjjLy6FDp9kYSFBQ2jn8UxWPJ8yS1x44ugx54@mail.gmail.com>
	<0C0069DC-258D-45D1-877E-3921693D2221@apple.com>
	<AANLkTi=xXK3XTdRc=i33aSeP1s7NsXcmPZu==vWhvvg_@mail.gmail.com>
	<AANLkTinCGvwsT_DFgR3qwd0ogRhO8QC3QPc4Ewpm4tb_@mail.gmail.com>
	<4CFC16E0.1050103@mxc.ca>
Message-ID: <AANLkTim5YnDwVB7s5of3RHs=eS1ziKY+n75x+R4yjoCt@mail.gmail.com>

On Sun, Dec 5, 2010 at 4:49 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Kenneth Uildriks wrote:
>>
>> Here's the updated version.
>
> Firstly, could you please reduce your tests? Try writing tests as .ll files
> by hand; they should be absolutely minimal to expose the optimization (or
> verify that we don't do an unsafe transformation).
>
> + ? ?DEBUG(errs() << "Invariant value is (" << *(BI->first) << ", "
> + ? ? ? ?<< BI->second.Size << ")\n");
> + ? ?DEBUG(errs() << "Target is (" << *MemLoc.Ptr << ", " << MemLoc.Size
> + ? ? ? ?<< ")\n");
>
> These should be DEBUG(dbgs() << ...) not errs(). Please check all of them.
>
> Nick
>
After reducing the tests, I found cases that it missed, so I reworked
the algorithm.  Now it recognizes invariant regions as regions of code
dominated by an llvm.invariant.begin that aren't reachable from the
matching llvm.invariant.end without going back through the
llvm.invariant.begin.  It brings in the DominatorTree and
DominanceFrontier analyses to figure this out more quickly and
cleanly.

In MemDepPrereqs.patch, there are changes to DominanceFrontier and
BreakCritical edges that were needed for my MemoryDependenceAnalysis
changes to pass all the nightly tests.  Since DominanceFrontier is
really a cache of frontier analysis results, it seems to me that it
shouldn't be asserting that an add attempt isn't redundant (and a
later pass was trying to add something that my algorithm had already
looked up in a few cases).  Also, there was a latent bug in
BreakCriticalEdges that allows an llvm_unreachable assertion to
occasionally hit if DominanceFrontier is in play and a block is
unreachable.
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From wendling at apple.com  Wed Dec 15 15:15:34 2010
From: wendling at apple.com (Bill Wendling)
Date: Wed, 15 Dec 2010 13:15:34 -0800
Subject: [llvm-commits] [llvm] r121851 - in /llvm/trunk:
	include/llvm/Support/MathExtras.h lib/MC/MCStreamer.cpp
In-Reply-To: <20101215071224.527C52A6C12C@llvm.org>
References: <20101215071224.527C52A6C12C@llvm.org>
Message-ID: <39CE75D9-4A54-435B-9B0B-24C5A719F8A5@apple.com>

On Dec 14, 2010, at 11:12 PM, Rafael Espindola wrote:

> Author: rafael
> Date: Wed Dec 15 01:12:24 2010
> New Revision: 121851
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121851&view=rev
> Log:
> Generalize an assert.
> 
> Modified:
>    llvm/trunk/include/llvm/Support/MathExtras.h
>    llvm/trunk/lib/MC/MCStreamer.cpp
> 
> Modified: llvm/trunk/include/llvm/Support/MathExtras.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MathExtras.h?rev=121851&r1=121850&r2=121851&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/MathExtras.h (original)
> +++ llvm/trunk/include/llvm/Support/MathExtras.h Wed Dec 15 01:12:24 2010
> @@ -76,6 +76,12 @@
>   return x == (x & (~0ULL >> (64 - N)));
> }
> 
> +/// isIIntN - Checks if an signed integer fits into the given (dynamic)

"isIIntN" is a typo.

-bw

> +/// bit width.
> +inline bool isIntN(unsigned N, int64_t x) {
> +  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
> +}
> +
> /// isMask_32 - This function returns true if the argument is a sequence of ones
> /// starting at the least significant bit with the remainder zero (32 bit
> /// version).   Ex. isMask_32(0x0000FFFFU) == true.
> 
> Modified: llvm/trunk/lib/MC/MCStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=121851&r1=121850&r2=121851&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Dec 15 01:12:24 2010
> @@ -48,7 +48,8 @@
> void MCStreamer::EmitIntValue(uint64_t Value, unsigned Size,
>                               unsigned AddrSpace) {
>   assert(Size <= 8 && "Invalid size");
> -  assert(!(Size == 1 && (signed)Value > 255) && "Invalid size");
> +  unsigned Bits = 8 * Size;
> +  assert((isUIntN(Bits, Value) || isIntN(Bits, Value)) && "Invalid size");
>   char buf[8];
>   // FIXME: Endianness assumption.
>   for (unsigned i = 0; i != Size; ++i)
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From bob.wilson at apple.com  Wed Dec 15 16:14:02 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 15 Dec 2010 22:14:02 -0000
Subject: [llvm-commits] [llvm] r121901 - /llvm/trunk/test/MC/ARM/
Message-ID: <20101215221402.7890D2A6C12C@llvm.org>

Author: bwilson
Date: Wed Dec 15 16:14:01 2010
New Revision: 121901

URL: http://llvm.org/viewvc/llvm-project?rev=121901&view=rev
Log:
Fix misspelled target triples in MC/ARM test commands.

Modified:
    llvm/trunk/test/MC/ARM/neon-abs-encoding.s
    llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s
    llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s
    llvm/trunk/test/MC/ARM/neon-cmp-encoding.s
    llvm/trunk/test/MC/ARM/neon-convert-encoding.s
    llvm/trunk/test/MC/ARM/neon-dup-encoding.s
    llvm/trunk/test/MC/ARM/neon-minmax-encoding.s
    llvm/trunk/test/MC/ARM/neon-mov-encoding.s
    llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s
    llvm/trunk/test/MC/ARM/neon-mul-encoding.s
    llvm/trunk/test/MC/ARM/neon-neg-encoding.s
    llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s
    llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s
    llvm/trunk/test/MC/ARM/neon-reverse-encoding.s
    llvm/trunk/test/MC/ARM/neon-satshift-encoding.s
    llvm/trunk/test/MC/ARM/neon-shift-encoding.s
    llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s
    llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s
    llvm/trunk/test/MC/ARM/neon-sub-encoding.s
    llvm/trunk/test/MC/ARM/neon-table-encoding.s
    llvm/trunk/test/MC/ARM/neont2-abs-encoding.s
    llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s
    llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s
    llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s
    llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s
    llvm/trunk/test/MC/ARM/neont2-convert-encoding.s
    llvm/trunk/test/MC/ARM/neont2-dup-encoding.s
    llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s
    llvm/trunk/test/MC/ARM/neont2-mov-encoding.s
    llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s
    llvm/trunk/test/MC/ARM/neont2-mul-encoding.s
    llvm/trunk/test/MC/ARM/neont2-neg-encoding.s
    llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s
    llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s
    llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s
    llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s
    llvm/trunk/test/MC/ARM/neont2-shift-encoding.s
    llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s
    llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s
    llvm/trunk/test/MC/ARM/neont2-sub-encoding.s
    llvm/trunk/test/MC/ARM/neont2-table-encoding.s

Modified: llvm/trunk/test/MC/ARM/neon-abs-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-abs-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-abs-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-abs-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vabs.s8	d16, d16                @ encoding: [0x20,0x03,0xf1,0xf3]
 	vabs.s8	d16, d16

Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 @ NOTE: This currently fails because the ASM parser doesn't parse vabal.
 

Modified: llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vcnt.8	d16, d16                @ encoding: [0x20,0x05,0xf0,0xf3]

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vand	d16, d17, d16           @ encoding: [0xb0,0x01,0x41,0xf2]

Modified: llvm/trunk/test/MC/ARM/neon-cmp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-cmp-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-cmp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-cmp-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ FIXME: We cannot currently test the following instructions, which are 

Modified: llvm/trunk/test/MC/ARM/neon-convert-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-convert-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-convert-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-convert-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vcvt.s32.f32	d16, d16        @ encoding: [0x20,0x07,0xfb,0xf3]
 	vcvt.s32.f32	d16, d16

Modified: llvm/trunk/test/MC/ARM/neon-dup-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-dup-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-dup-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-dup-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vdup.8	d16, r0                 @ encoding: [0x90,0x0b,0xc0,0xee]

Modified: llvm/trunk/test/MC/ARM/neon-minmax-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-minmax-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-minmax-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-minmax-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vmin.s8	d16, d16, d17           @ encoding: [0xb1,0x06,0x40,0xf2]
 	vmin.s8	d16, d16, d17

Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vmov.i8	d16, #0x8               @ encoding: [0x18,0x0e,0xc0,0xf2]

Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vmla.i8	d16, d18, d17           @ encoding: [0xa1,0x09,0x42,0xf2]

Modified: llvm/trunk/test/MC/ARM/neon-mul-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mul-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-mul-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vmul.i8	d16, d16, d17           @ encoding: [0xb1,0x09,0x40,0xf2]
 	vmul.i8	d16, d16, d17

Modified: llvm/trunk/test/MC/ARM/neon-neg-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-neg-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-neg-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-neg-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vneg.s8	d16, d16                @ encoding: [0xa0,0x03,0xf1,0xf3]
 	vneg.s8	d16, d16

Modified: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vpadd.i8	d16, d17, d16   @ encoding: [0xb0,0x0b,0x41,0xf2]

Modified: llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-reciprocal-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vrecpe.u32	d16, d16        @ encoding: [0x20,0x04,0xfb,0xf3]
 	vrecpe.u32	d16, d16

Modified: llvm/trunk/test/MC/ARM/neon-reverse-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-reverse-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-reverse-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-reverse-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vrev64.8	d16, d16        @ encoding: [0x20,0x00,0xf0,0xf3]
 	vrev64.8	d16, d16

Modified: llvm/trunk/test/MC/ARM/neon-satshift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-satshift-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-satshift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-satshift-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vqshl.s8	d16, d16, d17   @ encoding: [0xb0,0x04,0x41,0xf2]
 	vqshl.s8	d16, d16, d17

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vshl.u8	d16, d17, d16           @ encoding: [0xa1,0x04,0x40,0xf3]
 	vshl.u8	d16, d17, d16

Modified: llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vsra.s8	d17, d16, #8            @ encoding: [0x30,0x11,0xc8,0xf2]
 	vsra.s8	d17, d16, #8

Modified: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vext.8	d16, d17, d16, #3       @ encoding: [0xa0,0x03,0xf1,0xf2]
 	vext.8	d16, d17, d16, #3

Modified: llvm/trunk/test/MC/ARM/neon-sub-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-sub-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-sub-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-sub-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vsub.i8	d16, d17, d16           @ encoding: [0xa0,0x08,0x41,0xf3]
 	vsub.i8	d16, d17, d16

Modified: llvm/trunk/test/MC/ARM/neon-table-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-table-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-table-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-table-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 @ CHECK: vtbl.8	d16, {d17}, d16         @ encoding: [0xa0,0x08,0xf1,0xf3]

Modified: llvm/trunk/test/MC/ARM/neont2-abs-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-abs-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-abs-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-abs-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-absdiff-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 @ NOTE: This currently fails because the ASM parser doesn't parse vabal.
 

Modified: llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-bitcount-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16

Modified: llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-bitwise-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16

Modified: llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-cmp-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-convert-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-convert-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-convert-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-convert-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-dup-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-dup-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-dup-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-dup-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16

Modified: llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-minmax-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16

Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16

Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-neg-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-neg-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-neg-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-neg-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-pairwise-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16

Modified: llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-reciprocal-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-reverse-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vrev64.8	d16, d16        @ encoding: [0xf0,0xff,0x20,0x00]
 	vrev64.8	d16, d16

Modified: llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-satshift-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-shift-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-shift-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-shiftaccum-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-shuffle-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 

Modified: llvm/trunk/test/MC/ARM/neont2-sub-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-sub-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-sub-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-sub-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vext.8	d16, d17, d16, #3       @ encoding: [0xf1,0xef,0xa0,0x03]
 	vext.8	d16, d17, d16, #3

Modified: llvm/trunk/test/MC/ARM/neont2-table-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-table-encoding.s?rev=121901&r1=121900&r2=121901&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-table-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-table-encoding.s Wed Dec 15 16:14:01 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 @ XFAIL: *
 
 .code 16



From bob.wilson at apple.com  Wed Dec 15 16:14:13 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 15 Dec 2010 22:14:13 -0000
Subject: [llvm-commits] [llvm] r121902 - in /llvm/trunk:
 include/llvm/IntrinsicsARM.td lib/Target/ARM/ARM.td
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrNEON.td
 test/CodeGen/ARM/vcvt.ll test/MC/ARM/neon-convert-encoding.s
 test/MC/ARM/neont2-convert-encoding.s
Message-ID: <20101215221413.35D7D2A6C12C@llvm.org>

Author: bwilson
Date: Wed Dec 15 16:14:12 2010
New Revision: 121902

URL: http://llvm.org/viewvc/llvm-project?rev=121902&view=rev
Log:
Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

Modified:
    llvm/trunk/include/llvm/IntrinsicsARM.td
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/CodeGen/ARM/vcvt.ll
    llvm/trunk/test/MC/ARM/neon-convert-encoding.s
    llvm/trunk/test/MC/ARM/neont2-convert-encoding.s

Modified: llvm/trunk/include/llvm/IntrinsicsARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsARM.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsARM.td Wed Dec 15 16:14:12 2010
@@ -286,6 +286,12 @@
 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 
+// Vector Conversions Between Half-Precision and Single-Precision.
+def int_arm_neon_vcvtfp2hf
+    : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
+def int_arm_neon_vcvthf2fp
+    : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
+
 // Narrowing Saturating Vector Moves.
 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Wed Dec 15 16:14:12 2010
@@ -103,7 +103,8 @@
                                     FeatureHasSlowFPVMLx, FeatureT2XtPk]>;
 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
                                    "Cortex-A9 ARM processors",
-                                   [FeatureHasSlowFPVMLx, FeatureT2XtPk]>;
+                                   [FeatureHasSlowFPVMLx, FeatureT2XtPk,
+                                    FeatureFP16]>;
 
 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  : Processor<Name, GenericItineraries, Features>;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec 15 16:14:12 2010
@@ -156,6 +156,7 @@
 def HasVFP2          : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
 def HasVFP3          : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
+def HasFP16          : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
 def HasDivide        : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
                                  AssemblerPredicate;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Dec 15 16:14:12 2010
@@ -1724,6 +1724,15 @@
         (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
         [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
 
+// Long 2-register intrinsics.
+class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
+              bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
+              InstrItinClass itin, string OpcodeStr, string Dt,
+              ValueType TyQ, ValueType TyD, Intrinsic IntOp>
+  : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
+        (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
+        [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
+
 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
   : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
@@ -4447,6 +4456,16 @@
 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
                         v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
 
+//   VCVT     : Vector Convert Between Half-Precision and Single-Precision.
+def  VCVTf2h  : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
+                        IIC_VUNAQ, "vcvt", "f16.f32",
+                        v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
+                Requires<[HasNEON, HasFP16]>;
+def  VCVTh2f  : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
+                        IIC_VUNAQ, "vcvt", "f32.f16",
+                        v4f32, v4i16, int_arm_neon_vcvthf2fp>,
+                Requires<[HasNEON, HasFP16]>;
+
 // Vector Reverse.
 
 //   VREV64   : Vector Reverse elements within 64-bit doublewords

Modified: llvm/trunk/test/CodeGen/ARM/vcvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt.ll?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vcvt.ll Wed Dec 15 16:14:12 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
 
 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 ;CHECK: vcvt_f32tos32:
@@ -138,3 +138,21 @@
 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
 
+define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
+;CHECK: vcvt_f16tof32:
+;CHECK: vcvt.f32.f16
+	%tmp1 = load <4 x i16>* %A
+	%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
+	ret <4 x float> %tmp2
+}
+
+define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
+;CHECK: vcvt_f32tof16:
+;CHECK: vcvt.f16.f32
+	%tmp1 = load <4 x float>* %A
+	%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
+	ret <4 x i16> %tmp2
+}
+
+declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone

Modified: llvm/trunk/test/MC/ARM/neon-convert-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-convert-encoding.s?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-convert-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-convert-encoding.s Wed Dec 15 16:14:12 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a9 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
 @ CHECK: vcvt.s32.f32	d16, d16        @ encoding: [0x20,0x07,0xfb,0xf3]
 	vcvt.s32.f32	d16, d16
@@ -32,3 +32,7 @@
 	vcvt.f32.s32	q8, q8, #1
 @ CHECK: vcvt.f32.u32	q8, q8, #1      @ encoding: [0x70,0x0e,0xff,0xf3]
 	vcvt.f32.u32	q8, q8, #1
+@ CHECK: vcvt.f32.f16	q8, d16         @ encoding: [0x20,0x07,0xf6,0xf3]
+	vcvt.f32.f16	q8, d16
+@ CHECK: vcvt.f16.f32	d16, q8         @ encoding: [0x20,0x06,0xf6,0xf3]
+	vcvt.f16.f32	d16, q8

Modified: llvm/trunk/test/MC/ARM/neont2-convert-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-convert-encoding.s?rev=121902&r1=121901&r2=121902&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-convert-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-convert-encoding.s Wed Dec 15 16:14:12 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -mcpu=cortex-a9 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
 
 .code 16
 
@@ -34,3 +34,7 @@
 	vcvt.f32.s32	q8, q8, #1
 @ CHECK: vcvt.f32.u32	q8, q8, #1      @ encoding: [0xff,0xff,0x70,0x0e]
 	vcvt.f32.u32	q8, q8, #1
+@ CHECK: vcvt.f32.f16	q8, d16         @ encoding: [0xf6,0xff,0x20,0x07]
+	vcvt.f32.f16	q8, d16
+@ CHECK: vcvt.f16.f32	d16, q8         @ encoding: [0xf6,0xff,0x20,0x06]
+	vcvt.f16.f32	d16, q8



From evan.cheng at apple.com  Wed Dec 15 16:16:21 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 15 Dec 2010 22:16:21 -0000
Subject: [llvm-commits] [llvm] r121903 - in /llvm/trunk:
 lib/CodeGen/MachineCSE.cpp test/CodeGen/X86/machine-cse.ll
Message-ID: <20101215221621.73C952A6C12C@llvm.org>

Author: evancheng
Date: Wed Dec 15 16:16:21 2010
New Revision: 121903

URL: http://llvm.org/viewvc/llvm-project?rev=121903&view=rev
Log:
Teach machine cse to commute instructions.

Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/test/CodeGen/X86/machine-cse.ll

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=121903&r1=121902&r2=121903&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Wed Dec 15 16:16:21 2010
@@ -24,7 +24,6 @@
 #include "llvm/ADT/ScopedHashTable.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
@@ -33,6 +32,7 @@
 STATISTIC(NumCSEs,      "Number of common subexpression eliminated");
 STATISTIC(NumPhysCSEs,
           "Number of physreg referencing common subexpr eliminated");
+STATISTIC(NumCommutes,  "Number of copies coalesced after commuting");
 
 namespace {
   class MachineCSE : public MachineFunctionPass {
@@ -368,7 +368,22 @@
         FoundCSE = VNT.count(MI);
       }
     }
-    // FIXME: commute commutable instructions?
+
+    // Commute commutable instructions.
+    bool Commuted = false;
+    if (!FoundCSE && MI->getDesc().isCommutable()) {
+      MachineInstr *NewMI = TII->commuteInstruction(MI);
+      if (NewMI) {
+        Commuted = true;
+        FoundCSE = VNT.count(NewMI);
+        if (NewMI != MI)
+          // New instruction. It doesn't need to be kept.
+          NewMI->eraseFromParent();
+        else if (!FoundCSE)
+          // MI was changed but it didn't help, commute it back!
+          (void)TII->commuteInstruction(MI);
+      }
+    }
 
     // If the instruction defines physical registers and the values *may* be
     // used, then it's not safe to replace it with a common subexpression.
@@ -430,6 +445,8 @@
       ++NumCSEs;
       if (!PhysRefs.empty())
         ++NumPhysCSEs;
+      if (Commuted)
+        ++NumCommutes;
     } else {
       DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
       VNT.insert(MI, CurrVN++);

Modified: llvm/trunk/test/CodeGen/X86/machine-cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cse.ll?rev=121903&r1=121902&r2=121903&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-cse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/machine-cse.ll Wed Dec 15 16:16:21 2010
@@ -37,3 +37,43 @@
 declare void @bar(i32*)
 
 declare fastcc i8* @foo(%struct.s2*) nounwind
+
+; rdar://8773371
+
+declare void @printf(...) nounwind
+
+define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
+; CHECK: commute:
+entry:
+  switch i32 %test_case, label %sw.bb307 [
+    i32 1, label %sw.bb
+    i32 2, label %sw.bb
+    i32 3, label %sw.bb
+  ]
+
+sw.bb:                                            ; preds = %entry, %entry, %entry
+  %mul = mul nsw i32 %test_case, 3
+  %mul20 = mul nsw i32 %mul, %scale
+  br i1 undef, label %if.end34, label %sw.bb307
+
+if.end34:                                         ; preds = %sw.bb
+; CHECK: %if.end34
+; CHECK: imull
+; CHECK: leal
+; CHECK-NOT: imull
+  tail call void (...)* @printf(i32 %test_case, i32 %mul20) nounwind
+  %tmp = mul i32 %scale, %test_case
+  %tmp752 = mul i32 %tmp, 3
+  %tmp753 = zext i32 %tmp752 to i64
+  br label %bb.nph743.us
+
+for.body53.us:                                    ; preds = %bb.nph743.us, %for.body53.us
+  %exitcond = icmp eq i64 undef, %tmp753
+  br i1 %exitcond, label %bb.nph743.us, label %for.body53.us
+
+bb.nph743.us:                                     ; preds = %for.body53.us, %if.end34
+  br label %for.body53.us
+
+sw.bb307:                                         ; preds = %sw.bb, %entry
+  ret void
+}



From matthewbg at google.com  Wed Dec 15 16:21:20 2010
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Wed, 15 Dec 2010 22:21:20 -0000
Subject: [llvm-commits] [llvm] r121904 - /llvm/trunk/lib/MC/MCStreamer.cpp
Message-ID: <20101215222120.5B0202A6C12C@llvm.org>

Author: matthewbg
Date: Wed Dec 15 16:21:20 2010
New Revision: 121904

URL: http://llvm.org/viewvc/llvm-project?rev=121904&view=rev
Log:
Fix opt -Werror build

Modified:
    llvm/trunk/lib/MC/MCStreamer.cpp

Modified: llvm/trunk/lib/MC/MCStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=121904&r1=121903&r2=121904&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Dec 15 16:21:20 2010
@@ -49,6 +49,7 @@
                               unsigned AddrSpace) {
   assert(Size <= 8 && "Invalid size");
   unsigned Bits = 8 * Size;
+  (void)Bits;
   assert((isUIntN(Bits, Value) || isIntN(Bits, Value)) && "Invalid size");
   char buf[8];
   // FIXME: Endianness assumption.



From resistor at mac.com  Wed Dec 15 16:32:38 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 15 Dec 2010 22:32:38 -0000
Subject: [llvm-commits] [llvm] r121905 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineCompares.cpp
 test/Transforms/InstCombine/overflow.ll
Message-ID: <20101215223238.CDEC32A6C12C@llvm.org>

Author: resistor
Date: Wed Dec 15 16:32:38 2010
New Revision: 121905

URL: http://llvm.org/viewvc/llvm-project?rev=121905&view=rev
Log:
Add an InstCombine transform to recognize instances of manual overflow-safe addition
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics.  This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.

Fixes <rdar://problem/8558713>.

Added:
    llvm/trunk/test/Transforms/InstCombine/overflow.ll
Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=121905&r1=121904&r2=121905&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Dec 15 16:32:38 2010
@@ -1657,6 +1657,71 @@
   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
     Value *A = 0, *B = 0;
     
+    // Match the following pattern, which is a common idiom when writing
+    // overflow-safe integer arithmetic function.  The source performs an
+    // addition in wider type, and explicitly checks for overflow using
+    // comparisons against INT_MIN and INT_MAX.  Simplify this by using the
+    // sadd_with_overflow intrinsic.
+    // FIXME: This could probably be generalized to handle other overflow-safe
+    // operations if we worked out the formulas to compute the appropriate 
+    // magic constants.
+    // 
+    // INT64 : a, b, sum = a + b
+    // if sum < INT32_MIN || sum > INT_MAX then
+    //   ...
+    // else
+    //   ...
+    {
+    ConstantInt *CI2;
+    
+    // I = icmp ugt (add (add A B) CI2) CI
+    if (I.getPredicate() == ICmpInst::ICMP_UGT &&
+        match(Op0, m_Add(m_Add(m_Value(A), m_Value(B)),
+                   m_ConstantInt(CI2)))) {
+      const IntegerType *WideType = cast<IntegerType>(CI->getType());
+      unsigned WideWidth = WideType->getBitWidth();
+      unsigned NarrowWidth = WideWidth / 2;
+      const IntegerType *NarrowType =
+        IntegerType::get(CI->getContext(), NarrowWidth);
+      
+      // NarrowAllOnes and NarrowSignBit are the magic constants used to
+      // perform an overflow check in the wider type: 0x00..00FF..FF and
+      // 0x00..0010..00 respectively, where the highest set bit in each is
+      // what would be the sign bit in the narrower type.
+      ConstantInt *NarrowAllOnes = cast<ConstantInt>(ConstantInt::get(WideType,
+        APInt::getAllOnesValue(NarrowWidth).zext(WideWidth)));
+      APInt SignBit(WideWidth, 0);
+      SignBit.setBit(NarrowWidth-1);
+      ConstantInt *NarrowSignBit =
+       cast<ConstantInt>(ConstantInt::get(WideType, SignBit));
+      
+      if (CI == NarrowAllOnes && CI2 == NarrowSignBit) {
+        Module *M = I.getParent()->getParent()->getParent();
+        
+        const Type *IntrinsicType = NarrowType;
+        Value *F = Intrinsic::getDeclaration(M, Intrinsic::sadd_with_overflow,
+          &IntrinsicType, 1);
+        
+        // If the pattern matches, truncate the inputs to the narrower type and
+        // use the sadd_with_overflow intrinsic to efficiently compute both the
+        // result and the overflow bit.
+        Value *TruncA = Builder->CreateTrunc(A, NarrowType, A->getName());
+        Value *TruncB = Builder->CreateTrunc(B, NarrowType, B->getName());
+        CallInst *Call = Builder->CreateCall2(F, TruncA, TruncB);
+        Value *Add = Builder->CreateExtractValue(Call, 0);
+        Value *ZExt = Builder->CreateZExt(Add, WideType);
+        
+        // The inner add was the result of the narrow add, zero extended to the
+        // wider type.  Replace it with the result computed by the intrinsic.
+        Instruction *OrigAdd =
+          cast<Instruction>(cast<Instruction>(I.getOperand(0))->getOperand(0));
+        OrigAdd->replaceAllUsesWith(ZExt);
+        
+        return ExtractValueInst::Create(Call, 1);
+      }
+    }
+    }
+    
     // (icmp ne/eq (sub A B) 0) -> (icmp ne/eq A, B)
     if (I.isEquality() && CI->isZero() &&
         match(Op0, m_Sub(m_Value(A), m_Value(B)))) {

Added: llvm/trunk/test/Transforms/InstCombine/overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/overflow.ll?rev=121905&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/overflow.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/overflow.ll Wed Dec 15 16:32:38 2010
@@ -0,0 +1,27 @@
+; RUN: opt -S -instcombine < %s | FileCheck %s
+; <rdar://problem/8558713>
+
+; CHECK: @test1
+define i32 @test1(i32 %a, i32 %b) nounwind ssp {
+entry:
+; CHECK-NOT: sext
+  %conv = sext i32 %a to i64
+  %conv2 = sext i32 %b to i64
+  %add = add nsw i64 %conv2, %conv
+  %add.off = add i64 %add, 2147483648
+; CHECK: llvm.sadd.with.overflow
+  %0 = icmp ugt i64 %add.off, 4294967295
+  br i1 %0, label %if.then, label %if.end
+
+if.then:
+  %call = tail call i32 (...)* @throwAnExceptionOrWhatever() nounwind
+  br label %if.end
+
+if.end:
+; CHECK-NOT: trunc
+  %conv9 = trunc i64 %add to i32
+; CHECK: ret i32
+  ret i32 %conv9
+}
+
+declare i32 @throwAnExceptionOrWhatever(...)



From rafael.espindola at gmail.com  Wed Dec 15 16:33:06 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 15 Dec 2010 22:33:06 -0000
Subject: [llvm-commits] [llvm] r121906 -
	/llvm/trunk/include/llvm/Support/MathExtras.h
Message-ID: <20101215223306.46EA92A6C12C@llvm.org>

Author: rafael
Date: Wed Dec 15 16:33:06 2010
New Revision: 121906

URL: http://llvm.org/viewvc/llvm-project?rev=121906&view=rev
Log:
Typo.

Modified:
    llvm/trunk/include/llvm/Support/MathExtras.h

Modified: llvm/trunk/include/llvm/Support/MathExtras.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MathExtras.h?rev=121906&r1=121905&r2=121906&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/MathExtras.h (original)
+++ llvm/trunk/include/llvm/Support/MathExtras.h Wed Dec 15 16:33:06 2010
@@ -76,7 +76,7 @@
   return x == (x & (~0ULL >> (64 - N)));
 }
 
-/// isIIntN - Checks if an signed integer fits into the given (dynamic)
+/// isIntN - Checks if an signed integer fits into the given (dynamic)
 /// bit width.
 inline bool isIntN(unsigned N, int64_t x) {
   return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));



From echristo at apple.com  Wed Dec 15 16:57:02 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 15 Dec 2010 14:57:02 -0800
Subject: [llvm-commits] [llvm] r121904 -
	/llvm/trunk/lib/MC/MCStreamer.cpp
In-Reply-To: <20101215222120.5B0202A6C12C@llvm.org>
References: <20101215222120.5B0202A6C12C@llvm.org>
Message-ID: <4777796A-FFF8-47DE-8489-0C8DC9435BCA@apple.com>


On Dec 15, 2010, at 2:21 PM, Matt Beaumont-Gay wrote:

> Author: matthewbg
> Date: Wed Dec 15 16:21:20 2010
> New Revision: 121904
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121904&view=rev
> Log:
> Fix opt -Werror build
> 
> Modified:
>    llvm/trunk/lib/MC/MCStreamer.cpp
> 
> Modified: llvm/trunk/lib/MC/MCStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=121904&r1=121903&r2=121904&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Dec 15 16:21:20 2010
> @@ -49,6 +49,7 @@
>                               unsigned AddrSpace) {
>   assert(Size <= 8 && "Invalid size");
>   unsigned Bits = 8 * Size;
> +  (void)Bits;
>   assert((isUIntN(Bits, Value) || isIntN(Bits, Value)) && "Invalid size");
>   char buf[8];

Or:

assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) && "Invalid size");

Seems less lame.

?

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From evan.cheng at apple.com  Wed Dec 15 16:57:36 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 15 Dec 2010 22:57:36 -0000
Subject: [llvm-commits] [llvm] r121908 -
	/llvm/trunk/lib/Target/X86/X86InstrCompiler.td
Message-ID: <20101215225736.C1DD62A6C12C@llvm.org>

Author: evancheng
Date: Wed Dec 15 16:57:36 2010
New Revision: 121908

URL: http://llvm.org/viewvc/llvm-project?rev=121908&view=rev
Log:
Only rr forms of ADD*_DB are commutable.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=121908&r1=121907&r2=121908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Dec 15 16:57:36 2010
@@ -1038,8 +1038,9 @@
 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
 let AddedComplexity = 5 in { // Try this before the selecting to OR
 
-let isCommutable = 1, isConvertibleToThreeAddress = 1,
+let isConvertibleToThreeAddress = 1,
     Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
+let isCommutable = 1 in {
 def ADD16rr_DB  : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                     "", // orw/addw REG, REG
                     [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
@@ -1049,6 +1050,7 @@
 def ADD64rr_DB  : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
                     "", // orq/addq REG, REG
                     [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
+} // isCommutable
 
 // NOTE: These are order specific, we want the ri8 forms to be listed
 // first so that they are slightly preferred to the ri forms.



From arplynn at gmail.com  Wed Dec 15 17:02:29 2010
From: arplynn at gmail.com (Alistair Lynn)
Date: Wed, 15 Dec 2010 23:02:29 +0000
Subject: [llvm-commits] [llvm] r121905 - in /llvm/trunk:
	lib/Transforms/InstCombine/InstCombineCompares.cpp
	test/Transforms/InstCombine/overflow.ll
In-Reply-To: <20101215223238.CDEC32A6C12C@llvm.org>
References: <20101215223238.CDEC32A6C12C@llvm.org>
Message-ID: <6E381A42-3306-4DDA-83FA-0FA3A9D21462@gmail.com>

Hi Owen-

If these patterns can be matched automatically, would it not be better to do the matching in the DAG combiner and get rid of the intrinsics?

Alistair

On 15 Dec 2010, at 22:32, Owen Anderson wrote:

> Author: resistor
> Date: Wed Dec 15 16:32:38 2010
> New Revision: 121905
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121905&view=rev
> Log:
> Add an InstCombine transform to recognize instances of manual overflow-safe addition
> (performing the addition in a wider type and explicitly checking for overflow), and
> fold them down to intrinsics.  This currently only supports signed-addition, but could
> be generalized if someone works out the magic constant formulas for other operations.
> 
> Fixes <rdar://problem/8558713>.
> 
> Added:
>   llvm/trunk/test/Transforms/InstCombine/overflow.ll
> Modified:
>   llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
> 
> Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=121905&r1=121904&r2=121905&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
> +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed Dec 15 16:32:38 2010
> @@ -1657,6 +1657,71 @@
>  if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
>    Value *A = 0, *B = 0;
> 
> +    // Match the following pattern, which is a common idiom when writing
> +    // overflow-safe integer arithmetic function.  The source performs an
> +    // addition in wider type, and explicitly checks for overflow using
> +    // comparisons against INT_MIN and INT_MAX.  Simplify this by using the
> +    // sadd_with_overflow intrinsic.
> +    // FIXME: This could probably be generalized to handle other overflow-safe
> +    // operations if we worked out the formulas to compute the appropriate 
> +    // magic constants.
> +    // 
> +    // INT64 : a, b, sum = a + b
> +    // if sum < INT32_MIN || sum > INT_MAX then
> +    //   ...
> +    // else
> +    //   ...
> +    {
> +    ConstantInt *CI2;
> +    
> +    // I = icmp ugt (add (add A B) CI2) CI
> +    if (I.getPredicate() == ICmpInst::ICMP_UGT &&
> +        match(Op0, m_Add(m_Add(m_Value(A), m_Value(B)),
> +                   m_ConstantInt(CI2)))) {
> +      const IntegerType *WideType = cast<IntegerType>(CI->getType());
> +      unsigned WideWidth = WideType->getBitWidth();
> +      unsigned NarrowWidth = WideWidth / 2;
> +      const IntegerType *NarrowType =
> +        IntegerType::get(CI->getContext(), NarrowWidth);
> +      
> +      // NarrowAllOnes and NarrowSignBit are the magic constants used to
> +      // perform an overflow check in the wider type: 0x00..00FF..FF and
> +      // 0x00..0010..00 respectively, where the highest set bit in each is
> +      // what would be the sign bit in the narrower type.
> +      ConstantInt *NarrowAllOnes = cast<ConstantInt>(ConstantInt::get(WideType,
> +        APInt::getAllOnesValue(NarrowWidth).zext(WideWidth)));
> +      APInt SignBit(WideWidth, 0);
> +      SignBit.setBit(NarrowWidth-1);
> +      ConstantInt *NarrowSignBit =
> +       cast<ConstantInt>(ConstantInt::get(WideType, SignBit));
> +      
> +      if (CI == NarrowAllOnes && CI2 == NarrowSignBit) {
> +        Module *M = I.getParent()->getParent()->getParent();
> +        
> +        const Type *IntrinsicType = NarrowType;
> +        Value *F = Intrinsic::getDeclaration(M, Intrinsic::sadd_with_overflow,
> +          &IntrinsicType, 1);
> +        
> +        // If the pattern matches, truncate the inputs to the narrower type and
> +        // use the sadd_with_overflow intrinsic to efficiently compute both the
> +        // result and the overflow bit.
> +        Value *TruncA = Builder->CreateTrunc(A, NarrowType, A->getName());
> +        Value *TruncB = Builder->CreateTrunc(B, NarrowType, B->getName());
> +        CallInst *Call = Builder->CreateCall2(F, TruncA, TruncB);
> +        Value *Add = Builder->CreateExtractValue(Call, 0);
> +        Value *ZExt = Builder->CreateZExt(Add, WideType);
> +        
> +        // The inner add was the result of the narrow add, zero extended to the
> +        // wider type.  Replace it with the result computed by the intrinsic.
> +        Instruction *OrigAdd =
> +          cast<Instruction>(cast<Instruction>(I.getOperand(0))->getOperand(0));
> +        OrigAdd->replaceAllUsesWith(ZExt);
> +        
> +        return ExtractValueInst::Create(Call, 1);
> +      }
> +    }
> +    }
> +    
>    // (icmp ne/eq (sub A B) 0) -> (icmp ne/eq A, B)
>    if (I.isEquality() && CI->isZero() &&
>        match(Op0, m_Sub(m_Value(A), m_Value(B)))) {
> 
> Added: llvm/trunk/test/Transforms/InstCombine/overflow.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/overflow.ll?rev=121905&view=auto
> ==============================================================================
> --- llvm/trunk/test/Transforms/InstCombine/overflow.ll (added)
> +++ llvm/trunk/test/Transforms/InstCombine/overflow.ll Wed Dec 15 16:32:38 2010
> @@ -0,0 +1,27 @@
> +; RUN: opt -S -instcombine < %s | FileCheck %s
> +; <rdar://problem/8558713>
> +
> +; CHECK: @test1
> +define i32 @test1(i32 %a, i32 %b) nounwind ssp {
> +entry:
> +; CHECK-NOT: sext
> +  %conv = sext i32 %a to i64
> +  %conv2 = sext i32 %b to i64
> +  %add = add nsw i64 %conv2, %conv
> +  %add.off = add i64 %add, 2147483648
> +; CHECK: llvm.sadd.with.overflow
> +  %0 = icmp ugt i64 %add.off, 4294967295
> +  br i1 %0, label %if.then, label %if.end
> +
> +if.then:
> +  %call = tail call i32 (...)* @throwAnExceptionOrWhatever() nounwind
> +  br label %if.end
> +
> +if.end:
> +; CHECK-NOT: trunc
> +  %conv9 = trunc i64 %add to i32
> +; CHECK: ret i32
> +  ret i32 %conv9
> +}
> +
> +declare i32 @throwAnExceptionOrWhatever(...)
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From matthewbg at google.com  Wed Dec 15 17:05:02 2010
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Wed, 15 Dec 2010 15:05:02 -0800
Subject: [llvm-commits] [llvm] r121904 -
	/llvm/trunk/lib/MC/MCStreamer.cpp
In-Reply-To: <4777796A-FFF8-47DE-8489-0C8DC9435BCA@apple.com>
References: <20101215222120.5B0202A6C12C@llvm.org>
	<4777796A-FFF8-47DE-8489-0C8DC9435BCA@apple.com>
Message-ID: <AANLkTikJ6T+U+_+fWND2sfHsDqVe8tqOFBPDLSBUcUJC@mail.gmail.com>

On Wed, Dec 15, 2010 at 14:57, Eric Christopher <echristo at apple.com> wrote:
>
> On Dec 15, 2010, at 2:21 PM, Matt Beaumont-Gay wrote:
>
> Author: matthewbg
> Date: Wed Dec 15 16:21:20 2010
> New Revision: 121904
>
> URL: http://llvm.org/viewvc/llvm-project?rev=121904&view=rev
> Log:
> Fix opt -Werror build
>
> Modified:
> ???llvm/trunk/lib/MC/MCStreamer.cpp
>
> Modified: llvm/trunk/lib/MC/MCStreamer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=121904&r1=121903&r2=121904&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Dec 15 16:21:20 2010
> @@ -49,6 +49,7 @@
> ??????????????????????????????unsigned AddrSpace) {
> ??assert(Size <= 8 && "Invalid size");
> ??unsigned Bits = 8 * Size;
> + ?(void)Bits;
> ??assert((isUIntN(Bits, Value) || isIntN(Bits, Value)) && "Invalid size");
> ??char buf[8];
>
> Or:
> assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) && "Invalid
> size");
> Seems less lame.

Sounds good to me, patch on the way.

-Matt


From gohman at apple.com  Wed Dec 15 17:09:41 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 23:09:41 -0000
Subject: [llvm-commits] [llvm] r121909 - /llvm/trunk/docs/AliasAnalysis.html
Message-ID: <20101215230941.943EB2A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 17:09:41 2010
New Revision: 121909

URL: http://llvm.org/viewvc/llvm-project?rev=121909&view=rev
Log:
Fix a typo that Bill spotted.

Modified:
    llvm/trunk/docs/AliasAnalysis.html

Modified: llvm/trunk/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=121909&r1=121908&r2=121909&view=diff
==============================================================================
--- llvm/trunk/docs/AliasAnalysis.html (original)
+++ llvm/trunk/docs/AliasAnalysis.html Wed Dec 15 17:09:41 2010
@@ -31,7 +31,7 @@
     <li><a href="#chaining"><tt>AliasAnalysis</tt> chaining behavior</a></li>
     <li><a href="#updating">Updating analysis results for transformations</a></li>
     <li><a href="#implefficiency">Efficiency Issues</a></li>
-    <li><a href="#limitations">Limtations</a></li>
+    <li><a href="#limitations">Limitations</a></li>
     </ul>
   </li>
 



From matthewbg at google.com  Wed Dec 15 17:14:45 2010
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Wed, 15 Dec 2010 23:14:45 -0000
Subject: [llvm-commits] [llvm] r121910 - /llvm/trunk/lib/MC/MCStreamer.cpp
Message-ID: <20101215231445.CEFEC2A6C12C@llvm.org>

Author: matthewbg
Date: Wed Dec 15 17:14:45 2010
New Revision: 121910

URL: http://llvm.org/viewvc/llvm-project?rev=121910&view=rev
Log:
Better fix for opt build

Modified:
    llvm/trunk/lib/MC/MCStreamer.cpp

Modified: llvm/trunk/lib/MC/MCStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=121910&r1=121909&r2=121910&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Dec 15 17:14:45 2010
@@ -48,9 +48,8 @@
 void MCStreamer::EmitIntValue(uint64_t Value, unsigned Size,
                               unsigned AddrSpace) {
   assert(Size <= 8 && "Invalid size");
-  unsigned Bits = 8 * Size;
-  (void)Bits;
-  assert((isUIntN(Bits, Value) || isIntN(Bits, Value)) && "Invalid size");
+  assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) &&
+         "Invalid size");
   char buf[8];
   // FIXME: Endianness assumption.
   for (unsigned i = 0; i != Size; ++i)



From bob.wilson at apple.com  Wed Dec 15 17:16:25 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 15 Dec 2010 23:16:25 -0000
Subject: [llvm-commits] [llvm] r121911 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20101215231625.77CEA2A6C12C@llvm.org>

Author: bwilson
Date: Wed Dec 15 17:16:25 2010
New Revision: 121911

URL: http://llvm.org/viewvc/llvm-project?rev=121911&view=rev
Log:
Teach the Neon intrinsic generator to widen half-precision float types.
This isn't currently used for anything but I ran into it when experimenting
with some changes, and it might be useful in the future.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=121911&r1=121910&r2=121911&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Wed Dec 15 17:16:25 2010
@@ -73,6 +73,8 @@
       return 'i';
     case 'i':
       return 'l';
+    case 'h':
+      return 'f';
     default: throw "unhandled type in widen!";
   }
   return '\0';



From benny.kra at googlemail.com  Wed Dec 15 17:22:43 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 16 Dec 2010 00:22:43 +0100
Subject: [llvm-commits] [llvm] r121905 - in /llvm/trunk:
	lib/Transforms/InstCombine/InstCombineCompares.cpp
	test/Transforms/InstCombine/overflow.ll
In-Reply-To: <20101215223238.CDEC32A6C12C@llvm.org>
References: <20101215223238.CDEC32A6C12C@llvm.org>
Message-ID: <14F4C78C-E068-4BA0-AA72-163161289A63@gmail.com>

Is llvm.sadd.with.overflow implemented on all targets? http://llvm.org/bugs/show_bug.cgi?id=4917#c5 suggests that there are problems with mul+overflow, do we legalize add+overflow intrinsics for targets that don't support them?

On 15.12.2010, at 23:32, Owen Anderson <resistor at mac.com> wrote:

> llvm.sadd.with.overflow

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From resistor at mac.com  Wed Dec 15 17:29:00 2010
From: resistor at mac.com (Owen Anderson)
Date: Wed, 15 Dec 2010 15:29:00 -0800
Subject: [llvm-commits] [llvm] r121905 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineCompares.cpp
 test/Transforms/InstCombine/overflow.ll
In-Reply-To: <14F4C78C-E068-4BA0-AA72-163161289A63@gmail.com>
References: <20101215223238.CDEC32A6C12C@llvm.org>
	<14F4C78C-E068-4BA0-AA72-163161289A63@gmail.com>
Message-ID: <26FF2077-258A-4472-81C7-7FACACB4CD85@mac.com>


On Dec 15, 2010, at 3:22 PM, Benjamin Kramer wrote:

> Is llvm.sadd.with.overflow implemented on all targets? http://llvm.org/bugs/show_bug.cgi?id=4917#c5 suggests that there are problems with mul+overflow, do we legalize add+overflow intrinsics for targets that don't support them?
> 

LegalizeDAG.cpp contains a generic lowering for ISD::SADDO, which is the DAG node that sadd.with.overflow lowers to, so it ought to work on all targets.

--Owen
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From isanbard at gmail.com  Wed Dec 15 17:31:24 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 23:31:24 -0000
Subject: [llvm-commits] [llvm] r121914 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20101215233124.7900A2A6C12C@llvm.org>

Author: void
Date: Wed Dec 15 17:31:24 2010
New Revision: 121914

URL: http://llvm.org/viewvc/llvm-project?rev=121914&view=rev
Log:
Whitespace cleanups.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121914&r1=121913&r2=121914&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Dec 15 17:31:24 2010
@@ -679,8 +679,8 @@
 
 let canFoldAsLoad = 1 in
 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
-                  "ldr", "\t$Rt, $addr",
-                  [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
+                    "ldr", "\t$Rt, $addr",
+                    [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
               T1LdStSP<{1,?,?}> {
   bits<3> Rt;
   bits<8> addr;
@@ -693,7 +693,7 @@
 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
 // FIXME: Pseudo for tLDRspi
 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
-                    "ldr", "\t$dst, $addr", []>,
+                     "ldr", "\t$dst, $addr", []>,
                T1LdStSP<{1,?,?}>;
 
 // Load tconstpool



From isanbard at gmail.com  Wed Dec 15 17:32:27 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 15 Dec 2010 23:32:27 -0000
Subject: [llvm-commits] [llvm] r121915 - in /llvm/trunk/lib/Target/ARM:
 ARMMCCodeEmitter.cpp Thumb1RegisterInfo.cpp
Message-ID: <20101215233227.470E12A6C12C@llvm.org>

Author: void
Date: Wed Dec 15 17:32:27 2010
New Revision: 121915

URL: http://llvm.org/viewvc/llvm-project?rev=121915&view=rev
Log:
If we're changing the frame register to a physical register other than SP, we
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121915&r1=121914&r2=121915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 15 17:32:27 2010
@@ -806,10 +806,9 @@
   // [SP, #imm]
   //   {7-0} = imm8
   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
-#if 0  // FIXME: This crashes2003-05-14-initialize-string.c
   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
          "Unexpected base register!");
-#endif
+
   // The immediate is already shifted for the implicit zeroes, so no change
   // here.
   return MO1.getImm() & 0xff;

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121915&r1=121914&r2=121915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Dec 15 17:32:27 2010
@@ -351,6 +351,20 @@
     MI.RemoveOperand(Op);
 }
 
+/// convertToNonSPOpcode - Change the opcode to the non-SP version, because
+/// we're replacing the frame index with a non-SP register.
+static unsigned convertToNonSPOpcode(unsigned Opcode) {
+  switch (Opcode) {
+  case ARM::tLDRspi:
+    return ARM::tLDRi;
+
+  case ARM::tSTRspi:
+    return ARM::tSTRi;
+  }
+
+  return Opcode;
+}
+
 bool Thumb1RegisterInfo::
 rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
                   unsigned FrameReg, int &Offset,
@@ -452,55 +466,51 @@
     }
     return true;
   } else {
-    unsigned ImmIdx = 0;
-    int InstrOffs = 0;
-    unsigned NumBits = 0;
-    unsigned Scale = 1;
-    switch (AddrMode) {
-    case ARMII::AddrModeT1_s: {
-      ImmIdx = FrameRegIdx+1;
-      InstrOffs = MI.getOperand(ImmIdx).getImm();
-      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
-      Scale = 4;
-      break;
-    }
-    default:
+    if (AddrMode != ARMII::AddrModeT1_s)
       llvm_unreachable("Unsupported addressing mode!");
-      break;
-    }
+
+    unsigned ImmIdx = FrameRegIdx + 1;
+    int InstrOffs = MI.getOperand(ImmIdx).getImm();
+    unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
+    unsigned Scale = 4;
 
     Offset += InstrOffs * Scale;
-    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
+    assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
 
     // Common case: small offset, fits into instruction.
     MachineOperand &ImmOp = MI.getOperand(ImmIdx);
     int ImmedOffset = Offset / Scale;
     unsigned Mask = (1 << NumBits) - 1;
+
     if ((unsigned)Offset <= Mask * Scale) {
-      // Replace the FrameIndex with sp
+      // Replace the FrameIndex with the frame register (e.g., sp).
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       ImmOp.ChangeToImmediate(ImmedOffset);
+
+      // If we're using a register where sp was stored, convert the instruction
+      // to the non-SP version.
+      unsigned NewOpc = convertToNonSPOpcode(Opcode);
+      if (NewOpc != Opcode && FrameReg != ARM::SP)
+        MI.setDesc(TII.get(NewOpc));
+
       return true;
     }
 
-    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
-    if (AddrMode == ARMII::AddrModeT1_s) {
-      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
-      // a different base register.
-      NumBits = 5;
-      Mask = (1 << NumBits) - 1;
-    }
+    NumBits = 5;
+    Mask = (1 << NumBits) - 1;
+
     // If this is a thumb spill / restore, we will be using a constpool load to
     // materialize the offset.
-    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
+    if (Opcode == ARM::tRestore || Opcode == ARM::tSpill) {
       ImmOp.ChangeToImmediate(0);
-    else {
+    } else {
       // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
       ImmedOffset = ImmedOffset & Mask;
       ImmOp.ChangeToImmediate(ImmedOffset);
-      Offset &= ~(Mask*Scale);
+      Offset &= ~(Mask * Scale);
     }
   }
+
   return Offset == 0;
 }
 



From stoklund at 2pi.dk  Wed Dec 15 17:41:23 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 15 Dec 2010 23:41:23 -0000
Subject: [llvm-commits] [llvm] r121917 - in /llvm/trunk:
 include/llvm/CodeGen/MachineLoopRanges.h include/llvm/CodeGen/Passes.h
 include/llvm/InitializePasses.h lib/CodeGen/CMakeLists.txt
 lib/CodeGen/MachineLoopRanges.cpp
Message-ID: <20101215234123.F15EF2A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 17:41:23 2010
New Revision: 121917

URL: http://llvm.org/viewvc/llvm-project?rev=121917&view=rev
Log:
Add MachineLoopRanges analysis.

A MachineLoopRange contains the intervals of slot indexes covered by the blocks
in a loop. This representation of the loop blocks is more efficient to compare
against interfering registers during register coalescing.

Added:
    llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h
    llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp
Modified:
    llvm/trunk/include/llvm/CodeGen/Passes.h
    llvm/trunk/include/llvm/InitializePasses.h
    llvm/trunk/lib/CodeGen/CMakeLists.txt

Added: llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h?rev=121917&view=auto
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h (added)
+++ llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h Wed Dec 15 17:41:23 2010
@@ -0,0 +1,84 @@
+//===- MachineLoopRanges.h - Ranges of machine loops -----------*- c++ -*--===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides the interface to the MachineLoopRanges analysis.
+//
+// Provide on-demand information about the ranges of machine instructions
+// covered by a loop.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINELOOPRANGES_H
+#define LLVM_CODEGEN_MACHINELOOPRANGES_H
+
+#include "llvm/ADT/IntervalMap.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+
+namespace llvm {
+
+class MachineLoop;
+class MachineLoopInfo;
+class raw_ostream;
+
+/// MachineLoopRange - Range information for a single loop.
+class MachineLoopRange {
+  friend class MachineLoopRanges;
+  typedef IntervalMap<SlotIndex, unsigned, 4> RangeMap;
+  typedef RangeMap::Allocator Allocator;
+
+  /// The mapped loop.
+  const MachineLoop *const Loop;
+
+  /// Map intervals to a bit mask.
+  /// Bit 0 = inside loop block.
+  RangeMap Intervals;
+
+  /// Create a MachineLoopRange, only accessible to MachineLoopRanges.
+  MachineLoopRange(const MachineLoop*, Allocator&, SlotIndexes&);
+
+public:
+  /// overlaps - Return true if this loop overlaps the given range of machine
+  /// inteructions.
+  bool overlaps(SlotIndex Start, SlotIndex Stop);
+
+  /// print - Print loop ranges on OS.
+  void print(raw_ostream&) const;
+};
+
+raw_ostream &operator<<(raw_ostream&, const MachineLoopRange&);
+
+/// MachineLoopRanges - Analysis pass that provides on-demand per-loop range
+/// information.
+class MachineLoopRanges : public MachineFunctionPass {
+  typedef DenseMap<const MachineLoop*, MachineLoopRange*> CacheMap;
+  typedef MachineLoopRange::Allocator MapAllocator;
+
+  MapAllocator Allocator;
+  SlotIndexes *Indexes;
+  CacheMap Cache;
+
+public:
+  static char ID; // Pass identification, replacement for typeid
+
+  MachineLoopRanges() : MachineFunctionPass(ID), Indexes(0) {}
+  ~MachineLoopRanges() { releaseMemory(); }
+
+  /// getLoopRange - Return the range of loop.
+  MachineLoopRange *getLoopRange(const MachineLoop *Loop);
+
+private:
+  virtual bool runOnMachineFunction(MachineFunction&);
+  virtual void releaseMemory();
+  virtual void getAnalysisUsage(AnalysisUsage&) const;
+};
+
+
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_MACHINELOOPRANGES_H

Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=121917&r1=121916&r2=121917&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/Passes.h Wed Dec 15 17:41:23 2010
@@ -45,6 +45,11 @@
   ///
   extern char &MachineLoopInfoID;
 
+  /// MachineLoopRanges pass - This pass is an on-demand loop coverage
+  /// analysis pass.
+  ///
+  extern char &MachineLoopRangesID;
+
   /// MachineDominators pass - This pass is a machine dominators analysis pass.
   ///
   extern char &MachineDominatorsID;

Modified: llvm/trunk/include/llvm/InitializePasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=121917&r1=121916&r2=121917&view=diff
==============================================================================
--- llvm/trunk/include/llvm/InitializePasses.h (original)
+++ llvm/trunk/include/llvm/InitializePasses.h Wed Dec 15 17:41:23 2010
@@ -142,6 +142,7 @@
 void initializeMachineDominatorTreePass(PassRegistry&);
 void initializeMachineLICMPass(PassRegistry&);
 void initializeMachineLoopInfoPass(PassRegistry&);
+void initializeMachineLoopRangesPass(PassRegistry&);
 void initializeMachineModuleInfoPass(PassRegistry&);
 void initializeMachineSinkingPass(PassRegistry&);
 void initializeMachineVerifierPassPass(PassRegistry&);

Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=121917&r1=121916&r2=121917&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/trunk/lib/CodeGen/CMakeLists.txt Wed Dec 15 17:41:23 2010
@@ -40,6 +40,7 @@
   MachineInstr.cpp
   MachineLICM.cpp
   MachineLoopInfo.cpp
+  MachineLoopRanges.cpp
   MachineModuleInfo.cpp
   MachineModuleInfoImpls.cpp
   MachinePassRegistry.cpp

Added: llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp?rev=121917&view=auto
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp (added)
+++ llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp Wed Dec 15 17:41:23 2010
@@ -0,0 +1,85 @@
+//===- MachineLoopRanges.cpp - Ranges of machine loops --------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides the implementation of the MachineLoopRanges analysis.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineLoopRanges.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/Passes.h"
+
+using namespace llvm;
+
+char MachineLoopRanges::ID = 0;
+INITIALIZE_PASS_BEGIN(MachineLoopRanges, "machine-loop-ranges",
+                "Machine Loop Ranges", true, true)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_END(MachineLoopRanges, "machine-loop-ranges",
+                "Machine Loop Ranges", true, true)
+
+char &llvm::MachineLoopRangesID = MachineLoopRanges::ID;
+
+void MachineLoopRanges::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.setPreservesAll();
+  AU.addRequiredTransitive<SlotIndexes>();
+  AU.addRequiredTransitive<MachineLoopInfo>();
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+/// runOnMachineFunction - Don't do much, loop ranges are computed on demand.
+bool MachineLoopRanges::runOnMachineFunction(MachineFunction &) {
+  releaseMemory();
+  Indexes = &getAnalysis<SlotIndexes>();
+  return false;
+}
+
+void MachineLoopRanges::releaseMemory() {
+  DeleteContainerSeconds(Cache);
+  Cache.clear();
+}
+
+MachineLoopRange *MachineLoopRanges::getLoopRange(const MachineLoop *Loop) {
+  MachineLoopRange *&Range = Cache[Loop];
+  if (!Range)
+    Range = new MachineLoopRange(Loop, Allocator, *Indexes);
+  return Range;
+}
+
+/// Create a MachineLoopRange, only accessible to MachineLoopRanges.
+MachineLoopRange::MachineLoopRange(const MachineLoop *loop,
+                                   MachineLoopRange::Allocator &alloc,
+                                   SlotIndexes &Indexes)
+  : Loop(loop), Intervals(alloc) {
+  // Compute loop coverage.
+  for (MachineLoop::block_iterator I = Loop->block_begin(),
+         E = Loop->block_end(); I != E; ++I) {
+    const std::pair<SlotIndex, SlotIndex> &Range = Indexes.getMBBRange(*I);
+    Intervals.insert(Range.first, Range.second, 1u);
+  }
+}
+
+/// overlaps - Return true if this loop overlaps the given range of machine
+/// instructions.
+bool MachineLoopRange::overlaps(SlotIndex Start, SlotIndex Stop) {
+  RangeMap::const_iterator I = Intervals.find(Start);
+  return I.valid() && Stop > I.start();
+}
+
+void MachineLoopRange::print(raw_ostream &OS) const {
+  OS << "Loop#" << Loop->getHeader()->getNumber() << " =";
+  for (RangeMap::const_iterator I = Intervals.begin(); I.valid(); ++I)
+    OS << " [" << I.start() << ';' << I.stop() << ')';
+}
+
+raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineLoopRange &MLR) {
+  MLR.print(OS);
+  return OS;
+}



From stoklund at 2pi.dk  Wed Dec 15 17:46:13 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 15 Dec 2010 23:46:13 -0000
Subject: [llvm-commits] [llvm] r121918 - in /llvm/trunk/lib/CodeGen:
 LiveIntervalUnion.cpp RegAllocGreedy.cpp
Message-ID: <20101215234613.5915E2A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 17:46:13 2010
New Revision: 121918

URL: http://llvm.org/viewvc/llvm-project?rev=121918&view=rev
Log:
Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation of
live range splitting around loops guided by register pressure.

So far, trySplit() simply prints a lot of debug output.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=121918&r1=121917&r2=121918&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Wed Dec 15 17:46:13 2010
@@ -83,8 +83,8 @@
 
 void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
                                           const TargetRegisterInfo *TRI) const {
-  OS << '[' << start() << ';' << stop() << ")\t";
-  interference()->print(OS, TRI);
+  OS << '[' << start() << ';' << stop() << "):";
+  TRI->printReg(interference()->reg, OS);
 }
 
 void LiveIntervalUnion::Query::print(raw_ostream &OS,

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121918&r1=121917&r2=121918&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Wed Dec 15 17:46:13 2010
@@ -17,6 +17,7 @@
 #include "LiveIntervalUnion.h"
 #include "RegAllocBase.h"
 #include "Spiller.h"
+#include "SplitKit.h"
 #include "VirtRegMap.h"
 #include "VirtRegRewriter.h"
 #include "llvm/Analysis/AliasAnalysis.h"
@@ -27,6 +28,7 @@
 #include "llvm/CodeGen/LiveStackAnalysis.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineLoopRanges.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
@@ -50,9 +52,11 @@
 
   // analyses
   LiveStacks *LS;
-
+  MachineLoopInfo *Loops;
+  MachineLoopRanges *LoopRanges;
   // state
   std::auto_ptr<Spiller> SpillerInstance;
+  std::auto_ptr<SplitAnalysis> SA;
 
 public:
   RAGreedy();
@@ -106,6 +110,7 @@
   initializeLiveStacksPass(*PassRegistry::getPassRegistry());
   initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
   initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
+  initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
   initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
 }
 
@@ -125,6 +130,8 @@
   AU.addPreservedID(MachineDominatorsID);
   AU.addRequired<MachineLoopInfo>();
   AU.addPreserved<MachineLoopInfo>();
+  AU.addRequired<MachineLoopRanges>();
+  AU.addPreserved<MachineLoopRanges>();
   AU.addRequired<VirtRegMap>();
   AU.addPreserved<VirtRegMap>();
   MachineFunctionPass::getAnalysisUsage(AU);
@@ -256,14 +263,32 @@
 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
                             SmallVectorImpl<LiveInterval*>&SplitVRegs) {
   NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
-  DEBUG({
-    Order.rewind();
-    while (unsigned PhysReg = Order.next()) {
-        query(VirtReg, PhysReg).print(dbgs(), TRI);
-        for (const unsigned *AI = TRI->getAliasSet(PhysReg); *AI; ++AI)
-          query(VirtReg, *AI).print(dbgs(), TRI);
+  SA->analyze(&VirtReg);
+
+  // Get the set of loops that have VirtReg uses and are splittable.
+  SplitAnalysis::LoopPtrSet SplitLoops;
+  SA->getSplitLoops(SplitLoops);
+
+  Order.rewind();
+  while (unsigned PhysReg = Order.next()) {
+    for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
+      LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
+      if (!Q.checkInterference())
+        continue;
+      LiveIntervalUnion::InterferenceResult IR = Q.firstInterference();
+      do {
+        DEBUG({dbgs() << "  "; IR.print(dbgs(), TRI);});
+        for (SplitAnalysis::LoopPtrSet::iterator I = SplitLoops.begin(),
+               E = SplitLoops.end(); I != E; ++I) {
+          MachineLoopRange *Range = LoopRanges->getLoopRange(*I);
+          if (!Range->overlaps(IR.start(), IR.stop()))
+            continue;
+          DEBUG(dbgs() << ", overlaps " << *Range);
+        }
+        DEBUG(dbgs() << '\n');
+      } while (Q.nextInterference(IR));
     }
-  });
+  }
   return 0;
 }
 
@@ -336,9 +361,12 @@
 
   MF = &mf;
   RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
-
   ReservedRegs = TRI->getReservedRegs(*MF);
   SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
+  Loops = &getAnalysis<MachineLoopInfo>();
+  LoopRanges = &getAnalysis<MachineLoopRanges>();
+  SA.reset(new SplitAnalysis(*MF, *LIS, *Loops));
+
   allocatePhysRegs();
   addMBBLiveIns(MF);
 



From echristo at apple.com  Wed Dec 15 17:47:30 2010
From: echristo at apple.com (Eric Christopher)
Date: Wed, 15 Dec 2010 23:47:30 -0000
Subject: [llvm-commits] [llvm] r121919 - in /llvm/trunk:
 lib/Target/ARM/ARMFastISel.cpp lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/fast-isel-static.ll
Message-ID: <20101215234730.35E6C2A6C12C@llvm.org>

Author: echristo
Date: Wed Dec 15 17:47:29 2010
New Revision: 121919

URL: http://llvm.org/viewvc/llvm-project?rev=121919&view=rev
Log:
Don't handle -arm-long-calls in fast isel for now.

Added:
    llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=121919&r1=121918&r2=121919&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Dec 15 17:47:29 2010
@@ -52,6 +52,8 @@
                     cl::desc("Turn off experimental ARM fast-isel support"),
                     cl::init(false), cl::Hidden);
 
+extern cl::opt<bool> EnableARMLongCalls;
+
 namespace {
 
   // All possible address modes, plus some.
@@ -1656,6 +1658,9 @@
   // For now we're using BLX etc on the assumption that we have v5t ops.
   if (!Subtarget->hasV5TOps()) return false;
 
+  // TODO: For now if we have long calls specified we don't handle the call.
+  if (EnableARMLongCalls) return false;
+
   // Set up the argument vectors.
   SmallVector<Value*, 8> Args;
   SmallVector<unsigned, 8> ArgRegs;
@@ -1753,6 +1758,9 @@
   // TODO: Maybe?
   if (!Subtarget->hasV5TOps()) return false;
 
+  // TODO: For now if we have long calls specified we don't handle the call.
+  if (EnableARMLongCalls) return false;
+  
   // Set up the argument vectors.
   SmallVector<Value*, 8> Args;
   SmallVector<unsigned, 8> ArgRegs;

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=121919&r1=121918&r2=121919&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Dec 15 17:47:29 2010
@@ -59,7 +59,7 @@
   cl::desc("Generate tail calls (TEMPORARY OPTION)."),
   cl::init(false));
 
-static cl::opt<bool>
+cl::opt<bool>
 EnableARMLongCalls("arm-long-calls", cl::Hidden,
   cl::desc("Generate calls via indirect call instructions"),
   cl::init(false));

Added: llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll?rev=121919&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll Wed Dec 15 17:47:29 2010
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -relocation-model=static | FileCheck -check-prefix=NORM %s
+
+define void @myadd(float* %sum, float* %addend) nounwind {
+entry:
+  %sum.addr = alloca float*, align 4
+  %addend.addr = alloca float*, align 4
+  store float* %sum, float** %sum.addr, align 4
+  store float* %addend, float** %addend.addr, align 4
+  %tmp = load float** %sum.addr, align 4
+  %tmp1 = load float* %tmp
+  %tmp2 = load float** %addend.addr, align 4
+  %tmp3 = load float* %tmp2
+  %add = fadd float %tmp1, %tmp3
+  %tmp4 = load float** %sum.addr, align 4
+  store float %add, float* %tmp4
+  ret void
+}
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+  %ztot = alloca float, align 4
+  %z = alloca float, align 4
+  store float 0.000000e+00, float* %ztot, align 4
+  store float 1.000000e+00, float* %z, align 4
+; CHECK-LONG: blx     r2
+; CHECK-NORM: blx     _myadd
+  call void @myadd(float* %ztot, float* %z)
+  ret i32 0
+}



From grosbach at apple.com  Wed Dec 15 17:52:36 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 15 Dec 2010 23:52:36 -0000
Subject: [llvm-commits] [llvm] r121920 - in /llvm/trunk:
 lib/Target/ARM/ARMConstantIslandPass.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/Thumb1RegisterInfo.cpp
 test/CodeGen/Thumb/large-stack.ll
Message-ID: <20101215235236.EB98A2A6C12C@llvm.org>

Author: grosbach
Date: Wed Dec 15 17:52:36 2010
New Revision: 121920

URL: http://llvm.org/viewvc/llvm-project?rev=121920&view=rev
Log:
Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/test/CodeGen/Thumb/large-stack.ll

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=121920&r1=121919&r2=121920&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Dec 15 17:52:36 2010
@@ -615,7 +615,6 @@
             break;
 
           case ARM::tLDRpci:
-          case ARM::tLDRcp:
             Bits = 8;
             Scale = 4;  // +(offset_8*4)
             break;

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=121920&r1=121919&r2=121920&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Dec 15 17:52:36 2010
@@ -2187,7 +2187,7 @@
         SDValue Pred = getAL(CurDAG);
         SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
         SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
-        ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
+        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
                                          Ops, 4);
       } else {
         SDValue Ops[] = {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121920&r1=121919&r2=121920&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Dec 15 17:52:36 2010
@@ -710,19 +710,6 @@
   let Inst{7-0}  = addr;
 }
 
-// Special LDR for loads from non-pc-relative constpools.
-let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
-    isReMaterializable = 1 in
-def tLDRcp  : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
-                  "ldr", "\t$Rt, $addr", []>,
-              T1LdStSP<{1,?,?}> {
-  // A6.2 & A8.6.57 T2
-  bits<3> Rt;
-  bits<8> addr;
-  let Inst{10-8} = Rt;
-  let Inst{7-0}  = addr;
-}
-
 // A8.6.194 & A8.6.192
 defm tSTR  : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
                                 t_addrmode_is4, AddrModeT1_4,

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121920&r1=121919&r2=121920&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Dec 15 17:52:36 2010
@@ -63,7 +63,7 @@
           Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
 
-  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
+  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
           .addReg(DestReg, getDefRegState(true), SubIdx)
           .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
 }

Modified: llvm/trunk/test/CodeGen/Thumb/large-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=121920&r1=121919&r2=121920&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/large-stack.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/large-stack.ll Wed Dec 15 17:52:36 2010
@@ -10,7 +10,7 @@
 
 define void @test2() {
 ; CHECK: test2:
-; CHECK: ldr r0, LCPI
+; CHECK: ldr.n r0, LCPI
 ; CHECK: add sp, r0
 ; CHECK: subs r4, r7, #4
 ; CHECK: mov sp, r4
@@ -20,9 +20,9 @@
 
 define i32 @test3() {
 ; CHECK: test3:
-; CHECK: ldr r2, LCPI
+; CHECK: ldr.n r2, LCPI
 ; CHECK: add sp, r2
-; CHECK: ldr r1, LCPI
+; CHECK: ldr.n r1, LCPI
 ; CHECK: add r1, sp
 ; CHECK: subs r4, r7, #4
 ; CHECK: mov sp, r4



From gohman at apple.com  Wed Dec 15 17:53:55 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 23:53:55 -0000
Subject: [llvm-commits] [llvm] r121921 - in /llvm/trunk:
 lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/preserve-tbaa.ll
Message-ID: <20101215235356.09A5D2A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 17:53:55 2010
New Revision: 121921

URL: http://llvm.org/viewvc/llvm-project?rev=121921&view=rev
Log:
Preserve TBAA tags when doing load PRE.

Added:
    llvm/trunk/test/Transforms/GVN/preserve-tbaa.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=121921&r1=121920&r2=121921&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Dec 15 17:53:55 2010
@@ -22,6 +22,7 @@
 #include "llvm/GlobalVariable.h"
 #include "llvm/Function.h"
 #include "llvm/IntrinsicInst.h"
+#include "llvm/LLVMContext.h"
 #include "llvm/Operator.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/ConstantFolding.h"
@@ -1659,9 +1660,13 @@
     BasicBlock *UnavailablePred = I->first;
     Value *LoadPtr = I->second;
 
-    Value *NewLoad = new LoadInst(LoadPtr, LI->getName()+".pre", false,
-                                  LI->getAlignment(),
-                                  UnavailablePred->getTerminator());
+    Instruction *NewLoad = new LoadInst(LoadPtr, LI->getName()+".pre", false,
+                                        LI->getAlignment(),
+                                        UnavailablePred->getTerminator());
+
+    // Transfer the old load's TBAA tag to the new load.
+    if (MDNode *Tag = LI->getMetadata(LLVMContext::MD_tbaa))
+      NewLoad->setMetadata(LLVMContext::MD_tbaa, Tag);
 
     // Add the newly created load.
     ValuesPerBlock.push_back(AvailableValueInBlock::get(UnavailablePred,

Added: llvm/trunk/test/Transforms/GVN/preserve-tbaa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/preserve-tbaa.ll?rev=121921&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GVN/preserve-tbaa.ll (added)
+++ llvm/trunk/test/Transforms/GVN/preserve-tbaa.ll Wed Dec 15 17:53:55 2010
@@ -0,0 +1,28 @@
+; RUN: opt -tbaa -basicaa -gvn -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64"
+
+; GVN should preserve the TBAA tag on loads when doing PRE.
+
+; CHECK: @test
+; CHECK: %tmp33.pre = load i16* undef, align 2, !tbaa !0
+; CHECK: br label %for.body
+define void @test() nounwind {
+entry:
+  br i1 undef, label %bb.nph, label %for.end
+
+bb.nph:                                           ; preds = %entry
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %bb.nph
+  %tmp33 = load i16* undef, align 2, !tbaa !0
+  store i16 undef, i16* undef, align 2, !tbaa !0
+  br i1 false, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+!0 = metadata !{metadata !"short", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}



From gohman at apple.com  Wed Dec 15 17:58:44 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 15 Dec 2010 23:58:44 -0000
Subject: [llvm-commits] [llvm] r121923 -
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
Message-ID: <20101215235844.648772A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 17:58:44 2010
New Revision: 121923

URL: http://llvm.org/viewvc/llvm-project?rev=121923&view=rev
Log:
Enable TBAA by default.

Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=121923&r1=121922&r2=121923&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Wed Dec 15 17:58:44 2010
@@ -67,7 +67,7 @@
 using namespace llvm;
 
 // For testing purposes, enable TBAA only via a special option.
-static cl::opt<bool> EnableTBAA("enable-tbaa", cl::init(false));
+static cl::opt<bool> EnableTBAA("enable-tbaa", cl::init(true));
 
 namespace {
   /// TBAANode - This is a simple wrapper around an MDNode which provides a



From aggarwa4 at illinois.edu  Wed Dec 15 18:01:37 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 16 Dec 2010 00:01:37 -0000
Subject: [llvm-commits] [poolalloc] r121925 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20101216000137.C79882A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Dec 15 18:01:37 2010
New Revision: 121925

URL: http://llvm.org/viewvc/llvm-project?rev=121925&view=rev
Log:
Add an option to turn off folding of nodes in 
StdLib. This could allow us to test these changes.

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=121925&r1=121924&r2=121925&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Wed Dec 15 18:01:37 2010
@@ -29,10 +29,17 @@
 
 static RegisterPass<StdLibDataStructures>
 X("dsa-stdlib", "Standard Library Local Data Structure Analysis");
+STATISTIC(NumNodesFoldedInStdLib,    "Number of nodes folded in std lib");
 
 char StdLibDataStructures::ID;
 
 #define numOps 10
+namespace {
+  static cl::opt<bool> noStdLibFold("dsa-stdlib-no-fold",
+         cl::desc("Don't fold nodes in std-lib."),
+         cl::Hidden,
+         cl::init(false));
+}
 
 //
 // Structure: libAction
@@ -398,13 +405,19 @@
               // Collapse (fold) the DSNode of the return value and the actual
               // arguments if directed to do so.
               //
-              if (recFuncs[x].action.collapse) {
-                if (isa<PointerType>(CI->getType()))
+              if (!noStdLibFold && recFuncs[x].action.collapse) {
+                if (isa<PointerType>(CI->getType())){
                   Graph->getNodeForValue(CI).getNode()->foldNodeCompletely();
-                for (unsigned y = 1; y < CI->getNumOperands(); ++y)
-                  if (isa<PointerType>(CI->getOperand(y)->getType()))
-                    if (DSNode * Node=Graph->getNodeForValue(CI->getOperand(y)).getNode())
+                  NumNodesFoldedInStdLib++;
+                }
+                for (unsigned y = 1; y < CI->getNumOperands(); ++y){
+                  if (isa<PointerType>(CI->getOperand(y)->getType())){
+                    if (DSNode * Node=Graph->getNodeForValue(CI->getOperand(y)).getNode()){
                       Node->foldNodeCompletely();
+                      NumNodesFoldedInStdLib++;
+                    }
+                  }
+                }
               }
             }
           } else if(ConstantExpr *CE = dyn_cast<ConstantExpr>(ii)) {
@@ -464,13 +477,18 @@
                       // Collapse (fold) the DSNode of the return value and the actual
                       // arguments if directed to do so.
                       //
-                      if (recFuncs[x].action.collapse) {
-                        if (isa<PointerType>(CI->getType()))
+                      if (!noStdLibFold && recFuncs[x].action.collapse) {
+                        if (isa<PointerType>(CI->getType())){
                           Graph->getNodeForValue(CI).getNode()->foldNodeCompletely();
+                          NumNodesFoldedInStdLib++;
+                        }
                         for (unsigned y = 1; y < CI->getNumOperands(); ++y)
-                          if (isa<PointerType>(CI->getOperand(y)->getType()))
-                            if (DSNode * Node=Graph->getNodeForValue(CI->getOperand(y)).getNode())
+                          if (isa<PointerType>(CI->getOperand(y)->getType())){
+                            if (DSNode * Node=Graph->getNodeForValue(CI->getOperand(y)).getNode()){
                               Node->foldNodeCompletely();
+                              NumNodesFoldedInStdLib++;
+                            }
+                          }
                       }
                   }
                 }



From aggarwa4 at illinois.edu  Wed Dec 15 18:03:04 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 16 Dec 2010 00:03:04 -0000
Subject: [llvm-commits] [poolalloc] r121926 -
	/poolalloc/trunk/lib/DSA/DSGraph.cpp
Message-ID: <20101216000304.899F32A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Dec 15 18:03:04 2010
New Revision: 121926

URL: http://llvm.org/viewvc/llvm-project?rev=121926&view=rev
Log:
This works as well. Because, we have already 
checked that it V is a pointer value. 

Modified:
    poolalloc/trunk/lib/DSA/DSGraph.cpp

Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=121926&r1=121925&r2=121926&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSGraph.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSGraph.cpp Wed Dec 15 18:03:04 2010
@@ -69,7 +69,7 @@
   // Undef values, even ones of pointer type, don't get nodes.
   if (isa<UndefValue>(V)) return false;
 
-  if (isa<Constant>(V) && cast<Constant>(V)->isNullValue())
+  if (isa<ConstantPointerNull>(V))
     return false;
 
   // Use the Aliasee of GlobalAliases



From jason.w.kim.2009 at gmail.com  Wed Dec 15 18:15:10 2010
From: jason.w.kim.2009 at gmail.com (Jason W Kim)
Date: Thu, 16 Dec 2010 00:15:10 -0000
Subject: [llvm-commits] [llvm] r121927 - /llvm/trunk/test/Scripts/elf-dump
Message-ID: <20101216001510.B37E42A6C12C@llvm.org>

Author: jasonwkim
Date: Wed Dec 15 18:15:10 2010
New Revision: 121927

URL: http://llvm.org/viewvc/llvm-project?rev=121927&view=rev
Log:
Fix elf-dump --dump-section-data for .bss section

Modified:
    llvm/trunk/test/Scripts/elf-dump

Modified: llvm/trunk/test/Scripts/elf-dump
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/elf-dump?rev=121927&r1=121926&r2=121927&view=diff
==============================================================================
--- llvm/trunk/test/Scripts/elf-dump (original)
+++ llvm/trunk/test/Scripts/elf-dump Wed Dec 15 18:15:10 2010
@@ -97,8 +97,11 @@
             print "   ])"
         elif dumpdata:
             f.seek(self.sh_offset)
-            data = f.read(self.sh_size)
-            print "   ('_section_data', '%s')" % common_dump.dataToHex(data)
+            if self.sh_type != 8: # != SHT_NOBITS
+                data = f.read(self.sh_size)
+                print "   ('_section_data', '%s')" % common_dump.dataToHex(data)
+            else:
+                print "   ('_section_data', '')" 
         print "  ),"
 
 def dumpSymtab(f, section, strtab):



From isanbard at gmail.com  Wed Dec 15 18:38:41 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 16 Dec 2010 00:38:41 -0000
Subject: [llvm-commits] [llvm] r121929 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Message-ID: <20101216003841.C6ABE2A6C12C@llvm.org>

Author: void
Date: Wed Dec 15 18:38:41 2010
New Revision: 121929

URL: http://llvm.org/viewvc/llvm-project?rev=121929&view=rev
Log:
Add encodings for Thumb1 Spill and Restore pseudos.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121929&r1=121928&r2=121929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Dec 15 18:38:41 2010
@@ -694,7 +694,12 @@
 // FIXME: Pseudo for tLDRspi
 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
                      "ldr", "\t$dst, $addr", []>,
-               T1LdStSP<{1,?,?}>;
+               T1LdStSP<{1,?,?}> {
+  bits<3> Rt;
+  bits<8> addr;
+  let Inst{10-8} = Rt;
+  let Inst{7-0} = addr;
+}
 
 // Load tconstpool
 // FIXME: Use ldr.n to work around a Darwin assembler bug.
@@ -745,7 +750,12 @@
 // FIXME: Pseudo for tSTRspi
 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
                   "str", "\t$src, $addr", []>,
-             T1LdStSP<{0,?,?}>;
+             T1LdStSP<{0,?,?}> {
+  bits<3> Rt;
+  bits<8> addr;
+  let Inst{10-8} = Rt;
+  let Inst{7-0} = addr;
+}
 
 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.



From jasonwkim at google.com  Wed Dec 15 18:43:05 2010
From: jasonwkim at google.com (Jason Kim)
Date: Wed, 15 Dec 2010 16:43:05 -0800
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <nnglj3qlp24.fsf@royale.us.cray.com>
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	<nngy67sm3r7.fsf@royale.us.cray.com>
	<AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
	<nnglj3qlp24.fsf@royale.us.cray.com>
Message-ID: <AANLkTinJBBU4eY=ixfL1x7JF6v7ea6HNcLUGX4iEw3XY@mail.gmail.com>

On Wed, Dec 15, 2010 at 1:10 PM, David A. Greene <greened at obbligato.org> wrote:
> Jason Kim <jasonwkim at google.com> writes:
>
>> Hi David.
>>
>> Feedback below:
>
> Thanks!
>
>> 1. Please have one canonical list of executables (including things
>> like (elf/macho/coff)-dump that are used by test/ and prepend the
>> exact path to all of them, as having 3 sets of basically the same data
>> is not likely to be well received. Can you perhaps use word boundary
>> as a pattern check? (if you have to import re, so be it.)
>
> Ok.
>
>> 2. Add verbose comment to lit.cfg and TestRunner.py
>
> Ok. ?What kind of comment would you like to see? ?I'll add something
> about why we're doing the substitutions. ?Anything else?

That should be good enough :-)

>
>> 5. File a doc bug to remind the core developers about this change (or
>> patch the doc directly?) You can do this separately.
>
> I'll do it at the same time. ?It makes sense to keep it together.

Great!
Thanks!

-jason

>
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?-Dave
>


From isanbard at gmail.com  Wed Dec 15 18:49:54 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 16 Dec 2010 00:49:54 -0000
Subject: [llvm-commits] [llvm] r121931 -
	/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
Message-ID: <20101216004954.DD5462A6C12C@llvm.org>

Author: void
Date: Wed Dec 15 18:49:54 2010
New Revision: 121931

URL: http://llvm.org/viewvc/llvm-project?rev=121931&view=rev
Log:
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=121931&r1=121930&r2=121931&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Dec 15 18:49:54 2010
@@ -356,9 +356,11 @@
 static unsigned convertToNonSPOpcode(unsigned Opcode) {
   switch (Opcode) {
   case ARM::tLDRspi:
+  case ARM::tRestore:           // FIXME: Should this opcode be here?
     return ARM::tLDRi;
 
   case ARM::tSTRspi:
+  case ARM::tSpill:             // FIXME: Should this opcode be here?
     return ARM::tSTRi;
   }
 



From isanbard at gmail.com  Wed Dec 15 18:50:34 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 16 Dec 2010 00:50:34 -0000
Subject: [llvm-commits] [llvm] r121932 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmBackend.cpp ARMFixupKinds.h ARMMCCodeEmitter.cpp
Message-ID: <20101216005034.277D82A6C12C@llvm.org>

Author: void
Date: Wed Dec 15 18:50:33 2010
New Revision: 121932

URL: http://llvm.org/viewvc/llvm-project?rev=121932&view=rev
Log:
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
it. I.e., it was always an immediate value.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121932&r1=121931&r2=121932&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Dec 15 18:50:33 2010
@@ -237,9 +237,6 @@
     // 'off by 4' is implicitly handled by the half-word ordering of the
     // Thumb encoding, so we only need to adjust by 2 here.
     return ((Value - 2) >> 2) & 0xff;
-  case ARM::fixup_arm_thumb_ldst:
-    // Offset by 4.
-    return ((Value - 4) & 0x1f) << 6;
   case ARM::fixup_arm_thumb_cb: {
     // Offset by 4 and don't encode the lower bit, which is always 0.
     uint32_t Binary = (Value - 4) >> 1;
@@ -368,7 +365,6 @@
 
   case ARM::fixup_arm_thumb_br:
   case ARM::fixup_arm_thumb_cb:
-  case ARM::fixup_arm_thumb_ldst:
     return 2;
 
   case ARM::fixup_arm_ldst_pcrel_12:

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121932&r1=121931&r2=121932&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Wed Dec 15 18:50:33 2010
@@ -65,9 +65,6 @@
   // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
   fixup_arm_thumb_cp,
 
-  // fixup_arm_thumb_ldst - Fixup for Thumb load/store instrs.
-  fixup_arm_thumb_ldst,
-
   // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
   fixup_arm_thumb_bcc,
 

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121932&r1=121931&r2=121932&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 15 18:50:33 2010
@@ -68,7 +68,6 @@
 { "fixup_arm_thumb_blx",     7,            21,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cb",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_cp",      1,             8,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_ldst",    1,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_thumb_bcc",     1,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_movt_hi16",     0,            16,  0 },
 { "fixup_arm_movw_lo16",     0,            16,  0 },
@@ -824,16 +823,7 @@
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
   unsigned Rn = getARMRegisterNumbering(MO.getReg());
-  unsigned Imm5 = 0;
-
-  if (MO1.isExpr()) {
-    const MCExpr *Expr = MO.getExpr();
-    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_ldst);
-    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
-  } else {
-    Imm5 = MO1.getImm();
-  }
-
+  unsigned Imm5 = Imm5 = MO1.getImm();
   return ((Imm5 & 0x1f) << 3) | Rn;
 }
 



From stoklund at 2pi.dk  Wed Dec 15 19:18:29 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 16 Dec 2010 01:18:29 -0000
Subject: [llvm-commits] [llvm] r121935 -
	/llvm/trunk/include/llvm/ADT/IntervalMap.h
Message-ID: <20101216011829.40C792A6C12C@llvm.org>

Author: stoklund
Date: Wed Dec 15 19:18:29 2010
New Revision: 121935

URL: http://llvm.org/viewvc/llvm-project?rev=121935&view=rev
Log:
Add IntervalMapOverlaps - An iterator for overlapping intervals in two
IntervalMaps.

The IntervalMaps can have different template parameters, but the KeyT and Traits
types must be the same.

Tests are forthcoming.

Modified:
    llvm/trunk/include/llvm/ADT/IntervalMap.h

Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntervalMap.h?rev=121935&r1=121934&r2=121935&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/IntervalMap.h (original)
+++ llvm/trunk/include/llvm/ADT/IntervalMap.h Wed Dec 15 19:18:29 2010
@@ -940,6 +940,7 @@
 
 public:
   typedef typename Sizer::Allocator Allocator;
+  typedef Traits KeyTraits;
 
 private:
   // The root data is either a RootLeaf or a RootBranchData instance.
@@ -2006,6 +2007,96 @@
   return SplitRoot;
 }
 
+//===----------------------------------------------------------------------===//
+//---                       IntervalMapOverlaps                           ----//
+//===----------------------------------------------------------------------===//
+
+/// IntervalMapOverlaps - Iterate over the overlaps of mapped intervals in two
+/// IntervalMaps. The maps may be different, but the KeyT and Traits types
+/// should be the same.
+///
+/// Typical uses:
+///
+/// 1. Test for overlap:
+///    bool overlap = IntervalMapOverlaps(a, b).valid();
+///
+/// 2. Enumerate overlaps:
+///    for (IntervalMapOverlaps I(a, b); I.valid() ; ++I) { ... }
+///
+template <typename MapA, typename MapB>
+class IntervalMapOverlaps {
+  typedef typename MapA::KeyTraits Traits;
+  typename MapA::const_iterator posA;
+  typename MapB::const_iterator posB;
+
+  /// advance - Move posA and posB forward until reaching an overlap, or until
+  /// either meets end.
+  /// Don't move the iterators if they are already overlapping.
+  void advance() {
+    for (;;) {
+      // Make a.end > b.start.
+      posA.advanceTo(posB.start());
+      if (!posA.valid() || !Traits::stopLess(posB.end(), posA.start()))
+        return;
+      // Make b.end > a.start.
+      posB.advanceTo(posA.start());
+      if (!posB.valid() || !Traits::stopLess(posA.end(), posB.start()))
+        return;
+    }
+  }
+
+public:
+  /// IntervalMapOverlaps - Create an iterator for the overlaps of a and b.
+  IntervalMapOverlaps(const MapA &a, const MapB &b)
+    : posA(b.empty() ? a.end() : a.find(b.start())),
+      posB(posA.valid() ? b.find(posA.start()) : b.end()) {
+    if (valid())
+      advance();
+  }
+
+  /// valid - Return true if iterator is at an overlap.
+  bool valid() const {
+    return posA.valid() && posB.valid();
+  }
+
+  /// a - access the left hand side in the overlap.
+  const typename MapA::const_iterator &a() const { return posA; }
+
+  /// b - access the right hand side in the overlap.
+  const typename MapB::const_iterator &b() const { return posB; }
+
+  /// skipA - Move to the next overlap that doesn't involve a().
+  void skipA() {
+    ++posA;
+    if (!posA.valid() || !Traits::stopLess(posB.end(), posA.start()))
+      return;
+    // Second half-loop of advance().
+    posB.advanceTo(posA.start());
+    if (!posB.valid() || !Traits::stopLess(posA.end(), posB.start()))
+      return ;
+    advance();
+  }
+
+  /// skipB - Move to the next overlap that doesn't involve b().
+  void skipB() {
+    ++posB;
+    if (!posB.valid() || !Traits::stopLess(posA.end(), posB.start()))
+        return;
+    advance();
+  }
+
+  /// Preincrement - Move to the next overlap.
+  IntervalMapOverlaps &operator++() {
+    // Bump the iterator that ends first. The other one may have more overlaps.
+    if (Traits::startLess(posB.end(), posA.end()))
+      skipB();
+    else
+      skipA();
+    return *this;
+  }
+};
+
+
 } // namespace llvm
 
 #endif



From matthewbg at google.com  Wed Dec 15 19:34:27 2010
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Thu, 16 Dec 2010 01:34:27 -0000
Subject: [llvm-commits] [llvm] r121939 -
	/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
Message-ID: <20101216013427.283D72A6C12C@llvm.org>

Author: matthewbg
Date: Wed Dec 15 19:34:26 2010
New Revision: 121939

URL: http://llvm.org/viewvc/llvm-project?rev=121939&view=rev
Log:
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
(see PR4579).


Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121939&r1=121938&r2=121939&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 15 19:34:26 2010
@@ -823,7 +823,7 @@
   const MCOperand &MO = MI.getOperand(OpIdx);
   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
   unsigned Rn = getARMRegisterNumbering(MO.getReg());
-  unsigned Imm5 = Imm5 = MO1.getImm();
+  unsigned Imm5 = MO1.getImm();
   return ((Imm5 & 0x1f) << 3) | Rn;
 }
 



From geek4civic at gmail.com  Wed Dec 15 19:48:16 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 16 Dec 2010 01:48:16 -0000
Subject: [llvm-commits] [llvm] r121942 - /llvm/trunk/lib/Support/regexec.c
Message-ID: <20101216014816.0CFF52A6C12C@llvm.org>

Author: chapuni
Date: Wed Dec 15 19:48:15 2010
New Revision: 121942

URL: http://llvm.org/viewvc/llvm-project?rev=121942&view=rev
Log:
lib/Support/regexec.c: Let Regex LLP64-aware.

On LLP64 Win64, 'states1' (for small version) was expanded to 'char *' for large version. Thus small version would be mischosen when nstates > 32 regardless of sizeof(long) on Win64.

Modified:
    llvm/trunk/lib/Support/regexec.c

Modified: llvm/trunk/lib/Support/regexec.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/regexec.c?rev=121942&r1=121941&r2=121942&view=diff
==============================================================================
--- llvm/trunk/lib/Support/regexec.c (original)
+++ llvm/trunk/lib/Support/regexec.c Wed Dec 15 19:48:15 2010
@@ -54,8 +54,9 @@
 #include "regex2.h"
 
 /* macros for manipulating states, small version */
-#define	states	long
-#define	states1	states		/* for later use in llvm_regexec() decision */
+/* FIXME: 'states' is assumed as 'long' on small version. */
+#define	states1	long		/* for later use in llvm_regexec() decision */
+#define	states	states1
 #define	CLEAR(v)	((v) = 0)
 #define	SET0(v, n)	((v) &= ~((unsigned long)1 << (n)))
 #define	SET1(v, n)	((v) |= (unsigned long)1 << (n))



From geek4civic at gmail.com  Wed Dec 15 20:26:42 2010
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 16 Dec 2010 11:26:42 +0900
Subject: [llvm-commits] [Review request][Win64] Improve allocating
	shadow area
In-Reply-To: <AANLkTikiPKTWtkgdmU3i80eqcimmNn6M=KeHj6k4dhaY@mail.gmail.com>
References: <AANLkTikiPKTWtkgdmU3i80eqcimmNn6M=KeHj6k4dhaY@mail.gmail.com>
Message-ID: <AANLkTik+s4si01Vr1t-=t8jjkR_OAJPd_d811KZx9VuC@mail.gmail.com>

Good morning!

An additional patch(0002). Shadow area would not be allocated
explicitly by prologue any more.

...Takumi
-------------- next part --------------
From d0f65d20714f484ead070aa98f0a4b3c7cc77b0a Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi <geek4civic at gmail.com>
Date: Mon, 13 Dec 2010 17:59:20 +0900
Subject: [PATCH 1/2] Target/X86: Allocate Win64's shadow allocation, on stack, when callee requires one.

In leaf functions, shadow area would not be allocated any more.
---
 lib/Target/X86/X86FrameInfo.cpp                    |    5 -----
 lib/Target/X86/X86ISelLowering.cpp                 |    8 ++++++--
 test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll |    4 ++--
 test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll       |    9 ++++-----
 test/CodeGen/X86/win64_params.ll                   |    4 ++--
 test/CodeGen/X86/win64_vararg.ll                   |   10 +++++-----
 6 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/lib/Target/X86/X86FrameInfo.cpp b/lib/Target/X86/X86FrameInfo.cpp
index c47b0fa..3733f6c 100644
--- a/lib/Target/X86/X86FrameInfo.cpp
+++ b/lib/Target/X86/X86FrameInfo.cpp
@@ -325,11 +325,6 @@ void X86FrameInfo::emitPrologue(MachineFunction &MF) const {
     if (HasFP) MinSize += SlotSize;
     StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
     MFI->setStackSize(StackSize);
-  } else if (IsWin64) {
-    // We need to always allocate 32 bytes as register spill area.
-    // FIXME: We might reuse these 32 bytes for leaf functions.
-    StackSize += 32;
-    MFI->setStackSize(StackSize);
   }
 
   // Insert stack pointer adjustment for later moving of return addr.  Only
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 045bb93..fd93462 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1807,8 +1807,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
                                     DebugLoc dl, SelectionDAG &DAG,
                                     const CCValAssign &VA,
                                     ISD::ArgFlagsTy Flags) const {
-  const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
-  unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
+  unsigned LocMemOffset = VA.getLocMemOffset();
   SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
   PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
   if (Flags.isByVal())
@@ -1892,6 +1891,11 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
                  ArgLocs, *DAG.getContext());
+
+  // Win64 CC requires at least 4 x 64bit of shadow allocation.
+  if (Subtarget->isTargetWin64())
+    CCInfo.AllocateStack(32, 16);
+
   CCInfo.AnalyzeCallOperands(Outs, CC_X86);
 
   // Get a count of how many bytes are to be pushed on the stack.
diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
index c598228..0413044 100644
--- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
+++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp"
-target triple = "x86_64-pc-mingw64"
+; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s
+; CHECK: subq $8, %rsp
 
 define x86_fp80 @a(i64 %x) nounwind readnone {
 entry:
diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
index 810a6f4..9833d96 100644
--- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
+++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
@@ -1,8 +1,7 @@
-; RUN: llc < %s -o %t1
-; RUN: grep "subq.*\\\$72, \\\%rsp" %t1
-; RUN: grep "movaps	\\\%xmm8, 32\\\(\\\%rsp\\\)" %t1
-; RUN: grep "movaps	\\\%xmm7, 48\\\(\\\%rsp\\\)" %t1
-target triple = "x86_64-pc-mingw64"
+; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s
+; CHECK: subq    $40, %rsp
+; CHECK: movaps  %xmm8, (%rsp)
+; CHECK: movaps  %xmm7, 16(%rsp)
 
 define i32 @a() nounwind {
 entry:
diff --git a/test/CodeGen/X86/win64_params.ll b/test/CodeGen/X86/win64_params.ll
index 0b67368..f9d4bf9 100644
--- a/test/CodeGen/X86/win64_params.ll
+++ b/test/CodeGen/X86/win64_params.ll
@@ -4,8 +4,8 @@
 ; on the stack.
 define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
 entry:
-; CHECK: movl    80(%rsp), %eax
-; CHECK: addl    72(%rsp), %eax
+; CHECK: movl    48(%rsp), %eax
+; CHECK: addl    40(%rsp), %eax
   %add = add nsw i32 %p6, %p5
   ret i32 %add
 }
diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll
index 072f36a..aa7d786 100644
--- a/test/CodeGen/X86/win64_vararg.ll
+++ b/test/CodeGen/X86/win64_vararg.ll
@@ -5,11 +5,11 @@
 ; calculated.
 define void @average_va(i32 %count, ...) nounwind {
 entry:
-; CHECK: subq	$40, %rsp
-; CHECK: movq	%r9, 72(%rsp)
-; CHECK: movq	%r8, 64(%rsp)
-; CHECK: movq	%rdx, 56(%rsp)
-; CHECK: leaq	56(%rsp), %rax
+; CHECK: subq	$8, %rsp
+; CHECK: movq	%r9, 40(%rsp)
+; CHECK: movq	%r8, 32(%rsp)
+; CHECK: movq	%rdx, 24(%rsp)
+; CHECK: leaq	24(%rsp), %rax
 
   %ap = alloca i8*, align 8                       ; <i8**> [#uses=1]
   %ap1 = bitcast i8** %ap to i8*                  ; <i8*> [#uses=1]
-- 
1.7.1.GIT
-------------- next part --------------
From 55c46a76c00afbe3c8a9cfcfb59060f5688314c9 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi <geek4civic at gmail.com>
Date: Tue, 14 Dec 2010 14:59:04 +0900
Subject: [PATCH 2/2] Target/X86: Remove stack frame allocation "-40" for Win64. X86TargetLowering::LowerFormalArguments() does it.

---
 lib/Target/X86/X86FrameInfo.h      |    2 +-
 lib/Target/X86/X86ISelLowering.cpp |    5 +++++
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/lib/Target/X86/X86FrameInfo.h b/lib/Target/X86/X86FrameInfo.h
index fbbde92..6ac2a3a 100644
--- a/lib/Target/X86/X86FrameInfo.h
+++ b/lib/Target/X86/X86FrameInfo.h
@@ -28,7 +28,7 @@ public:
   explicit X86FrameInfo(const X86TargetMachine &tm, const X86Subtarget &sti)
     : TargetFrameInfo(StackGrowsDown,
                       sti.getStackAlignment(),
-                      (sti.isTargetWin64() ? -40 : (sti.is64Bit() ? -8 : -4))),
+                      (sti.is64Bit() ? -8 : -4)),
       TM(tm), STI(sti) {
   }
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index fd93462..0e40ca1 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1573,6 +1573,11 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
                  ArgLocs, *DAG.getContext());
+
+  // Win64 CC requires at least 4 x i64 of shadow allocation.
+  if (IsWin64)
+    CCInfo.AllocateStack(32, 16);
+
   CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
 
   unsigned LastVal = ~0U;
-- 
1.7.1.GIT

From bigcheesegs at gmail.com  Wed Dec 15 20:48:10 2010
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Wed, 15 Dec 2010 21:48:10 -0500
Subject: [llvm-commits] [PATCH] Object File Library
In-Reply-To: <AANLkTiniaynBbj3eV6At0MFApAyFuYgX2CNkfXBrFq=o@mail.gmail.com>
References: <AANLkTim2J+DTfFnTem61FYcdQW9pWuiwwT4vDnKciNKB@mail.gmail.com>
	<AANLkTiniaynBbj3eV6At0MFApAyFuYgX2CNkfXBrFq=o@mail.gmail.com>
Message-ID: <AANLkTin+5qqdfa3yaCC1yhYm57XUSN4o+bO656sC-84j@mail.gmail.com>

On Mon, Nov 22, 2010 at 8:00 PM, Michael Spencer <bigcheesegs at gmail.com> wrote:
> On Thu, Nov 11, 2010 at 9:23 PM, Michael Spencer <bigcheesegs at gmail.com> wrote:
>> Attached are updated patches to be reviewed. I've split them up into
>> the generic API, the COFF and ELF implementations, tool changes, and
>> tests.
>>
>> This does not currently implement the Serialization/Normalization
>> split that I reference in my talk. I'm going to wait to do that split
>> until the line is firmly defined, as I still haven't figured out how
>> exactly to represent relocation data.
>>
>> A current major blocker that you can see throughout the ELF
>> implementation (and ignored in COFF (which I knew much better and
>> didn't need debugging help)) is how invalid object file errors are
>> handled. I currently just call report_fatal_error, which is really not
>> how they should be handled. I've been complaining about the same
>> problem in the System library on IRC recently too while trying to
>> clean up the Windows impl.
>>
>> What I would like to do is use an error object based on the concept of
>> std::error_code to report both system (IO, memory, syscall), and
>> "parsing" errors from invalid object files. This should also include
>> at least the address in the file at which the error occurred. I don't
>> feel that we need detailed (clang style :P) diagnostics because tools
>> generate object files, not people. At the same time I don't want to
>> just dump "object file invalid at 0xdeadbeef" to the user. Using
>> 'std::error_category' would allow mixing the two while proving more
>> detailed info such as "invalid symbol name string index at
>> 0xblahblah". Also, each object file could use a custom error_category
>> for special errors. It also allows clients that simply don't care to
>> just check for success and not pay for message formatting.
>>
>> - Michael Spencer
>>
>
> Pinging reviews on the rest of the patches (all but the first).
>
> - Michael Spencer
>

Ping.

- Michael Spencer

From gohman at apple.com  Wed Dec 15 20:51:19 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 16 Dec 2010 02:51:19 -0000
Subject: [llvm-commits] [llvm] r121944 - in /llvm/trunk:
 lib/Analysis/AliasAnalysis.cpp lib/Transforms/Scalar/MemCpyOptimizer.cpp
 test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
Message-ID: <20101216025119.4A4662A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 20:51:19 2010
New Revision: 121944

URL: http://llvm.org/viewvc/llvm-project?rev=121944&view=rev
Log:
Make memcpyopt TBAA-aware.

Added:
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
Modified:
    llvm/trunk/lib/Analysis/AliasAnalysis.cpp
    llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp

Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=121944&r1=121943&r2=121944&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Wed Dec 15 20:51:19 2010
@@ -219,8 +219,11 @@
   if (ConstantInt *C = dyn_cast<ConstantInt>(MTI->getLength()))
     Size = C->getValue().getZExtValue();
 
-  // FIXME: Can memcpy/memmove have TBAA tags?
-  return Location(MTI->getRawSource(), Size, 0);
+  // memcpy/memmove can have TBAA tags. For memcpy, they apply
+  // to both the source and the destination.
+  MDNode *TBAATag = MTI->getMetadata(LLVMContext::MD_tbaa);
+
+  return Location(MTI->getRawSource(), Size, TBAATag);
 }
 
 AliasAnalysis::Location 
@@ -228,9 +231,12 @@
   uint64_t Size = UnknownSize;
   if (ConstantInt *C = dyn_cast<ConstantInt>(MTI->getLength()))
     Size = C->getValue().getZExtValue();
+
+  // memcpy/memmove can have TBAA tags. For memcpy, they apply
+  // to both the source and the destination.
+  MDNode *TBAATag = MTI->getMetadata(LLVMContext::MD_tbaa);
   
-  // FIXME: Can memcpy/memmove have TBAA tags?
-  return Location(MTI->getRawDest(), Size, 0);
+  return Location(MTI->getRawDest(), Size, TBAATag);
 }
 
 

Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=121944&r1=121943&r2=121944&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Wed Dec 15 20:51:19 2010
@@ -688,10 +688,6 @@
   ConstantInt *C1 = dyn_cast<ConstantInt>(MDep->getLength());
   if (!C1) return false;
   
-  uint64_t DepSize = C1->getValue().getZExtValue();
-  if (DepSize < MSize)
-    return false;
-  
   AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
 
   // Verify that the copied-from memory doesn't change in between the two
@@ -716,7 +712,8 @@
   // source and dest might overlap.  We still want to eliminate the intermediate
   // value, but we have to generate a memmove instead of memcpy.
   Intrinsic::ID ResultFn = Intrinsic::memcpy;
-  if (!AA.isNoAlias(M->getRawDest(), MSize, MDep->getRawSource(), DepSize))
+  if (AA.alias(AA.getLocationForDest(M), AA.getLocationForSource(MDep)) !=
+      AliasAnalysis::NoAlias)
     ResultFn = Intrinsic::memmove;
   
   // If all checks passed, then we can transform M.
@@ -795,14 +792,9 @@
 bool MemCpyOpt::processMemMove(MemMoveInst *M) {
   AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
 
-  // If the memmove is a constant size, use it for the alias query, this allows
-  // us to optimize things like: memmove(P, P+64, 64);
-  uint64_t MemMoveSize = AliasAnalysis::UnknownSize;
-  if (ConstantInt *Len = dyn_cast<ConstantInt>(M->getLength()))
-    MemMoveSize = Len->getZExtValue();
-  
   // See if the pointers alias.
-  if (AA.alias(M->getRawDest(), MemMoveSize, M->getRawSource(), MemMoveSize) !=
+  if (AA.alias(AA.getLocationForDest(M),
+               AA.getLocationForSource(M)) !=
       AliasAnalysis::NoAlias)
     return false;
   

Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll?rev=121944&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll (added)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll Wed Dec 15 20:51:19 2010
@@ -0,0 +1,23 @@
+; RUN: opt -S -tbaa -basicaa -memcpyopt -instcombine < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64"
+
+; The second memcpy is redundant and can be deleted. There's an intervening store, but
+; it has a TBAA tag which declares that it is unrelated.
+
+; CHECK: @foo
+; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 16, i32 1, i1 false), !tbaa !0
+; CHECK-NEXT: store i8 2, i8* %s, align 1, !tbaa !2
+; CHECK-NEXT: ret void
+define void @foo(i8* nocapture %p, i8* nocapture %q, i8* nocapture %s) nounwind {
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 16, i32 1, i1 false), !tbaa !2
+  store i8 2, i8* %s, align 1, !tbaa !1
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %q, i8* %p, i64 16, i32 1, i1 false), !tbaa !2
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
+
+!0 = metadata !{metadata !"tbaa root", null}
+!1 = metadata !{metadata !"A", metadata !0}
+!2 = metadata !{metadata !"B", metadata !0}



From gohman at apple.com  Wed Dec 15 20:53:48 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 16 Dec 2010 02:53:48 -0000
Subject: [llvm-commits] [llvm] r121945 - in
 /llvm/trunk/test/Analysis/TypeBasedAliasAnalysis: aliastest.ll
 argument-promotion.ll dse.ll functionattrs.ll gvn-nonlocal-type-mismatch.ll
 licm.ll precedence.ll sink.ll
Message-ID: <20101216025348.F30262A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 20:53:48 2010
New Revision: 121945

URL: http://llvm.org/viewvc/llvm-project?rev=121945&view=rev
Log:
-enable-tbaa is on by default now.

Modified:
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dse.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/licm.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll
    llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt < %s -enable-tbaa -tbaa -basicaa -gvn -S | FileCheck %s
+; RUN: opt < %s -tbaa -basicaa -gvn -S | FileCheck %s
 
 ; Test that basic alias queries work.
 

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt < %s -enable-tbaa -tbaa -basicaa -argpromotion -mem2reg -S | not grep alloca
+; RUN: opt < %s -tbaa -basicaa -argpromotion -mem2reg -S | not grep alloca
 
 target datalayout = "E-p:64:64:64"
 

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dse.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dse.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dse.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt < %s -enable-tbaa -tbaa -basicaa -dse -S | FileCheck %s
+; RUN: opt < %s -tbaa -basicaa -dse -S | FileCheck %s
 
 ; DSE should make use of TBAA.
 

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt < %s -enable-tbaa -tbaa -basicaa -functionattrs -S | FileCheck %s
+; RUN: opt < %s -tbaa -basicaa -functionattrs -S | FileCheck %s
 
 ; FunctionAttrs should make use of TBAA.
 

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt -enable-tbaa -tbaa -basicaa -gvn -S < %s | FileCheck %s
+; RUN: opt -tbaa -basicaa -gvn -S < %s | FileCheck %s
 
 target datalayout = "e-p:64:64:64"
 

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/licm.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/licm.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/licm.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt -tbaa -licm -enable-tbaa -S < %s | FileCheck %s
+; RUN: opt -tbaa -licm -S < %s | FileCheck %s
 
 ; LICM should be able to hoist the address load out of the loop
 ; by using TBAA information.

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/precedence.ll Wed Dec 15 20:53:48 2010
@@ -1,5 +1,5 @@
-; RUN: opt -enable-tbaa -basicaa -tbaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=TBAA
-; RUN: opt -enable-tbaa -tbaa -basicaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=BASICAA
+; RUN: opt -basicaa -tbaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=TBAA
+; RUN: opt -tbaa -basicaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=BASICAA
 
 ; According to the TBAA metadata the load and store don't alias. However,
 ; according to the actual code, they do. The order of the alias analysis

Modified: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll?rev=121945&r1=121944&r2=121945&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll (original)
+++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/sink.ll Wed Dec 15 20:53:48 2010
@@ -1,4 +1,4 @@
-; RUN: opt -tbaa -enable-tbaa -sink -S < %s | FileCheck %s
+; RUN: opt -tbaa -sink -S < %s | FileCheck %s
 
 ; CHECK: a:
 ; CHECK:   %f = load float* %p, !tbaa !2



From gohman at apple.com  Wed Dec 15 20:55:10 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 16 Dec 2010 02:55:10 -0000
Subject: [llvm-commits] [llvm] r121946 -
	/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
Message-ID: <20101216025511.008A02A6C12C@llvm.org>

Author: djg
Date: Wed Dec 15 20:55:10 2010
New Revision: 121946

URL: http://llvm.org/viewvc/llvm-project?rev=121946&view=rev
Log:
Update a comment.

Modified:
    llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp?rev=121946&r1=121945&r2=121946&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/TypeBasedAliasAnalysis.cpp Wed Dec 15 20:55:10 2010
@@ -66,7 +66,9 @@
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
-// For testing purposes, enable TBAA only via a special option.
+// A handy option for disabling TBAA functionality. The same effect can also be
+// achieved by stripping the !tbaa tags from IR, but this option is sometimes
+// more convenient.
 static cl::opt<bool> EnableTBAA("enable-tbaa", cl::init(true));
 
 namespace {



From daniel at zuster.org  Wed Dec 15 21:05:46 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 03:05:46 -0000
Subject: [llvm-commits] [llvm] r121947 -
	/llvm/trunk/include/llvm/MC/MCCodeEmitter.h
Message-ID: <20101216030546.677E32A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec 15 21:05:46 2010
New Revision: 121947

URL: http://llvm.org/viewvc/llvm-project?rev=121947&view=rev
Log:
MC: Remove a FIXME I no longer agree with.

Modified:
    llvm/trunk/include/llvm/MC/MCCodeEmitter.h

Modified: llvm/trunk/include/llvm/MC/MCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeEmitter.h?rev=121947&r1=121946&r2=121947&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/MC/MCCodeEmitter.h Wed Dec 15 21:05:46 2010
@@ -36,10 +36,6 @@
   const char *Name;
 
   /// The bit offset to write the relocation into.
-  //
-  // FIXME: These two fields are under-specified and not general enough, but it
-  // covers many things. It's enough to let the AsmStreamer pretty-print
-  // the encoding.
   unsigned TargetOffset;
 
   /// The number of bits written by this fixup. The bits are assumed to be



From daniel at zuster.org  Wed Dec 15 21:05:53 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 03:05:53 -0000
Subject: [llvm-commits] [llvm] r121948 - in /llvm/trunk/include/llvm/MC:
 MCCodeEmitter.h MCFixupKindInfo.h
Message-ID: <20101216030554.07B842A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec 15 21:05:53 2010
New Revision: 121948

URL: http://llvm.org/viewvc/llvm-project?rev=121948&view=rev
Log:
MC: Split MCFixupKindInfo out into its own header.

Added:
    llvm/trunk/include/llvm/MC/MCFixupKindInfo.h
Modified:
    llvm/trunk/include/llvm/MC/MCCodeEmitter.h

Modified: llvm/trunk/include/llvm/MC/MCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeEmitter.h?rev=121948&r1=121947&r2=121948&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/MC/MCCodeEmitter.h Wed Dec 15 21:05:53 2010
@@ -11,6 +11,7 @@
 #define LLVM_MC_MCCODEEMITTER_H
 
 #include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCFixupKindInfo.h"
 
 #include <cassert>
 
@@ -20,32 +21,6 @@
 class raw_ostream;
 template<typename T> class SmallVectorImpl;
 
-/// MCFixupKindInfo - Target independent information on a fixup kind.
-struct MCFixupKindInfo {
-  enum FixupKindFlags {
-    /// Is this fixup kind PCrelative? This is used by the assembler backend to
-    /// evaluate fixup values in a target independent manner when possible.
-    FKF_IsPCRel = (1 << 0),
-    
-    /// Should this fixup kind force a 4-byte aligned effective PC value?
-    FKF_IsAlignedDownTo32Bits = (1 << 1)
-  };
-
-  /// A target specific name for the fixup kind. The names will be unique for
-  /// distinct kinds on any given target.
-  const char *Name;
-
-  /// The bit offset to write the relocation into.
-  unsigned TargetOffset;
-
-  /// The number of bits written by this fixup. The bits are assumed to be
-  /// contiguous.
-  unsigned TargetSize;
-
-  /// Flags describing additional information on this fixup kind.
-  unsigned Flags;
-};
-
 /// MCCodeEmitter - Generic instruction encoding interface.
 class MCCodeEmitter {
 private:

Added: llvm/trunk/include/llvm/MC/MCFixupKindInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCFixupKindInfo.h?rev=121948&view=auto
==============================================================================
--- llvm/trunk/include/llvm/MC/MCFixupKindInfo.h (added)
+++ llvm/trunk/include/llvm/MC/MCFixupKindInfo.h Wed Dec 15 21:05:53 2010
@@ -0,0 +1,43 @@
+//===-- llvm/MC/MCFixupKindInfo.h - Fixup Descriptors -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCFIXUPKINDINFO_H
+#define LLVM_MC_MCFIXUPKINDINFO_H
+
+namespace llvm {
+
+/// MCFixupKindInfo - Target independent information on a fixup kind.
+struct MCFixupKindInfo {
+  enum FixupKindFlags {
+    /// Is this fixup kind PCrelative? This is used by the assembler backend to
+    /// evaluate fixup values in a target independent manner when possible.
+    FKF_IsPCRel = (1 << 0),
+    
+    /// Should this fixup kind force a 4-byte aligned effective PC value?
+    FKF_IsAlignedDownTo32Bits = (1 << 1)
+  };
+
+  /// A target specific name for the fixup kind. The names will be unique for
+  /// distinct kinds on any given target.
+  const char *Name;
+
+  /// The bit offset to write the relocation into.
+  unsigned TargetOffset;
+
+  /// The number of bits written by this fixup. The bits are assumed to be
+  /// contiguous.
+  unsigned TargetSize;
+
+  /// Flags describing additional information on this fixup kind.
+  unsigned Flags;
+};
+
+} // End llvm namespace
+
+#endif



From daniel at zuster.org  Wed Dec 15 21:05:59 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 03:05:59 -0000
Subject: [llvm-commits] [llvm] r121949 - in /llvm/trunk:
 include/llvm/MC/MCStreamer.h include/llvm/Target/TargetRegistry.h
 lib/CodeGen/LLVMTargetMachine.cpp lib/MC/MCAsmStreamer.cpp
 lib/Target/PTX/PTXMCAsmStreamer.cpp lib/Target/PTX/PTXTargetMachine.cpp
 tools/llvm-mc/llvm-mc.cpp
Message-ID: <20101216030559.B41782A6C12D@llvm.org>

Author: ddunbar
Date: Wed Dec 15 21:05:59 2010
New Revision: 121949

URL: http://llvm.org/viewvc/llvm-project?rev=121949&view=rev
Log:
MC: Make TargetAsmBackend available to the AsmStreamer.
 - Treaty talks on the non-proliferation of MC objects broke down.

Modified:
    llvm/trunk/include/llvm/MC/MCStreamer.h
    llvm/trunk/include/llvm/Target/TargetRegistry.h
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/MC/MCAsmStreamer.cpp
    llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp
    llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp

Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Dec 15 21:05:59 2010
@@ -426,6 +426,10 @@
   /// \param CE - If given, a code emitter to use to show the instruction
   /// encoding inline with the assembly. This method takes ownership of \arg CE.
   ///
+  /// \param TAB - If given, a target asm backend to use to show the fixup
+  /// information in conjunction with encoding information. This method takes
+  /// ownership of \arg TAB.
+  ///
   /// \param ShowInst - Whether to show the MCInst representation inline with
   /// the assembly.
   MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
@@ -433,6 +437,7 @@
                                 bool useLoc,
                                 MCInstPrinter *InstPrint = 0,
                                 MCCodeEmitter *CE = 0,
+                                TargetAsmBackend *TAB = 0,
                                 bool ShowInst = false);
 
   /// createMachOStreamer - Create a machine code streamer which will generate

Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegistry.h Wed Dec 15 21:05:59 2010
@@ -46,6 +46,7 @@
                                 bool useLoc,
                                 MCInstPrinter *InstPrint,
                                 MCCodeEmitter *CE,
+                                TargetAsmBackend *TAB,
                                 bool ShowInst);
 
   /// Target - Wrapper for Target specific information.
@@ -95,6 +96,7 @@
                                              bool useLoc,
                                              MCInstPrinter *InstPrint,
                                              MCCodeEmitter *CE,
+                                             TargetAsmBackend *TAB,
                                              bool ShowInst);
 
   private:
@@ -323,10 +325,11 @@
                                   bool useLoc,
                                   MCInstPrinter *InstPrint,
                                   MCCodeEmitter *CE,
+                                  TargetAsmBackend *TAB,
                                   bool ShowInst) const {
       // AsmStreamerCtorFn is default to llvm::createAsmStreamer
       return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc,
-                               InstPrint, CE, ShowInst);
+                               InstPrint, CE, TAB, ShowInst);
     }
 
     /// @}

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Dec 15 21:05:59 2010
@@ -143,14 +143,17 @@
 
     // Create a code emitter if asked to show the encoding.
     MCCodeEmitter *MCE = 0;
-    if (ShowMCEncoding)
+    TargetAsmBackend *TAB = 0;
+    if (ShowMCEncoding) {
       MCE = getTarget().createCodeEmitter(*this, *Context);
+      TAB = getTarget().createAsmBackend(TargetTriple);
+    }
 
     MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
                                                   getVerboseAsm(),
                                                   hasMCUseLoc(),
                                                   InstPrinter,
-                                                  MCE,
+                                                  MCE, TAB,
                                                   ShowMCInst);
     AsmStreamer.reset(S);
     break;

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Dec 15 21:05:59 2010
@@ -23,8 +23,9 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/FormattedStream.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
+#include "llvm/Target/TargetAsmBackend.h"
 #include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/Target/TargetLoweringObjectFile.h"
 using namespace llvm;
 
 namespace {
@@ -34,6 +35,7 @@
   const MCAsmInfo &MAI;
   OwningPtr<MCInstPrinter> InstPrinter;
   OwningPtr<MCCodeEmitter> Emitter;
+  OwningPtr<TargetAsmBackend> AsmBackend;
 
   SmallString<128> CommentToEmit;
   raw_svector_ostream CommentStream;
@@ -48,10 +50,12 @@
   MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
                 bool isVerboseAsm,
                 bool useLoc,
-                MCInstPrinter *printer, MCCodeEmitter *emitter, bool showInst)
+                MCInstPrinter *printer, MCCodeEmitter *emitter,
+                TargetAsmBackend *asmbackend,
+                bool showInst)
     : MCStreamer(Context), OS(os), MAI(Context.getAsmInfo()),
-      InstPrinter(printer), Emitter(emitter), CommentStream(CommentToEmit),
-      IsVerboseAsm(isVerboseAsm),
+      InstPrinter(printer), Emitter(emitter), AsmBackend(asmbackend),
+      CommentStream(CommentToEmit), IsVerboseAsm(isVerboseAsm),
       ShowInst(showInst), UseLoc(useLoc) {
     if (InstPrinter && IsVerboseAsm)
       InstPrinter->setCommentStream(CommentStream);
@@ -893,8 +897,8 @@
 MCStreamer *llvm::createAsmStreamer(MCContext &Context,
                                     formatted_raw_ostream &OS,
                                     bool isVerboseAsm, bool useLoc,
-                                    MCInstPrinter *IP,
-                                    MCCodeEmitter *CE, bool ShowInst) {
+                                    MCInstPrinter *IP, MCCodeEmitter *CE,
+                                    TargetAsmBackend *TAB, bool ShowInst) {
   return new MCAsmStreamer(Context, OS, isVerboseAsm, useLoc,
-                           IP, CE, ShowInst);
+                           IP, CE, TAB, ShowInst);
 }

Modified: llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp Wed Dec 15 21:05:59 2010
@@ -540,7 +540,8 @@
                                    formatted_raw_ostream &OS,
                                    bool isVerboseAsm, bool useLoc,
                                    MCInstPrinter *IP,
-                                   MCCodeEmitter *CE, bool ShowInst) {
+                                   MCCodeEmitter *CE, TargetAsmBackend *TAB,
+                                   bool ShowInst) {
     return new PTXMCAsmStreamer(Context, OS, isVerboseAsm, useLoc,
                                 IP, CE, ShowInst);
   }

Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Dec 15 21:05:59 2010
@@ -24,6 +24,7 @@
                                    bool isVerboseAsm, bool useLoc,
                                    MCInstPrinter *InstPrint,
                                    MCCodeEmitter *CE,
+                                   TargetAsmBackend *TAB,
                                    bool ShowInst);
 }
 

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=121949&r1=121948&r2=121949&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Dec 15 21:05:59 2010
@@ -340,10 +340,14 @@
     MCInstPrinter *IP =
       TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
     MCCodeEmitter *CE = 0;
-    if (ShowEncoding)
+    TargetAsmBackend *TAB = 0;
+    if (ShowEncoding) {
       CE = TheTarget->createCodeEmitter(*TM, Ctx);
+      TAB = TheTarget->createAsmBackend(TripleName);
+    }
     Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true,
-                                           /*useLoc*/ true, IP, CE, ShowInst));
+                                           /*useLoc*/ true, IP, CE, TAB,
+                                           ShowInst));
   } else if (FileType == OFT_Null) {
     Str.reset(createNullStreamer(Ctx));
   } else {



From jason.w.kim.2009 at gmail.com  Wed Dec 15 21:12:17 2010
From: jason.w.kim.2009 at gmail.com (Jason W Kim)
Date: Thu, 16 Dec 2010 03:12:17 -0000
Subject: [llvm-commits] [llvm] r121951 - in /llvm/trunk:
 lib/MC/ELFObjectWriter.cpp lib/MC/MCELFStreamer.cpp
 test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
Message-ID: <20101216031217.3BCE62A6C12C@llvm.org>

Author: jasonwkim
Date: Wed Dec 15 21:12:17 2010
New Revision: 121951

URL: http://llvm.org/viewvc/llvm-project?rev=121951&view=rev
Log:
1. ARM/MC/ELF: A few more ELF relocs for .o
2. Fixed EmitLocalCommonSymbol for ELF (Yes, they exist. :)
   Test added.


Added:
    llvm/trunk/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/MCELFStreamer.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=121951&r1=121950&r2=121951&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 15 21:12:17 2010
@@ -1565,8 +1565,12 @@
         Type = ELF::R_ARM_GOT_BREL; break;
       case MCSymbolRefExpr::VK_ARM_TLSGD:
         Type = ELF::R_ARM_TLS_GD32; break;
+      case MCSymbolRefExpr::VK_ARM_TPOFF:
+        Type = ELF::R_ARM_TLS_LE32; break;
       case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
         Type = ELF::R_ARM_TLS_IE32; break;
+      case MCSymbolRefExpr::VK_None:
+        Type = ELF::R_ARM_ABS32; break;
       case MCSymbolRefExpr::VK_ARM_GOTOFF:
         Type = ELF::R_ARM_GOTOFF32; break;
       } break;
@@ -1579,6 +1583,8 @@
     case ARM::fixup_arm_thumb_br:
       assert(0 && "Unimplemented"); break;
     case ARM::fixup_arm_branch:
+      // FIXME: Differentiate between R_ARM_CALL and
+      // R_ARM_JUMP24 (latter used for conditional jumps)
       Type = ELF::R_ARM_CALL; break;
     case ARM::fixup_arm_movt_hi16: 
       Type = ELF::R_ARM_MOVT_ABS; break;

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=121951&r1=121950&r2=121951&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Wed Dec 15 21:12:17 2010
@@ -113,9 +113,8 @@
      SD.setSize(Value);
   }
 
-  virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size) {
-    assert(0 && "ELF doesn't support this directive");
-  }
+  virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size);
+
   virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
                             unsigned Size = 0, unsigned ByteAlignment = 0) {
     assert(0 && "ELF doesn't support this directive");
@@ -362,6 +361,16 @@
   SD.setSize(MCConstantExpr::Create(Size, getContext()));
 }
 
+void MCELFStreamer::EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size) {
+  // FIXME: Should this be caught and done earlier?
+  MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
+  SetBinding(SD, ELF::STB_LOCAL);
+  SD.setExternal(false);
+  BindingExplicitlySet.insert(Symbol);
+  // FIXME: ByteAlignment is not needed here, but is required.
+  EmitCommonSymbol(Symbol, Size, 1);
+}
+
 void MCELFStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {
   // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into
   // MCObjectStreamer.

Added: llvm/trunk/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll?rev=121951&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll Wed Dec 15 21:12:17 2010
@@ -0,0 +1,35 @@
+; RUN: llc  %s -mtriple=armv7-linux-gnueabi -arm-use-movt -filetype=obj -o - | \
+; RUN:    elf-dump --dump-section-data | FileCheck  -check-prefix=OBJ %s
+; RUN: llc  %s -mtriple=armv7-linux-gnueabi -arm-use-movt -o - | \
+; RUN:    FileCheck  -check-prefix=ASM %s
+
+
+ at dummy = internal global i32 666
+ at array00 = internal global [20 x i32] zeroinitializer
+ at sum = internal global i32 55
+ at STRIDE = internal global i32 8
+
+; ASM:          .type   array00,%object         @ @array00
+; ASM-NEXT:     .lcomm  array00,80              @ @array00
+; ASM-NEXT:     .type   _MergedGlobals,%object  @ @_MergedGlobals
+
+
+
+; OBJ:          Section 0x00000003
+; OBJ-NEXT:     '.bss'
+
+; OBJ:          'array00'
+; OBJ-NEXT:     'st_value', 0x00000000
+; OBJ-NEXT:     'st_size', 0x00000050
+; OBJ-NEXT:     'st_bind', 0x00000000
+; OBJ-NEXT:     'st_type', 0x00000001
+; OBJ-NEXT:     'st_other', 0x00000000
+; OBJ-NEXT:     'st_shndx', 0x00000003
+
+define i32 @main(i32 %argc) nounwind {
+  %1 = load i32* @sum, align 4
+  %2 = getelementptr  [20 x i32]* @array00, i32 0, i32 %argc
+  %3 = load i32* %2, align 4
+  %4 = add i32 %1, %3
+  ret i32 %4;
+}



From daniel at zuster.org  Wed Dec 15 21:20:07 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 03:20:07 -0000
Subject: [llvm-commits] [llvm] r121953 - in /llvm/trunk: include/llvm/MC/
 include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/MBlaze/
 lib/Target/PowerPC/ lib/Target/X86/
Message-ID: <20101216032007.3B6422A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec 15 21:20:06 2010
New Revision: 121953

URL: http://llvm.org/viewvc/llvm-project?rev=121953&view=rev
Log:
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

Modified:
    llvm/trunk/include/llvm/MC/MCCodeEmitter.h
    llvm/trunk/include/llvm/Target/TargetAsmBackend.h
    llvm/trunk/lib/MC/MCAsmStreamer.cpp
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCCodeEmitter.cpp
    llvm/trunk/lib/MC/TargetAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
    llvm/trunk/lib/Target/X86/X86FixupKinds.h
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeEmitter.h?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCCodeEmitter.h (original)
+++ llvm/trunk/include/llvm/MC/MCCodeEmitter.h Wed Dec 15 21:20:06 2010
@@ -11,7 +11,6 @@
 #define LLVM_MC_MCCODEEMITTER_H
 
 #include "llvm/MC/MCFixup.h"
-#include "llvm/MC/MCFixupKindInfo.h"
 
 #include <cassert>
 
@@ -32,17 +31,6 @@
 public:
   virtual ~MCCodeEmitter();
 
-  /// @name Target Independent Fixup Information
-  /// @{
-
-  /// getNumFixupKinds - Get the number of target specific fixup kinds.
-  virtual unsigned getNumFixupKinds() const = 0;
-
-  /// getFixupKindInfo - Get information on a fixup kind.
-  virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
-
-  /// @}
-
   /// EncodeInstruction - Encode the given \arg Inst to bytes on the output
   /// stream \arg OS.
   virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,

Modified: llvm/trunk/include/llvm/Target/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmBackend.h?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmBackend.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmBackend.h Wed Dec 15 21:20:06 2010
@@ -11,6 +11,8 @@
 #define LLVM_TARGET_TARGETASMBACKEND_H
 
 #include "llvm/MC/MCDirectives.h"
+#include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/Support/DataTypes.h"
 
 namespace llvm {
@@ -80,12 +82,28 @@
     return true;
   }
 
+  /// @name Target Fixup Interfaces
+  /// @{
+
+  /// getNumFixupKinds - Get the number of target specific fixup kinds.
+  virtual unsigned getNumFixupKinds() const = 0;
+
+  /// getFixupKindInfo - Get information on a fixup kind.
+  virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
+
+  /// @}
+
   /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
   /// data fragment, at the offset specified by the fixup and following the
   /// fixup kind as appropriate.
   virtual void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                           uint64_t Value) const = 0;
 
+  /// @}
+
+  /// @name Target Relaxation Interfaces
+  /// @{
+
   /// MayNeedRelaxation - Check whether the given instruction may need
   /// relaxation.
   ///
@@ -100,6 +118,8 @@
   /// \parm Res [output] - On return, the relaxed instruction.
   virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
 
+  /// @}
+
   /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
   /// output. If the target cannot generate such a sequence, it should return an
   /// error.

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Dec 15 21:20:06 2010
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCSectionMachO.h"
@@ -794,7 +795,7 @@
 
   for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
     MCFixup &F = Fixups[i];
-    const MCFixupKindInfo &Info = Emitter->getFixupKindInfo(F.getKind());
+    const MCFixupKindInfo &Info = AsmBackend->getFixupKindInfo(F.getKind());
     for (unsigned j = 0; j != Info.TargetSize; ++j) {
       unsigned Index = F.getOffset() * 8 + Info.TargetOffset + j;
       assert(Index < Code.size() * 8 && "Invalid offset in fixup!");
@@ -848,7 +849,7 @@
 
   for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
     MCFixup &F = Fixups[i];
-    const MCFixupKindInfo &Info = Emitter->getFixupKindInfo(F.getKind());
+    const MCFixupKindInfo &Info = AsmBackend->getFixupKindInfo(F.getKind());
     OS << "  fixup " << char('A' + i) << " - " << "offset: " << F.getOffset()
        << ", value: " << *F.getValue() << ", kind: " << Info.Name << "\n";
   }

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Dec 15 21:20:06 2010
@@ -224,7 +224,7 @@
 
   Value = Target.getConstant();
 
-  bool IsPCRel = Emitter.getFixupKindInfo(
+  bool IsPCRel = Backend.getFixupKindInfo(
     Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsPCRel;
   bool IsResolved = true;
   bool IsThumb = false;
@@ -248,7 +248,7 @@
   if (IsResolved)
     IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
 
-  bool ShouldAlignPC = Emitter.getFixupKindInfo(Fixup.getKind()).Flags &
+  bool ShouldAlignPC = Backend.getFixupKindInfo(Fixup.getKind()).Flags &
                          MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
   assert((ShouldAlignPC ? IsPCRel : true) &&
     "FKF_IsAlignedDownTo32Bits is only allowed on PC-relative fixups!");

Modified: llvm/trunk/lib/MC/MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCCodeEmitter.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/MC/MCCodeEmitter.cpp Wed Dec 15 21:20:06 2010
@@ -16,18 +16,3 @@
 
 MCCodeEmitter::~MCCodeEmitter() {
 }
-
-const MCFixupKindInfo &MCCodeEmitter::getFixupKindInfo(MCFixupKind Kind) const {
-  static const MCFixupKindInfo Builtins[] = {
-    { "FK_Data_1", 0, 8, 0 },
-    { "FK_Data_2", 0, 16, 0 },
-    { "FK_Data_4", 0, 32, 0 },
-    { "FK_Data_8", 0, 64, 0 },
-    { "FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel }
-  };
-  
-  assert(Kind <= 6 && "Unknown fixup kind");
-  return Builtins[Kind];
-}

Modified: llvm/trunk/lib/MC/TargetAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/TargetAsmBackend.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/MC/TargetAsmBackend.cpp (original)
+++ llvm/trunk/lib/MC/TargetAsmBackend.cpp Wed Dec 15 21:20:06 2010
@@ -18,3 +18,20 @@
 
 TargetAsmBackend::~TargetAsmBackend() {
 }
+
+const MCFixupKindInfo &
+TargetAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
+  static const MCFixupKindInfo Builtins[] = {
+    { "FK_Data_1", 0, 8, 0 },
+    { "FK_Data_2", 0, 16, 0 },
+    { "FK_Data_4", 0, 32, 0 },
+    { "FK_Data_8", 0, 64, 0 },
+    { "FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
+    { "FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+    { "FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel }
+  };
+  
+  assert(Kind <= sizeof(Builtins) / sizeof(Builtins[0]) &&
+         "Unknown fixup kind");
+  return Builtins[Kind];
+}

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Dec 15 21:20:06 2010
@@ -32,6 +32,46 @@
 public:
   ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
 
+  unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
+
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+    const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
+// This table *must* be in the order that the fixup_* kinds are defined in
+// ARMFixupKinds.h.
+//
+// Name                      Offset (bits) Size (bits)     Flags
+{ "fixup_arm_ldst_pcrel_12", 1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_ldst_pcrel_12",  0,            32,  MCFixupKindInfo::FKF_IsPCRel |
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+{ "fixup_arm_pcrel_10",      1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+{ "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel |
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+{ "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
+                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+{ "fixup_arm_branch",        0,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_br",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_bl",      0,            32,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_blx",     7,            21,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_cb",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_cp",      1,             8,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_thumb_bcc",     1,             8,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_movt_hi16",     0,            16,  0 },
+{ "fixup_arm_movw_lo16",     0,            16,  0 },
+    };
+
+    if (Kind < FirstTargetFixupKind)
+      return TargetAsmBackend::getFixupKindInfo(Kind);
+
+    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+           "Invalid kind!");
+    return Infos[Kind - FirstTargetFixupKind];
+  }
+
   bool MayNeedRelaxation(const MCInst &Inst) const;
 
   void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 15 21:20:06 2010
@@ -41,45 +41,6 @@
 
   ~ARMMCCodeEmitter() {}
 
-  unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
-
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
-    const static MCFixupKindInfo Infos[] = {
-// This table *must* be in the order that the fixup_* kinds are defined in
-// ARMFixupKinds.h.
-//
-// Name                      Offset (bits) Size (bits)     Flags
-{ "fixup_arm_ldst_pcrel_12", 1,            24,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_ldst_pcrel_12",  0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-{ "fixup_arm_pcrel_10",      1,            24,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_pcrel_10",       0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-{ "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel |
-                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-{ "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
-                                   MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-{ "fixup_arm_branch",        0,            24,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_condbranch",     0,            32,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_uncondbranch",   0,            32,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_br",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_bl",      0,            32,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_blx",     7,            21,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_cb",      0,            16,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_cp",      1,             8,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_thumb_bcc",     1,             8,  MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_arm_movt_hi16",     0,            16,  0 },
-{ "fixup_arm_movw_lo16",     0,            16,  0 },
-    };
-
-    if (Kind < FirstTargetFixupKind)
-      return MCCodeEmitter::getFixupKindInfo(Kind);
-
-    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
-           "Invalid kind!");
-    return Infos[Kind - FirstTargetFixupKind];
-  }
   unsigned getMachineSoImmOpValue(unsigned SoImm) const;
 
   // getBinaryCodeForInstr - TableGen'erated function for getting the

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp Wed Dec 15 21:20:06 2010
@@ -47,6 +47,10 @@
     : TargetAsmBackend() {
   }
 
+  unsigned getNumFixupKinds() const {
+    return 2;
+  }
+
   bool MayNeedRelaxation(const MCInst &Inst) const;
 
   void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Wed Dec 15 21:20:06 2010
@@ -51,10 +51,6 @@
     return getMachineOpValue(MI, MI.getOperand(OpIdx));
   }
 
-  unsigned getNumFixupKinds() const {
-    return 2;
-  }
-
   static unsigned GetMBlazeRegNum(const MCOperand &MO) {
     // FIXME: getMBlazeRegisterNumbering() is sufficient?
     assert(0 && "MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet implemented.");

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Wed Dec 15 21:20:06 2010
@@ -22,6 +22,26 @@
   const Target &TheTarget;
   public:
     PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {}
+  
+    unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
+
+    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+      const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = {
+        // name                    offset  bits  flags
+        { "fixup_ppc_br24",        6,      24,   MCFixupKindInfo::FKF_IsPCRel },
+        { "fixup_ppc_brcond14",    16,     14,   MCFixupKindInfo::FKF_IsPCRel },
+        { "fixup_ppc_lo16",        16,     16,   0 },
+        { "fixup_ppc_ha16",        16,     16,   0 },
+        { "fixup_ppc_lo14",        16,     14,   0 }
+      };
+    
+      if (Kind < FirstTargetFixupKind)
+        return TargetAsmBackend::getFixupKindInfo(Kind);
+    
+      assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+             "Invalid kind!");
+      return Infos[Kind - FirstTargetFixupKind];
+    }
     
     bool MayNeedRelaxation(const MCInst &Inst) const {
       // FIXME.

Modified: llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp Wed Dec 15 21:20:06 2010
@@ -37,26 +37,6 @@
   }
   
   ~PPCMCCodeEmitter() {}
-  
-  unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
-  
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
-    const static MCFixupKindInfo Infos[] = {
-      // name                     offset  bits  flags
-      { "fixup_ppc_br24",         6,      24,   MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_ppc_brcond14",     16,     14,   MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_ppc_lo16",         16,     16,   0 },
-      { "fixup_ppc_ha16",         16,     16,   0 },
-      { "fixup_ppc_lo14",         16,     14,   0 }
-    };
-    
-    if (Kind < FirstTargetFixupKind)
-      return MCCodeEmitter::getFixupKindInfo(Kind);
-    
-    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
-           "Invalid kind!");
-    return Infos[Kind - FirstTargetFixupKind];
-  }
 
   unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups) const;

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Wed Dec 15 21:20:06 2010
@@ -13,6 +13,7 @@
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectFormat.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionCOFF.h"
@@ -49,6 +50,26 @@
   X86AsmBackend(const Target &T)
     : TargetAsmBackend() {}
 
+  unsigned getNumFixupKinds() const {
+    return X86::NumTargetFixupKinds;
+  }
+
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+    const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
+      { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
+      { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
+      { "reloc_signed_4byte", 0, 4 * 8, 0},
+      { "reloc_global_offset_table", 0, 4 * 8, 0}
+    };
+
+    if (Kind < FirstTargetFixupKind)
+      return TargetAsmBackend::getFixupKindInfo(Kind);
+
+    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+           "Invalid kind!");
+    return Infos[Kind - FirstTargetFixupKind];
+  }
+
   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value) const {
     unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());

Modified: llvm/trunk/lib/Target/X86/X86FixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FixupKinds.h?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FixupKinds.h (original)
+++ llvm/trunk/lib/Target/X86/X86FixupKinds.h Wed Dec 15 21:20:06 2010
@@ -20,9 +20,12 @@
   reloc_signed_4byte,                        // 32-bit signed. Unlike FK_Data_4
                                              // this will be sign extended at
                                              // runtime.
-  reloc_global_offset_table                  // 32-bit, relative to the start
+  reloc_global_offset_table,                 // 32-bit, relative to the start
                                              // of the instruction. Used only
                                              // for _GLOBAL_OFFSET_TABLE_.
+  // Marker
+  LastTargetFixupKind,
+  NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 };
 }
 }

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=121953&r1=121952&r2=121953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Wed Dec 15 21:20:06 2010
@@ -38,26 +38,6 @@
 
   ~X86MCCodeEmitter() {}
 
-  unsigned getNumFixupKinds() const {
-    return 7;
-  }
-
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
-    const static MCFixupKindInfo Infos[] = {
-      { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
-      { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
-      { "reloc_signed_4byte", 0, 4 * 8, 0},
-      { "reloc_global_offset_table", 0, 4 * 8, 0}
-    };
-
-    if (Kind < FirstTargetFixupKind)
-      return MCCodeEmitter::getFixupKindInfo(Kind);
-
-    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
-           "Invalid kind!");
-    return Infos[Kind - FirstTargetFixupKind];
-  }
-
   static unsigned GetX86RegNum(const MCOperand &MO) {
     return X86RegisterInfo::getX86RegNum(MO.getReg());
   }



From bigcheesegs at gmail.com  Wed Dec 15 21:25:38 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Thu, 16 Dec 2010 03:25:38 -0000
Subject: [llvm-commits] [llvm] r121955 - /llvm/trunk/.gitignore
Message-ID: <20101216032538.BA7902A6C12C@llvm.org>

Author: mspencer
Date: Wed Dec 15 21:25:38 2010
New Revision: 121955

URL: http://llvm.org/viewvc/llvm-project?rev=121955&view=rev
Log:
Add .gitignore. I chose not to dump the svn ignore list into this because most
of the entries there are useless for out of source builds.

Added:
    llvm/trunk/.gitignore

Added: llvm/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=121955&view=auto
==============================================================================
--- llvm/trunk/.gitignore (added)
+++ llvm/trunk/.gitignore Wed Dec 15 21:25:38 2010
@@ -0,0 +1,3 @@
+tools/clang
+
+*.pyc



From bigcheesegs at gmail.com  Wed Dec 15 21:29:14 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Thu, 16 Dec 2010 03:29:14 -0000
Subject: [llvm-commits] [llvm] r121958 - in /llvm/trunk:
 include/llvm/Support/ lib/Archive/ lib/AsmParser/ lib/Linker/ lib/Object/
 lib/Support/ lib/VMCore/ tools/llvm-bcanalyzer/ tools/llvm-dis/
 tools/llvm-mc/ tools/llvm-nm/ tools/llvm-prof/ tools/lto/ tools/macho-dump/
 utils/FileCheck/ utils/FileUpdate/ utils/TableGen/
Message-ID: <20101216032915.0CB222A6C12C@llvm.org>

Author: mspencer
Date: Wed Dec 15 21:29:14 2010
New Revision: 121958

URL: http://llvm.org/viewvc/llvm-project?rev=121958&view=rev
Log:
MemoryBuffer now return an error_code and returns a OwningPtr<MemoryBuffer> via an out parm.

Modified:
    llvm/trunk/include/llvm/Support/IRReader.h
    llvm/trunk/include/llvm/Support/MemoryBuffer.h
    llvm/trunk/lib/Archive/Archive.cpp
    llvm/trunk/lib/Archive/ArchiveWriter.cpp
    llvm/trunk/lib/AsmParser/Parser.cpp
    llvm/trunk/lib/Linker/LinkItems.cpp
    llvm/trunk/lib/Linker/Linker.cpp
    llvm/trunk/lib/Object/ObjectFile.cpp
    llvm/trunk/lib/Support/CommandLine.cpp
    llvm/trunk/lib/Support/FileUtilities.cpp
    llvm/trunk/lib/Support/MemoryBuffer.cpp
    llvm/trunk/lib/Support/SourceMgr.cpp
    llvm/trunk/lib/VMCore/Core.cpp
    llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
    llvm/trunk/tools/llvm-dis/llvm-dis.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp
    llvm/trunk/tools/llvm-prof/llvm-prof.cpp
    llvm/trunk/tools/lto/LTOCodeGenerator.cpp
    llvm/trunk/tools/lto/LTOModule.cpp
    llvm/trunk/tools/macho-dump/macho-dump.cpp
    llvm/trunk/utils/FileCheck/FileCheck.cpp
    llvm/trunk/utils/FileUpdate/FileUpdate.cpp
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/include/llvm/Support/IRReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRReader.h?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/IRReader.h (original)
+++ llvm/trunk/include/llvm/Support/IRReader.h Wed Dec 15 21:29:14 2010
@@ -19,6 +19,7 @@
 #ifndef LLVM_SUPPORT_IRREADER_H
 #define LLVM_SUPPORT_IRREADER_H
 
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Assembly/Parser.h"
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/Support/MemoryBuffer.h"
@@ -57,15 +58,14 @@
   inline Module *getLazyIRFileModule(const std::string &Filename,
                                      SMDiagnostic &Err,
                                      LLVMContext &Context) {
-    error_code ec;
-    MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), ec);
-    if (F == 0) {
+    OwningPtr<MemoryBuffer> File;
+    if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File)) {
       Err = SMDiagnostic(Filename,
                          "Could not open input file: " + ec.message());
       return 0;
     }
 
-    return getLazyIRModule(F, Err, Context);
+    return getLazyIRModule(File.take(), Err, Context);
   }
 
   /// If the given MemoryBuffer holds a bitcode image, return a Module
@@ -95,15 +95,14 @@
   inline Module *ParseIRFile(const std::string &Filename,
                              SMDiagnostic &Err,
                              LLVMContext &Context) {
-    error_code ec;
-    MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), ec);
-    if (F == 0) {
+    OwningPtr<MemoryBuffer> File;
+    if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File)) {
       Err = SMDiagnostic(Filename,
                          "Could not open input file: " + ec.message());
       return 0;
     }
 
-    return ParseIR(F, Err, Context);
+    return ParseIR(File.take(), Err, Context);
   }
 
 }

Modified: llvm/trunk/include/llvm/Support/MemoryBuffer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MemoryBuffer.h?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/MemoryBuffer.h (original)
+++ llvm/trunk/include/llvm/Support/MemoryBuffer.h Wed Dec 15 21:29:14 2010
@@ -20,6 +20,7 @@
 namespace llvm {
 
 class error_code;
+template<class T> class OwningPtr;
 
 /// MemoryBuffer - This interface provides simple read-only access to a block
 /// of memory, and provides simple methods for reading files and standard input
@@ -61,17 +62,18 @@
   /// MemoryBuffer if successful, otherwise returning null.  If FileSize is
   /// specified, this means that the client knows that the file exists and that
   /// it has the specified size.
-  static MemoryBuffer *getFile(StringRef Filename, error_code &ec,
-                               int64_t FileSize = -1);
-  static MemoryBuffer *getFile(const char *Filename, error_code &ec,
-                               int64_t FileSize = -1);
+  static error_code getFile(StringRef Filename, OwningPtr<MemoryBuffer> &result,
+                            int64_t FileSize = -1);
+  static error_code getFile(const char *Filename,
+                            OwningPtr<MemoryBuffer> &result,
+                            int64_t FileSize = -1);
 
   /// getOpenFile - Given an already-open file descriptor, read the file and
   /// return a MemoryBuffer.  This takes ownership of the descriptor,
   /// immediately closing it after reading the file.
-  static MemoryBuffer *getOpenFile(int FD, const char *Filename,
-                                   error_code &ec,
-                                   int64_t FileSize = -1);
+  static error_code getOpenFile(int FD, const char *Filename,
+                                OwningPtr<MemoryBuffer> &result,
+                                int64_t FileSize = -1);
 
   /// getMemBuffer - Open the specified memory range as a MemoryBuffer.  Note
   /// that InputData must be null terminated.
@@ -99,18 +101,18 @@
 
   /// getSTDIN - Read all of stdin into a file buffer, and return it.
   /// If an error occurs, this returns null and sets ec.
-  static MemoryBuffer *getSTDIN(error_code &ec);
+  static error_code getSTDIN(OwningPtr<MemoryBuffer> &result);
 
 
   /// getFileOrSTDIN - Open the specified file as a MemoryBuffer, or open stdin
   /// if the Filename is "-".  If an error occurs, this returns null and sets
   /// ec.
-  static MemoryBuffer *getFileOrSTDIN(StringRef Filename,
-                                      error_code &ec,
-                                      int64_t FileSize = -1);
-  static MemoryBuffer *getFileOrSTDIN(const char *Filename,
-                                      error_code &ec,
-                                      int64_t FileSize = -1);
+  static error_code getFileOrSTDIN(StringRef Filename,
+                                   OwningPtr<MemoryBuffer> &result,
+                                   int64_t FileSize = -1);
+  static error_code getFileOrSTDIN(const char *Filename,
+                                   OwningPtr<MemoryBuffer> &result,
+                                   int64_t FileSize = -1);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Archive/Archive.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Archive/Archive.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Archive/Archive.cpp (original)
+++ llvm/trunk/lib/Archive/Archive.cpp Wed Dec 15 21:29:14 2010
@@ -148,13 +148,13 @@
 
 bool
 Archive::mapToMemory(std::string* ErrMsg) {
-  error_code ec;
-  mapfile = MemoryBuffer::getFile(archPath.c_str(), ec);
-  if (mapfile == 0) {
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec = MemoryBuffer::getFile(archPath.c_str(), File)) {
     if (ErrMsg)
       *ErrMsg = ec.message();
     return true;
   }
+  mapfile = File.take();
   base = mapfile->getBufferStart();
   return false;
 }
@@ -218,10 +218,8 @@
                              LLVMContext& Context,
                              std::vector<std::string>& symbols,
                              std::string* ErrMsg) {
-  error_code ec;
-  std::auto_ptr<MemoryBuffer> Buffer(
-                       MemoryBuffer::getFileOrSTDIN(fName.c_str(), ec));
-  if (!Buffer.get()) {
+  OwningPtr<MemoryBuffer> Buffer;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(fName.c_str(), Buffer)) {
     if (ErrMsg) *ErrMsg = "Could not open file '" + fName.str() + "'" + ": "
                         + ec.message();
     return true;
@@ -246,7 +244,7 @@
                         std::vector<std::string>& symbols,
                         std::string* ErrMsg) {
   // Get the module.
-  std::auto_ptr<MemoryBuffer> Buffer(
+  OwningPtr<MemoryBuffer> Buffer(
     MemoryBuffer::getMemBufferCopy(StringRef(BufPtr, Length),ModuleID.c_str()));
   
   Module *M = ParseBitcodeFile(Buffer.get(), Context, ErrMsg);

Modified: llvm/trunk/lib/Archive/ArchiveWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Archive/ArchiveWriter.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Archive/ArchiveWriter.cpp (original)
+++ llvm/trunk/lib/Archive/ArchiveWriter.cpp Wed Dec 15 21:29:14 2010
@@ -213,13 +213,13 @@
   const char *data = (const char*)member.getData();
   MemoryBuffer *mFile = 0;
   if (!data) {
-    error_code ec;
-    mFile = MemoryBuffer::getFile(member.getPath().c_str(), ec);
-    if (mFile == 0) {
+    OwningPtr<MemoryBuffer> File;
+    if (error_code ec = MemoryBuffer::getFile(member.getPath().c_str(), File)) {
       if (ErrMsg)
         *ErrMsg = ec.message();
       return true;
     }
+    mFile = File.take();
     data = mFile->getBufferStart();
     fSize = mFile->getBufferSize();
   }
@@ -411,9 +411,8 @@
 
     // Map in the archive we just wrote.
     {
-    error_code ec;
-    OwningPtr<MemoryBuffer> arch(MemoryBuffer::getFile(TmpArchive.c_str(), ec));
-    if (arch == 0) {
+    OwningPtr<MemoryBuffer> arch;
+    if (error_code ec = MemoryBuffer::getFile(TmpArchive.c_str(), arch)) {
       if (ErrMsg)
         *ErrMsg = ec.message();
       return true;

Modified: llvm/trunk/lib/AsmParser/Parser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/Parser.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/Parser.cpp (original)
+++ llvm/trunk/lib/AsmParser/Parser.cpp Wed Dec 15 21:29:14 2010
@@ -42,15 +42,14 @@
 
 Module *llvm::ParseAssemblyFile(const std::string &Filename, SMDiagnostic &Err,
                                 LLVMContext &Context) {
-  error_code ec;
-  MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), ec);
-  if (F == 0) {
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File)) {
     Err = SMDiagnostic(Filename,
                        "Could not open input file: " + ec.message());
     return 0;
   }
 
-  return ParseAssembly(F, 0, Err, Context);
+  return ParseAssembly(File.take(), 0, Err, Context);
 }
 
 Module *llvm::ParseAssemblyString(const char *AsmString, Module *M,

Modified: llvm/trunk/lib/Linker/LinkItems.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkItems.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Linker/LinkItems.cpp (original)
+++ llvm/trunk/lib/Linker/LinkItems.cpp Wed Dec 15 21:29:14 2010
@@ -161,14 +161,13 @@
   // Check for a file of name "-", which means "read standard input"
   if (File.str() == "-") {
     std::auto_ptr<Module> M;
+    OwningPtr<MemoryBuffer> Buffer;
     error_code ec;
-    if (MemoryBuffer *Buffer = MemoryBuffer::getSTDIN(ec)) {
+    if (!(ec = MemoryBuffer::getSTDIN(Buffer))) {
       if (!Buffer->getBufferSize()) {
-        delete Buffer;
         Error = "standard input is empty";
       } else {
-        M.reset(ParseBitcodeFile(Buffer, Context, &Error));
-        delete Buffer;
+        M.reset(ParseBitcodeFile(Buffer.get(), Context, &Error));
         if (M.get())
           if (!LinkInModule(M.get(), &Error))
             return false;

Modified: llvm/trunk/lib/Linker/Linker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/Linker.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Linker/Linker.cpp (original)
+++ llvm/trunk/lib/Linker/Linker.cpp Wed Dec 15 21:29:14 2010
@@ -99,14 +99,12 @@
   std::string ParseErrorMessage;
   Module *Result = 0;
 
-  error_code ec;
-  std::auto_ptr<MemoryBuffer> Buffer(
-    MemoryBuffer::getFileOrSTDIN(FN.c_str(), ec));
-  if (Buffer.get())
-    Result = ParseBitcodeFile(Buffer.get(), Context, &ParseErrorMessage);
-  else
+  OwningPtr<MemoryBuffer> Buffer;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(FN.c_str(), Buffer))
     ParseErrorMessage = "Error reading file '" + FN.str() + "'" + ": "
                       + ec.message();
+  else
+    Result = ParseBitcodeFile(Buffer.get(), Context, &ParseErrorMessage);
 
   if (Result)
     return std::auto_ptr<Module>(Result);

Modified: llvm/trunk/lib/Object/ObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ObjectFile.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/ObjectFile.cpp Wed Dec 15 21:29:14 2010
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Object/ObjectFile.h"
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/Path.h"
@@ -63,6 +64,8 @@
 }
 
 ObjectFile *ObjectFile::createObjectFile(StringRef ObjectPath) {
-  error_code ec;
-  return createObjectFile(MemoryBuffer::getFile(ObjectPath, ec));
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec = MemoryBuffer::getFile(ObjectPath, File))
+    return NULL;
+  return createObjectFile(File.take());
 }

Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Wed Dec 15 21:29:14 2010
@@ -464,11 +464,6 @@
       const sys::FileStatus *FileStat = respFile.getFileStatus();
       if (FileStat && FileStat->getSize() != 0) {
 
-        // Mmap the response file into memory.
-        error_code ec;
-        OwningPtr<MemoryBuffer>
-          respFilePtr(MemoryBuffer::getFile(respFile.c_str(), ec));
-
         // If we could open the file, parse its contents, otherwise
         // pass the @file option verbatim.
 
@@ -477,7 +472,9 @@
         // itself contain additional @file options; any such options will be
         // processed recursively.")
 
-        if (respFilePtr != 0) {
+        // Mmap the response file into memory.
+        OwningPtr<MemoryBuffer> respFilePtr;
+        if (!MemoryBuffer::getFile(respFile.c_str(), respFilePtr)) {
           ParseCStringVector(newArgv, respFilePtr->getBufferStart());
           continue;
         }

Modified: llvm/trunk/lib/Support/FileUtilities.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FileUtilities.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Support/FileUtilities.cpp (original)
+++ llvm/trunk/lib/Support/FileUtilities.cpp Wed Dec 15 21:29:14 2010
@@ -201,14 +201,14 @@
   // Now its safe to mmap the files into memory becasue both files
   // have a non-zero size.
   error_code ec;
-  OwningPtr<MemoryBuffer> F1(MemoryBuffer::getFile(FileA.c_str(), ec));
-  if (F1 == 0) {
+  OwningPtr<MemoryBuffer> F1;
+  if (error_code ec = MemoryBuffer::getFile(FileA.c_str(), F1)) {
     if (Error)
       *Error = ec.message();
     return 2;
   }
-  OwningPtr<MemoryBuffer> F2(MemoryBuffer::getFile(FileB.c_str(), ec));
-  if (F2 == 0) {
+  OwningPtr<MemoryBuffer> F2;
+  if (error_code ec = MemoryBuffer::getFile(FileB.c_str(), F2)) {
     if (Error)
       *Error = ec.message();
     return 2;

Modified: llvm/trunk/lib/Support/MemoryBuffer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/MemoryBuffer.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Support/MemoryBuffer.cpp (original)
+++ llvm/trunk/lib/Support/MemoryBuffer.cpp Wed Dec 15 21:29:14 2010
@@ -35,6 +35,8 @@
 #include <fcntl.h>
 using namespace llvm;
 
+namespace { const llvm::error_code success; }
+
 //===----------------------------------------------------------------------===//
 // MemoryBuffer implementation itself.
 //===----------------------------------------------------------------------===//
@@ -143,20 +145,20 @@
 /// if the Filename is "-".  If an error occurs, this returns null and fills
 /// in *ErrStr with a reason.  If stdin is empty, this API (unlike getSTDIN)
 /// returns an empty buffer.
-MemoryBuffer *MemoryBuffer::getFileOrSTDIN(StringRef Filename,
-                                           error_code &ec,
-                                           int64_t FileSize) {
+error_code MemoryBuffer::getFileOrSTDIN(StringRef Filename,
+                                        OwningPtr<MemoryBuffer> &result,
+                                        int64_t FileSize) {
   if (Filename == "-")
-    return getSTDIN(ec);
-  return getFile(Filename, ec, FileSize);
+    return getSTDIN(result);
+  return getFile(Filename, result, FileSize);
 }
 
-MemoryBuffer *MemoryBuffer::getFileOrSTDIN(const char *Filename,
-                                           error_code &ec,
-                                           int64_t FileSize) {
+error_code MemoryBuffer::getFileOrSTDIN(const char *Filename,
+                                        OwningPtr<MemoryBuffer> &result,
+                                        int64_t FileSize) {
   if (strcmp(Filename, "-") == 0)
-    return getSTDIN(ec);
-  return getFile(Filename, ec, FileSize);
+    return getSTDIN(result);
+  return getFile(Filename, result, FileSize);
 }
 
 //===----------------------------------------------------------------------===//
@@ -186,30 +188,32 @@
 };
 }
 
-MemoryBuffer *MemoryBuffer::getFile(StringRef Filename, error_code &ec,
-                                    int64_t FileSize) {
+error_code MemoryBuffer::getFile(StringRef Filename,
+                                 OwningPtr<MemoryBuffer> &result,
+                                 int64_t FileSize) {
   // Ensure the path is null terminated.
   SmallString<256> PathBuf(Filename.begin(), Filename.end());
-  return MemoryBuffer::getFile(PathBuf.c_str(), ec, FileSize);
+  return MemoryBuffer::getFile(PathBuf.c_str(), result, FileSize);
 }
 
-MemoryBuffer *MemoryBuffer::getFile(const char *Filename, error_code &ec,
-                                    int64_t FileSize) {
+error_code MemoryBuffer::getFile(const char *Filename,
+                                 OwningPtr<MemoryBuffer> &result,
+                                 int64_t FileSize) {
   int OpenFlags = O_RDONLY;
 #ifdef O_BINARY
   OpenFlags |= O_BINARY;  // Open input file in binary mode on win32.
 #endif
   int FD = ::open(Filename, OpenFlags);
   if (FD == -1) {
-    ec = error_code(errno, posix_category());
-    return 0;
+    return error_code(errno, posix_category());
   }
 
-  return getOpenFile(FD, Filename, ec, FileSize);
+  return getOpenFile(FD, Filename, result, FileSize);
 }
 
-MemoryBuffer *MemoryBuffer::getOpenFile(int FD, const char *Filename,
-                                        error_code &ec, int64_t FileSize) {
+error_code MemoryBuffer::getOpenFile(int FD, const char *Filename,
+                                     OwningPtr<MemoryBuffer> &result,
+                                     int64_t FileSize) {
   FileCloser FC(FD); // Close FD on return.
 
   // If we don't know the file size, use fstat to find out.  fstat on an open
@@ -218,8 +222,7 @@
     struct stat FileInfo;
     // TODO: This should use fstat64 when available.
     if (fstat(FD, &FileInfo) == -1) {
-      ec = error_code(errno, posix_category());
-      return 0;
+      return error_code(errno, posix_category());
     }
     FileSize = FileInfo.st_size;
   }
@@ -234,8 +237,9 @@
   if (FileSize >= 4096*4 &&
       (FileSize & (sys::Process::GetPageSize()-1)) != 0) {
     if (const char *Pages = sys::Path::MapInFilePages(FD, FileSize)) {
-      return GetNamedBuffer<MemoryBufferMMapFile>(StringRef(Pages, FileSize),
-                                                  Filename);
+      result.reset(GetNamedBuffer<MemoryBufferMMapFile>(
+        StringRef(Pages, FileSize), Filename));
+      return success;
     }
   }
 
@@ -243,8 +247,7 @@
   if (!Buf) {
     // Failed to create a buffer. The only way it can fail is if
     // new(std::nothrow) returns 0.
-    ec = make_error_code(errc::not_enough_memory);
-    return 0;
+    return make_error_code(errc::not_enough_memory);
   }
 
   OwningPtr<MemoryBuffer> SB(Buf);
@@ -257,26 +260,27 @@
       if (errno == EINTR)
         continue;
       // Error while reading.
-      ec = error_code(errno, posix_category());
-      return 0;
+      return error_code(errno, posix_category());
     } else if (NumRead == 0) {
       // We hit EOF early, truncate and terminate buffer.
       Buf->BufferEnd = BufPtr;
       *BufPtr = 0;
-      return SB.take();
+      result.swap(SB);
+      return success;
     }
     BytesLeft -= NumRead;
     BufPtr += NumRead;
   }
 
-  return SB.take();
+  result.swap(SB);
+  return success;
 }
 
 //===----------------------------------------------------------------------===//
 // MemoryBuffer::getSTDIN implementation.
 //===----------------------------------------------------------------------===//
 
-MemoryBuffer *MemoryBuffer::getSTDIN(error_code &ec) {
+error_code MemoryBuffer::getSTDIN(OwningPtr<MemoryBuffer> &result) {
   // Read in all of the data from stdin, we cannot mmap stdin.
   //
   // FIXME: That isn't necessarily true, we should try to mmap stdin and
@@ -292,11 +296,11 @@
     ReadBytes = read(0, Buffer.end(), ChunkSize);
     if (ReadBytes == -1) {
       if (errno == EINTR) continue;
-      ec = error_code(errno, posix_category());
-      return 0;
+      return error_code(errno, posix_category());
     }
     Buffer.set_size(Buffer.size() + ReadBytes);
   } while (ReadBytes != 0);
 
-  return getMemBufferCopy(Buffer, "<stdin>");
+  result.reset(getMemBufferCopy(Buffer, "<stdin>"));
+  return success;
 }

Modified: llvm/trunk/lib/Support/SourceMgr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SourceMgr.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/Support/SourceMgr.cpp (original)
+++ llvm/trunk/lib/Support/SourceMgr.cpp Wed Dec 15 21:29:14 2010
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/MemoryBuffer.h"
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/system_error.h"
 using namespace llvm;
@@ -49,18 +50,18 @@
 /// ~0, otherwise it returns the buffer ID of the stacked file.
 unsigned SourceMgr::AddIncludeFile(const std::string &Filename,
                                    SMLoc IncludeLoc) {
-  error_code ec;
-  MemoryBuffer *NewBuf = MemoryBuffer::getFile(Filename.c_str(), ec);
+  OwningPtr<MemoryBuffer> NewBuf;
+  MemoryBuffer::getFile(Filename.c_str(), NewBuf);
 
   // If the file didn't exist directly, see if it's in an include path.
   for (unsigned i = 0, e = IncludeDirectories.size(); i != e && !NewBuf; ++i) {
     std::string IncFile = IncludeDirectories[i] + "/" + Filename;
-    NewBuf = MemoryBuffer::getFile(IncFile.c_str(), ec);
+    MemoryBuffer::getFile(IncFile.c_str(), NewBuf);
   }
 
   if (NewBuf == 0) return ~0U;
 
-  return AddNewSourceBuffer(NewBuf, IncludeLoc);
+  return AddNewSourceBuffer(NewBuf.take(), IncludeLoc);
 }
 
 

Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Wed Dec 15 21:29:14 2010
@@ -2221,9 +2221,10 @@
     LLVMMemoryBufferRef *OutMemBuf,
     char **OutMessage) {
 
+  OwningPtr<MemoryBuffer> MB;
   error_code ec;
-  if (MemoryBuffer *MB = MemoryBuffer::getFile(Path, ec)) {
-    *OutMemBuf = wrap(MB);
+  if (!(ec = MemoryBuffer::getFile(Path, MB))) {
+    *OutMemBuf = wrap(MB.take());
     return 0;
   }
 
@@ -2233,9 +2234,10 @@
 
 LLVMBool LLVMCreateMemoryBufferWithSTDIN(LLVMMemoryBufferRef *OutMemBuf,
                                          char **OutMessage) {
+  OwningPtr<MemoryBuffer> MB;
   error_code ec;
-  if (MemoryBuffer *MB = MemoryBuffer::getSTDIN(ec)) {
-    *OutMemBuf = wrap(MB);
+  if (!(ec = MemoryBuffer::getSTDIN(MB))) {
+    *OutMemBuf = wrap(MB.take());
     return 0;
   }
 

Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Wed Dec 15 21:29:14 2010
@@ -27,6 +27,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Analysis/Verifier.h"
 #include "llvm/Bitcode/BitstreamReader.h"
 #include "llvm/Bitcode/LLVMBitCodes.h"
@@ -58,7 +59,7 @@
 
 static cl::opt<bool>
 NonSymbolic("non-symbolic",
-            cl::desc("Emit numberic info in dump even if"
+            cl::desc("Emit numeric info in dump even if"
                      " symbolic info is available"));
 
 namespace {
@@ -481,11 +482,10 @@
 /// AnalyzeBitcode - Analyze the bitcode file specified by InputFilename.
 static int AnalyzeBitcode() {
   // Read the input file.
-  error_code ec;
-  MemoryBuffer *MemBuf =
-    MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), ec);
+  OwningPtr<MemoryBuffer> MemBuf;
 
-  if (MemBuf == 0)
+  if (error_code ec =
+        MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), MemBuf))
     return Error("Error reading '" + InputFilename + "': " + ec.message());
 
   if (MemBuf->getBufferSize() & 3)

Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original)
+++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Wed Dec 15 21:29:14 2010
@@ -81,12 +81,13 @@
   std::string ErrorMessage;
   error_code ec;
   std::auto_ptr<Module> M;
+  OwningPtr<MemoryBuffer> BufferPtr;
 
-  if (MemoryBuffer *Buffer = MemoryBuffer::getFileOrSTDIN(InputFilename, ec)) {
-    M.reset(ParseBitcodeFile(Buffer, Context, &ErrorMessage));
-    delete Buffer;
-  } else
+  if (ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
     ErrorMessage = ec.message();
+  else
+    M.reset(ParseBitcodeFile(BufferPtr.get(), Context, &ErrorMessage));
+  MemoryBuffer *Buffer = BufferPtr.take();
 
   if (M.get() == 0) {
     errs() << argv[0] << ": ";

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Dec 15 21:29:14 2010
@@ -168,12 +168,12 @@
 }
 
 static int AsLexInput(const char *ProgName) {
-  error_code ec;
-  MemoryBuffer *Buffer = MemoryBuffer::getFileOrSTDIN(InputFilename, ec);
-  if (Buffer == 0) {
+  OwningPtr<MemoryBuffer> BufferPtr;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr)) {
     errs() << ProgName << ": " << ec.message() << '\n';
     return 1;
   }
+  MemoryBuffer *Buffer = BufferPtr.take();
 
   SourceMgr SrcMgr;
   
@@ -281,12 +281,12 @@
   if (!TheTarget)
     return 1;
 
-  error_code ec;
-  MemoryBuffer *Buffer = MemoryBuffer::getFileOrSTDIN(InputFilename, ec);
-  if (Buffer == 0) {
+  OwningPtr<MemoryBuffer> BufferPtr;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr)) {
     errs() << ProgName << ": " << ec.message() << '\n';
     return 1;
   }
+  MemoryBuffer *Buffer = BufferPtr.take();
   
   SourceMgr SrcMgr;
   
@@ -387,9 +387,8 @@
   if (!TheTarget)
     return 0;
 
-  error_code ec;
-  MemoryBuffer *Buffer = MemoryBuffer::getFileOrSTDIN(InputFilename, ec);
-  if (Buffer == 0) {
+  OwningPtr<MemoryBuffer> Buffer;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename, Buffer)) {
     errs() << ProgName << ": " << ec.message() << '\n';
     return 1;
   }
@@ -400,9 +399,11 @@
 
   int Res;
   if (Enhanced)
-    Res = Disassembler::disassembleEnhanced(TripleName, *Buffer, Out->os());
+    Res =
+      Disassembler::disassembleEnhanced(TripleName, *Buffer.take(), Out->os());
   else
-    Res = Disassembler::disassemble(*TheTarget, TripleName, *Buffer, Out->os());
+    Res = Disassembler::disassemble(*TheTarget, TripleName,
+                                    *Buffer.take(), Out->os());
 
   // Keep output if no errors.
   if (Res == 0) Out->keep();

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Wed Dec 15 21:29:14 2010
@@ -144,10 +144,8 @@
   sys::Path aPath(Filename);
   // Note: Currently we do not support reading an archive from stdin.
   if (Filename == "-" || aPath.isBitcodeFile()) {
-    error_code ec;
-    std::auto_ptr<MemoryBuffer> Buffer(
-                   MemoryBuffer::getFileOrSTDIN(Filename, ec));
-    if (Buffer.get() == 0)
+    OwningPtr<MemoryBuffer> Buffer;
+    if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename, Buffer))
       ErrorMessage = ec.message();
     Module *Result = 0;
     if (Buffer.get())

Modified: llvm/trunk/tools/llvm-prof/llvm-prof.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-prof/llvm-prof.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-prof/llvm-prof.cpp (original)
+++ llvm/trunk/tools/llvm-prof/llvm-prof.cpp Wed Dec 15 21:29:14 2010
@@ -264,11 +264,11 @@
 
   // Read in the bitcode file...
   std::string ErrorMessage;
+  OwningPtr<MemoryBuffer> Buffer;
   error_code ec;
   Module *M = 0;
-  if (MemoryBuffer *Buffer = MemoryBuffer::getFileOrSTDIN(BitcodeFile, ec)) {
-    M = ParseBitcodeFile(Buffer, Context, &ErrorMessage);
-    delete Buffer;
+  if (!(ec = MemoryBuffer::getFileOrSTDIN(BitcodeFile, Buffer))) {
+    M = ParseBitcodeFile(Buffer.get(), Context, &ErrorMessage);
   } else
     ErrorMessage = ec.message();
   if (M == 0) {

Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Dec 15 21:29:14 2010
@@ -224,10 +224,10 @@
         delete _nativeObjectFile;
 
         // read .o file into memory buffer
-        error_code ec;
-        _nativeObjectFile = MemoryBuffer::getFile(uniqueObjStr.c_str(), ec);
-        if (ec)
+        OwningPtr<MemoryBuffer> BuffPtr;
+        if (error_code ec = MemoryBuffer::getFile(uniqueObjStr.c_str(),BuffPtr))
           errMsg = ec.message();
+        _nativeObjectFile = BuffPtr.take();
     }
 
     // remove temp files

Modified: llvm/trunk/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOModule.cpp (original)
+++ llvm/trunk/tools/lto/LTOModule.cpp Wed Dec 15 21:29:14 2010
@@ -57,18 +57,17 @@
 
 bool LTOModule::isBitcodeFileForTarget(const char *path,
                                        const char *triplePrefix) {
-  error_code ec;
-  MemoryBuffer *buffer = MemoryBuffer::getFile(path, ec);
-  if (buffer == NULL)
+  OwningPtr<MemoryBuffer> buffer;
+  if (MemoryBuffer::getFile(path, buffer))
     return false;
-  return isTargetMatch(buffer, triplePrefix);
+  return isTargetMatch(buffer.take(), triplePrefix);
 }
 
 // Takes ownership of buffer.
 bool LTOModule::isTargetMatch(MemoryBuffer *buffer, const char *triplePrefix) {
   std::string Triple = getBitcodeTargetTriple(buffer, getGlobalContext());
   delete buffer;
-  return (strncmp(Triple.c_str(), triplePrefix, 
+  return (strncmp(Triple.c_str(), triplePrefix,
  		  strlen(triplePrefix)) == 0);
 }
 
@@ -80,9 +79,8 @@
 
 LTOModule *LTOModule::makeLTOModule(const char *path,
                                     std::string &errMsg) {
-  error_code ec;
-  OwningPtr<MemoryBuffer> buffer(MemoryBuffer::getFile(path, ec));
-  if (!buffer) {
+  OwningPtr<MemoryBuffer> buffer;
+  if (error_code ec = MemoryBuffer::getFile(path, buffer)) {
     errMsg = ec.message();
     return NULL;
   }

Modified: llvm/trunk/tools/macho-dump/macho-dump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/macho-dump/macho-dump.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/tools/macho-dump/macho-dump.cpp (original)
+++ llvm/trunk/tools/macho-dump/macho-dump.cpp Wed Dec 15 21:29:14 2010
@@ -366,10 +366,8 @@
 
   // Load the input file.
   std::string ErrorStr;
-  error_code ec;
-  OwningPtr<MemoryBuffer> InputBuffer(
-    MemoryBuffer::getFileOrSTDIN(InputFile, ec));
-  if (!InputBuffer)
+  OwningPtr<MemoryBuffer> InputBuffer;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFile, InputBuffer))
     return Error("unable to read input: '" + ec.message() + "'");
 
   // Construct the Mach-O wrapper object.

Modified: llvm/trunk/utils/FileCheck/FileCheck.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileCheck/FileCheck.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/utils/FileCheck/FileCheck.cpp (original)
+++ llvm/trunk/utils/FileCheck/FileCheck.cpp Wed Dec 15 21:29:14 2010
@@ -16,6 +16,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
@@ -489,13 +490,14 @@
 static bool ReadCheckFile(SourceMgr &SM,
                           std::vector<CheckString> &CheckStrings) {
   // Open the check file, and tell SourceMgr about it.
-  error_code ec;
-  MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(CheckFilename.c_str(), ec);
-  if (F == 0) {
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec =
+        MemoryBuffer::getFileOrSTDIN(CheckFilename.c_str(), File)) {
     errs() << "Could not open check file '" << CheckFilename << "': "
            << ec.message() << '\n';
     return true;
   }
+  MemoryBuffer *F = File.take();
 
   // If we want to canonicalize whitespace, strip excess whitespace from the
   // buffer containing the CHECK lines.
@@ -648,13 +650,14 @@
     return 2;
 
   // Open the file to check and add it to SourceMgr.
-  error_code ec;
-  MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), ec);
-  if (F == 0) {
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec =
+        MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), File)) {
     errs() << "Could not open input file '" << InputFilename << "': "
            << ec.message() << '\n';
     return true;
   }
+  MemoryBuffer *F = File.take();
 
   // Remove duplicate spaces in the input file if requested.
   if (!NoCanonicalizeWhiteSpace)

Modified: llvm/trunk/utils/FileUpdate/FileUpdate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileUpdate/FileUpdate.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/utils/FileUpdate/FileUpdate.cpp (original)
+++ llvm/trunk/utils/FileUpdate/FileUpdate.cpp Wed Dec 15 21:29:14 2010
@@ -15,6 +15,7 @@
 
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MemoryBuffer.h"
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/ToolOutputFile.h"
 #include "llvm/Support/Signals.h"
@@ -43,17 +44,16 @@
   }
 
   // Get the input data.
-  error_code ec;
-  MemoryBuffer *In =
-    MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), ec);
-  if (In == 0) {
+  OwningPtr<MemoryBuffer> In;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), In)) {
     errs() << argv[0] << ": error: Unable to get input '"
            << InputFilename << "': " << ec.message() << '\n';
     return 1;
   }
 
   // Get the output data.
-  MemoryBuffer *Out = MemoryBuffer::getFile(OutputFilename.c_str(), ec);
+  OwningPtr<MemoryBuffer> Out;
+  MemoryBuffer::getFile(OutputFilename.c_str(), Out);
 
   // If the output exists and the contents match, we are done.
   if (Out && In->getBufferSize() == Out->getBufferSize() &&
@@ -65,8 +65,6 @@
     return 0;
   }
 
-  delete Out;
-
   // Otherwise, overwrite the output.
   if (!Quiet)
     errs() << argv[0] << ": Updating '" << OutputFilename

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=121958&r1=121957&r2=121958&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Dec 15 21:29:14 2010
@@ -37,6 +37,7 @@
 #include "ARMDecoderEmitter.h"
 #include "SubtargetEmitter.h"
 #include "TGParser.h"
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/PrettyStackTrace.h"
@@ -190,13 +191,13 @@
                       const std::vector<std::string> &IncludeDirs,
                       SourceMgr &SrcMgr,
                       RecordKeeper &Records) {
-  error_code ec;
-  MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), ec);
-  if (F == 0) {
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File)) {
     errs() << "Could not open input file '" << Filename << "': "
            << ec.message() <<"\n";
     return true;
   }
+  MemoryBuffer *F = File.take();
 
   // Tell SrcMgr about this buffer, which is what TGParser will pick up.
   SrcMgr.AddNewSourceBuffer(F, SMLoc());



From daniel at zuster.org  Wed Dec 15 22:36:42 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 04:36:42 -0000
Subject: [llvm-commits] [llvm] r121959 -
	/llvm/trunk/tools/llvm-dis/llvm-dis.cpp
Message-ID: <20101216043642.F107B2A6C12C@llvm.org>

Author: ddunbar
Date: Wed Dec 15 22:36:42 2010
New Revision: 121959

URL: http://llvm.org/viewvc/llvm-project?rev=121959&view=rev
Log:
Fix some compiler warnings.

Modified:
    llvm/trunk/tools/llvm-dis/llvm-dis.cpp

Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=121959&r1=121958&r2=121959&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original)
+++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Wed Dec 15 22:36:42 2010
@@ -83,11 +83,11 @@
   std::auto_ptr<Module> M;
   OwningPtr<MemoryBuffer> BufferPtr;
 
-  if (ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
+  if ((ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr)))
     ErrorMessage = ec.message();
   else
     M.reset(ParseBitcodeFile(BufferPtr.get(), Context, &ErrorMessage));
-  MemoryBuffer *Buffer = BufferPtr.take();
+  (void) BufferPtr.take();
 
   if (M.get() == 0) {
     errs() << argv[0] << ": ";



From baldrick at free.fr  Thu Dec 16 03:28:25 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 16 Dec 2010 10:28:25 +0100
Subject: [llvm-commits] [llvm] r121905 - in
 /llvm/trunk:	lib/Transforms/InstCombine/InstCombineCompares.cpp
 test/Transforms/InstCombine/overflow.ll
In-Reply-To: <14F4C78C-E068-4BA0-AA72-163161289A63@gmail.com>
References: <20101215223238.CDEC32A6C12C@llvm.org>
	<14F4C78C-E068-4BA0-AA72-163161289A63@gmail.com>
Message-ID: <4D09DBB9.4080208@free.fr>

> Is llvm.sadd.with.overflow implemented on all targets?
> <http://llvm.org/bugs/show_bug.cgi?id=4917#c5><http://llvm.org/bugs/show_bug.cgi?id=4917#c5>http://llvm.org/bugs/show_bug.cgi?id=4917#c5
> suggests that there are problems with mul+overflow, do we legalize add+overflow
> intrinsics for targets that don't support them?

IIRC the problem is with type legalization, for example if you do a 128 bit
mul+overflow it needs to be expanded into 64 bit code.  There's a PR about
this.

Ciao, Duncan.

From fvbommel at gmail.com  Thu Dec 16 03:36:04 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Thu, 16 Dec 2010 10:36:04 +0100
Subject: [llvm-commits] [llvm] r121959 -
	/llvm/trunk/tools/llvm-dis/llvm-dis.cpp
In-Reply-To: <20101216043642.F107B2A6C12C@llvm.org>
References: <20101216043642.F107B2A6C12C@llvm.org>
Message-ID: <AANLkTimdRutKrZ5regx5yFZJxkzZsyKPZsnw5CjqRHGw@mail.gmail.com>

On Thu, Dec 16, 2010 at 5:36 AM, Daniel Dunbar <daniel at zuster.org> wrote:
> ? OwningPtr<MemoryBuffer> BufferPtr;
>
> - ?if (ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
> + ?if ((ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr)))
> ? ? ErrorMessage = ec.message();
> ? else
> ? ? M.reset(ParseBitcodeFile(BufferPtr.get(), Context, &ErrorMessage));
> - ?MemoryBuffer *Buffer = BufferPtr.take();
> + ?(void) BufferPtr.take();

Shouldn't this just use .take() instead of .get() in the 'else'
branch? (BufferPtr should be null if there was an error, right?)


From baldrick at free.fr  Thu Dec 16 03:40:40 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 16 Dec 2010 10:40:40 +0100
Subject: [llvm-commits] [llvm] r121908
	-	/llvm/trunk/lib/Target/X86/X86InstrCompiler.td
In-Reply-To: <20101215225736.C1DD62A6C12C@llvm.org>
References: <20101215225736.C1DD62A6C12C@llvm.org>
Message-ID: <4D09DE98.6050702@free.fr>

Hi Evan,

> Only rr forms of ADD*_DB are commutable.

one of the dragonegg self-host buildbots was unhappy, saying:

LLVM ERROR: Don't know how to commute: %reg16399<def> = ADD32ri8_DB %reg16398, 
4, %EFLAGS<imp-def,dead>; GR32:%reg16399,16398

Hopefully this fixes it - thanks a lot!

Ciao, Duncan.

From baldrick at free.fr  Thu Dec 16 03:40:54 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 16 Dec 2010 09:40:54 -0000
Subject: [llvm-commits] [llvm] r121965 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineCompares.cpp
 test/Transforms/InstCombine/overflow.ll
Message-ID: <20101216094054.53DEA2A6C12C@llvm.org>

Author: baldrick
Date: Thu Dec 16 03:40:54 2010
New Revision: 121965

URL: http://llvm.org/viewvc/llvm-project?rev=121965&view=rev
Log:
Speculatively revert commit 121905 since it looks like it might have broken the
dragonegg self-host buildbot.  Original commit message:

Add an InstCombine transform to recognize instances of manual overflow-safe addition
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics.  This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.

Removed:
    llvm/trunk/test/Transforms/InstCombine/overflow.ll
Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=121965&r1=121964&r2=121965&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Thu Dec 16 03:40:54 2010
@@ -1657,71 +1657,6 @@
   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
     Value *A = 0, *B = 0;
     
-    // Match the following pattern, which is a common idiom when writing
-    // overflow-safe integer arithmetic function.  The source performs an
-    // addition in wider type, and explicitly checks for overflow using
-    // comparisons against INT_MIN and INT_MAX.  Simplify this by using the
-    // sadd_with_overflow intrinsic.
-    // FIXME: This could probably be generalized to handle other overflow-safe
-    // operations if we worked out the formulas to compute the appropriate 
-    // magic constants.
-    // 
-    // INT64 : a, b, sum = a + b
-    // if sum < INT32_MIN || sum > INT_MAX then
-    //   ...
-    // else
-    //   ...
-    {
-    ConstantInt *CI2;
-    
-    // I = icmp ugt (add (add A B) CI2) CI
-    if (I.getPredicate() == ICmpInst::ICMP_UGT &&
-        match(Op0, m_Add(m_Add(m_Value(A), m_Value(B)),
-                   m_ConstantInt(CI2)))) {
-      const IntegerType *WideType = cast<IntegerType>(CI->getType());
-      unsigned WideWidth = WideType->getBitWidth();
-      unsigned NarrowWidth = WideWidth / 2;
-      const IntegerType *NarrowType =
-        IntegerType::get(CI->getContext(), NarrowWidth);
-      
-      // NarrowAllOnes and NarrowSignBit are the magic constants used to
-      // perform an overflow check in the wider type: 0x00..00FF..FF and
-      // 0x00..0010..00 respectively, where the highest set bit in each is
-      // what would be the sign bit in the narrower type.
-      ConstantInt *NarrowAllOnes = cast<ConstantInt>(ConstantInt::get(WideType,
-        APInt::getAllOnesValue(NarrowWidth).zext(WideWidth)));
-      APInt SignBit(WideWidth, 0);
-      SignBit.setBit(NarrowWidth-1);
-      ConstantInt *NarrowSignBit =
-       cast<ConstantInt>(ConstantInt::get(WideType, SignBit));
-      
-      if (CI == NarrowAllOnes && CI2 == NarrowSignBit) {
-        Module *M = I.getParent()->getParent()->getParent();
-        
-        const Type *IntrinsicType = NarrowType;
-        Value *F = Intrinsic::getDeclaration(M, Intrinsic::sadd_with_overflow,
-          &IntrinsicType, 1);
-        
-        // If the pattern matches, truncate the inputs to the narrower type and
-        // use the sadd_with_overflow intrinsic to efficiently compute both the
-        // result and the overflow bit.
-        Value *TruncA = Builder->CreateTrunc(A, NarrowType, A->getName());
-        Value *TruncB = Builder->CreateTrunc(B, NarrowType, B->getName());
-        CallInst *Call = Builder->CreateCall2(F, TruncA, TruncB);
-        Value *Add = Builder->CreateExtractValue(Call, 0);
-        Value *ZExt = Builder->CreateZExt(Add, WideType);
-        
-        // The inner add was the result of the narrow add, zero extended to the
-        // wider type.  Replace it with the result computed by the intrinsic.
-        Instruction *OrigAdd =
-          cast<Instruction>(cast<Instruction>(I.getOperand(0))->getOperand(0));
-        OrigAdd->replaceAllUsesWith(ZExt);
-        
-        return ExtractValueInst::Create(Call, 1);
-      }
-    }
-    }
-    
     // (icmp ne/eq (sub A B) 0) -> (icmp ne/eq A, B)
     if (I.isEquality() && CI->isZero() &&
         match(Op0, m_Sub(m_Value(A), m_Value(B)))) {

Removed: llvm/trunk/test/Transforms/InstCombine/overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/overflow.ll?rev=121964&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/overflow.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/overflow.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: opt -S -instcombine < %s | FileCheck %s
-; <rdar://problem/8558713>
-
-; CHECK: @test1
-define i32 @test1(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK-NOT: sext
-  %conv = sext i32 %a to i64
-  %conv2 = sext i32 %b to i64
-  %add = add nsw i64 %conv2, %conv
-  %add.off = add i64 %add, 2147483648
-; CHECK: llvm.sadd.with.overflow
-  %0 = icmp ugt i64 %add.off, 4294967295
-  br i1 %0, label %if.then, label %if.end
-
-if.then:
-  %call = tail call i32 (...)* @throwAnExceptionOrWhatever() nounwind
-  br label %if.end
-
-if.end:
-; CHECK-NOT: trunc
-  %conv9 = trunc i64 %add to i32
-; CHECK: ret i32
-  ret i32 %conv9
-}
-
-declare i32 @throwAnExceptionOrWhatever(...)



From baldrick at free.fr  Thu Dec 16 03:43:29 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 16 Dec 2010 10:43:29 +0100
Subject: [llvm-commits] [llvm] r121905 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineCompares.cpp
 test/Transforms/InstCombine/overflow.ll
In-Reply-To: <20101215223238.CDEC32A6C12C@llvm.org>
References: <20101215223238.CDEC32A6C12C@llvm.org>
Message-ID: <4D09DF41.2060709@free.fr>

Hi Owen,

> Add an InstCombine transform to recognize instances of manual overflow-safe addition
> (performing the addition in a wider type and explicitly checking for overflow), and
> fold them down to intrinsics.  This currently only supports signed-addition, but could
> be generalized if someone works out the magic constant formulas for other operations.
>
> Fixes<rdar://problem/8558713>.

I've speculatively reverted this because it seems to have broken the dragonegg
self-host builder, see below.

Ciao, Duncan.

llvm[3]: Compiling AlphaRegisterInfo.cpp for Release+Debug+Asserts build
Instruction does not dominate all uses!
   %155 = extractvalue %40 %154, 0
   %130 = zext i16 %155 to i64
Instruction does not dominate all uses!
   %130 = zext i16 %155 to i64
   %131 = call %struct.raw_ostream* 
@_ZN4llvm11raw_ostreamlsEl(%struct.raw_ostream* %129, i64 %130) nounwind, !dbg !1672
Instruction does not dominate all uses!
   %131 = call %struct.raw_ostream* 
@_ZN4llvm11raw_ostreamlsEl(%struct.raw_ostream* %129, i64 %130) nounwind, !dbg !1672
   %132 = getelementptr inbounds %struct.raw_ostream* %131, i64 0, i32 3, !dbg !1682
Instruction does not dominate all uses!
   %132 = getelementptr inbounds %struct.raw_ostream* %131, i64 0, i32 3, !dbg !1682
   %133 = load i8** %132, align 8, !dbg !1682
Instruction does not dominate all uses!
   %133 = load i8** %132, align 8, !dbg !1682
   %134 = getelementptr inbounds i8* %133, i64 17, !dbg !1682
Instruction does not dominate all uses!
   %131 = call %struct.raw_ostream* 
@_ZN4llvm11raw_ostreamlsEl(%struct.raw_ostream* %129, i64 %130) nounwind, !dbg !1672
   %135 = getelementptr inbounds %struct.raw_ostream* %131, i64 0, i32 2, !dbg !1682
Instruction does not dominate all uses!
   %135 = getelementptr inbounds %struct.raw_ostream* %131, i64 0, i32 2, !dbg !1682
   %136 = load i8** %135, align 8, !dbg !1682
Instruction does not dominate all uses!
   %134 = getelementptr inbounds i8* %133, i64 17, !dbg !1682
   %137 = icmp ugt i8* %134, %136, !dbg !1682
Instruction does not dominate all uses!
   %137 = icmp ugt i8* %134, %136, !dbg !1682
   br i1 %137, label %"3.i.i40", label %"4.i.i41", !dbg !1682
Broken module found, compilation aborted!
Stack dump:
0.	Running pass 'Module Verifier' on function 
'@_ZNK4llvm17AlphaRegisterInfo19eliminateFrameIndexENS_14ilist_iteratorINS_12MachineInstrEEEiPNS_12RegScavengerE'
g++: Internal error: Aborted (program cc1plus)
Please submit a full bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.

From fvbommel at gmail.com  Thu Dec 16 06:16:00 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Thu, 16 Dec 2010 12:16:00 -0000
Subject: [llvm-commits] [llvm] r121966 -
	/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp
Message-ID: <20101216121600.91A1B2A6C12C@llvm.org>

Author: fvbommel
Date: Thu Dec 16 06:16:00 2010
New Revision: 121966

URL: http://llvm.org/viewvc/llvm-project?rev=121966&view=rev
Log:
Fix a bug in the loop in JumpThreading::ProcessThreadableEdges() where it could falsely produce a MultipleDestSentinel value if the first predecessor ended with an 'indirectbr'. If that happened, it caused an unnecessary FindMostPopularDest() call.
This wasn't a correctness problem, but it broke the fast path for single-predecessor blocks.

Modified:
    llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=121966&r1=121965&r2=121966&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Thu Dec 16 06:16:00 2010
@@ -984,7 +984,7 @@
     }
   }
 
-  // Okay, now we know the most popular destination.  If there is more than
+  // Okay, now we know the most popular destination.  If there is more than one
   // destination, we need to determine one.  This is arbitrary, but we need
   // to make a deterministic decision.  Pick the first one that appears in the
   // successor list.
@@ -1064,7 +1064,7 @@
     }
 
     // If we have exactly one destination, remember it for efficiency below.
-    if (i == 0)
+    if (PredToDestList.empty())
       OnlyDest = DestBB;
     else if (OnlyDest != DestBB)
       OnlyDest = MultipleDestSentinel;



From fvbommel at gmail.com  Thu Dec 16 06:30:27 2010
From: fvbommel at gmail.com (Frits van Bommel)
Date: Thu, 16 Dec 2010 13:30:27 +0100
Subject: [llvm-commits] [llvm] r121966 -
	/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp
In-Reply-To: <20101216121600.91A1B2A6C12C@llvm.org>
References: <20101216121600.91A1B2A6C12C@llvm.org>
Message-ID: <AANLkTimoYv4i9t2LUWYyzqKtszDLCTsv-26LPAxzBGxU@mail.gmail.com>

On Thu, Dec 16, 2010 at 1:16 PM, Frits van Bommel <fvbommel at gmail.com> wrote:
> This wasn't a correctness problem, but it broke the fast path for single-predecessor blocks.

Sorry, I meant "blocks that have a single predecessor jump threading
can transform".

From baldrick at free.fr  Thu Dec 16 06:47:52 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 16 Dec 2010 13:47:52 +0100
Subject: [llvm-commits] [llvm] r121905 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineCompares.cpp
 test/Transforms/InstCombine/overflow.ll
In-Reply-To: <20101215223238.CDEC32A6C12C@llvm.org>
References: <20101215223238.CDEC32A6C12C@llvm.org>
Message-ID: <4D0A0A78.3090209@free.fr>

Hi Owen,

>> Add an InstCombine transform to recognize instances of manual overflow-safe addition
>> (performing the addition in a wider type and explicitly checking for overflow), and
>> fold them down to intrinsics.  This currently only supports signed-addition, but could
>> be generalized if someone works out the magic constant formulas for other operations.
>>
>> Fixes<rdar://problem/8558713>.
>
> I've speculatively reverted this because it seems to have broken the dragonegg
> self-host builder, see below.

reverting your patch fixed the dragonegg self-host build.

Ciao, Duncan.

From daniel at zuster.org  Thu Dec 16 09:42:18 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 15:42:18 -0000
Subject: [llvm-commits] [llvm] r121968 - /llvm/trunk/.gitignore
Message-ID: <20101216154218.95DFB2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 09:42:18 2010
New Revision: 121968

URL: http://llvm.org/viewvc/llvm-project?rev=121968&view=rev
Log:
Add some more .gitignore entries.

Modified:
    llvm/trunk/.gitignore

Modified: llvm/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=121968&r1=121967&r2=121968&view=diff
==============================================================================
--- llvm/trunk/.gitignore (original)
+++ llvm/trunk/.gitignore Thu Dec 16 09:42:18 2010
@@ -1,3 +1,12 @@
 tools/clang
 
 *.pyc
+*~
+.gitignore
+.gitusers
+projects/test-suite
+projects/test-suite-externals
+projects/compiler-rt
+projects/libcxx
+cscope.files
+cscope.out



From daniel at zuster.org  Thu Dec 16 09:42:26 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 15:42:26 -0000
Subject: [llvm-commits] [llvm] r121969 - /llvm/trunk/tools/Makefile
Message-ID: <20101216154226.6E8232A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 09:42:26 2010
New Revision: 121969

URL: http://llvm.org/viewvc/llvm-project?rev=121969&view=rev
Log:
build: Fix ONLY_TOOLS to not build lto etc. unless specified.

Modified:
    llvm/trunk/tools/Makefile

Modified: llvm/trunk/tools/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=121969&r1=121968&r2=121969&view=diff
==============================================================================
--- llvm/trunk/tools/Makefile (original)
+++ llvm/trunk/tools/Makefile Thu Dec 16 09:42:26 2010
@@ -34,6 +34,7 @@
 
 # These libraries build as dynamic libraries (.dylib /.so), they can only be
 # built if ENABLE_PIC is set.
+ifndef ONLY_TOOLS
 ifeq ($(ENABLE_PIC),1)
   # gold only builds if binutils is around.  It requires "lto" to build before
   # it so it is added to DIRS.
@@ -57,6 +58,7 @@
 ifdef LLVM_HAS_POLLY
   PARALLEL_DIRS += polly
 endif
+endif
 
 # On Win32, loadable modules can be built with ENABLE_SHARED.
 ifneq ($(ENABLE_SHARED),1)



From daniel at zuster.org  Thu Dec 16 09:42:31 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 15:42:31 -0000
Subject: [llvm-commits] [llvm] r121970 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20101216154231.B71512A6C12D@llvm.org>

Author: ddunbar
Date: Thu Dec 16 09:42:31 2010
New Revision: 121970

URL: http://llvm.org/viewvc/llvm-project?rev=121970&view=rev
Log:
MC/Mach-O: Use fixup info instead of hard coded list.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=121970&r1=121969&r2=121970&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 09:42:31 2010
@@ -50,24 +50,6 @@
   }
 }
 
-static bool isFixupKindPCRel(unsigned Kind) {
-  switch (Kind) {
-  default:
-    return false;
-  case FK_PCRel_1:
-  case FK_PCRel_2:
-  case FK_PCRel_4:
-  case X86::reloc_riprel_4byte:
-  case X86::reloc_riprel_4byte_movq_load:
-    return true;
-  }
-}
-
-static bool isFixupKindRIPRel(unsigned Kind) {
-  return Kind == X86::reloc_riprel_4byte ||
-    Kind == X86::reloc_riprel_4byte_movq_load;
-}
-
 static bool doesSymbolRequireExternRelocation(MCSymbolData *SD) {
   // Undefined symbols are always extern.
   if (SD->Symbol->isUndefined())
@@ -179,6 +161,18 @@
     }
   };
 
+  /// @name Utility Methods
+  /// @{
+
+  bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
+    const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo(
+      (MCFixupKind) Kind);
+
+    return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
+  }
+
+  /// @}
+
   /// @name Relocation Data
   /// @{
 
@@ -489,11 +483,15 @@
   //  - Input errors, where something cannot be correctly encoded. 'as' allows
   //    these through in many cases.
 
+  static bool isFixupKindRIPRel(unsigned Kind) {
+    return Kind == X86::reloc_riprel_4byte ||
+      Kind == X86::reloc_riprel_4byte_movq_load;
+  }
   void RecordX86_64Relocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
                               const MCFragment *Fragment,
                               const MCFixup &Fixup, MCValue Target,
                               uint64_t &FixedValue) {
-    unsigned IsPCRel = isFixupKindPCRel(Fixup.getKind());
+    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
     unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
     unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
 
@@ -731,7 +729,7 @@
                                  const MCFixup &Fixup, MCValue Target,
                                  uint64_t &FixedValue) {
     uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned IsPCRel = isFixupKindPCRel(Fixup.getKind());
+    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
     unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
     unsigned Type = macho::RIT_Vanilla;
 
@@ -841,7 +839,7 @@
       return;
     }
 
-    unsigned IsPCRel = isFixupKindPCRel(Fixup.getKind());
+    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
     unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
 
     // If this is a 32-bit TLVP reloc it's handled a bit differently.



From grosbach at apple.com  Thu Dec 16 10:00:42 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 16 Dec 2010 08:00:42 -0800
Subject: [llvm-commits] [llvm] r121949 - in /llvm/trunk:
	include/llvm/MC/MCStreamer.h include/llvm/Target/TargetRegistry.h
	lib/CodeGen/LLVMTargetMachine.cpp lib/MC/MCAsmStreamer.cpp
	lib/Target/PTX/PTXMCAsmStreamer.cpp
	lib/Target/PTX/PTXTargetMachine.cpp tools/llvm-mc/llvm-mc.cpp
In-Reply-To: <20101216030559.B41782A6C12D@llvm.org>
References: <20101216030559.B41782A6C12D@llvm.org>
Message-ID: <F08119E4-1869-4E4C-8B06-38CE247FC813@apple.com>

True, but the non-aggression pact achieved was the best alternative. Now if we can only get TargetMachine to the bargaining table...
-j
On Dec 15, 2010, at 7:05 PM, Daniel Dunbar wrote:

> Author: ddunbar
> Date: Wed Dec 15 21:05:59 2010
> New Revision: 121949
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121949&view=rev
> Log:
> MC: Make TargetAsmBackend available to the AsmStreamer.
> - Treaty talks on the non-proliferation of MC objects broke down.
> 
> Modified:
>    llvm/trunk/include/llvm/MC/MCStreamer.h
>    llvm/trunk/include/llvm/Target/TargetRegistry.h
>    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
>    llvm/trunk/lib/MC/MCAsmStreamer.cpp
>    llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp
>    llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
>    llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> 
> Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
> +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Dec 15 21:05:59 2010
> @@ -426,6 +426,10 @@
>   /// \param CE - If given, a code emitter to use to show the instruction
>   /// encoding inline with the assembly. This method takes ownership of \arg CE.
>   ///
> +  /// \param TAB - If given, a target asm backend to use to show the fixup
> +  /// information in conjunction with encoding information. This method takes
> +  /// ownership of \arg TAB.
> +  ///
>   /// \param ShowInst - Whether to show the MCInst representation inline with
>   /// the assembly.
>   MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
> @@ -433,6 +437,7 @@
>                                 bool useLoc,
>                                 MCInstPrinter *InstPrint = 0,
>                                 MCCodeEmitter *CE = 0,
> +                                TargetAsmBackend *TAB = 0,
>                                 bool ShowInst = false);
> 
>   /// createMachOStreamer - Create a machine code streamer which will generate
> 
> Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Wed Dec 15 21:05:59 2010
> @@ -46,6 +46,7 @@
>                                 bool useLoc,
>                                 MCInstPrinter *InstPrint,
>                                 MCCodeEmitter *CE,
> +                                TargetAsmBackend *TAB,
>                                 bool ShowInst);
> 
>   /// Target - Wrapper for Target specific information.
> @@ -95,6 +96,7 @@
>                                              bool useLoc,
>                                              MCInstPrinter *InstPrint,
>                                              MCCodeEmitter *CE,
> +                                             TargetAsmBackend *TAB,
>                                              bool ShowInst);
> 
>   private:
> @@ -323,10 +325,11 @@
>                                   bool useLoc,
>                                   MCInstPrinter *InstPrint,
>                                   MCCodeEmitter *CE,
> +                                  TargetAsmBackend *TAB,
>                                   bool ShowInst) const {
>       // AsmStreamerCtorFn is default to llvm::createAsmStreamer
>       return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc,
> -                               InstPrint, CE, ShowInst);
> +                               InstPrint, CE, TAB, ShowInst);
>     }
> 
>     /// @}
> 
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Dec 15 21:05:59 2010
> @@ -143,14 +143,17 @@
> 
>     // Create a code emitter if asked to show the encoding.
>     MCCodeEmitter *MCE = 0;
> -    if (ShowMCEncoding)
> +    TargetAsmBackend *TAB = 0;
> +    if (ShowMCEncoding) {
>       MCE = getTarget().createCodeEmitter(*this, *Context);
> +      TAB = getTarget().createAsmBackend(TargetTriple);
> +    }
> 
>     MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
>                                                   getVerboseAsm(),
>                                                   hasMCUseLoc(),
>                                                   InstPrinter,
> -                                                  MCE,
> +                                                  MCE, TAB,
>                                                   ShowMCInst);
>     AsmStreamer.reset(S);
>     break;
> 
> Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Dec 15 21:05:59 2010
> @@ -23,8 +23,9 @@
> #include "llvm/Support/MathExtras.h"
> #include "llvm/Support/Format.h"
> #include "llvm/Support/FormattedStream.h"
> -#include "llvm/Target/TargetLoweringObjectFile.h"
> +#include "llvm/Target/TargetAsmBackend.h"
> #include "llvm/Target/TargetAsmInfo.h"
> +#include "llvm/Target/TargetLoweringObjectFile.h"
> using namespace llvm;
> 
> namespace {
> @@ -34,6 +35,7 @@
>   const MCAsmInfo &MAI;
>   OwningPtr<MCInstPrinter> InstPrinter;
>   OwningPtr<MCCodeEmitter> Emitter;
> +  OwningPtr<TargetAsmBackend> AsmBackend;
> 
>   SmallString<128> CommentToEmit;
>   raw_svector_ostream CommentStream;
> @@ -48,10 +50,12 @@
>   MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
>                 bool isVerboseAsm,
>                 bool useLoc,
> -                MCInstPrinter *printer, MCCodeEmitter *emitter, bool showInst)
> +                MCInstPrinter *printer, MCCodeEmitter *emitter,
> +                TargetAsmBackend *asmbackend,
> +                bool showInst)
>     : MCStreamer(Context), OS(os), MAI(Context.getAsmInfo()),
> -      InstPrinter(printer), Emitter(emitter), CommentStream(CommentToEmit),
> -      IsVerboseAsm(isVerboseAsm),
> +      InstPrinter(printer), Emitter(emitter), AsmBackend(asmbackend),
> +      CommentStream(CommentToEmit), IsVerboseAsm(isVerboseAsm),
>       ShowInst(showInst), UseLoc(useLoc) {
>     if (InstPrinter && IsVerboseAsm)
>       InstPrinter->setCommentStream(CommentStream);
> @@ -893,8 +897,8 @@
> MCStreamer *llvm::createAsmStreamer(MCContext &Context,
>                                     formatted_raw_ostream &OS,
>                                     bool isVerboseAsm, bool useLoc,
> -                                    MCInstPrinter *IP,
> -                                    MCCodeEmitter *CE, bool ShowInst) {
> +                                    MCInstPrinter *IP, MCCodeEmitter *CE,
> +                                    TargetAsmBackend *TAB, bool ShowInst) {
>   return new MCAsmStreamer(Context, OS, isVerboseAsm, useLoc,
> -                           IP, CE, ShowInst);
> +                           IP, CE, TAB, ShowInst);
> }
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp Wed Dec 15 21:05:59 2010
> @@ -540,7 +540,8 @@
>                                    formatted_raw_ostream &OS,
>                                    bool isVerboseAsm, bool useLoc,
>                                    MCInstPrinter *IP,
> -                                   MCCodeEmitter *CE, bool ShowInst) {
> +                                   MCCodeEmitter *CE, TargetAsmBackend *TAB,
> +                                   bool ShowInst) {
>     return new PTXMCAsmStreamer(Context, OS, isVerboseAsm, useLoc,
>                                 IP, CE, ShowInst);
>   }
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Dec 15 21:05:59 2010
> @@ -24,6 +24,7 @@
>                                    bool isVerboseAsm, bool useLoc,
>                                    MCInstPrinter *InstPrint,
>                                    MCCodeEmitter *CE,
> +                                   TargetAsmBackend *TAB,
>                                    bool ShowInst);
> }
> 
> 
> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=121949&r1=121948&r2=121949&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Dec 15 21:05:59 2010
> @@ -340,10 +340,14 @@
>     MCInstPrinter *IP =
>       TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
>     MCCodeEmitter *CE = 0;
> -    if (ShowEncoding)
> +    TargetAsmBackend *TAB = 0;
> +    if (ShowEncoding) {
>       CE = TheTarget->createCodeEmitter(*TM, Ctx);
> +      TAB = TheTarget->createAsmBackend(TripleName);
> +    }
>     Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true,
> -                                           /*useLoc*/ true, IP, CE, ShowInst));
> +                                           /*useLoc*/ true, IP, CE, TAB,
> +                                           ShowInst));
>   } else if (FileType == OFT_Null) {
>     Str.reset(createNullStreamer(Ctx));
>   } else {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From daniel at zuster.org  Thu Dec 16 10:08:33 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 16:08:33 -0000
Subject: [llvm-commits] [llvm] r121971 - in /llvm/trunk:
 include/llvm/MC/MCMachObjectWriter.h include/llvm/MC/MCObjectWriter.h
 lib/MC/MachObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp
 lib/Target/PowerPC/PPCAsmBackend.cpp lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20101216160833.F2CCC2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 10:08:33 2010
New Revision: 121971

URL: http://llvm.org/viewvc/llvm-project?rev=121971&view=rev
Log:
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.

Added:
    llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
Modified:
    llvm/trunk/include/llvm/MC/MCObjectWriter.h
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Added: llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCMachObjectWriter.h?rev=121971&view=auto
==============================================================================
--- llvm/trunk/include/llvm/MC/MCMachObjectWriter.h (added)
+++ llvm/trunk/include/llvm/MC/MCMachObjectWriter.h Thu Dec 16 10:08:33 2010
@@ -0,0 +1,23 @@
+//===-- llvm/MC/MCMachObjectWriter.h - Mach Object Writer -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCMACHOBJECTWRITER_H
+#define LLVM_MC_MCMACHOBJECTWRITER_H
+
+#include "llvm/MC/MCObjectWriter.h"
+
+namespace llvm {
+
+MCObjectWriter *createMachObjectWriter(raw_ostream &OS, bool is64Bit,
+                                       uint32_t CPUType, uint32_t CPUSubtype,
+                                       bool IsLittleEndian);
+
+} // End llvm namespace
+
+#endif

Modified: llvm/trunk/include/llvm/MC/MCObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectWriter.h?rev=121971&r1=121970&r2=121971&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCObjectWriter.h Thu Dec 16 10:08:33 2010
@@ -179,9 +179,6 @@
   static void EncodeULEB128(uint64_t Value, raw_ostream &OS);
 };
 
-MCObjectWriter *createMachObjectWriter(raw_ostream &OS, bool is64Bit,
-                                       uint32_t CPUType, uint32_t CPUSubtype,
-                                       bool IsLittleEndian);
 MCObjectWriter *createELFObjectWriter(raw_ostream &OS, bool is64Bit,
                                       Triple::OSType OSType, uint16_t EMachine,
                                       bool IsLittleEndian,

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=121971&r1=121970&r2=121971&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 10:08:33 2010
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSymbol.h"

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121971&r1=121970&r2=121971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec 16 10:08:33 2010
@@ -14,6 +14,7 @@
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectFormat.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionELF.h"

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=121971&r1=121970&r2=121971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Thu Dec 16 10:08:33 2010
@@ -10,6 +10,7 @@
 #include "llvm/Target/TargetAsmBackend.h"
 #include "PPC.h"
 #include "PPCFixupKinds.h"
+#include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCObjectFormat.h"
 #include "llvm/MC/MCObjectWriter.h"

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=121971&r1=121970&r2=121971&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Thu Dec 16 10:08:33 2010
@@ -14,6 +14,7 @@
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectFormat.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionCOFF.h"



From daniel at zuster.org  Thu Dec 16 10:08:43 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 16:08:43 -0000
Subject: [llvm-commits] [llvm] r121972 -
	/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
Message-ID: <20101216160843.2E3862A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 10:08:43 2010
New Revision: 121972

URL: http://llvm.org/viewvc/llvm-project?rev=121972&view=rev
Log:
Fix indentation (per style guide).

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=121972&r1=121971&r2=121972&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Thu Dec 16 10:08:43 2010
@@ -19,56 +19,56 @@
 using namespace llvm;
 
 namespace {
-  class PPCAsmBackend : public TargetAsmBackend {
-  const Target &TheTarget;
-  public:
-    PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {}
+class PPCAsmBackend : public TargetAsmBackend {
+const Target &TheTarget;
+public:
+  PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {}
+
+  unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
+
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+    const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = {
+      // name                    offset  bits  flags
+      { "fixup_ppc_br24",        6,      24,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_ppc_brcond14",    16,     14,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_ppc_lo16",        16,     16,   0 },
+      { "fixup_ppc_ha16",        16,     16,   0 },
+      { "fixup_ppc_lo14",        16,     14,   0 }
+    };
   
-    unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
-
-    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
-      const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = {
-        // name                    offset  bits  flags
-        { "fixup_ppc_br24",        6,      24,   MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_ppc_brcond14",    16,     14,   MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_ppc_lo16",        16,     16,   0 },
-        { "fixup_ppc_ha16",        16,     16,   0 },
-        { "fixup_ppc_lo14",        16,     14,   0 }
-      };
-    
-      if (Kind < FirstTargetFixupKind)
-        return TargetAsmBackend::getFixupKindInfo(Kind);
-    
-      assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
-             "Invalid kind!");
-      return Infos[Kind - FirstTargetFixupKind];
-    }
-    
-    bool MayNeedRelaxation(const MCInst &Inst) const {
-      // FIXME.
-      return false;
-    }
-    
-    void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
-      // FIXME.
-      assert(0 && "RelaxInstruction() unimplemented");
-    }
-    
-    bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
-      // FIXME: Zero fill for now. That's not right, but at least will get the
-      // section size right.
-      for (uint64_t i = 0; i != Count; ++i)
-        OW->Write8(0);
-      return true;
-    }      
-    
-    unsigned getPointerSize() const {
-      StringRef Name = TheTarget.getName();
-      if (Name == "ppc64") return 8;
-      assert(Name == "ppc32" && "Unknown target name!");
-      return 4;
-    }
-  };
+    if (Kind < FirstTargetFixupKind)
+      return TargetAsmBackend::getFixupKindInfo(Kind);
+  
+    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+           "Invalid kind!");
+    return Infos[Kind - FirstTargetFixupKind];
+  }
+  
+  bool MayNeedRelaxation(const MCInst &Inst) const {
+    // FIXME.
+    return false;
+  }
+  
+  void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
+    // FIXME.
+    assert(0 && "RelaxInstruction() unimplemented");
+  }
+  
+  bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
+    // FIXME: Zero fill for now. That's not right, but at least will get the
+    // section size right.
+    for (uint64_t i = 0; i != Count; ++i)
+      OW->Write8(0);
+    return true;
+  }      
+  
+  unsigned getPointerSize() const {
+    StringRef Name = TheTarget.getName();
+    if (Name == "ppc64") return 8;
+    assert(Name == "ppc32" && "Unknown target name!");
+    return 4;
+  }
+};
 } // end anonymous namespace
 
 



From daniel at zuster.org  Thu Dec 16 10:09:19 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 16:09:19 -0000
Subject: [llvm-commits] [llvm] r121973 - in /llvm/trunk:
 include/llvm/MC/MCMachObjectWriter.h lib/MC/CMakeLists.txt
 lib/MC/MCMachObjectTargetWriter.cpp lib/MC/MachObjectWriter.cpp
 lib/Target/ARM/ARMAsmBackend.cpp lib/Target/PowerPC/PPCAsmBackend.cpp
 lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20101216160919.7A7F52A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 10:09:19 2010
New Revision: 121973

URL: http://llvm.org/viewvc/llvm-project?rev=121973&view=rev
Log:
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.

Added:
    llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp
Modified:
    llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
    llvm/trunk/lib/MC/CMakeLists.txt
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCMachObjectWriter.h?rev=121973&r1=121972&r2=121973&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCMachObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCMachObjectWriter.h Thu Dec 16 10:09:19 2010
@@ -14,7 +14,23 @@
 
 namespace llvm {
 
-MCObjectWriter *createMachObjectWriter(raw_ostream &OS, bool is64Bit,
+class MCMachObjectTargetWriter {
+protected:
+  MCMachObjectTargetWriter();
+
+public:
+  virtual ~MCMachObjectTargetWriter();
+};
+
+/// \brief Construct a new Mach-O writer instance.
+///
+/// This routine takes ownership of the target writer subclass.
+///
+/// \param MOTW - The target specific Mach-O writer subclass.
+/// \param OS - The stream to write to.
+/// \returns The constructed object writer.
+MCObjectWriter *createMachObjectWriter(MCMachObjectTargetWriter *MOTW,
+                                       raw_ostream &OS, bool is64Bit,
                                        uint32_t CPUType, uint32_t CPUSubtype,
                                        bool IsLittleEndian);
 

Modified: llvm/trunk/lib/MC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=121973&r1=121972&r2=121973&view=diff
==============================================================================
--- llvm/trunk/lib/MC/CMakeLists.txt (original)
+++ llvm/trunk/lib/MC/CMakeLists.txt Thu Dec 16 10:09:19 2010
@@ -16,6 +16,7 @@
   MCDwarf.cpp
   MCLoggingStreamer.cpp
   MCMachOStreamer.cpp
+  MCMachObjectTargetWriter.cpp
   MCNullStreamer.cpp
   MCObjectStreamer.cpp
   MCObjectFormat.cpp

Added: llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp?rev=121973&view=auto
==============================================================================
--- llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp (added)
+++ llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp Thu Dec 16 10:09:19 2010
@@ -0,0 +1,18 @@
+//===-- MCMachObjectTargetWriter.cpp - Mach-O Target Writer Subclass ------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCMachObjectWriter.h"
+
+using namespace llvm;
+
+MCMachObjectTargetWriter::MCMachObjectTargetWriter() {
+}
+
+MCMachObjectTargetWriter::~MCMachObjectTargetWriter() {
+}

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=121973&r1=121972&r2=121973&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 10:09:19 2010
@@ -7,12 +7,13 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/MC/MCMachObjectWriter.h"
+#include "llvm/ADT/OwningPtr.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSymbol.h"
@@ -162,17 +163,8 @@
     }
   };
 
-  /// @name Utility Methods
-  /// @{
-
-  bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
-    const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo(
-      (MCFixupKind) Kind);
-
-    return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
-  }
-
-  /// @}
+  /// The target specific Mach-O writer instance.
+  llvm::OwningPtr<MCMachObjectTargetWriter> TargetObjectWriter;
 
   /// @name Relocation Data
   /// @{
@@ -192,6 +184,19 @@
 
   /// @}
 
+private:
+  /// @name Utility Methods
+  /// @{
+
+  bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
+    const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo(
+      (MCFixupKind) Kind);
+
+    return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
+  }
+
+  /// @}
+
   SectionAddrMap SectionAddress;
   uint64_t getSectionAddress(const MCSectionData* SD) const {
     return SectionAddress.lookup(SD);
@@ -226,10 +231,10 @@
   uint32_t CPUSubtype;
 
 public:
-  MachObjectWriter(raw_ostream &_OS,
+  MachObjectWriter(MCMachObjectTargetWriter *MOTW, raw_ostream &_OS,
                    bool _Is64Bit, uint32_t _CPUType, uint32_t _CPUSubtype,
                    bool _IsLittleEndian)
-    : MCObjectWriter(_OS, _IsLittleEndian),
+    : MCObjectWriter(_OS, _IsLittleEndian), TargetObjectWriter(MOTW),
       Is64Bit(_Is64Bit), CPUType(_CPUType), CPUSubtype(_CPUSubtype) {
   }
 
@@ -1321,9 +1326,11 @@
 
 }
 
-MCObjectWriter *llvm::createMachObjectWriter(raw_ostream &OS, bool is64Bit,
+MCObjectWriter *llvm::createMachObjectWriter(MCMachObjectTargetWriter *MOTW,
+                                             raw_ostream &OS, bool is64Bit,
                                              uint32_t CPUType,
                                              uint32_t CPUSubtype,
                                              bool IsLittleEndian) {
-  return new MachObjectWriter(OS, is64Bit, CPUType, CPUSubtype, IsLittleEndian);
+  return new MachObjectWriter(MOTW, OS, is64Bit, CPUType, CPUSubtype,
+                              IsLittleEndian);
 }

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121973&r1=121972&r2=121973&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec 16 10:09:19 2010
@@ -28,6 +28,9 @@
 using namespace llvm;
 
 namespace {
+class ARMMachObjectWriter : public MCMachObjectTargetWriter {
+};
+
 class ARMAsmBackend : public TargetAsmBackend {
   bool isThumbMode;  // Currently emitting Thumb code.
 public:
@@ -382,7 +385,8 @@
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
     // FIXME: Subtarget info should be derived. Force v7 for now.
-    return createMachObjectWriter(OS, /*Is64Bit=*/false,
+    return createMachObjectWriter(new ARMMachObjectWriter,
+                                  OS, /*Is64Bit=*/false,
                                   object::mach::CTM_ARM,
                                   object::mach::CSARM_V7,
                                   /*IsLittleEndian=*/true);

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=121973&r1=121972&r2=121973&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Thu Dec 16 10:09:19 2010
@@ -19,6 +19,9 @@
 using namespace llvm;
 
 namespace {
+class PPCMachObjectWriter : public MCMachObjectTargetWriter {
+};
+
 class PPCAsmBackend : public TargetAsmBackend {
 const Target &TheTarget;
 public:
@@ -92,7 +95,8 @@
     
     MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
       bool is64 = getPointerSize() == 8;
-      return createMachObjectWriter(OS, /*Is64Bit=*/is64,
+      return createMachObjectWriter(new PPCMachObjectWriter,
+                                    OS, /*Is64Bit=*/is64,
                                     (is64 ? object::mach::CTM_PowerPC64 :
                                      object::mach::CTM_PowerPC),
                                     object::mach::CSPPC_ALL,

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=121973&r1=121972&r2=121973&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Thu Dec 16 10:09:19 2010
@@ -46,6 +46,9 @@
 }
 
 namespace {
+class X86MachObjectWriter : public MCMachObjectTargetWriter {
+};
+
 class X86AsmBackend : public TargetAsmBackend {
 public:
   X86AsmBackend(const Target &T)
@@ -362,7 +365,8 @@
     : DarwinX86AsmBackend(T) {}
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
-    return createMachObjectWriter(OS, /*Is64Bit=*/false,
+    return createMachObjectWriter(new X86MachObjectWriter,
+                                  OS, /*Is64Bit=*/false,
                                   object::mach::CTM_i386,
                                   object::mach::CSX86_ALL,
                                   /*IsLittleEndian=*/true);
@@ -377,7 +381,8 @@
   }
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
-    return createMachObjectWriter(OS, /*Is64Bit=*/true,
+    return createMachObjectWriter(new X86MachObjectWriter,
+                                  OS, /*Is64Bit=*/true,
                                   object::mach::CTM_x86_64,
                                   object::mach::CSX86_ALL,
                                   /*IsLittleEndian=*/true);



From bigcheesegs at gmail.com  Thu Dec 16 10:23:30 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Thu, 16 Dec 2010 16:23:30 -0000
Subject: [llvm-commits] [llvm] r121974 -
	/llvm/trunk/tools/llvm-dis/llvm-dis.cpp
Message-ID: <20101216162330.45A912A6C12C@llvm.org>

Author: mspencer
Date: Thu Dec 16 10:23:30 2010
New Revision: 121974

URL: http://llvm.org/viewvc/llvm-project?rev=121974&view=rev
Log:
Fix whitespace.

Modified:
    llvm/trunk/tools/llvm-dis/llvm-dis.cpp

Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=121974&r1=121973&r2=121974&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original)
+++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Thu Dec 16 10:23:30 2010
@@ -49,7 +49,7 @@
                 cl::desc("Add informational comments to the .ll file"));
 
 namespace {
-  
+
 class CommentWriter : public AssemblyAnnotationWriter {
 public:
   void emitFunctionAnnot(const Function *F,
@@ -59,23 +59,23 @@
   }
   void printInfoComment(const Value &V, formatted_raw_ostream &OS) {
     if (V.getType()->isVoidTy()) return;
-      
+
     OS.PadToColumn(50);
     OS << "; [#uses=" << V.getNumUses() << ']';  // Output # uses
   }
 };
-  
+
 } // end anon namespace
 
 int main(int argc, char **argv) {
   // Print a stack trace if we signal out.
   sys::PrintStackTraceOnErrorSignal();
   PrettyStackTraceProgram X(argc, argv);
-  
+
   LLVMContext &Context = getGlobalContext();
   llvm_shutdown_obj Y;  // Call llvm_shutdown() on exit.
-  
-  
+
+
   cl::ParseCommandLineOptions(argc, argv, "llvm .bc -> .ll disassembler\n");
 
   std::string ErrorMessage;
@@ -97,11 +97,11 @@
       errs() << "bitcode didn't read correctly.\n";
     return 1;
   }
-  
+
   // Just use stdout.  We won't actually print anything on it.
   if (DontPrint)
     OutputFilename = "-";
-  
+
   if (OutputFilename.empty()) { // Unspecified output, infer it.
     if (InputFilename == "-") {
       OutputFilename = "-";
@@ -117,7 +117,7 @@
   }
 
   std::string ErrorInfo;
-  OwningPtr<tool_output_file> 
+  OwningPtr<tool_output_file>
   Out(new tool_output_file(OutputFilename.c_str(), ErrorInfo,
                            raw_fd_ostream::F_Binary));
   if (!ErrorInfo.empty()) {
@@ -128,7 +128,7 @@
   OwningPtr<AssemblyAnnotationWriter> Annotator;
   if (ShowAnnotations)
     Annotator.reset(new CommentWriter());
-  
+
   // All that llvm-dis does is write the assembly to a file.
   if (!DontPrint)
     M->print(Out->os(), Annotator.get());



From bigcheesegs at gmail.com  Thu Dec 16 10:23:38 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Thu, 16 Dec 2010 16:23:38 -0000
Subject: [llvm-commits] [llvm] r121975 -
	/llvm/trunk/tools/llvm-dis/llvm-dis.cpp
Message-ID: <20101216162338.510BC2A6C12C@llvm.org>

Author: mspencer
Date: Thu Dec 16 10:23:38 2010
New Revision: 121975

URL: http://llvm.org/viewvc/llvm-project?rev=121975&view=rev
Log:
llvm-dis: Simplify MemoryBuffer usage.

Modified:
    llvm/trunk/tools/llvm-dis/llvm-dis.cpp

Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=121975&r1=121974&r2=121975&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original)
+++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Thu Dec 16 10:23:38 2010
@@ -79,15 +79,13 @@
   cl::ParseCommandLineOptions(argc, argv, "llvm .bc -> .ll disassembler\n");
 
   std::string ErrorMessage;
-  error_code ec;
   std::auto_ptr<Module> M;
   OwningPtr<MemoryBuffer> BufferPtr;
 
-  if ((ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr)))
+  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
     ErrorMessage = ec.message();
   else
-    M.reset(ParseBitcodeFile(BufferPtr.get(), Context, &ErrorMessage));
-  (void) BufferPtr.take();
+    M.reset(ParseBitcodeFile(BufferPtr.take(), Context, &ErrorMessage));
 
   if (M.get() == 0) {
     errs() << argv[0] << ": ";



From greened at obbligato.org  Thu Dec 16 10:32:43 2010
From: greened at obbligato.org (David A. Greene)
Date: Thu, 16 Dec 2010 10:32:43 -0600
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
	(Jason Kim's message of "Tue, 14 Dec 2010 16:21:16 -0800")
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	<nngy67sm3r7.fsf@royale.us.cray.com>
	<AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
Message-ID: <nng8vzplluc.fsf@royale.us.cray.com>

Jason Kim <jasonwkim at google.com> writes:

>
> 1. Please have one canonical list of executables (including things
> like (elf/macho/coff)-dump that are used by test/ and prepend the

I don't see elf-dump and coff-dump.  Where are they?

                               -Dave

From greened at obbligato.org  Thu Dec 16 10:34:33 2010
From: greened at obbligato.org (David A. Greene)
Date: Thu, 16 Dec 2010 10:34:33 -0600
Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed?
In-Reply-To: <AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
	(Jason Kim's message of "Tue, 14 Dec 2010 16:21:16 -0800")
References: <nnglj3to4aw.fsf@royale.us.cray.com>
	<AANLkTi=nKnnEx8GG6E4UOoex0QAhsET6DO8sU_5dxKRt@mail.gmail.com>
	<nngy67sm3r7.fsf@royale.us.cray.com>
	<AANLkTikiUTyKS_pDFsr+d2Lg8dUqM2_Y6oP9OBX9b8uX@mail.gmail.com>
Message-ID: <nng4oadllra.fsf@royale.us.cray.com>

Jason Kim <jasonwkim at google.com> writes:

> 1. Please have one canonical list of executables (including things
> like (elf/macho/coff)-dump that are used by test/ and prepend the

Ignore last message.  I found them.

                               -Dave

From daniel at zuster.org  Thu Dec 16 11:21:02 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 17:21:02 -0000
Subject: [llvm-commits] [llvm] r121981 - in /llvm/trunk:
 include/llvm/MC/MCMachObjectWriter.h lib/MC/MCMachObjectTargetWriter.cpp
 lib/MC/MachObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp
 lib/Target/PowerPC/PPCAsmBackend.cpp lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20101216172102.4575D2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 11:21:02 2010
New Revision: 121981

URL: http://llvm.org/viewvc/llvm-project?rev=121981&view=rev
Log:
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific

interface.

Modified:
    llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
    llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCMachObjectWriter.h?rev=121981&r1=121980&r2=121981&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCMachObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCMachObjectWriter.h Thu Dec 16 11:21:02 2010
@@ -11,15 +11,30 @@
 #define LLVM_MC_MCMACHOBJECTWRITER_H
 
 #include "llvm/MC/MCObjectWriter.h"
+#include "llvm/Support/DataTypes.h"
 
 namespace llvm {
 
 class MCMachObjectTargetWriter {
+  const unsigned Is64Bit : 1;
+  const uint32_t CPUType;
+  const uint32_t CPUSubtype;
+
 protected:
-  MCMachObjectTargetWriter();
+  MCMachObjectTargetWriter(bool Is64Bit_, uint32_t CPUType_,
+                           uint32_t CPUSubtype_);
 
 public:
   virtual ~MCMachObjectTargetWriter();
+
+  /// @name Accessors
+  /// @{
+
+  bool is64Bit() const { return Is64Bit; }
+  uint32_t getCPUType() const { return CPUType; }
+  uint32_t getCPUSubtype() const { return CPUSubtype; }
+
+  /// @}
 };
 
 /// \brief Construct a new Mach-O writer instance.
@@ -30,9 +45,7 @@
 /// \param OS - The stream to write to.
 /// \returns The constructed object writer.
 MCObjectWriter *createMachObjectWriter(MCMachObjectTargetWriter *MOTW,
-                                       raw_ostream &OS, bool is64Bit,
-                                       uint32_t CPUType, uint32_t CPUSubtype,
-                                       bool IsLittleEndian);
+                                       raw_ostream &OS, bool IsLittleEndian);
 
 } // End llvm namespace
 

Modified: llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp?rev=121981&r1=121980&r2=121981&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp (original)
+++ llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp Thu Dec 16 11:21:02 2010
@@ -11,7 +11,9 @@
 
 using namespace llvm;
 
-MCMachObjectTargetWriter::MCMachObjectTargetWriter() {
+MCMachObjectTargetWriter::MCMachObjectTargetWriter(
+  bool Is64Bit_, uint32_t CPUType_, uint32_t CPUSubtype_)
+  : Is64Bit(Is64Bit_), CPUType(CPUType_), CPUSubtype(CPUSubtype_) {
 }
 
 MCMachObjectTargetWriter::~MCMachObjectTargetWriter() {

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=121981&r1=121980&r2=121981&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 11:21:02 2010
@@ -225,19 +225,19 @@
     return OffsetToAlignment(EndAddr, NextSD.getAlignment());
   }
 
-  unsigned Is64Bit : 1;
-
-  uint32_t CPUType;
-  uint32_t CPUSubtype;
-
 public:
   MachObjectWriter(MCMachObjectTargetWriter *MOTW, raw_ostream &_OS,
-                   bool _Is64Bit, uint32_t _CPUType, uint32_t _CPUSubtype,
                    bool _IsLittleEndian)
-    : MCObjectWriter(_OS, _IsLittleEndian), TargetObjectWriter(MOTW),
-      Is64Bit(_Is64Bit), CPUType(_CPUType), CPUSubtype(_CPUSubtype) {
+    : MCObjectWriter(_OS, _IsLittleEndian), TargetObjectWriter(MOTW) {
   }
 
+  /// @name Target Writer Proxy Accessors
+  /// @{
+
+  bool is64Bit() const { return TargetObjectWriter->is64Bit(); }
+
+  /// @}
+
   void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,
                    bool SubsectionsViaSymbols) {
     uint32_t Flags = 0;
@@ -251,19 +251,19 @@
     uint64_t Start = OS.tell();
     (void) Start;
 
-    Write32(Is64Bit ? macho::HM_Object64 : macho::HM_Object32);
+    Write32(is64Bit() ? macho::HM_Object64 : macho::HM_Object32);
 
-    Write32(CPUType);
-    Write32(CPUSubtype);
+    Write32(TargetObjectWriter->getCPUType());
+    Write32(TargetObjectWriter->getCPUSubtype());
 
     Write32(macho::HFT_Object);
     Write32(NumLoadCommands);
     Write32(LoadCommandsSize);
     Write32(Flags);
-    if (Is64Bit)
+    if (is64Bit())
       Write32(0); // reserved
 
-    assert(OS.tell() - Start == Is64Bit ? 
+    assert(OS.tell() - Start == is64Bit() ? 
            macho::Header64Size : macho::Header32Size);
   }
 
@@ -281,15 +281,16 @@
     uint64_t Start = OS.tell();
     (void) Start;
 
-    unsigned SegmentLoadCommandSize = Is64Bit ? macho::SegmentLoadCommand64Size:
+    unsigned SegmentLoadCommandSize =
+      is64Bit() ? macho::SegmentLoadCommand64Size:
       macho::SegmentLoadCommand32Size;
-    Write32(Is64Bit ? macho::LCT_Segment64 : macho::LCT_Segment);
+    Write32(is64Bit() ? macho::LCT_Segment64 : macho::LCT_Segment);
     Write32(SegmentLoadCommandSize +
-            NumSections * (Is64Bit ? macho::Section64Size :
+            NumSections * (is64Bit() ? macho::Section64Size :
                            macho::Section32Size));
 
     WriteBytes("", 16);
-    if (Is64Bit) {
+    if (is64Bit()) {
       Write64(0); // vmaddr
       Write64(VMSize); // vmsize
       Write64(SectionDataStartOffset); // file offset
@@ -328,7 +329,7 @@
     const MCSectionMachO &Section = cast<MCSectionMachO>(SD.getSection());
     WriteBytes(Section.getSectionName(), 16);
     WriteBytes(Section.getSegmentName(), 16);
-    if (Is64Bit) {
+    if (is64Bit()) {
       Write64(getSectionAddress(&SD)); // address
       Write64(SectionSize); // size
     } else {
@@ -348,10 +349,10 @@
     Write32(Flags);
     Write32(IndirectSymBase.lookup(&SD)); // reserved1
     Write32(Section.getStubSize()); // reserved2
-    if (Is64Bit)
+    if (is64Bit())
       Write32(0); // reserved3
 
-    assert(OS.tell() - Start == Is64Bit ? macho::Section64Size :
+    assert(OS.tell() - Start == is64Bit() ? macho::Section64Size :
            macho::Section32Size);
   }
 
@@ -469,7 +470,7 @@
     // The Mach-O streamer uses the lowest 16-bits of the flags for the 'desc'
     // value.
     Write16(Flags);
-    if (Is64Bit)
+    if (is64Bit())
       Write64(Address);
     else
       Write32(Address);
@@ -798,7 +799,7 @@
                             const MCFixup &Fixup, MCValue Target,
                             uint64_t &FixedValue) {
     assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
-           !Is64Bit &&
+           !is64Bit() &&
            "Should only be called with a 32-bit TLVP relocation!");
 
     unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
@@ -840,7 +841,7 @@
   void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
                         const MCFragment *Fragment, const MCFixup &Fixup,
                         MCValue Target, uint64_t &FixedValue) {
-    if (Is64Bit) {
+    if (is64Bit()) {
       RecordX86_64Relocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
       return;
     }
@@ -1164,7 +1165,7 @@
     // The section data starts after the header, the segment load command (and
     // section headers) and the symbol table.
     unsigned NumLoadCommands = 1;
-    uint64_t LoadCommandsSize = Is64Bit ?
+    uint64_t LoadCommandsSize = is64Bit() ?
       macho::SegmentLoadCommand64Size + NumSections * macho::Section64Size :
       macho::SegmentLoadCommand32Size + NumSections * macho::Section32Size;
 
@@ -1179,7 +1180,7 @@
 
     // Compute the total size of the section data, as well as its file size and
     // vm size.
-    uint64_t SectionDataStart = (Is64Bit ? macho::Header64Size :
+    uint64_t SectionDataStart = (is64Bit() ? macho::Header64Size :
                                  macho::Header32Size) + LoadCommandsSize;
     uint64_t SectionDataSize = 0;
     uint64_t SectionDataFileSize = 0;
@@ -1247,7 +1248,7 @@
 
       // The string table is written after symbol table.
       uint64_t StringTableOffset =
-        SymbolTableOffset + NumSymTabSymbols * (Is64Bit ? macho::Nlist64Size :
+        SymbolTableOffset + NumSymTabSymbols * (is64Bit() ? macho::Nlist64Size :
                                                 macho::Nlist32Size);
       WriteSymtabLoadCommand(SymbolTableOffset, NumSymTabSymbols,
                              StringTableOffset, StringTable.size());
@@ -1327,10 +1328,7 @@
 }
 
 MCObjectWriter *llvm::createMachObjectWriter(MCMachObjectTargetWriter *MOTW,
-                                             raw_ostream &OS, bool is64Bit,
-                                             uint32_t CPUType,
-                                             uint32_t CPUSubtype,
+                                             raw_ostream &OS,
                                              bool IsLittleEndian) {
-  return new MachObjectWriter(MOTW, OS, is64Bit, CPUType, CPUSubtype,
-                              IsLittleEndian);
+  return new MachObjectWriter(MOTW, OS, IsLittleEndian);
 }

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121981&r1=121980&r2=121981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec 16 11:21:02 2010
@@ -29,6 +29,10 @@
 
 namespace {
 class ARMMachObjectWriter : public MCMachObjectTargetWriter {
+public:
+  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
+                      uint32_t CPUSubtype)
+    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
 };
 
 class ARMAsmBackend : public TargetAsmBackend {
@@ -385,10 +389,11 @@
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
     // FIXME: Subtarget info should be derived. Force v7 for now.
-    return createMachObjectWriter(new ARMMachObjectWriter,
-                                  OS, /*Is64Bit=*/false,
-                                  object::mach::CTM_ARM,
-                                  object::mach::CSARM_V7,
+    return createMachObjectWriter(new ARMMachObjectWriter(
+                                    /*Is64Bit=*/false,
+                                    object::mach::CTM_ARM,
+                                    object::mach::CSARM_V7),
+                                  OS,
                                   /*IsLittleEndian=*/true);
   }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=121981&r1=121980&r2=121981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Thu Dec 16 11:21:02 2010
@@ -20,6 +20,10 @@
 
 namespace {
 class PPCMachObjectWriter : public MCMachObjectTargetWriter {
+public:
+  PPCMachObjectWriter(bool Is64Bit, uint32_t CPUType,
+                      uint32_t CPUSubtype)
+    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
 };
 
 class PPCAsmBackend : public TargetAsmBackend {
@@ -95,12 +99,12 @@
     
     MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
       bool is64 = getPointerSize() == 8;
-      return createMachObjectWriter(new PPCMachObjectWriter,
-                                    OS, /*Is64Bit=*/is64,
-                                    (is64 ? object::mach::CTM_PowerPC64 :
-                                     object::mach::CTM_PowerPC),
-                                    object::mach::CSPPC_ALL,
-                                    /*IsLittleEndian=*/false);
+      return createMachObjectWriter(new PPCMachObjectWriter(
+                                      /*Is64Bit=*/is64,
+                                      (is64 ? object::mach::CTM_PowerPC64 :
+                                       object::mach::CTM_PowerPC),
+                                      object::mach::CSPPC_ALL),
+                                    OS, /*IsLittleEndian=*/false);
     }
     
     virtual bool doesSectionRequireSymbols(const MCSection &Section) const {

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=121981&r1=121980&r2=121981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Thu Dec 16 11:21:02 2010
@@ -47,6 +47,10 @@
 
 namespace {
 class X86MachObjectWriter : public MCMachObjectTargetWriter {
+public:
+  X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
+                      uint32_t CPUSubtype)
+    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
 };
 
 class X86AsmBackend : public TargetAsmBackend {
@@ -365,11 +369,11 @@
     : DarwinX86AsmBackend(T) {}
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
-    return createMachObjectWriter(new X86MachObjectWriter,
-                                  OS, /*Is64Bit=*/false,
-                                  object::mach::CTM_i386,
-                                  object::mach::CSX86_ALL,
-                                  /*IsLittleEndian=*/true);
+    return createMachObjectWriter(new X86MachObjectWriter(
+                                    /*Is64Bit=*/false,
+                                    object::mach::CTM_i386,
+                                    object::mach::CSX86_ALL),
+                                  OS, /*IsLittleEndian=*/true);
   }
 };
 
@@ -381,11 +385,11 @@
   }
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
-    return createMachObjectWriter(new X86MachObjectWriter,
-                                  OS, /*Is64Bit=*/true,
-                                  object::mach::CTM_x86_64,
-                                  object::mach::CSX86_ALL,
-                                  /*IsLittleEndian=*/true);
+    return createMachObjectWriter(new X86MachObjectWriter(
+                                    /*Is64Bit=*/true,
+                                    object::mach::CTM_x86_64,
+                                    object::mach::CSX86_ALL),
+                                  OS, /*IsLittleEndian=*/true);
   }
 
   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {



From daniel at zuster.org  Thu Dec 16 11:51:14 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 17:51:14 -0000
Subject: [llvm-commits] [llvm] r121985 - /llvm/trunk/.gitignore
Message-ID: <20101216175114.A5D9F2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 11:51:14 2010
New Revision: 121985

URL: http://llvm.org/viewvc/llvm-project?rev=121985&view=rev
Log:
Oops, didn't mean to ignore .gitignore.

Modified:
    llvm/trunk/.gitignore

Modified: llvm/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=121985&r1=121984&r2=121985&view=diff
==============================================================================
--- llvm/trunk/.gitignore (original)
+++ llvm/trunk/.gitignore Thu Dec 16 11:51:14 2010
@@ -2,7 +2,6 @@
 
 *.pyc
 *~
-.gitignore
 .gitusers
 projects/test-suite
 projects/test-suite-externals



From fjahanian at apple.com  Thu Dec 16 12:20:44 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Thu, 16 Dec 2010 18:20:44 -0000
Subject: [llvm-commits] [test-suite] r121987 -
 /test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
Message-ID: <20101216182044.EE26F2A6C12C@llvm.org>

Author: fjahanian
Date: Thu Dec 16 12:20:44 2010
New Revision: 121987

URL: http://llvm.org/viewvc/llvm-project?rev=121987&view=rev
Log:
Another useful test case for imported c++ objects
into blocks. // rdar://8768050


Added:
    test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp

Added: test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp?rev=121987&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp (added)
+++ test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp Thu Dec 16 12:20:44 2010
@@ -0,0 +1,54 @@
+#if defined(__BLOCKS__) && defined(__clang__)
+// rdar://8768050
+#include <stdio.h>
+#include <stdlib.h>
+#include <Block.h>
+#include <auto_zone.h>
+
+static int expected_dtors;
+
+class A {
+private:
+	void *p;
+public:
+	A() throw() {
+		printf("%u\t%p\t%s\n", __LINE__, this, __PRETTY_FUNCTION__);
+	}
+	A(const A &a) throw() : p(a.p) {
+		printf("%u\t%p\t%p\t%s\n", __LINE__, this, &a, __PRETTY_FUNCTION__);
+	}
+	A &operator =(const A &a) throw() {
+		printf("%u\t%p\t%p\t%s\n", __LINE__, this, &a, __PRETTY_FUNCTION__);
+		return *this;
+	}
+	~A() throw() {
+		printf("%u\t%p\t%s\n", __LINE__, this, __PRETTY_FUNCTION__);
+		expected_dtors--;
+		if (expected_dtors < 0) {
+			abort();
+		}
+	}
+	void m() const throw() {
+		printf("%u\t%p\t%s\n", __LINE__, this, __PRETTY_FUNCTION__);
+	}
+};
+
+#endif
+
+int
+main(void)
+{
+#if defined(__BLOCKS__) && defined(__clang__)
+	A a;
+
+	void (^b)(void) = Block_copy(^{
+		a.m();
+	});
+
+	b();
+
+        expected_dtors = 3;
+	Block_release(b);
+#endif
+	return 0;
+}



From daniel at zuster.org  Thu Dec 16 12:36:25 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 18:36:25 -0000
Subject: [llvm-commits] [llvm] r121988 - /llvm/trunk/lib/MC/MCExpr.cpp
Message-ID: <20101216183625.EE5282A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 12:36:25 2010
New Revision: 121988

URL: http://llvm.org/viewvc/llvm-project?rev=121988&view=rev
Log:
MC/Expr: Add a doxyment.

Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=121988&r1=121987&r2=121988&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 12:36:25 2010
@@ -290,6 +290,20 @@
   return true;
 }
 
+/// \brief Evaluate the result of an add between (conceptually) two MCValues.
+///
+/// This routine conceptually attempts to construct an MCValue:
+///   Result = (Result_A - Result_B + Result_Cst)
+/// from two MCValue's LHS and RHS where
+///   Result = LHS + RHS
+/// and
+///   Result = (LHS_A - LHS_B + LHS_Cst) + (RHS_A - RHS_B + RHS_Cst).
+///
+/// This routine attempts to aggresively fold the operands such that the result
+/// is representable in an MCValue, but may not always succeed.
+///
+/// \returns True on success, false if the result is not representable in an
+/// MCValue.
 static bool EvaluateSymbolicAdd(const MCAssembler *Asm,
                                 const MCAsmLayout *Layout,
                                 const SectionAddrMap *Addrs,



From grosbach at apple.com  Thu Dec 16 13:11:16 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 16 Dec 2010 19:11:16 -0000
Subject: [llvm-commits] [llvm] r121990 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMInstrThumb.td
Message-ID: <20101216191116.825982A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec 16 13:11:16 2010
New Revision: 121990

URL: http://llvm.org/viewvc/llvm-project?rev=121990&view=rev
Log:
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=121990&r1=121989&r2=121990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Dec 16 13:11:16 2010
@@ -746,6 +746,14 @@
     }
     return;
   }
+  case ARM::tBfar: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::tBL);
+    TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+          MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
+    OutStreamer.EmitInstruction(TmpInst);
+    return;
+  }
   case ARM::LEApcrel:
   case ARM::tLEApcrel:
   case ARM::t2LEApcrel: {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121990&r1=121989&r2=121990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Dec 16 13:11:16 2010
@@ -535,10 +535,11 @@
   }
 
   // Far jump
-  // FIXME: Encoding. This should probably be a pseudo for tBL
+  // Just a pseudo for a tBL instruction. Needed to let regalloc know about
+  // the clobber of LR.
   let Defs = [LR] in
-  def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
-                    "bl\t$target",[]>;
+  def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
+                          Size4Bytes, IIC_Br, []>;
 
   def tBR_JTr : tPseudoInst<(outs),
                       (ins tGPR:$target, i32imm:$jt, i32imm:$id),



From aggarwa4 at illinois.edu  Thu Dec 16 13:21:58 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 16 Dec 2010 19:21:58 -0000
Subject: [llvm-commits] [poolalloc] r121991 - in /poolalloc/trunk/test:
 TEST.dsgraph.Makefile TEST.dsgraph.report
Message-ID: <20101216192158.5E3242A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Dec 16 13:21:58 2010
New Revision: 121991

URL: http://llvm.org/viewvc/llvm-project?rev=121991&view=rev
Log:
Get more stats in the DSA tests, mostly for type safety.

Modified:
    poolalloc/trunk/test/TEST.dsgraph.Makefile
    poolalloc/trunk/test/TEST.dsgraph.report

Modified: poolalloc/trunk/test/TEST.dsgraph.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsgraph.Makefile?rev=121991&r1=121990&r2=121991&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsgraph.Makefile (original)
+++ poolalloc/trunk/test/TEST.dsgraph.Makefile Thu Dec 16 13:21:58 2010
@@ -22,16 +22,17 @@
 # PASS - The dsgraph pass to run: ds, bu, td
 PASS := td
 
-#ANALYZE_OPTS := -stats -time-passes -only-print-main-ds -dsstats
-ANALYZE_OPTS := -stats -time-passes -dsstats
+ANALYZE_OPTS := -stats -time-passes -disable-output -dsstats
+#ANALYZE_OPTS := -stats -time-passes -dsstats 
 ANALYZE_OPTS +=  -instcount -disable-verify
-MEM := -track-memory -time-passes
+MEM := -track-memory -time-passes -disable-output
 
 $(PROGRAMS_TO_TEST:%=Output/%.$(TEST).report.txt): \
 Output/%.$(TEST).report.txt: Output/%.llvm.bc Output/%.LOC.txt $(LOPT)
 	@# Gather data
-	-($(RUNOPT) -analyze -dsa-$(PASS) $(ANALYZE_OPTS) $<)> $@.time.1 2>&1
-	-($(RUNOPT) -analyze $(MEM) -dsa-$(PASS) -disable-verify $<)> $@.mem.1 2>&1
+	-($(RUNOPT) -dsa-$(PASS)  $(ANALYZE_OPTS) $<)> $@.time.1 2>&1
+	-($(RUNOPT) -dsa-$(PASS) -dsa-stdlib-no-fold  $(ANALYZE_OPTS) $<)> $@.time.2 2>&1
+	-($(RUNOPT)  $(MEM) -dsa-$(PASS) -disable-verify -debug-pass=Details $<)> $@.mem.1 2>&1
 	@# Emit data.
 	@echo "---------------------------------------------------------------" > $@
 	@echo ">>> ========= '$(RELDIR)/$*' Program" >> $@
@@ -63,6 +64,30 @@
 	@/bin/echo -n "ACCESSES UNTYPED: " >> $@
 	- at grep 'Number of loads/stores which are untyped' $@.time.1 >> $@
 	@echo >> $@
+	@/bin/echo -n "ACCESSES TYPED1: " >> $@
+	- at grep 'Number of loads/stores which are access a DSNode with 1 type' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "ACCESSES TYPED2: " >> $@
+	- at grep 'Number of loads/stores which are access a DSNode with 2 type' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "ACCESSES TYPED3: " >> $@
+	- at grep 'Number of loads/stores which are access a DSNode with 3 type' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "ACCESSES TYPED4: " >> $@
+	- at grep 'Number of loads/stores which are access a DSNode with >3 type' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "ACCESSES I: " >> $@
+	- at grep 'Number of loads/stores which are on incomplete nodes' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "ACCESSES E: " >> $@
+	- at grep 'Number of loads/stores which are on external nodes' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "ACCESSES U: " >> $@
+	- at grep 'Number of loads/stores which are on unknown nodes' $@.time.1 >> $@
+	@echo >> $@
+	@/bin/echo -n "STD_LIB_FOLD: " >> $@
+	- at grep 'Number of nodes folded in std lib' $@.time.1 >> $@
+	@echo >> $@
 	@# Emit timing data.
 	@/bin/echo -n "TIME: " >> $@
 	- at grep '  Local Data Structure' $@.time.1 >> $@

Modified: poolalloc/trunk/test/TEST.dsgraph.report
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsgraph.report?rev=121991&r1=121990&r2=121991&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsgraph.report (original)
+++ poolalloc/trunk/test/TEST.dsgraph.report Thu Dec 16 13:21:58 2010
@@ -159,5 +159,16 @@
             ["TypeSafe", "ACCESSES TYPED: *([0-9]+)"],
             ["NonType",  "ACCESSES UNTYPED: *([0-9]+)"],
             ["TS %" , sub { return TypeSafeRatio(@_); }],
+            [],
+            ["Type1", "ACCESSES TYPED1: *([0-9]+)"],
+            ["Type2", "ACCESSES TYPED2: *([0-9]+)"],
+            ["Type3", "ACCESSES TYPED3: *([0-9]+)"],
+            ["Type4", "ACCESSES TYPED4: *([0-9]+)"],
+            ["I", "ACCESSES I: *([0-9]+)"],
+            ["E", "ACCESSES E: *([0-9]+)"],
+            ["U", "ACCESSES U: *([0-9]+)"],
+            ["U", "ACCESSES U: *([0-9]+)"],
             []
+# Nodes Folded
+            ["StdLibFold", "STD_LIB_FOLD: *([0-9]+)"],
            );



From peckw at wesleypeck.com  Thu Dec 16 13:41:31 2010
From: peckw at wesleypeck.com (Wesley Peck)
Date: Thu, 16 Dec 2010 19:41:31 -0000
Subject: [llvm-commits] [llvm] r121994 - in /llvm/trunk/lib/Target/MBlaze:
 MBlazeDelaySlotFiller.cpp MBlazeInstrInfo.td
Message-ID: <20101216194131.EB43C2A6C12C@llvm.org>

Author: peckw
Date: Thu Dec 16 13:41:31 2010
New Revision: 121994

URL: http://llvm.org/viewvc/llvm-project?rev=121994&view=rev
Log:
Fix MBlaze backend call instructions so that arguments passed through registers
are correctly marked as used. This removes a hack where the call instructions
marked all possible argument registers as used in the tablegen description.

Modified:
    llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp?rev=121994&r1=121993&r2=121994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp Thu Dec 16 13:41:31 2010
@@ -146,7 +146,8 @@
       unsigned aop_reg = a->getOperand(aop).getReg();
 
       for (unsigned bop = 0, bend = b->getNumOperands(); bop<bend; ++bop) {
-        if (b->getOperand(bop).isReg() && (!b->getOperand(bop).isImplicit())) {
+        if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit() &&
+            !b->getOperand(bop).isKill()) {
           unsigned bop_reg = b->getOperand(bop).getReg();
           if (aop_reg == bop_reg)
             return true;

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=121994&r1=121993&r2=121994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Thu Dec 16 13:41:31 2010
@@ -19,7 +19,7 @@
 // def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
 def SDT_MBlazeRet     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 def SDT_MBlazeIRet    : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
-def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def SDT_MBlazeJmpLink : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
 def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
 def SDT_MBCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
 
@@ -33,7 +33,8 @@
                            [SDNPHasChain, SDNPOptInFlag]>;
 
 def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
-                           [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
+                           [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag,
+                            SDNPVariadic]>;
 
 def MBWrapper   : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>;
 
@@ -290,7 +291,7 @@
 // Branch and Link Instructions
 //===----------------------------------------------------------------------===//
 class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
-              TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
+              TA<op, flags, (outs), (ins GPR:$link, GPR:$target, variable_ops),
                  !strconcat(instr_asm, "   $link, $target"),
                  [], IIBranch> {
   let ra = br;
@@ -298,7 +299,7 @@
 }
 
 class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
-               TB<op, (outs), (ins GPR:$link, calltarget:$target),
+               TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops),
                   !strconcat(instr_asm, "   $link, $target"),
                   [], IIBranch> {
   let ra = br;
@@ -500,17 +501,16 @@
   def BGED   :  BranchC<0x27, 0x15, 0x000, "bged   ">;
 }
 
-let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
+let isCall =1, hasDelaySlot = 1,
     Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
-    Uses = [R1,R5,R6,R7,R8,R9,R10] in {
+    Uses = [R1] in {
   def BRLID  : BranchLI<0x2E, 0x14, "brlid  ">;
   def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
 }
 
-let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
-    isBarrier = 1,
+let isCall = 1, hasDelaySlot = 1,
     Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
-    Uses = [R1,R5,R6,R7,R8,R9,R10] in {
+    Uses = [R1] in {
   def BRLD   : BranchL<0x26, 0x14, 0x000, "brld   ">;
   def BRALD  : BranchL<0x26, 0x1C, 0x000, "brald  ">;
 }



From stoklund at 2pi.dk  Thu Dec 16 13:46:09 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 16 Dec 2010 19:46:09 -0000
Subject: [llvm-commits] [llvm] r121995 - in /llvm/trunk:
 include/llvm/ADT/IntervalMap.h unittests/ADT/IntervalMapTest.cpp
Message-ID: <20101216194609.BF5C82A6C12C@llvm.org>

Author: stoklund
Date: Thu Dec 16 13:46:09 2010
New Revision: 121995

URL: http://llvm.org/viewvc/llvm-project?rev=121995&view=rev
Log:
Add basic test exposing many bugs.

Modified:
    llvm/trunk/include/llvm/ADT/IntervalMap.h
    llvm/trunk/unittests/ADT/IntervalMapTest.cpp

Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntervalMap.h?rev=121995&r1=121994&r2=121995&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/IntervalMap.h (original)
+++ llvm/trunk/include/llvm/ADT/IntervalMap.h Thu Dec 16 13:46:09 2010
@@ -2036,11 +2036,11 @@
     for (;;) {
       // Make a.end > b.start.
       posA.advanceTo(posB.start());
-      if (!posA.valid() || !Traits::stopLess(posB.end(), posA.start()))
+      if (!posA.valid() || !Traits::stopLess(posB.stop(), posA.start()))
         return;
       // Make b.end > a.start.
       posB.advanceTo(posA.start());
-      if (!posB.valid() || !Traits::stopLess(posA.end(), posB.start()))
+      if (!posB.valid() || !Traits::stopLess(posA.stop(), posB.start()))
         return;
     }
   }
@@ -2068,11 +2068,11 @@
   /// skipA - Move to the next overlap that doesn't involve a().
   void skipA() {
     ++posA;
-    if (!posA.valid() || !Traits::stopLess(posB.end(), posA.start()))
+    if (!posA.valid() || !Traits::stopLess(posB.stop(), posA.start()))
       return;
     // Second half-loop of advance().
     posB.advanceTo(posA.start());
-    if (!posB.valid() || !Traits::stopLess(posA.end(), posB.start()))
+    if (!posB.valid() || !Traits::stopLess(posA.stop(), posB.start()))
       return ;
     advance();
   }
@@ -2080,7 +2080,7 @@
   /// skipB - Move to the next overlap that doesn't involve b().
   void skipB() {
     ++posB;
-    if (!posB.valid() || !Traits::stopLess(posA.end(), posB.start()))
+    if (!posB.valid() || !Traits::stopLess(posA.stop(), posB.start()))
         return;
     advance();
   }
@@ -2088,7 +2088,7 @@
   /// Preincrement - Move to the next overlap.
   IntervalMapOverlaps &operator++() {
     // Bump the iterator that ends first. The other one may have more overlaps.
-    if (Traits::startLess(posB.end(), posA.end()))
+    if (Traits::startLess(posB.stop(), posA.stop()))
       skipB();
     else
       skipA();

Modified: llvm/trunk/unittests/ADT/IntervalMapTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/IntervalMapTest.cpp?rev=121995&r1=121994&r2=121995&view=diff
==============================================================================
--- llvm/trunk/unittests/ADT/IntervalMapTest.cpp (original)
+++ llvm/trunk/unittests/ADT/IntervalMapTest.cpp Thu Dec 16 13:46:09 2010
@@ -550,4 +550,19 @@
 
 }
 
+TEST(IntervalMapOverlapsTest, EmptyMaps) {
+  typedef IntervalMapOverlaps<UUMap,UUMap> UUOverlaps;
+  UUMap::Allocator allocator;
+  UUMap mapA(allocator);
+  UUMap mapB(allocator);
+
+  // empty, empty.
+  EXPECT_FALSE(UUOverlaps(mapA, mapB).valid());
+
+  mapA.insert(1, 2, 3);
+  // full, empty
+  EXPECT_FALSE(UUOverlaps(mapA, mapB).valid());
+  // empty, full
+  EXPECT_FALSE(UUOverlaps(mapB, mapA).valid());
+}
 } // namespace



From aggarwa4 at illinois.edu  Thu Dec 16 14:07:30 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 16 Dec 2010 20:07:30 -0000
Subject: [llvm-commits] [poolalloc] r121998 -
	/poolalloc/trunk/test/TEST.dsgraph.report
Message-ID: <20101216200730.E6E822A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Dec 16 14:07:30 2010
New Revision: 121998

URL: http://llvm.org/viewvc/llvm-project?rev=121998&view=rev
Log:
Fixed typo.

Modified:
    poolalloc/trunk/test/TEST.dsgraph.report

Modified: poolalloc/trunk/test/TEST.dsgraph.report
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsgraph.report?rev=121998&r1=121997&r2=121998&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsgraph.report (original)
+++ poolalloc/trunk/test/TEST.dsgraph.report Thu Dec 16 14:07:30 2010
@@ -168,7 +168,7 @@
             ["E", "ACCESSES E: *([0-9]+)"],
             ["U", "ACCESSES U: *([0-9]+)"],
             ["U", "ACCESSES U: *([0-9]+)"],
-            []
+            [],
 # Nodes Folded
             ["StdLibFold", "STD_LIB_FOLD: *([0-9]+)"],
            );



From criswell at cs.uiuc.edu  Thu Dec 16 15:05:34 2010
From: criswell at cs.uiuc.edu (John Criswell)
Date: Thu, 16 Dec 2010 15:05:34 -0600
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/other.html
Message-ID: <201012162105.oBGL5YlA029893@zion.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

other.html updated: 1.7 -> 1.8
---
Log message:

Added papers on other techniques (such as taint tracking and control-flow
integrity).


---
Diffs of the changes:  (+49 -2)

 other.html |   51 +++++++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 49 insertions(+), 2 deletions(-)


Index: llvm-www/safecode/menagerie/other.html
diff -u llvm-www/safecode/menagerie/other.html:1.7 llvm-www/safecode/menagerie/other.html:1.8
--- llvm-www/safecode/menagerie/other.html:1.7	Fri Jul  2 14:15:04 2010
+++ llvm-www/safecode/menagerie/other.html	Thu Dec 16 15:04:29 2010
@@ -88,7 +88,36 @@
         <br>
         </li>
 
+        <br>
+
+        <li><a href="http://www.crhc.illinois.edu/DEPEND/pubs/papers/DSN_05_Pointer_Taintedness.pdf">
+        <b>
+        Defeating Memory Corruption Attacks via Pointer Taintedness Detection
+        </b></a>
+        <br>
+        Shuo Chen, Jun Xu, Nithin Nakka, Zbigniew Kalbarczyk, and Ravishankar
+        K. Iyer
+        <br>
+        <i>Proceedings of the 2005 International Conference on Dependable
+        Systems and Networks (DSN 2005)</i>,
+        June 2005.
+        <br>
+        </li>
 
+        <br>
+
+        <li><a href="http://www.cs.berkeley.edu/%7Edawnsong/papers/taintcheck.pdf">
+        <b>
+         Dynamic Taint Analysis: Automatic Detection, Analysis, and Signature
+Generation of Exploit Attacks on Commodity Software
+        </b></a>
+        <br>
+        James Newsome and Dawn Song
+        <br>
+        <i>Proceedings of the Network and Distributed Systems Security
+        Symposium </i>, February 2005.
+        <br>
+        </li>
       </ul>
 
       <a name="random"></a>
@@ -201,8 +230,8 @@
         </li>
       </ul>
 
-      <a name="adhoc"></a>
-      <h1>Miscellaneous Papers</h1>
+      <a name="cfi"></a>
+      <h1>Control Flow Integrity Papers</h1>
 
       <ul>
         <li><a href="http://www.csc.ncsu.edu/faculty/jiang/pubs/OAKLAND10.pdf">
@@ -221,6 +250,24 @@
 
         <br>
 
+        <li><a href="http://portal.acm.org/citation.cfm?id=1609956.1609960">
+        <b>
+        Control-flow Integrity Principles, Implementations, and Applications
+        </b></a>
+        <br>
+        Mart??n Abadi, Mihai Budiu, ??lfar Erlingsson, and Jay Ligatti
+        <br>
+        <i>
+        ACM Transactions on Information and System Security (TISSEC 2009)</i>,
+        October 2009.
+        <br>
+        </li>
+      </ul>
+
+      <a name="adhoc"></a>
+      <h1>Miscellaneous Papers</h1>
+
+      <ul>
         <li><a href="http://portal.acm.org/citation.cfm?id=1755913.1755934">
         <b>
         Defeating Return-Oriented Rootkits with "Return-Less" Kernels




From bigcheesegs at gmail.com  Thu Dec 16 16:37:52 2010
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Thu, 16 Dec 2010 22:37:52 -0000
Subject: [llvm-commits] [llvm] r122004 -
	/llvm/trunk/tools/llvm-dis/llvm-dis.cpp
Message-ID: <20101216223752.604FD2A6C12C@llvm.org>

Author: mspencer
Date: Thu Dec 16 16:37:52 2010
New Revision: 122004

URL: http://llvm.org/viewvc/llvm-project?rev=122004&view=rev
Log:
llvm-dis: Fix memory leak. ParseBitcodeFile should be taking ownership of
the MemoryBuffer*, however, it doesn't seem to delete it.

Modified:
    llvm/trunk/tools/llvm-dis/llvm-dis.cpp

Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=122004&r1=122003&r2=122004&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original)
+++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Thu Dec 16 16:37:52 2010
@@ -80,12 +80,14 @@
 
   std::string ErrorMessage;
   std::auto_ptr<Module> M;
-  OwningPtr<MemoryBuffer> BufferPtr;
 
-  if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
-    ErrorMessage = ec.message();
-  else
-    M.reset(ParseBitcodeFile(BufferPtr.take(), Context, &ErrorMessage));
+  {
+    OwningPtr<MemoryBuffer> BufferPtr;
+    if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
+      ErrorMessage = ec.message();
+    else
+      M.reset(ParseBitcodeFile(BufferPtr.get(), Context, &ErrorMessage));
+  }
 
   if (M.get() == 0) {
     errs() << argv[0] << ": ";



From rafael.espindola at gmail.com  Thu Dec 16 16:50:01 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 16 Dec 2010 22:50:01 -0000
Subject: [llvm-commits] [llvm] r122005 - in /llvm/trunk:
 lib/Target/X86/X86MCCodeEmitter.cpp test/MC/ELF/relocation.s
Message-ID: <20101216225001.3964A2A6C12C@llvm.org>

Author: rafael
Date: Thu Dec 16 16:50:01 2010
New Revision: 122005

URL: http://llvm.org/viewvc/llvm-project?rev=122005&view=rev
Log:
Make pushq produce signed relocations.

Modified:
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/ELF/relocation.s

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=122005&r1=122004&r2=122005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Thu Dec 16 16:50:01 2010
@@ -996,7 +996,10 @@
                     Fixups);
     } else {
       unsigned FixupKind;
-      if (MI.getOpcode() == X86::MOV64ri32 || MI.getOpcode() == X86::MOV64mi32)
+      // FIXME: Is there a better way to know that we need a signed relocation?
+      if (MI.getOpcode() == X86::MOV64ri32 ||
+          MI.getOpcode() == X86::MOV64mi32 ||
+          MI.getOpcode() == X86::PUSH64i32)
         FixupKind = X86::reloc_signed_4byte;
       else
         FixupKind = getImmFixupKind(TSFlags);

Modified: llvm/trunk/test/MC/ELF/relocation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relocation.s?rev=122005&r1=122004&r2=122005&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/relocation.s (original)
+++ llvm/trunk/test/MC/ELF/relocation.s Thu Dec 16 16:50:01 2010
@@ -14,6 +14,8 @@
         leaq	foo at TPOFF(%rax), %rax    # R_X86_64_TPOFF32
         leaq	foo at TLSLD(%rip), %rdi    # R_X86_64_TLSLD
         leaq	foo at DTPOFF(%rax), %rcx   # R_X86_64_DTPOFF32
+        pushq    $bar
+
 
 // CHECK:  # Section 0x00000001
 // CHECK: (('sh_name', 0x00000001) # '.text'
@@ -90,3 +92,9 @@
 // CHECK-NEXT:   ('r_sym', 0x00000006)
 // CHECK-NEXT:   ('r_type', 0x00000015)
 // CHECK-NEXT:   ('r_addend', 0x00000000)
+
+// CHECK: # Relocation 0x0000000b
+// CHECK-NEXT:  (('r_offset', 0x0000004e)
+// CHECK-NEXT:   ('r_sym', 0x00000002)
+// CHECK-NEXT:   ('r_type', 0x0000000b)
+// CHECK-NEXT:   ('r_addend', 0x00000000)



From nlewycky at google.com  Thu Dec 16 18:22:54 2010
From: nlewycky at google.com (Nick Lewycky)
Date: Thu, 16 Dec 2010 16:22:54 -0800
Subject: [llvm-commits] patch: make LazyValueInfo non-recursive
Message-ID: <AANLkTikxQVAB8+pb6f=tJQJBZeUDNEHQJk9KAJiFLkO=@mail.gmail.com>

This patch removes all recursion from LazyValueInfo by breaking it up into
five queues and many helper functions. In this patch
 * getValue{InBlock,OnEdge} are now purely externally facing and their
short-circuit cases were sunk
 * getEdgeValue was cloned into hasEdgeValue which has the surprising
side-effect of queueing the blocks we need in order to solve the edge (if
applicable)
 * Having both hasEdgeValue and getEdgeValue means that we use pred_iterator
twice instead of once per edge query. In exchange, I rigged the
getBlockValue queries on PHINodes to use the phi node's list of predecessors
directly instead of pred_iterator.
 * getBlockValue now does a retrieval of the cached value and nothing more,
the compute was broken into four solveBlockValue* methods.

The good news is that it passes make check, a nightly test, and my own
internal testcase (yay!). Please review!

Nick
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From stoklund at 2pi.dk  Thu Dec 16 18:27:58 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 16 Dec 2010 16:27:58 -0800
Subject: [llvm-commits] [test-suite] r121987 -
	/test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
In-Reply-To: <20101216182044.EE26F2A6C12C@llvm.org>
References: <20101216182044.EE26F2A6C12C@llvm.org>
Message-ID: <7A8D9F0B-EFA8-47C9-B05B-E3D90056532B@2pi.dk>


On Dec 16, 2010, at 10:20 AM, Fariborz Jahanian wrote:

> Author: fjahanian
> Date: Thu Dec 16 12:20:44 2010
> New Revision: 121987
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121987&view=rev
> Log:
> Another useful test case for imported c++ objects
> into blocks. // rdar://8768050
> 
> 
> Added:
>    test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
> 
> Added: test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
> URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp?rev=121987&view=auto
> ==============================================================================
> --- test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp (added)
> +++ test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp Thu Dec 16 12:20:44 2010
> @@ -0,0 +1,54 @@
> +#if defined(__BLOCKS__) && defined(__clang__)
> +// rdar://8768050
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <Block.h>
> +#include <auto_zone.h>

Hi Fariborz,

My Mac OS X 10.6.5 doesn't have an auto_zone.h anywhere.

/jakob

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From rafael.espindola at gmail.com  Thu Dec 16 18:28:02 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 17 Dec 2010 00:28:02 -0000
Subject: [llvm-commits] [llvm] r122006 - in /llvm/trunk: lib/MC/MCDwarf.cpp
	test/MC/ELF/cfi.s
Message-ID: <20101217002802.3B9A62A6C12C@llvm.org>

Author: rafael
Date: Thu Dec 16 18:28:02 2010
New Revision: 122006

URL: http://llvm.org/viewvc/llvm-project?rev=122006&view=rev
Log:
"Fix" FDE alignment to match what gas does.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp
    llvm/trunk/test/MC/ELF/cfi.s

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=122006&r1=122005&r2=122006&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Dec 16 18:28:02 2010
@@ -569,11 +569,9 @@
   return *sectionStart;
 }
 
-static void EmitFDE(MCStreamer &streamer,
-                    const MCSymbol &cieStart,
-                    const MCDwarfFrameInfo &frame) {
-  MCContext &context = streamer.getContext();
-  const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
+static MCSymbol *EmitFDE(MCStreamer &streamer,
+                         const MCSymbol &cieStart,
+                         const MCDwarfFrameInfo &frame) {
   MCSymbol *fdeStart = streamer.getContext().CreateTempSymbol();
   MCSymbol *fdeEnd = streamer.getContext().CreateTempSymbol();
 
@@ -602,12 +600,22 @@
   // Call Frame Instructions
 
   // Padding
-  streamer.EmitValueToAlignment(asmInfo.getPointerSize());
-  streamer.EmitLabel(fdeEnd);
+  streamer.EmitValueToAlignment(4);
+
+  return fdeEnd;
 }
 
 void MCDwarfFrameEmitter::Emit(MCStreamer &streamer) {
+  const MCContext &context = streamer.getContext();
+  const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
   const MCSymbol &cieStart = EmitCIE(streamer);
-  for (unsigned i = 0, n = streamer.getNumFrameInfos(); i < n; ++i)
-    EmitFDE(streamer, cieStart, streamer.getFrameInfo(i));
+  MCSymbol *fdeEnd = NULL;
+  for (unsigned i = 0, n = streamer.getNumFrameInfos(); i < n; ++i) {
+    fdeEnd = EmitFDE(streamer, cieStart, streamer.getFrameInfo(i));
+    if (i != n - 1)
+      streamer.EmitLabel(fdeEnd);
+  }
+  streamer.EmitValueToAlignment(asmInfo.getPointerSize());
+  if (fdeEnd)
+    streamer.EmitLabel(fdeEnd);
 }

Modified: llvm/trunk/test/MC/ELF/cfi.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/cfi.s?rev=122006&r1=122005&r2=122006&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/cfi.s (original)
+++ llvm/trunk/test/MC/ELF/cfi.s Thu Dec 16 18:28:02 2010
@@ -1,6 +1,11 @@
 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump  --dump-section-data | FileCheck %s
 
-f:
+f1:
+        .cfi_startproc
+        nop
+        .cfi_endproc
+
+f2:
         .cfi_startproc
         nop
         .cfi_endproc
@@ -11,12 +16,12 @@
 // CHECK-NEXT:  ('sh_flags', 0x00000002)
 // CHECK-NEXT:  ('sh_addr', 0x00000000)
 // CHECK-NEXT:  ('sh_offset', 0x00000048)
-// CHECK-NEXT:  ('sh_size', 0x00000030)
+// CHECK-NEXT:  ('sh_size', 0x00000040)
 // CHECK-NEXT:  ('sh_link', 0x00000000)
 // CHECK-NEXT:  ('sh_info', 0x00000000)
 // CHECK-NEXT:  ('sh_addralign', 0x00000008)
 // CHECK-NEXT:  ('sh_entsize', 0x00000000)
-// CHECK-NEXT:  ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 01000000 00000000 00000000')
+// CHECK-NEXT:  ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 10000000 1c000000 00000000 01000000 00000000 10000000 30000000 00000000 01000000 00000000')
 // CHECK-NEXT: ),
 
 // CHECK:      # Section 0x00000008
@@ -24,8 +29,8 @@
 // CHECK-NEXT:  ('sh_type', 0x00000004)
 // CHECK-NEXT:  ('sh_flags', 0x00000000)
 // CHECK-NEXT:  ('sh_addr', 0x00000000)
-// CHECK-NEXT:  ('sh_offset', 0x00000158)
-// CHECK-NEXT:  ('sh_size', 0x00000018)
+// CHECK-NEXT:  ('sh_offset', 0x00000180)
+// CHECK-NEXT:  ('sh_size', 0x00000030)
 // CHECK-NEXT:  ('sh_link', 0x00000006)
 // CHECK-NEXT:  ('sh_info', 0x00000004)
 // CHECK-NEXT:  ('sh_addralign', 0x00000008)
@@ -33,9 +38,15 @@
 // CHECK-NEXT:  ('_relocations', [
 // CHECK-NEXT:   # Relocation 0x00000000
 // CHECK-NEXT:   (('r_offset', 0x00000020)
-// CHECK-NEXT:    ('r_sym', 0x00000002)
+// CHECK-NEXT:    ('r_sym', 0x00000003)
 // CHECK-NEXT:    ('r_type', 0x00000002)
 // CHECK-NEXT:    ('r_addend', 0x00000000)
 // CHECK-NEXT:   ),
+// CHECK-NEXT:   # Relocation 0x00000001
+// CHECK-NEXT:   (('r_offset', 0x00000034)
+// CHECK-NEXT:    ('r_sym', 0x00000003)
+// CHECK-NEXT:    ('r_type', 0x00000002)
+// CHECK-NEXT:    ('r_addend', 0x00000001)
+// CHECK-NEXT:   ),
 // CHECK-NEXT:  ])
 // CHECK-NEXT: ),



From fjahanian at apple.com  Thu Dec 16 18:33:54 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Fri, 17 Dec 2010 00:33:54 -0000
Subject: [llvm-commits] [test-suite] r122007 -
 /test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
Message-ID: <20101217003354.6612B2A6C12C@llvm.org>

Author: fjahanian
Date: Thu Dec 16 18:33:54 2010
New Revision: 122007

URL: http://llvm.org/viewvc/llvm-project?rev=122007&view=rev
Log:
Removed unneeded header file.


Modified:
    test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp

Modified: test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp?rev=122007&r1=122006&r2=122007&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp (original)
+++ test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp Thu Dec 16 18:33:54 2010
@@ -3,7 +3,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <Block.h>
-#include <auto_zone.h>
 
 static int expected_dtors;
 



From fjahanian at apple.com  Thu Dec 16 18:36:48 2010
From: fjahanian at apple.com (jahanian)
Date: Thu, 16 Dec 2010 16:36:48 -0800
Subject: [llvm-commits] [test-suite] r121987 -
	/test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
In-Reply-To: <7A8D9F0B-EFA8-47C9-B05B-E3D90056532B@2pi.dk>
References: <20101216182044.EE26F2A6C12C@llvm.org>
	<7A8D9F0B-EFA8-47C9-B05B-E3D90056532B@2pi.dk>
Message-ID: <356A119E-4BC8-4F63-9780-EBC7BBA6948C@apple.com>


On Dec 16, 2010, at 4:27 PM, Jakob Stoklund Olesen wrote:

> 
> On Dec 16, 2010, at 10:20 AM, Fariborz Jahanian wrote:
> 
>> Author: fjahanian
>> Date: Thu Dec 16 12:20:44 2010
>> New Revision: 121987
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=121987&view=rev
>> Log:
>> Another useful test case for imported c++ objects
>> into blocks. // rdar://8768050
>> 
>> 
>> Added:
>>   test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
>> 
>> Added: test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp
>> URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp?rev=121987&view=auto
>> ==============================================================================
>> --- test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp (added)
>> +++ test-suite/trunk/SingleSource/UnitTests/block-copied-in-cxxobj-1.cpp Thu Dec 16 12:20:44 2010
>> @@ -0,0 +1,54 @@
>> +#if defined(__BLOCKS__) && defined(__clang__)
>> +// rdar://8768050
>> +#include <stdio.h>
>> +#include <stdlib.h>
>> +#include <Block.h>
>> +#include <auto_zone.h>
> 
> Hi Fariborz,
> 
> My Mac OS X 10.6.5 doesn't have an auto_zone.h anywhere.

Thanks. Was't needed and removed.

- fariborz

> 
> /jakob
> 



From daniel at zuster.org  Thu Dec 16 19:07:20 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 01:07:20 -0000
Subject: [llvm-commits] [llvm] r122008 - /llvm/trunk/lib/MC/MCExpr.cpp
Message-ID: <20101217010720.3E5482A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 19:07:20 2010
New Revision: 122008

URL: http://llvm.org/viewvc/llvm-project?rev=122008&view=rev
Log:
MC/Expr: Simplify (and add a FIXME).

Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122008&r1=122007&r2=122008&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 19:07:20 2010
@@ -311,13 +311,21 @@
                                 const MCValue &LHS,const MCSymbolRefExpr *RHS_A,
                                 const MCSymbolRefExpr *RHS_B, int64_t RHS_Cst,
                                 MCValue &Res) {
-  // We can't add or subtract two symbols.
-  if ((LHS.getSymA() && RHS_A) ||
-      (LHS.getSymB() && RHS_B))
+  // FIXME: This routine (and other evaluation parts) are *incredibly* sloppy
+  // about dealing with modifiers. This will ultimately bite us, one day.
+  const MCSymbolRefExpr *LHS_A = LHS.getSymA();
+  const MCSymbolRefExpr *LHS_B = LHS.getSymB();
+  int64_t LHS_Cst = LHS.getConstant();
+
+  // Fold the result constant immediately.
+  int64_t Result_Cst = LHS_Cst + RHS_Cst;
+
+  // We can't represent the addition or subtraction of two symbols.
+  if ((LHS_A && RHS_A) || (LHS_B && RHS_B))
     return false;
 
-  const MCSymbolRefExpr *A = LHS.getSymA() ? LHS.getSymA() : RHS_A;
-  const MCSymbolRefExpr *B = LHS.getSymB() ? LHS.getSymB() : RHS_B;
+  const MCSymbolRefExpr *A = LHS_A ? LHS_A : RHS_A;
+  const MCSymbolRefExpr *B = LHS_B ? LHS_B : RHS_B;
   if (B) {
     // If we have a negated symbol, then we must have also have a non-negated
     // symbol in order to encode the expression. We can do this check later to
@@ -343,8 +351,7 @@
       if (AD.getFragment() == BD.getFragment()) {
         Res = MCValue::get(+ AD.getOffset()
                            - BD.getOffset()
-                           + LHS.getConstant()
-                           + RHS_Cst);
+                           + Result_Cst);
         return true;
       }
 
@@ -353,8 +360,7 @@
         const MCSectionData &SecB = *BD.getFragment()->getParent();
         int64_t Val = + Layout->getSymbolOffset(&AD)
                       - Layout->getSymbolOffset(&BD)
-                      + LHS.getConstant()
-                      + RHS_Cst;
+                      + Result_Cst;
         if (&SecA != &SecB) {
           if (!Addrs)
             return false;
@@ -367,7 +373,7 @@
     }
   }
 
-  Res = MCValue::get(A, B, LHS.getConstant() + RHS_Cst);
+  Res = MCValue::get(A, B, Result_Cst);
   return true;
 }
 



From daniel at zuster.org  Thu Dec 16 19:07:23 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 01:07:23 -0000
Subject: [llvm-commits] [llvm] r122009 - /llvm/trunk/lib/MC/MCExpr.cpp
Message-ID: <20101217010723.2975D2A6C12D@llvm.org>

Author: ddunbar
Date: Thu Dec 16 19:07:22 2010
New Revision: 122009

URL: http://llvm.org/viewvc/llvm-project?rev=122009&view=rev
Log:
Write => in a more normal form.

Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122009&r1=122008&r2=122009&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 19:07:22 2010
@@ -338,7 +338,8 @@
   // Absolutize symbol differences between defined symbols when we have a
   // layout object and the target requests it.
 
-  assert(!(Layout && !Asm));
+  assert((!Layout || Asm) &&
+         "Must have an assembler object if layout is given!");
 
   if (Asm && A && B) {
     const MCSymbol &SA = A->getSymbol();



From daniel at zuster.org  Thu Dec 16 19:07:25 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 01:07:25 -0000
Subject: [llvm-commits] [llvm] r122010 -
	/llvm/trunk/include/llvm/MC/MCAsmLayout.h
Message-ID: <20101217010725.F18F52A6C12E@llvm.org>

Author: ddunbar
Date: Thu Dec 16 19:07:25 2010
New Revision: 122010

URL: http://llvm.org/viewvc/llvm-project?rev=122010&view=rev
Log:
Fix 80-col viola.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmLayout.h

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=122010&r1=122009&r2=122010&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Thu Dec 16 19:07:25 2010
@@ -53,8 +53,8 @@
   /// Get the assembler object this is a layout for.
   MCAssembler &getAssembler() const { return Assembler; }
 
-  /// \brief Invalidate all following fragments because a fragment has been resized. The
-  /// fragments size should have already been updated.
+  /// \brief Invalidate all following fragments because a fragment has been
+  /// resized. The fragments size should have already been updated.
   void Invalidate(MCFragment *F);
 
   /// \brief Perform layout for a single fragment, assuming that the previous



From daniel at zuster.org  Thu Dec 16 19:07:28 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 01:07:28 -0000
Subject: [llvm-commits] [llvm] r122011 - /llvm/trunk/lib/MC/MCExpr.cpp
Message-ID: <20101217010728.97D8A2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 19:07:28 2010
New Revision: 122011

URL: http://llvm.org/viewvc/llvm-project?rev=122011&view=rev
Log:
MC: Simplify (remove unnecessary MCAssembler argument, obsoleted by containment
in MCAsmLayout).

Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122011&r1=122010&r2=122011&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 19:07:28 2010
@@ -304,8 +304,7 @@
 ///
 /// \returns True on success, false if the result is not representable in an
 /// MCValue.
-static bool EvaluateSymbolicAdd(const MCAssembler *Asm,
-                                const MCAsmLayout *Layout,
+static bool EvaluateSymbolicAdd(const MCAsmLayout *Layout,
                                 const SectionAddrMap *Addrs,
                                 bool InSet,
                                 const MCValue &LHS,const MCSymbolRefExpr *RHS_A,
@@ -337,17 +336,14 @@
 
   // Absolutize symbol differences between defined symbols when we have a
   // layout object and the target requests it.
-
-  assert((!Layout || Asm) &&
-         "Must have an assembler object if layout is given!");
-
-  if (Asm && A && B) {
+  if (Layout && A && B) {
+    const MCAssembler &Asm = Layout->getAssembler();
     const MCSymbol &SA = A->getSymbol();
     const MCSymbol &SB = B->getSymbol();
-    const MCObjectFormat &F = Asm->getBackend().getObjectFormat();
+    const MCObjectFormat &F = Asm.getBackend().getObjectFormat();
     if (SA.isDefined() && SB.isDefined() && F.isAbsolute(InSet, SA, SB)) {
-      MCSymbolData &AD = Asm->getSymbolData(A->getSymbol());
-      MCSymbolData &BD = Asm->getSymbolData(B->getSymbol());
+      MCSymbolData &AD = Asm.getSymbolData(A->getSymbol());
+      MCSymbolData &BD = Asm.getSymbolData(B->getSymbol());
 
       if (AD.getFragment() == BD.getFragment()) {
         Res = MCValue::get(+ AD.getOffset()
@@ -474,13 +470,13 @@
         return false;
       case MCBinaryExpr::Sub:
         // Negate RHS and add.
-        return EvaluateSymbolicAdd(Asm, Layout, Addrs, InSet, LHSValue,
+        return EvaluateSymbolicAdd(Layout, Addrs, InSet, LHSValue,
                                    RHSValue.getSymB(), RHSValue.getSymA(),
                                    -RHSValue.getConstant(),
                                    Res);
 
       case MCBinaryExpr::Add:
-        return EvaluateSymbolicAdd(Asm, Layout, Addrs, InSet, LHSValue,
+        return EvaluateSymbolicAdd(Layout, Addrs, InSet, LHSValue,
                                    RHSValue.getSymA(), RHSValue.getSymB(),
                                    RHSValue.getConstant(),
                                    Res);



From daniel at zuster.org  Thu Dec 16 19:07:32 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 01:07:32 -0000
Subject: [llvm-commits] [llvm] r122012 - in /llvm/trunk:
	include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp
Message-ID: <20101217010732.0AE552A6C12D@llvm.org>

Author: ddunbar
Date: Thu Dec 16 19:07:31 2010
New Revision: 122012

URL: http://llvm.org/viewvc/llvm-project?rev=122012&view=rev
Log:
MC: Remove dead MCAssembler argument -- Rafael, can you check the FIXME I added
here?

Modified:
    llvm/trunk/include/llvm/MC/MCExpr.h
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=122012&r1=122011&r2=122012&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Thu Dec 16 19:07:31 2010
@@ -50,8 +50,7 @@
 protected:
   explicit MCExpr(ExprKind _Kind) : Kind(_Kind) {}
 
-  bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm,
-                                 const MCAsmLayout *Layout,
+  bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
                                  const SectionAddrMap *Addrs,
                                  bool InSet) const;
 public:

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122012&r1=122011&r2=122012&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 19:07:31 2010
@@ -267,7 +267,8 @@
     return true;
   }
 
-  if (!EvaluateAsRelocatableImpl(Value, Asm, Layout, Addrs, Addrs) ||
+  // FIXME: This use of Addrs is wrong, right?
+  if (!EvaluateAsRelocatableImpl(Value, Layout, Addrs, /*InSet=*/Addrs) ||
       !Value.isAbsolute()) {
     // EvaluateAsAbsolute is defined to return the "current value" of
     // the expression if we are given a Layout object, even in cases
@@ -377,14 +378,12 @@
 bool MCExpr::EvaluateAsRelocatable(MCValue &Res,
                                    const MCAsmLayout *Layout) const {
   if (Layout)
-    return EvaluateAsRelocatableImpl(Res, &Layout->getAssembler(), Layout,
-                                     0, false);
+    return EvaluateAsRelocatableImpl(Res, Layout, 0, false);
   else
-    return EvaluateAsRelocatableImpl(Res, 0, 0, 0, false);
+    return EvaluateAsRelocatableImpl(Res, 0, 0, false);
 }
 
 bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
-                                       const MCAssembler *Asm,
                                        const MCAsmLayout *Layout,
                                        const SectionAddrMap *Addrs,
                                        bool InSet) const {
@@ -404,10 +403,8 @@
 
     // Evaluate recursively if this is a variable.
     if (Sym.isVariable() && SRE->getKind() == MCSymbolRefExpr::VK_None) {
-      bool Ret = Sym.getVariableValue()->EvaluateAsRelocatableImpl(Res, Asm,
-                                                                   Layout,
-                                                                   Addrs,
-                                                                   true);
+      bool Ret = Sym.getVariableValue()->EvaluateAsRelocatableImpl(Res, Layout,
+                                                                   Addrs, true);
       // If we failed to simplify this to a constant, let the target
       // handle it.
       if (Ret && !Res.getSymA() && !Res.getSymB())
@@ -422,7 +419,7 @@
     const MCUnaryExpr *AUE = cast<MCUnaryExpr>(this);
     MCValue Value;
 
-    if (!AUE->getSubExpr()->EvaluateAsRelocatableImpl(Value, Asm, Layout,
+    if (!AUE->getSubExpr()->EvaluateAsRelocatableImpl(Value, Layout,
                                                       Addrs, InSet))
       return false;
 
@@ -456,9 +453,9 @@
     const MCBinaryExpr *ABE = cast<MCBinaryExpr>(this);
     MCValue LHSValue, RHSValue;
 
-    if (!ABE->getLHS()->EvaluateAsRelocatableImpl(LHSValue, Asm, Layout,
+    if (!ABE->getLHS()->EvaluateAsRelocatableImpl(LHSValue, Layout,
                                                   Addrs, InSet) ||
-        !ABE->getRHS()->EvaluateAsRelocatableImpl(RHSValue, Asm, Layout,
+        !ABE->getRHS()->EvaluateAsRelocatableImpl(RHSValue, Layout,
                                                   Addrs, InSet))
       return false;
 



From daniel at zuster.org  Thu Dec 16 19:07:35 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 01:07:35 -0000
Subject: [llvm-commits] [llvm] r122013 - in /llvm/trunk:
 include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp lib/MC/MCObjectStreamer.cpp
Message-ID: <20101217010735.8B7932A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 19:07:35 2010
New Revision: 122013

URL: http://llvm.org/viewvc/llvm-project?rev=122013&view=rev
Log:
MC: Remove another dead MCAssembler argument, and update clients.

Modified:
    llvm/trunk/include/llvm/MC/MCExpr.h
    llvm/trunk/lib/MC/MCExpr.cpp
    llvm/trunk/lib/MC/MCObjectStreamer.cpp

Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=122013&r1=122012&r2=122013&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Thu Dec 16 19:07:35 2010
@@ -44,8 +44,7 @@
   MCExpr(const MCExpr&); // DO NOT IMPLEMENT
   void operator=(const MCExpr&); // DO NOT IMPLEMENT
 
-  bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler *Asm,
-                          const MCAsmLayout *Layout,
+  bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout *Layout,
                           const SectionAddrMap *Addrs) const;
 protected:
   explicit MCExpr(ExprKind _Kind) : Kind(_Kind) {}
@@ -77,11 +76,16 @@
   /// values. If not given, then only non-symbolic expressions will be
   /// evaluated.
   /// @result - True on success.
-  bool EvaluateAsAbsolute(int64_t &Res) const;
-  bool EvaluateAsAbsolute(int64_t &Res, const MCAssembler &Asm) const;
-  bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout) const;
+  bool EvaluateAsAbsolute(int64_t &Res) const {
+    return EvaluateAsAbsolute(Res, 0, 0);
+  }
+  bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout) const{
+    return EvaluateAsAbsolute(Res, &Layout, 0);
+  }
   bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout,
-                          const SectionAddrMap &Addrs) const;
+                          const SectionAddrMap &Addrs) const {
+    return EvaluateAsAbsolute(Res, &Layout, &Addrs);
+  }
 
   /// EvaluateAsRelocatable - Try to evaluate the expression to a relocatable
   /// value, i.e. an expression of the fixed form (a - b + constant).

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122013&r1=122012&r2=122013&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 19:07:35 2010
@@ -237,27 +237,7 @@
 
 /* *** */
 
-bool MCExpr::EvaluateAsAbsolute(int64_t &Res) const {
-  return EvaluateAsAbsolute(Res, 0, 0, 0);
-}
-
-bool MCExpr::EvaluateAsAbsolute(int64_t &Res,
-                                const MCAsmLayout &Layout) const {
-  return EvaluateAsAbsolute(Res, &Layout.getAssembler(), &Layout, 0);
-}
-
-bool MCExpr::EvaluateAsAbsolute(int64_t &Res,
-                                const MCAsmLayout &Layout,
-                                const SectionAddrMap &Addrs) const {
-  return EvaluateAsAbsolute(Res, &Layout.getAssembler(), &Layout, &Addrs);
-}
-
-bool MCExpr::EvaluateAsAbsolute(int64_t &Res, const MCAssembler &Asm) const {
-  return EvaluateAsAbsolute(Res, &Asm, 0, 0);
-}
-
-bool MCExpr::EvaluateAsAbsolute(int64_t &Res, const MCAssembler *Asm,
-                                const MCAsmLayout *Layout,
+bool MCExpr::EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout *Layout,
                                 const SectionAddrMap *Addrs) const {
   MCValue Value;
 

Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=122013&r1=122012&r2=122013&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Thu Dec 16 19:07:35 2010
@@ -83,7 +83,7 @@
 
   // Avoid fixups when possible.
   int64_t AbsValue;
-  if (AddValueSymbols(Value)->EvaluateAsAbsolute(AbsValue, getAssembler())) {
+  if (AddValueSymbols(Value)->EvaluateAsAbsolute(AbsValue)) {
     EmitIntValue(AbsValue, Size, AddrSpace);
     return;
   }
@@ -114,7 +114,7 @@
 void MCObjectStreamer::EmitULEB128Value(const MCExpr *Value,
                                         unsigned AddrSpace) {
   int64_t IntValue;
-  if (Value->EvaluateAsAbsolute(IntValue, getAssembler())) {
+  if (Value->EvaluateAsAbsolute(IntValue)) {
     EmitULEB128IntValue(IntValue, AddrSpace);
     return;
   }
@@ -124,7 +124,7 @@
 void MCObjectStreamer::EmitSLEB128Value(const MCExpr *Value,
                                         unsigned AddrSpace) {
   int64_t IntValue;
-  if (Value->EvaluateAsAbsolute(IntValue, getAssembler())) {
+  if (Value->EvaluateAsAbsolute(IntValue)) {
     EmitSLEB128IntValue(IntValue, AddrSpace);
     return;
   }
@@ -204,7 +204,7 @@
     MCBinaryExpr::Create(MCBinaryExpr::Sub, LabelRef, LastLabelRef,
                          getContext());
   int64_t Res;
-  if (AddrDelta->EvaluateAsAbsolute(Res, getAssembler())) {
+  if (AddrDelta->EvaluateAsAbsolute(Res)) {
     MCDwarfLineAddr::Emit(this, LineDelta, Res);
     return;
   }



From gohman at apple.com  Thu Dec 16 19:09:43 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 17 Dec 2010 01:09:43 -0000
Subject: [llvm-commits] [llvm] r122014 - in /llvm/trunk:
 lib/Transforms/Scalar/SimplifyLibCalls.cpp
 test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll
Message-ID: <20101217010943.3AFFA2A6C12C@llvm.org>

Author: djg
Date: Thu Dec 16 19:09:43 2010
New Revision: 122014

URL: http://llvm.org/viewvc/llvm-project?rev=122014&view=rev
Log:
Revert r64460. strtol and friends cannot be marked readonly, even with
a null endptr argument, because they may write to errno.

This fixes a seflhost miscompile observed on Linux targets when TBAA
was enabled.

Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=122014&r1=122013&r2=122014&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Thu Dec 16 19:09:43 2010
@@ -577,7 +577,8 @@
 
     Value *EndPtr = CI->getArgOperand(1);
     if (isa<ConstantPointerNull>(EndPtr)) {
-      CI->setOnlyReadsMemory();
+      // With a null EndPtr, this function won't capture the main argument.
+      // It would be readonly too, except that it still may write to errno.
       CI->addAttribute(1, Attribute::NoCapture);
     }
 

Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll?rev=122014&r1=122013&r2=122014&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/2009-02-12-StrTo.ll Thu Dec 16 19:09:43 2010
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -simplify-libcalls -S > %t
 ; RUN: grep nocapture %t | count 2
 ; RUN: grep null %t | grep nocapture | count 1
-; RUN: grep null %t | grep call | grep readonly | count 1
+; RUN: grep null %t | grep call | not grep readonly
 
 ; Test that we add nocapture to the declaration, and to the second call only.
 



From bob.wilson at apple.com  Thu Dec 16 19:21:03 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 17 Dec 2010 01:21:03 -0000
Subject: [llvm-commits] [llvm] r122015 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20101217012103.7B1962A6C12C@llvm.org>

Author: bwilson
Date: Thu Dec 16 19:21:03 2010
New Revision: 122015

URL: http://llvm.org/viewvc/llvm-project?rev=122015&view=rev
Log:
Neon intrinsic tests need to be compiled for Cortex-A9 for f16 support.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=122015&r1=122014&r2=122015&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Thu Dec 16 19:21:03 2010
@@ -1492,7 +1492,7 @@
 void NeonEmitter::runTests(raw_ostream &OS) {
   OS <<
     "// RUN: %clang_cc1 -triple thumbv7-apple-darwin \\\n"
-    "// RUN:  -target-cpu cortex-a8 -ffreestanding -S -o - %s | FileCheck %s\n"
+    "// RUN:  -target-cpu cortex-a9 -ffreestanding -S -o - %s | FileCheck %s\n"
     "\n"
     "#include <arm_neon.h>\n"
     "\n";



From bob.wilson at apple.com  Thu Dec 16 19:21:05 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 17 Dec 2010 01:21:05 -0000
Subject: [llvm-commits] [llvm] r122016 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <20101217012106.0405A2A6C12D@llvm.org>

Author: bwilson
Date: Thu Dec 16 19:21:05 2010
New Revision: 122016

URL: http://llvm.org/viewvc/llvm-project?rev=122016&view=rev
Log:
Fix a comment typo.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=122016&r1=122015&r2=122016&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Dec 16 19:21:05 2010
@@ -621,8 +621,8 @@
       return false;
   }
 
-  // If destination register has a sub-register index on it, make sure it mtches
-  // the instruction register class.
+  // If destination register has a sub-register index on it, make sure it
+  // matches the instruction register class.
   if (DstSubIdx) {
     const TargetInstrDesc &TID = DefMI->getDesc();
     if (TID.getNumDefs() != 1)



From bob.wilson at apple.com  Thu Dec 16 19:21:08 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 17 Dec 2010 01:21:08 -0000
Subject: [llvm-commits] [llvm] r122017 -
	/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <20101217012108.A3C682A6C12E@llvm.org>

Author: bwilson
Date: Thu Dec 16 19:21:08 2010
New Revision: 122017

URL: http://llvm.org/viewvc/llvm-project?rev=122017&view=rev
Log:
Use PairDRegs to implement ConcatVectors.  No functionality change.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=122017&r1=122016&r2=122017&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Dec 16 19:21:08 2010
@@ -2141,13 +2141,7 @@
   EVT VT = N->getValueType(0);
   if (!VT.is128BitVector() || N->getNumOperands() != 2)
     llvm_unreachable("unexpected CONCAT_VECTORS");
-  DebugLoc dl = N->getDebugLoc();
-  SDValue V0 = N->getOperand(0);
-  SDValue V1 = N->getOperand(1);
-  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
-  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
-  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
-  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
+  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
 }
 
 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {



From bob.wilson at apple.com  Thu Dec 16 19:21:12 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 17 Dec 2010 01:21:12 -0000
Subject: [llvm-commits] [llvm] r122018 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/InstrEmitter.cpp
 lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/ARM/vldlane.ll
Message-ID: <20101217012112.65CC22A6C12C@llvm.org>

Author: bwilson
Date: Thu Dec 16 19:21:12 2010
New Revision: 122018

URL: http://llvm.org/viewvc/llvm-project?rev=122018&view=rev
Log:
Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.
Radar 8776599

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/test/CodeGen/ARM/vldlane.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=122018&r1=122017&r2=122018&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Dec 16 19:21:12 2010
@@ -543,9 +543,7 @@
       const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
       const TargetRegisterClass *SRC =
         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
-      if (!SRC)
-        llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
-      if (SRC != RC) {
+      if (SRC && SRC != RC) {
         MRI->setRegClass(NewVReg, SRC);
         RC = SRC;
       }

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=122018&r1=122017&r2=122018&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Dec 16 19:21:12 2010
@@ -1417,6 +1417,7 @@
     SmallSet<unsigned, 4> Seen;
     for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
       unsigned SrcReg = MI->getOperand(i).getReg();
+      unsigned SubIdx = MI->getOperand(i+1).getImm();
       if (MI->getOperand(i).getSubReg() ||
           TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
         DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
@@ -1436,7 +1437,9 @@
 
       bool isKill = MI->getOperand(i).isKill();
       if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() ||
-          !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI)) {
+          !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
+          !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
+                                         MRI->getRegClass(SrcReg), SubIdx)) {
         // REG_SEQUENCE cannot have duplicated operands, add a copy.
         // Also add an copy if the source is live-in the block. We don't want
         // to end up with a partial-redef of a livein, e.g.
@@ -1465,7 +1468,7 @@
         MachineBasicBlock::iterator InsertLoc = MI;
         MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
                                 MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
-            .addReg(DstReg, RegState::Define, MI->getOperand(i+1).getImm())
+            .addReg(DstReg, RegState::Define, SubIdx)
             .addReg(SrcReg, getKillRegState(isKill));
         MI->getOperand(i).setReg(0);
         if (LV && isKill)

Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=122018&r1=122017&r2=122018&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Thu Dec 16 19:21:12 2010
@@ -432,3 +432,22 @@
 declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly
 declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly
 declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
+
+; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register
+; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
+; we don't currently have a QQQQ_VFP2 super-regclass.  (The "0" for the low
+; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
+define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
+;CHECK: test_qqqq_regsequence_subreg
+;CHECK: vld3.16
+  %tmp63 = extractvalue [6 x i64] %b, 5
+  %tmp64 = zext i64 %tmp63 to i128
+  %tmp65 = shl i128 %tmp64, 64
+  %ins67 = or i128 %tmp65, 0
+  %tmp78 = bitcast i128 %ins67 to <8 x i16>
+  %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2)
+  call void @llvm.trap()
+  unreachable
+}
+
+declare void @llvm.trap() nounwind



From stoklund at 2pi.dk  Thu Dec 16 19:31:49 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 17 Dec 2010 01:31:49 -0000
Subject: [llvm-commits] [llvm] r122019 -
	/llvm/trunk/unittests/ADT/IntervalMapTest.cpp
Message-ID: <20101217013149.47F682A6C12C@llvm.org>

Author: stoklund
Date: Thu Dec 16 19:31:49 2010
New Revision: 122019

URL: http://llvm.org/viewvc/llvm-project?rev=122019&view=rev
Log:
Complete tests for IntervalMapOverlaps.

Modified:
    llvm/trunk/unittests/ADT/IntervalMapTest.cpp

Modified: llvm/trunk/unittests/ADT/IntervalMapTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/IntervalMapTest.cpp?rev=122019&r1=122018&r2=122019&view=diff
==============================================================================
--- llvm/trunk/unittests/ADT/IntervalMapTest.cpp (original)
+++ llvm/trunk/unittests/ADT/IntervalMapTest.cpp Thu Dec 16 19:31:49 2010
@@ -550,7 +550,7 @@
 
 }
 
-TEST(IntervalMapOverlapsTest, EmptyMaps) {
+TEST(IntervalMapOverlapsTest, SmallMaps) {
   typedef IntervalMapOverlaps<UUMap,UUMap> UUOverlaps;
   UUMap::Allocator allocator;
   UUMap mapA(allocator);
@@ -560,9 +560,114 @@
   EXPECT_FALSE(UUOverlaps(mapA, mapB).valid());
 
   mapA.insert(1, 2, 3);
+
   // full, empty
   EXPECT_FALSE(UUOverlaps(mapA, mapB).valid());
   // empty, full
   EXPECT_FALSE(UUOverlaps(mapB, mapA).valid());
+
+  mapB.insert(3, 4, 5);
+
+  // full, full, non-overlapping
+  EXPECT_FALSE(UUOverlaps(mapA, mapB).valid());
+  EXPECT_FALSE(UUOverlaps(mapB, mapA).valid());
+
+  // Add an overlapping segment.
+  mapA.insert(4, 5, 6);
+
+  UUOverlaps AB(mapA, mapB);
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(4u, AB.a().start());
+  EXPECT_EQ(3u, AB.b().start());
+  ++AB;
+  EXPECT_FALSE(AB.valid());
+
+  UUOverlaps BA(mapB, mapA);
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(3u, BA.a().start());
+  EXPECT_EQ(4u, BA.b().start());
+  ++BA;
+  EXPECT_FALSE(BA.valid());
 }
+
+TEST(IntervalMapOverlapsTest, BigMaps) {
+  typedef IntervalMapOverlaps<UUMap,UUMap> UUOverlaps;
+  UUMap::Allocator allocator;
+  UUMap mapA(allocator);
+  UUMap mapB(allocator);
+
+  // [0;4] [10;14] [20;24] ...
+  for (unsigned n = 0; n != 100; ++n)
+    mapA.insert(10*n, 10*n+4, n);
+
+  // [5;6] [15;16] [25;26] ...
+  for (unsigned n = 10; n != 20; ++n)
+    mapB.insert(10*n+5, 10*n+6, n);
+
+  // [208;209] [218;219] ...
+  for (unsigned n = 20; n != 30; ++n)
+    mapB.insert(10*n+8, 10*n+9, n);
+
+  // insert some overlapping segments.
+  mapB.insert(400, 400, 400);
+  mapB.insert(401, 401, 401);
+  mapB.insert(402, 500, 402);
+  mapB.insert(600, 601, 402);
+
+  UUOverlaps AB(mapA, mapB);
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(400u, AB.a().start());
+  EXPECT_EQ(400u, AB.b().start());
+  ++AB;
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(400u, AB.a().start());
+  EXPECT_EQ(401u, AB.b().start());
+  ++AB;
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(400u, AB.a().start());
+  EXPECT_EQ(402u, AB.b().start());
+  ++AB;
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(410u, AB.a().start());
+  EXPECT_EQ(402u, AB.b().start());
+  ++AB;
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(420u, AB.a().start());
+  EXPECT_EQ(402u, AB.b().start());
+  AB.skipB();
+  ASSERT_TRUE(AB.valid());
+  EXPECT_EQ(600u, AB.a().start());
+  EXPECT_EQ(600u, AB.b().start());
+  ++AB;
+  EXPECT_FALSE(AB.valid());
+
+  // Check reversed maps.
+  UUOverlaps BA(mapB, mapA);
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(400u, BA.b().start());
+  EXPECT_EQ(400u, BA.a().start());
+  ++BA;
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(400u, BA.b().start());
+  EXPECT_EQ(401u, BA.a().start());
+  ++BA;
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(400u, BA.b().start());
+  EXPECT_EQ(402u, BA.a().start());
+  ++BA;
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(410u, BA.b().start());
+  EXPECT_EQ(402u, BA.a().start());
+  ++BA;
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(420u, BA.b().start());
+  EXPECT_EQ(402u, BA.a().start());
+  BA.skipA();
+  ASSERT_TRUE(BA.valid());
+  EXPECT_EQ(600u, BA.b().start());
+  EXPECT_EQ(600u, BA.a().start());
+  ++BA;
+  EXPECT_FALSE(BA.valid());
+}
+
 } // namespace



From daniel at zuster.org  Thu Dec 16 20:05:45 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 02:05:45 -0000
Subject: [llvm-commits] [llvm] r122023 - in /llvm/trunk:
	include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp
Message-ID: <20101217020545.D58CA2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 20:05:45 2010
New Revision: 122023

URL: http://llvm.org/viewvc/llvm-project?rev=122023&view=rev
Log:
MC/Expr: Simplify.

Modified:
    llvm/trunk/include/llvm/MC/MCExpr.h
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=122023&r1=122022&r2=122023&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Thu Dec 16 20:05:45 2010
@@ -93,7 +93,10 @@
   /// @param Res - The relocatable value, if evaluation succeeds.
   /// @param Layout - The assembler layout object to use for evaluating values.
   /// @result - True on success.
-  bool EvaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout = 0) const;
+  bool EvaluateAsRelocatable(MCValue &Res,
+                             const MCAsmLayout *Layout = 0) const {
+    return EvaluateAsRelocatableImpl(Res, Layout, 0, false);
+  }
 
   /// @}
 

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122023&r1=122022&r2=122023&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 20:05:45 2010
@@ -355,14 +355,6 @@
   return true;
 }
 
-bool MCExpr::EvaluateAsRelocatable(MCValue &Res,
-                                   const MCAsmLayout *Layout) const {
-  if (Layout)
-    return EvaluateAsRelocatableImpl(Res, Layout, 0, false);
-  else
-    return EvaluateAsRelocatableImpl(Res, 0, 0, false);
-}
-
 bool MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
                                        const MCAsmLayout *Layout,
                                        const SectionAddrMap *Addrs,



From daniel at zuster.org  Thu Dec 16 20:06:08 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 02:06:08 -0000
Subject: [llvm-commits] [llvm] r122024 - in /llvm/trunk:
 include/llvm/Target/TargetAsmBackend.h lib/MC/MachObjectWriter.cpp
 lib/MC/TargetAsmBackend.cpp lib/Target/ARM/ARMAsmBackend.cpp
 lib/Target/MBlaze/MBlazeAsmBackend.cpp lib/Target/PowerPC/PPCAsmBackend.cpp
 lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20101217020608.5A59A2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 20:06:08 2010
New Revision: 122024

URL: http://llvm.org/viewvc/llvm-project?rev=122024&view=rev
Log:
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
superceded and was effectively dead.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmBackend.h
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/MC/TargetAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/Target/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmBackend.h?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmBackend.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmBackend.h Thu Dec 16 20:06:08 2010
@@ -33,7 +33,6 @@
   TargetAsmBackend();
 
   unsigned HasReliableSymbolDifference : 1;
-  unsigned HasScatteredSymbols : 1;
 
 public:
   virtual ~TargetAsmBackend();
@@ -58,16 +57,6 @@
     return HasReliableSymbolDifference;
   }
 
-  /// hasScatteredSymbols - Check whether this target supports scattered
-  /// symbols. If so, the assembler should assume that atoms can be scattered by
-  /// the linker. In particular, this means that the offsets between symbols
-  /// which are in distinct atoms is not known at link time, and the assembler
-  /// must generate fixups and relocations appropriately.
-  ///
-  /// Note that the assembler currently does not reason about atoms, instead it
-  /// assumes all temporary symbols reside in the "current atom".
-  bool hasScatteredSymbols() const { return HasScatteredSymbols; }
-
   /// doesSectionRequireSymbols - Check whether the given section requires that
   /// all symbols (even temporaries) have symbol table entries.
   virtual bool doesSectionRequireSymbols(const MCSection &Section) const {

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 20:06:08 2010
@@ -1123,15 +1123,10 @@
                        UndefinedSymbolData);
   }
 
-
   bool IsFixupFullyResolved(const MCAssembler &Asm,
                             const MCValue Target,
                             bool IsPCRel,
                             const MCFragment *DF) const {
-    // If we aren't using scattered symbols, the fixup is fully resolved.
-    if (!Asm.getBackend().hasScatteredSymbols())
-      return true;
-
     // Otherwise, determine whether this value is actually resolved; scattering
     // may cause atoms to move.
 

Modified: llvm/trunk/lib/MC/TargetAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/TargetAsmBackend.cpp?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/lib/MC/TargetAsmBackend.cpp (original)
+++ llvm/trunk/lib/MC/TargetAsmBackend.cpp Thu Dec 16 20:06:08 2010
@@ -11,8 +11,7 @@
 using namespace llvm;
 
 TargetAsmBackend::TargetAsmBackend()
-  : HasReliableSymbolDifference(false),
-    HasScatteredSymbols(false)
+  : HasReliableSymbolDifference(false)
 {
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec 16 20:06:08 2010
@@ -336,9 +336,7 @@
 public:
   Triple::OSType OSType;
   ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
-    : ARMAsmBackend(T), OSType(_OSType) {
-    HasScatteredSymbols = true;
-  }
+    : ARMAsmBackend(T), OSType(_OSType) { }
 
   virtual const MCObjectFormat &getObjectFormat() const {
     return Format;
@@ -376,9 +374,7 @@
 class DarwinARMAsmBackend : public ARMAsmBackend {
   MCMachOObjectFormat Format;
 public:
-  DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
-    HasScatteredSymbols = true;
-  }
+  DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) { }
 
   virtual const MCObjectFormat &getObjectFormat() const {
     return Format;

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmBackend.cpp Thu Dec 16 20:06:08 2010
@@ -105,9 +105,7 @@
 public:
   Triple::OSType OSType;
   ELFMBlazeAsmBackend(const Target &T, Triple::OSType _OSType)
-    : MBlazeAsmBackend(T), OSType(_OSType) {
-    HasScatteredSymbols = true;
-  }
+    : MBlazeAsmBackend(T), OSType(_OSType) { }
 
   virtual const MCObjectFormat &getObjectFormat() const {
     return Format;

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Thu Dec 16 20:06:08 2010
@@ -84,9 +84,7 @@
   class DarwinPPCAsmBackend : public PPCAsmBackend {
     MCMachOObjectFormat Format;
   public:
-    DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) {
-      HasScatteredSymbols = true;
-    }
+    DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { }
     
     virtual const MCObjectFormat &getObjectFormat() const {
       return Format;

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=122024&r1=122023&r2=122024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Thu Dec 16 20:06:08 2010
@@ -289,7 +289,6 @@
   Triple::OSType OSType;
   ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
     : X86AsmBackend(T), OSType(_OSType) {
-    HasScatteredSymbols = true;
     HasReliableSymbolDifference = true;
   }
 
@@ -337,7 +336,6 @@
   WindowsX86AsmBackend(const Target &T, bool is64Bit)
     : X86AsmBackend(T)
     , Is64Bit(is64Bit) {
-    HasScatteredSymbols = true;
   }
 
   virtual const MCObjectFormat &getObjectFormat() const {
@@ -354,9 +352,7 @@
 
 public:
   DarwinX86AsmBackend(const Target &T)
-    : X86AsmBackend(T) {
-    HasScatteredSymbols = true;
-  }
+    : X86AsmBackend(T) { }
 
   virtual const MCObjectFormat &getObjectFormat() const {
     return Format;



From grosbach at apple.com  Thu Dec 16 20:11:00 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 17 Dec 2010 02:11:00 -0000
Subject: [llvm-commits] [llvm] r122026 - /llvm/trunk/lib/Support/Triple.cpp
Message-ID: <20101217021100.208D52A6C12C@llvm.org>

Author: grosbach
Date: Thu Dec 16 20:10:59 2010
New Revision: 122026

URL: http://llvm.org/viewvc/llvm-project?rev=122026&view=rev
Log:
Trailing whitespace and 80 column fixups.

Modified:
    llvm/trunk/lib/Support/Triple.cpp

Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=122026&r1=122025&r2=122026&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Thu Dec 16 20:10:59 2010
@@ -22,7 +22,7 @@
   switch (Kind) {
   case InvalidArch: return "<invalid>";
   case UnknownArch: return "unknown";
-    
+
   case alpha:   return "alpha";
   case arm:     return "arm";
   case bfin:    return "bfin";
@@ -225,7 +225,8 @@
     return "arm";
   if (Str == "armv4t" || Str == "thumbv4t")
     return "armv4t";
-  if (Str == "armv5" || Str == "armv5e" || Str == "thumbv5" || Str == "thumbv5e")
+  if (Str == "armv5" || Str == "armv5e" || Str == "thumbv5"
+      || Str == "thumbv5e")
     return "armv5";
   if (Str == "armv6" || Str == "thumbv6")
     return "armv6";
@@ -239,8 +240,8 @@
 //
 
 Triple::ArchType Triple::ParseArch(StringRef ArchName) {
-  if (ArchName.size() == 4 && ArchName[0] == 'i' && 
-      ArchName[2] == '8' && ArchName[3] == '6' && 
+  if (ArchName.size() == 4 && ArchName[0] == 'i' &&
+      ArchName[2] == '8' && ArchName[3] == '6' &&
       ArchName[1] - '3' < 6) // i[3-9]86
     return x86;
   else if (ArchName == "amd64" || ArchName == "x86_64")
@@ -512,17 +513,17 @@
 static unsigned EatNumber(StringRef &Str) {
   assert(!Str.empty() && Str[0] >= '0' && Str[0] <= '9' && "Not a number");
   unsigned Result = Str[0]-'0';
-  
+
   // Eat the digit.
   Str = Str.substr(1);
-  
+
   // Handle "darwin11".
   if (Result == 1 && !Str.empty() && Str[0] >= '0' && Str[0] <= '9') {
     Result = Result*10 + (Str[0] - '0');
     // Eat the digit.
     Str = Str.substr(1);
   }
-  
+
   return Result;
 }
 
@@ -535,10 +536,10 @@
   assert(getOS() == Darwin && "Not a darwin target triple!");
   StringRef OSName = getOSName();
   assert(OSName.startswith("darwin") && "Unknown darwin target triple!");
-  
+
   // Strip off "darwin".
   OSName = OSName.substr(6);
-  
+
   Maj = Min = Revision = 0;
 
   if (OSName.empty() || OSName[0] < '0' || OSName[0] > '9')
@@ -547,27 +548,27 @@
   // The major version is the first digit.
   Maj = EatNumber(OSName);
   if (OSName.empty()) return;
-  
+
   // Handle minor version: 10.4.9 -> darwin8.9.
   if (OSName[0] != '.')
     return;
-  
+
   // Eat the '.'.
   OSName = OSName.substr(1);
 
   if (OSName.empty() || OSName[0] < '0' || OSName[0] > '9')
     return;
-  
+
   Min = EatNumber(OSName);
   if (OSName.empty()) return;
 
   // Handle revision darwin8.9.1
   if (OSName[0] != '.')
     return;
-  
+
   // Eat the '.'.
   OSName = OSName.substr(1);
-  
+
   if (OSName.empty() || OSName[0] < '0' || OSName[0] > '9')
     return;
 



From daniel at zuster.org  Thu Dec 16 20:29:17 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 16 Dec 2010 18:29:17 -0800
Subject: [llvm-commits] [llvm] r121959 -
	/llvm/trunk/tools/llvm-dis/llvm-dis.cpp
In-Reply-To: <AANLkTimdRutKrZ5regx5yFZJxkzZsyKPZsnw5CjqRHGw@mail.gmail.com>
References: <20101216043642.F107B2A6C12C@llvm.org>
	<AANLkTimdRutKrZ5regx5yFZJxkzZsyKPZsnw5CjqRHGw@mail.gmail.com>
Message-ID: <AANLkTin7=sjH6W5UD+Wcm6aWL8hxEAGr6Nna5xwOpZ6r@mail.gmail.com>

On Thu, Dec 16, 2010 at 1:36 AM, Frits van Bommel <fvbommel at gmail.com> wrote:
> On Thu, Dec 16, 2010 at 5:36 AM, Daniel Dunbar <daniel at zuster.org> wrote:
>> ? OwningPtr<MemoryBuffer> BufferPtr;
>>
>> - ?if (ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr))
>> + ?if ((ec = MemoryBuffer::getFileOrSTDIN(InputFilename, BufferPtr)))
>> ? ? ErrorMessage = ec.message();
>> ? else
>> ? ? M.reset(ParseBitcodeFile(BufferPtr.get(), Context, &ErrorMessage));
>> - ?MemoryBuffer *Buffer = BufferPtr.take();
>> + ?(void) BufferPtr.take();
>
> Shouldn't this just use .take() instead of .get() in the 'else'
> branch? (BufferPtr should be null if there was an error, right?)

Probably, but I don't think I just disable compiler warnings and leave
thinking to the original author...

 - Daniel


From aggarwa4 at illinois.edu  Thu Dec 16 20:36:02 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Fri, 17 Dec 2010 02:36:02 -0000
Subject: [llvm-commits] [poolalloc] r122028 -
	/poolalloc/trunk/lib/DSA/Local.cpp
Message-ID: <20101217023602.504132A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Dec 16 20:36:02 2010
New Revision: 122028

URL: http://llvm.org/viewvc/llvm-project?rev=122028&view=rev
Log:
Remove dead code. Also, revert the change that allows
merging arrays of multiple sizes.

Modified:
    poolalloc/trunk/lib/DSA/Local.cpp

Modified: poolalloc/trunk/lib/DSA/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=122028&r1=122027&r2=122028&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/Local.cpp (original)
+++ poolalloc/trunk/lib/DSA/Local.cpp Thu Dec 16 20:36:02 2010
@@ -568,10 +568,6 @@
       if(!Value.getNode()->isArrayNode() || Value.getNode()->getSize() <= 0){
         if (requiredSize > Value.getNode()->getSize())
           Value.getNode()->growSize(requiredSize);
-      } else {
-         if (((Offset + Value.getOffset()) % Value.getNode()->getSize()) == 0
-             && (TD.getTypeAllocSize(STy) % Value.getNode()->getSize() == 0))
-           Value.getNode()->growSize(requiredSize);
       }
       
       Offset += (unsigned)TD.getStructLayout(STy)->getElementOffset(FieldNo);
@@ -642,36 +638,6 @@
     }
 
 
-#if 0
-    if (const SequentialType *STy = cast<SequentialType>(*I)) {
-      CurTy = STy->getElementType();
-      if (ConstantInt *CS = dyn_cast<ConstantInt>(GEP.getOperand(i))) {
-        Offset += 
-          (CS->getType()->isSigned() ? CS->getSExtValue() : CS->getZExtValue())
-          * TD.getTypeAllocSize(CurTy);
-      } else {
-        // Variable index into a node.  We must merge all of the elements of the
-        // sequential type here.
-        if (isa<PointerType>(STy)) {
-          DEBUG(errs() << "Pointer indexing not handled yet!\n");
-	} else {
-          const ArrayType *ATy = cast<ArrayType>(STy);
-          unsigned ElSize = TD.getTypeAllocSize(CurTy);
-          DSNode *N = Value.getNode();
-          assert(N && "Value must have a node!");
-          unsigned RawOffset = Offset+Value.getOffset();
-
-          // Loop over all of the elements of the array, merging them into the
-          // zeroth element.
-          for (unsigned i = 1, e = ATy->getNumElements(); i != e; ++i)
-            // Merge all of the byte components of this array element
-            for (unsigned j = 0; j != ElSize; ++j)
-              N->mergeIndexes(RawOffset+j, RawOffset+i*ElSize+j);
-        }
-      }
-    }
-#endif
-
   // Add in the offset calculated...
   Value.setOffset(Value.getOffset()+Offset);
 



From aggarwa4 at illinois.edu  Thu Dec 16 20:37:52 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Fri, 17 Dec 2010 02:37:52 -0000
Subject: [llvm-commits] [poolalloc] r122029 -
	/poolalloc/trunk/lib/DSA/DataStructure.cpp
Message-ID: <20101217023752.5EC5C2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Dec 16 20:37:52 2010
New Revision: 122029

URL: http://llvm.org/viewvc/llvm-project?rev=122029&view=rev
Log:
Makes code more readable.
No functionality change.

Modified:
    poolalloc/trunk/lib/DSA/DataStructure.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=122029&r1=122028&r2=122029&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Thu Dec 16 20:37:52 2010
@@ -548,7 +548,7 @@
     if(NH.getNode()->getSize() != 0 && CurNodeH.getNode()->getSize() != 0) { 
       if((NH.getNode()->getSize() != CurNodeH.getNode()->getSize() &&
        (NH.getOffset() != 0 || CurNodeH.getOffset() != 0) 
-        && NH.getNode()->getSize() <= CurNodeH.getNode()->getSize())) {
+        && NH.getNode()->getSize() < CurNodeH.getNode()->getSize())) {
         CurNodeH.getNode()->foldNodeCompletely();
         NH.getNode()->foldNodeCompletely();
         NSize = NH.getNode()->getSize();



From daniel at zuster.org  Thu Dec 16 20:45:41 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 02:45:41 -0000
Subject: [llvm-commits] [llvm] r122031 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp
 lib/MC/MCObjectStreamer.cpp
Message-ID: <20101217024541.4119C2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 20:45:41 2010
New Revision: 122031

URL: http://llvm.org/viewvc/llvm-project?rev=122031&view=rev
Log:
MC/Assembler: Make the MCObjectWriter available through the lifetime of the
assembler.

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MCObjectStreamer.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=122031&r1=122030&r2=122031&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Dec 16 20:45:41 2010
@@ -648,6 +648,8 @@
 
   MCCodeEmitter &Emitter;
 
+  MCObjectWriter &Writer;
+
   raw_ostream &OS;
 
   iplist<MCSectionData> Sections;
@@ -770,8 +772,9 @@
   // concrete and require clients to pass in a target like object. The other
   // option is to make this abstract, and have targets provide concrete
   // implementations as we do with AsmParser.
-  MCAssembler(MCContext &_Context, TargetAsmBackend &_Backend,
-              MCCodeEmitter &_Emitter, raw_ostream &OS);
+  MCAssembler(MCContext &Context_, TargetAsmBackend &Backend_,
+              MCCodeEmitter &Emitter_, MCObjectWriter &Writer_,
+              raw_ostream &OS);
   ~MCAssembler();
 
   MCContext &getContext() const { return Context; }
@@ -780,10 +783,12 @@
 
   MCCodeEmitter &getEmitter() const { return Emitter; }
 
+  MCObjectWriter &getWriter() const { return Writer; }
+
   /// Finish - Do final processing and write the object to the output stream.
   /// \arg Writer is used for custom object writer (as the MCJIT does),
   /// if not specified it is automatically created from backend.
-  void Finish(MCObjectWriter *Writer = 0);
+  void Finish();
 
   // FIXME: This does not belong here.
   bool getSubsectionsViaSymbols() const {

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=122031&r1=122030&r2=122031&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Dec 16 20:45:41 2010
@@ -167,10 +167,11 @@
 
 /* *** */
 
-MCAssembler::MCAssembler(MCContext &_Context, TargetAsmBackend &_Backend,
-                         MCCodeEmitter &_Emitter, raw_ostream &_OS)
-  : Context(_Context), Backend(_Backend), Emitter(_Emitter),
-    OS(_OS), RelaxAll(false), SubsectionsViaSymbols(false)
+MCAssembler::MCAssembler(MCContext &Context_, TargetAsmBackend &Backend_,
+                         MCCodeEmitter &Emitter_, MCObjectWriter &Writer_,
+                         raw_ostream &OS_)
+  : Context(Context_), Backend(Backend_), Emitter(Emitter_), Writer(Writer_),
+    OS(OS_), RelaxAll(false), SubsectionsViaSymbols(false)
 {
 }
 
@@ -495,7 +496,7 @@
    return FixedValue;
  }
 
-void MCAssembler::Finish(MCObjectWriter *Writer) {
+void MCAssembler::Finish() {
   DEBUG_WITH_TYPE("mc-dump", {
       llvm::errs() << "assembler backend - pre-layout\n--\n";
       dump(); });
@@ -503,8 +504,6 @@
   // Create the layout object.
   MCAsmLayout Layout(*this);
 
-
-
   // Create dummy fragments and assign section ordinals.
   unsigned SectionIndex = 0;
   for (MCAssembler::iterator it = begin(), ie = end(); it != ie; ++it) {
@@ -527,17 +526,8 @@
       it2->setLayoutOrder(FragmentIndex++);
   }
 
-  llvm::OwningPtr<MCObjectWriter> OwnWriter(0);
-  if (Writer == 0) {
-    //no custom Writer_ : create the default one life-managed by OwningPtr
-    OwnWriter.reset(getBackend().createObjectWriter(OS));
-    Writer = OwnWriter.get();
-    if (!Writer)
-      report_fatal_error("unable to create object writer!");
-  }
-
   // Layout until everything fits.
-  while (LayoutOnce(*Writer, Layout))
+  while (LayoutOnce(Writer, Layout))
     continue;
 
   DEBUG_WITH_TYPE("mc-dump", {
@@ -555,7 +545,7 @@
 
   // Allow the object writer a chance to perform post-layout binding (for
   // example, to set the index fields in the symbol data).
-  Writer->ExecutePostLayoutBinding(*this, Layout);
+  Writer.ExecutePostLayoutBinding(*this, Layout);
 
   // Evaluate and apply the fixups, generating relocation entries as necessary.
   for (MCAssembler::iterator it = begin(), ie = end(); it != ie; ++it) {
@@ -566,7 +556,7 @@
         for (MCDataFragment::fixup_iterator it3 = DF->fixup_begin(),
                ie3 = DF->fixup_end(); it3 != ie3; ++it3) {
           MCFixup &Fixup = *it3;
-          uint64_t FixedValue = HandleFixup(*Writer, Layout, *DF, Fixup);
+          uint64_t FixedValue = HandleFixup(Writer, Layout, *DF, Fixup);
           getBackend().ApplyFixup(Fixup, DF->getContents().data(),
                                   DF->getContents().size(), FixedValue);
         }
@@ -576,7 +566,7 @@
         for (MCInstFragment::fixup_iterator it3 = IF->fixup_begin(),
                ie3 = IF->fixup_end(); it3 != ie3; ++it3) {
           MCFixup &Fixup = *it3;
-          uint64_t FixedValue = HandleFixup(*Writer, Layout, *IF, Fixup);
+          uint64_t FixedValue = HandleFixup(Writer, Layout, *IF, Fixup);
           getBackend().ApplyFixup(Fixup, IF->getCode().data(),
                                   IF->getCode().size(), FixedValue);
         }
@@ -585,7 +575,7 @@
   }
 
   // Write the object file.
-  Writer->WriteObject(*this, Layout);
+  Writer.WriteObject(*this, Layout);
 
   stats::ObjectBytes += OS.tell() - StartOffset;
 }

Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=122031&r1=122030&r2=122031&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Thu Dec 16 20:45:41 2010
@@ -21,10 +21,11 @@
 using namespace llvm;
 
 MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
-                                   raw_ostream &_OS, MCCodeEmitter *_Emitter)
-  : MCStreamer(Context), Assembler(new MCAssembler(Context, TAB,
-                                                   *_Emitter,
-                                                   _OS)),
+                                   raw_ostream &OS, MCCodeEmitter *Emitter_)
+  : MCStreamer(Context),
+    Assembler(new MCAssembler(Context, TAB,
+                              *Emitter_, *TAB.createObjectWriter(OS),
+                              OS)),
     CurSectionData(0)
 {
 }
@@ -32,6 +33,7 @@
 MCObjectStreamer::~MCObjectStreamer() {
   delete &Assembler->getBackend();
   delete &Assembler->getEmitter();
+  delete &Assembler->getWriter();
   delete Assembler;
 }
 



From daniel at zuster.org  Thu Dec 16 20:45:59 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 02:45:59 -0000
Subject: [llvm-commits] [llvm] r122032 - in /llvm/trunk:
 include/llvm/MC/MCAssembler.h lib/MC/ELFObjectWriter.cpp
 lib/MC/MCAssembler.cpp lib/MC/MachObjectWriter.cpp
 lib/MC/WinCOFFObjectWriter.cpp
Message-ID: <20101217024559.E0F012A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 20:45:59 2010
New Revision: 122032

URL: http://llvm.org/viewvc/llvm-project?rev=122032&view=rev
Log:
MC/Assembler: Strip out object writer arguments, now that it is always available
-- and remove FIXME asking for the same!

Modified:
    llvm/trunk/include/llvm/MC/MCAssembler.h
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/MCAssembler.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=122032&r1=122031&r2=122032&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAssembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCAssembler.h Thu Dec 16 20:45:59 2010
@@ -694,44 +694,37 @@
   /// \return Whether the fixup value was fully resolved. This is true if the
   /// \arg Value result is fixed, otherwise the value may change due to
   /// relocation.
-  bool EvaluateFixup(const MCObjectWriter &Writer, const MCAsmLayout &Layout,
+  bool EvaluateFixup(const MCAsmLayout &Layout,
                      const MCFixup &Fixup, const MCFragment *DF,
                      MCValue &Target, uint64_t &Value) const;
 
   /// Check whether a fixup can be satisfied, or whether it needs to be relaxed
   /// (increased in size, in order to hold its value correctly).
-  bool FixupNeedsRelaxation(const MCObjectWriter &Writer,
-                            const MCFixup &Fixup, const MCFragment *DF,
+  bool FixupNeedsRelaxation(const MCFixup &Fixup, const MCFragment *DF,
                             const MCAsmLayout &Layout) const;
 
   /// Check whether the given fragment needs relaxation.
-  bool FragmentNeedsRelaxation(const MCObjectWriter &Writer,
-                               const MCInstFragment *IF,
+  bool FragmentNeedsRelaxation(const MCInstFragment *IF,
                                const MCAsmLayout &Layout) const;
 
   /// LayoutOnce - Perform one layout iteration and return true if any offsets
   /// were adjusted.
-  bool LayoutOnce(const MCObjectWriter &Writer, MCAsmLayout &Layout);
+  bool LayoutOnce(MCAsmLayout &Layout);
 
-  bool RelaxInstruction(const MCObjectWriter &Writer, MCAsmLayout &Layout,
-                        MCInstFragment &IF);
+  bool RelaxInstruction(MCAsmLayout &Layout, MCInstFragment &IF);
 
-  bool RelaxOrg(const MCObjectWriter &Writer, MCAsmLayout &Layout,
-                MCOrgFragment &OF);
+  bool RelaxOrg(MCAsmLayout &Layout, MCOrgFragment &OF);
 
-  bool RelaxLEB(const MCObjectWriter &Writer, MCAsmLayout &Layout,
-                MCLEBFragment &IF);
+  bool RelaxLEB(MCAsmLayout &Layout, MCLEBFragment &IF);
 
-  bool RelaxDwarfLineAddr(const MCObjectWriter &Writer, MCAsmLayout &Layout,
-			  MCDwarfLineAddrFragment &DF);
+  bool RelaxDwarfLineAddr(MCAsmLayout &Layout, MCDwarfLineAddrFragment &DF);
 
-  bool RelaxAlignment(const MCObjectWriter &Writer, MCAsmLayout &Layout,
-		      MCAlignFragment &DF);
+  bool RelaxAlignment(MCAsmLayout &Layout, MCAlignFragment &DF);
 
   /// FinishLayout - Finalize a layout, including fragment lowering.
   void FinishLayout(MCAsmLayout &Layout);
 
-  uint64_t HandleFixup(MCObjectWriter &Writer, const MCAsmLayout &Layout,
+  uint64_t HandleFixup(const MCAsmLayout &Layout,
                        MCFragment &F, const MCFixup &Fixup);
 
 public:
@@ -750,10 +743,8 @@
   bool isSymbolLinkerVisible(const MCSymbol &SD) const;
 
   /// Emit the section contents using the given object writer.
-  //
-  // FIXME: Should MCAssembler always have a reference to the object writer?
-  void WriteSectionData(const MCSectionData *Section, const MCAsmLayout &Layout,
-                        MCObjectWriter *OW) const;
+  void WriteSectionData(const MCSectionData *Section,
+                        const MCAsmLayout &Layout) const;
 
   /// Check whether a given symbol has been flagged with .thumb_func.
   bool isThumbFunc(const MCSymbol *Func) const {

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=122032&r1=122031&r2=122032&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Dec 16 20:45:59 2010
@@ -1455,7 +1455,7 @@
     if (IsELFMetaDataSection(SD))
       WriteDataSectionData(this, SD);
     else
-      Asm.WriteSectionData(&SD, Layout, this);
+      Asm.WriteSectionData(&SD, Layout);
   }
 
   uint64_t Padding = OffsetToAlignment(FileOff, NaturalAlignment);

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=122032&r1=122031&r2=122032&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Dec 16 20:45:59 2010
@@ -210,8 +210,7 @@
   return SD->getFragment()->getAtom();
 }
 
-bool MCAssembler::EvaluateFixup(const MCObjectWriter &Writer,
-                                const MCAsmLayout &Layout,
+bool MCAssembler::EvaluateFixup(const MCAsmLayout &Layout,
                                 const MCFixup &Fixup, const MCFragment *DF,
                                 MCValue &Target, uint64_t &Value) const {
   ++stats::EvaluateFixup;
@@ -247,7 +246,7 @@
   }
 
   if (IsResolved)
-    IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
+    IsResolved = getWriter().IsFixupFullyResolved(*this, Target, IsPCRel, DF);
 
   bool ShouldAlignPC = Backend.getFixupKindInfo(Fixup.getKind()).Flags &
                          MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
@@ -322,7 +321,8 @@
 
 /// WriteFragmentData - Write the \arg F data to the output file.
 static void WriteFragmentData(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                              const MCFragment &F, MCObjectWriter *OW) {
+                              const MCFragment &F) {
+  MCObjectWriter *OW = &Asm.getWriter();
   uint64_t Start = OW->getStream().tell();
   (void) Start;
 
@@ -428,8 +428,7 @@
 }
 
 void MCAssembler::WriteSectionData(const MCSectionData *SD,
-                                   const MCAsmLayout &Layout,
-                                   MCObjectWriter *OW) const {
+                                   const MCAsmLayout &Layout) const {
   // Ignore virtual sections.
   if (SD->getSection().isVirtualSection()) {
     assert(Layout.getSectionFileSize(SD) == 0 && "Invalid size for section!");
@@ -469,29 +468,29 @@
     return;
   }
 
-  uint64_t Start = OW->getStream().tell();
+  uint64_t Start = getWriter().getStream().tell();
   (void) Start;
 
   for (MCSectionData::const_iterator it = SD->begin(),
          ie = SD->end(); it != ie; ++it)
-    WriteFragmentData(*this, Layout, *it, OW);
+    WriteFragmentData(*this, Layout, *it);
 
-  assert(OW->getStream().tell() - Start == Layout.getSectionAddressSize(SD));
+  assert(getWriter().getStream().tell() - Start ==
+         Layout.getSectionAddressSize(SD));
 }
 
 
-uint64_t MCAssembler::HandleFixup(MCObjectWriter &Writer,
-                              const MCAsmLayout &Layout,
-                              MCFragment &F,
-                              const MCFixup &Fixup) {
+uint64_t MCAssembler::HandleFixup(const MCAsmLayout &Layout,
+                                  MCFragment &F,
+                                  const MCFixup &Fixup) {
    // Evaluate the fixup.
    MCValue Target;
    uint64_t FixedValue;
-   if (!EvaluateFixup(Writer, Layout, Fixup, &F, Target, FixedValue)) {
+   if (!EvaluateFixup(Layout, Fixup, &F, Target, FixedValue)) {
      // The fixup was unresolved, we need a relocation. Inform the object
      // writer of the relocation, and give it an opportunity to adjust the
      // fixup value if need be.
-     Writer.RecordRelocation(*this, Layout, &F, Fixup, Target, FixedValue);
+     getWriter().RecordRelocation(*this, Layout, &F, Fixup, Target, FixedValue);
    }
    return FixedValue;
  }
@@ -527,7 +526,7 @@
   }
 
   // Layout until everything fits.
-  while (LayoutOnce(Writer, Layout))
+  while (LayoutOnce(Layout))
     continue;
 
   DEBUG_WITH_TYPE("mc-dump", {
@@ -545,7 +544,7 @@
 
   // Allow the object writer a chance to perform post-layout binding (for
   // example, to set the index fields in the symbol data).
-  Writer.ExecutePostLayoutBinding(*this, Layout);
+  getWriter().ExecutePostLayoutBinding(*this, Layout);
 
   // Evaluate and apply the fixups, generating relocation entries as necessary.
   for (MCAssembler::iterator it = begin(), ie = end(); it != ie; ++it) {
@@ -556,7 +555,7 @@
         for (MCDataFragment::fixup_iterator it3 = DF->fixup_begin(),
                ie3 = DF->fixup_end(); it3 != ie3; ++it3) {
           MCFixup &Fixup = *it3;
-          uint64_t FixedValue = HandleFixup(Writer, Layout, *DF, Fixup);
+          uint64_t FixedValue = HandleFixup(Layout, *DF, Fixup);
           getBackend().ApplyFixup(Fixup, DF->getContents().data(),
                                   DF->getContents().size(), FixedValue);
         }
@@ -566,7 +565,7 @@
         for (MCInstFragment::fixup_iterator it3 = IF->fixup_begin(),
                ie3 = IF->fixup_end(); it3 != ie3; ++it3) {
           MCFixup &Fixup = *it3;
-          uint64_t FixedValue = HandleFixup(Writer, Layout, *IF, Fixup);
+          uint64_t FixedValue = HandleFixup(Layout, *IF, Fixup);
           getBackend().ApplyFixup(Fixup, IF->getCode().data(),
                                   IF->getCode().size(), FixedValue);
         }
@@ -575,13 +574,12 @@
   }
 
   // Write the object file.
-  Writer.WriteObject(*this, Layout);
+  getWriter().WriteObject(*this, Layout);
 
   stats::ObjectBytes += OS.tell() - StartOffset;
 }
 
-bool MCAssembler::FixupNeedsRelaxation(const MCObjectWriter &Writer,
-                                       const MCFixup &Fixup,
+bool MCAssembler::FixupNeedsRelaxation(const MCFixup &Fixup,
                                        const MCFragment *DF,
                                        const MCAsmLayout &Layout) const {
   if (getRelaxAll())
@@ -590,7 +588,7 @@
   // If we cannot resolve the fixup value, it requires relaxation.
   MCValue Target;
   uint64_t Value;
-  if (!EvaluateFixup(Writer, Layout, Fixup, DF, Target, Value))
+  if (!EvaluateFixup(Layout, Fixup, DF, Target, Value))
     return true;
 
   // Otherwise, relax if the value is too big for a (signed) i8.
@@ -599,8 +597,7 @@
   return int64_t(Value) != int64_t(int8_t(Value));
 }
 
-bool MCAssembler::FragmentNeedsRelaxation(const MCObjectWriter &Writer,
-                                          const MCInstFragment *IF,
+bool MCAssembler::FragmentNeedsRelaxation(const MCInstFragment *IF,
                                           const MCAsmLayout &Layout) const {
   // If this inst doesn't ever need relaxation, ignore it. This occurs when we
   // are intentionally pushing out inst fragments, or because we relaxed a
@@ -610,16 +607,15 @@
 
   for (MCInstFragment::const_fixup_iterator it = IF->fixup_begin(),
          ie = IF->fixup_end(); it != ie; ++it)
-    if (FixupNeedsRelaxation(Writer, *it, IF, Layout))
+    if (FixupNeedsRelaxation(*it, IF, Layout))
       return true;
 
   return false;
 }
 
-bool MCAssembler::RelaxInstruction(const MCObjectWriter &Writer,
-                                   MCAsmLayout &Layout,
+bool MCAssembler::RelaxInstruction(MCAsmLayout &Layout,
                                    MCInstFragment &IF) {
-  if (!FragmentNeedsRelaxation(Writer, &IF, Layout))
+  if (!FragmentNeedsRelaxation(&IF, Layout))
     return false;
 
   ++stats::RelaxedInstructions;
@@ -653,9 +649,7 @@
   return true;
 }
 
-bool MCAssembler::RelaxOrg(const MCObjectWriter &Writer,
-                           MCAsmLayout &Layout,
-                           MCOrgFragment &OF) {
+bool MCAssembler::RelaxOrg(MCAsmLayout &Layout, MCOrgFragment &OF) {
   int64_t TargetLocation;
   if (!OF.getOffset().EvaluateAsAbsolute(TargetLocation, Layout))
     report_fatal_error("expected assembly-time absolute expression");
@@ -672,9 +666,7 @@
   return OldSize != OF.getSize();
 }
 
-bool MCAssembler::RelaxLEB(const MCObjectWriter &Writer,
-                           MCAsmLayout &Layout,
-                           MCLEBFragment &LF) {
+bool MCAssembler::RelaxLEB(MCAsmLayout &Layout, MCLEBFragment &LF) {
   int64_t Value = 0;
   uint64_t OldSize = LF.getContents().size();
   LF.getValue().EvaluateAsAbsolute(Value, Layout);
@@ -689,8 +681,7 @@
   return OldSize != LF.getContents().size();
 }
 
-bool MCAssembler::RelaxDwarfLineAddr(const MCObjectWriter &Writer,
-				     MCAsmLayout &Layout,
+bool MCAssembler::RelaxDwarfLineAddr(MCAsmLayout &Layout,
 				     MCDwarfLineAddrFragment &DF) {
   int64_t AddrDelta = 0;
   uint64_t OldSize = DF.getContents().size();
@@ -705,8 +696,7 @@
   return OldSize != Data.size();
 }
 
-bool MCAssembler::RelaxAlignment(const MCObjectWriter &Writer,
-				 MCAsmLayout &Layout,
+bool MCAssembler::RelaxAlignment(MCAsmLayout &Layout,
 				 MCAlignFragment &AF) {
   unsigned Offset = Layout.getFragmentOffset(&AF);
   unsigned Size = OffsetToAlignment(Offset, AF.getAlignment());
@@ -717,8 +707,7 @@
   return OldSize != Size;
 }
 
-bool MCAssembler::LayoutOnce(const MCObjectWriter &Writer,
-                             MCAsmLayout &Layout) {
+bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) {
   ++stats::RelaxationSteps;
 
   // Scan for fragments that need relaxation.
@@ -735,22 +724,20 @@
       default:
         break;
       case MCFragment::FT_Align:
-	relaxedFrag = RelaxAlignment(Writer, Layout,
-				     *cast<MCAlignFragment>(it2));
+	relaxedFrag = RelaxAlignment(Layout, *cast<MCAlignFragment>(it2));
 	break;
       case MCFragment::FT_Inst:
-        relaxedFrag = RelaxInstruction(Writer, Layout,
-                                       *cast<MCInstFragment>(it2));
+        relaxedFrag = RelaxInstruction(Layout, *cast<MCInstFragment>(it2));
         break;
       case MCFragment::FT_Org:
-        relaxedFrag = RelaxOrg(Writer, Layout, *cast<MCOrgFragment>(it2));
+        relaxedFrag = RelaxOrg(Layout, *cast<MCOrgFragment>(it2));
         break;
       case MCFragment::FT_Dwarf:
-        relaxedFrag = RelaxDwarfLineAddr(Writer, Layout,
-					 *cast<MCDwarfLineAddrFragment>(it2));
+        relaxedFrag = RelaxDwarfLineAddr(Layout,
+                                         *cast<MCDwarfLineAddrFragment>(it2));
 	break;
       case MCFragment::FT_LEB:
-        relaxedFrag = RelaxLEB(Writer, Layout, *cast<MCLEBFragment>(it2));
+        relaxedFrag = RelaxLEB(Layout, *cast<MCLEBFragment>(it2));
         break;
       }
       // Update the layout, and remember that we relaxed.

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=122032&r1=122031&r2=122032&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 20:45:59 2010
@@ -1257,7 +1257,7 @@
     // Write the actual section data.
     for (MCAssembler::const_iterator it = Asm.begin(),
            ie = Asm.end(); it != ie; ++it) {
-      Asm.WriteSectionData(it, Layout, this);
+      Asm.WriteSectionData(it, Layout);
 
       uint64_t Pad = getPaddingSize(it, Layout);
       for (unsigned int i = 0; i < Pad; ++i)

Modified: llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp?rev=122032&r1=122031&r2=122032&view=diff
==============================================================================
--- llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Thu Dec 16 20:45:59 2010
@@ -874,7 +874,7 @@
         assert(OS.tell() == (*i)->Header.PointerToRawData &&
                "Section::PointerToRawData is insane!");
 
-        Asm.WriteSectionData(j, Layout, this);
+        Asm.WriteSectionData(j, Layout);
       }
 
       if ((*i)->Relocations.size() > 0) {



From stoklund at 2pi.dk  Thu Dec 16 22:09:47 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 17 Dec 2010 04:09:47 -0000
Subject: [llvm-commits] [llvm] r122034 - in /llvm/trunk:
 include/llvm/ADT/IntervalMap.h include/llvm/CodeGen/MachineLoopRanges.h
 lib/CodeGen/LiveIntervalUnion.cpp lib/CodeGen/LiveIntervalUnion.h
 lib/CodeGen/MachineLoopRanges.cpp
Message-ID: <20101217040947.82D272A6C12C@llvm.org>

Author: stoklund
Date: Thu Dec 16 22:09:47 2010
New Revision: 122034

URL: http://llvm.org/viewvc/llvm-project?rev=122034&view=rev
Log:
Provide LiveIntervalUnion::Query::checkLoopInterference.

This is a three-way interval list intersection between a virtual register, a
live interval union, and a loop. It will be used to identify interference-free
loops for live range splitting.

Modified:
    llvm/trunk/include/llvm/ADT/IntervalMap.h
    llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
    llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
    llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp

Modified: llvm/trunk/include/llvm/ADT/IntervalMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntervalMap.h?rev=122034&r1=122033&r2=122034&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/IntervalMap.h (original)
+++ llvm/trunk/include/llvm/ADT/IntervalMap.h Thu Dec 16 22:09:47 2010
@@ -940,6 +940,8 @@
 
 public:
   typedef typename Sizer::Allocator Allocator;
+  typedef KeyT KeyType;
+  typedef ValT ValueType;
   typedef Traits KeyTraits;
 
 private:
@@ -2025,6 +2027,7 @@
 ///
 template <typename MapA, typename MapB>
 class IntervalMapOverlaps {
+  typedef typename MapA::KeyType KeyType;
   typedef typename MapA::KeyTraits Traits;
   typename MapA::const_iterator posA;
   typename MapB::const_iterator posB;
@@ -2065,6 +2068,20 @@
   /// b - access the right hand side in the overlap.
   const typename MapB::const_iterator &b() const { return posB; }
 
+  /// start - Beginning of the overlapping interval.
+  KeyType start() const {
+    KeyType ak = a().start();
+    KeyType bk = b().start();
+    return Traits::startLess(ak, bk) ? bk : ak;
+  }
+
+  /// stop - End of the overlaping interval.
+  KeyType stop() const {
+    KeyType ak = a().stop();
+    KeyType bk = b().stop();
+    return Traits::startLess(ak, bk) ? ak : bk;
+  }
+
   /// skipA - Move to the next overlap that doesn't involve a().
   void skipA() {
     ++posA;
@@ -2094,8 +2111,15 @@
       skipA();
     return *this;
   }
-};
 
+  /// advanceTo - Move to the first overlapping interval with
+  /// stopLess(x, stop()).
+  void advanceTo(KeyType x) {
+    posA.advanceTo(x);
+    posB.advanceTo(x);
+    advance();
+  }
+};
 
 } // namespace llvm
 

Modified: llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h?rev=122034&r1=122033&r2=122034&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineLoopRanges.h Thu Dec 16 22:09:47 2010
@@ -29,15 +29,18 @@
 /// MachineLoopRange - Range information for a single loop.
 class MachineLoopRange {
   friend class MachineLoopRanges;
-  typedef IntervalMap<SlotIndex, unsigned, 4> RangeMap;
-  typedef RangeMap::Allocator Allocator;
 
+public:
+  typedef IntervalMap<SlotIndex, unsigned, 4> Map;
+  typedef Map::Allocator Allocator;
+
+private:
   /// The mapped loop.
   const MachineLoop *const Loop;
 
   /// Map intervals to a bit mask.
   /// Bit 0 = inside loop block.
-  RangeMap Intervals;
+  Map Intervals;
 
   /// Create a MachineLoopRange, only accessible to MachineLoopRanges.
   MachineLoopRange(const MachineLoop*, Allocator&, SlotIndexes&);
@@ -47,6 +50,9 @@
   /// inteructions.
   bool overlaps(SlotIndex Start, SlotIndex Stop);
 
+  /// getMap - Allow public read-only access for IntervalMapOverlaps.
+  const Map &getMap() { return Intervals; }
+
   /// print - Print loop ranges on OS.
   void print(raw_ostream&) const;
 };

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp?rev=122034&r1=122033&r2=122034&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp Thu Dec 16 22:09:47 2010
@@ -16,6 +16,7 @@
 #define DEBUG_TYPE "regalloc"
 #include "LiveIntervalUnion.h"
 #include "llvm/ADT/SparseBitVector.h"
+#include "llvm/CodeGen/MachineLoopRanges.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetRegisterInfo.h"
@@ -284,3 +285,30 @@
   SeenAllInterferences = true;
   return InterferingVRegs.size();
 }
+
+bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
+  // VirtReg is likely live throughout the loop, so start by checking LIU-Loop
+  // overlaps.
+  IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
+    Overlaps(LiveUnion->getMap(), Loop->getMap());
+  if (!Overlaps.valid())
+    return false;
+
+  // The loop is overlapping an LIU assignment. Check VirtReg as well.
+  LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
+
+  for (;;) {
+    if (VRI == VirtReg->end())
+      return false;
+    if (VRI->start < Overlaps.stop())
+      return true;
+
+    Overlaps.advanceTo(VRI->start);
+    if (!Overlaps.valid())
+      return false;
+    if (Overlaps.start() < VRI->end)
+      return true;
+
+    VRI = VirtReg->advanceTo(VRI, Overlaps.start());
+  }
+}

Modified: llvm/trunk/lib/CodeGen/LiveIntervalUnion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalUnion.h?rev=122034&r1=122033&r2=122034&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalUnion.h (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.h Thu Dec 16 22:09:47 2010
@@ -24,6 +24,7 @@
 
 namespace llvm {
 
+class MachineLoopRange;
 class TargetRegisterInfo;
 
 #ifndef NDEBUG
@@ -76,6 +77,10 @@
   bool empty() const { return Segments.empty(); }
   SlotIndex startIndex() const { return Segments.start(); }
 
+  // Provide public access to the underlying map to allow overlap iteration.
+  typedef LiveSegments Map;
+  const Map &getMap() { return Segments; }
+
   // Add a live virtual register to this union and merge its segments.
   void unify(LiveInterval &VirtReg);
 
@@ -223,6 +228,10 @@
       return InterferingVRegs;
     }
 
+    /// checkLoopInterference - Return true if there is interference overlapping
+    /// Loop.
+    bool checkLoopInterference(MachineLoopRange*);
+
     void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
   private:
     Query(const Query&);          // DO NOT IMPLEMENT

Modified: llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp?rev=122034&r1=122033&r2=122034&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLoopRanges.cpp Thu Dec 16 22:09:47 2010
@@ -69,13 +69,13 @@
 /// overlaps - Return true if this loop overlaps the given range of machine
 /// instructions.
 bool MachineLoopRange::overlaps(SlotIndex Start, SlotIndex Stop) {
-  RangeMap::const_iterator I = Intervals.find(Start);
+  Map::const_iterator I = Intervals.find(Start);
   return I.valid() && Stop > I.start();
 }
 
 void MachineLoopRange::print(raw_ostream &OS) const {
   OS << "Loop#" << Loop->getHeader()->getNumber() << " =";
-  for (RangeMap::const_iterator I = Intervals.begin(); I.valid(); ++I)
+  for (Map::const_iterator I = Intervals.begin(); I.valid(); ++I)
     OS << " [" << I.start() << ';' << I.stop() << ')';
 }
 



From daniel at zuster.org  Thu Dec 16 22:54:54 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 04:54:54 -0000
Subject: [llvm-commits] [llvm] r122037 - in /llvm/trunk:
 include/llvm/MC/MCObjectWriter.h lib/MC/ELFObjectWriter.cpp
 lib/MC/MachObjectWriter.cpp lib/MC/WinCOFFObjectWriter.cpp
Message-ID: <20101217045454.C755E2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 22:54:54 2010
New Revision: 122037

URL: http://llvm.org/viewvc/llvm-project?rev=122037&view=rev
Log:
MC/ObjectWriter: Add a new IsSymbolRefDifferenceFullyResolved target format specific hook.
 - Currently just has stub implementations for Mach-O, ELF, and COFF.

Modified:
    llvm/trunk/include/llvm/MC/MCObjectWriter.h
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectWriter.h?rev=122037&r1=122036&r2=122037&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCObjectWriter.h Thu Dec 16 22:54:54 2010
@@ -20,6 +20,7 @@
 class MCAssembler;
 class MCFixup;
 class MCFragment;
+class MCSymbolRefExpr;
 class MCValue;
 class raw_ostream;
 
@@ -77,6 +78,16 @@
                                 const MCFixup &Fixup, MCValue Target,
                                 uint64_t &FixedValue) = 0;
 
+  /// \brief Check whether the difference (A - B) between two symbol
+  /// references is fully resolved.
+  ///
+  /// Clients are not required to answer precisely and may conservatively return
+  /// false, even when a difference is fully resolved.
+  virtual bool
+  IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
+                                     const MCSymbolRefExpr *A,
+                                     const MCSymbolRefExpr *B) const = 0;
+
   /// Check if a fixup is fully resolved.
   ///
   /// This routine is used by the assembler to let the file format decide

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=122037&r1=122036&r2=122037&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Dec 16 22:54:54 2010
@@ -333,8 +333,17 @@
                           uint64_t Size, uint32_t Link, uint32_t Info,
                           uint64_t Alignment, uint64_t EntrySize);
 
-    virtual void WriteRelocationsFragment(const MCAssembler &Asm, MCDataFragment *F,
-                                  const MCSectionData *SD);
+    virtual void WriteRelocationsFragment(const MCAssembler &Asm,
+                                          MCDataFragment *F,
+                                          const MCSectionData *SD);
+
+    virtual bool
+    IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
+                                       const MCSymbolRefExpr *A,
+                                       const MCSymbolRefExpr *B) const {
+      // FIXME: Implement this!
+      return false;
+    }
 
     virtual bool IsFixupFullyResolved(const MCAssembler &Asm,
                               const MCValue Target,

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=122037&r1=122036&r2=122037&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 22:54:54 2010
@@ -1123,6 +1123,12 @@
                        UndefinedSymbolData);
   }
 
+  bool IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
+                                          const MCSymbolRefExpr *A,
+                                          const MCSymbolRefExpr *B) const {
+    return false;
+  }
+
   bool IsFixupFullyResolved(const MCAssembler &Asm,
                             const MCValue Target,
                             bool IsPCRel,

Modified: llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp?rev=122037&r1=122036&r2=122037&view=diff
==============================================================================
--- llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Thu Dec 16 22:54:54 2010
@@ -179,6 +179,14 @@
                         MCValue Target,
                         uint64_t &FixedValue);
 
+  virtual bool
+  IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
+                                     const MCSymbolRefExpr *A,
+                                     const MCSymbolRefExpr *B) const {
+    // FIXME: Implement this!
+    return false;
+  }
+
   virtual bool IsFixupFullyResolved(const MCAssembler &Asm,
                                     const MCValue Target,
                                     bool IsPCRel,



From daniel at zuster.org  Thu Dec 16 22:54:59 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 04:54:59 -0000
Subject: [llvm-commits] [llvm] r122038 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20101217045459.1DFB12A6C12D@llvm.org>

Author: ddunbar
Date: Thu Dec 16 22:54:58 2010
New Revision: 122038

URL: http://llvm.org/viewvc/llvm-project?rev=122038&view=rev
Log:
MC/Mach-O: Implement IsSymbolRefDifferenceFullyResolved.
 - Unlike for fixups, we always do the "reliable" thing (not just for x86_64).
 - Since Darwin 'as' would typically reject things that using this will allow,
   we don't need to worry about compatibility.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=122038&r1=122037&r2=122038&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 22:54:58 2010
@@ -1126,6 +1126,31 @@
   bool IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
                                           const MCSymbolRefExpr *A,
                                           const MCSymbolRefExpr *B) const {
+    // The effective address is
+    //     addr(atom(A)) + offset(A)
+    //   - addr(atom(B)) - offset(B)
+    // and the offsets are not relocatable, so the fixup is fully resolved when
+    //  addr(atom(A)) - addr(atom(B)) == 0.
+    const MCSymbolData *A_Base = 0, *B_Base = 0;
+
+    // Modified symbol references cannot be resolved.
+    if (A->getKind() != MCSymbolRefExpr::VK_None ||
+        B->getKind() != MCSymbolRefExpr::VK_None)
+      return false;
+
+    A_Base = Asm.getAtom(&Asm.getSymbolData(A->getSymbol()));
+    if (!A_Base)
+      return false;
+
+    B_Base = Asm.getAtom(&Asm.getSymbolData(B->getSymbol()));
+    if (!B_Base)
+      return false;
+
+    // If the atoms are the same, they are guaranteed to have the same address.
+    if (A_Base == B_Base)
+      return true;
+
+    // Otherwise, we can't prove this is fully resolved.
     return false;
   }
 



From aggarwa4 at illinois.edu  Thu Dec 16 23:14:20 2010
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Fri, 17 Dec 2010 05:14:20 -0000
Subject: [llvm-commits] [poolalloc] r122039 - in /poolalloc/trunk/lib/DSA:
 DataStructure.cpp TopDownClosure.cpp
Message-ID: <20101217051420.1CFB92A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Dec 16 23:14:19 2010
New Revision: 122039

URL: http://llvm.org/viewvc/llvm-project?rev=122039&view=rev
Log:
Making sure behavior with and without cloning is 
identical. Earlier only TD was using cloning, and
as in r121232, while cloning the DontCloneAuxCallNodes
flag was set. Thus the AuxCall list for the DSGraphs
in TD was empty. We must maintain that property. Fixes 
failures on lit tests, where extra nodes were getting 
marked I.

Modified:
    poolalloc/trunk/lib/DSA/DataStructure.cpp
    poolalloc/trunk/lib/DSA/TopDownClosure.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=122039&r1=122038&r2=122039&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Thu Dec 16 23:14:19 2010
@@ -1345,6 +1345,8 @@
     DSGraph* BaseGraph = GraphSource->getDSGraph(*F);
     if (Clone) {
       G = new DSGraph(BaseGraph, GlobalECs, *TypeSS);
+      if (resetAuxCalls) 
+        G->getAuxFunctionCalls() = G->getFunctionCalls();
     } else {
       G = new DSGraph(GlobalECs, GraphSource->getTargetData(), *TypeSS);
       G->spliceFrom(BaseGraph);

Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=122039&r1=122038&r2=122039&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original)
+++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Thu Dec 16 23:14:19 2010
@@ -81,6 +81,13 @@
   init(useEQBU ? &getAnalysis<EquivBUDataStructures>()
        : &getAnalysis<BUDataStructures>(), 
        true, true, true, false);
+  
+  for (Module::iterator F = M.begin(); F != M.end(); ++F) {
+    if (!(F->isDeclaration())){
+      DSGraph *G = getOrCreateGraph(F);
+      G->getAuxFunctionCalls().clear();
+    }
+  }
   // Figure out which functions must not mark their arguments complete because
   // they are accessible outside this compilation unit.  Currently, these
   // arguments are functions which are reachable by incomplete or external



From daniel at zuster.org  Thu Dec 16 23:50:29 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 05:50:29 -0000
Subject: [llvm-commits] [llvm] r122042 - in /llvm/trunk:
 include/llvm/MC/MCMachObjectWriter.h lib/MC/MCMachObjectTargetWriter.cpp
 lib/MC/MachObjectWriter.cpp lib/Target/X86/X86AsmBackend.cpp
Message-ID: <20101217055029.9D4262A6C12C@llvm.org>

Author: ddunbar
Date: Thu Dec 16 23:50:29 2010
New Revision: 122042

URL: http://llvm.org/viewvc/llvm-project?rev=122042&view=rev
Log:
MC/Mach-O: On second thought, use a custom hook for enabling aggressive
IsSymbolRefDifferenceFullyResolved, it turns out this does change behavior on
enough cases for x86-32 that I would rather wait a bit on it.
 - In practice, we will want to change this eventually because it only means we
   generate less relocations (it also eliminates the need for the horrible
   '.set' hack that Darwin requires in some places).

Modified:
    llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
    llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCMachObjectWriter.h?rev=122042&r1=122041&r2=122042&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCMachObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCMachObjectWriter.h Thu Dec 16 23:50:29 2010
@@ -19,10 +19,14 @@
   const unsigned Is64Bit : 1;
   const uint32_t CPUType;
   const uint32_t CPUSubtype;
+  // FIXME: Remove this, we should just always use it once we no longer care
+  // about Darwin 'as' compatibility.
+  const unsigned UseAggressiveSymbolFolding : 1;
 
 protected:
   MCMachObjectTargetWriter(bool Is64Bit_, uint32_t CPUType_,
-                           uint32_t CPUSubtype_);
+                           uint32_t CPUSubtype_,
+                           bool UseAggressiveSymbolFolding_ = false);
 
 public:
   virtual ~MCMachObjectTargetWriter();
@@ -31,6 +35,7 @@
   /// @{
 
   bool is64Bit() const { return Is64Bit; }
+  bool useAggressiveSymbolFolding() const { return UseAggressiveSymbolFolding; }
   uint32_t getCPUType() const { return CPUType; }
   uint32_t getCPUSubtype() const { return CPUSubtype; }
 

Modified: llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp?rev=122042&r1=122041&r2=122042&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp (original)
+++ llvm/trunk/lib/MC/MCMachObjectTargetWriter.cpp Thu Dec 16 23:50:29 2010
@@ -12,8 +12,10 @@
 using namespace llvm;
 
 MCMachObjectTargetWriter::MCMachObjectTargetWriter(
-  bool Is64Bit_, uint32_t CPUType_, uint32_t CPUSubtype_)
-  : Is64Bit(Is64Bit_), CPUType(CPUType_), CPUSubtype(CPUSubtype_) {
+  bool Is64Bit_, uint32_t CPUType_, uint32_t CPUSubtype_,
+  bool UseAggressiveSymbolFolding_)
+  : Is64Bit(Is64Bit_), CPUType(CPUType_), CPUSubtype(CPUSubtype_),
+    UseAggressiveSymbolFolding(UseAggressiveSymbolFolding_) {
 }
 
 MCMachObjectTargetWriter::~MCMachObjectTargetWriter() {

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=122042&r1=122041&r2=122042&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Dec 16 23:50:29 2010
@@ -1126,6 +1126,9 @@
   bool IsSymbolRefDifferenceFullyResolved(const MCAssembler &Asm,
                                           const MCSymbolRefExpr *A,
                                           const MCSymbolRefExpr *B) const {
+    if (!TargetObjectWriter->useAggressiveSymbolFolding())
+      return false;
+
     // The effective address is
     //     addr(atom(A)) + offset(A)
     //   - addr(atom(B)) - offset(B)

Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=122042&r1=122041&r2=122042&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Thu Dec 16 23:50:29 2010
@@ -50,7 +50,8 @@
 public:
   X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
                       uint32_t CPUSubtype)
-    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
+    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
+                               /*UseAggressiveSymbolFolding=*/Is64Bit) {}
 };
 
 class X86AsmBackend : public TargetAsmBackend {



From daniel at zuster.org  Thu Dec 16 23:50:34 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 05:50:34 -0000
Subject: [llvm-commits] [llvm] r122043 - in /llvm/trunk: lib/MC/MCExpr.cpp
 test/MC/MachO/darwin-complex-difference.s
Message-ID: <20101217055034.207EA2A6C12D@llvm.org>

Author: ddunbar
Date: Thu Dec 16 23:50:33 2010
New Revision: 122043

URL: http://llvm.org/viewvc/llvm-project?rev=122043&view=rev
Log:
MC/Expr: Implemnt more aggressive folding during symbol evaluation using
IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away
something like:
--
_a:
...
L0:
...
L1:
...
.long (L1 - L0) / 2
--

Added:
    llvm/trunk/test/MC/MachO/darwin-complex-difference.s
Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=122043&r1=122042&r2=122043&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Thu Dec 16 23:50:33 2010
@@ -271,6 +271,25 @@
   return true;
 }
 
+/// \brief Helper method for \see EvaluateSymbolAdd().
+static void AttemptToFoldSymbolOffsetDifference(const MCAsmLayout *Layout,
+                                                const MCSymbolRefExpr *&A,
+                                                const MCSymbolRefExpr *&B,
+                                                int64_t &Addend) {
+  const MCAssembler &Asm = Layout->getAssembler();
+
+  if (A && B &&
+      Asm.getWriter().IsSymbolRefDifferenceFullyResolved(Asm, A, B)) {
+    // Eagerly evaluate.
+    Addend += (Layout->getSymbolOffset(&Asm.getSymbolData(A->getSymbol())) -
+               Layout->getSymbolOffset(&Asm.getSymbolData(B->getSymbol())));
+
+    // Clear the symbol expr pointers to indicate we have folded these
+    // operands.
+    A = B = 0;
+  }
+}
+
 /// \brief Evaluate the result of an add between (conceptually) two MCValues.
 ///
 /// This routine conceptually attempts to construct an MCValue:
@@ -300,20 +319,37 @@
   // Fold the result constant immediately.
   int64_t Result_Cst = LHS_Cst + RHS_Cst;
 
+  // If we have a layout, we can fold resolved differences.
+  if (Layout) {
+    // First, fold out any differences which are fully resolved. By
+    // reassociating terms in
+    //   Result = (LHS_A - LHS_B + LHS_Cst) + (RHS_A - RHS_B + RHS_Cst).
+    // we have the four possible differences:
+    //   (LHS_A - LHS_B),
+    //   (LHS_A - RHS_B),
+    //   (RHS_A - LHS_B),
+    //   (RHS_A - RHS_B).
+    // Since we are attempting to be as aggresive as possible about folding, we
+    // attempt to evaluate each possible alternative.
+    AttemptToFoldSymbolOffsetDifference(Layout, LHS_A, LHS_B, Result_Cst);
+    AttemptToFoldSymbolOffsetDifference(Layout, LHS_A, RHS_B, Result_Cst);
+    AttemptToFoldSymbolOffsetDifference(Layout, RHS_A, LHS_B, Result_Cst);
+    AttemptToFoldSymbolOffsetDifference(Layout, RHS_A, RHS_B, Result_Cst);
+  }
+
   // We can't represent the addition or subtraction of two symbols.
   if ((LHS_A && RHS_A) || (LHS_B && RHS_B))
     return false;
 
+  // At this point, we have at most one additive symbol and one subtractive
+  // symbol -- find them.
   const MCSymbolRefExpr *A = LHS_A ? LHS_A : RHS_A;
   const MCSymbolRefExpr *B = LHS_B ? LHS_B : RHS_B;
-  if (B) {
-    // If we have a negated symbol, then we must have also have a non-negated
-    // symbol in order to encode the expression. We can do this check later to
-    // permit expressions which eventually fold to a representable form -- such
-    // as (a + (0 - b)) -- if necessary.
-    if (!A)
-      return false;
-  }
+
+  // If we have a negated symbol, then we must have also have a non-negated
+  // symbol in order to encode the expression.
+  if (B && !A)
+    return false;
 
   // Absolutize symbol differences between defined symbols when we have a
   // layout object and the target requests it.

Added: llvm/trunk/test/MC/MachO/darwin-complex-difference.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/darwin-complex-difference.s?rev=122043&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/darwin-complex-difference.s (added)
+++ llvm/trunk/test/MC/MachO/darwin-complex-difference.s Thu Dec 16 23:50:33 2010
@@ -0,0 +1,129 @@
+// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o
+// RUN: macho-dump --dump-section-data < %t.o > %t.dump
+// RUN: FileCheck < %t.dump %s
+        
+_a:
+L0:     
+        .long 1
+L1:     
+        .long 2
+        .long _c - _d + 4
+        .long (_c - L0) - (_d - L1) // == (_c - _d) + (L1 - L0)
+                                    // == (_c - _d + 4)
+_c:
+        .long 0
+_d:
+        .long 0
+
+// CHECK: ('cputype', 16777223)
+// CHECK: ('cpusubtype', 3)
+// CHECK: ('filetype', 1)
+// CHECK: ('num_load_commands', 3)
+// CHECK: ('load_commands_size', 256)
+// CHECK: ('flag', 0)
+// CHECK: ('reserved', 0)
+// CHECK: ('load_commands', [
+// CHECK:   # Load Command 0
+// CHECK:  (('command', 25)
+// CHECK:   ('size', 152)
+// CHECK:   ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:   ('vm_addr', 0)
+// CHECK:   ('vm_size', 24)
+// CHECK:   ('file_offset', 288)
+// CHECK:   ('file_size', 24)
+// CHECK:   ('maxprot', 7)
+// CHECK:   ('initprot', 7)
+// CHECK:   ('num_sections', 1)
+// CHECK:   ('flags', 0)
+// CHECK:   ('sections', [
+// CHECK:     # Section 0
+// CHECK:    (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('address', 0)
+// CHECK:     ('size', 24)
+// CHECK:     ('offset', 288)
+// CHECK:     ('alignment', 0)
+// CHECK:     ('reloc_offset', 312)
+// CHECK:     ('num_reloc', 4)
+// CHECK:     ('flags', 0x80000000)
+// CHECK:     ('reserved1', 0)
+// CHECK:     ('reserved2', 0)
+// CHECK:     ('reserved3', 0)
+// CHECK:    ),
+// CHECK:   ('_relocations', [
+// CHECK:     # Relocation 0
+// CHECK:     (('word-0', 0xc),
+// CHECK:      ('word-1', 0x5c000002)),
+// CHECK:     # Relocation 1
+// CHECK:     (('word-0', 0xc),
+// CHECK:      ('word-1', 0xc000001)),
+// CHECK:     # Relocation 2
+// CHECK:     (('word-0', 0x8),
+// CHECK:      ('word-1', 0x5c000002)),
+// CHECK:     # Relocation 3
+// CHECK:     (('word-0', 0x8),
+// CHECK:      ('word-1', 0xc000001)),
+// CHECK:   ])
+// CHECK:   ('_section_data', '01000000 02000000 04000000 04000000 00000000 00000000')
+// CHECK:   ])
+// CHECK:  ),
+// CHECK:   # Load Command 1
+// CHECK:  (('command', 2)
+// CHECK:   ('size', 24)
+// CHECK:   ('symoff', 344)
+// CHECK:   ('nsyms', 3)
+// CHECK:   ('stroff', 392)
+// CHECK:   ('strsize', 12)
+// CHECK:   ('_string_data', '\x00_a\x00_c\x00_d\x00\x00\x00')
+// CHECK:   ('_symbols', [
+// CHECK:     # Symbol 0
+// CHECK:    (('n_strx', 1)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 1)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 0)
+// CHECK:     ('_string', '_a')
+// CHECK:    ),
+// CHECK:     # Symbol 1
+// CHECK:    (('n_strx', 4)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 1)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 16)
+// CHECK:     ('_string', '_c')
+// CHECK:    ),
+// CHECK:     # Symbol 2
+// CHECK:    (('n_strx', 7)
+// CHECK:     ('n_type', 0xe)
+// CHECK:     ('n_sect', 1)
+// CHECK:     ('n_desc', 0)
+// CHECK:     ('n_value', 20)
+// CHECK:     ('_string', '_d')
+// CHECK:    ),
+// CHECK:   ])
+// CHECK:  ),
+// CHECK:   # Load Command 2
+// CHECK:  (('command', 11)
+// CHECK:   ('size', 80)
+// CHECK:   ('ilocalsym', 0)
+// CHECK:   ('nlocalsym', 3)
+// CHECK:   ('iextdefsym', 3)
+// CHECK:   ('nextdefsym', 0)
+// CHECK:   ('iundefsym', 3)
+// CHECK:   ('nundefsym', 0)
+// CHECK:   ('tocoff', 0)
+// CHECK:   ('ntoc', 0)
+// CHECK:   ('modtaboff', 0)
+// CHECK:   ('nmodtab', 0)
+// CHECK:   ('extrefsymoff', 0)
+// CHECK:   ('nextrefsyms', 0)
+// CHECK:   ('indirectsymoff', 0)
+// CHECK:   ('nindirectsyms', 0)
+// CHECK:   ('extreloff', 0)
+// CHECK:   ('nextrel', 0)
+// CHECK:   ('locreloff', 0)
+// CHECK:   ('nlocrel', 0)
+// CHECK:   ('_indirect_symbols', [
+// CHECK:   ])
+// CHECK:  ),
+// CHECK: ])



From daniel at zuster.org  Fri Dec 17 00:00:25 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Fri, 17 Dec 2010 06:00:25 -0000
Subject: [llvm-commits] [llvm] r122044 -
	/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
Message-ID: <20101217060025.2BCA22A6C12C@llvm.org>

Author: ddunbar
Date: Fri Dec 17 00:00:24 2010
New Revision: 122044

URL: http://llvm.org/viewvc/llvm-project?rev=122044&view=rev
Log:
MC/ARM: Use aggressive symbol folding (important for jump tables, for example).

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=122044&r1=122043&r2=122044&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Fri Dec 17 00:00:24 2010
@@ -32,7 +32,8 @@
 public:
   ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
                       uint32_t CPUSubtype)
-    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
+    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
+                               /*UseAggressiveSymbolFolding=*/true) {}
 };
 
 class ARMAsmBackend : public TargetAsmBackend {



From sabre at nondot.org  Fri Dec 17 00:20:15 2010
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 17 Dec 2010 06:20:15 -0000
Subject: [llvm-commits] [llvm] r122045 - in /llvm/trunk:
 include/llvm/Support/ConstantRange.h lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101217062015.7D2472A6C12C@llvm.org>

Author: lattner
Date: Fri Dec 17 00:20:15 2010
New Revision: 122045

URL: http://llvm.org/viewvc/llvm-project?rev=122045&view=rev
Log:
improve switch formation to handle small range 
comparisons formed by comparisons.  For example,
this:

void foo(unsigned x) {
  if (x == 0 || x == 1 || x == 3 || x == 4 || x == 6) 
    bar();
}

compiles into:

_foo:                                   ## @foo
## BB#0:                                ## %entry
	cmpl	$6, %edi
	ja	LBB0_2
## BB#1:                                ## %entry
	movl	%edi, %eax
	movl	$91, %ecx
	btq	%rax, %rcx
	jb	LBB0_3

instead of:

_foo:                                   ## @foo
## BB#0:                                ## %entry
	cmpl	$2, %edi
	jb	LBB0_4
## BB#1:                                ## %switch.early.test
	cmpl	$6, %edi
	ja	LBB0_3
## BB#2:                                ## %switch.early.test
	movl	%edi, %eax
	movl	$88, %ecx
	btq	%rax, %rcx
	jb	LBB0_4

This catches a bunch of cases in GCC, which look like this:

 %804 = load i32* @which_alternative, align 4, !tbaa !0
 %805 = icmp ult i32 %804, 2
 %806 = icmp eq i32 %804, 3
 %or.cond121 = or i1 %805, %806
 %807 = icmp eq i32 %804, 4
 %or.cond124 = or i1 %or.cond121, %807
 br i1 %or.cond124, label %.thread, label %808

turning this into a range comparison.


Modified:
    llvm/trunk/include/llvm/Support/ConstantRange.h
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/include/llvm/Support/ConstantRange.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantRange.h?rev=122045&r1=122044&r2=122045&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ConstantRange.h (original)
+++ llvm/trunk/include/llvm/Support/ConstantRange.h Fri Dec 17 00:20:15 2010
@@ -54,7 +54,7 @@
   /// @brief Initialize a range of values explicitly. This will assert out if
   /// Lower==Upper and Lower != Min or Max value for its type. It will also
   /// assert out if the two APInt's are not the same bit width.
-  ConstantRange(const APInt& Lower, const APInt& Upper);
+  ConstantRange(const APInt &Lower, const APInt &Upper);
 
   /// makeICmpRegion - Produce the smallest range that contains all values that
   /// might satisfy the comparison specified by Pred when compared to any value

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=122045&r1=122044&r2=122045&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Fri Dec 17 00:20:15 2010
@@ -28,6 +28,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/CFG.h"
+#include "llvm/Support/ConstantRange.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
@@ -305,11 +306,33 @@
   
   // If this is an icmp against a constant, handle this as one of the cases.
   if (ICmpInst *ICI = dyn_cast<ICmpInst>(I)) {
-    if (ICI->getPredicate() == (isEQ ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE))
-      if (ConstantInt *C = GetConstantInt(I->getOperand(1), TD)) {
+    if (ConstantInt *C = GetConstantInt(I->getOperand(1), TD)) {
+      if (ICI->getPredicate() == (isEQ ? ICmpInst::ICMP_EQ:ICmpInst::ICMP_NE)) {
         Vals.push_back(C);
         return I->getOperand(0);
       }
+      
+      // If we have "x ult 3" comparison, for example, then we can add 0,1,2 to
+      // the set.
+      ConstantRange Span =
+        ConstantRange::makeICmpRegion(ICI->getPredicate(),
+                                      ConstantRange(C->getValue()));
+      
+      // If this is an and/!= check then we want to optimize "x ugt 2" into
+      // x != 0 && x != 1.
+      if (!isEQ)
+        Span = Span.inverse();
+      
+      // If there are a ton of values, we don't want to make a ginormous switch.
+      if (Span.getSetSize().getZExtValue() > 8 || Span.isEmptySet() ||
+          // We don't handle wrapped sets yet.
+          Span.isWrappedSet())
+        return 0;
+      
+      for (APInt Tmp = Span.getLower(); Tmp != Span.getUpper(); ++Tmp)
+        Vals.push_back(ConstantInt::get(V->getContext(), Tmp));
+      return I->getOperand(0);
+    }
     return 0;
   }
   

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=122045&r1=122044&r2=122045&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Fri Dec 17 00:20:15 2010
@@ -351,4 +351,73 @@
   ret void
 ; CHECK: @test12
 
-}
\ No newline at end of file
+}
+
+; test13 - handle switch formation with ult.
+define void @test13(i32 %x) nounwind ssp noredzone {
+entry:
+  %cmp = icmp ult i32 %x, 2
+  br i1 %cmp, label %if.then, label %lor.lhs.false3
+
+lor.lhs.false3:                                   ; preds = %lor.lhs.false
+  %cmp5 = icmp eq i32 %x, 3
+  br i1 %cmp5, label %if.then, label %lor.lhs.false6
+
+lor.lhs.false6:                                   ; preds = %lor.lhs.false3
+  %cmp8 = icmp eq i32 %x, 4
+  br i1 %cmp8, label %if.then, label %lor.lhs.false9
+
+lor.lhs.false9:                                   ; preds = %lor.lhs.false6
+  %cmp11 = icmp eq i32 %x, 6
+  br i1 %cmp11, label %if.then, label %if.end
+
+if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
+  call void @foo1() noredzone
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %lor.lhs.false9
+  ret void
+; CHECK: @test13
+; CHECK:  switch i32 %x, label %if.end [
+; CHECK:     i32 6, label %if.then
+; CHECK:     i32 4, label %if.then
+; CHECK:     i32 3, label %if.then
+; CHECK:     i32 1, label %if.then
+; CHECK:     i32 0, label %if.then
+; CHECK:   ]
+}
+
+; test14 - handle switch formation with ult.
+define void @test14(i32 %x) nounwind ssp noredzone {
+entry:
+  %cmp = icmp ugt i32 %x, 2
+  br i1 %cmp, label %lor.lhs.false3, label %if.then
+
+lor.lhs.false3:                                   ; preds = %lor.lhs.false
+  %cmp5 = icmp ne i32 %x, 3
+  br i1 %cmp5, label %lor.lhs.false6, label %if.then
+
+lor.lhs.false6:                                   ; preds = %lor.lhs.false3
+  %cmp8 = icmp ne i32 %x, 4
+  br i1 %cmp8, label %lor.lhs.false9, label %if.then
+
+lor.lhs.false9:                                   ; preds = %lor.lhs.false6
+  %cmp11 = icmp ne i32 %x, 6
+  br i1 %cmp11, label %if.end, label %if.then
+
+if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
+  call void @foo1() noredzone
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %lor.lhs.false9
+  ret void
+; CHECK: @test14
+; CHECK:  switch i32 %x, label %if.end [
+; CHECK:     i32 6, label %if.then
+; CHECK:     i32 4, label %if.then
+; CHECK:     i32 3, label %if.then
+; CHECK:     i32 1, label %if.then
+; CHECK:     i32 0, label %if.then
+; CHECK:   ]
+}
+



From rafael.espindola at gmail.com  Fri Dec 17 01:28:17 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 17 Dec 2010 07:28:17 -0000
Subject: [llvm-commits] [llvm] r122050 -
	/llvm/trunk/lib/MC/ELFObjectWriter.cpp
Message-ID: <20101217072817.9B24B2A6C12C@llvm.org>

Author: rafael
Date: Fri Dec 17 01:28:17 2010
New Revision: 122050

URL: http://llvm.org/viewvc/llvm-project?rev=122050&view=rev
Log:
Use getFixupKindInfo to implement isFixupKindPCRel, ELF version.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=122050&r1=122049&r2=122050&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Fri Dec 17 01:28:17 2010
@@ -87,6 +87,13 @@
   }
 }
 
+static bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
+  const MCFixupKindInfo &FKI =
+    Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind);
+
+  return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
+}
+
 namespace {
   class ELFObjectWriter : public MCObjectWriter {
   protected:
@@ -361,8 +368,6 @@
     virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                                   bool IsPCRel, bool IsRelocWithSymbol,
                                   int64_t Addend) = 0;
-
-    virtual bool isFixupKindPCRel(unsigned Kind) const = 0;
   };
 
   //===- X86ELFObjectWriter -------------------------------------------===//
@@ -378,19 +383,6 @@
     virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                                   bool IsPCRel, bool IsRelocWithSymbol,
                                   int64_t Addend);
-
-    virtual bool isFixupKindPCRel(unsigned Kind) const {
-      switch (Kind) {
-      default:
-        return false;
-      case FK_PCRel_1:
-      case FK_PCRel_2:
-      case FK_PCRel_4:
-      case X86::reloc_riprel_4byte:
-      case X86::reloc_riprel_4byte_movq_load:
-        return true;
-      }
-    }
   };
 
 
@@ -407,19 +399,6 @@
     virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                                   bool IsPCRel, bool IsRelocWithSymbol,
                                   int64_t Addend);
-    virtual bool isFixupKindPCRel(unsigned Kind) const {
-      switch (Kind) {
-      default:
-        return false;
-      case FK_PCRel_1:
-      case FK_PCRel_2:
-      case FK_PCRel_4:
-      case ARM::fixup_arm_ldst_pcrel_12:
-      case ARM::fixup_arm_pcrel_10:
-      case ARM::fixup_arm_branch:
-        return true;
-      }
-    }
   };
 
   //===- MBlazeELFObjectWriter -------------------------------------------===//
@@ -435,17 +414,6 @@
     virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                                   bool IsPCRel, bool IsRelocWithSymbol,
                                   int64_t Addend);
-
-    virtual bool isFixupKindPCRel(unsigned Kind) const {
-      switch (Kind) {
-      default:
-        return false;
-      case FK_PCRel_1:
-      case FK_PCRel_2:
-      case FK_PCRel_4:
-        return true;
-      }
-    }
   };
 }
 
@@ -777,7 +745,7 @@
   int64_t Value = Target.getConstant();
   const MCSymbol *RelocSymbol = NULL;
 
-  bool IsPCRel = isFixupKindPCRel(Fixup.getKind());
+  bool IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
   if (!Target.isAbsolute()) {
     const MCSymbol &Symbol = Target.getSymA()->getSymbol();
     const MCSymbol &ASymbol = Symbol.AliasedSymbol();



From nicholas at mxc.ca  Fri Dec 17 02:30:55 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 17 Dec 2010 00:30:55 -0800
Subject: [llvm-commits] [llvm] r122045 - in /llvm/trunk:
 include/llvm/Support/ConstantRange.h lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
In-Reply-To: <20101217062015.7D2472A6C12C@llvm.org>
References: <20101217062015.7D2472A6C12C@llvm.org>
Message-ID: <4D0B1FBF.4080509@mxc.ca>

Chris Lattner wrote:
> Author: lattner
> Date: Fri Dec 17 00:20:15 2010
> New Revision: 122045
>
> URL: http://llvm.org/viewvc/llvm-project?rev=122045&view=rev
> Log:
> improve switch formation to handle small range
> comparisons formed by comparisons.  For example,
> this:
>
> void foo(unsigned x) {
>    if (x == 0 || x == 1 || x == 3 || x == 4 || x == 6)
>      bar();
> }
>
> compiles into:
>
> _foo:                                   ## @foo
> ## BB#0:                                ## %entry
> 	cmpl	$6, %edi
> 	ja	LBB0_2
> ## BB#1:                                ## %entry
> 	movl	%edi, %eax
> 	movl	$91, %ecx
> 	btq	%rax, %rcx
> 	jb	LBB0_3
>
> instead of:
>
> _foo:                                   ## @foo
> ## BB#0:                                ## %entry
> 	cmpl	$2, %edi
> 	jb	LBB0_4
> ## BB#1:                                ## %switch.early.test
> 	cmpl	$6, %edi
> 	ja	LBB0_3
> ## BB#2:                                ## %switch.early.test
> 	movl	%edi, %eax
> 	movl	$88, %ecx
> 	btq	%rax, %rcx
> 	jb	LBB0_4
>
> This catches a bunch of cases in GCC, which look like this:
>
>   %804 = load i32* @which_alternative, align 4, !tbaa !0
>   %805 = icmp ult i32 %804, 2
>   %806 = icmp eq i32 %804, 3
>   %or.cond121 = or i1 %805, %806
>   %807 = icmp eq i32 %804, 4
>   %or.cond124 = or i1 %or.cond121, %807
>   br i1 %or.cond124, label %.thread, label %808
>
> turning this into a range comparison.
>
>
> Modified:
>      llvm/trunk/include/llvm/Support/ConstantRange.h
>      llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
>      llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
>
> Modified: llvm/trunk/include/llvm/Support/ConstantRange.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantRange.h?rev=122045&r1=122044&r2=122045&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/ConstantRange.h (original)
> +++ llvm/trunk/include/llvm/Support/ConstantRange.h Fri Dec 17 00:20:15 2010
> @@ -54,7 +54,7 @@
>     /// @brief Initialize a range of values explicitly. This will assert out if
>     /// Lower==Upper and Lower != Min or Max value for its type. It will also
>     /// assert out if the two APInt's are not the same bit width.
> -  ConstantRange(const APInt&  Lower, const APInt&  Upper);
> +  ConstantRange(const APInt&Lower, const APInt&Upper);
>
>     /// makeICmpRegion - Produce the smallest range that contains all values that
>     /// might satisfy the comparison specified by Pred when compared to any value
>
> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=122045&r1=122044&r2=122045&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Fri Dec 17 00:20:15 2010
> @@ -28,6 +28,7 @@
>   #include "llvm/ADT/Statistic.h"
>   #include "llvm/ADT/STLExtras.h"
>   #include "llvm/Support/CFG.h"
> +#include "llvm/Support/ConstantRange.h"
>   #include "llvm/Support/Debug.h"
>   #include "llvm/Support/raw_ostream.h"
>   #include<algorithm>
> @@ -305,11 +306,33 @@
>
>     // If this is an icmp against a constant, handle this as one of the cases.
>     if (ICmpInst *ICI = dyn_cast<ICmpInst>(I)) {
> -    if (ICI->getPredicate() == (isEQ ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE))
> -      if (ConstantInt *C = GetConstantInt(I->getOperand(1), TD)) {
> +    if (ConstantInt *C = GetConstantInt(I->getOperand(1), TD)) {
> +      if (ICI->getPredicate() == (isEQ ? ICmpInst::ICMP_EQ:ICmpInst::ICMP_NE)) {
>           Vals.push_back(C);
>           return I->getOperand(0);
>         }
> +
> +      // If we have "x ult 3" comparison, for example, then we can add 0,1,2 to
> +      // the set.
> +      ConstantRange Span =
> +        ConstantRange::makeICmpRegion(ICI->getPredicate(),
> +                                      ConstantRange(C->getValue()));

This simplifies to:

   ConstantRange Span = ICmpInst::makeConstantRange(ICI->getPredicate(), 
C->getValue());

Nick

> +
> +      // If this is an and/!= check then we want to optimize "x ugt 2" into
> +      // x != 0&&  x != 1.
> +      if (!isEQ)
> +        Span = Span.inverse();
> +
> +      // If there are a ton of values, we don't want to make a ginormous switch.
> +      if (Span.getSetSize().getZExtValue()>  8 || Span.isEmptySet() ||
> +          // We don't handle wrapped sets yet.
> +          Span.isWrappedSet())
> +        return 0;
> +
> +      for (APInt Tmp = Span.getLower(); Tmp != Span.getUpper(); ++Tmp)
> +        Vals.push_back(ConstantInt::get(V->getContext(), Tmp));
> +      return I->getOperand(0);
> +    }
>       return 0;
>     }
>
>
> Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=122045&r1=122044&r2=122045&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
> +++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Fri Dec 17 00:20:15 2010
> @@ -351,4 +351,73 @@
>     ret void
>   ; CHECK: @test12
>
> -}
> \ No newline at end of file
> +}
> +
> +; test13 - handle switch formation with ult.
> +define void @test13(i32 %x) nounwind ssp noredzone {
> +entry:
> +  %cmp = icmp ult i32 %x, 2
> +  br i1 %cmp, label %if.then, label %lor.lhs.false3
> +
> +lor.lhs.false3:                                   ; preds = %lor.lhs.false
> +  %cmp5 = icmp eq i32 %x, 3
> +  br i1 %cmp5, label %if.then, label %lor.lhs.false6
> +
> +lor.lhs.false6:                                   ; preds = %lor.lhs.false3
> +  %cmp8 = icmp eq i32 %x, 4
> +  br i1 %cmp8, label %if.then, label %lor.lhs.false9
> +
> +lor.lhs.false9:                                   ; preds = %lor.lhs.false6
> +  %cmp11 = icmp eq i32 %x, 6
> +  br i1 %cmp11, label %if.then, label %if.end
> +
> +if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
> +  call void @foo1() noredzone
> +  br label %if.end
> +
> +if.end:                                           ; preds = %if.then, %lor.lhs.false9
> +  ret void
> +; CHECK: @test13
> +; CHECK:  switch i32 %x, label %if.end [
> +; CHECK:     i32 6, label %if.then
> +; CHECK:     i32 4, label %if.then
> +; CHECK:     i32 3, label %if.then
> +; CHECK:     i32 1, label %if.then
> +; CHECK:     i32 0, label %if.then
> +; CHECK:   ]
> +}
> +
> +; test14 - handle switch formation with ult.
> +define void @test14(i32 %x) nounwind ssp noredzone {
> +entry:
> +  %cmp = icmp ugt i32 %x, 2
> +  br i1 %cmp, label %lor.lhs.false3, label %if.then
> +
> +lor.lhs.false3:                                   ; preds = %lor.lhs.false
> +  %cmp5 = icmp ne i32 %x, 3
> +  br i1 %cmp5, label %lor.lhs.false6, label %if.then
> +
> +lor.lhs.false6:                                   ; preds = %lor.lhs.false3
> +  %cmp8 = icmp ne i32 %x, 4
> +  br i1 %cmp8, label %lor.lhs.false9, label %if.then
> +
> +lor.lhs.false9:                                   ; preds = %lor.lhs.false6
> +  %cmp11 = icmp ne i32 %x, 6
> +  br i1 %cmp11, label %if.end, label %if.then
> +
> +if.then:                                          ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
> +  call void @foo1() noredzone
> +  br label %if.end
> +
> +if.end:                                           ; preds = %if.then, %lor.lhs.false9
> +  ret void
> +; CHECK: @test14
> +; CHECK:  switch i32 %x, label %if.end [
> +; CHECK:     i32 6, label %if.then
> +; CHECK:     i32 4, label %if.then
> +; CHECK:     i32 3, label %if.then
> +; CHECK:     i32 1, label %if.then
> +; CHECK:     i32 0, label %if.then
> +; CHECK:   ]
> +}
> +
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From kalle.raiskila at nokia.com  Fri Dec 17 03:36:09 2010
From: kalle.raiskila at nokia.com (Kalle Raiskila)
Date: Fri, 17 Dec 2010 09:36:09 -0000
Subject: [llvm-commits] [llvm] r122052 - in /llvm/trunk:
 lib/Target/CellSPU/SPUOperands.td test/CodeGen/CellSPU/immed32.ll
Message-ID: <20101217093609.607DF2A6C12C@llvm.org>

Author: kraiskil
Date: Fri Dec 17 03:36:09 2010
New Revision: 122052

URL: http://llvm.org/viewvc/llvm-project?rev=122052&view=rev
Log:
Don't feed 19 bit immediates to ILA.

Patch (slightly modified) by Visa Putkinen.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUOperands.td
    llvm/trunk/test/CodeGen/CellSPU/immed32.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=122052&r1=122051&r2=122052&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Fri Dec 17 03:36:09 2010
@@ -143,7 +143,7 @@
 def imm18  : PatLeaf<(imm), [{
   // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
   int Value = (int) N->getZExtValue();
-  return ((Value & ((1 << 19) - 1)) == Value);
+  return isUInt<18>(Value); 
 }]>;
 
 def lo16 : PatLeaf<(imm), [{
@@ -203,7 +203,7 @@
 
 def FPimm_u18 : SDNodeXForm<fpimm, [{
   float fval = N->getValueAPF().convertToFloat();
-  return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
+  return getI32Imm(FloatToBits(fval) & ((1 << 18) - 1));
 }]>;
 
 def fpimmSExt16 : PatLeaf<(fpimm), [{
@@ -225,7 +225,7 @@
 def fpimm18  : PatLeaf<(fpimm), [{
   if (N->getValueType(0) == MVT::f32) {
     uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
-    return ((Value & ((1 << 19) - 1)) == Value);
+    return isUInt<18>(Value);
   }
 
   return false;

Modified: llvm/trunk/test/CodeGen/CellSPU/immed32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed32.ll?rev=122052&r1=122051&r2=122052&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/immed32.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/immed32.ll Fri Dec 17 03:36:09 2010
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
-; RUN: grep ilhu  %t1.s | count 8
-; RUN: grep iohl  %t1.s | count 6
+; RUN: grep ilhu  %t1.s | count 9
+; RUN: grep iohl  %t1.s | count 7
 ; RUN: grep -w il    %t1.s | count 3
 ; RUN: grep 16429 %t1.s | count 1
 ; RUN: grep 63572 %t1.s | count 1
@@ -12,6 +12,7 @@
 ; RUN: grep 49077 %t1.s | count 1
 ; RUN: grep  1267 %t1.s | count 2
 ; RUN: grep 16309 %t1.s | count 1
+; RUN: cat %t1.s | FileCheck %s
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 
@@ -31,6 +32,16 @@
   ret i32 -512                  ;; IL via pattern
 }
 
+define i32 @test_5()
+{
+;CHECK: test_5:
+;CHECK-NOT: ila $3, 40000
+;CHECK: ilhu
+;CHECK: iohl
+;CHECK: bi $lr
+  ret i32 400000
+}
+
 ;; double             float       floatval
 ;; 0x4005bf0a80000000 0x402d|f854 2.718282
 define float @float_const_1() {



From benny.kra at googlemail.com  Fri Dec 17 03:56:50 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 17 Dec 2010 09:56:50 -0000
Subject: [llvm-commits] [llvm] r122053 -
	/llvm/trunk/lib/Object/MachOObject.cpp
Message-ID: <20101217095650.85B5B2A6C12C@llvm.org>

Author: d0k
Date: Fri Dec 17 03:56:50 2010
New Revision: 122053

URL: http://llvm.org/viewvc/llvm-project?rev=122053&view=rev
Log:
Fix mismatched new[]/delete.

Modified:
    llvm/trunk/lib/Object/MachOObject.cpp

Modified: llvm/trunk/lib/Object/MachOObject.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObject.cpp?rev=122053&r1=122052&r2=122053&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObject.cpp (original)
+++ llvm/trunk/lib/Object/MachOObject.cpp Fri Dec 17 03:56:50 2010
@@ -84,7 +84,7 @@
 }
 
 MachOObject::~MachOObject() {
-  delete LoadCommands;
+  delete [] LoadCommands;
 }
 
 MachOObject *MachOObject::LoadFromBuffer(MemoryBuffer *Buffer,



From benny.kra at googlemail.com  Fri Dec 17 04:48:15 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 17 Dec 2010 10:48:15 -0000
Subject: [llvm-commits] [llvm] r122054 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/switch_create.ll
Message-ID: <20101217104815.221212A6C12C@llvm.org>

Author: d0k
Date: Fri Dec 17 04:48:14 2010
New Revision: 122054

URL: http://llvm.org/viewvc/llvm-project?rev=122054&view=rev
Log:
SimplifyCFG: Ranges can be larger than 64 bits. Fixes Release-selfhost build.

Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=122054&r1=122053&r2=122054&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Fri Dec 17 04:48:14 2010
@@ -324,7 +324,7 @@
         Span = Span.inverse();
       
       // If there are a ton of values, we don't want to make a ginormous switch.
-      if (Span.getSetSize().getZExtValue() > 8 || Span.isEmptySet() ||
+      if (Span.getSetSize().ugt(8) || Span.isEmptySet() ||
           // We don't handle wrapped sets yet.
           Span.isWrappedSet())
         return 0;

Modified: llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll?rev=122054&r1=122053&r2=122054&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll Fri Dec 17 04:48:14 2010
@@ -421,3 +421,23 @@
 ; CHECK:   ]
 }
 
+; Don't crash on ginormous ranges.
+define void @test15(i128 %x) nounwind {
+  %cmp = icmp ugt i128 %x, 2
+  br i1 %cmp, label %if.end, label %lor.false
+
+lor.false:
+  %cmp2 = icmp ne i128 %x, 100000000000000000000
+  br i1 %cmp2, label %if.end, label %if.then
+
+if.then:
+  call void @foo1() noredzone
+  br label %if.end
+
+if.end:
+  ret void
+
+; CHECK: @test15
+; CHECK-NOT: switch
+; CHECK: ret void
+}



From isanbard at gmail.com  Fri Dec 17 06:13:20 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 17 Dec 2010 12:13:20 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r122055 - in /llvm-gcc-4.2/trunk/gcc:
	configure configure.ac
Message-ID: <20101217121320.E67A02A6C12C@llvm.org>

Author: void
Date: Fri Dec 17 06:13:20 2010
New Revision: 122055

URL: http://llvm.org/viewvc/llvm-project?rev=122055&view=rev
Log:
Use tabs and spaces in the pattern instead of just spaces.

Modified:
    llvm-gcc-4.2/trunk/gcc/configure
    llvm-gcc-4.2/trunk/gcc/configure.ac

Modified: llvm-gcc-4.2/trunk/gcc/configure
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure?rev=122055&r1=122054&r2=122055&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/configure (original)
+++ llvm-gcc-4.2/trunk/gcc/configure Fri Dec 17 06:13:20 2010
@@ -18551,14 +18551,14 @@
       # glibc 2.4 and later provides __stack_chk_fail and
       # either __stack_chk_guard, or TLS access to stack guard canary.
       if test -f $glibc_header_dir/features.h \
-         && $EGREP '^[       ]*#[         ]*define[       ]+__GNU_LIBRARY__[      ]+([1-9][0-9]|[6-9])' \
+         && $EGREP '^[	 ]*#[	 ]*define[	 ]+__GNU_LIBRARY__[	 ]+([1-9][0-9]|[6-9])' \
             $glibc_header_dir/features.h > /dev/null; then
-        if $EGREP '^[        ]*#[         ]*define[       ]+__GLIBC__[    ]+([1-9][0-9]|[3-9])' \
+        if $EGREP '^[	 ]*#[	 ]*define[	 ]+__GLIBC__[	 ]+([1-9][0-9]|[3-9])' \
            $glibc_header_dir/features.h > /dev/null; then
           gcc_cv_libc_provides_ssp=yes
-        elif $EGREP '^[      ]*#[         ]*define[       ]+__GLIBC__[    ]+2' \
+        elif $EGREP '^[	 ]*#[	 ]*define[	 ]+__GLIBC__[	 ]+2' \
              $glibc_header_dir/features.h > /dev/null \
-             && $EGREP '^[   ]*#[         ]*define[       ]+__GLIBC_MINOR__[      ]+([1-9][0-9]|[4-9])' \
+             && $EGREP '^[	 ]*#[	 ]*define[	 ]+__GLIBC_MINOR__[	 ]+([1-9][0-9]|[4-9])' \
              $glibc_header_dir/features.h > /dev/null; then
           gcc_cv_libc_provides_ssp=yes
         fi

Modified: llvm-gcc-4.2/trunk/gcc/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure.ac?rev=122055&r1=122054&r2=122055&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/configure.ac (original)
+++ llvm-gcc-4.2/trunk/gcc/configure.ac Fri Dec 17 06:13:20 2010
@@ -3348,14 +3348,14 @@
       # glibc 2.4 and later provides __stack_chk_fail and
       # either __stack_chk_guard, or TLS access to stack guard canary.
       if test -f $glibc_header_dir/features.h \
-         && $EGREP '^@<:@       @:>@*#[         ]*define[       ]+__GNU_LIBRARY__[      ]+([1-9][0-9]|[6-9])' \
+         && $EGREP '^@<:@	 @:>@*#[	 ]*define[	 ]+__GNU_LIBRARY__[	 ]+([1-9][0-9]|[6-9])' \
             $glibc_header_dir/features.h > /dev/null; then
-        if $EGREP '^@<:@        @:>@*#[         ]*define[       ]+__GLIBC__[    ]+([1-9][0-9]|[3-9])' \
+        if $EGREP '^@<:@	 @:>@*#[	 ]*define[	 ]+__GLIBC__[	 ]+([1-9][0-9]|[3-9])' \
            $glibc_header_dir/features.h > /dev/null; then
           gcc_cv_libc_provides_ssp=yes
-        elif $EGREP '^@<:@      @:>@*#[         ]*define[       ]+__GLIBC__[    ]+2' \
+        elif $EGREP '^@<:@	 @:>@*#[	 ]*define[	 ]+__GLIBC__[	 ]+2' \
              $glibc_header_dir/features.h > /dev/null \
-             && $EGREP '^@<:@   @:>@*#[         ]*define[       ]+__GLIBC_MINOR__[      ]+([1-9][0-9]|[4-9])' \
+             && $EGREP '^@<:@	 @:>@*#[	 ]*define[	 ]+__GLIBC_MINOR__[	 ]+([1-9][0-9]|[4-9])' \
              $glibc_header_dir/features.h > /dev/null; then
           gcc_cv_libc_provides_ssp=yes
         fi



From jan_sjodin at yahoo.com  Fri Dec 17 08:38:13 2010
From: jan_sjodin at yahoo.com (Jan Sjodin)
Date: Fri, 17 Dec 2010 06:38:13 -0800 (PST)
Subject: [llvm-commits] [llvm] r121949 - in /llvm/trunk:
	include/llvm/MC/MCStreamer.h include/llvm/Target/TargetRegistry.h
	lib/CodeGen/LLVMTargetMachine.cpp lib/MC/MCAsmStreamer.cpp
	lib/Target/PTX/PTXMCAsmStreamer.cpp
	lib/Target/PTX/PTXTargetMachine.cpp tools/llvm-mc/llvm-mc.cpp
In-Reply-To: <F08119E4-1869-4E4C-8B06-38CE247FC813@apple.com>
References: <20101216030559.B41782A6C12D@llvm.org>
	<F08119E4-1869-4E4C-8B06-38CE247FC813@apple.com>
Message-ID: <960820.36471.qm@web55604.mail.re4.yahoo.com>

Could I please get a copy of pact agreement and transcripts of the discussions 
leading up to it?

- Jan



----- Original Message ----
> From: Jim Grosbach <grosbach at apple.com>
> To: Daniel Dunbar <daniel at zuster.org>
> Cc: llvm-commits at cs.uiuc.edu
> Sent: Thu, December 16, 2010 11:00:42 AM
> Subject: Re: [llvm-commits] [llvm] r121949 - in /llvm/trunk: 
>include/llvm/MC/MCStreamer.h include/llvm/Target/TargetRegistry.h 
>lib/CodeGen/LLVMTargetMachine.cpp lib/MC/MCAsmStreamer.cpp 
>lib/Target/PTX/PTXMCAsmStreamer.cpp lib/Target/PTX/PTXTargetMachine.cpp 
>tools/llvm-mc/llvm-mc.cpp
> 
> True, but the non-aggression pact achieved was the best alternative. Now if we  
>can only get TargetMachine to the bargaining table...
> -j
> On Dec 15, 2010,  at 7:05 PM, Daniel Dunbar wrote:
> 
> > Author: ddunbar
> > Date: Wed  Dec 15 21:05:59 2010
> > New Revision: 121949
> > 
> > URL:  http://llvm.org/viewvc/llvm-project?rev=121949&view=rev
> > Log:
> > MC:  Make TargetAsmBackend available to the AsmStreamer.
> > - Treaty talks on  the non-proliferation of MC objects broke down.
> > 
> >  Modified:
> >     llvm/trunk/include/llvm/MC/MCStreamer.h
> >     llvm/trunk/include/llvm/Target/TargetRegistry.h
> >     llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> >     llvm/trunk/lib/MC/MCAsmStreamer.cpp
> >     llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp
> >     llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
> >     llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> > 
> > Modified:  llvm/trunk/include/llvm/MC/MCStreamer.h
> > URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
> > +++  llvm/trunk/include/llvm/MC/MCStreamer.h Wed Dec 15 21:05:59 2010
> > @@  -426,6 +426,10 @@
> >   /// \param CE - If given, a code emitter to use  to show the instruction
> >   /// encoding inline with the assembly.  This method takes ownership of \arg 
>CE.
> >   ///
> > +  ///  \param TAB - If given, a target asm backend to use to show the fixup
> >  +  /// information in conjunction with encoding information. This method  
>takes
> > +  /// ownership of \arg TAB.
> > +   ///
> >   /// \param ShowInst - Whether to show the MCInst  representation inline 
>with
> >   /// the assembly.
> >    MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream  &OS,
> > @@ -433,6 +437,7 @@
> >                                   bool useLoc,
> >                                  MCInstPrinter  *InstPrint = 0,
> >                                  MCCodeEmitter *CE =  0,
> > +                                 TargetAsmBackend *TAB =  0,
> >                                  bool ShowInst = false);
> > 
> >   /// createMachOStreamer - Create a machine code streamer which  will 
>generate
> > 
> > Modified:  llvm/trunk/include/llvm/Target/TargetRegistry.h
> > URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
> > +++  llvm/trunk/include/llvm/Target/TargetRegistry.h Wed Dec 15 21:05:59 
2010
> >  @@ -46,6 +46,7 @@
> >                                  bool  useLoc,
> >                                  MCInstPrinter  *InstPrint,
> >                                  MCCodeEmitter  *CE,
> > +                                 TargetAsmBackend  *TAB,
> >                                  bool ShowInst);
> > 
> >   /// Target - Wrapper for Target specific information.
> > @@  -95,6 +96,7 @@
> >                                                bool useLoc,
> >                                                MCInstPrinter  *InstPrint,
> >                                                MCCodeEmitter *CE,
> > +                                               TargetAsmBackend  *TAB,
> >                                                bool ShowInst);
> > 
> >   private:
> > @@  -323,10 +325,11 @@
> >                                    bool  useLoc,
> >                                    MCInstPrinter  *InstPrint,
> >                                    MCCodeEmitter  *CE,
> > +                                   TargetAsmBackend  *TAB,
> >                                    bool ShowInst) const  {
> >       // AsmStreamerCtorFn is default to  llvm::createAsmStreamer
> >       return  AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc,
> > -                                 InstPrint, CE, ShowInst);
> > +                                 InstPrint, CE, TAB, ShowInst);
> >     }
> > 
> >      /// @}
> > 
> > Modified:  llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> > URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> > +++  llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Dec 15 21:05:59 2010
> > @@  -143,14 +143,17 @@
> > 
> >     // Create a code emitter if  asked to show the encoding.
> >     MCCodeEmitter *MCE =  0;
> > -    if (ShowMCEncoding)
> > +     TargetAsmBackend *TAB = 0;
> > +    if (ShowMCEncoding)  {
> >       MCE = getTarget().createCodeEmitter(*this,  *Context);
> > +      TAB =  getTarget().createAsmBackend(TargetTriple);
> > +    }
> > 
> >     MCStreamer *S = getTarget().createAsmStreamer(*Context,  Out,
> >                                                     getVerboseAsm(),
> >                                                      hasMCUseLoc(),
> >                                                     InstPrinter,
> > -                                                     MCE,
> > +                                                    MCE, TAB,
> >                                                      ShowMCInst);
> >     AsmStreamer.reset(S);
> >      break;
> > 
> > Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
> >  URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
> > +++  llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Dec 15 21:05:59 2010
> > @@ -23,8  +23,9 @@
> > #include "llvm/Support/MathExtras.h"
> > #include  "llvm/Support/Format.h"
> > #include  "llvm/Support/FormattedStream.h"
> > -#include  "llvm/Target/TargetLoweringObjectFile.h"
> > +#include  "llvm/Target/TargetAsmBackend.h"
> > #include  "llvm/Target/TargetAsmInfo.h"
> > +#include  "llvm/Target/TargetLoweringObjectFile.h"
> > using namespace llvm;
> > 
> > namespace {
> > @@ -34,6 +35,7 @@
> >   const MCAsmInfo  &MAI;
> >   OwningPtr<MCInstPrinter>  InstPrinter;
> >   OwningPtr<MCCodeEmitter> Emitter;
> >  +  OwningPtr<TargetAsmBackend> AsmBackend;
> > 
> >    SmallString<128> CommentToEmit;
> >   raw_svector_ostream  CommentStream;
> > @@ -48,10 +50,12 @@
> >    MCAsmStreamer(MCContext &Context, formatted_raw_ostream  &os,
> >                 bool  isVerboseAsm,
> >                  bool useLoc,
> > -                 MCInstPrinter *printer, MCCodeEmitter *emitter, bool 
>showInst)
> > +                 MCInstPrinter *printer,  MCCodeEmitter *emitter,
> > +                 TargetAsmBackend *asmbackend,
> > +                 bool showInst)
> >     :  MCStreamer(Context), OS(os), MAI(Context.getAsmInfo()),
> > -       InstPrinter(printer), Emitter(emitter),  
>CommentStream(CommentToEmit),
> > -       IsVerboseAsm(isVerboseAsm),
> > +      InstPrinter(printer),  Emitter(emitter), AsmBackend(asmbackend),
> > +       CommentStream(CommentToEmit), IsVerboseAsm(isVerboseAsm),
> >        ShowInst(showInst), UseLoc(useLoc) {
> >     if  (InstPrinter && IsVerboseAsm)
> >        InstPrinter->setCommentStream(CommentStream);
> > @@ -893,8 +897,8  @@
> > MCStreamer *llvm::createAsmStreamer(MCContext  &Context,
> >                                       formatted_raw_ostream &OS,
> >                                       bool isVerboseAsm, bool useLoc,
> > -                                      MCInstPrinter *IP,
> > -                                      MCCodeEmitter *CE, bool ShowInst) {
> > +                                      MCInstPrinter *IP, MCCodeEmitter *CE,
> >  +                                     TargetAsmBackend *TAB, bool  ShowInst) 
>{
> >   return new MCAsmStreamer(Context, OS, isVerboseAsm,  useLoc,
> > -                            IP, CE, ShowInst);
> > +                            IP, CE,  TAB, ShowInst);
> > }
> > 
> > Modified:  llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp
> > URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp (original)
> > +++  llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp Wed Dec 15 21:05:59 2010
> >  @@ -540,7 +540,8 @@
> >                                      formatted_raw_ostream &OS,
> >                                      bool isVerboseAsm, bool useLoc,
> >                                      MCInstPrinter *IP,
> > -                                     MCCodeEmitter *CE, bool ShowInst) {
> > +                                     MCCodeEmitter *CE, TargetAsmBackend 
>*TAB,
> > +                                     bool ShowInst) {
> >     return new  PTXMCAsmStreamer(Context, OS, isVerboseAsm, useLoc,
> >                                   IP, CE, ShowInst);
> >   }
> > 
> > Modified:  llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
> > URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original)
> > +++  llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Dec 15 21:05:59 2010
> >  @@ -24,6 +24,7 @@
> >                                     bool  isVerboseAsm, bool useLoc,
> >                                      MCInstPrinter *InstPrint,
> >                                      MCCodeEmitter *CE,
> > +                                     TargetAsmBackend *TAB,
> >                                      bool ShowInst);
> > }
> > 
> > 
> > Modified:  llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> > URL:  
>http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=121949&r1=121948&r2=121949&view=diff
>
> > 
>==============================================================================
> > ; --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
> > +++  llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Dec 15 21:05:59 2010
> > @@ -340,10  +340,14 @@
> >     MCInstPrinter *IP =
> >        TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
> >      MCCodeEmitter *CE = 0;
> > -    if (ShowEncoding)
> > +     TargetAsmBackend *TAB = 0;
> > +    if (ShowEncoding)  {
> >       CE = TheTarget->createCodeEmitter(*TM,  Ctx);
> > +      TAB =  TheTarget->createAsmBackend(TripleName);
> > +     }
> >     Str.reset(TheTarget->createAsmStreamer(Ctx, FOS,  /*asmverbose*/true,
> > -                                             /*useLoc*/ true, IP, CE, 
>ShowInst));
> > +                                             /*useLoc*/ true,  IP, CE, TAB,
> > +                                             ShowInst));
> >   } else if (FileType == OFT_Null)  {
> >     Str.reset(createNullStreamer(Ctx));
> >   }  else {
> > 
> > 
> >  _______________________________________________
> > llvm-commits mailing  list
> > llvm-commits at cs.uiuc.edu
> >  http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits  mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

From fjahanian at apple.com  Fri Dec 17 10:37:06 2010
From: fjahanian at apple.com (Fariborz Jahanian)
Date: Fri, 17 Dec 2010 16:37:06 -0000
Subje